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KVM: x86: fix em_fxstor() sleeping while in atomic
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
9ed96e87
MT		 110unsigned int min_timer_period_us = 500;
111module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
112
630994b3
MT		 113static bool __read_mostly kvmclock_periodic_sync = true;
114module_param(kvmclock_periodic_sync, bool, S_IRUGO);
115
893590c7 116bool __read_mostly kvm_has_tsc_control;
92a1f12d 117EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 118u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 119EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 120u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
121EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
122u64 __read_mostly kvm_max_tsc_scaling_ratio;
123EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 124u64 __read_mostly kvm_default_tsc_scaling_ratio;
125EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 126
cc578287 127/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 128static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 129module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
130
d0659d94 131/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 132unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 133module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
134
52004014
FW		 135static bool __read_mostly vector_hashing = true;
136module_param(vector_hashing, bool, S_IRUGO);
137
18863bdd
AK		 138#define KVM_NR_SHARED_MSRS 16
139
140struct kvm_shared_msrs_global {
141 int nr;
2bf78fa7 142 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 143};
144
145struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
2bf78fa7
SY		 148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 152};
153
154static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 155static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 156
417bc304 157struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 168 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 173 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 181 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 182 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 183 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 184 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
185 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
186 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
187 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
188 { "mmu_flooded", VM_STAT(mmu_flooded) },
189 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 190 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 191 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 192 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 193 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 194 { "max_mmu_page_hash_collisions",
195 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 196 { NULL }
197};
198
2acf923e
DC		 199u64 __read_mostly host_xcr0;
200
b6785def 201static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 202
af585b92
GN		 203static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
204{
205 int i;
206 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
207 vcpu->arch.apf.gfns[i] = ~0;
208}
209
18863bdd
AK		 210static void kvm_on_user_return(struct user_return_notifier *urn)
211{
212 unsigned slot;
18863bdd
AK		 213 struct kvm_shared_msrs *locals
214 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 215 struct kvm_shared_msr_values *values;
1650b4eb
IA		 216 unsigned long flags;
217
218 /*
219 * Disabling irqs at this point since the following code could be
220 * interrupted and executed through kvm_arch_hardware_disable()
221 */
222 local_irq_save(flags);
223 if (locals->registered) {
224 locals->registered = false;
225 user_return_notifier_unregister(urn);
226 }
227 local_irq_restore(flags);
18863bdd 228 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 229 values = &locals->values[slot];
230 if (values->host != values->curr) {
231 wrmsrl(shared_msrs_global.msrs[slot], values->host);
232 values->curr = values->host;
18863bdd
AK		 233 }
234 }
18863bdd
AK		 235}
236
2bf78fa7 237static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 238{
18863bdd 239 u64 value;
013f6a5d
MT		 240 unsigned int cpu = smp_processor_id();
241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 242
2bf78fa7
SY		 243 /* only read, and nobody should modify it at this time,
244 * so don't need lock */
245 if (slot >= shared_msrs_global.nr) {
246 printk(KERN_ERR "kvm: invalid MSR slot!");
247 return;
248 }
249 rdmsrl_safe(msr, &value);
250 smsr->values[slot].host = value;
251 smsr->values[slot].curr = value;
252}
253
254void kvm_define_shared_msr(unsigned slot, u32 msr)
255{
0123be42 256 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 257 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 258 if (slot >= shared_msrs_global.nr)
259 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 260}
261EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
262
263static void kvm_shared_msr_cpu_online(void)
264{
265 unsigned i;
18863bdd
AK		 266
267 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 268 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 269}
270
8b3c3104 271int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 272{
013f6a5d
MT		 273 unsigned int cpu = smp_processor_id();
274 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 275 int err;
18863bdd 276
2bf78fa7 277 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 278 return 0;
2bf78fa7 279 smsr->values[slot].curr = value;
8b3c3104
AH		 280 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
281 if (err)
282 return 1;
283
18863bdd
AK		 284 if (!smsr->registered) {
285 smsr->urn.on_user_return = kvm_on_user_return;
286 user_return_notifier_register(&smsr->urn);
287 smsr->registered = true;
288 }
8b3c3104 289 return 0;
18863bdd
AK		 290}
291EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
292
13a34e06 293static void drop_user_return_notifiers(void)
3548bab5 294{
013f6a5d
MT		 295 unsigned int cpu = smp_processor_id();
296 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 297
298 if (smsr->registered)
299 kvm_on_user_return(&smsr->urn);
300}
301
6866b83e
CO		 302u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
303{
8a5a87d9 304 return vcpu->arch.apic_base;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_get_apic_base);
307
58cb628d
JK		 308int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
309{
310 u64 old_state = vcpu->arch.apic_base &
311 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
312 u64 new_state = msr_info->data &
313 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 314 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
315 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 316
d3802286
JM		 317 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
318 return 1;
58cb628d 319 if (!msr_info->host_initiated &&
d3802286 320 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 321 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
322 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
323 old_state == 0)))
324 return 1;
325
326 kvm_lapic_set_base(vcpu, msr_info->data);
327 return 0;
6866b83e
CO		 328}
329EXPORT_SYMBOL_GPL(kvm_set_apic_base);
330
2605fc21 331asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 332{
333 /* Fault while not rebooting. We want the trace. */
334 BUG();
335}
336EXPORT_SYMBOL_GPL(kvm_spurious_fault);
337
3fd28fce
ED		 338#define EXCPT_BENIGN 0
339#define EXCPT_CONTRIBUTORY 1
340#define EXCPT_PF 2
341
342static int exception_class(int vector)
343{
344 switch (vector) {
345 case PF_VECTOR:
346 return EXCPT_PF;
347 case DE_VECTOR:
348 case TS_VECTOR:
349 case NP_VECTOR:
350 case SS_VECTOR:
351 case GP_VECTOR:
352 return EXCPT_CONTRIBUTORY;
353 default:
354 break;
355 }
356 return EXCPT_BENIGN;
357}
358
d6e8c854
NA		 359#define EXCPT_FAULT 0
360#define EXCPT_TRAP 1
361#define EXCPT_ABORT 2
362#define EXCPT_INTERRUPT 3
363
364static int exception_type(int vector)
365{
366 unsigned int mask;
367
368 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
369 return EXCPT_INTERRUPT;
370
371 mask = 1 << vector;
372
373 /* #DB is trap, as instruction watchpoints are handled elsewhere */
374 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
375 return EXCPT_TRAP;
376
377 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
378 return EXCPT_ABORT;
379
380 /* Reserved exceptions will result in fault */
381 return EXCPT_FAULT;
382}
383
3fd28fce 384static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 385 unsigned nr, bool has_error, u32 error_code,
386 bool reinject)
3fd28fce
ED		 387{
388 u32 prev_nr;
389 int class1, class2;
390
3842d135
AK		 391 kvm_make_request(KVM_REQ_EVENT, vcpu);
392
664f8e26 393 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 394 queue:
3ffb2468
NA		 395 if (has_error && !is_protmode(vcpu))
396 has_error = false;
664f8e26
WL		 397 if (reinject) {
398 /*
399 * On vmentry, vcpu->arch.exception.pending is only
400 * true if an event injection was blocked by
401 * nested_run_pending. In that case, however,
402 * vcpu_enter_guest requests an immediate exit,
403 * and the guest shouldn't proceed far enough to
404 * need reinjection.
405 */
406 WARN_ON_ONCE(vcpu->arch.exception.pending);
407 vcpu->arch.exception.injected = true;
408 } else {
409 vcpu->arch.exception.pending = true;
410 vcpu->arch.exception.injected = false;
411 }
3fd28fce
ED		 412 vcpu->arch.exception.has_error_code = has_error;
413 vcpu->arch.exception.nr = nr;
414 vcpu->arch.exception.error_code = error_code;
415 return;
416 }
417
418 /* to check exception */
419 prev_nr = vcpu->arch.exception.nr;
420 if (prev_nr == DF_VECTOR) {
421 /* triple fault -> shutdown */
a8eeb04a 422 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 423 return;
424 }
425 class1 = exception_class(prev_nr);
426 class2 = exception_class(nr);
427 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
428 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 429 /*
430 * Generate double fault per SDM Table 5-5. Set
431 * exception.pending = true so that the double fault
432 * can trigger a nested vmexit.
433 */
3fd28fce 434 vcpu->arch.exception.pending = true;
664f8e26 435 vcpu->arch.exception.injected = false;
3fd28fce
ED		 436 vcpu->arch.exception.has_error_code = true;
437 vcpu->arch.exception.nr = DF_VECTOR;
438 vcpu->arch.exception.error_code = 0;
439 } else
440 /* replace previous exception with a new one in a hope
441 that instruction re-execution will regenerate lost
442 exception */
443 goto queue;
444}
445
298101da
AK		 446void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
447{
ce7ddec4 448 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 449}
450EXPORT_SYMBOL_GPL(kvm_queue_exception);
451
ce7ddec4
JR		 452void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
453{
454 kvm_multiple_exception(vcpu, nr, false, 0, true);
455}
456EXPORT_SYMBOL_GPL(kvm_requeue_exception);
457
6affcbed 458int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 459{
db8fcefa
AP		 460 if (err)
461 kvm_inject_gp(vcpu, 0);
462 else
6affcbed
KH		 463 return kvm_skip_emulated_instruction(vcpu);
464
465 return 1;
db8fcefa
AP		 466}
467EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 468
6389ee94 469void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 470{
471 ++vcpu->stat.pf_guest;
adfe20fb
WL		 472 vcpu->arch.exception.nested_apf =
473 is_guest_mode(vcpu) && fault->async_page_fault;
474 if (vcpu->arch.exception.nested_apf)
475 vcpu->arch.apf.nested_apf_token = fault->address;
476 else
477 vcpu->arch.cr2 = fault->address;
6389ee94 478 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 479}
27d6c865 480EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 481
ef54bcfe 482static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 483{
6389ee94
AK		 484 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
485 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 486 else
6389ee94 487 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 488
489 return fault->nested_page_fault;
d4f8cf66
JR		 490}
491
3419ffc8
SY		 492void kvm_inject_nmi(struct kvm_vcpu *vcpu)
493{
7460fb4a
AK		 494 atomic_inc(&vcpu->arch.nmi_queued);
495 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 496}
497EXPORT_SYMBOL_GPL(kvm_inject_nmi);
498
298101da
AK		 499void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
500{
ce7ddec4 501 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 502}
503EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
504
ce7ddec4
JR		 505void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
506{
507 kvm_multiple_exception(vcpu, nr, true, error_code, true);
508}
509EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
510
0a79b009
AK		 511/*
512 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
513 * a #GP and return false.
514 */
515bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 516{
0a79b009
AK		 517 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
518 return true;
519 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
520 return false;
298101da 521}
0a79b009 522EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 523
16f8a6f9
NA		 524bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
525{
526 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
527 return true;
528
529 kvm_queue_exception(vcpu, UD_VECTOR);
530 return false;
531}
532EXPORT_SYMBOL_GPL(kvm_require_dr);
533
ec92fe44
JR		 534/*
535 * This function will be used to read from the physical memory of the currently
54bf36aa 536 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 537 * can read from guest physical or from the guest's guest physical memory.
538 */
539int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
540 gfn_t ngfn, void *data, int offset, int len,
541 u32 access)
542{
54987b7a 543 struct x86_exception exception;
ec92fe44
JR		 544 gfn_t real_gfn;
545 gpa_t ngpa;
546
547 ngpa = gfn_to_gpa(ngfn);
54987b7a 548 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 549 if (real_gfn == UNMAPPED_GVA)
550 return -EFAULT;
551
552 real_gfn = gpa_to_gfn(real_gfn);
553
54bf36aa 554 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 555}
556EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
557
69b0049a 558static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 559 void *data, int offset, int len, u32 access)
560{
561 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
562 data, offset, len, access);
563}
564
a03490ed
CO		 565/*
566 * Load the pae pdptrs. Return true is they are all valid.
567 */
ff03a073 568int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 569{
570 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
571 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
572 int i;
573 int ret;
ff03a073 574 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 575
ff03a073
JR		 576 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
577 offset * sizeof(u64), sizeof(pdpte),
578 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 579 if (ret < 0) {
580 ret = 0;
581 goto out;
582 }
583 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 584 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 585 (pdpte[i] &
586 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 587 ret = 0;
588 goto out;
589 }
590 }
591 ret = 1;
592
ff03a073 593 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 594 __set_bit(VCPU_EXREG_PDPTR,
595 (unsigned long *)&vcpu->arch.regs_avail);
596 __set_bit(VCPU_EXREG_PDPTR,
597 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 598out:
a03490ed
CO		 599
600 return ret;
601}
cc4b6871 602EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 603
9ed38ffa 604bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 605{
ff03a073 606 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 607 bool changed = true;
3d06b8bf
JR		 608 int offset;
609 gfn_t gfn;
d835dfec
AK		 610 int r;
611
612 if (is_long_mode(vcpu) || !is_pae(vcpu))
613 return false;
614
6de4f3ad
AK		 615 if (!test_bit(VCPU_EXREG_PDPTR,
616 (unsigned long *)&vcpu->arch.regs_avail))
617 return true;
618
a512177e
PB		 619 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
620 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 621 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
622 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 623 if (r < 0)
624 goto out;
ff03a073 625 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 626out:
d835dfec
AK		 627
628 return changed;
629}
9ed38ffa 630EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 631
49a9b07e 632int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 633{
aad82703 634 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 635 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 636
f9a48e6a
AK		 637 cr0 |= X86_CR0_ET;
638
ab344828 639#ifdef CONFIG_X86_64
0f12244f
GN		 640 if (cr0 & 0xffffffff00000000UL)
641 return 1;
ab344828
GN		 642#endif
643
644 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 645
0f12244f
GN		 646 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
647 return 1;
a03490ed 648
0f12244f
GN		 649 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
650 return 1;
a03490ed
CO		 651
652 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
653#ifdef CONFIG_X86_64
f6801dff 654 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 655 int cs_db, cs_l;
656
0f12244f
GN		 657 if (!is_pae(vcpu))
658 return 1;
a03490ed 659 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 660 if (cs_l)
661 return 1;
a03490ed
CO		 662 } else
663#endif
ff03a073 664 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 665 kvm_read_cr3(vcpu)))
0f12244f 666 return 1;
a03490ed
CO		 667 }
668
ad756a16
MJ		 669 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
670 return 1;
671
a03490ed 672 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 673
d170c419 674 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 675 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 676 kvm_async_pf_hash_reset(vcpu);
677 }
e5f3f027 678
aad82703
SY		 679 if ((cr0 ^ old_cr0) & update_bits)
680 kvm_mmu_reset_context(vcpu);
b18d5431 681
879ae188
LE		 682 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
683 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
684 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 685 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
686
0f12244f
GN		 687 return 0;
688}
2d3ad1f4 689EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 690
2d3ad1f4 691void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 692{
49a9b07e 693 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 696
42bdf991
MT		 697static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
698{
699 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
700 !vcpu->guest_xcr0_loaded) {
701 /* kvm_set_xcr() also depends on this */
702 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
703 vcpu->guest_xcr0_loaded = 1;
704 }
705}
706
707static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
708{
709 if (vcpu->guest_xcr0_loaded) {
710 if (vcpu->arch.xcr0 != host_xcr0)
711 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
712 vcpu->guest_xcr0_loaded = 0;
713 }
714}
715
69b0049a 716static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 717{
56c103ec
LJ		 718 u64 xcr0 = xcr;
719 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 720 u64 valid_bits;
2acf923e
DC		 721
722 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
723 if (index != XCR_XFEATURE_ENABLED_MASK)
724 return 1;
d91cab78 725 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 726 return 1;
d91cab78 727 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 728 return 1;
46c34cb0
PB		 729
730 /*
731 * Do not allow the guest to set bits that we do not support
732 * saving. However, xcr0 bit 0 is always set, even if the
733 * emulated CPU does not support XSAVE (see fx_init).
734 */
d91cab78 735 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 736 if (xcr0 & ~valid_bits)
2acf923e 737 return 1;
46c34cb0 738
d91cab78
DH		 739 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
740 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 741 return 1;
742
d91cab78
DH		 743 if (xcr0 & XFEATURE_MASK_AVX512) {
744 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 745 return 1;
d91cab78 746 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 747 return 1;
748 }
2acf923e 749 vcpu->arch.xcr0 = xcr0;
56c103ec 750
d91cab78 751 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 752 kvm_update_cpuid(vcpu);
2acf923e
DC		 753 return 0;
754}
755
756int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
757{
764bcbc5
Z		 758 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
759 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 760 kvm_inject_gp(vcpu, 0);
761 return 1;
762 }
763 return 0;
764}
765EXPORT_SYMBOL_GPL(kvm_set_xcr);
766
a83b29c6 767int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 768{
fc78f519 769 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 770 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 771 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 772
0f12244f
GN		 773 if (cr4 & CR4_RESERVED_BITS)
774 return 1;
a03490ed 775
d6321d49 776 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 777 return 1;
778
d6321d49 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 780 return 1;
781
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 783 return 1;
784
d6321d49 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 786 return 1;
787
d6321d49 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 789 return 1;
790
fd8cb433 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 792 return 1;
793
a03490ed 794 if (is_long_mode(vcpu)) {
0f12244f
GN		 795 if (!(cr4 & X86_CR4_PAE))
796 return 1;
a2edf57f
AK		 797 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
798 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 799 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
800 kvm_read_cr3(vcpu)))
0f12244f
GN		 801 return 1;
802
ad756a16 803 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 804 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 805 return 1;
806
807 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
808 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
809 return 1;
810 }
811
5e1746d6 812 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 813 return 1;
a03490ed 814
ad756a16
MJ		 815 if (((cr4 ^ old_cr4) & pdptr_bits) ||
816 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 817 kvm_mmu_reset_context(vcpu);
0f12244f 818
b9baba86 819 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 820 kvm_update_cpuid(vcpu);
2acf923e 821
0f12244f
GN		 822 return 0;
823}
2d3ad1f4 824EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 825
2390218b 826int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 827{
ac146235 828#ifdef CONFIG_X86_64
9d88fca7 829 cr3 &= ~CR3_PCID_INVD;
ac146235 830#endif
9d88fca7 831
9f8fe504 832 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 833 kvm_mmu_sync_roots(vcpu);
77c3913b 834 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 835 return 0;
d835dfec
AK		 836 }
837
d1cd3ce9
YZ		 838 if (is_long_mode(vcpu) &&
839 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
840 return 1;
841 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 842 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 843 return 1;
a03490ed 844
0f12244f 845 vcpu->arch.cr3 = cr3;
aff48baa 846 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 847 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 848 return 0;
849}
2d3ad1f4 850EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 851
eea1cff9 852int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 853{
0f12244f
GN		 854 if (cr8 & CR8_RESERVED_BITS)
855 return 1;
35754c98 856 if (lapic_in_kernel(vcpu))
a03490ed
CO		 857 kvm_lapic_set_tpr(vcpu, cr8);
858 else
ad312c7c 859 vcpu->arch.cr8 = cr8;
0f12244f
GN		 860 return 0;
861}
2d3ad1f4 862EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 863
2d3ad1f4 864unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 865{
35754c98 866 if (lapic_in_kernel(vcpu))
a03490ed
CO		 867 return kvm_lapic_get_cr8(vcpu);
868 else
ad312c7c 869 return vcpu->arch.cr8;
a03490ed 870}
2d3ad1f4 871EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 872
ae561ede
NA		 873static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
874{
875 int i;
876
877 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
878 for (i = 0; i < KVM_NR_DB_REGS; i++)
879 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
880 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
881 }
882}
883
73aaf249
JK		 884static void kvm_update_dr6(struct kvm_vcpu *vcpu)
885{
886 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
887 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
888}
889
c8639010
JK		 890static void kvm_update_dr7(struct kvm_vcpu *vcpu)
891{
892 unsigned long dr7;
893
894 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
895 dr7 = vcpu->arch.guest_debug_dr7;
896 else
897 dr7 = vcpu->arch.dr7;
898 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 899 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
900 if (dr7 & DR7_BP_EN_MASK)
901 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 902}
903
6f43ed01
NA		 904static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
905{
906 u64 fixed = DR6_FIXED_1;
907
d6321d49 908 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 909 fixed |= DR6_RTM;
910 return fixed;
911}
912
338dbc97 913static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 914{
915 switch (dr) {
916 case 0 ... 3:
917 vcpu->arch.db[dr] = val;
918 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
919 vcpu->arch.eff_db[dr] = val;
920 break;
921 case 4:
020df079
GN		 922 /* fall through */
923 case 6:
338dbc97
GN		 924 if (val & 0xffffffff00000000ULL)
925 return -1; /* #GP */
6f43ed01 926 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 927 kvm_update_dr6(vcpu);
020df079
GN		 928 break;
929 case 5:
020df079
GN		 930 /* fall through */
931 default: /* 7 */
338dbc97
GN		 932 if (val & 0xffffffff00000000ULL)
933 return -1; /* #GP */
020df079 934 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 935 kvm_update_dr7(vcpu);
020df079
GN		 936 break;
937 }
938
939 return 0;
940}
338dbc97
GN		 941
942int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
943{
16f8a6f9 944 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 945 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 946 return 1;
947 }
948 return 0;
338dbc97 949}
020df079
GN		 950EXPORT_SYMBOL_GPL(kvm_set_dr);
951
16f8a6f9 952int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 953{
954 switch (dr) {
955 case 0 ... 3:
956 *val = vcpu->arch.db[dr];
957 break;
958 case 4:
020df079
GN		 959 /* fall through */
960 case 6:
73aaf249
JK		 961 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
962 *val = vcpu->arch.dr6;
963 else
964 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 965 break;
966 case 5:
020df079
GN		 967 /* fall through */
968 default: /* 7 */
969 *val = vcpu->arch.dr7;
970 break;
971 }
338dbc97
GN		 972 return 0;
973}
020df079
GN		 974EXPORT_SYMBOL_GPL(kvm_get_dr);
975
022cd0e8
AK		 976bool kvm_rdpmc(struct kvm_vcpu *vcpu)
977{
978 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
979 u64 data;
980 int err;
981
c6702c9d 982 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 983 if (err)
984 return err;
985 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
986 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
987 return err;
988}
989EXPORT_SYMBOL_GPL(kvm_rdpmc);
990
043405e1
CO		 991/*
992 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
993 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
994 *
995 * This list is modified at module load time to reflect the
e3267cbb 996 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 997 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
998 * may depend on host virtualization features rather than host cpu features.
043405e1 999 */
e3267cbb 1000
043405e1
CO		 1001static u32 msrs_to_save[] = {
1002 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1003 MSR_STAR,
043405e1
CO		 1004#ifdef CONFIG_X86_64
1005 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1006#endif
b3897a49 1007 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1008 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 1009};
1010
1011static unsigned num_msrs_to_save;
1012
62ef68bb
PB		 1013static u32 emulated_msrs[] = {
1014 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1015 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1016 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1017 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1018 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1019 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1020 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1021 HV_X64_MSR_RESET,
11c4b1ca 1022 HV_X64_MSR_VP_INDEX,
9eec50b8 1023 HV_X64_MSR_VP_RUNTIME,
5c919412 1024 HV_X64_MSR_SCONTROL,
1f4b34f8 1025 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1026 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1027 MSR_KVM_PV_EOI_EN,
1028
ba904635 1029 MSR_IA32_TSC_ADJUST,
a3e06bbe 1030 MSR_IA32_TSCDEADLINE,
043405e1 1031 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1032 MSR_IA32_MCG_STATUS,
1033 MSR_IA32_MCG_CTL,
c45dcc71 1034 MSR_IA32_MCG_EXT_CTL,
64d60670 1035 MSR_IA32_SMBASE,
db2336a8
KH		 1036 MSR_PLATFORM_INFO,
1037 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1038};
1039
62ef68bb
PB		 1040static unsigned num_emulated_msrs;
1041
384bb783 1042bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1043{
b69e8cae 1044 if (efer & efer_reserved_bits)
384bb783 1045 return false;
15c4a640 1046
1b4d56b8 1047 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1048 return false;
1b2fd70c 1049
1b4d56b8 1050 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1051 return false;
d8017474 1052
384bb783
JK		 1053 return true;
1054}
1055EXPORT_SYMBOL_GPL(kvm_valid_efer);
1056
1057static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1058{
1059 u64 old_efer = vcpu->arch.efer;
1060
1061 if (!kvm_valid_efer(vcpu, efer))
1062 return 1;
1063
1064 if (is_paging(vcpu)
1065 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1066 return 1;
1067
15c4a640 1068 efer &= ~EFER_LMA;
f6801dff 1069 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1070
a3d204e2
SY		 1071 kvm_x86_ops->set_efer(vcpu, efer);
1072
aad82703
SY		 1073 /* Update reserved bits */
1074 if ((efer ^ old_efer) & EFER_NX)
1075 kvm_mmu_reset_context(vcpu);
1076
b69e8cae 1077 return 0;
15c4a640
CO		 1078}
1079
f2b4b7dd
JR		 1080void kvm_enable_efer_bits(u64 mask)
1081{
1082 efer_reserved_bits &= ~mask;
1083}
1084EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1085
15c4a640
CO		 1086/*
1087 * Writes msr value into into the appropriate "register".
1088 * Returns 0 on success, non-0 otherwise.
1089 * Assumes vcpu_load() was already called.
1090 */
8fe8ab46 1091int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1092{
854e8bb1
NA		 1093 switch (msr->index) {
1094 case MSR_FS_BASE:
1095 case MSR_GS_BASE:
1096 case MSR_KERNEL_GS_BASE:
1097 case MSR_CSTAR:
1098 case MSR_LSTAR:
fd8cb433 1099 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1100 return 1;
1101 break;
1102 case MSR_IA32_SYSENTER_EIP:
1103 case MSR_IA32_SYSENTER_ESP:
1104 /*
1105 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1106 * non-canonical address is written on Intel but not on
1107 * AMD (which ignores the top 32-bits, because it does
1108 * not implement 64-bit SYSENTER).
1109 *
1110 * 64-bit code should hence be able to write a non-canonical
1111 * value on AMD. Making the address canonical ensures that
1112 * vmentry does not fail on Intel after writing a non-canonical
1113 * value, and that something deterministic happens if the guest
1114 * invokes 64-bit SYSENTER.
1115 */
fd8cb433 1116 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1117 }
8fe8ab46 1118 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1119}
854e8bb1 1120EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1121
313a3dc7
CO		 1122/*
1123 * Adapt set_msr() to msr_io()'s calling convention
1124 */
609e36d3
PB		 1125static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1126{
1127 struct msr_data msr;
1128 int r;
1129
1130 msr.index = index;
1131 msr.host_initiated = true;
1132 r = kvm_get_msr(vcpu, &msr);
1133 if (r)
1134 return r;
1135
1136 *data = msr.data;
1137 return 0;
1138}
1139
313a3dc7
CO		 1140static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1141{
8fe8ab46
WA		 1142 struct msr_data msr;
1143
1144 msr.data = *data;
1145 msr.index = index;
1146 msr.host_initiated = true;
1147 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1148}
1149
16e8d74d
MT		 1150#ifdef CONFIG_X86_64
1151struct pvclock_gtod_data {
1152 seqcount_t seq;
1153
1154 struct { /* extract of a clocksource struct */
1155 int vclock_mode;
a5a1d1c2
TG		 1156 u64 cycle_last;
1157 u64 mask;
16e8d74d
MT		 1158 u32 mult;
1159 u32 shift;
1160 } clock;
1161
cbcf2dd3
TG		 1162 u64 boot_ns;
1163 u64 nsec_base;
55dd00a7 1164 u64 wall_time_sec;
16e8d74d
MT		 1165};
1166
1167static struct pvclock_gtod_data pvclock_gtod_data;
1168
1169static void update_pvclock_gtod(struct timekeeper *tk)
1170{
1171 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1172 u64 boot_ns;
1173
876e7881 1174 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1175
1176 write_seqcount_begin(&vdata->seq);
1177
1178 /* copy pvclock gtod data */
876e7881
PZ		 1179 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1180 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1181 vdata->clock.mask = tk->tkr_mono.mask;
1182 vdata->clock.mult = tk->tkr_mono.mult;
1183 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1184
cbcf2dd3 1185 vdata->boot_ns = boot_ns;
876e7881 1186 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1187
55dd00a7
MT		 1188 vdata->wall_time_sec = tk->xtime_sec;
1189
16e8d74d
MT		 1190 write_seqcount_end(&vdata->seq);
1191}
1192#endif
1193
bab5bb39
NK		 1194void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1195{
1196 /*
1197 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1198 * vcpu_enter_guest. This function is only called from
1199 * the physical CPU that is running vcpu.
1200 */
1201 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1202}
16e8d74d 1203
18068523
GOC		 1204static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1205{
9ed3c444
AK		 1206 int version;
1207 int r;
50d0a0f9 1208 struct pvclock_wall_clock wc;
87aeb54f 1209 struct timespec64 boot;
18068523
GOC		 1210
1211 if (!wall_clock)
1212 return;
1213
9ed3c444
AK		 1214 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1215 if (r)
1216 return;
1217
1218 if (version & 1)
1219 ++version; /* first time write, random junk */
1220
1221 ++version;
18068523 1222
1dab1345
NK		 1223 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1224 return;
18068523 1225
50d0a0f9
GH		 1226 /*
1227 * The guest calculates current wall clock time by adding
34c238a1 1228 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1229 * wall clock specified here. guest system time equals host
1230 * system time for us, thus we must fill in host boot time here.
1231 */
87aeb54f 1232 getboottime64(&boot);
50d0a0f9 1233
4b648665 1234 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1235 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1236 boot = timespec64_sub(boot, ts);
4b648665 1237 }
87aeb54f 1238 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1239 wc.nsec = boot.tv_nsec;
1240 wc.version = version;
18068523
GOC		 1241
1242 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1243
1244 version++;
1245 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1246}
1247
50d0a0f9
GH		 1248static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1249{
b51012de
PB		 1250 do_shl32_div32(dividend, divisor);
1251 return dividend;
50d0a0f9
GH		 1252}
1253
3ae13faa 1254static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1255 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1256{
5f4e3f88 1257 uint64_t scaled64;
50d0a0f9
GH		 1258 int32_t shift = 0;
1259 uint64_t tps64;
1260 uint32_t tps32;
1261
3ae13faa
PB		 1262 tps64 = base_hz;
1263 scaled64 = scaled_hz;
50933623 1264 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1265 tps64 >>= 1;
1266 shift--;
1267 }
1268
1269 tps32 = (uint32_t)tps64;
50933623
JK		 1270 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1271 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1272 scaled64 >>= 1;
1273 else
1274 tps32 <<= 1;
50d0a0f9
GH		 1275 shift++;
1276 }
1277
5f4e3f88
ZA		 1278 *pshift = shift;
1279 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1280
3ae13faa
PB		 1281 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1282 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1283}
1284
d828199e 1285#ifdef CONFIG_X86_64
16e8d74d 1286static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1287#endif
16e8d74d 1288
c8076604 1289static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1290static unsigned long max_tsc_khz;
c8076604 1291
cc578287 1292static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1293{
cc578287
ZA		 1294 u64 v = (u64)khz * (1000000 + ppm);
1295 do_div(v, 1000000);
1296 return v;
1e993611
JR		 1297}
1298
381d585c
HZ		 1299static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1300{
1301 u64 ratio;
1302
1303 /* Guest TSC same frequency as host TSC? */
1304 if (!scale) {
1305 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1306 return 0;
1307 }
1308
1309 /* TSC scaling supported? */
1310 if (!kvm_has_tsc_control) {
1311 if (user_tsc_khz > tsc_khz) {
1312 vcpu->arch.tsc_catchup = 1;
1313 vcpu->arch.tsc_always_catchup = 1;
1314 return 0;
1315 } else {
1316 WARN(1, "user requested TSC rate below hardware speed\n");
1317 return -1;
1318 }
1319 }
1320
1321 /* TSC scaling required - calculate ratio */
1322 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1323 user_tsc_khz, tsc_khz);
1324
1325 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1326 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1327 user_tsc_khz);
1328 return -1;
1329 }
1330
1331 vcpu->arch.tsc_scaling_ratio = ratio;
1332 return 0;
1333}
1334
4941b8cb 1335static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1336{
cc578287
ZA		 1337 u32 thresh_lo, thresh_hi;
1338 int use_scaling = 0;
217fc9cf 1339
03ba32ca 1340 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1341 if (user_tsc_khz == 0) {
ad721883
HZ		 1342 /* set tsc_scaling_ratio to a safe value */
1343 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1344 return -1;
ad721883 1345 }
03ba32ca 1346
c285545f 1347 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1348 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1349 &vcpu->arch.virtual_tsc_shift,
1350 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1351 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1352
1353 /*
1354 * Compute the variation in TSC rate which is acceptable
1355 * within the range of tolerance and decide if the
1356 * rate being applied is within that bounds of the hardware
1357 * rate. If so, no scaling or compensation need be done.
1358 */
1359 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1360 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1361 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1362 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1363 use_scaling = 1;
1364 }
4941b8cb 1365 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1366}
1367
1368static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1369{
e26101b1 1370 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1371 vcpu->arch.virtual_tsc_mult,
1372 vcpu->arch.virtual_tsc_shift);
e26101b1 1373 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1374 return tsc;
1375}
1376
69b0049a 1377static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1378{
1379#ifdef CONFIG_X86_64
1380 bool vcpus_matched;
b48aa97e
MT		 1381 struct kvm_arch *ka = &vcpu->kvm->arch;
1382 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1383
1384 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1385 atomic_read(&vcpu->kvm->online_vcpus));
1386
7f187922
MT		 1387 /*
1388 * Once the masterclock is enabled, always perform request in
1389 * order to update it.
1390 *
1391 * In order to enable masterclock, the host clocksource must be TSC
1392 * and the vcpus need to have matched TSCs. When that happens,
1393 * perform request to enable masterclock.
1394 */
1395 if (ka->use_master_clock ||
1396 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1397 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1398
1399 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1400 atomic_read(&vcpu->kvm->online_vcpus),
1401 ka->use_master_clock, gtod->clock.vclock_mode);
1402#endif
1403}
1404
ba904635
WA		 1405static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1406{
3e3f5026 1407 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1408 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1409}
1410
35181e86
HZ		 1411/*
1412 * Multiply tsc by a fixed point number represented by ratio.
1413 *
1414 * The most significant 64-N bits (mult) of ratio represent the
1415 * integral part of the fixed point number; the remaining N bits
1416 * (frac) represent the fractional part, ie. ratio represents a fixed
1417 * point number (mult + frac * 2^(-N)).
1418 *
1419 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1420 */
1421static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1422{
1423 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1424}
1425
1426u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1427{
1428 u64 _tsc = tsc;
1429 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1430
1431 if (ratio != kvm_default_tsc_scaling_ratio)
1432 _tsc = __scale_tsc(ratio, tsc);
1433
1434 return _tsc;
1435}
1436EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1437
07c1419a
HZ		 1438static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1439{
1440 u64 tsc;
1441
1442 tsc = kvm_scale_tsc(vcpu, rdtsc());
1443
1444 return target_tsc - tsc;
1445}
1446
4ba76538
HZ		 1447u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1448{
ea26e4ec 1449 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1450}
1451EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1452
a545ab6a
LC		 1453static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1454{
1455 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1456 vcpu->arch.tsc_offset = offset;
1457}
1458
8fe8ab46 1459void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1460{
1461 struct kvm *kvm = vcpu->kvm;
f38e098f 1462 u64 offset, ns, elapsed;
99e3e30a 1463 unsigned long flags;
b48aa97e 1464 bool matched;
0d3da0d2 1465 bool already_matched;
8fe8ab46 1466 u64 data = msr->data;
c5e8ec8e 1467 bool synchronizing = false;
99e3e30a 1468
038f8c11 1469 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1470 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1471 ns = ktime_get_boot_ns();
f38e098f 1472 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1473
03ba32ca 1474 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1475 if (data == 0 && msr->host_initiated) {
1476 /*
1477 * detection of vcpu initialization -- need to sync
1478 * with other vCPUs. This particularly helps to keep
1479 * kvm_clock stable after CPU hotplug
1480 */
1481 synchronizing = true;
1482 } else {
1483 u64 tsc_exp = kvm->arch.last_tsc_write +
1484 nsec_to_cycles(vcpu, elapsed);
1485 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1486 /*
1487 * Special case: TSC write with a small delta (1 second)
1488 * of virtual cycle time against real time is
1489 * interpreted as an attempt to synchronize the CPU.
1490 */
1491 synchronizing = data < tsc_exp + tsc_hz &&
1492 data + tsc_hz > tsc_exp;
1493 }
c5e8ec8e 1494 }
f38e098f
ZA		 1495
1496 /*
5d3cb0f6
ZA		 1497 * For a reliable TSC, we can match TSC offsets, and for an unstable
1498 * TSC, we add elapsed time in this computation. We could let the
1499 * compensation code attempt to catch up if we fall behind, but
1500 * it's better to try to match offsets from the beginning.
1501 */
c5e8ec8e 1502 if (synchronizing &&
5d3cb0f6 1503 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1504 if (!check_tsc_unstable()) {
e26101b1 1505 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1506 pr_debug("kvm: matched tsc offset for %llu\n", data);
1507 } else {
857e4099 1508 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1509 data += delta;
07c1419a 1510 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1511 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1512 }
b48aa97e 1513 matched = true;
0d3da0d2 1514 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1515 } else {
1516 /*
1517 * We split periods of matched TSC writes into generations.
1518 * For each generation, we track the original measured
1519 * nanosecond time, offset, and write, so if TSCs are in
1520 * sync, we can match exact offset, and if not, we can match
4a969980 1521 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1522 *
1523 * These values are tracked in kvm->arch.cur_xxx variables.
1524 */
1525 kvm->arch.cur_tsc_generation++;
1526 kvm->arch.cur_tsc_nsec = ns;
1527 kvm->arch.cur_tsc_write = data;
1528 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1529 matched = false;
0d3da0d2 1530 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1531 kvm->arch.cur_tsc_generation, data);
f38e098f 1532 }
e26101b1
ZA		 1533
1534 /*
1535 * We also track th most recent recorded KHZ, write and time to
1536 * allow the matching interval to be extended at each write.
1537 */
f38e098f
ZA		 1538 kvm->arch.last_tsc_nsec = ns;
1539 kvm->arch.last_tsc_write = data;
5d3cb0f6 1540 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1541
b183aa58 1542 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1543
1544 /* Keep track of which generation this VCPU has synchronized to */
1545 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1546 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1547 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1548
d6321d49 1549 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1550 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1551
a545ab6a 1552 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1553 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1554
1555 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1556 if (!matched) {
b48aa97e 1557 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1558 } else if (!already_matched) {
1559 kvm->arch.nr_vcpus_matched_tsc++;
1560 }
b48aa97e
MT		 1561
1562 kvm_track_tsc_matching(vcpu);
1563 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1564}
e26101b1 1565
99e3e30a
ZA		 1566EXPORT_SYMBOL_GPL(kvm_write_tsc);
1567
58ea6767
HZ		 1568static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1569 s64 adjustment)
1570{
ea26e4ec 1571 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1572}
1573
1574static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1575{
1576 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1577 WARN_ON(adjustment < 0);
1578 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1579 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1580}
1581
d828199e
MT		 1582#ifdef CONFIG_X86_64
1583
a5a1d1c2 1584static u64 read_tsc(void)
d828199e 1585{
a5a1d1c2 1586 u64 ret = (u64)rdtsc_ordered();
03b9730b 1587 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1588
1589 if (likely(ret >= last))
1590 return ret;
1591
1592 /*
1593 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1594 * predictable (it's just a function of time and the likely is
d828199e
MT		 1595 * very likely) and there's a data dependence, so force GCC
1596 * to generate a branch instead. I don't barrier() because
1597 * we don't actually need a barrier, and if this function
1598 * ever gets inlined it will generate worse code.
1599 */
1600 asm volatile ("");
1601 return last;
1602}
1603
a5a1d1c2 1604static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1605{
1606 long v;
1607 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1608
1609 *cycle_now = read_tsc();
1610
1611 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1612 return v * gtod->clock.mult;
1613}
1614
a5a1d1c2 1615static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1616{
cbcf2dd3 1617 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1618 unsigned long seq;
d828199e 1619 int mode;
cbcf2dd3 1620 u64 ns;
d828199e 1621
d828199e
MT		 1622 do {
1623 seq = read_seqcount_begin(&gtod->seq);
1624 mode = gtod->clock.vclock_mode;
cbcf2dd3 1625 ns = gtod->nsec_base;
d828199e
MT		 1626 ns += vgettsc(cycle_now);
1627 ns >>= gtod->clock.shift;
cbcf2dd3 1628 ns += gtod->boot_ns;
d828199e 1629 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1630 *t = ns;
d828199e
MT		 1631
1632 return mode;
1633}
1634
55dd00a7
MT		 1635static int do_realtime(struct timespec *ts, u64 *cycle_now)
1636{
1637 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1638 unsigned long seq;
1639 int mode;
1640 u64 ns;
1641
1642 do {
1643 seq = read_seqcount_begin(&gtod->seq);
1644 mode = gtod->clock.vclock_mode;
1645 ts->tv_sec = gtod->wall_time_sec;
1646 ns = gtod->nsec_base;
1647 ns += vgettsc(cycle_now);
1648 ns >>= gtod->clock.shift;
1649 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1650
1651 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1652 ts->tv_nsec = ns;
1653
1654 return mode;
1655}
1656
d828199e 1657/* returns true if host is using tsc clocksource */
a5a1d1c2 1658static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1659{
d828199e
MT		 1660 /* checked again under seqlock below */
1661 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1662 return false;
1663
cbcf2dd3 1664 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1665}
55dd00a7
MT		 1666
1667/* returns true if host is using tsc clocksource */
1668static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1669 u64 *cycle_now)
1670{
1671 /* checked again under seqlock below */
1672 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1673 return false;
1674
1675 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1676}
d828199e
MT		 1677#endif
1678
1679/*
1680 *
b48aa97e
MT		 1681 * Assuming a stable TSC across physical CPUS, and a stable TSC
1682 * across virtual CPUs, the following condition is possible.
1683 * Each numbered line represents an event visible to both
d828199e
MT		 1684 * CPUs at the next numbered event.
1685 *
1686 * "timespecX" represents host monotonic time. "tscX" represents
1687 * RDTSC value.
1688 *
1689 * VCPU0 on CPU0 | VCPU1 on CPU1
1690 *
1691 * 1. read timespec0,tsc0
1692 * 2. | timespec1 = timespec0 + N
1693 * | tsc1 = tsc0 + M
1694 * 3. transition to guest | transition to guest
1695 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1696 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1697 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1698 *
1699 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1700 *
1701 * - ret0 < ret1
1702 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1703 * ...
1704 * - 0 < N - M => M < N
1705 *
1706 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1707 * always the case (the difference between two distinct xtime instances
1708 * might be smaller then the difference between corresponding TSC reads,
1709 * when updating guest vcpus pvclock areas).
1710 *
1711 * To avoid that problem, do not allow visibility of distinct
1712 * system_timestamp/tsc_timestamp values simultaneously: use a master
1713 * copy of host monotonic time values. Update that master copy
1714 * in lockstep.
1715 *
b48aa97e 1716 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1717 *
1718 */
1719
1720static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1721{
1722#ifdef CONFIG_X86_64
1723 struct kvm_arch *ka = &kvm->arch;
1724 int vclock_mode;
b48aa97e
MT		 1725 bool host_tsc_clocksource, vcpus_matched;
1726
1727 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1728 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1729
1730 /*
1731 * If the host uses TSC clock, then passthrough TSC as stable
1732 * to the guest.
1733 */
b48aa97e 1734 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1735 &ka->master_kernel_ns,
1736 &ka->master_cycle_now);
1737
16a96021 1738 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1739 && !ka->backwards_tsc_observed
54750f2c 1740 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1741
d828199e
MT		 1742 if (ka->use_master_clock)
1743 atomic_set(&kvm_guest_has_master_clock, 1);
1744
1745 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1746 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1747 vcpus_matched);
d828199e
MT		 1748#endif
1749}
1750
2860c4b1
PB		 1751void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1752{
1753 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1754}
1755
2e762ff7
MT		 1756static void kvm_gen_update_masterclock(struct kvm *kvm)
1757{
1758#ifdef CONFIG_X86_64
1759 int i;
1760 struct kvm_vcpu *vcpu;
1761 struct kvm_arch *ka = &kvm->arch;
1762
1763 spin_lock(&ka->pvclock_gtod_sync_lock);
1764 kvm_make_mclock_inprogress_request(kvm);
1765 /* no guest entries from this point */
1766 pvclock_update_vm_gtod_copy(kvm);
1767
1768 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1769 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1770
1771 /* guest entries allowed */
1772 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1773 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1774
1775 spin_unlock(&ka->pvclock_gtod_sync_lock);
1776#endif
1777}
1778
e891a32e 1779u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1780{
108b249c 1781 struct kvm_arch *ka = &kvm->arch;
8b953440 1782 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1783 u64 ret;
108b249c 1784
8b953440
PB		 1785 spin_lock(&ka->pvclock_gtod_sync_lock);
1786 if (!ka->use_master_clock) {
1787 spin_unlock(&ka->pvclock_gtod_sync_lock);
1788 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1789 }
1790
8b953440
PB		 1791 hv_clock.tsc_timestamp = ka->master_cycle_now;
1792 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1793 spin_unlock(&ka->pvclock_gtod_sync_lock);
1794
e2c2206a
WL		 1795 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1796 get_cpu();
1797
8b953440
PB		 1798 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1799 &hv_clock.tsc_shift,
1800 &hv_clock.tsc_to_system_mul);
e2c2206a
WL		 1801 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1802
1803 put_cpu();
1804
1805 return ret;
108b249c
PB		 1806}
1807
0d6dd2ff
PB		 1808static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1809{
1810 struct kvm_vcpu_arch *vcpu = &v->arch;
1811 struct pvclock_vcpu_time_info guest_hv_clock;
1812
4e335d9e 1813 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1814 &guest_hv_clock, sizeof(guest_hv_clock))))
1815 return;
1816
1817 /* This VCPU is paused, but it's legal for a guest to read another
1818 * VCPU's kvmclock, so we really have to follow the specification where
1819 * it says that version is odd if data is being modified, and even after
1820 * it is consistent.
1821 *
1822 * Version field updates must be kept separate. This is because
1823 * kvm_write_guest_cached might use a "rep movs" instruction, and
1824 * writes within a string instruction are weakly ordered. So there
1825 * are three writes overall.
1826 *
1827 * As a small optimization, only write the version field in the first
1828 * and third write. The vcpu->pv_time cache is still valid, because the
1829 * version field is the first in the struct.
1830 */
1831 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1832
51c4b8bb
LA		 1833 if (guest_hv_clock.version & 1)
1834 ++guest_hv_clock.version; /* first time write, random junk */
1835
0d6dd2ff 1836 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1837 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1838 &vcpu->hv_clock,
1839 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1840
1841 smp_wmb();
1842
1843 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1844 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1845
1846 if (vcpu->pvclock_set_guest_stopped_request) {
1847 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1848 vcpu->pvclock_set_guest_stopped_request = false;
1849 }
1850
1851 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1852
4e335d9e
PB		 1853 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1854 &vcpu->hv_clock,
1855 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1856
1857 smp_wmb();
1858
1859 vcpu->hv_clock.version++;
4e335d9e
PB		 1860 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1861 &vcpu->hv_clock,
1862 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1863}
1864
34c238a1 1865static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1866{
78db6a50 1867 unsigned long flags, tgt_tsc_khz;
18068523 1868 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1869 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1870 s64 kernel_ns;
d828199e 1871 u64 tsc_timestamp, host_tsc;
51d59c6b 1872 u8 pvclock_flags;
d828199e
MT		 1873 bool use_master_clock;
1874
1875 kernel_ns = 0;
1876 host_tsc = 0;
18068523 1877
d828199e
MT		 1878 /*
1879 * If the host uses TSC clock, then passthrough TSC as stable
1880 * to the guest.
1881 */
1882 spin_lock(&ka->pvclock_gtod_sync_lock);
1883 use_master_clock = ka->use_master_clock;
1884 if (use_master_clock) {
1885 host_tsc = ka->master_cycle_now;
1886 kernel_ns = ka->master_kernel_ns;
1887 }
1888 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1889
1890 /* Keep irq disabled to prevent changes to the clock */
1891 local_irq_save(flags);
78db6a50
PB		 1892 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1893 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1894 local_irq_restore(flags);
1895 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1896 return 1;
1897 }
d828199e 1898 if (!use_master_clock) {
4ea1636b 1899 host_tsc = rdtsc();
108b249c 1900 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1901 }
1902
4ba76538 1903 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1904
c285545f
ZA		 1905 /*
1906 * We may have to catch up the TSC to match elapsed wall clock
1907 * time for two reasons, even if kvmclock is used.
1908 * 1) CPU could have been running below the maximum TSC rate
1909 * 2) Broken TSC compensation resets the base at each VCPU
1910 * entry to avoid unknown leaps of TSC even when running
1911 * again on the same CPU. This may cause apparent elapsed
1912 * time to disappear, and the guest to stand still or run
1913 * very slowly.
1914 */
1915 if (vcpu->tsc_catchup) {
1916 u64 tsc = compute_guest_tsc(v, kernel_ns);
1917 if (tsc > tsc_timestamp) {
f1e2b260 1918 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1919 tsc_timestamp = tsc;
1920 }
50d0a0f9
GH		 1921 }
1922
18068523
GOC		 1923 local_irq_restore(flags);
1924
0d6dd2ff 1925 /* With all the info we got, fill in the values */
18068523 1926
78db6a50
PB		 1927 if (kvm_has_tsc_control)
1928 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1929
1930 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1931 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1932 &vcpu->hv_clock.tsc_shift,
1933 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1934 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1935 }
1936
1d5f066e 1937 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1938 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1939 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1940
d828199e 1941 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1942 pvclock_flags = 0;
d828199e
MT		 1943 if (use_master_clock)
1944 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1945
78c0337a
MT		 1946 vcpu->hv_clock.flags = pvclock_flags;
1947
095cf55d
PB		 1948 if (vcpu->pv_time_enabled)
1949 kvm_setup_pvclock_page(v);
1950 if (v == kvm_get_vcpu(v->kvm, 0))
1951 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1952 return 0;
c8076604
GH		 1953}
1954
0061d53d
MT		 1955/*
1956 * kvmclock updates which are isolated to a given vcpu, such as
1957 * vcpu->cpu migration, should not allow system_timestamp from
1958 * the rest of the vcpus to remain static. Otherwise ntp frequency
1959 * correction applies to one vcpu's system_timestamp but not
1960 * the others.
1961 *
1962 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1963 * We need to rate-limit these requests though, as they can
1964 * considerably slow guests that have a large number of vcpus.
1965 * The time for a remote vcpu to update its kvmclock is bound
1966 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1967 */
1968
7e44e449
AJ		 1969#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1970
1971static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1972{
1973 int i;
7e44e449
AJ		 1974 struct delayed_work *dwork = to_delayed_work(work);
1975 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1976 kvmclock_update_work);
1977 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1978 struct kvm_vcpu *vcpu;
1979
1980 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1981 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1982 kvm_vcpu_kick(vcpu);
1983 }
1984}
1985
7e44e449
AJ		 1986static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1987{
1988 struct kvm *kvm = v->kvm;
1989
105b21bb 1990 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1991 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1992 KVMCLOCK_UPDATE_DELAY);
1993}
1994
332967a3
AJ		 1995#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1996
1997static void kvmclock_sync_fn(struct work_struct *work)
1998{
1999 struct delayed_work *dwork = to_delayed_work(work);
2000 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2001 kvmclock_sync_work);
2002 struct kvm *kvm = container_of(ka, struct kvm, arch);
2003
630994b3
MT		 2004 if (!kvmclock_periodic_sync)
2005 return;
2006
332967a3
AJ		 2007 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2008 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2009 KVMCLOCK_SYNC_PERIOD);
2010}
2011
9ffd986c 2012static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2013{
890ca9ae
HY		 2014 u64 mcg_cap = vcpu->arch.mcg_cap;
2015 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2016 u32 msr = msr_info->index;
2017 u64 data = msr_info->data;
890ca9ae 2018
15c4a640 2019 switch (msr) {
15c4a640 2020 case MSR_IA32_MCG_STATUS:
890ca9ae 2021 vcpu->arch.mcg_status = data;
15c4a640 2022 break;
c7ac679c 2023 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2024 if (!(mcg_cap & MCG_CTL_P))
2025 return 1;
2026 if (data != 0 && data != ~(u64)0)
2027 return -1;
2028 vcpu->arch.mcg_ctl = data;
2029 break;
2030 default:
2031 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2032 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2033 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2034 /* only 0 or all 1s can be written to IA32_MCi_CTL
2035 * some Linux kernels though clear bit 10 in bank 4 to
2036 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2037 * this to avoid an uncatched #GP in the guest
2038 */
890ca9ae 2039 if ((offset & 0x3) == 0 &&
114be429 2040 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2041 return -1;
9ffd986c
WL		 2042 if (!msr_info->host_initiated &&
2043 (offset & 0x3) == 1 && data != 0)
2044 return -1;
890ca9ae
HY		 2045 vcpu->arch.mce_banks[offset] = data;
2046 break;
2047 }
2048 return 1;
2049 }
2050 return 0;
2051}
2052
ffde22ac
ES		 2053static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2054{
2055 struct kvm *kvm = vcpu->kvm;
2056 int lm = is_long_mode(vcpu);
2057 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2058 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2059 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2060 : kvm->arch.xen_hvm_config.blob_size_32;
2061 u32 page_num = data & ~PAGE_MASK;
2062 u64 page_addr = data & PAGE_MASK;
2063 u8 *page;
2064 int r;
2065
2066 r = -E2BIG;
2067 if (page_num >= blob_size)
2068 goto out;
2069 r = -ENOMEM;
ff5c2c03
SL		 2070 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2071 if (IS_ERR(page)) {
2072 r = PTR_ERR(page);
ffde22ac 2073 goto out;
ff5c2c03 2074 }
54bf36aa 2075 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2076 goto out_free;
2077 r = 0;
2078out_free:
2079 kfree(page);
2080out:
2081 return r;
2082}
2083
344d9588
GN		 2084static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2085{
2086 gpa_t gpa = data & ~0x3f;
2087
52a5c155
WL		 2088 /* Bits 3:5 are reserved, Should be zero */
2089 if (data & 0x38)
344d9588
GN		 2090 return 1;
2091
2092 vcpu->arch.apf.msr_val = data;
2093
2094 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2095 kvm_clear_async_pf_completion_queue(vcpu);
2096 kvm_async_pf_hash_reset(vcpu);
2097 return 0;
2098 }
2099
4e335d9e 2100 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2101 sizeof(u32)))
344d9588
GN		 2102 return 1;
2103
6adba527 2104 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2105 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2106 kvm_async_pf_wakeup_all(vcpu);
2107 return 0;
2108}
2109
12f9a48f
GC		 2110static void kvmclock_reset(struct kvm_vcpu *vcpu)
2111{
0b79459b 2112 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2113}
2114
c9aaa895
GC		 2115static void record_steal_time(struct kvm_vcpu *vcpu)
2116{
2117 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2118 return;
2119
4e335d9e 2120 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2121 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2122 return;
2123
0b9f6c46
PX		 2124 vcpu->arch.st.steal.preempted = 0;
2125
35f3fae1
WL		 2126 if (vcpu->arch.st.steal.version & 1)
2127 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2128
2129 vcpu->arch.st.steal.version += 1;
2130
4e335d9e 2131 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2132 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2133
2134 smp_wmb();
2135
c54cdf14
LC		 2136 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2137 vcpu->arch.st.last_steal;
2138 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2139
4e335d9e 2140 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2141 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2142
2143 smp_wmb();
2144
2145 vcpu->arch.st.steal.version += 1;
c9aaa895 2146
4e335d9e 2147 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2148 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2149}
2150
8fe8ab46 2151int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2152{
5753785f 2153 bool pr = false;
8fe8ab46
WA		 2154 u32 msr = msr_info->index;
2155 u64 data = msr_info->data;
5753785f 2156
15c4a640 2157 switch (msr) {
2e32b719
BP		 2158 case MSR_AMD64_NB_CFG:
2159 case MSR_IA32_UCODE_REV:
2160 case MSR_IA32_UCODE_WRITE:
2161 case MSR_VM_HSAVE_PA:
2162 case MSR_AMD64_PATCH_LOADER:
2163 case MSR_AMD64_BU_CFG2:
405a353a 2164 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2165 break;
2166
15c4a640 2167 case MSR_EFER:
b69e8cae 2168 return set_efer(vcpu, data);
8f1589d9
AP		 2169 case MSR_K7_HWCR:
2170 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2171 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2172 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2173 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2174 if (data != 0) {
a737f256
CD		 2175 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2176 data);
8f1589d9
AP		 2177 return 1;
2178 }
15c4a640 2179 break;
f7c6d140
AP		 2180 case MSR_FAM10H_MMIO_CONF_BASE:
2181 if (data != 0) {
a737f256
CD		 2182 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2183 "0x%llx\n", data);
f7c6d140
AP		 2184 return 1;
2185 }
15c4a640 2186 break;
b5e2fec0
AG		 2187 case MSR_IA32_DEBUGCTLMSR:
2188 if (!data) {
2189 /* We support the non-activated case already */
2190 break;
2191 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2192 /* Values other than LBR and BTF are vendor-specific,
2193 thus reserved and should throw a #GP */
2194 return 1;
2195 }
a737f256
CD		 2196 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2197 __func__, data);
b5e2fec0 2198 break;
9ba075a6 2199 case 0x200 ... 0x2ff:
ff53604b 2200 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2201 case MSR_IA32_APICBASE:
58cb628d 2202 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2203 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2204 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2205 case MSR_IA32_TSCDEADLINE:
2206 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2207 break;
ba904635 2208 case MSR_IA32_TSC_ADJUST:
d6321d49 2209 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2210 if (!msr_info->host_initiated) {
d913b904 2211 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2212 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2213 }
2214 vcpu->arch.ia32_tsc_adjust_msr = data;
2215 }
2216 break;
15c4a640 2217 case MSR_IA32_MISC_ENABLE:
ad312c7c 2218 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2219 break;
64d60670
PB		 2220 case MSR_IA32_SMBASE:
2221 if (!msr_info->host_initiated)
2222 return 1;
2223 vcpu->arch.smbase = data;
2224 break;
11c6bffa 2225 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2226 case MSR_KVM_WALL_CLOCK:
2227 vcpu->kvm->arch.wall_clock = data;
2228 kvm_write_wall_clock(vcpu->kvm, data);
2229 break;
11c6bffa 2230 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2231 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2232 struct kvm_arch *ka = &vcpu->kvm->arch;
2233
12f9a48f 2234 kvmclock_reset(vcpu);
18068523 2235
54750f2c
MT		 2236 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2237 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2238
2239 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2240 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2241
2242 ka->boot_vcpu_runs_old_kvmclock = tmp;
2243 }
2244
18068523 2245 vcpu->arch.time = data;
0061d53d 2246 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2247
2248 /* we verify if the enable bit is set... */
2249 if (!(data & 1))
2250 break;
2251
4e335d9e 2252 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2253 &vcpu->arch.pv_time, data & ~1ULL,
2254 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2255 vcpu->arch.pv_time_enabled = false;
2256 else
2257 vcpu->arch.pv_time_enabled = true;
32cad84f 2258
18068523
GOC		 2259 break;
2260 }
344d9588
GN		 2261 case MSR_KVM_ASYNC_PF_EN:
2262 if (kvm_pv_enable_async_pf(vcpu, data))
2263 return 1;
2264 break;
c9aaa895
GC		 2265 case MSR_KVM_STEAL_TIME:
2266
2267 if (unlikely(!sched_info_on()))
2268 return 1;
2269
2270 if (data & KVM_STEAL_RESERVED_MASK)
2271 return 1;
2272
4e335d9e 2273 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2274 data & KVM_STEAL_VALID_BITS,
2275 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2276 return 1;
2277
2278 vcpu->arch.st.msr_val = data;
2279
2280 if (!(data & KVM_MSR_ENABLED))
2281 break;
2282
c9aaa895
GC		 2283 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2284
2285 break;
ae7a2a3f
MT		 2286 case MSR_KVM_PV_EOI_EN:
2287 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2288 return 1;
2289 break;
c9aaa895 2290
890ca9ae
HY		 2291 case MSR_IA32_MCG_CTL:
2292 case MSR_IA32_MCG_STATUS:
81760dcc 2293 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2294 return set_msr_mce(vcpu, msr_info);
71db6023 2295
6912ac32
WH		 2296 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2297 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2298 pr = true; /* fall through */
2299 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2300 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2301 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2302 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2303
2304 if (pr || data != 0)
a737f256
CD		 2305 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2306 "0x%x data 0x%llx\n", msr, data);
5753785f 2307 break;
84e0cefa
JS		 2308 case MSR_K7_CLK_CTL:
2309 /*
2310 * Ignore all writes to this no longer documented MSR.
2311 * Writes are only relevant for old K7 processors,
2312 * all pre-dating SVM, but a recommended workaround from
4a969980 2313 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2314 * affected processor models on the command line, hence
2315 * the need to ignore the workaround.
2316 */
2317 break;
55cd8e5a 2318 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2319 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2320 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2321 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2322 return kvm_hv_set_msr_common(vcpu, msr, data,
2323 msr_info->host_initiated);
91c9c3ed 2324 case MSR_IA32_BBL_CR_CTL3:
2325 /* Drop writes to this legacy MSR -- see rdmsr
2326 * counterpart for further detail.
2327 */
796f4687 2328 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2329 break;
2b036c6b 2330 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2331 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2332 return 1;
2333 vcpu->arch.osvw.length = data;
2334 break;
2335 case MSR_AMD64_OSVW_STATUS:
d6321d49 2336 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2337 return 1;
2338 vcpu->arch.osvw.status = data;
2339 break;
db2336a8
KH		 2340 case MSR_PLATFORM_INFO:
2341 if (!msr_info->host_initiated ||
2342 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2343 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2344 cpuid_fault_enabled(vcpu)))
2345 return 1;
2346 vcpu->arch.msr_platform_info = data;
2347 break;
2348 case MSR_MISC_FEATURES_ENABLES:
2349 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2350 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2351 !supports_cpuid_fault(vcpu)))
2352 return 1;
2353 vcpu->arch.msr_misc_features_enables = data;
2354 break;
15c4a640 2355 default:
ffde22ac
ES		 2356 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2357 return xen_hvm_config(vcpu, data);
c6702c9d 2358 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2359 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2360 if (!ignore_msrs) {
ae0f5499 2361 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2362 msr, data);
ed85c068
AP		 2363 return 1;
2364 } else {
796f4687 2365 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2366 msr, data);
ed85c068
AP		 2367 break;
2368 }
15c4a640
CO		 2369 }
2370 return 0;
2371}
2372EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2373
2374
2375/*
2376 * Reads an msr value (of 'msr_index') into 'pdata'.
2377 * Returns 0 on success, non-0 otherwise.
2378 * Assumes vcpu_load() was already called.
2379 */
609e36d3 2380int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2381{
609e36d3 2382 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2383}
ff651cb6 2384EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2385
890ca9ae 2386static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2387{
2388 u64 data;
890ca9ae
HY		 2389 u64 mcg_cap = vcpu->arch.mcg_cap;
2390 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2391
2392 switch (msr) {
15c4a640
CO		 2393 case MSR_IA32_P5_MC_ADDR:
2394 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2395 data = 0;
2396 break;
15c4a640 2397 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2398 data = vcpu->arch.mcg_cap;
2399 break;
c7ac679c 2400 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2401 if (!(mcg_cap & MCG_CTL_P))
2402 return 1;
2403 data = vcpu->arch.mcg_ctl;
2404 break;
2405 case MSR_IA32_MCG_STATUS:
2406 data = vcpu->arch.mcg_status;
2407 break;
2408 default:
2409 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2410 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2411 u32 offset = msr - MSR_IA32_MC0_CTL;
2412 data = vcpu->arch.mce_banks[offset];
2413 break;
2414 }
2415 return 1;
2416 }
2417 *pdata = data;
2418 return 0;
2419}
2420
609e36d3 2421int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2422{
609e36d3 2423 switch (msr_info->index) {
890ca9ae 2424 case MSR_IA32_PLATFORM_ID:
15c4a640 2425 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2426 case MSR_IA32_DEBUGCTLMSR:
2427 case MSR_IA32_LASTBRANCHFROMIP:
2428 case MSR_IA32_LASTBRANCHTOIP:
2429 case MSR_IA32_LASTINTFROMIP:
2430 case MSR_IA32_LASTINTTOIP:
60af2ecd 2431 case MSR_K8_SYSCFG:
3afb1121
PB		 2432 case MSR_K8_TSEG_ADDR:
2433 case MSR_K8_TSEG_MASK:
60af2ecd 2434 case MSR_K7_HWCR:
61a6bd67 2435 case MSR_VM_HSAVE_PA:
1fdbd48c 2436 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2437 case MSR_AMD64_NB_CFG:
f7c6d140 2438 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2439 case MSR_AMD64_BU_CFG2:
0c2df2a1 2440 case MSR_IA32_PERF_CTL:
405a353a 2441 case MSR_AMD64_DC_CFG:
609e36d3 2442 msr_info->data = 0;
15c4a640 2443 break;
6912ac32
WH		 2444 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2445 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2446 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2447 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2448 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2449 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2450 msr_info->data = 0;
5753785f 2451 break;
742bc670 2452 case MSR_IA32_UCODE_REV:
609e36d3 2453 msr_info->data = 0x100000000ULL;
742bc670 2454 break;
9ba075a6 2455 case MSR_MTRRcap:
9ba075a6 2456 case 0x200 ... 0x2ff:
ff53604b 2457 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2458 case 0xcd: /* fsb frequency */
609e36d3 2459 msr_info->data = 3;
15c4a640 2460 break;
7b914098
JS		 2461 /*
2462 * MSR_EBC_FREQUENCY_ID
2463 * Conservative value valid for even the basic CPU models.
2464 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2465 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2466 * and 266MHz for model 3, or 4. Set Core Clock
2467 * Frequency to System Bus Frequency Ratio to 1 (bits
2468 * 31:24) even though these are only valid for CPU
2469 * models > 2, however guests may end up dividing or
2470 * multiplying by zero otherwise.
2471 */
2472 case MSR_EBC_FREQUENCY_ID:
609e36d3 2473 msr_info->data = 1 << 24;
7b914098 2474 break;
15c4a640 2475 case MSR_IA32_APICBASE:
609e36d3 2476 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2477 break;
0105d1a5 2478 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2479 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2480 break;
a3e06bbe 2481 case MSR_IA32_TSCDEADLINE:
609e36d3 2482 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2483 break;
ba904635 2484 case MSR_IA32_TSC_ADJUST:
609e36d3 2485 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2486 break;
15c4a640 2487 case MSR_IA32_MISC_ENABLE:
609e36d3 2488 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2489 break;
64d60670
PB		 2490 case MSR_IA32_SMBASE:
2491 if (!msr_info->host_initiated)
2492 return 1;
2493 msr_info->data = vcpu->arch.smbase;
15c4a640 2494 break;
847f0ad8
AG		 2495 case MSR_IA32_PERF_STATUS:
2496 /* TSC increment by tick */
609e36d3 2497 msr_info->data = 1000ULL;
847f0ad8 2498 /* CPU multiplier */
b0996ae4 2499 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2500 break;
15c4a640 2501 case MSR_EFER:
609e36d3 2502 msr_info->data = vcpu->arch.efer;
15c4a640 2503 break;
18068523 2504 case MSR_KVM_WALL_CLOCK:
11c6bffa 2505 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2506 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2507 break;
2508 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2509 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2510 msr_info->data = vcpu->arch.time;
18068523 2511 break;
344d9588 2512 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2513 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2514 break;
c9aaa895 2515 case MSR_KVM_STEAL_TIME:
609e36d3 2516 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2517 break;
1d92128f 2518 case MSR_KVM_PV_EOI_EN:
609e36d3 2519 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2520 break;
890ca9ae
HY		 2521 case MSR_IA32_P5_MC_ADDR:
2522 case MSR_IA32_P5_MC_TYPE:
2523 case MSR_IA32_MCG_CAP:
2524 case MSR_IA32_MCG_CTL:
2525 case MSR_IA32_MCG_STATUS:
81760dcc 2526 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2527 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2528 case MSR_K7_CLK_CTL:
2529 /*
2530 * Provide expected ramp-up count for K7. All other
2531 * are set to zero, indicating minimum divisors for
2532 * every field.
2533 *
2534 * This prevents guest kernels on AMD host with CPU
2535 * type 6, model 8 and higher from exploding due to
2536 * the rdmsr failing.
2537 */
609e36d3 2538 msr_info->data = 0x20000000;
84e0cefa 2539 break;
55cd8e5a 2540 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2541 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2542 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2543 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2544 return kvm_hv_get_msr_common(vcpu,
2545 msr_info->index, &msr_info->data);
55cd8e5a 2546 break;
91c9c3ed 2547 case MSR_IA32_BBL_CR_CTL3:
2548 /* This legacy MSR exists but isn't fully documented in current
2549 * silicon. It is however accessed by winxp in very narrow
2550 * scenarios where it sets bit #19, itself documented as
2551 * a "reserved" bit. Best effort attempt to source coherent
2552 * read data here should the balance of the register be
2553 * interpreted by the guest:
2554 *
2555 * L2 cache control register 3: 64GB range, 256KB size,
2556 * enabled, latency 0x1, configured
2557 */
609e36d3 2558 msr_info->data = 0xbe702111;
91c9c3ed 2559 break;
2b036c6b 2560 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2561 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2562 return 1;
609e36d3 2563 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2564 break;
2565 case MSR_AMD64_OSVW_STATUS:
d6321d49 2566 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2567 return 1;
609e36d3 2568 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2569 break;
db2336a8
KH		 2570 case MSR_PLATFORM_INFO:
2571 msr_info->data = vcpu->arch.msr_platform_info;
2572 break;
2573 case MSR_MISC_FEATURES_ENABLES:
2574 msr_info->data = vcpu->arch.msr_misc_features_enables;
2575 break;
15c4a640 2576 default:
c6702c9d 2577 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2578 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2579 if (!ignore_msrs) {
ae0f5499
BD		 2580 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2581 msr_info->index);
ed85c068
AP		 2582 return 1;
2583 } else {
609e36d3
PB		 2584 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2585 msr_info->data = 0;
ed85c068
AP		 2586 }
2587 break;
15c4a640 2588 }
15c4a640
CO		 2589 return 0;
2590}
2591EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2592
313a3dc7
CO		 2593/*
2594 * Read or write a bunch of msrs. All parameters are kernel addresses.
2595 *
2596 * @return number of msrs set successfully.
2597 */
2598static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2599 struct kvm_msr_entry *entries,
2600 int (*do_msr)(struct kvm_vcpu *vcpu,
2601 unsigned index, u64 *data))
2602{
f656ce01 2603 int i, idx;
313a3dc7 2604
f656ce01 2605 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2606 for (i = 0; i < msrs->nmsrs; ++i)
2607 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2608 break;
f656ce01 2609 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2610
313a3dc7
CO		 2611 return i;
2612}
2613
2614/*
2615 * Read or write a bunch of msrs. Parameters are user addresses.
2616 *
2617 * @return number of msrs set successfully.
2618 */
2619static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2620 int (*do_msr)(struct kvm_vcpu *vcpu,
2621 unsigned index, u64 *data),
2622 int writeback)
2623{
2624 struct kvm_msrs msrs;
2625 struct kvm_msr_entry *entries;
2626 int r, n;
2627 unsigned size;
2628
2629 r = -EFAULT;
2630 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2631 goto out;
2632
2633 r = -E2BIG;
2634 if (msrs.nmsrs >= MAX_IO_MSRS)
2635 goto out;
2636
313a3dc7 2637 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2638 entries = memdup_user(user_msrs->entries, size);
2639 if (IS_ERR(entries)) {
2640 r = PTR_ERR(entries);
313a3dc7 2641 goto out;
ff5c2c03 2642 }
313a3dc7
CO		 2643
2644 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2645 if (r < 0)
2646 goto out_free;
2647
2648 r = -EFAULT;
2649 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2650 goto out_free;
2651
2652 r = n;
2653
2654out_free:
7a73c028 2655 kfree(entries);
313a3dc7
CO		 2656out:
2657 return r;
2658}
2659
784aa3d7 2660int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2661{
2662 int r;
2663
2664 switch (ext) {
2665 case KVM_CAP_IRQCHIP:
2666 case KVM_CAP_HLT:
2667 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2668 case KVM_CAP_SET_TSS_ADDR:
07716717 2669 case KVM_CAP_EXT_CPUID:
9c15bb1d 2670 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2671 case KVM_CAP_CLOCKSOURCE:
7837699f 2672 case KVM_CAP_PIT:
a28e4f5a 2673 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2674 case KVM_CAP_MP_STATE:
ed848624 2675 case KVM_CAP_SYNC_MMU:
a355c85c 2676 case KVM_CAP_USER_NMI:
52d939a0 2677 case KVM_CAP_REINJECT_CONTROL:
4925663a 2678 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2679 case KVM_CAP_IOEVENTFD:
f848a5a8 2680 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2681 case KVM_CAP_PIT2:
e9f42757 2682 case KVM_CAP_PIT_STATE2:
b927a3ce 2683 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2684 case KVM_CAP_XEN_HVM:
3cfc3092 2685 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2686 case KVM_CAP_HYPERV:
10388a07 2687 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2688 case KVM_CAP_HYPERV_SPIN:
5c919412 2689 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2690 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2691 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2692 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2693 case KVM_CAP_DEBUGREGS:
d2be1651 2694 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2695 case KVM_CAP_XSAVE:
344d9588 2696 case KVM_CAP_ASYNC_PF:
92a1f12d 2697 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2698 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2699 case KVM_CAP_READONLY_MEM:
5f66b620 2700 case KVM_CAP_HYPERV_TIME:
100943c5 2701 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2702 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2703 case KVM_CAP_ENABLE_CAP_VM:
2704 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2705 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2706 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2707 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2708 r = 1;
2709 break;
e3fd9a93
PB		 2710 case KVM_CAP_ADJUST_CLOCK:
2711 r = KVM_CLOCK_TSC_STABLE;
2712 break;
668fffa3
MT		 2713 case KVM_CAP_X86_GUEST_MWAIT:
2714 r = kvm_mwait_in_guest();
2715 break;
6d396b55
PB		 2716 case KVM_CAP_X86_SMM:
2717 /* SMBASE is usually relocated above 1M on modern chipsets,
2718 * and SMM handlers might indeed rely on 4G segment limits,
2719 * so do not report SMM to be available if real mode is
2720 * emulated via vm86 mode. Still, do not go to great lengths
2721 * to avoid userspace's usage of the feature, because it is a
2722 * fringe case that is not enabled except via specific settings
2723 * of the module parameters.
2724 */
2725 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2726 break;
774ead3a
AK		 2727 case KVM_CAP_VAPIC:
2728 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2729 break;
f725230a 2730 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2731 r = KVM_SOFT_MAX_VCPUS;
2732 break;
2733 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2734 r = KVM_MAX_VCPUS;
2735 break;
a988b910 2736 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2737 r = KVM_USER_MEM_SLOTS;
a988b910 2738 break;
a68a6a72
MT		 2739 case KVM_CAP_PV_MMU: /* obsolete */
2740 r = 0;
2f333bcb 2741 break;
890ca9ae
HY		 2742 case KVM_CAP_MCE:
2743 r = KVM_MAX_MCE_BANKS;
2744 break;
2d5b5a66 2745 case KVM_CAP_XCRS:
d366bf7e 2746 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2747 break;
92a1f12d
JR		 2748 case KVM_CAP_TSC_CONTROL:
2749 r = kvm_has_tsc_control;
2750 break;
37131313
RK		 2751 case KVM_CAP_X2APIC_API:
2752 r = KVM_X2APIC_API_VALID_FLAGS;
2753 break;
018d00d2
ZX		 2754 default:
2755 r = 0;
2756 break;
2757 }
2758 return r;
2759
2760}
2761
043405e1
CO		 2762long kvm_arch_dev_ioctl(struct file *filp,
2763 unsigned int ioctl, unsigned long arg)
2764{
2765 void __user *argp = (void __user *)arg;
2766 long r;
2767
2768 switch (ioctl) {
2769 case KVM_GET_MSR_INDEX_LIST: {
2770 struct kvm_msr_list __user *user_msr_list = argp;
2771 struct kvm_msr_list msr_list;
2772 unsigned n;
2773
2774 r = -EFAULT;
2775 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2776 goto out;
2777 n = msr_list.nmsrs;
62ef68bb 2778 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2779 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2780 goto out;
2781 r = -E2BIG;
e125e7b6 2782 if (n < msr_list.nmsrs)
043405e1
CO		 2783 goto out;
2784 r = -EFAULT;
2785 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2786 num_msrs_to_save * sizeof(u32)))
2787 goto out;
e125e7b6 2788 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2789 &emulated_msrs,
62ef68bb 2790 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2791 goto out;
2792 r = 0;
2793 break;
2794 }
9c15bb1d
BP		 2795 case KVM_GET_SUPPORTED_CPUID:
2796 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2797 struct kvm_cpuid2 __user *cpuid_arg = argp;
2798 struct kvm_cpuid2 cpuid;
2799
2800 r = -EFAULT;
2801 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2802 goto out;
9c15bb1d
BP		 2803
2804 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2805 ioctl);
674eea0f
AK		 2806 if (r)
2807 goto out;
2808
2809 r = -EFAULT;
2810 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2811 goto out;
2812 r = 0;
2813 break;
2814 }
890ca9ae 2815 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2816 r = -EFAULT;
c45dcc71
AR		 2817 if (copy_to_user(argp, &kvm_mce_cap_supported,
2818 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2819 goto out;
2820 r = 0;
2821 break;
2822 }
043405e1
CO		 2823 default:
2824 r = -EINVAL;
2825 }
2826out:
2827 return r;
2828}
2829
f5f48ee1
SY		 2830static void wbinvd_ipi(void *garbage)
2831{
2832 wbinvd();
2833}
2834
2835static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2836{
e0f0bbc5 2837 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2838}
2839
313a3dc7
CO		 2840void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2841{
f5f48ee1
SY		 2842 /* Address WBINVD may be executed by guest */
2843 if (need_emulate_wbinvd(vcpu)) {
2844 if (kvm_x86_ops->has_wbinvd_exit())
2845 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2846 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2847 smp_call_function_single(vcpu->cpu,
2848 wbinvd_ipi, NULL, 1);
2849 }
2850
313a3dc7 2851 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2852
0dd6a6ed
ZA		 2853 /* Apply any externally detected TSC adjustments (due to suspend) */
2854 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2855 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2856 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2857 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2858 }
8f6055cb 2859
48434c20 2860 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2861 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2862 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2863 if (tsc_delta < 0)
2864 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2865
c285545f 2866 if (check_tsc_unstable()) {
07c1419a 2867 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2868 vcpu->arch.last_guest_tsc);
a545ab6a 2869 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2870 vcpu->arch.tsc_catchup = 1;
c285545f 2871 }
a749e247
PB		 2872
2873 if (kvm_lapic_hv_timer_in_use(vcpu))
2874 kvm_lapic_restart_hv_timer(vcpu);
2875
d98d07ca
MT		 2876 /*
2877 * On a host with synchronized TSC, there is no need to update
2878 * kvmclock on vcpu->cpu migration
2879 */
2880 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2881 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2882 if (vcpu->cpu != cpu)
1bd2009e 2883 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2884 vcpu->cpu = cpu;
6b7d7e76 2885 }
c9aaa895 2886
c9aaa895 2887 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2888}
2889
0b9f6c46
PX		 2890static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2891{
2892 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2893 return;
2894
2895 vcpu->arch.st.steal.preempted = 1;
2896
4e335d9e 2897 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2898 &vcpu->arch.st.steal.preempted,
2899 offsetof(struct kvm_steal_time, preempted),
2900 sizeof(vcpu->arch.st.steal.preempted));
2901}
2902
313a3dc7
CO		 2903void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2904{
cc0d907c 2905 int idx;
de63ad4c
LM		 2906
2907 if (vcpu->preempted)
2908 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2909
931f261b
AA		 2910 /*
2911 * Disable page faults because we're in atomic context here.
2912 * kvm_write_guest_offset_cached() would call might_fault()
2913 * that relies on pagefault_disable() to tell if there's a
2914 * bug. NOTE: the write to guest memory may not go through if
2915 * during postcopy live migration or if there's heavy guest
2916 * paging.
2917 */
2918 pagefault_disable();
cc0d907c
AA		 2919 /*
2920 * kvm_memslots() will be called by
2921 * kvm_write_guest_offset_cached() so take the srcu lock.
2922 */
2923 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2924 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2925 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2926 pagefault_enable();
02daab21 2927 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2928 kvm_put_guest_fpu(vcpu);
4ea1636b 2929 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2930}
2931
313a3dc7
CO		 2932static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2933 struct kvm_lapic_state *s)
2934{
76dfafd5 2935 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2936 kvm_x86_ops->sync_pir_to_irr(vcpu);
2937
a92e2543 2938 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2939}
2940
2941static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2942 struct kvm_lapic_state *s)
2943{
a92e2543
RK		 2944 int r;
2945
2946 r = kvm_apic_set_state(vcpu, s);
2947 if (r)
2948 return r;
cb142eb7 2949 update_cr8_intercept(vcpu);
313a3dc7
CO		 2950
2951 return 0;
2952}
2953
127a457a
MG		 2954static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2955{
2956 return (!lapic_in_kernel(vcpu) ||
2957 kvm_apic_accept_pic_intr(vcpu));
2958}
2959
782d422b
MG		 2960/*
2961 * if userspace requested an interrupt window, check that the
2962 * interrupt window is open.
2963 *
2964 * No need to exit to userspace if we already have an interrupt queued.
2965 */
2966static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2967{
2968 return kvm_arch_interrupt_allowed(vcpu) &&
2969 !kvm_cpu_has_interrupt(vcpu) &&
2970 !kvm_event_needs_reinjection(vcpu) &&
2971 kvm_cpu_accept_dm_intr(vcpu);
2972}
2973
f77bc6a4
ZX		 2974static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2975 struct kvm_interrupt *irq)
2976{
02cdb50f 2977 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2978 return -EINVAL;
1c1a9ce9
SR		 2979
2980 if (!irqchip_in_kernel(vcpu->kvm)) {
2981 kvm_queue_interrupt(vcpu, irq->irq, false);
2982 kvm_make_request(KVM_REQ_EVENT, vcpu);
2983 return 0;
2984 }
2985
2986 /*
2987 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2988 * fail for in-kernel 8259.
2989 */
2990 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2991 return -ENXIO;
f77bc6a4 2992
1c1a9ce9
SR		 2993 if (vcpu->arch.pending_external_vector != -1)
2994 return -EEXIST;
f77bc6a4 2995
1c1a9ce9 2996 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2997 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2998 return 0;
2999}
3000
c4abb7c9
JK		 3001static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3002{
c4abb7c9 3003 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3004
3005 return 0;
3006}
3007
f077825a
PB		 3008static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3009{
64d60670
PB		 3010 kvm_make_request(KVM_REQ_SMI, vcpu);
3011
f077825a
PB		 3012 return 0;
3013}
3014
b209749f
AK		 3015static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3016 struct kvm_tpr_access_ctl *tac)
3017{
3018 if (tac->flags)
3019 return -EINVAL;
3020 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3021 return 0;
3022}
3023
890ca9ae
HY		 3024static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3025 u64 mcg_cap)
3026{
3027 int r;
3028 unsigned bank_num = mcg_cap & 0xff, bank;
3029
3030 r = -EINVAL;
a9e38c3e 3031 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3032 goto out;
c45dcc71 3033 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3034 goto out;
3035 r = 0;
3036 vcpu->arch.mcg_cap = mcg_cap;
3037 /* Init IA32_MCG_CTL to all 1s */
3038 if (mcg_cap & MCG_CTL_P)
3039 vcpu->arch.mcg_ctl = ~(u64)0;
3040 /* Init IA32_MCi_CTL to all 1s */
3041 for (bank = 0; bank < bank_num; bank++)
3042 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3043
3044 if (kvm_x86_ops->setup_mce)
3045 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3046out:
3047 return r;
3048}
3049
3050static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3051 struct kvm_x86_mce *mce)
3052{
3053 u64 mcg_cap = vcpu->arch.mcg_cap;
3054 unsigned bank_num = mcg_cap & 0xff;
3055 u64 *banks = vcpu->arch.mce_banks;
3056
3057 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3058 return -EINVAL;
3059 /*
3060 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3061 * reporting is disabled
3062 */
3063 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3064 vcpu->arch.mcg_ctl != ~(u64)0)
3065 return 0;
3066 banks += 4 * mce->bank;
3067 /*
3068 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3069 * reporting is disabled for the bank
3070 */
3071 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3072 return 0;
3073 if (mce->status & MCI_STATUS_UC) {
3074 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3075 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3076 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3077 return 0;
3078 }
3079 if (banks[1] & MCI_STATUS_VAL)
3080 mce->status |= MCI_STATUS_OVER;
3081 banks[2] = mce->addr;
3082 banks[3] = mce->misc;
3083 vcpu->arch.mcg_status = mce->mcg_status;
3084 banks[1] = mce->status;
3085 kvm_queue_exception(vcpu, MC_VECTOR);
3086 } else if (!(banks[1] & MCI_STATUS_VAL)
3087 || !(banks[1] & MCI_STATUS_UC)) {
3088 if (banks[1] & MCI_STATUS_VAL)
3089 mce->status |= MCI_STATUS_OVER;
3090 banks[2] = mce->addr;
3091 banks[3] = mce->misc;
3092 banks[1] = mce->status;
3093 } else
3094 banks[1] |= MCI_STATUS_OVER;
3095 return 0;
3096}
3097
3cfc3092
JK		 3098static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3099 struct kvm_vcpu_events *events)
3100{
7460fb4a 3101 process_nmi(vcpu);
664f8e26
WL		 3102 /*
3103 * FIXME: pass injected and pending separately. This is only
3104 * needed for nested virtualization, whose state cannot be
3105 * migrated yet. For now we can combine them.
3106 */
03b82a30 3107 events->exception.injected =
664f8e26
WL		 3108 (vcpu->arch.exception.pending ||
3109 vcpu->arch.exception.injected) &&
03b82a30 3110 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3111 events->exception.nr = vcpu->arch.exception.nr;
3112 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3113 events->exception.pad = 0;
3cfc3092
JK		 3114 events->exception.error_code = vcpu->arch.exception.error_code;
3115
03b82a30
JK		 3116 events->interrupt.injected =
3117 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3118 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3119 events->interrupt.soft = 0;
37ccdcbe 3120 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3121
3122 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3123 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3124 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3125 events->nmi.pad = 0;
3cfc3092 3126
66450a21 3127 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3128
f077825a
PB		 3129 events->smi.smm = is_smm(vcpu);
3130 events->smi.pending = vcpu->arch.smi_pending;
3131 events->smi.smm_inside_nmi =
3132 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3133 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3134
dab4b911 3135 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3136 | KVM_VCPUEVENT_VALID_SHADOW
3137 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3138 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3139}
3140
6ef4e07e
XG		 3141static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3142
3cfc3092
JK		 3143static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3144 struct kvm_vcpu_events *events)
3145{
dab4b911 3146 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3147 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3148 | KVM_VCPUEVENT_VALID_SHADOW
3149 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3150 return -EINVAL;
3151
78e546c8 3152 if (events->exception.injected &&
28d06353
JM		 3153 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3154 is_guest_mode(vcpu)))
78e546c8
PB		 3155 return -EINVAL;
3156
28bf2888
DH		 3157 /* INITs are latched while in SMM */
3158 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3159 (events->smi.smm || events->smi.pending) &&
3160 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3161 return -EINVAL;
3162
7460fb4a 3163 process_nmi(vcpu);
664f8e26 3164 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3165 vcpu->arch.exception.pending = events->exception.injected;
3166 vcpu->arch.exception.nr = events->exception.nr;
3167 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3168 vcpu->arch.exception.error_code = events->exception.error_code;
3169
3170 vcpu->arch.interrupt.pending = events->interrupt.injected;
3171 vcpu->arch.interrupt.nr = events->interrupt.nr;
3172 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3173 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3174 kvm_x86_ops->set_interrupt_shadow(vcpu,
3175 events->interrupt.shadow);
3cfc3092
JK		 3176
3177 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3178 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3179 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3180 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3181
66450a21 3182 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3183 lapic_in_kernel(vcpu))
66450a21 3184 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3185
f077825a 3186 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3187 u32 hflags = vcpu->arch.hflags;
f077825a 3188 if (events->smi.smm)
6ef4e07e 3189 hflags |= HF_SMM_MASK;
f077825a 3190 else
6ef4e07e
XG		 3191 hflags &= ~HF_SMM_MASK;
3192 kvm_set_hflags(vcpu, hflags);
3193
f077825a 3194 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3195
3196 if (events->smi.smm) {
3197 if (events->smi.smm_inside_nmi)
3198 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3199 else
f4ef1910
WL		 3200 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3201 if (lapic_in_kernel(vcpu)) {
3202 if (events->smi.latched_init)
3203 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3204 else
3205 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3206 }
f077825a
PB		 3207 }
3208 }
3209
3842d135
AK		 3210 kvm_make_request(KVM_REQ_EVENT, vcpu);
3211
3cfc3092
JK		 3212 return 0;
3213}
3214
a1efbe77
JK		 3215static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3216 struct kvm_debugregs *dbgregs)
3217{
73aaf249
JK		 3218 unsigned long val;
3219
a1efbe77 3220 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3221 kvm_get_dr(vcpu, 6, &val);
73aaf249 3222 dbgregs->dr6 = val;
a1efbe77
JK		 3223 dbgregs->dr7 = vcpu->arch.dr7;
3224 dbgregs->flags = 0;
97e69aa6 3225 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3226}
3227
3228static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3229 struct kvm_debugregs *dbgregs)
3230{
3231 if (dbgregs->flags)
3232 return -EINVAL;
3233
d14bdb55
PB		 3234 if (dbgregs->dr6 & ~0xffffffffull)
3235 return -EINVAL;
3236 if (dbgregs->dr7 & ~0xffffffffull)
3237 return -EINVAL;
3238
a1efbe77 3239 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3240 kvm_update_dr0123(vcpu);
a1efbe77 3241 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3242 kvm_update_dr6(vcpu);
a1efbe77 3243 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3244 kvm_update_dr7(vcpu);
a1efbe77 3245
a1efbe77
JK		 3246 return 0;
3247}
3248
df1daba7
PB		 3249#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3250
3251static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3252{
c47ada30 3253 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3254 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3255 u64 valid;
3256
3257 /*
3258 * Copy legacy XSAVE area, to avoid complications with CPUID
3259 * leaves 0 and 1 in the loop below.
3260 */
3261 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3262
3263 /* Set XSTATE_BV */
00c87e9a 3264 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3265 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3266
3267 /*
3268 * Copy each region from the possibly compacted offset to the
3269 * non-compacted offset.
3270 */
d91cab78 3271 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3272 while (valid) {
3273 u64 feature = valid & -valid;
3274 int index = fls64(feature) - 1;
3275 void *src = get_xsave_addr(xsave, feature);
3276
3277 if (src) {
3278 u32 size, offset, ecx, edx;
3279 cpuid_count(XSTATE_CPUID, index,
3280 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3281 if (feature == XFEATURE_MASK_PKRU)
3282 memcpy(dest + offset, &vcpu->arch.pkru,
3283 sizeof(vcpu->arch.pkru));
3284 else
3285 memcpy(dest + offset, src, size);
3286
df1daba7
PB		 3287 }
3288
3289 valid -= feature;
3290 }
3291}
3292
3293static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3294{
c47ada30 3295 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3296 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3297 u64 valid;
3298
3299 /*
3300 * Copy legacy XSAVE area, to avoid complications with CPUID
3301 * leaves 0 and 1 in the loop below.
3302 */
3303 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3304
3305 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3306 xsave->header.xfeatures = xstate_bv;
782511b0 3307 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3308 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3309
3310 /*
3311 * Copy each region from the non-compacted offset to the
3312 * possibly compacted offset.
3313 */
d91cab78 3314 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3315 while (valid) {
3316 u64 feature = valid & -valid;
3317 int index = fls64(feature) - 1;
3318 void *dest = get_xsave_addr(xsave, feature);
3319
3320 if (dest) {
3321 u32 size, offset, ecx, edx;
3322 cpuid_count(XSTATE_CPUID, index,
3323 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3324 if (feature == XFEATURE_MASK_PKRU)
3325 memcpy(&vcpu->arch.pkru, src + offset,
3326 sizeof(vcpu->arch.pkru));
3327 else
3328 memcpy(dest, src + offset, size);
ee4100da 3329 }
df1daba7
PB		 3330
3331 valid -= feature;
3332 }
3333}
3334
2d5b5a66
SY		 3335static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3336 struct kvm_xsave *guest_xsave)
3337{
d366bf7e 3338 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3339 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3340 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3341 } else {
2d5b5a66 3342 memcpy(guest_xsave->region,
7366ed77 3343 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3344 sizeof(struct fxregs_state));
2d5b5a66 3345 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3346 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3347 }
3348}
3349
a575813b
WL		 3350#define XSAVE_MXCSR_OFFSET 24
3351
2d5b5a66
SY		 3352static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3353 struct kvm_xsave *guest_xsave)
3354{
3355 u64 xstate_bv =
3356 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3357 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3358
d366bf7e 3359 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3360 /*
3361 * Here we allow setting states that are not present in
3362 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3363 * with old userspace.
3364 */
a575813b
WL		 3365 if (xstate_bv & ~kvm_supported_xcr0() ||
3366 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3367 return -EINVAL;
df1daba7 3368 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3369 } else {
a575813b
WL		 3370 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3371 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3372 return -EINVAL;
7366ed77 3373 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3374 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3375 }
3376 return 0;
3377}
3378
3379static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3380 struct kvm_xcrs *guest_xcrs)
3381{
d366bf7e 3382 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3383 guest_xcrs->nr_xcrs = 0;
3384 return;
3385 }
3386
3387 guest_xcrs->nr_xcrs = 1;
3388 guest_xcrs->flags = 0;
3389 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3390 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3391}
3392
3393static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3394 struct kvm_xcrs *guest_xcrs)
3395{
3396 int i, r = 0;
3397
d366bf7e 3398 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3399 return -EINVAL;
3400
3401 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3402 return -EINVAL;
3403
3404 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3405 /* Only support XCR0 currently */
c67a04cb 3406 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3407 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3408 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3409 break;
3410 }
3411 if (r)
3412 r = -EINVAL;
3413 return r;
3414}
3415
1c0b28c2
EM		 3416/*
3417 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3418 * stopped by the hypervisor. This function will be called from the host only.
3419 * EINVAL is returned when the host attempts to set the flag for a guest that
3420 * does not support pv clocks.
3421 */
3422static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3423{
0b79459b 3424 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3425 return -EINVAL;
51d59c6b 3426 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3427 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3428 return 0;
3429}
3430
5c919412
AS		 3431static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3432 struct kvm_enable_cap *cap)
3433{
3434 if (cap->flags)
3435 return -EINVAL;
3436
3437 switch (cap->cap) {
efc479e6
RK		 3438 case KVM_CAP_HYPERV_SYNIC2:
3439 if (cap->args[0])
3440 return -EINVAL;
5c919412 3441 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3442 if (!irqchip_in_kernel(vcpu->kvm))
3443 return -EINVAL;
efc479e6
RK		 3444 return kvm_hv_activate_synic(vcpu, cap->cap ==
3445 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3446 default:
3447 return -EINVAL;
3448 }
3449}
3450
313a3dc7
CO		 3451long kvm_arch_vcpu_ioctl(struct file *filp,
3452 unsigned int ioctl, unsigned long arg)
3453{
3454 struct kvm_vcpu *vcpu = filp->private_data;
3455 void __user *argp = (void __user *)arg;
3456 int r;
d1ac91d8
AK		 3457 union {
3458 struct kvm_lapic_state *lapic;
3459 struct kvm_xsave *xsave;
3460 struct kvm_xcrs *xcrs;
3461 void *buffer;
3462 } u;
3463
3464 u.buffer = NULL;
313a3dc7
CO		 3465 switch (ioctl) {
3466 case KVM_GET_LAPIC: {
2204ae3c 3467 r = -EINVAL;
bce87cce 3468 if (!lapic_in_kernel(vcpu))
2204ae3c 3469 goto out;
d1ac91d8 3470 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3471
b772ff36 3472 r = -ENOMEM;
d1ac91d8 3473 if (!u.lapic)
b772ff36 3474 goto out;
d1ac91d8 3475 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3476 if (r)
3477 goto out;
3478 r = -EFAULT;
d1ac91d8 3479 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3480 goto out;
3481 r = 0;
3482 break;
3483 }
3484 case KVM_SET_LAPIC: {
2204ae3c 3485 r = -EINVAL;
bce87cce 3486 if (!lapic_in_kernel(vcpu))
2204ae3c 3487 goto out;
ff5c2c03 3488 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3489 if (IS_ERR(u.lapic))
3490 return PTR_ERR(u.lapic);
ff5c2c03 3491
d1ac91d8 3492 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3493 break;
3494 }
f77bc6a4
ZX		 3495 case KVM_INTERRUPT: {
3496 struct kvm_interrupt irq;
3497
3498 r = -EFAULT;
3499 if (copy_from_user(&irq, argp, sizeof irq))
3500 goto out;
3501 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3502 break;
3503 }
c4abb7c9
JK		 3504 case KVM_NMI: {
3505 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3506 break;
3507 }
f077825a
PB		 3508 case KVM_SMI: {
3509 r = kvm_vcpu_ioctl_smi(vcpu);
3510 break;
3511 }
313a3dc7
CO		 3512 case KVM_SET_CPUID: {
3513 struct kvm_cpuid __user *cpuid_arg = argp;
3514 struct kvm_cpuid cpuid;
3515
3516 r = -EFAULT;
3517 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3518 goto out;
3519 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3520 break;
3521 }
07716717
DK		 3522 case KVM_SET_CPUID2: {
3523 struct kvm_cpuid2 __user *cpuid_arg = argp;
3524 struct kvm_cpuid2 cpuid;
3525
3526 r = -EFAULT;
3527 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3528 goto out;
3529 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3530 cpuid_arg->entries);
07716717
DK		 3531 break;
3532 }
3533 case KVM_GET_CPUID2: {
3534 struct kvm_cpuid2 __user *cpuid_arg = argp;
3535 struct kvm_cpuid2 cpuid;
3536
3537 r = -EFAULT;
3538 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3539 goto out;
3540 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3541 cpuid_arg->entries);
07716717
DK		 3542 if (r)
3543 goto out;
3544 r = -EFAULT;
3545 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3546 goto out;
3547 r = 0;
3548 break;
3549 }
313a3dc7 3550 case KVM_GET_MSRS:
609e36d3 3551 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3552 break;
3553 case KVM_SET_MSRS:
3554 r = msr_io(vcpu, argp, do_set_msr, 0);
3555 break;
b209749f
AK		 3556 case KVM_TPR_ACCESS_REPORTING: {
3557 struct kvm_tpr_access_ctl tac;
3558
3559 r = -EFAULT;
3560 if (copy_from_user(&tac, argp, sizeof tac))
3561 goto out;
3562 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3563 if (r)
3564 goto out;
3565 r = -EFAULT;
3566 if (copy_to_user(argp, &tac, sizeof tac))
3567 goto out;
3568 r = 0;
3569 break;
3570 };
b93463aa
AK		 3571 case KVM_SET_VAPIC_ADDR: {
3572 struct kvm_vapic_addr va;
7301d6ab 3573 int idx;
b93463aa
AK		 3574
3575 r = -EINVAL;
35754c98 3576 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3577 goto out;
3578 r = -EFAULT;
3579 if (copy_from_user(&va, argp, sizeof va))
3580 goto out;
7301d6ab 3581 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3582 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3583 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3584 break;
3585 }
890ca9ae
HY		 3586 case KVM_X86_SETUP_MCE: {
3587 u64 mcg_cap;
3588
3589 r = -EFAULT;
3590 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3591 goto out;
3592 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3593 break;
3594 }
3595 case KVM_X86_SET_MCE: {
3596 struct kvm_x86_mce mce;
3597
3598 r = -EFAULT;
3599 if (copy_from_user(&mce, argp, sizeof mce))
3600 goto out;
3601 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3602 break;
3603 }
3cfc3092
JK		 3604 case KVM_GET_VCPU_EVENTS: {
3605 struct kvm_vcpu_events events;
3606
3607 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3608
3609 r = -EFAULT;
3610 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3611 break;
3612 r = 0;
3613 break;
3614 }
3615 case KVM_SET_VCPU_EVENTS: {
3616 struct kvm_vcpu_events events;
3617
3618 r = -EFAULT;
3619 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3620 break;
3621
3622 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3623 break;
3624 }
a1efbe77
JK		 3625 case KVM_GET_DEBUGREGS: {
3626 struct kvm_debugregs dbgregs;
3627
3628 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3629
3630 r = -EFAULT;
3631 if (copy_to_user(argp, &dbgregs,
3632 sizeof(struct kvm_debugregs)))
3633 break;
3634 r = 0;
3635 break;
3636 }
3637 case KVM_SET_DEBUGREGS: {
3638 struct kvm_debugregs dbgregs;
3639
3640 r = -EFAULT;
3641 if (copy_from_user(&dbgregs, argp,
3642 sizeof(struct kvm_debugregs)))
3643 break;
3644
3645 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3646 break;
3647 }
2d5b5a66 3648 case KVM_GET_XSAVE: {
d1ac91d8 3649 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3650 r = -ENOMEM;
d1ac91d8 3651 if (!u.xsave)
2d5b5a66
SY		 3652 break;
3653
d1ac91d8 3654 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3655
3656 r = -EFAULT;
d1ac91d8 3657 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3658 break;
3659 r = 0;
3660 break;
3661 }
3662 case KVM_SET_XSAVE: {
ff5c2c03 3663 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3664 if (IS_ERR(u.xsave))
3665 return PTR_ERR(u.xsave);
2d5b5a66 3666
d1ac91d8 3667 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3668 break;
3669 }
3670 case KVM_GET_XCRS: {
d1ac91d8 3671 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3672 r = -ENOMEM;
d1ac91d8 3673 if (!u.xcrs)
2d5b5a66
SY		 3674 break;
3675
d1ac91d8 3676 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3677
3678 r = -EFAULT;
d1ac91d8 3679 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3680 sizeof(struct kvm_xcrs)))
3681 break;
3682 r = 0;
3683 break;
3684 }
3685 case KVM_SET_XCRS: {
ff5c2c03 3686 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3687 if (IS_ERR(u.xcrs))
3688 return PTR_ERR(u.xcrs);
2d5b5a66 3689
d1ac91d8 3690 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3691 break;
3692 }
92a1f12d
JR		 3693 case KVM_SET_TSC_KHZ: {
3694 u32 user_tsc_khz;
3695
3696 r = -EINVAL;
92a1f12d
JR		 3697 user_tsc_khz = (u32)arg;
3698
3699 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3700 goto out;
3701
cc578287
ZA		 3702 if (user_tsc_khz == 0)
3703 user_tsc_khz = tsc_khz;
3704
381d585c
HZ		 3705 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3706 r = 0;
92a1f12d 3707
92a1f12d
JR		 3708 goto out;
3709 }
3710 case KVM_GET_TSC_KHZ: {
cc578287 3711 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3712 goto out;
3713 }
1c0b28c2
EM		 3714 case KVM_KVMCLOCK_CTRL: {
3715 r = kvm_set_guest_paused(vcpu);
3716 goto out;
3717 }
5c919412
AS		 3718 case KVM_ENABLE_CAP: {
3719 struct kvm_enable_cap cap;
3720
3721 r = -EFAULT;
3722 if (copy_from_user(&cap, argp, sizeof(cap)))
3723 goto out;
3724 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3725 break;
3726 }
313a3dc7
CO		 3727 default:
3728 r = -EINVAL;
3729 }
3730out:
d1ac91d8 3731 kfree(u.buffer);
313a3dc7
CO		 3732 return r;
3733}
3734
5b1c1493
CO		 3735int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3736{
3737 return VM_FAULT_SIGBUS;
3738}
3739
1fe779f8
CO		 3740static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3741{
3742 int ret;
3743
3744 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3745 return -EINVAL;
1fe779f8
CO		 3746 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3747 return ret;
3748}
3749
b927a3ce
SY		 3750static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3751 u64 ident_addr)
3752{
3753 kvm->arch.ept_identity_map_addr = ident_addr;
3754 return 0;
3755}
3756
1fe779f8
CO		 3757static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3758 u32 kvm_nr_mmu_pages)
3759{
3760 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3761 return -EINVAL;
3762
79fac95e 3763 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3764
3765 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3766 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3767
79fac95e 3768 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3769 return 0;
3770}
3771
3772static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3773{
39de71ec 3774 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3775}
3776
1fe779f8
CO		 3777static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3778{
90bca052 3779 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3780 int r;
3781
3782 r = 0;
3783 switch (chip->chip_id) {
3784 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3785 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3786 sizeof(struct kvm_pic_state));
3787 break;
3788 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3789 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3790 sizeof(struct kvm_pic_state));
3791 break;
3792 case KVM_IRQCHIP_IOAPIC:
33392b49 3793 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3794 break;
3795 default:
3796 r = -EINVAL;
3797 break;
3798 }
3799 return r;
3800}
3801
3802static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3803{
90bca052 3804 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3805 int r;
3806
3807 r = 0;
3808 switch (chip->chip_id) {
3809 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3810 spin_lock(&pic->lock);
3811 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3812 sizeof(struct kvm_pic_state));
90bca052 3813 spin_unlock(&pic->lock);
1fe779f8
CO		 3814 break;
3815 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3816 spin_lock(&pic->lock);
3817 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3818 sizeof(struct kvm_pic_state));
90bca052 3819 spin_unlock(&pic->lock);
1fe779f8
CO		 3820 break;
3821 case KVM_IRQCHIP_IOAPIC:
33392b49 3822 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3823 break;
3824 default:
3825 r = -EINVAL;
3826 break;
3827 }
90bca052 3828 kvm_pic_update_irq(pic);
1fe779f8
CO		 3829 return r;
3830}
3831
e0f63cb9
SY		 3832static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3833{
34f3941c
RK		 3834 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3835
3836 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3837
3838 mutex_lock(&kps->lock);
3839 memcpy(ps, &kps->channels, sizeof(*ps));
3840 mutex_unlock(&kps->lock);
2da29bcc 3841 return 0;
e0f63cb9
SY		 3842}
3843
3844static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3845{
0185604c 3846 int i;
09edea72
RK		 3847 struct kvm_pit *pit = kvm->arch.vpit;
3848
3849 mutex_lock(&pit->pit_state.lock);
34f3941c 3850 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3851 for (i = 0; i < 3; i++)
09edea72
RK		 3852 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3853 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3854 return 0;
e9f42757
BK		 3855}
3856
3857static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3858{
e9f42757
BK		 3859 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3860 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3861 sizeof(ps->channels));
3862 ps->flags = kvm->arch.vpit->pit_state.flags;
3863 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3864 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3865 return 0;
e9f42757
BK		 3866}
3867
3868static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3869{
2da29bcc 3870 int start = 0;
0185604c 3871 int i;
e9f42757 3872 u32 prev_legacy, cur_legacy;
09edea72
RK		 3873 struct kvm_pit *pit = kvm->arch.vpit;
3874
3875 mutex_lock(&pit->pit_state.lock);
3876 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3877 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3878 if (!prev_legacy && cur_legacy)
3879 start = 1;
09edea72
RK		 3880 memcpy(&pit->pit_state.channels, &ps->channels,
3881 sizeof(pit->pit_state.channels));
3882 pit->pit_state.flags = ps->flags;
0185604c 3883 for (i = 0; i < 3; i++)
09edea72 3884 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3885 start && i == 0);
09edea72 3886 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3887 return 0;
e0f63cb9
SY		 3888}
3889
52d939a0
MT		 3890static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3891 struct kvm_reinject_control *control)
3892{
71474e2f
RK		 3893 struct kvm_pit *pit = kvm->arch.vpit;
3894
3895 if (!pit)
52d939a0 3896 return -ENXIO;
b39c90b6 3897
71474e2f
RK		 3898 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3899 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3900 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3901 */
3902 mutex_lock(&pit->pit_state.lock);
3903 kvm_pit_set_reinject(pit, control->pit_reinject);
3904 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3905
52d939a0
MT		 3906 return 0;
3907}
3908
95d4c16c 3909/**
60c34612
TY		 3910 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3911 * @kvm: kvm instance
3912 * @log: slot id and address to which we copy the log
95d4c16c 3913 *
e108ff2f
PB		 3914 * Steps 1-4 below provide general overview of dirty page logging. See
3915 * kvm_get_dirty_log_protect() function description for additional details.
3916 *
3917 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3918 * always flush the TLB (step 4) even if previous step failed and the dirty
3919 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3920 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3921 * writes will be marked dirty for next log read.
95d4c16c 3922 *
60c34612
TY		 3923 * 1. Take a snapshot of the bit and clear it if needed.
3924 * 2. Write protect the corresponding page.
e108ff2f
PB		 3925 * 3. Copy the snapshot to the userspace.
3926 * 4. Flush TLB's if needed.
5bb064dc 3927 */
60c34612 3928int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3929{
60c34612 3930 bool is_dirty = false;
e108ff2f 3931 int r;
5bb064dc 3932
79fac95e 3933 mutex_lock(&kvm->slots_lock);
5bb064dc 3934
88178fd4
KH		 3935 /*
3936 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3937 */
3938 if (kvm_x86_ops->flush_log_dirty)
3939 kvm_x86_ops->flush_log_dirty(kvm);
3940
e108ff2f 3941 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3942
3943 /*
3944 * All the TLBs can be flushed out of mmu lock, see the comments in
3945 * kvm_mmu_slot_remove_write_access().
3946 */
e108ff2f 3947 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3948 if (is_dirty)
3949 kvm_flush_remote_tlbs(kvm);
3950
79fac95e 3951 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3952 return r;
3953}
3954
aa2fbe6d
YZ		 3955int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3956 bool line_status)
23d43cf9
CD		 3957{
3958 if (!irqchip_in_kernel(kvm))
3959 return -ENXIO;
3960
3961 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3962 irq_event->irq, irq_event->level,
3963 line_status);
23d43cf9
CD		 3964 return 0;
3965}
3966
90de4a18
NA		 3967static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3968 struct kvm_enable_cap *cap)
3969{
3970 int r;
3971
3972 if (cap->flags)
3973 return -EINVAL;
3974
3975 switch (cap->cap) {
3976 case KVM_CAP_DISABLE_QUIRKS:
3977 kvm->arch.disabled_quirks = cap->args[0];
3978 r = 0;
3979 break;
49df6397
SR		 3980 case KVM_CAP_SPLIT_IRQCHIP: {
3981 mutex_lock(&kvm->lock);
b053b2ae
SR		 3982 r = -EINVAL;
3983 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3984 goto split_irqchip_unlock;
49df6397
SR		 3985 r = -EEXIST;
3986 if (irqchip_in_kernel(kvm))
3987 goto split_irqchip_unlock;
557abc40 3988 if (kvm->created_vcpus)
49df6397
SR		 3989 goto split_irqchip_unlock;
3990 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 3991 if (r)
49df6397
SR		 3992 goto split_irqchip_unlock;
3993 /* Pairs with irqchip_in_kernel. */
3994 smp_wmb();
49776faf 3995 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3996 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3997 r = 0;
3998split_irqchip_unlock:
3999 mutex_unlock(&kvm->lock);
4000 break;
4001 }
37131313
RK		 4002 case KVM_CAP_X2APIC_API:
4003 r = -EINVAL;
4004 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4005 break;
4006
4007 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4008 kvm->arch.x2apic_format = true;
c519265f
RK		 4009 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4010 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4011
4012 r = 0;
4013 break;
90de4a18
NA		 4014 default:
4015 r = -EINVAL;
4016 break;
4017 }
4018 return r;
4019}
4020
1fe779f8
CO		 4021long kvm_arch_vm_ioctl(struct file *filp,
4022 unsigned int ioctl, unsigned long arg)
4023{
4024 struct kvm *kvm = filp->private_data;
4025 void __user *argp = (void __user *)arg;
367e1319 4026 int r = -ENOTTY;
f0d66275
DH		 4027 /*
4028 * This union makes it completely explicit to gcc-3.x
4029 * that these two variables' stack usage should be
4030 * combined, not added together.
4031 */
4032 union {
4033 struct kvm_pit_state ps;
e9f42757 4034 struct kvm_pit_state2 ps2;
c5ff41ce 4035 struct kvm_pit_config pit_config;
f0d66275 4036 } u;
1fe779f8
CO		 4037
4038 switch (ioctl) {
4039 case KVM_SET_TSS_ADDR:
4040 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4041 break;
b927a3ce
SY		 4042 case KVM_SET_IDENTITY_MAP_ADDR: {
4043 u64 ident_addr;
4044
1af1ac91
DH		 4045 mutex_lock(&kvm->lock);
4046 r = -EINVAL;
4047 if (kvm->created_vcpus)
4048 goto set_identity_unlock;
b927a3ce
SY		 4049 r = -EFAULT;
4050 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4051 goto set_identity_unlock;
b927a3ce 4052 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4053set_identity_unlock:
4054 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4055 break;
4056 }
1fe779f8
CO		 4057 case KVM_SET_NR_MMU_PAGES:
4058 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4059 break;
4060 case KVM_GET_NR_MMU_PAGES:
4061 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4062 break;
3ddea128 4063 case KVM_CREATE_IRQCHIP: {
3ddea128 4064 mutex_lock(&kvm->lock);
09941366 4065
3ddea128 4066 r = -EEXIST;
35e6eaa3 4067 if (irqchip_in_kernel(kvm))
3ddea128 4068 goto create_irqchip_unlock;
09941366 4069
3e515705 4070 r = -EINVAL;
557abc40 4071 if (kvm->created_vcpus)
3e515705 4072 goto create_irqchip_unlock;
09941366
RK		 4073
4074 r = kvm_pic_init(kvm);
4075 if (r)
3ddea128 4076 goto create_irqchip_unlock;
09941366
RK		 4077
4078 r = kvm_ioapic_init(kvm);
4079 if (r) {
09941366 4080 kvm_pic_destroy(kvm);
3ddea128 4081 goto create_irqchip_unlock;
09941366
RK		 4082 }
4083
399ec807
AK		 4084 r = kvm_setup_default_irq_routing(kvm);
4085 if (r) {
72bb2fcd 4086 kvm_ioapic_destroy(kvm);
09941366 4087 kvm_pic_destroy(kvm);
71ba994c 4088 goto create_irqchip_unlock;
399ec807 4089 }
49776faf 4090 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4091 smp_wmb();
49776faf 4092 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4093 create_irqchip_unlock:
4094 mutex_unlock(&kvm->lock);
1fe779f8 4095 break;
3ddea128 4096 }
7837699f 4097 case KVM_CREATE_PIT:
c5ff41ce
JK		 4098 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4099 goto create_pit;
4100 case KVM_CREATE_PIT2:
4101 r = -EFAULT;
4102 if (copy_from_user(&u.pit_config, argp,
4103 sizeof(struct kvm_pit_config)))
4104 goto out;
4105 create_pit:
250715a6 4106 mutex_lock(&kvm->lock);
269e05e4
AK		 4107 r = -EEXIST;
4108 if (kvm->arch.vpit)
4109 goto create_pit_unlock;
7837699f 4110 r = -ENOMEM;
c5ff41ce 4111 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4112 if (kvm->arch.vpit)
4113 r = 0;
269e05e4 4114 create_pit_unlock:
250715a6 4115 mutex_unlock(&kvm->lock);
7837699f 4116 break;
1fe779f8
CO		 4117 case KVM_GET_IRQCHIP: {
4118 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4119 struct kvm_irqchip *chip;
1fe779f8 4120
ff5c2c03
SL		 4121 chip = memdup_user(argp, sizeof(*chip));
4122 if (IS_ERR(chip)) {
4123 r = PTR_ERR(chip);
1fe779f8 4124 goto out;
ff5c2c03
SL		 4125 }
4126
1fe779f8 4127 r = -ENXIO;
826da321 4128 if (!irqchip_kernel(kvm))
f0d66275
DH		 4129 goto get_irqchip_out;
4130 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4131 if (r)
f0d66275 4132 goto get_irqchip_out;
1fe779f8 4133 r = -EFAULT;
f0d66275
DH		 4134 if (copy_to_user(argp, chip, sizeof *chip))
4135 goto get_irqchip_out;
1fe779f8 4136 r = 0;
f0d66275
DH		 4137 get_irqchip_out:
4138 kfree(chip);
1fe779f8
CO		 4139 break;
4140 }
4141 case KVM_SET_IRQCHIP: {
4142 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4143 struct kvm_irqchip *chip;
1fe779f8 4144
ff5c2c03
SL		 4145 chip = memdup_user(argp, sizeof(*chip));
4146 if (IS_ERR(chip)) {
4147 r = PTR_ERR(chip);
1fe779f8 4148 goto out;
ff5c2c03
SL		 4149 }
4150
1fe779f8 4151 r = -ENXIO;
826da321 4152 if (!irqchip_kernel(kvm))
f0d66275
DH		 4153 goto set_irqchip_out;
4154 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4155 if (r)
f0d66275 4156 goto set_irqchip_out;
1fe779f8 4157 r = 0;
f0d66275
DH		 4158 set_irqchip_out:
4159 kfree(chip);
1fe779f8
CO		 4160 break;
4161 }
e0f63cb9 4162 case KVM_GET_PIT: {
e0f63cb9 4163 r = -EFAULT;
f0d66275 4164 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4165 goto out;
4166 r = -ENXIO;
4167 if (!kvm->arch.vpit)
4168 goto out;
f0d66275 4169 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4170 if (r)
4171 goto out;
4172 r = -EFAULT;
f0d66275 4173 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4174 goto out;
4175 r = 0;
4176 break;
4177 }
4178 case KVM_SET_PIT: {
e0f63cb9 4179 r = -EFAULT;
f0d66275 4180 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4181 goto out;
4182 r = -ENXIO;
4183 if (!kvm->arch.vpit)
4184 goto out;
f0d66275 4185 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4186 break;
4187 }
e9f42757
BK		 4188 case KVM_GET_PIT2: {
4189 r = -ENXIO;
4190 if (!kvm->arch.vpit)
4191 goto out;
4192 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4193 if (r)
4194 goto out;
4195 r = -EFAULT;
4196 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4197 goto out;
4198 r = 0;
4199 break;
4200 }
4201 case KVM_SET_PIT2: {
4202 r = -EFAULT;
4203 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4204 goto out;
4205 r = -ENXIO;
4206 if (!kvm->arch.vpit)
4207 goto out;
4208 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4209 break;
4210 }
52d939a0
MT		 4211 case KVM_REINJECT_CONTROL: {
4212 struct kvm_reinject_control control;
4213 r = -EFAULT;
4214 if (copy_from_user(&control, argp, sizeof(control)))
4215 goto out;
4216 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4217 break;
4218 }
d71ba788
PB		 4219 case KVM_SET_BOOT_CPU_ID:
4220 r = 0;
4221 mutex_lock(&kvm->lock);
557abc40 4222 if (kvm->created_vcpus)
d71ba788
PB		 4223 r = -EBUSY;
4224 else
4225 kvm->arch.bsp_vcpu_id = arg;
4226 mutex_unlock(&kvm->lock);
4227 break;
ffde22ac
ES		 4228 case KVM_XEN_HVM_CONFIG: {
4229 r = -EFAULT;
4230 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4231 sizeof(struct kvm_xen_hvm_config)))
4232 goto out;
4233 r = -EINVAL;
4234 if (kvm->arch.xen_hvm_config.flags)
4235 goto out;
4236 r = 0;
4237 break;
4238 }
afbcf7ab 4239 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4240 struct kvm_clock_data user_ns;
4241 u64 now_ns;
afbcf7ab
GC		 4242
4243 r = -EFAULT;
4244 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4245 goto out;
4246
4247 r = -EINVAL;
4248 if (user_ns.flags)
4249 goto out;
4250
4251 r = 0;
0bc48bea
RK		 4252 /*
4253 * TODO: userspace has to take care of races with VCPU_RUN, so
4254 * kvm_gen_update_masterclock() can be cut down to locked
4255 * pvclock_update_vm_gtod_copy().
4256 */
4257 kvm_gen_update_masterclock(kvm);
e891a32e 4258 now_ns = get_kvmclock_ns(kvm);
108b249c 4259 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4260 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4261 break;
4262 }
4263 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4264 struct kvm_clock_data user_ns;
4265 u64 now_ns;
4266
e891a32e 4267 now_ns = get_kvmclock_ns(kvm);
108b249c 4268 user_ns.clock = now_ns;
e3fd9a93 4269 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4270 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4271
4272 r = -EFAULT;
4273 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4274 goto out;
4275 r = 0;
4276 break;
4277 }
90de4a18
NA		 4278 case KVM_ENABLE_CAP: {
4279 struct kvm_enable_cap cap;
afbcf7ab 4280
90de4a18
NA		 4281 r = -EFAULT;
4282 if (copy_from_user(&cap, argp, sizeof(cap)))
4283 goto out;
4284 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4285 break;
4286 }
1fe779f8 4287 default:
ad6260da 4288 r = -ENOTTY;
1fe779f8
CO		 4289 }
4290out:
4291 return r;
4292}
4293
a16b043c 4294static void kvm_init_msr_list(void)
043405e1
CO		 4295{
4296 u32 dummy[2];
4297 unsigned i, j;
4298
62ef68bb 4299 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4300 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4301 continue;
93c4adc7
PB		 4302
4303 /*
4304 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4305 * to the guests in some cases.
93c4adc7
PB		 4306 */
4307 switch (msrs_to_save[i]) {
4308 case MSR_IA32_BNDCFGS:
4309 if (!kvm_x86_ops->mpx_supported())
4310 continue;
4311 break;
9dbe6cf9
PB		 4312 case MSR_TSC_AUX:
4313 if (!kvm_x86_ops->rdtscp_supported())
4314 continue;
4315 break;
93c4adc7
PB		 4316 default:
4317 break;
4318 }
4319
043405e1
CO		 4320 if (j < i)
4321 msrs_to_save[j] = msrs_to_save[i];
4322 j++;
4323 }
4324 num_msrs_to_save = j;
62ef68bb
PB		 4325
4326 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4327 switch (emulated_msrs[i]) {
6d396b55
PB		 4328 case MSR_IA32_SMBASE:
4329 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4330 continue;
4331 break;
62ef68bb
PB		 4332 default:
4333 break;
4334 }
4335
4336 if (j < i)
4337 emulated_msrs[j] = emulated_msrs[i];
4338 j++;
4339 }
4340 num_emulated_msrs = j;
043405e1
CO		 4341}
4342
bda9020e
MT		 4343static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4344 const void *v)
bbd9b64e 4345{
70252a10
AK		 4346 int handled = 0;
4347 int n;
4348
4349 do {
4350 n = min(len, 8);
bce87cce 4351 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4352 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4353 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4354 break;
4355 handled += n;
4356 addr += n;
4357 len -= n;
4358 v += n;
4359 } while (len);
bbd9b64e 4360
70252a10 4361 return handled;
bbd9b64e
CO		 4362}
4363
bda9020e 4364static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4365{
70252a10
AK		 4366 int handled = 0;
4367 int n;
4368
4369 do {
4370 n = min(len, 8);
bce87cce 4371 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4372 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4373 addr, n, v))
4374 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4375 break;
4376 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4377 handled += n;
4378 addr += n;
4379 len -= n;
4380 v += n;
4381 } while (len);
bbd9b64e 4382
70252a10 4383 return handled;
bbd9b64e
CO		 4384}
4385
2dafc6c2
GN		 4386static void kvm_set_segment(struct kvm_vcpu *vcpu,
4387 struct kvm_segment *var, int seg)
4388{
4389 kvm_x86_ops->set_segment(vcpu, var, seg);
4390}
4391
4392void kvm_get_segment(struct kvm_vcpu *vcpu,
4393 struct kvm_segment *var, int seg)
4394{
4395 kvm_x86_ops->get_segment(vcpu, var, seg);
4396}
4397
54987b7a
PB		 4398gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4399 struct x86_exception *exception)
02f59dc9
JR		 4400{
4401 gpa_t t_gpa;
02f59dc9
JR		 4402
4403 BUG_ON(!mmu_is_nested(vcpu));
4404
4405 /* NPT walks are always user-walks */
4406 access |= PFERR_USER_MASK;
54987b7a 4407 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4408
4409 return t_gpa;
4410}
4411
ab9ae313
AK		 4412gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4413 struct x86_exception *exception)
1871c602
GN		 4414{
4415 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4416 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4417}
4418
ab9ae313
AK		 4419 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4420 struct x86_exception *exception)
1871c602
GN		 4421{
4422 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4423 access |= PFERR_FETCH_MASK;
ab9ae313 4424 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4425}
4426
ab9ae313
AK		 4427gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4428 struct x86_exception *exception)
1871c602
GN		 4429{
4430 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4431 access |= PFERR_WRITE_MASK;
ab9ae313 4432 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4433}
4434
4435/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4436gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4437 struct x86_exception *exception)
1871c602 4438{
ab9ae313 4439 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4440}
4441
4442static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4443 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4444 struct x86_exception *exception)
bbd9b64e
CO		 4445{
4446 void *data = val;
10589a46 4447 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4448
4449 while (bytes) {
14dfe855 4450 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4451 exception);
bbd9b64e 4452 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4453 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4454 int ret;
4455
bcc55cba 4456 if (gpa == UNMAPPED_GVA)
ab9ae313 4457 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4458 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4459 offset, toread);
10589a46 4460 if (ret < 0) {
c3cd7ffa 4461 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4462 goto out;
4463 }
bbd9b64e 4464
77c2002e
IE		 4465 bytes -= toread;
4466 data += toread;
4467 addr += toread;
bbd9b64e 4468 }
10589a46 4469out:
10589a46 4470 return r;
bbd9b64e 4471}
77c2002e 4472
1871c602 4473/* used for instruction fetching */
0f65dd70
AK		 4474static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4475 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4476 struct x86_exception *exception)
1871c602 4477{
0f65dd70 4478 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4479 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4480 unsigned offset;
4481 int ret;
0f65dd70 4482
44583cba
PB		 4483 /* Inline kvm_read_guest_virt_helper for speed. */
4484 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4485 exception);
4486 if (unlikely(gpa == UNMAPPED_GVA))
4487 return X86EMUL_PROPAGATE_FAULT;
4488
4489 offset = addr & (PAGE_SIZE-1);
4490 if (WARN_ON(offset + bytes > PAGE_SIZE))
4491 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4492 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4493 offset, bytes);
44583cba
PB		 4494 if (unlikely(ret < 0))
4495 return X86EMUL_IO_NEEDED;
4496
4497 return X86EMUL_CONTINUE;
1871c602
GN		 4498}
4499
064aea77 4500int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4501 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4502 struct x86_exception *exception)
1871c602 4503{
0f65dd70 4504 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4505 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4506
1871c602 4507 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4508 exception);
1871c602 4509}
064aea77 4510EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4511
0f65dd70
AK		 4512static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4513 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4514 struct x86_exception *exception)
1871c602 4515{
0f65dd70 4516 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4517 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4518}
4519
7a036a6f
RK		 4520static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4521 unsigned long addr, void *val, unsigned int bytes)
4522{
4523 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4524 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4525
4526 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4527}
4528
6a4d7550 4529int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4530 gva_t addr, void *val,
2dafc6c2 4531 unsigned int bytes,
bcc55cba 4532 struct x86_exception *exception)
77c2002e 4533{
0f65dd70 4534 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4535 void *data = val;
4536 int r = X86EMUL_CONTINUE;
4537
4538 while (bytes) {
14dfe855
JR		 4539 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4540 PFERR_WRITE_MASK,
ab9ae313 4541 exception);
77c2002e
IE		 4542 unsigned offset = addr & (PAGE_SIZE-1);
4543 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4544 int ret;
4545
bcc55cba 4546 if (gpa == UNMAPPED_GVA)
ab9ae313 4547 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4548 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4549 if (ret < 0) {
c3cd7ffa 4550 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4551 goto out;
4552 }
4553
4554 bytes -= towrite;
4555 data += towrite;
4556 addr += towrite;
4557 }
4558out:
4559 return r;
4560}
6a4d7550 4561EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4562
0f89b207
TL		 4563static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4564 gpa_t gpa, bool write)
4565{
4566 /* For APIC access vmexit */
4567 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4568 return 1;
4569
4570 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4571 trace_vcpu_match_mmio(gva, gpa, write, true);
4572 return 1;
4573 }
4574
4575 return 0;
4576}
4577
af7cc7d1
XG		 4578static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4579 gpa_t *gpa, struct x86_exception *exception,
4580 bool write)
4581{
97d64b78
AK		 4582 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4583 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4584
be94f6b7
HH		 4585 /*
4586 * currently PKRU is only applied to ept enabled guest so
4587 * there is no pkey in EPT page table for L1 guest or EPT
4588 * shadow page table for L2 guest.
4589 */
97d64b78 4590 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4591 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4592 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4593 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4594 (gva & (PAGE_SIZE - 1));
4f022648 4595 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4596 return 1;
4597 }
4598
af7cc7d1
XG		 4599 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4600
4601 if (*gpa == UNMAPPED_GVA)
4602 return -1;
4603
0f89b207 4604 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4605}
4606
3200f405 4607int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4608 const void *val, int bytes)
bbd9b64e
CO		 4609{
4610 int ret;
4611
54bf36aa 4612 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4613 if (ret < 0)
bbd9b64e 4614 return 0;
0eb05bf2 4615 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4616 return 1;
4617}
4618
77d197b2
XG		 4619struct read_write_emulator_ops {
4620 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4621 int bytes);
4622 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4623 void *val, int bytes);
4624 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4625 int bytes, void *val);
4626 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4627 void *val, int bytes);
4628 bool write;
4629};
4630
4631static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4632{
4633 if (vcpu->mmio_read_completed) {
77d197b2 4634 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4635 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4636 vcpu->mmio_read_completed = 0;
4637 return 1;
4638 }
4639
4640 return 0;
4641}
4642
4643static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4644 void *val, int bytes)
4645{
54bf36aa 4646 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4647}
4648
4649static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4650 void *val, int bytes)
4651{
4652 return emulator_write_phys(vcpu, gpa, val, bytes);
4653}
4654
4655static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4656{
4657 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4658 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4659}
4660
4661static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4662 void *val, int bytes)
4663{
4664 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4665 return X86EMUL_IO_NEEDED;
4666}
4667
4668static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4669 void *val, int bytes)
4670{
f78146b0
AK		 4671 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4672
87da7e66 4673 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4674 return X86EMUL_CONTINUE;
4675}
4676
0fbe9b0b 4677static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4678 .read_write_prepare = read_prepare,
4679 .read_write_emulate = read_emulate,
4680 .read_write_mmio = vcpu_mmio_read,
4681 .read_write_exit_mmio = read_exit_mmio,
4682};
4683
0fbe9b0b 4684static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4685 .read_write_emulate = write_emulate,
4686 .read_write_mmio = write_mmio,
4687 .read_write_exit_mmio = write_exit_mmio,
4688 .write = true,
4689};
4690
22388a3c
XG		 4691static int emulator_read_write_onepage(unsigned long addr, void *val,
4692 unsigned int bytes,
4693 struct x86_exception *exception,
4694 struct kvm_vcpu *vcpu,
0fbe9b0b 4695 const struct read_write_emulator_ops *ops)
bbd9b64e 4696{
af7cc7d1
XG		 4697 gpa_t gpa;
4698 int handled, ret;
22388a3c 4699 bool write = ops->write;
f78146b0 4700 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4701 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4702
4703 /*
4704 * If the exit was due to a NPF we may already have a GPA.
4705 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4706 * Note, this cannot be used on string operations since string
4707 * operation using rep will only have the initial GPA from the NPF
4708 * occurred.
4709 */
4710 if (vcpu->arch.gpa_available &&
4711 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4712 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4713 gpa = vcpu->arch.gpa_val;
4714 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4715 } else {
4716 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4717 if (ret < 0)
4718 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4719 }
10589a46 4720
618232e2 4721 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4722 return X86EMUL_CONTINUE;
4723
bbd9b64e
CO		 4724 /*
4725 * Is this MMIO handled locally?
4726 */
22388a3c 4727 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4728 if (handled == bytes)
bbd9b64e 4729 return X86EMUL_CONTINUE;
bbd9b64e 4730
70252a10
AK		 4731 gpa += handled;
4732 bytes -= handled;
4733 val += handled;
4734
87da7e66
XG		 4735 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4736 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4737 frag->gpa = gpa;
4738 frag->data = val;
4739 frag->len = bytes;
f78146b0 4740 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4741}
4742
52eb5a6d
XL		 4743static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4744 unsigned long addr,
22388a3c
XG		 4745 void *val, unsigned int bytes,
4746 struct x86_exception *exception,
0fbe9b0b 4747 const struct read_write_emulator_ops *ops)
bbd9b64e 4748{
0f65dd70 4749 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4750 gpa_t gpa;
4751 int rc;
4752
4753 if (ops->read_write_prepare &&
4754 ops->read_write_prepare(vcpu, val, bytes))
4755 return X86EMUL_CONTINUE;
4756
4757 vcpu->mmio_nr_fragments = 0;
0f65dd70 4758
bbd9b64e
CO		 4759 /* Crossing a page boundary? */
4760 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4761 int now;
bbd9b64e
CO		 4762
4763 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4764 rc = emulator_read_write_onepage(addr, val, now, exception,
4765 vcpu, ops);
4766
bbd9b64e
CO		 4767 if (rc != X86EMUL_CONTINUE)
4768 return rc;
4769 addr += now;
bac15531
NA		 4770 if (ctxt->mode != X86EMUL_MODE_PROT64)
4771 addr = (u32)addr;
bbd9b64e
CO		 4772 val += now;
4773 bytes -= now;
4774 }
22388a3c 4775
f78146b0
AK		 4776 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4777 vcpu, ops);
4778 if (rc != X86EMUL_CONTINUE)
4779 return rc;
4780
4781 if (!vcpu->mmio_nr_fragments)
4782 return rc;
4783
4784 gpa = vcpu->mmio_fragments[0].gpa;
4785
4786 vcpu->mmio_needed = 1;
4787 vcpu->mmio_cur_fragment = 0;
4788
87da7e66 4789 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4790 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4791 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4792 vcpu->run->mmio.phys_addr = gpa;
4793
4794 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4795}
4796
4797static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4798 unsigned long addr,
4799 void *val,
4800 unsigned int bytes,
4801 struct x86_exception *exception)
4802{
4803 return emulator_read_write(ctxt, addr, val, bytes,
4804 exception, &read_emultor);
4805}
4806
52eb5a6d 4807static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4808 unsigned long addr,
4809 const void *val,
4810 unsigned int bytes,
4811 struct x86_exception *exception)
4812{
4813 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4814 exception, &write_emultor);
bbd9b64e 4815}
bbd9b64e 4816
daea3e73
AK		 4817#define CMPXCHG_TYPE(t, ptr, old, new) \
4818 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4819
4820#ifdef CONFIG_X86_64
4821# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4822#else
4823# define CMPXCHG64(ptr, old, new) \
9749a6c0 4824 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4825#endif
4826
0f65dd70
AK		 4827static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4828 unsigned long addr,
bbd9b64e
CO		 4829 const void *old,
4830 const void *new,
4831 unsigned int bytes,
0f65dd70 4832 struct x86_exception *exception)
bbd9b64e 4833{
0f65dd70 4834 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4835 gpa_t gpa;
4836 struct page *page;
4837 char *kaddr;
4838 bool exchanged;
2bacc55c 4839
daea3e73
AK		 4840 /* guests cmpxchg8b have to be emulated atomically */
4841 if (bytes > 8 || (bytes & (bytes - 1)))
4842 goto emul_write;
10589a46 4843
daea3e73 4844 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4845
daea3e73
AK		 4846 if (gpa == UNMAPPED_GVA ||
4847 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4848 goto emul_write;
2bacc55c 4849
daea3e73
AK		 4850 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4851 goto emul_write;
72dc67a6 4852
54bf36aa 4853 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4854 if (is_error_page(page))
c19b8bd6 4855 goto emul_write;
72dc67a6 4856
8fd75e12 4857 kaddr = kmap_atomic(page);
daea3e73
AK		 4858 kaddr += offset_in_page(gpa);
4859 switch (bytes) {
4860 case 1:
4861 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4862 break;
4863 case 2:
4864 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4865 break;
4866 case 4:
4867 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4868 break;
4869 case 8:
4870 exchanged = CMPXCHG64(kaddr, old, new);
4871 break;
4872 default:
4873 BUG();
2bacc55c 4874 }
8fd75e12 4875 kunmap_atomic(kaddr);
daea3e73
AK		 4876 kvm_release_page_dirty(page);
4877
4878 if (!exchanged)
4879 return X86EMUL_CMPXCHG_FAILED;
4880
54bf36aa 4881 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4882 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4883
4884 return X86EMUL_CONTINUE;
4a5f48f6 4885
3200f405 4886emul_write:
daea3e73 4887 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4888
0f65dd70 4889 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4890}
4891
cf8f70bf
GN		 4892static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4893{
cbfc6c91 4894 int r = 0, i;
cf8f70bf 4895
cbfc6c91
WL		 4896 for (i = 0; i < vcpu->arch.pio.count; i++) {
4897 if (vcpu->arch.pio.in)
4898 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4899 vcpu->arch.pio.size, pd);
4900 else
4901 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4902 vcpu->arch.pio.port, vcpu->arch.pio.size,
4903 pd);
4904 if (r)
4905 break;
4906 pd += vcpu->arch.pio.size;
4907 }
cf8f70bf
GN		 4908 return r;
4909}
4910
6f6fbe98
XG		 4911static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4912 unsigned short port, void *val,
4913 unsigned int count, bool in)
cf8f70bf 4914{
cf8f70bf 4915 vcpu->arch.pio.port = port;
6f6fbe98 4916 vcpu->arch.pio.in = in;
7972995b 4917 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4918 vcpu->arch.pio.size = size;
4919
4920 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4921 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4922 return 1;
4923 }
4924
4925 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4926 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4927 vcpu->run->io.size = size;
4928 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4929 vcpu->run->io.count = count;
4930 vcpu->run->io.port = port;
4931
4932 return 0;
4933}
4934
6f6fbe98
XG		 4935static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4936 int size, unsigned short port, void *val,
4937 unsigned int count)
cf8f70bf 4938{
ca1d4a9e 4939 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4940 int ret;
ca1d4a9e 4941
6f6fbe98
XG		 4942 if (vcpu->arch.pio.count)
4943 goto data_avail;
cf8f70bf 4944
cbfc6c91
WL		 4945 memset(vcpu->arch.pio_data, 0, size * count);
4946
6f6fbe98
XG		 4947 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4948 if (ret) {
4949data_avail:
4950 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4951 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4952 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4953 return 1;
4954 }
4955
cf8f70bf
GN		 4956 return 0;
4957}
4958
6f6fbe98
XG		 4959static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4960 int size, unsigned short port,
4961 const void *val, unsigned int count)
4962{
4963 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4964
4965 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4966 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4967 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4968}
4969
bbd9b64e
CO		 4970static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4971{
4972 return kvm_x86_ops->get_segment_base(vcpu, seg);
4973}
4974
3cb16fe7 4975static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4976{
3cb16fe7 4977 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4978}
4979
ae6a2375 4980static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4981{
4982 if (!need_emulate_wbinvd(vcpu))
4983 return X86EMUL_CONTINUE;
4984
4985 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4986 int cpu = get_cpu();
4987
4988 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4989 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4990 wbinvd_ipi, NULL, 1);
2eec7343 4991 put_cpu();
f5f48ee1 4992 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4993 } else
4994 wbinvd();
f5f48ee1
SY		 4995 return X86EMUL_CONTINUE;
4996}
5cb56059
JS		 4997
4998int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4999{
6affcbed
KH		 5000 kvm_emulate_wbinvd_noskip(vcpu);
5001 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5002}
f5f48ee1
SY		 5003EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5004
5cb56059
JS		 5005
5006
bcaf5cc5
AK		 5007static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5008{
5cb56059 5009 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5010}
5011
52eb5a6d
XL		 5012static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5013 unsigned long *dest)
bbd9b64e 5014{
16f8a6f9 5015 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5016}
5017
52eb5a6d
XL		 5018static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5019 unsigned long value)
bbd9b64e 5020{
338dbc97 5021
717746e3 5022 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5023}
5024
52a46617 5025static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5026{
52a46617 5027 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5028}
5029
717746e3 5030static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5031{
717746e3 5032 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5033 unsigned long value;
5034
5035 switch (cr) {
5036 case 0:
5037 value = kvm_read_cr0(vcpu);
5038 break;
5039 case 2:
5040 value = vcpu->arch.cr2;
5041 break;
5042 case 3:
9f8fe504 5043 value = kvm_read_cr3(vcpu);
52a46617
GN		 5044 break;
5045 case 4:
5046 value = kvm_read_cr4(vcpu);
5047 break;
5048 case 8:
5049 value = kvm_get_cr8(vcpu);
5050 break;
5051 default:
a737f256 5052 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5053 return 0;
5054 }
5055
5056 return value;
5057}
5058
717746e3 5059static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5060{
717746e3 5061 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5062 int res = 0;
5063
52a46617
GN		 5064 switch (cr) {
5065 case 0:
49a9b07e 5066 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5067 break;
5068 case 2:
5069 vcpu->arch.cr2 = val;
5070 break;
5071 case 3:
2390218b 5072 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5073 break;
5074 case 4:
a83b29c6 5075 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5076 break;
5077 case 8:
eea1cff9 5078 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5079 break;
5080 default:
a737f256 5081 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5082 res = -1;
52a46617 5083 }
0f12244f
GN		 5084
5085 return res;
52a46617
GN		 5086}
5087
717746e3 5088static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5089{
717746e3 5090 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5091}
5092
4bff1e86 5093static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5094{
4bff1e86 5095 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5096}
5097
4bff1e86 5098static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5099{
4bff1e86 5100 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5101}
5102
1ac9d0cf
AK		 5103static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5104{
5105 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5106}
5107
5108static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5109{
5110 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5111}
5112
4bff1e86
AK		 5113static unsigned long emulator_get_cached_segment_base(
5114 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5115{
4bff1e86 5116 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5117}
5118
1aa36616
AK		 5119static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5120 struct desc_struct *desc, u32 *base3,
5121 int seg)
2dafc6c2
GN		 5122{
5123 struct kvm_segment var;
5124
4bff1e86 5125 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5126 *selector = var.selector;
2dafc6c2 5127
378a8b09
GN		 5128 if (var.unusable) {
5129 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5130 if (base3)
5131 *base3 = 0;
2dafc6c2 5132 return false;
378a8b09 5133 }
2dafc6c2
GN		 5134
5135 if (var.g)
5136 var.limit >>= 12;
5137 set_desc_limit(desc, var.limit);
5138 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5139#ifdef CONFIG_X86_64
5140 if (base3)
5141 *base3 = var.base >> 32;
5142#endif
2dafc6c2
GN		 5143 desc->type = var.type;
5144 desc->s = var.s;
5145 desc->dpl = var.dpl;
5146 desc->p = var.present;
5147 desc->avl = var.avl;
5148 desc->l = var.l;
5149 desc->d = var.db;
5150 desc->g = var.g;
5151
5152 return true;
5153}
5154
1aa36616
AK		 5155static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5156 struct desc_struct *desc, u32 base3,
5157 int seg)
2dafc6c2 5158{
4bff1e86 5159 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5160 struct kvm_segment var;
5161
1aa36616 5162 var.selector = selector;
2dafc6c2 5163 var.base = get_desc_base(desc);
5601d05b
GN		 5164#ifdef CONFIG_X86_64
5165 var.base |= ((u64)base3) << 32;
5166#endif
2dafc6c2
GN		 5167 var.limit = get_desc_limit(desc);
5168 if (desc->g)
5169 var.limit = (var.limit << 12) | 0xfff;
5170 var.type = desc->type;
2dafc6c2
GN		 5171 var.dpl = desc->dpl;
5172 var.db = desc->d;
5173 var.s = desc->s;
5174 var.l = desc->l;
5175 var.g = desc->g;
5176 var.avl = desc->avl;
5177 var.present = desc->p;
5178 var.unusable = !var.present;
5179 var.padding = 0;
5180
5181 kvm_set_segment(vcpu, &var, seg);
5182 return;
5183}
5184
717746e3
AK		 5185static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5186 u32 msr_index, u64 *pdata)
5187{
609e36d3
PB		 5188 struct msr_data msr;
5189 int r;
5190
5191 msr.index = msr_index;
5192 msr.host_initiated = false;
5193 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5194 if (r)
5195 return r;
5196
5197 *pdata = msr.data;
5198 return 0;
717746e3
AK		 5199}
5200
5201static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5202 u32 msr_index, u64 data)
5203{
8fe8ab46
WA		 5204 struct msr_data msr;
5205
5206 msr.data = data;
5207 msr.index = msr_index;
5208 msr.host_initiated = false;
5209 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5210}
5211
64d60670
PB		 5212static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5213{
5214 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5215
5216 return vcpu->arch.smbase;
5217}
5218
5219static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5220{
5221 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5222
5223 vcpu->arch.smbase = smbase;
5224}
5225
67f4d428
NA		 5226static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5227 u32 pmc)
5228{
c6702c9d 5229 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5230}
5231
222d21aa
AK		 5232static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5233 u32 pmc, u64 *pdata)
5234{
c6702c9d 5235 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5236}
5237
6c3287f7
AK		 5238static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5239{
5240 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5241}
5242
5037f6f3
AK		 5243static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5244{
5245 preempt_disable();
5197b808 5246 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5247}
5248
5249static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5250{
5251 preempt_enable();
5252}
5253
2953538e 5254static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5255 struct x86_instruction_info *info,
c4f035c6
AK		 5256 enum x86_intercept_stage stage)
5257{
2953538e 5258 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5259}
5260
e911eb3b
YZ		 5261static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5262 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5263{
e911eb3b 5264 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5265}
5266
dd856efa
AK		 5267static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5268{
5269 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5270}
5271
5272static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5273{
5274 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5275}
5276
801806d9
NA		 5277static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5278{
5279 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5280}
5281
6ed071f0
LP		 5282static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5283{
5284 return emul_to_vcpu(ctxt)->arch.hflags;
5285}
5286
5287static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5288{
5289 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5290}
5291
0234bf88
LP		 5292static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5293{
5294 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5295}
5296
0225fb50 5297static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5298 .read_gpr = emulator_read_gpr,
5299 .write_gpr = emulator_write_gpr,
1871c602 5300 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5301 .write_std = kvm_write_guest_virt_system,
7a036a6f 5302 .read_phys = kvm_read_guest_phys_system,
1871c602 5303 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5304 .read_emulated = emulator_read_emulated,
5305 .write_emulated = emulator_write_emulated,
5306 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5307 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5308 .pio_in_emulated = emulator_pio_in_emulated,
5309 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5310 .get_segment = emulator_get_segment,
5311 .set_segment = emulator_set_segment,
5951c442 5312 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5313 .get_gdt = emulator_get_gdt,
160ce1f1 5314 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5315 .set_gdt = emulator_set_gdt,
5316 .set_idt = emulator_set_idt,
52a46617
GN		 5317 .get_cr = emulator_get_cr,
5318 .set_cr = emulator_set_cr,
9c537244 5319 .cpl = emulator_get_cpl,
35aa5375
GN		 5320 .get_dr = emulator_get_dr,
5321 .set_dr = emulator_set_dr,
64d60670
PB		 5322 .get_smbase = emulator_get_smbase,
5323 .set_smbase = emulator_set_smbase,
717746e3
AK		 5324 .set_msr = emulator_set_msr,
5325 .get_msr = emulator_get_msr,
67f4d428 5326 .check_pmc = emulator_check_pmc,
222d21aa 5327 .read_pmc = emulator_read_pmc,
6c3287f7 5328 .halt = emulator_halt,
bcaf5cc5 5329 .wbinvd = emulator_wbinvd,
d6aa1000 5330 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5331 .get_fpu = emulator_get_fpu,
5332 .put_fpu = emulator_put_fpu,
c4f035c6 5333 .intercept = emulator_intercept,
bdb42f5a 5334 .get_cpuid = emulator_get_cpuid,
801806d9 5335 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5336 .get_hflags = emulator_get_hflags,
5337 .set_hflags = emulator_set_hflags,
0234bf88 5338 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5339};
5340
95cb2295
GN		 5341static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5342{
37ccdcbe 5343 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5344 /*
5345 * an sti; sti; sequence only disable interrupts for the first
5346 * instruction. So, if the last instruction, be it emulated or
5347 * not, left the system with the INT_STI flag enabled, it
5348 * means that the last instruction is an sti. We should not
5349 * leave the flag on in this case. The same goes for mov ss
5350 */
37ccdcbe
PB		 5351 if (int_shadow & mask)
5352 mask = 0;
6addfc42 5353 if (unlikely(int_shadow || mask)) {
95cb2295 5354 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5355 if (!mask)
5356 kvm_make_request(KVM_REQ_EVENT, vcpu);
5357 }
95cb2295
GN		 5358}
5359
ef54bcfe 5360static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5361{
5362 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5363 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5364 return kvm_propagate_fault(vcpu, &ctxt->exception);
5365
5366 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5367 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5368 ctxt->exception.error_code);
54b8486f 5369 else
da9cb575 5370 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5371 return false;
54b8486f
GN		 5372}
5373
8ec4722d
MG		 5374static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5375{
adf52235 5376 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5377 int cs_db, cs_l;
5378
8ec4722d
MG		 5379 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5380
adf52235 5381 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5382 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5383
adf52235
TY		 5384 ctxt->eip = kvm_rip_read(vcpu);
5385 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5386 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5387 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5388 cs_db ? X86EMUL_MODE_PROT32 :
5389 X86EMUL_MODE_PROT16;
a584539b 5390 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5391 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5392 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5393
dd856efa 5394 init_decode_cache(ctxt);
7ae441ea 5395 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5396}
5397
71f9833b 5398int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5399{
9d74191a 5400 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5401 int ret;
5402
5403 init_emulate_ctxt(vcpu);
5404
9dac77fa
AK		 5405 ctxt->op_bytes = 2;
5406 ctxt->ad_bytes = 2;
5407 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5408 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5409
5410 if (ret != X86EMUL_CONTINUE)
5411 return EMULATE_FAIL;
5412
9dac77fa 5413 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5414 kvm_rip_write(vcpu, ctxt->eip);
5415 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5416
5417 if (irq == NMI_VECTOR)
7460fb4a 5418 vcpu->arch.nmi_pending = 0;
63995653
MG		 5419 else
5420 vcpu->arch.interrupt.pending = false;
5421
5422 return EMULATE_DONE;
5423}
5424EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5425
6d77dbfc
GN		 5426static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5427{
fc3a9157
JR		 5428 int r = EMULATE_DONE;
5429
6d77dbfc
GN		 5430 ++vcpu->stat.insn_emulation_fail;
5431 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5432 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5433 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5434 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5435 vcpu->run->internal.ndata = 0;
1f4dcb3b 5436 r = EMULATE_USER_EXIT;
fc3a9157 5437 }
6d77dbfc 5438 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5439
5440 return r;
6d77dbfc
GN		 5441}
5442
93c05d3e 5443static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5444 bool write_fault_to_shadow_pgtable,
5445 int emulation_type)
a6f177ef 5446{
95b3cf69 5447 gpa_t gpa = cr2;
ba049e93 5448 kvm_pfn_t pfn;
a6f177ef 5449
991eebf9
GN		 5450 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5451 return false;
5452
95b3cf69
XG		 5453 if (!vcpu->arch.mmu.direct_map) {
5454 /*
5455 * Write permission should be allowed since only
5456 * write access need to be emulated.
5457 */
5458 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5459
95b3cf69
XG		 5460 /*
5461 * If the mapping is invalid in guest, let cpu retry
5462 * it to generate fault.
5463 */
5464 if (gpa == UNMAPPED_GVA)
5465 return true;
5466 }
a6f177ef 5467
8e3d9d06
XG		 5468 /*
5469 * Do not retry the unhandleable instruction if it faults on the
5470 * readonly host memory, otherwise it will goto a infinite loop:
5471 * retry instruction -> write #PF -> emulation fail -> retry
5472 * instruction -> ...
5473 */
5474 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5475
5476 /*
5477 * If the instruction failed on the error pfn, it can not be fixed,
5478 * report the error to userspace.
5479 */
5480 if (is_error_noslot_pfn(pfn))
5481 return false;
5482
5483 kvm_release_pfn_clean(pfn);
5484
5485 /* The instructions are well-emulated on direct mmu. */
5486 if (vcpu->arch.mmu.direct_map) {
5487 unsigned int indirect_shadow_pages;
5488
5489 spin_lock(&vcpu->kvm->mmu_lock);
5490 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5491 spin_unlock(&vcpu->kvm->mmu_lock);
5492
5493 if (indirect_shadow_pages)
5494 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5495
a6f177ef 5496 return true;
8e3d9d06 5497 }
a6f177ef 5498
95b3cf69
XG		 5499 /*
5500 * if emulation was due to access to shadowed page table
5501 * and it failed try to unshadow page and re-enter the
5502 * guest to let CPU execute the instruction.
5503 */
5504 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5505
5506 /*
5507 * If the access faults on its page table, it can not
5508 * be fixed by unprotecting shadow page and it should
5509 * be reported to userspace.
5510 */
5511 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5512}
5513
1cb3f3ae
XG		 5514static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5515 unsigned long cr2, int emulation_type)
5516{
5517 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5518 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5519
5520 last_retry_eip = vcpu->arch.last_retry_eip;
5521 last_retry_addr = vcpu->arch.last_retry_addr;
5522
5523 /*
5524 * If the emulation is caused by #PF and it is non-page_table
5525 * writing instruction, it means the VM-EXIT is caused by shadow
5526 * page protected, we can zap the shadow page and retry this
5527 * instruction directly.
5528 *
5529 * Note: if the guest uses a non-page-table modifying instruction
5530 * on the PDE that points to the instruction, then we will unmap
5531 * the instruction and go to an infinite loop. So, we cache the
5532 * last retried eip and the last fault address, if we meet the eip
5533 * and the address again, we can break out of the potential infinite
5534 * loop.
5535 */
5536 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5537
5538 if (!(emulation_type & EMULTYPE_RETRY))
5539 return false;
5540
5541 if (x86_page_table_writing_insn(ctxt))
5542 return false;
5543
5544 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5545 return false;
5546
5547 vcpu->arch.last_retry_eip = ctxt->eip;
5548 vcpu->arch.last_retry_addr = cr2;
5549
5550 if (!vcpu->arch.mmu.direct_map)
5551 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5552
22368028 5553 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5554
5555 return true;
5556}
5557
716d51ab
GN		 5558static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5559static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5560
64d60670 5561static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5562{
64d60670 5563 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5564 /* This is a good place to trace that we are exiting SMM. */
5565 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5566
c43203ca
PB		 5567 /* Process a latched INIT or SMI, if any. */
5568 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5569 }
699023e2
PB		 5570
5571 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5572}
5573
5574static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5575{
5576 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5577
a584539b 5578 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5579
5580 if (changed & HF_SMM_MASK)
5581 kvm_smm_changed(vcpu);
a584539b
PB		 5582}
5583
4a1e10d5
PB		 5584static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5585 unsigned long *db)
5586{
5587 u32 dr6 = 0;
5588 int i;
5589 u32 enable, rwlen;
5590
5591 enable = dr7;
5592 rwlen = dr7 >> 16;
5593 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5594 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5595 dr6 |= (1 << i);
5596 return dr6;
5597}
5598
c8401dda 5599static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5600{
5601 struct kvm_run *kvm_run = vcpu->run;
5602
c8401dda
PB		 5603 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5604 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5605 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5606 kvm_run->debug.arch.exception = DB_VECTOR;
5607 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5608 *r = EMULATE_USER_EXIT;
5609 } else {
5610 /*
5611 * "Certain debug exceptions may clear bit 0-3. The
5612 * remaining contents of the DR6 register are never
5613 * cleared by the processor".
5614 */
5615 vcpu->arch.dr6 &= ~15;
5616 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5617 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5618 }
5619}
5620
6affcbed
KH		 5621int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5622{
5623 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5624 int r = EMULATE_DONE;
5625
5626 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5627
5628 /*
5629 * rflags is the old, "raw" value of the flags. The new value has
5630 * not been saved yet.
5631 *
5632 * This is correct even for TF set by the guest, because "the
5633 * processor will not generate this exception after the instruction
5634 * that sets the TF flag".
5635 */
5636 if (unlikely(rflags & X86_EFLAGS_TF))
5637 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5638 return r == EMULATE_DONE;
5639}
5640EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5641
4a1e10d5
PB		 5642static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5643{
4a1e10d5
PB		 5644 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5645 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5646 struct kvm_run *kvm_run = vcpu->run;
5647 unsigned long eip = kvm_get_linear_rip(vcpu);
5648 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5649 vcpu->arch.guest_debug_dr7,
5650 vcpu->arch.eff_db);
5651
5652 if (dr6 != 0) {
6f43ed01 5653 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5654 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5655 kvm_run->debug.arch.exception = DB_VECTOR;
5656 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5657 *r = EMULATE_USER_EXIT;
5658 return true;
5659 }
5660 }
5661
4161a569
NA		 5662 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5663 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5664 unsigned long eip = kvm_get_linear_rip(vcpu);
5665 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5666 vcpu->arch.dr7,
5667 vcpu->arch.db);
5668
5669 if (dr6 != 0) {
5670 vcpu->arch.dr6 &= ~15;
6f43ed01 5671 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5672 kvm_queue_exception(vcpu, DB_VECTOR);
5673 *r = EMULATE_DONE;
5674 return true;
5675 }
5676 }
5677
5678 return false;
5679}
5680
51d8b661
AP		 5681int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5682 unsigned long cr2,
dc25e89e
AP		 5683 int emulation_type,
5684 void *insn,
5685 int insn_len)
bbd9b64e 5686{
95cb2295 5687 int r;
9d74191a 5688 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5689 bool writeback = true;
93c05d3e 5690 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5691
93c05d3e
XG		 5692 /*
5693 * Clear write_fault_to_shadow_pgtable here to ensure it is
5694 * never reused.
5695 */
5696 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5697 kvm_clear_exception_queue(vcpu);
8d7d8102 5698
571008da 5699 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5700 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5701
5702 /*
5703 * We will reenter on the same instruction since
5704 * we do not set complete_userspace_io. This does not
5705 * handle watchpoints yet, those would be handled in
5706 * the emulate_ops.
5707 */
5708 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5709 return r;
5710
9d74191a
TY		 5711 ctxt->interruptibility = 0;
5712 ctxt->have_exception = false;
e0ad0b47 5713 ctxt->exception.vector = -1;
9d74191a 5714 ctxt->perm_ok = false;
bbd9b64e 5715
b51e974f 5716 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5717
9d74191a 5718 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5719
e46479f8 5720 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5721 ++vcpu->stat.insn_emulation;
1d2887e2 5722 if (r != EMULATION_OK) {
4005996e
AK		 5723 if (emulation_type & EMULTYPE_TRAP_UD)
5724 return EMULATE_FAIL;
991eebf9
GN		 5725 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5726 emulation_type))
bbd9b64e 5727 return EMULATE_DONE;
6d77dbfc
GN		 5728 if (emulation_type & EMULTYPE_SKIP)
5729 return EMULATE_FAIL;
5730 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5731 }
5732 }
5733
ba8afb6b 5734 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5735 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5736 if (ctxt->eflags & X86_EFLAGS_RF)
5737 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5738 return EMULATE_DONE;
5739 }
5740
1cb3f3ae
XG		 5741 if (retry_instruction(ctxt, cr2, emulation_type))
5742 return EMULATE_DONE;
5743
7ae441ea 5744 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5745 changes registers values during IO operation */
7ae441ea
GN		 5746 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5747 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5748 emulator_invalidate_register_cache(ctxt);
7ae441ea 5749 }
4d2179e1 5750
5cd21917 5751restart:
0f89b207
TL		 5752 /* Save the faulting GPA (cr2) in the address field */
5753 ctxt->exception.address = cr2;
5754
9d74191a 5755 r = x86_emulate_insn(ctxt);
bbd9b64e 5756
775fde86
JR		 5757 if (r == EMULATION_INTERCEPTED)
5758 return EMULATE_DONE;
5759
d2ddd1c4 5760 if (r == EMULATION_FAILED) {
991eebf9
GN		 5761 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5762 emulation_type))
c3cd7ffa
GN		 5763 return EMULATE_DONE;
5764
6d77dbfc 5765 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5766 }
5767
9d74191a 5768 if (ctxt->have_exception) {
d2ddd1c4 5769 r = EMULATE_DONE;
ef54bcfe
PB		 5770 if (inject_emulated_exception(vcpu))
5771 return r;
d2ddd1c4 5772 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5773 if (!vcpu->arch.pio.in) {
5774 /* FIXME: return into emulator if single-stepping. */
3457e419 5775 vcpu->arch.pio.count = 0;
0912c977 5776 } else {
7ae441ea 5777 writeback = false;
716d51ab
GN		 5778 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5779 }
ac0a48c3 5780 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5781 } else if (vcpu->mmio_needed) {
5782 if (!vcpu->mmio_is_write)
5783 writeback = false;
ac0a48c3 5784 r = EMULATE_USER_EXIT;
716d51ab 5785 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5786 } else if (r == EMULATION_RESTART)
5cd21917 5787 goto restart;
d2ddd1c4
GN		 5788 else
5789 r = EMULATE_DONE;
f850e2e6 5790
7ae441ea 5791 if (writeback) {
6addfc42 5792 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5793 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5794 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5795 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5796 if (r == EMULATE_DONE &&
5797 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5798 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5799 if (!ctxt->have_exception ||
5800 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5801 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5802
5803 /*
5804 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5805 * do nothing, and it will be requested again as soon as
5806 * the shadow expires. But we still need to check here,
5807 * because POPF has no interrupt shadow.
5808 */
5809 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5810 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5811 } else
5812 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5813
5814 return r;
de7d789a 5815}
51d8b661 5816EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5817
cf8f70bf 5818int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5819{
cf8f70bf 5820 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5821 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5822 size, port, &val, 1);
cf8f70bf 5823 /* do not return to emulator after return from userspace */
7972995b 5824 vcpu->arch.pio.count = 0;
de7d789a
CO		 5825 return ret;
5826}
cf8f70bf 5827EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5828
8370c3d0
TL		 5829static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5830{
5831 unsigned long val;
5832
5833 /* We should only ever be called with arch.pio.count equal to 1 */
5834 BUG_ON(vcpu->arch.pio.count != 1);
5835
5836 /* For size less than 4 we merge, else we zero extend */
5837 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5838 : 0;
5839
5840 /*
5841 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5842 * the copy and tracing
5843 */
5844 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5845 vcpu->arch.pio.port, &val, 1);
5846 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5847
5848 return 1;
5849}
5850
5851int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5852{
5853 unsigned long val;
5854 int ret;
5855
5856 /* For size less than 4 we merge, else we zero extend */
5857 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5858
5859 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5860 &val, 1);
5861 if (ret) {
5862 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5863 return ret;
5864 }
5865
5866 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5867
5868 return 0;
5869}
5870EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5871
251a5fd6 5872static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5873{
0a3aee0d 5874 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5875 return 0;
8cfdc000
ZA		 5876}
5877
5878static void tsc_khz_changed(void *data)
c8076604 5879{
8cfdc000
ZA		 5880 struct cpufreq_freqs *freq = data;
5881 unsigned long khz = 0;
5882
5883 if (data)
5884 khz = freq->new;
5885 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5886 khz = cpufreq_quick_get(raw_smp_processor_id());
5887 if (!khz)
5888 khz = tsc_khz;
0a3aee0d 5889 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5890}
5891
c8076604
GH		 5892static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5893 void *data)
5894{
5895 struct cpufreq_freqs *freq = data;
5896 struct kvm *kvm;
5897 struct kvm_vcpu *vcpu;
5898 int i, send_ipi = 0;
5899
8cfdc000
ZA		 5900 /*
5901 * We allow guests to temporarily run on slowing clocks,
5902 * provided we notify them after, or to run on accelerating
5903 * clocks, provided we notify them before. Thus time never
5904 * goes backwards.
5905 *
5906 * However, we have a problem. We can't atomically update
5907 * the frequency of a given CPU from this function; it is
5908 * merely a notifier, which can be called from any CPU.
5909 * Changing the TSC frequency at arbitrary points in time
5910 * requires a recomputation of local variables related to
5911 * the TSC for each VCPU. We must flag these local variables
5912 * to be updated and be sure the update takes place with the
5913 * new frequency before any guests proceed.
5914 *
5915 * Unfortunately, the combination of hotplug CPU and frequency
5916 * change creates an intractable locking scenario; the order
5917 * of when these callouts happen is undefined with respect to
5918 * CPU hotplug, and they can race with each other. As such,
5919 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5920 * undefined; you can actually have a CPU frequency change take
5921 * place in between the computation of X and the setting of the
5922 * variable. To protect against this problem, all updates of
5923 * the per_cpu tsc_khz variable are done in an interrupt
5924 * protected IPI, and all callers wishing to update the value
5925 * must wait for a synchronous IPI to complete (which is trivial
5926 * if the caller is on the CPU already). This establishes the
5927 * necessary total order on variable updates.
5928 *
5929 * Note that because a guest time update may take place
5930 * anytime after the setting of the VCPU's request bit, the
5931 * correct TSC value must be set before the request. However,
5932 * to ensure the update actually makes it to any guest which
5933 * starts running in hardware virtualization between the set
5934 * and the acquisition of the spinlock, we must also ping the
5935 * CPU after setting the request bit.
5936 *
5937 */
5938
c8076604
GH		 5939 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5940 return 0;
5941 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5942 return 0;
8cfdc000
ZA		 5943
5944 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5945
2f303b74 5946 spin_lock(&kvm_lock);
c8076604 5947 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5948 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5949 if (vcpu->cpu != freq->cpu)
5950 continue;
c285545f 5951 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5952 if (vcpu->cpu != smp_processor_id())
8cfdc000 5953 send_ipi = 1;
c8076604
GH		 5954 }
5955 }
2f303b74 5956 spin_unlock(&kvm_lock);
c8076604
GH		 5957
5958 if (freq->old < freq->new && send_ipi) {
5959 /*
5960 * We upscale the frequency. Must make the guest
5961 * doesn't see old kvmclock values while running with
5962 * the new frequency, otherwise we risk the guest sees
5963 * time go backwards.
5964 *
5965 * In case we update the frequency for another cpu
5966 * (which might be in guest context) send an interrupt
5967 * to kick the cpu out of guest context. Next time
5968 * guest context is entered kvmclock will be updated,
5969 * so the guest will not see stale values.
5970 */
8cfdc000 5971 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5972 }
5973 return 0;
5974}
5975
5976static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5977 .notifier_call = kvmclock_cpufreq_notifier
5978};
5979
251a5fd6 5980static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5981{
251a5fd6
SAS		 5982 tsc_khz_changed(NULL);
5983 return 0;
8cfdc000
ZA		 5984}
5985
b820cc0c
ZA		 5986static void kvm_timer_init(void)
5987{
c285545f 5988 max_tsc_khz = tsc_khz;
460dd42e 5989
b820cc0c 5990 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5991#ifdef CONFIG_CPU_FREQ
5992 struct cpufreq_policy policy;
758f588d
BP		 5993 int cpu;
5994
c285545f 5995 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5996 cpu = get_cpu();
5997 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5998 if (policy.cpuinfo.max_freq)
5999 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6000 put_cpu();
c285545f 6001#endif
b820cc0c
ZA		 6002 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6003 CPUFREQ_TRANSITION_NOTIFIER);
6004 }
c285545f 6005 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6006
73c1b41e 6007 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6008 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6009}
6010
ff9d07a0
ZY		 6011static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6012
f5132b01 6013int kvm_is_in_guest(void)
ff9d07a0 6014{
086c9855 6015 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6016}
6017
6018static int kvm_is_user_mode(void)
6019{
6020 int user_mode = 3;
dcf46b94 6021
086c9855
AS		 6022 if (__this_cpu_read(current_vcpu))
6023 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6024
ff9d07a0
ZY		 6025 return user_mode != 0;
6026}
6027
6028static unsigned long kvm_get_guest_ip(void)
6029{
6030 unsigned long ip = 0;
dcf46b94 6031
086c9855
AS		 6032 if (__this_cpu_read(current_vcpu))
6033 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6034
ff9d07a0
ZY		 6035 return ip;
6036}
6037
6038static struct perf_guest_info_callbacks kvm_guest_cbs = {
6039 .is_in_guest = kvm_is_in_guest,
6040 .is_user_mode = kvm_is_user_mode,
6041 .get_guest_ip = kvm_get_guest_ip,
6042};
6043
6044void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6045{
086c9855 6046 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6047}
6048EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6049
6050void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6051{
086c9855 6052 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6053}
6054EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6055
ce88decf
XG		 6056static void kvm_set_mmio_spte_mask(void)
6057{
6058 u64 mask;
6059 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6060
6061 /*
6062 * Set the reserved bits and the present bit of an paging-structure
6063 * entry to generate page fault with PFER.RSV = 1.
6064 */
885032b9 6065 /* Mask the reserved physical address bits. */
d1431483 6066 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6067
885032b9 6068 /* Set the present bit. */
ce88decf
XG		 6069 mask |= 1ull;
6070
6071#ifdef CONFIG_X86_64
6072 /*
6073 * If reserved bit is not supported, clear the present bit to disable
6074 * mmio page fault.
6075 */
6076 if (maxphyaddr == 52)
6077 mask &= ~1ull;
6078#endif
6079
dcdca5fe 6080 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6081}
6082
16e8d74d
MT		 6083#ifdef CONFIG_X86_64
6084static void pvclock_gtod_update_fn(struct work_struct *work)
6085{
d828199e
MT		 6086 struct kvm *kvm;
6087
6088 struct kvm_vcpu *vcpu;
6089 int i;
6090
2f303b74 6091 spin_lock(&kvm_lock);
d828199e
MT		 6092 list_for_each_entry(kvm, &vm_list, vm_list)
6093 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6094 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6095 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6096 spin_unlock(&kvm_lock);
16e8d74d
MT		 6097}
6098
6099static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6100
6101/*
6102 * Notification about pvclock gtod data update.
6103 */
6104static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6105 void *priv)
6106{
6107 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6108 struct timekeeper *tk = priv;
6109
6110 update_pvclock_gtod(tk);
6111
6112 /* disable master clock if host does not trust, or does not
6113 * use, TSC clocksource
6114 */
6115 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6116 atomic_read(&kvm_guest_has_master_clock) != 0)
6117 queue_work(system_long_wq, &pvclock_gtod_work);
6118
6119 return 0;
6120}
6121
6122static struct notifier_block pvclock_gtod_notifier = {
6123 .notifier_call = pvclock_gtod_notify,
6124};
6125#endif
6126
f8c16bba 6127int kvm_arch_init(void *opaque)
043405e1 6128{
b820cc0c 6129 int r;
6b61edf7 6130 struct kvm_x86_ops *ops = opaque;
f8c16bba 6131
f8c16bba
ZX		 6132 if (kvm_x86_ops) {
6133 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6134 r = -EEXIST;
6135 goto out;
f8c16bba
ZX		 6136 }
6137
6138 if (!ops->cpu_has_kvm_support()) {
6139 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6140 r = -EOPNOTSUPP;
6141 goto out;
f8c16bba
ZX		 6142 }
6143 if (ops->disabled_by_bios()) {
6144 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6145 r = -EOPNOTSUPP;
6146 goto out;
f8c16bba
ZX		 6147 }
6148
013f6a5d
MT		 6149 r = -ENOMEM;
6150 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6151 if (!shared_msrs) {
6152 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6153 goto out;
6154 }
6155
97db56ce
AK		 6156 r = kvm_mmu_module_init();
6157 if (r)
013f6a5d 6158 goto out_free_percpu;
97db56ce 6159
ce88decf 6160 kvm_set_mmio_spte_mask();
97db56ce 6161
f8c16bba 6162 kvm_x86_ops = ops;
920c8377 6163
7b52345e 6164 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6165 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6166 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6167 kvm_timer_init();
c8076604 6168
ff9d07a0
ZY		 6169 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6170
d366bf7e 6171 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6172 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6173
c5cc421b 6174 kvm_lapic_init();
16e8d74d
MT		 6175#ifdef CONFIG_X86_64
6176 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6177#endif
6178
f8c16bba 6179 return 0;
56c6d28a 6180
013f6a5d
MT		 6181out_free_percpu:
6182 free_percpu(shared_msrs);
56c6d28a 6183out:
56c6d28a 6184 return r;
043405e1 6185}
8776e519 6186
f8c16bba
ZX		 6187void kvm_arch_exit(void)
6188{
cef84c30 6189 kvm_lapic_exit();
ff9d07a0
ZY		 6190 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6191
888d256e
JK		 6192 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6193 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6194 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6195 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6196#ifdef CONFIG_X86_64
6197 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6198#endif
f8c16bba 6199 kvm_x86_ops = NULL;
56c6d28a 6200 kvm_mmu_module_exit();
013f6a5d 6201 free_percpu(shared_msrs);
56c6d28a 6202}
f8c16bba 6203
5cb56059 6204int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6205{
6206 ++vcpu->stat.halt_exits;
35754c98 6207 if (lapic_in_kernel(vcpu)) {
a4535290 6208 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6209 return 1;
6210 } else {
6211 vcpu->run->exit_reason = KVM_EXIT_HLT;
6212 return 0;
6213 }
6214}
5cb56059
JS		 6215EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6216
6217int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6218{
6affcbed
KH		 6219 int ret = kvm_skip_emulated_instruction(vcpu);
6220 /*
6221 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6222 * KVM_EXIT_DEBUG here.
6223 */
6224 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6225}
8776e519
HB		 6226EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6227
8ef81a9a 6228#ifdef CONFIG_X86_64
55dd00a7
MT		 6229static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6230 unsigned long clock_type)
6231{
6232 struct kvm_clock_pairing clock_pairing;
6233 struct timespec ts;
80fbd89c 6234 u64 cycle;
55dd00a7
MT		 6235 int ret;
6236
6237 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6238 return -KVM_EOPNOTSUPP;
6239
6240 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6241 return -KVM_EOPNOTSUPP;
6242
6243 clock_pairing.sec = ts.tv_sec;
6244 clock_pairing.nsec = ts.tv_nsec;
6245 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6246 clock_pairing.flags = 0;
6247
6248 ret = 0;
6249 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6250 sizeof(struct kvm_clock_pairing)))
6251 ret = -KVM_EFAULT;
6252
6253 return ret;
6254}
8ef81a9a 6255#endif
55dd00a7 6256
6aef266c
SV		 6257/*
6258 * kvm_pv_kick_cpu_op: Kick a vcpu.
6259 *
6260 * @apicid - apicid of vcpu to be kicked.
6261 */
6262static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6263{
24d2166b 6264 struct kvm_lapic_irq lapic_irq;
6aef266c 6265
24d2166b
R		 6266 lapic_irq.shorthand = 0;
6267 lapic_irq.dest_mode = 0;
ebd28fcb 6268 lapic_irq.level = 0;
24d2166b 6269 lapic_irq.dest_id = apicid;
93bbf0b8 6270 lapic_irq.msi_redir_hint = false;
6aef266c 6271
24d2166b 6272 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6273 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6274}
6275
d62caabb
AS		 6276void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6277{
6278 vcpu->arch.apicv_active = false;
6279 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6280}
6281
8776e519
HB		 6282int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6283{
6284 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6285 int op_64_bit, r;
8776e519 6286
6affcbed 6287 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6288
55cd8e5a
GN		 6289 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6290 return kvm_hv_hypercall(vcpu);
6291
5fdbf976
MT		 6292 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6293 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6294 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6295 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6296 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6297
229456fc 6298 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6299
a449c7aa
NA		 6300 op_64_bit = is_64_bit_mode(vcpu);
6301 if (!op_64_bit) {
8776e519
HB		 6302 nr &= 0xFFFFFFFF;
6303 a0 &= 0xFFFFFFFF;
6304 a1 &= 0xFFFFFFFF;
6305 a2 &= 0xFFFFFFFF;
6306 a3 &= 0xFFFFFFFF;
6307 }
6308
07708c4a
JK		 6309 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6310 ret = -KVM_EPERM;
6311 goto out;
6312 }
6313
8776e519 6314 switch (nr) {
b93463aa
AK		 6315 case KVM_HC_VAPIC_POLL_IRQ:
6316 ret = 0;
6317 break;
6aef266c
SV		 6318 case KVM_HC_KICK_CPU:
6319 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6320 ret = 0;
6321 break;
8ef81a9a 6322#ifdef CONFIG_X86_64
55dd00a7
MT		 6323 case KVM_HC_CLOCK_PAIRING:
6324 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6325 break;
8ef81a9a 6326#endif
8776e519
HB		 6327 default:
6328 ret = -KVM_ENOSYS;
6329 break;
6330 }
07708c4a 6331out:
a449c7aa
NA		 6332 if (!op_64_bit)
6333 ret = (u32)ret;
5fdbf976 6334 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6335 ++vcpu->stat.hypercalls;
2f333bcb 6336 return r;
8776e519
HB		 6337}
6338EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6339
b6785def 6340static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6341{
d6aa1000 6342 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6343 char instruction[3];
5fdbf976 6344 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6345
8776e519 6346 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6347
ce2e852e
DV		 6348 return emulator_write_emulated(ctxt, rip, instruction, 3,
6349 &ctxt->exception);
8776e519
HB		 6350}
6351
851ba692 6352static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6353{
782d422b
MG		 6354 return vcpu->run->request_interrupt_window &&
6355 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6356}
6357
851ba692 6358static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6359{
851ba692
AK		 6360 struct kvm_run *kvm_run = vcpu->run;
6361
91586a3b 6362 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6363 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6364 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6365 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6366 kvm_run->ready_for_interrupt_injection =
6367 pic_in_kernel(vcpu->kvm) ||
782d422b 6368 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6369}
6370
95ba8273
GN		 6371static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6372{
6373 int max_irr, tpr;
6374
6375 if (!kvm_x86_ops->update_cr8_intercept)
6376 return;
6377
bce87cce 6378 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6379 return;
6380
d62caabb
AS		 6381 if (vcpu->arch.apicv_active)
6382 return;
6383
8db3baa2
GN		 6384 if (!vcpu->arch.apic->vapic_addr)
6385 max_irr = kvm_lapic_find_highest_irr(vcpu);
6386 else
6387 max_irr = -1;
95ba8273
GN		 6388
6389 if (max_irr != -1)
6390 max_irr >>= 4;
6391
6392 tpr = kvm_lapic_get_cr8(vcpu);
6393
6394 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6395}
6396
b6b8a145 6397static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6398{
b6b8a145
JK		 6399 int r;
6400
95ba8273 6401 /* try to reinject previous events if any */
664f8e26
WL		 6402 if (vcpu->arch.exception.injected) {
6403 kvm_x86_ops->queue_exception(vcpu);
6404 return 0;
6405 }
6406
6407 /*
6408 * Exceptions must be injected immediately, or the exception
6409 * frame will have the address of the NMI or interrupt handler.
6410 */
6411 if (!vcpu->arch.exception.pending) {
6412 if (vcpu->arch.nmi_injected) {
6413 kvm_x86_ops->set_nmi(vcpu);
6414 return 0;
6415 }
6416
6417 if (vcpu->arch.interrupt.pending) {
6418 kvm_x86_ops->set_irq(vcpu);
6419 return 0;
6420 }
6421 }
6422
6423 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6424 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6425 if (r != 0)
6426 return r;
6427 }
6428
6429 /* try to inject new event if pending */
b59bb7bd 6430 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6431 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6432 vcpu->arch.exception.has_error_code,
6433 vcpu->arch.exception.error_code);
d6e8c854 6434
664f8e26
WL		 6435 vcpu->arch.exception.pending = false;
6436 vcpu->arch.exception.injected = true;
6437
d6e8c854
NA		 6438 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6439 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6440 X86_EFLAGS_RF);
6441
6bdf0662
NA		 6442 if (vcpu->arch.exception.nr == DB_VECTOR &&
6443 (vcpu->arch.dr7 & DR7_GD)) {
6444 vcpu->arch.dr7 &= ~DR7_GD;
6445 kvm_update_dr7(vcpu);
6446 }
6447
cfcd20e5 6448 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6449 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6450 vcpu->arch.smi_pending = false;
ee2cd4b7 6451 enter_smm(vcpu);
c43203ca 6452 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6453 --vcpu->arch.nmi_pending;
6454 vcpu->arch.nmi_injected = true;
6455 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6456 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6457 /*
6458 * Because interrupts can be injected asynchronously, we are
6459 * calling check_nested_events again here to avoid a race condition.
6460 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6461 * proposal and current concerns. Perhaps we should be setting
6462 * KVM_REQ_EVENT only on certain events and not unconditionally?
6463 */
6464 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6465 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6466 if (r != 0)
6467 return r;
6468 }
95ba8273 6469 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6470 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6471 false);
6472 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6473 }
6474 }
ee2cd4b7 6475
b6b8a145 6476 return 0;
95ba8273
GN		 6477}
6478
7460fb4a
AK		 6479static void process_nmi(struct kvm_vcpu *vcpu)
6480{
6481 unsigned limit = 2;
6482
6483 /*
6484 * x86 is limited to one NMI running, and one NMI pending after it.
6485 * If an NMI is already in progress, limit further NMIs to just one.
6486 * Otherwise, allow two (and we'll inject the first one immediately).
6487 */
6488 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6489 limit = 1;
6490
6491 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6492 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6493 kvm_make_request(KVM_REQ_EVENT, vcpu);
6494}
6495
ee2cd4b7 6496static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6497{
6498 u32 flags = 0;
6499 flags |= seg->g << 23;
6500 flags |= seg->db << 22;
6501 flags |= seg->l << 21;
6502 flags |= seg->avl << 20;
6503 flags |= seg->present << 15;
6504 flags |= seg->dpl << 13;
6505 flags |= seg->s << 12;
6506 flags |= seg->type << 8;
6507 return flags;
6508}
6509
ee2cd4b7 6510static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6511{
6512 struct kvm_segment seg;
6513 int offset;
6514
6515 kvm_get_segment(vcpu, &seg, n);
6516 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6517
6518 if (n < 3)
6519 offset = 0x7f84 + n * 12;
6520 else
6521 offset = 0x7f2c + (n - 3) * 12;
6522
6523 put_smstate(u32, buf, offset + 8, seg.base);
6524 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6525 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6526}
6527
efbb288a 6528#ifdef CONFIG_X86_64
ee2cd4b7 6529static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6530{
6531 struct kvm_segment seg;
6532 int offset;
6533 u16 flags;
6534
6535 kvm_get_segment(vcpu, &seg, n);
6536 offset = 0x7e00 + n * 16;
6537
ee2cd4b7 6538 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6539 put_smstate(u16, buf, offset, seg.selector);
6540 put_smstate(u16, buf, offset + 2, flags);
6541 put_smstate(u32, buf, offset + 4, seg.limit);
6542 put_smstate(u64, buf, offset + 8, seg.base);
6543}
efbb288a 6544#endif
660a5d51 6545
ee2cd4b7 6546static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6547{
6548 struct desc_ptr dt;
6549 struct kvm_segment seg;
6550 unsigned long val;
6551 int i;
6552
6553 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6554 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6555 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6556 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6557
6558 for (i = 0; i < 8; i++)
6559 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6560
6561 kvm_get_dr(vcpu, 6, &val);
6562 put_smstate(u32, buf, 0x7fcc, (u32)val);
6563 kvm_get_dr(vcpu, 7, &val);
6564 put_smstate(u32, buf, 0x7fc8, (u32)val);
6565
6566 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6567 put_smstate(u32, buf, 0x7fc4, seg.selector);
6568 put_smstate(u32, buf, 0x7f64, seg.base);
6569 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6570 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6571
6572 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6573 put_smstate(u32, buf, 0x7fc0, seg.selector);
6574 put_smstate(u32, buf, 0x7f80, seg.base);
6575 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6576 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6577
6578 kvm_x86_ops->get_gdt(vcpu, &dt);
6579 put_smstate(u32, buf, 0x7f74, dt.address);
6580 put_smstate(u32, buf, 0x7f70, dt.size);
6581
6582 kvm_x86_ops->get_idt(vcpu, &dt);
6583 put_smstate(u32, buf, 0x7f58, dt.address);
6584 put_smstate(u32, buf, 0x7f54, dt.size);
6585
6586 for (i = 0; i < 6; i++)
ee2cd4b7 6587 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6588
6589 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6590
6591 /* revision id */
6592 put_smstate(u32, buf, 0x7efc, 0x00020000);
6593 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6594}
6595
ee2cd4b7 6596static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6597{
6598#ifdef CONFIG_X86_64
6599 struct desc_ptr dt;
6600 struct kvm_segment seg;
6601 unsigned long val;
6602 int i;
6603
6604 for (i = 0; i < 16; i++)
6605 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6606
6607 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6608 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6609
6610 kvm_get_dr(vcpu, 6, &val);
6611 put_smstate(u64, buf, 0x7f68, val);
6612 kvm_get_dr(vcpu, 7, &val);
6613 put_smstate(u64, buf, 0x7f60, val);
6614
6615 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6616 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6617 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6618
6619 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6620
6621 /* revision id */
6622 put_smstate(u32, buf, 0x7efc, 0x00020064);
6623
6624 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6625
6626 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6627 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6628 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6629 put_smstate(u32, buf, 0x7e94, seg.limit);
6630 put_smstate(u64, buf, 0x7e98, seg.base);
6631
6632 kvm_x86_ops->get_idt(vcpu, &dt);
6633 put_smstate(u32, buf, 0x7e84, dt.size);
6634 put_smstate(u64, buf, 0x7e88, dt.address);
6635
6636 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6637 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6638 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6639 put_smstate(u32, buf, 0x7e74, seg.limit);
6640 put_smstate(u64, buf, 0x7e78, seg.base);
6641
6642 kvm_x86_ops->get_gdt(vcpu, &dt);
6643 put_smstate(u32, buf, 0x7e64, dt.size);
6644 put_smstate(u64, buf, 0x7e68, dt.address);
6645
6646 for (i = 0; i < 6; i++)
ee2cd4b7 6647 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6648#else
6649 WARN_ON_ONCE(1);
6650#endif
6651}
6652
ee2cd4b7 6653static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6654{
660a5d51 6655 struct kvm_segment cs, ds;
18c3626e 6656 struct desc_ptr dt;
660a5d51
PB		 6657 char buf[512];
6658 u32 cr0;
6659
660a5d51 6660 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6661 memset(buf, 0, 512);
d6321d49 6662 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6663 enter_smm_save_state_64(vcpu, buf);
660a5d51 6664 else
ee2cd4b7 6665 enter_smm_save_state_32(vcpu, buf);
660a5d51 6666
0234bf88
LP		 6667 /*
6668 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6669 * vCPU state (e.g. leave guest mode) after we've saved the state into
6670 * the SMM state-save area.
6671 */
6672 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6673
6674 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6675 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6676
6677 if (kvm_x86_ops->get_nmi_mask(vcpu))
6678 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6679 else
6680 kvm_x86_ops->set_nmi_mask(vcpu, true);
6681
6682 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6683 kvm_rip_write(vcpu, 0x8000);
6684
6685 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6686 kvm_x86_ops->set_cr0(vcpu, cr0);
6687 vcpu->arch.cr0 = cr0;
6688
6689 kvm_x86_ops->set_cr4(vcpu, 0);
6690
18c3626e
PB		 6691 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6692 dt.address = dt.size = 0;
6693 kvm_x86_ops->set_idt(vcpu, &dt);
6694
660a5d51
PB		 6695 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6696
6697 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6698 cs.base = vcpu->arch.smbase;
6699
6700 ds.selector = 0;
6701 ds.base = 0;
6702
6703 cs.limit = ds.limit = 0xffffffff;
6704 cs.type = ds.type = 0x3;
6705 cs.dpl = ds.dpl = 0;
6706 cs.db = ds.db = 0;
6707 cs.s = ds.s = 1;
6708 cs.l = ds.l = 0;
6709 cs.g = ds.g = 1;
6710 cs.avl = ds.avl = 0;
6711 cs.present = ds.present = 1;
6712 cs.unusable = ds.unusable = 0;
6713 cs.padding = ds.padding = 0;
6714
6715 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6716 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6717 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6718 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6719 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6720 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6721
d6321d49 6722 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6723 kvm_x86_ops->set_efer(vcpu, 0);
6724
6725 kvm_update_cpuid(vcpu);
6726 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6727}
6728
ee2cd4b7 6729static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6730{
6731 vcpu->arch.smi_pending = true;
6732 kvm_make_request(KVM_REQ_EVENT, vcpu);
6733}
6734
2860c4b1
PB		 6735void kvm_make_scan_ioapic_request(struct kvm *kvm)
6736{
6737 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6738}
6739
3d81bc7e 6740static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6741{
5c919412
AS		 6742 u64 eoi_exit_bitmap[4];
6743
3d81bc7e
YZ		 6744 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6745 return;
c7c9c56c 6746
6308630b 6747 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6748
b053b2ae 6749 if (irqchip_split(vcpu->kvm))
6308630b 6750 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6751 else {
76dfafd5 6752 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6753 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6754 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6755 }
5c919412
AS		 6756 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6757 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6758 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6759}
6760
a70656b6
RK		 6761static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6762{
6763 ++vcpu->stat.tlb_flush;
6764 kvm_x86_ops->tlb_flush(vcpu);
6765}
6766
4256f43f
TC		 6767void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6768{
c24ae0dc
TC		 6769 struct page *page = NULL;
6770
35754c98 6771 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6772 return;
6773
4256f43f
TC		 6774 if (!kvm_x86_ops->set_apic_access_page_addr)
6775 return;
6776
c24ae0dc 6777 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6778 if (is_error_page(page))
6779 return;
c24ae0dc
TC		 6780 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6781
6782 /*
6783 * Do not pin apic access page in memory, the MMU notifier
6784 * will call us again if it is migrated or swapped out.
6785 */
6786 put_page(page);
4256f43f
TC		 6787}
6788EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6789
9357d939 6790/*
362c698f 6791 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6792 * exiting to the userspace. Otherwise, the value will be returned to the
6793 * userspace.
6794 */
851ba692 6795static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6796{
6797 int r;
62a193ed
MG		 6798 bool req_int_win =
6799 dm_request_for_irq_injection(vcpu) &&
6800 kvm_cpu_accept_dm_intr(vcpu);
6801
730dca42 6802 bool req_immediate_exit = false;
b6c7a5dc 6803
2fa6e1e1 6804 if (kvm_request_pending(vcpu)) {
a8eeb04a 6805 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6806 kvm_mmu_unload(vcpu);
a8eeb04a 6807 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6808 __kvm_migrate_timers(vcpu);
d828199e
MT		 6809 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6810 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6811 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6812 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6813 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6814 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6815 if (unlikely(r))
6816 goto out;
6817 }
a8eeb04a 6818 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6819 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6820 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6821 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6822 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6823 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6824 r = 0;
6825 goto out;
6826 }
a8eeb04a 6827 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6828 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6829 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6830 r = 0;
6831 goto out;
6832 }
af585b92
GN		 6833 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6834 /* Page is swapped out. Do synthetic halt */
6835 vcpu->arch.apf.halted = true;
6836 r = 1;
6837 goto out;
6838 }
c9aaa895
GC		 6839 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6840 record_steal_time(vcpu);
64d60670
PB		 6841 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6842 process_smi(vcpu);
7460fb4a
AK		 6843 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6844 process_nmi(vcpu);
f5132b01 6845 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6846 kvm_pmu_handle_event(vcpu);
f5132b01 6847 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6848 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6849 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6850 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6851 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6852 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6853 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6854 vcpu->run->eoi.vector =
6855 vcpu->arch.pending_ioapic_eoi;
6856 r = 0;
6857 goto out;
6858 }
6859 }
3d81bc7e
YZ		 6860 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6861 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6862 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6863 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6864 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6865 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6866 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6867 r = 0;
6868 goto out;
6869 }
e516cebb
AS		 6870 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6871 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6872 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6873 r = 0;
6874 goto out;
6875 }
db397571
AS		 6876 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6877 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6878 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6879 r = 0;
6880 goto out;
6881 }
f3b138c5
AS		 6882
6883 /*
6884 * KVM_REQ_HV_STIMER has to be processed after
6885 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6886 * depend on the guest clock being up-to-date
6887 */
1f4b34f8
AS		 6888 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6889 kvm_hv_process_stimers(vcpu);
2f52d58c 6890 }
b93463aa 6891
b463a6f7 6892 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6893 ++vcpu->stat.req_event;
66450a21
JK		 6894 kvm_apic_accept_events(vcpu);
6895 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6896 r = 1;
6897 goto out;
6898 }
6899
b6b8a145
JK		 6900 if (inject_pending_event(vcpu, req_int_win) != 0)
6901 req_immediate_exit = true;
321c5658 6902 else {
cc3d967f 6903 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 6904 *
cc3d967f
LP		 6905 * SMIs have three cases:
6906 * 1) They can be nested, and then there is nothing to
6907 * do here because RSM will cause a vmexit anyway.
6908 * 2) There is an ISA-specific reason why SMI cannot be
6909 * injected, and the moment when this changes can be
6910 * intercepted.
6911 * 3) Or the SMI can be pending because
6912 * inject_pending_event has completed the injection
6913 * of an IRQ or NMI from the previous vmexit, and
6914 * then we request an immediate exit to inject the
6915 * SMI.
c43203ca
PB		 6916 */
6917 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 6918 if (!kvm_x86_ops->enable_smi_window(vcpu))
6919 req_immediate_exit = true;
321c5658
YS		 6920 if (vcpu->arch.nmi_pending)
6921 kvm_x86_ops->enable_nmi_window(vcpu);
6922 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6923 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6924 WARN_ON(vcpu->arch.exception.pending);
321c5658 6925 }
b463a6f7
AK		 6926
6927 if (kvm_lapic_enabled(vcpu)) {
6928 update_cr8_intercept(vcpu);
6929 kvm_lapic_sync_to_vapic(vcpu);
6930 }
6931 }
6932
d8368af8
AK		 6933 r = kvm_mmu_reload(vcpu);
6934 if (unlikely(r)) {
d905c069 6935 goto cancel_injection;
d8368af8
AK		 6936 }
6937
b6c7a5dc
HB		 6938 preempt_disable();
6939
6940 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6941 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6942
6943 /*
6944 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6945 * IPI are then delayed after guest entry, which ensures that they
6946 * result in virtual interrupt delivery.
6947 */
6948 local_irq_disable();
6b7e2d09
XG		 6949 vcpu->mode = IN_GUEST_MODE;
6950
01b71917
MT		 6951 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6952
0f127d12 6953 /*
b95234c8 6954 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6955 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6956 *
6957 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6958 * pairs with the memory barrier implicit in pi_test_and_set_on
6959 * (see vmx_deliver_posted_interrupt).
6960 *
6961 * 3) This also orders the write to mode from any reads to the page
6962 * tables done while the VCPU is running. Please see the comment
6963 * in kvm_flush_remote_tlbs.
6b7e2d09 6964 */
01b71917 6965 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6966
b95234c8
PB		 6967 /*
6968 * This handles the case where a posted interrupt was
6969 * notified with kvm_vcpu_kick.
6970 */
6971 if (kvm_lapic_enabled(vcpu)) {
6972 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6973 kvm_x86_ops->sync_pir_to_irr(vcpu);
6974 }
32f88400 6975
2fa6e1e1 6976 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 6977 || need_resched() || signal_pending(current)) {
6b7e2d09 6978 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6979 smp_wmb();
6c142801
AK		 6980 local_irq_enable();
6981 preempt_enable();
01b71917 6982 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6983 r = 1;
d905c069 6984 goto cancel_injection;
6c142801
AK		 6985 }
6986
fc5b7f3b
DM		 6987 kvm_load_guest_xcr0(vcpu);
6988
c43203ca
PB		 6989 if (req_immediate_exit) {
6990 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6991 smp_send_reschedule(vcpu->cpu);
c43203ca 6992 }
d6185f20 6993
8b89fe1f
PB		 6994 trace_kvm_entry(vcpu->vcpu_id);
6995 wait_lapic_expire(vcpu);
6edaa530 6996 guest_enter_irqoff();
b6c7a5dc 6997
42dbaa5a 6998 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6999 set_debugreg(0, 7);
7000 set_debugreg(vcpu->arch.eff_db[0], 0);
7001 set_debugreg(vcpu->arch.eff_db[1], 1);
7002 set_debugreg(vcpu->arch.eff_db[2], 2);
7003 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7004 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7005 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7006 }
b6c7a5dc 7007
851ba692 7008 kvm_x86_ops->run(vcpu);
b6c7a5dc 7009
c77fb5fe
PB		 7010 /*
7011 * Do this here before restoring debug registers on the host. And
7012 * since we do this before handling the vmexit, a DR access vmexit
7013 * can (a) read the correct value of the debug registers, (b) set
7014 * KVM_DEBUGREG_WONT_EXIT again.
7015 */
7016 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7017 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7018 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7019 kvm_update_dr0123(vcpu);
7020 kvm_update_dr6(vcpu);
7021 kvm_update_dr7(vcpu);
7022 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7023 }
7024
24f1e32c
FW		 7025 /*
7026 * If the guest has used debug registers, at least dr7
7027 * will be disabled while returning to the host.
7028 * If we don't have active breakpoints in the host, we don't
7029 * care about the messed up debug address registers. But if
7030 * we have some of them active, restore the old state.
7031 */
59d8eb53 7032 if (hw_breakpoint_active())
24f1e32c 7033 hw_breakpoint_restore();
42dbaa5a 7034
4ba76538 7035 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7036
6b7e2d09 7037 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7038 smp_wmb();
a547c6db 7039
fc5b7f3b
DM		 7040 kvm_put_guest_xcr0(vcpu);
7041
a547c6db 7042 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7043
7044 ++vcpu->stat.exits;
7045
f2485b3e 7046 guest_exit_irqoff();
b6c7a5dc 7047
f2485b3e 7048 local_irq_enable();
b6c7a5dc
HB		 7049 preempt_enable();
7050
f656ce01 7051 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7052
b6c7a5dc
HB		 7053 /*
7054 * Profile KVM exit RIPs:
7055 */
7056 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7057 unsigned long rip = kvm_rip_read(vcpu);
7058 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7059 }
7060
cc578287
ZA		 7061 if (unlikely(vcpu->arch.tsc_always_catchup))
7062 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7063
5cfb1d5a
MT		 7064 if (vcpu->arch.apic_attention)
7065 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7066
618232e2 7067 vcpu->arch.gpa_available = false;
851ba692 7068 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7069 return r;
7070
7071cancel_injection:
7072 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7073 if (unlikely(vcpu->arch.apic_attention))
7074 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7075out:
7076 return r;
7077}
b6c7a5dc 7078
362c698f
PB		 7079static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7080{
bf9f6ac8
FW		 7081 if (!kvm_arch_vcpu_runnable(vcpu) &&
7082 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7083 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7084 kvm_vcpu_block(vcpu);
7085 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7086
7087 if (kvm_x86_ops->post_block)
7088 kvm_x86_ops->post_block(vcpu);
7089
9c8fd1ba
PB		 7090 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7091 return 1;
7092 }
362c698f
PB		 7093
7094 kvm_apic_accept_events(vcpu);
7095 switch(vcpu->arch.mp_state) {
7096 case KVM_MP_STATE_HALTED:
7097 vcpu->arch.pv.pv_unhalted = false;
7098 vcpu->arch.mp_state =
7099 KVM_MP_STATE_RUNNABLE;
7100 case KVM_MP_STATE_RUNNABLE:
7101 vcpu->arch.apf.halted = false;
7102 break;
7103 case KVM_MP_STATE_INIT_RECEIVED:
7104 break;
7105 default:
7106 return -EINTR;
7107 break;
7108 }
7109 return 1;
7110}
09cec754 7111
5d9bc648
PB		 7112static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7113{
0ad3bed6
PB		 7114 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7115 kvm_x86_ops->check_nested_events(vcpu, false);
7116
5d9bc648
PB		 7117 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7118 !vcpu->arch.apf.halted);
7119}
7120
362c698f 7121static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7122{
7123 int r;
f656ce01 7124 struct kvm *kvm = vcpu->kvm;
d7690175 7125
f656ce01 7126 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7127
362c698f 7128 for (;;) {
58f800d5 7129 if (kvm_vcpu_running(vcpu)) {
851ba692 7130 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7131 } else {
362c698f 7132 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7133 }
7134
09cec754
GN		 7135 if (r <= 0)
7136 break;
7137
72875d8a 7138 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7139 if (kvm_cpu_has_pending_timer(vcpu))
7140 kvm_inject_pending_timer_irqs(vcpu);
7141
782d422b
MG		 7142 if (dm_request_for_irq_injection(vcpu) &&
7143 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7144 r = 0;
7145 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7146 ++vcpu->stat.request_irq_exits;
362c698f 7147 break;
09cec754 7148 }
af585b92
GN		 7149
7150 kvm_check_async_pf_completion(vcpu);
7151
09cec754
GN		 7152 if (signal_pending(current)) {
7153 r = -EINTR;
851ba692 7154 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7155 ++vcpu->stat.signal_exits;
362c698f 7156 break;
09cec754
GN		 7157 }
7158 if (need_resched()) {
f656ce01 7159 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7160 cond_resched();
f656ce01 7161 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7162 }
b6c7a5dc
HB		 7163 }
7164
f656ce01 7165 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7166
7167 return r;
7168}
7169
716d51ab
GN		 7170static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7171{
7172 int r;
7173 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7174 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7175 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7176 if (r != EMULATE_DONE)
7177 return 0;
7178 return 1;
7179}
7180
7181static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7182{
7183 BUG_ON(!vcpu->arch.pio.count);
7184
7185 return complete_emulated_io(vcpu);
7186}
7187
f78146b0
AK		 7188/*
7189 * Implements the following, as a state machine:
7190 *
7191 * read:
7192 * for each fragment
87da7e66
XG		 7193 * for each mmio piece in the fragment
7194 * write gpa, len
7195 * exit
7196 * copy data
f78146b0
AK		 7197 * execute insn
7198 *
7199 * write:
7200 * for each fragment
87da7e66
XG		 7201 * for each mmio piece in the fragment
7202 * write gpa, len
7203 * copy data
7204 * exit
f78146b0 7205 */
716d51ab 7206static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7207{
7208 struct kvm_run *run = vcpu->run;
f78146b0 7209 struct kvm_mmio_fragment *frag;
87da7e66 7210 unsigned len;
5287f194 7211
716d51ab 7212 BUG_ON(!vcpu->mmio_needed);
5287f194 7213
716d51ab 7214 /* Complete previous fragment */
87da7e66
XG		 7215 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7216 len = min(8u, frag->len);
716d51ab 7217 if (!vcpu->mmio_is_write)
87da7e66
XG		 7218 memcpy(frag->data, run->mmio.data, len);
7219
7220 if (frag->len <= 8) {
7221 /* Switch to the next fragment. */
7222 frag++;
7223 vcpu->mmio_cur_fragment++;
7224 } else {
7225 /* Go forward to the next mmio piece. */
7226 frag->data += len;
7227 frag->gpa += len;
7228 frag->len -= len;
7229 }
7230
a08d3b3b 7231 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7232 vcpu->mmio_needed = 0;
0912c977
PB		 7233
7234 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7235 if (vcpu->mmio_is_write)
716d51ab
GN		 7236 return 1;
7237 vcpu->mmio_read_completed = 1;
7238 return complete_emulated_io(vcpu);
7239 }
87da7e66 7240
716d51ab
GN		 7241 run->exit_reason = KVM_EXIT_MMIO;
7242 run->mmio.phys_addr = frag->gpa;
7243 if (vcpu->mmio_is_write)
87da7e66
XG		 7244 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7245 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7246 run->mmio.is_write = vcpu->mmio_is_write;
7247 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7248 return 0;
5287f194
AK		 7249}
7250
716d51ab 7251
b6c7a5dc
HB		 7252int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7253{
c5bedc68 7254 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7255 int r;
7256 sigset_t sigsaved;
7257
2ce03d85 7258 fpu__initialize(fpu);
e5c30142 7259
ac9f6dc0
AK		 7260 if (vcpu->sigset_active)
7261 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7262
a4535290 7263 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7264 if (kvm_run->immediate_exit) {
7265 r = -EINTR;
7266 goto out;
7267 }
b6c7a5dc 7268 kvm_vcpu_block(vcpu);
66450a21 7269 kvm_apic_accept_events(vcpu);
72875d8a 7270 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7271 r = -EAGAIN;
a0595000
JS		 7272 if (signal_pending(current)) {
7273 r = -EINTR;
7274 vcpu->run->exit_reason = KVM_EXIT_INTR;
7275 ++vcpu->stat.signal_exits;
7276 }
ac9f6dc0 7277 goto out;
b6c7a5dc
HB		 7278 }
7279
b6c7a5dc 7280 /* re-sync apic's tpr */
35754c98 7281 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7282 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7283 r = -EINVAL;
7284 goto out;
7285 }
7286 }
b6c7a5dc 7287
716d51ab
GN		 7288 if (unlikely(vcpu->arch.complete_userspace_io)) {
7289 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7290 vcpu->arch.complete_userspace_io = NULL;
7291 r = cui(vcpu);
7292 if (r <= 0)
7293 goto out;
7294 } else
7295 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7296
460df4c1
PB		 7297 if (kvm_run->immediate_exit)
7298 r = -EINTR;
7299 else
7300 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7301
7302out:
f1d86e46 7303 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7304 if (vcpu->sigset_active)
7305 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7306
b6c7a5dc
HB		 7307 return r;
7308}
7309
7310int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7311{
7ae441ea
GN		 7312 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7313 /*
7314 * We are here if userspace calls get_regs() in the middle of
7315 * instruction emulation. Registers state needs to be copied
4a969980 7316 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7317 * that usually, but some bad designed PV devices (vmware
7318 * backdoor interface) need this to work
7319 */
dd856efa 7320 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7321 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7322 }
5fdbf976
MT		 7323 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7324 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7325 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7326 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7327 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7328 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7329 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7330 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7331#ifdef CONFIG_X86_64
5fdbf976
MT		 7332 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7333 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7334 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7335 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7336 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7337 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7338 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7339 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7340#endif
7341
5fdbf976 7342 regs->rip = kvm_rip_read(vcpu);
91586a3b 7343 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7344
b6c7a5dc
HB		 7345 return 0;
7346}
7347
7348int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7349{
7ae441ea
GN		 7350 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7351 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7352
5fdbf976
MT		 7353 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7354 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7355 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7356 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7357 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7358 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7359 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7360 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7361#ifdef CONFIG_X86_64
5fdbf976
MT		 7362 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7363 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7364 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7365 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7366 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7367 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7368 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7369 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7370#endif
7371
5fdbf976 7372 kvm_rip_write(vcpu, regs->rip);
91586a3b 7373 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7374
b4f14abd
JK		 7375 vcpu->arch.exception.pending = false;
7376
3842d135
AK		 7377 kvm_make_request(KVM_REQ_EVENT, vcpu);
7378
b6c7a5dc
HB		 7379 return 0;
7380}
7381
b6c7a5dc
HB		 7382void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7383{
7384 struct kvm_segment cs;
7385
3e6e0aab 7386 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7387 *db = cs.db;
7388 *l = cs.l;
7389}
7390EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7391
7392int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7393 struct kvm_sregs *sregs)
7394{
89a27f4d 7395 struct desc_ptr dt;
b6c7a5dc 7396
3e6e0aab
GT		 7397 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7398 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7399 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7400 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7401 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7402 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7403
3e6e0aab
GT		 7404 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7405 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7406
7407 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7408 sregs->idt.limit = dt.size;
7409 sregs->idt.base = dt.address;
b6c7a5dc 7410 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7411 sregs->gdt.limit = dt.size;
7412 sregs->gdt.base = dt.address;
b6c7a5dc 7413
4d4ec087 7414 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7415 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7416 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7417 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7418 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7419 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7420 sregs->apic_base = kvm_get_apic_base(vcpu);
7421
923c61bb 7422 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7423
36752c9b 7424 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7425 set_bit(vcpu->arch.interrupt.nr,
7426 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7427
b6c7a5dc
HB		 7428 return 0;
7429}
7430
62d9f0db
MT		 7431int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7432 struct kvm_mp_state *mp_state)
7433{
66450a21 7434 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7435 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7436 vcpu->arch.pv.pv_unhalted)
7437 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7438 else
7439 mp_state->mp_state = vcpu->arch.mp_state;
7440
62d9f0db
MT		 7441 return 0;
7442}
7443
7444int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7445 struct kvm_mp_state *mp_state)
7446{
bce87cce 7447 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7448 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7449 return -EINVAL;
7450
28bf2888
DH		 7451 /* INITs are latched while in SMM */
7452 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7453 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7454 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7455 return -EINVAL;
7456
66450a21
JK		 7457 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7458 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7459 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7460 } else
7461 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7462 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7463 return 0;
7464}
7465
7f3d35fd
KW		 7466int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7467 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7468{
9d74191a 7469 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7470 int ret;
e01c2426 7471
8ec4722d 7472 init_emulate_ctxt(vcpu);
c697518a 7473
7f3d35fd 7474 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7475 has_error_code, error_code);
c697518a 7476
c697518a 7477 if (ret)
19d04437 7478 return EMULATE_FAIL;
37817f29 7479
9d74191a
TY		 7480 kvm_rip_write(vcpu, ctxt->eip);
7481 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7482 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7483 return EMULATE_DONE;
37817f29
IE		 7484}
7485EXPORT_SYMBOL_GPL(kvm_task_switch);
7486
b6c7a5dc
HB		 7487int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7488 struct kvm_sregs *sregs)
7489{
58cb628d 7490 struct msr_data apic_base_msr;
b6c7a5dc 7491 int mmu_reset_needed = 0;
63f42e02 7492 int pending_vec, max_bits, idx;
89a27f4d 7493 struct desc_ptr dt;
b6c7a5dc 7494
d6321d49
RK		 7495 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7496 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7497 return -EINVAL;
7498
d3802286
JM		 7499 apic_base_msr.data = sregs->apic_base;
7500 apic_base_msr.host_initiated = true;
7501 if (kvm_set_apic_base(vcpu, &apic_base_msr))
6d1068b3
PM		 7502 return -EINVAL;
7503
89a27f4d
GN		 7504 dt.size = sregs->idt.limit;
7505 dt.address = sregs->idt.base;
b6c7a5dc 7506 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7507 dt.size = sregs->gdt.limit;
7508 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7509 kvm_x86_ops->set_gdt(vcpu, &dt);
7510
ad312c7c 7511 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7512 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7513 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7514 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7515
2d3ad1f4 7516 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7517
f6801dff 7518 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7519 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7520
4d4ec087 7521 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7522 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7523 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7524
fc78f519 7525 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7526 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7527 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7528 kvm_update_cpuid(vcpu);
63f42e02
XG		 7529
7530 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7531 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7532 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7533 mmu_reset_needed = 1;
7534 }
63f42e02 7535 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7536
7537 if (mmu_reset_needed)
7538 kvm_mmu_reset_context(vcpu);
7539
a50abc3b 7540 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7541 pending_vec = find_first_bit(
7542 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7543 if (pending_vec < max_bits) {
66fd3f7f 7544 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7545 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7546 }
7547
3e6e0aab
GT		 7548 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7549 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7550 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7551 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7552 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7553 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7554
3e6e0aab
GT		 7555 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7556 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7557
5f0269f5
ME		 7558 update_cr8_intercept(vcpu);
7559
9c3e4aab 7560 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7561 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7562 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7563 !is_protmode(vcpu))
9c3e4aab
MT		 7564 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7565
3842d135
AK		 7566 kvm_make_request(KVM_REQ_EVENT, vcpu);
7567
b6c7a5dc
HB		 7568 return 0;
7569}
7570
d0bfb940
JK		 7571int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7572 struct kvm_guest_debug *dbg)
b6c7a5dc 7573{
355be0b9 7574 unsigned long rflags;
ae675ef0 7575 int i, r;
b6c7a5dc 7576
4f926bf2
JK		 7577 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7578 r = -EBUSY;
7579 if (vcpu->arch.exception.pending)
2122ff5e 7580 goto out;
4f926bf2
JK		 7581 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7582 kvm_queue_exception(vcpu, DB_VECTOR);
7583 else
7584 kvm_queue_exception(vcpu, BP_VECTOR);
7585 }
7586
91586a3b
JK		 7587 /*
7588 * Read rflags as long as potentially injected trace flags are still
7589 * filtered out.
7590 */
7591 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7592
7593 vcpu->guest_debug = dbg->control;
7594 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7595 vcpu->guest_debug = 0;
7596
7597 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7598 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7599 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7600 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7601 } else {
7602 for (i = 0; i < KVM_NR_DB_REGS; i++)
7603 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7604 }
c8639010 7605 kvm_update_dr7(vcpu);
ae675ef0 7606
f92653ee
JK		 7607 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7608 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7609 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7610
91586a3b
JK		 7611 /*
7612 * Trigger an rflags update that will inject or remove the trace
7613 * flags.
7614 */
7615 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7616
a96036b8 7617 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7618
4f926bf2 7619 r = 0;
d0bfb940 7620
2122ff5e 7621out:
b6c7a5dc
HB		 7622
7623 return r;
7624}
7625
8b006791
ZX		 7626/*
7627 * Translate a guest virtual address to a guest physical address.
7628 */
7629int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7630 struct kvm_translation *tr)
7631{
7632 unsigned long vaddr = tr->linear_address;
7633 gpa_t gpa;
f656ce01 7634 int idx;
8b006791 7635
f656ce01 7636 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7637 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7638 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7639 tr->physical_address = gpa;
7640 tr->valid = gpa != UNMAPPED_GVA;
7641 tr->writeable = 1;
7642 tr->usermode = 0;
8b006791
ZX		 7643
7644 return 0;
7645}
7646
d0752060
HB		 7647int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7648{
c47ada30 7649 struct fxregs_state *fxsave =
7366ed77 7650 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7651
d0752060
HB		 7652 memcpy(fpu->fpr, fxsave->st_space, 128);
7653 fpu->fcw = fxsave->cwd;
7654 fpu->fsw = fxsave->swd;
7655 fpu->ftwx = fxsave->twd;
7656 fpu->last_opcode = fxsave->fop;
7657 fpu->last_ip = fxsave->rip;
7658 fpu->last_dp = fxsave->rdp;
7659 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7660
d0752060
HB		 7661 return 0;
7662}
7663
7664int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7665{
c47ada30 7666 struct fxregs_state *fxsave =
7366ed77 7667 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7668
d0752060
HB		 7669 memcpy(fxsave->st_space, fpu->fpr, 128);
7670 fxsave->cwd = fpu->fcw;
7671 fxsave->swd = fpu->fsw;
7672 fxsave->twd = fpu->ftwx;
7673 fxsave->fop = fpu->last_opcode;
7674 fxsave->rip = fpu->last_ip;
7675 fxsave->rdp = fpu->last_dp;
7676 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7677
d0752060
HB		 7678 return 0;
7679}
7680
0ee6a517 7681static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7682{
bf935b0b 7683 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7684 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7685 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7686 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7687
2acf923e
DC		 7688 /*
7689 * Ensure guest xcr0 is valid for loading
7690 */
d91cab78 7691 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7692
ad312c7c 7693 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7694}
d0752060
HB		 7695
7696void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7697{
2608d7a1 7698 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7699 return;
7700
2acf923e
DC		 7701 /*
7702 * Restore all possible states in the guest,
7703 * and assume host would use all available bits.
7704 * Guest xcr0 would be loaded later.
7705 */
d0752060 7706 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7707 __kernel_fpu_begin();
38cfd5e3
PB		 7708 /* PKRU is separately restored in kvm_x86_ops->run. */
7709 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7710 ~XFEATURE_MASK_PKRU);
0c04851c 7711 trace_kvm_fpu(1);
d0752060 7712}
d0752060
HB		 7713
7714void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7715{
3d42de25 7716 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7717 return;
7718
7719 vcpu->guest_fpu_loaded = 0;
4f836347 7720 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7721 __kernel_fpu_end();
f096ed85 7722 ++vcpu->stat.fpu_reload;
0c04851c 7723 trace_kvm_fpu(0);
d0752060 7724}
e9b11c17
ZX		 7725
7726void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7727{
bd768e14
IY		 7728 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7729
12f9a48f 7730 kvmclock_reset(vcpu);
7f1ea208 7731
e9b11c17 7732 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7733 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7734}
7735
7736struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7737 unsigned int id)
7738{
c447e76b
LL		 7739 struct kvm_vcpu *vcpu;
7740
6755bae8
ZA		 7741 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7742 printk_once(KERN_WARNING
7743 "kvm: SMP vm created on host with unstable TSC; "
7744 "guest TSC will not be reliable\n");
c447e76b
LL		 7745
7746 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7747
c447e76b 7748 return vcpu;
26e5215f 7749}
e9b11c17 7750
26e5215f
AK		 7751int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7752{
7753 int r;
e9b11c17 7754
19efffa2 7755 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7756 r = vcpu_load(vcpu);
7757 if (r)
7758 return r;
d28bc9dd 7759 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7760 kvm_mmu_setup(vcpu);
e9b11c17 7761 vcpu_put(vcpu);
26e5215f 7762 return r;
e9b11c17
ZX		 7763}
7764
31928aa5 7765void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7766{
8fe8ab46 7767 struct msr_data msr;
332967a3 7768 struct kvm *kvm = vcpu->kvm;
42897d86 7769
d3457c87
RK		 7770 kvm_hv_vcpu_postcreate(vcpu);
7771
31928aa5
DD		 7772 if (vcpu_load(vcpu))
7773 return;
8fe8ab46
WA		 7774 msr.data = 0x0;
7775 msr.index = MSR_IA32_TSC;
7776 msr.host_initiated = true;
7777 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7778 vcpu_put(vcpu);
7779
630994b3
MT		 7780 if (!kvmclock_periodic_sync)
7781 return;
7782
332967a3
AJ		 7783 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7784 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7785}
7786
d40ccc62 7787void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7788{
9fc77441 7789 int r;
344d9588
GN		 7790 vcpu->arch.apf.msr_val = 0;
7791
9fc77441
MT		 7792 r = vcpu_load(vcpu);
7793 BUG_ON(r);
e9b11c17
ZX		 7794 kvm_mmu_unload(vcpu);
7795 vcpu_put(vcpu);
7796
7797 kvm_x86_ops->vcpu_free(vcpu);
7798}
7799
d28bc9dd 7800void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7801{
e69fab5d
PB		 7802 vcpu->arch.hflags = 0;
7803
c43203ca 7804 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7805 atomic_set(&vcpu->arch.nmi_queued, 0);
7806 vcpu->arch.nmi_pending = 0;
448fa4a9 7807 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7808 kvm_clear_interrupt_queue(vcpu);
7809 kvm_clear_exception_queue(vcpu);
664f8e26 7810 vcpu->arch.exception.pending = false;
448fa4a9 7811
42dbaa5a 7812 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7813 kvm_update_dr0123(vcpu);
6f43ed01 7814 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7815 kvm_update_dr6(vcpu);
42dbaa5a 7816 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7817 kvm_update_dr7(vcpu);
42dbaa5a 7818
1119022c
NA		 7819 vcpu->arch.cr2 = 0;
7820
3842d135 7821 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7822 vcpu->arch.apf.msr_val = 0;
c9aaa895 7823 vcpu->arch.st.msr_val = 0;
3842d135 7824
12f9a48f
GC		 7825 kvmclock_reset(vcpu);
7826
af585b92
GN		 7827 kvm_clear_async_pf_completion_queue(vcpu);
7828 kvm_async_pf_hash_reset(vcpu);
7829 vcpu->arch.apf.halted = false;
3842d135 7830
a554d207
WL		 7831 if (kvm_mpx_supported()) {
7832 void *mpx_state_buffer;
7833
7834 /*
7835 * To avoid have the INIT path from kvm_apic_has_events() that be
7836 * called with loaded FPU and does not let userspace fix the state.
7837 */
7838 kvm_put_guest_fpu(vcpu);
7839 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7840 XFEATURE_MASK_BNDREGS);
7841 if (mpx_state_buffer)
7842 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7843 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7844 XFEATURE_MASK_BNDCSR);
7845 if (mpx_state_buffer)
7846 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
7847 }
7848
64d60670 7849 if (!init_event) {
d28bc9dd 7850 kvm_pmu_reset(vcpu);
64d60670 7851 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7852
7853 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7854 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 7855
7856 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7857 }
f5132b01 7858
66f7b72e
JS		 7859 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7860 vcpu->arch.regs_avail = ~0;
7861 vcpu->arch.regs_dirty = ~0;
7862
a554d207
WL		 7863 vcpu->arch.ia32_xss = 0;
7864
d28bc9dd 7865 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7866}
7867
2b4a273b 7868void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7869{
7870 struct kvm_segment cs;
7871
7872 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7873 cs.selector = vector << 8;
7874 cs.base = vector << 12;
7875 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7876 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7877}
7878
13a34e06 7879int kvm_arch_hardware_enable(void)
e9b11c17 7880{
ca84d1a2
ZA		 7881 struct kvm *kvm;
7882 struct kvm_vcpu *vcpu;
7883 int i;
0dd6a6ed
ZA		 7884 int ret;
7885 u64 local_tsc;
7886 u64 max_tsc = 0;
7887 bool stable, backwards_tsc = false;
18863bdd
AK		 7888
7889 kvm_shared_msr_cpu_online();
13a34e06 7890 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7891 if (ret != 0)
7892 return ret;
7893
4ea1636b 7894 local_tsc = rdtsc();
0dd6a6ed
ZA		 7895 stable = !check_tsc_unstable();
7896 list_for_each_entry(kvm, &vm_list, vm_list) {
7897 kvm_for_each_vcpu(i, vcpu, kvm) {
7898 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7899 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7900 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7901 backwards_tsc = true;
7902 if (vcpu->arch.last_host_tsc > max_tsc)
7903 max_tsc = vcpu->arch.last_host_tsc;
7904 }
7905 }
7906 }
7907
7908 /*
7909 * Sometimes, even reliable TSCs go backwards. This happens on
7910 * platforms that reset TSC during suspend or hibernate actions, but
7911 * maintain synchronization. We must compensate. Fortunately, we can
7912 * detect that condition here, which happens early in CPU bringup,
7913 * before any KVM threads can be running. Unfortunately, we can't
7914 * bring the TSCs fully up to date with real time, as we aren't yet far
7915 * enough into CPU bringup that we know how much real time has actually
108b249c 7916 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7917 * variables that haven't been updated yet.
7918 *
7919 * So we simply find the maximum observed TSC above, then record the
7920 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7921 * the adjustment will be applied. Note that we accumulate
7922 * adjustments, in case multiple suspend cycles happen before some VCPU
7923 * gets a chance to run again. In the event that no KVM threads get a
7924 * chance to run, we will miss the entire elapsed period, as we'll have
7925 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7926 * loose cycle time. This isn't too big a deal, since the loss will be
7927 * uniform across all VCPUs (not to mention the scenario is extremely
7928 * unlikely). It is possible that a second hibernate recovery happens
7929 * much faster than a first, causing the observed TSC here to be
7930 * smaller; this would require additional padding adjustment, which is
7931 * why we set last_host_tsc to the local tsc observed here.
7932 *
7933 * N.B. - this code below runs only on platforms with reliable TSC,
7934 * as that is the only way backwards_tsc is set above. Also note
7935 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7936 * have the same delta_cyc adjustment applied if backwards_tsc
7937 * is detected. Note further, this adjustment is only done once,
7938 * as we reset last_host_tsc on all VCPUs to stop this from being
7939 * called multiple times (one for each physical CPU bringup).
7940 *
4a969980 7941 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7942 * will be compensated by the logic in vcpu_load, which sets the TSC to
7943 * catchup mode. This will catchup all VCPUs to real time, but cannot
7944 * guarantee that they stay in perfect synchronization.
7945 */
7946 if (backwards_tsc) {
7947 u64 delta_cyc = max_tsc - local_tsc;
7948 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7949 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7950 kvm_for_each_vcpu(i, vcpu, kvm) {
7951 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7952 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7953 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7954 }
7955
7956 /*
7957 * We have to disable TSC offset matching.. if you were
7958 * booting a VM while issuing an S4 host suspend....
7959 * you may have some problem. Solving this issue is
7960 * left as an exercise to the reader.
7961 */
7962 kvm->arch.last_tsc_nsec = 0;
7963 kvm->arch.last_tsc_write = 0;
7964 }
7965
7966 }
7967 return 0;
e9b11c17
ZX		 7968}
7969
13a34e06 7970void kvm_arch_hardware_disable(void)
e9b11c17 7971{
13a34e06
RK		 7972 kvm_x86_ops->hardware_disable();
7973 drop_user_return_notifiers();
e9b11c17
ZX		 7974}
7975
7976int kvm_arch_hardware_setup(void)
7977{
9e9c3fe4
NA		 7978 int r;
7979
7980 r = kvm_x86_ops->hardware_setup();
7981 if (r != 0)
7982 return r;
7983
35181e86
HZ		 7984 if (kvm_has_tsc_control) {
7985 /*
7986 * Make sure the user can only configure tsc_khz values that
7987 * fit into a signed integer.
7988 * A min value is not calculated needed because it will always
7989 * be 1 on all machines.
7990 */
7991 u64 max = min(0x7fffffffULL,
7992 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7993 kvm_max_guest_tsc_khz = max;
7994
ad721883 7995 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7996 }
ad721883 7997
9e9c3fe4
NA		 7998 kvm_init_msr_list();
7999 return 0;
e9b11c17
ZX		 8000}
8001
8002void kvm_arch_hardware_unsetup(void)
8003{
8004 kvm_x86_ops->hardware_unsetup();
8005}
8006
8007void kvm_arch_check_processor_compat(void *rtn)
8008{
8009 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8010}
8011
8012bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8013{
8014 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8015}
8016EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8017
8018bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8019{
8020 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8021}
8022
54e9818f 8023struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8024EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8025
e9b11c17
ZX		 8026int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8027{
8028 struct page *page;
e9b11c17
ZX		 8029 int r;
8030
b2a05fef 8031 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8032 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8033 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8034 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8035 else
a4535290 8036 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8037
8038 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8039 if (!page) {
8040 r = -ENOMEM;
8041 goto fail;
8042 }
ad312c7c 8043 vcpu->arch.pio_data = page_address(page);
e9b11c17 8044
cc578287 8045 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8046
e9b11c17
ZX		 8047 r = kvm_mmu_create(vcpu);
8048 if (r < 0)
8049 goto fail_free_pio_data;
8050
26de7988 8051 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8052 r = kvm_create_lapic(vcpu);
8053 if (r < 0)
8054 goto fail_mmu_destroy;
54e9818f
GN		 8055 } else
8056 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8057
890ca9ae
HY		 8058 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8059 GFP_KERNEL);
8060 if (!vcpu->arch.mce_banks) {
8061 r = -ENOMEM;
443c39bc 8062 goto fail_free_lapic;
890ca9ae
HY		 8063 }
8064 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8065
f1797359
WY		 8066 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8067 r = -ENOMEM;
f5f48ee1 8068 goto fail_free_mce_banks;
f1797359 8069 }
f5f48ee1 8070
0ee6a517 8071 fx_init(vcpu);
66f7b72e 8072
4344ee98 8073 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8074
5a4f55cd
EK		 8075 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8076
74545705
RK		 8077 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8078
af585b92 8079 kvm_async_pf_hash_reset(vcpu);
f5132b01 8080 kvm_pmu_init(vcpu);
af585b92 8081
1c1a9ce9 8082 vcpu->arch.pending_external_vector = -1;
de63ad4c 8083 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8084
5c919412
AS		 8085 kvm_hv_vcpu_init(vcpu);
8086
e9b11c17 8087 return 0;
0ee6a517 8088
f5f48ee1
SY		 8089fail_free_mce_banks:
8090 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8091fail_free_lapic:
8092 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8093fail_mmu_destroy:
8094 kvm_mmu_destroy(vcpu);
8095fail_free_pio_data:
ad312c7c 8096 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8097fail:
8098 return r;
8099}
8100
8101void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8102{
f656ce01
MT		 8103 int idx;
8104
1f4b34f8 8105 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8106 kvm_pmu_destroy(vcpu);
36cb93fd 8107 kfree(vcpu->arch.mce_banks);
e9b11c17 8108 kvm_free_lapic(vcpu);
f656ce01 8109 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8110 kvm_mmu_destroy(vcpu);
f656ce01 8111 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8112 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8113 if (!lapic_in_kernel(vcpu))
54e9818f 8114 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8115}
d19a9cd2 8116
e790d9ef
RK		 8117void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8118{
ae97a3b8 8119 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8120}
8121
e08b9637 8122int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8123{
e08b9637
CO		 8124 if (type)
8125 return -EINVAL;
8126
6ef768fa 8127 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8128 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8129 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8130 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8131 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8132
5550af4d
SY		 8133 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8134 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8135 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8136 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8137 &kvm->arch.irq_sources_bitmap);
5550af4d 8138
038f8c11 8139 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8140 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8141 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8142 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8143
108b249c 8144 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8145 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8146
7e44e449 8147 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8148 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8149
0eb05bf2 8150 kvm_page_track_init(kvm);
13d268ca 8151 kvm_mmu_init_vm(kvm);
0eb05bf2 8152
03543133
SS		 8153 if (kvm_x86_ops->vm_init)
8154 return kvm_x86_ops->vm_init(kvm);
8155
d89f5eff 8156 return 0;
d19a9cd2
ZX		 8157}
8158
8159static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8160{
9fc77441
MT		 8161 int r;
8162 r = vcpu_load(vcpu);
8163 BUG_ON(r);
d19a9cd2
ZX		 8164 kvm_mmu_unload(vcpu);
8165 vcpu_put(vcpu);
8166}
8167
8168static void kvm_free_vcpus(struct kvm *kvm)
8169{
8170 unsigned int i;
988a2cae 8171 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8172
8173 /*
8174 * Unpin any mmu pages first.
8175 */
af585b92
GN		 8176 kvm_for_each_vcpu(i, vcpu, kvm) {
8177 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8178 kvm_unload_vcpu_mmu(vcpu);
af585b92 8179 }
988a2cae
GN		 8180 kvm_for_each_vcpu(i, vcpu, kvm)
8181 kvm_arch_vcpu_free(vcpu);
8182
8183 mutex_lock(&kvm->lock);
8184 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8185 kvm->vcpus[i] = NULL;
d19a9cd2 8186
988a2cae
GN		 8187 atomic_set(&kvm->online_vcpus, 0);
8188 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8189}
8190
ad8ba2cd
SY		 8191void kvm_arch_sync_events(struct kvm *kvm)
8192{
332967a3 8193 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8194 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8195 kvm_free_pit(kvm);
ad8ba2cd
SY		 8196}
8197
1d8007bd 8198int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8199{
8200 int i, r;
25188b99 8201 unsigned long hva;
f0d648bd
PB		 8202 struct kvm_memslots *slots = kvm_memslots(kvm);
8203 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8204
8205 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8206 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8207 return -EINVAL;
9da0e4d5 8208
f0d648bd
PB		 8209 slot = id_to_memslot(slots, id);
8210 if (size) {
b21629da 8211 if (slot->npages)
f0d648bd
PB		 8212 return -EEXIST;
8213
8214 /*
8215 * MAP_SHARED to prevent internal slot pages from being moved
8216 * by fork()/COW.
8217 */
8218 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8219 MAP_SHARED | MAP_ANONYMOUS, 0);
8220 if (IS_ERR((void *)hva))
8221 return PTR_ERR((void *)hva);
8222 } else {
8223 if (!slot->npages)
8224 return 0;
8225
8226 hva = 0;
8227 }
8228
8229 old = *slot;
9da0e4d5 8230 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8231 struct kvm_userspace_memory_region m;
9da0e4d5 8232
1d8007bd
PB		 8233 m.slot = id | (i << 16);
8234 m.flags = 0;
8235 m.guest_phys_addr = gpa;
f0d648bd 8236 m.userspace_addr = hva;
1d8007bd 8237 m.memory_size = size;
9da0e4d5
PB		 8238 r = __kvm_set_memory_region(kvm, &m);
8239 if (r < 0)
8240 return r;
8241 }
8242
f0d648bd
PB		 8243 if (!size) {
8244 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8245 WARN_ON(r < 0);
8246 }
8247
9da0e4d5
PB		 8248 return 0;
8249}
8250EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8251
1d8007bd 8252int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8253{
8254 int r;
8255
8256 mutex_lock(&kvm->slots_lock);
1d8007bd 8257 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8258 mutex_unlock(&kvm->slots_lock);
8259
8260 return r;
8261}
8262EXPORT_SYMBOL_GPL(x86_set_memory_region);
8263
d19a9cd2
ZX		 8264void kvm_arch_destroy_vm(struct kvm *kvm)
8265{
27469d29
AH		 8266 if (current->mm == kvm->mm) {
8267 /*
8268 * Free memory regions allocated on behalf of userspace,
8269 * unless the the memory map has changed due to process exit
8270 * or fd copying.
8271 */
1d8007bd
PB		 8272 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8273 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8274 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8275 }
03543133
SS		 8276 if (kvm_x86_ops->vm_destroy)
8277 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8278 kvm_pic_destroy(kvm);
8279 kvm_ioapic_destroy(kvm);
d19a9cd2 8280 kvm_free_vcpus(kvm);
af1bae54 8281 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8282 kvm_mmu_uninit_vm(kvm);
2beb6dad 8283 kvm_page_track_cleanup(kvm);
d19a9cd2 8284}
0de10343 8285
5587027c 8286void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8287 struct kvm_memory_slot *dont)
8288{
8289 int i;
8290
d89cc617
TY		 8291 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8292 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8293 kvfree(free->arch.rmap[i]);
d89cc617 8294 free->arch.rmap[i] = NULL;
77d11309 8295 }
d89cc617
TY		 8296 if (i == 0)
8297 continue;
8298
8299 if (!dont || free->arch.lpage_info[i - 1] !=
8300 dont->arch.lpage_info[i - 1]) {
548ef284 8301 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8302 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8303 }
8304 }
21ebbeda
XG		 8305
8306 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8307}
8308
5587027c
AK		 8309int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8310 unsigned long npages)
db3fe4eb
TY		 8311{
8312 int i;
8313
d89cc617 8314 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8315 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8316 unsigned long ugfn;
8317 int lpages;
d89cc617 8318 int level = i + 1;
db3fe4eb
TY		 8319
8320 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8321 slot->base_gfn, level) + 1;
8322
d89cc617 8323 slot->arch.rmap[i] =
a7c3e901 8324 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8325 if (!slot->arch.rmap[i])
77d11309 8326 goto out_free;
d89cc617
TY		 8327 if (i == 0)
8328 continue;
77d11309 8329
a7c3e901 8330 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8331 if (!linfo)
db3fe4eb
TY		 8332 goto out_free;
8333
92f94f1e
XG		 8334 slot->arch.lpage_info[i - 1] = linfo;
8335
db3fe4eb 8336 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8337 linfo[0].disallow_lpage = 1;
db3fe4eb 8338 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8339 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8340 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8341 /*
8342 * If the gfn and userspace address are not aligned wrt each
8343 * other, or if explicitly asked to, disable large page
8344 * support for this slot
8345 */
8346 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8347 !kvm_largepages_enabled()) {
8348 unsigned long j;
8349
8350 for (j = 0; j < lpages; ++j)
92f94f1e 8351 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8352 }
8353 }
8354
21ebbeda
XG		 8355 if (kvm_page_track_create_memslot(slot, npages))
8356 goto out_free;
8357
db3fe4eb
TY		 8358 return 0;
8359
8360out_free:
d89cc617 8361 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8362 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8363 slot->arch.rmap[i] = NULL;
8364 if (i == 0)
8365 continue;
8366
548ef284 8367 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8368 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8369 }
8370 return -ENOMEM;
8371}
8372
15f46015 8373void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8374{
e6dff7d1
TY		 8375 /*
8376 * memslots->generation has been incremented.
8377 * mmio generation may have reached its maximum value.
8378 */
54bf36aa 8379 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8380}
8381
f7784b8e
MT		 8382int kvm_arch_prepare_memory_region(struct kvm *kvm,
8383 struct kvm_memory_slot *memslot,
09170a49 8384 const struct kvm_userspace_memory_region *mem,
7b6195a9 8385 enum kvm_mr_change change)
0de10343 8386{
f7784b8e
MT		 8387 return 0;
8388}
8389
88178fd4
KH		 8390static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8391 struct kvm_memory_slot *new)
8392{
8393 /* Still write protect RO slot */
8394 if (new->flags & KVM_MEM_READONLY) {
8395 kvm_mmu_slot_remove_write_access(kvm, new);
8396 return;
8397 }
8398
8399 /*
8400 * Call kvm_x86_ops dirty logging hooks when they are valid.
8401 *
8402 * kvm_x86_ops->slot_disable_log_dirty is called when:
8403 *
8404 * - KVM_MR_CREATE with dirty logging is disabled
8405 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8406 *
8407 * The reason is, in case of PML, we need to set D-bit for any slots
8408 * with dirty logging disabled in order to eliminate unnecessary GPA
8409 * logging in PML buffer (and potential PML buffer full VMEXT). This
8410 * guarantees leaving PML enabled during guest's lifetime won't have
8411 * any additonal overhead from PML when guest is running with dirty
8412 * logging disabled for memory slots.
8413 *
8414 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8415 * to dirty logging mode.
8416 *
8417 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8418 *
8419 * In case of write protect:
8420 *
8421 * Write protect all pages for dirty logging.
8422 *
8423 * All the sptes including the large sptes which point to this
8424 * slot are set to readonly. We can not create any new large
8425 * spte on this slot until the end of the logging.
8426 *
8427 * See the comments in fast_page_fault().
8428 */
8429 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8430 if (kvm_x86_ops->slot_enable_log_dirty)
8431 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8432 else
8433 kvm_mmu_slot_remove_write_access(kvm, new);
8434 } else {
8435 if (kvm_x86_ops->slot_disable_log_dirty)
8436 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8437 }
8438}
8439
f7784b8e 8440void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8441 const struct kvm_userspace_memory_region *mem,
8482644a 8442 const struct kvm_memory_slot *old,
f36f3f28 8443 const struct kvm_memory_slot *new,
8482644a 8444 enum kvm_mr_change change)
f7784b8e 8445{
8482644a 8446 int nr_mmu_pages = 0;
f7784b8e 8447
48c0e4e9
XG		 8448 if (!kvm->arch.n_requested_mmu_pages)
8449 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8450
48c0e4e9 8451 if (nr_mmu_pages)
0de10343 8452 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8453
3ea3b7fa
WL		 8454 /*
8455 * Dirty logging tracks sptes in 4k granularity, meaning that large
8456 * sptes have to be split. If live migration is successful, the guest
8457 * in the source machine will be destroyed and large sptes will be
8458 * created in the destination. However, if the guest continues to run
8459 * in the source machine (for example if live migration fails), small
8460 * sptes will remain around and cause bad performance.
8461 *
8462 * Scan sptes if dirty logging has been stopped, dropping those
8463 * which can be collapsed into a single large-page spte. Later
8464 * page faults will create the large-page sptes.
8465 */
8466 if ((change != KVM_MR_DELETE) &&
8467 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8468 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8469 kvm_mmu_zap_collapsible_sptes(kvm, new);
8470
c972f3b1 8471 /*
88178fd4 8472 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8473 *
88178fd4
KH		 8474 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8475 * been zapped so no dirty logging staff is needed for old slot. For
8476 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8477 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8478 *
8479 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8480 */
88178fd4 8481 if (change != KVM_MR_DELETE)
f36f3f28 8482 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8483}
1d737c8a 8484
2df72e9b 8485void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8486{
6ca18b69 8487 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8488}
8489
2df72e9b
MT		 8490void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8491 struct kvm_memory_slot *slot)
8492{
ae7cd873 8493 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8494}
8495
5d9bc648
PB		 8496static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8497{
8498 if (!list_empty_careful(&vcpu->async_pf.done))
8499 return true;
8500
8501 if (kvm_apic_has_events(vcpu))
8502 return true;
8503
8504 if (vcpu->arch.pv.pv_unhalted)
8505 return true;
8506
a5f01f8e
WL		 8507 if (vcpu->arch.exception.pending)
8508 return true;
8509
47a66eed
Z		 8510 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8511 (vcpu->arch.nmi_pending &&
8512 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8513 return true;
8514
47a66eed
Z		 8515 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8516 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8517 return true;
8518
5d9bc648
PB		 8519 if (kvm_arch_interrupt_allowed(vcpu) &&
8520 kvm_cpu_has_interrupt(vcpu))
8521 return true;
8522
1f4b34f8
AS		 8523 if (kvm_hv_has_stimer_pending(vcpu))
8524 return true;
8525
5d9bc648
PB		 8526 return false;
8527}
8528
1d737c8a
ZX		 8529int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8530{
5d9bc648 8531 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8532}
5736199a 8533
199b5763
LM		 8534bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8535{
de63ad4c 8536 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8537}
8538
b6d33834 8539int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8540{
b6d33834 8541 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8542}
78646121
GN		 8543
8544int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8545{
8546 return kvm_x86_ops->interrupt_allowed(vcpu);
8547}
229456fc 8548
82b32774 8549unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8550{
82b32774
NA		 8551 if (is_64_bit_mode(vcpu))
8552 return kvm_rip_read(vcpu);
8553 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8554 kvm_rip_read(vcpu));
8555}
8556EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8557
82b32774
NA		 8558bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8559{
8560 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8561}
8562EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8563
94fe45da
JK		 8564unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8565{
8566 unsigned long rflags;
8567
8568 rflags = kvm_x86_ops->get_rflags(vcpu);
8569 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8570 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8571 return rflags;
8572}
8573EXPORT_SYMBOL_GPL(kvm_get_rflags);
8574
6addfc42 8575static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8576{
8577 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8578 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8579 rflags |= X86_EFLAGS_TF;
94fe45da 8580 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8581}
8582
8583void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8584{
8585 __kvm_set_rflags(vcpu, rflags);
3842d135 8586 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8587}
8588EXPORT_SYMBOL_GPL(kvm_set_rflags);
8589
56028d08
GN		 8590void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8591{
8592 int r;
8593
fb67e14f 8594 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8595 work->wakeup_all)
56028d08
GN		 8596 return;
8597
8598 r = kvm_mmu_reload(vcpu);
8599 if (unlikely(r))
8600 return;
8601
fb67e14f
XG		 8602 if (!vcpu->arch.mmu.direct_map &&
8603 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8604 return;
8605
56028d08
GN		 8606 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8607}
8608
af585b92
GN		 8609static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8610{
8611 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8612}
8613
8614static inline u32 kvm_async_pf_next_probe(u32 key)
8615{
8616 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8617}
8618
8619static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8620{
8621 u32 key = kvm_async_pf_hash_fn(gfn);
8622
8623 while (vcpu->arch.apf.gfns[key] != ~0)
8624 key = kvm_async_pf_next_probe(key);
8625
8626 vcpu->arch.apf.gfns[key] = gfn;
8627}
8628
8629static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8630{
8631 int i;
8632 u32 key = kvm_async_pf_hash_fn(gfn);
8633
8634 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8635 (vcpu->arch.apf.gfns[key] != gfn &&
8636 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8637 key = kvm_async_pf_next_probe(key);
8638
8639 return key;
8640}
8641
8642bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8643{
8644 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8645}
8646
8647static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8648{
8649 u32 i, j, k;
8650
8651 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8652 while (true) {
8653 vcpu->arch.apf.gfns[i] = ~0;
8654 do {
8655 j = kvm_async_pf_next_probe(j);
8656 if (vcpu->arch.apf.gfns[j] == ~0)
8657 return;
8658 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8659 /*
8660 * k lies cyclically in ]i,j]
8661 * | i.k.j |
8662 * |....j i.k.| or |.k..j i...|
8663 */
8664 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8665 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8666 i = j;
8667 }
8668}
8669
7c90705b
GN		 8670static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8671{
4e335d9e
PB		 8672
8673 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8674 sizeof(val));
7c90705b
GN		 8675}
8676
9a6e7c39
WL		 8677static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8678{
8679
8680 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8681 sizeof(u32));
8682}
8683
af585b92
GN		 8684void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8685 struct kvm_async_pf *work)
8686{
6389ee94
AK		 8687 struct x86_exception fault;
8688
7c90705b 8689 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8690 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8691
8692 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8693 (vcpu->arch.apf.send_user_only &&
8694 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8695 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8696 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8697 fault.vector = PF_VECTOR;
8698 fault.error_code_valid = true;
8699 fault.error_code = 0;
8700 fault.nested_page_fault = false;
8701 fault.address = work->arch.token;
adfe20fb 8702 fault.async_page_fault = true;
6389ee94 8703 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8704 }
af585b92
GN		 8705}
8706
8707void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8708 struct kvm_async_pf *work)
8709{
6389ee94 8710 struct x86_exception fault;
9a6e7c39 8711 u32 val;
6389ee94 8712
f2e10669 8713 if (work->wakeup_all)
7c90705b
GN		 8714 work->arch.token = ~0; /* broadcast wakeup */
8715 else
8716 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8717 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8718
9a6e7c39
WL		 8719 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8720 !apf_get_user(vcpu, &val)) {
8721 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8722 vcpu->arch.exception.pending &&
8723 vcpu->arch.exception.nr == PF_VECTOR &&
8724 !apf_put_user(vcpu, 0)) {
8725 vcpu->arch.exception.injected = false;
8726 vcpu->arch.exception.pending = false;
8727 vcpu->arch.exception.nr = 0;
8728 vcpu->arch.exception.has_error_code = false;
8729 vcpu->arch.exception.error_code = 0;
8730 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8731 fault.vector = PF_VECTOR;
8732 fault.error_code_valid = true;
8733 fault.error_code = 0;
8734 fault.nested_page_fault = false;
8735 fault.address = work->arch.token;
8736 fault.async_page_fault = true;
8737 kvm_inject_page_fault(vcpu, &fault);
8738 }
7c90705b 8739 }
e6d53e3b 8740 vcpu->arch.apf.halted = false;
a4fa1635 8741 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8742}
8743
8744bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8745{
8746 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8747 return true;
8748 else
9bc1f09f 8749 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8750}
8751
5544eb9b
PB		 8752void kvm_arch_start_assignment(struct kvm *kvm)
8753{
8754 atomic_inc(&kvm->arch.assigned_device_count);
8755}
8756EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8757
8758void kvm_arch_end_assignment(struct kvm *kvm)
8759{
8760 atomic_dec(&kvm->arch.assigned_device_count);
8761}
8762EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8763
8764bool kvm_arch_has_assigned_device(struct kvm *kvm)
8765{
8766 return atomic_read(&kvm->arch.assigned_device_count);
8767}
8768EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8769
e0f0bbc5
AW		 8770void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8771{
8772 atomic_inc(&kvm->arch.noncoherent_dma_count);
8773}
8774EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8775
8776void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8777{
8778 atomic_dec(&kvm->arch.noncoherent_dma_count);
8779}
8780EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8781
8782bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8783{
8784 return atomic_read(&kvm->arch.noncoherent_dma_count);
8785}
8786EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8787
14717e20
AW		 8788bool kvm_arch_has_irq_bypass(void)
8789{
8790 return kvm_x86_ops->update_pi_irte != NULL;
8791}
8792
87276880
FW		 8793int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8794 struct irq_bypass_producer *prod)
8795{
8796 struct kvm_kernel_irqfd *irqfd =
8797 container_of(cons, struct kvm_kernel_irqfd, consumer);
8798
14717e20 8799 irqfd->producer = prod;
87276880 8800
14717e20
AW		 8801 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8802 prod->irq, irqfd->gsi, 1);
87276880
FW		 8803}
8804
8805void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8806 struct irq_bypass_producer *prod)
8807{
8808 int ret;
8809 struct kvm_kernel_irqfd *irqfd =
8810 container_of(cons, struct kvm_kernel_irqfd, consumer);
8811
87276880
FW		 8812 WARN_ON(irqfd->producer != prod);
8813 irqfd->producer = NULL;
8814
8815 /*
8816 * When producer of consumer is unregistered, we change back to
8817 * remapped mode, so we can re-use the current implementation
bb3541f1 8818 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8819 * int this case doesn't want to receive the interrupts.
8820 */
8821 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8822 if (ret)
8823 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8824 " fails: %d\n", irqfd->consumer.token, ret);
8825}
8826
8827int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8828 uint32_t guest_irq, bool set)
8829{
8830 if (!kvm_x86_ops->update_pi_irte)
8831 return -EINVAL;
8832
8833 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8834}
8835
52004014
FW		 8836bool kvm_vector_hashing_enabled(void)
8837{
8838 return vector_hashing;
8839}
8840EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8841
229456fc 8842EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8843EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8844EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8845EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8846EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8847EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8848EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8849EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8850EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8851EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8852EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8853EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8854EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8855EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8856EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8857EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8858EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8859EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8860EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)