projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: X86: Provide a capability to disable MWAIT intercepts
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
9ed96e87
MT		 117unsigned int min_timer_period_us = 500;
118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
141
52004014
FW		 142static bool __read_mostly vector_hashing = true;
143module_param(vector_hashing, bool, S_IRUGO);
144
c4ae60e4
LA		 145bool __read_mostly enable_vmware_backdoor = false;
146module_param(enable_vmware_backdoor, bool, S_IRUGO);
147EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
148
18863bdd
AK		 149#define KVM_NR_SHARED_MSRS 16
150
151struct kvm_shared_msrs_global {
152 int nr;
2bf78fa7 153 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 154};
155
156struct kvm_shared_msrs {
157 struct user_return_notifier urn;
158 bool registered;
2bf78fa7
SY		 159 struct kvm_shared_msr_values {
160 u64 host;
161 u64 curr;
162 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 163};
164
165static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 166static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 167
417bc304 168struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 169 { "pf_fixed", VCPU_STAT(pf_fixed) },
170 { "pf_guest", VCPU_STAT(pf_guest) },
171 { "tlb_flush", VCPU_STAT(tlb_flush) },
172 { "invlpg", VCPU_STAT(invlpg) },
173 { "exits", VCPU_STAT(exits) },
174 { "io_exits", VCPU_STAT(io_exits) },
175 { "mmio_exits", VCPU_STAT(mmio_exits) },
176 { "signal_exits", VCPU_STAT(signal_exits) },
177 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 178 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 179 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 180 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 181 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 182 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 183 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 184 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 185 { "request_irq", VCPU_STAT(request_irq_exits) },
186 { "irq_exits", VCPU_STAT(irq_exits) },
187 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 188 { "fpu_reload", VCPU_STAT(fpu_reload) },
189 { "insn_emulation", VCPU_STAT(insn_emulation) },
190 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 191 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 192 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 193 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 194 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
195 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
196 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
197 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
198 { "mmu_flooded", VM_STAT(mmu_flooded) },
199 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 200 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 201 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 202 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 203 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 204 { "max_mmu_page_hash_collisions",
205 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 206 { NULL }
207};
208
2acf923e
DC		 209u64 __read_mostly host_xcr0;
210
b6785def 211static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 212
af585b92
GN		 213static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
214{
215 int i;
216 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
217 vcpu->arch.apf.gfns[i] = ~0;
218}
219
18863bdd
AK		 220static void kvm_on_user_return(struct user_return_notifier *urn)
221{
222 unsigned slot;
18863bdd
AK		 223 struct kvm_shared_msrs *locals
224 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 225 struct kvm_shared_msr_values *values;
1650b4eb
IA		 226 unsigned long flags;
227
228 /*
229 * Disabling irqs at this point since the following code could be
230 * interrupted and executed through kvm_arch_hardware_disable()
231 */
232 local_irq_save(flags);
233 if (locals->registered) {
234 locals->registered = false;
235 user_return_notifier_unregister(urn);
236 }
237 local_irq_restore(flags);
18863bdd 238 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 239 values = &locals->values[slot];
240 if (values->host != values->curr) {
241 wrmsrl(shared_msrs_global.msrs[slot], values->host);
242 values->curr = values->host;
18863bdd
AK		 243 }
244 }
18863bdd
AK		 245}
246
2bf78fa7 247static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 248{
18863bdd 249 u64 value;
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 252
2bf78fa7
SY		 253 /* only read, and nobody should modify it at this time,
254 * so don't need lock */
255 if (slot >= shared_msrs_global.nr) {
256 printk(KERN_ERR "kvm: invalid MSR slot!");
257 return;
258 }
259 rdmsrl_safe(msr, &value);
260 smsr->values[slot].host = value;
261 smsr->values[slot].curr = value;
262}
263
264void kvm_define_shared_msr(unsigned slot, u32 msr)
265{
0123be42 266 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 267 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 268 if (slot >= shared_msrs_global.nr)
269 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 270}
271EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
272
273static void kvm_shared_msr_cpu_online(void)
274{
275 unsigned i;
18863bdd
AK		 276
277 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 278 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 279}
280
8b3c3104 281int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 282{
013f6a5d
MT		 283 unsigned int cpu = smp_processor_id();
284 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 285 int err;
18863bdd 286
2bf78fa7 287 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 288 return 0;
2bf78fa7 289 smsr->values[slot].curr = value;
8b3c3104
AH		 290 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
291 if (err)
292 return 1;
293
18863bdd
AK		 294 if (!smsr->registered) {
295 smsr->urn.on_user_return = kvm_on_user_return;
296 user_return_notifier_register(&smsr->urn);
297 smsr->registered = true;
298 }
8b3c3104 299 return 0;
18863bdd
AK		 300}
301EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
302
13a34e06 303static void drop_user_return_notifiers(void)
3548bab5 304{
013f6a5d
MT		 305 unsigned int cpu = smp_processor_id();
306 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 307
308 if (smsr->registered)
309 kvm_on_user_return(&smsr->urn);
310}
311
6866b83e
CO		 312u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
313{
8a5a87d9 314 return vcpu->arch.apic_base;
6866b83e
CO		 315}
316EXPORT_SYMBOL_GPL(kvm_get_apic_base);
317
58cb628d
JK		 318int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
319{
320 u64 old_state = vcpu->arch.apic_base &
321 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
322 u64 new_state = msr_info->data &
323 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 324 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
325 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 326
d3802286
JM		 327 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
328 return 1;
58cb628d 329 if (!msr_info->host_initiated &&
d3802286 330 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 331 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
332 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
333 old_state == 0)))
334 return 1;
335
336 kvm_lapic_set_base(vcpu, msr_info->data);
337 return 0;
6866b83e
CO		 338}
339EXPORT_SYMBOL_GPL(kvm_set_apic_base);
340
2605fc21 341asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 342{
343 /* Fault while not rebooting. We want the trace. */
344 BUG();
345}
346EXPORT_SYMBOL_GPL(kvm_spurious_fault);
347
3fd28fce
ED		 348#define EXCPT_BENIGN 0
349#define EXCPT_CONTRIBUTORY 1
350#define EXCPT_PF 2
351
352static int exception_class(int vector)
353{
354 switch (vector) {
355 case PF_VECTOR:
356 return EXCPT_PF;
357 case DE_VECTOR:
358 case TS_VECTOR:
359 case NP_VECTOR:
360 case SS_VECTOR:
361 case GP_VECTOR:
362 return EXCPT_CONTRIBUTORY;
363 default:
364 break;
365 }
366 return EXCPT_BENIGN;
367}
368
d6e8c854
NA		 369#define EXCPT_FAULT 0
370#define EXCPT_TRAP 1
371#define EXCPT_ABORT 2
372#define EXCPT_INTERRUPT 3
373
374static int exception_type(int vector)
375{
376 unsigned int mask;
377
378 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
379 return EXCPT_INTERRUPT;
380
381 mask = 1 << vector;
382
383 /* #DB is trap, as instruction watchpoints are handled elsewhere */
384 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
385 return EXCPT_TRAP;
386
387 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
388 return EXCPT_ABORT;
389
390 /* Reserved exceptions will result in fault */
391 return EXCPT_FAULT;
392}
393
3fd28fce 394static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 395 unsigned nr, bool has_error, u32 error_code,
396 bool reinject)
3fd28fce
ED		 397{
398 u32 prev_nr;
399 int class1, class2;
400
3842d135
AK		 401 kvm_make_request(KVM_REQ_EVENT, vcpu);
402
664f8e26 403 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 404 queue:
3ffb2468
NA		 405 if (has_error && !is_protmode(vcpu))
406 has_error = false;
664f8e26
WL		 407 if (reinject) {
408 /*
409 * On vmentry, vcpu->arch.exception.pending is only
410 * true if an event injection was blocked by
411 * nested_run_pending. In that case, however,
412 * vcpu_enter_guest requests an immediate exit,
413 * and the guest shouldn't proceed far enough to
414 * need reinjection.
415 */
416 WARN_ON_ONCE(vcpu->arch.exception.pending);
417 vcpu->arch.exception.injected = true;
418 } else {
419 vcpu->arch.exception.pending = true;
420 vcpu->arch.exception.injected = false;
421 }
3fd28fce
ED		 422 vcpu->arch.exception.has_error_code = has_error;
423 vcpu->arch.exception.nr = nr;
424 vcpu->arch.exception.error_code = error_code;
425 return;
426 }
427
428 /* to check exception */
429 prev_nr = vcpu->arch.exception.nr;
430 if (prev_nr == DF_VECTOR) {
431 /* triple fault -> shutdown */
a8eeb04a 432 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 433 return;
434 }
435 class1 = exception_class(prev_nr);
436 class2 = exception_class(nr);
437 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
438 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 439 /*
440 * Generate double fault per SDM Table 5-5. Set
441 * exception.pending = true so that the double fault
442 * can trigger a nested vmexit.
443 */
3fd28fce 444 vcpu->arch.exception.pending = true;
664f8e26 445 vcpu->arch.exception.injected = false;
3fd28fce
ED		 446 vcpu->arch.exception.has_error_code = true;
447 vcpu->arch.exception.nr = DF_VECTOR;
448 vcpu->arch.exception.error_code = 0;
449 } else
450 /* replace previous exception with a new one in a hope
451 that instruction re-execution will regenerate lost
452 exception */
453 goto queue;
454}
455
298101da
AK		 456void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457{
ce7ddec4 458 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 459}
460EXPORT_SYMBOL_GPL(kvm_queue_exception);
461
ce7ddec4
JR		 462void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
463{
464 kvm_multiple_exception(vcpu, nr, false, 0, true);
465}
466EXPORT_SYMBOL_GPL(kvm_requeue_exception);
467
6affcbed 468int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 469{
db8fcefa
AP		 470 if (err)
471 kvm_inject_gp(vcpu, 0);
472 else
6affcbed
KH		 473 return kvm_skip_emulated_instruction(vcpu);
474
475 return 1;
db8fcefa
AP		 476}
477EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 478
6389ee94 479void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 480{
481 ++vcpu->stat.pf_guest;
adfe20fb
WL		 482 vcpu->arch.exception.nested_apf =
483 is_guest_mode(vcpu) && fault->async_page_fault;
484 if (vcpu->arch.exception.nested_apf)
485 vcpu->arch.apf.nested_apf_token = fault->address;
486 else
487 vcpu->arch.cr2 = fault->address;
6389ee94 488 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 489}
27d6c865 490EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 491
ef54bcfe 492static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 493{
6389ee94
AK		 494 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
495 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 496 else
6389ee94 497 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 498
499 return fault->nested_page_fault;
d4f8cf66
JR		 500}
501
3419ffc8
SY		 502void kvm_inject_nmi(struct kvm_vcpu *vcpu)
503{
7460fb4a
AK		 504 atomic_inc(&vcpu->arch.nmi_queued);
505 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 506}
507EXPORT_SYMBOL_GPL(kvm_inject_nmi);
508
298101da
AK		 509void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510{
ce7ddec4 511 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 512}
513EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
514
ce7ddec4
JR		 515void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
516{
517 kvm_multiple_exception(vcpu, nr, true, error_code, true);
518}
519EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
520
0a79b009
AK		 521/*
522 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
523 * a #GP and return false.
524 */
525bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 526{
0a79b009
AK		 527 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
528 return true;
529 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
530 return false;
298101da 531}
0a79b009 532EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 533
16f8a6f9
NA		 534bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
535{
536 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
537 return true;
538
539 kvm_queue_exception(vcpu, UD_VECTOR);
540 return false;
541}
542EXPORT_SYMBOL_GPL(kvm_require_dr);
543
ec92fe44
JR		 544/*
545 * This function will be used to read from the physical memory of the currently
54bf36aa 546 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 547 * can read from guest physical or from the guest's guest physical memory.
548 */
549int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
550 gfn_t ngfn, void *data, int offset, int len,
551 u32 access)
552{
54987b7a 553 struct x86_exception exception;
ec92fe44
JR		 554 gfn_t real_gfn;
555 gpa_t ngpa;
556
557 ngpa = gfn_to_gpa(ngfn);
54987b7a 558 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 559 if (real_gfn == UNMAPPED_GVA)
560 return -EFAULT;
561
562 real_gfn = gpa_to_gfn(real_gfn);
563
54bf36aa 564 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 565}
566EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
567
69b0049a 568static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 569 void *data, int offset, int len, u32 access)
570{
571 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
572 data, offset, len, access);
573}
574
a03490ed
CO		 575/*
576 * Load the pae pdptrs. Return true is they are all valid.
577 */
ff03a073 578int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 579{
580 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
581 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
582 int i;
583 int ret;
ff03a073 584 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 585
ff03a073
JR		 586 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
587 offset * sizeof(u64), sizeof(pdpte),
588 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 589 if (ret < 0) {
590 ret = 0;
591 goto out;
592 }
593 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 594 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 595 (pdpte[i] &
596 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 597 ret = 0;
598 goto out;
599 }
600 }
601 ret = 1;
602
ff03a073 603 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 604 __set_bit(VCPU_EXREG_PDPTR,
605 (unsigned long *)&vcpu->arch.regs_avail);
606 __set_bit(VCPU_EXREG_PDPTR,
607 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 608out:
a03490ed
CO		 609
610 return ret;
611}
cc4b6871 612EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 613
9ed38ffa 614bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 615{
ff03a073 616 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 617 bool changed = true;
3d06b8bf
JR		 618 int offset;
619 gfn_t gfn;
d835dfec
AK		 620 int r;
621
622 if (is_long_mode(vcpu) || !is_pae(vcpu))
623 return false;
624
6de4f3ad
AK		 625 if (!test_bit(VCPU_EXREG_PDPTR,
626 (unsigned long *)&vcpu->arch.regs_avail))
627 return true;
628
a512177e
PB		 629 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
630 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 631 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
632 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 633 if (r < 0)
634 goto out;
ff03a073 635 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 636out:
d835dfec
AK		 637
638 return changed;
639}
9ed38ffa 640EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 641
49a9b07e 642int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 643{
aad82703 644 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 645 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 646
f9a48e6a
AK		 647 cr0 |= X86_CR0_ET;
648
ab344828 649#ifdef CONFIG_X86_64
0f12244f
GN		 650 if (cr0 & 0xffffffff00000000UL)
651 return 1;
ab344828
GN		 652#endif
653
654 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 655
0f12244f
GN		 656 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
657 return 1;
a03490ed 658
0f12244f
GN		 659 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
660 return 1;
a03490ed
CO		 661
662 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
663#ifdef CONFIG_X86_64
f6801dff 664 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 665 int cs_db, cs_l;
666
0f12244f
GN		 667 if (!is_pae(vcpu))
668 return 1;
a03490ed 669 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 670 if (cs_l)
671 return 1;
a03490ed
CO		 672 } else
673#endif
ff03a073 674 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 675 kvm_read_cr3(vcpu)))
0f12244f 676 return 1;
a03490ed
CO		 677 }
678
ad756a16
MJ		 679 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
680 return 1;
681
a03490ed 682 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 683
d170c419 684 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 685 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 686 kvm_async_pf_hash_reset(vcpu);
687 }
e5f3f027 688
aad82703
SY		 689 if ((cr0 ^ old_cr0) & update_bits)
690 kvm_mmu_reset_context(vcpu);
b18d5431 691
879ae188
LE		 692 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
693 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
694 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 695 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
696
0f12244f
GN		 697 return 0;
698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 700
2d3ad1f4 701void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 702{
49a9b07e 703 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 704}
2d3ad1f4 705EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 706
42bdf991
MT		 707static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
708{
709 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
710 !vcpu->guest_xcr0_loaded) {
711 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 712 if (vcpu->arch.xcr0 != host_xcr0)
713 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 714 vcpu->guest_xcr0_loaded = 1;
715 }
716}
717
718static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
719{
720 if (vcpu->guest_xcr0_loaded) {
721 if (vcpu->arch.xcr0 != host_xcr0)
722 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
723 vcpu->guest_xcr0_loaded = 0;
724 }
725}
726
69b0049a 727static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 728{
56c103ec
LJ		 729 u64 xcr0 = xcr;
730 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 731 u64 valid_bits;
2acf923e
DC		 732
733 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
734 if (index != XCR_XFEATURE_ENABLED_MASK)
735 return 1;
d91cab78 736 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 737 return 1;
d91cab78 738 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 739 return 1;
46c34cb0
PB		 740
741 /*
742 * Do not allow the guest to set bits that we do not support
743 * saving. However, xcr0 bit 0 is always set, even if the
744 * emulated CPU does not support XSAVE (see fx_init).
745 */
d91cab78 746 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 747 if (xcr0 & ~valid_bits)
2acf923e 748 return 1;
46c34cb0 749
d91cab78
DH		 750 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
751 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 752 return 1;
753
d91cab78
DH		 754 if (xcr0 & XFEATURE_MASK_AVX512) {
755 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 756 return 1;
d91cab78 757 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 758 return 1;
759 }
2acf923e 760 vcpu->arch.xcr0 = xcr0;
56c103ec 761
d91cab78 762 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 763 kvm_update_cpuid(vcpu);
2acf923e
DC		 764 return 0;
765}
766
767int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
768{
764bcbc5
Z		 769 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
770 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 771 kvm_inject_gp(vcpu, 0);
772 return 1;
773 }
774 return 0;
775}
776EXPORT_SYMBOL_GPL(kvm_set_xcr);
777
a83b29c6 778int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 779{
fc78f519 780 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 781 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 782 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 783
0f12244f
GN		 784 if (cr4 & CR4_RESERVED_BITS)
785 return 1;
a03490ed 786
d6321d49 787 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 788 return 1;
789
d6321d49 790 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 791 return 1;
792
d6321d49 793 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 794 return 1;
795
d6321d49 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 797 return 1;
798
d6321d49 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 800 return 1;
801
fd8cb433 802 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 803 return 1;
804
ae3e61e1
PB		 805 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
806 return 1;
807
a03490ed 808 if (is_long_mode(vcpu)) {
0f12244f
GN		 809 if (!(cr4 & X86_CR4_PAE))
810 return 1;
a2edf57f
AK		 811 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
812 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 813 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
814 kvm_read_cr3(vcpu)))
0f12244f
GN		 815 return 1;
816
ad756a16 817 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 818 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 819 return 1;
820
821 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
822 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
823 return 1;
824 }
825
5e1746d6 826 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 827 return 1;
a03490ed 828
ad756a16
MJ		 829 if (((cr4 ^ old_cr4) & pdptr_bits) ||
830 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 831 kvm_mmu_reset_context(vcpu);
0f12244f 832
b9baba86 833 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 834 kvm_update_cpuid(vcpu);
2acf923e 835
0f12244f
GN		 836 return 0;
837}
2d3ad1f4 838EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 839
2390218b 840int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 841{
ac146235 842#ifdef CONFIG_X86_64
9d88fca7 843 cr3 &= ~CR3_PCID_INVD;
ac146235 844#endif
9d88fca7 845
9f8fe504 846 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 847 kvm_mmu_sync_roots(vcpu);
77c3913b 848 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 849 return 0;
d835dfec
AK		 850 }
851
d1cd3ce9
YZ		 852 if (is_long_mode(vcpu) &&
853 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
854 return 1;
855 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 856 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 857 return 1;
a03490ed 858
0f12244f 859 vcpu->arch.cr3 = cr3;
aff48baa 860 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 861 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 862 return 0;
863}
2d3ad1f4 864EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 865
eea1cff9 866int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 867{
0f12244f
GN		 868 if (cr8 & CR8_RESERVED_BITS)
869 return 1;
35754c98 870 if (lapic_in_kernel(vcpu))
a03490ed
CO		 871 kvm_lapic_set_tpr(vcpu, cr8);
872 else
ad312c7c 873 vcpu->arch.cr8 = cr8;
0f12244f
GN		 874 return 0;
875}
2d3ad1f4 876EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 877
2d3ad1f4 878unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 879{
35754c98 880 if (lapic_in_kernel(vcpu))
a03490ed
CO		 881 return kvm_lapic_get_cr8(vcpu);
882 else
ad312c7c 883 return vcpu->arch.cr8;
a03490ed 884}
2d3ad1f4 885EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 886
ae561ede
NA		 887static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
888{
889 int i;
890
891 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
892 for (i = 0; i < KVM_NR_DB_REGS; i++)
893 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
894 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
895 }
896}
897
73aaf249
JK		 898static void kvm_update_dr6(struct kvm_vcpu *vcpu)
899{
900 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
901 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
902}
903
c8639010
JK		 904static void kvm_update_dr7(struct kvm_vcpu *vcpu)
905{
906 unsigned long dr7;
907
908 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
909 dr7 = vcpu->arch.guest_debug_dr7;
910 else
911 dr7 = vcpu->arch.dr7;
912 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 913 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
914 if (dr7 & DR7_BP_EN_MASK)
915 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 916}
917
6f43ed01
NA		 918static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
919{
920 u64 fixed = DR6_FIXED_1;
921
d6321d49 922 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 923 fixed |= DR6_RTM;
924 return fixed;
925}
926
338dbc97 927static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 928{
929 switch (dr) {
930 case 0 ... 3:
931 vcpu->arch.db[dr] = val;
932 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
933 vcpu->arch.eff_db[dr] = val;
934 break;
935 case 4:
020df079
GN		 936 /* fall through */
937 case 6:
338dbc97
GN		 938 if (val & 0xffffffff00000000ULL)
939 return -1; /* #GP */
6f43ed01 940 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 941 kvm_update_dr6(vcpu);
020df079
GN		 942 break;
943 case 5:
020df079
GN		 944 /* fall through */
945 default: /* 7 */
338dbc97
GN		 946 if (val & 0xffffffff00000000ULL)
947 return -1; /* #GP */
020df079 948 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 949 kvm_update_dr7(vcpu);
020df079
GN		 950 break;
951 }
952
953 return 0;
954}
338dbc97
GN		 955
956int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
957{
16f8a6f9 958 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 959 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 960 return 1;
961 }
962 return 0;
338dbc97 963}
020df079
GN		 964EXPORT_SYMBOL_GPL(kvm_set_dr);
965
16f8a6f9 966int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 967{
968 switch (dr) {
969 case 0 ... 3:
970 *val = vcpu->arch.db[dr];
971 break;
972 case 4:
020df079
GN		 973 /* fall through */
974 case 6:
73aaf249
JK		 975 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
976 *val = vcpu->arch.dr6;
977 else
978 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 979 break;
980 case 5:
020df079
GN		 981 /* fall through */
982 default: /* 7 */
983 *val = vcpu->arch.dr7;
984 break;
985 }
338dbc97
GN		 986 return 0;
987}
020df079
GN		 988EXPORT_SYMBOL_GPL(kvm_get_dr);
989
022cd0e8
AK		 990bool kvm_rdpmc(struct kvm_vcpu *vcpu)
991{
992 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
993 u64 data;
994 int err;
995
c6702c9d 996 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 997 if (err)
998 return err;
999 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1000 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1001 return err;
1002}
1003EXPORT_SYMBOL_GPL(kvm_rdpmc);
1004
043405e1
CO		 1005/*
1006 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1007 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1008 *
1009 * This list is modified at module load time to reflect the
e3267cbb 1010 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1011 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1012 * may depend on host virtualization features rather than host cpu features.
043405e1 1013 */
e3267cbb 1014
043405e1
CO		 1015static u32 msrs_to_save[] = {
1016 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1017 MSR_STAR,
043405e1
CO		 1018#ifdef CONFIG_X86_64
1019 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1020#endif
b3897a49 1021 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1022 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1023 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1024};
1025
1026static unsigned num_msrs_to_save;
1027
62ef68bb
PB		 1028static u32 emulated_msrs[] = {
1029 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1030 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1031 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1032 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1033 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1034 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1035 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1036 HV_X64_MSR_RESET,
11c4b1ca 1037 HV_X64_MSR_VP_INDEX,
9eec50b8 1038 HV_X64_MSR_VP_RUNTIME,
5c919412 1039 HV_X64_MSR_SCONTROL,
1f4b34f8 1040 HV_X64_MSR_STIMER0_CONFIG,
a2e164e7
VK		 1041 HV_X64_MSR_APIC_ASSIST_PAGE,
1042 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1043 HV_X64_MSR_TSC_EMULATION_STATUS,
1044
1045 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1046 MSR_KVM_PV_EOI_EN,
1047
ba904635 1048 MSR_IA32_TSC_ADJUST,
a3e06bbe 1049 MSR_IA32_TSCDEADLINE,
043405e1 1050 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1051 MSR_IA32_MCG_STATUS,
1052 MSR_IA32_MCG_CTL,
c45dcc71 1053 MSR_IA32_MCG_EXT_CTL,
64d60670 1054 MSR_IA32_SMBASE,
52797bf9 1055 MSR_SMI_COUNT,
db2336a8
KH		 1056 MSR_PLATFORM_INFO,
1057 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1058};
1059
62ef68bb
PB		 1060static unsigned num_emulated_msrs;
1061
801e459a
TL		 1062/*
1063 * List of msr numbers which are used to expose MSR-based features that
1064 * can be used by a hypervisor to validate requested CPU features.
1065 */
1066static u32 msr_based_features[] = {
1389309c
PB		 1067 MSR_IA32_VMX_BASIC,
1068 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1069 MSR_IA32_VMX_PINBASED_CTLS,
1070 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1071 MSR_IA32_VMX_PROCBASED_CTLS,
1072 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1073 MSR_IA32_VMX_EXIT_CTLS,
1074 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1075 MSR_IA32_VMX_ENTRY_CTLS,
1076 MSR_IA32_VMX_MISC,
1077 MSR_IA32_VMX_CR0_FIXED0,
1078 MSR_IA32_VMX_CR0_FIXED1,
1079 MSR_IA32_VMX_CR4_FIXED0,
1080 MSR_IA32_VMX_CR4_FIXED1,
1081 MSR_IA32_VMX_VMCS_ENUM,
1082 MSR_IA32_VMX_PROCBASED_CTLS2,
1083 MSR_IA32_VMX_EPT_VPID_CAP,
1084 MSR_IA32_VMX_VMFUNC,
1085
d1d93fa9 1086 MSR_F10H_DECFG,
518e7b94 1087 MSR_IA32_UCODE_REV,
801e459a
TL		 1088};
1089
1090static unsigned int num_msr_based_features;
1091
66421c1e
WL		 1092static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1093{
1094 switch (msr->index) {
518e7b94
WL		 1095 case MSR_IA32_UCODE_REV:
1096 rdmsrl(msr->index, msr->data);
1097 break;
66421c1e
WL		 1098 default:
1099 if (kvm_x86_ops->get_msr_feature(msr))
1100 return 1;
1101 }
1102 return 0;
1103}
1104
801e459a
TL		 1105static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1106{
1107 struct kvm_msr_entry msr;
66421c1e 1108 int r;
801e459a
TL		 1109
1110 msr.index = index;
66421c1e
WL		 1111 r = kvm_get_msr_feature(&msr);
1112 if (r)
1113 return r;
801e459a
TL		 1114
1115 *data = msr.data;
1116
1117 return 0;
1118}
1119
384bb783 1120bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1121{
b69e8cae 1122 if (efer & efer_reserved_bits)
384bb783 1123 return false;
15c4a640 1124
1b4d56b8 1125 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1126 return false;
1b2fd70c 1127
1b4d56b8 1128 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1129 return false;
d8017474 1130
384bb783
JK		 1131 return true;
1132}
1133EXPORT_SYMBOL_GPL(kvm_valid_efer);
1134
1135static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1136{
1137 u64 old_efer = vcpu->arch.efer;
1138
1139 if (!kvm_valid_efer(vcpu, efer))
1140 return 1;
1141
1142 if (is_paging(vcpu)
1143 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1144 return 1;
1145
15c4a640 1146 efer &= ~EFER_LMA;
f6801dff 1147 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1148
a3d204e2
SY		 1149 kvm_x86_ops->set_efer(vcpu, efer);
1150
aad82703
SY		 1151 /* Update reserved bits */
1152 if ((efer ^ old_efer) & EFER_NX)
1153 kvm_mmu_reset_context(vcpu);
1154
b69e8cae 1155 return 0;
15c4a640
CO		 1156}
1157
f2b4b7dd
JR		 1158void kvm_enable_efer_bits(u64 mask)
1159{
1160 efer_reserved_bits &= ~mask;
1161}
1162EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1163
15c4a640
CO		 1164/*
1165 * Writes msr value into into the appropriate "register".
1166 * Returns 0 on success, non-0 otherwise.
1167 * Assumes vcpu_load() was already called.
1168 */
8fe8ab46 1169int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1170{
854e8bb1
NA		 1171 switch (msr->index) {
1172 case MSR_FS_BASE:
1173 case MSR_GS_BASE:
1174 case MSR_KERNEL_GS_BASE:
1175 case MSR_CSTAR:
1176 case MSR_LSTAR:
fd8cb433 1177 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1178 return 1;
1179 break;
1180 case MSR_IA32_SYSENTER_EIP:
1181 case MSR_IA32_SYSENTER_ESP:
1182 /*
1183 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1184 * non-canonical address is written on Intel but not on
1185 * AMD (which ignores the top 32-bits, because it does
1186 * not implement 64-bit SYSENTER).
1187 *
1188 * 64-bit code should hence be able to write a non-canonical
1189 * value on AMD. Making the address canonical ensures that
1190 * vmentry does not fail on Intel after writing a non-canonical
1191 * value, and that something deterministic happens if the guest
1192 * invokes 64-bit SYSENTER.
1193 */
fd8cb433 1194 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1195 }
8fe8ab46 1196 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1197}
854e8bb1 1198EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1199
313a3dc7
CO		 1200/*
1201 * Adapt set_msr() to msr_io()'s calling convention
1202 */
609e36d3
PB		 1203static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1204{
1205 struct msr_data msr;
1206 int r;
1207
1208 msr.index = index;
1209 msr.host_initiated = true;
1210 r = kvm_get_msr(vcpu, &msr);
1211 if (r)
1212 return r;
1213
1214 *data = msr.data;
1215 return 0;
1216}
1217
313a3dc7
CO		 1218static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1219{
8fe8ab46
WA		 1220 struct msr_data msr;
1221
1222 msr.data = *data;
1223 msr.index = index;
1224 msr.host_initiated = true;
1225 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1226}
1227
16e8d74d
MT		 1228#ifdef CONFIG_X86_64
1229struct pvclock_gtod_data {
1230 seqcount_t seq;
1231
1232 struct { /* extract of a clocksource struct */
1233 int vclock_mode;
a5a1d1c2
TG		 1234 u64 cycle_last;
1235 u64 mask;
16e8d74d
MT		 1236 u32 mult;
1237 u32 shift;
1238 } clock;
1239
cbcf2dd3
TG		 1240 u64 boot_ns;
1241 u64 nsec_base;
55dd00a7 1242 u64 wall_time_sec;
16e8d74d
MT		 1243};
1244
1245static struct pvclock_gtod_data pvclock_gtod_data;
1246
1247static void update_pvclock_gtod(struct timekeeper *tk)
1248{
1249 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1250 u64 boot_ns;
1251
876e7881 1252 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1253
1254 write_seqcount_begin(&vdata->seq);
1255
1256 /* copy pvclock gtod data */
876e7881
PZ		 1257 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1258 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1259 vdata->clock.mask = tk->tkr_mono.mask;
1260 vdata->clock.mult = tk->tkr_mono.mult;
1261 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1262
cbcf2dd3 1263 vdata->boot_ns = boot_ns;
876e7881 1264 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1265
55dd00a7
MT		 1266 vdata->wall_time_sec = tk->xtime_sec;
1267
16e8d74d
MT		 1268 write_seqcount_end(&vdata->seq);
1269}
1270#endif
1271
bab5bb39
NK		 1272void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1273{
1274 /*
1275 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1276 * vcpu_enter_guest. This function is only called from
1277 * the physical CPU that is running vcpu.
1278 */
1279 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1280}
16e8d74d 1281
18068523
GOC		 1282static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1283{
9ed3c444
AK		 1284 int version;
1285 int r;
50d0a0f9 1286 struct pvclock_wall_clock wc;
87aeb54f 1287 struct timespec64 boot;
18068523
GOC		 1288
1289 if (!wall_clock)
1290 return;
1291
9ed3c444
AK		 1292 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1293 if (r)
1294 return;
1295
1296 if (version & 1)
1297 ++version; /* first time write, random junk */
1298
1299 ++version;
18068523 1300
1dab1345
NK		 1301 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1302 return;
18068523 1303
50d0a0f9
GH		 1304 /*
1305 * The guest calculates current wall clock time by adding
34c238a1 1306 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1307 * wall clock specified here. guest system time equals host
1308 * system time for us, thus we must fill in host boot time here.
1309 */
87aeb54f 1310 getboottime64(&boot);
50d0a0f9 1311
4b648665 1312 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1313 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1314 boot = timespec64_sub(boot, ts);
4b648665 1315 }
87aeb54f 1316 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1317 wc.nsec = boot.tv_nsec;
1318 wc.version = version;
18068523
GOC		 1319
1320 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1321
1322 version++;
1323 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1324}
1325
50d0a0f9
GH		 1326static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1327{
b51012de
PB		 1328 do_shl32_div32(dividend, divisor);
1329 return dividend;
50d0a0f9
GH		 1330}
1331
3ae13faa 1332static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1333 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1334{
5f4e3f88 1335 uint64_t scaled64;
50d0a0f9
GH		 1336 int32_t shift = 0;
1337 uint64_t tps64;
1338 uint32_t tps32;
1339
3ae13faa
PB		 1340 tps64 = base_hz;
1341 scaled64 = scaled_hz;
50933623 1342 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1343 tps64 >>= 1;
1344 shift--;
1345 }
1346
1347 tps32 = (uint32_t)tps64;
50933623
JK		 1348 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1349 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1350 scaled64 >>= 1;
1351 else
1352 tps32 <<= 1;
50d0a0f9
GH		 1353 shift++;
1354 }
1355
5f4e3f88
ZA		 1356 *pshift = shift;
1357 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1358
3ae13faa
PB		 1359 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1360 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1361}
1362
d828199e 1363#ifdef CONFIG_X86_64
16e8d74d 1364static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1365#endif
16e8d74d 1366
c8076604 1367static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1368static unsigned long max_tsc_khz;
c8076604 1369
cc578287 1370static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1371{
cc578287
ZA		 1372 u64 v = (u64)khz * (1000000 + ppm);
1373 do_div(v, 1000000);
1374 return v;
1e993611
JR		 1375}
1376
381d585c
HZ		 1377static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1378{
1379 u64 ratio;
1380
1381 /* Guest TSC same frequency as host TSC? */
1382 if (!scale) {
1383 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1384 return 0;
1385 }
1386
1387 /* TSC scaling supported? */
1388 if (!kvm_has_tsc_control) {
1389 if (user_tsc_khz > tsc_khz) {
1390 vcpu->arch.tsc_catchup = 1;
1391 vcpu->arch.tsc_always_catchup = 1;
1392 return 0;
1393 } else {
1394 WARN(1, "user requested TSC rate below hardware speed\n");
1395 return -1;
1396 }
1397 }
1398
1399 /* TSC scaling required - calculate ratio */
1400 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1401 user_tsc_khz, tsc_khz);
1402
1403 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1404 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1405 user_tsc_khz);
1406 return -1;
1407 }
1408
1409 vcpu->arch.tsc_scaling_ratio = ratio;
1410 return 0;
1411}
1412
4941b8cb 1413static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1414{
cc578287
ZA		 1415 u32 thresh_lo, thresh_hi;
1416 int use_scaling = 0;
217fc9cf 1417
03ba32ca 1418 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1419 if (user_tsc_khz == 0) {
ad721883
HZ		 1420 /* set tsc_scaling_ratio to a safe value */
1421 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1422 return -1;
ad721883 1423 }
03ba32ca 1424
c285545f 1425 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1426 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1427 &vcpu->arch.virtual_tsc_shift,
1428 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1429 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1430
1431 /*
1432 * Compute the variation in TSC rate which is acceptable
1433 * within the range of tolerance and decide if the
1434 * rate being applied is within that bounds of the hardware
1435 * rate. If so, no scaling or compensation need be done.
1436 */
1437 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1438 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1439 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1440 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1441 use_scaling = 1;
1442 }
4941b8cb 1443 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1444}
1445
1446static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1447{
e26101b1 1448 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1449 vcpu->arch.virtual_tsc_mult,
1450 vcpu->arch.virtual_tsc_shift);
e26101b1 1451 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1452 return tsc;
1453}
1454
b0c39dc6
VK		 1455static inline int gtod_is_based_on_tsc(int mode)
1456{
1457 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1458}
1459
69b0049a 1460static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1461{
1462#ifdef CONFIG_X86_64
1463 bool vcpus_matched;
b48aa97e
MT		 1464 struct kvm_arch *ka = &vcpu->kvm->arch;
1465 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1466
1467 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1468 atomic_read(&vcpu->kvm->online_vcpus));
1469
7f187922
MT		 1470 /*
1471 * Once the masterclock is enabled, always perform request in
1472 * order to update it.
1473 *
1474 * In order to enable masterclock, the host clocksource must be TSC
1475 * and the vcpus need to have matched TSCs. When that happens,
1476 * perform request to enable masterclock.
1477 */
1478 if (ka->use_master_clock ||
b0c39dc6 1479 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1480 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1481
1482 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1483 atomic_read(&vcpu->kvm->online_vcpus),
1484 ka->use_master_clock, gtod->clock.vclock_mode);
1485#endif
1486}
1487
ba904635
WA		 1488static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1489{
3e3f5026 1490 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1491 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1492}
1493
35181e86
HZ		 1494/*
1495 * Multiply tsc by a fixed point number represented by ratio.
1496 *
1497 * The most significant 64-N bits (mult) of ratio represent the
1498 * integral part of the fixed point number; the remaining N bits
1499 * (frac) represent the fractional part, ie. ratio represents a fixed
1500 * point number (mult + frac * 2^(-N)).
1501 *
1502 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1503 */
1504static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1505{
1506 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1507}
1508
1509u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1510{
1511 u64 _tsc = tsc;
1512 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1513
1514 if (ratio != kvm_default_tsc_scaling_ratio)
1515 _tsc = __scale_tsc(ratio, tsc);
1516
1517 return _tsc;
1518}
1519EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1520
07c1419a
HZ		 1521static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1522{
1523 u64 tsc;
1524
1525 tsc = kvm_scale_tsc(vcpu, rdtsc());
1526
1527 return target_tsc - tsc;
1528}
1529
4ba76538
HZ		 1530u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1531{
ea26e4ec 1532 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1533}
1534EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1535
a545ab6a
LC		 1536static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1537{
1538 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1539 vcpu->arch.tsc_offset = offset;
1540}
1541
b0c39dc6
VK		 1542static inline bool kvm_check_tsc_unstable(void)
1543{
1544#ifdef CONFIG_X86_64
1545 /*
1546 * TSC is marked unstable when we're running on Hyper-V,
1547 * 'TSC page' clocksource is good.
1548 */
1549 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1550 return false;
1551#endif
1552 return check_tsc_unstable();
1553}
1554
8fe8ab46 1555void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1556{
1557 struct kvm *kvm = vcpu->kvm;
f38e098f 1558 u64 offset, ns, elapsed;
99e3e30a 1559 unsigned long flags;
b48aa97e 1560 bool matched;
0d3da0d2 1561 bool already_matched;
8fe8ab46 1562 u64 data = msr->data;
c5e8ec8e 1563 bool synchronizing = false;
99e3e30a 1564
038f8c11 1565 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1566 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1567 ns = ktime_get_boot_ns();
f38e098f 1568 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1569
03ba32ca 1570 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1571 if (data == 0 && msr->host_initiated) {
1572 /*
1573 * detection of vcpu initialization -- need to sync
1574 * with other vCPUs. This particularly helps to keep
1575 * kvm_clock stable after CPU hotplug
1576 */
1577 synchronizing = true;
1578 } else {
1579 u64 tsc_exp = kvm->arch.last_tsc_write +
1580 nsec_to_cycles(vcpu, elapsed);
1581 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1582 /*
1583 * Special case: TSC write with a small delta (1 second)
1584 * of virtual cycle time against real time is
1585 * interpreted as an attempt to synchronize the CPU.
1586 */
1587 synchronizing = data < tsc_exp + tsc_hz &&
1588 data + tsc_hz > tsc_exp;
1589 }
c5e8ec8e 1590 }
f38e098f
ZA		 1591
1592 /*
5d3cb0f6
ZA		 1593 * For a reliable TSC, we can match TSC offsets, and for an unstable
1594 * TSC, we add elapsed time in this computation. We could let the
1595 * compensation code attempt to catch up if we fall behind, but
1596 * it's better to try to match offsets from the beginning.
1597 */
c5e8ec8e 1598 if (synchronizing &&
5d3cb0f6 1599 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1600 if (!kvm_check_tsc_unstable()) {
e26101b1 1601 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1602 pr_debug("kvm: matched tsc offset for %llu\n", data);
1603 } else {
857e4099 1604 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1605 data += delta;
07c1419a 1606 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1607 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1608 }
b48aa97e 1609 matched = true;
0d3da0d2 1610 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1611 } else {
1612 /*
1613 * We split periods of matched TSC writes into generations.
1614 * For each generation, we track the original measured
1615 * nanosecond time, offset, and write, so if TSCs are in
1616 * sync, we can match exact offset, and if not, we can match
4a969980 1617 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1618 *
1619 * These values are tracked in kvm->arch.cur_xxx variables.
1620 */
1621 kvm->arch.cur_tsc_generation++;
1622 kvm->arch.cur_tsc_nsec = ns;
1623 kvm->arch.cur_tsc_write = data;
1624 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1625 matched = false;
0d3da0d2 1626 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1627 kvm->arch.cur_tsc_generation, data);
f38e098f 1628 }
e26101b1
ZA		 1629
1630 /*
1631 * We also track th most recent recorded KHZ, write and time to
1632 * allow the matching interval to be extended at each write.
1633 */
f38e098f
ZA		 1634 kvm->arch.last_tsc_nsec = ns;
1635 kvm->arch.last_tsc_write = data;
5d3cb0f6 1636 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1637
b183aa58 1638 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1639
1640 /* Keep track of which generation this VCPU has synchronized to */
1641 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1642 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1643 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1644
d6321d49 1645 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1646 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1647
a545ab6a 1648 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1649 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1650
1651 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1652 if (!matched) {
b48aa97e 1653 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1654 } else if (!already_matched) {
1655 kvm->arch.nr_vcpus_matched_tsc++;
1656 }
b48aa97e
MT		 1657
1658 kvm_track_tsc_matching(vcpu);
1659 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1660}
e26101b1 1661
99e3e30a
ZA		 1662EXPORT_SYMBOL_GPL(kvm_write_tsc);
1663
58ea6767
HZ		 1664static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1665 s64 adjustment)
1666{
ea26e4ec 1667 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1668}
1669
1670static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1671{
1672 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1673 WARN_ON(adjustment < 0);
1674 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1675 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1676}
1677
d828199e
MT		 1678#ifdef CONFIG_X86_64
1679
a5a1d1c2 1680static u64 read_tsc(void)
d828199e 1681{
a5a1d1c2 1682 u64 ret = (u64)rdtsc_ordered();
03b9730b 1683 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1684
1685 if (likely(ret >= last))
1686 return ret;
1687
1688 /*
1689 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1690 * predictable (it's just a function of time and the likely is
d828199e
MT		 1691 * very likely) and there's a data dependence, so force GCC
1692 * to generate a branch instead. I don't barrier() because
1693 * we don't actually need a barrier, and if this function
1694 * ever gets inlined it will generate worse code.
1695 */
1696 asm volatile ("");
1697 return last;
1698}
1699
b0c39dc6 1700static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1701{
1702 long v;
1703 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1704 u64 tsc_pg_val;
1705
1706 switch (gtod->clock.vclock_mode) {
1707 case VCLOCK_HVCLOCK:
1708 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1709 tsc_timestamp);
1710 if (tsc_pg_val != U64_MAX) {
1711 /* TSC page valid */
1712 *mode = VCLOCK_HVCLOCK;
1713 v = (tsc_pg_val - gtod->clock.cycle_last) &
1714 gtod->clock.mask;
1715 } else {
1716 /* TSC page invalid */
1717 *mode = VCLOCK_NONE;
1718 }
1719 break;
1720 case VCLOCK_TSC:
1721 *mode = VCLOCK_TSC;
1722 *tsc_timestamp = read_tsc();
1723 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1724 gtod->clock.mask;
1725 break;
1726 default:
1727 *mode = VCLOCK_NONE;
1728 }
d828199e 1729
b0c39dc6
VK		 1730 if (*mode == VCLOCK_NONE)
1731 *tsc_timestamp = v = 0;
d828199e 1732
d828199e
MT		 1733 return v * gtod->clock.mult;
1734}
1735
b0c39dc6 1736static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1737{
cbcf2dd3 1738 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1739 unsigned long seq;
d828199e 1740 int mode;
cbcf2dd3 1741 u64 ns;
d828199e 1742
d828199e
MT		 1743 do {
1744 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1745 ns = gtod->nsec_base;
b0c39dc6 1746 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1747 ns >>= gtod->clock.shift;
cbcf2dd3 1748 ns += gtod->boot_ns;
d828199e 1749 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1750 *t = ns;
d828199e
MT		 1751
1752 return mode;
1753}
1754
b0c39dc6 1755static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1756{
1757 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1758 unsigned long seq;
1759 int mode;
1760 u64 ns;
1761
1762 do {
1763 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1764 ts->tv_sec = gtod->wall_time_sec;
1765 ns = gtod->nsec_base;
b0c39dc6 1766 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1767 ns >>= gtod->clock.shift;
1768 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1769
1770 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1771 ts->tv_nsec = ns;
1772
1773 return mode;
1774}
1775
b0c39dc6
VK		 1776/* returns true if host is using TSC based clocksource */
1777static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1778{
d828199e 1779 /* checked again under seqlock below */
b0c39dc6 1780 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1781 return false;
1782
b0c39dc6
VK		 1783 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1784 tsc_timestamp));
d828199e 1785}
55dd00a7 1786
b0c39dc6 1787/* returns true if host is using TSC based clocksource */
55dd00a7 1788static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1789 u64 *tsc_timestamp)
55dd00a7
MT		 1790{
1791 /* checked again under seqlock below */
b0c39dc6 1792 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1793 return false;
1794
b0c39dc6 1795 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1796}
d828199e
MT		 1797#endif
1798
1799/*
1800 *
b48aa97e
MT		 1801 * Assuming a stable TSC across physical CPUS, and a stable TSC
1802 * across virtual CPUs, the following condition is possible.
1803 * Each numbered line represents an event visible to both
d828199e
MT		 1804 * CPUs at the next numbered event.
1805 *
1806 * "timespecX" represents host monotonic time. "tscX" represents
1807 * RDTSC value.
1808 *
1809 * VCPU0 on CPU0 | VCPU1 on CPU1
1810 *
1811 * 1. read timespec0,tsc0
1812 * 2. | timespec1 = timespec0 + N
1813 * | tsc1 = tsc0 + M
1814 * 3. transition to guest | transition to guest
1815 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1816 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1817 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1818 *
1819 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1820 *
1821 * - ret0 < ret1
1822 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1823 * ...
1824 * - 0 < N - M => M < N
1825 *
1826 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1827 * always the case (the difference between two distinct xtime instances
1828 * might be smaller then the difference between corresponding TSC reads,
1829 * when updating guest vcpus pvclock areas).
1830 *
1831 * To avoid that problem, do not allow visibility of distinct
1832 * system_timestamp/tsc_timestamp values simultaneously: use a master
1833 * copy of host monotonic time values. Update that master copy
1834 * in lockstep.
1835 *
b48aa97e 1836 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1837 *
1838 */
1839
1840static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1841{
1842#ifdef CONFIG_X86_64
1843 struct kvm_arch *ka = &kvm->arch;
1844 int vclock_mode;
b48aa97e
MT		 1845 bool host_tsc_clocksource, vcpus_matched;
1846
1847 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1848 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1849
1850 /*
1851 * If the host uses TSC clock, then passthrough TSC as stable
1852 * to the guest.
1853 */
b48aa97e 1854 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1855 &ka->master_kernel_ns,
1856 &ka->master_cycle_now);
1857
16a96021 1858 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1859 && !ka->backwards_tsc_observed
54750f2c 1860 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1861
d828199e
MT		 1862 if (ka->use_master_clock)
1863 atomic_set(&kvm_guest_has_master_clock, 1);
1864
1865 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1866 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1867 vcpus_matched);
d828199e
MT		 1868#endif
1869}
1870
2860c4b1
PB		 1871void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1872{
1873 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1874}
1875
2e762ff7
MT		 1876static void kvm_gen_update_masterclock(struct kvm *kvm)
1877{
1878#ifdef CONFIG_X86_64
1879 int i;
1880 struct kvm_vcpu *vcpu;
1881 struct kvm_arch *ka = &kvm->arch;
1882
1883 spin_lock(&ka->pvclock_gtod_sync_lock);
1884 kvm_make_mclock_inprogress_request(kvm);
1885 /* no guest entries from this point */
1886 pvclock_update_vm_gtod_copy(kvm);
1887
1888 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1889 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1890
1891 /* guest entries allowed */
1892 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1893 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1894
1895 spin_unlock(&ka->pvclock_gtod_sync_lock);
1896#endif
1897}
1898
e891a32e 1899u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1900{
108b249c 1901 struct kvm_arch *ka = &kvm->arch;
8b953440 1902 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1903 u64 ret;
108b249c 1904
8b953440
PB		 1905 spin_lock(&ka->pvclock_gtod_sync_lock);
1906 if (!ka->use_master_clock) {
1907 spin_unlock(&ka->pvclock_gtod_sync_lock);
1908 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1909 }
1910
8b953440
PB		 1911 hv_clock.tsc_timestamp = ka->master_cycle_now;
1912 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1913 spin_unlock(&ka->pvclock_gtod_sync_lock);
1914
e2c2206a
WL		 1915 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1916 get_cpu();
1917
e70b57a6
WL		 1918 if (__this_cpu_read(cpu_tsc_khz)) {
1919 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1920 &hv_clock.tsc_shift,
1921 &hv_clock.tsc_to_system_mul);
1922 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1923 } else
1924 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1925
1926 put_cpu();
1927
1928 return ret;
108b249c
PB		 1929}
1930
0d6dd2ff
PB		 1931static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1932{
1933 struct kvm_vcpu_arch *vcpu = &v->arch;
1934 struct pvclock_vcpu_time_info guest_hv_clock;
1935
4e335d9e 1936 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1937 &guest_hv_clock, sizeof(guest_hv_clock))))
1938 return;
1939
1940 /* This VCPU is paused, but it's legal for a guest to read another
1941 * VCPU's kvmclock, so we really have to follow the specification where
1942 * it says that version is odd if data is being modified, and even after
1943 * it is consistent.
1944 *
1945 * Version field updates must be kept separate. This is because
1946 * kvm_write_guest_cached might use a "rep movs" instruction, and
1947 * writes within a string instruction are weakly ordered. So there
1948 * are three writes overall.
1949 *
1950 * As a small optimization, only write the version field in the first
1951 * and third write. The vcpu->pv_time cache is still valid, because the
1952 * version field is the first in the struct.
1953 */
1954 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1955
51c4b8bb
LA		 1956 if (guest_hv_clock.version & 1)
1957 ++guest_hv_clock.version; /* first time write, random junk */
1958
0d6dd2ff 1959 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1960 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1961 &vcpu->hv_clock,
1962 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1963
1964 smp_wmb();
1965
1966 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1967 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1968
1969 if (vcpu->pvclock_set_guest_stopped_request) {
1970 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1971 vcpu->pvclock_set_guest_stopped_request = false;
1972 }
1973
1974 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1975
4e335d9e
PB		 1976 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1977 &vcpu->hv_clock,
1978 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1979
1980 smp_wmb();
1981
1982 vcpu->hv_clock.version++;
4e335d9e
PB		 1983 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1984 &vcpu->hv_clock,
1985 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1986}
1987
34c238a1 1988static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1989{
78db6a50 1990 unsigned long flags, tgt_tsc_khz;
18068523 1991 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1992 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1993 s64 kernel_ns;
d828199e 1994 u64 tsc_timestamp, host_tsc;
51d59c6b 1995 u8 pvclock_flags;
d828199e
MT		 1996 bool use_master_clock;
1997
1998 kernel_ns = 0;
1999 host_tsc = 0;
18068523 2000
d828199e
MT		 2001 /*
2002 * If the host uses TSC clock, then passthrough TSC as stable
2003 * to the guest.
2004 */
2005 spin_lock(&ka->pvclock_gtod_sync_lock);
2006 use_master_clock = ka->use_master_clock;
2007 if (use_master_clock) {
2008 host_tsc = ka->master_cycle_now;
2009 kernel_ns = ka->master_kernel_ns;
2010 }
2011 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2012
2013 /* Keep irq disabled to prevent changes to the clock */
2014 local_irq_save(flags);
78db6a50
PB		 2015 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2016 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2017 local_irq_restore(flags);
2018 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2019 return 1;
2020 }
d828199e 2021 if (!use_master_clock) {
4ea1636b 2022 host_tsc = rdtsc();
108b249c 2023 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2024 }
2025
4ba76538 2026 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2027
c285545f
ZA		 2028 /*
2029 * We may have to catch up the TSC to match elapsed wall clock
2030 * time for two reasons, even if kvmclock is used.
2031 * 1) CPU could have been running below the maximum TSC rate
2032 * 2) Broken TSC compensation resets the base at each VCPU
2033 * entry to avoid unknown leaps of TSC even when running
2034 * again on the same CPU. This may cause apparent elapsed
2035 * time to disappear, and the guest to stand still or run
2036 * very slowly.
2037 */
2038 if (vcpu->tsc_catchup) {
2039 u64 tsc = compute_guest_tsc(v, kernel_ns);
2040 if (tsc > tsc_timestamp) {
f1e2b260 2041 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2042 tsc_timestamp = tsc;
2043 }
50d0a0f9
GH		 2044 }
2045
18068523
GOC		 2046 local_irq_restore(flags);
2047
0d6dd2ff 2048 /* With all the info we got, fill in the values */
18068523 2049
78db6a50
PB		 2050 if (kvm_has_tsc_control)
2051 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2052
2053 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2054 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2055 &vcpu->hv_clock.tsc_shift,
2056 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2057 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2058 }
2059
1d5f066e 2060 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2061 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2062 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2063
d828199e 2064 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2065 pvclock_flags = 0;
d828199e
MT		 2066 if (use_master_clock)
2067 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2068
78c0337a
MT		 2069 vcpu->hv_clock.flags = pvclock_flags;
2070
095cf55d
PB		 2071 if (vcpu->pv_time_enabled)
2072 kvm_setup_pvclock_page(v);
2073 if (v == kvm_get_vcpu(v->kvm, 0))
2074 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2075 return 0;
c8076604
GH		 2076}
2077
0061d53d
MT		 2078/*
2079 * kvmclock updates which are isolated to a given vcpu, such as
2080 * vcpu->cpu migration, should not allow system_timestamp from
2081 * the rest of the vcpus to remain static. Otherwise ntp frequency
2082 * correction applies to one vcpu's system_timestamp but not
2083 * the others.
2084 *
2085 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2086 * We need to rate-limit these requests though, as they can
2087 * considerably slow guests that have a large number of vcpus.
2088 * The time for a remote vcpu to update its kvmclock is bound
2089 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2090 */
2091
7e44e449
AJ		 2092#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2093
2094static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2095{
2096 int i;
7e44e449
AJ		 2097 struct delayed_work *dwork = to_delayed_work(work);
2098 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2099 kvmclock_update_work);
2100 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2101 struct kvm_vcpu *vcpu;
2102
2103 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2104 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2105 kvm_vcpu_kick(vcpu);
2106 }
2107}
2108
7e44e449
AJ		 2109static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2110{
2111 struct kvm *kvm = v->kvm;
2112
105b21bb 2113 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2114 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2115 KVMCLOCK_UPDATE_DELAY);
2116}
2117
332967a3
AJ		 2118#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2119
2120static void kvmclock_sync_fn(struct work_struct *work)
2121{
2122 struct delayed_work *dwork = to_delayed_work(work);
2123 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2124 kvmclock_sync_work);
2125 struct kvm *kvm = container_of(ka, struct kvm, arch);
2126
630994b3
MT		 2127 if (!kvmclock_periodic_sync)
2128 return;
2129
332967a3
AJ		 2130 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2131 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2132 KVMCLOCK_SYNC_PERIOD);
2133}
2134
9ffd986c 2135static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2136{
890ca9ae
HY		 2137 u64 mcg_cap = vcpu->arch.mcg_cap;
2138 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2139 u32 msr = msr_info->index;
2140 u64 data = msr_info->data;
890ca9ae 2141
15c4a640 2142 switch (msr) {
15c4a640 2143 case MSR_IA32_MCG_STATUS:
890ca9ae 2144 vcpu->arch.mcg_status = data;
15c4a640 2145 break;
c7ac679c 2146 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2147 if (!(mcg_cap & MCG_CTL_P))
2148 return 1;
2149 if (data != 0 && data != ~(u64)0)
2150 return -1;
2151 vcpu->arch.mcg_ctl = data;
2152 break;
2153 default:
2154 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2155 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2156 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2157 /* only 0 or all 1s can be written to IA32_MCi_CTL
2158 * some Linux kernels though clear bit 10 in bank 4 to
2159 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2160 * this to avoid an uncatched #GP in the guest
2161 */
890ca9ae 2162 if ((offset & 0x3) == 0 &&
114be429 2163 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2164 return -1;
9ffd986c
WL		 2165 if (!msr_info->host_initiated &&
2166 (offset & 0x3) == 1 && data != 0)
2167 return -1;
890ca9ae
HY		 2168 vcpu->arch.mce_banks[offset] = data;
2169 break;
2170 }
2171 return 1;
2172 }
2173 return 0;
2174}
2175
ffde22ac
ES		 2176static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2177{
2178 struct kvm *kvm = vcpu->kvm;
2179 int lm = is_long_mode(vcpu);
2180 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2181 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2182 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2183 : kvm->arch.xen_hvm_config.blob_size_32;
2184 u32 page_num = data & ~PAGE_MASK;
2185 u64 page_addr = data & PAGE_MASK;
2186 u8 *page;
2187 int r;
2188
2189 r = -E2BIG;
2190 if (page_num >= blob_size)
2191 goto out;
2192 r = -ENOMEM;
ff5c2c03
SL		 2193 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2194 if (IS_ERR(page)) {
2195 r = PTR_ERR(page);
ffde22ac 2196 goto out;
ff5c2c03 2197 }
54bf36aa 2198 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2199 goto out_free;
2200 r = 0;
2201out_free:
2202 kfree(page);
2203out:
2204 return r;
2205}
2206
344d9588
GN		 2207static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2208{
2209 gpa_t gpa = data & ~0x3f;
2210
52a5c155
WL		 2211 /* Bits 3:5 are reserved, Should be zero */
2212 if (data & 0x38)
344d9588
GN		 2213 return 1;
2214
2215 vcpu->arch.apf.msr_val = data;
2216
2217 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2218 kvm_clear_async_pf_completion_queue(vcpu);
2219 kvm_async_pf_hash_reset(vcpu);
2220 return 0;
2221 }
2222
4e335d9e 2223 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2224 sizeof(u32)))
344d9588
GN		 2225 return 1;
2226
6adba527 2227 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2228 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2229 kvm_async_pf_wakeup_all(vcpu);
2230 return 0;
2231}
2232
12f9a48f
GC		 2233static void kvmclock_reset(struct kvm_vcpu *vcpu)
2234{
0b79459b 2235 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2236}
2237
f38a7b75
WL		 2238static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2239{
2240 ++vcpu->stat.tlb_flush;
2241 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2242}
2243
c9aaa895
GC		 2244static void record_steal_time(struct kvm_vcpu *vcpu)
2245{
2246 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2247 return;
2248
4e335d9e 2249 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2250 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2251 return;
2252
f38a7b75
WL		 2253 /*
2254 * Doing a TLB flush here, on the guest's behalf, can avoid
2255 * expensive IPIs.
2256 */
2257 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2258 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2259
35f3fae1
WL		 2260 if (vcpu->arch.st.steal.version & 1)
2261 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2262
2263 vcpu->arch.st.steal.version += 1;
2264
4e335d9e 2265 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2266 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2267
2268 smp_wmb();
2269
c54cdf14
LC		 2270 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2271 vcpu->arch.st.last_steal;
2272 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2273
4e335d9e 2274 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2275 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2276
2277 smp_wmb();
2278
2279 vcpu->arch.st.steal.version += 1;
c9aaa895 2280
4e335d9e 2281 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2282 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2283}
2284
8fe8ab46 2285int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2286{
5753785f 2287 bool pr = false;
8fe8ab46
WA		 2288 u32 msr = msr_info->index;
2289 u64 data = msr_info->data;
5753785f 2290
15c4a640 2291 switch (msr) {
2e32b719 2292 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2293 case MSR_IA32_UCODE_WRITE:
2294 case MSR_VM_HSAVE_PA:
2295 case MSR_AMD64_PATCH_LOADER:
2296 case MSR_AMD64_BU_CFG2:
405a353a 2297 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2298 break;
2299
518e7b94
WL		 2300 case MSR_IA32_UCODE_REV:
2301 if (msr_info->host_initiated)
2302 vcpu->arch.microcode_version = data;
2303 break;
15c4a640 2304 case MSR_EFER:
b69e8cae 2305 return set_efer(vcpu, data);
8f1589d9
AP		 2306 case MSR_K7_HWCR:
2307 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2308 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2309 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2310 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2311 if (data != 0) {
a737f256
CD		 2312 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2313 data);
8f1589d9
AP		 2314 return 1;
2315 }
15c4a640 2316 break;
f7c6d140
AP		 2317 case MSR_FAM10H_MMIO_CONF_BASE:
2318 if (data != 0) {
a737f256
CD		 2319 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2320 "0x%llx\n", data);
f7c6d140
AP		 2321 return 1;
2322 }
15c4a640 2323 break;
b5e2fec0
AG		 2324 case MSR_IA32_DEBUGCTLMSR:
2325 if (!data) {
2326 /* We support the non-activated case already */
2327 break;
2328 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2329 /* Values other than LBR and BTF are vendor-specific,
2330 thus reserved and should throw a #GP */
2331 return 1;
2332 }
a737f256
CD		 2333 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2334 __func__, data);
b5e2fec0 2335 break;
9ba075a6 2336 case 0x200 ... 0x2ff:
ff53604b 2337 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2338 case MSR_IA32_APICBASE:
58cb628d 2339 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2340 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2341 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2342 case MSR_IA32_TSCDEADLINE:
2343 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2344 break;
ba904635 2345 case MSR_IA32_TSC_ADJUST:
d6321d49 2346 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2347 if (!msr_info->host_initiated) {
d913b904 2348 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2349 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2350 }
2351 vcpu->arch.ia32_tsc_adjust_msr = data;
2352 }
2353 break;
15c4a640 2354 case MSR_IA32_MISC_ENABLE:
ad312c7c 2355 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2356 break;
64d60670
PB		 2357 case MSR_IA32_SMBASE:
2358 if (!msr_info->host_initiated)
2359 return 1;
2360 vcpu->arch.smbase = data;
2361 break;
52797bf9
LA		 2362 case MSR_SMI_COUNT:
2363 if (!msr_info->host_initiated)
2364 return 1;
2365 vcpu->arch.smi_count = data;
2366 break;
11c6bffa 2367 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2368 case MSR_KVM_WALL_CLOCK:
2369 vcpu->kvm->arch.wall_clock = data;
2370 kvm_write_wall_clock(vcpu->kvm, data);
2371 break;
11c6bffa 2372 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2373 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2374 struct kvm_arch *ka = &vcpu->kvm->arch;
2375
12f9a48f 2376 kvmclock_reset(vcpu);
18068523 2377
54750f2c
MT		 2378 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2379 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2380
2381 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2382 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2383
2384 ka->boot_vcpu_runs_old_kvmclock = tmp;
2385 }
2386
18068523 2387 vcpu->arch.time = data;
0061d53d 2388 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2389
2390 /* we verify if the enable bit is set... */
2391 if (!(data & 1))
2392 break;
2393
4e335d9e 2394 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2395 &vcpu->arch.pv_time, data & ~1ULL,
2396 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2397 vcpu->arch.pv_time_enabled = false;
2398 else
2399 vcpu->arch.pv_time_enabled = true;
32cad84f 2400
18068523
GOC		 2401 break;
2402 }
344d9588
GN		 2403 case MSR_KVM_ASYNC_PF_EN:
2404 if (kvm_pv_enable_async_pf(vcpu, data))
2405 return 1;
2406 break;
c9aaa895
GC		 2407 case MSR_KVM_STEAL_TIME:
2408
2409 if (unlikely(!sched_info_on()))
2410 return 1;
2411
2412 if (data & KVM_STEAL_RESERVED_MASK)
2413 return 1;
2414
4e335d9e 2415 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2416 data & KVM_STEAL_VALID_BITS,
2417 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2418 return 1;
2419
2420 vcpu->arch.st.msr_val = data;
2421
2422 if (!(data & KVM_MSR_ENABLED))
2423 break;
2424
c9aaa895
GC		 2425 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2426
2427 break;
ae7a2a3f
MT		 2428 case MSR_KVM_PV_EOI_EN:
2429 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2430 return 1;
2431 break;
c9aaa895 2432
890ca9ae
HY		 2433 case MSR_IA32_MCG_CTL:
2434 case MSR_IA32_MCG_STATUS:
81760dcc 2435 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2436 return set_msr_mce(vcpu, msr_info);
71db6023 2437
6912ac32
WH		 2438 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2439 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2440 pr = true; /* fall through */
2441 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2442 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2443 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2444 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2445
2446 if (pr || data != 0)
a737f256
CD		 2447 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2448 "0x%x data 0x%llx\n", msr, data);
5753785f 2449 break;
84e0cefa
JS		 2450 case MSR_K7_CLK_CTL:
2451 /*
2452 * Ignore all writes to this no longer documented MSR.
2453 * Writes are only relevant for old K7 processors,
2454 * all pre-dating SVM, but a recommended workaround from
4a969980 2455 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2456 * affected processor models on the command line, hence
2457 * the need to ignore the workaround.
2458 */
2459 break;
55cd8e5a 2460 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2461 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2462 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2463 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2464 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2465 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2466 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2467 return kvm_hv_set_msr_common(vcpu, msr, data,
2468 msr_info->host_initiated);
91c9c3ed 2469 case MSR_IA32_BBL_CR_CTL3:
2470 /* Drop writes to this legacy MSR -- see rdmsr
2471 * counterpart for further detail.
2472 */
fab0aa3b
EM		 2473 if (report_ignored_msrs)
2474 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2475 msr, data);
91c9c3ed 2476 break;
2b036c6b 2477 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2478 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2479 return 1;
2480 vcpu->arch.osvw.length = data;
2481 break;
2482 case MSR_AMD64_OSVW_STATUS:
d6321d49 2483 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2484 return 1;
2485 vcpu->arch.osvw.status = data;
2486 break;
db2336a8
KH		 2487 case MSR_PLATFORM_INFO:
2488 if (!msr_info->host_initiated ||
2489 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2490 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2491 cpuid_fault_enabled(vcpu)))
2492 return 1;
2493 vcpu->arch.msr_platform_info = data;
2494 break;
2495 case MSR_MISC_FEATURES_ENABLES:
2496 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2497 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2498 !supports_cpuid_fault(vcpu)))
2499 return 1;
2500 vcpu->arch.msr_misc_features_enables = data;
2501 break;
15c4a640 2502 default:
ffde22ac
ES		 2503 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2504 return xen_hvm_config(vcpu, data);
c6702c9d 2505 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2506 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2507 if (!ignore_msrs) {
ae0f5499 2508 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2509 msr, data);
ed85c068
AP		 2510 return 1;
2511 } else {
fab0aa3b
EM		 2512 if (report_ignored_msrs)
2513 vcpu_unimpl(vcpu,
2514 "ignored wrmsr: 0x%x data 0x%llx\n",
2515 msr, data);
ed85c068
AP		 2516 break;
2517 }
15c4a640
CO		 2518 }
2519 return 0;
2520}
2521EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2522
2523
2524/*
2525 * Reads an msr value (of 'msr_index') into 'pdata'.
2526 * Returns 0 on success, non-0 otherwise.
2527 * Assumes vcpu_load() was already called.
2528 */
609e36d3 2529int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2530{
609e36d3 2531 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2532}
ff651cb6 2533EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2534
890ca9ae 2535static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2536{
2537 u64 data;
890ca9ae
HY		 2538 u64 mcg_cap = vcpu->arch.mcg_cap;
2539 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2540
2541 switch (msr) {
15c4a640
CO		 2542 case MSR_IA32_P5_MC_ADDR:
2543 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2544 data = 0;
2545 break;
15c4a640 2546 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2547 data = vcpu->arch.mcg_cap;
2548 break;
c7ac679c 2549 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2550 if (!(mcg_cap & MCG_CTL_P))
2551 return 1;
2552 data = vcpu->arch.mcg_ctl;
2553 break;
2554 case MSR_IA32_MCG_STATUS:
2555 data = vcpu->arch.mcg_status;
2556 break;
2557 default:
2558 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2559 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2560 u32 offset = msr - MSR_IA32_MC0_CTL;
2561 data = vcpu->arch.mce_banks[offset];
2562 break;
2563 }
2564 return 1;
2565 }
2566 *pdata = data;
2567 return 0;
2568}
2569
609e36d3 2570int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2571{
609e36d3 2572 switch (msr_info->index) {
890ca9ae 2573 case MSR_IA32_PLATFORM_ID:
15c4a640 2574 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2575 case MSR_IA32_DEBUGCTLMSR:
2576 case MSR_IA32_LASTBRANCHFROMIP:
2577 case MSR_IA32_LASTBRANCHTOIP:
2578 case MSR_IA32_LASTINTFROMIP:
2579 case MSR_IA32_LASTINTTOIP:
60af2ecd 2580 case MSR_K8_SYSCFG:
3afb1121
PB		 2581 case MSR_K8_TSEG_ADDR:
2582 case MSR_K8_TSEG_MASK:
60af2ecd 2583 case MSR_K7_HWCR:
61a6bd67 2584 case MSR_VM_HSAVE_PA:
1fdbd48c 2585 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2586 case MSR_AMD64_NB_CFG:
f7c6d140 2587 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2588 case MSR_AMD64_BU_CFG2:
0c2df2a1 2589 case MSR_IA32_PERF_CTL:
405a353a 2590 case MSR_AMD64_DC_CFG:
609e36d3 2591 msr_info->data = 0;
15c4a640 2592 break;
c51eb52b 2593 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2594 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2595 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2596 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2597 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2598 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2599 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2600 msr_info->data = 0;
5753785f 2601 break;
742bc670 2602 case MSR_IA32_UCODE_REV:
518e7b94 2603 msr_info->data = vcpu->arch.microcode_version;
742bc670 2604 break;
9ba075a6 2605 case MSR_MTRRcap:
9ba075a6 2606 case 0x200 ... 0x2ff:
ff53604b 2607 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2608 case 0xcd: /* fsb frequency */
609e36d3 2609 msr_info->data = 3;
15c4a640 2610 break;
7b914098
JS		 2611 /*
2612 * MSR_EBC_FREQUENCY_ID
2613 * Conservative value valid for even the basic CPU models.
2614 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2615 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2616 * and 266MHz for model 3, or 4. Set Core Clock
2617 * Frequency to System Bus Frequency Ratio to 1 (bits
2618 * 31:24) even though these are only valid for CPU
2619 * models > 2, however guests may end up dividing or
2620 * multiplying by zero otherwise.
2621 */
2622 case MSR_EBC_FREQUENCY_ID:
609e36d3 2623 msr_info->data = 1 << 24;
7b914098 2624 break;
15c4a640 2625 case MSR_IA32_APICBASE:
609e36d3 2626 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2627 break;
0105d1a5 2628 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2629 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2630 break;
a3e06bbe 2631 case MSR_IA32_TSCDEADLINE:
609e36d3 2632 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2633 break;
ba904635 2634 case MSR_IA32_TSC_ADJUST:
609e36d3 2635 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2636 break;
15c4a640 2637 case MSR_IA32_MISC_ENABLE:
609e36d3 2638 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2639 break;
64d60670
PB		 2640 case MSR_IA32_SMBASE:
2641 if (!msr_info->host_initiated)
2642 return 1;
2643 msr_info->data = vcpu->arch.smbase;
15c4a640 2644 break;
52797bf9
LA		 2645 case MSR_SMI_COUNT:
2646 msr_info->data = vcpu->arch.smi_count;
2647 break;
847f0ad8
AG		 2648 case MSR_IA32_PERF_STATUS:
2649 /* TSC increment by tick */
609e36d3 2650 msr_info->data = 1000ULL;
847f0ad8 2651 /* CPU multiplier */
b0996ae4 2652 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2653 break;
15c4a640 2654 case MSR_EFER:
609e36d3 2655 msr_info->data = vcpu->arch.efer;
15c4a640 2656 break;
18068523 2657 case MSR_KVM_WALL_CLOCK:
11c6bffa 2658 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2659 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2660 break;
2661 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2662 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2663 msr_info->data = vcpu->arch.time;
18068523 2664 break;
344d9588 2665 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2666 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2667 break;
c9aaa895 2668 case MSR_KVM_STEAL_TIME:
609e36d3 2669 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2670 break;
1d92128f 2671 case MSR_KVM_PV_EOI_EN:
609e36d3 2672 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2673 break;
890ca9ae
HY		 2674 case MSR_IA32_P5_MC_ADDR:
2675 case MSR_IA32_P5_MC_TYPE:
2676 case MSR_IA32_MCG_CAP:
2677 case MSR_IA32_MCG_CTL:
2678 case MSR_IA32_MCG_STATUS:
81760dcc 2679 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2680 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2681 case MSR_K7_CLK_CTL:
2682 /*
2683 * Provide expected ramp-up count for K7. All other
2684 * are set to zero, indicating minimum divisors for
2685 * every field.
2686 *
2687 * This prevents guest kernels on AMD host with CPU
2688 * type 6, model 8 and higher from exploding due to
2689 * the rdmsr failing.
2690 */
609e36d3 2691 msr_info->data = 0x20000000;
84e0cefa 2692 break;
55cd8e5a 2693 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2694 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2695 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2696 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2697 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2698 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2699 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887
AS		 2700 return kvm_hv_get_msr_common(vcpu,
2701 msr_info->index, &msr_info->data);
55cd8e5a 2702 break;
91c9c3ed 2703 case MSR_IA32_BBL_CR_CTL3:
2704 /* This legacy MSR exists but isn't fully documented in current
2705 * silicon. It is however accessed by winxp in very narrow
2706 * scenarios where it sets bit #19, itself documented as
2707 * a "reserved" bit. Best effort attempt to source coherent
2708 * read data here should the balance of the register be
2709 * interpreted by the guest:
2710 *
2711 * L2 cache control register 3: 64GB range, 256KB size,
2712 * enabled, latency 0x1, configured
2713 */
609e36d3 2714 msr_info->data = 0xbe702111;
91c9c3ed 2715 break;
2b036c6b 2716 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2717 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2718 return 1;
609e36d3 2719 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2720 break;
2721 case MSR_AMD64_OSVW_STATUS:
d6321d49 2722 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2723 return 1;
609e36d3 2724 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2725 break;
db2336a8
KH		 2726 case MSR_PLATFORM_INFO:
2727 msr_info->data = vcpu->arch.msr_platform_info;
2728 break;
2729 case MSR_MISC_FEATURES_ENABLES:
2730 msr_info->data = vcpu->arch.msr_misc_features_enables;
2731 break;
15c4a640 2732 default:
c6702c9d 2733 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2734 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2735 if (!ignore_msrs) {
ae0f5499
BD		 2736 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2737 msr_info->index);
ed85c068
AP		 2738 return 1;
2739 } else {
fab0aa3b
EM		 2740 if (report_ignored_msrs)
2741 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2742 msr_info->index);
609e36d3 2743 msr_info->data = 0;
ed85c068
AP		 2744 }
2745 break;
15c4a640 2746 }
15c4a640
CO		 2747 return 0;
2748}
2749EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2750
313a3dc7
CO		 2751/*
2752 * Read or write a bunch of msrs. All parameters are kernel addresses.
2753 *
2754 * @return number of msrs set successfully.
2755 */
2756static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2757 struct kvm_msr_entry *entries,
2758 int (*do_msr)(struct kvm_vcpu *vcpu,
2759 unsigned index, u64 *data))
2760{
801e459a 2761 int i;
313a3dc7 2762
313a3dc7
CO		 2763 for (i = 0; i < msrs->nmsrs; ++i)
2764 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2765 break;
2766
313a3dc7
CO		 2767 return i;
2768}
2769
2770/*
2771 * Read or write a bunch of msrs. Parameters are user addresses.
2772 *
2773 * @return number of msrs set successfully.
2774 */
2775static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2776 int (*do_msr)(struct kvm_vcpu *vcpu,
2777 unsigned index, u64 *data),
2778 int writeback)
2779{
2780 struct kvm_msrs msrs;
2781 struct kvm_msr_entry *entries;
2782 int r, n;
2783 unsigned size;
2784
2785 r = -EFAULT;
2786 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2787 goto out;
2788
2789 r = -E2BIG;
2790 if (msrs.nmsrs >= MAX_IO_MSRS)
2791 goto out;
2792
313a3dc7 2793 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2794 entries = memdup_user(user_msrs->entries, size);
2795 if (IS_ERR(entries)) {
2796 r = PTR_ERR(entries);
313a3dc7 2797 goto out;
ff5c2c03 2798 }
313a3dc7
CO		 2799
2800 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2801 if (r < 0)
2802 goto out_free;
2803
2804 r = -EFAULT;
2805 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2806 goto out_free;
2807
2808 r = n;
2809
2810out_free:
7a73c028 2811 kfree(entries);
313a3dc7
CO		 2812out:
2813 return r;
2814}
2815
4d5422ce
WL		 2816static inline bool kvm_can_mwait_in_guest(void)
2817{
2818 return boot_cpu_has(X86_FEATURE_MWAIT) &&
2819 !boot_cpu_has_bug(X86_BUG_MONITOR);
2820}
2821
784aa3d7 2822int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2823{
4d5422ce 2824 int r = 0;
018d00d2
ZX		 2825
2826 switch (ext) {
2827 case KVM_CAP_IRQCHIP:
2828 case KVM_CAP_HLT:
2829 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2830 case KVM_CAP_SET_TSS_ADDR:
07716717 2831 case KVM_CAP_EXT_CPUID:
9c15bb1d 2832 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2833 case KVM_CAP_CLOCKSOURCE:
7837699f 2834 case KVM_CAP_PIT:
a28e4f5a 2835 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2836 case KVM_CAP_MP_STATE:
ed848624 2837 case KVM_CAP_SYNC_MMU:
a355c85c 2838 case KVM_CAP_USER_NMI:
52d939a0 2839 case KVM_CAP_REINJECT_CONTROL:
4925663a 2840 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2841 case KVM_CAP_IOEVENTFD:
f848a5a8 2842 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2843 case KVM_CAP_PIT2:
e9f42757 2844 case KVM_CAP_PIT_STATE2:
b927a3ce 2845 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2846 case KVM_CAP_XEN_HVM:
3cfc3092 2847 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2848 case KVM_CAP_HYPERV:
10388a07 2849 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2850 case KVM_CAP_HYPERV_SPIN:
5c919412 2851 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2852 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2853 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2854 case KVM_CAP_HYPERV_EVENTFD:
ab9f4ecb 2855 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2856 case KVM_CAP_DEBUGREGS:
d2be1651 2857 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2858 case KVM_CAP_XSAVE:
344d9588 2859 case KVM_CAP_ASYNC_PF:
92a1f12d 2860 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2861 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2862 case KVM_CAP_READONLY_MEM:
5f66b620 2863 case KVM_CAP_HYPERV_TIME:
100943c5 2864 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2865 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2866 case KVM_CAP_ENABLE_CAP_VM:
2867 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2868 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2869 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2870 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2871 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2872 r = 1;
2873 break;
01643c51
KH		 2874 case KVM_CAP_SYNC_REGS:
2875 r = KVM_SYNC_X86_VALID_FIELDS;
2876 break;
e3fd9a93
PB		 2877 case KVM_CAP_ADJUST_CLOCK:
2878 r = KVM_CLOCK_TSC_STABLE;
2879 break;
4d5422ce
WL		 2880 case KVM_CAP_X86_DISABLE_EXITS:
2881 if(kvm_can_mwait_in_guest())
2882 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2883 break;
6d396b55
PB		 2884 case KVM_CAP_X86_SMM:
2885 /* SMBASE is usually relocated above 1M on modern chipsets,
2886 * and SMM handlers might indeed rely on 4G segment limits,
2887 * so do not report SMM to be available if real mode is
2888 * emulated via vm86 mode. Still, do not go to great lengths
2889 * to avoid userspace's usage of the feature, because it is a
2890 * fringe case that is not enabled except via specific settings
2891 * of the module parameters.
2892 */
2893 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2894 break;
774ead3a
AK		 2895 case KVM_CAP_VAPIC:
2896 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2897 break;
f725230a 2898 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2899 r = KVM_SOFT_MAX_VCPUS;
2900 break;
2901 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2902 r = KVM_MAX_VCPUS;
2903 break;
a988b910 2904 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2905 r = KVM_USER_MEM_SLOTS;
a988b910 2906 break;
a68a6a72
MT		 2907 case KVM_CAP_PV_MMU: /* obsolete */
2908 r = 0;
2f333bcb 2909 break;
890ca9ae
HY		 2910 case KVM_CAP_MCE:
2911 r = KVM_MAX_MCE_BANKS;
2912 break;
2d5b5a66 2913 case KVM_CAP_XCRS:
d366bf7e 2914 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2915 break;
92a1f12d
JR		 2916 case KVM_CAP_TSC_CONTROL:
2917 r = kvm_has_tsc_control;
2918 break;
37131313
RK		 2919 case KVM_CAP_X2APIC_API:
2920 r = KVM_X2APIC_API_VALID_FLAGS;
2921 break;
018d00d2 2922 default:
018d00d2
ZX		 2923 break;
2924 }
2925 return r;
2926
2927}
2928
043405e1
CO		 2929long kvm_arch_dev_ioctl(struct file *filp,
2930 unsigned int ioctl, unsigned long arg)
2931{
2932 void __user *argp = (void __user *)arg;
2933 long r;
2934
2935 switch (ioctl) {
2936 case KVM_GET_MSR_INDEX_LIST: {
2937 struct kvm_msr_list __user *user_msr_list = argp;
2938 struct kvm_msr_list msr_list;
2939 unsigned n;
2940
2941 r = -EFAULT;
2942 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2943 goto out;
2944 n = msr_list.nmsrs;
62ef68bb 2945 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2946 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2947 goto out;
2948 r = -E2BIG;
e125e7b6 2949 if (n < msr_list.nmsrs)
043405e1
CO		 2950 goto out;
2951 r = -EFAULT;
2952 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2953 num_msrs_to_save * sizeof(u32)))
2954 goto out;
e125e7b6 2955 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2956 &emulated_msrs,
62ef68bb 2957 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2958 goto out;
2959 r = 0;
2960 break;
2961 }
9c15bb1d
BP		 2962 case KVM_GET_SUPPORTED_CPUID:
2963 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2964 struct kvm_cpuid2 __user *cpuid_arg = argp;
2965 struct kvm_cpuid2 cpuid;
2966
2967 r = -EFAULT;
2968 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2969 goto out;
9c15bb1d
BP		 2970
2971 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2972 ioctl);
674eea0f
AK		 2973 if (r)
2974 goto out;
2975
2976 r = -EFAULT;
2977 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2978 goto out;
2979 r = 0;
2980 break;
2981 }
890ca9ae 2982 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2983 r = -EFAULT;
c45dcc71
AR		 2984 if (copy_to_user(argp, &kvm_mce_cap_supported,
2985 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2986 goto out;
2987 r = 0;
2988 break;
801e459a
TL		 2989 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2990 struct kvm_msr_list __user *user_msr_list = argp;
2991 struct kvm_msr_list msr_list;
2992 unsigned int n;
2993
2994 r = -EFAULT;
2995 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2996 goto out;
2997 n = msr_list.nmsrs;
2998 msr_list.nmsrs = num_msr_based_features;
2999 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3000 goto out;
3001 r = -E2BIG;
3002 if (n < msr_list.nmsrs)
3003 goto out;
3004 r = -EFAULT;
3005 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3006 num_msr_based_features * sizeof(u32)))
3007 goto out;
3008 r = 0;
3009 break;
3010 }
3011 case KVM_GET_MSRS:
3012 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3013 break;
890ca9ae 3014 }
043405e1
CO		 3015 default:
3016 r = -EINVAL;
3017 }
3018out:
3019 return r;
3020}
3021
f5f48ee1
SY		 3022static void wbinvd_ipi(void *garbage)
3023{
3024 wbinvd();
3025}
3026
3027static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3028{
e0f0bbc5 3029 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3030}
3031
313a3dc7
CO		 3032void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3033{
f5f48ee1
SY		 3034 /* Address WBINVD may be executed by guest */
3035 if (need_emulate_wbinvd(vcpu)) {
3036 if (kvm_x86_ops->has_wbinvd_exit())
3037 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3038 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3039 smp_call_function_single(vcpu->cpu,
3040 wbinvd_ipi, NULL, 1);
3041 }
3042
313a3dc7 3043 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3044
0dd6a6ed
ZA		 3045 /* Apply any externally detected TSC adjustments (due to suspend) */
3046 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3047 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3048 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3049 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3050 }
8f6055cb 3051
b0c39dc6 3052 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3053 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3054 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3055 if (tsc_delta < 0)
3056 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3057
b0c39dc6 3058 if (kvm_check_tsc_unstable()) {
07c1419a 3059 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3060 vcpu->arch.last_guest_tsc);
a545ab6a 3061 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3062 vcpu->arch.tsc_catchup = 1;
c285545f 3063 }
a749e247
PB		 3064
3065 if (kvm_lapic_hv_timer_in_use(vcpu))
3066 kvm_lapic_restart_hv_timer(vcpu);
3067
d98d07ca
MT		 3068 /*
3069 * On a host with synchronized TSC, there is no need to update
3070 * kvmclock on vcpu->cpu migration
3071 */
3072 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3073 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3074 if (vcpu->cpu != cpu)
1bd2009e 3075 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3076 vcpu->cpu = cpu;
6b7d7e76 3077 }
c9aaa895 3078
c9aaa895 3079 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3080}
3081
0b9f6c46
PX		 3082static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3083{
3084 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3085 return;
3086
fa55eedd 3087 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3088
4e335d9e 3089 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3090 &vcpu->arch.st.steal.preempted,
3091 offsetof(struct kvm_steal_time, preempted),
3092 sizeof(vcpu->arch.st.steal.preempted));
3093}
3094
313a3dc7
CO		 3095void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3096{
cc0d907c 3097 int idx;
de63ad4c
LM		 3098
3099 if (vcpu->preempted)
3100 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3101
931f261b
AA		 3102 /*
3103 * Disable page faults because we're in atomic context here.
3104 * kvm_write_guest_offset_cached() would call might_fault()
3105 * that relies on pagefault_disable() to tell if there's a
3106 * bug. NOTE: the write to guest memory may not go through if
3107 * during postcopy live migration or if there's heavy guest
3108 * paging.
3109 */
3110 pagefault_disable();
cc0d907c
AA		 3111 /*
3112 * kvm_memslots() will be called by
3113 * kvm_write_guest_offset_cached() so take the srcu lock.
3114 */
3115 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3116 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3117 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3118 pagefault_enable();
02daab21 3119 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3120 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3121 /*
3122 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3123 * on every vmexit, but if not, we might have a stale dr6 from the
3124 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3125 */
3126 set_debugreg(0, 6);
313a3dc7
CO		 3127}
3128
313a3dc7
CO		 3129static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3130 struct kvm_lapic_state *s)
3131{
fa59cc00 3132 if (vcpu->arch.apicv_active)
d62caabb
AS		 3133 kvm_x86_ops->sync_pir_to_irr(vcpu);
3134
a92e2543 3135 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3136}
3137
3138static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3139 struct kvm_lapic_state *s)
3140{
a92e2543
RK		 3141 int r;
3142
3143 r = kvm_apic_set_state(vcpu, s);
3144 if (r)
3145 return r;
cb142eb7 3146 update_cr8_intercept(vcpu);
313a3dc7
CO		 3147
3148 return 0;
3149}
3150
127a457a
MG		 3151static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3152{
3153 return (!lapic_in_kernel(vcpu) ||
3154 kvm_apic_accept_pic_intr(vcpu));
3155}
3156
782d422b
MG		 3157/*
3158 * if userspace requested an interrupt window, check that the
3159 * interrupt window is open.
3160 *
3161 * No need to exit to userspace if we already have an interrupt queued.
3162 */
3163static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3164{
3165 return kvm_arch_interrupt_allowed(vcpu) &&
3166 !kvm_cpu_has_interrupt(vcpu) &&
3167 !kvm_event_needs_reinjection(vcpu) &&
3168 kvm_cpu_accept_dm_intr(vcpu);
3169}
3170
f77bc6a4
ZX		 3171static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3172 struct kvm_interrupt *irq)
3173{
02cdb50f 3174 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3175 return -EINVAL;
1c1a9ce9
SR		 3176
3177 if (!irqchip_in_kernel(vcpu->kvm)) {
3178 kvm_queue_interrupt(vcpu, irq->irq, false);
3179 kvm_make_request(KVM_REQ_EVENT, vcpu);
3180 return 0;
3181 }
3182
3183 /*
3184 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3185 * fail for in-kernel 8259.
3186 */
3187 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3188 return -ENXIO;
f77bc6a4 3189
1c1a9ce9
SR		 3190 if (vcpu->arch.pending_external_vector != -1)
3191 return -EEXIST;
f77bc6a4 3192
1c1a9ce9 3193 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3194 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3195 return 0;
3196}
3197
c4abb7c9
JK		 3198static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3199{
c4abb7c9 3200 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3201
3202 return 0;
3203}
3204
f077825a
PB		 3205static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3206{
64d60670
PB		 3207 kvm_make_request(KVM_REQ_SMI, vcpu);
3208
f077825a
PB		 3209 return 0;
3210}
3211
b209749f
AK		 3212static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3213 struct kvm_tpr_access_ctl *tac)
3214{
3215 if (tac->flags)
3216 return -EINVAL;
3217 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3218 return 0;
3219}
3220
890ca9ae
HY		 3221static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3222 u64 mcg_cap)
3223{
3224 int r;
3225 unsigned bank_num = mcg_cap & 0xff, bank;
3226
3227 r = -EINVAL;
a9e38c3e 3228 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3229 goto out;
c45dcc71 3230 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3231 goto out;
3232 r = 0;
3233 vcpu->arch.mcg_cap = mcg_cap;
3234 /* Init IA32_MCG_CTL to all 1s */
3235 if (mcg_cap & MCG_CTL_P)
3236 vcpu->arch.mcg_ctl = ~(u64)0;
3237 /* Init IA32_MCi_CTL to all 1s */
3238 for (bank = 0; bank < bank_num; bank++)
3239 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3240
3241 if (kvm_x86_ops->setup_mce)
3242 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3243out:
3244 return r;
3245}
3246
3247static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3248 struct kvm_x86_mce *mce)
3249{
3250 u64 mcg_cap = vcpu->arch.mcg_cap;
3251 unsigned bank_num = mcg_cap & 0xff;
3252 u64 *banks = vcpu->arch.mce_banks;
3253
3254 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3255 return -EINVAL;
3256 /*
3257 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3258 * reporting is disabled
3259 */
3260 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3261 vcpu->arch.mcg_ctl != ~(u64)0)
3262 return 0;
3263 banks += 4 * mce->bank;
3264 /*
3265 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3266 * reporting is disabled for the bank
3267 */
3268 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3269 return 0;
3270 if (mce->status & MCI_STATUS_UC) {
3271 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3272 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3273 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3274 return 0;
3275 }
3276 if (banks[1] & MCI_STATUS_VAL)
3277 mce->status |= MCI_STATUS_OVER;
3278 banks[2] = mce->addr;
3279 banks[3] = mce->misc;
3280 vcpu->arch.mcg_status = mce->mcg_status;
3281 banks[1] = mce->status;
3282 kvm_queue_exception(vcpu, MC_VECTOR);
3283 } else if (!(banks[1] & MCI_STATUS_VAL)
3284 || !(banks[1] & MCI_STATUS_UC)) {
3285 if (banks[1] & MCI_STATUS_VAL)
3286 mce->status |= MCI_STATUS_OVER;
3287 banks[2] = mce->addr;
3288 banks[3] = mce->misc;
3289 banks[1] = mce->status;
3290 } else
3291 banks[1] |= MCI_STATUS_OVER;
3292 return 0;
3293}
3294
3cfc3092
JK		 3295static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3296 struct kvm_vcpu_events *events)
3297{
7460fb4a 3298 process_nmi(vcpu);
664f8e26
WL		 3299 /*
3300 * FIXME: pass injected and pending separately. This is only
3301 * needed for nested virtualization, whose state cannot be
3302 * migrated yet. For now we can combine them.
3303 */
03b82a30 3304 events->exception.injected =
664f8e26
WL		 3305 (vcpu->arch.exception.pending ||
3306 vcpu->arch.exception.injected) &&
03b82a30 3307 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3308 events->exception.nr = vcpu->arch.exception.nr;
3309 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3310 events->exception.pad = 0;
3cfc3092
JK		 3311 events->exception.error_code = vcpu->arch.exception.error_code;
3312
03b82a30
JK		 3313 events->interrupt.injected =
3314 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3315 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3316 events->interrupt.soft = 0;
37ccdcbe 3317 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3318
3319 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3320 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3321 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3322 events->nmi.pad = 0;
3cfc3092 3323
66450a21 3324 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3325
f077825a
PB		 3326 events->smi.smm = is_smm(vcpu);
3327 events->smi.pending = vcpu->arch.smi_pending;
3328 events->smi.smm_inside_nmi =
3329 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3330 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3331
dab4b911 3332 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3333 | KVM_VCPUEVENT_VALID_SHADOW
3334 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3335 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3336}
3337
6ef4e07e
XG		 3338static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3339
3cfc3092
JK		 3340static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3341 struct kvm_vcpu_events *events)
3342{
dab4b911 3343 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3344 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3345 | KVM_VCPUEVENT_VALID_SHADOW
3346 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3347 return -EINVAL;
3348
78e546c8 3349 if (events->exception.injected &&
28d06353
JM		 3350 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3351 is_guest_mode(vcpu)))
78e546c8
PB		 3352 return -EINVAL;
3353
28bf2888
DH		 3354 /* INITs are latched while in SMM */
3355 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3356 (events->smi.smm || events->smi.pending) &&
3357 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3358 return -EINVAL;
3359
7460fb4a 3360 process_nmi(vcpu);
664f8e26 3361 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3362 vcpu->arch.exception.pending = events->exception.injected;
3363 vcpu->arch.exception.nr = events->exception.nr;
3364 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3365 vcpu->arch.exception.error_code = events->exception.error_code;
3366
3367 vcpu->arch.interrupt.pending = events->interrupt.injected;
3368 vcpu->arch.interrupt.nr = events->interrupt.nr;
3369 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3370 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3371 kvm_x86_ops->set_interrupt_shadow(vcpu,
3372 events->interrupt.shadow);
3cfc3092
JK		 3373
3374 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3375 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3376 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3377 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3378
66450a21 3379 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3380 lapic_in_kernel(vcpu))
66450a21 3381 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3382
f077825a 3383 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3384 u32 hflags = vcpu->arch.hflags;
f077825a 3385 if (events->smi.smm)
6ef4e07e 3386 hflags |= HF_SMM_MASK;
f077825a 3387 else
6ef4e07e
XG		 3388 hflags &= ~HF_SMM_MASK;
3389 kvm_set_hflags(vcpu, hflags);
3390
f077825a 3391 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3392
3393 if (events->smi.smm) {
3394 if (events->smi.smm_inside_nmi)
3395 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3396 else
f4ef1910
WL		 3397 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3398 if (lapic_in_kernel(vcpu)) {
3399 if (events->smi.latched_init)
3400 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3401 else
3402 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3403 }
f077825a
PB		 3404 }
3405 }
3406
3842d135
AK		 3407 kvm_make_request(KVM_REQ_EVENT, vcpu);
3408
3cfc3092
JK		 3409 return 0;
3410}
3411
a1efbe77
JK		 3412static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3413 struct kvm_debugregs *dbgregs)
3414{
73aaf249
JK		 3415 unsigned long val;
3416
a1efbe77 3417 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3418 kvm_get_dr(vcpu, 6, &val);
73aaf249 3419 dbgregs->dr6 = val;
a1efbe77
JK		 3420 dbgregs->dr7 = vcpu->arch.dr7;
3421 dbgregs->flags = 0;
97e69aa6 3422 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3423}
3424
3425static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3426 struct kvm_debugregs *dbgregs)
3427{
3428 if (dbgregs->flags)
3429 return -EINVAL;
3430
d14bdb55
PB		 3431 if (dbgregs->dr6 & ~0xffffffffull)
3432 return -EINVAL;
3433 if (dbgregs->dr7 & ~0xffffffffull)
3434 return -EINVAL;
3435
a1efbe77 3436 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3437 kvm_update_dr0123(vcpu);
a1efbe77 3438 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3439 kvm_update_dr6(vcpu);
a1efbe77 3440 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3441 kvm_update_dr7(vcpu);
a1efbe77 3442
a1efbe77
JK		 3443 return 0;
3444}
3445
df1daba7
PB		 3446#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3447
3448static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3449{
c47ada30 3450 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3451 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3452 u64 valid;
3453
3454 /*
3455 * Copy legacy XSAVE area, to avoid complications with CPUID
3456 * leaves 0 and 1 in the loop below.
3457 */
3458 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3459
3460 /* Set XSTATE_BV */
00c87e9a 3461 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3462 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3463
3464 /*
3465 * Copy each region from the possibly compacted offset to the
3466 * non-compacted offset.
3467 */
d91cab78 3468 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3469 while (valid) {
3470 u64 feature = valid & -valid;
3471 int index = fls64(feature) - 1;
3472 void *src = get_xsave_addr(xsave, feature);
3473
3474 if (src) {
3475 u32 size, offset, ecx, edx;
3476 cpuid_count(XSTATE_CPUID, index,
3477 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3478 if (feature == XFEATURE_MASK_PKRU)
3479 memcpy(dest + offset, &vcpu->arch.pkru,
3480 sizeof(vcpu->arch.pkru));
3481 else
3482 memcpy(dest + offset, src, size);
3483
df1daba7
PB		 3484 }
3485
3486 valid -= feature;
3487 }
3488}
3489
3490static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3491{
c47ada30 3492 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3493 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3494 u64 valid;
3495
3496 /*
3497 * Copy legacy XSAVE area, to avoid complications with CPUID
3498 * leaves 0 and 1 in the loop below.
3499 */
3500 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3501
3502 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3503 xsave->header.xfeatures = xstate_bv;
782511b0 3504 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3505 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3506
3507 /*
3508 * Copy each region from the non-compacted offset to the
3509 * possibly compacted offset.
3510 */
d91cab78 3511 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3512 while (valid) {
3513 u64 feature = valid & -valid;
3514 int index = fls64(feature) - 1;
3515 void *dest = get_xsave_addr(xsave, feature);
3516
3517 if (dest) {
3518 u32 size, offset, ecx, edx;
3519 cpuid_count(XSTATE_CPUID, index,
3520 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3521 if (feature == XFEATURE_MASK_PKRU)
3522 memcpy(&vcpu->arch.pkru, src + offset,
3523 sizeof(vcpu->arch.pkru));
3524 else
3525 memcpy(dest, src + offset, size);
ee4100da 3526 }
df1daba7
PB		 3527
3528 valid -= feature;
3529 }
3530}
3531
2d5b5a66
SY		 3532static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3533 struct kvm_xsave *guest_xsave)
3534{
d366bf7e 3535 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3536 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3537 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3538 } else {
2d5b5a66 3539 memcpy(guest_xsave->region,
7366ed77 3540 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3541 sizeof(struct fxregs_state));
2d5b5a66 3542 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3543 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3544 }
3545}
3546
a575813b
WL		 3547#define XSAVE_MXCSR_OFFSET 24
3548
2d5b5a66
SY		 3549static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3550 struct kvm_xsave *guest_xsave)
3551{
3552 u64 xstate_bv =
3553 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3554 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3555
d366bf7e 3556 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3557 /*
3558 * Here we allow setting states that are not present in
3559 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3560 * with old userspace.
3561 */
a575813b
WL		 3562 if (xstate_bv & ~kvm_supported_xcr0() ||
3563 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3564 return -EINVAL;
df1daba7 3565 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3566 } else {
a575813b
WL		 3567 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3568 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3569 return -EINVAL;
7366ed77 3570 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3571 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3572 }
3573 return 0;
3574}
3575
3576static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3577 struct kvm_xcrs *guest_xcrs)
3578{
d366bf7e 3579 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3580 guest_xcrs->nr_xcrs = 0;
3581 return;
3582 }
3583
3584 guest_xcrs->nr_xcrs = 1;
3585 guest_xcrs->flags = 0;
3586 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3587 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3588}
3589
3590static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3591 struct kvm_xcrs *guest_xcrs)
3592{
3593 int i, r = 0;
3594
d366bf7e 3595 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3596 return -EINVAL;
3597
3598 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3599 return -EINVAL;
3600
3601 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3602 /* Only support XCR0 currently */
c67a04cb 3603 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3604 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3605 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3606 break;
3607 }
3608 if (r)
3609 r = -EINVAL;
3610 return r;
3611}
3612
1c0b28c2
EM		 3613/*
3614 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3615 * stopped by the hypervisor. This function will be called from the host only.
3616 * EINVAL is returned when the host attempts to set the flag for a guest that
3617 * does not support pv clocks.
3618 */
3619static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3620{
0b79459b 3621 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3622 return -EINVAL;
51d59c6b 3623 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3624 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3625 return 0;
3626}
3627
5c919412
AS		 3628static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3629 struct kvm_enable_cap *cap)
3630{
3631 if (cap->flags)
3632 return -EINVAL;
3633
3634 switch (cap->cap) {
efc479e6
RK		 3635 case KVM_CAP_HYPERV_SYNIC2:
3636 if (cap->args[0])
3637 return -EINVAL;
5c919412 3638 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3639 if (!irqchip_in_kernel(vcpu->kvm))
3640 return -EINVAL;
efc479e6
RK		 3641 return kvm_hv_activate_synic(vcpu, cap->cap ==
3642 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3643 default:
3644 return -EINVAL;
3645 }
3646}
3647
313a3dc7
CO		 3648long kvm_arch_vcpu_ioctl(struct file *filp,
3649 unsigned int ioctl, unsigned long arg)
3650{
3651 struct kvm_vcpu *vcpu = filp->private_data;
3652 void __user *argp = (void __user *)arg;
3653 int r;
d1ac91d8
AK		 3654 union {
3655 struct kvm_lapic_state *lapic;
3656 struct kvm_xsave *xsave;
3657 struct kvm_xcrs *xcrs;
3658 void *buffer;
3659 } u;
3660
9b062471
CD		 3661 vcpu_load(vcpu);
3662
d1ac91d8 3663 u.buffer = NULL;
313a3dc7
CO		 3664 switch (ioctl) {
3665 case KVM_GET_LAPIC: {
2204ae3c 3666 r = -EINVAL;
bce87cce 3667 if (!lapic_in_kernel(vcpu))
2204ae3c 3668 goto out;
d1ac91d8 3669 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3670
b772ff36 3671 r = -ENOMEM;
d1ac91d8 3672 if (!u.lapic)
b772ff36 3673 goto out;
d1ac91d8 3674 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3675 if (r)
3676 goto out;
3677 r = -EFAULT;
d1ac91d8 3678 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3679 goto out;
3680 r = 0;
3681 break;
3682 }
3683 case KVM_SET_LAPIC: {
2204ae3c 3684 r = -EINVAL;
bce87cce 3685 if (!lapic_in_kernel(vcpu))
2204ae3c 3686 goto out;
ff5c2c03 3687 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3688 if (IS_ERR(u.lapic)) {
3689 r = PTR_ERR(u.lapic);
3690 goto out_nofree;
3691 }
ff5c2c03 3692
d1ac91d8 3693 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3694 break;
3695 }
f77bc6a4
ZX		 3696 case KVM_INTERRUPT: {
3697 struct kvm_interrupt irq;
3698
3699 r = -EFAULT;
3700 if (copy_from_user(&irq, argp, sizeof irq))
3701 goto out;
3702 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3703 break;
3704 }
c4abb7c9
JK		 3705 case KVM_NMI: {
3706 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3707 break;
3708 }
f077825a
PB		 3709 case KVM_SMI: {
3710 r = kvm_vcpu_ioctl_smi(vcpu);
3711 break;
3712 }
313a3dc7
CO		 3713 case KVM_SET_CPUID: {
3714 struct kvm_cpuid __user *cpuid_arg = argp;
3715 struct kvm_cpuid cpuid;
3716
3717 r = -EFAULT;
3718 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3719 goto out;
3720 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3721 break;
3722 }
07716717
DK		 3723 case KVM_SET_CPUID2: {
3724 struct kvm_cpuid2 __user *cpuid_arg = argp;
3725 struct kvm_cpuid2 cpuid;
3726
3727 r = -EFAULT;
3728 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3729 goto out;
3730 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3731 cpuid_arg->entries);
07716717
DK		 3732 break;
3733 }
3734 case KVM_GET_CPUID2: {
3735 struct kvm_cpuid2 __user *cpuid_arg = argp;
3736 struct kvm_cpuid2 cpuid;
3737
3738 r = -EFAULT;
3739 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3740 goto out;
3741 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3742 cpuid_arg->entries);
07716717
DK		 3743 if (r)
3744 goto out;
3745 r = -EFAULT;
3746 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3747 goto out;
3748 r = 0;
3749 break;
3750 }
801e459a
TL		 3751 case KVM_GET_MSRS: {
3752 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3753 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3754 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3755 break;
801e459a
TL		 3756 }
3757 case KVM_SET_MSRS: {
3758 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3759 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3760 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3761 break;
801e459a 3762 }
b209749f
AK		 3763 case KVM_TPR_ACCESS_REPORTING: {
3764 struct kvm_tpr_access_ctl tac;
3765
3766 r = -EFAULT;
3767 if (copy_from_user(&tac, argp, sizeof tac))
3768 goto out;
3769 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3770 if (r)
3771 goto out;
3772 r = -EFAULT;
3773 if (copy_to_user(argp, &tac, sizeof tac))
3774 goto out;
3775 r = 0;
3776 break;
3777 };
b93463aa
AK		 3778 case KVM_SET_VAPIC_ADDR: {
3779 struct kvm_vapic_addr va;
7301d6ab 3780 int idx;
b93463aa
AK		 3781
3782 r = -EINVAL;
35754c98 3783 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3784 goto out;
3785 r = -EFAULT;
3786 if (copy_from_user(&va, argp, sizeof va))
3787 goto out;
7301d6ab 3788 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3789 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3790 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3791 break;
3792 }
890ca9ae
HY		 3793 case KVM_X86_SETUP_MCE: {
3794 u64 mcg_cap;
3795
3796 r = -EFAULT;
3797 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3798 goto out;
3799 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3800 break;
3801 }
3802 case KVM_X86_SET_MCE: {
3803 struct kvm_x86_mce mce;
3804
3805 r = -EFAULT;
3806 if (copy_from_user(&mce, argp, sizeof mce))
3807 goto out;
3808 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3809 break;
3810 }
3cfc3092
JK		 3811 case KVM_GET_VCPU_EVENTS: {
3812 struct kvm_vcpu_events events;
3813
3814 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3815
3816 r = -EFAULT;
3817 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3818 break;
3819 r = 0;
3820 break;
3821 }
3822 case KVM_SET_VCPU_EVENTS: {
3823 struct kvm_vcpu_events events;
3824
3825 r = -EFAULT;
3826 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3827 break;
3828
3829 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3830 break;
3831 }
a1efbe77
JK		 3832 case KVM_GET_DEBUGREGS: {
3833 struct kvm_debugregs dbgregs;
3834
3835 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3836
3837 r = -EFAULT;
3838 if (copy_to_user(argp, &dbgregs,
3839 sizeof(struct kvm_debugregs)))
3840 break;
3841 r = 0;
3842 break;
3843 }
3844 case KVM_SET_DEBUGREGS: {
3845 struct kvm_debugregs dbgregs;
3846
3847 r = -EFAULT;
3848 if (copy_from_user(&dbgregs, argp,
3849 sizeof(struct kvm_debugregs)))
3850 break;
3851
3852 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3853 break;
3854 }
2d5b5a66 3855 case KVM_GET_XSAVE: {
d1ac91d8 3856 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3857 r = -ENOMEM;
d1ac91d8 3858 if (!u.xsave)
2d5b5a66
SY		 3859 break;
3860
d1ac91d8 3861 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3862
3863 r = -EFAULT;
d1ac91d8 3864 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3865 break;
3866 r = 0;
3867 break;
3868 }
3869 case KVM_SET_XSAVE: {
ff5c2c03 3870 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3871 if (IS_ERR(u.xsave)) {
3872 r = PTR_ERR(u.xsave);
3873 goto out_nofree;
3874 }
2d5b5a66 3875
d1ac91d8 3876 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3877 break;
3878 }
3879 case KVM_GET_XCRS: {
d1ac91d8 3880 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3881 r = -ENOMEM;
d1ac91d8 3882 if (!u.xcrs)
2d5b5a66
SY		 3883 break;
3884
d1ac91d8 3885 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3886
3887 r = -EFAULT;
d1ac91d8 3888 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3889 sizeof(struct kvm_xcrs)))
3890 break;
3891 r = 0;
3892 break;
3893 }
3894 case KVM_SET_XCRS: {
ff5c2c03 3895 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3896 if (IS_ERR(u.xcrs)) {
3897 r = PTR_ERR(u.xcrs);
3898 goto out_nofree;
3899 }
2d5b5a66 3900
d1ac91d8 3901 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3902 break;
3903 }
92a1f12d
JR		 3904 case KVM_SET_TSC_KHZ: {
3905 u32 user_tsc_khz;
3906
3907 r = -EINVAL;
92a1f12d
JR		 3908 user_tsc_khz = (u32)arg;
3909
3910 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3911 goto out;
3912
cc578287
ZA		 3913 if (user_tsc_khz == 0)
3914 user_tsc_khz = tsc_khz;
3915
381d585c
HZ		 3916 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3917 r = 0;
92a1f12d 3918
92a1f12d
JR		 3919 goto out;
3920 }
3921 case KVM_GET_TSC_KHZ: {
cc578287 3922 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3923 goto out;
3924 }
1c0b28c2
EM		 3925 case KVM_KVMCLOCK_CTRL: {
3926 r = kvm_set_guest_paused(vcpu);
3927 goto out;
3928 }
5c919412
AS		 3929 case KVM_ENABLE_CAP: {
3930 struct kvm_enable_cap cap;
3931
3932 r = -EFAULT;
3933 if (copy_from_user(&cap, argp, sizeof(cap)))
3934 goto out;
3935 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3936 break;
3937 }
313a3dc7
CO		 3938 default:
3939 r = -EINVAL;
3940 }
3941out:
d1ac91d8 3942 kfree(u.buffer);
9b062471
CD		 3943out_nofree:
3944 vcpu_put(vcpu);
313a3dc7
CO		 3945 return r;
3946}
3947
5b1c1493
CO		 3948int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3949{
3950 return VM_FAULT_SIGBUS;
3951}
3952
1fe779f8
CO		 3953static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3954{
3955 int ret;
3956
3957 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3958 return -EINVAL;
1fe779f8
CO		 3959 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3960 return ret;
3961}
3962
b927a3ce
SY		 3963static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3964 u64 ident_addr)
3965{
3966 kvm->arch.ept_identity_map_addr = ident_addr;
3967 return 0;
3968}
3969
1fe779f8
CO		 3970static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3971 u32 kvm_nr_mmu_pages)
3972{
3973 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3974 return -EINVAL;
3975
79fac95e 3976 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3977
3978 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3979 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3980
79fac95e 3981 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3982 return 0;
3983}
3984
3985static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3986{
39de71ec 3987 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3988}
3989
1fe779f8
CO		 3990static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3991{
90bca052 3992 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3993 int r;
3994
3995 r = 0;
3996 switch (chip->chip_id) {
3997 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3998 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3999 sizeof(struct kvm_pic_state));
4000 break;
4001 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4002 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4003 sizeof(struct kvm_pic_state));
4004 break;
4005 case KVM_IRQCHIP_IOAPIC:
33392b49 4006 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4007 break;
4008 default:
4009 r = -EINVAL;
4010 break;
4011 }
4012 return r;
4013}
4014
4015static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4016{
90bca052 4017 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4018 int r;
4019
4020 r = 0;
4021 switch (chip->chip_id) {
4022 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4023 spin_lock(&pic->lock);
4024 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4025 sizeof(struct kvm_pic_state));
90bca052 4026 spin_unlock(&pic->lock);
1fe779f8
CO		 4027 break;
4028 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4029 spin_lock(&pic->lock);
4030 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4031 sizeof(struct kvm_pic_state));
90bca052 4032 spin_unlock(&pic->lock);
1fe779f8
CO		 4033 break;
4034 case KVM_IRQCHIP_IOAPIC:
33392b49 4035 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4036 break;
4037 default:
4038 r = -EINVAL;
4039 break;
4040 }
90bca052 4041 kvm_pic_update_irq(pic);
1fe779f8
CO		 4042 return r;
4043}
4044
e0f63cb9
SY		 4045static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4046{
34f3941c
RK		 4047 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4048
4049 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4050
4051 mutex_lock(&kps->lock);
4052 memcpy(ps, &kps->channels, sizeof(*ps));
4053 mutex_unlock(&kps->lock);
2da29bcc 4054 return 0;
e0f63cb9
SY		 4055}
4056
4057static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4058{
0185604c 4059 int i;
09edea72
RK		 4060 struct kvm_pit *pit = kvm->arch.vpit;
4061
4062 mutex_lock(&pit->pit_state.lock);
34f3941c 4063 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4064 for (i = 0; i < 3; i++)
09edea72
RK		 4065 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4066 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4067 return 0;
e9f42757
BK		 4068}
4069
4070static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4071{
e9f42757
BK		 4072 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4073 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4074 sizeof(ps->channels));
4075 ps->flags = kvm->arch.vpit->pit_state.flags;
4076 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4077 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4078 return 0;
e9f42757
BK		 4079}
4080
4081static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4082{
2da29bcc 4083 int start = 0;
0185604c 4084 int i;
e9f42757 4085 u32 prev_legacy, cur_legacy;
09edea72
RK		 4086 struct kvm_pit *pit = kvm->arch.vpit;
4087
4088 mutex_lock(&pit->pit_state.lock);
4089 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4090 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4091 if (!prev_legacy && cur_legacy)
4092 start = 1;
09edea72
RK		 4093 memcpy(&pit->pit_state.channels, &ps->channels,
4094 sizeof(pit->pit_state.channels));
4095 pit->pit_state.flags = ps->flags;
0185604c 4096 for (i = 0; i < 3; i++)
09edea72 4097 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4098 start && i == 0);
09edea72 4099 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4100 return 0;
e0f63cb9
SY		 4101}
4102
52d939a0
MT		 4103static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4104 struct kvm_reinject_control *control)
4105{
71474e2f
RK		 4106 struct kvm_pit *pit = kvm->arch.vpit;
4107
4108 if (!pit)
52d939a0 4109 return -ENXIO;
b39c90b6 4110
71474e2f
RK		 4111 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4112 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4113 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4114 */
4115 mutex_lock(&pit->pit_state.lock);
4116 kvm_pit_set_reinject(pit, control->pit_reinject);
4117 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4118
52d939a0
MT		 4119 return 0;
4120}
4121
95d4c16c 4122/**
60c34612
TY		 4123 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4124 * @kvm: kvm instance
4125 * @log: slot id and address to which we copy the log
95d4c16c 4126 *
e108ff2f
PB		 4127 * Steps 1-4 below provide general overview of dirty page logging. See
4128 * kvm_get_dirty_log_protect() function description for additional details.
4129 *
4130 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4131 * always flush the TLB (step 4) even if previous step failed and the dirty
4132 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4133 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4134 * writes will be marked dirty for next log read.
95d4c16c 4135 *
60c34612
TY		 4136 * 1. Take a snapshot of the bit and clear it if needed.
4137 * 2. Write protect the corresponding page.
e108ff2f
PB		 4138 * 3. Copy the snapshot to the userspace.
4139 * 4. Flush TLB's if needed.
5bb064dc 4140 */
60c34612 4141int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4142{
60c34612 4143 bool is_dirty = false;
e108ff2f 4144 int r;
5bb064dc 4145
79fac95e 4146 mutex_lock(&kvm->slots_lock);
5bb064dc 4147
88178fd4
KH		 4148 /*
4149 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4150 */
4151 if (kvm_x86_ops->flush_log_dirty)
4152 kvm_x86_ops->flush_log_dirty(kvm);
4153
e108ff2f 4154 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4155
4156 /*
4157 * All the TLBs can be flushed out of mmu lock, see the comments in
4158 * kvm_mmu_slot_remove_write_access().
4159 */
e108ff2f 4160 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4161 if (is_dirty)
4162 kvm_flush_remote_tlbs(kvm);
4163
79fac95e 4164 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4165 return r;
4166}
4167
aa2fbe6d
YZ		 4168int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4169 bool line_status)
23d43cf9
CD		 4170{
4171 if (!irqchip_in_kernel(kvm))
4172 return -ENXIO;
4173
4174 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4175 irq_event->irq, irq_event->level,
4176 line_status);
23d43cf9
CD		 4177 return 0;
4178}
4179
90de4a18
NA		 4180static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4181 struct kvm_enable_cap *cap)
4182{
4183 int r;
4184
4185 if (cap->flags)
4186 return -EINVAL;
4187
4188 switch (cap->cap) {
4189 case KVM_CAP_DISABLE_QUIRKS:
4190 kvm->arch.disabled_quirks = cap->args[0];
4191 r = 0;
4192 break;
49df6397
SR		 4193 case KVM_CAP_SPLIT_IRQCHIP: {
4194 mutex_lock(&kvm->lock);
b053b2ae
SR		 4195 r = -EINVAL;
4196 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4197 goto split_irqchip_unlock;
49df6397
SR		 4198 r = -EEXIST;
4199 if (irqchip_in_kernel(kvm))
4200 goto split_irqchip_unlock;
557abc40 4201 if (kvm->created_vcpus)
49df6397
SR		 4202 goto split_irqchip_unlock;
4203 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4204 if (r)
49df6397
SR		 4205 goto split_irqchip_unlock;
4206 /* Pairs with irqchip_in_kernel. */
4207 smp_wmb();
49776faf 4208 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4209 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4210 r = 0;
4211split_irqchip_unlock:
4212 mutex_unlock(&kvm->lock);
4213 break;
4214 }
37131313
RK		 4215 case KVM_CAP_X2APIC_API:
4216 r = -EINVAL;
4217 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4218 break;
4219
4220 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4221 kvm->arch.x2apic_format = true;
c519265f
RK		 4222 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4223 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4224
4225 r = 0;
4226 break;
4d5422ce
WL		 4227 case KVM_CAP_X86_DISABLE_EXITS:
4228 r = -EINVAL;
4229 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4230 break;
4231
4232 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4233 kvm_can_mwait_in_guest())
4234 kvm->arch.mwait_in_guest = true;
4235 r = 0;
4236 break;
90de4a18
NA		 4237 default:
4238 r = -EINVAL;
4239 break;
4240 }
4241 return r;
4242}
4243
1fe779f8
CO		 4244long kvm_arch_vm_ioctl(struct file *filp,
4245 unsigned int ioctl, unsigned long arg)
4246{
4247 struct kvm *kvm = filp->private_data;
4248 void __user *argp = (void __user *)arg;
367e1319 4249 int r = -ENOTTY;
f0d66275
DH		 4250 /*
4251 * This union makes it completely explicit to gcc-3.x
4252 * that these two variables' stack usage should be
4253 * combined, not added together.
4254 */
4255 union {
4256 struct kvm_pit_state ps;
e9f42757 4257 struct kvm_pit_state2 ps2;
c5ff41ce 4258 struct kvm_pit_config pit_config;
f0d66275 4259 } u;
1fe779f8
CO		 4260
4261 switch (ioctl) {
4262 case KVM_SET_TSS_ADDR:
4263 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4264 break;
b927a3ce
SY		 4265 case KVM_SET_IDENTITY_MAP_ADDR: {
4266 u64 ident_addr;
4267
1af1ac91
DH		 4268 mutex_lock(&kvm->lock);
4269 r = -EINVAL;
4270 if (kvm->created_vcpus)
4271 goto set_identity_unlock;
b927a3ce
SY		 4272 r = -EFAULT;
4273 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4274 goto set_identity_unlock;
b927a3ce 4275 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4276set_identity_unlock:
4277 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4278 break;
4279 }
1fe779f8
CO		 4280 case KVM_SET_NR_MMU_PAGES:
4281 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4282 break;
4283 case KVM_GET_NR_MMU_PAGES:
4284 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4285 break;
3ddea128 4286 case KVM_CREATE_IRQCHIP: {
3ddea128 4287 mutex_lock(&kvm->lock);
09941366 4288
3ddea128 4289 r = -EEXIST;
35e6eaa3 4290 if (irqchip_in_kernel(kvm))
3ddea128 4291 goto create_irqchip_unlock;
09941366 4292
3e515705 4293 r = -EINVAL;
557abc40 4294 if (kvm->created_vcpus)
3e515705 4295 goto create_irqchip_unlock;
09941366
RK		 4296
4297 r = kvm_pic_init(kvm);
4298 if (r)
3ddea128 4299 goto create_irqchip_unlock;
09941366
RK		 4300
4301 r = kvm_ioapic_init(kvm);
4302 if (r) {
09941366 4303 kvm_pic_destroy(kvm);
3ddea128 4304 goto create_irqchip_unlock;
09941366
RK		 4305 }
4306
399ec807
AK		 4307 r = kvm_setup_default_irq_routing(kvm);
4308 if (r) {
72bb2fcd 4309 kvm_ioapic_destroy(kvm);
09941366 4310 kvm_pic_destroy(kvm);
71ba994c 4311 goto create_irqchip_unlock;
399ec807 4312 }
49776faf 4313 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4314 smp_wmb();
49776faf 4315 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4316 create_irqchip_unlock:
4317 mutex_unlock(&kvm->lock);
1fe779f8 4318 break;
3ddea128 4319 }
7837699f 4320 case KVM_CREATE_PIT:
c5ff41ce
JK		 4321 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4322 goto create_pit;
4323 case KVM_CREATE_PIT2:
4324 r = -EFAULT;
4325 if (copy_from_user(&u.pit_config, argp,
4326 sizeof(struct kvm_pit_config)))
4327 goto out;
4328 create_pit:
250715a6 4329 mutex_lock(&kvm->lock);
269e05e4
AK		 4330 r = -EEXIST;
4331 if (kvm->arch.vpit)
4332 goto create_pit_unlock;
7837699f 4333 r = -ENOMEM;
c5ff41ce 4334 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4335 if (kvm->arch.vpit)
4336 r = 0;
269e05e4 4337 create_pit_unlock:
250715a6 4338 mutex_unlock(&kvm->lock);
7837699f 4339 break;
1fe779f8
CO		 4340 case KVM_GET_IRQCHIP: {
4341 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4342 struct kvm_irqchip *chip;
1fe779f8 4343
ff5c2c03
SL		 4344 chip = memdup_user(argp, sizeof(*chip));
4345 if (IS_ERR(chip)) {
4346 r = PTR_ERR(chip);
1fe779f8 4347 goto out;
ff5c2c03
SL		 4348 }
4349
1fe779f8 4350 r = -ENXIO;
826da321 4351 if (!irqchip_kernel(kvm))
f0d66275
DH		 4352 goto get_irqchip_out;
4353 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4354 if (r)
f0d66275 4355 goto get_irqchip_out;
1fe779f8 4356 r = -EFAULT;
f0d66275
DH		 4357 if (copy_to_user(argp, chip, sizeof *chip))
4358 goto get_irqchip_out;
1fe779f8 4359 r = 0;
f0d66275
DH		 4360 get_irqchip_out:
4361 kfree(chip);
1fe779f8
CO		 4362 break;
4363 }
4364 case KVM_SET_IRQCHIP: {
4365 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4366 struct kvm_irqchip *chip;
1fe779f8 4367
ff5c2c03
SL		 4368 chip = memdup_user(argp, sizeof(*chip));
4369 if (IS_ERR(chip)) {
4370 r = PTR_ERR(chip);
1fe779f8 4371 goto out;
ff5c2c03
SL		 4372 }
4373
1fe779f8 4374 r = -ENXIO;
826da321 4375 if (!irqchip_kernel(kvm))
f0d66275
DH		 4376 goto set_irqchip_out;
4377 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4378 if (r)
f0d66275 4379 goto set_irqchip_out;
1fe779f8 4380 r = 0;
f0d66275
DH		 4381 set_irqchip_out:
4382 kfree(chip);
1fe779f8
CO		 4383 break;
4384 }
e0f63cb9 4385 case KVM_GET_PIT: {
e0f63cb9 4386 r = -EFAULT;
f0d66275 4387 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4388 goto out;
4389 r = -ENXIO;
4390 if (!kvm->arch.vpit)
4391 goto out;
f0d66275 4392 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4393 if (r)
4394 goto out;
4395 r = -EFAULT;
f0d66275 4396 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4397 goto out;
4398 r = 0;
4399 break;
4400 }
4401 case KVM_SET_PIT: {
e0f63cb9 4402 r = -EFAULT;
f0d66275 4403 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4404 goto out;
4405 r = -ENXIO;
4406 if (!kvm->arch.vpit)
4407 goto out;
f0d66275 4408 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4409 break;
4410 }
e9f42757
BK		 4411 case KVM_GET_PIT2: {
4412 r = -ENXIO;
4413 if (!kvm->arch.vpit)
4414 goto out;
4415 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4416 if (r)
4417 goto out;
4418 r = -EFAULT;
4419 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4420 goto out;
4421 r = 0;
4422 break;
4423 }
4424 case KVM_SET_PIT2: {
4425 r = -EFAULT;
4426 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4427 goto out;
4428 r = -ENXIO;
4429 if (!kvm->arch.vpit)
4430 goto out;
4431 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4432 break;
4433 }
52d939a0
MT		 4434 case KVM_REINJECT_CONTROL: {
4435 struct kvm_reinject_control control;
4436 r = -EFAULT;
4437 if (copy_from_user(&control, argp, sizeof(control)))
4438 goto out;
4439 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4440 break;
4441 }
d71ba788
PB		 4442 case KVM_SET_BOOT_CPU_ID:
4443 r = 0;
4444 mutex_lock(&kvm->lock);
557abc40 4445 if (kvm->created_vcpus)
d71ba788
PB		 4446 r = -EBUSY;
4447 else
4448 kvm->arch.bsp_vcpu_id = arg;
4449 mutex_unlock(&kvm->lock);
4450 break;
ffde22ac 4451 case KVM_XEN_HVM_CONFIG: {
51776043 4452 struct kvm_xen_hvm_config xhc;
ffde22ac 4453 r = -EFAULT;
51776043 4454 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4455 goto out;
4456 r = -EINVAL;
51776043 4457 if (xhc.flags)
ffde22ac 4458 goto out;
51776043 4459 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4460 r = 0;
4461 break;
4462 }
afbcf7ab 4463 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4464 struct kvm_clock_data user_ns;
4465 u64 now_ns;
afbcf7ab
GC		 4466
4467 r = -EFAULT;
4468 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4469 goto out;
4470
4471 r = -EINVAL;
4472 if (user_ns.flags)
4473 goto out;
4474
4475 r = 0;
0bc48bea
RK		 4476 /*
4477 * TODO: userspace has to take care of races with VCPU_RUN, so
4478 * kvm_gen_update_masterclock() can be cut down to locked
4479 * pvclock_update_vm_gtod_copy().
4480 */
4481 kvm_gen_update_masterclock(kvm);
e891a32e 4482 now_ns = get_kvmclock_ns(kvm);
108b249c 4483 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4484 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4485 break;
4486 }
4487 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4488 struct kvm_clock_data user_ns;
4489 u64 now_ns;
4490
e891a32e 4491 now_ns = get_kvmclock_ns(kvm);
108b249c 4492 user_ns.clock = now_ns;
e3fd9a93 4493 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4494 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4495
4496 r = -EFAULT;
4497 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4498 goto out;
4499 r = 0;
4500 break;
4501 }
90de4a18
NA		 4502 case KVM_ENABLE_CAP: {
4503 struct kvm_enable_cap cap;
afbcf7ab 4504
90de4a18
NA		 4505 r = -EFAULT;
4506 if (copy_from_user(&cap, argp, sizeof(cap)))
4507 goto out;
4508 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4509 break;
4510 }
5acc5c06
BS		 4511 case KVM_MEMORY_ENCRYPT_OP: {
4512 r = -ENOTTY;
4513 if (kvm_x86_ops->mem_enc_op)
4514 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4515 break;
4516 }
69eaedee
BS		 4517 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4518 struct kvm_enc_region region;
4519
4520 r = -EFAULT;
4521 if (copy_from_user(&region, argp, sizeof(region)))
4522 goto out;
4523
4524 r = -ENOTTY;
4525 if (kvm_x86_ops->mem_enc_reg_region)
4526 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4527 break;
4528 }
4529 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4530 struct kvm_enc_region region;
4531
4532 r = -EFAULT;
4533 if (copy_from_user(&region, argp, sizeof(region)))
4534 goto out;
4535
4536 r = -ENOTTY;
4537 if (kvm_x86_ops->mem_enc_unreg_region)
4538 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4539 break;
4540 }
faeb7833
RK		 4541 case KVM_HYPERV_EVENTFD: {
4542 struct kvm_hyperv_eventfd hvevfd;
4543
4544 r = -EFAULT;
4545 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4546 goto out;
4547 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4548 break;
4549 }
1fe779f8 4550 default:
ad6260da 4551 r = -ENOTTY;
1fe779f8
CO		 4552 }
4553out:
4554 return r;
4555}
4556
a16b043c 4557static void kvm_init_msr_list(void)
043405e1
CO		 4558{
4559 u32 dummy[2];
4560 unsigned i, j;
4561
62ef68bb 4562 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4563 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4564 continue;
93c4adc7
PB		 4565
4566 /*
4567 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4568 * to the guests in some cases.
93c4adc7
PB		 4569 */
4570 switch (msrs_to_save[i]) {
4571 case MSR_IA32_BNDCFGS:
4572 if (!kvm_x86_ops->mpx_supported())
4573 continue;
4574 break;
9dbe6cf9
PB		 4575 case MSR_TSC_AUX:
4576 if (!kvm_x86_ops->rdtscp_supported())
4577 continue;
4578 break;
93c4adc7
PB		 4579 default:
4580 break;
4581 }
4582
043405e1
CO		 4583 if (j < i)
4584 msrs_to_save[j] = msrs_to_save[i];
4585 j++;
4586 }
4587 num_msrs_to_save = j;
62ef68bb
PB		 4588
4589 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4590 switch (emulated_msrs[i]) {
6d396b55
PB		 4591 case MSR_IA32_SMBASE:
4592 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4593 continue;
4594 break;
62ef68bb
PB		 4595 default:
4596 break;
4597 }
4598
4599 if (j < i)
4600 emulated_msrs[j] = emulated_msrs[i];
4601 j++;
4602 }
4603 num_emulated_msrs = j;
801e459a
TL		 4604
4605 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4606 struct kvm_msr_entry msr;
4607
4608 msr.index = msr_based_features[i];
66421c1e 4609 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4610 continue;
4611
4612 if (j < i)
4613 msr_based_features[j] = msr_based_features[i];
4614 j++;
4615 }
4616 num_msr_based_features = j;
043405e1
CO		 4617}
4618
bda9020e
MT		 4619static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4620 const void *v)
bbd9b64e 4621{
70252a10
AK		 4622 int handled = 0;
4623 int n;
4624
4625 do {
4626 n = min(len, 8);
bce87cce 4627 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4628 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4629 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4630 break;
4631 handled += n;
4632 addr += n;
4633 len -= n;
4634 v += n;
4635 } while (len);
bbd9b64e 4636
70252a10 4637 return handled;
bbd9b64e
CO		 4638}
4639
bda9020e 4640static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4641{
70252a10
AK		 4642 int handled = 0;
4643 int n;
4644
4645 do {
4646 n = min(len, 8);
bce87cce 4647 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4648 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4649 addr, n, v))
4650 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4651 break;
e39d200f 4652 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4653 handled += n;
4654 addr += n;
4655 len -= n;
4656 v += n;
4657 } while (len);
bbd9b64e 4658
70252a10 4659 return handled;
bbd9b64e
CO		 4660}
4661
2dafc6c2
GN		 4662static void kvm_set_segment(struct kvm_vcpu *vcpu,
4663 struct kvm_segment *var, int seg)
4664{
4665 kvm_x86_ops->set_segment(vcpu, var, seg);
4666}
4667
4668void kvm_get_segment(struct kvm_vcpu *vcpu,
4669 struct kvm_segment *var, int seg)
4670{
4671 kvm_x86_ops->get_segment(vcpu, var, seg);
4672}
4673
54987b7a
PB		 4674gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4675 struct x86_exception *exception)
02f59dc9
JR		 4676{
4677 gpa_t t_gpa;
02f59dc9
JR		 4678
4679 BUG_ON(!mmu_is_nested(vcpu));
4680
4681 /* NPT walks are always user-walks */
4682 access |= PFERR_USER_MASK;
54987b7a 4683 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4684
4685 return t_gpa;
4686}
4687
ab9ae313
AK		 4688gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4689 struct x86_exception *exception)
1871c602
GN		 4690{
4691 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4692 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4693}
4694
ab9ae313
AK		 4695 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4696 struct x86_exception *exception)
1871c602
GN		 4697{
4698 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4699 access |= PFERR_FETCH_MASK;
ab9ae313 4700 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4701}
4702
ab9ae313
AK		 4703gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4704 struct x86_exception *exception)
1871c602
GN		 4705{
4706 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4707 access |= PFERR_WRITE_MASK;
ab9ae313 4708 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4709}
4710
4711/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4712gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4713 struct x86_exception *exception)
1871c602 4714{
ab9ae313 4715 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4716}
4717
4718static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4719 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4720 struct x86_exception *exception)
bbd9b64e
CO		 4721{
4722 void *data = val;
10589a46 4723 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4724
4725 while (bytes) {
14dfe855 4726 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4727 exception);
bbd9b64e 4728 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4729 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4730 int ret;
4731
bcc55cba 4732 if (gpa == UNMAPPED_GVA)
ab9ae313 4733 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4734 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4735 offset, toread);
10589a46 4736 if (ret < 0) {
c3cd7ffa 4737 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4738 goto out;
4739 }
bbd9b64e 4740
77c2002e
IE		 4741 bytes -= toread;
4742 data += toread;
4743 addr += toread;
bbd9b64e 4744 }
10589a46 4745out:
10589a46 4746 return r;
bbd9b64e 4747}
77c2002e 4748
1871c602 4749/* used for instruction fetching */
0f65dd70
AK		 4750static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4751 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4752 struct x86_exception *exception)
1871c602 4753{
0f65dd70 4754 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4755 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4756 unsigned offset;
4757 int ret;
0f65dd70 4758
44583cba
PB		 4759 /* Inline kvm_read_guest_virt_helper for speed. */
4760 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4761 exception);
4762 if (unlikely(gpa == UNMAPPED_GVA))
4763 return X86EMUL_PROPAGATE_FAULT;
4764
4765 offset = addr & (PAGE_SIZE-1);
4766 if (WARN_ON(offset + bytes > PAGE_SIZE))
4767 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4768 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4769 offset, bytes);
44583cba
PB		 4770 if (unlikely(ret < 0))
4771 return X86EMUL_IO_NEEDED;
4772
4773 return X86EMUL_CONTINUE;
1871c602
GN		 4774}
4775
064aea77 4776int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4777 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4778 struct x86_exception *exception)
1871c602 4779{
0f65dd70 4780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4781 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4782
1871c602 4783 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4784 exception);
1871c602 4785}
064aea77 4786EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4787
0f65dd70
AK		 4788static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4789 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4790 struct x86_exception *exception)
1871c602 4791{
0f65dd70 4792 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4793 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4794}
4795
7a036a6f
RK		 4796static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4797 unsigned long addr, void *val, unsigned int bytes)
4798{
4799 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4800 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4801
4802 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4803}
4804
6a4d7550 4805int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4806 gva_t addr, void *val,
2dafc6c2 4807 unsigned int bytes,
bcc55cba 4808 struct x86_exception *exception)
77c2002e 4809{
0f65dd70 4810 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4811 void *data = val;
4812 int r = X86EMUL_CONTINUE;
4813
4814 while (bytes) {
14dfe855
JR		 4815 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4816 PFERR_WRITE_MASK,
ab9ae313 4817 exception);
77c2002e
IE		 4818 unsigned offset = addr & (PAGE_SIZE-1);
4819 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4820 int ret;
4821
bcc55cba 4822 if (gpa == UNMAPPED_GVA)
ab9ae313 4823 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4824 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4825 if (ret < 0) {
c3cd7ffa 4826 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4827 goto out;
4828 }
4829
4830 bytes -= towrite;
4831 data += towrite;
4832 addr += towrite;
4833 }
4834out:
4835 return r;
4836}
6a4d7550 4837EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4838
0f89b207
TL		 4839static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4840 gpa_t gpa, bool write)
4841{
4842 /* For APIC access vmexit */
4843 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4844 return 1;
4845
4846 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4847 trace_vcpu_match_mmio(gva, gpa, write, true);
4848 return 1;
4849 }
4850
4851 return 0;
4852}
4853
af7cc7d1
XG		 4854static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4855 gpa_t *gpa, struct x86_exception *exception,
4856 bool write)
4857{
97d64b78
AK		 4858 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4859 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4860
be94f6b7
HH		 4861 /*
4862 * currently PKRU is only applied to ept enabled guest so
4863 * there is no pkey in EPT page table for L1 guest or EPT
4864 * shadow page table for L2 guest.
4865 */
97d64b78 4866 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4867 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4868 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4869 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4870 (gva & (PAGE_SIZE - 1));
4f022648 4871 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4872 return 1;
4873 }
4874
af7cc7d1
XG		 4875 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4876
4877 if (*gpa == UNMAPPED_GVA)
4878 return -1;
4879
0f89b207 4880 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4881}
4882
3200f405 4883int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4884 const void *val, int bytes)
bbd9b64e
CO		 4885{
4886 int ret;
4887
54bf36aa 4888 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4889 if (ret < 0)
bbd9b64e 4890 return 0;
0eb05bf2 4891 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4892 return 1;
4893}
4894
77d197b2
XG		 4895struct read_write_emulator_ops {
4896 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4897 int bytes);
4898 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4899 void *val, int bytes);
4900 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4901 int bytes, void *val);
4902 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4903 void *val, int bytes);
4904 bool write;
4905};
4906
4907static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4908{
4909 if (vcpu->mmio_read_completed) {
77d197b2 4910 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4911 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4912 vcpu->mmio_read_completed = 0;
4913 return 1;
4914 }
4915
4916 return 0;
4917}
4918
4919static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4920 void *val, int bytes)
4921{
54bf36aa 4922 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4923}
4924
4925static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4926 void *val, int bytes)
4927{
4928 return emulator_write_phys(vcpu, gpa, val, bytes);
4929}
4930
4931static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4932{
e39d200f 4933 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4934 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4935}
4936
4937static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4938 void *val, int bytes)
4939{
e39d200f 4940 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4941 return X86EMUL_IO_NEEDED;
4942}
4943
4944static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4945 void *val, int bytes)
4946{
f78146b0
AK		 4947 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4948
87da7e66 4949 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4950 return X86EMUL_CONTINUE;
4951}
4952
0fbe9b0b 4953static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4954 .read_write_prepare = read_prepare,
4955 .read_write_emulate = read_emulate,
4956 .read_write_mmio = vcpu_mmio_read,
4957 .read_write_exit_mmio = read_exit_mmio,
4958};
4959
0fbe9b0b 4960static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4961 .read_write_emulate = write_emulate,
4962 .read_write_mmio = write_mmio,
4963 .read_write_exit_mmio = write_exit_mmio,
4964 .write = true,
4965};
4966
22388a3c
XG		 4967static int emulator_read_write_onepage(unsigned long addr, void *val,
4968 unsigned int bytes,
4969 struct x86_exception *exception,
4970 struct kvm_vcpu *vcpu,
0fbe9b0b 4971 const struct read_write_emulator_ops *ops)
bbd9b64e 4972{
af7cc7d1
XG		 4973 gpa_t gpa;
4974 int handled, ret;
22388a3c 4975 bool write = ops->write;
f78146b0 4976 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4977 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4978
4979 /*
4980 * If the exit was due to a NPF we may already have a GPA.
4981 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4982 * Note, this cannot be used on string operations since string
4983 * operation using rep will only have the initial GPA from the NPF
4984 * occurred.
4985 */
4986 if (vcpu->arch.gpa_available &&
4987 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4988 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4989 gpa = vcpu->arch.gpa_val;
4990 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4991 } else {
4992 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4993 if (ret < 0)
4994 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4995 }
10589a46 4996
618232e2 4997 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4998 return X86EMUL_CONTINUE;
4999
bbd9b64e
CO		 5000 /*
5001 * Is this MMIO handled locally?
5002 */
22388a3c 5003 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5004 if (handled == bytes)
bbd9b64e 5005 return X86EMUL_CONTINUE;
bbd9b64e 5006
70252a10
AK		 5007 gpa += handled;
5008 bytes -= handled;
5009 val += handled;
5010
87da7e66
XG		 5011 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5012 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5013 frag->gpa = gpa;
5014 frag->data = val;
5015 frag->len = bytes;
f78146b0 5016 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5017}
5018
52eb5a6d
XL		 5019static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5020 unsigned long addr,
22388a3c
XG		 5021 void *val, unsigned int bytes,
5022 struct x86_exception *exception,
0fbe9b0b 5023 const struct read_write_emulator_ops *ops)
bbd9b64e 5024{
0f65dd70 5025 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5026 gpa_t gpa;
5027 int rc;
5028
5029 if (ops->read_write_prepare &&
5030 ops->read_write_prepare(vcpu, val, bytes))
5031 return X86EMUL_CONTINUE;
5032
5033 vcpu->mmio_nr_fragments = 0;
0f65dd70 5034
bbd9b64e
CO		 5035 /* Crossing a page boundary? */
5036 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5037 int now;
bbd9b64e
CO		 5038
5039 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5040 rc = emulator_read_write_onepage(addr, val, now, exception,
5041 vcpu, ops);
5042
bbd9b64e
CO		 5043 if (rc != X86EMUL_CONTINUE)
5044 return rc;
5045 addr += now;
bac15531
NA		 5046 if (ctxt->mode != X86EMUL_MODE_PROT64)
5047 addr = (u32)addr;
bbd9b64e
CO		 5048 val += now;
5049 bytes -= now;
5050 }
22388a3c 5051
f78146b0
AK		 5052 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5053 vcpu, ops);
5054 if (rc != X86EMUL_CONTINUE)
5055 return rc;
5056
5057 if (!vcpu->mmio_nr_fragments)
5058 return rc;
5059
5060 gpa = vcpu->mmio_fragments[0].gpa;
5061
5062 vcpu->mmio_needed = 1;
5063 vcpu->mmio_cur_fragment = 0;
5064
87da7e66 5065 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5066 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5067 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5068 vcpu->run->mmio.phys_addr = gpa;
5069
5070 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5071}
5072
5073static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5074 unsigned long addr,
5075 void *val,
5076 unsigned int bytes,
5077 struct x86_exception *exception)
5078{
5079 return emulator_read_write(ctxt, addr, val, bytes,
5080 exception, &read_emultor);
5081}
5082
52eb5a6d 5083static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5084 unsigned long addr,
5085 const void *val,
5086 unsigned int bytes,
5087 struct x86_exception *exception)
5088{
5089 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5090 exception, &write_emultor);
bbd9b64e 5091}
bbd9b64e 5092
daea3e73
AK		 5093#define CMPXCHG_TYPE(t, ptr, old, new) \
5094 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5095
5096#ifdef CONFIG_X86_64
5097# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5098#else
5099# define CMPXCHG64(ptr, old, new) \
9749a6c0 5100 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5101#endif
5102
0f65dd70
AK		 5103static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5104 unsigned long addr,
bbd9b64e
CO		 5105 const void *old,
5106 const void *new,
5107 unsigned int bytes,
0f65dd70 5108 struct x86_exception *exception)
bbd9b64e 5109{
0f65dd70 5110 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5111 gpa_t gpa;
5112 struct page *page;
5113 char *kaddr;
5114 bool exchanged;
2bacc55c 5115
daea3e73
AK		 5116 /* guests cmpxchg8b have to be emulated atomically */
5117 if (bytes > 8 || (bytes & (bytes - 1)))
5118 goto emul_write;
10589a46 5119
daea3e73 5120 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5121
daea3e73
AK		 5122 if (gpa == UNMAPPED_GVA ||
5123 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5124 goto emul_write;
2bacc55c 5125
daea3e73
AK		 5126 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5127 goto emul_write;
72dc67a6 5128
54bf36aa 5129 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5130 if (is_error_page(page))
c19b8bd6 5131 goto emul_write;
72dc67a6 5132
8fd75e12 5133 kaddr = kmap_atomic(page);
daea3e73
AK		 5134 kaddr += offset_in_page(gpa);
5135 switch (bytes) {
5136 case 1:
5137 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5138 break;
5139 case 2:
5140 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5141 break;
5142 case 4:
5143 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5144 break;
5145 case 8:
5146 exchanged = CMPXCHG64(kaddr, old, new);
5147 break;
5148 default:
5149 BUG();
2bacc55c 5150 }
8fd75e12 5151 kunmap_atomic(kaddr);
daea3e73
AK		 5152 kvm_release_page_dirty(page);
5153
5154 if (!exchanged)
5155 return X86EMUL_CMPXCHG_FAILED;
5156
54bf36aa 5157 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5158 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5159
5160 return X86EMUL_CONTINUE;
4a5f48f6 5161
3200f405 5162emul_write:
daea3e73 5163 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5164
0f65dd70 5165 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5166}
5167
cf8f70bf
GN		 5168static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5169{
cbfc6c91 5170 int r = 0, i;
cf8f70bf 5171
cbfc6c91
WL		 5172 for (i = 0; i < vcpu->arch.pio.count; i++) {
5173 if (vcpu->arch.pio.in)
5174 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5175 vcpu->arch.pio.size, pd);
5176 else
5177 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5178 vcpu->arch.pio.port, vcpu->arch.pio.size,
5179 pd);
5180 if (r)
5181 break;
5182 pd += vcpu->arch.pio.size;
5183 }
cf8f70bf
GN		 5184 return r;
5185}
5186
6f6fbe98
XG		 5187static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5188 unsigned short port, void *val,
5189 unsigned int count, bool in)
cf8f70bf 5190{
cf8f70bf 5191 vcpu->arch.pio.port = port;
6f6fbe98 5192 vcpu->arch.pio.in = in;
7972995b 5193 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5194 vcpu->arch.pio.size = size;
5195
5196 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5197 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5198 return 1;
5199 }
5200
5201 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5202 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5203 vcpu->run->io.size = size;
5204 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5205 vcpu->run->io.count = count;
5206 vcpu->run->io.port = port;
5207
5208 return 0;
5209}
5210
6f6fbe98
XG		 5211static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5212 int size, unsigned short port, void *val,
5213 unsigned int count)
cf8f70bf 5214{
ca1d4a9e 5215 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5216 int ret;
ca1d4a9e 5217
6f6fbe98
XG		 5218 if (vcpu->arch.pio.count)
5219 goto data_avail;
cf8f70bf 5220
cbfc6c91
WL		 5221 memset(vcpu->arch.pio_data, 0, size * count);
5222
6f6fbe98
XG		 5223 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5224 if (ret) {
5225data_avail:
5226 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5227 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5228 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5229 return 1;
5230 }
5231
cf8f70bf
GN		 5232 return 0;
5233}
5234
6f6fbe98
XG		 5235static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5236 int size, unsigned short port,
5237 const void *val, unsigned int count)
5238{
5239 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5240
5241 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5242 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5243 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5244}
5245
bbd9b64e
CO		 5246static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5247{
5248 return kvm_x86_ops->get_segment_base(vcpu, seg);
5249}
5250
3cb16fe7 5251static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5252{
3cb16fe7 5253 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5254}
5255
ae6a2375 5256static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5257{
5258 if (!need_emulate_wbinvd(vcpu))
5259 return X86EMUL_CONTINUE;
5260
5261 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5262 int cpu = get_cpu();
5263
5264 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5265 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5266 wbinvd_ipi, NULL, 1);
2eec7343 5267 put_cpu();
f5f48ee1 5268 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5269 } else
5270 wbinvd();
f5f48ee1
SY		 5271 return X86EMUL_CONTINUE;
5272}
5cb56059
JS		 5273
5274int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5275{
6affcbed
KH		 5276 kvm_emulate_wbinvd_noskip(vcpu);
5277 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5278}
f5f48ee1
SY		 5279EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5280
5cb56059
JS		 5281
5282
bcaf5cc5
AK		 5283static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5284{
5cb56059 5285 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5286}
5287
52eb5a6d
XL		 5288static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5289 unsigned long *dest)
bbd9b64e 5290{
16f8a6f9 5291 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5292}
5293
52eb5a6d
XL		 5294static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5295 unsigned long value)
bbd9b64e 5296{
338dbc97 5297
717746e3 5298 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5299}
5300
52a46617 5301static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5302{
52a46617 5303 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5304}
5305
717746e3 5306static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5307{
717746e3 5308 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5309 unsigned long value;
5310
5311 switch (cr) {
5312 case 0:
5313 value = kvm_read_cr0(vcpu);
5314 break;
5315 case 2:
5316 value = vcpu->arch.cr2;
5317 break;
5318 case 3:
9f8fe504 5319 value = kvm_read_cr3(vcpu);
52a46617
GN		 5320 break;
5321 case 4:
5322 value = kvm_read_cr4(vcpu);
5323 break;
5324 case 8:
5325 value = kvm_get_cr8(vcpu);
5326 break;
5327 default:
a737f256 5328 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5329 return 0;
5330 }
5331
5332 return value;
5333}
5334
717746e3 5335static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5336{
717746e3 5337 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5338 int res = 0;
5339
52a46617
GN		 5340 switch (cr) {
5341 case 0:
49a9b07e 5342 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5343 break;
5344 case 2:
5345 vcpu->arch.cr2 = val;
5346 break;
5347 case 3:
2390218b 5348 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5349 break;
5350 case 4:
a83b29c6 5351 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5352 break;
5353 case 8:
eea1cff9 5354 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5355 break;
5356 default:
a737f256 5357 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5358 res = -1;
52a46617 5359 }
0f12244f
GN		 5360
5361 return res;
52a46617
GN		 5362}
5363
717746e3 5364static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5365{
717746e3 5366 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5367}
5368
4bff1e86 5369static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5370{
4bff1e86 5371 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5372}
5373
4bff1e86 5374static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5375{
4bff1e86 5376 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5377}
5378
1ac9d0cf
AK		 5379static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5380{
5381 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5382}
5383
5384static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5385{
5386 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5387}
5388
4bff1e86
AK		 5389static unsigned long emulator_get_cached_segment_base(
5390 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5391{
4bff1e86 5392 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5393}
5394
1aa36616
AK		 5395static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5396 struct desc_struct *desc, u32 *base3,
5397 int seg)
2dafc6c2
GN		 5398{
5399 struct kvm_segment var;
5400
4bff1e86 5401 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5402 *selector = var.selector;
2dafc6c2 5403
378a8b09
GN		 5404 if (var.unusable) {
5405 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5406 if (base3)
5407 *base3 = 0;
2dafc6c2 5408 return false;
378a8b09 5409 }
2dafc6c2
GN		 5410
5411 if (var.g)
5412 var.limit >>= 12;
5413 set_desc_limit(desc, var.limit);
5414 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5415#ifdef CONFIG_X86_64
5416 if (base3)
5417 *base3 = var.base >> 32;
5418#endif
2dafc6c2
GN		 5419 desc->type = var.type;
5420 desc->s = var.s;
5421 desc->dpl = var.dpl;
5422 desc->p = var.present;
5423 desc->avl = var.avl;
5424 desc->l = var.l;
5425 desc->d = var.db;
5426 desc->g = var.g;
5427
5428 return true;
5429}
5430
1aa36616
AK		 5431static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5432 struct desc_struct *desc, u32 base3,
5433 int seg)
2dafc6c2 5434{
4bff1e86 5435 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5436 struct kvm_segment var;
5437
1aa36616 5438 var.selector = selector;
2dafc6c2 5439 var.base = get_desc_base(desc);
5601d05b
GN		 5440#ifdef CONFIG_X86_64
5441 var.base |= ((u64)base3) << 32;
5442#endif
2dafc6c2
GN		 5443 var.limit = get_desc_limit(desc);
5444 if (desc->g)
5445 var.limit = (var.limit << 12) | 0xfff;
5446 var.type = desc->type;
2dafc6c2
GN		 5447 var.dpl = desc->dpl;
5448 var.db = desc->d;
5449 var.s = desc->s;
5450 var.l = desc->l;
5451 var.g = desc->g;
5452 var.avl = desc->avl;
5453 var.present = desc->p;
5454 var.unusable = !var.present;
5455 var.padding = 0;
5456
5457 kvm_set_segment(vcpu, &var, seg);
5458 return;
5459}
5460
717746e3
AK		 5461static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5462 u32 msr_index, u64 *pdata)
5463{
609e36d3
PB		 5464 struct msr_data msr;
5465 int r;
5466
5467 msr.index = msr_index;
5468 msr.host_initiated = false;
5469 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5470 if (r)
5471 return r;
5472
5473 *pdata = msr.data;
5474 return 0;
717746e3
AK		 5475}
5476
5477static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5478 u32 msr_index, u64 data)
5479{
8fe8ab46
WA		 5480 struct msr_data msr;
5481
5482 msr.data = data;
5483 msr.index = msr_index;
5484 msr.host_initiated = false;
5485 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5486}
5487
64d60670
PB		 5488static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5489{
5490 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5491
5492 return vcpu->arch.smbase;
5493}
5494
5495static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5496{
5497 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5498
5499 vcpu->arch.smbase = smbase;
5500}
5501
67f4d428
NA		 5502static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5503 u32 pmc)
5504{
c6702c9d 5505 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5506}
5507
222d21aa
AK		 5508static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5509 u32 pmc, u64 *pdata)
5510{
c6702c9d 5511 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5512}
5513
6c3287f7
AK		 5514static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5515{
5516 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5517}
5518
2953538e 5519static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5520 struct x86_instruction_info *info,
c4f035c6
AK		 5521 enum x86_intercept_stage stage)
5522{
2953538e 5523 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5524}
5525
e911eb3b
YZ		 5526static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5527 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5528{
e911eb3b 5529 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5530}
5531
dd856efa
AK		 5532static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5533{
5534 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5535}
5536
5537static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5538{
5539 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5540}
5541
801806d9
NA		 5542static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5543{
5544 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5545}
5546
6ed071f0
LP		 5547static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5548{
5549 return emul_to_vcpu(ctxt)->arch.hflags;
5550}
5551
5552static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5553{
5554 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5555}
5556
0234bf88
LP		 5557static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5558{
5559 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5560}
5561
0225fb50 5562static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5563 .read_gpr = emulator_read_gpr,
5564 .write_gpr = emulator_write_gpr,
1871c602 5565 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5566 .write_std = kvm_write_guest_virt_system,
7a036a6f 5567 .read_phys = kvm_read_guest_phys_system,
1871c602 5568 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5569 .read_emulated = emulator_read_emulated,
5570 .write_emulated = emulator_write_emulated,
5571 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5572 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5573 .pio_in_emulated = emulator_pio_in_emulated,
5574 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5575 .get_segment = emulator_get_segment,
5576 .set_segment = emulator_set_segment,
5951c442 5577 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5578 .get_gdt = emulator_get_gdt,
160ce1f1 5579 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5580 .set_gdt = emulator_set_gdt,
5581 .set_idt = emulator_set_idt,
52a46617
GN		 5582 .get_cr = emulator_get_cr,
5583 .set_cr = emulator_set_cr,
9c537244 5584 .cpl = emulator_get_cpl,
35aa5375
GN		 5585 .get_dr = emulator_get_dr,
5586 .set_dr = emulator_set_dr,
64d60670
PB		 5587 .get_smbase = emulator_get_smbase,
5588 .set_smbase = emulator_set_smbase,
717746e3
AK		 5589 .set_msr = emulator_set_msr,
5590 .get_msr = emulator_get_msr,
67f4d428 5591 .check_pmc = emulator_check_pmc,
222d21aa 5592 .read_pmc = emulator_read_pmc,
6c3287f7 5593 .halt = emulator_halt,
bcaf5cc5 5594 .wbinvd = emulator_wbinvd,
d6aa1000 5595 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5596 .intercept = emulator_intercept,
bdb42f5a 5597 .get_cpuid = emulator_get_cpuid,
801806d9 5598 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5599 .get_hflags = emulator_get_hflags,
5600 .set_hflags = emulator_set_hflags,
0234bf88 5601 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5602};
5603
95cb2295
GN		 5604static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5605{
37ccdcbe 5606 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5607 /*
5608 * an sti; sti; sequence only disable interrupts for the first
5609 * instruction. So, if the last instruction, be it emulated or
5610 * not, left the system with the INT_STI flag enabled, it
5611 * means that the last instruction is an sti. We should not
5612 * leave the flag on in this case. The same goes for mov ss
5613 */
37ccdcbe
PB		 5614 if (int_shadow & mask)
5615 mask = 0;
6addfc42 5616 if (unlikely(int_shadow || mask)) {
95cb2295 5617 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5618 if (!mask)
5619 kvm_make_request(KVM_REQ_EVENT, vcpu);
5620 }
95cb2295
GN		 5621}
5622
ef54bcfe 5623static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5624{
5625 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5626 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5627 return kvm_propagate_fault(vcpu, &ctxt->exception);
5628
5629 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5630 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5631 ctxt->exception.error_code);
54b8486f 5632 else
da9cb575 5633 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5634 return false;
54b8486f
GN		 5635}
5636
8ec4722d
MG		 5637static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5638{
adf52235 5639 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5640 int cs_db, cs_l;
5641
8ec4722d
MG		 5642 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5643
adf52235 5644 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5645 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5646
adf52235
TY		 5647 ctxt->eip = kvm_rip_read(vcpu);
5648 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5649 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5650 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5651 cs_db ? X86EMUL_MODE_PROT32 :
5652 X86EMUL_MODE_PROT16;
a584539b 5653 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5654 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5655 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5656
dd856efa 5657 init_decode_cache(ctxt);
7ae441ea 5658 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5659}
5660
71f9833b 5661int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5662{
9d74191a 5663 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5664 int ret;
5665
5666 init_emulate_ctxt(vcpu);
5667
9dac77fa
AK		 5668 ctxt->op_bytes = 2;
5669 ctxt->ad_bytes = 2;
5670 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5671 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5672
5673 if (ret != X86EMUL_CONTINUE)
5674 return EMULATE_FAIL;
5675
9dac77fa 5676 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5677 kvm_rip_write(vcpu, ctxt->eip);
5678 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5679
5680 if (irq == NMI_VECTOR)
7460fb4a 5681 vcpu->arch.nmi_pending = 0;
63995653
MG		 5682 else
5683 vcpu->arch.interrupt.pending = false;
5684
5685 return EMULATE_DONE;
5686}
5687EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5688
e2366171 5689static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5690{
fc3a9157
JR		 5691 int r = EMULATE_DONE;
5692
6d77dbfc
GN		 5693 ++vcpu->stat.insn_emulation_fail;
5694 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5695
5696 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5697 return EMULATE_FAIL;
5698
a2b9e6c1 5699 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5700 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5701 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5702 vcpu->run->internal.ndata = 0;
1f4dcb3b 5703 r = EMULATE_USER_EXIT;
fc3a9157 5704 }
e2366171 5705
6d77dbfc 5706 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5707
5708 return r;
6d77dbfc
GN		 5709}
5710
93c05d3e 5711static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5712 bool write_fault_to_shadow_pgtable,
5713 int emulation_type)
a6f177ef 5714{
95b3cf69 5715 gpa_t gpa = cr2;
ba049e93 5716 kvm_pfn_t pfn;
a6f177ef 5717
991eebf9
GN		 5718 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5719 return false;
5720
95b3cf69
XG		 5721 if (!vcpu->arch.mmu.direct_map) {
5722 /*
5723 * Write permission should be allowed since only
5724 * write access need to be emulated.
5725 */
5726 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5727
95b3cf69
XG		 5728 /*
5729 * If the mapping is invalid in guest, let cpu retry
5730 * it to generate fault.
5731 */
5732 if (gpa == UNMAPPED_GVA)
5733 return true;
5734 }
a6f177ef 5735
8e3d9d06
XG		 5736 /*
5737 * Do not retry the unhandleable instruction if it faults on the
5738 * readonly host memory, otherwise it will goto a infinite loop:
5739 * retry instruction -> write #PF -> emulation fail -> retry
5740 * instruction -> ...
5741 */
5742 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5743
5744 /*
5745 * If the instruction failed on the error pfn, it can not be fixed,
5746 * report the error to userspace.
5747 */
5748 if (is_error_noslot_pfn(pfn))
5749 return false;
5750
5751 kvm_release_pfn_clean(pfn);
5752
5753 /* The instructions are well-emulated on direct mmu. */
5754 if (vcpu->arch.mmu.direct_map) {
5755 unsigned int indirect_shadow_pages;
5756
5757 spin_lock(&vcpu->kvm->mmu_lock);
5758 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5759 spin_unlock(&vcpu->kvm->mmu_lock);
5760
5761 if (indirect_shadow_pages)
5762 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5763
a6f177ef 5764 return true;
8e3d9d06 5765 }
a6f177ef 5766
95b3cf69
XG		 5767 /*
5768 * if emulation was due to access to shadowed page table
5769 * and it failed try to unshadow page and re-enter the
5770 * guest to let CPU execute the instruction.
5771 */
5772 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5773
5774 /*
5775 * If the access faults on its page table, it can not
5776 * be fixed by unprotecting shadow page and it should
5777 * be reported to userspace.
5778 */
5779 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5780}
5781
1cb3f3ae
XG		 5782static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5783 unsigned long cr2, int emulation_type)
5784{
5785 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5786 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5787
5788 last_retry_eip = vcpu->arch.last_retry_eip;
5789 last_retry_addr = vcpu->arch.last_retry_addr;
5790
5791 /*
5792 * If the emulation is caused by #PF and it is non-page_table
5793 * writing instruction, it means the VM-EXIT is caused by shadow
5794 * page protected, we can zap the shadow page and retry this
5795 * instruction directly.
5796 *
5797 * Note: if the guest uses a non-page-table modifying instruction
5798 * on the PDE that points to the instruction, then we will unmap
5799 * the instruction and go to an infinite loop. So, we cache the
5800 * last retried eip and the last fault address, if we meet the eip
5801 * and the address again, we can break out of the potential infinite
5802 * loop.
5803 */
5804 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5805
5806 if (!(emulation_type & EMULTYPE_RETRY))
5807 return false;
5808
5809 if (x86_page_table_writing_insn(ctxt))
5810 return false;
5811
5812 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5813 return false;
5814
5815 vcpu->arch.last_retry_eip = ctxt->eip;
5816 vcpu->arch.last_retry_addr = cr2;
5817
5818 if (!vcpu->arch.mmu.direct_map)
5819 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5820
22368028 5821 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5822
5823 return true;
5824}
5825
716d51ab
GN		 5826static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5827static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5828
64d60670 5829static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5830{
64d60670 5831 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5832 /* This is a good place to trace that we are exiting SMM. */
5833 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5834
c43203ca
PB		 5835 /* Process a latched INIT or SMI, if any. */
5836 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5837 }
699023e2
PB		 5838
5839 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5840}
5841
5842static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5843{
5844 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5845
a584539b 5846 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5847
5848 if (changed & HF_SMM_MASK)
5849 kvm_smm_changed(vcpu);
a584539b
PB		 5850}
5851
4a1e10d5
PB		 5852static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5853 unsigned long *db)
5854{
5855 u32 dr6 = 0;
5856 int i;
5857 u32 enable, rwlen;
5858
5859 enable = dr7;
5860 rwlen = dr7 >> 16;
5861 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5862 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5863 dr6 |= (1 << i);
5864 return dr6;
5865}
5866
c8401dda 5867static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5868{
5869 struct kvm_run *kvm_run = vcpu->run;
5870
c8401dda
PB		 5871 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5872 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5873 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5874 kvm_run->debug.arch.exception = DB_VECTOR;
5875 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5876 *r = EMULATE_USER_EXIT;
5877 } else {
5878 /*
5879 * "Certain debug exceptions may clear bit 0-3. The
5880 * remaining contents of the DR6 register are never
5881 * cleared by the processor".
5882 */
5883 vcpu->arch.dr6 &= ~15;
5884 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5885 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5886 }
5887}
5888
6affcbed
KH		 5889int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5890{
5891 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5892 int r = EMULATE_DONE;
5893
5894 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5895
5896 /*
5897 * rflags is the old, "raw" value of the flags. The new value has
5898 * not been saved yet.
5899 *
5900 * This is correct even for TF set by the guest, because "the
5901 * processor will not generate this exception after the instruction
5902 * that sets the TF flag".
5903 */
5904 if (unlikely(rflags & X86_EFLAGS_TF))
5905 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5906 return r == EMULATE_DONE;
5907}
5908EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5909
4a1e10d5
PB		 5910static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5911{
4a1e10d5
PB		 5912 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5913 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5914 struct kvm_run *kvm_run = vcpu->run;
5915 unsigned long eip = kvm_get_linear_rip(vcpu);
5916 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5917 vcpu->arch.guest_debug_dr7,
5918 vcpu->arch.eff_db);
5919
5920 if (dr6 != 0) {
6f43ed01 5921 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5922 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5923 kvm_run->debug.arch.exception = DB_VECTOR;
5924 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5925 *r = EMULATE_USER_EXIT;
5926 return true;
5927 }
5928 }
5929
4161a569
NA		 5930 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5931 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5932 unsigned long eip = kvm_get_linear_rip(vcpu);
5933 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5934 vcpu->arch.dr7,
5935 vcpu->arch.db);
5936
5937 if (dr6 != 0) {
5938 vcpu->arch.dr6 &= ~15;
6f43ed01 5939 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5940 kvm_queue_exception(vcpu, DB_VECTOR);
5941 *r = EMULATE_DONE;
5942 return true;
5943 }
5944 }
5945
5946 return false;
5947}
5948
04789b66
LA		 5949static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
5950{
2d7921c4
AM		 5951 switch (ctxt->opcode_len) {
5952 case 1:
5953 switch (ctxt->b) {
5954 case 0xe4: /* IN */
5955 case 0xe5:
5956 case 0xec:
5957 case 0xed:
5958 case 0xe6: /* OUT */
5959 case 0xe7:
5960 case 0xee:
5961 case 0xef:
5962 case 0x6c: /* INS */
5963 case 0x6d:
5964 case 0x6e: /* OUTS */
5965 case 0x6f:
5966 return true;
5967 }
5968 break;
5969 case 2:
5970 switch (ctxt->b) {
5971 case 0x33: /* RDPMC */
5972 return true;
5973 }
5974 break;
04789b66
LA		 5975 }
5976
5977 return false;
5978}
5979
51d8b661
AP		 5980int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5981 unsigned long cr2,
dc25e89e
AP		 5982 int emulation_type,
5983 void *insn,
5984 int insn_len)
bbd9b64e 5985{
95cb2295 5986 int r;
9d74191a 5987 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5988 bool writeback = true;
93c05d3e 5989 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5990
93c05d3e
XG		 5991 /*
5992 * Clear write_fault_to_shadow_pgtable here to ensure it is
5993 * never reused.
5994 */
5995 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5996 kvm_clear_exception_queue(vcpu);
8d7d8102 5997
571008da 5998 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5999 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6000
6001 /*
6002 * We will reenter on the same instruction since
6003 * we do not set complete_userspace_io. This does not
6004 * handle watchpoints yet, those would be handled in
6005 * the emulate_ops.
6006 */
d391f120
VK		 6007 if (!(emulation_type & EMULTYPE_SKIP) &&
6008 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6009 return r;
6010
9d74191a
TY		 6011 ctxt->interruptibility = 0;
6012 ctxt->have_exception = false;
e0ad0b47 6013 ctxt->exception.vector = -1;
9d74191a 6014 ctxt->perm_ok = false;
bbd9b64e 6015
b51e974f 6016 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6017
9d74191a 6018 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6019
e46479f8 6020 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6021 ++vcpu->stat.insn_emulation;
1d2887e2 6022 if (r != EMULATION_OK) {
4005996e
AK		 6023 if (emulation_type & EMULTYPE_TRAP_UD)
6024 return EMULATE_FAIL;
991eebf9
GN		 6025 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6026 emulation_type))
bbd9b64e 6027 return EMULATE_DONE;
6ea6e843
PB		 6028 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6029 return EMULATE_DONE;
6d77dbfc
GN		 6030 if (emulation_type & EMULTYPE_SKIP)
6031 return EMULATE_FAIL;
e2366171 6032 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6033 }
6034 }
6035
04789b66
LA		 6036 if ((emulation_type & EMULTYPE_VMWARE) &&
6037 !is_vmware_backdoor_opcode(ctxt))
6038 return EMULATE_FAIL;
6039
ba8afb6b 6040 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6041 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6042 if (ctxt->eflags & X86_EFLAGS_RF)
6043 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6044 return EMULATE_DONE;
6045 }
6046
1cb3f3ae
XG		 6047 if (retry_instruction(ctxt, cr2, emulation_type))
6048 return EMULATE_DONE;
6049
7ae441ea 6050 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6051 changes registers values during IO operation */
7ae441ea
GN		 6052 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6053 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6054 emulator_invalidate_register_cache(ctxt);
7ae441ea 6055 }
4d2179e1 6056
5cd21917 6057restart:
0f89b207
TL		 6058 /* Save the faulting GPA (cr2) in the address field */
6059 ctxt->exception.address = cr2;
6060
9d74191a 6061 r = x86_emulate_insn(ctxt);
bbd9b64e 6062
775fde86
JR		 6063 if (r == EMULATION_INTERCEPTED)
6064 return EMULATE_DONE;
6065
d2ddd1c4 6066 if (r == EMULATION_FAILED) {
991eebf9
GN		 6067 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6068 emulation_type))
c3cd7ffa
GN		 6069 return EMULATE_DONE;
6070
e2366171 6071 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6072 }
6073
9d74191a 6074 if (ctxt->have_exception) {
d2ddd1c4 6075 r = EMULATE_DONE;
ef54bcfe
PB		 6076 if (inject_emulated_exception(vcpu))
6077 return r;
d2ddd1c4 6078 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6079 if (!vcpu->arch.pio.in) {
6080 /* FIXME: return into emulator if single-stepping. */
3457e419 6081 vcpu->arch.pio.count = 0;
0912c977 6082 } else {
7ae441ea 6083 writeback = false;
716d51ab
GN		 6084 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6085 }
ac0a48c3 6086 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6087 } else if (vcpu->mmio_needed) {
6088 if (!vcpu->mmio_is_write)
6089 writeback = false;
ac0a48c3 6090 r = EMULATE_USER_EXIT;
716d51ab 6091 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6092 } else if (r == EMULATION_RESTART)
5cd21917 6093 goto restart;
d2ddd1c4
GN		 6094 else
6095 r = EMULATE_DONE;
f850e2e6 6096
7ae441ea 6097 if (writeback) {
6addfc42 6098 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6099 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6100 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6101 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6102 if (r == EMULATE_DONE &&
6103 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6104 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6105 if (!ctxt->have_exception ||
6106 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6107 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6108
6109 /*
6110 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6111 * do nothing, and it will be requested again as soon as
6112 * the shadow expires. But we still need to check here,
6113 * because POPF has no interrupt shadow.
6114 */
6115 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6116 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6117 } else
6118 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6119
6120 return r;
de7d789a 6121}
51d8b661 6122EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6123
dca7f128
SC		 6124static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6125 unsigned short port)
de7d789a 6126{
cf8f70bf 6127 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6128 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6129 size, port, &val, 1);
cf8f70bf 6130 /* do not return to emulator after return from userspace */
7972995b 6131 vcpu->arch.pio.count = 0;
de7d789a
CO		 6132 return ret;
6133}
de7d789a 6134
8370c3d0
TL		 6135static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6136{
6137 unsigned long val;
6138
6139 /* We should only ever be called with arch.pio.count equal to 1 */
6140 BUG_ON(vcpu->arch.pio.count != 1);
6141
6142 /* For size less than 4 we merge, else we zero extend */
6143 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6144 : 0;
6145
6146 /*
6147 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6148 * the copy and tracing
6149 */
6150 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6151 vcpu->arch.pio.port, &val, 1);
6152 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6153
6154 return 1;
6155}
6156
dca7f128
SC		 6157static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6158 unsigned short port)
8370c3d0
TL		 6159{
6160 unsigned long val;
6161 int ret;
6162
6163 /* For size less than 4 we merge, else we zero extend */
6164 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6165
6166 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6167 &val, 1);
6168 if (ret) {
6169 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6170 return ret;
6171 }
6172
6173 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6174
6175 return 0;
6176}
dca7f128
SC		 6177
6178int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6179{
6180 int ret = kvm_skip_emulated_instruction(vcpu);
6181
6182 /*
6183 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6184 * KVM_EXIT_DEBUG here.
6185 */
6186 if (in)
6187 return kvm_fast_pio_in(vcpu, size, port) && ret;
6188 else
6189 return kvm_fast_pio_out(vcpu, size, port) && ret;
6190}
6191EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6192
251a5fd6 6193static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6194{
0a3aee0d 6195 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6196 return 0;
8cfdc000
ZA		 6197}
6198
6199static void tsc_khz_changed(void *data)
c8076604 6200{
8cfdc000
ZA		 6201 struct cpufreq_freqs *freq = data;
6202 unsigned long khz = 0;
6203
6204 if (data)
6205 khz = freq->new;
6206 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6207 khz = cpufreq_quick_get(raw_smp_processor_id());
6208 if (!khz)
6209 khz = tsc_khz;
0a3aee0d 6210 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6211}
6212
5fa4ec9c 6213#ifdef CONFIG_X86_64
0092e434
VK		 6214static void kvm_hyperv_tsc_notifier(void)
6215{
0092e434
VK		 6216 struct kvm *kvm;
6217 struct kvm_vcpu *vcpu;
6218 int cpu;
6219
6220 spin_lock(&kvm_lock);
6221 list_for_each_entry(kvm, &vm_list, vm_list)
6222 kvm_make_mclock_inprogress_request(kvm);
6223
6224 hyperv_stop_tsc_emulation();
6225
6226 /* TSC frequency always matches when on Hyper-V */
6227 for_each_present_cpu(cpu)
6228 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6229 kvm_max_guest_tsc_khz = tsc_khz;
6230
6231 list_for_each_entry(kvm, &vm_list, vm_list) {
6232 struct kvm_arch *ka = &kvm->arch;
6233
6234 spin_lock(&ka->pvclock_gtod_sync_lock);
6235
6236 pvclock_update_vm_gtod_copy(kvm);
6237
6238 kvm_for_each_vcpu(cpu, vcpu, kvm)
6239 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6240
6241 kvm_for_each_vcpu(cpu, vcpu, kvm)
6242 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6243
6244 spin_unlock(&ka->pvclock_gtod_sync_lock);
6245 }
6246 spin_unlock(&kvm_lock);
0092e434 6247}
5fa4ec9c 6248#endif
0092e434 6249
c8076604
GH		 6250static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6251 void *data)
6252{
6253 struct cpufreq_freqs *freq = data;
6254 struct kvm *kvm;
6255 struct kvm_vcpu *vcpu;
6256 int i, send_ipi = 0;
6257
8cfdc000
ZA		 6258 /*
6259 * We allow guests to temporarily run on slowing clocks,
6260 * provided we notify them after, or to run on accelerating
6261 * clocks, provided we notify them before. Thus time never
6262 * goes backwards.
6263 *
6264 * However, we have a problem. We can't atomically update
6265 * the frequency of a given CPU from this function; it is
6266 * merely a notifier, which can be called from any CPU.
6267 * Changing the TSC frequency at arbitrary points in time
6268 * requires a recomputation of local variables related to
6269 * the TSC for each VCPU. We must flag these local variables
6270 * to be updated and be sure the update takes place with the
6271 * new frequency before any guests proceed.
6272 *
6273 * Unfortunately, the combination of hotplug CPU and frequency
6274 * change creates an intractable locking scenario; the order
6275 * of when these callouts happen is undefined with respect to
6276 * CPU hotplug, and they can race with each other. As such,
6277 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6278 * undefined; you can actually have a CPU frequency change take
6279 * place in between the computation of X and the setting of the
6280 * variable. To protect against this problem, all updates of
6281 * the per_cpu tsc_khz variable are done in an interrupt
6282 * protected IPI, and all callers wishing to update the value
6283 * must wait for a synchronous IPI to complete (which is trivial
6284 * if the caller is on the CPU already). This establishes the
6285 * necessary total order on variable updates.
6286 *
6287 * Note that because a guest time update may take place
6288 * anytime after the setting of the VCPU's request bit, the
6289 * correct TSC value must be set before the request. However,
6290 * to ensure the update actually makes it to any guest which
6291 * starts running in hardware virtualization between the set
6292 * and the acquisition of the spinlock, we must also ping the
6293 * CPU after setting the request bit.
6294 *
6295 */
6296
c8076604
GH		 6297 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6298 return 0;
6299 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6300 return 0;
8cfdc000
ZA		 6301
6302 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6303
2f303b74 6304 spin_lock(&kvm_lock);
c8076604 6305 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6306 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6307 if (vcpu->cpu != freq->cpu)
6308 continue;
c285545f 6309 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6310 if (vcpu->cpu != smp_processor_id())
8cfdc000 6311 send_ipi = 1;
c8076604
GH		 6312 }
6313 }
2f303b74 6314 spin_unlock(&kvm_lock);
c8076604
GH		 6315
6316 if (freq->old < freq->new && send_ipi) {
6317 /*
6318 * We upscale the frequency. Must make the guest
6319 * doesn't see old kvmclock values while running with
6320 * the new frequency, otherwise we risk the guest sees
6321 * time go backwards.
6322 *
6323 * In case we update the frequency for another cpu
6324 * (which might be in guest context) send an interrupt
6325 * to kick the cpu out of guest context. Next time
6326 * guest context is entered kvmclock will be updated,
6327 * so the guest will not see stale values.
6328 */
8cfdc000 6329 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6330 }
6331 return 0;
6332}
6333
6334static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6335 .notifier_call = kvmclock_cpufreq_notifier
6336};
6337
251a5fd6 6338static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6339{
251a5fd6
SAS		 6340 tsc_khz_changed(NULL);
6341 return 0;
8cfdc000
ZA		 6342}
6343
b820cc0c
ZA		 6344static void kvm_timer_init(void)
6345{
c285545f 6346 max_tsc_khz = tsc_khz;
460dd42e 6347
b820cc0c 6348 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6349#ifdef CONFIG_CPU_FREQ
6350 struct cpufreq_policy policy;
758f588d
BP		 6351 int cpu;
6352
c285545f 6353 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6354 cpu = get_cpu();
6355 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6356 if (policy.cpuinfo.max_freq)
6357 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6358 put_cpu();
c285545f 6359#endif
b820cc0c
ZA		 6360 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6361 CPUFREQ_TRANSITION_NOTIFIER);
6362 }
c285545f 6363 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6364
73c1b41e 6365 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6366 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6367}
6368
ff9d07a0
ZY		 6369static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6370
f5132b01 6371int kvm_is_in_guest(void)
ff9d07a0 6372{
086c9855 6373 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6374}
6375
6376static int kvm_is_user_mode(void)
6377{
6378 int user_mode = 3;
dcf46b94 6379
086c9855
AS		 6380 if (__this_cpu_read(current_vcpu))
6381 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6382
ff9d07a0
ZY		 6383 return user_mode != 0;
6384}
6385
6386static unsigned long kvm_get_guest_ip(void)
6387{
6388 unsigned long ip = 0;
dcf46b94 6389
086c9855
AS		 6390 if (__this_cpu_read(current_vcpu))
6391 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6392
ff9d07a0
ZY		 6393 return ip;
6394}
6395
6396static struct perf_guest_info_callbacks kvm_guest_cbs = {
6397 .is_in_guest = kvm_is_in_guest,
6398 .is_user_mode = kvm_is_user_mode,
6399 .get_guest_ip = kvm_get_guest_ip,
6400};
6401
6402void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6403{
086c9855 6404 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6405}
6406EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6407
6408void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6409{
086c9855 6410 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6411}
6412EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6413
ce88decf
XG		 6414static void kvm_set_mmio_spte_mask(void)
6415{
6416 u64 mask;
6417 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6418
6419 /*
6420 * Set the reserved bits and the present bit of an paging-structure
6421 * entry to generate page fault with PFER.RSV = 1.
6422 */
885032b9 6423 /* Mask the reserved physical address bits. */
d1431483 6424 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6425
885032b9 6426 /* Set the present bit. */
ce88decf
XG		 6427 mask |= 1ull;
6428
6429#ifdef CONFIG_X86_64
6430 /*
6431 * If reserved bit is not supported, clear the present bit to disable
6432 * mmio page fault.
6433 */
6434 if (maxphyaddr == 52)
6435 mask &= ~1ull;
6436#endif
6437
dcdca5fe 6438 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6439}
6440
16e8d74d
MT		 6441#ifdef CONFIG_X86_64
6442static void pvclock_gtod_update_fn(struct work_struct *work)
6443{
d828199e
MT		 6444 struct kvm *kvm;
6445
6446 struct kvm_vcpu *vcpu;
6447 int i;
6448
2f303b74 6449 spin_lock(&kvm_lock);
d828199e
MT		 6450 list_for_each_entry(kvm, &vm_list, vm_list)
6451 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6452 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6453 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6454 spin_unlock(&kvm_lock);
16e8d74d
MT		 6455}
6456
6457static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6458
6459/*
6460 * Notification about pvclock gtod data update.
6461 */
6462static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6463 void *priv)
6464{
6465 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6466 struct timekeeper *tk = priv;
6467
6468 update_pvclock_gtod(tk);
6469
6470 /* disable master clock if host does not trust, or does not
b0c39dc6 6471 * use, TSC based clocksource.
16e8d74d 6472 */
b0c39dc6 6473 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6474 atomic_read(&kvm_guest_has_master_clock) != 0)
6475 queue_work(system_long_wq, &pvclock_gtod_work);
6476
6477 return 0;
6478}
6479
6480static struct notifier_block pvclock_gtod_notifier = {
6481 .notifier_call = pvclock_gtod_notify,
6482};
6483#endif
6484
f8c16bba 6485int kvm_arch_init(void *opaque)
043405e1 6486{
b820cc0c 6487 int r;
6b61edf7 6488 struct kvm_x86_ops *ops = opaque;
f8c16bba 6489
f8c16bba
ZX		 6490 if (kvm_x86_ops) {
6491 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6492 r = -EEXIST;
6493 goto out;
f8c16bba
ZX		 6494 }
6495
6496 if (!ops->cpu_has_kvm_support()) {
6497 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6498 r = -EOPNOTSUPP;
6499 goto out;
f8c16bba
ZX		 6500 }
6501 if (ops->disabled_by_bios()) {
6502 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6503 r = -EOPNOTSUPP;
6504 goto out;
f8c16bba
ZX		 6505 }
6506
013f6a5d
MT		 6507 r = -ENOMEM;
6508 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6509 if (!shared_msrs) {
6510 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6511 goto out;
6512 }
6513
97db56ce
AK		 6514 r = kvm_mmu_module_init();
6515 if (r)
013f6a5d 6516 goto out_free_percpu;
97db56ce 6517
ce88decf 6518 kvm_set_mmio_spte_mask();
97db56ce 6519
f8c16bba 6520 kvm_x86_ops = ops;
920c8377 6521
7b52345e 6522 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6523 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6524 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6525 kvm_timer_init();
c8076604 6526
ff9d07a0
ZY		 6527 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6528
d366bf7e 6529 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6530 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6531
c5cc421b 6532 kvm_lapic_init();
16e8d74d
MT		 6533#ifdef CONFIG_X86_64
6534 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6535
5fa4ec9c 6536 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6537 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6538#endif
6539
f8c16bba 6540 return 0;
56c6d28a 6541
013f6a5d
MT		 6542out_free_percpu:
6543 free_percpu(shared_msrs);
56c6d28a 6544out:
56c6d28a 6545 return r;
043405e1 6546}
8776e519 6547
f8c16bba
ZX		 6548void kvm_arch_exit(void)
6549{
0092e434 6550#ifdef CONFIG_X86_64
5fa4ec9c 6551 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6552 clear_hv_tscchange_cb();
6553#endif
cef84c30 6554 kvm_lapic_exit();
ff9d07a0
ZY		 6555 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6556
888d256e
JK		 6557 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6558 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6559 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6560 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6561#ifdef CONFIG_X86_64
6562 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6563#endif
f8c16bba 6564 kvm_x86_ops = NULL;
56c6d28a 6565 kvm_mmu_module_exit();
013f6a5d 6566 free_percpu(shared_msrs);
56c6d28a 6567}
f8c16bba 6568
5cb56059 6569int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6570{
6571 ++vcpu->stat.halt_exits;
35754c98 6572 if (lapic_in_kernel(vcpu)) {
a4535290 6573 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6574 return 1;
6575 } else {
6576 vcpu->run->exit_reason = KVM_EXIT_HLT;
6577 return 0;
6578 }
6579}
5cb56059
JS		 6580EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6581
6582int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6583{
6affcbed
KH		 6584 int ret = kvm_skip_emulated_instruction(vcpu);
6585 /*
6586 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6587 * KVM_EXIT_DEBUG here.
6588 */
6589 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6590}
8776e519
HB		 6591EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6592
8ef81a9a 6593#ifdef CONFIG_X86_64
55dd00a7
MT		 6594static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6595 unsigned long clock_type)
6596{
6597 struct kvm_clock_pairing clock_pairing;
6598 struct timespec ts;
80fbd89c 6599 u64 cycle;
55dd00a7
MT		 6600 int ret;
6601
6602 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6603 return -KVM_EOPNOTSUPP;
6604
6605 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6606 return -KVM_EOPNOTSUPP;
6607
6608 clock_pairing.sec = ts.tv_sec;
6609 clock_pairing.nsec = ts.tv_nsec;
6610 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6611 clock_pairing.flags = 0;
6612
6613 ret = 0;
6614 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6615 sizeof(struct kvm_clock_pairing)))
6616 ret = -KVM_EFAULT;
6617
6618 return ret;
6619}
8ef81a9a 6620#endif
55dd00a7 6621
6aef266c
SV		 6622/*
6623 * kvm_pv_kick_cpu_op: Kick a vcpu.
6624 *
6625 * @apicid - apicid of vcpu to be kicked.
6626 */
6627static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6628{
24d2166b 6629 struct kvm_lapic_irq lapic_irq;
6aef266c 6630
24d2166b
R		 6631 lapic_irq.shorthand = 0;
6632 lapic_irq.dest_mode = 0;
ebd28fcb 6633 lapic_irq.level = 0;
24d2166b 6634 lapic_irq.dest_id = apicid;
93bbf0b8 6635 lapic_irq.msi_redir_hint = false;
6aef266c 6636
24d2166b 6637 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6638 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6639}
6640
d62caabb
AS		 6641void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6642{
6643 vcpu->arch.apicv_active = false;
6644 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6645}
6646
8776e519
HB		 6647int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6648{
6649 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6650 int op_64_bit, r;
8776e519 6651
6affcbed 6652 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6653
55cd8e5a
GN		 6654 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6655 return kvm_hv_hypercall(vcpu);
6656
5fdbf976
MT		 6657 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6658 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6659 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6660 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6661 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6662
229456fc 6663 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6664
a449c7aa
NA		 6665 op_64_bit = is_64_bit_mode(vcpu);
6666 if (!op_64_bit) {
8776e519
HB		 6667 nr &= 0xFFFFFFFF;
6668 a0 &= 0xFFFFFFFF;
6669 a1 &= 0xFFFFFFFF;
6670 a2 &= 0xFFFFFFFF;
6671 a3 &= 0xFFFFFFFF;
6672 }
6673
07708c4a
JK		 6674 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6675 ret = -KVM_EPERM;
6676 goto out;
6677 }
6678
8776e519 6679 switch (nr) {
b93463aa
AK		 6680 case KVM_HC_VAPIC_POLL_IRQ:
6681 ret = 0;
6682 break;
6aef266c
SV		 6683 case KVM_HC_KICK_CPU:
6684 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6685 ret = 0;
6686 break;
8ef81a9a 6687#ifdef CONFIG_X86_64
55dd00a7
MT		 6688 case KVM_HC_CLOCK_PAIRING:
6689 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6690 break;
8ef81a9a 6691#endif
8776e519
HB		 6692 default:
6693 ret = -KVM_ENOSYS;
6694 break;
6695 }
07708c4a 6696out:
a449c7aa
NA		 6697 if (!op_64_bit)
6698 ret = (u32)ret;
5fdbf976 6699 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6700 ++vcpu->stat.hypercalls;
2f333bcb 6701 return r;
8776e519
HB		 6702}
6703EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6704
b6785def 6705static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6706{
d6aa1000 6707 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6708 char instruction[3];
5fdbf976 6709 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6710
8776e519 6711 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6712
ce2e852e
DV		 6713 return emulator_write_emulated(ctxt, rip, instruction, 3,
6714 &ctxt->exception);
8776e519
HB		 6715}
6716
851ba692 6717static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6718{
782d422b
MG		 6719 return vcpu->run->request_interrupt_window &&
6720 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6721}
6722
851ba692 6723static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6724{
851ba692
AK		 6725 struct kvm_run *kvm_run = vcpu->run;
6726
91586a3b 6727 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6728 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6729 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6730 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6731 kvm_run->ready_for_interrupt_injection =
6732 pic_in_kernel(vcpu->kvm) ||
782d422b 6733 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6734}
6735
95ba8273
GN		 6736static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6737{
6738 int max_irr, tpr;
6739
6740 if (!kvm_x86_ops->update_cr8_intercept)
6741 return;
6742
bce87cce 6743 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6744 return;
6745
d62caabb
AS		 6746 if (vcpu->arch.apicv_active)
6747 return;
6748
8db3baa2
GN		 6749 if (!vcpu->arch.apic->vapic_addr)
6750 max_irr = kvm_lapic_find_highest_irr(vcpu);
6751 else
6752 max_irr = -1;
95ba8273
GN		 6753
6754 if (max_irr != -1)
6755 max_irr >>= 4;
6756
6757 tpr = kvm_lapic_get_cr8(vcpu);
6758
6759 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6760}
6761
b6b8a145 6762static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6763{
b6b8a145
JK		 6764 int r;
6765
95ba8273 6766 /* try to reinject previous events if any */
664f8e26
WL		 6767 if (vcpu->arch.exception.injected) {
6768 kvm_x86_ops->queue_exception(vcpu);
6769 return 0;
6770 }
6771
6772 /*
6773 * Exceptions must be injected immediately, or the exception
6774 * frame will have the address of the NMI or interrupt handler.
6775 */
6776 if (!vcpu->arch.exception.pending) {
6777 if (vcpu->arch.nmi_injected) {
6778 kvm_x86_ops->set_nmi(vcpu);
6779 return 0;
6780 }
6781
6782 if (vcpu->arch.interrupt.pending) {
6783 kvm_x86_ops->set_irq(vcpu);
6784 return 0;
6785 }
6786 }
6787
6788 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6789 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6790 if (r != 0)
6791 return r;
6792 }
6793
6794 /* try to inject new event if pending */
b59bb7bd 6795 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6796 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6797 vcpu->arch.exception.has_error_code,
6798 vcpu->arch.exception.error_code);
d6e8c854 6799
664f8e26
WL		 6800 vcpu->arch.exception.pending = false;
6801 vcpu->arch.exception.injected = true;
6802
d6e8c854
NA		 6803 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6804 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6805 X86_EFLAGS_RF);
6806
6bdf0662
NA		 6807 if (vcpu->arch.exception.nr == DB_VECTOR &&
6808 (vcpu->arch.dr7 & DR7_GD)) {
6809 vcpu->arch.dr7 &= ~DR7_GD;
6810 kvm_update_dr7(vcpu);
6811 }
6812
cfcd20e5 6813 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6814 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6815 vcpu->arch.smi_pending = false;
52797bf9 6816 ++vcpu->arch.smi_count;
ee2cd4b7 6817 enter_smm(vcpu);
c43203ca 6818 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6819 --vcpu->arch.nmi_pending;
6820 vcpu->arch.nmi_injected = true;
6821 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6822 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6823 /*
6824 * Because interrupts can be injected asynchronously, we are
6825 * calling check_nested_events again here to avoid a race condition.
6826 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6827 * proposal and current concerns. Perhaps we should be setting
6828 * KVM_REQ_EVENT only on certain events and not unconditionally?
6829 */
6830 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6831 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6832 if (r != 0)
6833 return r;
6834 }
95ba8273 6835 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6836 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6837 false);
6838 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6839 }
6840 }
ee2cd4b7 6841
b6b8a145 6842 return 0;
95ba8273
GN		 6843}
6844
7460fb4a
AK		 6845static void process_nmi(struct kvm_vcpu *vcpu)
6846{
6847 unsigned limit = 2;
6848
6849 /*
6850 * x86 is limited to one NMI running, and one NMI pending after it.
6851 * If an NMI is already in progress, limit further NMIs to just one.
6852 * Otherwise, allow two (and we'll inject the first one immediately).
6853 */
6854 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6855 limit = 1;
6856
6857 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6858 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6859 kvm_make_request(KVM_REQ_EVENT, vcpu);
6860}
6861
ee2cd4b7 6862static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6863{
6864 u32 flags = 0;
6865 flags |= seg->g << 23;
6866 flags |= seg->db << 22;
6867 flags |= seg->l << 21;
6868 flags |= seg->avl << 20;
6869 flags |= seg->present << 15;
6870 flags |= seg->dpl << 13;
6871 flags |= seg->s << 12;
6872 flags |= seg->type << 8;
6873 return flags;
6874}
6875
ee2cd4b7 6876static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6877{
6878 struct kvm_segment seg;
6879 int offset;
6880
6881 kvm_get_segment(vcpu, &seg, n);
6882 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6883
6884 if (n < 3)
6885 offset = 0x7f84 + n * 12;
6886 else
6887 offset = 0x7f2c + (n - 3) * 12;
6888
6889 put_smstate(u32, buf, offset + 8, seg.base);
6890 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6891 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6892}
6893
efbb288a 6894#ifdef CONFIG_X86_64
ee2cd4b7 6895static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6896{
6897 struct kvm_segment seg;
6898 int offset;
6899 u16 flags;
6900
6901 kvm_get_segment(vcpu, &seg, n);
6902 offset = 0x7e00 + n * 16;
6903
ee2cd4b7 6904 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6905 put_smstate(u16, buf, offset, seg.selector);
6906 put_smstate(u16, buf, offset + 2, flags);
6907 put_smstate(u32, buf, offset + 4, seg.limit);
6908 put_smstate(u64, buf, offset + 8, seg.base);
6909}
efbb288a 6910#endif
660a5d51 6911
ee2cd4b7 6912static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6913{
6914 struct desc_ptr dt;
6915 struct kvm_segment seg;
6916 unsigned long val;
6917 int i;
6918
6919 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6920 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6921 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6922 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6923
6924 for (i = 0; i < 8; i++)
6925 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6926
6927 kvm_get_dr(vcpu, 6, &val);
6928 put_smstate(u32, buf, 0x7fcc, (u32)val);
6929 kvm_get_dr(vcpu, 7, &val);
6930 put_smstate(u32, buf, 0x7fc8, (u32)val);
6931
6932 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6933 put_smstate(u32, buf, 0x7fc4, seg.selector);
6934 put_smstate(u32, buf, 0x7f64, seg.base);
6935 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6936 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6937
6938 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6939 put_smstate(u32, buf, 0x7fc0, seg.selector);
6940 put_smstate(u32, buf, 0x7f80, seg.base);
6941 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6942 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6943
6944 kvm_x86_ops->get_gdt(vcpu, &dt);
6945 put_smstate(u32, buf, 0x7f74, dt.address);
6946 put_smstate(u32, buf, 0x7f70, dt.size);
6947
6948 kvm_x86_ops->get_idt(vcpu, &dt);
6949 put_smstate(u32, buf, 0x7f58, dt.address);
6950 put_smstate(u32, buf, 0x7f54, dt.size);
6951
6952 for (i = 0; i < 6; i++)
ee2cd4b7 6953 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6954
6955 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6956
6957 /* revision id */
6958 put_smstate(u32, buf, 0x7efc, 0x00020000);
6959 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6960}
6961
ee2cd4b7 6962static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6963{
6964#ifdef CONFIG_X86_64
6965 struct desc_ptr dt;
6966 struct kvm_segment seg;
6967 unsigned long val;
6968 int i;
6969
6970 for (i = 0; i < 16; i++)
6971 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6972
6973 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6974 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6975
6976 kvm_get_dr(vcpu, 6, &val);
6977 put_smstate(u64, buf, 0x7f68, val);
6978 kvm_get_dr(vcpu, 7, &val);
6979 put_smstate(u64, buf, 0x7f60, val);
6980
6981 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6982 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6983 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6984
6985 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6986
6987 /* revision id */
6988 put_smstate(u32, buf, 0x7efc, 0x00020064);
6989
6990 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6991
6992 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6993 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6994 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6995 put_smstate(u32, buf, 0x7e94, seg.limit);
6996 put_smstate(u64, buf, 0x7e98, seg.base);
6997
6998 kvm_x86_ops->get_idt(vcpu, &dt);
6999 put_smstate(u32, buf, 0x7e84, dt.size);
7000 put_smstate(u64, buf, 0x7e88, dt.address);
7001
7002 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7003 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7004 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7005 put_smstate(u32, buf, 0x7e74, seg.limit);
7006 put_smstate(u64, buf, 0x7e78, seg.base);
7007
7008 kvm_x86_ops->get_gdt(vcpu, &dt);
7009 put_smstate(u32, buf, 0x7e64, dt.size);
7010 put_smstate(u64, buf, 0x7e68, dt.address);
7011
7012 for (i = 0; i < 6; i++)
ee2cd4b7 7013 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7014#else
7015 WARN_ON_ONCE(1);
7016#endif
7017}
7018
ee2cd4b7 7019static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7020{
660a5d51 7021 struct kvm_segment cs, ds;
18c3626e 7022 struct desc_ptr dt;
660a5d51
PB		 7023 char buf[512];
7024 u32 cr0;
7025
660a5d51 7026 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7027 memset(buf, 0, 512);
d6321d49 7028 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7029 enter_smm_save_state_64(vcpu, buf);
660a5d51 7030 else
ee2cd4b7 7031 enter_smm_save_state_32(vcpu, buf);
660a5d51 7032
0234bf88
LP		 7033 /*
7034 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7035 * vCPU state (e.g. leave guest mode) after we've saved the state into
7036 * the SMM state-save area.
7037 */
7038 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7039
7040 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7041 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7042
7043 if (kvm_x86_ops->get_nmi_mask(vcpu))
7044 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7045 else
7046 kvm_x86_ops->set_nmi_mask(vcpu, true);
7047
7048 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7049 kvm_rip_write(vcpu, 0x8000);
7050
7051 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7052 kvm_x86_ops->set_cr0(vcpu, cr0);
7053 vcpu->arch.cr0 = cr0;
7054
7055 kvm_x86_ops->set_cr4(vcpu, 0);
7056
18c3626e
PB		 7057 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7058 dt.address = dt.size = 0;
7059 kvm_x86_ops->set_idt(vcpu, &dt);
7060
660a5d51
PB		 7061 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7062
7063 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7064 cs.base = vcpu->arch.smbase;
7065
7066 ds.selector = 0;
7067 ds.base = 0;
7068
7069 cs.limit = ds.limit = 0xffffffff;
7070 cs.type = ds.type = 0x3;
7071 cs.dpl = ds.dpl = 0;
7072 cs.db = ds.db = 0;
7073 cs.s = ds.s = 1;
7074 cs.l = ds.l = 0;
7075 cs.g = ds.g = 1;
7076 cs.avl = ds.avl = 0;
7077 cs.present = ds.present = 1;
7078 cs.unusable = ds.unusable = 0;
7079 cs.padding = ds.padding = 0;
7080
7081 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7082 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7083 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7084 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7085 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7086 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7087
d6321d49 7088 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7089 kvm_x86_ops->set_efer(vcpu, 0);
7090
7091 kvm_update_cpuid(vcpu);
7092 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7093}
7094
ee2cd4b7 7095static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7096{
7097 vcpu->arch.smi_pending = true;
7098 kvm_make_request(KVM_REQ_EVENT, vcpu);
7099}
7100
2860c4b1
PB		 7101void kvm_make_scan_ioapic_request(struct kvm *kvm)
7102{
7103 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7104}
7105
3d81bc7e 7106static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7107{
5c919412
AS		 7108 u64 eoi_exit_bitmap[4];
7109
3d81bc7e
YZ		 7110 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7111 return;
c7c9c56c 7112
6308630b 7113 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7114
b053b2ae 7115 if (irqchip_split(vcpu->kvm))
6308630b 7116 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7117 else {
fa59cc00 7118 if (vcpu->arch.apicv_active)
d62caabb 7119 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7120 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7121 }
5c919412
AS		 7122 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7123 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7124 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7125}
7126
b1394e74
RK		 7127void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7128 unsigned long start, unsigned long end)
7129{
7130 unsigned long apic_address;
7131
7132 /*
7133 * The physical address of apic access page is stored in the VMCS.
7134 * Update it when it becomes invalid.
7135 */
7136 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7137 if (start <= apic_address && apic_address < end)
7138 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7139}
7140
4256f43f
TC		 7141void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7142{
c24ae0dc
TC		 7143 struct page *page = NULL;
7144
35754c98 7145 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7146 return;
7147
4256f43f
TC		 7148 if (!kvm_x86_ops->set_apic_access_page_addr)
7149 return;
7150
c24ae0dc 7151 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7152 if (is_error_page(page))
7153 return;
c24ae0dc
TC		 7154 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7155
7156 /*
7157 * Do not pin apic access page in memory, the MMU notifier
7158 * will call us again if it is migrated or swapped out.
7159 */
7160 put_page(page);
4256f43f
TC		 7161}
7162EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7163
9357d939 7164/*
362c698f 7165 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7166 * exiting to the userspace. Otherwise, the value will be returned to the
7167 * userspace.
7168 */
851ba692 7169static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7170{
7171 int r;
62a193ed
MG		 7172 bool req_int_win =
7173 dm_request_for_irq_injection(vcpu) &&
7174 kvm_cpu_accept_dm_intr(vcpu);
7175
730dca42 7176 bool req_immediate_exit = false;
b6c7a5dc 7177
2fa6e1e1 7178 if (kvm_request_pending(vcpu)) {
a8eeb04a 7179 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7180 kvm_mmu_unload(vcpu);
a8eeb04a 7181 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7182 __kvm_migrate_timers(vcpu);
d828199e
MT		 7183 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7184 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7185 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7186 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7187 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7188 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7189 if (unlikely(r))
7190 goto out;
7191 }
a8eeb04a 7192 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7193 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7194 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7195 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7196 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7197 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7198 r = 0;
7199 goto out;
7200 }
a8eeb04a 7201 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7202 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7203 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7204 r = 0;
7205 goto out;
7206 }
af585b92
GN		 7207 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7208 /* Page is swapped out. Do synthetic halt */
7209 vcpu->arch.apf.halted = true;
7210 r = 1;
7211 goto out;
7212 }
c9aaa895
GC		 7213 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7214 record_steal_time(vcpu);
64d60670
PB		 7215 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7216 process_smi(vcpu);
7460fb4a
AK		 7217 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7218 process_nmi(vcpu);
f5132b01 7219 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7220 kvm_pmu_handle_event(vcpu);
f5132b01 7221 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7222 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7223 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7224 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7225 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7226 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7227 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7228 vcpu->run->eoi.vector =
7229 vcpu->arch.pending_ioapic_eoi;
7230 r = 0;
7231 goto out;
7232 }
7233 }
3d81bc7e
YZ		 7234 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7235 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 7236 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7237 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7238 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7239 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7240 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7241 r = 0;
7242 goto out;
7243 }
e516cebb
AS		 7244 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7245 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7246 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7247 r = 0;
7248 goto out;
7249 }
db397571
AS		 7250 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7251 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7252 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7253 r = 0;
7254 goto out;
7255 }
f3b138c5
AS		 7256
7257 /*
7258 * KVM_REQ_HV_STIMER has to be processed after
7259 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7260 * depend on the guest clock being up-to-date
7261 */
1f4b34f8
AS		 7262 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7263 kvm_hv_process_stimers(vcpu);
2f52d58c 7264 }
b93463aa 7265
b463a6f7 7266 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7267 ++vcpu->stat.req_event;
66450a21
JK		 7268 kvm_apic_accept_events(vcpu);
7269 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7270 r = 1;
7271 goto out;
7272 }
7273
b6b8a145
JK		 7274 if (inject_pending_event(vcpu, req_int_win) != 0)
7275 req_immediate_exit = true;
321c5658 7276 else {
cc3d967f 7277 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7278 *
cc3d967f
LP		 7279 * SMIs have three cases:
7280 * 1) They can be nested, and then there is nothing to
7281 * do here because RSM will cause a vmexit anyway.
7282 * 2) There is an ISA-specific reason why SMI cannot be
7283 * injected, and the moment when this changes can be
7284 * intercepted.
7285 * 3) Or the SMI can be pending because
7286 * inject_pending_event has completed the injection
7287 * of an IRQ or NMI from the previous vmexit, and
7288 * then we request an immediate exit to inject the
7289 * SMI.
c43203ca
PB		 7290 */
7291 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7292 if (!kvm_x86_ops->enable_smi_window(vcpu))
7293 req_immediate_exit = true;
321c5658
YS		 7294 if (vcpu->arch.nmi_pending)
7295 kvm_x86_ops->enable_nmi_window(vcpu);
7296 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7297 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7298 WARN_ON(vcpu->arch.exception.pending);
321c5658 7299 }
b463a6f7
AK		 7300
7301 if (kvm_lapic_enabled(vcpu)) {
7302 update_cr8_intercept(vcpu);
7303 kvm_lapic_sync_to_vapic(vcpu);
7304 }
7305 }
7306
d8368af8
AK		 7307 r = kvm_mmu_reload(vcpu);
7308 if (unlikely(r)) {
d905c069 7309 goto cancel_injection;
d8368af8
AK		 7310 }
7311
b6c7a5dc
HB		 7312 preempt_disable();
7313
7314 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7315
7316 /*
7317 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7318 * IPI are then delayed after guest entry, which ensures that they
7319 * result in virtual interrupt delivery.
7320 */
7321 local_irq_disable();
6b7e2d09
XG		 7322 vcpu->mode = IN_GUEST_MODE;
7323
01b71917
MT		 7324 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7325
0f127d12 7326 /*
b95234c8 7327 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7328 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7329 *
7330 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7331 * pairs with the memory barrier implicit in pi_test_and_set_on
7332 * (see vmx_deliver_posted_interrupt).
7333 *
7334 * 3) This also orders the write to mode from any reads to the page
7335 * tables done while the VCPU is running. Please see the comment
7336 * in kvm_flush_remote_tlbs.
6b7e2d09 7337 */
01b71917 7338 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7339
b95234c8
PB		 7340 /*
7341 * This handles the case where a posted interrupt was
7342 * notified with kvm_vcpu_kick.
7343 */
fa59cc00
LA		 7344 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7345 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7346
2fa6e1e1 7347 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7348 || need_resched() || signal_pending(current)) {
6b7e2d09 7349 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7350 smp_wmb();
6c142801
AK		 7351 local_irq_enable();
7352 preempt_enable();
01b71917 7353 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7354 r = 1;
d905c069 7355 goto cancel_injection;
6c142801
AK		 7356 }
7357
fc5b7f3b
DM		 7358 kvm_load_guest_xcr0(vcpu);
7359
c43203ca
PB		 7360 if (req_immediate_exit) {
7361 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7362 smp_send_reschedule(vcpu->cpu);
c43203ca 7363 }
d6185f20 7364
8b89fe1f 7365 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7366 if (lapic_timer_advance_ns)
7367 wait_lapic_expire(vcpu);
6edaa530 7368 guest_enter_irqoff();
b6c7a5dc 7369
42dbaa5a 7370 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7371 set_debugreg(0, 7);
7372 set_debugreg(vcpu->arch.eff_db[0], 0);
7373 set_debugreg(vcpu->arch.eff_db[1], 1);
7374 set_debugreg(vcpu->arch.eff_db[2], 2);
7375 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7376 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7377 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7378 }
b6c7a5dc 7379
851ba692 7380 kvm_x86_ops->run(vcpu);
b6c7a5dc 7381
c77fb5fe
PB		 7382 /*
7383 * Do this here before restoring debug registers on the host. And
7384 * since we do this before handling the vmexit, a DR access vmexit
7385 * can (a) read the correct value of the debug registers, (b) set
7386 * KVM_DEBUGREG_WONT_EXIT again.
7387 */
7388 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7389 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7390 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7391 kvm_update_dr0123(vcpu);
7392 kvm_update_dr6(vcpu);
7393 kvm_update_dr7(vcpu);
7394 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7395 }
7396
24f1e32c
FW		 7397 /*
7398 * If the guest has used debug registers, at least dr7
7399 * will be disabled while returning to the host.
7400 * If we don't have active breakpoints in the host, we don't
7401 * care about the messed up debug address registers. But if
7402 * we have some of them active, restore the old state.
7403 */
59d8eb53 7404 if (hw_breakpoint_active())
24f1e32c 7405 hw_breakpoint_restore();
42dbaa5a 7406
4ba76538 7407 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7408
6b7e2d09 7409 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7410 smp_wmb();
a547c6db 7411
fc5b7f3b
DM		 7412 kvm_put_guest_xcr0(vcpu);
7413
a547c6db 7414 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7415
7416 ++vcpu->stat.exits;
7417
f2485b3e 7418 guest_exit_irqoff();
b6c7a5dc 7419
f2485b3e 7420 local_irq_enable();
b6c7a5dc
HB		 7421 preempt_enable();
7422
f656ce01 7423 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7424
b6c7a5dc
HB		 7425 /*
7426 * Profile KVM exit RIPs:
7427 */
7428 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7429 unsigned long rip = kvm_rip_read(vcpu);
7430 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7431 }
7432
cc578287
ZA		 7433 if (unlikely(vcpu->arch.tsc_always_catchup))
7434 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7435
5cfb1d5a
MT		 7436 if (vcpu->arch.apic_attention)
7437 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7438
618232e2 7439 vcpu->arch.gpa_available = false;
851ba692 7440 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7441 return r;
7442
7443cancel_injection:
7444 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7445 if (unlikely(vcpu->arch.apic_attention))
7446 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7447out:
7448 return r;
7449}
b6c7a5dc 7450
362c698f
PB		 7451static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7452{
bf9f6ac8
FW		 7453 if (!kvm_arch_vcpu_runnable(vcpu) &&
7454 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7455 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7456 kvm_vcpu_block(vcpu);
7457 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7458
7459 if (kvm_x86_ops->post_block)
7460 kvm_x86_ops->post_block(vcpu);
7461
9c8fd1ba
PB		 7462 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7463 return 1;
7464 }
362c698f
PB		 7465
7466 kvm_apic_accept_events(vcpu);
7467 switch(vcpu->arch.mp_state) {
7468 case KVM_MP_STATE_HALTED:
7469 vcpu->arch.pv.pv_unhalted = false;
7470 vcpu->arch.mp_state =
7471 KVM_MP_STATE_RUNNABLE;
7472 case KVM_MP_STATE_RUNNABLE:
7473 vcpu->arch.apf.halted = false;
7474 break;
7475 case KVM_MP_STATE_INIT_RECEIVED:
7476 break;
7477 default:
7478 return -EINTR;
7479 break;
7480 }
7481 return 1;
7482}
09cec754 7483
5d9bc648
PB		 7484static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7485{
0ad3bed6
PB		 7486 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7487 kvm_x86_ops->check_nested_events(vcpu, false);
7488
5d9bc648
PB		 7489 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7490 !vcpu->arch.apf.halted);
7491}
7492
362c698f 7493static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7494{
7495 int r;
f656ce01 7496 struct kvm *kvm = vcpu->kvm;
d7690175 7497
f656ce01 7498 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7499
362c698f 7500 for (;;) {
58f800d5 7501 if (kvm_vcpu_running(vcpu)) {
851ba692 7502 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7503 } else {
362c698f 7504 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7505 }
7506
09cec754
GN		 7507 if (r <= 0)
7508 break;
7509
72875d8a 7510 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7511 if (kvm_cpu_has_pending_timer(vcpu))
7512 kvm_inject_pending_timer_irqs(vcpu);
7513
782d422b
MG		 7514 if (dm_request_for_irq_injection(vcpu) &&
7515 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7516 r = 0;
7517 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7518 ++vcpu->stat.request_irq_exits;
362c698f 7519 break;
09cec754 7520 }
af585b92
GN		 7521
7522 kvm_check_async_pf_completion(vcpu);
7523
09cec754
GN		 7524 if (signal_pending(current)) {
7525 r = -EINTR;
851ba692 7526 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7527 ++vcpu->stat.signal_exits;
362c698f 7528 break;
09cec754
GN		 7529 }
7530 if (need_resched()) {
f656ce01 7531 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7532 cond_resched();
f656ce01 7533 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7534 }
b6c7a5dc
HB		 7535 }
7536
f656ce01 7537 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7538
7539 return r;
7540}
7541
716d51ab
GN		 7542static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7543{
7544 int r;
7545 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7546 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7547 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7548 if (r != EMULATE_DONE)
7549 return 0;
7550 return 1;
7551}
7552
7553static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7554{
7555 BUG_ON(!vcpu->arch.pio.count);
7556
7557 return complete_emulated_io(vcpu);
7558}
7559
f78146b0
AK		 7560/*
7561 * Implements the following, as a state machine:
7562 *
7563 * read:
7564 * for each fragment
87da7e66
XG		 7565 * for each mmio piece in the fragment
7566 * write gpa, len
7567 * exit
7568 * copy data
f78146b0
AK		 7569 * execute insn
7570 *
7571 * write:
7572 * for each fragment
87da7e66
XG		 7573 * for each mmio piece in the fragment
7574 * write gpa, len
7575 * copy data
7576 * exit
f78146b0 7577 */
716d51ab 7578static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7579{
7580 struct kvm_run *run = vcpu->run;
f78146b0 7581 struct kvm_mmio_fragment *frag;
87da7e66 7582 unsigned len;
5287f194 7583
716d51ab 7584 BUG_ON(!vcpu->mmio_needed);
5287f194 7585
716d51ab 7586 /* Complete previous fragment */
87da7e66
XG		 7587 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7588 len = min(8u, frag->len);
716d51ab 7589 if (!vcpu->mmio_is_write)
87da7e66
XG		 7590 memcpy(frag->data, run->mmio.data, len);
7591
7592 if (frag->len <= 8) {
7593 /* Switch to the next fragment. */
7594 frag++;
7595 vcpu->mmio_cur_fragment++;
7596 } else {
7597 /* Go forward to the next mmio piece. */
7598 frag->data += len;
7599 frag->gpa += len;
7600 frag->len -= len;
7601 }
7602
a08d3b3b 7603 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7604 vcpu->mmio_needed = 0;
0912c977
PB		 7605
7606 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7607 if (vcpu->mmio_is_write)
716d51ab
GN		 7608 return 1;
7609 vcpu->mmio_read_completed = 1;
7610 return complete_emulated_io(vcpu);
7611 }
87da7e66 7612
716d51ab
GN		 7613 run->exit_reason = KVM_EXIT_MMIO;
7614 run->mmio.phys_addr = frag->gpa;
7615 if (vcpu->mmio_is_write)
87da7e66
XG		 7616 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7617 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7618 run->mmio.is_write = vcpu->mmio_is_write;
7619 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7620 return 0;
5287f194
AK		 7621}
7622
b6c7a5dc
HB		 7623int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7624{
7625 int r;
b6c7a5dc 7626
accb757d 7627 vcpu_load(vcpu);
20b7035c 7628 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7629 kvm_load_guest_fpu(vcpu);
7630
a4535290 7631 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7632 if (kvm_run->immediate_exit) {
7633 r = -EINTR;
7634 goto out;
7635 }
b6c7a5dc 7636 kvm_vcpu_block(vcpu);
66450a21 7637 kvm_apic_accept_events(vcpu);
72875d8a 7638 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7639 r = -EAGAIN;
a0595000
JS		 7640 if (signal_pending(current)) {
7641 r = -EINTR;
7642 vcpu->run->exit_reason = KVM_EXIT_INTR;
7643 ++vcpu->stat.signal_exits;
7644 }
ac9f6dc0 7645 goto out;
b6c7a5dc
HB		 7646 }
7647
01643c51
KH		 7648 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7649 r = -EINVAL;
7650 goto out;
7651 }
7652
7653 if (vcpu->run->kvm_dirty_regs) {
7654 r = sync_regs(vcpu);
7655 if (r != 0)
7656 goto out;
7657 }
7658
b6c7a5dc 7659 /* re-sync apic's tpr */
35754c98 7660 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7661 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7662 r = -EINVAL;
7663 goto out;
7664 }
7665 }
b6c7a5dc 7666
716d51ab
GN		 7667 if (unlikely(vcpu->arch.complete_userspace_io)) {
7668 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7669 vcpu->arch.complete_userspace_io = NULL;
7670 r = cui(vcpu);
7671 if (r <= 0)
5663d8f9 7672 goto out;
716d51ab
GN		 7673 } else
7674 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7675
460df4c1
PB		 7676 if (kvm_run->immediate_exit)
7677 r = -EINTR;
7678 else
7679 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7680
7681out:
5663d8f9 7682 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7683 if (vcpu->run->kvm_valid_regs)
7684 store_regs(vcpu);
f1d86e46 7685 post_kvm_run_save(vcpu);
20b7035c 7686 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7687
accb757d 7688 vcpu_put(vcpu);
b6c7a5dc
HB		 7689 return r;
7690}
7691
01643c51 7692static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7693{
7ae441ea
GN		 7694 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7695 /*
7696 * We are here if userspace calls get_regs() in the middle of
7697 * instruction emulation. Registers state needs to be copied
4a969980 7698 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7699 * that usually, but some bad designed PV devices (vmware
7700 * backdoor interface) need this to work
7701 */
dd856efa 7702 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7703 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7704 }
5fdbf976
MT		 7705 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7706 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7707 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7708 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7709 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7710 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7711 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7712 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7713#ifdef CONFIG_X86_64
5fdbf976
MT		 7714 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7715 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7716 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7717 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7718 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7719 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7720 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7721 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7722#endif
7723
5fdbf976 7724 regs->rip = kvm_rip_read(vcpu);
91586a3b 7725 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7726}
b6c7a5dc 7727
01643c51
KH		 7728int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7729{
7730 vcpu_load(vcpu);
7731 __get_regs(vcpu, regs);
1fc9b76b 7732 vcpu_put(vcpu);
b6c7a5dc
HB		 7733 return 0;
7734}
7735
01643c51 7736static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7737{
7ae441ea
GN		 7738 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7739 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7740
5fdbf976
MT		 7741 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7742 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7743 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7744 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7745 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7746 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7747 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7748 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7749#ifdef CONFIG_X86_64
5fdbf976
MT		 7750 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7751 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7752 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7753 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7754 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7755 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7756 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7757 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7758#endif
7759
5fdbf976 7760 kvm_rip_write(vcpu, regs->rip);
d73235d1 7761 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7762
b4f14abd
JK		 7763 vcpu->arch.exception.pending = false;
7764
3842d135 7765 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7766}
3842d135 7767
01643c51
KH		 7768int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7769{
7770 vcpu_load(vcpu);
7771 __set_regs(vcpu, regs);
875656fe 7772 vcpu_put(vcpu);
b6c7a5dc
HB		 7773 return 0;
7774}
7775
b6c7a5dc
HB		 7776void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7777{
7778 struct kvm_segment cs;
7779
3e6e0aab 7780 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7781 *db = cs.db;
7782 *l = cs.l;
7783}
7784EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7785
01643c51 7786static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7787{
89a27f4d 7788 struct desc_ptr dt;
b6c7a5dc 7789
3e6e0aab
GT		 7790 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7791 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7792 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7793 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7794 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7795 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7796
3e6e0aab
GT		 7797 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7798 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7799
7800 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7801 sregs->idt.limit = dt.size;
7802 sregs->idt.base = dt.address;
b6c7a5dc 7803 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7804 sregs->gdt.limit = dt.size;
7805 sregs->gdt.base = dt.address;
b6c7a5dc 7806
4d4ec087 7807 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7808 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7809 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7810 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7811 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7812 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7813 sregs->apic_base = kvm_get_apic_base(vcpu);
7814
923c61bb 7815 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7816
36752c9b 7817 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7818 set_bit(vcpu->arch.interrupt.nr,
7819 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7820}
16d7a191 7821
01643c51
KH		 7822int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7823 struct kvm_sregs *sregs)
7824{
7825 vcpu_load(vcpu);
7826 __get_sregs(vcpu, sregs);
bcdec41c 7827 vcpu_put(vcpu);
b6c7a5dc
HB		 7828 return 0;
7829}
7830
62d9f0db
MT		 7831int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7832 struct kvm_mp_state *mp_state)
7833{
fd232561
CD		 7834 vcpu_load(vcpu);
7835
66450a21 7836 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7837 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7838 vcpu->arch.pv.pv_unhalted)
7839 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7840 else
7841 mp_state->mp_state = vcpu->arch.mp_state;
7842
fd232561 7843 vcpu_put(vcpu);
62d9f0db
MT		 7844 return 0;
7845}
7846
7847int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7848 struct kvm_mp_state *mp_state)
7849{
e83dff5e
CD		 7850 int ret = -EINVAL;
7851
7852 vcpu_load(vcpu);
7853
bce87cce 7854 if (!lapic_in_kernel(vcpu) &&
66450a21 7855 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7856 goto out;
66450a21 7857
28bf2888
DH		 7858 /* INITs are latched while in SMM */
7859 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7860 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7861 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7862 goto out;
28bf2888 7863
66450a21
JK		 7864 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7865 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7866 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7867 } else
7868 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7869 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7870
7871 ret = 0;
7872out:
7873 vcpu_put(vcpu);
7874 return ret;
62d9f0db
MT		 7875}
7876
7f3d35fd
KW		 7877int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7878 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7879{
9d74191a 7880 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7881 int ret;
e01c2426 7882
8ec4722d 7883 init_emulate_ctxt(vcpu);
c697518a 7884
7f3d35fd 7885 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7886 has_error_code, error_code);
c697518a 7887
c697518a 7888 if (ret)
19d04437 7889 return EMULATE_FAIL;
37817f29 7890
9d74191a
TY		 7891 kvm_rip_write(vcpu, ctxt->eip);
7892 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7893 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7894 return EMULATE_DONE;
37817f29
IE		 7895}
7896EXPORT_SYMBOL_GPL(kvm_task_switch);
7897
f2981033
LT		 7898int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7899{
37b95951 7900 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7901 /*
7902 * When EFER.LME and CR0.PG are set, the processor is in
7903 * 64-bit mode (though maybe in a 32-bit code segment).
7904 * CR4.PAE and EFER.LMA must be set.
7905 */
37b95951 7906 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7907 || !(sregs->efer & EFER_LMA))
7908 return -EINVAL;
7909 } else {
7910 /*
7911 * Not in 64-bit mode: EFER.LMA is clear and the code
7912 * segment cannot be 64-bit.
7913 */
7914 if (sregs->efer & EFER_LMA || sregs->cs.l)
7915 return -EINVAL;
7916 }
7917
7918 return 0;
7919}
7920
01643c51 7921static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7922{
58cb628d 7923 struct msr_data apic_base_msr;
b6c7a5dc 7924 int mmu_reset_needed = 0;
63f42e02 7925 int pending_vec, max_bits, idx;
89a27f4d 7926 struct desc_ptr dt;
b4ef9d4e
CD		 7927 int ret = -EINVAL;
7928
d6321d49
RK		 7929 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7930 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7931 goto out;
6d1068b3 7932
f2981033 7933 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 7934 goto out;
f2981033 7935
d3802286
JM		 7936 apic_base_msr.data = sregs->apic_base;
7937 apic_base_msr.host_initiated = true;
7938 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7939 goto out;
6d1068b3 7940
89a27f4d
GN		 7941 dt.size = sregs->idt.limit;
7942 dt.address = sregs->idt.base;
b6c7a5dc 7943 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7944 dt.size = sregs->gdt.limit;
7945 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7946 kvm_x86_ops->set_gdt(vcpu, &dt);
7947
ad312c7c 7948 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7949 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7950 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7951 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7952
2d3ad1f4 7953 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7954
f6801dff 7955 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7956 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7957
4d4ec087 7958 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7959 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7960 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7961
fc78f519 7962 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7963 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7964 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7965 kvm_update_cpuid(vcpu);
63f42e02
XG		 7966
7967 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7968 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7969 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7970 mmu_reset_needed = 1;
7971 }
63f42e02 7972 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7973
7974 if (mmu_reset_needed)
7975 kvm_mmu_reset_context(vcpu);
7976
a50abc3b 7977 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7978 pending_vec = find_first_bit(
7979 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7980 if (pending_vec < max_bits) {
66fd3f7f 7981 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7982 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7983 }
7984
3e6e0aab
GT		 7985 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7986 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7987 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7988 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7989 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7990 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7991
3e6e0aab
GT		 7992 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7993 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7994
5f0269f5
ME		 7995 update_cr8_intercept(vcpu);
7996
9c3e4aab 7997 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7998 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7999 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8000 !is_protmode(vcpu))
9c3e4aab
MT		 8001 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8002
3842d135
AK		 8003 kvm_make_request(KVM_REQ_EVENT, vcpu);
8004
b4ef9d4e
CD		 8005 ret = 0;
8006out:
01643c51
KH		 8007 return ret;
8008}
8009
8010int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8011 struct kvm_sregs *sregs)
8012{
8013 int ret;
8014
8015 vcpu_load(vcpu);
8016 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8017 vcpu_put(vcpu);
8018 return ret;
b6c7a5dc
HB		 8019}
8020
d0bfb940
JK		 8021int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8022 struct kvm_guest_debug *dbg)
b6c7a5dc 8023{
355be0b9 8024 unsigned long rflags;
ae675ef0 8025 int i, r;
b6c7a5dc 8026
66b56562
CD		 8027 vcpu_load(vcpu);
8028
4f926bf2
JK		 8029 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8030 r = -EBUSY;
8031 if (vcpu->arch.exception.pending)
2122ff5e 8032 goto out;
4f926bf2
JK		 8033 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8034 kvm_queue_exception(vcpu, DB_VECTOR);
8035 else
8036 kvm_queue_exception(vcpu, BP_VECTOR);
8037 }
8038
91586a3b
JK		 8039 /*
8040 * Read rflags as long as potentially injected trace flags are still
8041 * filtered out.
8042 */
8043 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8044
8045 vcpu->guest_debug = dbg->control;
8046 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8047 vcpu->guest_debug = 0;
8048
8049 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8050 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8051 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8052 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8053 } else {
8054 for (i = 0; i < KVM_NR_DB_REGS; i++)
8055 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8056 }
c8639010 8057 kvm_update_dr7(vcpu);
ae675ef0 8058
f92653ee
JK		 8059 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8060 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8061 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8062
91586a3b
JK		 8063 /*
8064 * Trigger an rflags update that will inject or remove the trace
8065 * flags.
8066 */
8067 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8068
a96036b8 8069 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8070
4f926bf2 8071 r = 0;
d0bfb940 8072
2122ff5e 8073out:
66b56562 8074 vcpu_put(vcpu);
b6c7a5dc
HB		 8075 return r;
8076}
8077
8b006791
ZX		 8078/*
8079 * Translate a guest virtual address to a guest physical address.
8080 */
8081int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8082 struct kvm_translation *tr)
8083{
8084 unsigned long vaddr = tr->linear_address;
8085 gpa_t gpa;
f656ce01 8086 int idx;
8b006791 8087
1da5b61d
CD		 8088 vcpu_load(vcpu);
8089
f656ce01 8090 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8091 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8092 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8093 tr->physical_address = gpa;
8094 tr->valid = gpa != UNMAPPED_GVA;
8095 tr->writeable = 1;
8096 tr->usermode = 0;
8b006791 8097
1da5b61d 8098 vcpu_put(vcpu);
8b006791
ZX		 8099 return 0;
8100}
8101
d0752060
HB		 8102int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8103{
1393123e 8104 struct fxregs_state *fxsave;
d0752060 8105
1393123e 8106 vcpu_load(vcpu);
d0752060 8107
1393123e 8108 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8109 memcpy(fpu->fpr, fxsave->st_space, 128);
8110 fpu->fcw = fxsave->cwd;
8111 fpu->fsw = fxsave->swd;
8112 fpu->ftwx = fxsave->twd;
8113 fpu->last_opcode = fxsave->fop;
8114 fpu->last_ip = fxsave->rip;
8115 fpu->last_dp = fxsave->rdp;
8116 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8117
1393123e 8118 vcpu_put(vcpu);
d0752060
HB		 8119 return 0;
8120}
8121
8122int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8123{
6a96bc7f
CD		 8124 struct fxregs_state *fxsave;
8125
8126 vcpu_load(vcpu);
8127
8128 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8129
d0752060
HB		 8130 memcpy(fxsave->st_space, fpu->fpr, 128);
8131 fxsave->cwd = fpu->fcw;
8132 fxsave->swd = fpu->fsw;
8133 fxsave->twd = fpu->ftwx;
8134 fxsave->fop = fpu->last_opcode;
8135 fxsave->rip = fpu->last_ip;
8136 fxsave->rdp = fpu->last_dp;
8137 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8138
6a96bc7f 8139 vcpu_put(vcpu);
d0752060
HB		 8140 return 0;
8141}
8142
01643c51
KH		 8143static void store_regs(struct kvm_vcpu *vcpu)
8144{
8145 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8146
8147 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8148 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8149
8150 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8151 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8152
8153 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8154 kvm_vcpu_ioctl_x86_get_vcpu_events(
8155 vcpu, &vcpu->run->s.regs.events);
8156}
8157
8158static int sync_regs(struct kvm_vcpu *vcpu)
8159{
8160 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8161 return -EINVAL;
8162
8163 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8164 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8165 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8166 }
8167 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8168 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8169 return -EINVAL;
8170 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8171 }
8172 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8173 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8174 vcpu, &vcpu->run->s.regs.events))
8175 return -EINVAL;
8176 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8177 }
8178
8179 return 0;
8180}
8181
0ee6a517 8182static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8183{
bf935b0b 8184 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8185 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8186 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8187 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8188
2acf923e
DC		 8189 /*
8190 * Ensure guest xcr0 is valid for loading
8191 */
d91cab78 8192 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8193
ad312c7c 8194 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8195}
d0752060 8196
f775b13e 8197/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8198void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8199{
f775b13e
RR		 8200 preempt_disable();
8201 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8202 /* PKRU is separately restored in kvm_x86_ops->run. */
8203 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8204 ~XFEATURE_MASK_PKRU);
f775b13e 8205 preempt_enable();
0c04851c 8206 trace_kvm_fpu(1);
d0752060 8207}
d0752060 8208
f775b13e 8209/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8210void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8211{
f775b13e 8212 preempt_disable();
4f836347 8213 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8214 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8215 preempt_enable();
f096ed85 8216 ++vcpu->stat.fpu_reload;
0c04851c 8217 trace_kvm_fpu(0);
d0752060 8218}
e9b11c17
ZX		 8219
8220void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8221{
bd768e14
IY		 8222 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8223
12f9a48f 8224 kvmclock_reset(vcpu);
7f1ea208 8225
e9b11c17 8226 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8227 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8228}
8229
8230struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8231 unsigned int id)
8232{
c447e76b
LL		 8233 struct kvm_vcpu *vcpu;
8234
b0c39dc6 8235 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8236 printk_once(KERN_WARNING
8237 "kvm: SMP vm created on host with unstable TSC; "
8238 "guest TSC will not be reliable\n");
c447e76b
LL		 8239
8240 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8241
c447e76b 8242 return vcpu;
26e5215f 8243}
e9b11c17 8244
26e5215f
AK		 8245int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8246{
19efffa2 8247 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8248 vcpu_load(vcpu);
d28bc9dd 8249 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8250 kvm_mmu_setup(vcpu);
e9b11c17 8251 vcpu_put(vcpu);
ec7660cc 8252 return 0;
e9b11c17
ZX		 8253}
8254
31928aa5 8255void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8256{
8fe8ab46 8257 struct msr_data msr;
332967a3 8258 struct kvm *kvm = vcpu->kvm;
42897d86 8259
d3457c87
RK		 8260 kvm_hv_vcpu_postcreate(vcpu);
8261
ec7660cc 8262 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8263 return;
ec7660cc 8264 vcpu_load(vcpu);
8fe8ab46
WA		 8265 msr.data = 0x0;
8266 msr.index = MSR_IA32_TSC;
8267 msr.host_initiated = true;
8268 kvm_write_tsc(vcpu, &msr);
42897d86 8269 vcpu_put(vcpu);
ec7660cc 8270 mutex_unlock(&vcpu->mutex);
42897d86 8271
630994b3
MT		 8272 if (!kvmclock_periodic_sync)
8273 return;
8274
332967a3
AJ		 8275 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8276 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8277}
8278
d40ccc62 8279void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8280{
344d9588
GN		 8281 vcpu->arch.apf.msr_val = 0;
8282
ec7660cc 8283 vcpu_load(vcpu);
e9b11c17
ZX		 8284 kvm_mmu_unload(vcpu);
8285 vcpu_put(vcpu);
8286
8287 kvm_x86_ops->vcpu_free(vcpu);
8288}
8289
d28bc9dd 8290void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8291{
b7e31be3
RK		 8292 kvm_lapic_reset(vcpu, init_event);
8293
e69fab5d
PB		 8294 vcpu->arch.hflags = 0;
8295
c43203ca 8296 vcpu->arch.smi_pending = 0;
52797bf9 8297 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8298 atomic_set(&vcpu->arch.nmi_queued, 0);
8299 vcpu->arch.nmi_pending = 0;
448fa4a9 8300 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8301 kvm_clear_interrupt_queue(vcpu);
8302 kvm_clear_exception_queue(vcpu);
664f8e26 8303 vcpu->arch.exception.pending = false;
448fa4a9 8304
42dbaa5a 8305 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8306 kvm_update_dr0123(vcpu);
6f43ed01 8307 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8308 kvm_update_dr6(vcpu);
42dbaa5a 8309 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8310 kvm_update_dr7(vcpu);
42dbaa5a 8311
1119022c
NA		 8312 vcpu->arch.cr2 = 0;
8313
3842d135 8314 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8315 vcpu->arch.apf.msr_val = 0;
c9aaa895 8316 vcpu->arch.st.msr_val = 0;
3842d135 8317
12f9a48f
GC		 8318 kvmclock_reset(vcpu);
8319
af585b92
GN		 8320 kvm_clear_async_pf_completion_queue(vcpu);
8321 kvm_async_pf_hash_reset(vcpu);
8322 vcpu->arch.apf.halted = false;
3842d135 8323
a554d207
WL		 8324 if (kvm_mpx_supported()) {
8325 void *mpx_state_buffer;
8326
8327 /*
8328 * To avoid have the INIT path from kvm_apic_has_events() that be
8329 * called with loaded FPU and does not let userspace fix the state.
8330 */
f775b13e
RR		 8331 if (init_event)
8332 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8333 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8334 XFEATURE_MASK_BNDREGS);
8335 if (mpx_state_buffer)
8336 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8337 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8338 XFEATURE_MASK_BNDCSR);
8339 if (mpx_state_buffer)
8340 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8341 if (init_event)
8342 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8343 }
8344
64d60670 8345 if (!init_event) {
d28bc9dd 8346 kvm_pmu_reset(vcpu);
64d60670 8347 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8348
8349 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8350 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8351
8352 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8353 }
f5132b01 8354
66f7b72e
JS		 8355 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8356 vcpu->arch.regs_avail = ~0;
8357 vcpu->arch.regs_dirty = ~0;
8358
a554d207
WL		 8359 vcpu->arch.ia32_xss = 0;
8360
d28bc9dd 8361 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8362}
8363
2b4a273b 8364void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8365{
8366 struct kvm_segment cs;
8367
8368 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8369 cs.selector = vector << 8;
8370 cs.base = vector << 12;
8371 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8372 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8373}
8374
13a34e06 8375int kvm_arch_hardware_enable(void)
e9b11c17 8376{
ca84d1a2
ZA		 8377 struct kvm *kvm;
8378 struct kvm_vcpu *vcpu;
8379 int i;
0dd6a6ed
ZA		 8380 int ret;
8381 u64 local_tsc;
8382 u64 max_tsc = 0;
8383 bool stable, backwards_tsc = false;
18863bdd
AK		 8384
8385 kvm_shared_msr_cpu_online();
13a34e06 8386 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8387 if (ret != 0)
8388 return ret;
8389
4ea1636b 8390 local_tsc = rdtsc();
b0c39dc6 8391 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8392 list_for_each_entry(kvm, &vm_list, vm_list) {
8393 kvm_for_each_vcpu(i, vcpu, kvm) {
8394 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8395 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8396 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8397 backwards_tsc = true;
8398 if (vcpu->arch.last_host_tsc > max_tsc)
8399 max_tsc = vcpu->arch.last_host_tsc;
8400 }
8401 }
8402 }
8403
8404 /*
8405 * Sometimes, even reliable TSCs go backwards. This happens on
8406 * platforms that reset TSC during suspend or hibernate actions, but
8407 * maintain synchronization. We must compensate. Fortunately, we can
8408 * detect that condition here, which happens early in CPU bringup,
8409 * before any KVM threads can be running. Unfortunately, we can't
8410 * bring the TSCs fully up to date with real time, as we aren't yet far
8411 * enough into CPU bringup that we know how much real time has actually
108b249c 8412 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8413 * variables that haven't been updated yet.
8414 *
8415 * So we simply find the maximum observed TSC above, then record the
8416 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8417 * the adjustment will be applied. Note that we accumulate
8418 * adjustments, in case multiple suspend cycles happen before some VCPU
8419 * gets a chance to run again. In the event that no KVM threads get a
8420 * chance to run, we will miss the entire elapsed period, as we'll have
8421 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8422 * loose cycle time. This isn't too big a deal, since the loss will be
8423 * uniform across all VCPUs (not to mention the scenario is extremely
8424 * unlikely). It is possible that a second hibernate recovery happens
8425 * much faster than a first, causing the observed TSC here to be
8426 * smaller; this would require additional padding adjustment, which is
8427 * why we set last_host_tsc to the local tsc observed here.
8428 *
8429 * N.B. - this code below runs only on platforms with reliable TSC,
8430 * as that is the only way backwards_tsc is set above. Also note
8431 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8432 * have the same delta_cyc adjustment applied if backwards_tsc
8433 * is detected. Note further, this adjustment is only done once,
8434 * as we reset last_host_tsc on all VCPUs to stop this from being
8435 * called multiple times (one for each physical CPU bringup).
8436 *
4a969980 8437 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8438 * will be compensated by the logic in vcpu_load, which sets the TSC to
8439 * catchup mode. This will catchup all VCPUs to real time, but cannot
8440 * guarantee that they stay in perfect synchronization.
8441 */
8442 if (backwards_tsc) {
8443 u64 delta_cyc = max_tsc - local_tsc;
8444 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8445 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8446 kvm_for_each_vcpu(i, vcpu, kvm) {
8447 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8448 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8449 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8450 }
8451
8452 /*
8453 * We have to disable TSC offset matching.. if you were
8454 * booting a VM while issuing an S4 host suspend....
8455 * you may have some problem. Solving this issue is
8456 * left as an exercise to the reader.
8457 */
8458 kvm->arch.last_tsc_nsec = 0;
8459 kvm->arch.last_tsc_write = 0;
8460 }
8461
8462 }
8463 return 0;
e9b11c17
ZX		 8464}
8465
13a34e06 8466void kvm_arch_hardware_disable(void)
e9b11c17 8467{
13a34e06
RK		 8468 kvm_x86_ops->hardware_disable();
8469 drop_user_return_notifiers();
e9b11c17
ZX		 8470}
8471
8472int kvm_arch_hardware_setup(void)
8473{
9e9c3fe4
NA		 8474 int r;
8475
8476 r = kvm_x86_ops->hardware_setup();
8477 if (r != 0)
8478 return r;
8479
35181e86
HZ		 8480 if (kvm_has_tsc_control) {
8481 /*
8482 * Make sure the user can only configure tsc_khz values that
8483 * fit into a signed integer.
8484 * A min value is not calculated needed because it will always
8485 * be 1 on all machines.
8486 */
8487 u64 max = min(0x7fffffffULL,
8488 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8489 kvm_max_guest_tsc_khz = max;
8490
ad721883 8491 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8492 }
ad721883 8493
9e9c3fe4
NA		 8494 kvm_init_msr_list();
8495 return 0;
e9b11c17
ZX		 8496}
8497
8498void kvm_arch_hardware_unsetup(void)
8499{
8500 kvm_x86_ops->hardware_unsetup();
8501}
8502
8503void kvm_arch_check_processor_compat(void *rtn)
8504{
8505 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8506}
8507
8508bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8509{
8510 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8511}
8512EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8513
8514bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8515{
8516 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8517}
8518
54e9818f 8519struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8520EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8521
e9b11c17
ZX		 8522int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8523{
8524 struct page *page;
e9b11c17
ZX		 8525 int r;
8526
b2a05fef 8527 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8528 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8529 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8530 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8531 else
a4535290 8532 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8533
8534 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8535 if (!page) {
8536 r = -ENOMEM;
8537 goto fail;
8538 }
ad312c7c 8539 vcpu->arch.pio_data = page_address(page);
e9b11c17 8540
cc578287 8541 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8542
e9b11c17
ZX		 8543 r = kvm_mmu_create(vcpu);
8544 if (r < 0)
8545 goto fail_free_pio_data;
8546
26de7988 8547 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8548 r = kvm_create_lapic(vcpu);
8549 if (r < 0)
8550 goto fail_mmu_destroy;
54e9818f
GN		 8551 } else
8552 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8553
890ca9ae
HY		 8554 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8555 GFP_KERNEL);
8556 if (!vcpu->arch.mce_banks) {
8557 r = -ENOMEM;
443c39bc 8558 goto fail_free_lapic;
890ca9ae
HY		 8559 }
8560 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8561
f1797359
WY		 8562 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8563 r = -ENOMEM;
f5f48ee1 8564 goto fail_free_mce_banks;
f1797359 8565 }
f5f48ee1 8566
0ee6a517 8567 fx_init(vcpu);
66f7b72e 8568
4344ee98 8569 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8570
5a4f55cd
EK		 8571 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8572
74545705
RK		 8573 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8574
af585b92 8575 kvm_async_pf_hash_reset(vcpu);
f5132b01 8576 kvm_pmu_init(vcpu);
af585b92 8577
1c1a9ce9 8578 vcpu->arch.pending_external_vector = -1;
de63ad4c 8579 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8580
5c919412
AS		 8581 kvm_hv_vcpu_init(vcpu);
8582
e9b11c17 8583 return 0;
0ee6a517 8584
f5f48ee1
SY		 8585fail_free_mce_banks:
8586 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8587fail_free_lapic:
8588 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8589fail_mmu_destroy:
8590 kvm_mmu_destroy(vcpu);
8591fail_free_pio_data:
ad312c7c 8592 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8593fail:
8594 return r;
8595}
8596
8597void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8598{
f656ce01
MT		 8599 int idx;
8600
1f4b34f8 8601 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8602 kvm_pmu_destroy(vcpu);
36cb93fd 8603 kfree(vcpu->arch.mce_banks);
e9b11c17 8604 kvm_free_lapic(vcpu);
f656ce01 8605 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8606 kvm_mmu_destroy(vcpu);
f656ce01 8607 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8608 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8609 if (!lapic_in_kernel(vcpu))
54e9818f 8610 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8611}
d19a9cd2 8612
e790d9ef
RK		 8613void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8614{
ae97a3b8 8615 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8616}
8617
e08b9637 8618int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8619{
e08b9637
CO		 8620 if (type)
8621 return -EINVAL;
8622
6ef768fa 8623 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8624 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8625 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8626 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8627 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8628
5550af4d
SY		 8629 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8630 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8631 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8632 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8633 &kvm->arch.irq_sources_bitmap);
5550af4d 8634
038f8c11 8635 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8636 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8637 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8638
108b249c 8639 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8640 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8641
7e44e449 8642 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8643 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8644
cbc0236a 8645 kvm_hv_init_vm(kvm);
0eb05bf2 8646 kvm_page_track_init(kvm);
13d268ca 8647 kvm_mmu_init_vm(kvm);
0eb05bf2 8648
03543133
SS		 8649 if (kvm_x86_ops->vm_init)
8650 return kvm_x86_ops->vm_init(kvm);
8651
d89f5eff 8652 return 0;
d19a9cd2
ZX		 8653}
8654
8655static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8656{
ec7660cc 8657 vcpu_load(vcpu);
d19a9cd2
ZX		 8658 kvm_mmu_unload(vcpu);
8659 vcpu_put(vcpu);
8660}
8661
8662static void kvm_free_vcpus(struct kvm *kvm)
8663{
8664 unsigned int i;
988a2cae 8665 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8666
8667 /*
8668 * Unpin any mmu pages first.
8669 */
af585b92
GN		 8670 kvm_for_each_vcpu(i, vcpu, kvm) {
8671 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8672 kvm_unload_vcpu_mmu(vcpu);
af585b92 8673 }
988a2cae
GN		 8674 kvm_for_each_vcpu(i, vcpu, kvm)
8675 kvm_arch_vcpu_free(vcpu);
8676
8677 mutex_lock(&kvm->lock);
8678 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8679 kvm->vcpus[i] = NULL;
d19a9cd2 8680
988a2cae
GN		 8681 atomic_set(&kvm->online_vcpus, 0);
8682 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8683}
8684
ad8ba2cd
SY		 8685void kvm_arch_sync_events(struct kvm *kvm)
8686{
332967a3 8687 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8688 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8689 kvm_free_pit(kvm);
ad8ba2cd
SY		 8690}
8691
1d8007bd 8692int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8693{
8694 int i, r;
25188b99 8695 unsigned long hva;
f0d648bd
PB		 8696 struct kvm_memslots *slots = kvm_memslots(kvm);
8697 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8698
8699 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8700 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8701 return -EINVAL;
9da0e4d5 8702
f0d648bd
PB		 8703 slot = id_to_memslot(slots, id);
8704 if (size) {
b21629da 8705 if (slot->npages)
f0d648bd
PB		 8706 return -EEXIST;
8707
8708 /*
8709 * MAP_SHARED to prevent internal slot pages from being moved
8710 * by fork()/COW.
8711 */
8712 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8713 MAP_SHARED | MAP_ANONYMOUS, 0);
8714 if (IS_ERR((void *)hva))
8715 return PTR_ERR((void *)hva);
8716 } else {
8717 if (!slot->npages)
8718 return 0;
8719
8720 hva = 0;
8721 }
8722
8723 old = *slot;
9da0e4d5 8724 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8725 struct kvm_userspace_memory_region m;
9da0e4d5 8726
1d8007bd
PB		 8727 m.slot = id | (i << 16);
8728 m.flags = 0;
8729 m.guest_phys_addr = gpa;
f0d648bd 8730 m.userspace_addr = hva;
1d8007bd 8731 m.memory_size = size;
9da0e4d5
PB		 8732 r = __kvm_set_memory_region(kvm, &m);
8733 if (r < 0)
8734 return r;
8735 }
8736
103c763c
EB		 8737 if (!size)
8738 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8739
9da0e4d5
PB		 8740 return 0;
8741}
8742EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8743
1d8007bd 8744int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8745{
8746 int r;
8747
8748 mutex_lock(&kvm->slots_lock);
1d8007bd 8749 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8750 mutex_unlock(&kvm->slots_lock);
8751
8752 return r;
8753}
8754EXPORT_SYMBOL_GPL(x86_set_memory_region);
8755
d19a9cd2
ZX		 8756void kvm_arch_destroy_vm(struct kvm *kvm)
8757{
27469d29
AH		 8758 if (current->mm == kvm->mm) {
8759 /*
8760 * Free memory regions allocated on behalf of userspace,
8761 * unless the the memory map has changed due to process exit
8762 * or fd copying.
8763 */
1d8007bd
PB		 8764 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8765 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8766 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8767 }
03543133
SS		 8768 if (kvm_x86_ops->vm_destroy)
8769 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8770 kvm_pic_destroy(kvm);
8771 kvm_ioapic_destroy(kvm);
d19a9cd2 8772 kvm_free_vcpus(kvm);
af1bae54 8773 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8774 kvm_mmu_uninit_vm(kvm);
2beb6dad 8775 kvm_page_track_cleanup(kvm);
cbc0236a 8776 kvm_hv_destroy_vm(kvm);
d19a9cd2 8777}
0de10343 8778
5587027c 8779void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8780 struct kvm_memory_slot *dont)
8781{
8782 int i;
8783
d89cc617
TY		 8784 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8785 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8786 kvfree(free->arch.rmap[i]);
d89cc617 8787 free->arch.rmap[i] = NULL;
77d11309 8788 }
d89cc617
TY		 8789 if (i == 0)
8790 continue;
8791
8792 if (!dont || free->arch.lpage_info[i - 1] !=
8793 dont->arch.lpage_info[i - 1]) {
548ef284 8794 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8795 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8796 }
8797 }
21ebbeda
XG		 8798
8799 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8800}
8801
5587027c
AK		 8802int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8803 unsigned long npages)
db3fe4eb
TY		 8804{
8805 int i;
8806
d89cc617 8807 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8808 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8809 unsigned long ugfn;
8810 int lpages;
d89cc617 8811 int level = i + 1;
db3fe4eb
TY		 8812
8813 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8814 slot->base_gfn, level) + 1;
8815
d89cc617 8816 slot->arch.rmap[i] =
a7c3e901 8817 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8818 if (!slot->arch.rmap[i])
77d11309 8819 goto out_free;
d89cc617
TY		 8820 if (i == 0)
8821 continue;
77d11309 8822
a7c3e901 8823 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8824 if (!linfo)
db3fe4eb
TY		 8825 goto out_free;
8826
92f94f1e
XG		 8827 slot->arch.lpage_info[i - 1] = linfo;
8828
db3fe4eb 8829 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8830 linfo[0].disallow_lpage = 1;
db3fe4eb 8831 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8832 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8833 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8834 /*
8835 * If the gfn and userspace address are not aligned wrt each
8836 * other, or if explicitly asked to, disable large page
8837 * support for this slot
8838 */
8839 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8840 !kvm_largepages_enabled()) {
8841 unsigned long j;
8842
8843 for (j = 0; j < lpages; ++j)
92f94f1e 8844 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8845 }
8846 }
8847
21ebbeda
XG		 8848 if (kvm_page_track_create_memslot(slot, npages))
8849 goto out_free;
8850
db3fe4eb
TY		 8851 return 0;
8852
8853out_free:
d89cc617 8854 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8855 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8856 slot->arch.rmap[i] = NULL;
8857 if (i == 0)
8858 continue;
8859
548ef284 8860 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8861 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8862 }
8863 return -ENOMEM;
8864}
8865
15f46015 8866void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8867{
e6dff7d1
TY		 8868 /*
8869 * memslots->generation has been incremented.
8870 * mmio generation may have reached its maximum value.
8871 */
54bf36aa 8872 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8873}
8874
f7784b8e
MT		 8875int kvm_arch_prepare_memory_region(struct kvm *kvm,
8876 struct kvm_memory_slot *memslot,
09170a49 8877 const struct kvm_userspace_memory_region *mem,
7b6195a9 8878 enum kvm_mr_change change)
0de10343 8879{
f7784b8e
MT		 8880 return 0;
8881}
8882
88178fd4
KH		 8883static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8884 struct kvm_memory_slot *new)
8885{
8886 /* Still write protect RO slot */
8887 if (new->flags & KVM_MEM_READONLY) {
8888 kvm_mmu_slot_remove_write_access(kvm, new);
8889 return;
8890 }
8891
8892 /*
8893 * Call kvm_x86_ops dirty logging hooks when they are valid.
8894 *
8895 * kvm_x86_ops->slot_disable_log_dirty is called when:
8896 *
8897 * - KVM_MR_CREATE with dirty logging is disabled
8898 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8899 *
8900 * The reason is, in case of PML, we need to set D-bit for any slots
8901 * with dirty logging disabled in order to eliminate unnecessary GPA
8902 * logging in PML buffer (and potential PML buffer full VMEXT). This
8903 * guarantees leaving PML enabled during guest's lifetime won't have
8904 * any additonal overhead from PML when guest is running with dirty
8905 * logging disabled for memory slots.
8906 *
8907 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8908 * to dirty logging mode.
8909 *
8910 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8911 *
8912 * In case of write protect:
8913 *
8914 * Write protect all pages for dirty logging.
8915 *
8916 * All the sptes including the large sptes which point to this
8917 * slot are set to readonly. We can not create any new large
8918 * spte on this slot until the end of the logging.
8919 *
8920 * See the comments in fast_page_fault().
8921 */
8922 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8923 if (kvm_x86_ops->slot_enable_log_dirty)
8924 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8925 else
8926 kvm_mmu_slot_remove_write_access(kvm, new);
8927 } else {
8928 if (kvm_x86_ops->slot_disable_log_dirty)
8929 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8930 }
8931}
8932
f7784b8e 8933void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8934 const struct kvm_userspace_memory_region *mem,
8482644a 8935 const struct kvm_memory_slot *old,
f36f3f28 8936 const struct kvm_memory_slot *new,
8482644a 8937 enum kvm_mr_change change)
f7784b8e 8938{
8482644a 8939 int nr_mmu_pages = 0;
f7784b8e 8940
48c0e4e9
XG		 8941 if (!kvm->arch.n_requested_mmu_pages)
8942 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8943
48c0e4e9 8944 if (nr_mmu_pages)
0de10343 8945 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8946
3ea3b7fa
WL		 8947 /*
8948 * Dirty logging tracks sptes in 4k granularity, meaning that large
8949 * sptes have to be split. If live migration is successful, the guest
8950 * in the source machine will be destroyed and large sptes will be
8951 * created in the destination. However, if the guest continues to run
8952 * in the source machine (for example if live migration fails), small
8953 * sptes will remain around and cause bad performance.
8954 *
8955 * Scan sptes if dirty logging has been stopped, dropping those
8956 * which can be collapsed into a single large-page spte. Later
8957 * page faults will create the large-page sptes.
8958 */
8959 if ((change != KVM_MR_DELETE) &&
8960 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8961 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8962 kvm_mmu_zap_collapsible_sptes(kvm, new);
8963
c972f3b1 8964 /*
88178fd4 8965 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8966 *
88178fd4
KH		 8967 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8968 * been zapped so no dirty logging staff is needed for old slot. For
8969 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8970 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8971 *
8972 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8973 */
88178fd4 8974 if (change != KVM_MR_DELETE)
f36f3f28 8975 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8976}
1d737c8a 8977
2df72e9b 8978void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8979{
6ca18b69 8980 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8981}
8982
2df72e9b
MT		 8983void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8984 struct kvm_memory_slot *slot)
8985{
ae7cd873 8986 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8987}
8988
5d9bc648
PB		 8989static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8990{
8991 if (!list_empty_careful(&vcpu->async_pf.done))
8992 return true;
8993
8994 if (kvm_apic_has_events(vcpu))
8995 return true;
8996
8997 if (vcpu->arch.pv.pv_unhalted)
8998 return true;
8999
a5f01f8e
WL		 9000 if (vcpu->arch.exception.pending)
9001 return true;
9002
47a66eed
Z		 9003 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9004 (vcpu->arch.nmi_pending &&
9005 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9006 return true;
9007
47a66eed
Z		 9008 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9009 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9010 return true;
9011
5d9bc648
PB		 9012 if (kvm_arch_interrupt_allowed(vcpu) &&
9013 kvm_cpu_has_interrupt(vcpu))
9014 return true;
9015
1f4b34f8
AS		 9016 if (kvm_hv_has_stimer_pending(vcpu))
9017 return true;
9018
5d9bc648
PB		 9019 return false;
9020}
9021
1d737c8a
ZX		 9022int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9023{
5d9bc648 9024 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9025}
5736199a 9026
199b5763
LM		 9027bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9028{
de63ad4c 9029 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9030}
9031
b6d33834 9032int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9033{
b6d33834 9034 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9035}
78646121
GN		 9036
9037int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9038{
9039 return kvm_x86_ops->interrupt_allowed(vcpu);
9040}
229456fc 9041
82b32774 9042unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9043{
82b32774
NA		 9044 if (is_64_bit_mode(vcpu))
9045 return kvm_rip_read(vcpu);
9046 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9047 kvm_rip_read(vcpu));
9048}
9049EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9050
82b32774
NA		 9051bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9052{
9053 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9054}
9055EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9056
94fe45da
JK		 9057unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9058{
9059 unsigned long rflags;
9060
9061 rflags = kvm_x86_ops->get_rflags(vcpu);
9062 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9063 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9064 return rflags;
9065}
9066EXPORT_SYMBOL_GPL(kvm_get_rflags);
9067
6addfc42 9068static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9069{
9070 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9071 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9072 rflags |= X86_EFLAGS_TF;
94fe45da 9073 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9074}
9075
9076void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9077{
9078 __kvm_set_rflags(vcpu, rflags);
3842d135 9079 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9080}
9081EXPORT_SYMBOL_GPL(kvm_set_rflags);
9082
56028d08
GN		 9083void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9084{
9085 int r;
9086
fb67e14f 9087 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9088 work->wakeup_all)
56028d08
GN		 9089 return;
9090
9091 r = kvm_mmu_reload(vcpu);
9092 if (unlikely(r))
9093 return;
9094
fb67e14f
XG		 9095 if (!vcpu->arch.mmu.direct_map &&
9096 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9097 return;
9098
56028d08
GN		 9099 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9100}
9101
af585b92
GN		 9102static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9103{
9104 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9105}
9106
9107static inline u32 kvm_async_pf_next_probe(u32 key)
9108{
9109 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9110}
9111
9112static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9113{
9114 u32 key = kvm_async_pf_hash_fn(gfn);
9115
9116 while (vcpu->arch.apf.gfns[key] != ~0)
9117 key = kvm_async_pf_next_probe(key);
9118
9119 vcpu->arch.apf.gfns[key] = gfn;
9120}
9121
9122static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9123{
9124 int i;
9125 u32 key = kvm_async_pf_hash_fn(gfn);
9126
9127 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9128 (vcpu->arch.apf.gfns[key] != gfn &&
9129 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9130 key = kvm_async_pf_next_probe(key);
9131
9132 return key;
9133}
9134
9135bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9136{
9137 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9138}
9139
9140static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9141{
9142 u32 i, j, k;
9143
9144 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9145 while (true) {
9146 vcpu->arch.apf.gfns[i] = ~0;
9147 do {
9148 j = kvm_async_pf_next_probe(j);
9149 if (vcpu->arch.apf.gfns[j] == ~0)
9150 return;
9151 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9152 /*
9153 * k lies cyclically in ]i,j]
9154 * | i.k.j |
9155 * |....j i.k.| or |.k..j i...|
9156 */
9157 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9158 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9159 i = j;
9160 }
9161}
9162
7c90705b
GN		 9163static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9164{
4e335d9e
PB		 9165
9166 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9167 sizeof(val));
7c90705b
GN		 9168}
9169
9a6e7c39
WL		 9170static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9171{
9172
9173 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9174 sizeof(u32));
9175}
9176
af585b92
GN		 9177void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9178 struct kvm_async_pf *work)
9179{
6389ee94
AK		 9180 struct x86_exception fault;
9181
7c90705b 9182 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9183 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9184
9185 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9186 (vcpu->arch.apf.send_user_only &&
9187 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9188 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9189 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9190 fault.vector = PF_VECTOR;
9191 fault.error_code_valid = true;
9192 fault.error_code = 0;
9193 fault.nested_page_fault = false;
9194 fault.address = work->arch.token;
adfe20fb 9195 fault.async_page_fault = true;
6389ee94 9196 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9197 }
af585b92
GN		 9198}
9199
9200void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9201 struct kvm_async_pf *work)
9202{
6389ee94 9203 struct x86_exception fault;
9a6e7c39 9204 u32 val;
6389ee94 9205
f2e10669 9206 if (work->wakeup_all)
7c90705b
GN		 9207 work->arch.token = ~0; /* broadcast wakeup */
9208 else
9209 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9210 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9211
9a6e7c39
WL		 9212 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9213 !apf_get_user(vcpu, &val)) {
9214 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9215 vcpu->arch.exception.pending &&
9216 vcpu->arch.exception.nr == PF_VECTOR &&
9217 !apf_put_user(vcpu, 0)) {
9218 vcpu->arch.exception.injected = false;
9219 vcpu->arch.exception.pending = false;
9220 vcpu->arch.exception.nr = 0;
9221 vcpu->arch.exception.has_error_code = false;
9222 vcpu->arch.exception.error_code = 0;
9223 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9224 fault.vector = PF_VECTOR;
9225 fault.error_code_valid = true;
9226 fault.error_code = 0;
9227 fault.nested_page_fault = false;
9228 fault.address = work->arch.token;
9229 fault.async_page_fault = true;
9230 kvm_inject_page_fault(vcpu, &fault);
9231 }
7c90705b 9232 }
e6d53e3b 9233 vcpu->arch.apf.halted = false;
a4fa1635 9234 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9235}
9236
9237bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9238{
9239 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9240 return true;
9241 else
9bc1f09f 9242 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9243}
9244
5544eb9b
PB		 9245void kvm_arch_start_assignment(struct kvm *kvm)
9246{
9247 atomic_inc(&kvm->arch.assigned_device_count);
9248}
9249EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9250
9251void kvm_arch_end_assignment(struct kvm *kvm)
9252{
9253 atomic_dec(&kvm->arch.assigned_device_count);
9254}
9255EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9256
9257bool kvm_arch_has_assigned_device(struct kvm *kvm)
9258{
9259 return atomic_read(&kvm->arch.assigned_device_count);
9260}
9261EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9262
e0f0bbc5
AW		 9263void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9264{
9265 atomic_inc(&kvm->arch.noncoherent_dma_count);
9266}
9267EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9268
9269void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9270{
9271 atomic_dec(&kvm->arch.noncoherent_dma_count);
9272}
9273EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9274
9275bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9276{
9277 return atomic_read(&kvm->arch.noncoherent_dma_count);
9278}
9279EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9280
14717e20
AW		 9281bool kvm_arch_has_irq_bypass(void)
9282{
9283 return kvm_x86_ops->update_pi_irte != NULL;
9284}
9285
87276880
FW		 9286int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9287 struct irq_bypass_producer *prod)
9288{
9289 struct kvm_kernel_irqfd *irqfd =
9290 container_of(cons, struct kvm_kernel_irqfd, consumer);
9291
14717e20 9292 irqfd->producer = prod;
87276880 9293
14717e20
AW		 9294 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9295 prod->irq, irqfd->gsi, 1);
87276880
FW		 9296}
9297
9298void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9299 struct irq_bypass_producer *prod)
9300{
9301 int ret;
9302 struct kvm_kernel_irqfd *irqfd =
9303 container_of(cons, struct kvm_kernel_irqfd, consumer);
9304
87276880
FW		 9305 WARN_ON(irqfd->producer != prod);
9306 irqfd->producer = NULL;
9307
9308 /*
9309 * When producer of consumer is unregistered, we change back to
9310 * remapped mode, so we can re-use the current implementation
bb3541f1 9311 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9312 * int this case doesn't want to receive the interrupts.
9313 */
9314 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9315 if (ret)
9316 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9317 " fails: %d\n", irqfd->consumer.token, ret);
9318}
9319
9320int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9321 uint32_t guest_irq, bool set)
9322{
9323 if (!kvm_x86_ops->update_pi_irte)
9324 return -EINVAL;
9325
9326 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9327}
9328
52004014
FW		 9329bool kvm_vector_hashing_enabled(void)
9330{
9331 return vector_hashing;
9332}
9333EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9334
229456fc 9335EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9336EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9337EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9338EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9339EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9340EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9341EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9342EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9343EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9344EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9345EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9346EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9347EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9348EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9349EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9350EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9351EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9352EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9353EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)