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KVM: LAPIC: Make lapic timer unpinned
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
043405e1
CO		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 17 */
18
edf88417 19#include <linux/kvm_host.h>
313a3dc7 20#include "irq.h"
1d737c8a 21#include "mmu.h"
7837699f 22#include "i8254.h"
37817f29 23#include "tss.h"
5fdbf976 24#include "kvm_cache_regs.h"
26eef70c 25#include "x86.h"
00b27a3e 26#include "cpuid.h"
474a5bb9 27#include "pmu.h"
e83d5887 28#include "hyperv.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
1767e931
PG		 35#include <linux/export.h>
36#include <linux/moduleparam.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
87276880
FW		 51#include <linux/kvm_irqfd.h>
52#include <linux/irqbypass.h>
3905f9ad 53#include <linux/sched/stat.h>
d0ec49d4 54#include <linux/mem_encrypt.h>
3905f9ad 55
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
24f1e32c 58#include <asm/debugreg.h>
d825ed0a 59#include <asm/msr.h>
a5f61300 60#include <asm/desc.h>
890ca9ae 61#include <asm/mce.h>
f89e32e0 62#include <linux/kernel_stat.h>
78f7f1e5 63#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
efc64404 66#include <asm/irq_remapping.h>
b0c39dc6 67#include <asm/mshyperv.h>
0092e434 68#include <asm/hypervisor.h>
bf8c55d8 69#include <asm/intel_pt.h>
dd2cb348 70#include <clocksource/hyperv_timer.h>
043405e1 71
d1898b73
DH		 72#define CREATE_TRACE_POINTS
73#include "trace.h"
74
313a3dc7 75#define MAX_IO_MSRS 256
890ca9ae 76#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 77u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
78EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 79
0f65dd70
AK		 80#define emul_to_vcpu(ctxt) \
81 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
82
50a37eb4
JR		 83/* EFER defaults:
84 * - enable syscall per default because its emulated by KVM
85 * - enable LME and LMA per default on 64 bit KVM
86 */
87#ifdef CONFIG_X86_64
1260edbe
LJ		 88static
89u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 90#else
1260edbe 91static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 92#endif
313a3dc7 93
ba1389b7
AK		 94#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
95#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 96
c519265f
RK		 97#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
98 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 99
cb142eb7 100static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 101static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 102static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 103static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 104static void store_regs(struct kvm_vcpu *vcpu);
105static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 106
893590c7 107struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 108EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 109
893590c7 110static bool __read_mostly ignore_msrs = 0;
476bc001 111module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 112
fab0aa3b
EM		 113static bool __read_mostly report_ignored_msrs = true;
114module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
115
4c27625b 116unsigned int min_timer_period_us = 200;
9ed96e87
MT		 117module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
118
630994b3
MT		 119static bool __read_mostly kvmclock_periodic_sync = true;
120module_param(kvmclock_periodic_sync, bool, S_IRUGO);
121
893590c7 122bool __read_mostly kvm_has_tsc_control;
92a1f12d 123EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 124u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 125EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 126u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
127EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
128u64 __read_mostly kvm_max_tsc_scaling_ratio;
129EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 130u64 __read_mostly kvm_default_tsc_scaling_ratio;
131EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 132
cc578287 133/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 134static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 135module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
136
c3941d9e
SC		 137/*
138 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
139 * adaptive tuning starting from default advancment of 1000ns. '0' disables
140 * advancement entirely. Any other value is used as-is and disables adaptive
141 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
142 */
143static int __read_mostly lapic_timer_advance_ns = -1;
0e6edceb 144module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
d0659d94 145
52004014
FW		 146static bool __read_mostly vector_hashing = true;
147module_param(vector_hashing, bool, S_IRUGO);
148
c4ae60e4
LA		 149bool __read_mostly enable_vmware_backdoor = false;
150module_param(enable_vmware_backdoor, bool, S_IRUGO);
151EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
152
6c86eedc
WL		 153static bool __read_mostly force_emulation_prefix = false;
154module_param(force_emulation_prefix, bool, S_IRUGO);
155
18863bdd
AK		 156#define KVM_NR_SHARED_MSRS 16
157
158struct kvm_shared_msrs_global {
159 int nr;
2bf78fa7 160 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 161};
162
163struct kvm_shared_msrs {
164 struct user_return_notifier urn;
165 bool registered;
2bf78fa7
SY		 166 struct kvm_shared_msr_values {
167 u64 host;
168 u64 curr;
169 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 170};
171
172static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 173static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 174
417bc304 175struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 176 { "pf_fixed", VCPU_STAT(pf_fixed) },
177 { "pf_guest", VCPU_STAT(pf_guest) },
178 { "tlb_flush", VCPU_STAT(tlb_flush) },
179 { "invlpg", VCPU_STAT(invlpg) },
180 { "exits", VCPU_STAT(exits) },
181 { "io_exits", VCPU_STAT(io_exits) },
182 { "mmio_exits", VCPU_STAT(mmio_exits) },
183 { "signal_exits", VCPU_STAT(signal_exits) },
184 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 185 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 186 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 187 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 188 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 189 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 190 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 191 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 192 { "request_irq", VCPU_STAT(request_irq_exits) },
193 { "irq_exits", VCPU_STAT(irq_exits) },
194 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 195 { "fpu_reload", VCPU_STAT(fpu_reload) },
196 { "insn_emulation", VCPU_STAT(insn_emulation) },
197 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 198 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 199 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 200 { "req_event", VCPU_STAT(req_event) },
c595ceee 201 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 202 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
203 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
204 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
205 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
206 { "mmu_flooded", VM_STAT(mmu_flooded) },
207 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 208 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 209 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 210 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 211 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 212 { "max_mmu_page_hash_collisions",
213 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 214 { NULL }
215};
216
2acf923e
DC		 217u64 __read_mostly host_xcr0;
218
b666a4b6
MO		 219struct kmem_cache *x86_fpu_cache;
220EXPORT_SYMBOL_GPL(x86_fpu_cache);
221
b6785def 222static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 223
af585b92
GN		 224static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
225{
226 int i;
227 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
228 vcpu->arch.apf.gfns[i] = ~0;
229}
230
18863bdd
AK		 231static void kvm_on_user_return(struct user_return_notifier *urn)
232{
233 unsigned slot;
18863bdd
AK		 234 struct kvm_shared_msrs *locals
235 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 236 struct kvm_shared_msr_values *values;
1650b4eb
IA		 237 unsigned long flags;
238
239 /*
240 * Disabling irqs at this point since the following code could be
241 * interrupted and executed through kvm_arch_hardware_disable()
242 */
243 local_irq_save(flags);
244 if (locals->registered) {
245 locals->registered = false;
246 user_return_notifier_unregister(urn);
247 }
248 local_irq_restore(flags);
18863bdd 249 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 250 values = &locals->values[slot];
251 if (values->host != values->curr) {
252 wrmsrl(shared_msrs_global.msrs[slot], values->host);
253 values->curr = values->host;
18863bdd
AK		 254 }
255 }
18863bdd
AK		 256}
257
2bf78fa7 258static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 259{
18863bdd 260 u64 value;
013f6a5d
MT		 261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 263
2bf78fa7
SY		 264 /* only read, and nobody should modify it at this time,
265 * so don't need lock */
266 if (slot >= shared_msrs_global.nr) {
267 printk(KERN_ERR "kvm: invalid MSR slot!");
268 return;
269 }
270 rdmsrl_safe(msr, &value);
271 smsr->values[slot].host = value;
272 smsr->values[slot].curr = value;
273}
274
275void kvm_define_shared_msr(unsigned slot, u32 msr)
276{
0123be42 277 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 278 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 279 if (slot >= shared_msrs_global.nr)
280 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 281}
282EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
283
284static void kvm_shared_msr_cpu_online(void)
285{
286 unsigned i;
18863bdd
AK		 287
288 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 289 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 290}
291
8b3c3104 292int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 293{
013f6a5d
MT		 294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 296 int err;
18863bdd 297
2bf78fa7 298 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 299 return 0;
2bf78fa7 300 smsr->values[slot].curr = value;
8b3c3104
AH		 301 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
302 if (err)
303 return 1;
304
18863bdd
AK		 305 if (!smsr->registered) {
306 smsr->urn.on_user_return = kvm_on_user_return;
307 user_return_notifier_register(&smsr->urn);
308 smsr->registered = true;
309 }
8b3c3104 310 return 0;
18863bdd
AK		 311}
312EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
313
13a34e06 314static void drop_user_return_notifiers(void)
3548bab5 315{
013f6a5d
MT		 316 unsigned int cpu = smp_processor_id();
317 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 318
319 if (smsr->registered)
320 kvm_on_user_return(&smsr->urn);
321}
322
6866b83e
CO		 323u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
324{
8a5a87d9 325 return vcpu->arch.apic_base;
6866b83e
CO		 326}
327EXPORT_SYMBOL_GPL(kvm_get_apic_base);
328
58871649
JM		 329enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
330{
331 return kvm_apic_mode(kvm_get_apic_base(vcpu));
332}
333EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
334
58cb628d
JK		 335int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
336{
58871649
JM		 337 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
338 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 339 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
340 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 341
58871649 342 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 343 return 1;
58871649
JM		 344 if (!msr_info->host_initiated) {
345 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
346 return 1;
347 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
348 return 1;
349 }
58cb628d
JK		 350
351 kvm_lapic_set_base(vcpu, msr_info->data);
352 return 0;
6866b83e
CO		 353}
354EXPORT_SYMBOL_GPL(kvm_set_apic_base);
355
2605fc21 356asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 357{
358 /* Fault while not rebooting. We want the trace. */
359 BUG();
360}
361EXPORT_SYMBOL_GPL(kvm_spurious_fault);
362
3fd28fce
ED		 363#define EXCPT_BENIGN 0
364#define EXCPT_CONTRIBUTORY 1
365#define EXCPT_PF 2
366
367static int exception_class(int vector)
368{
369 switch (vector) {
370 case PF_VECTOR:
371 return EXCPT_PF;
372 case DE_VECTOR:
373 case TS_VECTOR:
374 case NP_VECTOR:
375 case SS_VECTOR:
376 case GP_VECTOR:
377 return EXCPT_CONTRIBUTORY;
378 default:
379 break;
380 }
381 return EXCPT_BENIGN;
382}
383
d6e8c854
NA		 384#define EXCPT_FAULT 0
385#define EXCPT_TRAP 1
386#define EXCPT_ABORT 2
387#define EXCPT_INTERRUPT 3
388
389static int exception_type(int vector)
390{
391 unsigned int mask;
392
393 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
394 return EXCPT_INTERRUPT;
395
396 mask = 1 << vector;
397
398 /* #DB is trap, as instruction watchpoints are handled elsewhere */
399 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
400 return EXCPT_TRAP;
401
402 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
403 return EXCPT_ABORT;
404
405 /* Reserved exceptions will result in fault */
406 return EXCPT_FAULT;
407}
408
da998b46
JM		 409void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
410{
411 unsigned nr = vcpu->arch.exception.nr;
412 bool has_payload = vcpu->arch.exception.has_payload;
413 unsigned long payload = vcpu->arch.exception.payload;
414
415 if (!has_payload)
416 return;
417
418 switch (nr) {
f10c729f
JM		 419 case DB_VECTOR:
420 /*
421 * "Certain debug exceptions may clear bit 0-3. The
422 * remaining contents of the DR6 register are never
423 * cleared by the processor".
424 */
425 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
426 /*
427 * DR6.RTM is set by all #DB exceptions that don't clear it.
428 */
429 vcpu->arch.dr6 |= DR6_RTM;
430 vcpu->arch.dr6 |= payload;
431 /*
432 * Bit 16 should be set in the payload whenever the #DB
433 * exception should clear DR6.RTM. This makes the payload
434 * compatible with the pending debug exceptions under VMX.
435 * Though not currently documented in the SDM, this also
436 * makes the payload compatible with the exit qualification
437 * for #DB exceptions under VMX.
438 */
439 vcpu->arch.dr6 ^= payload & DR6_RTM;
440 break;
da998b46
JM		 441 case PF_VECTOR:
442 vcpu->arch.cr2 = payload;
443 break;
444 }
445
446 vcpu->arch.exception.has_payload = false;
447 vcpu->arch.exception.payload = 0;
448}
449EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
450
3fd28fce 451static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 452 unsigned nr, bool has_error, u32 error_code,
91e86d22 453 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 454{
455 u32 prev_nr;
456 int class1, class2;
457
3842d135
AK		 458 kvm_make_request(KVM_REQ_EVENT, vcpu);
459
664f8e26 460 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 461 queue:
3ffb2468
NA		 462 if (has_error && !is_protmode(vcpu))
463 has_error = false;
664f8e26
WL		 464 if (reinject) {
465 /*
466 * On vmentry, vcpu->arch.exception.pending is only
467 * true if an event injection was blocked by
468 * nested_run_pending. In that case, however,
469 * vcpu_enter_guest requests an immediate exit,
470 * and the guest shouldn't proceed far enough to
471 * need reinjection.
472 */
473 WARN_ON_ONCE(vcpu->arch.exception.pending);
474 vcpu->arch.exception.injected = true;
91e86d22
JM		 475 if (WARN_ON_ONCE(has_payload)) {
476 /*
477 * A reinjected event has already
478 * delivered its payload.
479 */
480 has_payload = false;
481 payload = 0;
482 }
664f8e26
WL		 483 } else {
484 vcpu->arch.exception.pending = true;
485 vcpu->arch.exception.injected = false;
486 }
3fd28fce
ED		 487 vcpu->arch.exception.has_error_code = has_error;
488 vcpu->arch.exception.nr = nr;
489 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 490 vcpu->arch.exception.has_payload = has_payload;
491 vcpu->arch.exception.payload = payload;
da998b46
JM		 492 /*
493 * In guest mode, payload delivery should be deferred,
494 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 495 * CR2 is modified (or intercept #DB before DR6 is
496 * modified under nVMX). However, for ABI
497 * compatibility with KVM_GET_VCPU_EVENTS and
498 * KVM_SET_VCPU_EVENTS, we can't delay payload
499 * delivery unless userspace has enabled this
500 * functionality via the per-VM capability,
501 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 502 */
503 if (!vcpu->kvm->arch.exception_payload_enabled ||
504 !is_guest_mode(vcpu))
505 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 506 return;
507 }
508
509 /* to check exception */
510 prev_nr = vcpu->arch.exception.nr;
511 if (prev_nr == DF_VECTOR) {
512 /* triple fault -> shutdown */
a8eeb04a 513 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 514 return;
515 }
516 class1 = exception_class(prev_nr);
517 class2 = exception_class(nr);
518 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
519 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 520 /*
521 * Generate double fault per SDM Table 5-5. Set
522 * exception.pending = true so that the double fault
523 * can trigger a nested vmexit.
524 */
3fd28fce 525 vcpu->arch.exception.pending = true;
664f8e26 526 vcpu->arch.exception.injected = false;
3fd28fce
ED		 527 vcpu->arch.exception.has_error_code = true;
528 vcpu->arch.exception.nr = DF_VECTOR;
529 vcpu->arch.exception.error_code = 0;
c851436a
JM		 530 vcpu->arch.exception.has_payload = false;
531 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 532 } else
533 /* replace previous exception with a new one in a hope
534 that instruction re-execution will regenerate lost
535 exception */
536 goto queue;
537}
538
298101da
AK		 539void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
540{
91e86d22 541 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 542}
543EXPORT_SYMBOL_GPL(kvm_queue_exception);
544
ce7ddec4
JR		 545void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
546{
91e86d22 547 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 548}
549EXPORT_SYMBOL_GPL(kvm_requeue_exception);
550
f10c729f
JM		 551static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
552 unsigned long payload)
553{
554 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
555}
556
da998b46
JM		 557static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
558 u32 error_code, unsigned long payload)
559{
560 kvm_multiple_exception(vcpu, nr, true, error_code,
561 true, payload, false);
562}
563
6affcbed 564int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 565{
db8fcefa
AP		 566 if (err)
567 kvm_inject_gp(vcpu, 0);
568 else
6affcbed
KH		 569 return kvm_skip_emulated_instruction(vcpu);
570
571 return 1;
db8fcefa
AP		 572}
573EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 574
6389ee94 575void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 576{
577 ++vcpu->stat.pf_guest;
adfe20fb
WL		 578 vcpu->arch.exception.nested_apf =
579 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 580 if (vcpu->arch.exception.nested_apf) {
adfe20fb 581 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 582 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
583 } else {
584 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
585 fault->address);
586 }
c3c91fee 587}
27d6c865 588EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 589
ef54bcfe 590static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 591{
6389ee94
AK		 592 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
593 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 594 else
44dd3ffa 595 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 596
597 return fault->nested_page_fault;
d4f8cf66
JR		 598}
599
3419ffc8
SY		 600void kvm_inject_nmi(struct kvm_vcpu *vcpu)
601{
7460fb4a
AK		 602 atomic_inc(&vcpu->arch.nmi_queued);
603 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 604}
605EXPORT_SYMBOL_GPL(kvm_inject_nmi);
606
298101da
AK		 607void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
608{
91e86d22 609 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 610}
611EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
612
ce7ddec4
JR		 613void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
614{
91e86d22 615 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 616}
617EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
618
0a79b009
AK		 619/*
620 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
621 * a #GP and return false.
622 */
623bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 624{
0a79b009
AK		 625 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
626 return true;
627 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
628 return false;
298101da 629}
0a79b009 630EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 631
16f8a6f9
NA		 632bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
633{
634 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
635 return true;
636
637 kvm_queue_exception(vcpu, UD_VECTOR);
638 return false;
639}
640EXPORT_SYMBOL_GPL(kvm_require_dr);
641
ec92fe44
JR		 642/*
643 * This function will be used to read from the physical memory of the currently
54bf36aa 644 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 645 * can read from guest physical or from the guest's guest physical memory.
646 */
647int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
648 gfn_t ngfn, void *data, int offset, int len,
649 u32 access)
650{
54987b7a 651 struct x86_exception exception;
ec92fe44
JR		 652 gfn_t real_gfn;
653 gpa_t ngpa;
654
655 ngpa = gfn_to_gpa(ngfn);
54987b7a 656 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 657 if (real_gfn == UNMAPPED_GVA)
658 return -EFAULT;
659
660 real_gfn = gpa_to_gfn(real_gfn);
661
54bf36aa 662 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 663}
664EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
665
69b0049a 666static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 667 void *data, int offset, int len, u32 access)
668{
669 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
670 data, offset, len, access);
671}
672
a03490ed
CO		 673/*
674 * Load the pae pdptrs. Return true is they are all valid.
675 */
ff03a073 676int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 677{
678 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
679 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
680 int i;
681 int ret;
ff03a073 682 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 683
ff03a073
JR		 684 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
685 offset * sizeof(u64), sizeof(pdpte),
686 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 687 if (ret < 0) {
688 ret = 0;
689 goto out;
690 }
691 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 692 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 693 (pdpte[i] &
44dd3ffa 694 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 695 ret = 0;
696 goto out;
697 }
698 }
699 ret = 1;
700
ff03a073 701 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 702 __set_bit(VCPU_EXREG_PDPTR,
703 (unsigned long *)&vcpu->arch.regs_avail);
704 __set_bit(VCPU_EXREG_PDPTR,
705 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 706out:
a03490ed
CO		 707
708 return ret;
709}
cc4b6871 710EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 711
9ed38ffa 712bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 713{
ff03a073 714 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 715 bool changed = true;
3d06b8bf
JR		 716 int offset;
717 gfn_t gfn;
d835dfec
AK		 718 int r;
719
bf03d4f9 720 if (!is_pae_paging(vcpu))
d835dfec
AK		 721 return false;
722
6de4f3ad
AK		 723 if (!test_bit(VCPU_EXREG_PDPTR,
724 (unsigned long *)&vcpu->arch.regs_avail))
725 return true;
726
a512177e
PB		 727 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
728 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 729 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
730 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 731 if (r < 0)
732 goto out;
ff03a073 733 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 734out:
d835dfec
AK		 735
736 return changed;
737}
9ed38ffa 738EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 739
49a9b07e 740int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 741{
aad82703 742 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 743 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 744
f9a48e6a
AK		 745 cr0 |= X86_CR0_ET;
746
ab344828 747#ifdef CONFIG_X86_64
0f12244f
GN		 748 if (cr0 & 0xffffffff00000000UL)
749 return 1;
ab344828
GN		 750#endif
751
752 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 753
0f12244f
GN		 754 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
755 return 1;
a03490ed 756
0f12244f
GN		 757 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
758 return 1;
a03490ed
CO		 759
760 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
761#ifdef CONFIG_X86_64
f6801dff 762 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 763 int cs_db, cs_l;
764
0f12244f
GN		 765 if (!is_pae(vcpu))
766 return 1;
a03490ed 767 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 768 if (cs_l)
769 return 1;
a03490ed
CO		 770 } else
771#endif
ff03a073 772 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 773 kvm_read_cr3(vcpu)))
0f12244f 774 return 1;
a03490ed
CO		 775 }
776
ad756a16
MJ		 777 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
778 return 1;
779
a03490ed 780 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 781
d170c419 782 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 783 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 784 kvm_async_pf_hash_reset(vcpu);
785 }
e5f3f027 786
aad82703
SY		 787 if ((cr0 ^ old_cr0) & update_bits)
788 kvm_mmu_reset_context(vcpu);
b18d5431 789
879ae188
LE		 790 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
791 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
792 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 793 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
794
0f12244f
GN		 795 return 0;
796}
2d3ad1f4 797EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 798
2d3ad1f4 799void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 800{
49a9b07e 801 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 802}
2d3ad1f4 803EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 804
1811d979 805void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 806{
807 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
808 !vcpu->guest_xcr0_loaded) {
809 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 810 if (vcpu->arch.xcr0 != host_xcr0)
811 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 812 vcpu->guest_xcr0_loaded = 1;
813 }
814}
1811d979 815EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
42bdf991 816
1811d979 817void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 818{
819 if (vcpu->guest_xcr0_loaded) {
820 if (vcpu->arch.xcr0 != host_xcr0)
821 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
822 vcpu->guest_xcr0_loaded = 0;
823 }
824}
1811d979 825EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
42bdf991 826
69b0049a 827static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 828{
56c103ec
LJ		 829 u64 xcr0 = xcr;
830 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 831 u64 valid_bits;
2acf923e
DC		 832
833 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
834 if (index != XCR_XFEATURE_ENABLED_MASK)
835 return 1;
d91cab78 836 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 837 return 1;
d91cab78 838 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 839 return 1;
46c34cb0
PB		 840
841 /*
842 * Do not allow the guest to set bits that we do not support
843 * saving. However, xcr0 bit 0 is always set, even if the
844 * emulated CPU does not support XSAVE (see fx_init).
845 */
d91cab78 846 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 847 if (xcr0 & ~valid_bits)
2acf923e 848 return 1;
46c34cb0 849
d91cab78
DH		 850 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
851 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 852 return 1;
853
d91cab78
DH		 854 if (xcr0 & XFEATURE_MASK_AVX512) {
855 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 856 return 1;
d91cab78 857 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 858 return 1;
859 }
2acf923e 860 vcpu->arch.xcr0 = xcr0;
56c103ec 861
d91cab78 862 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 863 kvm_update_cpuid(vcpu);
2acf923e
DC		 864 return 0;
865}
866
867int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
868{
764bcbc5
Z		 869 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
870 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 871 kvm_inject_gp(vcpu, 0);
872 return 1;
873 }
874 return 0;
875}
876EXPORT_SYMBOL_GPL(kvm_set_xcr);
877
a83b29c6 878int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 879{
fc78f519 880 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 881 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 882 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 883
0f12244f
GN		 884 if (cr4 & CR4_RESERVED_BITS)
885 return 1;
a03490ed 886
d6321d49 887 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 888 return 1;
889
d6321d49 890 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 891 return 1;
892
d6321d49 893 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 894 return 1;
895
d6321d49 896 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 897 return 1;
898
d6321d49 899 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 900 return 1;
901
fd8cb433 902 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 903 return 1;
904
ae3e61e1
PB		 905 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
906 return 1;
907
a03490ed 908 if (is_long_mode(vcpu)) {
0f12244f
GN		 909 if (!(cr4 & X86_CR4_PAE))
910 return 1;
a2edf57f
AK		 911 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
912 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 913 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
914 kvm_read_cr3(vcpu)))
0f12244f
GN		 915 return 1;
916
ad756a16 917 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 918 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 919 return 1;
920
921 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
922 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
923 return 1;
924 }
925
5e1746d6 926 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 927 return 1;
a03490ed 928
ad756a16
MJ		 929 if (((cr4 ^ old_cr4) & pdptr_bits) ||
930 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 931 kvm_mmu_reset_context(vcpu);
0f12244f 932
b9baba86 933 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 934 kvm_update_cpuid(vcpu);
2acf923e 935
0f12244f
GN		 936 return 0;
937}
2d3ad1f4 938EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 939
2390218b 940int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 941{
ade61e28 942 bool skip_tlb_flush = false;
ac146235 943#ifdef CONFIG_X86_64
c19986fe
JS		 944 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
945
ade61e28 946 if (pcid_enabled) {
208320ba
JS		 947 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
948 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 949 }
ac146235 950#endif
9d88fca7 951
9f8fe504 952 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 953 if (!skip_tlb_flush) {
954 kvm_mmu_sync_roots(vcpu);
ade61e28 955 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 956 }
0f12244f 957 return 0;
d835dfec
AK		 958 }
959
d1cd3ce9 960 if (is_long_mode(vcpu) &&
a780a3ea 961 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9 962 return 1;
bf03d4f9
PB		 963 else if (is_pae_paging(vcpu) &&
964 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 965 return 1;
a03490ed 966
ade61e28 967 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 968 vcpu->arch.cr3 = cr3;
aff48baa 969 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 970
0f12244f
GN		 971 return 0;
972}
2d3ad1f4 973EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 974
eea1cff9 975int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 976{
0f12244f
GN		 977 if (cr8 & CR8_RESERVED_BITS)
978 return 1;
35754c98 979 if (lapic_in_kernel(vcpu))
a03490ed
CO		 980 kvm_lapic_set_tpr(vcpu, cr8);
981 else
ad312c7c 982 vcpu->arch.cr8 = cr8;
0f12244f
GN		 983 return 0;
984}
2d3ad1f4 985EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 986
2d3ad1f4 987unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 988{
35754c98 989 if (lapic_in_kernel(vcpu))
a03490ed
CO		 990 return kvm_lapic_get_cr8(vcpu);
991 else
ad312c7c 992 return vcpu->arch.cr8;
a03490ed 993}
2d3ad1f4 994EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 995
ae561ede
NA		 996static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
997{
998 int i;
999
1000 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1001 for (i = 0; i < KVM_NR_DB_REGS; i++)
1002 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1003 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1004 }
1005}
1006
73aaf249
JK		 1007static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1008{
1009 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1010 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1011}
1012
c8639010
JK		 1013static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1014{
1015 unsigned long dr7;
1016
1017 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1018 dr7 = vcpu->arch.guest_debug_dr7;
1019 else
1020 dr7 = vcpu->arch.dr7;
1021 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1022 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1023 if (dr7 & DR7_BP_EN_MASK)
1024 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1025}
1026
6f43ed01
NA		 1027static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1028{
1029 u64 fixed = DR6_FIXED_1;
1030
d6321d49 1031 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1032 fixed |= DR6_RTM;
1033 return fixed;
1034}
1035
338dbc97 1036static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1037{
1038 switch (dr) {
1039 case 0 ... 3:
1040 vcpu->arch.db[dr] = val;
1041 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1042 vcpu->arch.eff_db[dr] = val;
1043 break;
1044 case 4:
020df079
GN		 1045 /* fall through */
1046 case 6:
338dbc97
GN		 1047 if (val & 0xffffffff00000000ULL)
1048 return -1; /* #GP */
6f43ed01 1049 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1050 kvm_update_dr6(vcpu);
020df079
GN		 1051 break;
1052 case 5:
020df079
GN		 1053 /* fall through */
1054 default: /* 7 */
338dbc97
GN		 1055 if (val & 0xffffffff00000000ULL)
1056 return -1; /* #GP */
020df079 1057 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1058 kvm_update_dr7(vcpu);
020df079
GN		 1059 break;
1060 }
1061
1062 return 0;
1063}
338dbc97
GN		 1064
1065int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1066{
16f8a6f9 1067 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1068 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1069 return 1;
1070 }
1071 return 0;
338dbc97 1072}
020df079
GN		 1073EXPORT_SYMBOL_GPL(kvm_set_dr);
1074
16f8a6f9 1075int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1076{
1077 switch (dr) {
1078 case 0 ... 3:
1079 *val = vcpu->arch.db[dr];
1080 break;
1081 case 4:
020df079
GN		 1082 /* fall through */
1083 case 6:
73aaf249
JK		 1084 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1085 *val = vcpu->arch.dr6;
1086 else
1087 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1088 break;
1089 case 5:
020df079
GN		 1090 /* fall through */
1091 default: /* 7 */
1092 *val = vcpu->arch.dr7;
1093 break;
1094 }
338dbc97
GN		 1095 return 0;
1096}
020df079
GN		 1097EXPORT_SYMBOL_GPL(kvm_get_dr);
1098
022cd0e8
AK		 1099bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1100{
de3cd117 1101 u32 ecx = kvm_rcx_read(vcpu);
022cd0e8
AK		 1102 u64 data;
1103 int err;
1104
c6702c9d 1105 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1106 if (err)
1107 return err;
de3cd117
SC		 1108 kvm_rax_write(vcpu, (u32)data);
1109 kvm_rdx_write(vcpu, data >> 32);
022cd0e8
AK		 1110 return err;
1111}
1112EXPORT_SYMBOL_GPL(kvm_rdpmc);
1113
043405e1
CO		 1114/*
1115 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1116 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1117 *
1118 * This list is modified at module load time to reflect the
e3267cbb 1119 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1120 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1121 * may depend on host virtualization features rather than host cpu features.
043405e1 1122 */
e3267cbb 1123
043405e1
CO		 1124static u32 msrs_to_save[] = {
1125 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1126 MSR_STAR,
043405e1
CO		 1127#ifdef CONFIG_X86_64
1128 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1129#endif
b3897a49 1130 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1131 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1132 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1133 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1134 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1135 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1136 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1137 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1138 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
043405e1
CO		 1139};
1140
1141static unsigned num_msrs_to_save;
1142
62ef68bb
PB		 1143static u32 emulated_msrs[] = {
1144 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1145 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1146 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1147 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1148 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1149 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1150 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1151 HV_X64_MSR_RESET,
11c4b1ca 1152 HV_X64_MSR_VP_INDEX,
9eec50b8 1153 HV_X64_MSR_VP_RUNTIME,
5c919412 1154 HV_X64_MSR_SCONTROL,
1f4b34f8 1155 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1156 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1157 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1158 HV_X64_MSR_TSC_EMULATION_STATUS,
1159
1160 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1161 MSR_KVM_PV_EOI_EN,
1162
ba904635 1163 MSR_IA32_TSC_ADJUST,
a3e06bbe 1164 MSR_IA32_TSCDEADLINE,
2bdb76c0 1165 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1166 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1167 MSR_IA32_MCG_STATUS,
1168 MSR_IA32_MCG_CTL,
c45dcc71 1169 MSR_IA32_MCG_EXT_CTL,
64d60670 1170 MSR_IA32_SMBASE,
52797bf9 1171 MSR_SMI_COUNT,
db2336a8
KH		 1172 MSR_PLATFORM_INFO,
1173 MSR_MISC_FEATURES_ENABLES,
bc226f07 1174 MSR_AMD64_VIRT_SPEC_CTRL,
6c6a2ab9 1175 MSR_IA32_POWER_CTL,
191c8137 1176
95c5c7c7
PB		 1177 /*
1178 * The following list leaves out MSRs whose values are determined
1179 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1180 * We always support the "true" VMX control MSRs, even if the host
1181 * processor does not, so I am putting these registers here rather
1182 * than in msrs_to_save.
1183 */
1184 MSR_IA32_VMX_BASIC,
1185 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1186 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1187 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1188 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1189 MSR_IA32_VMX_MISC,
1190 MSR_IA32_VMX_CR0_FIXED0,
1191 MSR_IA32_VMX_CR4_FIXED0,
1192 MSR_IA32_VMX_VMCS_ENUM,
1193 MSR_IA32_VMX_PROCBASED_CTLS2,
1194 MSR_IA32_VMX_EPT_VPID_CAP,
1195 MSR_IA32_VMX_VMFUNC,
1196
191c8137 1197 MSR_K7_HWCR,
2d5ba19b 1198 MSR_KVM_POLL_CONTROL,
043405e1
CO		 1199};
1200
62ef68bb
PB		 1201static unsigned num_emulated_msrs;
1202
801e459a
TL		 1203/*
1204 * List of msr numbers which are used to expose MSR-based features that
1205 * can be used by a hypervisor to validate requested CPU features.
1206 */
1207static u32 msr_based_features[] = {
1389309c
PB		 1208 MSR_IA32_VMX_BASIC,
1209 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1210 MSR_IA32_VMX_PINBASED_CTLS,
1211 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1212 MSR_IA32_VMX_PROCBASED_CTLS,
1213 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1214 MSR_IA32_VMX_EXIT_CTLS,
1215 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1216 MSR_IA32_VMX_ENTRY_CTLS,
1217 MSR_IA32_VMX_MISC,
1218 MSR_IA32_VMX_CR0_FIXED0,
1219 MSR_IA32_VMX_CR0_FIXED1,
1220 MSR_IA32_VMX_CR4_FIXED0,
1221 MSR_IA32_VMX_CR4_FIXED1,
1222 MSR_IA32_VMX_VMCS_ENUM,
1223 MSR_IA32_VMX_PROCBASED_CTLS2,
1224 MSR_IA32_VMX_EPT_VPID_CAP,
1225 MSR_IA32_VMX_VMFUNC,
1226
d1d93fa9 1227 MSR_F10H_DECFG,
518e7b94 1228 MSR_IA32_UCODE_REV,
cd283252 1229 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1230};
1231
1232static unsigned int num_msr_based_features;
1233
4d22c17c 1234static u64 kvm_get_arch_capabilities(void)
5b76a3cf 1235{
4d22c17c 1236 u64 data = 0;
5b76a3cf 1237
4d22c17c
XL		 1238 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1239 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
5b76a3cf
PB		 1240
1241 /*
1242 * If we're doing cache flushes (either "always" or "cond")
1243 * we will do one whenever the guest does a vmlaunch/vmresume.
1244 * If an outer hypervisor is doing the cache flush for us
1245 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1246 * capability to the guest too, and if EPT is disabled we're not
1247 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1248 * require a nested hypervisor to do a flush of its own.
1249 */
1250 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1251 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1252
1253 return data;
1254}
5b76a3cf 1255
66421c1e
WL		 1256static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1257{
1258 switch (msr->index) {
cd283252 1259 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1260 msr->data = kvm_get_arch_capabilities();
1261 break;
1262 case MSR_IA32_UCODE_REV:
cd283252 1263 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1264 break;
66421c1e
WL		 1265 default:
1266 if (kvm_x86_ops->get_msr_feature(msr))
1267 return 1;
1268 }
1269 return 0;
1270}
1271
801e459a
TL		 1272static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1273{
1274 struct kvm_msr_entry msr;
66421c1e 1275 int r;
801e459a
TL		 1276
1277 msr.index = index;
66421c1e
WL		 1278 r = kvm_get_msr_feature(&msr);
1279 if (r)
1280 return r;
801e459a
TL		 1281
1282 *data = msr.data;
1283
1284 return 0;
1285}
1286
11988499 1287static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1288{
1b4d56b8 1289 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
11988499 1290 return false;
1b2fd70c 1291
1b4d56b8 1292 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
11988499 1293 return false;
d8017474 1294
0a629563
SC		 1295 if (efer & (EFER_LME | EFER_LMA) &&
1296 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1297 return false;
1298
1299 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1300 return false;
d8017474 1301
384bb783 1302 return true;
11988499
SC		 1303
1304}
1305bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1306{
1307 if (efer & efer_reserved_bits)
1308 return false;
1309
1310 return __kvm_valid_efer(vcpu, efer);
384bb783
JK		 1311}
1312EXPORT_SYMBOL_GPL(kvm_valid_efer);
1313
11988499 1314static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
384bb783
JK		 1315{
1316 u64 old_efer = vcpu->arch.efer;
11988499 1317 u64 efer = msr_info->data;
384bb783 1318
11988499 1319 if (efer & efer_reserved_bits)
66f61c92 1320 return 1;
384bb783 1321
11988499
SC		 1322 if (!msr_info->host_initiated) {
1323 if (!__kvm_valid_efer(vcpu, efer))
1324 return 1;
1325
1326 if (is_paging(vcpu) &&
1327 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1328 return 1;
1329 }
384bb783 1330
15c4a640 1331 efer &= ~EFER_LMA;
f6801dff 1332 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1333
a3d204e2
SY		 1334 kvm_x86_ops->set_efer(vcpu, efer);
1335
aad82703
SY		 1336 /* Update reserved bits */
1337 if ((efer ^ old_efer) & EFER_NX)
1338 kvm_mmu_reset_context(vcpu);
1339
b69e8cae 1340 return 0;
15c4a640
CO		 1341}
1342
f2b4b7dd
JR		 1343void kvm_enable_efer_bits(u64 mask)
1344{
1345 efer_reserved_bits &= ~mask;
1346}
1347EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1348
15c4a640
CO		 1349/*
1350 * Writes msr value into into the appropriate "register".
1351 * Returns 0 on success, non-0 otherwise.
1352 * Assumes vcpu_load() was already called.
1353 */
8fe8ab46 1354int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1355{
854e8bb1
NA		 1356 switch (msr->index) {
1357 case MSR_FS_BASE:
1358 case MSR_GS_BASE:
1359 case MSR_KERNEL_GS_BASE:
1360 case MSR_CSTAR:
1361 case MSR_LSTAR:
fd8cb433 1362 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1363 return 1;
1364 break;
1365 case MSR_IA32_SYSENTER_EIP:
1366 case MSR_IA32_SYSENTER_ESP:
1367 /*
1368 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1369 * non-canonical address is written on Intel but not on
1370 * AMD (which ignores the top 32-bits, because it does
1371 * not implement 64-bit SYSENTER).
1372 *
1373 * 64-bit code should hence be able to write a non-canonical
1374 * value on AMD. Making the address canonical ensures that
1375 * vmentry does not fail on Intel after writing a non-canonical
1376 * value, and that something deterministic happens if the guest
1377 * invokes 64-bit SYSENTER.
1378 */
fd8cb433 1379 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1380 }
8fe8ab46 1381 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1382}
854e8bb1 1383EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1384
313a3dc7
CO		 1385/*
1386 * Adapt set_msr() to msr_io()'s calling convention
1387 */
609e36d3
PB		 1388static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1389{
1390 struct msr_data msr;
1391 int r;
1392
1393 msr.index = index;
1394 msr.host_initiated = true;
1395 r = kvm_get_msr(vcpu, &msr);
1396 if (r)
1397 return r;
1398
1399 *data = msr.data;
1400 return 0;
1401}
1402
313a3dc7
CO		 1403static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1404{
8fe8ab46
WA		 1405 struct msr_data msr;
1406
1407 msr.data = *data;
1408 msr.index = index;
1409 msr.host_initiated = true;
1410 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1411}
1412
16e8d74d
MT		 1413#ifdef CONFIG_X86_64
1414struct pvclock_gtod_data {
1415 seqcount_t seq;
1416
1417 struct { /* extract of a clocksource struct */
1418 int vclock_mode;
a5a1d1c2
TG		 1419 u64 cycle_last;
1420 u64 mask;
16e8d74d
MT		 1421 u32 mult;
1422 u32 shift;
1423 } clock;
1424
cbcf2dd3
TG		 1425 u64 boot_ns;
1426 u64 nsec_base;
55dd00a7 1427 u64 wall_time_sec;
16e8d74d
MT		 1428};
1429
1430static struct pvclock_gtod_data pvclock_gtod_data;
1431
1432static void update_pvclock_gtod(struct timekeeper *tk)
1433{
1434 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1435 u64 boot_ns;
1436
876e7881 1437 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1438
1439 write_seqcount_begin(&vdata->seq);
1440
1441 /* copy pvclock gtod data */
876e7881
PZ		 1442 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1443 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1444 vdata->clock.mask = tk->tkr_mono.mask;
1445 vdata->clock.mult = tk->tkr_mono.mult;
1446 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1447
cbcf2dd3 1448 vdata->boot_ns = boot_ns;
876e7881 1449 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1450
55dd00a7
MT		 1451 vdata->wall_time_sec = tk->xtime_sec;
1452
16e8d74d
MT		 1453 write_seqcount_end(&vdata->seq);
1454}
1455#endif
1456
bab5bb39
NK		 1457void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1458{
bab5bb39 1459 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
4d151bf3 1460 kvm_vcpu_kick(vcpu);
bab5bb39 1461}
16e8d74d 1462
18068523
GOC		 1463static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1464{
9ed3c444
AK		 1465 int version;
1466 int r;
50d0a0f9 1467 struct pvclock_wall_clock wc;
87aeb54f 1468 struct timespec64 boot;
18068523
GOC		 1469
1470 if (!wall_clock)
1471 return;
1472
9ed3c444
AK		 1473 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1474 if (r)
1475 return;
1476
1477 if (version & 1)
1478 ++version; /* first time write, random junk */
1479
1480 ++version;
18068523 1481
1dab1345
NK		 1482 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1483 return;
18068523 1484
50d0a0f9
GH		 1485 /*
1486 * The guest calculates current wall clock time by adding
34c238a1 1487 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1488 * wall clock specified here. guest system time equals host
1489 * system time for us, thus we must fill in host boot time here.
1490 */
87aeb54f 1491 getboottime64(&boot);
50d0a0f9 1492
4b648665 1493 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1494 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1495 boot = timespec64_sub(boot, ts);
4b648665 1496 }
87aeb54f 1497 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1498 wc.nsec = boot.tv_nsec;
1499 wc.version = version;
18068523
GOC		 1500
1501 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1502
1503 version++;
1504 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1505}
1506
50d0a0f9
GH		 1507static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1508{
b51012de
PB		 1509 do_shl32_div32(dividend, divisor);
1510 return dividend;
50d0a0f9
GH		 1511}
1512
3ae13faa 1513static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1514 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1515{
5f4e3f88 1516 uint64_t scaled64;
50d0a0f9
GH		 1517 int32_t shift = 0;
1518 uint64_t tps64;
1519 uint32_t tps32;
1520
3ae13faa
PB		 1521 tps64 = base_hz;
1522 scaled64 = scaled_hz;
50933623 1523 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1524 tps64 >>= 1;
1525 shift--;
1526 }
1527
1528 tps32 = (uint32_t)tps64;
50933623
JK		 1529 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1530 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1531 scaled64 >>= 1;
1532 else
1533 tps32 <<= 1;
50d0a0f9
GH		 1534 shift++;
1535 }
1536
5f4e3f88
ZA		 1537 *pshift = shift;
1538 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9
GH		 1539}
1540
d828199e 1541#ifdef CONFIG_X86_64
16e8d74d 1542static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1543#endif
16e8d74d 1544
c8076604 1545static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1546static unsigned long max_tsc_khz;
c8076604 1547
cc578287 1548static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1549{
cc578287
ZA		 1550 u64 v = (u64)khz * (1000000 + ppm);
1551 do_div(v, 1000000);
1552 return v;
1e993611
JR		 1553}
1554
381d585c
HZ		 1555static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1556{
1557 u64 ratio;
1558
1559 /* Guest TSC same frequency as host TSC? */
1560 if (!scale) {
1561 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1562 return 0;
1563 }
1564
1565 /* TSC scaling supported? */
1566 if (!kvm_has_tsc_control) {
1567 if (user_tsc_khz > tsc_khz) {
1568 vcpu->arch.tsc_catchup = 1;
1569 vcpu->arch.tsc_always_catchup = 1;
1570 return 0;
1571 } else {
3f16a5c3 1572 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
381d585c
HZ		 1573 return -1;
1574 }
1575 }
1576
1577 /* TSC scaling required - calculate ratio */
1578 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1579 user_tsc_khz, tsc_khz);
1580
1581 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
3f16a5c3
PB		 1582 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1583 user_tsc_khz);
381d585c
HZ		 1584 return -1;
1585 }
1586
1587 vcpu->arch.tsc_scaling_ratio = ratio;
1588 return 0;
1589}
1590
4941b8cb 1591static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1592{
cc578287
ZA		 1593 u32 thresh_lo, thresh_hi;
1594 int use_scaling = 0;
217fc9cf 1595
03ba32ca 1596 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1597 if (user_tsc_khz == 0) {
ad721883
HZ		 1598 /* set tsc_scaling_ratio to a safe value */
1599 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1600 return -1;
ad721883 1601 }
03ba32ca 1602
c285545f 1603 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1604 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1605 &vcpu->arch.virtual_tsc_shift,
1606 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1607 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1608
1609 /*
1610 * Compute the variation in TSC rate which is acceptable
1611 * within the range of tolerance and decide if the
1612 * rate being applied is within that bounds of the hardware
1613 * rate. If so, no scaling or compensation need be done.
1614 */
1615 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1616 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1617 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1618 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1619 use_scaling = 1;
1620 }
4941b8cb 1621 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1622}
1623
1624static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1625{
e26101b1 1626 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1627 vcpu->arch.virtual_tsc_mult,
1628 vcpu->arch.virtual_tsc_shift);
e26101b1 1629 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1630 return tsc;
1631}
1632
b0c39dc6
VK		 1633static inline int gtod_is_based_on_tsc(int mode)
1634{
1635 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1636}
1637
69b0049a 1638static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1639{
1640#ifdef CONFIG_X86_64
1641 bool vcpus_matched;
b48aa97e
MT		 1642 struct kvm_arch *ka = &vcpu->kvm->arch;
1643 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1644
1645 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1646 atomic_read(&vcpu->kvm->online_vcpus));
1647
7f187922
MT		 1648 /*
1649 * Once the masterclock is enabled, always perform request in
1650 * order to update it.
1651 *
1652 * In order to enable masterclock, the host clocksource must be TSC
1653 * and the vcpus need to have matched TSCs. When that happens,
1654 * perform request to enable masterclock.
1655 */
1656 if (ka->use_master_clock ||
b0c39dc6 1657 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1658 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1659
1660 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1661 atomic_read(&vcpu->kvm->online_vcpus),
1662 ka->use_master_clock, gtod->clock.vclock_mode);
1663#endif
1664}
1665
ba904635
WA		 1666static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1667{
e79f245d 1668 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1669 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1670}
1671
35181e86
HZ		 1672/*
1673 * Multiply tsc by a fixed point number represented by ratio.
1674 *
1675 * The most significant 64-N bits (mult) of ratio represent the
1676 * integral part of the fixed point number; the remaining N bits
1677 * (frac) represent the fractional part, ie. ratio represents a fixed
1678 * point number (mult + frac * 2^(-N)).
1679 *
1680 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1681 */
1682static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1683{
1684 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1685}
1686
1687u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1688{
1689 u64 _tsc = tsc;
1690 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1691
1692 if (ratio != kvm_default_tsc_scaling_ratio)
1693 _tsc = __scale_tsc(ratio, tsc);
1694
1695 return _tsc;
1696}
1697EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1698
07c1419a
HZ		 1699static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1700{
1701 u64 tsc;
1702
1703 tsc = kvm_scale_tsc(vcpu, rdtsc());
1704
1705 return target_tsc - tsc;
1706}
1707
4ba76538
HZ		 1708u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1709{
e79f245d
KA		 1710 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1711
1712 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1713}
1714EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1715
a545ab6a
LC		 1716static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1717{
326e7425 1718 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1719}
1720
b0c39dc6
VK		 1721static inline bool kvm_check_tsc_unstable(void)
1722{
1723#ifdef CONFIG_X86_64
1724 /*
1725 * TSC is marked unstable when we're running on Hyper-V,
1726 * 'TSC page' clocksource is good.
1727 */
1728 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1729 return false;
1730#endif
1731 return check_tsc_unstable();
1732}
1733
8fe8ab46 1734void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1735{
1736 struct kvm *kvm = vcpu->kvm;
f38e098f 1737 u64 offset, ns, elapsed;
99e3e30a 1738 unsigned long flags;
b48aa97e 1739 bool matched;
0d3da0d2 1740 bool already_matched;
8fe8ab46 1741 u64 data = msr->data;
c5e8ec8e 1742 bool synchronizing = false;
99e3e30a 1743
038f8c11 1744 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1745 offset = kvm_compute_tsc_offset(vcpu, data);
9285ec4c 1746 ns = ktime_get_boottime_ns();
f38e098f 1747 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1748
03ba32ca 1749 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1750 if (data == 0 && msr->host_initiated) {
1751 /*
1752 * detection of vcpu initialization -- need to sync
1753 * with other vCPUs. This particularly helps to keep
1754 * kvm_clock stable after CPU hotplug
1755 */
1756 synchronizing = true;
1757 } else {
1758 u64 tsc_exp = kvm->arch.last_tsc_write +
1759 nsec_to_cycles(vcpu, elapsed);
1760 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1761 /*
1762 * Special case: TSC write with a small delta (1 second)
1763 * of virtual cycle time against real time is
1764 * interpreted as an attempt to synchronize the CPU.
1765 */
1766 synchronizing = data < tsc_exp + tsc_hz &&
1767 data + tsc_hz > tsc_exp;
1768 }
c5e8ec8e 1769 }
f38e098f
ZA		 1770
1771 /*
5d3cb0f6
ZA		 1772 * For a reliable TSC, we can match TSC offsets, and for an unstable
1773 * TSC, we add elapsed time in this computation. We could let the
1774 * compensation code attempt to catch up if we fall behind, but
1775 * it's better to try to match offsets from the beginning.
1776 */
c5e8ec8e 1777 if (synchronizing &&
5d3cb0f6 1778 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1779 if (!kvm_check_tsc_unstable()) {
e26101b1 1780 offset = kvm->arch.cur_tsc_offset;
f38e098f 1781 } else {
857e4099 1782 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1783 data += delta;
07c1419a 1784 offset = kvm_compute_tsc_offset(vcpu, data);
f38e098f 1785 }
b48aa97e 1786 matched = true;
0d3da0d2 1787 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1788 } else {
1789 /*
1790 * We split periods of matched TSC writes into generations.
1791 * For each generation, we track the original measured
1792 * nanosecond time, offset, and write, so if TSCs are in
1793 * sync, we can match exact offset, and if not, we can match
4a969980 1794 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1795 *
1796 * These values are tracked in kvm->arch.cur_xxx variables.
1797 */
1798 kvm->arch.cur_tsc_generation++;
1799 kvm->arch.cur_tsc_nsec = ns;
1800 kvm->arch.cur_tsc_write = data;
1801 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1802 matched = false;
f38e098f 1803 }
e26101b1
ZA		 1804
1805 /*
1806 * We also track th most recent recorded KHZ, write and time to
1807 * allow the matching interval to be extended at each write.
1808 */
f38e098f
ZA		 1809 kvm->arch.last_tsc_nsec = ns;
1810 kvm->arch.last_tsc_write = data;
5d3cb0f6 1811 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1812
b183aa58 1813 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1814
1815 /* Keep track of which generation this VCPU has synchronized to */
1816 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1817 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1818 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1819
d6321d49 1820 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1821 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1822
a545ab6a 1823 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1824 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1825
1826 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1827 if (!matched) {
b48aa97e 1828 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1829 } else if (!already_matched) {
1830 kvm->arch.nr_vcpus_matched_tsc++;
1831 }
b48aa97e
MT		 1832
1833 kvm_track_tsc_matching(vcpu);
1834 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1835}
e26101b1 1836
99e3e30a
ZA		 1837EXPORT_SYMBOL_GPL(kvm_write_tsc);
1838
58ea6767
HZ		 1839static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1840 s64 adjustment)
1841{
326e7425
LS		 1842 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1843 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1844}
1845
1846static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1847{
1848 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1849 WARN_ON(adjustment < 0);
1850 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1851 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1852}
1853
d828199e
MT		 1854#ifdef CONFIG_X86_64
1855
a5a1d1c2 1856static u64 read_tsc(void)
d828199e 1857{
a5a1d1c2 1858 u64 ret = (u64)rdtsc_ordered();
03b9730b 1859 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1860
1861 if (likely(ret >= last))
1862 return ret;
1863
1864 /*
1865 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1866 * predictable (it's just a function of time and the likely is
d828199e
MT		 1867 * very likely) and there's a data dependence, so force GCC
1868 * to generate a branch instead. I don't barrier() because
1869 * we don't actually need a barrier, and if this function
1870 * ever gets inlined it will generate worse code.
1871 */
1872 asm volatile ("");
1873 return last;
1874}
1875
b0c39dc6 1876static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1877{
1878 long v;
1879 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1880 u64 tsc_pg_val;
1881
1882 switch (gtod->clock.vclock_mode) {
1883 case VCLOCK_HVCLOCK:
1884 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1885 tsc_timestamp);
1886 if (tsc_pg_val != U64_MAX) {
1887 /* TSC page valid */
1888 *mode = VCLOCK_HVCLOCK;
1889 v = (tsc_pg_val - gtod->clock.cycle_last) &
1890 gtod->clock.mask;
1891 } else {
1892 /* TSC page invalid */
1893 *mode = VCLOCK_NONE;
1894 }
1895 break;
1896 case VCLOCK_TSC:
1897 *mode = VCLOCK_TSC;
1898 *tsc_timestamp = read_tsc();
1899 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1900 gtod->clock.mask;
1901 break;
1902 default:
1903 *mode = VCLOCK_NONE;
1904 }
d828199e 1905
b0c39dc6
VK		 1906 if (*mode == VCLOCK_NONE)
1907 *tsc_timestamp = v = 0;
d828199e 1908
d828199e
MT		 1909 return v * gtod->clock.mult;
1910}
1911
b0c39dc6 1912static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1913{
cbcf2dd3 1914 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1915 unsigned long seq;
d828199e 1916 int mode;
cbcf2dd3 1917 u64 ns;
d828199e 1918
d828199e
MT		 1919 do {
1920 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1921 ns = gtod->nsec_base;
b0c39dc6 1922 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1923 ns >>= gtod->clock.shift;
cbcf2dd3 1924 ns += gtod->boot_ns;
d828199e 1925 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1926 *t = ns;
d828199e
MT		 1927
1928 return mode;
1929}
1930
899a31f5 1931static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1932{
1933 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1934 unsigned long seq;
1935 int mode;
1936 u64 ns;
1937
1938 do {
1939 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1940 ts->tv_sec = gtod->wall_time_sec;
1941 ns = gtod->nsec_base;
b0c39dc6 1942 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1943 ns >>= gtod->clock.shift;
1944 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1945
1946 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1947 ts->tv_nsec = ns;
1948
1949 return mode;
1950}
1951
b0c39dc6
VK		 1952/* returns true if host is using TSC based clocksource */
1953static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1954{
d828199e 1955 /* checked again under seqlock below */
b0c39dc6 1956 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1957 return false;
1958
b0c39dc6
VK		 1959 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1960 tsc_timestamp));
d828199e 1961}
55dd00a7 1962
b0c39dc6 1963/* returns true if host is using TSC based clocksource */
899a31f5 1964static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1965 u64 *tsc_timestamp)
55dd00a7
MT		 1966{
1967 /* checked again under seqlock below */
b0c39dc6 1968 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1969 return false;
1970
b0c39dc6 1971 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1972}
d828199e
MT		 1973#endif
1974
1975/*
1976 *
b48aa97e
MT		 1977 * Assuming a stable TSC across physical CPUS, and a stable TSC
1978 * across virtual CPUs, the following condition is possible.
1979 * Each numbered line represents an event visible to both
d828199e
MT		 1980 * CPUs at the next numbered event.
1981 *
1982 * "timespecX" represents host monotonic time. "tscX" represents
1983 * RDTSC value.
1984 *
1985 * VCPU0 on CPU0 | VCPU1 on CPU1
1986 *
1987 * 1. read timespec0,tsc0
1988 * 2. | timespec1 = timespec0 + N
1989 * | tsc1 = tsc0 + M
1990 * 3. transition to guest | transition to guest
1991 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1992 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1993 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1994 *
1995 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1996 *
1997 * - ret0 < ret1
1998 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1999 * ...
2000 * - 0 < N - M => M < N
2001 *
2002 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2003 * always the case (the difference between two distinct xtime instances
2004 * might be smaller then the difference between corresponding TSC reads,
2005 * when updating guest vcpus pvclock areas).
2006 *
2007 * To avoid that problem, do not allow visibility of distinct
2008 * system_timestamp/tsc_timestamp values simultaneously: use a master
2009 * copy of host monotonic time values. Update that master copy
2010 * in lockstep.
2011 *
b48aa97e 2012 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 2013 *
2014 */
2015
2016static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2017{
2018#ifdef CONFIG_X86_64
2019 struct kvm_arch *ka = &kvm->arch;
2020 int vclock_mode;
b48aa97e
MT		 2021 bool host_tsc_clocksource, vcpus_matched;
2022
2023 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2024 atomic_read(&kvm->online_vcpus));
d828199e
MT		 2025
2026 /*
2027 * If the host uses TSC clock, then passthrough TSC as stable
2028 * to the guest.
2029 */
b48aa97e 2030 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 2031 &ka->master_kernel_ns,
2032 &ka->master_cycle_now);
2033
16a96021 2034 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2035 && !ka->backwards_tsc_observed
54750f2c 2036 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2037
d828199e
MT		 2038 if (ka->use_master_clock)
2039 atomic_set(&kvm_guest_has_master_clock, 1);
2040
2041 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2042 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2043 vcpus_matched);
d828199e
MT		 2044#endif
2045}
2046
2860c4b1
PB		 2047void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2048{
2049 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2050}
2051
2e762ff7
MT		 2052static void kvm_gen_update_masterclock(struct kvm *kvm)
2053{
2054#ifdef CONFIG_X86_64
2055 int i;
2056 struct kvm_vcpu *vcpu;
2057 struct kvm_arch *ka = &kvm->arch;
2058
2059 spin_lock(&ka->pvclock_gtod_sync_lock);
2060 kvm_make_mclock_inprogress_request(kvm);
2061 /* no guest entries from this point */
2062 pvclock_update_vm_gtod_copy(kvm);
2063
2064 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2065 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2066
2067 /* guest entries allowed */
2068 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2069 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2070
2071 spin_unlock(&ka->pvclock_gtod_sync_lock);
2072#endif
2073}
2074
e891a32e 2075u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2076{
108b249c 2077 struct kvm_arch *ka = &kvm->arch;
8b953440 2078 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2079 u64 ret;
108b249c 2080
8b953440
PB		 2081 spin_lock(&ka->pvclock_gtod_sync_lock);
2082 if (!ka->use_master_clock) {
2083 spin_unlock(&ka->pvclock_gtod_sync_lock);
9285ec4c 2084 return ktime_get_boottime_ns() + ka->kvmclock_offset;
108b249c
PB		 2085 }
2086
8b953440
PB		 2087 hv_clock.tsc_timestamp = ka->master_cycle_now;
2088 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2089 spin_unlock(&ka->pvclock_gtod_sync_lock);
2090
e2c2206a
WL		 2091 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2092 get_cpu();
2093
e70b57a6
WL		 2094 if (__this_cpu_read(cpu_tsc_khz)) {
2095 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2096 &hv_clock.tsc_shift,
2097 &hv_clock.tsc_to_system_mul);
2098 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2099 } else
9285ec4c 2100 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2101
2102 put_cpu();
2103
2104 return ret;
108b249c
PB		 2105}
2106
0d6dd2ff
PB		 2107static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2108{
2109 struct kvm_vcpu_arch *vcpu = &v->arch;
2110 struct pvclock_vcpu_time_info guest_hv_clock;
2111
4e335d9e 2112 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2113 &guest_hv_clock, sizeof(guest_hv_clock))))
2114 return;
2115
2116 /* This VCPU is paused, but it's legal for a guest to read another
2117 * VCPU's kvmclock, so we really have to follow the specification where
2118 * it says that version is odd if data is being modified, and even after
2119 * it is consistent.
2120 *
2121 * Version field updates must be kept separate. This is because
2122 * kvm_write_guest_cached might use a "rep movs" instruction, and
2123 * writes within a string instruction are weakly ordered. So there
2124 * are three writes overall.
2125 *
2126 * As a small optimization, only write the version field in the first
2127 * and third write. The vcpu->pv_time cache is still valid, because the
2128 * version field is the first in the struct.
2129 */
2130 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2131
51c4b8bb
LA		 2132 if (guest_hv_clock.version & 1)
2133 ++guest_hv_clock.version; /* first time write, random junk */
2134
0d6dd2ff 2135 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2136 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2137 &vcpu->hv_clock,
2138 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2139
2140 smp_wmb();
2141
2142 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2143 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2144
2145 if (vcpu->pvclock_set_guest_stopped_request) {
2146 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2147 vcpu->pvclock_set_guest_stopped_request = false;
2148 }
2149
2150 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2151
4e335d9e
PB		 2152 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2153 &vcpu->hv_clock,
2154 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2155
2156 smp_wmb();
2157
2158 vcpu->hv_clock.version++;
4e335d9e
PB		 2159 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2160 &vcpu->hv_clock,
2161 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2162}
2163
34c238a1 2164static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2165{
78db6a50 2166 unsigned long flags, tgt_tsc_khz;
18068523 2167 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2168 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2169 s64 kernel_ns;
d828199e 2170 u64 tsc_timestamp, host_tsc;
51d59c6b 2171 u8 pvclock_flags;
d828199e
MT		 2172 bool use_master_clock;
2173
2174 kernel_ns = 0;
2175 host_tsc = 0;
18068523 2176
d828199e
MT		 2177 /*
2178 * If the host uses TSC clock, then passthrough TSC as stable
2179 * to the guest.
2180 */
2181 spin_lock(&ka->pvclock_gtod_sync_lock);
2182 use_master_clock = ka->use_master_clock;
2183 if (use_master_clock) {
2184 host_tsc = ka->master_cycle_now;
2185 kernel_ns = ka->master_kernel_ns;
2186 }
2187 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2188
2189 /* Keep irq disabled to prevent changes to the clock */
2190 local_irq_save(flags);
78db6a50
PB		 2191 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2192 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2193 local_irq_restore(flags);
2194 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2195 return 1;
2196 }
d828199e 2197 if (!use_master_clock) {
4ea1636b 2198 host_tsc = rdtsc();
9285ec4c 2199 kernel_ns = ktime_get_boottime_ns();
d828199e
MT		 2200 }
2201
4ba76538 2202 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2203
c285545f
ZA		 2204 /*
2205 * We may have to catch up the TSC to match elapsed wall clock
2206 * time for two reasons, even if kvmclock is used.
2207 * 1) CPU could have been running below the maximum TSC rate
2208 * 2) Broken TSC compensation resets the base at each VCPU
2209 * entry to avoid unknown leaps of TSC even when running
2210 * again on the same CPU. This may cause apparent elapsed
2211 * time to disappear, and the guest to stand still or run
2212 * very slowly.
2213 */
2214 if (vcpu->tsc_catchup) {
2215 u64 tsc = compute_guest_tsc(v, kernel_ns);
2216 if (tsc > tsc_timestamp) {
f1e2b260 2217 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2218 tsc_timestamp = tsc;
2219 }
50d0a0f9
GH		 2220 }
2221
18068523
GOC		 2222 local_irq_restore(flags);
2223
0d6dd2ff 2224 /* With all the info we got, fill in the values */
18068523 2225
78db6a50
PB		 2226 if (kvm_has_tsc_control)
2227 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2228
2229 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2230 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2231 &vcpu->hv_clock.tsc_shift,
2232 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2233 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2234 }
2235
1d5f066e 2236 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2237 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2238 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2239
d828199e 2240 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2241 pvclock_flags = 0;
d828199e
MT		 2242 if (use_master_clock)
2243 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2244
78c0337a
MT		 2245 vcpu->hv_clock.flags = pvclock_flags;
2246
095cf55d
PB		 2247 if (vcpu->pv_time_enabled)
2248 kvm_setup_pvclock_page(v);
2249 if (v == kvm_get_vcpu(v->kvm, 0))
2250 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2251 return 0;
c8076604
GH		 2252}
2253
0061d53d
MT		 2254/*
2255 * kvmclock updates which are isolated to a given vcpu, such as
2256 * vcpu->cpu migration, should not allow system_timestamp from
2257 * the rest of the vcpus to remain static. Otherwise ntp frequency
2258 * correction applies to one vcpu's system_timestamp but not
2259 * the others.
2260 *
2261 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2262 * We need to rate-limit these requests though, as they can
2263 * considerably slow guests that have a large number of vcpus.
2264 * The time for a remote vcpu to update its kvmclock is bound
2265 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2266 */
2267
7e44e449
AJ		 2268#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2269
2270static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2271{
2272 int i;
7e44e449
AJ		 2273 struct delayed_work *dwork = to_delayed_work(work);
2274 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2275 kvmclock_update_work);
2276 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2277 struct kvm_vcpu *vcpu;
2278
2279 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2280 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2281 kvm_vcpu_kick(vcpu);
2282 }
2283}
2284
7e44e449
AJ		 2285static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2286{
2287 struct kvm *kvm = v->kvm;
2288
105b21bb 2289 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2290 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2291 KVMCLOCK_UPDATE_DELAY);
2292}
2293
332967a3
AJ		 2294#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2295
2296static void kvmclock_sync_fn(struct work_struct *work)
2297{
2298 struct delayed_work *dwork = to_delayed_work(work);
2299 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2300 kvmclock_sync_work);
2301 struct kvm *kvm = container_of(ka, struct kvm, arch);
2302
630994b3
MT		 2303 if (!kvmclock_periodic_sync)
2304 return;
2305
332967a3
AJ		 2306 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2307 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2308 KVMCLOCK_SYNC_PERIOD);
2309}
2310
191c8137
BP		 2311/*
2312 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2313 */
2314static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2315{
2316 /* McStatusWrEn enabled? */
2317 if (guest_cpuid_is_amd(vcpu))
2318 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2319
2320 return false;
2321}
2322
9ffd986c 2323static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2324{
890ca9ae
HY		 2325 u64 mcg_cap = vcpu->arch.mcg_cap;
2326 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2327 u32 msr = msr_info->index;
2328 u64 data = msr_info->data;
890ca9ae 2329
15c4a640 2330 switch (msr) {
15c4a640 2331 case MSR_IA32_MCG_STATUS:
890ca9ae 2332 vcpu->arch.mcg_status = data;
15c4a640 2333 break;
c7ac679c 2334 case MSR_IA32_MCG_CTL:
44883f01
PB		 2335 if (!(mcg_cap & MCG_CTL_P) &&
2336 (data || !msr_info->host_initiated))
890ca9ae
HY		 2337 return 1;
2338 if (data != 0 && data != ~(u64)0)
44883f01 2339 return 1;
890ca9ae
HY		 2340 vcpu->arch.mcg_ctl = data;
2341 break;
2342 default:
2343 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2344 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2345 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2346 /* only 0 or all 1s can be written to IA32_MCi_CTL
2347 * some Linux kernels though clear bit 10 in bank 4 to
2348 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2349 * this to avoid an uncatched #GP in the guest
2350 */
890ca9ae 2351 if ((offset & 0x3) == 0 &&
114be429 2352 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2353 return -1;
191c8137
BP		 2354
2355 /* MCi_STATUS */
9ffd986c 2356 if (!msr_info->host_initiated &&
191c8137
BP		 2357 (offset & 0x3) == 1 && data != 0) {
2358 if (!can_set_mci_status(vcpu))
2359 return -1;
2360 }
2361
890ca9ae
HY		 2362 vcpu->arch.mce_banks[offset] = data;
2363 break;
2364 }
2365 return 1;
2366 }
2367 return 0;
2368}
2369
ffde22ac
ES		 2370static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2371{
2372 struct kvm *kvm = vcpu->kvm;
2373 int lm = is_long_mode(vcpu);
2374 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2375 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2376 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2377 : kvm->arch.xen_hvm_config.blob_size_32;
2378 u32 page_num = data & ~PAGE_MASK;
2379 u64 page_addr = data & PAGE_MASK;
2380 u8 *page;
2381 int r;
2382
2383 r = -E2BIG;
2384 if (page_num >= blob_size)
2385 goto out;
2386 r = -ENOMEM;
ff5c2c03
SL		 2387 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2388 if (IS_ERR(page)) {
2389 r = PTR_ERR(page);
ffde22ac 2390 goto out;
ff5c2c03 2391 }
54bf36aa 2392 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2393 goto out_free;
2394 r = 0;
2395out_free:
2396 kfree(page);
2397out:
2398 return r;
2399}
2400
344d9588
GN		 2401static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2402{
2403 gpa_t gpa = data & ~0x3f;
2404
52a5c155
WL		 2405 /* Bits 3:5 are reserved, Should be zero */
2406 if (data & 0x38)
344d9588
GN		 2407 return 1;
2408
2409 vcpu->arch.apf.msr_val = data;
2410
2411 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2412 kvm_clear_async_pf_completion_queue(vcpu);
2413 kvm_async_pf_hash_reset(vcpu);
2414 return 0;
2415 }
2416
4e335d9e 2417 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2418 sizeof(u32)))
344d9588
GN		 2419 return 1;
2420
6adba527 2421 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2422 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2423 kvm_async_pf_wakeup_all(vcpu);
2424 return 0;
2425}
2426
12f9a48f
GC		 2427static void kvmclock_reset(struct kvm_vcpu *vcpu)
2428{
0b79459b 2429 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2430}
2431
f38a7b75
WL		 2432static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2433{
2434 ++vcpu->stat.tlb_flush;
2435 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2436}
2437
c9aaa895
GC		 2438static void record_steal_time(struct kvm_vcpu *vcpu)
2439{
2440 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2441 return;
2442
4e335d9e 2443 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2444 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2445 return;
2446
f38a7b75
WL		 2447 /*
2448 * Doing a TLB flush here, on the guest's behalf, can avoid
2449 * expensive IPIs.
2450 */
2451 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2452 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2453
35f3fae1
WL		 2454 if (vcpu->arch.st.steal.version & 1)
2455 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2456
2457 vcpu->arch.st.steal.version += 1;
2458
4e335d9e 2459 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2460 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2461
2462 smp_wmb();
2463
c54cdf14
LC		 2464 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2465 vcpu->arch.st.last_steal;
2466 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2467
4e335d9e 2468 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2469 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2470
2471 smp_wmb();
2472
2473 vcpu->arch.st.steal.version += 1;
c9aaa895 2474
4e335d9e 2475 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2476 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2477}
2478
8fe8ab46 2479int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2480{
5753785f 2481 bool pr = false;
8fe8ab46
WA		 2482 u32 msr = msr_info->index;
2483 u64 data = msr_info->data;
5753785f 2484
15c4a640 2485 switch (msr) {
2e32b719 2486 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2487 case MSR_IA32_UCODE_WRITE:
2488 case MSR_VM_HSAVE_PA:
2489 case MSR_AMD64_PATCH_LOADER:
2490 case MSR_AMD64_BU_CFG2:
405a353a 2491 case MSR_AMD64_DC_CFG:
0e1b869f 2492 case MSR_F15H_EX_CFG:
2e32b719
BP		 2493 break;
2494
518e7b94
WL		 2495 case MSR_IA32_UCODE_REV:
2496 if (msr_info->host_initiated)
2497 vcpu->arch.microcode_version = data;
2498 break;
0cf9135b
SC		 2499 case MSR_IA32_ARCH_CAPABILITIES:
2500 if (!msr_info->host_initiated)
2501 return 1;
2502 vcpu->arch.arch_capabilities = data;
2503 break;
15c4a640 2504 case MSR_EFER:
11988499 2505 return set_efer(vcpu, msr_info);
8f1589d9
AP		 2506 case MSR_K7_HWCR:
2507 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2508 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2509 data &= ~(u64)0x8; /* ignore TLB cache disable */
191c8137
BP		 2510
2511 /* Handle McStatusWrEn */
2512 if (data == BIT_ULL(18)) {
2513 vcpu->arch.msr_hwcr = data;
2514 } else if (data != 0) {
a737f256
CD		 2515 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2516 data);
8f1589d9
AP		 2517 return 1;
2518 }
15c4a640 2519 break;
f7c6d140
AP		 2520 case MSR_FAM10H_MMIO_CONF_BASE:
2521 if (data != 0) {
a737f256
CD		 2522 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2523 "0x%llx\n", data);
f7c6d140
AP		 2524 return 1;
2525 }
15c4a640 2526 break;
b5e2fec0
AG		 2527 case MSR_IA32_DEBUGCTLMSR:
2528 if (!data) {
2529 /* We support the non-activated case already */
2530 break;
2531 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2532 /* Values other than LBR and BTF are vendor-specific,
2533 thus reserved and should throw a #GP */
2534 return 1;
2535 }
a737f256
CD		 2536 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2537 __func__, data);
b5e2fec0 2538 break;
9ba075a6 2539 case 0x200 ... 0x2ff:
ff53604b 2540 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2541 case MSR_IA32_APICBASE:
58cb628d 2542 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2543 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2544 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2545 case MSR_IA32_TSCDEADLINE:
2546 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2547 break;
ba904635 2548 case MSR_IA32_TSC_ADJUST:
d6321d49 2549 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2550 if (!msr_info->host_initiated) {
d913b904 2551 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2552 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2553 }
2554 vcpu->arch.ia32_tsc_adjust_msr = data;
2555 }
2556 break;
15c4a640 2557 case MSR_IA32_MISC_ENABLE:
511a8556
WL		 2558 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2559 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2560 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2561 return 1;
2562 vcpu->arch.ia32_misc_enable_msr = data;
2563 kvm_update_cpuid(vcpu);
2564 } else {
2565 vcpu->arch.ia32_misc_enable_msr = data;
2566 }
15c4a640 2567 break;
64d60670
PB		 2568 case MSR_IA32_SMBASE:
2569 if (!msr_info->host_initiated)
2570 return 1;
2571 vcpu->arch.smbase = data;
2572 break;
73f624f4
PB		 2573 case MSR_IA32_POWER_CTL:
2574 vcpu->arch.msr_ia32_power_ctl = data;
2575 break;
dd259935
PB		 2576 case MSR_IA32_TSC:
2577 kvm_write_tsc(vcpu, msr_info);
2578 break;
52797bf9
LA		 2579 case MSR_SMI_COUNT:
2580 if (!msr_info->host_initiated)
2581 return 1;
2582 vcpu->arch.smi_count = data;
2583 break;
11c6bffa 2584 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2585 case MSR_KVM_WALL_CLOCK:
2586 vcpu->kvm->arch.wall_clock = data;
2587 kvm_write_wall_clock(vcpu->kvm, data);
2588 break;
11c6bffa 2589 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2590 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2591 struct kvm_arch *ka = &vcpu->kvm->arch;
2592
12f9a48f 2593 kvmclock_reset(vcpu);
18068523 2594
54750f2c
MT		 2595 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2596 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2597
2598 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2599 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2600
2601 ka->boot_vcpu_runs_old_kvmclock = tmp;
2602 }
2603
18068523 2604 vcpu->arch.time = data;
0061d53d 2605 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2606
2607 /* we verify if the enable bit is set... */
2608 if (!(data & 1))
2609 break;
2610
4e335d9e 2611 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2612 &vcpu->arch.pv_time, data & ~1ULL,
2613 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2614 vcpu->arch.pv_time_enabled = false;
2615 else
2616 vcpu->arch.pv_time_enabled = true;
32cad84f 2617
18068523
GOC		 2618 break;
2619 }
344d9588
GN		 2620 case MSR_KVM_ASYNC_PF_EN:
2621 if (kvm_pv_enable_async_pf(vcpu, data))
2622 return 1;
2623 break;
c9aaa895
GC		 2624 case MSR_KVM_STEAL_TIME:
2625
2626 if (unlikely(!sched_info_on()))
2627 return 1;
2628
2629 if (data & KVM_STEAL_RESERVED_MASK)
2630 return 1;
2631
4e335d9e 2632 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2633 data & KVM_STEAL_VALID_BITS,
2634 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2635 return 1;
2636
2637 vcpu->arch.st.msr_val = data;
2638
2639 if (!(data & KVM_MSR_ENABLED))
2640 break;
2641
c9aaa895
GC		 2642 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2643
2644 break;
ae7a2a3f 2645 case MSR_KVM_PV_EOI_EN:
72bbf935 2646 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2647 return 1;
2648 break;
c9aaa895 2649
2d5ba19b
MT		 2650 case MSR_KVM_POLL_CONTROL:
2651 /* only enable bit supported */
2652 if (data & (-1ULL << 1))
2653 return 1;
2654
2655 vcpu->arch.msr_kvm_poll_control = data;
2656 break;
2657
890ca9ae
HY		 2658 case MSR_IA32_MCG_CTL:
2659 case MSR_IA32_MCG_STATUS:
81760dcc 2660 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2661 return set_msr_mce(vcpu, msr_info);
71db6023 2662
6912ac32
WH		 2663 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2664 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2665 pr = true; /* fall through */
2666 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2667 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2668 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2669 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2670
2671 if (pr || data != 0)
a737f256
CD		 2672 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2673 "0x%x data 0x%llx\n", msr, data);
5753785f 2674 break;
84e0cefa
JS		 2675 case MSR_K7_CLK_CTL:
2676 /*
2677 * Ignore all writes to this no longer documented MSR.
2678 * Writes are only relevant for old K7 processors,
2679 * all pre-dating SVM, but a recommended workaround from
4a969980 2680 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2681 * affected processor models on the command line, hence
2682 * the need to ignore the workaround.
2683 */
2684 break;
55cd8e5a 2685 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2686 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2687 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2688 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2689 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2690 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2691 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2692 return kvm_hv_set_msr_common(vcpu, msr, data,
2693 msr_info->host_initiated);
91c9c3ed 2694 case MSR_IA32_BBL_CR_CTL3:
2695 /* Drop writes to this legacy MSR -- see rdmsr
2696 * counterpart for further detail.
2697 */
fab0aa3b
EM		 2698 if (report_ignored_msrs)
2699 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2700 msr, data);
91c9c3ed 2701 break;
2b036c6b 2702 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2703 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2704 return 1;
2705 vcpu->arch.osvw.length = data;
2706 break;
2707 case MSR_AMD64_OSVW_STATUS:
d6321d49 2708 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2709 return 1;
2710 vcpu->arch.osvw.status = data;
2711 break;
db2336a8
KH		 2712 case MSR_PLATFORM_INFO:
2713 if (!msr_info->host_initiated ||
db2336a8
KH		 2714 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2715 cpuid_fault_enabled(vcpu)))
2716 return 1;
2717 vcpu->arch.msr_platform_info = data;
2718 break;
2719 case MSR_MISC_FEATURES_ENABLES:
2720 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2721 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2722 !supports_cpuid_fault(vcpu)))
2723 return 1;
2724 vcpu->arch.msr_misc_features_enables = data;
2725 break;
15c4a640 2726 default:
ffde22ac
ES		 2727 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2728 return xen_hvm_config(vcpu, data);
c6702c9d 2729 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2730 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2731 if (!ignore_msrs) {
ae0f5499 2732 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2733 msr, data);
ed85c068
AP		 2734 return 1;
2735 } else {
fab0aa3b
EM		 2736 if (report_ignored_msrs)
2737 vcpu_unimpl(vcpu,
2738 "ignored wrmsr: 0x%x data 0x%llx\n",
2739 msr, data);
ed85c068
AP		 2740 break;
2741 }
15c4a640
CO		 2742 }
2743 return 0;
2744}
2745EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2746
2747
2748/*
2749 * Reads an msr value (of 'msr_index') into 'pdata'.
2750 * Returns 0 on success, non-0 otherwise.
2751 * Assumes vcpu_load() was already called.
2752 */
609e36d3 2753int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2754{
609e36d3 2755 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2756}
ff651cb6 2757EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2758
44883f01 2759static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2760{
2761 u64 data;
890ca9ae
HY		 2762 u64 mcg_cap = vcpu->arch.mcg_cap;
2763 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2764
2765 switch (msr) {
15c4a640
CO		 2766 case MSR_IA32_P5_MC_ADDR:
2767 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2768 data = 0;
2769 break;
15c4a640 2770 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2771 data = vcpu->arch.mcg_cap;
2772 break;
c7ac679c 2773 case MSR_IA32_MCG_CTL:
44883f01 2774 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2775 return 1;
2776 data = vcpu->arch.mcg_ctl;
2777 break;
2778 case MSR_IA32_MCG_STATUS:
2779 data = vcpu->arch.mcg_status;
2780 break;
2781 default:
2782 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2783 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2784 u32 offset = msr - MSR_IA32_MC0_CTL;
2785 data = vcpu->arch.mce_banks[offset];
2786 break;
2787 }
2788 return 1;
2789 }
2790 *pdata = data;
2791 return 0;
2792}
2793
609e36d3 2794int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2795{
609e36d3 2796 switch (msr_info->index) {
890ca9ae 2797 case MSR_IA32_PLATFORM_ID:
15c4a640 2798 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2799 case MSR_IA32_DEBUGCTLMSR:
2800 case MSR_IA32_LASTBRANCHFROMIP:
2801 case MSR_IA32_LASTBRANCHTOIP:
2802 case MSR_IA32_LASTINTFROMIP:
2803 case MSR_IA32_LASTINTTOIP:
60af2ecd 2804 case MSR_K8_SYSCFG:
3afb1121
PB		 2805 case MSR_K8_TSEG_ADDR:
2806 case MSR_K8_TSEG_MASK:
61a6bd67 2807 case MSR_VM_HSAVE_PA:
1fdbd48c 2808 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2809 case MSR_AMD64_NB_CFG:
f7c6d140 2810 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2811 case MSR_AMD64_BU_CFG2:
0c2df2a1 2812 case MSR_IA32_PERF_CTL:
405a353a 2813 case MSR_AMD64_DC_CFG:
0e1b869f 2814 case MSR_F15H_EX_CFG:
609e36d3 2815 msr_info->data = 0;
15c4a640 2816 break;
c51eb52b 2817 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2818 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2819 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2820 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2821 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2822 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2823 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2824 msr_info->data = 0;
5753785f 2825 break;
742bc670 2826 case MSR_IA32_UCODE_REV:
518e7b94 2827 msr_info->data = vcpu->arch.microcode_version;
742bc670 2828 break;
0cf9135b
SC		 2829 case MSR_IA32_ARCH_CAPABILITIES:
2830 if (!msr_info->host_initiated &&
2831 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2832 return 1;
2833 msr_info->data = vcpu->arch.arch_capabilities;
2834 break;
73f624f4
PB		 2835 case MSR_IA32_POWER_CTL:
2836 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2837 break;
dd259935
PB		 2838 case MSR_IA32_TSC:
2839 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2840 break;
9ba075a6 2841 case MSR_MTRRcap:
9ba075a6 2842 case 0x200 ... 0x2ff:
ff53604b 2843 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2844 case 0xcd: /* fsb frequency */
609e36d3 2845 msr_info->data = 3;
15c4a640 2846 break;
7b914098
JS		 2847 /*
2848 * MSR_EBC_FREQUENCY_ID
2849 * Conservative value valid for even the basic CPU models.
2850 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2851 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2852 * and 266MHz for model 3, or 4. Set Core Clock
2853 * Frequency to System Bus Frequency Ratio to 1 (bits
2854 * 31:24) even though these are only valid for CPU
2855 * models > 2, however guests may end up dividing or
2856 * multiplying by zero otherwise.
2857 */
2858 case MSR_EBC_FREQUENCY_ID:
609e36d3 2859 msr_info->data = 1 << 24;
7b914098 2860 break;
15c4a640 2861 case MSR_IA32_APICBASE:
609e36d3 2862 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2863 break;
0105d1a5 2864 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2865 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2866 break;
a3e06bbe 2867 case MSR_IA32_TSCDEADLINE:
609e36d3 2868 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2869 break;
ba904635 2870 case MSR_IA32_TSC_ADJUST:
609e36d3 2871 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2872 break;
15c4a640 2873 case MSR_IA32_MISC_ENABLE:
609e36d3 2874 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2875 break;
64d60670
PB		 2876 case MSR_IA32_SMBASE:
2877 if (!msr_info->host_initiated)
2878 return 1;
2879 msr_info->data = vcpu->arch.smbase;
15c4a640 2880 break;
52797bf9
LA		 2881 case MSR_SMI_COUNT:
2882 msr_info->data = vcpu->arch.smi_count;
2883 break;
847f0ad8
AG		 2884 case MSR_IA32_PERF_STATUS:
2885 /* TSC increment by tick */
609e36d3 2886 msr_info->data = 1000ULL;
847f0ad8 2887 /* CPU multiplier */
b0996ae4 2888 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2889 break;
15c4a640 2890 case MSR_EFER:
609e36d3 2891 msr_info->data = vcpu->arch.efer;
15c4a640 2892 break;
18068523 2893 case MSR_KVM_WALL_CLOCK:
11c6bffa 2894 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2895 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2896 break;
2897 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2898 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2899 msr_info->data = vcpu->arch.time;
18068523 2900 break;
344d9588 2901 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2902 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2903 break;
c9aaa895 2904 case MSR_KVM_STEAL_TIME:
609e36d3 2905 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2906 break;
1d92128f 2907 case MSR_KVM_PV_EOI_EN:
609e36d3 2908 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2909 break;
2d5ba19b
MT		 2910 case MSR_KVM_POLL_CONTROL:
2911 msr_info->data = vcpu->arch.msr_kvm_poll_control;
2912 break;
890ca9ae
HY		 2913 case MSR_IA32_P5_MC_ADDR:
2914 case MSR_IA32_P5_MC_TYPE:
2915 case MSR_IA32_MCG_CAP:
2916 case MSR_IA32_MCG_CTL:
2917 case MSR_IA32_MCG_STATUS:
81760dcc 2918 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2919 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2920 msr_info->host_initiated);
84e0cefa
JS		 2921 case MSR_K7_CLK_CTL:
2922 /*
2923 * Provide expected ramp-up count for K7. All other
2924 * are set to zero, indicating minimum divisors for
2925 * every field.
2926 *
2927 * This prevents guest kernels on AMD host with CPU
2928 * type 6, model 8 and higher from exploding due to
2929 * the rdmsr failing.
2930 */
609e36d3 2931 msr_info->data = 0x20000000;
84e0cefa 2932 break;
55cd8e5a 2933 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2934 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2935 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2936 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2937 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2938 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2939 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2940 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2941 msr_info->index, &msr_info->data,
2942 msr_info->host_initiated);
55cd8e5a 2943 break;
91c9c3ed 2944 case MSR_IA32_BBL_CR_CTL3:
2945 /* This legacy MSR exists but isn't fully documented in current
2946 * silicon. It is however accessed by winxp in very narrow
2947 * scenarios where it sets bit #19, itself documented as
2948 * a "reserved" bit. Best effort attempt to source coherent
2949 * read data here should the balance of the register be
2950 * interpreted by the guest:
2951 *
2952 * L2 cache control register 3: 64GB range, 256KB size,
2953 * enabled, latency 0x1, configured
2954 */
609e36d3 2955 msr_info->data = 0xbe702111;
91c9c3ed 2956 break;
2b036c6b 2957 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2958 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2959 return 1;
609e36d3 2960 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2961 break;
2962 case MSR_AMD64_OSVW_STATUS:
d6321d49 2963 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2964 return 1;
609e36d3 2965 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2966 break;
db2336a8 2967 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2968 if (!msr_info->host_initiated &&
2969 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2970 return 1;
db2336a8
KH		 2971 msr_info->data = vcpu->arch.msr_platform_info;
2972 break;
2973 case MSR_MISC_FEATURES_ENABLES:
2974 msr_info->data = vcpu->arch.msr_misc_features_enables;
2975 break;
191c8137
BP		 2976 case MSR_K7_HWCR:
2977 msr_info->data = vcpu->arch.msr_hwcr;
2978 break;
15c4a640 2979 default:
c6702c9d 2980 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2981 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2982 if (!ignore_msrs) {
ae0f5499
BD		 2983 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2984 msr_info->index);
ed85c068
AP		 2985 return 1;
2986 } else {
fab0aa3b
EM		 2987 if (report_ignored_msrs)
2988 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2989 msr_info->index);
609e36d3 2990 msr_info->data = 0;
ed85c068
AP		 2991 }
2992 break;
15c4a640 2993 }
15c4a640
CO		 2994 return 0;
2995}
2996EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2997
313a3dc7
CO		 2998/*
2999 * Read or write a bunch of msrs. All parameters are kernel addresses.
3000 *
3001 * @return number of msrs set successfully.
3002 */
3003static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3004 struct kvm_msr_entry *entries,
3005 int (*do_msr)(struct kvm_vcpu *vcpu,
3006 unsigned index, u64 *data))
3007{
801e459a 3008 int i;
313a3dc7 3009
313a3dc7
CO		 3010 for (i = 0; i < msrs->nmsrs; ++i)
3011 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3012 break;
3013
313a3dc7
CO		 3014 return i;
3015}
3016
3017/*
3018 * Read or write a bunch of msrs. Parameters are user addresses.
3019 *
3020 * @return number of msrs set successfully.
3021 */
3022static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3023 int (*do_msr)(struct kvm_vcpu *vcpu,
3024 unsigned index, u64 *data),
3025 int writeback)
3026{
3027 struct kvm_msrs msrs;
3028 struct kvm_msr_entry *entries;
3029 int r, n;
3030 unsigned size;
3031
3032 r = -EFAULT;
0e96f31e 3033 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 3034 goto out;
3035
3036 r = -E2BIG;
3037 if (msrs.nmsrs >= MAX_IO_MSRS)
3038 goto out;
3039
313a3dc7 3040 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 3041 entries = memdup_user(user_msrs->entries, size);
3042 if (IS_ERR(entries)) {
3043 r = PTR_ERR(entries);
313a3dc7 3044 goto out;
ff5c2c03 3045 }
313a3dc7
CO		 3046
3047 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3048 if (r < 0)
3049 goto out_free;
3050
3051 r = -EFAULT;
3052 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3053 goto out_free;
3054
3055 r = n;
3056
3057out_free:
7a73c028 3058 kfree(entries);
313a3dc7
CO		 3059out:
3060 return r;
3061}
3062
4d5422ce
WL		 3063static inline bool kvm_can_mwait_in_guest(void)
3064{
3065 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 3066 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3067 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 3068}
3069
784aa3d7 3070int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 3071{
4d5422ce 3072 int r = 0;
018d00d2
ZX		 3073
3074 switch (ext) {
3075 case KVM_CAP_IRQCHIP:
3076 case KVM_CAP_HLT:
3077 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 3078 case KVM_CAP_SET_TSS_ADDR:
07716717 3079 case KVM_CAP_EXT_CPUID:
9c15bb1d 3080 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3081 case KVM_CAP_CLOCKSOURCE:
7837699f 3082 case KVM_CAP_PIT:
a28e4f5a 3083 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3084 case KVM_CAP_MP_STATE:
ed848624 3085 case KVM_CAP_SYNC_MMU:
a355c85c 3086 case KVM_CAP_USER_NMI:
52d939a0 3087 case KVM_CAP_REINJECT_CONTROL:
4925663a 3088 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3089 case KVM_CAP_IOEVENTFD:
f848a5a8 3090 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3091 case KVM_CAP_PIT2:
e9f42757 3092 case KVM_CAP_PIT_STATE2:
b927a3ce 3093 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3094 case KVM_CAP_XEN_HVM:
3cfc3092 3095 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3096 case KVM_CAP_HYPERV:
10388a07 3097 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3098 case KVM_CAP_HYPERV_SPIN:
5c919412 3099 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3100 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3101 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3102 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3103 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3104 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 3105 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
2bc39970 3106 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3107 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3108 case KVM_CAP_DEBUGREGS:
d2be1651 3109 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3110 case KVM_CAP_XSAVE:
344d9588 3111 case KVM_CAP_ASYNC_PF:
92a1f12d 3112 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3113 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3114 case KVM_CAP_READONLY_MEM:
5f66b620 3115 case KVM_CAP_HYPERV_TIME:
100943c5 3116 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3117 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3118 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3119 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3120 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3121 case KVM_CAP_IMMEDIATE_EXIT:
66bb8a06 3122 case KVM_CAP_PMU_EVENT_FILTER:
801e459a 3123 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3124 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3125 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3126 r = 1;
3127 break;
01643c51
KH		 3128 case KVM_CAP_SYNC_REGS:
3129 r = KVM_SYNC_X86_VALID_FIELDS;
3130 break;
e3fd9a93
PB		 3131 case KVM_CAP_ADJUST_CLOCK:
3132 r = KVM_CLOCK_TSC_STABLE;
3133 break;
4d5422ce 3134 case KVM_CAP_X86_DISABLE_EXITS:
b5170063
WL		 3135 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3136 KVM_X86_DISABLE_EXITS_CSTATE;
4d5422ce
WL		 3137 if(kvm_can_mwait_in_guest())
3138 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3139 break;
6d396b55
PB		 3140 case KVM_CAP_X86_SMM:
3141 /* SMBASE is usually relocated above 1M on modern chipsets,
3142 * and SMM handlers might indeed rely on 4G segment limits,
3143 * so do not report SMM to be available if real mode is
3144 * emulated via vm86 mode. Still, do not go to great lengths
3145 * to avoid userspace's usage of the feature, because it is a
3146 * fringe case that is not enabled except via specific settings
3147 * of the module parameters.
3148 */
bc226f07 3149 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3150 break;
774ead3a
AK		 3151 case KVM_CAP_VAPIC:
3152 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3153 break;
f725230a 3154 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3155 r = KVM_SOFT_MAX_VCPUS;
3156 break;
3157 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3158 r = KVM_MAX_VCPUS;
3159 break;
a86cb413
TH		 3160 case KVM_CAP_MAX_VCPU_ID:
3161 r = KVM_MAX_VCPU_ID;
3162 break;
a68a6a72
MT		 3163 case KVM_CAP_PV_MMU: /* obsolete */
3164 r = 0;
2f333bcb 3165 break;
890ca9ae
HY		 3166 case KVM_CAP_MCE:
3167 r = KVM_MAX_MCE_BANKS;
3168 break;
2d5b5a66 3169 case KVM_CAP_XCRS:
d366bf7e 3170 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3171 break;
92a1f12d
JR		 3172 case KVM_CAP_TSC_CONTROL:
3173 r = kvm_has_tsc_control;
3174 break;
37131313
RK		 3175 case KVM_CAP_X2APIC_API:
3176 r = KVM_X2APIC_API_VALID_FLAGS;
3177 break;
8fcc4b59
JM		 3178 case KVM_CAP_NESTED_STATE:
3179 r = kvm_x86_ops->get_nested_state ?
be43c440 3180 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3181 break;
018d00d2 3182 default:
018d00d2
ZX		 3183 break;
3184 }
3185 return r;
3186
3187}
3188
043405e1
CO		 3189long kvm_arch_dev_ioctl(struct file *filp,
3190 unsigned int ioctl, unsigned long arg)
3191{
3192 void __user *argp = (void __user *)arg;
3193 long r;
3194
3195 switch (ioctl) {
3196 case KVM_GET_MSR_INDEX_LIST: {
3197 struct kvm_msr_list __user *user_msr_list = argp;
3198 struct kvm_msr_list msr_list;
3199 unsigned n;
3200
3201 r = -EFAULT;
0e96f31e 3202 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3203 goto out;
3204 n = msr_list.nmsrs;
62ef68bb 3205 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3206 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3207 goto out;
3208 r = -E2BIG;
e125e7b6 3209 if (n < msr_list.nmsrs)
043405e1
CO		 3210 goto out;
3211 r = -EFAULT;
3212 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3213 num_msrs_to_save * sizeof(u32)))
3214 goto out;
e125e7b6 3215 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3216 &emulated_msrs,
62ef68bb 3217 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3218 goto out;
3219 r = 0;
3220 break;
3221 }
9c15bb1d
BP		 3222 case KVM_GET_SUPPORTED_CPUID:
3223 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3224 struct kvm_cpuid2 __user *cpuid_arg = argp;
3225 struct kvm_cpuid2 cpuid;
3226
3227 r = -EFAULT;
0e96f31e 3228 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3229 goto out;
9c15bb1d
BP		 3230
3231 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3232 ioctl);
674eea0f
AK		 3233 if (r)
3234 goto out;
3235
3236 r = -EFAULT;
0e96f31e 3237 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3238 goto out;
3239 r = 0;
3240 break;
3241 }
890ca9ae 3242 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3243 r = -EFAULT;
c45dcc71
AR		 3244 if (copy_to_user(argp, &kvm_mce_cap_supported,
3245 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3246 goto out;
3247 r = 0;
3248 break;
801e459a
TL		 3249 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3250 struct kvm_msr_list __user *user_msr_list = argp;
3251 struct kvm_msr_list msr_list;
3252 unsigned int n;
3253
3254 r = -EFAULT;
3255 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3256 goto out;
3257 n = msr_list.nmsrs;
3258 msr_list.nmsrs = num_msr_based_features;
3259 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3260 goto out;
3261 r = -E2BIG;
3262 if (n < msr_list.nmsrs)
3263 goto out;
3264 r = -EFAULT;
3265 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3266 num_msr_based_features * sizeof(u32)))
3267 goto out;
3268 r = 0;
3269 break;
3270 }
3271 case KVM_GET_MSRS:
3272 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3273 break;
890ca9ae 3274 }
043405e1
CO		 3275 default:
3276 r = -EINVAL;
3277 }
3278out:
3279 return r;
3280}
3281
f5f48ee1
SY		 3282static void wbinvd_ipi(void *garbage)
3283{
3284 wbinvd();
3285}
3286
3287static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3288{
e0f0bbc5 3289 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3290}
3291
313a3dc7
CO		 3292void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3293{
f5f48ee1
SY		 3294 /* Address WBINVD may be executed by guest */
3295 if (need_emulate_wbinvd(vcpu)) {
3296 if (kvm_x86_ops->has_wbinvd_exit())
3297 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3298 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3299 smp_call_function_single(vcpu->cpu,
3300 wbinvd_ipi, NULL, 1);
3301 }
3302
313a3dc7 3303 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3304
0dd6a6ed
ZA		 3305 /* Apply any externally detected TSC adjustments (due to suspend) */
3306 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3307 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3308 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3309 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3310 }
8f6055cb 3311
b0c39dc6 3312 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3313 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3314 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3315 if (tsc_delta < 0)
3316 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3317
b0c39dc6 3318 if (kvm_check_tsc_unstable()) {
07c1419a 3319 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3320 vcpu->arch.last_guest_tsc);
a545ab6a 3321 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3322 vcpu->arch.tsc_catchup = 1;
c285545f 3323 }
a749e247
PB		 3324
3325 if (kvm_lapic_hv_timer_in_use(vcpu))
3326 kvm_lapic_restart_hv_timer(vcpu);
3327
d98d07ca
MT		 3328 /*
3329 * On a host with synchronized TSC, there is no need to update
3330 * kvmclock on vcpu->cpu migration
3331 */
3332 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3333 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3334 if (vcpu->cpu != cpu)
1bd2009e 3335 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3336 vcpu->cpu = cpu;
6b7d7e76 3337 }
c9aaa895 3338
c9aaa895 3339 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3340}
3341
0b9f6c46
PX		 3342static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3343{
3344 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3345 return;
3346
fa55eedd 3347 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3348
4e335d9e 3349 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3350 &vcpu->arch.st.steal.preempted,
3351 offsetof(struct kvm_steal_time, preempted),
3352 sizeof(vcpu->arch.st.steal.preempted));
3353}
3354
313a3dc7
CO		 3355void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3356{
cc0d907c 3357 int idx;
de63ad4c
LM		 3358
3359 if (vcpu->preempted)
3360 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3361
931f261b
AA		 3362 /*
3363 * Disable page faults because we're in atomic context here.
3364 * kvm_write_guest_offset_cached() would call might_fault()
3365 * that relies on pagefault_disable() to tell if there's a
3366 * bug. NOTE: the write to guest memory may not go through if
3367 * during postcopy live migration or if there's heavy guest
3368 * paging.
3369 */
3370 pagefault_disable();
cc0d907c
AA		 3371 /*
3372 * kvm_memslots() will be called by
3373 * kvm_write_guest_offset_cached() so take the srcu lock.
3374 */
3375 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3376 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3377 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3378 pagefault_enable();
02daab21 3379 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3380 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3381 /*
f9dcf08e
RK		 3382 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3383 * on every vmexit, but if not, we might have a stale dr6 from the
3384 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3385 */
f9dcf08e 3386 set_debugreg(0, 6);
313a3dc7
CO		 3387}
3388
313a3dc7
CO		 3389static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3390 struct kvm_lapic_state *s)
3391{
fa59cc00 3392 if (vcpu->arch.apicv_active)
d62caabb
AS		 3393 kvm_x86_ops->sync_pir_to_irr(vcpu);
3394
a92e2543 3395 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3396}
3397
3398static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3399 struct kvm_lapic_state *s)
3400{
a92e2543
RK		 3401 int r;
3402
3403 r = kvm_apic_set_state(vcpu, s);
3404 if (r)
3405 return r;
cb142eb7 3406 update_cr8_intercept(vcpu);
313a3dc7
CO		 3407
3408 return 0;
3409}
3410
127a457a
MG		 3411static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3412{
3413 return (!lapic_in_kernel(vcpu) ||
3414 kvm_apic_accept_pic_intr(vcpu));
3415}
3416
782d422b
MG		 3417/*
3418 * if userspace requested an interrupt window, check that the
3419 * interrupt window is open.
3420 *
3421 * No need to exit to userspace if we already have an interrupt queued.
3422 */
3423static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3424{
3425 return kvm_arch_interrupt_allowed(vcpu) &&
3426 !kvm_cpu_has_interrupt(vcpu) &&
3427 !kvm_event_needs_reinjection(vcpu) &&
3428 kvm_cpu_accept_dm_intr(vcpu);
3429}
3430
f77bc6a4
ZX		 3431static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3432 struct kvm_interrupt *irq)
3433{
02cdb50f 3434 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3435 return -EINVAL;
1c1a9ce9
SR		 3436
3437 if (!irqchip_in_kernel(vcpu->kvm)) {
3438 kvm_queue_interrupt(vcpu, irq->irq, false);
3439 kvm_make_request(KVM_REQ_EVENT, vcpu);
3440 return 0;
3441 }
3442
3443 /*
3444 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3445 * fail for in-kernel 8259.
3446 */
3447 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3448 return -ENXIO;
f77bc6a4 3449
1c1a9ce9
SR		 3450 if (vcpu->arch.pending_external_vector != -1)
3451 return -EEXIST;
f77bc6a4 3452
1c1a9ce9 3453 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3454 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3455 return 0;
3456}
3457
c4abb7c9
JK		 3458static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3459{
c4abb7c9 3460 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3461
3462 return 0;
3463}
3464
f077825a
PB		 3465static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3466{
64d60670
PB		 3467 kvm_make_request(KVM_REQ_SMI, vcpu);
3468
f077825a
PB		 3469 return 0;
3470}
3471
b209749f
AK		 3472static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3473 struct kvm_tpr_access_ctl *tac)
3474{
3475 if (tac->flags)
3476 return -EINVAL;
3477 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3478 return 0;
3479}
3480
890ca9ae
HY		 3481static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3482 u64 mcg_cap)
3483{
3484 int r;
3485 unsigned bank_num = mcg_cap & 0xff, bank;
3486
3487 r = -EINVAL;
a9e38c3e 3488 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3489 goto out;
c45dcc71 3490 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3491 goto out;
3492 r = 0;
3493 vcpu->arch.mcg_cap = mcg_cap;
3494 /* Init IA32_MCG_CTL to all 1s */
3495 if (mcg_cap & MCG_CTL_P)
3496 vcpu->arch.mcg_ctl = ~(u64)0;
3497 /* Init IA32_MCi_CTL to all 1s */
3498 for (bank = 0; bank < bank_num; bank++)
3499 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3500
3501 if (kvm_x86_ops->setup_mce)
3502 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3503out:
3504 return r;
3505}
3506
3507static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3508 struct kvm_x86_mce *mce)
3509{
3510 u64 mcg_cap = vcpu->arch.mcg_cap;
3511 unsigned bank_num = mcg_cap & 0xff;
3512 u64 *banks = vcpu->arch.mce_banks;
3513
3514 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3515 return -EINVAL;
3516 /*
3517 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3518 * reporting is disabled
3519 */
3520 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3521 vcpu->arch.mcg_ctl != ~(u64)0)
3522 return 0;
3523 banks += 4 * mce->bank;
3524 /*
3525 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3526 * reporting is disabled for the bank
3527 */
3528 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3529 return 0;
3530 if (mce->status & MCI_STATUS_UC) {
3531 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3532 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3533 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3534 return 0;
3535 }
3536 if (banks[1] & MCI_STATUS_VAL)
3537 mce->status |= MCI_STATUS_OVER;
3538 banks[2] = mce->addr;
3539 banks[3] = mce->misc;
3540 vcpu->arch.mcg_status = mce->mcg_status;
3541 banks[1] = mce->status;
3542 kvm_queue_exception(vcpu, MC_VECTOR);
3543 } else if (!(banks[1] & MCI_STATUS_VAL)
3544 || !(banks[1] & MCI_STATUS_UC)) {
3545 if (banks[1] & MCI_STATUS_VAL)
3546 mce->status |= MCI_STATUS_OVER;
3547 banks[2] = mce->addr;
3548 banks[3] = mce->misc;
3549 banks[1] = mce->status;
3550 } else
3551 banks[1] |= MCI_STATUS_OVER;
3552 return 0;
3553}
3554
3cfc3092
JK		 3555static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3556 struct kvm_vcpu_events *events)
3557{
7460fb4a 3558 process_nmi(vcpu);
59073aaf 3559
664f8e26 3560 /*
59073aaf
JM		 3561 * The API doesn't provide the instruction length for software
3562 * exceptions, so don't report them. As long as the guest RIP
3563 * isn't advanced, we should expect to encounter the exception
3564 * again.
664f8e26 3565 */
59073aaf
JM		 3566 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3567 events->exception.injected = 0;
3568 events->exception.pending = 0;
3569 } else {
3570 events->exception.injected = vcpu->arch.exception.injected;
3571 events->exception.pending = vcpu->arch.exception.pending;
3572 /*
3573 * For ABI compatibility, deliberately conflate
3574 * pending and injected exceptions when
3575 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3576 */
3577 if (!vcpu->kvm->arch.exception_payload_enabled)
3578 events->exception.injected |=
3579 vcpu->arch.exception.pending;
3580 }
3cfc3092
JK		 3581 events->exception.nr = vcpu->arch.exception.nr;
3582 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3583 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3584 events->exception_has_payload = vcpu->arch.exception.has_payload;
3585 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3586
03b82a30 3587 events->interrupt.injected =
04140b41 3588 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3589 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3590 events->interrupt.soft = 0;
37ccdcbe 3591 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3592
3593 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3594 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3595 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3596 events->nmi.pad = 0;
3cfc3092 3597
66450a21 3598 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3599
f077825a
PB		 3600 events->smi.smm = is_smm(vcpu);
3601 events->smi.pending = vcpu->arch.smi_pending;
3602 events->smi.smm_inside_nmi =
3603 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3604 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3605
dab4b911 3606 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3607 | KVM_VCPUEVENT_VALID_SHADOW
3608 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3609 if (vcpu->kvm->arch.exception_payload_enabled)
3610 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3611
97e69aa6 3612 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3613}
3614
c5833c7a 3615static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3616
3cfc3092
JK		 3617static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3618 struct kvm_vcpu_events *events)
3619{
dab4b911 3620 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3621 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3622 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3623 | KVM_VCPUEVENT_VALID_SMM
3624 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3625 return -EINVAL;
3626
59073aaf
JM		 3627 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3628 if (!vcpu->kvm->arch.exception_payload_enabled)
3629 return -EINVAL;
3630 if (events->exception.pending)
3631 events->exception.injected = 0;
3632 else
3633 events->exception_has_payload = 0;
3634 } else {
3635 events->exception.pending = 0;
3636 events->exception_has_payload = 0;
3637 }
3638
3639 if ((events->exception.injected || events->exception.pending) &&
3640 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3641 return -EINVAL;
3642
28bf2888
DH		 3643 /* INITs are latched while in SMM */
3644 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3645 (events->smi.smm || events->smi.pending) &&
3646 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3647 return -EINVAL;
3648
7460fb4a 3649 process_nmi(vcpu);
59073aaf
JM		 3650 vcpu->arch.exception.injected = events->exception.injected;
3651 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3652 vcpu->arch.exception.nr = events->exception.nr;
3653 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3654 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3655 vcpu->arch.exception.has_payload = events->exception_has_payload;
3656 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3657
04140b41 3658 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3659 vcpu->arch.interrupt.nr = events->interrupt.nr;
3660 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3661 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3662 kvm_x86_ops->set_interrupt_shadow(vcpu,
3663 events->interrupt.shadow);
3cfc3092
JK		 3664
3665 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3666 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3667 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3668 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3669
66450a21 3670 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3671 lapic_in_kernel(vcpu))
66450a21 3672 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3673
f077825a 3674 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3675 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3676 if (events->smi.smm)
3677 vcpu->arch.hflags |= HF_SMM_MASK;
3678 else
3679 vcpu->arch.hflags &= ~HF_SMM_MASK;
3680 kvm_smm_changed(vcpu);
3681 }
6ef4e07e 3682
f077825a 3683 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3684
3685 if (events->smi.smm) {
3686 if (events->smi.smm_inside_nmi)
3687 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3688 else
f4ef1910
WL		 3689 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3690 if (lapic_in_kernel(vcpu)) {
3691 if (events->smi.latched_init)
3692 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3693 else
3694 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3695 }
f077825a
PB		 3696 }
3697 }
3698
3842d135
AK		 3699 kvm_make_request(KVM_REQ_EVENT, vcpu);
3700
3cfc3092
JK		 3701 return 0;
3702}
3703
a1efbe77
JK		 3704static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3705 struct kvm_debugregs *dbgregs)
3706{
73aaf249
JK		 3707 unsigned long val;
3708
a1efbe77 3709 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3710 kvm_get_dr(vcpu, 6, &val);
73aaf249 3711 dbgregs->dr6 = val;
a1efbe77
JK		 3712 dbgregs->dr7 = vcpu->arch.dr7;
3713 dbgregs->flags = 0;
97e69aa6 3714 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3715}
3716
3717static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3718 struct kvm_debugregs *dbgregs)
3719{
3720 if (dbgregs->flags)
3721 return -EINVAL;
3722
d14bdb55
PB		 3723 if (dbgregs->dr6 & ~0xffffffffull)
3724 return -EINVAL;
3725 if (dbgregs->dr7 & ~0xffffffffull)
3726 return -EINVAL;
3727
a1efbe77 3728 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3729 kvm_update_dr0123(vcpu);
a1efbe77 3730 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3731 kvm_update_dr6(vcpu);
a1efbe77 3732 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3733 kvm_update_dr7(vcpu);
a1efbe77 3734
a1efbe77
JK		 3735 return 0;
3736}
3737
df1daba7
PB		 3738#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3739
3740static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3741{
b666a4b6 3742 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3743 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3744 u64 valid;
3745
3746 /*
3747 * Copy legacy XSAVE area, to avoid complications with CPUID
3748 * leaves 0 and 1 in the loop below.
3749 */
3750 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3751
3752 /* Set XSTATE_BV */
00c87e9a 3753 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3754 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3755
3756 /*
3757 * Copy each region from the possibly compacted offset to the
3758 * non-compacted offset.
3759 */
d91cab78 3760 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3761 while (valid) {
abd16d68
SAS		 3762 u64 xfeature_mask = valid & -valid;
3763 int xfeature_nr = fls64(xfeature_mask) - 1;
3764 void *src = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3765
3766 if (src) {
3767 u32 size, offset, ecx, edx;
abd16d68 3768 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3769 &size, &offset, &ecx, &edx);
abd16d68 3770 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3771 memcpy(dest + offset, &vcpu->arch.pkru,
3772 sizeof(vcpu->arch.pkru));
3773 else
3774 memcpy(dest + offset, src, size);
3775
df1daba7
PB		 3776 }
3777
abd16d68 3778 valid -= xfeature_mask;
df1daba7
PB		 3779 }
3780}
3781
3782static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3783{
b666a4b6 3784 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3785 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3786 u64 valid;
3787
3788 /*
3789 * Copy legacy XSAVE area, to avoid complications with CPUID
3790 * leaves 0 and 1 in the loop below.
3791 */
3792 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3793
3794 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3795 xsave->header.xfeatures = xstate_bv;
782511b0 3796 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3797 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3798
3799 /*
3800 * Copy each region from the non-compacted offset to the
3801 * possibly compacted offset.
3802 */
d91cab78 3803 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3804 while (valid) {
abd16d68
SAS		 3805 u64 xfeature_mask = valid & -valid;
3806 int xfeature_nr = fls64(xfeature_mask) - 1;
3807 void *dest = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3808
3809 if (dest) {
3810 u32 size, offset, ecx, edx;
abd16d68 3811 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3812 &size, &offset, &ecx, &edx);
abd16d68 3813 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3814 memcpy(&vcpu->arch.pkru, src + offset,
3815 sizeof(vcpu->arch.pkru));
3816 else
3817 memcpy(dest, src + offset, size);
ee4100da 3818 }
df1daba7 3819
abd16d68 3820 valid -= xfeature_mask;
df1daba7
PB		 3821 }
3822}
3823
2d5b5a66
SY		 3824static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3825 struct kvm_xsave *guest_xsave)
3826{
d366bf7e 3827 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3828 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3829 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3830 } else {
2d5b5a66 3831 memcpy(guest_xsave->region,
b666a4b6 3832 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3833 sizeof(struct fxregs_state));
2d5b5a66 3834 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3835 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3836 }
3837}
3838
a575813b
WL		 3839#define XSAVE_MXCSR_OFFSET 24
3840
2d5b5a66
SY		 3841static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3842 struct kvm_xsave *guest_xsave)
3843{
3844 u64 xstate_bv =
3845 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3846 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3847
d366bf7e 3848 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3849 /*
3850 * Here we allow setting states that are not present in
3851 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3852 * with old userspace.
3853 */
a575813b
WL		 3854 if (xstate_bv & ~kvm_supported_xcr0() ||
3855 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3856 return -EINVAL;
df1daba7 3857 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3858 } else {
a575813b
WL		 3859 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3860 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3861 return -EINVAL;
b666a4b6 3862 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3863 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3864 }
3865 return 0;
3866}
3867
3868static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3869 struct kvm_xcrs *guest_xcrs)
3870{
d366bf7e 3871 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3872 guest_xcrs->nr_xcrs = 0;
3873 return;
3874 }
3875
3876 guest_xcrs->nr_xcrs = 1;
3877 guest_xcrs->flags = 0;
3878 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3879 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3880}
3881
3882static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3883 struct kvm_xcrs *guest_xcrs)
3884{
3885 int i, r = 0;
3886
d366bf7e 3887 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3888 return -EINVAL;
3889
3890 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3891 return -EINVAL;
3892
3893 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3894 /* Only support XCR0 currently */
c67a04cb 3895 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3896 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3897 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3898 break;
3899 }
3900 if (r)
3901 r = -EINVAL;
3902 return r;
3903}
3904
1c0b28c2
EM		 3905/*
3906 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3907 * stopped by the hypervisor. This function will be called from the host only.
3908 * EINVAL is returned when the host attempts to set the flag for a guest that
3909 * does not support pv clocks.
3910 */
3911static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3912{
0b79459b 3913 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3914 return -EINVAL;
51d59c6b 3915 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3916 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3917 return 0;
3918}
3919
5c919412
AS		 3920static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3921 struct kvm_enable_cap *cap)
3922{
57b119da
VK		 3923 int r;
3924 uint16_t vmcs_version;
3925 void __user *user_ptr;
3926
5c919412
AS		 3927 if (cap->flags)
3928 return -EINVAL;
3929
3930 switch (cap->cap) {
efc479e6
RK		 3931 case KVM_CAP_HYPERV_SYNIC2:
3932 if (cap->args[0])
3933 return -EINVAL;
b2869f28
GS		 3934 /* fall through */
3935
5c919412 3936 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3937 if (!irqchip_in_kernel(vcpu->kvm))
3938 return -EINVAL;
efc479e6
RK		 3939 return kvm_hv_activate_synic(vcpu, cap->cap ==
3940 KVM_CAP_HYPERV_SYNIC2);
57b119da 3941 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 3942 if (!kvm_x86_ops->nested_enable_evmcs)
3943 return -ENOTTY;
57b119da
VK		 3944 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3945 if (!r) {
3946 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3947 if (copy_to_user(user_ptr, &vmcs_version,
3948 sizeof(vmcs_version)))
3949 r = -EFAULT;
3950 }
3951 return r;
3952
5c919412
AS		 3953 default:
3954 return -EINVAL;
3955 }
3956}
3957
313a3dc7
CO		 3958long kvm_arch_vcpu_ioctl(struct file *filp,
3959 unsigned int ioctl, unsigned long arg)
3960{
3961 struct kvm_vcpu *vcpu = filp->private_data;
3962 void __user *argp = (void __user *)arg;
3963 int r;
d1ac91d8
AK		 3964 union {
3965 struct kvm_lapic_state *lapic;
3966 struct kvm_xsave *xsave;
3967 struct kvm_xcrs *xcrs;
3968 void *buffer;
3969 } u;
3970
9b062471
CD		 3971 vcpu_load(vcpu);
3972
d1ac91d8 3973 u.buffer = NULL;
313a3dc7
CO		 3974 switch (ioctl) {
3975 case KVM_GET_LAPIC: {
2204ae3c 3976 r = -EINVAL;
bce87cce 3977 if (!lapic_in_kernel(vcpu))
2204ae3c 3978 goto out;
254272ce
BG		 3979 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3980 GFP_KERNEL_ACCOUNT);
313a3dc7 3981
b772ff36 3982 r = -ENOMEM;
d1ac91d8 3983 if (!u.lapic)
b772ff36 3984 goto out;
d1ac91d8 3985 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3986 if (r)
3987 goto out;
3988 r = -EFAULT;
d1ac91d8 3989 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3990 goto out;
3991 r = 0;
3992 break;
3993 }
3994 case KVM_SET_LAPIC: {
2204ae3c 3995 r = -EINVAL;
bce87cce 3996 if (!lapic_in_kernel(vcpu))
2204ae3c 3997 goto out;
ff5c2c03 3998 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3999 if (IS_ERR(u.lapic)) {
4000 r = PTR_ERR(u.lapic);
4001 goto out_nofree;
4002 }
ff5c2c03 4003
d1ac91d8 4004 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 4005 break;
4006 }
f77bc6a4
ZX		 4007 case KVM_INTERRUPT: {
4008 struct kvm_interrupt irq;
4009
4010 r = -EFAULT;
0e96f31e 4011 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 4012 goto out;
4013 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 4014 break;
4015 }
c4abb7c9
JK		 4016 case KVM_NMI: {
4017 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 4018 break;
4019 }
f077825a
PB		 4020 case KVM_SMI: {
4021 r = kvm_vcpu_ioctl_smi(vcpu);
4022 break;
4023 }
313a3dc7
CO		 4024 case KVM_SET_CPUID: {
4025 struct kvm_cpuid __user *cpuid_arg = argp;
4026 struct kvm_cpuid cpuid;
4027
4028 r = -EFAULT;
0e96f31e 4029 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 4030 goto out;
4031 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 4032 break;
4033 }
07716717
DK		 4034 case KVM_SET_CPUID2: {
4035 struct kvm_cpuid2 __user *cpuid_arg = argp;
4036 struct kvm_cpuid2 cpuid;
4037
4038 r = -EFAULT;
0e96f31e 4039 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4040 goto out;
4041 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 4042 cpuid_arg->entries);
07716717
DK		 4043 break;
4044 }
4045 case KVM_GET_CPUID2: {
4046 struct kvm_cpuid2 __user *cpuid_arg = argp;
4047 struct kvm_cpuid2 cpuid;
4048
4049 r = -EFAULT;
0e96f31e 4050 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4051 goto out;
4052 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 4053 cpuid_arg->entries);
07716717
DK		 4054 if (r)
4055 goto out;
4056 r = -EFAULT;
0e96f31e 4057 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 4058 goto out;
4059 r = 0;
4060 break;
4061 }
801e459a
TL		 4062 case KVM_GET_MSRS: {
4063 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 4064 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 4065 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4066 break;
801e459a
TL		 4067 }
4068 case KVM_SET_MSRS: {
4069 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 4070 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 4071 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4072 break;
801e459a 4073 }
b209749f
AK		 4074 case KVM_TPR_ACCESS_REPORTING: {
4075 struct kvm_tpr_access_ctl tac;
4076
4077 r = -EFAULT;
0e96f31e 4078 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 4079 goto out;
4080 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4081 if (r)
4082 goto out;
4083 r = -EFAULT;
0e96f31e 4084 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4085 goto out;
4086 r = 0;
4087 break;
4088 };
b93463aa
AK		 4089 case KVM_SET_VAPIC_ADDR: {
4090 struct kvm_vapic_addr va;
7301d6ab 4091 int idx;
b93463aa
AK		 4092
4093 r = -EINVAL;
35754c98 4094 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4095 goto out;
4096 r = -EFAULT;
0e96f31e 4097 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4098 goto out;
7301d6ab 4099 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4100 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4101 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4102 break;
4103 }
890ca9ae
HY		 4104 case KVM_X86_SETUP_MCE: {
4105 u64 mcg_cap;
4106
4107 r = -EFAULT;
0e96f31e 4108 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4109 goto out;
4110 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4111 break;
4112 }
4113 case KVM_X86_SET_MCE: {
4114 struct kvm_x86_mce mce;
4115
4116 r = -EFAULT;
0e96f31e 4117 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4118 goto out;
4119 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4120 break;
4121 }
3cfc3092
JK		 4122 case KVM_GET_VCPU_EVENTS: {
4123 struct kvm_vcpu_events events;
4124
4125 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4126
4127 r = -EFAULT;
4128 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4129 break;
4130 r = 0;
4131 break;
4132 }
4133 case KVM_SET_VCPU_EVENTS: {
4134 struct kvm_vcpu_events events;
4135
4136 r = -EFAULT;
4137 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4138 break;
4139
4140 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4141 break;
4142 }
a1efbe77
JK		 4143 case KVM_GET_DEBUGREGS: {
4144 struct kvm_debugregs dbgregs;
4145
4146 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4147
4148 r = -EFAULT;
4149 if (copy_to_user(argp, &dbgregs,
4150 sizeof(struct kvm_debugregs)))
4151 break;
4152 r = 0;
4153 break;
4154 }
4155 case KVM_SET_DEBUGREGS: {
4156 struct kvm_debugregs dbgregs;
4157
4158 r = -EFAULT;
4159 if (copy_from_user(&dbgregs, argp,
4160 sizeof(struct kvm_debugregs)))
4161 break;
4162
4163 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4164 break;
4165 }
2d5b5a66 4166 case KVM_GET_XSAVE: {
254272ce 4167 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4168 r = -ENOMEM;
d1ac91d8 4169 if (!u.xsave)
2d5b5a66
SY		 4170 break;
4171
d1ac91d8 4172 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4173
4174 r = -EFAULT;
d1ac91d8 4175 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4176 break;
4177 r = 0;
4178 break;
4179 }
4180 case KVM_SET_XSAVE: {
ff5c2c03 4181 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4182 if (IS_ERR(u.xsave)) {
4183 r = PTR_ERR(u.xsave);
4184 goto out_nofree;
4185 }
2d5b5a66 4186
d1ac91d8 4187 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4188 break;
4189 }
4190 case KVM_GET_XCRS: {
254272ce 4191 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4192 r = -ENOMEM;
d1ac91d8 4193 if (!u.xcrs)
2d5b5a66
SY		 4194 break;
4195
d1ac91d8 4196 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4197
4198 r = -EFAULT;
d1ac91d8 4199 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4200 sizeof(struct kvm_xcrs)))
4201 break;
4202 r = 0;
4203 break;
4204 }
4205 case KVM_SET_XCRS: {
ff5c2c03 4206 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4207 if (IS_ERR(u.xcrs)) {
4208 r = PTR_ERR(u.xcrs);
4209 goto out_nofree;
4210 }
2d5b5a66 4211
d1ac91d8 4212 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4213 break;
4214 }
92a1f12d
JR		 4215 case KVM_SET_TSC_KHZ: {
4216 u32 user_tsc_khz;
4217
4218 r = -EINVAL;
92a1f12d
JR		 4219 user_tsc_khz = (u32)arg;
4220
4221 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4222 goto out;
4223
cc578287
ZA		 4224 if (user_tsc_khz == 0)
4225 user_tsc_khz = tsc_khz;
4226
381d585c
HZ		 4227 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4228 r = 0;
92a1f12d 4229
92a1f12d
JR		 4230 goto out;
4231 }
4232 case KVM_GET_TSC_KHZ: {
cc578287 4233 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4234 goto out;
4235 }
1c0b28c2
EM		 4236 case KVM_KVMCLOCK_CTRL: {
4237 r = kvm_set_guest_paused(vcpu);
4238 goto out;
4239 }
5c919412
AS		 4240 case KVM_ENABLE_CAP: {
4241 struct kvm_enable_cap cap;
4242
4243 r = -EFAULT;
4244 if (copy_from_user(&cap, argp, sizeof(cap)))
4245 goto out;
4246 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4247 break;
4248 }
8fcc4b59
JM		 4249 case KVM_GET_NESTED_STATE: {
4250 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4251 u32 user_data_size;
4252
4253 r = -EINVAL;
4254 if (!kvm_x86_ops->get_nested_state)
4255 break;
4256
4257 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4258 r = -EFAULT;
8fcc4b59 4259 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4260 break;
8fcc4b59
JM		 4261
4262 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4263 user_data_size);
4264 if (r < 0)
26b471c7 4265 break;
8fcc4b59
JM		 4266
4267 if (r > user_data_size) {
4268 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4269 r = -EFAULT;
4270 else
4271 r = -E2BIG;
4272 break;
8fcc4b59 4273 }
26b471c7 4274
8fcc4b59
JM		 4275 r = 0;
4276 break;
4277 }
4278 case KVM_SET_NESTED_STATE: {
4279 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4280 struct kvm_nested_state kvm_state;
4281
4282 r = -EINVAL;
4283 if (!kvm_x86_ops->set_nested_state)
4284 break;
4285
26b471c7 4286 r = -EFAULT;
8fcc4b59 4287 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4288 break;
8fcc4b59 4289
26b471c7 4290 r = -EINVAL;
8fcc4b59 4291 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4292 break;
8fcc4b59
JM		 4293
4294 if (kvm_state.flags &
8cab6507
VK		 4295 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4296 | KVM_STATE_NESTED_EVMCS))
26b471c7 4297 break;
8fcc4b59
JM		 4298
4299 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4300 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4301 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4302 break;
8fcc4b59
JM		 4303
4304 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4305 break;
4306 }
2bc39970
VK		 4307 case KVM_GET_SUPPORTED_HV_CPUID: {
4308 struct kvm_cpuid2 __user *cpuid_arg = argp;
4309 struct kvm_cpuid2 cpuid;
4310
4311 r = -EFAULT;
4312 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4313 goto out;
4314
4315 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4316 cpuid_arg->entries);
4317 if (r)
4318 goto out;
4319
4320 r = -EFAULT;
4321 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4322 goto out;
4323 r = 0;
4324 break;
4325 }
313a3dc7
CO		 4326 default:
4327 r = -EINVAL;
4328 }
4329out:
d1ac91d8 4330 kfree(u.buffer);
9b062471
CD		 4331out_nofree:
4332 vcpu_put(vcpu);
313a3dc7
CO		 4333 return r;
4334}
4335
1499fa80 4336vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4337{
4338 return VM_FAULT_SIGBUS;
4339}
4340
1fe779f8
CO		 4341static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4342{
4343 int ret;
4344
4345 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4346 return -EINVAL;
1fe779f8
CO		 4347 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4348 return ret;
4349}
4350
b927a3ce
SY		 4351static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4352 u64 ident_addr)
4353{
2ac52ab8 4354 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4355}
4356
1fe779f8 4357static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4358 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4359{
4360 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4361 return -EINVAL;
4362
79fac95e 4363 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4364
4365 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4366 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4367
79fac95e 4368 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4369 return 0;
4370}
4371
bc8a3d89 4372static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4373{
39de71ec 4374 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4375}
4376
1fe779f8
CO		 4377static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4378{
90bca052 4379 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4380 int r;
4381
4382 r = 0;
4383 switch (chip->chip_id) {
4384 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4385 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4386 sizeof(struct kvm_pic_state));
4387 break;
4388 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4389 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4390 sizeof(struct kvm_pic_state));
4391 break;
4392 case KVM_IRQCHIP_IOAPIC:
33392b49 4393 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4394 break;
4395 default:
4396 r = -EINVAL;
4397 break;
4398 }
4399 return r;
4400}
4401
4402static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4403{
90bca052 4404 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4405 int r;
4406
4407 r = 0;
4408 switch (chip->chip_id) {
4409 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4410 spin_lock(&pic->lock);
4411 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4412 sizeof(struct kvm_pic_state));
90bca052 4413 spin_unlock(&pic->lock);
1fe779f8
CO		 4414 break;
4415 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4416 spin_lock(&pic->lock);
4417 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4418 sizeof(struct kvm_pic_state));
90bca052 4419 spin_unlock(&pic->lock);
1fe779f8
CO		 4420 break;
4421 case KVM_IRQCHIP_IOAPIC:
33392b49 4422 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4423 break;
4424 default:
4425 r = -EINVAL;
4426 break;
4427 }
90bca052 4428 kvm_pic_update_irq(pic);
1fe779f8
CO		 4429 return r;
4430}
4431
e0f63cb9
SY		 4432static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4433{
34f3941c
RK		 4434 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4435
4436 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4437
4438 mutex_lock(&kps->lock);
4439 memcpy(ps, &kps->channels, sizeof(*ps));
4440 mutex_unlock(&kps->lock);
2da29bcc 4441 return 0;
e0f63cb9
SY		 4442}
4443
4444static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4445{
0185604c 4446 int i;
09edea72
RK		 4447 struct kvm_pit *pit = kvm->arch.vpit;
4448
4449 mutex_lock(&pit->pit_state.lock);
34f3941c 4450 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4451 for (i = 0; i < 3; i++)
09edea72
RK		 4452 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4453 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4454 return 0;
e9f42757
BK		 4455}
4456
4457static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4458{
e9f42757
BK		 4459 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4460 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4461 sizeof(ps->channels));
4462 ps->flags = kvm->arch.vpit->pit_state.flags;
4463 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4464 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4465 return 0;
e9f42757
BK		 4466}
4467
4468static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4469{
2da29bcc 4470 int start = 0;
0185604c 4471 int i;
e9f42757 4472 u32 prev_legacy, cur_legacy;
09edea72
RK		 4473 struct kvm_pit *pit = kvm->arch.vpit;
4474
4475 mutex_lock(&pit->pit_state.lock);
4476 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4477 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4478 if (!prev_legacy && cur_legacy)
4479 start = 1;
09edea72
RK		 4480 memcpy(&pit->pit_state.channels, &ps->channels,
4481 sizeof(pit->pit_state.channels));
4482 pit->pit_state.flags = ps->flags;
0185604c 4483 for (i = 0; i < 3; i++)
09edea72 4484 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4485 start && i == 0);
09edea72 4486 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4487 return 0;
e0f63cb9
SY		 4488}
4489
52d939a0
MT		 4490static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4491 struct kvm_reinject_control *control)
4492{
71474e2f
RK		 4493 struct kvm_pit *pit = kvm->arch.vpit;
4494
4495 if (!pit)
52d939a0 4496 return -ENXIO;
b39c90b6 4497
71474e2f
RK		 4498 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4499 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4500 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4501 */
4502 mutex_lock(&pit->pit_state.lock);
4503 kvm_pit_set_reinject(pit, control->pit_reinject);
4504 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4505
52d939a0
MT		 4506 return 0;
4507}
4508
95d4c16c 4509/**
60c34612
TY		 4510 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4511 * @kvm: kvm instance
4512 * @log: slot id and address to which we copy the log
95d4c16c 4513 *
e108ff2f
PB		 4514 * Steps 1-4 below provide general overview of dirty page logging. See
4515 * kvm_get_dirty_log_protect() function description for additional details.
4516 *
4517 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4518 * always flush the TLB (step 4) even if previous step failed and the dirty
4519 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4520 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4521 * writes will be marked dirty for next log read.
95d4c16c 4522 *
60c34612
TY		 4523 * 1. Take a snapshot of the bit and clear it if needed.
4524 * 2. Write protect the corresponding page.
e108ff2f
PB		 4525 * 3. Copy the snapshot to the userspace.
4526 * 4. Flush TLB's if needed.
5bb064dc 4527 */
60c34612 4528int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4529{
8fe65a82 4530 bool flush = false;
e108ff2f 4531 int r;
5bb064dc 4532
79fac95e 4533 mutex_lock(&kvm->slots_lock);
5bb064dc 4534
88178fd4
KH		 4535 /*
4536 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4537 */
4538 if (kvm_x86_ops->flush_log_dirty)
4539 kvm_x86_ops->flush_log_dirty(kvm);
4540
8fe65a82 4541 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4542
4543 /*
4544 * All the TLBs can be flushed out of mmu lock, see the comments in
4545 * kvm_mmu_slot_remove_write_access().
4546 */
e108ff2f 4547 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4548 if (flush)
2a31b9db
PB		 4549 kvm_flush_remote_tlbs(kvm);
4550
4551 mutex_unlock(&kvm->slots_lock);
4552 return r;
4553}
4554
4555int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4556{
4557 bool flush = false;
4558 int r;
4559
4560 mutex_lock(&kvm->slots_lock);
4561
4562 /*
4563 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4564 */
4565 if (kvm_x86_ops->flush_log_dirty)
4566 kvm_x86_ops->flush_log_dirty(kvm);
4567
4568 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4569
4570 /*
4571 * All the TLBs can be flushed out of mmu lock, see the comments in
4572 * kvm_mmu_slot_remove_write_access().
4573 */
4574 lockdep_assert_held(&kvm->slots_lock);
4575 if (flush)
198c74f4
XG		 4576 kvm_flush_remote_tlbs(kvm);
4577
79fac95e 4578 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4579 return r;
4580}
4581
aa2fbe6d
YZ		 4582int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4583 bool line_status)
23d43cf9
CD		 4584{
4585 if (!irqchip_in_kernel(kvm))
4586 return -ENXIO;
4587
4588 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4589 irq_event->irq, irq_event->level,
4590 line_status);
23d43cf9
CD		 4591 return 0;
4592}
4593
e5d83c74
PB		 4594int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4595 struct kvm_enable_cap *cap)
90de4a18
NA		 4596{
4597 int r;
4598
4599 if (cap->flags)
4600 return -EINVAL;
4601
4602 switch (cap->cap) {
4603 case KVM_CAP_DISABLE_QUIRKS:
4604 kvm->arch.disabled_quirks = cap->args[0];
4605 r = 0;
4606 break;
49df6397
SR		 4607 case KVM_CAP_SPLIT_IRQCHIP: {
4608 mutex_lock(&kvm->lock);
b053b2ae
SR		 4609 r = -EINVAL;
4610 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4611 goto split_irqchip_unlock;
49df6397
SR		 4612 r = -EEXIST;
4613 if (irqchip_in_kernel(kvm))
4614 goto split_irqchip_unlock;
557abc40 4615 if (kvm->created_vcpus)
49df6397
SR		 4616 goto split_irqchip_unlock;
4617 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4618 if (r)
49df6397
SR		 4619 goto split_irqchip_unlock;
4620 /* Pairs with irqchip_in_kernel. */
4621 smp_wmb();
49776faf 4622 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4623 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4624 r = 0;
4625split_irqchip_unlock:
4626 mutex_unlock(&kvm->lock);
4627 break;
4628 }
37131313
RK		 4629 case KVM_CAP_X2APIC_API:
4630 r = -EINVAL;
4631 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4632 break;
4633
4634 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4635 kvm->arch.x2apic_format = true;
c519265f
RK		 4636 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4637 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4638
4639 r = 0;
4640 break;
4d5422ce
WL		 4641 case KVM_CAP_X86_DISABLE_EXITS:
4642 r = -EINVAL;
4643 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4644 break;
4645
4646 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4647 kvm_can_mwait_in_guest())
4648 kvm->arch.mwait_in_guest = true;
766d3571 4649 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4650 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4651 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4652 kvm->arch.pause_in_guest = true;
b5170063
WL		 4653 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4654 kvm->arch.cstate_in_guest = true;
4d5422ce
WL		 4655 r = 0;
4656 break;
6fbbde9a
DS		 4657 case KVM_CAP_MSR_PLATFORM_INFO:
4658 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4659 r = 0;
c4f55198
JM		 4660 break;
4661 case KVM_CAP_EXCEPTION_PAYLOAD:
4662 kvm->arch.exception_payload_enabled = cap->args[0];
4663 r = 0;
6fbbde9a 4664 break;
90de4a18
NA		 4665 default:
4666 r = -EINVAL;
4667 break;
4668 }
4669 return r;
4670}
4671
1fe779f8
CO		 4672long kvm_arch_vm_ioctl(struct file *filp,
4673 unsigned int ioctl, unsigned long arg)
4674{
4675 struct kvm *kvm = filp->private_data;
4676 void __user *argp = (void __user *)arg;
367e1319 4677 int r = -ENOTTY;
f0d66275
DH		 4678 /*
4679 * This union makes it completely explicit to gcc-3.x
4680 * that these two variables' stack usage should be
4681 * combined, not added together.
4682 */
4683 union {
4684 struct kvm_pit_state ps;
e9f42757 4685 struct kvm_pit_state2 ps2;
c5ff41ce 4686 struct kvm_pit_config pit_config;
f0d66275 4687 } u;
1fe779f8
CO		 4688
4689 switch (ioctl) {
4690 case KVM_SET_TSS_ADDR:
4691 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4692 break;
b927a3ce
SY		 4693 case KVM_SET_IDENTITY_MAP_ADDR: {
4694 u64 ident_addr;
4695
1af1ac91
DH		 4696 mutex_lock(&kvm->lock);
4697 r = -EINVAL;
4698 if (kvm->created_vcpus)
4699 goto set_identity_unlock;
b927a3ce 4700 r = -EFAULT;
0e96f31e 4701 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4702 goto set_identity_unlock;
b927a3ce 4703 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4704set_identity_unlock:
4705 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4706 break;
4707 }
1fe779f8
CO		 4708 case KVM_SET_NR_MMU_PAGES:
4709 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4710 break;
4711 case KVM_GET_NR_MMU_PAGES:
4712 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4713 break;
3ddea128 4714 case KVM_CREATE_IRQCHIP: {
3ddea128 4715 mutex_lock(&kvm->lock);
09941366 4716
3ddea128 4717 r = -EEXIST;
35e6eaa3 4718 if (irqchip_in_kernel(kvm))
3ddea128 4719 goto create_irqchip_unlock;
09941366 4720
3e515705 4721 r = -EINVAL;
557abc40 4722 if (kvm->created_vcpus)
3e515705 4723 goto create_irqchip_unlock;
09941366
RK		 4724
4725 r = kvm_pic_init(kvm);
4726 if (r)
3ddea128 4727 goto create_irqchip_unlock;
09941366
RK		 4728
4729 r = kvm_ioapic_init(kvm);
4730 if (r) {
09941366 4731 kvm_pic_destroy(kvm);
3ddea128 4732 goto create_irqchip_unlock;
09941366
RK		 4733 }
4734
399ec807
AK		 4735 r = kvm_setup_default_irq_routing(kvm);
4736 if (r) {
72bb2fcd 4737 kvm_ioapic_destroy(kvm);
09941366 4738 kvm_pic_destroy(kvm);
71ba994c 4739 goto create_irqchip_unlock;
399ec807 4740 }
49776faf 4741 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4742 smp_wmb();
49776faf 4743 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4744 create_irqchip_unlock:
4745 mutex_unlock(&kvm->lock);
1fe779f8 4746 break;
3ddea128 4747 }
7837699f 4748 case KVM_CREATE_PIT:
c5ff41ce
JK		 4749 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4750 goto create_pit;
4751 case KVM_CREATE_PIT2:
4752 r = -EFAULT;
4753 if (copy_from_user(&u.pit_config, argp,
4754 sizeof(struct kvm_pit_config)))
4755 goto out;
4756 create_pit:
250715a6 4757 mutex_lock(&kvm->lock);
269e05e4
AK		 4758 r = -EEXIST;
4759 if (kvm->arch.vpit)
4760 goto create_pit_unlock;
7837699f 4761 r = -ENOMEM;
c5ff41ce 4762 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4763 if (kvm->arch.vpit)
4764 r = 0;
269e05e4 4765 create_pit_unlock:
250715a6 4766 mutex_unlock(&kvm->lock);
7837699f 4767 break;
1fe779f8
CO		 4768 case KVM_GET_IRQCHIP: {
4769 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4770 struct kvm_irqchip *chip;
1fe779f8 4771
ff5c2c03
SL		 4772 chip = memdup_user(argp, sizeof(*chip));
4773 if (IS_ERR(chip)) {
4774 r = PTR_ERR(chip);
1fe779f8 4775 goto out;
ff5c2c03
SL		 4776 }
4777
1fe779f8 4778 r = -ENXIO;
826da321 4779 if (!irqchip_kernel(kvm))
f0d66275
DH		 4780 goto get_irqchip_out;
4781 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4782 if (r)
f0d66275 4783 goto get_irqchip_out;
1fe779f8 4784 r = -EFAULT;
0e96f31e 4785 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4786 goto get_irqchip_out;
1fe779f8 4787 r = 0;
f0d66275
DH		 4788 get_irqchip_out:
4789 kfree(chip);
1fe779f8
CO		 4790 break;
4791 }
4792 case KVM_SET_IRQCHIP: {
4793 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4794 struct kvm_irqchip *chip;
1fe779f8 4795
ff5c2c03
SL		 4796 chip = memdup_user(argp, sizeof(*chip));
4797 if (IS_ERR(chip)) {
4798 r = PTR_ERR(chip);
1fe779f8 4799 goto out;
ff5c2c03
SL		 4800 }
4801
1fe779f8 4802 r = -ENXIO;
826da321 4803 if (!irqchip_kernel(kvm))
f0d66275
DH		 4804 goto set_irqchip_out;
4805 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4806 if (r)
f0d66275 4807 goto set_irqchip_out;
1fe779f8 4808 r = 0;
f0d66275
DH		 4809 set_irqchip_out:
4810 kfree(chip);
1fe779f8
CO		 4811 break;
4812 }
e0f63cb9 4813 case KVM_GET_PIT: {
e0f63cb9 4814 r = -EFAULT;
f0d66275 4815 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4816 goto out;
4817 r = -ENXIO;
4818 if (!kvm->arch.vpit)
4819 goto out;
f0d66275 4820 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4821 if (r)
4822 goto out;
4823 r = -EFAULT;
f0d66275 4824 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4825 goto out;
4826 r = 0;
4827 break;
4828 }
4829 case KVM_SET_PIT: {
e0f63cb9 4830 r = -EFAULT;
0e96f31e 4831 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4832 goto out;
4833 r = -ENXIO;
4834 if (!kvm->arch.vpit)
4835 goto out;
f0d66275 4836 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4837 break;
4838 }
e9f42757
BK		 4839 case KVM_GET_PIT2: {
4840 r = -ENXIO;
4841 if (!kvm->arch.vpit)
4842 goto out;
4843 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4844 if (r)
4845 goto out;
4846 r = -EFAULT;
4847 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4848 goto out;
4849 r = 0;
4850 break;
4851 }
4852 case KVM_SET_PIT2: {
4853 r = -EFAULT;
4854 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4855 goto out;
4856 r = -ENXIO;
4857 if (!kvm->arch.vpit)
4858 goto out;
4859 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4860 break;
4861 }
52d939a0
MT		 4862 case KVM_REINJECT_CONTROL: {
4863 struct kvm_reinject_control control;
4864 r = -EFAULT;
4865 if (copy_from_user(&control, argp, sizeof(control)))
4866 goto out;
4867 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4868 break;
4869 }
d71ba788
PB		 4870 case KVM_SET_BOOT_CPU_ID:
4871 r = 0;
4872 mutex_lock(&kvm->lock);
557abc40 4873 if (kvm->created_vcpus)
d71ba788
PB		 4874 r = -EBUSY;
4875 else
4876 kvm->arch.bsp_vcpu_id = arg;
4877 mutex_unlock(&kvm->lock);
4878 break;
ffde22ac 4879 case KVM_XEN_HVM_CONFIG: {
51776043 4880 struct kvm_xen_hvm_config xhc;
ffde22ac 4881 r = -EFAULT;
51776043 4882 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4883 goto out;
4884 r = -EINVAL;
51776043 4885 if (xhc.flags)
ffde22ac 4886 goto out;
51776043 4887 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4888 r = 0;
4889 break;
4890 }
afbcf7ab 4891 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4892 struct kvm_clock_data user_ns;
4893 u64 now_ns;
afbcf7ab
GC		 4894
4895 r = -EFAULT;
4896 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4897 goto out;
4898
4899 r = -EINVAL;
4900 if (user_ns.flags)
4901 goto out;
4902
4903 r = 0;
0bc48bea
RK		 4904 /*
4905 * TODO: userspace has to take care of races with VCPU_RUN, so
4906 * kvm_gen_update_masterclock() can be cut down to locked
4907 * pvclock_update_vm_gtod_copy().
4908 */
4909 kvm_gen_update_masterclock(kvm);
e891a32e 4910 now_ns = get_kvmclock_ns(kvm);
108b249c 4911 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4912 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4913 break;
4914 }
4915 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4916 struct kvm_clock_data user_ns;
4917 u64 now_ns;
4918
e891a32e 4919 now_ns = get_kvmclock_ns(kvm);
108b249c 4920 user_ns.clock = now_ns;
e3fd9a93 4921 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4922 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4923
4924 r = -EFAULT;
4925 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4926 goto out;
4927 r = 0;
4928 break;
4929 }
5acc5c06
BS		 4930 case KVM_MEMORY_ENCRYPT_OP: {
4931 r = -ENOTTY;
4932 if (kvm_x86_ops->mem_enc_op)
4933 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4934 break;
4935 }
69eaedee
BS		 4936 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4937 struct kvm_enc_region region;
4938
4939 r = -EFAULT;
4940 if (copy_from_user(&region, argp, sizeof(region)))
4941 goto out;
4942
4943 r = -ENOTTY;
4944 if (kvm_x86_ops->mem_enc_reg_region)
4945 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4946 break;
4947 }
4948 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4949 struct kvm_enc_region region;
4950
4951 r = -EFAULT;
4952 if (copy_from_user(&region, argp, sizeof(region)))
4953 goto out;
4954
4955 r = -ENOTTY;
4956 if (kvm_x86_ops->mem_enc_unreg_region)
4957 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4958 break;
4959 }
faeb7833
RK		 4960 case KVM_HYPERV_EVENTFD: {
4961 struct kvm_hyperv_eventfd hvevfd;
4962
4963 r = -EFAULT;
4964 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4965 goto out;
4966 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4967 break;
4968 }
66bb8a06
EH		 4969 case KVM_SET_PMU_EVENT_FILTER:
4970 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
4971 break;
1fe779f8 4972 default:
ad6260da 4973 r = -ENOTTY;
1fe779f8
CO		 4974 }
4975out:
4976 return r;
4977}
4978
a16b043c 4979static void kvm_init_msr_list(void)
043405e1
CO		 4980{
4981 u32 dummy[2];
4982 unsigned i, j;
4983
62ef68bb 4984 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4985 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4986 continue;
93c4adc7
PB		 4987
4988 /*
4989 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4990 * to the guests in some cases.
93c4adc7
PB		 4991 */
4992 switch (msrs_to_save[i]) {
4993 case MSR_IA32_BNDCFGS:
503234b3 4994 if (!kvm_mpx_supported())
93c4adc7
PB		 4995 continue;
4996 break;
9dbe6cf9
PB		 4997 case MSR_TSC_AUX:
4998 if (!kvm_x86_ops->rdtscp_supported())
4999 continue;
5000 break;
bf8c55d8
CP		 5001 case MSR_IA32_RTIT_CTL:
5002 case MSR_IA32_RTIT_STATUS:
5003 if (!kvm_x86_ops->pt_supported())
5004 continue;
5005 break;
5006 case MSR_IA32_RTIT_CR3_MATCH:
5007 if (!kvm_x86_ops->pt_supported() ||
5008 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5009 continue;
5010 break;
5011 case MSR_IA32_RTIT_OUTPUT_BASE:
5012 case MSR_IA32_RTIT_OUTPUT_MASK:
5013 if (!kvm_x86_ops->pt_supported() ||
5014 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5015 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5016 continue;
5017 break;
5018 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5019 if (!kvm_x86_ops->pt_supported() ||
5020 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5021 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5022 continue;
5023 break;
5024 }
93c4adc7
PB		 5025 default:
5026 break;
5027 }
5028
043405e1
CO		 5029 if (j < i)
5030 msrs_to_save[j] = msrs_to_save[i];
5031 j++;
5032 }
5033 num_msrs_to_save = j;
62ef68bb
PB		 5034
5035 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 5036 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5037 continue;
62ef68bb
PB		 5038
5039 if (j < i)
5040 emulated_msrs[j] = emulated_msrs[i];
5041 j++;
5042 }
5043 num_emulated_msrs = j;
801e459a
TL		 5044
5045 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5046 struct kvm_msr_entry msr;
5047
5048 msr.index = msr_based_features[i];
66421c1e 5049 if (kvm_get_msr_feature(&msr))
801e459a
TL		 5050 continue;
5051
5052 if (j < i)
5053 msr_based_features[j] = msr_based_features[i];
5054 j++;
5055 }
5056 num_msr_based_features = j;
043405e1
CO		 5057}
5058
bda9020e
MT		 5059static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5060 const void *v)
bbd9b64e 5061{
70252a10
AK		 5062 int handled = 0;
5063 int n;
5064
5065 do {
5066 n = min(len, 8);
bce87cce 5067 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5068 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5069 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 5070 break;
5071 handled += n;
5072 addr += n;
5073 len -= n;
5074 v += n;
5075 } while (len);
bbd9b64e 5076
70252a10 5077 return handled;
bbd9b64e
CO		 5078}
5079
bda9020e 5080static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 5081{
70252a10
AK		 5082 int handled = 0;
5083 int n;
5084
5085 do {
5086 n = min(len, 8);
bce87cce 5087 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5088 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5089 addr, n, v))
5090 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5091 break;
e39d200f 5092 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5093 handled += n;
5094 addr += n;
5095 len -= n;
5096 v += n;
5097 } while (len);
bbd9b64e 5098
70252a10 5099 return handled;
bbd9b64e
CO		 5100}
5101
2dafc6c2
GN		 5102static void kvm_set_segment(struct kvm_vcpu *vcpu,
5103 struct kvm_segment *var, int seg)
5104{
5105 kvm_x86_ops->set_segment(vcpu, var, seg);
5106}
5107
5108void kvm_get_segment(struct kvm_vcpu *vcpu,
5109 struct kvm_segment *var, int seg)
5110{
5111 kvm_x86_ops->get_segment(vcpu, var, seg);
5112}
5113
54987b7a
PB		 5114gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5115 struct x86_exception *exception)
02f59dc9
JR		 5116{
5117 gpa_t t_gpa;
02f59dc9
JR		 5118
5119 BUG_ON(!mmu_is_nested(vcpu));
5120
5121 /* NPT walks are always user-walks */
5122 access |= PFERR_USER_MASK;
44dd3ffa 5123 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5124
5125 return t_gpa;
5126}
5127
ab9ae313
AK		 5128gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5129 struct x86_exception *exception)
1871c602
GN		 5130{
5131 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5132 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5133}
5134
ab9ae313
AK		 5135 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5136 struct x86_exception *exception)
1871c602
GN		 5137{
5138 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5139 access |= PFERR_FETCH_MASK;
ab9ae313 5140 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5141}
5142
ab9ae313
AK		 5143gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5144 struct x86_exception *exception)
1871c602
GN		 5145{
5146 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5147 access |= PFERR_WRITE_MASK;
ab9ae313 5148 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5149}
5150
5151/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5152gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5153 struct x86_exception *exception)
1871c602 5154{
ab9ae313 5155 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5156}
5157
5158static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5159 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5160 struct x86_exception *exception)
bbd9b64e
CO		 5161{
5162 void *data = val;
10589a46 5163 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5164
5165 while (bytes) {
14dfe855 5166 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5167 exception);
bbd9b64e 5168 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5169 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5170 int ret;
5171
bcc55cba 5172 if (gpa == UNMAPPED_GVA)
ab9ae313 5173 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5174 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5175 offset, toread);
10589a46 5176 if (ret < 0) {
c3cd7ffa 5177 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5178 goto out;
5179 }
bbd9b64e 5180
77c2002e
IE		 5181 bytes -= toread;
5182 data += toread;
5183 addr += toread;
bbd9b64e 5184 }
10589a46 5185out:
10589a46 5186 return r;
bbd9b64e 5187}
77c2002e 5188
1871c602 5189/* used for instruction fetching */
0f65dd70
AK		 5190static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5191 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5192 struct x86_exception *exception)
1871c602 5193{
0f65dd70 5194 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5195 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5196 unsigned offset;
5197 int ret;
0f65dd70 5198
44583cba
PB		 5199 /* Inline kvm_read_guest_virt_helper for speed. */
5200 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5201 exception);
5202 if (unlikely(gpa == UNMAPPED_GVA))
5203 return X86EMUL_PROPAGATE_FAULT;
5204
5205 offset = addr & (PAGE_SIZE-1);
5206 if (WARN_ON(offset + bytes > PAGE_SIZE))
5207 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5208 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5209 offset, bytes);
44583cba
PB		 5210 if (unlikely(ret < 0))
5211 return X86EMUL_IO_NEEDED;
5212
5213 return X86EMUL_CONTINUE;
1871c602
GN		 5214}
5215
ce14e868 5216int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5217 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5218 struct x86_exception *exception)
1871c602
GN		 5219{
5220 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5221
353c0956
PB		 5222 /*
5223 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5224 * is returned, but our callers are not ready for that and they blindly
5225 * call kvm_inject_page_fault. Ensure that they at least do not leak
5226 * uninitialized kernel stack memory into cr2 and error code.
5227 */
5228 memset(exception, 0, sizeof(*exception));
1871c602 5229 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5230 exception);
1871c602 5231}
064aea77 5232EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5233
ce14e868
PB		 5234static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5235 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5236 struct x86_exception *exception, bool system)
1871c602 5237{
0f65dd70 5238 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5239 u32 access = 0;
5240
5241 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5242 access |= PFERR_USER_MASK;
5243
5244 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5245}
5246
7a036a6f
RK		 5247static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5248 unsigned long addr, void *val, unsigned int bytes)
5249{
5250 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5251 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5252
5253 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5254}
5255
ce14e868
PB		 5256static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5257 struct kvm_vcpu *vcpu, u32 access,
5258 struct x86_exception *exception)
77c2002e
IE		 5259{
5260 void *data = val;
5261 int r = X86EMUL_CONTINUE;
5262
5263 while (bytes) {
14dfe855 5264 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5265 access,
ab9ae313 5266 exception);
77c2002e
IE		 5267 unsigned offset = addr & (PAGE_SIZE-1);
5268 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5269 int ret;
5270
bcc55cba 5271 if (gpa == UNMAPPED_GVA)
ab9ae313 5272 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5273 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5274 if (ret < 0) {
c3cd7ffa 5275 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5276 goto out;
5277 }
5278
5279 bytes -= towrite;
5280 data += towrite;
5281 addr += towrite;
5282 }
5283out:
5284 return r;
5285}
ce14e868
PB		 5286
5287static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5288 unsigned int bytes, struct x86_exception *exception,
5289 bool system)
ce14e868
PB		 5290{
5291 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5292 u32 access = PFERR_WRITE_MASK;
5293
5294 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5295 access |= PFERR_USER_MASK;
ce14e868
PB		 5296
5297 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5298 access, exception);
ce14e868
PB		 5299}
5300
5301int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5302 unsigned int bytes, struct x86_exception *exception)
5303{
c595ceee
PB		 5304 /* kvm_write_guest_virt_system can pull in tons of pages. */
5305 vcpu->arch.l1tf_flush_l1d = true;
5306
ce14e868
PB		 5307 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5308 PFERR_WRITE_MASK, exception);
5309}
6a4d7550 5310EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5311
082d06ed
WL		 5312int handle_ud(struct kvm_vcpu *vcpu)
5313{
6c86eedc 5314 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5315 enum emulation_result er;
6c86eedc
WL		 5316 char sig[5]; /* ud2; .ascii "kvm" */
5317 struct x86_exception e;
5318
5319 if (force_emulation_prefix &&
3c9fa24c
PB		 5320 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5321 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5322 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5323 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5324 emul_type = 0;
5325 }
082d06ed 5326
0ce97a2b 5327 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5328 if (er == EMULATE_USER_EXIT)
5329 return 0;
5330 if (er != EMULATE_DONE)
5331 kvm_queue_exception(vcpu, UD_VECTOR);
5332 return 1;
5333}
5334EXPORT_SYMBOL_GPL(handle_ud);
5335
0f89b207
TL		 5336static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5337 gpa_t gpa, bool write)
5338{
5339 /* For APIC access vmexit */
5340 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5341 return 1;
5342
5343 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5344 trace_vcpu_match_mmio(gva, gpa, write, true);
5345 return 1;
5346 }
5347
5348 return 0;
5349}
5350
af7cc7d1
XG		 5351static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5352 gpa_t *gpa, struct x86_exception *exception,
5353 bool write)
5354{
97d64b78
AK		 5355 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5356 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5357
be94f6b7
HH		 5358 /*
5359 * currently PKRU is only applied to ept enabled guest so
5360 * there is no pkey in EPT page table for L1 guest or EPT
5361 * shadow page table for L2 guest.
5362 */
97d64b78 5363 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5364 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5365 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5366 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5367 (gva & (PAGE_SIZE - 1));
4f022648 5368 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5369 return 1;
5370 }
5371
af7cc7d1
XG		 5372 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5373
5374 if (*gpa == UNMAPPED_GVA)
5375 return -1;
5376
0f89b207 5377 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5378}
5379
3200f405 5380int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5381 const void *val, int bytes)
bbd9b64e
CO		 5382{
5383 int ret;
5384
54bf36aa 5385 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5386 if (ret < 0)
bbd9b64e 5387 return 0;
0eb05bf2 5388 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5389 return 1;
5390}
5391
77d197b2
XG		 5392struct read_write_emulator_ops {
5393 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5394 int bytes);
5395 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5396 void *val, int bytes);
5397 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5398 int bytes, void *val);
5399 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5400 void *val, int bytes);
5401 bool write;
5402};
5403
5404static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5405{
5406 if (vcpu->mmio_read_completed) {
77d197b2 5407 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5408 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5409 vcpu->mmio_read_completed = 0;
5410 return 1;
5411 }
5412
5413 return 0;
5414}
5415
5416static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5417 void *val, int bytes)
5418{
54bf36aa 5419 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5420}
5421
5422static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5423 void *val, int bytes)
5424{
5425 return emulator_write_phys(vcpu, gpa, val, bytes);
5426}
5427
5428static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5429{
e39d200f 5430 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5431 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5432}
5433
5434static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5435 void *val, int bytes)
5436{
e39d200f 5437 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5438 return X86EMUL_IO_NEEDED;
5439}
5440
5441static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5442 void *val, int bytes)
5443{
f78146b0
AK		 5444 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5445
87da7e66 5446 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5447 return X86EMUL_CONTINUE;
5448}
5449
0fbe9b0b 5450static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5451 .read_write_prepare = read_prepare,
5452 .read_write_emulate = read_emulate,
5453 .read_write_mmio = vcpu_mmio_read,
5454 .read_write_exit_mmio = read_exit_mmio,
5455};
5456
0fbe9b0b 5457static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5458 .read_write_emulate = write_emulate,
5459 .read_write_mmio = write_mmio,
5460 .read_write_exit_mmio = write_exit_mmio,
5461 .write = true,
5462};
5463
22388a3c
XG		 5464static int emulator_read_write_onepage(unsigned long addr, void *val,
5465 unsigned int bytes,
5466 struct x86_exception *exception,
5467 struct kvm_vcpu *vcpu,
0fbe9b0b 5468 const struct read_write_emulator_ops *ops)
bbd9b64e 5469{
af7cc7d1
XG		 5470 gpa_t gpa;
5471 int handled, ret;
22388a3c 5472 bool write = ops->write;
f78146b0 5473 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5474 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5475
5476 /*
5477 * If the exit was due to a NPF we may already have a GPA.
5478 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5479 * Note, this cannot be used on string operations since string
5480 * operation using rep will only have the initial GPA from the NPF
5481 * occurred.
5482 */
5483 if (vcpu->arch.gpa_available &&
5484 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5485 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5486 gpa = vcpu->arch.gpa_val;
5487 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5488 } else {
5489 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5490 if (ret < 0)
5491 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5492 }
10589a46 5493
618232e2 5494 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5495 return X86EMUL_CONTINUE;
5496
bbd9b64e
CO		 5497 /*
5498 * Is this MMIO handled locally?
5499 */
22388a3c 5500 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5501 if (handled == bytes)
bbd9b64e 5502 return X86EMUL_CONTINUE;
bbd9b64e 5503
70252a10
AK		 5504 gpa += handled;
5505 bytes -= handled;
5506 val += handled;
5507
87da7e66
XG		 5508 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5509 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5510 frag->gpa = gpa;
5511 frag->data = val;
5512 frag->len = bytes;
f78146b0 5513 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5514}
5515
52eb5a6d
XL		 5516static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5517 unsigned long addr,
22388a3c
XG		 5518 void *val, unsigned int bytes,
5519 struct x86_exception *exception,
0fbe9b0b 5520 const struct read_write_emulator_ops *ops)
bbd9b64e 5521{
0f65dd70 5522 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5523 gpa_t gpa;
5524 int rc;
5525
5526 if (ops->read_write_prepare &&
5527 ops->read_write_prepare(vcpu, val, bytes))
5528 return X86EMUL_CONTINUE;
5529
5530 vcpu->mmio_nr_fragments = 0;
0f65dd70 5531
bbd9b64e
CO		 5532 /* Crossing a page boundary? */
5533 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5534 int now;
bbd9b64e
CO		 5535
5536 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5537 rc = emulator_read_write_onepage(addr, val, now, exception,
5538 vcpu, ops);
5539
bbd9b64e
CO		 5540 if (rc != X86EMUL_CONTINUE)
5541 return rc;
5542 addr += now;
bac15531
NA		 5543 if (ctxt->mode != X86EMUL_MODE_PROT64)
5544 addr = (u32)addr;
bbd9b64e
CO		 5545 val += now;
5546 bytes -= now;
5547 }
22388a3c 5548
f78146b0
AK		 5549 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5550 vcpu, ops);
5551 if (rc != X86EMUL_CONTINUE)
5552 return rc;
5553
5554 if (!vcpu->mmio_nr_fragments)
5555 return rc;
5556
5557 gpa = vcpu->mmio_fragments[0].gpa;
5558
5559 vcpu->mmio_needed = 1;
5560 vcpu->mmio_cur_fragment = 0;
5561
87da7e66 5562 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5563 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5564 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5565 vcpu->run->mmio.phys_addr = gpa;
5566
5567 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5568}
5569
5570static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5571 unsigned long addr,
5572 void *val,
5573 unsigned int bytes,
5574 struct x86_exception *exception)
5575{
5576 return emulator_read_write(ctxt, addr, val, bytes,
5577 exception, &read_emultor);
5578}
5579
52eb5a6d 5580static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5581 unsigned long addr,
5582 const void *val,
5583 unsigned int bytes,
5584 struct x86_exception *exception)
5585{
5586 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5587 exception, &write_emultor);
bbd9b64e 5588}
bbd9b64e 5589
daea3e73
AK		 5590#define CMPXCHG_TYPE(t, ptr, old, new) \
5591 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5592
5593#ifdef CONFIG_X86_64
5594# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5595#else
5596# define CMPXCHG64(ptr, old, new) \
9749a6c0 5597 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5598#endif
5599
0f65dd70
AK		 5600static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5601 unsigned long addr,
bbd9b64e
CO		 5602 const void *old,
5603 const void *new,
5604 unsigned int bytes,
0f65dd70 5605 struct x86_exception *exception)
bbd9b64e 5606{
42e35f80 5607 struct kvm_host_map map;
0f65dd70 5608 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73 5609 gpa_t gpa;
daea3e73
AK		 5610 char *kaddr;
5611 bool exchanged;
2bacc55c 5612
daea3e73
AK		 5613 /* guests cmpxchg8b have to be emulated atomically */
5614 if (bytes > 8 || (bytes & (bytes - 1)))
5615 goto emul_write;
10589a46 5616
daea3e73 5617 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5618
daea3e73
AK		 5619 if (gpa == UNMAPPED_GVA ||
5620 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5621 goto emul_write;
2bacc55c 5622
daea3e73
AK		 5623 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5624 goto emul_write;
72dc67a6 5625
42e35f80 5626 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
c19b8bd6 5627 goto emul_write;
72dc67a6 5628
42e35f80
KA		 5629 kaddr = map.hva + offset_in_page(gpa);
5630
daea3e73
AK		 5631 switch (bytes) {
5632 case 1:
5633 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5634 break;
5635 case 2:
5636 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5637 break;
5638 case 4:
5639 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5640 break;
5641 case 8:
5642 exchanged = CMPXCHG64(kaddr, old, new);
5643 break;
5644 default:
5645 BUG();
2bacc55c 5646 }
42e35f80
KA		 5647
5648 kvm_vcpu_unmap(vcpu, &map, true);
daea3e73
AK		 5649
5650 if (!exchanged)
5651 return X86EMUL_CMPXCHG_FAILED;
5652
0eb05bf2 5653 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5654
5655 return X86EMUL_CONTINUE;
4a5f48f6 5656
3200f405 5657emul_write:
daea3e73 5658 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5659
0f65dd70 5660 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5661}
5662
cf8f70bf
GN		 5663static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5664{
cbfc6c91 5665 int r = 0, i;
cf8f70bf 5666
cbfc6c91
WL		 5667 for (i = 0; i < vcpu->arch.pio.count; i++) {
5668 if (vcpu->arch.pio.in)
5669 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5670 vcpu->arch.pio.size, pd);
5671 else
5672 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5673 vcpu->arch.pio.port, vcpu->arch.pio.size,
5674 pd);
5675 if (r)
5676 break;
5677 pd += vcpu->arch.pio.size;
5678 }
cf8f70bf
GN		 5679 return r;
5680}
5681
6f6fbe98
XG		 5682static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5683 unsigned short port, void *val,
5684 unsigned int count, bool in)
cf8f70bf 5685{
cf8f70bf 5686 vcpu->arch.pio.port = port;
6f6fbe98 5687 vcpu->arch.pio.in = in;
7972995b 5688 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5689 vcpu->arch.pio.size = size;
5690
5691 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5692 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5693 return 1;
5694 }
5695
5696 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5697 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5698 vcpu->run->io.size = size;
5699 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5700 vcpu->run->io.count = count;
5701 vcpu->run->io.port = port;
5702
5703 return 0;
5704}
5705
6f6fbe98
XG		 5706static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5707 int size, unsigned short port, void *val,
5708 unsigned int count)
cf8f70bf 5709{
ca1d4a9e 5710 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5711 int ret;
ca1d4a9e 5712
6f6fbe98
XG		 5713 if (vcpu->arch.pio.count)
5714 goto data_avail;
cf8f70bf 5715
cbfc6c91
WL		 5716 memset(vcpu->arch.pio_data, 0, size * count);
5717
6f6fbe98
XG		 5718 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5719 if (ret) {
5720data_avail:
5721 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5722 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5723 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5724 return 1;
5725 }
5726
cf8f70bf
GN		 5727 return 0;
5728}
5729
6f6fbe98
XG		 5730static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5731 int size, unsigned short port,
5732 const void *val, unsigned int count)
5733{
5734 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5735
5736 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5737 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5738 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5739}
5740
bbd9b64e
CO		 5741static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5742{
5743 return kvm_x86_ops->get_segment_base(vcpu, seg);
5744}
5745
3cb16fe7 5746static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5747{
3cb16fe7 5748 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5749}
5750
ae6a2375 5751static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5752{
5753 if (!need_emulate_wbinvd(vcpu))
5754 return X86EMUL_CONTINUE;
5755
5756 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5757 int cpu = get_cpu();
5758
5759 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5760 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5761 wbinvd_ipi, NULL, 1);
2eec7343 5762 put_cpu();
f5f48ee1 5763 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5764 } else
5765 wbinvd();
f5f48ee1
SY		 5766 return X86EMUL_CONTINUE;
5767}
5cb56059
JS		 5768
5769int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5770{
6affcbed
KH		 5771 kvm_emulate_wbinvd_noskip(vcpu);
5772 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5773}
f5f48ee1
SY		 5774EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5775
5cb56059
JS		 5776
5777
bcaf5cc5
AK		 5778static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5779{
5cb56059 5780 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5781}
5782
52eb5a6d
XL		 5783static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5784 unsigned long *dest)
bbd9b64e 5785{
16f8a6f9 5786 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5787}
5788
52eb5a6d
XL		 5789static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5790 unsigned long value)
bbd9b64e 5791{
338dbc97 5792
717746e3 5793 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5794}
5795
52a46617 5796static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5797{
52a46617 5798 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5799}
5800
717746e3 5801static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5802{
717746e3 5803 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5804 unsigned long value;
5805
5806 switch (cr) {
5807 case 0:
5808 value = kvm_read_cr0(vcpu);
5809 break;
5810 case 2:
5811 value = vcpu->arch.cr2;
5812 break;
5813 case 3:
9f8fe504 5814 value = kvm_read_cr3(vcpu);
52a46617
GN		 5815 break;
5816 case 4:
5817 value = kvm_read_cr4(vcpu);
5818 break;
5819 case 8:
5820 value = kvm_get_cr8(vcpu);
5821 break;
5822 default:
a737f256 5823 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5824 return 0;
5825 }
5826
5827 return value;
5828}
5829
717746e3 5830static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5831{
717746e3 5832 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5833 int res = 0;
5834
52a46617
GN		 5835 switch (cr) {
5836 case 0:
49a9b07e 5837 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5838 break;
5839 case 2:
5840 vcpu->arch.cr2 = val;
5841 break;
5842 case 3:
2390218b 5843 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5844 break;
5845 case 4:
a83b29c6 5846 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5847 break;
5848 case 8:
eea1cff9 5849 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5850 break;
5851 default:
a737f256 5852 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5853 res = -1;
52a46617 5854 }
0f12244f
GN		 5855
5856 return res;
52a46617
GN		 5857}
5858
717746e3 5859static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5860{
717746e3 5861 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5862}
5863
4bff1e86 5864static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5865{
4bff1e86 5866 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5867}
5868
4bff1e86 5869static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5870{
4bff1e86 5871 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5872}
5873
1ac9d0cf
AK		 5874static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5875{
5876 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5877}
5878
5879static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5880{
5881 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5882}
5883
4bff1e86
AK		 5884static unsigned long emulator_get_cached_segment_base(
5885 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5886{
4bff1e86 5887 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5888}
5889
1aa36616
AK		 5890static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5891 struct desc_struct *desc, u32 *base3,
5892 int seg)
2dafc6c2
GN		 5893{
5894 struct kvm_segment var;
5895
4bff1e86 5896 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5897 *selector = var.selector;
2dafc6c2 5898
378a8b09
GN		 5899 if (var.unusable) {
5900 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5901 if (base3)
5902 *base3 = 0;
2dafc6c2 5903 return false;
378a8b09 5904 }
2dafc6c2
GN		 5905
5906 if (var.g)
5907 var.limit >>= 12;
5908 set_desc_limit(desc, var.limit);
5909 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5910#ifdef CONFIG_X86_64
5911 if (base3)
5912 *base3 = var.base >> 32;
5913#endif
2dafc6c2
GN		 5914 desc->type = var.type;
5915 desc->s = var.s;
5916 desc->dpl = var.dpl;
5917 desc->p = var.present;
5918 desc->avl = var.avl;
5919 desc->l = var.l;
5920 desc->d = var.db;
5921 desc->g = var.g;
5922
5923 return true;
5924}
5925
1aa36616
AK		 5926static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5927 struct desc_struct *desc, u32 base3,
5928 int seg)
2dafc6c2 5929{
4bff1e86 5930 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5931 struct kvm_segment var;
5932
1aa36616 5933 var.selector = selector;
2dafc6c2 5934 var.base = get_desc_base(desc);
5601d05b
GN		 5935#ifdef CONFIG_X86_64
5936 var.base |= ((u64)base3) << 32;
5937#endif
2dafc6c2
GN		 5938 var.limit = get_desc_limit(desc);
5939 if (desc->g)
5940 var.limit = (var.limit << 12) | 0xfff;
5941 var.type = desc->type;
2dafc6c2
GN		 5942 var.dpl = desc->dpl;
5943 var.db = desc->d;
5944 var.s = desc->s;
5945 var.l = desc->l;
5946 var.g = desc->g;
5947 var.avl = desc->avl;
5948 var.present = desc->p;
5949 var.unusable = !var.present;
5950 var.padding = 0;
5951
5952 kvm_set_segment(vcpu, &var, seg);
5953 return;
5954}
5955
717746e3
AK		 5956static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5957 u32 msr_index, u64 *pdata)
5958{
609e36d3
PB		 5959 struct msr_data msr;
5960 int r;
5961
5962 msr.index = msr_index;
5963 msr.host_initiated = false;
5964 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5965 if (r)
5966 return r;
5967
5968 *pdata = msr.data;
5969 return 0;
717746e3
AK		 5970}
5971
5972static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5973 u32 msr_index, u64 data)
5974{
8fe8ab46
WA		 5975 struct msr_data msr;
5976
5977 msr.data = data;
5978 msr.index = msr_index;
5979 msr.host_initiated = false;
5980 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5981}
5982
64d60670
PB		 5983static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5984{
5985 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5986
5987 return vcpu->arch.smbase;
5988}
5989
5990static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5991{
5992 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5993
5994 vcpu->arch.smbase = smbase;
5995}
5996
67f4d428
NA		 5997static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5998 u32 pmc)
5999{
c6702c9d 6000 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 6001}
6002
222d21aa
AK		 6003static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6004 u32 pmc, u64 *pdata)
6005{
c6702c9d 6006 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 6007}
6008
6c3287f7
AK		 6009static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6010{
6011 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6012}
6013
2953538e 6014static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 6015 struct x86_instruction_info *info,
c4f035c6
AK		 6016 enum x86_intercept_stage stage)
6017{
2953538e 6018 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 6019}
6020
e911eb3b
YZ		 6021static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6022 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 6023{
e911eb3b 6024 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 6025}
6026
dd856efa
AK		 6027static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6028{
6029 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6030}
6031
6032static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6033{
6034 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6035}
6036
801806d9
NA		 6037static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6038{
6039 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6040}
6041
6ed071f0
LP		 6042static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6043{
6044 return emul_to_vcpu(ctxt)->arch.hflags;
6045}
6046
6047static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6048{
c5833c7a 6049 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 6050}
6051
ed19321f
SC		 6052static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6053 const char *smstate)
0234bf88 6054{
ed19321f 6055 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 6056}
6057
c5833c7a
SC		 6058static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6059{
6060 kvm_smm_changed(emul_to_vcpu(ctxt));
6061}
6062
0225fb50 6063static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 6064 .read_gpr = emulator_read_gpr,
6065 .write_gpr = emulator_write_gpr,
ce14e868
PB		 6066 .read_std = emulator_read_std,
6067 .write_std = emulator_write_std,
7a036a6f 6068 .read_phys = kvm_read_guest_phys_system,
1871c602 6069 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 6070 .read_emulated = emulator_read_emulated,
6071 .write_emulated = emulator_write_emulated,
6072 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 6073 .invlpg = emulator_invlpg,
cf8f70bf
GN		 6074 .pio_in_emulated = emulator_pio_in_emulated,
6075 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 6076 .get_segment = emulator_get_segment,
6077 .set_segment = emulator_set_segment,
5951c442 6078 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 6079 .get_gdt = emulator_get_gdt,
160ce1f1 6080 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 6081 .set_gdt = emulator_set_gdt,
6082 .set_idt = emulator_set_idt,
52a46617
GN		 6083 .get_cr = emulator_get_cr,
6084 .set_cr = emulator_set_cr,
9c537244 6085 .cpl = emulator_get_cpl,
35aa5375
GN		 6086 .get_dr = emulator_get_dr,
6087 .set_dr = emulator_set_dr,
64d60670
PB		 6088 .get_smbase = emulator_get_smbase,
6089 .set_smbase = emulator_set_smbase,
717746e3
AK		 6090 .set_msr = emulator_set_msr,
6091 .get_msr = emulator_get_msr,
67f4d428 6092 .check_pmc = emulator_check_pmc,
222d21aa 6093 .read_pmc = emulator_read_pmc,
6c3287f7 6094 .halt = emulator_halt,
bcaf5cc5 6095 .wbinvd = emulator_wbinvd,
d6aa1000 6096 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6097 .intercept = emulator_intercept,
bdb42f5a 6098 .get_cpuid = emulator_get_cpuid,
801806d9 6099 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6100 .get_hflags = emulator_get_hflags,
6101 .set_hflags = emulator_set_hflags,
0234bf88 6102 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6103 .post_leave_smm = emulator_post_leave_smm,
bbd9b64e
CO		 6104};
6105
95cb2295
GN		 6106static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6107{
37ccdcbe 6108 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6109 /*
6110 * an sti; sti; sequence only disable interrupts for the first
6111 * instruction. So, if the last instruction, be it emulated or
6112 * not, left the system with the INT_STI flag enabled, it
6113 * means that the last instruction is an sti. We should not
6114 * leave the flag on in this case. The same goes for mov ss
6115 */
37ccdcbe
PB		 6116 if (int_shadow & mask)
6117 mask = 0;
6addfc42 6118 if (unlikely(int_shadow || mask)) {
95cb2295 6119 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6120 if (!mask)
6121 kvm_make_request(KVM_REQ_EVENT, vcpu);
6122 }
95cb2295
GN		 6123}
6124
ef54bcfe 6125static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6126{
6127 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6128 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6129 return kvm_propagate_fault(vcpu, &ctxt->exception);
6130
6131 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6132 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6133 ctxt->exception.error_code);
54b8486f 6134 else
da9cb575 6135 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6136 return false;
54b8486f
GN		 6137}
6138
8ec4722d
MG		 6139static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6140{
adf52235 6141 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6142 int cs_db, cs_l;
6143
8ec4722d
MG		 6144 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6145
adf52235 6146 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6147 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6148
adf52235
TY		 6149 ctxt->eip = kvm_rip_read(vcpu);
6150 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6151 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6152 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6153 cs_db ? X86EMUL_MODE_PROT32 :
6154 X86EMUL_MODE_PROT16;
a584539b 6155 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6156 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6157 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6158
dd856efa 6159 init_decode_cache(ctxt);
7ae441ea 6160 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6161}
6162
71f9833b 6163int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6164{
9d74191a 6165 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6166 int ret;
6167
6168 init_emulate_ctxt(vcpu);
6169
9dac77fa
AK		 6170 ctxt->op_bytes = 2;
6171 ctxt->ad_bytes = 2;
6172 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6173 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6174
6175 if (ret != X86EMUL_CONTINUE)
6176 return EMULATE_FAIL;
6177
9dac77fa 6178 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6179 kvm_rip_write(vcpu, ctxt->eip);
6180 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6181
63995653
MG		 6182 return EMULATE_DONE;
6183}
6184EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6185
e2366171 6186static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6187{
fc3a9157
JR		 6188 int r = EMULATE_DONE;
6189
6d77dbfc
GN		 6190 ++vcpu->stat.insn_emulation_fail;
6191 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6192
6193 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6194 return EMULATE_FAIL;
6195
a2b9e6c1 6196 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6197 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6198 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6199 vcpu->run->internal.ndata = 0;
1f4dcb3b 6200 r = EMULATE_USER_EXIT;
fc3a9157 6201 }
e2366171 6202
6d77dbfc 6203 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6204
6205 return r;
6d77dbfc
GN		 6206}
6207
93c05d3e 6208static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6209 bool write_fault_to_shadow_pgtable,
6210 int emulation_type)
a6f177ef 6211{
95b3cf69 6212 gpa_t gpa = cr2;
ba049e93 6213 kvm_pfn_t pfn;
a6f177ef 6214
384bf221 6215 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6216 return false;
6217
6c3dfeb6
SC		 6218 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6219 return false;
6220
44dd3ffa 6221 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6222 /*
6223 * Write permission should be allowed since only
6224 * write access need to be emulated.
6225 */
6226 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6227
95b3cf69
XG		 6228 /*
6229 * If the mapping is invalid in guest, let cpu retry
6230 * it to generate fault.
6231 */
6232 if (gpa == UNMAPPED_GVA)
6233 return true;
6234 }
a6f177ef 6235
8e3d9d06
XG		 6236 /*
6237 * Do not retry the unhandleable instruction if it faults on the
6238 * readonly host memory, otherwise it will goto a infinite loop:
6239 * retry instruction -> write #PF -> emulation fail -> retry
6240 * instruction -> ...
6241 */
6242 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6243
6244 /*
6245 * If the instruction failed on the error pfn, it can not be fixed,
6246 * report the error to userspace.
6247 */
6248 if (is_error_noslot_pfn(pfn))
6249 return false;
6250
6251 kvm_release_pfn_clean(pfn);
6252
6253 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6254 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6255 unsigned int indirect_shadow_pages;
6256
6257 spin_lock(&vcpu->kvm->mmu_lock);
6258 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6259 spin_unlock(&vcpu->kvm->mmu_lock);
6260
6261 if (indirect_shadow_pages)
6262 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6263
a6f177ef 6264 return true;
8e3d9d06 6265 }
a6f177ef 6266
95b3cf69
XG		 6267 /*
6268 * if emulation was due to access to shadowed page table
6269 * and it failed try to unshadow page and re-enter the
6270 * guest to let CPU execute the instruction.
6271 */
6272 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6273
6274 /*
6275 * If the access faults on its page table, it can not
6276 * be fixed by unprotecting shadow page and it should
6277 * be reported to userspace.
6278 */
6279 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6280}
6281
1cb3f3ae
XG		 6282static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6283 unsigned long cr2, int emulation_type)
6284{
6285 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6286 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6287
6288 last_retry_eip = vcpu->arch.last_retry_eip;
6289 last_retry_addr = vcpu->arch.last_retry_addr;
6290
6291 /*
6292 * If the emulation is caused by #PF and it is non-page_table
6293 * writing instruction, it means the VM-EXIT is caused by shadow
6294 * page protected, we can zap the shadow page and retry this
6295 * instruction directly.
6296 *
6297 * Note: if the guest uses a non-page-table modifying instruction
6298 * on the PDE that points to the instruction, then we will unmap
6299 * the instruction and go to an infinite loop. So, we cache the
6300 * last retried eip and the last fault address, if we meet the eip
6301 * and the address again, we can break out of the potential infinite
6302 * loop.
6303 */
6304 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6305
384bf221 6306 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6307 return false;
6308
6c3dfeb6
SC		 6309 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6310 return false;
6311
1cb3f3ae
XG		 6312 if (x86_page_table_writing_insn(ctxt))
6313 return false;
6314
6315 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6316 return false;
6317
6318 vcpu->arch.last_retry_eip = ctxt->eip;
6319 vcpu->arch.last_retry_addr = cr2;
6320
44dd3ffa 6321 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6322 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6323
22368028 6324 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6325
6326 return true;
6327}
6328
716d51ab
GN		 6329static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6330static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6331
64d60670 6332static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6333{
64d60670 6334 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6335 /* This is a good place to trace that we are exiting SMM. */
6336 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6337
c43203ca
PB		 6338 /* Process a latched INIT or SMI, if any. */
6339 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6340 }
699023e2
PB		 6341
6342 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6343}
6344
4a1e10d5
PB		 6345static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6346 unsigned long *db)
6347{
6348 u32 dr6 = 0;
6349 int i;
6350 u32 enable, rwlen;
6351
6352 enable = dr7;
6353 rwlen = dr7 >> 16;
6354 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6355 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6356 dr6 |= (1 << i);
6357 return dr6;
6358}
6359
c8401dda 6360static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6361{
6362 struct kvm_run *kvm_run = vcpu->run;
6363
c8401dda
PB		 6364 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6365 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6366 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6367 kvm_run->debug.arch.exception = DB_VECTOR;
6368 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6369 *r = EMULATE_USER_EXIT;
6370 } else {
f10c729f 6371 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6372 }
6373}
6374
6affcbed
KH		 6375int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6376{
6377 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6378 int r = EMULATE_DONE;
6379
6380 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6381
6382 /*
6383 * rflags is the old, "raw" value of the flags. The new value has
6384 * not been saved yet.
6385 *
6386 * This is correct even for TF set by the guest, because "the
6387 * processor will not generate this exception after the instruction
6388 * that sets the TF flag".
6389 */
6390 if (unlikely(rflags & X86_EFLAGS_TF))
6391 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6392 return r == EMULATE_DONE;
6393}
6394EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6395
4a1e10d5
PB		 6396static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6397{
4a1e10d5
PB		 6398 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6399 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6400 struct kvm_run *kvm_run = vcpu->run;
6401 unsigned long eip = kvm_get_linear_rip(vcpu);
6402 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6403 vcpu->arch.guest_debug_dr7,
6404 vcpu->arch.eff_db);
6405
6406 if (dr6 != 0) {
6f43ed01 6407 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6408 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6409 kvm_run->debug.arch.exception = DB_VECTOR;
6410 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6411 *r = EMULATE_USER_EXIT;
6412 return true;
6413 }
6414 }
6415
4161a569
NA		 6416 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6417 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6418 unsigned long eip = kvm_get_linear_rip(vcpu);
6419 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6420 vcpu->arch.dr7,
6421 vcpu->arch.db);
6422
6423 if (dr6 != 0) {
1fc5d194 6424 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 6425 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6426 kvm_queue_exception(vcpu, DB_VECTOR);
6427 *r = EMULATE_DONE;
6428 return true;
6429 }
6430 }
6431
6432 return false;
6433}
6434
04789b66
LA		 6435static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6436{
2d7921c4
AM		 6437 switch (ctxt->opcode_len) {
6438 case 1:
6439 switch (ctxt->b) {
6440 case 0xe4: /* IN */
6441 case 0xe5:
6442 case 0xec:
6443 case 0xed:
6444 case 0xe6: /* OUT */
6445 case 0xe7:
6446 case 0xee:
6447 case 0xef:
6448 case 0x6c: /* INS */
6449 case 0x6d:
6450 case 0x6e: /* OUTS */
6451 case 0x6f:
6452 return true;
6453 }
6454 break;
6455 case 2:
6456 switch (ctxt->b) {
6457 case 0x33: /* RDPMC */
6458 return true;
6459 }
6460 break;
04789b66
LA		 6461 }
6462
6463 return false;
6464}
6465
51d8b661
AP		 6466int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6467 unsigned long cr2,
dc25e89e
AP		 6468 int emulation_type,
6469 void *insn,
6470 int insn_len)
bbd9b64e 6471{
95cb2295 6472 int r;
9d74191a 6473 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6474 bool writeback = true;
93c05d3e 6475 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6476
c595ceee
PB		 6477 vcpu->arch.l1tf_flush_l1d = true;
6478
93c05d3e
XG		 6479 /*
6480 * Clear write_fault_to_shadow_pgtable here to ensure it is
6481 * never reused.
6482 */
6483 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6484 kvm_clear_exception_queue(vcpu);
8d7d8102 6485
571008da 6486 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6487 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6488
6489 /*
6490 * We will reenter on the same instruction since
6491 * we do not set complete_userspace_io. This does not
6492 * handle watchpoints yet, those would be handled in
6493 * the emulate_ops.
6494 */
d391f120
VK		 6495 if (!(emulation_type & EMULTYPE_SKIP) &&
6496 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6497 return r;
6498
9d74191a
TY		 6499 ctxt->interruptibility = 0;
6500 ctxt->have_exception = false;
e0ad0b47 6501 ctxt->exception.vector = -1;
9d74191a 6502 ctxt->perm_ok = false;
bbd9b64e 6503
b51e974f 6504 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6505
9d74191a 6506 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6507
e46479f8 6508 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6509 ++vcpu->stat.insn_emulation;
1d2887e2 6510 if (r != EMULATION_OK) {
4005996e
AK		 6511 if (emulation_type & EMULTYPE_TRAP_UD)
6512 return EMULATE_FAIL;
991eebf9
GN		 6513 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6514 emulation_type))
bbd9b64e 6515 return EMULATE_DONE;
6ea6e843
PB		 6516 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6517 return EMULATE_DONE;
6d77dbfc
GN		 6518 if (emulation_type & EMULTYPE_SKIP)
6519 return EMULATE_FAIL;
e2366171 6520 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6521 }
6522 }
6523
04789b66
LA		 6524 if ((emulation_type & EMULTYPE_VMWARE) &&
6525 !is_vmware_backdoor_opcode(ctxt))
6526 return EMULATE_FAIL;
6527
ba8afb6b 6528 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6529 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6530 if (ctxt->eflags & X86_EFLAGS_RF)
6531 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6532 return EMULATE_DONE;
6533 }
6534
1cb3f3ae
XG		 6535 if (retry_instruction(ctxt, cr2, emulation_type))
6536 return EMULATE_DONE;
6537
7ae441ea 6538 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6539 changes registers values during IO operation */
7ae441ea
GN		 6540 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6541 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6542 emulator_invalidate_register_cache(ctxt);
7ae441ea 6543 }
4d2179e1 6544
5cd21917 6545restart:
0f89b207
TL		 6546 /* Save the faulting GPA (cr2) in the address field */
6547 ctxt->exception.address = cr2;
6548
9d74191a 6549 r = x86_emulate_insn(ctxt);
bbd9b64e 6550
775fde86
JR		 6551 if (r == EMULATION_INTERCEPTED)
6552 return EMULATE_DONE;
6553
d2ddd1c4 6554 if (r == EMULATION_FAILED) {
991eebf9
GN		 6555 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6556 emulation_type))
c3cd7ffa
GN		 6557 return EMULATE_DONE;
6558
e2366171 6559 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6560 }
6561
9d74191a 6562 if (ctxt->have_exception) {
d2ddd1c4 6563 r = EMULATE_DONE;
ef54bcfe
PB		 6564 if (inject_emulated_exception(vcpu))
6565 return r;
d2ddd1c4 6566 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6567 if (!vcpu->arch.pio.in) {
6568 /* FIXME: return into emulator if single-stepping. */
3457e419 6569 vcpu->arch.pio.count = 0;
0912c977 6570 } else {
7ae441ea 6571 writeback = false;
716d51ab
GN		 6572 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6573 }
ac0a48c3 6574 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6575 } else if (vcpu->mmio_needed) {
6576 if (!vcpu->mmio_is_write)
6577 writeback = false;
ac0a48c3 6578 r = EMULATE_USER_EXIT;
716d51ab 6579 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6580 } else if (r == EMULATION_RESTART)
5cd21917 6581 goto restart;
d2ddd1c4
GN		 6582 else
6583 r = EMULATE_DONE;
f850e2e6 6584
7ae441ea 6585 if (writeback) {
6addfc42 6586 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6587 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6588 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6589 kvm_rip_write(vcpu, ctxt->eip);
5cc244a2 6590 if (r == EMULATE_DONE && ctxt->tf)
c8401dda 6591 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6592 if (!ctxt->have_exception ||
6593 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6594 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6595
6596 /*
6597 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6598 * do nothing, and it will be requested again as soon as
6599 * the shadow expires. But we still need to check here,
6600 * because POPF has no interrupt shadow.
6601 */
6602 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6603 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6604 } else
6605 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6606
6607 return r;
de7d789a 6608}
c60658d1
SC		 6609
6610int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6611{
6612 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6613}
6614EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6615
6616int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6617 void *insn, int insn_len)
6618{
6619 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6620}
6621EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6622
8764ed55
SC		 6623static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6624{
6625 vcpu->arch.pio.count = 0;
6626 return 1;
6627}
6628
45def77e
SC		 6629static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6630{
6631 vcpu->arch.pio.count = 0;
6632
6633 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6634 return 1;
6635
6636 return kvm_skip_emulated_instruction(vcpu);
6637}
6638
dca7f128
SC		 6639static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6640 unsigned short port)
de7d789a 6641{
de3cd117 6642 unsigned long val = kvm_rax_read(vcpu);
ca1d4a9e
AK		 6643 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6644 size, port, &val, 1);
8764ed55
SC		 6645 if (ret)
6646 return ret;
45def77e 6647
8764ed55
SC		 6648 /*
6649 * Workaround userspace that relies on old KVM behavior of %rip being
6650 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6651 */
6652 if (port == 0x7e &&
6653 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6654 vcpu->arch.complete_userspace_io =
6655 complete_fast_pio_out_port_0x7e;
6656 kvm_skip_emulated_instruction(vcpu);
6657 } else {
45def77e
SC		 6658 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6659 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6660 }
8764ed55 6661 return 0;
de7d789a 6662}
de7d789a 6663
8370c3d0
TL		 6664static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6665{
6666 unsigned long val;
6667
6668 /* We should only ever be called with arch.pio.count equal to 1 */
6669 BUG_ON(vcpu->arch.pio.count != 1);
6670
45def77e
SC		 6671 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6672 vcpu->arch.pio.count = 0;
6673 return 1;
6674 }
6675
8370c3d0 6676 /* For size less than 4 we merge, else we zero extend */
de3cd117 6677 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6678
6679 /*
6680 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6681 * the copy and tracing
6682 */
6683 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6684 vcpu->arch.pio.port, &val, 1);
de3cd117 6685 kvm_rax_write(vcpu, val);
8370c3d0 6686
45def77e 6687 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6688}
6689
dca7f128
SC		 6690static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6691 unsigned short port)
8370c3d0
TL		 6692{
6693 unsigned long val;
6694 int ret;
6695
6696 /* For size less than 4 we merge, else we zero extend */
de3cd117 6697 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6698
6699 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6700 &val, 1);
6701 if (ret) {
de3cd117 6702 kvm_rax_write(vcpu, val);
8370c3d0
TL		 6703 return ret;
6704 }
6705
45def77e 6706 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6707 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6708
6709 return 0;
6710}
dca7f128
SC		 6711
6712int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6713{
45def77e 6714 int ret;
dca7f128 6715
dca7f128 6716 if (in)
45def77e 6717 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6718 else
45def77e
SC		 6719 ret = kvm_fast_pio_out(vcpu, size, port);
6720 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 6721}
6722EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6723
251a5fd6 6724static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6725{
0a3aee0d 6726 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6727 return 0;
8cfdc000
ZA		 6728}
6729
6730static void tsc_khz_changed(void *data)
c8076604 6731{
8cfdc000
ZA		 6732 struct cpufreq_freqs *freq = data;
6733 unsigned long khz = 0;
6734
6735 if (data)
6736 khz = freq->new;
6737 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6738 khz = cpufreq_quick_get(raw_smp_processor_id());
6739 if (!khz)
6740 khz = tsc_khz;
0a3aee0d 6741 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6742}
6743
5fa4ec9c 6744#ifdef CONFIG_X86_64
0092e434
VK		 6745static void kvm_hyperv_tsc_notifier(void)
6746{
0092e434
VK		 6747 struct kvm *kvm;
6748 struct kvm_vcpu *vcpu;
6749 int cpu;
6750
0d9ce162 6751 mutex_lock(&kvm_lock);
0092e434
VK		 6752 list_for_each_entry(kvm, &vm_list, vm_list)
6753 kvm_make_mclock_inprogress_request(kvm);
6754
6755 hyperv_stop_tsc_emulation();
6756
6757 /* TSC frequency always matches when on Hyper-V */
6758 for_each_present_cpu(cpu)
6759 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6760 kvm_max_guest_tsc_khz = tsc_khz;
6761
6762 list_for_each_entry(kvm, &vm_list, vm_list) {
6763 struct kvm_arch *ka = &kvm->arch;
6764
6765 spin_lock(&ka->pvclock_gtod_sync_lock);
6766
6767 pvclock_update_vm_gtod_copy(kvm);
6768
6769 kvm_for_each_vcpu(cpu, vcpu, kvm)
6770 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6771
6772 kvm_for_each_vcpu(cpu, vcpu, kvm)
6773 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6774
6775 spin_unlock(&ka->pvclock_gtod_sync_lock);
6776 }
0d9ce162 6777 mutex_unlock(&kvm_lock);
0092e434 6778}
5fa4ec9c 6779#endif
0092e434 6780
df24014a 6781static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
c8076604 6782{
c8076604
GH		 6783 struct kvm *kvm;
6784 struct kvm_vcpu *vcpu;
6785 int i, send_ipi = 0;
6786
8cfdc000
ZA		 6787 /*
6788 * We allow guests to temporarily run on slowing clocks,
6789 * provided we notify them after, or to run on accelerating
6790 * clocks, provided we notify them before. Thus time never
6791 * goes backwards.
6792 *
6793 * However, we have a problem. We can't atomically update
6794 * the frequency of a given CPU from this function; it is
6795 * merely a notifier, which can be called from any CPU.
6796 * Changing the TSC frequency at arbitrary points in time
6797 * requires a recomputation of local variables related to
6798 * the TSC for each VCPU. We must flag these local variables
6799 * to be updated and be sure the update takes place with the
6800 * new frequency before any guests proceed.
6801 *
6802 * Unfortunately, the combination of hotplug CPU and frequency
6803 * change creates an intractable locking scenario; the order
6804 * of when these callouts happen is undefined with respect to
6805 * CPU hotplug, and they can race with each other. As such,
6806 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6807 * undefined; you can actually have a CPU frequency change take
6808 * place in between the computation of X and the setting of the
6809 * variable. To protect against this problem, all updates of
6810 * the per_cpu tsc_khz variable are done in an interrupt
6811 * protected IPI, and all callers wishing to update the value
6812 * must wait for a synchronous IPI to complete (which is trivial
6813 * if the caller is on the CPU already). This establishes the
6814 * necessary total order on variable updates.
6815 *
6816 * Note that because a guest time update may take place
6817 * anytime after the setting of the VCPU's request bit, the
6818 * correct TSC value must be set before the request. However,
6819 * to ensure the update actually makes it to any guest which
6820 * starts running in hardware virtualization between the set
6821 * and the acquisition of the spinlock, we must also ping the
6822 * CPU after setting the request bit.
6823 *
6824 */
6825
df24014a 6826 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6827
0d9ce162 6828 mutex_lock(&kvm_lock);
c8076604 6829 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6830 kvm_for_each_vcpu(i, vcpu, kvm) {
df24014a 6831 if (vcpu->cpu != cpu)
c8076604 6832 continue;
c285545f 6833 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0d9ce162 6834 if (vcpu->cpu != raw_smp_processor_id())
8cfdc000 6835 send_ipi = 1;
c8076604
GH		 6836 }
6837 }
0d9ce162 6838 mutex_unlock(&kvm_lock);
c8076604
GH		 6839
6840 if (freq->old < freq->new && send_ipi) {
6841 /*
6842 * We upscale the frequency. Must make the guest
6843 * doesn't see old kvmclock values while running with
6844 * the new frequency, otherwise we risk the guest sees
6845 * time go backwards.
6846 *
6847 * In case we update the frequency for another cpu
6848 * (which might be in guest context) send an interrupt
6849 * to kick the cpu out of guest context. Next time
6850 * guest context is entered kvmclock will be updated,
6851 * so the guest will not see stale values.
6852 */
df24014a 6853 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6854 }
df24014a
VK		 6855}
6856
6857static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6858 void *data)
6859{
6860 struct cpufreq_freqs *freq = data;
6861 int cpu;
6862
6863 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6864 return 0;
6865 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6866 return 0;
6867
6868 for_each_cpu(cpu, freq->policy->cpus)
6869 __kvmclock_cpufreq_notifier(freq, cpu);
6870
c8076604
GH		 6871 return 0;
6872}
6873
6874static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6875 .notifier_call = kvmclock_cpufreq_notifier
6876};
6877
251a5fd6 6878static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6879{
251a5fd6
SAS		 6880 tsc_khz_changed(NULL);
6881 return 0;
8cfdc000
ZA		 6882}
6883
b820cc0c
ZA		 6884static void kvm_timer_init(void)
6885{
c285545f 6886 max_tsc_khz = tsc_khz;
460dd42e 6887
b820cc0c 6888 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6889#ifdef CONFIG_CPU_FREQ
6890 struct cpufreq_policy policy;
758f588d
BP		 6891 int cpu;
6892
c285545f 6893 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6894 cpu = get_cpu();
6895 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6896 if (policy.cpuinfo.max_freq)
6897 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6898 put_cpu();
c285545f 6899#endif
b820cc0c
ZA		 6900 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6901 CPUFREQ_TRANSITION_NOTIFIER);
6902 }
460dd42e 6903
73c1b41e 6904 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6905 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6906}
6907
dd60d217
AK		 6908DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6909EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6910
f5132b01 6911int kvm_is_in_guest(void)
ff9d07a0 6912{
086c9855 6913 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6914}
6915
6916static int kvm_is_user_mode(void)
6917{
6918 int user_mode = 3;
dcf46b94 6919
086c9855
AS		 6920 if (__this_cpu_read(current_vcpu))
6921 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6922
ff9d07a0
ZY		 6923 return user_mode != 0;
6924}
6925
6926static unsigned long kvm_get_guest_ip(void)
6927{
6928 unsigned long ip = 0;
dcf46b94 6929
086c9855
AS		 6930 if (__this_cpu_read(current_vcpu))
6931 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6932
ff9d07a0
ZY		 6933 return ip;
6934}
6935
8479e04e
LK		 6936static void kvm_handle_intel_pt_intr(void)
6937{
6938 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6939
6940 kvm_make_request(KVM_REQ_PMI, vcpu);
6941 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6942 (unsigned long *)&vcpu->arch.pmu.global_status);
6943}
6944
ff9d07a0
ZY		 6945static struct perf_guest_info_callbacks kvm_guest_cbs = {
6946 .is_in_guest = kvm_is_in_guest,
6947 .is_user_mode = kvm_is_user_mode,
6948 .get_guest_ip = kvm_get_guest_ip,
8479e04e 6949 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
ff9d07a0
ZY		 6950};
6951
16e8d74d
MT		 6952#ifdef CONFIG_X86_64
6953static void pvclock_gtod_update_fn(struct work_struct *work)
6954{
d828199e
MT		 6955 struct kvm *kvm;
6956
6957 struct kvm_vcpu *vcpu;
6958 int i;
6959
0d9ce162 6960 mutex_lock(&kvm_lock);
d828199e
MT		 6961 list_for_each_entry(kvm, &vm_list, vm_list)
6962 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6963 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6964 atomic_set(&kvm_guest_has_master_clock, 0);
0d9ce162 6965 mutex_unlock(&kvm_lock);
16e8d74d
MT		 6966}
6967
6968static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6969
6970/*
6971 * Notification about pvclock gtod data update.
6972 */
6973static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6974 void *priv)
6975{
6976 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6977 struct timekeeper *tk = priv;
6978
6979 update_pvclock_gtod(tk);
6980
6981 /* disable master clock if host does not trust, or does not
b0c39dc6 6982 * use, TSC based clocksource.
16e8d74d 6983 */
b0c39dc6 6984 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6985 atomic_read(&kvm_guest_has_master_clock) != 0)
6986 queue_work(system_long_wq, &pvclock_gtod_work);
6987
6988 return 0;
6989}
6990
6991static struct notifier_block pvclock_gtod_notifier = {
6992 .notifier_call = pvclock_gtod_notify,
6993};
6994#endif
6995
f8c16bba 6996int kvm_arch_init(void *opaque)
043405e1 6997{
b820cc0c 6998 int r;
6b61edf7 6999 struct kvm_x86_ops *ops = opaque;
f8c16bba 7000
f8c16bba
ZX		 7001 if (kvm_x86_ops) {
7002 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 7003 r = -EEXIST;
7004 goto out;
f8c16bba
ZX		 7005 }
7006
7007 if (!ops->cpu_has_kvm_support()) {
7008 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 7009 r = -EOPNOTSUPP;
7010 goto out;
f8c16bba
ZX		 7011 }
7012 if (ops->disabled_by_bios()) {
7013 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 7014 r = -EOPNOTSUPP;
7015 goto out;
f8c16bba
ZX		 7016 }
7017
b666a4b6
MO		 7018 /*
7019 * KVM explicitly assumes that the guest has an FPU and
7020 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7021 * vCPU's FPU state as a fxregs_state struct.
7022 */
7023 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7024 printk(KERN_ERR "kvm: inadequate fpu\n");
7025 r = -EOPNOTSUPP;
7026 goto out;
7027 }
7028
013f6a5d 7029 r = -ENOMEM;
ed8e4812 7030 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 7031 __alignof__(struct fpu), SLAB_ACCOUNT,
7032 NULL);
7033 if (!x86_fpu_cache) {
7034 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7035 goto out;
7036 }
7037
013f6a5d
MT		 7038 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7039 if (!shared_msrs) {
7040 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 7041 goto out_free_x86_fpu_cache;
013f6a5d
MT		 7042 }
7043
97db56ce
AK		 7044 r = kvm_mmu_module_init();
7045 if (r)
013f6a5d 7046 goto out_free_percpu;
97db56ce 7047
f8c16bba 7048 kvm_x86_ops = ops;
920c8377 7049
7b52345e 7050 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 7051 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 7052 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 7053 kvm_timer_init();
c8076604 7054
ff9d07a0
ZY		 7055 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7056
d366bf7e 7057 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 7058 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7059
c5cc421b 7060 kvm_lapic_init();
16e8d74d
MT		 7061#ifdef CONFIG_X86_64
7062 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 7063
5fa4ec9c 7064 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 7065 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 7066#endif
7067
f8c16bba 7068 return 0;
56c6d28a 7069
013f6a5d
MT		 7070out_free_percpu:
7071 free_percpu(shared_msrs);
b666a4b6
MO		 7072out_free_x86_fpu_cache:
7073 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7074out:
56c6d28a 7075 return r;
043405e1 7076}
8776e519 7077
f8c16bba
ZX		 7078void kvm_arch_exit(void)
7079{
0092e434 7080#ifdef CONFIG_X86_64
5fa4ec9c 7081 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 7082 clear_hv_tscchange_cb();
7083#endif
cef84c30 7084 kvm_lapic_exit();
ff9d07a0
ZY		 7085 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7086
888d256e
JK		 7087 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7088 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7089 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7090 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7091#ifdef CONFIG_X86_64
7092 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7093#endif
f8c16bba 7094 kvm_x86_ops = NULL;
56c6d28a 7095 kvm_mmu_module_exit();
013f6a5d 7096 free_percpu(shared_msrs);
b666a4b6 7097 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7098}
f8c16bba 7099
5cb56059 7100int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7101{
7102 ++vcpu->stat.halt_exits;
35754c98 7103 if (lapic_in_kernel(vcpu)) {
a4535290 7104 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7105 return 1;
7106 } else {
7107 vcpu->run->exit_reason = KVM_EXIT_HLT;
7108 return 0;
7109 }
7110}
5cb56059
JS		 7111EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7112
7113int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7114{
6affcbed
KH		 7115 int ret = kvm_skip_emulated_instruction(vcpu);
7116 /*
7117 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7118 * KVM_EXIT_DEBUG here.
7119 */
7120 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7121}
8776e519
HB		 7122EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7123
8ef81a9a 7124#ifdef CONFIG_X86_64
55dd00a7
MT		 7125static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7126 unsigned long clock_type)
7127{
7128 struct kvm_clock_pairing clock_pairing;
899a31f5 7129 struct timespec64 ts;
80fbd89c 7130 u64 cycle;
55dd00a7
MT		 7131 int ret;
7132
7133 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7134 return -KVM_EOPNOTSUPP;
7135
7136 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7137 return -KVM_EOPNOTSUPP;
7138
7139 clock_pairing.sec = ts.tv_sec;
7140 clock_pairing.nsec = ts.tv_nsec;
7141 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7142 clock_pairing.flags = 0;
bcbfbd8e 7143 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7144
7145 ret = 0;
7146 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7147 sizeof(struct kvm_clock_pairing)))
7148 ret = -KVM_EFAULT;
7149
7150 return ret;
7151}
8ef81a9a 7152#endif
55dd00a7 7153
6aef266c
SV		 7154/*
7155 * kvm_pv_kick_cpu_op: Kick a vcpu.
7156 *
7157 * @apicid - apicid of vcpu to be kicked.
7158 */
7159static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7160{
24d2166b 7161 struct kvm_lapic_irq lapic_irq;
6aef266c 7162
24d2166b
R		 7163 lapic_irq.shorthand = 0;
7164 lapic_irq.dest_mode = 0;
ebd28fcb 7165 lapic_irq.level = 0;
24d2166b 7166 lapic_irq.dest_id = apicid;
93bbf0b8 7167 lapic_irq.msi_redir_hint = false;
6aef266c 7168
24d2166b 7169 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7170 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7171}
7172
d62caabb
AS		 7173void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7174{
f7589cca
PB		 7175 if (!lapic_in_kernel(vcpu)) {
7176 WARN_ON_ONCE(vcpu->arch.apicv_active);
7177 return;
7178 }
7179 if (!vcpu->arch.apicv_active)
7180 return;
7181
d62caabb
AS		 7182 vcpu->arch.apicv_active = false;
7183 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7184}
7185
71506297
WL		 7186static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7187{
7188 struct kvm_vcpu *target = NULL;
7189 struct kvm_apic_map *map;
7190
7191 rcu_read_lock();
7192 map = rcu_dereference(kvm->arch.apic_map);
7193
7194 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7195 target = map->phys_map[dest_id]->vcpu;
7196
7197 rcu_read_unlock();
7198
7199 if (target)
7200 kvm_vcpu_yield_to(target);
7201}
7202
8776e519
HB		 7203int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7204{
7205 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7206 int op_64_bit;
8776e519 7207
696ca779
RK		 7208 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7209 return kvm_hv_hypercall(vcpu);
55cd8e5a 7210
de3cd117
SC		 7211 nr = kvm_rax_read(vcpu);
7212 a0 = kvm_rbx_read(vcpu);
7213 a1 = kvm_rcx_read(vcpu);
7214 a2 = kvm_rdx_read(vcpu);
7215 a3 = kvm_rsi_read(vcpu);
8776e519 7216
229456fc 7217 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7218
a449c7aa
NA		 7219 op_64_bit = is_64_bit_mode(vcpu);
7220 if (!op_64_bit) {
8776e519
HB		 7221 nr &= 0xFFFFFFFF;
7222 a0 &= 0xFFFFFFFF;
7223 a1 &= 0xFFFFFFFF;
7224 a2 &= 0xFFFFFFFF;
7225 a3 &= 0xFFFFFFFF;
7226 }
7227
07708c4a
JK		 7228 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7229 ret = -KVM_EPERM;
696ca779 7230 goto out;
07708c4a
JK		 7231 }
7232
8776e519 7233 switch (nr) {
b93463aa
AK		 7234 case KVM_HC_VAPIC_POLL_IRQ:
7235 ret = 0;
7236 break;
6aef266c
SV		 7237 case KVM_HC_KICK_CPU:
7238 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7239 ret = 0;
7240 break;
8ef81a9a 7241#ifdef CONFIG_X86_64
55dd00a7
MT		 7242 case KVM_HC_CLOCK_PAIRING:
7243 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7244 break;
1ed199a4 7245#endif
4180bf1b
WL		 7246 case KVM_HC_SEND_IPI:
7247 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7248 break;
71506297
WL		 7249 case KVM_HC_SCHED_YIELD:
7250 kvm_sched_yield(vcpu->kvm, a0);
7251 ret = 0;
7252 break;
8776e519
HB		 7253 default:
7254 ret = -KVM_ENOSYS;
7255 break;
7256 }
696ca779 7257out:
a449c7aa
NA		 7258 if (!op_64_bit)
7259 ret = (u32)ret;
de3cd117 7260 kvm_rax_write(vcpu, ret);
6356ee0c 7261
f11c3a8d 7262 ++vcpu->stat.hypercalls;
6356ee0c 7263 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7264}
7265EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7266
b6785def 7267static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7268{
d6aa1000 7269 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7270 char instruction[3];
5fdbf976 7271 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7272
8776e519 7273 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7274
ce2e852e
DV		 7275 return emulator_write_emulated(ctxt, rip, instruction, 3,
7276 &ctxt->exception);
8776e519
HB		 7277}
7278
851ba692 7279static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7280{
782d422b
MG		 7281 return vcpu->run->request_interrupt_window &&
7282 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7283}
7284
851ba692 7285static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7286{
851ba692
AK		 7287 struct kvm_run *kvm_run = vcpu->run;
7288
91586a3b 7289 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7290 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7291 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7292 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7293 kvm_run->ready_for_interrupt_injection =
7294 pic_in_kernel(vcpu->kvm) ||
782d422b 7295 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7296}
7297
95ba8273
GN		 7298static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7299{
7300 int max_irr, tpr;
7301
7302 if (!kvm_x86_ops->update_cr8_intercept)
7303 return;
7304
bce87cce 7305 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7306 return;
7307
d62caabb
AS		 7308 if (vcpu->arch.apicv_active)
7309 return;
7310
8db3baa2
GN		 7311 if (!vcpu->arch.apic->vapic_addr)
7312 max_irr = kvm_lapic_find_highest_irr(vcpu);
7313 else
7314 max_irr = -1;
95ba8273
GN		 7315
7316 if (max_irr != -1)
7317 max_irr >>= 4;
7318
7319 tpr = kvm_lapic_get_cr8(vcpu);
7320
7321 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7322}
7323
b6b8a145 7324static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7325{
b6b8a145
JK		 7326 int r;
7327
95ba8273 7328 /* try to reinject previous events if any */
664f8e26 7329
1a680e35
LA		 7330 if (vcpu->arch.exception.injected)
7331 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7332 /*
a042c26f
LA		 7333 * Do not inject an NMI or interrupt if there is a pending
7334 * exception. Exceptions and interrupts are recognized at
7335 * instruction boundaries, i.e. the start of an instruction.
7336 * Trap-like exceptions, e.g. #DB, have higher priority than
7337 * NMIs and interrupts, i.e. traps are recognized before an
7338 * NMI/interrupt that's pending on the same instruction.
7339 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7340 * priority, but are only generated (pended) during instruction
7341 * execution, i.e. a pending fault-like exception means the
7342 * fault occurred on the *previous* instruction and must be
7343 * serviced prior to recognizing any new events in order to
7344 * fully complete the previous instruction.
664f8e26 7345 */
1a680e35
LA		 7346 else if (!vcpu->arch.exception.pending) {
7347 if (vcpu->arch.nmi_injected)
664f8e26 7348 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7349 else if (vcpu->arch.interrupt.injected)
664f8e26 7350 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7351 }
7352
1a680e35
LA		 7353 /*
7354 * Call check_nested_events() even if we reinjected a previous event
7355 * in order for caller to determine if it should require immediate-exit
7356 * from L2 to L1 due to pending L1 events which require exit
7357 * from L2 to L1.
7358 */
664f8e26
WL		 7359 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7360 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7361 if (r != 0)
7362 return r;
7363 }
7364
7365 /* try to inject new event if pending */
b59bb7bd 7366 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7367 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7368 vcpu->arch.exception.has_error_code,
7369 vcpu->arch.exception.error_code);
d6e8c854 7370
1a680e35 7371 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7372 vcpu->arch.exception.pending = false;
7373 vcpu->arch.exception.injected = true;
7374
d6e8c854
NA		 7375 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7376 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7377 X86_EFLAGS_RF);
7378
f10c729f
JM		 7379 if (vcpu->arch.exception.nr == DB_VECTOR) {
7380 /*
7381 * This code assumes that nSVM doesn't use
7382 * check_nested_events(). If it does, the
7383 * DR6/DR7 changes should happen before L1
7384 * gets a #VMEXIT for an intercepted #DB in
7385 * L2. (Under VMX, on the other hand, the
7386 * DR6/DR7 changes should not happen in the
7387 * event of a VM-exit to L1 for an intercepted
7388 * #DB in L2.)
7389 */
7390 kvm_deliver_exception_payload(vcpu);
7391 if (vcpu->arch.dr7 & DR7_GD) {
7392 vcpu->arch.dr7 &= ~DR7_GD;
7393 kvm_update_dr7(vcpu);
7394 }
6bdf0662
NA		 7395 }
7396
cfcd20e5 7397 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7398 }
7399
7400 /* Don't consider new event if we re-injected an event */
7401 if (kvm_event_needs_reinjection(vcpu))
7402 return 0;
7403
7404 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7405 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7406 vcpu->arch.smi_pending = false;
52797bf9 7407 ++vcpu->arch.smi_count;
ee2cd4b7 7408 enter_smm(vcpu);
c43203ca 7409 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7410 --vcpu->arch.nmi_pending;
7411 vcpu->arch.nmi_injected = true;
7412 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7413 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7414 /*
7415 * Because interrupts can be injected asynchronously, we are
7416 * calling check_nested_events again here to avoid a race condition.
7417 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7418 * proposal and current concerns. Perhaps we should be setting
7419 * KVM_REQ_EVENT only on certain events and not unconditionally?
7420 */
7421 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7422 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7423 if (r != 0)
7424 return r;
7425 }
95ba8273 7426 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7427 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7428 false);
7429 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7430 }
7431 }
ee2cd4b7 7432
b6b8a145 7433 return 0;
95ba8273
GN		 7434}
7435
7460fb4a
AK		 7436static void process_nmi(struct kvm_vcpu *vcpu)
7437{
7438 unsigned limit = 2;
7439
7440 /*
7441 * x86 is limited to one NMI running, and one NMI pending after it.
7442 * If an NMI is already in progress, limit further NMIs to just one.
7443 * Otherwise, allow two (and we'll inject the first one immediately).
7444 */
7445 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7446 limit = 1;
7447
7448 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7449 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7450 kvm_make_request(KVM_REQ_EVENT, vcpu);
7451}
7452
ee2cd4b7 7453static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7454{
7455 u32 flags = 0;
7456 flags |= seg->g << 23;
7457 flags |= seg->db << 22;
7458 flags |= seg->l << 21;
7459 flags |= seg->avl << 20;
7460 flags |= seg->present << 15;
7461 flags |= seg->dpl << 13;
7462 flags |= seg->s << 12;
7463 flags |= seg->type << 8;
7464 return flags;
7465}
7466
ee2cd4b7 7467static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7468{
7469 struct kvm_segment seg;
7470 int offset;
7471
7472 kvm_get_segment(vcpu, &seg, n);
7473 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7474
7475 if (n < 3)
7476 offset = 0x7f84 + n * 12;
7477 else
7478 offset = 0x7f2c + (n - 3) * 12;
7479
7480 put_smstate(u32, buf, offset + 8, seg.base);
7481 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7482 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7483}
7484
efbb288a 7485#ifdef CONFIG_X86_64
ee2cd4b7 7486static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7487{
7488 struct kvm_segment seg;
7489 int offset;
7490 u16 flags;
7491
7492 kvm_get_segment(vcpu, &seg, n);
7493 offset = 0x7e00 + n * 16;
7494
ee2cd4b7 7495 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7496 put_smstate(u16, buf, offset, seg.selector);
7497 put_smstate(u16, buf, offset + 2, flags);
7498 put_smstate(u32, buf, offset + 4, seg.limit);
7499 put_smstate(u64, buf, offset + 8, seg.base);
7500}
efbb288a 7501#endif
660a5d51 7502
ee2cd4b7 7503static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7504{
7505 struct desc_ptr dt;
7506 struct kvm_segment seg;
7507 unsigned long val;
7508 int i;
7509
7510 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7511 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7512 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7513 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7514
7515 for (i = 0; i < 8; i++)
7516 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7517
7518 kvm_get_dr(vcpu, 6, &val);
7519 put_smstate(u32, buf, 0x7fcc, (u32)val);
7520 kvm_get_dr(vcpu, 7, &val);
7521 put_smstate(u32, buf, 0x7fc8, (u32)val);
7522
7523 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7524 put_smstate(u32, buf, 0x7fc4, seg.selector);
7525 put_smstate(u32, buf, 0x7f64, seg.base);
7526 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7527 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7528
7529 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7530 put_smstate(u32, buf, 0x7fc0, seg.selector);
7531 put_smstate(u32, buf, 0x7f80, seg.base);
7532 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7533 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7534
7535 kvm_x86_ops->get_gdt(vcpu, &dt);
7536 put_smstate(u32, buf, 0x7f74, dt.address);
7537 put_smstate(u32, buf, 0x7f70, dt.size);
7538
7539 kvm_x86_ops->get_idt(vcpu, &dt);
7540 put_smstate(u32, buf, 0x7f58, dt.address);
7541 put_smstate(u32, buf, 0x7f54, dt.size);
7542
7543 for (i = 0; i < 6; i++)
ee2cd4b7 7544 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7545
7546 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7547
7548 /* revision id */
7549 put_smstate(u32, buf, 0x7efc, 0x00020000);
7550 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7551}
7552
b68f3cc7 7553#ifdef CONFIG_X86_64
ee2cd4b7 7554static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7555{
660a5d51
PB		 7556 struct desc_ptr dt;
7557 struct kvm_segment seg;
7558 unsigned long val;
7559 int i;
7560
7561 for (i = 0; i < 16; i++)
7562 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7563
7564 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7565 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7566
7567 kvm_get_dr(vcpu, 6, &val);
7568 put_smstate(u64, buf, 0x7f68, val);
7569 kvm_get_dr(vcpu, 7, &val);
7570 put_smstate(u64, buf, 0x7f60, val);
7571
7572 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7573 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7574 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7575
7576 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7577
7578 /* revision id */
7579 put_smstate(u32, buf, 0x7efc, 0x00020064);
7580
7581 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7582
7583 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7584 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7585 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7586 put_smstate(u32, buf, 0x7e94, seg.limit);
7587 put_smstate(u64, buf, 0x7e98, seg.base);
7588
7589 kvm_x86_ops->get_idt(vcpu, &dt);
7590 put_smstate(u32, buf, 0x7e84, dt.size);
7591 put_smstate(u64, buf, 0x7e88, dt.address);
7592
7593 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7594 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7595 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7596 put_smstate(u32, buf, 0x7e74, seg.limit);
7597 put_smstate(u64, buf, 0x7e78, seg.base);
7598
7599 kvm_x86_ops->get_gdt(vcpu, &dt);
7600 put_smstate(u32, buf, 0x7e64, dt.size);
7601 put_smstate(u64, buf, 0x7e68, dt.address);
7602
7603 for (i = 0; i < 6; i++)
ee2cd4b7 7604 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7605}
b68f3cc7 7606#endif
660a5d51 7607
ee2cd4b7 7608static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7609{
660a5d51 7610 struct kvm_segment cs, ds;
18c3626e 7611 struct desc_ptr dt;
660a5d51
PB		 7612 char buf[512];
7613 u32 cr0;
7614
660a5d51 7615 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7616 memset(buf, 0, 512);
b68f3cc7 7617#ifdef CONFIG_X86_64
d6321d49 7618 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7619 enter_smm_save_state_64(vcpu, buf);
660a5d51 7620 else
b68f3cc7 7621#endif
ee2cd4b7 7622 enter_smm_save_state_32(vcpu, buf);
660a5d51 7623
0234bf88
LP		 7624 /*
7625 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7626 * vCPU state (e.g. leave guest mode) after we've saved the state into
7627 * the SMM state-save area.
7628 */
7629 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7630
7631 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7632 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7633
7634 if (kvm_x86_ops->get_nmi_mask(vcpu))
7635 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7636 else
7637 kvm_x86_ops->set_nmi_mask(vcpu, true);
7638
7639 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7640 kvm_rip_write(vcpu, 0x8000);
7641
7642 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7643 kvm_x86_ops->set_cr0(vcpu, cr0);
7644 vcpu->arch.cr0 = cr0;
7645
7646 kvm_x86_ops->set_cr4(vcpu, 0);
7647
18c3626e
PB		 7648 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7649 dt.address = dt.size = 0;
7650 kvm_x86_ops->set_idt(vcpu, &dt);
7651
660a5d51
PB		 7652 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7653
7654 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7655 cs.base = vcpu->arch.smbase;
7656
7657 ds.selector = 0;
7658 ds.base = 0;
7659
7660 cs.limit = ds.limit = 0xffffffff;
7661 cs.type = ds.type = 0x3;
7662 cs.dpl = ds.dpl = 0;
7663 cs.db = ds.db = 0;
7664 cs.s = ds.s = 1;
7665 cs.l = ds.l = 0;
7666 cs.g = ds.g = 1;
7667 cs.avl = ds.avl = 0;
7668 cs.present = ds.present = 1;
7669 cs.unusable = ds.unusable = 0;
7670 cs.padding = ds.padding = 0;
7671
7672 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7673 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7674 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7675 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7676 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7677 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7678
b68f3cc7 7679#ifdef CONFIG_X86_64
d6321d49 7680 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7681 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7682#endif
660a5d51
PB		 7683
7684 kvm_update_cpuid(vcpu);
7685 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7686}
7687
ee2cd4b7 7688static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7689{
7690 vcpu->arch.smi_pending = true;
7691 kvm_make_request(KVM_REQ_EVENT, vcpu);
7692}
7693
2860c4b1
PB		 7694void kvm_make_scan_ioapic_request(struct kvm *kvm)
7695{
7696 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7697}
7698
3d81bc7e 7699static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7700{
dcbd3e49 7701 if (!kvm_apic_present(vcpu))
3d81bc7e 7702 return;
c7c9c56c 7703
6308630b 7704 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7705
b053b2ae 7706 if (irqchip_split(vcpu->kvm))
6308630b 7707 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7708 else {
fa59cc00 7709 if (vcpu->arch.apicv_active)
d62caabb 7710 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7711 if (ioapic_in_kernel(vcpu->kvm))
7712 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7713 }
e40ff1d6
LA		 7714
7715 if (is_guest_mode(vcpu))
7716 vcpu->arch.load_eoi_exitmap_pending = true;
7717 else
7718 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7719}
7720
7721static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7722{
7723 u64 eoi_exit_bitmap[4];
7724
7725 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7726 return;
7727
5c919412
AS		 7728 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7729 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7730 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7731}
7732
93065ac7
MH		 7733int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7734 unsigned long start, unsigned long end,
7735 bool blockable)
b1394e74
RK		 7736{
7737 unsigned long apic_address;
7738
7739 /*
7740 * The physical address of apic access page is stored in the VMCS.
7741 * Update it when it becomes invalid.
7742 */
7743 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7744 if (start <= apic_address && apic_address < end)
7745 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7746
7747 return 0;
b1394e74
RK		 7748}
7749
4256f43f
TC		 7750void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7751{
c24ae0dc
TC		 7752 struct page *page = NULL;
7753
35754c98 7754 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7755 return;
7756
4256f43f
TC		 7757 if (!kvm_x86_ops->set_apic_access_page_addr)
7758 return;
7759
c24ae0dc 7760 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7761 if (is_error_page(page))
7762 return;
c24ae0dc
TC		 7763 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7764
7765 /*
7766 * Do not pin apic access page in memory, the MMU notifier
7767 * will call us again if it is migrated or swapped out.
7768 */
7769 put_page(page);
4256f43f
TC		 7770}
7771EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7772
d264ee0c
SC		 7773void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7774{
7775 smp_send_reschedule(vcpu->cpu);
7776}
7777EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7778
9357d939 7779/*
362c698f 7780 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7781 * exiting to the userspace. Otherwise, the value will be returned to the
7782 * userspace.
7783 */
851ba692 7784static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7785{
7786 int r;
62a193ed
MG		 7787 bool req_int_win =
7788 dm_request_for_irq_injection(vcpu) &&
7789 kvm_cpu_accept_dm_intr(vcpu);
7790
730dca42 7791 bool req_immediate_exit = false;
b6c7a5dc 7792
2fa6e1e1 7793 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7794 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7795 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7796 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7797 kvm_mmu_unload(vcpu);
a8eeb04a 7798 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7799 __kvm_migrate_timers(vcpu);
d828199e
MT		 7800 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7801 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7802 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7803 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7804 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7805 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7806 if (unlikely(r))
7807 goto out;
7808 }
a8eeb04a 7809 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7810 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7811 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7812 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7813 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7814 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7815 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7816 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7817 r = 0;
7818 goto out;
7819 }
a8eeb04a 7820 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7821 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7822 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7823 r = 0;
7824 goto out;
7825 }
af585b92
GN		 7826 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7827 /* Page is swapped out. Do synthetic halt */
7828 vcpu->arch.apf.halted = true;
7829 r = 1;
7830 goto out;
7831 }
c9aaa895
GC		 7832 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7833 record_steal_time(vcpu);
64d60670
PB		 7834 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7835 process_smi(vcpu);
7460fb4a
AK		 7836 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7837 process_nmi(vcpu);
f5132b01 7838 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7839 kvm_pmu_handle_event(vcpu);
f5132b01 7840 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7841 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7842 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7843 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7844 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7845 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7846 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7847 vcpu->run->eoi.vector =
7848 vcpu->arch.pending_ioapic_eoi;
7849 r = 0;
7850 goto out;
7851 }
7852 }
3d81bc7e
YZ		 7853 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7854 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7855 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7856 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7857 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7858 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7859 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7860 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7861 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7862 r = 0;
7863 goto out;
7864 }
e516cebb
AS		 7865 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7866 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7867 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7868 r = 0;
7869 goto out;
7870 }
db397571
AS		 7871 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7872 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7873 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7874 r = 0;
7875 goto out;
7876 }
f3b138c5
AS		 7877
7878 /*
7879 * KVM_REQ_HV_STIMER has to be processed after
7880 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7881 * depend on the guest clock being up-to-date
7882 */
1f4b34f8
AS		 7883 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7884 kvm_hv_process_stimers(vcpu);
2f52d58c 7885 }
b93463aa 7886
b463a6f7 7887 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7888 ++vcpu->stat.req_event;
66450a21
JK		 7889 kvm_apic_accept_events(vcpu);
7890 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7891 r = 1;
7892 goto out;
7893 }
7894
b6b8a145
JK		 7895 if (inject_pending_event(vcpu, req_int_win) != 0)
7896 req_immediate_exit = true;
321c5658 7897 else {
cc3d967f 7898 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7899 *
cc3d967f
LP		 7900 * SMIs have three cases:
7901 * 1) They can be nested, and then there is nothing to
7902 * do here because RSM will cause a vmexit anyway.
7903 * 2) There is an ISA-specific reason why SMI cannot be
7904 * injected, and the moment when this changes can be
7905 * intercepted.
7906 * 3) Or the SMI can be pending because
7907 * inject_pending_event has completed the injection
7908 * of an IRQ or NMI from the previous vmexit, and
7909 * then we request an immediate exit to inject the
7910 * SMI.
c43203ca
PB		 7911 */
7912 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7913 if (!kvm_x86_ops->enable_smi_window(vcpu))
7914 req_immediate_exit = true;
321c5658
YS		 7915 if (vcpu->arch.nmi_pending)
7916 kvm_x86_ops->enable_nmi_window(vcpu);
7917 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7918 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7919 WARN_ON(vcpu->arch.exception.pending);
321c5658 7920 }
b463a6f7
AK		 7921
7922 if (kvm_lapic_enabled(vcpu)) {
7923 update_cr8_intercept(vcpu);
7924 kvm_lapic_sync_to_vapic(vcpu);
7925 }
7926 }
7927
d8368af8
AK		 7928 r = kvm_mmu_reload(vcpu);
7929 if (unlikely(r)) {
d905c069 7930 goto cancel_injection;
d8368af8
AK		 7931 }
7932
b6c7a5dc
HB		 7933 preempt_disable();
7934
7935 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7936
7937 /*
7938 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7939 * IPI are then delayed after guest entry, which ensures that they
7940 * result in virtual interrupt delivery.
7941 */
7942 local_irq_disable();
6b7e2d09
XG		 7943 vcpu->mode = IN_GUEST_MODE;
7944
01b71917
MT		 7945 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7946
0f127d12 7947 /*
b95234c8 7948 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7949 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 7950 *
81b01667 7951 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 7952 * pairs with the memory barrier implicit in pi_test_and_set_on
7953 * (see vmx_deliver_posted_interrupt).
7954 *
7955 * 3) This also orders the write to mode from any reads to the page
7956 * tables done while the VCPU is running. Please see the comment
7957 * in kvm_flush_remote_tlbs.
6b7e2d09 7958 */
01b71917 7959 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7960
b95234c8
PB		 7961 /*
7962 * This handles the case where a posted interrupt was
7963 * notified with kvm_vcpu_kick.
7964 */
fa59cc00
LA		 7965 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7966 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7967
2fa6e1e1 7968 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7969 || need_resched() || signal_pending(current)) {
6b7e2d09 7970 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7971 smp_wmb();
6c142801
AK		 7972 local_irq_enable();
7973 preempt_enable();
01b71917 7974 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7975 r = 1;
d905c069 7976 goto cancel_injection;
6c142801
AK		 7977 }
7978
c43203ca
PB		 7979 if (req_immediate_exit) {
7980 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7981 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7982 }
d6185f20 7983
8b89fe1f 7984 trace_kvm_entry(vcpu->vcpu_id);
6edaa530 7985 guest_enter_irqoff();
b6c7a5dc 7986
5f409e20
RR		 7987 fpregs_assert_state_consistent();
7988 if (test_thread_flag(TIF_NEED_FPU_LOAD))
7989 switch_fpu_return();
7990
42dbaa5a 7991 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7992 set_debugreg(0, 7);
7993 set_debugreg(vcpu->arch.eff_db[0], 0);
7994 set_debugreg(vcpu->arch.eff_db[1], 1);
7995 set_debugreg(vcpu->arch.eff_db[2], 2);
7996 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7997 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7998 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7999 }
b6c7a5dc 8000
851ba692 8001 kvm_x86_ops->run(vcpu);
b6c7a5dc 8002
c77fb5fe
PB		 8003 /*
8004 * Do this here before restoring debug registers on the host. And
8005 * since we do this before handling the vmexit, a DR access vmexit
8006 * can (a) read the correct value of the debug registers, (b) set
8007 * KVM_DEBUGREG_WONT_EXIT again.
8008 */
8009 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 8010 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8011 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 8012 kvm_update_dr0123(vcpu);
8013 kvm_update_dr6(vcpu);
8014 kvm_update_dr7(vcpu);
8015 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 8016 }
8017
24f1e32c
FW		 8018 /*
8019 * If the guest has used debug registers, at least dr7
8020 * will be disabled while returning to the host.
8021 * If we don't have active breakpoints in the host, we don't
8022 * care about the messed up debug address registers. But if
8023 * we have some of them active, restore the old state.
8024 */
59d8eb53 8025 if (hw_breakpoint_active())
24f1e32c 8026 hw_breakpoint_restore();
42dbaa5a 8027
4ba76538 8028 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 8029
6b7e2d09 8030 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8031 smp_wmb();
a547c6db 8032
95b5a48c 8033 kvm_x86_ops->handle_exit_irqoff(vcpu);
b6c7a5dc 8034
d7a08882
SC		 8035 /*
8036 * Consume any pending interrupts, including the possible source of
8037 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8038 * An instruction is required after local_irq_enable() to fully unblock
8039 * interrupts on processors that implement an interrupt shadow, the
8040 * stat.exits increment will do nicely.
8041 */
8042 kvm_before_interrupt(vcpu);
8043 local_irq_enable();
b6c7a5dc 8044 ++vcpu->stat.exits;
d7a08882
SC		 8045 local_irq_disable();
8046 kvm_after_interrupt(vcpu);
b6c7a5dc 8047
f2485b3e 8048 guest_exit_irqoff();
ec0671d5
WL		 8049 if (lapic_in_kernel(vcpu)) {
8050 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8051 if (delta != S64_MIN) {
8052 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8053 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8054 }
8055 }
b6c7a5dc 8056
f2485b3e 8057 local_irq_enable();
b6c7a5dc
HB		 8058 preempt_enable();
8059
f656ce01 8060 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 8061
b6c7a5dc
HB		 8062 /*
8063 * Profile KVM exit RIPs:
8064 */
8065 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 8066 unsigned long rip = kvm_rip_read(vcpu);
8067 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 8068 }
8069
cc578287
ZA		 8070 if (unlikely(vcpu->arch.tsc_always_catchup))
8071 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 8072
5cfb1d5a
MT		 8073 if (vcpu->arch.apic_attention)
8074 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 8075
618232e2 8076 vcpu->arch.gpa_available = false;
851ba692 8077 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 8078 return r;
8079
8080cancel_injection:
8081 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 8082 if (unlikely(vcpu->arch.apic_attention))
8083 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 8084out:
8085 return r;
8086}
b6c7a5dc 8087
362c698f
PB		 8088static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8089{
bf9f6ac8
FW		 8090 if (!kvm_arch_vcpu_runnable(vcpu) &&
8091 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 8092 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8093 kvm_vcpu_block(vcpu);
8094 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 8095
8096 if (kvm_x86_ops->post_block)
8097 kvm_x86_ops->post_block(vcpu);
8098
9c8fd1ba
PB		 8099 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8100 return 1;
8101 }
362c698f
PB		 8102
8103 kvm_apic_accept_events(vcpu);
8104 switch(vcpu->arch.mp_state) {
8105 case KVM_MP_STATE_HALTED:
8106 vcpu->arch.pv.pv_unhalted = false;
8107 vcpu->arch.mp_state =
8108 KVM_MP_STATE_RUNNABLE;
b2869f28 8109 /* fall through */
362c698f
PB		 8110 case KVM_MP_STATE_RUNNABLE:
8111 vcpu->arch.apf.halted = false;
8112 break;
8113 case KVM_MP_STATE_INIT_RECEIVED:
8114 break;
8115 default:
8116 return -EINTR;
8117 break;
8118 }
8119 return 1;
8120}
09cec754 8121
5d9bc648
PB		 8122static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8123{
0ad3bed6
PB		 8124 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8125 kvm_x86_ops->check_nested_events(vcpu, false);
8126
5d9bc648
PB		 8127 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8128 !vcpu->arch.apf.halted);
8129}
8130
362c698f 8131static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8132{
8133 int r;
f656ce01 8134 struct kvm *kvm = vcpu->kvm;
d7690175 8135
f656ce01 8136 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8137 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8138
362c698f 8139 for (;;) {
58f800d5 8140 if (kvm_vcpu_running(vcpu)) {
851ba692 8141 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8142 } else {
362c698f 8143 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8144 }
8145
09cec754
GN		 8146 if (r <= 0)
8147 break;
8148
72875d8a 8149 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8150 if (kvm_cpu_has_pending_timer(vcpu))
8151 kvm_inject_pending_timer_irqs(vcpu);
8152
782d422b
MG		 8153 if (dm_request_for_irq_injection(vcpu) &&
8154 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8155 r = 0;
8156 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8157 ++vcpu->stat.request_irq_exits;
362c698f 8158 break;
09cec754 8159 }
af585b92
GN		 8160
8161 kvm_check_async_pf_completion(vcpu);
8162
09cec754
GN		 8163 if (signal_pending(current)) {
8164 r = -EINTR;
851ba692 8165 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8166 ++vcpu->stat.signal_exits;
362c698f 8167 break;
09cec754
GN		 8168 }
8169 if (need_resched()) {
f656ce01 8170 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8171 cond_resched();
f656ce01 8172 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8173 }
b6c7a5dc
HB		 8174 }
8175
f656ce01 8176 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8177
8178 return r;
8179}
8180
716d51ab
GN		 8181static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8182{
8183 int r;
8184 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8185 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 8186 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8187 if (r != EMULATE_DONE)
8188 return 0;
8189 return 1;
8190}
8191
8192static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8193{
8194 BUG_ON(!vcpu->arch.pio.count);
8195
8196 return complete_emulated_io(vcpu);
8197}
8198
f78146b0
AK		 8199/*
8200 * Implements the following, as a state machine:
8201 *
8202 * read:
8203 * for each fragment
87da7e66
XG		 8204 * for each mmio piece in the fragment
8205 * write gpa, len
8206 * exit
8207 * copy data
f78146b0
AK		 8208 * execute insn
8209 *
8210 * write:
8211 * for each fragment
87da7e66
XG		 8212 * for each mmio piece in the fragment
8213 * write gpa, len
8214 * copy data
8215 * exit
f78146b0 8216 */
716d51ab 8217static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8218{
8219 struct kvm_run *run = vcpu->run;
f78146b0 8220 struct kvm_mmio_fragment *frag;
87da7e66 8221 unsigned len;
5287f194 8222
716d51ab 8223 BUG_ON(!vcpu->mmio_needed);
5287f194 8224
716d51ab 8225 /* Complete previous fragment */
87da7e66
XG		 8226 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8227 len = min(8u, frag->len);
716d51ab 8228 if (!vcpu->mmio_is_write)
87da7e66
XG		 8229 memcpy(frag->data, run->mmio.data, len);
8230
8231 if (frag->len <= 8) {
8232 /* Switch to the next fragment. */
8233 frag++;
8234 vcpu->mmio_cur_fragment++;
8235 } else {
8236 /* Go forward to the next mmio piece. */
8237 frag->data += len;
8238 frag->gpa += len;
8239 frag->len -= len;
8240 }
8241
a08d3b3b 8242 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8243 vcpu->mmio_needed = 0;
0912c977
PB		 8244
8245 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8246 if (vcpu->mmio_is_write)
716d51ab
GN		 8247 return 1;
8248 vcpu->mmio_read_completed = 1;
8249 return complete_emulated_io(vcpu);
8250 }
87da7e66 8251
716d51ab
GN		 8252 run->exit_reason = KVM_EXIT_MMIO;
8253 run->mmio.phys_addr = frag->gpa;
8254 if (vcpu->mmio_is_write)
87da7e66
XG		 8255 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8256 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8257 run->mmio.is_write = vcpu->mmio_is_write;
8258 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8259 return 0;
5287f194
AK		 8260}
8261
822f312d
SAS		 8262/* Swap (qemu) user FPU context for the guest FPU context. */
8263static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8264{
5f409e20
RR		 8265 fpregs_lock();
8266
240c35a3 8267 copy_fpregs_to_fpstate(&current->thread.fpu);
822f312d 8268 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8269 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d 8270 ~XFEATURE_MASK_PKRU);
5f409e20
RR		 8271
8272 fpregs_mark_activate();
8273 fpregs_unlock();
8274
822f312d
SAS		 8275 trace_kvm_fpu(1);
8276}
8277
8278/* When vcpu_run ends, restore user space FPU context. */
8279static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8280{
5f409e20
RR		 8281 fpregs_lock();
8282
b666a4b6 8283 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
240c35a3 8284 copy_kernel_to_fpregs(&current->thread.fpu.state);
5f409e20
RR		 8285
8286 fpregs_mark_activate();
8287 fpregs_unlock();
8288
822f312d
SAS		 8289 ++vcpu->stat.fpu_reload;
8290 trace_kvm_fpu(0);
8291}
8292
b6c7a5dc
HB		 8293int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8294{
8295 int r;
b6c7a5dc 8296
accb757d 8297 vcpu_load(vcpu);
20b7035c 8298 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8299 kvm_load_guest_fpu(vcpu);
8300
a4535290 8301 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8302 if (kvm_run->immediate_exit) {
8303 r = -EINTR;
8304 goto out;
8305 }
b6c7a5dc 8306 kvm_vcpu_block(vcpu);
66450a21 8307 kvm_apic_accept_events(vcpu);
72875d8a 8308 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8309 r = -EAGAIN;
a0595000
JS		 8310 if (signal_pending(current)) {
8311 r = -EINTR;
8312 vcpu->run->exit_reason = KVM_EXIT_INTR;
8313 ++vcpu->stat.signal_exits;
8314 }
ac9f6dc0 8315 goto out;
b6c7a5dc
HB		 8316 }
8317
01643c51
KH		 8318 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8319 r = -EINVAL;
8320 goto out;
8321 }
8322
8323 if (vcpu->run->kvm_dirty_regs) {
8324 r = sync_regs(vcpu);
8325 if (r != 0)
8326 goto out;
8327 }
8328
b6c7a5dc 8329 /* re-sync apic's tpr */
35754c98 8330 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8331 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8332 r = -EINVAL;
8333 goto out;
8334 }
8335 }
b6c7a5dc 8336
716d51ab
GN		 8337 if (unlikely(vcpu->arch.complete_userspace_io)) {
8338 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8339 vcpu->arch.complete_userspace_io = NULL;
8340 r = cui(vcpu);
8341 if (r <= 0)
5663d8f9 8342 goto out;
716d51ab
GN		 8343 } else
8344 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8345
460df4c1
PB		 8346 if (kvm_run->immediate_exit)
8347 r = -EINTR;
8348 else
8349 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8350
8351out:
5663d8f9 8352 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8353 if (vcpu->run->kvm_valid_regs)
8354 store_regs(vcpu);
f1d86e46 8355 post_kvm_run_save(vcpu);
20b7035c 8356 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8357
accb757d 8358 vcpu_put(vcpu);
b6c7a5dc
HB		 8359 return r;
8360}
8361
01643c51 8362static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8363{
7ae441ea
GN		 8364 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8365 /*
8366 * We are here if userspace calls get_regs() in the middle of
8367 * instruction emulation. Registers state needs to be copied
4a969980 8368 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8369 * that usually, but some bad designed PV devices (vmware
8370 * backdoor interface) need this to work
8371 */
dd856efa 8372 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8373 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8374 }
de3cd117
SC		 8375 regs->rax = kvm_rax_read(vcpu);
8376 regs->rbx = kvm_rbx_read(vcpu);
8377 regs->rcx = kvm_rcx_read(vcpu);
8378 regs->rdx = kvm_rdx_read(vcpu);
8379 regs->rsi = kvm_rsi_read(vcpu);
8380 regs->rdi = kvm_rdi_read(vcpu);
e9c16c78 8381 regs->rsp = kvm_rsp_read(vcpu);
de3cd117 8382 regs->rbp = kvm_rbp_read(vcpu);
b6c7a5dc 8383#ifdef CONFIG_X86_64
de3cd117
SC		 8384 regs->r8 = kvm_r8_read(vcpu);
8385 regs->r9 = kvm_r9_read(vcpu);
8386 regs->r10 = kvm_r10_read(vcpu);
8387 regs->r11 = kvm_r11_read(vcpu);
8388 regs->r12 = kvm_r12_read(vcpu);
8389 regs->r13 = kvm_r13_read(vcpu);
8390 regs->r14 = kvm_r14_read(vcpu);
8391 regs->r15 = kvm_r15_read(vcpu);
b6c7a5dc
HB		 8392#endif
8393
5fdbf976 8394 regs->rip = kvm_rip_read(vcpu);
91586a3b 8395 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8396}
b6c7a5dc 8397
01643c51
KH		 8398int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8399{
8400 vcpu_load(vcpu);
8401 __get_regs(vcpu, regs);
1fc9b76b 8402 vcpu_put(vcpu);
b6c7a5dc
HB		 8403 return 0;
8404}
8405
01643c51 8406static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8407{
7ae441ea
GN		 8408 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8409 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8410
de3cd117
SC		 8411 kvm_rax_write(vcpu, regs->rax);
8412 kvm_rbx_write(vcpu, regs->rbx);
8413 kvm_rcx_write(vcpu, regs->rcx);
8414 kvm_rdx_write(vcpu, regs->rdx);
8415 kvm_rsi_write(vcpu, regs->rsi);
8416 kvm_rdi_write(vcpu, regs->rdi);
e9c16c78 8417 kvm_rsp_write(vcpu, regs->rsp);
de3cd117 8418 kvm_rbp_write(vcpu, regs->rbp);
b6c7a5dc 8419#ifdef CONFIG_X86_64
de3cd117
SC		 8420 kvm_r8_write(vcpu, regs->r8);
8421 kvm_r9_write(vcpu, regs->r9);
8422 kvm_r10_write(vcpu, regs->r10);
8423 kvm_r11_write(vcpu, regs->r11);
8424 kvm_r12_write(vcpu, regs->r12);
8425 kvm_r13_write(vcpu, regs->r13);
8426 kvm_r14_write(vcpu, regs->r14);
8427 kvm_r15_write(vcpu, regs->r15);
b6c7a5dc
HB		 8428#endif
8429
5fdbf976 8430 kvm_rip_write(vcpu, regs->rip);
d73235d1 8431 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8432
b4f14abd
JK		 8433 vcpu->arch.exception.pending = false;
8434
3842d135 8435 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8436}
3842d135 8437
01643c51
KH		 8438int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8439{
8440 vcpu_load(vcpu);
8441 __set_regs(vcpu, regs);
875656fe 8442 vcpu_put(vcpu);
b6c7a5dc
HB		 8443 return 0;
8444}
8445
b6c7a5dc
HB		 8446void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8447{
8448 struct kvm_segment cs;
8449
3e6e0aab 8450 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8451 *db = cs.db;
8452 *l = cs.l;
8453}
8454EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8455
01643c51 8456static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8457{
89a27f4d 8458 struct desc_ptr dt;
b6c7a5dc 8459
3e6e0aab
GT		 8460 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8461 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8462 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8463 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8464 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8465 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8466
3e6e0aab
GT		 8467 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8468 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8469
8470 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8471 sregs->idt.limit = dt.size;
8472 sregs->idt.base = dt.address;
b6c7a5dc 8473 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8474 sregs->gdt.limit = dt.size;
8475 sregs->gdt.base = dt.address;
b6c7a5dc 8476
4d4ec087 8477 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8478 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8479 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8480 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8481 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8482 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8483 sregs->apic_base = kvm_get_apic_base(vcpu);
8484
0e96f31e 8485 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8486
04140b41 8487 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8488 set_bit(vcpu->arch.interrupt.nr,
8489 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8490}
16d7a191 8491
01643c51
KH		 8492int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8493 struct kvm_sregs *sregs)
8494{
8495 vcpu_load(vcpu);
8496 __get_sregs(vcpu, sregs);
bcdec41c 8497 vcpu_put(vcpu);
b6c7a5dc
HB		 8498 return 0;
8499}
8500
62d9f0db
MT		 8501int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8502 struct kvm_mp_state *mp_state)
8503{
fd232561
CD		 8504 vcpu_load(vcpu);
8505
66450a21 8506 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8507 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8508 vcpu->arch.pv.pv_unhalted)
8509 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8510 else
8511 mp_state->mp_state = vcpu->arch.mp_state;
8512
fd232561 8513 vcpu_put(vcpu);
62d9f0db
MT		 8514 return 0;
8515}
8516
8517int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8518 struct kvm_mp_state *mp_state)
8519{
e83dff5e
CD		 8520 int ret = -EINVAL;
8521
8522 vcpu_load(vcpu);
8523
bce87cce 8524 if (!lapic_in_kernel(vcpu) &&
66450a21 8525 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8526 goto out;
66450a21 8527
28bf2888
DH		 8528 /* INITs are latched while in SMM */
8529 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8530 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8531 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8532 goto out;
28bf2888 8533
66450a21
JK		 8534 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8535 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8536 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8537 } else
8538 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8539 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8540
8541 ret = 0;
8542out:
8543 vcpu_put(vcpu);
8544 return ret;
62d9f0db
MT		 8545}
8546
7f3d35fd
KW		 8547int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8548 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8549{
9d74191a 8550 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8551 int ret;
e01c2426 8552
8ec4722d 8553 init_emulate_ctxt(vcpu);
c697518a 8554
7f3d35fd 8555 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8556 has_error_code, error_code);
c697518a 8557
c697518a 8558 if (ret)
19d04437 8559 return EMULATE_FAIL;
37817f29 8560
9d74191a
TY		 8561 kvm_rip_write(vcpu, ctxt->eip);
8562 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8563 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8564 return EMULATE_DONE;
37817f29
IE		 8565}
8566EXPORT_SYMBOL_GPL(kvm_task_switch);
8567
3140c156 8568static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8569{
74fec5b9
TL		 8570 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8571 (sregs->cr4 & X86_CR4_OSXSAVE))
8572 return -EINVAL;
8573
37b95951 8574 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8575 /*
8576 * When EFER.LME and CR0.PG are set, the processor is in
8577 * 64-bit mode (though maybe in a 32-bit code segment).
8578 * CR4.PAE and EFER.LMA must be set.
8579 */
37b95951 8580 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8581 || !(sregs->efer & EFER_LMA))
8582 return -EINVAL;
8583 } else {
8584 /*
8585 * Not in 64-bit mode: EFER.LMA is clear and the code
8586 * segment cannot be 64-bit.
8587 */
8588 if (sregs->efer & EFER_LMA || sregs->cs.l)
8589 return -EINVAL;
8590 }
8591
8592 return 0;
8593}
8594
01643c51 8595static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8596{
58cb628d 8597 struct msr_data apic_base_msr;
b6c7a5dc 8598 int mmu_reset_needed = 0;
c4d21882 8599 int cpuid_update_needed = 0;
63f42e02 8600 int pending_vec, max_bits, idx;
89a27f4d 8601 struct desc_ptr dt;
b4ef9d4e
CD		 8602 int ret = -EINVAL;
8603
f2981033 8604 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8605 goto out;
f2981033 8606
d3802286
JM		 8607 apic_base_msr.data = sregs->apic_base;
8608 apic_base_msr.host_initiated = true;
8609 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8610 goto out;
6d1068b3 8611
89a27f4d
GN		 8612 dt.size = sregs->idt.limit;
8613 dt.address = sregs->idt.base;
b6c7a5dc 8614 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8615 dt.size = sregs->gdt.limit;
8616 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8617 kvm_x86_ops->set_gdt(vcpu, &dt);
8618
ad312c7c 8619 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8620 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8621 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8622 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8623
2d3ad1f4 8624 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8625
f6801dff 8626 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8627 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8628
4d4ec087 8629 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8630 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8631 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8632
fc78f519 8633 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8634 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8635 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8636 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8637 if (cpuid_update_needed)
00b27a3e 8638 kvm_update_cpuid(vcpu);
63f42e02
XG		 8639
8640 idx = srcu_read_lock(&vcpu->kvm->srcu);
bf03d4f9 8641 if (is_pae_paging(vcpu)) {
9f8fe504 8642 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8643 mmu_reset_needed = 1;
8644 }
63f42e02 8645 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8646
8647 if (mmu_reset_needed)
8648 kvm_mmu_reset_context(vcpu);
8649
a50abc3b 8650 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8651 pending_vec = find_first_bit(
8652 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8653 if (pending_vec < max_bits) {
66fd3f7f 8654 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8655 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8656 }
8657
3e6e0aab
GT		 8658 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8659 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8660 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8661 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8662 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8663 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8664
3e6e0aab
GT		 8665 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8666 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8667
5f0269f5
ME		 8668 update_cr8_intercept(vcpu);
8669
9c3e4aab 8670 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8671 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8672 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8673 !is_protmode(vcpu))
9c3e4aab
MT		 8674 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8675
3842d135
AK		 8676 kvm_make_request(KVM_REQ_EVENT, vcpu);
8677
b4ef9d4e
CD		 8678 ret = 0;
8679out:
01643c51
KH		 8680 return ret;
8681}
8682
8683int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8684 struct kvm_sregs *sregs)
8685{
8686 int ret;
8687
8688 vcpu_load(vcpu);
8689 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8690 vcpu_put(vcpu);
8691 return ret;
b6c7a5dc
HB		 8692}
8693
d0bfb940
JK		 8694int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8695 struct kvm_guest_debug *dbg)
b6c7a5dc 8696{
355be0b9 8697 unsigned long rflags;
ae675ef0 8698 int i, r;
b6c7a5dc 8699
66b56562
CD		 8700 vcpu_load(vcpu);
8701
4f926bf2
JK		 8702 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8703 r = -EBUSY;
8704 if (vcpu->arch.exception.pending)
2122ff5e 8705 goto out;
4f926bf2
JK		 8706 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8707 kvm_queue_exception(vcpu, DB_VECTOR);
8708 else
8709 kvm_queue_exception(vcpu, BP_VECTOR);
8710 }
8711
91586a3b
JK		 8712 /*
8713 * Read rflags as long as potentially injected trace flags are still
8714 * filtered out.
8715 */
8716 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8717
8718 vcpu->guest_debug = dbg->control;
8719 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8720 vcpu->guest_debug = 0;
8721
8722 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8723 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8724 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8725 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8726 } else {
8727 for (i = 0; i < KVM_NR_DB_REGS; i++)
8728 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8729 }
c8639010 8730 kvm_update_dr7(vcpu);
ae675ef0 8731
f92653ee
JK		 8732 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8733 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8734 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8735
91586a3b
JK		 8736 /*
8737 * Trigger an rflags update that will inject or remove the trace
8738 * flags.
8739 */
8740 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8741
a96036b8 8742 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8743
4f926bf2 8744 r = 0;
d0bfb940 8745
2122ff5e 8746out:
66b56562 8747 vcpu_put(vcpu);
b6c7a5dc
HB		 8748 return r;
8749}
8750
8b006791
ZX		 8751/*
8752 * Translate a guest virtual address to a guest physical address.
8753 */
8754int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8755 struct kvm_translation *tr)
8756{
8757 unsigned long vaddr = tr->linear_address;
8758 gpa_t gpa;
f656ce01 8759 int idx;
8b006791 8760
1da5b61d
CD		 8761 vcpu_load(vcpu);
8762
f656ce01 8763 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8764 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8765 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8766 tr->physical_address = gpa;
8767 tr->valid = gpa != UNMAPPED_GVA;
8768 tr->writeable = 1;
8769 tr->usermode = 0;
8b006791 8770
1da5b61d 8771 vcpu_put(vcpu);
8b006791
ZX		 8772 return 0;
8773}
8774
d0752060
HB		 8775int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8776{
1393123e 8777 struct fxregs_state *fxsave;
d0752060 8778
1393123e 8779 vcpu_load(vcpu);
d0752060 8780
b666a4b6 8781 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8782 memcpy(fpu->fpr, fxsave->st_space, 128);
8783 fpu->fcw = fxsave->cwd;
8784 fpu->fsw = fxsave->swd;
8785 fpu->ftwx = fxsave->twd;
8786 fpu->last_opcode = fxsave->fop;
8787 fpu->last_ip = fxsave->rip;
8788 fpu->last_dp = fxsave->rdp;
0e96f31e 8789 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8790
1393123e 8791 vcpu_put(vcpu);
d0752060
HB		 8792 return 0;
8793}
8794
8795int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8796{
6a96bc7f
CD		 8797 struct fxregs_state *fxsave;
8798
8799 vcpu_load(vcpu);
8800
b666a4b6 8801 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8802
d0752060
HB		 8803 memcpy(fxsave->st_space, fpu->fpr, 128);
8804 fxsave->cwd = fpu->fcw;
8805 fxsave->swd = fpu->fsw;
8806 fxsave->twd = fpu->ftwx;
8807 fxsave->fop = fpu->last_opcode;
8808 fxsave->rip = fpu->last_ip;
8809 fxsave->rdp = fpu->last_dp;
0e96f31e 8810 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8811
6a96bc7f 8812 vcpu_put(vcpu);
d0752060
HB		 8813 return 0;
8814}
8815
01643c51
KH		 8816static void store_regs(struct kvm_vcpu *vcpu)
8817{
8818 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8819
8820 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8821 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8822
8823 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8824 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8825
8826 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8827 kvm_vcpu_ioctl_x86_get_vcpu_events(
8828 vcpu, &vcpu->run->s.regs.events);
8829}
8830
8831static int sync_regs(struct kvm_vcpu *vcpu)
8832{
8833 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8834 return -EINVAL;
8835
8836 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8837 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8838 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8839 }
8840 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8841 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8842 return -EINVAL;
8843 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8844 }
8845 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8846 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8847 vcpu, &vcpu->run->s.regs.events))
8848 return -EINVAL;
8849 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8850 }
8851
8852 return 0;
8853}
8854
0ee6a517 8855static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8856{
b666a4b6 8857 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 8858 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 8859 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 8860 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8861
2acf923e
DC		 8862 /*
8863 * Ensure guest xcr0 is valid for loading
8864 */
d91cab78 8865 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8866
ad312c7c 8867 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8868}
d0752060 8869
e9b11c17
ZX		 8870void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8871{
bd768e14
IY		 8872 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8873
12f9a48f 8874 kvmclock_reset(vcpu);
7f1ea208 8875
e9b11c17 8876 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8877 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8878}
8879
8880struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8881 unsigned int id)
8882{
c447e76b
LL		 8883 struct kvm_vcpu *vcpu;
8884
b0c39dc6 8885 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8886 printk_once(KERN_WARNING
8887 "kvm: SMP vm created on host with unstable TSC; "
8888 "guest TSC will not be reliable\n");
c447e76b
LL		 8889
8890 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8891
c447e76b 8892 return vcpu;
26e5215f 8893}
e9b11c17 8894
26e5215f
AK		 8895int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8896{
0cf9135b 8897 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 8898 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 8899 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8900 vcpu_load(vcpu);
d28bc9dd 8901 kvm_vcpu_reset(vcpu, false);
e1732991 8902 kvm_init_mmu(vcpu, false);
e9b11c17 8903 vcpu_put(vcpu);
ec7660cc 8904 return 0;
e9b11c17
ZX		 8905}
8906
31928aa5 8907void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8908{
8fe8ab46 8909 struct msr_data msr;
332967a3 8910 struct kvm *kvm = vcpu->kvm;
42897d86 8911
d3457c87
RK		 8912 kvm_hv_vcpu_postcreate(vcpu);
8913
ec7660cc 8914 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8915 return;
ec7660cc 8916 vcpu_load(vcpu);
8fe8ab46
WA		 8917 msr.data = 0x0;
8918 msr.index = MSR_IA32_TSC;
8919 msr.host_initiated = true;
8920 kvm_write_tsc(vcpu, &msr);
42897d86 8921 vcpu_put(vcpu);
2d5ba19b
MT		 8922
8923 /* poll control enabled by default */
8924 vcpu->arch.msr_kvm_poll_control = 1;
8925
ec7660cc 8926 mutex_unlock(&vcpu->mutex);
42897d86 8927
630994b3
MT		 8928 if (!kvmclock_periodic_sync)
8929 return;
8930
332967a3
AJ		 8931 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8932 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8933}
8934
d40ccc62 8935void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8936{
344d9588
GN		 8937 vcpu->arch.apf.msr_val = 0;
8938
ec7660cc 8939 vcpu_load(vcpu);
e9b11c17
ZX		 8940 kvm_mmu_unload(vcpu);
8941 vcpu_put(vcpu);
8942
8943 kvm_x86_ops->vcpu_free(vcpu);
8944}
8945
d28bc9dd 8946void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8947{
b7e31be3
RK		 8948 kvm_lapic_reset(vcpu, init_event);
8949
e69fab5d
PB		 8950 vcpu->arch.hflags = 0;
8951
c43203ca 8952 vcpu->arch.smi_pending = 0;
52797bf9 8953 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8954 atomic_set(&vcpu->arch.nmi_queued, 0);
8955 vcpu->arch.nmi_pending = 0;
448fa4a9 8956 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8957 kvm_clear_interrupt_queue(vcpu);
8958 kvm_clear_exception_queue(vcpu);
664f8e26 8959 vcpu->arch.exception.pending = false;
448fa4a9 8960
42dbaa5a 8961 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8962 kvm_update_dr0123(vcpu);
6f43ed01 8963 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8964 kvm_update_dr6(vcpu);
42dbaa5a 8965 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8966 kvm_update_dr7(vcpu);
42dbaa5a 8967
1119022c
NA		 8968 vcpu->arch.cr2 = 0;
8969
3842d135 8970 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8971 vcpu->arch.apf.msr_val = 0;
c9aaa895 8972 vcpu->arch.st.msr_val = 0;
3842d135 8973
12f9a48f
GC		 8974 kvmclock_reset(vcpu);
8975
af585b92
GN		 8976 kvm_clear_async_pf_completion_queue(vcpu);
8977 kvm_async_pf_hash_reset(vcpu);
8978 vcpu->arch.apf.halted = false;
3842d135 8979
a554d207
WL		 8980 if (kvm_mpx_supported()) {
8981 void *mpx_state_buffer;
8982
8983 /*
8984 * To avoid have the INIT path from kvm_apic_has_events() that be
8985 * called with loaded FPU and does not let userspace fix the state.
8986 */
f775b13e
RR		 8987 if (init_event)
8988 kvm_put_guest_fpu(vcpu);
b666a4b6 8989 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 8990 XFEATURE_BNDREGS);
a554d207
WL		 8991 if (mpx_state_buffer)
8992 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 8993 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 8994 XFEATURE_BNDCSR);
a554d207
WL		 8995 if (mpx_state_buffer)
8996 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8997 if (init_event)
8998 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8999 }
9000
64d60670 9001 if (!init_event) {
d28bc9dd 9002 kvm_pmu_reset(vcpu);
64d60670 9003 vcpu->arch.smbase = 0x30000;
db2336a8 9004
db2336a8 9005 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 9006
9007 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 9008 }
f5132b01 9009
66f7b72e
JS		 9010 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9011 vcpu->arch.regs_avail = ~0;
9012 vcpu->arch.regs_dirty = ~0;
9013
a554d207
WL		 9014 vcpu->arch.ia32_xss = 0;
9015
d28bc9dd 9016 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 9017}
9018
2b4a273b 9019void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 9020{
9021 struct kvm_segment cs;
9022
9023 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9024 cs.selector = vector << 8;
9025 cs.base = vector << 12;
9026 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9027 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 9028}
9029
13a34e06 9030int kvm_arch_hardware_enable(void)
e9b11c17 9031{
ca84d1a2
ZA		 9032 struct kvm *kvm;
9033 struct kvm_vcpu *vcpu;
9034 int i;
0dd6a6ed
ZA		 9035 int ret;
9036 u64 local_tsc;
9037 u64 max_tsc = 0;
9038 bool stable, backwards_tsc = false;
18863bdd
AK		 9039
9040 kvm_shared_msr_cpu_online();
13a34e06 9041 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 9042 if (ret != 0)
9043 return ret;
9044
4ea1636b 9045 local_tsc = rdtsc();
b0c39dc6 9046 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 9047 list_for_each_entry(kvm, &vm_list, vm_list) {
9048 kvm_for_each_vcpu(i, vcpu, kvm) {
9049 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 9050 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9051 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9052 backwards_tsc = true;
9053 if (vcpu->arch.last_host_tsc > max_tsc)
9054 max_tsc = vcpu->arch.last_host_tsc;
9055 }
9056 }
9057 }
9058
9059 /*
9060 * Sometimes, even reliable TSCs go backwards. This happens on
9061 * platforms that reset TSC during suspend or hibernate actions, but
9062 * maintain synchronization. We must compensate. Fortunately, we can
9063 * detect that condition here, which happens early in CPU bringup,
9064 * before any KVM threads can be running. Unfortunately, we can't
9065 * bring the TSCs fully up to date with real time, as we aren't yet far
9066 * enough into CPU bringup that we know how much real time has actually
9285ec4c 9067 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
0dd6a6ed
ZA		 9068 * variables that haven't been updated yet.
9069 *
9070 * So we simply find the maximum observed TSC above, then record the
9071 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9072 * the adjustment will be applied. Note that we accumulate
9073 * adjustments, in case multiple suspend cycles happen before some VCPU
9074 * gets a chance to run again. In the event that no KVM threads get a
9075 * chance to run, we will miss the entire elapsed period, as we'll have
9076 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9077 * loose cycle time. This isn't too big a deal, since the loss will be
9078 * uniform across all VCPUs (not to mention the scenario is extremely
9079 * unlikely). It is possible that a second hibernate recovery happens
9080 * much faster than a first, causing the observed TSC here to be
9081 * smaller; this would require additional padding adjustment, which is
9082 * why we set last_host_tsc to the local tsc observed here.
9083 *
9084 * N.B. - this code below runs only on platforms with reliable TSC,
9085 * as that is the only way backwards_tsc is set above. Also note
9086 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9087 * have the same delta_cyc adjustment applied if backwards_tsc
9088 * is detected. Note further, this adjustment is only done once,
9089 * as we reset last_host_tsc on all VCPUs to stop this from being
9090 * called multiple times (one for each physical CPU bringup).
9091 *
4a969980 9092 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 9093 * will be compensated by the logic in vcpu_load, which sets the TSC to
9094 * catchup mode. This will catchup all VCPUs to real time, but cannot
9095 * guarantee that they stay in perfect synchronization.
9096 */
9097 if (backwards_tsc) {
9098 u64 delta_cyc = max_tsc - local_tsc;
9099 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 9100 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 9101 kvm_for_each_vcpu(i, vcpu, kvm) {
9102 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9103 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 9104 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9105 }
9106
9107 /*
9108 * We have to disable TSC offset matching.. if you were
9109 * booting a VM while issuing an S4 host suspend....
9110 * you may have some problem. Solving this issue is
9111 * left as an exercise to the reader.
9112 */
9113 kvm->arch.last_tsc_nsec = 0;
9114 kvm->arch.last_tsc_write = 0;
9115 }
9116
9117 }
9118 return 0;
e9b11c17
ZX		 9119}
9120
13a34e06 9121void kvm_arch_hardware_disable(void)
e9b11c17 9122{
13a34e06
RK		 9123 kvm_x86_ops->hardware_disable();
9124 drop_user_return_notifiers();
e9b11c17
ZX		 9125}
9126
9127int kvm_arch_hardware_setup(void)
9128{
9e9c3fe4
NA		 9129 int r;
9130
9131 r = kvm_x86_ops->hardware_setup();
9132 if (r != 0)
9133 return r;
9134
35181e86
HZ		 9135 if (kvm_has_tsc_control) {
9136 /*
9137 * Make sure the user can only configure tsc_khz values that
9138 * fit into a signed integer.
273ba457 9139 * A min value is not calculated because it will always
35181e86
HZ		 9140 * be 1 on all machines.
9141 */
9142 u64 max = min(0x7fffffffULL,
9143 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9144 kvm_max_guest_tsc_khz = max;
9145
ad721883 9146 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9147 }
ad721883 9148
9e9c3fe4
NA		 9149 kvm_init_msr_list();
9150 return 0;
e9b11c17
ZX		 9151}
9152
9153void kvm_arch_hardware_unsetup(void)
9154{
9155 kvm_x86_ops->hardware_unsetup();
9156}
9157
f257d6dc 9158int kvm_arch_check_processor_compat(void)
e9b11c17 9159{
f257d6dc 9160 return kvm_x86_ops->check_processor_compatibility();
d71ba788
PB		 9161}
9162
9163bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9164{
9165 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9166}
9167EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9168
9169bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9170{
9171 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9172}
9173
54e9818f 9174struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9175EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9176
e9b11c17
ZX		 9177int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9178{
9179 struct page *page;
e9b11c17
ZX		 9180 int r;
9181
9aabc88f 9182 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9183 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9184 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9185 else
a4535290 9186 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9187
9188 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9189 if (!page) {
9190 r = -ENOMEM;
9191 goto fail;
9192 }
ad312c7c 9193 vcpu->arch.pio_data = page_address(page);
e9b11c17 9194
cc578287 9195 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9196
e9b11c17
ZX		 9197 r = kvm_mmu_create(vcpu);
9198 if (r < 0)
9199 goto fail_free_pio_data;
9200
26de7988 9201 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9202 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
39497d76 9203 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
e9b11c17
ZX		 9204 if (r < 0)
9205 goto fail_mmu_destroy;
54e9818f
GN		 9206 } else
9207 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9208
890ca9ae 9209 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
254272ce 9210 GFP_KERNEL_ACCOUNT);
890ca9ae
HY		 9211 if (!vcpu->arch.mce_banks) {
9212 r = -ENOMEM;
443c39bc 9213 goto fail_free_lapic;
890ca9ae
HY		 9214 }
9215 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9216
254272ce
BG		 9217 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9218 GFP_KERNEL_ACCOUNT)) {
f1797359 9219 r = -ENOMEM;
f5f48ee1 9220 goto fail_free_mce_banks;
f1797359 9221 }
f5f48ee1 9222
0ee6a517 9223 fx_init(vcpu);
66f7b72e 9224
4344ee98 9225 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9226
5a4f55cd
EK		 9227 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9228
74545705
RK		 9229 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9230
af585b92 9231 kvm_async_pf_hash_reset(vcpu);
f5132b01 9232 kvm_pmu_init(vcpu);
af585b92 9233
1c1a9ce9 9234 vcpu->arch.pending_external_vector = -1;
de63ad4c 9235 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9236
5c919412
AS		 9237 kvm_hv_vcpu_init(vcpu);
9238
e9b11c17 9239 return 0;
0ee6a517 9240
f5f48ee1
SY		 9241fail_free_mce_banks:
9242 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9243fail_free_lapic:
9244 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9245fail_mmu_destroy:
9246 kvm_mmu_destroy(vcpu);
9247fail_free_pio_data:
ad312c7c 9248 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9249fail:
9250 return r;
9251}
9252
9253void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9254{
f656ce01
MT		 9255 int idx;
9256
1f4b34f8 9257 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9258 kvm_pmu_destroy(vcpu);
36cb93fd 9259 kfree(vcpu->arch.mce_banks);
e9b11c17 9260 kvm_free_lapic(vcpu);
f656ce01 9261 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9262 kvm_mmu_destroy(vcpu);
f656ce01 9263 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9264 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9265 if (!lapic_in_kernel(vcpu))
54e9818f 9266 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9267}
d19a9cd2 9268
e790d9ef
RK		 9269void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9270{
c595ceee 9271 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9272 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9273}
9274
e08b9637 9275int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9276{
e08b9637
CO		 9277 if (type)
9278 return -EINVAL;
9279
6ef768fa 9280 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9281 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 9282 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9283 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9284
5550af4d
SY		 9285 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9286 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9287 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9288 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9289 &kvm->arch.irq_sources_bitmap);
5550af4d 9290
038f8c11 9291 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9292 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9293 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9294
9285ec4c 9295 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
d828199e 9296 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9297
6fbbde9a
DS		 9298 kvm->arch.guest_can_read_msr_platform_info = true;
9299
7e44e449 9300 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9301 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9302
cbc0236a 9303 kvm_hv_init_vm(kvm);
0eb05bf2 9304 kvm_page_track_init(kvm);
13d268ca 9305 kvm_mmu_init_vm(kvm);
0eb05bf2 9306
03543133
SS		 9307 if (kvm_x86_ops->vm_init)
9308 return kvm_x86_ops->vm_init(kvm);
9309
d89f5eff 9310 return 0;
d19a9cd2
ZX		 9311}
9312
9313static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9314{
ec7660cc 9315 vcpu_load(vcpu);
d19a9cd2
ZX		 9316 kvm_mmu_unload(vcpu);
9317 vcpu_put(vcpu);
9318}
9319
9320static void kvm_free_vcpus(struct kvm *kvm)
9321{
9322 unsigned int i;
988a2cae 9323 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9324
9325 /*
9326 * Unpin any mmu pages first.
9327 */
af585b92
GN		 9328 kvm_for_each_vcpu(i, vcpu, kvm) {
9329 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9330 kvm_unload_vcpu_mmu(vcpu);
af585b92 9331 }
988a2cae
GN		 9332 kvm_for_each_vcpu(i, vcpu, kvm)
9333 kvm_arch_vcpu_free(vcpu);
9334
9335 mutex_lock(&kvm->lock);
9336 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9337 kvm->vcpus[i] = NULL;
d19a9cd2 9338
988a2cae
GN		 9339 atomic_set(&kvm->online_vcpus, 0);
9340 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9341}
9342
ad8ba2cd
SY		 9343void kvm_arch_sync_events(struct kvm *kvm)
9344{
332967a3 9345 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9346 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9347 kvm_free_pit(kvm);
ad8ba2cd
SY		 9348}
9349
1d8007bd 9350int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9351{
9352 int i, r;
25188b99 9353 unsigned long hva;
f0d648bd
PB		 9354 struct kvm_memslots *slots = kvm_memslots(kvm);
9355 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9356
9357 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9358 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9359 return -EINVAL;
9da0e4d5 9360
f0d648bd
PB		 9361 slot = id_to_memslot(slots, id);
9362 if (size) {
b21629da 9363 if (slot->npages)
f0d648bd
PB		 9364 return -EEXIST;
9365
9366 /*
9367 * MAP_SHARED to prevent internal slot pages from being moved
9368 * by fork()/COW.
9369 */
9370 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9371 MAP_SHARED | MAP_ANONYMOUS, 0);
9372 if (IS_ERR((void *)hva))
9373 return PTR_ERR((void *)hva);
9374 } else {
9375 if (!slot->npages)
9376 return 0;
9377
9378 hva = 0;
9379 }
9380
9381 old = *slot;
9da0e4d5 9382 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9383 struct kvm_userspace_memory_region m;
9da0e4d5 9384
1d8007bd
PB		 9385 m.slot = id | (i << 16);
9386 m.flags = 0;
9387 m.guest_phys_addr = gpa;
f0d648bd 9388 m.userspace_addr = hva;
1d8007bd 9389 m.memory_size = size;
9da0e4d5
PB		 9390 r = __kvm_set_memory_region(kvm, &m);
9391 if (r < 0)
9392 return r;
9393 }
9394
103c763c
EB		 9395 if (!size)
9396 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9397
9da0e4d5
PB		 9398 return 0;
9399}
9400EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9401
1d8007bd 9402int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9403{
9404 int r;
9405
9406 mutex_lock(&kvm->slots_lock);
1d8007bd 9407 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9408 mutex_unlock(&kvm->slots_lock);
9409
9410 return r;
9411}
9412EXPORT_SYMBOL_GPL(x86_set_memory_region);
9413
d19a9cd2
ZX		 9414void kvm_arch_destroy_vm(struct kvm *kvm)
9415{
27469d29
AH		 9416 if (current->mm == kvm->mm) {
9417 /*
9418 * Free memory regions allocated on behalf of userspace,
9419 * unless the the memory map has changed due to process exit
9420 * or fd copying.
9421 */
1d8007bd
PB		 9422 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9423 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9424 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9425 }
03543133
SS		 9426 if (kvm_x86_ops->vm_destroy)
9427 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9428 kvm_pic_destroy(kvm);
9429 kvm_ioapic_destroy(kvm);
d19a9cd2 9430 kvm_free_vcpus(kvm);
af1bae54 9431 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
66bb8a06 9432 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
13d268ca 9433 kvm_mmu_uninit_vm(kvm);
2beb6dad 9434 kvm_page_track_cleanup(kvm);
cbc0236a 9435 kvm_hv_destroy_vm(kvm);
d19a9cd2 9436}
0de10343 9437
5587027c 9438void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9439 struct kvm_memory_slot *dont)
9440{
9441 int i;
9442
d89cc617
TY		 9443 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9444 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9445 kvfree(free->arch.rmap[i]);
d89cc617 9446 free->arch.rmap[i] = NULL;
77d11309 9447 }
d89cc617
TY		 9448 if (i == 0)
9449 continue;
9450
9451 if (!dont || free->arch.lpage_info[i - 1] !=
9452 dont->arch.lpage_info[i - 1]) {
548ef284 9453 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9454 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9455 }
9456 }
21ebbeda
XG		 9457
9458 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9459}
9460
5587027c
AK		 9461int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9462 unsigned long npages)
db3fe4eb
TY		 9463{
9464 int i;
9465
d89cc617 9466 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9467 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9468 unsigned long ugfn;
9469 int lpages;
d89cc617 9470 int level = i + 1;
db3fe4eb
TY		 9471
9472 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9473 slot->base_gfn, level) + 1;
9474
d89cc617 9475 slot->arch.rmap[i] =
778e1cdd 9476 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9477 GFP_KERNEL_ACCOUNT);
d89cc617 9478 if (!slot->arch.rmap[i])
77d11309 9479 goto out_free;
d89cc617
TY		 9480 if (i == 0)
9481 continue;
77d11309 9482
254272ce 9483 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9484 if (!linfo)
db3fe4eb
TY		 9485 goto out_free;
9486
92f94f1e
XG		 9487 slot->arch.lpage_info[i - 1] = linfo;
9488
db3fe4eb 9489 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9490 linfo[0].disallow_lpage = 1;
db3fe4eb 9491 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9492 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9493 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9494 /*
9495 * If the gfn and userspace address are not aligned wrt each
9496 * other, or if explicitly asked to, disable large page
9497 * support for this slot
9498 */
9499 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9500 !kvm_largepages_enabled()) {
9501 unsigned long j;
9502
9503 for (j = 0; j < lpages; ++j)
92f94f1e 9504 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9505 }
9506 }
9507
21ebbeda
XG		 9508 if (kvm_page_track_create_memslot(slot, npages))
9509 goto out_free;
9510
db3fe4eb
TY		 9511 return 0;
9512
9513out_free:
d89cc617 9514 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9515 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9516 slot->arch.rmap[i] = NULL;
9517 if (i == 0)
9518 continue;
9519
548ef284 9520 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9521 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9522 }
9523 return -ENOMEM;
9524}
9525
15248258 9526void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9527{
e6dff7d1
TY		 9528 /*
9529 * memslots->generation has been incremented.
9530 * mmio generation may have reached its maximum value.
9531 */
15248258 9532 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9533}
9534
f7784b8e
MT		 9535int kvm_arch_prepare_memory_region(struct kvm *kvm,
9536 struct kvm_memory_slot *memslot,
09170a49 9537 const struct kvm_userspace_memory_region *mem,
7b6195a9 9538 enum kvm_mr_change change)
0de10343 9539{
f7784b8e
MT		 9540 return 0;
9541}
9542
88178fd4
KH		 9543static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9544 struct kvm_memory_slot *new)
9545{
9546 /* Still write protect RO slot */
9547 if (new->flags & KVM_MEM_READONLY) {
9548 kvm_mmu_slot_remove_write_access(kvm, new);
9549 return;
9550 }
9551
9552 /*
9553 * Call kvm_x86_ops dirty logging hooks when they are valid.
9554 *
9555 * kvm_x86_ops->slot_disable_log_dirty is called when:
9556 *
9557 * - KVM_MR_CREATE with dirty logging is disabled
9558 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9559 *
9560 * The reason is, in case of PML, we need to set D-bit for any slots
9561 * with dirty logging disabled in order to eliminate unnecessary GPA
9562 * logging in PML buffer (and potential PML buffer full VMEXT). This
9563 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9564 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9565 * logging disabled for memory slots.
9566 *
9567 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9568 * to dirty logging mode.
9569 *
9570 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9571 *
9572 * In case of write protect:
9573 *
9574 * Write protect all pages for dirty logging.
9575 *
9576 * All the sptes including the large sptes which point to this
9577 * slot are set to readonly. We can not create any new large
9578 * spte on this slot until the end of the logging.
9579 *
9580 * See the comments in fast_page_fault().
9581 */
9582 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9583 if (kvm_x86_ops->slot_enable_log_dirty)
9584 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9585 else
9586 kvm_mmu_slot_remove_write_access(kvm, new);
9587 } else {
9588 if (kvm_x86_ops->slot_disable_log_dirty)
9589 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9590 }
9591}
9592
f7784b8e 9593void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9594 const struct kvm_userspace_memory_region *mem,
8482644a 9595 const struct kvm_memory_slot *old,
f36f3f28 9596 const struct kvm_memory_slot *new,
8482644a 9597 enum kvm_mr_change change)
f7784b8e 9598{
48c0e4e9 9599 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9600 kvm_mmu_change_mmu_pages(kvm,
9601 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9602
3ea3b7fa
WL		 9603 /*
9604 * Dirty logging tracks sptes in 4k granularity, meaning that large
9605 * sptes have to be split. If live migration is successful, the guest
9606 * in the source machine will be destroyed and large sptes will be
9607 * created in the destination. However, if the guest continues to run
9608 * in the source machine (for example if live migration fails), small
9609 * sptes will remain around and cause bad performance.
9610 *
9611 * Scan sptes if dirty logging has been stopped, dropping those
9612 * which can be collapsed into a single large-page spte. Later
9613 * page faults will create the large-page sptes.
9614 */
9615 if ((change != KVM_MR_DELETE) &&
9616 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9617 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9618 kvm_mmu_zap_collapsible_sptes(kvm, new);
9619
c972f3b1 9620 /*
88178fd4 9621 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9622 *
88178fd4
KH		 9623 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9624 * been zapped so no dirty logging staff is needed for old slot. For
9625 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9626 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9627 *
9628 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9629 */
88178fd4 9630 if (change != KVM_MR_DELETE)
f36f3f28 9631 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9632}
1d737c8a 9633
2df72e9b 9634void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9635{
7390de1e 9636 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9637}
9638
2df72e9b
MT		 9639void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9640 struct kvm_memory_slot *slot)
9641{
ae7cd873 9642 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9643}
9644
e6c67d8c
LA		 9645static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9646{
9647 return (is_guest_mode(vcpu) &&
9648 kvm_x86_ops->guest_apic_has_interrupt &&
9649 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9650}
9651
5d9bc648
PB		 9652static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9653{
9654 if (!list_empty_careful(&vcpu->async_pf.done))
9655 return true;
9656
9657 if (kvm_apic_has_events(vcpu))
9658 return true;
9659
9660 if (vcpu->arch.pv.pv_unhalted)
9661 return true;
9662
a5f01f8e
WL		 9663 if (vcpu->arch.exception.pending)
9664 return true;
9665
47a66eed
Z		 9666 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9667 (vcpu->arch.nmi_pending &&
9668 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9669 return true;
9670
47a66eed
Z		 9671 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9672 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9673 return true;
9674
5d9bc648 9675 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9676 (kvm_cpu_has_interrupt(vcpu) ||
9677 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9678 return true;
9679
1f4b34f8
AS		 9680 if (kvm_hv_has_stimer_pending(vcpu))
9681 return true;
9682
5d9bc648
PB		 9683 return false;
9684}
9685
1d737c8a
ZX		 9686int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9687{
5d9bc648 9688 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9689}
5736199a 9690
199b5763
LM		 9691bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9692{
de63ad4c 9693 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9694}
9695
b6d33834 9696int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9697{
b6d33834 9698 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9699}
78646121
GN		 9700
9701int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9702{
9703 return kvm_x86_ops->interrupt_allowed(vcpu);
9704}
229456fc 9705
82b32774 9706unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9707{
82b32774
NA		 9708 if (is_64_bit_mode(vcpu))
9709 return kvm_rip_read(vcpu);
9710 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9711 kvm_rip_read(vcpu));
9712}
9713EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9714
82b32774
NA		 9715bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9716{
9717 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9718}
9719EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9720
94fe45da
JK		 9721unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9722{
9723 unsigned long rflags;
9724
9725 rflags = kvm_x86_ops->get_rflags(vcpu);
9726 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9727 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9728 return rflags;
9729}
9730EXPORT_SYMBOL_GPL(kvm_get_rflags);
9731
6addfc42 9732static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9733{
9734 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9735 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9736 rflags |= X86_EFLAGS_TF;
94fe45da 9737 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9738}
9739
9740void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9741{
9742 __kvm_set_rflags(vcpu, rflags);
3842d135 9743 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9744}
9745EXPORT_SYMBOL_GPL(kvm_set_rflags);
9746
56028d08
GN		 9747void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9748{
9749 int r;
9750
44dd3ffa 9751 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9752 work->wakeup_all)
56028d08
GN		 9753 return;
9754
9755 r = kvm_mmu_reload(vcpu);
9756 if (unlikely(r))
9757 return;
9758
44dd3ffa
VK		 9759 if (!vcpu->arch.mmu->direct_map &&
9760 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9761 return;
9762
44dd3ffa 9763 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9764}
9765
af585b92
GN		 9766static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9767{
9768 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9769}
9770
9771static inline u32 kvm_async_pf_next_probe(u32 key)
9772{
9773 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9774}
9775
9776static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9777{
9778 u32 key = kvm_async_pf_hash_fn(gfn);
9779
9780 while (vcpu->arch.apf.gfns[key] != ~0)
9781 key = kvm_async_pf_next_probe(key);
9782
9783 vcpu->arch.apf.gfns[key] = gfn;
9784}
9785
9786static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9787{
9788 int i;
9789 u32 key = kvm_async_pf_hash_fn(gfn);
9790
9791 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9792 (vcpu->arch.apf.gfns[key] != gfn &&
9793 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9794 key = kvm_async_pf_next_probe(key);
9795
9796 return key;
9797}
9798
9799bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9800{
9801 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9802}
9803
9804static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9805{
9806 u32 i, j, k;
9807
9808 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9809 while (true) {
9810 vcpu->arch.apf.gfns[i] = ~0;
9811 do {
9812 j = kvm_async_pf_next_probe(j);
9813 if (vcpu->arch.apf.gfns[j] == ~0)
9814 return;
9815 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9816 /*
9817 * k lies cyclically in ]i,j]
9818 * | i.k.j |
9819 * |....j i.k.| or |.k..j i...|
9820 */
9821 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9822 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9823 i = j;
9824 }
9825}
9826
7c90705b
GN		 9827static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9828{
4e335d9e
PB		 9829
9830 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9831 sizeof(val));
7c90705b
GN		 9832}
9833
9a6e7c39
WL		 9834static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9835{
9836
9837 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9838 sizeof(u32));
9839}
9840
1dfdb45e
PB		 9841static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
9842{
9843 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
9844 return false;
9845
9846 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9847 (vcpu->arch.apf.send_user_only &&
9848 kvm_x86_ops->get_cpl(vcpu) == 0))
9849 return false;
9850
9851 return true;
9852}
9853
9854bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
9855{
9856 if (unlikely(!lapic_in_kernel(vcpu) ||
9857 kvm_event_needs_reinjection(vcpu) ||
9858 vcpu->arch.exception.pending))
9859 return false;
9860
9861 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
9862 return false;
9863
9864 /*
9865 * If interrupts are off we cannot even use an artificial
9866 * halt state.
9867 */
9868 return kvm_x86_ops->interrupt_allowed(vcpu);
9869}
9870
af585b92
GN		 9871void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9872 struct kvm_async_pf *work)
9873{
6389ee94
AK		 9874 struct x86_exception fault;
9875
7c90705b 9876 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9877 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b 9878
1dfdb45e
PB		 9879 if (kvm_can_deliver_async_pf(vcpu) &&
9880 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9881 fault.vector = PF_VECTOR;
9882 fault.error_code_valid = true;
9883 fault.error_code = 0;
9884 fault.nested_page_fault = false;
9885 fault.address = work->arch.token;
adfe20fb 9886 fault.async_page_fault = true;
6389ee94 9887 kvm_inject_page_fault(vcpu, &fault);
1dfdb45e
PB		 9888 } else {
9889 /*
9890 * It is not possible to deliver a paravirtualized asynchronous
9891 * page fault, but putting the guest in an artificial halt state
9892 * can be beneficial nevertheless: if an interrupt arrives, we
9893 * can deliver it timely and perhaps the guest will schedule
9894 * another process. When the instruction that triggered a page
9895 * fault is retried, hopefully the page will be ready in the host.
9896 */
9897 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7c90705b 9898 }
af585b92
GN		 9899}
9900
9901void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9902 struct kvm_async_pf *work)
9903{
6389ee94 9904 struct x86_exception fault;
9a6e7c39 9905 u32 val;
6389ee94 9906
f2e10669 9907 if (work->wakeup_all)
7c90705b
GN		 9908 work->arch.token = ~0; /* broadcast wakeup */
9909 else
9910 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9911 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9912
9a6e7c39
WL		 9913 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9914 !apf_get_user(vcpu, &val)) {
9915 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9916 vcpu->arch.exception.pending &&
9917 vcpu->arch.exception.nr == PF_VECTOR &&
9918 !apf_put_user(vcpu, 0)) {
9919 vcpu->arch.exception.injected = false;
9920 vcpu->arch.exception.pending = false;
9921 vcpu->arch.exception.nr = 0;
9922 vcpu->arch.exception.has_error_code = false;
9923 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9924 vcpu->arch.exception.has_payload = false;
9925 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9926 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9927 fault.vector = PF_VECTOR;
9928 fault.error_code_valid = true;
9929 fault.error_code = 0;
9930 fault.nested_page_fault = false;
9931 fault.address = work->arch.token;
9932 fault.async_page_fault = true;
9933 kvm_inject_page_fault(vcpu, &fault);
9934 }
7c90705b 9935 }
e6d53e3b 9936 vcpu->arch.apf.halted = false;
a4fa1635 9937 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9938}
9939
9940bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9941{
9942 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9943 return true;
9944 else
9bc1f09f 9945 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9946}
9947
5544eb9b
PB		 9948void kvm_arch_start_assignment(struct kvm *kvm)
9949{
9950 atomic_inc(&kvm->arch.assigned_device_count);
9951}
9952EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9953
9954void kvm_arch_end_assignment(struct kvm *kvm)
9955{
9956 atomic_dec(&kvm->arch.assigned_device_count);
9957}
9958EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9959
9960bool kvm_arch_has_assigned_device(struct kvm *kvm)
9961{
9962 return atomic_read(&kvm->arch.assigned_device_count);
9963}
9964EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9965
e0f0bbc5
AW		 9966void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9967{
9968 atomic_inc(&kvm->arch.noncoherent_dma_count);
9969}
9970EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9971
9972void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9973{
9974 atomic_dec(&kvm->arch.noncoherent_dma_count);
9975}
9976EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9977
9978bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9979{
9980 return atomic_read(&kvm->arch.noncoherent_dma_count);
9981}
9982EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9983
14717e20
AW		 9984bool kvm_arch_has_irq_bypass(void)
9985{
9986 return kvm_x86_ops->update_pi_irte != NULL;
9987}
9988
87276880
FW		 9989int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9990 struct irq_bypass_producer *prod)
9991{
9992 struct kvm_kernel_irqfd *irqfd =
9993 container_of(cons, struct kvm_kernel_irqfd, consumer);
9994
14717e20 9995 irqfd->producer = prod;
87276880 9996
14717e20
AW		 9997 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9998 prod->irq, irqfd->gsi, 1);
87276880
FW		 9999}
10000
10001void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10002 struct irq_bypass_producer *prod)
10003{
10004 int ret;
10005 struct kvm_kernel_irqfd *irqfd =
10006 container_of(cons, struct kvm_kernel_irqfd, consumer);
10007
87276880
FW		 10008 WARN_ON(irqfd->producer != prod);
10009 irqfd->producer = NULL;
10010
10011 /*
10012 * When producer of consumer is unregistered, we change back to
10013 * remapped mode, so we can re-use the current implementation
bb3541f1 10014 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 10015 * int this case doesn't want to receive the interrupts.
10016 */
10017 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10018 if (ret)
10019 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10020 " fails: %d\n", irqfd->consumer.token, ret);
10021}
10022
10023int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10024 uint32_t guest_irq, bool set)
10025{
10026 if (!kvm_x86_ops->update_pi_irte)
10027 return -EINVAL;
10028
10029 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10030}
10031
52004014
FW		 10032bool kvm_vector_hashing_enabled(void)
10033{
10034 return vector_hashing;
10035}
10036EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10037
2d5ba19b
MT		 10038bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10039{
10040 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10041}
10042EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10043
10044
229456fc 10045EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 10046EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 10047EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10048EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10049EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10050EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 10051EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 10052EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 10053EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 10054EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 10055EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 10056EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 10057EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 10058EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 10059EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 10060EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 10061EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 10062EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10063EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)