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KVM: Replace smp_mb() with smp_load_acquire() in the kvm_flush_remote_tlbs()
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
52004014
FW		 126static bool __read_mostly vector_hashing = true;
127module_param(vector_hashing, bool, S_IRUGO);
128
893590c7 129static bool __read_mostly backwards_tsc_observed = false;
16a96021 130
18863bdd
AK		 131#define KVM_NR_SHARED_MSRS 16
132
133struct kvm_shared_msrs_global {
134 int nr;
2bf78fa7 135 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 136};
137
138struct kvm_shared_msrs {
139 struct user_return_notifier urn;
140 bool registered;
2bf78fa7
SY		 141 struct kvm_shared_msr_values {
142 u64 host;
143 u64 curr;
144 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 145};
146
147static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 148static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 149
417bc304 150struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 161 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 164 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 165 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 166 { "request_irq", VCPU_STAT(request_irq_exits) },
167 { "irq_exits", VCPU_STAT(irq_exits) },
168 { "host_state_reload", VCPU_STAT(host_state_reload) },
169 { "efer_reload", VCPU_STAT(efer_reload) },
170 { "fpu_reload", VCPU_STAT(fpu_reload) },
171 { "insn_emulation", VCPU_STAT(insn_emulation) },
172 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 173 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 174 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 175 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
176 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
177 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
178 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
179 { "mmu_flooded", VM_STAT(mmu_flooded) },
180 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 181 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 182 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 183 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 184 { "largepages", VM_STAT(lpages) },
417bc304
HB		 185 { NULL }
186};
187
2acf923e
DC		 188u64 __read_mostly host_xcr0;
189
b6785def 190static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 191
af585b92
GN		 192static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
193{
194 int i;
195 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
196 vcpu->arch.apf.gfns[i] = ~0;
197}
198
18863bdd
AK		 199static void kvm_on_user_return(struct user_return_notifier *urn)
200{
201 unsigned slot;
18863bdd
AK		 202 struct kvm_shared_msrs *locals
203 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 204 struct kvm_shared_msr_values *values;
18863bdd
AK		 205
206 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 207 values = &locals->values[slot];
208 if (values->host != values->curr) {
209 wrmsrl(shared_msrs_global.msrs[slot], values->host);
210 values->curr = values->host;
18863bdd
AK		 211 }
212 }
213 locals->registered = false;
214 user_return_notifier_unregister(urn);
215}
216
2bf78fa7 217static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 218{
18863bdd 219 u64 value;
013f6a5d
MT		 220 unsigned int cpu = smp_processor_id();
221 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 222
2bf78fa7
SY		 223 /* only read, and nobody should modify it at this time,
224 * so don't need lock */
225 if (slot >= shared_msrs_global.nr) {
226 printk(KERN_ERR "kvm: invalid MSR slot!");
227 return;
228 }
229 rdmsrl_safe(msr, &value);
230 smsr->values[slot].host = value;
231 smsr->values[slot].curr = value;
232}
233
234void kvm_define_shared_msr(unsigned slot, u32 msr)
235{
0123be42 236 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 237 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 238 if (slot >= shared_msrs_global.nr)
239 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 240}
241EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
242
243static void kvm_shared_msr_cpu_online(void)
244{
245 unsigned i;
18863bdd
AK		 246
247 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 248 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 249}
250
8b3c3104 251int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 252{
013f6a5d
MT		 253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 255 int err;
18863bdd 256
2bf78fa7 257 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 258 return 0;
2bf78fa7 259 smsr->values[slot].curr = value;
8b3c3104
AH		 260 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
261 if (err)
262 return 1;
263
18863bdd
AK		 264 if (!smsr->registered) {
265 smsr->urn.on_user_return = kvm_on_user_return;
266 user_return_notifier_register(&smsr->urn);
267 smsr->registered = true;
268 }
8b3c3104 269 return 0;
18863bdd
AK		 270}
271EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
272
13a34e06 273static void drop_user_return_notifiers(void)
3548bab5 274{
013f6a5d
MT		 275 unsigned int cpu = smp_processor_id();
276 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 277
278 if (smsr->registered)
279 kvm_on_user_return(&smsr->urn);
280}
281
6866b83e
CO		 282u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
283{
8a5a87d9 284 return vcpu->arch.apic_base;
6866b83e
CO		 285}
286EXPORT_SYMBOL_GPL(kvm_get_apic_base);
287
58cb628d
JK		 288int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
289{
290 u64 old_state = vcpu->arch.apic_base &
291 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
292 u64 new_state = msr_info->data &
293 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
294 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
295 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
296
297 if (!msr_info->host_initiated &&
298 ((msr_info->data & reserved_bits) != 0 ||
299 new_state == X2APIC_ENABLE ||
300 (new_state == MSR_IA32_APICBASE_ENABLE &&
301 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
302 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
303 old_state == 0)))
304 return 1;
305
306 kvm_lapic_set_base(vcpu, msr_info->data);
307 return 0;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_set_apic_base);
310
2605fc21 311asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 312{
313 /* Fault while not rebooting. We want the trace. */
314 BUG();
315}
316EXPORT_SYMBOL_GPL(kvm_spurious_fault);
317
3fd28fce
ED		 318#define EXCPT_BENIGN 0
319#define EXCPT_CONTRIBUTORY 1
320#define EXCPT_PF 2
321
322static int exception_class(int vector)
323{
324 switch (vector) {
325 case PF_VECTOR:
326 return EXCPT_PF;
327 case DE_VECTOR:
328 case TS_VECTOR:
329 case NP_VECTOR:
330 case SS_VECTOR:
331 case GP_VECTOR:
332 return EXCPT_CONTRIBUTORY;
333 default:
334 break;
335 }
336 return EXCPT_BENIGN;
337}
338
d6e8c854
NA		 339#define EXCPT_FAULT 0
340#define EXCPT_TRAP 1
341#define EXCPT_ABORT 2
342#define EXCPT_INTERRUPT 3
343
344static int exception_type(int vector)
345{
346 unsigned int mask;
347
348 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
349 return EXCPT_INTERRUPT;
350
351 mask = 1 << vector;
352
353 /* #DB is trap, as instruction watchpoints are handled elsewhere */
354 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
355 return EXCPT_TRAP;
356
357 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
358 return EXCPT_ABORT;
359
360 /* Reserved exceptions will result in fault */
361 return EXCPT_FAULT;
362}
363
3fd28fce 364static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 365 unsigned nr, bool has_error, u32 error_code,
366 bool reinject)
3fd28fce
ED		 367{
368 u32 prev_nr;
369 int class1, class2;
370
3842d135
AK		 371 kvm_make_request(KVM_REQ_EVENT, vcpu);
372
3fd28fce
ED		 373 if (!vcpu->arch.exception.pending) {
374 queue:
3ffb2468
NA		 375 if (has_error && !is_protmode(vcpu))
376 has_error = false;
3fd28fce
ED		 377 vcpu->arch.exception.pending = true;
378 vcpu->arch.exception.has_error_code = has_error;
379 vcpu->arch.exception.nr = nr;
380 vcpu->arch.exception.error_code = error_code;
3f0fd292 381 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 382 return;
383 }
384
385 /* to check exception */
386 prev_nr = vcpu->arch.exception.nr;
387 if (prev_nr == DF_VECTOR) {
388 /* triple fault -> shutdown */
a8eeb04a 389 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 390 return;
391 }
392 class1 = exception_class(prev_nr);
393 class2 = exception_class(nr);
394 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
395 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
396 /* generate double fault per SDM Table 5-5 */
397 vcpu->arch.exception.pending = true;
398 vcpu->arch.exception.has_error_code = true;
399 vcpu->arch.exception.nr = DF_VECTOR;
400 vcpu->arch.exception.error_code = 0;
401 } else
402 /* replace previous exception with a new one in a hope
403 that instruction re-execution will regenerate lost
404 exception */
405 goto queue;
406}
407
298101da
AK		 408void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
409{
ce7ddec4 410 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 411}
412EXPORT_SYMBOL_GPL(kvm_queue_exception);
413
ce7ddec4
JR		 414void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
415{
416 kvm_multiple_exception(vcpu, nr, false, 0, true);
417}
418EXPORT_SYMBOL_GPL(kvm_requeue_exception);
419
db8fcefa 420void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 421{
db8fcefa
AP		 422 if (err)
423 kvm_inject_gp(vcpu, 0);
424 else
425 kvm_x86_ops->skip_emulated_instruction(vcpu);
426}
427EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 428
6389ee94 429void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 430{
431 ++vcpu->stat.pf_guest;
6389ee94
AK		 432 vcpu->arch.cr2 = fault->address;
433 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 434}
27d6c865 435EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 436
ef54bcfe 437static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 438{
6389ee94
AK		 439 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
440 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 441 else
6389ee94 442 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 443
444 return fault->nested_page_fault;
d4f8cf66
JR		 445}
446
3419ffc8
SY		 447void kvm_inject_nmi(struct kvm_vcpu *vcpu)
448{
7460fb4a
AK		 449 atomic_inc(&vcpu->arch.nmi_queued);
450 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 451}
452EXPORT_SYMBOL_GPL(kvm_inject_nmi);
453
298101da
AK		 454void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
455{
ce7ddec4 456 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 457}
458EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
459
ce7ddec4
JR		 460void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
461{
462 kvm_multiple_exception(vcpu, nr, true, error_code, true);
463}
464EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
465
0a79b009
AK		 466/*
467 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
468 * a #GP and return false.
469 */
470bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 471{
0a79b009
AK		 472 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
473 return true;
474 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
475 return false;
298101da 476}
0a79b009 477EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 478
16f8a6f9
NA		 479bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
480{
481 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
482 return true;
483
484 kvm_queue_exception(vcpu, UD_VECTOR);
485 return false;
486}
487EXPORT_SYMBOL_GPL(kvm_require_dr);
488
ec92fe44
JR		 489/*
490 * This function will be used to read from the physical memory of the currently
54bf36aa 491 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 492 * can read from guest physical or from the guest's guest physical memory.
493 */
494int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
495 gfn_t ngfn, void *data, int offset, int len,
496 u32 access)
497{
54987b7a 498 struct x86_exception exception;
ec92fe44
JR		 499 gfn_t real_gfn;
500 gpa_t ngpa;
501
502 ngpa = gfn_to_gpa(ngfn);
54987b7a 503 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 504 if (real_gfn == UNMAPPED_GVA)
505 return -EFAULT;
506
507 real_gfn = gpa_to_gfn(real_gfn);
508
54bf36aa 509 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 510}
511EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
512
69b0049a 513static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 514 void *data, int offset, int len, u32 access)
515{
516 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
517 data, offset, len, access);
518}
519
a03490ed
CO		 520/*
521 * Load the pae pdptrs. Return true is they are all valid.
522 */
ff03a073 523int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 524{
525 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
526 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
527 int i;
528 int ret;
ff03a073 529 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 530
ff03a073
JR		 531 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
532 offset * sizeof(u64), sizeof(pdpte),
533 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 534 if (ret < 0) {
535 ret = 0;
536 goto out;
537 }
538 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 539 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 540 (pdpte[i] &
541 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 542 ret = 0;
543 goto out;
544 }
545 }
546 ret = 1;
547
ff03a073 548 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 549 __set_bit(VCPU_EXREG_PDPTR,
550 (unsigned long *)&vcpu->arch.regs_avail);
551 __set_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 553out:
a03490ed
CO		 554
555 return ret;
556}
cc4b6871 557EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 558
d835dfec
AK		 559static bool pdptrs_changed(struct kvm_vcpu *vcpu)
560{
ff03a073 561 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 562 bool changed = true;
3d06b8bf
JR		 563 int offset;
564 gfn_t gfn;
d835dfec
AK		 565 int r;
566
567 if (is_long_mode(vcpu) || !is_pae(vcpu))
568 return false;
569
6de4f3ad
AK		 570 if (!test_bit(VCPU_EXREG_PDPTR,
571 (unsigned long *)&vcpu->arch.regs_avail))
572 return true;
573
9f8fe504
AK		 574 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
575 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 576 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
577 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 578 if (r < 0)
579 goto out;
ff03a073 580 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 581out:
d835dfec
AK		 582
583 return changed;
584}
585
49a9b07e 586int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 587{
aad82703 588 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 589 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 590
f9a48e6a
AK		 591 cr0 |= X86_CR0_ET;
592
ab344828 593#ifdef CONFIG_X86_64
0f12244f
GN		 594 if (cr0 & 0xffffffff00000000UL)
595 return 1;
ab344828
GN		 596#endif
597
598 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
601 return 1;
a03490ed 602
0f12244f
GN		 603 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
604 return 1;
a03490ed
CO		 605
606 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
607#ifdef CONFIG_X86_64
f6801dff 608 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 609 int cs_db, cs_l;
610
0f12244f
GN		 611 if (!is_pae(vcpu))
612 return 1;
a03490ed 613 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 614 if (cs_l)
615 return 1;
a03490ed
CO		 616 } else
617#endif
ff03a073 618 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 619 kvm_read_cr3(vcpu)))
0f12244f 620 return 1;
a03490ed
CO		 621 }
622
ad756a16
MJ		 623 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
624 return 1;
625
a03490ed 626 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 627
d170c419 628 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 629 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 630 kvm_async_pf_hash_reset(vcpu);
631 }
e5f3f027 632
aad82703
SY		 633 if ((cr0 ^ old_cr0) & update_bits)
634 kvm_mmu_reset_context(vcpu);
b18d5431 635
879ae188
LE		 636 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
637 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
638 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 639 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
640
0f12244f
GN		 641 return 0;
642}
2d3ad1f4 643EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 644
2d3ad1f4 645void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 646{
49a9b07e 647 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 648}
2d3ad1f4 649EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 650
42bdf991
MT		 651static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
652{
653 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
654 !vcpu->guest_xcr0_loaded) {
655 /* kvm_set_xcr() also depends on this */
656 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
657 vcpu->guest_xcr0_loaded = 1;
658 }
659}
660
661static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
662{
663 if (vcpu->guest_xcr0_loaded) {
664 if (vcpu->arch.xcr0 != host_xcr0)
665 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
666 vcpu->guest_xcr0_loaded = 0;
667 }
668}
669
69b0049a 670static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 671{
56c103ec
LJ		 672 u64 xcr0 = xcr;
673 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 674 u64 valid_bits;
2acf923e
DC		 675
676 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
677 if (index != XCR_XFEATURE_ENABLED_MASK)
678 return 1;
d91cab78 679 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 680 return 1;
d91cab78 681 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 682 return 1;
46c34cb0
PB		 683
684 /*
685 * Do not allow the guest to set bits that we do not support
686 * saving. However, xcr0 bit 0 is always set, even if the
687 * emulated CPU does not support XSAVE (see fx_init).
688 */
d91cab78 689 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 690 if (xcr0 & ~valid_bits)
2acf923e 691 return 1;
46c34cb0 692
d91cab78
DH		 693 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
694 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 695 return 1;
696
d91cab78
DH		 697 if (xcr0 & XFEATURE_MASK_AVX512) {
698 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 699 return 1;
d91cab78 700 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 701 return 1;
702 }
42bdf991 703 kvm_put_guest_xcr0(vcpu);
2acf923e 704 vcpu->arch.xcr0 = xcr0;
56c103ec 705
d91cab78 706 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 707 kvm_update_cpuid(vcpu);
2acf923e
DC		 708 return 0;
709}
710
711int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
712{
764bcbc5
Z		 713 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
714 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 715 kvm_inject_gp(vcpu, 0);
716 return 1;
717 }
718 return 0;
719}
720EXPORT_SYMBOL_GPL(kvm_set_xcr);
721
a83b29c6 722int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 723{
fc78f519 724 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 725 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 726 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 727
0f12244f
GN		 728 if (cr4 & CR4_RESERVED_BITS)
729 return 1;
a03490ed 730
2acf923e
DC		 731 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
732 return 1;
733
c68b734f
YW		 734 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
735 return 1;
736
97ec8c06
FW		 737 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
738 return 1;
739
afcbf13f 740 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 741 return 1;
742
b9baba86
HH		 743 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
744 return 1;
745
a03490ed 746 if (is_long_mode(vcpu)) {
0f12244f
GN		 747 if (!(cr4 & X86_CR4_PAE))
748 return 1;
a2edf57f
AK		 749 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
750 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 751 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
752 kvm_read_cr3(vcpu)))
0f12244f
GN		 753 return 1;
754
ad756a16
MJ		 755 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
756 if (!guest_cpuid_has_pcid(vcpu))
757 return 1;
758
759 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
760 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
761 return 1;
762 }
763
5e1746d6 764 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 765 return 1;
a03490ed 766
ad756a16
MJ		 767 if (((cr4 ^ old_cr4) & pdptr_bits) ||
768 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 769 kvm_mmu_reset_context(vcpu);
0f12244f 770
b9baba86 771 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 772 kvm_update_cpuid(vcpu);
2acf923e 773
0f12244f
GN		 774 return 0;
775}
2d3ad1f4 776EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 777
2390218b 778int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 779{
ac146235 780#ifdef CONFIG_X86_64
9d88fca7 781 cr3 &= ~CR3_PCID_INVD;
ac146235 782#endif
9d88fca7 783
9f8fe504 784 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 785 kvm_mmu_sync_roots(vcpu);
77c3913b 786 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 787 return 0;
d835dfec
AK		 788 }
789
a03490ed 790 if (is_long_mode(vcpu)) {
d9f89b88
JK		 791 if (cr3 & CR3_L_MODE_RESERVED_BITS)
792 return 1;
793 } else if (is_pae(vcpu) && is_paging(vcpu) &&
794 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 795 return 1;
a03490ed 796
0f12244f 797 vcpu->arch.cr3 = cr3;
aff48baa 798 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 799 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 800 return 0;
801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 803
eea1cff9 804int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 805{
0f12244f
GN		 806 if (cr8 & CR8_RESERVED_BITS)
807 return 1;
35754c98 808 if (lapic_in_kernel(vcpu))
a03490ed
CO		 809 kvm_lapic_set_tpr(vcpu, cr8);
810 else
ad312c7c 811 vcpu->arch.cr8 = cr8;
0f12244f
GN		 812 return 0;
813}
2d3ad1f4 814EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 815
2d3ad1f4 816unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 817{
35754c98 818 if (lapic_in_kernel(vcpu))
a03490ed
CO		 819 return kvm_lapic_get_cr8(vcpu);
820 else
ad312c7c 821 return vcpu->arch.cr8;
a03490ed 822}
2d3ad1f4 823EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 824
ae561ede
NA		 825static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
826{
827 int i;
828
829 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
830 for (i = 0; i < KVM_NR_DB_REGS; i++)
831 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
833 }
834}
835
73aaf249
JK		 836static void kvm_update_dr6(struct kvm_vcpu *vcpu)
837{
838 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
839 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
840}
841
c8639010
JK		 842static void kvm_update_dr7(struct kvm_vcpu *vcpu)
843{
844 unsigned long dr7;
845
846 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
847 dr7 = vcpu->arch.guest_debug_dr7;
848 else
849 dr7 = vcpu->arch.dr7;
850 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 851 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
852 if (dr7 & DR7_BP_EN_MASK)
853 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 854}
855
6f43ed01
NA		 856static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
857{
858 u64 fixed = DR6_FIXED_1;
859
860 if (!guest_cpuid_has_rtm(vcpu))
861 fixed |= DR6_RTM;
862 return fixed;
863}
864
338dbc97 865static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 866{
867 switch (dr) {
868 case 0 ... 3:
869 vcpu->arch.db[dr] = val;
870 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
871 vcpu->arch.eff_db[dr] = val;
872 break;
873 case 4:
020df079
GN		 874 /* fall through */
875 case 6:
338dbc97
GN		 876 if (val & 0xffffffff00000000ULL)
877 return -1; /* #GP */
6f43ed01 878 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 879 kvm_update_dr6(vcpu);
020df079
GN		 880 break;
881 case 5:
020df079
GN		 882 /* fall through */
883 default: /* 7 */
338dbc97
GN		 884 if (val & 0xffffffff00000000ULL)
885 return -1; /* #GP */
020df079 886 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 887 kvm_update_dr7(vcpu);
020df079
GN		 888 break;
889 }
890
891 return 0;
892}
338dbc97
GN		 893
894int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
895{
16f8a6f9 896 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 897 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 898 return 1;
899 }
900 return 0;
338dbc97 901}
020df079
GN		 902EXPORT_SYMBOL_GPL(kvm_set_dr);
903
16f8a6f9 904int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 905{
906 switch (dr) {
907 case 0 ... 3:
908 *val = vcpu->arch.db[dr];
909 break;
910 case 4:
020df079
GN		 911 /* fall through */
912 case 6:
73aaf249
JK		 913 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
914 *val = vcpu->arch.dr6;
915 else
916 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 917 break;
918 case 5:
020df079
GN		 919 /* fall through */
920 default: /* 7 */
921 *val = vcpu->arch.dr7;
922 break;
923 }
338dbc97
GN		 924 return 0;
925}
020df079
GN		 926EXPORT_SYMBOL_GPL(kvm_get_dr);
927
022cd0e8
AK		 928bool kvm_rdpmc(struct kvm_vcpu *vcpu)
929{
930 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
931 u64 data;
932 int err;
933
c6702c9d 934 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 935 if (err)
936 return err;
937 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
938 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
939 return err;
940}
941EXPORT_SYMBOL_GPL(kvm_rdpmc);
942
043405e1
CO		 943/*
944 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
945 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
946 *
947 * This list is modified at module load time to reflect the
e3267cbb 948 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 949 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
950 * may depend on host virtualization features rather than host cpu features.
043405e1 951 */
e3267cbb 952
043405e1
CO		 953static u32 msrs_to_save[] = {
954 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 955 MSR_STAR,
043405e1
CO		 956#ifdef CONFIG_X86_64
957 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
958#endif
b3897a49 959 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 960 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 961};
962
963static unsigned num_msrs_to_save;
964
62ef68bb
PB		 965static u32 emulated_msrs[] = {
966 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
967 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
968 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
969 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 970 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
971 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 972 HV_X64_MSR_RESET,
11c4b1ca 973 HV_X64_MSR_VP_INDEX,
9eec50b8 974 HV_X64_MSR_VP_RUNTIME,
5c919412 975 HV_X64_MSR_SCONTROL,
1f4b34f8 976 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 977 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
978 MSR_KVM_PV_EOI_EN,
979
ba904635 980 MSR_IA32_TSC_ADJUST,
a3e06bbe 981 MSR_IA32_TSCDEADLINE,
043405e1 982 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 983 MSR_IA32_MCG_STATUS,
984 MSR_IA32_MCG_CTL,
64d60670 985 MSR_IA32_SMBASE,
043405e1
CO		 986};
987
62ef68bb
PB		 988static unsigned num_emulated_msrs;
989
384bb783 990bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 991{
b69e8cae 992 if (efer & efer_reserved_bits)
384bb783 993 return false;
15c4a640 994
1b2fd70c
AG		 995 if (efer & EFER_FFXSR) {
996 struct kvm_cpuid_entry2 *feat;
997
998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 999 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1000 return false;
1b2fd70c
AG		 1001 }
1002
d8017474
AG		 1003 if (efer & EFER_SVME) {
1004 struct kvm_cpuid_entry2 *feat;
1005
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1007 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1008 return false;
d8017474
AG		 1009 }
1010
384bb783
JK		 1011 return true;
1012}
1013EXPORT_SYMBOL_GPL(kvm_valid_efer);
1014
1015static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1016{
1017 u64 old_efer = vcpu->arch.efer;
1018
1019 if (!kvm_valid_efer(vcpu, efer))
1020 return 1;
1021
1022 if (is_paging(vcpu)
1023 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1024 return 1;
1025
15c4a640 1026 efer &= ~EFER_LMA;
f6801dff 1027 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1028
a3d204e2
SY		 1029 kvm_x86_ops->set_efer(vcpu, efer);
1030
aad82703
SY		 1031 /* Update reserved bits */
1032 if ((efer ^ old_efer) & EFER_NX)
1033 kvm_mmu_reset_context(vcpu);
1034
b69e8cae 1035 return 0;
15c4a640
CO		 1036}
1037
f2b4b7dd
JR		 1038void kvm_enable_efer_bits(u64 mask)
1039{
1040 efer_reserved_bits &= ~mask;
1041}
1042EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1043
15c4a640
CO		 1044/*
1045 * Writes msr value into into the appropriate "register".
1046 * Returns 0 on success, non-0 otherwise.
1047 * Assumes vcpu_load() was already called.
1048 */
8fe8ab46 1049int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1050{
854e8bb1
NA		 1051 switch (msr->index) {
1052 case MSR_FS_BASE:
1053 case MSR_GS_BASE:
1054 case MSR_KERNEL_GS_BASE:
1055 case MSR_CSTAR:
1056 case MSR_LSTAR:
1057 if (is_noncanonical_address(msr->data))
1058 return 1;
1059 break;
1060 case MSR_IA32_SYSENTER_EIP:
1061 case MSR_IA32_SYSENTER_ESP:
1062 /*
1063 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1064 * non-canonical address is written on Intel but not on
1065 * AMD (which ignores the top 32-bits, because it does
1066 * not implement 64-bit SYSENTER).
1067 *
1068 * 64-bit code should hence be able to write a non-canonical
1069 * value on AMD. Making the address canonical ensures that
1070 * vmentry does not fail on Intel after writing a non-canonical
1071 * value, and that something deterministic happens if the guest
1072 * invokes 64-bit SYSENTER.
1073 */
1074 msr->data = get_canonical(msr->data);
1075 }
8fe8ab46 1076 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1077}
854e8bb1 1078EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1079
313a3dc7
CO		 1080/*
1081 * Adapt set_msr() to msr_io()'s calling convention
1082 */
609e36d3
PB		 1083static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1084{
1085 struct msr_data msr;
1086 int r;
1087
1088 msr.index = index;
1089 msr.host_initiated = true;
1090 r = kvm_get_msr(vcpu, &msr);
1091 if (r)
1092 return r;
1093
1094 *data = msr.data;
1095 return 0;
1096}
1097
313a3dc7
CO		 1098static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1099{
8fe8ab46
WA		 1100 struct msr_data msr;
1101
1102 msr.data = *data;
1103 msr.index = index;
1104 msr.host_initiated = true;
1105 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1106}
1107
16e8d74d
MT		 1108#ifdef CONFIG_X86_64
1109struct pvclock_gtod_data {
1110 seqcount_t seq;
1111
1112 struct { /* extract of a clocksource struct */
1113 int vclock_mode;
1114 cycle_t cycle_last;
1115 cycle_t mask;
1116 u32 mult;
1117 u32 shift;
1118 } clock;
1119
cbcf2dd3
TG		 1120 u64 boot_ns;
1121 u64 nsec_base;
16e8d74d
MT		 1122};
1123
1124static struct pvclock_gtod_data pvclock_gtod_data;
1125
1126static void update_pvclock_gtod(struct timekeeper *tk)
1127{
1128 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1129 u64 boot_ns;
1130
876e7881 1131 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1132
1133 write_seqcount_begin(&vdata->seq);
1134
1135 /* copy pvclock gtod data */
876e7881
PZ		 1136 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1137 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1138 vdata->clock.mask = tk->tkr_mono.mask;
1139 vdata->clock.mult = tk->tkr_mono.mult;
1140 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1141
cbcf2dd3 1142 vdata->boot_ns = boot_ns;
876e7881 1143 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1144
1145 write_seqcount_end(&vdata->seq);
1146}
1147#endif
1148
bab5bb39
NK		 1149void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1150{
1151 /*
1152 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1153 * vcpu_enter_guest. This function is only called from
1154 * the physical CPU that is running vcpu.
1155 */
1156 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1157}
16e8d74d 1158
18068523
GOC		 1159static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1160{
9ed3c444
AK		 1161 int version;
1162 int r;
50d0a0f9 1163 struct pvclock_wall_clock wc;
923de3cf 1164 struct timespec boot;
18068523
GOC		 1165
1166 if (!wall_clock)
1167 return;
1168
9ed3c444
AK		 1169 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1170 if (r)
1171 return;
1172
1173 if (version & 1)
1174 ++version; /* first time write, random junk */
1175
1176 ++version;
18068523 1177
1dab1345
NK		 1178 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1179 return;
18068523 1180
50d0a0f9
GH		 1181 /*
1182 * The guest calculates current wall clock time by adding
34c238a1 1183 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1184 * wall clock specified here. guest system time equals host
1185 * system time for us, thus we must fill in host boot time here.
1186 */
923de3cf 1187 getboottime(&boot);
50d0a0f9 1188
4b648665
BR		 1189 if (kvm->arch.kvmclock_offset) {
1190 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1191 boot = timespec_sub(boot, ts);
1192 }
50d0a0f9
GH		 1193 wc.sec = boot.tv_sec;
1194 wc.nsec = boot.tv_nsec;
1195 wc.version = version;
18068523
GOC		 1196
1197 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1198
1199 version++;
1200 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1201}
1202
50d0a0f9
GH		 1203static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1204{
b51012de
PB		 1205 do_shl32_div32(dividend, divisor);
1206 return dividend;
50d0a0f9
GH		 1207}
1208
3ae13faa 1209static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1210 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1211{
5f4e3f88 1212 uint64_t scaled64;
50d0a0f9
GH		 1213 int32_t shift = 0;
1214 uint64_t tps64;
1215 uint32_t tps32;
1216
3ae13faa
PB		 1217 tps64 = base_hz;
1218 scaled64 = scaled_hz;
50933623 1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1220 tps64 >>= 1;
1221 shift--;
1222 }
1223
1224 tps32 = (uint32_t)tps64;
50933623
JK		 1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1227 scaled64 >>= 1;
1228 else
1229 tps32 <<= 1;
50d0a0f9
GH		 1230 shift++;
1231 }
1232
5f4e3f88
ZA		 1233 *pshift = shift;
1234 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1235
3ae13faa
PB		 1236 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1237 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1238}
1239
d828199e 1240#ifdef CONFIG_X86_64
16e8d74d 1241static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1242#endif
16e8d74d 1243
c8076604 1244static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1245static unsigned long max_tsc_khz;
c8076604 1246
cc578287 1247static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1248{
cc578287
ZA		 1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1250 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1251}
1252
cc578287 1253static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1254{
cc578287
ZA		 1255 u64 v = (u64)khz * (1000000 + ppm);
1256 do_div(v, 1000000);
1257 return v;
1e993611
JR		 1258}
1259
381d585c
HZ		 1260static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1261{
1262 u64 ratio;
1263
1264 /* Guest TSC same frequency as host TSC? */
1265 if (!scale) {
1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1267 return 0;
1268 }
1269
1270 /* TSC scaling supported? */
1271 if (!kvm_has_tsc_control) {
1272 if (user_tsc_khz > tsc_khz) {
1273 vcpu->arch.tsc_catchup = 1;
1274 vcpu->arch.tsc_always_catchup = 1;
1275 return 0;
1276 } else {
1277 WARN(1, "user requested TSC rate below hardware speed\n");
1278 return -1;
1279 }
1280 }
1281
1282 /* TSC scaling required - calculate ratio */
1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1284 user_tsc_khz, tsc_khz);
1285
1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1288 user_tsc_khz);
1289 return -1;
1290 }
1291
1292 vcpu->arch.tsc_scaling_ratio = ratio;
1293 return 0;
1294}
1295
4941b8cb 1296static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1297{
cc578287
ZA		 1298 u32 thresh_lo, thresh_hi;
1299 int use_scaling = 0;
217fc9cf 1300
03ba32ca 1301 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1302 if (user_tsc_khz == 0) {
ad721883
HZ		 1303 /* set tsc_scaling_ratio to a safe value */
1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1305 return -1;
ad721883 1306 }
03ba32ca 1307
c285545f 1308 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1309 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1310 &vcpu->arch.virtual_tsc_shift,
1311 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1312 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1313
1314 /*
1315 * Compute the variation in TSC rate which is acceptable
1316 * within the range of tolerance and decide if the
1317 * rate being applied is within that bounds of the hardware
1318 * rate. If so, no scaling or compensation need be done.
1319 */
1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1322 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1324 use_scaling = 1;
1325 }
4941b8cb 1326 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1327}
1328
1329static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1330{
e26101b1 1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1332 vcpu->arch.virtual_tsc_mult,
1333 vcpu->arch.virtual_tsc_shift);
e26101b1 1334 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1335 return tsc;
1336}
1337
69b0049a 1338static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1339{
1340#ifdef CONFIG_X86_64
1341 bool vcpus_matched;
b48aa97e
MT		 1342 struct kvm_arch *ka = &vcpu->kvm->arch;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1346 atomic_read(&vcpu->kvm->online_vcpus));
1347
7f187922
MT		 1348 /*
1349 * Once the masterclock is enabled, always perform request in
1350 * order to update it.
1351 *
1352 * In order to enable masterclock, the host clocksource must be TSC
1353 * and the vcpus need to have matched TSCs. When that happens,
1354 * perform request to enable masterclock.
1355 */
1356 if (ka->use_master_clock ||
1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1359
1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1361 atomic_read(&vcpu->kvm->online_vcpus),
1362 ka->use_master_clock, gtod->clock.vclock_mode);
1363#endif
1364}
1365
ba904635
WA		 1366static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1367{
1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1370}
1371
35181e86
HZ		 1372/*
1373 * Multiply tsc by a fixed point number represented by ratio.
1374 *
1375 * The most significant 64-N bits (mult) of ratio represent the
1376 * integral part of the fixed point number; the remaining N bits
1377 * (frac) represent the fractional part, ie. ratio represents a fixed
1378 * point number (mult + frac * 2^(-N)).
1379 *
1380 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1381 */
1382static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1383{
1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1385}
1386
1387u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1388{
1389 u64 _tsc = tsc;
1390 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1391
1392 if (ratio != kvm_default_tsc_scaling_ratio)
1393 _tsc = __scale_tsc(ratio, tsc);
1394
1395 return _tsc;
1396}
1397EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1398
07c1419a
HZ		 1399static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1400{
1401 u64 tsc;
1402
1403 tsc = kvm_scale_tsc(vcpu, rdtsc());
1404
1405 return target_tsc - tsc;
1406}
1407
4ba76538
HZ		 1408u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1409{
1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1411}
1412EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1413
8fe8ab46 1414void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1415{
1416 struct kvm *kvm = vcpu->kvm;
f38e098f 1417 u64 offset, ns, elapsed;
99e3e30a 1418 unsigned long flags;
02626b6a 1419 s64 usdiff;
b48aa97e 1420 bool matched;
0d3da0d2 1421 bool already_matched;
8fe8ab46 1422 u64 data = msr->data;
99e3e30a 1423
038f8c11 1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1425 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1426 ns = get_kernel_ns();
f38e098f 1427 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1428
03ba32ca 1429 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1430 int faulted = 0;
1431
03ba32ca
MT		 1432 /* n.b - signed multiplication and division required */
1433 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1434#ifdef CONFIG_X86_64
03ba32ca 1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1436#else
03ba32ca 1437 /* do_div() only does unsigned */
8915aa27
MT		 1438 asm("1: idivl %[divisor]\n"
1439 "2: xor %%edx, %%edx\n"
1440 " movl $0, %[faulted]\n"
1441 "3:\n"
1442 ".section .fixup,\"ax\"\n"
1443 "4: movl $1, %[faulted]\n"
1444 " jmp 3b\n"
1445 ".previous\n"
1446
1447 _ASM_EXTABLE(1b, 4b)
1448
1449 : "=A"(usdiff), [faulted] "=r" (faulted)
1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1451
5d3cb0f6 1452#endif
03ba32ca
MT		 1453 do_div(elapsed, 1000);
1454 usdiff -= elapsed;
1455 if (usdiff < 0)
1456 usdiff = -usdiff;
8915aa27
MT		 1457
1458 /* idivl overflow => difference is larger than USEC_PER_SEC */
1459 if (faulted)
1460 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1461 } else
1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1463
1464 /*
5d3cb0f6
ZA		 1465 * Special case: TSC write with a small delta (1 second) of virtual
1466 * cycle time against real time is interpreted as an attempt to
1467 * synchronize the CPU.
1468 *
1469 * For a reliable TSC, we can match TSC offsets, and for an unstable
1470 * TSC, we add elapsed time in this computation. We could let the
1471 * compensation code attempt to catch up if we fall behind, but
1472 * it's better to try to match offsets from the beginning.
1473 */
02626b6a 1474 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1476 if (!check_tsc_unstable()) {
e26101b1 1477 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1478 pr_debug("kvm: matched tsc offset for %llu\n", data);
1479 } else {
857e4099 1480 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1481 data += delta;
07c1419a 1482 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1484 }
b48aa97e 1485 matched = true;
0d3da0d2 1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1487 } else {
1488 /*
1489 * We split periods of matched TSC writes into generations.
1490 * For each generation, we track the original measured
1491 * nanosecond time, offset, and write, so if TSCs are in
1492 * sync, we can match exact offset, and if not, we can match
4a969980 1493 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1494 *
1495 * These values are tracked in kvm->arch.cur_xxx variables.
1496 */
1497 kvm->arch.cur_tsc_generation++;
1498 kvm->arch.cur_tsc_nsec = ns;
1499 kvm->arch.cur_tsc_write = data;
1500 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1501 matched = false;
0d3da0d2 1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1503 kvm->arch.cur_tsc_generation, data);
f38e098f 1504 }
e26101b1
ZA		 1505
1506 /*
1507 * We also track th most recent recorded KHZ, write and time to
1508 * allow the matching interval to be extended at each write.
1509 */
f38e098f
ZA		 1510 kvm->arch.last_tsc_nsec = ns;
1511 kvm->arch.last_tsc_write = data;
5d3cb0f6 1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1513
b183aa58 1514 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1515
1516 /* Keep track of which generation this VCPU has synchronized to */
1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1520
ba904635
WA		 1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1522 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1523 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1525
1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1527 if (!matched) {
b48aa97e 1528 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1529 } else if (!already_matched) {
1530 kvm->arch.nr_vcpus_matched_tsc++;
1531 }
b48aa97e
MT		 1532
1533 kvm_track_tsc_matching(vcpu);
1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1535}
e26101b1 1536
99e3e30a
ZA		 1537EXPORT_SYMBOL_GPL(kvm_write_tsc);
1538
58ea6767
HZ		 1539static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1540 s64 adjustment)
1541{
1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1543}
1544
1545static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1546{
1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1548 WARN_ON(adjustment < 0);
1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1551}
1552
d828199e
MT		 1553#ifdef CONFIG_X86_64
1554
1555static cycle_t read_tsc(void)
1556{
03b9730b
AL		 1557 cycle_t ret = (cycle_t)rdtsc_ordered();
1558 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1559
1560 if (likely(ret >= last))
1561 return ret;
1562
1563 /*
1564 * GCC likes to generate cmov here, but this branch is extremely
1565 * predictable (it's just a funciton of time and the likely is
1566 * very likely) and there's a data dependence, so force GCC
1567 * to generate a branch instead. I don't barrier() because
1568 * we don't actually need a barrier, and if this function
1569 * ever gets inlined it will generate worse code.
1570 */
1571 asm volatile ("");
1572 return last;
1573}
1574
1575static inline u64 vgettsc(cycle_t *cycle_now)
1576{
1577 long v;
1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1579
1580 *cycle_now = read_tsc();
1581
1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1583 return v * gtod->clock.mult;
1584}
1585
cbcf2dd3 1586static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1587{
cbcf2dd3 1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1589 unsigned long seq;
d828199e 1590 int mode;
cbcf2dd3 1591 u64 ns;
d828199e 1592
d828199e
MT		 1593 do {
1594 seq = read_seqcount_begin(&gtod->seq);
1595 mode = gtod->clock.vclock_mode;
cbcf2dd3 1596 ns = gtod->nsec_base;
d828199e
MT		 1597 ns += vgettsc(cycle_now);
1598 ns >>= gtod->clock.shift;
cbcf2dd3 1599 ns += gtod->boot_ns;
d828199e 1600 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1601 *t = ns;
d828199e
MT		 1602
1603 return mode;
1604}
1605
1606/* returns true if host is using tsc clocksource */
1607static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1608{
d828199e
MT		 1609 /* checked again under seqlock below */
1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1611 return false;
1612
cbcf2dd3 1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1614}
1615#endif
1616
1617/*
1618 *
b48aa97e
MT		 1619 * Assuming a stable TSC across physical CPUS, and a stable TSC
1620 * across virtual CPUs, the following condition is possible.
1621 * Each numbered line represents an event visible to both
d828199e
MT		 1622 * CPUs at the next numbered event.
1623 *
1624 * "timespecX" represents host monotonic time. "tscX" represents
1625 * RDTSC value.
1626 *
1627 * VCPU0 on CPU0 | VCPU1 on CPU1
1628 *
1629 * 1. read timespec0,tsc0
1630 * 2. | timespec1 = timespec0 + N
1631 * | tsc1 = tsc0 + M
1632 * 3. transition to guest | transition to guest
1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1636 *
1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1638 *
1639 * - ret0 < ret1
1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1641 * ...
1642 * - 0 < N - M => M < N
1643 *
1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1645 * always the case (the difference between two distinct xtime instances
1646 * might be smaller then the difference between corresponding TSC reads,
1647 * when updating guest vcpus pvclock areas).
1648 *
1649 * To avoid that problem, do not allow visibility of distinct
1650 * system_timestamp/tsc_timestamp values simultaneously: use a master
1651 * copy of host monotonic time values. Update that master copy
1652 * in lockstep.
1653 *
b48aa97e 1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1655 *
1656 */
1657
1658static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1659{
1660#ifdef CONFIG_X86_64
1661 struct kvm_arch *ka = &kvm->arch;
1662 int vclock_mode;
b48aa97e
MT		 1663 bool host_tsc_clocksource, vcpus_matched;
1664
1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1666 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1667
1668 /*
1669 * If the host uses TSC clock, then passthrough TSC as stable
1670 * to the guest.
1671 */
b48aa97e 1672 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1673 &ka->master_kernel_ns,
1674 &ka->master_cycle_now);
1675
16a96021 1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1677 && !backwards_tsc_observed
1678 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1679
d828199e
MT		 1680 if (ka->use_master_clock)
1681 atomic_set(&kvm_guest_has_master_clock, 1);
1682
1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1685 vcpus_matched);
d828199e
MT		 1686#endif
1687}
1688
2860c4b1
PB		 1689void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1690{
1691 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1692}
1693
2e762ff7
MT		 1694static void kvm_gen_update_masterclock(struct kvm *kvm)
1695{
1696#ifdef CONFIG_X86_64
1697 int i;
1698 struct kvm_vcpu *vcpu;
1699 struct kvm_arch *ka = &kvm->arch;
1700
1701 spin_lock(&ka->pvclock_gtod_sync_lock);
1702 kvm_make_mclock_inprogress_request(kvm);
1703 /* no guest entries from this point */
1704 pvclock_update_vm_gtod_copy(kvm);
1705
1706 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1708
1709 /* guest entries allowed */
1710 kvm_for_each_vcpu(i, vcpu, kvm)
1711 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1712
1713 spin_unlock(&ka->pvclock_gtod_sync_lock);
1714#endif
1715}
1716
34c238a1 1717static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1718{
78db6a50 1719 unsigned long flags, tgt_tsc_khz;
18068523 1720 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1721 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1722 s64 kernel_ns;
d828199e 1723 u64 tsc_timestamp, host_tsc;
0b79459b 1724 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1725 u8 pvclock_flags;
d828199e
MT		 1726 bool use_master_clock;
1727
1728 kernel_ns = 0;
1729 host_tsc = 0;
18068523 1730
d828199e
MT		 1731 /*
1732 * If the host uses TSC clock, then passthrough TSC as stable
1733 * to the guest.
1734 */
1735 spin_lock(&ka->pvclock_gtod_sync_lock);
1736 use_master_clock = ka->use_master_clock;
1737 if (use_master_clock) {
1738 host_tsc = ka->master_cycle_now;
1739 kernel_ns = ka->master_kernel_ns;
1740 }
1741 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1742
1743 /* Keep irq disabled to prevent changes to the clock */
1744 local_irq_save(flags);
78db6a50
PB		 1745 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1746 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1747 local_irq_restore(flags);
1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1749 return 1;
1750 }
d828199e 1751 if (!use_master_clock) {
4ea1636b 1752 host_tsc = rdtsc();
d828199e
MT		 1753 kernel_ns = get_kernel_ns();
1754 }
1755
4ba76538 1756 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1757
c285545f
ZA		 1758 /*
1759 * We may have to catch up the TSC to match elapsed wall clock
1760 * time for two reasons, even if kvmclock is used.
1761 * 1) CPU could have been running below the maximum TSC rate
1762 * 2) Broken TSC compensation resets the base at each VCPU
1763 * entry to avoid unknown leaps of TSC even when running
1764 * again on the same CPU. This may cause apparent elapsed
1765 * time to disappear, and the guest to stand still or run
1766 * very slowly.
1767 */
1768 if (vcpu->tsc_catchup) {
1769 u64 tsc = compute_guest_tsc(v, kernel_ns);
1770 if (tsc > tsc_timestamp) {
f1e2b260 1771 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1772 tsc_timestamp = tsc;
1773 }
50d0a0f9
GH		 1774 }
1775
18068523
GOC		 1776 local_irq_restore(flags);
1777
0b79459b 1778 if (!vcpu->pv_time_enabled)
c285545f 1779 return 0;
18068523 1780
78db6a50
PB		 1781 if (kvm_has_tsc_control)
1782 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1783
1784 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1785 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1786 &vcpu->hv_clock.tsc_shift,
1787 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1788 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1789 }
1790
1791 /* With all the info we got, fill in the values */
1d5f066e 1792 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1793 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1794 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1795
09a0c3f1
OH		 1796 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1797 &guest_hv_clock, sizeof(guest_hv_clock))))
1798 return 0;
1799
5dca0d91
RK		 1800 /* This VCPU is paused, but it's legal for a guest to read another
1801 * VCPU's kvmclock, so we really have to follow the specification where
1802 * it says that version is odd if data is being modified, and even after
1803 * it is consistent.
1804 *
1805 * Version field updates must be kept separate. This is because
1806 * kvm_write_guest_cached might use a "rep movs" instruction, and
1807 * writes within a string instruction are weakly ordered. So there
1808 * are three writes overall.
1809 *
1810 * As a small optimization, only write the version field in the first
1811 * and third write. The vcpu->pv_time cache is still valid, because the
1812 * version field is the first in the struct.
18068523 1813 */
5dca0d91
RK		 1814 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1815
1816 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1817 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1818 &vcpu->hv_clock,
1819 sizeof(vcpu->hv_clock.version));
1820
1821 smp_wmb();
78c0337a
MT		 1822
1823 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1824 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1825
1826 if (vcpu->pvclock_set_guest_stopped_request) {
1827 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1828 vcpu->pvclock_set_guest_stopped_request = false;
1829 }
1830
d828199e
MT		 1831 /* If the host uses TSC clocksource, then it is stable */
1832 if (use_master_clock)
1833 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1834
78c0337a
MT		 1835 vcpu->hv_clock.flags = pvclock_flags;
1836
ce1a5e60
DM		 1837 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1838
0b79459b
AH		 1839 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1840 &vcpu->hv_clock,
1841 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1842
1843 smp_wmb();
1844
1845 vcpu->hv_clock.version++;
1846 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1847 &vcpu->hv_clock,
1848 sizeof(vcpu->hv_clock.version));
8cfdc000 1849 return 0;
c8076604
GH		 1850}
1851
0061d53d
MT		 1852/*
1853 * kvmclock updates which are isolated to a given vcpu, such as
1854 * vcpu->cpu migration, should not allow system_timestamp from
1855 * the rest of the vcpus to remain static. Otherwise ntp frequency
1856 * correction applies to one vcpu's system_timestamp but not
1857 * the others.
1858 *
1859 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1860 * We need to rate-limit these requests though, as they can
1861 * considerably slow guests that have a large number of vcpus.
1862 * The time for a remote vcpu to update its kvmclock is bound
1863 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1864 */
1865
7e44e449
AJ		 1866#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1867
1868static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1869{
1870 int i;
7e44e449
AJ		 1871 struct delayed_work *dwork = to_delayed_work(work);
1872 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1873 kvmclock_update_work);
1874 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1875 struct kvm_vcpu *vcpu;
1876
1877 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1879 kvm_vcpu_kick(vcpu);
1880 }
1881}
1882
7e44e449
AJ		 1883static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1884{
1885 struct kvm *kvm = v->kvm;
1886
105b21bb 1887 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1888 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1889 KVMCLOCK_UPDATE_DELAY);
1890}
1891
332967a3
AJ		 1892#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1893
1894static void kvmclock_sync_fn(struct work_struct *work)
1895{
1896 struct delayed_work *dwork = to_delayed_work(work);
1897 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1898 kvmclock_sync_work);
1899 struct kvm *kvm = container_of(ka, struct kvm, arch);
1900
630994b3
MT		 1901 if (!kvmclock_periodic_sync)
1902 return;
1903
332967a3
AJ		 1904 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1905 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1906 KVMCLOCK_SYNC_PERIOD);
1907}
1908
890ca9ae 1909static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1910{
890ca9ae
HY		 1911 u64 mcg_cap = vcpu->arch.mcg_cap;
1912 unsigned bank_num = mcg_cap & 0xff;
1913
15c4a640 1914 switch (msr) {
15c4a640 1915 case MSR_IA32_MCG_STATUS:
890ca9ae 1916 vcpu->arch.mcg_status = data;
15c4a640 1917 break;
c7ac679c 1918 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1919 if (!(mcg_cap & MCG_CTL_P))
1920 return 1;
1921 if (data != 0 && data != ~(u64)0)
1922 return -1;
1923 vcpu->arch.mcg_ctl = data;
1924 break;
1925 default:
1926 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1927 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1928 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1929 /* only 0 or all 1s can be written to IA32_MCi_CTL
1930 * some Linux kernels though clear bit 10 in bank 4 to
1931 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1932 * this to avoid an uncatched #GP in the guest
1933 */
890ca9ae 1934 if ((offset & 0x3) == 0 &&
114be429 1935 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1936 return -1;
1937 vcpu->arch.mce_banks[offset] = data;
1938 break;
1939 }
1940 return 1;
1941 }
1942 return 0;
1943}
1944
ffde22ac
ES		 1945static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1946{
1947 struct kvm *kvm = vcpu->kvm;
1948 int lm = is_long_mode(vcpu);
1949 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1950 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1951 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1952 : kvm->arch.xen_hvm_config.blob_size_32;
1953 u32 page_num = data & ~PAGE_MASK;
1954 u64 page_addr = data & PAGE_MASK;
1955 u8 *page;
1956 int r;
1957
1958 r = -E2BIG;
1959 if (page_num >= blob_size)
1960 goto out;
1961 r = -ENOMEM;
ff5c2c03
SL		 1962 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1963 if (IS_ERR(page)) {
1964 r = PTR_ERR(page);
ffde22ac 1965 goto out;
ff5c2c03 1966 }
54bf36aa 1967 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1968 goto out_free;
1969 r = 0;
1970out_free:
1971 kfree(page);
1972out:
1973 return r;
1974}
1975
344d9588
GN		 1976static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1977{
1978 gpa_t gpa = data & ~0x3f;
1979
4a969980 1980 /* Bits 2:5 are reserved, Should be zero */
6adba527 1981 if (data & 0x3c)
344d9588
GN		 1982 return 1;
1983
1984 vcpu->arch.apf.msr_val = data;
1985
1986 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1987 kvm_clear_async_pf_completion_queue(vcpu);
1988 kvm_async_pf_hash_reset(vcpu);
1989 return 0;
1990 }
1991
8f964525
AH		 1992 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1993 sizeof(u32)))
344d9588
GN		 1994 return 1;
1995
6adba527 1996 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1997 kvm_async_pf_wakeup_all(vcpu);
1998 return 0;
1999}
2000
12f9a48f
GC		 2001static void kvmclock_reset(struct kvm_vcpu *vcpu)
2002{
0b79459b 2003 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2004}
2005
c9aaa895
GC		 2006static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2007{
2008 u64 delta;
2009
2010 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2011 return;
2012
2013 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2014 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2015 vcpu->arch.st.accum_steal = delta;
2016}
2017
2018static void record_steal_time(struct kvm_vcpu *vcpu)
2019{
7cae2bed
MT		 2020 accumulate_steal_time(vcpu);
2021
c9aaa895
GC		 2022 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2023 return;
2024
2025 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2026 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2027 return;
2028
2029 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2030 vcpu->arch.st.steal.version += 2;
2031 vcpu->arch.st.accum_steal = 0;
2032
2033 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2034 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2035}
2036
8fe8ab46 2037int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2038{
5753785f 2039 bool pr = false;
8fe8ab46
WA		 2040 u32 msr = msr_info->index;
2041 u64 data = msr_info->data;
5753785f 2042
15c4a640 2043 switch (msr) {
2e32b719
BP		 2044 case MSR_AMD64_NB_CFG:
2045 case MSR_IA32_UCODE_REV:
2046 case MSR_IA32_UCODE_WRITE:
2047 case MSR_VM_HSAVE_PA:
2048 case MSR_AMD64_PATCH_LOADER:
2049 case MSR_AMD64_BU_CFG2:
2050 break;
2051
15c4a640 2052 case MSR_EFER:
b69e8cae 2053 return set_efer(vcpu, data);
8f1589d9
AP		 2054 case MSR_K7_HWCR:
2055 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2056 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2057 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2058 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2059 if (data != 0) {
a737f256
CD		 2060 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2061 data);
8f1589d9
AP		 2062 return 1;
2063 }
15c4a640 2064 break;
f7c6d140
AP		 2065 case MSR_FAM10H_MMIO_CONF_BASE:
2066 if (data != 0) {
a737f256
CD		 2067 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2068 "0x%llx\n", data);
f7c6d140
AP		 2069 return 1;
2070 }
15c4a640 2071 break;
b5e2fec0
AG		 2072 case MSR_IA32_DEBUGCTLMSR:
2073 if (!data) {
2074 /* We support the non-activated case already */
2075 break;
2076 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2077 /* Values other than LBR and BTF are vendor-specific,
2078 thus reserved and should throw a #GP */
2079 return 1;
2080 }
a737f256
CD		 2081 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2082 __func__, data);
b5e2fec0 2083 break;
9ba075a6 2084 case 0x200 ... 0x2ff:
ff53604b 2085 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2086 case MSR_IA32_APICBASE:
58cb628d 2087 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2088 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2089 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2090 case MSR_IA32_TSCDEADLINE:
2091 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2092 break;
ba904635
WA		 2093 case MSR_IA32_TSC_ADJUST:
2094 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2095 if (!msr_info->host_initiated) {
d913b904 2096 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2097 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2098 }
2099 vcpu->arch.ia32_tsc_adjust_msr = data;
2100 }
2101 break;
15c4a640 2102 case MSR_IA32_MISC_ENABLE:
ad312c7c 2103 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2104 break;
64d60670
PB		 2105 case MSR_IA32_SMBASE:
2106 if (!msr_info->host_initiated)
2107 return 1;
2108 vcpu->arch.smbase = data;
2109 break;
11c6bffa 2110 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2111 case MSR_KVM_WALL_CLOCK:
2112 vcpu->kvm->arch.wall_clock = data;
2113 kvm_write_wall_clock(vcpu->kvm, data);
2114 break;
11c6bffa 2115 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2116 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2117 u64 gpa_offset;
54750f2c
MT		 2118 struct kvm_arch *ka = &vcpu->kvm->arch;
2119
12f9a48f 2120 kvmclock_reset(vcpu);
18068523 2121
54750f2c
MT		 2122 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2123 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2124
2125 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2126 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2127 &vcpu->requests);
2128
2129 ka->boot_vcpu_runs_old_kvmclock = tmp;
2130 }
2131
18068523 2132 vcpu->arch.time = data;
0061d53d 2133 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2134
2135 /* we verify if the enable bit is set... */
2136 if (!(data & 1))
2137 break;
2138
0b79459b 2139 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2140
0b79459b 2141 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2142 &vcpu->arch.pv_time, data & ~1ULL,
2143 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2144 vcpu->arch.pv_time_enabled = false;
2145 else
2146 vcpu->arch.pv_time_enabled = true;
32cad84f 2147
18068523
GOC		 2148 break;
2149 }
344d9588
GN		 2150 case MSR_KVM_ASYNC_PF_EN:
2151 if (kvm_pv_enable_async_pf(vcpu, data))
2152 return 1;
2153 break;
c9aaa895
GC		 2154 case MSR_KVM_STEAL_TIME:
2155
2156 if (unlikely(!sched_info_on()))
2157 return 1;
2158
2159 if (data & KVM_STEAL_RESERVED_MASK)
2160 return 1;
2161
2162 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2163 data & KVM_STEAL_VALID_BITS,
2164 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2165 return 1;
2166
2167 vcpu->arch.st.msr_val = data;
2168
2169 if (!(data & KVM_MSR_ENABLED))
2170 break;
2171
c9aaa895
GC		 2172 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2173
2174 break;
ae7a2a3f
MT		 2175 case MSR_KVM_PV_EOI_EN:
2176 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2177 return 1;
2178 break;
c9aaa895 2179
890ca9ae
HY		 2180 case MSR_IA32_MCG_CTL:
2181 case MSR_IA32_MCG_STATUS:
81760dcc 2182 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2183 return set_msr_mce(vcpu, msr, data);
71db6023 2184
6912ac32
WH		 2185 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2186 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2187 pr = true; /* fall through */
2188 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2189 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2190 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2191 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2192
2193 if (pr || data != 0)
a737f256
CD		 2194 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2195 "0x%x data 0x%llx\n", msr, data);
5753785f 2196 break;
84e0cefa
JS		 2197 case MSR_K7_CLK_CTL:
2198 /*
2199 * Ignore all writes to this no longer documented MSR.
2200 * Writes are only relevant for old K7 processors,
2201 * all pre-dating SVM, but a recommended workaround from
4a969980 2202 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2203 * affected processor models on the command line, hence
2204 * the need to ignore the workaround.
2205 */
2206 break;
55cd8e5a 2207 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2208 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2209 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2210 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2211 return kvm_hv_set_msr_common(vcpu, msr, data,
2212 msr_info->host_initiated);
91c9c3ed 2213 case MSR_IA32_BBL_CR_CTL3:
2214 /* Drop writes to this legacy MSR -- see rdmsr
2215 * counterpart for further detail.
2216 */
a737f256 2217 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2218 break;
2b036c6b
BO		 2219 case MSR_AMD64_OSVW_ID_LENGTH:
2220 if (!guest_cpuid_has_osvw(vcpu))
2221 return 1;
2222 vcpu->arch.osvw.length = data;
2223 break;
2224 case MSR_AMD64_OSVW_STATUS:
2225 if (!guest_cpuid_has_osvw(vcpu))
2226 return 1;
2227 vcpu->arch.osvw.status = data;
2228 break;
15c4a640 2229 default:
ffde22ac
ES		 2230 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2231 return xen_hvm_config(vcpu, data);
c6702c9d 2232 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2233 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2234 if (!ignore_msrs) {
a737f256
CD		 2235 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2236 msr, data);
ed85c068
AP		 2237 return 1;
2238 } else {
a737f256
CD		 2239 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2240 msr, data);
ed85c068
AP		 2241 break;
2242 }
15c4a640
CO		 2243 }
2244 return 0;
2245}
2246EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2247
2248
2249/*
2250 * Reads an msr value (of 'msr_index') into 'pdata'.
2251 * Returns 0 on success, non-0 otherwise.
2252 * Assumes vcpu_load() was already called.
2253 */
609e36d3 2254int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2255{
609e36d3 2256 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2257}
ff651cb6 2258EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2259
890ca9ae 2260static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2261{
2262 u64 data;
890ca9ae
HY		 2263 u64 mcg_cap = vcpu->arch.mcg_cap;
2264 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2265
2266 switch (msr) {
15c4a640
CO		 2267 case MSR_IA32_P5_MC_ADDR:
2268 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2269 data = 0;
2270 break;
15c4a640 2271 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2272 data = vcpu->arch.mcg_cap;
2273 break;
c7ac679c 2274 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2275 if (!(mcg_cap & MCG_CTL_P))
2276 return 1;
2277 data = vcpu->arch.mcg_ctl;
2278 break;
2279 case MSR_IA32_MCG_STATUS:
2280 data = vcpu->arch.mcg_status;
2281 break;
2282 default:
2283 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2284 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2285 u32 offset = msr - MSR_IA32_MC0_CTL;
2286 data = vcpu->arch.mce_banks[offset];
2287 break;
2288 }
2289 return 1;
2290 }
2291 *pdata = data;
2292 return 0;
2293}
2294
609e36d3 2295int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2296{
609e36d3 2297 switch (msr_info->index) {
890ca9ae 2298 case MSR_IA32_PLATFORM_ID:
15c4a640 2299 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2300 case MSR_IA32_DEBUGCTLMSR:
2301 case MSR_IA32_LASTBRANCHFROMIP:
2302 case MSR_IA32_LASTBRANCHTOIP:
2303 case MSR_IA32_LASTINTFROMIP:
2304 case MSR_IA32_LASTINTTOIP:
60af2ecd 2305 case MSR_K8_SYSCFG:
3afb1121
PB		 2306 case MSR_K8_TSEG_ADDR:
2307 case MSR_K8_TSEG_MASK:
60af2ecd 2308 case MSR_K7_HWCR:
61a6bd67 2309 case MSR_VM_HSAVE_PA:
1fdbd48c 2310 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2311 case MSR_AMD64_NB_CFG:
f7c6d140 2312 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2313 case MSR_AMD64_BU_CFG2:
609e36d3 2314 msr_info->data = 0;
15c4a640 2315 break;
6912ac32
WH		 2316 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2317 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2318 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2319 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2320 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2321 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2322 msr_info->data = 0;
5753785f 2323 break;
742bc670 2324 case MSR_IA32_UCODE_REV:
609e36d3 2325 msr_info->data = 0x100000000ULL;
742bc670 2326 break;
9ba075a6 2327 case MSR_MTRRcap:
9ba075a6 2328 case 0x200 ... 0x2ff:
ff53604b 2329 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2330 case 0xcd: /* fsb frequency */
609e36d3 2331 msr_info->data = 3;
15c4a640 2332 break;
7b914098
JS		 2333 /*
2334 * MSR_EBC_FREQUENCY_ID
2335 * Conservative value valid for even the basic CPU models.
2336 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2337 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2338 * and 266MHz for model 3, or 4. Set Core Clock
2339 * Frequency to System Bus Frequency Ratio to 1 (bits
2340 * 31:24) even though these are only valid for CPU
2341 * models > 2, however guests may end up dividing or
2342 * multiplying by zero otherwise.
2343 */
2344 case MSR_EBC_FREQUENCY_ID:
609e36d3 2345 msr_info->data = 1 << 24;
7b914098 2346 break;
15c4a640 2347 case MSR_IA32_APICBASE:
609e36d3 2348 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2349 break;
0105d1a5 2350 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2351 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2352 break;
a3e06bbe 2353 case MSR_IA32_TSCDEADLINE:
609e36d3 2354 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2355 break;
ba904635 2356 case MSR_IA32_TSC_ADJUST:
609e36d3 2357 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2358 break;
15c4a640 2359 case MSR_IA32_MISC_ENABLE:
609e36d3 2360 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2361 break;
64d60670
PB		 2362 case MSR_IA32_SMBASE:
2363 if (!msr_info->host_initiated)
2364 return 1;
2365 msr_info->data = vcpu->arch.smbase;
15c4a640 2366 break;
847f0ad8
AG		 2367 case MSR_IA32_PERF_STATUS:
2368 /* TSC increment by tick */
609e36d3 2369 msr_info->data = 1000ULL;
847f0ad8 2370 /* CPU multiplier */
b0996ae4 2371 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2372 break;
15c4a640 2373 case MSR_EFER:
609e36d3 2374 msr_info->data = vcpu->arch.efer;
15c4a640 2375 break;
18068523 2376 case MSR_KVM_WALL_CLOCK:
11c6bffa 2377 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2378 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2379 break;
2380 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2381 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2382 msr_info->data = vcpu->arch.time;
18068523 2383 break;
344d9588 2384 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2385 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2386 break;
c9aaa895 2387 case MSR_KVM_STEAL_TIME:
609e36d3 2388 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2389 break;
1d92128f 2390 case MSR_KVM_PV_EOI_EN:
609e36d3 2391 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2392 break;
890ca9ae
HY		 2393 case MSR_IA32_P5_MC_ADDR:
2394 case MSR_IA32_P5_MC_TYPE:
2395 case MSR_IA32_MCG_CAP:
2396 case MSR_IA32_MCG_CTL:
2397 case MSR_IA32_MCG_STATUS:
81760dcc 2398 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2399 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2400 case MSR_K7_CLK_CTL:
2401 /*
2402 * Provide expected ramp-up count for K7. All other
2403 * are set to zero, indicating minimum divisors for
2404 * every field.
2405 *
2406 * This prevents guest kernels on AMD host with CPU
2407 * type 6, model 8 and higher from exploding due to
2408 * the rdmsr failing.
2409 */
609e36d3 2410 msr_info->data = 0x20000000;
84e0cefa 2411 break;
55cd8e5a 2412 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2413 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2414 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2415 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2416 return kvm_hv_get_msr_common(vcpu,
2417 msr_info->index, &msr_info->data);
55cd8e5a 2418 break;
91c9c3ed 2419 case MSR_IA32_BBL_CR_CTL3:
2420 /* This legacy MSR exists but isn't fully documented in current
2421 * silicon. It is however accessed by winxp in very narrow
2422 * scenarios where it sets bit #19, itself documented as
2423 * a "reserved" bit. Best effort attempt to source coherent
2424 * read data here should the balance of the register be
2425 * interpreted by the guest:
2426 *
2427 * L2 cache control register 3: 64GB range, 256KB size,
2428 * enabled, latency 0x1, configured
2429 */
609e36d3 2430 msr_info->data = 0xbe702111;
91c9c3ed 2431 break;
2b036c6b
BO		 2432 case MSR_AMD64_OSVW_ID_LENGTH:
2433 if (!guest_cpuid_has_osvw(vcpu))
2434 return 1;
609e36d3 2435 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2436 break;
2437 case MSR_AMD64_OSVW_STATUS:
2438 if (!guest_cpuid_has_osvw(vcpu))
2439 return 1;
609e36d3 2440 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2441 break;
15c4a640 2442 default:
c6702c9d 2443 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2444 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2445 if (!ignore_msrs) {
609e36d3 2446 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2447 return 1;
2448 } else {
609e36d3
PB		 2449 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2450 msr_info->data = 0;
ed85c068
AP		 2451 }
2452 break;
15c4a640 2453 }
15c4a640
CO		 2454 return 0;
2455}
2456EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2457
313a3dc7
CO		 2458/*
2459 * Read or write a bunch of msrs. All parameters are kernel addresses.
2460 *
2461 * @return number of msrs set successfully.
2462 */
2463static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2464 struct kvm_msr_entry *entries,
2465 int (*do_msr)(struct kvm_vcpu *vcpu,
2466 unsigned index, u64 *data))
2467{
f656ce01 2468 int i, idx;
313a3dc7 2469
f656ce01 2470 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2471 for (i = 0; i < msrs->nmsrs; ++i)
2472 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2473 break;
f656ce01 2474 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2475
313a3dc7
CO		 2476 return i;
2477}
2478
2479/*
2480 * Read or write a bunch of msrs. Parameters are user addresses.
2481 *
2482 * @return number of msrs set successfully.
2483 */
2484static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2485 int (*do_msr)(struct kvm_vcpu *vcpu,
2486 unsigned index, u64 *data),
2487 int writeback)
2488{
2489 struct kvm_msrs msrs;
2490 struct kvm_msr_entry *entries;
2491 int r, n;
2492 unsigned size;
2493
2494 r = -EFAULT;
2495 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2496 goto out;
2497
2498 r = -E2BIG;
2499 if (msrs.nmsrs >= MAX_IO_MSRS)
2500 goto out;
2501
313a3dc7 2502 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2503 entries = memdup_user(user_msrs->entries, size);
2504 if (IS_ERR(entries)) {
2505 r = PTR_ERR(entries);
313a3dc7 2506 goto out;
ff5c2c03 2507 }
313a3dc7
CO		 2508
2509 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2510 if (r < 0)
2511 goto out_free;
2512
2513 r = -EFAULT;
2514 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2515 goto out_free;
2516
2517 r = n;
2518
2519out_free:
7a73c028 2520 kfree(entries);
313a3dc7
CO		 2521out:
2522 return r;
2523}
2524
784aa3d7 2525int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2526{
2527 int r;
2528
2529 switch (ext) {
2530 case KVM_CAP_IRQCHIP:
2531 case KVM_CAP_HLT:
2532 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2533 case KVM_CAP_SET_TSS_ADDR:
07716717 2534 case KVM_CAP_EXT_CPUID:
9c15bb1d 2535 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2536 case KVM_CAP_CLOCKSOURCE:
7837699f 2537 case KVM_CAP_PIT:
a28e4f5a 2538 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2539 case KVM_CAP_MP_STATE:
ed848624 2540 case KVM_CAP_SYNC_MMU:
a355c85c 2541 case KVM_CAP_USER_NMI:
52d939a0 2542 case KVM_CAP_REINJECT_CONTROL:
4925663a 2543 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2544 case KVM_CAP_IOEVENTFD:
f848a5a8 2545 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2546 case KVM_CAP_PIT2:
e9f42757 2547 case KVM_CAP_PIT_STATE2:
b927a3ce 2548 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2549 case KVM_CAP_XEN_HVM:
afbcf7ab 2550 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2551 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2552 case KVM_CAP_HYPERV:
10388a07 2553 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2554 case KVM_CAP_HYPERV_SPIN:
5c919412 2555 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2556 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2557 case KVM_CAP_DEBUGREGS:
d2be1651 2558 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2559 case KVM_CAP_XSAVE:
344d9588 2560 case KVM_CAP_ASYNC_PF:
92a1f12d 2561 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2562 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2563 case KVM_CAP_READONLY_MEM:
5f66b620 2564 case KVM_CAP_HYPERV_TIME:
100943c5 2565 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2566 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2567 case KVM_CAP_ENABLE_CAP_VM:
2568 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2569 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2570 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2571#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2572 case KVM_CAP_ASSIGN_DEV_IRQ:
2573 case KVM_CAP_PCI_2_3:
2574#endif
018d00d2
ZX		 2575 r = 1;
2576 break;
6d396b55
PB		 2577 case KVM_CAP_X86_SMM:
2578 /* SMBASE is usually relocated above 1M on modern chipsets,
2579 * and SMM handlers might indeed rely on 4G segment limits,
2580 * so do not report SMM to be available if real mode is
2581 * emulated via vm86 mode. Still, do not go to great lengths
2582 * to avoid userspace's usage of the feature, because it is a
2583 * fringe case that is not enabled except via specific settings
2584 * of the module parameters.
2585 */
2586 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2587 break;
542472b5
LV		 2588 case KVM_CAP_COALESCED_MMIO:
2589 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2590 break;
774ead3a
AK		 2591 case KVM_CAP_VAPIC:
2592 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2593 break;
f725230a 2594 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2595 r = KVM_SOFT_MAX_VCPUS;
2596 break;
2597 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2598 r = KVM_MAX_VCPUS;
2599 break;
a988b910 2600 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2601 r = KVM_USER_MEM_SLOTS;
a988b910 2602 break;
a68a6a72
MT		 2603 case KVM_CAP_PV_MMU: /* obsolete */
2604 r = 0;
2f333bcb 2605 break;
4cee4b72 2606#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2607 case KVM_CAP_IOMMU:
a1b60c1c 2608 r = iommu_present(&pci_bus_type);
62c476c7 2609 break;
4cee4b72 2610#endif
890ca9ae
HY		 2611 case KVM_CAP_MCE:
2612 r = KVM_MAX_MCE_BANKS;
2613 break;
2d5b5a66
SY		 2614 case KVM_CAP_XCRS:
2615 r = cpu_has_xsave;
2616 break;
92a1f12d
JR		 2617 case KVM_CAP_TSC_CONTROL:
2618 r = kvm_has_tsc_control;
2619 break;
018d00d2
ZX		 2620 default:
2621 r = 0;
2622 break;
2623 }
2624 return r;
2625
2626}
2627
043405e1
CO		 2628long kvm_arch_dev_ioctl(struct file *filp,
2629 unsigned int ioctl, unsigned long arg)
2630{
2631 void __user *argp = (void __user *)arg;
2632 long r;
2633
2634 switch (ioctl) {
2635 case KVM_GET_MSR_INDEX_LIST: {
2636 struct kvm_msr_list __user *user_msr_list = argp;
2637 struct kvm_msr_list msr_list;
2638 unsigned n;
2639
2640 r = -EFAULT;
2641 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2642 goto out;
2643 n = msr_list.nmsrs;
62ef68bb 2644 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2645 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2646 goto out;
2647 r = -E2BIG;
e125e7b6 2648 if (n < msr_list.nmsrs)
043405e1
CO		 2649 goto out;
2650 r = -EFAULT;
2651 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2652 num_msrs_to_save * sizeof(u32)))
2653 goto out;
e125e7b6 2654 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2655 &emulated_msrs,
62ef68bb 2656 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2657 goto out;
2658 r = 0;
2659 break;
2660 }
9c15bb1d
BP		 2661 case KVM_GET_SUPPORTED_CPUID:
2662 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2663 struct kvm_cpuid2 __user *cpuid_arg = argp;
2664 struct kvm_cpuid2 cpuid;
2665
2666 r = -EFAULT;
2667 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2668 goto out;
9c15bb1d
BP		 2669
2670 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2671 ioctl);
674eea0f
AK		 2672 if (r)
2673 goto out;
2674
2675 r = -EFAULT;
2676 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2677 goto out;
2678 r = 0;
2679 break;
2680 }
890ca9ae
HY		 2681 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2682 u64 mce_cap;
2683
2684 mce_cap = KVM_MCE_CAP_SUPPORTED;
2685 r = -EFAULT;
2686 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2687 goto out;
2688 r = 0;
2689 break;
2690 }
043405e1
CO		 2691 default:
2692 r = -EINVAL;
2693 }
2694out:
2695 return r;
2696}
2697
f5f48ee1
SY		 2698static void wbinvd_ipi(void *garbage)
2699{
2700 wbinvd();
2701}
2702
2703static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2704{
e0f0bbc5 2705 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2706}
2707
2860c4b1
PB		 2708static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2709{
2710 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2711}
2712
313a3dc7
CO		 2713void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2714{
f5f48ee1
SY		 2715 /* Address WBINVD may be executed by guest */
2716 if (need_emulate_wbinvd(vcpu)) {
2717 if (kvm_x86_ops->has_wbinvd_exit())
2718 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2719 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2720 smp_call_function_single(vcpu->cpu,
2721 wbinvd_ipi, NULL, 1);
2722 }
2723
313a3dc7 2724 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2725
0dd6a6ed
ZA		 2726 /* Apply any externally detected TSC adjustments (due to suspend) */
2727 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2728 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2729 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2730 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2731 }
8f6055cb 2732
48434c20 2733 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2734 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2735 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2736 if (tsc_delta < 0)
2737 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2738 if (check_tsc_unstable()) {
07c1419a 2739 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2740 vcpu->arch.last_guest_tsc);
2741 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2742 vcpu->arch.tsc_catchup = 1;
c285545f 2743 }
d98d07ca
MT		 2744 /*
2745 * On a host with synchronized TSC, there is no need to update
2746 * kvmclock on vcpu->cpu migration
2747 */
2748 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2749 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2750 if (vcpu->cpu != cpu)
2751 kvm_migrate_timers(vcpu);
e48672fa 2752 vcpu->cpu = cpu;
6b7d7e76 2753 }
c9aaa895 2754
c9aaa895 2755 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2756}
2757
2758void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2759{
02daab21 2760 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2761 kvm_put_guest_fpu(vcpu);
4ea1636b 2762 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2763}
2764
313a3dc7
CO		 2765static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2766 struct kvm_lapic_state *s)
2767{
d62caabb
AS		 2768 if (vcpu->arch.apicv_active)
2769 kvm_x86_ops->sync_pir_to_irr(vcpu);
2770
ad312c7c 2771 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2772
2773 return 0;
2774}
2775
2776static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2777 struct kvm_lapic_state *s)
2778{
64eb0620 2779 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2780 update_cr8_intercept(vcpu);
313a3dc7
CO		 2781
2782 return 0;
2783}
2784
127a457a
MG		 2785static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2786{
2787 return (!lapic_in_kernel(vcpu) ||
2788 kvm_apic_accept_pic_intr(vcpu));
2789}
2790
782d422b
MG		 2791/*
2792 * if userspace requested an interrupt window, check that the
2793 * interrupt window is open.
2794 *
2795 * No need to exit to userspace if we already have an interrupt queued.
2796 */
2797static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2798{
2799 return kvm_arch_interrupt_allowed(vcpu) &&
2800 !kvm_cpu_has_interrupt(vcpu) &&
2801 !kvm_event_needs_reinjection(vcpu) &&
2802 kvm_cpu_accept_dm_intr(vcpu);
2803}
2804
f77bc6a4
ZX		 2805static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2806 struct kvm_interrupt *irq)
2807{
02cdb50f 2808 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2809 return -EINVAL;
1c1a9ce9
SR		 2810
2811 if (!irqchip_in_kernel(vcpu->kvm)) {
2812 kvm_queue_interrupt(vcpu, irq->irq, false);
2813 kvm_make_request(KVM_REQ_EVENT, vcpu);
2814 return 0;
2815 }
2816
2817 /*
2818 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2819 * fail for in-kernel 8259.
2820 */
2821 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2822 return -ENXIO;
f77bc6a4 2823
1c1a9ce9
SR		 2824 if (vcpu->arch.pending_external_vector != -1)
2825 return -EEXIST;
f77bc6a4 2826
1c1a9ce9 2827 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2828 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2829 return 0;
2830}
2831
c4abb7c9
JK		 2832static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2833{
c4abb7c9 2834 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2835
2836 return 0;
2837}
2838
f077825a
PB		 2839static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2840{
64d60670
PB		 2841 kvm_make_request(KVM_REQ_SMI, vcpu);
2842
f077825a
PB		 2843 return 0;
2844}
2845
b209749f
AK		 2846static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2847 struct kvm_tpr_access_ctl *tac)
2848{
2849 if (tac->flags)
2850 return -EINVAL;
2851 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2852 return 0;
2853}
2854
890ca9ae
HY		 2855static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2856 u64 mcg_cap)
2857{
2858 int r;
2859 unsigned bank_num = mcg_cap & 0xff, bank;
2860
2861 r = -EINVAL;
a9e38c3e 2862 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2863 goto out;
2864 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2865 goto out;
2866 r = 0;
2867 vcpu->arch.mcg_cap = mcg_cap;
2868 /* Init IA32_MCG_CTL to all 1s */
2869 if (mcg_cap & MCG_CTL_P)
2870 vcpu->arch.mcg_ctl = ~(u64)0;
2871 /* Init IA32_MCi_CTL to all 1s */
2872 for (bank = 0; bank < bank_num; bank++)
2873 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2874out:
2875 return r;
2876}
2877
2878static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2879 struct kvm_x86_mce *mce)
2880{
2881 u64 mcg_cap = vcpu->arch.mcg_cap;
2882 unsigned bank_num = mcg_cap & 0xff;
2883 u64 *banks = vcpu->arch.mce_banks;
2884
2885 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2886 return -EINVAL;
2887 /*
2888 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2889 * reporting is disabled
2890 */
2891 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2892 vcpu->arch.mcg_ctl != ~(u64)0)
2893 return 0;
2894 banks += 4 * mce->bank;
2895 /*
2896 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2897 * reporting is disabled for the bank
2898 */
2899 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2900 return 0;
2901 if (mce->status & MCI_STATUS_UC) {
2902 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2903 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2904 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2905 return 0;
2906 }
2907 if (banks[1] & MCI_STATUS_VAL)
2908 mce->status |= MCI_STATUS_OVER;
2909 banks[2] = mce->addr;
2910 banks[3] = mce->misc;
2911 vcpu->arch.mcg_status = mce->mcg_status;
2912 banks[1] = mce->status;
2913 kvm_queue_exception(vcpu, MC_VECTOR);
2914 } else if (!(banks[1] & MCI_STATUS_VAL)
2915 || !(banks[1] & MCI_STATUS_UC)) {
2916 if (banks[1] & MCI_STATUS_VAL)
2917 mce->status |= MCI_STATUS_OVER;
2918 banks[2] = mce->addr;
2919 banks[3] = mce->misc;
2920 banks[1] = mce->status;
2921 } else
2922 banks[1] |= MCI_STATUS_OVER;
2923 return 0;
2924}
2925
3cfc3092
JK		 2926static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2927 struct kvm_vcpu_events *events)
2928{
7460fb4a 2929 process_nmi(vcpu);
03b82a30
JK		 2930 events->exception.injected =
2931 vcpu->arch.exception.pending &&
2932 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2933 events->exception.nr = vcpu->arch.exception.nr;
2934 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2935 events->exception.pad = 0;
3cfc3092
JK		 2936 events->exception.error_code = vcpu->arch.exception.error_code;
2937
03b82a30
JK		 2938 events->interrupt.injected =
2939 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2940 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2941 events->interrupt.soft = 0;
37ccdcbe 2942 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2943
2944 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2945 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2946 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2947 events->nmi.pad = 0;
3cfc3092 2948
66450a21 2949 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2950
f077825a
PB		 2951 events->smi.smm = is_smm(vcpu);
2952 events->smi.pending = vcpu->arch.smi_pending;
2953 events->smi.smm_inside_nmi =
2954 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2955 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2956
dab4b911 2957 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2958 | KVM_VCPUEVENT_VALID_SHADOW
2959 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2960 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2961}
2962
2963static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2964 struct kvm_vcpu_events *events)
2965{
dab4b911 2966 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2967 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2968 | KVM_VCPUEVENT_VALID_SHADOW
2969 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2970 return -EINVAL;
2971
7460fb4a 2972 process_nmi(vcpu);
3cfc3092
JK		 2973 vcpu->arch.exception.pending = events->exception.injected;
2974 vcpu->arch.exception.nr = events->exception.nr;
2975 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2976 vcpu->arch.exception.error_code = events->exception.error_code;
2977
2978 vcpu->arch.interrupt.pending = events->interrupt.injected;
2979 vcpu->arch.interrupt.nr = events->interrupt.nr;
2980 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2981 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2982 kvm_x86_ops->set_interrupt_shadow(vcpu,
2983 events->interrupt.shadow);
3cfc3092
JK		 2984
2985 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2986 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2987 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2988 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2989
66450a21 2990 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 2991 lapic_in_kernel(vcpu))
66450a21 2992 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2993
f077825a
PB		 2994 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2995 if (events->smi.smm)
2996 vcpu->arch.hflags |= HF_SMM_MASK;
2997 else
2998 vcpu->arch.hflags &= ~HF_SMM_MASK;
2999 vcpu->arch.smi_pending = events->smi.pending;
3000 if (events->smi.smm_inside_nmi)
3001 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3002 else
3003 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3004 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3005 if (events->smi.latched_init)
3006 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3007 else
3008 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3009 }
3010 }
3011
3842d135
AK		 3012 kvm_make_request(KVM_REQ_EVENT, vcpu);
3013
3cfc3092
JK		 3014 return 0;
3015}
3016
a1efbe77
JK		 3017static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3018 struct kvm_debugregs *dbgregs)
3019{
73aaf249
JK		 3020 unsigned long val;
3021
a1efbe77 3022 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3023 kvm_get_dr(vcpu, 6, &val);
73aaf249 3024 dbgregs->dr6 = val;
a1efbe77
JK		 3025 dbgregs->dr7 = vcpu->arch.dr7;
3026 dbgregs->flags = 0;
97e69aa6 3027 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3028}
3029
3030static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3031 struct kvm_debugregs *dbgregs)
3032{
3033 if (dbgregs->flags)
3034 return -EINVAL;
3035
a1efbe77 3036 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3037 kvm_update_dr0123(vcpu);
a1efbe77 3038 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3039 kvm_update_dr6(vcpu);
a1efbe77 3040 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3041 kvm_update_dr7(vcpu);
a1efbe77 3042
a1efbe77
JK		 3043 return 0;
3044}
3045
df1daba7
PB		 3046#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3047
3048static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3049{
c47ada30 3050 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3051 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3052 u64 valid;
3053
3054 /*
3055 * Copy legacy XSAVE area, to avoid complications with CPUID
3056 * leaves 0 and 1 in the loop below.
3057 */
3058 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3059
3060 /* Set XSTATE_BV */
3061 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3062
3063 /*
3064 * Copy each region from the possibly compacted offset to the
3065 * non-compacted offset.
3066 */
d91cab78 3067 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3068 while (valid) {
3069 u64 feature = valid & -valid;
3070 int index = fls64(feature) - 1;
3071 void *src = get_xsave_addr(xsave, feature);
3072
3073 if (src) {
3074 u32 size, offset, ecx, edx;
3075 cpuid_count(XSTATE_CPUID, index,
3076 &size, &offset, &ecx, &edx);
3077 memcpy(dest + offset, src, size);
3078 }
3079
3080 valid -= feature;
3081 }
3082}
3083
3084static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3085{
c47ada30 3086 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3087 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3088 u64 valid;
3089
3090 /*
3091 * Copy legacy XSAVE area, to avoid complications with CPUID
3092 * leaves 0 and 1 in the loop below.
3093 */
3094 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3095
3096 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3097 xsave->header.xfeatures = xstate_bv;
df1daba7 3098 if (cpu_has_xsaves)
3a54450b 3099 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3100
3101 /*
3102 * Copy each region from the non-compacted offset to the
3103 * possibly compacted offset.
3104 */
d91cab78 3105 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3106 while (valid) {
3107 u64 feature = valid & -valid;
3108 int index = fls64(feature) - 1;
3109 void *dest = get_xsave_addr(xsave, feature);
3110
3111 if (dest) {
3112 u32 size, offset, ecx, edx;
3113 cpuid_count(XSTATE_CPUID, index,
3114 &size, &offset, &ecx, &edx);
3115 memcpy(dest, src + offset, size);
ee4100da 3116 }
df1daba7
PB		 3117
3118 valid -= feature;
3119 }
3120}
3121
2d5b5a66
SY		 3122static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3123 struct kvm_xsave *guest_xsave)
3124{
4344ee98 3125 if (cpu_has_xsave) {
df1daba7
PB		 3126 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3127 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3128 } else {
2d5b5a66 3129 memcpy(guest_xsave->region,
7366ed77 3130 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3131 sizeof(struct fxregs_state));
2d5b5a66 3132 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3133 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3134 }
3135}
3136
3137static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3138 struct kvm_xsave *guest_xsave)
3139{
3140 u64 xstate_bv =
3141 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3142
d7876f1b
PB		 3143 if (cpu_has_xsave) {
3144 /*
3145 * Here we allow setting states that are not present in
3146 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3147 * with old userspace.
3148 */
4ff41732 3149 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3150 return -EINVAL;
df1daba7 3151 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3152 } else {
d91cab78 3153 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3154 return -EINVAL;
7366ed77 3155 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3156 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3157 }
3158 return 0;
3159}
3160
3161static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3162 struct kvm_xcrs *guest_xcrs)
3163{
3164 if (!cpu_has_xsave) {
3165 guest_xcrs->nr_xcrs = 0;
3166 return;
3167 }
3168
3169 guest_xcrs->nr_xcrs = 1;
3170 guest_xcrs->flags = 0;
3171 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3172 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3173}
3174
3175static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3176 struct kvm_xcrs *guest_xcrs)
3177{
3178 int i, r = 0;
3179
3180 if (!cpu_has_xsave)
3181 return -EINVAL;
3182
3183 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3184 return -EINVAL;
3185
3186 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3187 /* Only support XCR0 currently */
c67a04cb 3188 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3189 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3190 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3191 break;
3192 }
3193 if (r)
3194 r = -EINVAL;
3195 return r;
3196}
3197
1c0b28c2
EM		 3198/*
3199 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3200 * stopped by the hypervisor. This function will be called from the host only.
3201 * EINVAL is returned when the host attempts to set the flag for a guest that
3202 * does not support pv clocks.
3203 */
3204static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3205{
0b79459b 3206 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3207 return -EINVAL;
51d59c6b 3208 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3209 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3210 return 0;
3211}
3212
5c919412
AS		 3213static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3214 struct kvm_enable_cap *cap)
3215{
3216 if (cap->flags)
3217 return -EINVAL;
3218
3219 switch (cap->cap) {
3220 case KVM_CAP_HYPERV_SYNIC:
3221 return kvm_hv_activate_synic(vcpu);
3222 default:
3223 return -EINVAL;
3224 }
3225}
3226
313a3dc7
CO		 3227long kvm_arch_vcpu_ioctl(struct file *filp,
3228 unsigned int ioctl, unsigned long arg)
3229{
3230 struct kvm_vcpu *vcpu = filp->private_data;
3231 void __user *argp = (void __user *)arg;
3232 int r;
d1ac91d8
AK		 3233 union {
3234 struct kvm_lapic_state *lapic;
3235 struct kvm_xsave *xsave;
3236 struct kvm_xcrs *xcrs;
3237 void *buffer;
3238 } u;
3239
3240 u.buffer = NULL;
313a3dc7
CO		 3241 switch (ioctl) {
3242 case KVM_GET_LAPIC: {
2204ae3c 3243 r = -EINVAL;
bce87cce 3244 if (!lapic_in_kernel(vcpu))
2204ae3c 3245 goto out;
d1ac91d8 3246 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3247
b772ff36 3248 r = -ENOMEM;
d1ac91d8 3249 if (!u.lapic)
b772ff36 3250 goto out;
d1ac91d8 3251 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3252 if (r)
3253 goto out;
3254 r = -EFAULT;
d1ac91d8 3255 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3256 goto out;
3257 r = 0;
3258 break;
3259 }
3260 case KVM_SET_LAPIC: {
2204ae3c 3261 r = -EINVAL;
bce87cce 3262 if (!lapic_in_kernel(vcpu))
2204ae3c 3263 goto out;
ff5c2c03 3264 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3265 if (IS_ERR(u.lapic))
3266 return PTR_ERR(u.lapic);
ff5c2c03 3267
d1ac91d8 3268 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3269 break;
3270 }
f77bc6a4
ZX		 3271 case KVM_INTERRUPT: {
3272 struct kvm_interrupt irq;
3273
3274 r = -EFAULT;
3275 if (copy_from_user(&irq, argp, sizeof irq))
3276 goto out;
3277 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3278 break;
3279 }
c4abb7c9
JK		 3280 case KVM_NMI: {
3281 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3282 break;
3283 }
f077825a
PB		 3284 case KVM_SMI: {
3285 r = kvm_vcpu_ioctl_smi(vcpu);
3286 break;
3287 }
313a3dc7
CO		 3288 case KVM_SET_CPUID: {
3289 struct kvm_cpuid __user *cpuid_arg = argp;
3290 struct kvm_cpuid cpuid;
3291
3292 r = -EFAULT;
3293 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3294 goto out;
3295 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3296 break;
3297 }
07716717
DK		 3298 case KVM_SET_CPUID2: {
3299 struct kvm_cpuid2 __user *cpuid_arg = argp;
3300 struct kvm_cpuid2 cpuid;
3301
3302 r = -EFAULT;
3303 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3304 goto out;
3305 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3306 cpuid_arg->entries);
07716717
DK		 3307 break;
3308 }
3309 case KVM_GET_CPUID2: {
3310 struct kvm_cpuid2 __user *cpuid_arg = argp;
3311 struct kvm_cpuid2 cpuid;
3312
3313 r = -EFAULT;
3314 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3315 goto out;
3316 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3317 cpuid_arg->entries);
07716717
DK		 3318 if (r)
3319 goto out;
3320 r = -EFAULT;
3321 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3322 goto out;
3323 r = 0;
3324 break;
3325 }
313a3dc7 3326 case KVM_GET_MSRS:
609e36d3 3327 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3328 break;
3329 case KVM_SET_MSRS:
3330 r = msr_io(vcpu, argp, do_set_msr, 0);
3331 break;
b209749f
AK		 3332 case KVM_TPR_ACCESS_REPORTING: {
3333 struct kvm_tpr_access_ctl tac;
3334
3335 r = -EFAULT;
3336 if (copy_from_user(&tac, argp, sizeof tac))
3337 goto out;
3338 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3339 if (r)
3340 goto out;
3341 r = -EFAULT;
3342 if (copy_to_user(argp, &tac, sizeof tac))
3343 goto out;
3344 r = 0;
3345 break;
3346 };
b93463aa
AK		 3347 case KVM_SET_VAPIC_ADDR: {
3348 struct kvm_vapic_addr va;
3349
3350 r = -EINVAL;
35754c98 3351 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3352 goto out;
3353 r = -EFAULT;
3354 if (copy_from_user(&va, argp, sizeof va))
3355 goto out;
fda4e2e8 3356 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3357 break;
3358 }
890ca9ae
HY		 3359 case KVM_X86_SETUP_MCE: {
3360 u64 mcg_cap;
3361
3362 r = -EFAULT;
3363 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3364 goto out;
3365 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3366 break;
3367 }
3368 case KVM_X86_SET_MCE: {
3369 struct kvm_x86_mce mce;
3370
3371 r = -EFAULT;
3372 if (copy_from_user(&mce, argp, sizeof mce))
3373 goto out;
3374 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3375 break;
3376 }
3cfc3092
JK		 3377 case KVM_GET_VCPU_EVENTS: {
3378 struct kvm_vcpu_events events;
3379
3380 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3381
3382 r = -EFAULT;
3383 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3384 break;
3385 r = 0;
3386 break;
3387 }
3388 case KVM_SET_VCPU_EVENTS: {
3389 struct kvm_vcpu_events events;
3390
3391 r = -EFAULT;
3392 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3393 break;
3394
3395 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3396 break;
3397 }
a1efbe77
JK		 3398 case KVM_GET_DEBUGREGS: {
3399 struct kvm_debugregs dbgregs;
3400
3401 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3402
3403 r = -EFAULT;
3404 if (copy_to_user(argp, &dbgregs,
3405 sizeof(struct kvm_debugregs)))
3406 break;
3407 r = 0;
3408 break;
3409 }
3410 case KVM_SET_DEBUGREGS: {
3411 struct kvm_debugregs dbgregs;
3412
3413 r = -EFAULT;
3414 if (copy_from_user(&dbgregs, argp,
3415 sizeof(struct kvm_debugregs)))
3416 break;
3417
3418 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3419 break;
3420 }
2d5b5a66 3421 case KVM_GET_XSAVE: {
d1ac91d8 3422 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3423 r = -ENOMEM;
d1ac91d8 3424 if (!u.xsave)
2d5b5a66
SY		 3425 break;
3426
d1ac91d8 3427 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3428
3429 r = -EFAULT;
d1ac91d8 3430 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3431 break;
3432 r = 0;
3433 break;
3434 }
3435 case KVM_SET_XSAVE: {
ff5c2c03 3436 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3437 if (IS_ERR(u.xsave))
3438 return PTR_ERR(u.xsave);
2d5b5a66 3439
d1ac91d8 3440 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3441 break;
3442 }
3443 case KVM_GET_XCRS: {
d1ac91d8 3444 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3445 r = -ENOMEM;
d1ac91d8 3446 if (!u.xcrs)
2d5b5a66
SY		 3447 break;
3448
d1ac91d8 3449 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3450
3451 r = -EFAULT;
d1ac91d8 3452 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3453 sizeof(struct kvm_xcrs)))
3454 break;
3455 r = 0;
3456 break;
3457 }
3458 case KVM_SET_XCRS: {
ff5c2c03 3459 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3460 if (IS_ERR(u.xcrs))
3461 return PTR_ERR(u.xcrs);
2d5b5a66 3462
d1ac91d8 3463 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3464 break;
3465 }
92a1f12d
JR		 3466 case KVM_SET_TSC_KHZ: {
3467 u32 user_tsc_khz;
3468
3469 r = -EINVAL;
92a1f12d
JR		 3470 user_tsc_khz = (u32)arg;
3471
3472 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3473 goto out;
3474
cc578287
ZA		 3475 if (user_tsc_khz == 0)
3476 user_tsc_khz = tsc_khz;
3477
381d585c
HZ		 3478 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3479 r = 0;
92a1f12d 3480
92a1f12d
JR		 3481 goto out;
3482 }
3483 case KVM_GET_TSC_KHZ: {
cc578287 3484 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3485 goto out;
3486 }
1c0b28c2
EM		 3487 case KVM_KVMCLOCK_CTRL: {
3488 r = kvm_set_guest_paused(vcpu);
3489 goto out;
3490 }
5c919412
AS		 3491 case KVM_ENABLE_CAP: {
3492 struct kvm_enable_cap cap;
3493
3494 r = -EFAULT;
3495 if (copy_from_user(&cap, argp, sizeof(cap)))
3496 goto out;
3497 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3498 break;
3499 }
313a3dc7
CO		 3500 default:
3501 r = -EINVAL;
3502 }
3503out:
d1ac91d8 3504 kfree(u.buffer);
313a3dc7
CO		 3505 return r;
3506}
3507
5b1c1493
CO		 3508int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3509{
3510 return VM_FAULT_SIGBUS;
3511}
3512
1fe779f8
CO		 3513static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3514{
3515 int ret;
3516
3517 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3518 return -EINVAL;
1fe779f8
CO		 3519 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3520 return ret;
3521}
3522
b927a3ce
SY		 3523static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3524 u64 ident_addr)
3525{
3526 kvm->arch.ept_identity_map_addr = ident_addr;
3527 return 0;
3528}
3529
1fe779f8
CO		 3530static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3531 u32 kvm_nr_mmu_pages)
3532{
3533 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3534 return -EINVAL;
3535
79fac95e 3536 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3537
3538 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3539 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3540
79fac95e 3541 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3542 return 0;
3543}
3544
3545static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3546{
39de71ec 3547 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3548}
3549
1fe779f8
CO		 3550static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3551{
3552 int r;
3553
3554 r = 0;
3555 switch (chip->chip_id) {
3556 case KVM_IRQCHIP_PIC_MASTER:
3557 memcpy(&chip->chip.pic,
3558 &pic_irqchip(kvm)->pics[0],
3559 sizeof(struct kvm_pic_state));
3560 break;
3561 case KVM_IRQCHIP_PIC_SLAVE:
3562 memcpy(&chip->chip.pic,
3563 &pic_irqchip(kvm)->pics[1],
3564 sizeof(struct kvm_pic_state));
3565 break;
3566 case KVM_IRQCHIP_IOAPIC:
eba0226b 3567 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3568 break;
3569 default:
3570 r = -EINVAL;
3571 break;
3572 }
3573 return r;
3574}
3575
3576static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3577{
3578 int r;
3579
3580 r = 0;
3581 switch (chip->chip_id) {
3582 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3583 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3584 memcpy(&pic_irqchip(kvm)->pics[0],
3585 &chip->chip.pic,
3586 sizeof(struct kvm_pic_state));
f4f51050 3587 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3588 break;
3589 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3590 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3591 memcpy(&pic_irqchip(kvm)->pics[1],
3592 &chip->chip.pic,
3593 sizeof(struct kvm_pic_state));
f4f51050 3594 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3595 break;
3596 case KVM_IRQCHIP_IOAPIC:
eba0226b 3597 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3598 break;
3599 default:
3600 r = -EINVAL;
3601 break;
3602 }
3603 kvm_pic_update_irq(pic_irqchip(kvm));
3604 return r;
3605}
3606
e0f63cb9
SY		 3607static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3608{
34f3941c
RK		 3609 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3610
3611 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3612
3613 mutex_lock(&kps->lock);
3614 memcpy(ps, &kps->channels, sizeof(*ps));
3615 mutex_unlock(&kps->lock);
2da29bcc 3616 return 0;
e0f63cb9
SY		 3617}
3618
3619static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3620{
0185604c 3621 int i;
09edea72
RK		 3622 struct kvm_pit *pit = kvm->arch.vpit;
3623
3624 mutex_lock(&pit->pit_state.lock);
34f3941c 3625 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3626 for (i = 0; i < 3; i++)
09edea72
RK		 3627 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3628 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3629 return 0;
e9f42757
BK		 3630}
3631
3632static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3633{
e9f42757
BK		 3634 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3635 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3636 sizeof(ps->channels));
3637 ps->flags = kvm->arch.vpit->pit_state.flags;
3638 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3639 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3640 return 0;
e9f42757
BK		 3641}
3642
3643static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3644{
2da29bcc 3645 int start = 0;
0185604c 3646 int i;
e9f42757 3647 u32 prev_legacy, cur_legacy;
09edea72
RK		 3648 struct kvm_pit *pit = kvm->arch.vpit;
3649
3650 mutex_lock(&pit->pit_state.lock);
3651 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3652 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3653 if (!prev_legacy && cur_legacy)
3654 start = 1;
09edea72
RK		 3655 memcpy(&pit->pit_state.channels, &ps->channels,
3656 sizeof(pit->pit_state.channels));
3657 pit->pit_state.flags = ps->flags;
0185604c 3658 for (i = 0; i < 3; i++)
09edea72 3659 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3660 start && i == 0);
09edea72 3661 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3662 return 0;
e0f63cb9
SY		 3663}
3664
52d939a0
MT		 3665static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3666 struct kvm_reinject_control *control)
3667{
71474e2f
RK		 3668 struct kvm_pit *pit = kvm->arch.vpit;
3669
3670 if (!pit)
52d939a0 3671 return -ENXIO;
b39c90b6 3672
71474e2f
RK		 3673 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3674 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3675 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3676 */
3677 mutex_lock(&pit->pit_state.lock);
3678 kvm_pit_set_reinject(pit, control->pit_reinject);
3679 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3680
52d939a0
MT		 3681 return 0;
3682}
3683
95d4c16c 3684/**
60c34612
TY		 3685 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3686 * @kvm: kvm instance
3687 * @log: slot id and address to which we copy the log
95d4c16c 3688 *
e108ff2f
PB		 3689 * Steps 1-4 below provide general overview of dirty page logging. See
3690 * kvm_get_dirty_log_protect() function description for additional details.
3691 *
3692 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3693 * always flush the TLB (step 4) even if previous step failed and the dirty
3694 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3695 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3696 * writes will be marked dirty for next log read.
95d4c16c 3697 *
60c34612
TY		 3698 * 1. Take a snapshot of the bit and clear it if needed.
3699 * 2. Write protect the corresponding page.
e108ff2f
PB		 3700 * 3. Copy the snapshot to the userspace.
3701 * 4. Flush TLB's if needed.
5bb064dc 3702 */
60c34612 3703int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3704{
60c34612 3705 bool is_dirty = false;
e108ff2f 3706 int r;
5bb064dc 3707
79fac95e 3708 mutex_lock(&kvm->slots_lock);
5bb064dc 3709
88178fd4
KH		 3710 /*
3711 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3712 */
3713 if (kvm_x86_ops->flush_log_dirty)
3714 kvm_x86_ops->flush_log_dirty(kvm);
3715
e108ff2f 3716 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3717
3718 /*
3719 * All the TLBs can be flushed out of mmu lock, see the comments in
3720 * kvm_mmu_slot_remove_write_access().
3721 */
e108ff2f 3722 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3723 if (is_dirty)
3724 kvm_flush_remote_tlbs(kvm);
3725
79fac95e 3726 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3727 return r;
3728}
3729
aa2fbe6d
YZ		 3730int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3731 bool line_status)
23d43cf9
CD		 3732{
3733 if (!irqchip_in_kernel(kvm))
3734 return -ENXIO;
3735
3736 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3737 irq_event->irq, irq_event->level,
3738 line_status);
23d43cf9
CD		 3739 return 0;
3740}
3741
90de4a18
NA		 3742static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3743 struct kvm_enable_cap *cap)
3744{
3745 int r;
3746
3747 if (cap->flags)
3748 return -EINVAL;
3749
3750 switch (cap->cap) {
3751 case KVM_CAP_DISABLE_QUIRKS:
3752 kvm->arch.disabled_quirks = cap->args[0];
3753 r = 0;
3754 break;
49df6397
SR		 3755 case KVM_CAP_SPLIT_IRQCHIP: {
3756 mutex_lock(&kvm->lock);
b053b2ae
SR		 3757 r = -EINVAL;
3758 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3759 goto split_irqchip_unlock;
49df6397
SR		 3760 r = -EEXIST;
3761 if (irqchip_in_kernel(kvm))
3762 goto split_irqchip_unlock;
3763 if (atomic_read(&kvm->online_vcpus))
3764 goto split_irqchip_unlock;
3765 r = kvm_setup_empty_irq_routing(kvm);
3766 if (r)
3767 goto split_irqchip_unlock;
3768 /* Pairs with irqchip_in_kernel. */
3769 smp_wmb();
3770 kvm->arch.irqchip_split = true;
b053b2ae 3771 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3772 r = 0;
3773split_irqchip_unlock:
3774 mutex_unlock(&kvm->lock);
3775 break;
3776 }
90de4a18
NA		 3777 default:
3778 r = -EINVAL;
3779 break;
3780 }
3781 return r;
3782}
3783
1fe779f8
CO		 3784long kvm_arch_vm_ioctl(struct file *filp,
3785 unsigned int ioctl, unsigned long arg)
3786{
3787 struct kvm *kvm = filp->private_data;
3788 void __user *argp = (void __user *)arg;
367e1319 3789 int r = -ENOTTY;
f0d66275
DH		 3790 /*
3791 * This union makes it completely explicit to gcc-3.x
3792 * that these two variables' stack usage should be
3793 * combined, not added together.
3794 */
3795 union {
3796 struct kvm_pit_state ps;
e9f42757 3797 struct kvm_pit_state2 ps2;
c5ff41ce 3798 struct kvm_pit_config pit_config;
f0d66275 3799 } u;
1fe779f8
CO		 3800
3801 switch (ioctl) {
3802 case KVM_SET_TSS_ADDR:
3803 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3804 break;
b927a3ce
SY		 3805 case KVM_SET_IDENTITY_MAP_ADDR: {
3806 u64 ident_addr;
3807
3808 r = -EFAULT;
3809 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3810 goto out;
3811 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3812 break;
3813 }
1fe779f8
CO		 3814 case KVM_SET_NR_MMU_PAGES:
3815 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3816 break;
3817 case KVM_GET_NR_MMU_PAGES:
3818 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3819 break;
3ddea128
MT		 3820 case KVM_CREATE_IRQCHIP: {
3821 struct kvm_pic *vpic;
3822
3823 mutex_lock(&kvm->lock);
3824 r = -EEXIST;
3825 if (kvm->arch.vpic)
3826 goto create_irqchip_unlock;
3e515705
AK		 3827 r = -EINVAL;
3828 if (atomic_read(&kvm->online_vcpus))
3829 goto create_irqchip_unlock;
1fe779f8 3830 r = -ENOMEM;
3ddea128
MT		 3831 vpic = kvm_create_pic(kvm);
3832 if (vpic) {
1fe779f8
CO		 3833 r = kvm_ioapic_init(kvm);
3834 if (r) {
175504cd 3835 mutex_lock(&kvm->slots_lock);
71ba994c 3836 kvm_destroy_pic(vpic);
175504cd 3837 mutex_unlock(&kvm->slots_lock);
3ddea128 3838 goto create_irqchip_unlock;
1fe779f8
CO		 3839 }
3840 } else
3ddea128 3841 goto create_irqchip_unlock;
399ec807
AK		 3842 r = kvm_setup_default_irq_routing(kvm);
3843 if (r) {
175504cd 3844 mutex_lock(&kvm->slots_lock);
3ddea128 3845 mutex_lock(&kvm->irq_lock);
72bb2fcd 3846 kvm_ioapic_destroy(kvm);
71ba994c 3847 kvm_destroy_pic(vpic);
3ddea128 3848 mutex_unlock(&kvm->irq_lock);
175504cd 3849 mutex_unlock(&kvm->slots_lock);
71ba994c 3850 goto create_irqchip_unlock;
399ec807 3851 }
71ba994c
PB		 3852 /* Write kvm->irq_routing before kvm->arch.vpic. */
3853 smp_wmb();
3854 kvm->arch.vpic = vpic;
3ddea128
MT		 3855 create_irqchip_unlock:
3856 mutex_unlock(&kvm->lock);
1fe779f8 3857 break;
3ddea128 3858 }
7837699f 3859 case KVM_CREATE_PIT:
c5ff41ce
JK		 3860 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3861 goto create_pit;
3862 case KVM_CREATE_PIT2:
3863 r = -EFAULT;
3864 if (copy_from_user(&u.pit_config, argp,
3865 sizeof(struct kvm_pit_config)))
3866 goto out;
3867 create_pit:
79fac95e 3868 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3869 r = -EEXIST;
3870 if (kvm->arch.vpit)
3871 goto create_pit_unlock;
7837699f 3872 r = -ENOMEM;
c5ff41ce 3873 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3874 if (kvm->arch.vpit)
3875 r = 0;
269e05e4 3876 create_pit_unlock:
79fac95e 3877 mutex_unlock(&kvm->slots_lock);
7837699f 3878 break;
1fe779f8
CO		 3879 case KVM_GET_IRQCHIP: {
3880 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3881 struct kvm_irqchip *chip;
1fe779f8 3882
ff5c2c03
SL		 3883 chip = memdup_user(argp, sizeof(*chip));
3884 if (IS_ERR(chip)) {
3885 r = PTR_ERR(chip);
1fe779f8 3886 goto out;
ff5c2c03
SL		 3887 }
3888
1fe779f8 3889 r = -ENXIO;
49df6397 3890 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3891 goto get_irqchip_out;
3892 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3893 if (r)
f0d66275 3894 goto get_irqchip_out;
1fe779f8 3895 r = -EFAULT;
f0d66275
DH		 3896 if (copy_to_user(argp, chip, sizeof *chip))
3897 goto get_irqchip_out;
1fe779f8 3898 r = 0;
f0d66275
DH		 3899 get_irqchip_out:
3900 kfree(chip);
1fe779f8
CO		 3901 break;
3902 }
3903 case KVM_SET_IRQCHIP: {
3904 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3905 struct kvm_irqchip *chip;
1fe779f8 3906
ff5c2c03
SL		 3907 chip = memdup_user(argp, sizeof(*chip));
3908 if (IS_ERR(chip)) {
3909 r = PTR_ERR(chip);
1fe779f8 3910 goto out;
ff5c2c03
SL		 3911 }
3912
1fe779f8 3913 r = -ENXIO;
49df6397 3914 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3915 goto set_irqchip_out;
3916 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3917 if (r)
f0d66275 3918 goto set_irqchip_out;
1fe779f8 3919 r = 0;
f0d66275
DH		 3920 set_irqchip_out:
3921 kfree(chip);
1fe779f8
CO		 3922 break;
3923 }
e0f63cb9 3924 case KVM_GET_PIT: {
e0f63cb9 3925 r = -EFAULT;
f0d66275 3926 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3927 goto out;
3928 r = -ENXIO;
3929 if (!kvm->arch.vpit)
3930 goto out;
f0d66275 3931 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3932 if (r)
3933 goto out;
3934 r = -EFAULT;
f0d66275 3935 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3936 goto out;
3937 r = 0;
3938 break;
3939 }
3940 case KVM_SET_PIT: {
e0f63cb9 3941 r = -EFAULT;
f0d66275 3942 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3943 goto out;
3944 r = -ENXIO;
3945 if (!kvm->arch.vpit)
3946 goto out;
f0d66275 3947 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3948 break;
3949 }
e9f42757
BK		 3950 case KVM_GET_PIT2: {
3951 r = -ENXIO;
3952 if (!kvm->arch.vpit)
3953 goto out;
3954 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3955 if (r)
3956 goto out;
3957 r = -EFAULT;
3958 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3959 goto out;
3960 r = 0;
3961 break;
3962 }
3963 case KVM_SET_PIT2: {
3964 r = -EFAULT;
3965 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3966 goto out;
3967 r = -ENXIO;
3968 if (!kvm->arch.vpit)
3969 goto out;
3970 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3971 break;
3972 }
52d939a0
MT		 3973 case KVM_REINJECT_CONTROL: {
3974 struct kvm_reinject_control control;
3975 r = -EFAULT;
3976 if (copy_from_user(&control, argp, sizeof(control)))
3977 goto out;
3978 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3979 break;
3980 }
d71ba788
PB		 3981 case KVM_SET_BOOT_CPU_ID:
3982 r = 0;
3983 mutex_lock(&kvm->lock);
3984 if (atomic_read(&kvm->online_vcpus) != 0)
3985 r = -EBUSY;
3986 else
3987 kvm->arch.bsp_vcpu_id = arg;
3988 mutex_unlock(&kvm->lock);
3989 break;
ffde22ac
ES		 3990 case KVM_XEN_HVM_CONFIG: {
3991 r = -EFAULT;
3992 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3993 sizeof(struct kvm_xen_hvm_config)))
3994 goto out;
3995 r = -EINVAL;
3996 if (kvm->arch.xen_hvm_config.flags)
3997 goto out;
3998 r = 0;
3999 break;
4000 }
afbcf7ab 4001 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4002 struct kvm_clock_data user_ns;
4003 u64 now_ns;
4004 s64 delta;
4005
4006 r = -EFAULT;
4007 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4008 goto out;
4009
4010 r = -EINVAL;
4011 if (user_ns.flags)
4012 goto out;
4013
4014 r = 0;
395c6b0a 4015 local_irq_disable();
759379dd 4016 now_ns = get_kernel_ns();
afbcf7ab 4017 delta = user_ns.clock - now_ns;
395c6b0a 4018 local_irq_enable();
afbcf7ab 4019 kvm->arch.kvmclock_offset = delta;
2e762ff7 4020 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4021 break;
4022 }
4023 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4024 struct kvm_clock_data user_ns;
4025 u64 now_ns;
4026
395c6b0a 4027 local_irq_disable();
759379dd 4028 now_ns = get_kernel_ns();
afbcf7ab 4029 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4030 local_irq_enable();
afbcf7ab 4031 user_ns.flags = 0;
97e69aa6 4032 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4033
4034 r = -EFAULT;
4035 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4036 goto out;
4037 r = 0;
4038 break;
4039 }
90de4a18
NA		 4040 case KVM_ENABLE_CAP: {
4041 struct kvm_enable_cap cap;
afbcf7ab 4042
90de4a18
NA		 4043 r = -EFAULT;
4044 if (copy_from_user(&cap, argp, sizeof(cap)))
4045 goto out;
4046 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4047 break;
4048 }
1fe779f8 4049 default:
c274e03a 4050 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4051 }
4052out:
4053 return r;
4054}
4055
a16b043c 4056static void kvm_init_msr_list(void)
043405e1
CO		 4057{
4058 u32 dummy[2];
4059 unsigned i, j;
4060
62ef68bb 4061 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4062 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4063 continue;
93c4adc7
PB		 4064
4065 /*
4066 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4067 * to the guests in some cases.
93c4adc7
PB		 4068 */
4069 switch (msrs_to_save[i]) {
4070 case MSR_IA32_BNDCFGS:
4071 if (!kvm_x86_ops->mpx_supported())
4072 continue;
4073 break;
9dbe6cf9
PB		 4074 case MSR_TSC_AUX:
4075 if (!kvm_x86_ops->rdtscp_supported())
4076 continue;
4077 break;
93c4adc7
PB		 4078 default:
4079 break;
4080 }
4081
043405e1
CO		 4082 if (j < i)
4083 msrs_to_save[j] = msrs_to_save[i];
4084 j++;
4085 }
4086 num_msrs_to_save = j;
62ef68bb
PB		 4087
4088 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4089 switch (emulated_msrs[i]) {
6d396b55
PB		 4090 case MSR_IA32_SMBASE:
4091 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4092 continue;
4093 break;
62ef68bb
PB		 4094 default:
4095 break;
4096 }
4097
4098 if (j < i)
4099 emulated_msrs[j] = emulated_msrs[i];
4100 j++;
4101 }
4102 num_emulated_msrs = j;
043405e1
CO		 4103}
4104
bda9020e
MT		 4105static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4106 const void *v)
bbd9b64e 4107{
70252a10
AK		 4108 int handled = 0;
4109 int n;
4110
4111 do {
4112 n = min(len, 8);
bce87cce 4113 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4114 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4115 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4116 break;
4117 handled += n;
4118 addr += n;
4119 len -= n;
4120 v += n;
4121 } while (len);
bbd9b64e 4122
70252a10 4123 return handled;
bbd9b64e
CO		 4124}
4125
bda9020e 4126static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4127{
70252a10
AK		 4128 int handled = 0;
4129 int n;
4130
4131 do {
4132 n = min(len, 8);
bce87cce 4133 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4134 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4135 addr, n, v))
4136 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4137 break;
4138 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4139 handled += n;
4140 addr += n;
4141 len -= n;
4142 v += n;
4143 } while (len);
bbd9b64e 4144
70252a10 4145 return handled;
bbd9b64e
CO		 4146}
4147
2dafc6c2
GN		 4148static void kvm_set_segment(struct kvm_vcpu *vcpu,
4149 struct kvm_segment *var, int seg)
4150{
4151 kvm_x86_ops->set_segment(vcpu, var, seg);
4152}
4153
4154void kvm_get_segment(struct kvm_vcpu *vcpu,
4155 struct kvm_segment *var, int seg)
4156{
4157 kvm_x86_ops->get_segment(vcpu, var, seg);
4158}
4159
54987b7a
PB		 4160gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4161 struct x86_exception *exception)
02f59dc9
JR		 4162{
4163 gpa_t t_gpa;
02f59dc9
JR		 4164
4165 BUG_ON(!mmu_is_nested(vcpu));
4166
4167 /* NPT walks are always user-walks */
4168 access |= PFERR_USER_MASK;
54987b7a 4169 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4170
4171 return t_gpa;
4172}
4173
ab9ae313
AK		 4174gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4175 struct x86_exception *exception)
1871c602
GN		 4176{
4177 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4178 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4179}
4180
ab9ae313
AK		 4181 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4182 struct x86_exception *exception)
1871c602
GN		 4183{
4184 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4185 access |= PFERR_FETCH_MASK;
ab9ae313 4186 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4187}
4188
ab9ae313
AK		 4189gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4190 struct x86_exception *exception)
1871c602
GN		 4191{
4192 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4193 access |= PFERR_WRITE_MASK;
ab9ae313 4194 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4195}
4196
4197/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4198gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4199 struct x86_exception *exception)
1871c602 4200{
ab9ae313 4201 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4202}
4203
4204static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4205 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4206 struct x86_exception *exception)
bbd9b64e
CO		 4207{
4208 void *data = val;
10589a46 4209 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4210
4211 while (bytes) {
14dfe855 4212 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4213 exception);
bbd9b64e 4214 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4215 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4216 int ret;
4217
bcc55cba 4218 if (gpa == UNMAPPED_GVA)
ab9ae313 4219 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4220 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4221 offset, toread);
10589a46 4222 if (ret < 0) {
c3cd7ffa 4223 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4224 goto out;
4225 }
bbd9b64e 4226
77c2002e
IE		 4227 bytes -= toread;
4228 data += toread;
4229 addr += toread;
bbd9b64e 4230 }
10589a46 4231out:
10589a46 4232 return r;
bbd9b64e 4233}
77c2002e 4234
1871c602 4235/* used for instruction fetching */
0f65dd70
AK		 4236static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4237 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4238 struct x86_exception *exception)
1871c602 4239{
0f65dd70 4240 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4241 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4242 unsigned offset;
4243 int ret;
0f65dd70 4244
44583cba
PB		 4245 /* Inline kvm_read_guest_virt_helper for speed. */
4246 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4247 exception);
4248 if (unlikely(gpa == UNMAPPED_GVA))
4249 return X86EMUL_PROPAGATE_FAULT;
4250
4251 offset = addr & (PAGE_SIZE-1);
4252 if (WARN_ON(offset + bytes > PAGE_SIZE))
4253 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4254 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4255 offset, bytes);
44583cba
PB		 4256 if (unlikely(ret < 0))
4257 return X86EMUL_IO_NEEDED;
4258
4259 return X86EMUL_CONTINUE;
1871c602
GN		 4260}
4261
064aea77 4262int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4263 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4264 struct x86_exception *exception)
1871c602 4265{
0f65dd70 4266 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4267 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4268
1871c602 4269 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4270 exception);
1871c602 4271}
064aea77 4272EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4273
0f65dd70
AK		 4274static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4275 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4276 struct x86_exception *exception)
1871c602 4277{
0f65dd70 4278 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4279 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4280}
4281
7a036a6f
RK		 4282static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4283 unsigned long addr, void *val, unsigned int bytes)
4284{
4285 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4286 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4287
4288 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4289}
4290
6a4d7550 4291int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4292 gva_t addr, void *val,
2dafc6c2 4293 unsigned int bytes,
bcc55cba 4294 struct x86_exception *exception)
77c2002e 4295{
0f65dd70 4296 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4297 void *data = val;
4298 int r = X86EMUL_CONTINUE;
4299
4300 while (bytes) {
14dfe855
JR		 4301 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4302 PFERR_WRITE_MASK,
ab9ae313 4303 exception);
77c2002e
IE		 4304 unsigned offset = addr & (PAGE_SIZE-1);
4305 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4306 int ret;
4307
bcc55cba 4308 if (gpa == UNMAPPED_GVA)
ab9ae313 4309 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4310 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4311 if (ret < 0) {
c3cd7ffa 4312 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4313 goto out;
4314 }
4315
4316 bytes -= towrite;
4317 data += towrite;
4318 addr += towrite;
4319 }
4320out:
4321 return r;
4322}
6a4d7550 4323EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4324
af7cc7d1
XG		 4325static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4326 gpa_t *gpa, struct x86_exception *exception,
4327 bool write)
4328{
97d64b78
AK		 4329 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4330 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4331
be94f6b7
HH		 4332 /*
4333 * currently PKRU is only applied to ept enabled guest so
4334 * there is no pkey in EPT page table for L1 guest or EPT
4335 * shadow page table for L2 guest.
4336 */
97d64b78 4337 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4338 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4339 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4340 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4341 (gva & (PAGE_SIZE - 1));
4f022648 4342 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4343 return 1;
4344 }
4345
af7cc7d1
XG		 4346 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4347
4348 if (*gpa == UNMAPPED_GVA)
4349 return -1;
4350
4351 /* For APIC access vmexit */
4352 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4353 return 1;
4354
4f022648
XG		 4355 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4356 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4357 return 1;
4f022648 4358 }
bebb106a 4359
af7cc7d1
XG		 4360 return 0;
4361}
4362
3200f405 4363int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4364 const void *val, int bytes)
bbd9b64e
CO		 4365{
4366 int ret;
4367
54bf36aa 4368 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4369 if (ret < 0)
bbd9b64e 4370 return 0;
0eb05bf2 4371 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4372 return 1;
4373}
4374
77d197b2
XG		 4375struct read_write_emulator_ops {
4376 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4377 int bytes);
4378 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4379 void *val, int bytes);
4380 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4381 int bytes, void *val);
4382 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4383 void *val, int bytes);
4384 bool write;
4385};
4386
4387static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4388{
4389 if (vcpu->mmio_read_completed) {
77d197b2 4390 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4391 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4392 vcpu->mmio_read_completed = 0;
4393 return 1;
4394 }
4395
4396 return 0;
4397}
4398
4399static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4400 void *val, int bytes)
4401{
54bf36aa 4402 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4403}
4404
4405static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4406 void *val, int bytes)
4407{
4408 return emulator_write_phys(vcpu, gpa, val, bytes);
4409}
4410
4411static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4412{
4413 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4414 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4415}
4416
4417static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4418 void *val, int bytes)
4419{
4420 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4421 return X86EMUL_IO_NEEDED;
4422}
4423
4424static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4425 void *val, int bytes)
4426{
f78146b0
AK		 4427 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4428
87da7e66 4429 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4430 return X86EMUL_CONTINUE;
4431}
4432
0fbe9b0b 4433static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4434 .read_write_prepare = read_prepare,
4435 .read_write_emulate = read_emulate,
4436 .read_write_mmio = vcpu_mmio_read,
4437 .read_write_exit_mmio = read_exit_mmio,
4438};
4439
0fbe9b0b 4440static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4441 .read_write_emulate = write_emulate,
4442 .read_write_mmio = write_mmio,
4443 .read_write_exit_mmio = write_exit_mmio,
4444 .write = true,
4445};
4446
22388a3c
XG		 4447static int emulator_read_write_onepage(unsigned long addr, void *val,
4448 unsigned int bytes,
4449 struct x86_exception *exception,
4450 struct kvm_vcpu *vcpu,
0fbe9b0b 4451 const struct read_write_emulator_ops *ops)
bbd9b64e 4452{
af7cc7d1
XG		 4453 gpa_t gpa;
4454 int handled, ret;
22388a3c 4455 bool write = ops->write;
f78146b0 4456 struct kvm_mmio_fragment *frag;
10589a46 4457
22388a3c 4458 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4459
af7cc7d1 4460 if (ret < 0)
bbd9b64e 4461 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4462
4463 /* For APIC access vmexit */
af7cc7d1 4464 if (ret)
bbd9b64e
CO		 4465 goto mmio;
4466
22388a3c 4467 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4468 return X86EMUL_CONTINUE;
4469
4470mmio:
4471 /*
4472 * Is this MMIO handled locally?
4473 */
22388a3c 4474 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4475 if (handled == bytes)
bbd9b64e 4476 return X86EMUL_CONTINUE;
bbd9b64e 4477
70252a10
AK		 4478 gpa += handled;
4479 bytes -= handled;
4480 val += handled;
4481
87da7e66
XG		 4482 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4483 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4484 frag->gpa = gpa;
4485 frag->data = val;
4486 frag->len = bytes;
f78146b0 4487 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4488}
4489
52eb5a6d
XL		 4490static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4491 unsigned long addr,
22388a3c
XG		 4492 void *val, unsigned int bytes,
4493 struct x86_exception *exception,
0fbe9b0b 4494 const struct read_write_emulator_ops *ops)
bbd9b64e 4495{
0f65dd70 4496 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4497 gpa_t gpa;
4498 int rc;
4499
4500 if (ops->read_write_prepare &&
4501 ops->read_write_prepare(vcpu, val, bytes))
4502 return X86EMUL_CONTINUE;
4503
4504 vcpu->mmio_nr_fragments = 0;
0f65dd70 4505
bbd9b64e
CO		 4506 /* Crossing a page boundary? */
4507 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4508 int now;
bbd9b64e
CO		 4509
4510 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4511 rc = emulator_read_write_onepage(addr, val, now, exception,
4512 vcpu, ops);
4513
bbd9b64e
CO		 4514 if (rc != X86EMUL_CONTINUE)
4515 return rc;
4516 addr += now;
bac15531
NA		 4517 if (ctxt->mode != X86EMUL_MODE_PROT64)
4518 addr = (u32)addr;
bbd9b64e
CO		 4519 val += now;
4520 bytes -= now;
4521 }
22388a3c 4522
f78146b0
AK		 4523 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4524 vcpu, ops);
4525 if (rc != X86EMUL_CONTINUE)
4526 return rc;
4527
4528 if (!vcpu->mmio_nr_fragments)
4529 return rc;
4530
4531 gpa = vcpu->mmio_fragments[0].gpa;
4532
4533 vcpu->mmio_needed = 1;
4534 vcpu->mmio_cur_fragment = 0;
4535
87da7e66 4536 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4537 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4538 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4539 vcpu->run->mmio.phys_addr = gpa;
4540
4541 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4542}
4543
4544static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4545 unsigned long addr,
4546 void *val,
4547 unsigned int bytes,
4548 struct x86_exception *exception)
4549{
4550 return emulator_read_write(ctxt, addr, val, bytes,
4551 exception, &read_emultor);
4552}
4553
52eb5a6d 4554static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4555 unsigned long addr,
4556 const void *val,
4557 unsigned int bytes,
4558 struct x86_exception *exception)
4559{
4560 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4561 exception, &write_emultor);
bbd9b64e 4562}
bbd9b64e 4563
daea3e73
AK		 4564#define CMPXCHG_TYPE(t, ptr, old, new) \
4565 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4566
4567#ifdef CONFIG_X86_64
4568# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4569#else
4570# define CMPXCHG64(ptr, old, new) \
9749a6c0 4571 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4572#endif
4573
0f65dd70
AK		 4574static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4575 unsigned long addr,
bbd9b64e
CO		 4576 const void *old,
4577 const void *new,
4578 unsigned int bytes,
0f65dd70 4579 struct x86_exception *exception)
bbd9b64e 4580{
0f65dd70 4581 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4582 gpa_t gpa;
4583 struct page *page;
4584 char *kaddr;
4585 bool exchanged;
2bacc55c 4586
daea3e73
AK		 4587 /* guests cmpxchg8b have to be emulated atomically */
4588 if (bytes > 8 || (bytes & (bytes - 1)))
4589 goto emul_write;
10589a46 4590
daea3e73 4591 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4592
daea3e73
AK		 4593 if (gpa == UNMAPPED_GVA ||
4594 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4595 goto emul_write;
2bacc55c 4596
daea3e73
AK		 4597 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4598 goto emul_write;
72dc67a6 4599
54bf36aa 4600 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4601 if (is_error_page(page))
c19b8bd6 4602 goto emul_write;
72dc67a6 4603
8fd75e12 4604 kaddr = kmap_atomic(page);
daea3e73
AK		 4605 kaddr += offset_in_page(gpa);
4606 switch (bytes) {
4607 case 1:
4608 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4609 break;
4610 case 2:
4611 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4612 break;
4613 case 4:
4614 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4615 break;
4616 case 8:
4617 exchanged = CMPXCHG64(kaddr, old, new);
4618 break;
4619 default:
4620 BUG();
2bacc55c 4621 }
8fd75e12 4622 kunmap_atomic(kaddr);
daea3e73
AK		 4623 kvm_release_page_dirty(page);
4624
4625 if (!exchanged)
4626 return X86EMUL_CMPXCHG_FAILED;
4627
54bf36aa 4628 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4629 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4630
4631 return X86EMUL_CONTINUE;
4a5f48f6 4632
3200f405 4633emul_write:
daea3e73 4634 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4635
0f65dd70 4636 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4637}
4638
cf8f70bf
GN		 4639static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4640{
4641 /* TODO: String I/O for in kernel device */
4642 int r;
4643
4644 if (vcpu->arch.pio.in)
e32edf4f 4645 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4646 vcpu->arch.pio.size, pd);
4647 else
e32edf4f 4648 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4649 vcpu->arch.pio.port, vcpu->arch.pio.size,
4650 pd);
4651 return r;
4652}
4653
6f6fbe98
XG		 4654static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4655 unsigned short port, void *val,
4656 unsigned int count, bool in)
cf8f70bf 4657{
cf8f70bf 4658 vcpu->arch.pio.port = port;
6f6fbe98 4659 vcpu->arch.pio.in = in;
7972995b 4660 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4661 vcpu->arch.pio.size = size;
4662
4663 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4664 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4665 return 1;
4666 }
4667
4668 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4669 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4670 vcpu->run->io.size = size;
4671 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4672 vcpu->run->io.count = count;
4673 vcpu->run->io.port = port;
4674
4675 return 0;
4676}
4677
6f6fbe98
XG		 4678static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4679 int size, unsigned short port, void *val,
4680 unsigned int count)
cf8f70bf 4681{
ca1d4a9e 4682 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4683 int ret;
ca1d4a9e 4684
6f6fbe98
XG		 4685 if (vcpu->arch.pio.count)
4686 goto data_avail;
cf8f70bf 4687
6f6fbe98
XG		 4688 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4689 if (ret) {
4690data_avail:
4691 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4692 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4693 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4694 return 1;
4695 }
4696
cf8f70bf
GN		 4697 return 0;
4698}
4699
6f6fbe98
XG		 4700static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4701 int size, unsigned short port,
4702 const void *val, unsigned int count)
4703{
4704 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4705
4706 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4707 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4708 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4709}
4710
bbd9b64e
CO		 4711static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4712{
4713 return kvm_x86_ops->get_segment_base(vcpu, seg);
4714}
4715
3cb16fe7 4716static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4717{
3cb16fe7 4718 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4719}
4720
5cb56059 4721int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4722{
4723 if (!need_emulate_wbinvd(vcpu))
4724 return X86EMUL_CONTINUE;
4725
4726 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4727 int cpu = get_cpu();
4728
4729 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4730 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4731 wbinvd_ipi, NULL, 1);
2eec7343 4732 put_cpu();
f5f48ee1 4733 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4734 } else
4735 wbinvd();
f5f48ee1
SY		 4736 return X86EMUL_CONTINUE;
4737}
5cb56059
JS		 4738
4739int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4740{
4741 kvm_x86_ops->skip_emulated_instruction(vcpu);
4742 return kvm_emulate_wbinvd_noskip(vcpu);
4743}
f5f48ee1
SY		 4744EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4745
5cb56059
JS		 4746
4747
bcaf5cc5
AK		 4748static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4749{
5cb56059 4750 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4751}
4752
52eb5a6d
XL		 4753static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4754 unsigned long *dest)
bbd9b64e 4755{
16f8a6f9 4756 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4757}
4758
52eb5a6d
XL		 4759static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4760 unsigned long value)
bbd9b64e 4761{
338dbc97 4762
717746e3 4763 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4764}
4765
52a46617 4766static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4767{
52a46617 4768 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4769}
4770
717746e3 4771static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4772{
717746e3 4773 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4774 unsigned long value;
4775
4776 switch (cr) {
4777 case 0:
4778 value = kvm_read_cr0(vcpu);
4779 break;
4780 case 2:
4781 value = vcpu->arch.cr2;
4782 break;
4783 case 3:
9f8fe504 4784 value = kvm_read_cr3(vcpu);
52a46617
GN		 4785 break;
4786 case 4:
4787 value = kvm_read_cr4(vcpu);
4788 break;
4789 case 8:
4790 value = kvm_get_cr8(vcpu);
4791 break;
4792 default:
a737f256 4793 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4794 return 0;
4795 }
4796
4797 return value;
4798}
4799
717746e3 4800static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4801{
717746e3 4802 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4803 int res = 0;
4804
52a46617
GN		 4805 switch (cr) {
4806 case 0:
49a9b07e 4807 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4808 break;
4809 case 2:
4810 vcpu->arch.cr2 = val;
4811 break;
4812 case 3:
2390218b 4813 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4814 break;
4815 case 4:
a83b29c6 4816 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4817 break;
4818 case 8:
eea1cff9 4819 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4820 break;
4821 default:
a737f256 4822 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4823 res = -1;
52a46617 4824 }
0f12244f
GN		 4825
4826 return res;
52a46617
GN		 4827}
4828
717746e3 4829static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4830{
717746e3 4831 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4832}
4833
4bff1e86 4834static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4835{
4bff1e86 4836 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4837}
4838
4bff1e86 4839static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4840{
4bff1e86 4841 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4842}
4843
1ac9d0cf
AK		 4844static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4845{
4846 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4847}
4848
4849static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4850{
4851 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4852}
4853
4bff1e86
AK		 4854static unsigned long emulator_get_cached_segment_base(
4855 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4856{
4bff1e86 4857 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4858}
4859
1aa36616
AK		 4860static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4861 struct desc_struct *desc, u32 *base3,
4862 int seg)
2dafc6c2
GN		 4863{
4864 struct kvm_segment var;
4865
4bff1e86 4866 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4867 *selector = var.selector;
2dafc6c2 4868
378a8b09
GN		 4869 if (var.unusable) {
4870 memset(desc, 0, sizeof(*desc));
2dafc6c2 4871 return false;
378a8b09 4872 }
2dafc6c2
GN		 4873
4874 if (var.g)
4875 var.limit >>= 12;
4876 set_desc_limit(desc, var.limit);
4877 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4878#ifdef CONFIG_X86_64
4879 if (base3)
4880 *base3 = var.base >> 32;
4881#endif
2dafc6c2
GN		 4882 desc->type = var.type;
4883 desc->s = var.s;
4884 desc->dpl = var.dpl;
4885 desc->p = var.present;
4886 desc->avl = var.avl;
4887 desc->l = var.l;
4888 desc->d = var.db;
4889 desc->g = var.g;
4890
4891 return true;
4892}
4893
1aa36616
AK		 4894static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4895 struct desc_struct *desc, u32 base3,
4896 int seg)
2dafc6c2 4897{
4bff1e86 4898 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4899 struct kvm_segment var;
4900
1aa36616 4901 var.selector = selector;
2dafc6c2 4902 var.base = get_desc_base(desc);
5601d05b
GN		 4903#ifdef CONFIG_X86_64
4904 var.base |= ((u64)base3) << 32;
4905#endif
2dafc6c2
GN		 4906 var.limit = get_desc_limit(desc);
4907 if (desc->g)
4908 var.limit = (var.limit << 12) | 0xfff;
4909 var.type = desc->type;
2dafc6c2
GN		 4910 var.dpl = desc->dpl;
4911 var.db = desc->d;
4912 var.s = desc->s;
4913 var.l = desc->l;
4914 var.g = desc->g;
4915 var.avl = desc->avl;
4916 var.present = desc->p;
4917 var.unusable = !var.present;
4918 var.padding = 0;
4919
4920 kvm_set_segment(vcpu, &var, seg);
4921 return;
4922}
4923
717746e3
AK		 4924static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4925 u32 msr_index, u64 *pdata)
4926{
609e36d3
PB		 4927 struct msr_data msr;
4928 int r;
4929
4930 msr.index = msr_index;
4931 msr.host_initiated = false;
4932 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4933 if (r)
4934 return r;
4935
4936 *pdata = msr.data;
4937 return 0;
717746e3
AK		 4938}
4939
4940static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4941 u32 msr_index, u64 data)
4942{
8fe8ab46
WA		 4943 struct msr_data msr;
4944
4945 msr.data = data;
4946 msr.index = msr_index;
4947 msr.host_initiated = false;
4948 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4949}
4950
64d60670
PB		 4951static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4952{
4953 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4954
4955 return vcpu->arch.smbase;
4956}
4957
4958static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4959{
4960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4961
4962 vcpu->arch.smbase = smbase;
4963}
4964
67f4d428
NA		 4965static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4966 u32 pmc)
4967{
c6702c9d 4968 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4969}
4970
222d21aa
AK		 4971static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4972 u32 pmc, u64 *pdata)
4973{
c6702c9d 4974 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4975}
4976
6c3287f7
AK		 4977static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4978{
4979 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4980}
4981
5037f6f3
AK		 4982static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4983{
4984 preempt_disable();
5197b808 4985 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4986 /*
4987 * CR0.TS may reference the host fpu state, not the guest fpu state,
4988 * so it may be clear at this point.
4989 */
4990 clts();
4991}
4992
4993static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4994{
4995 preempt_enable();
4996}
4997
2953538e 4998static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4999 struct x86_instruction_info *info,
c4f035c6
AK		 5000 enum x86_intercept_stage stage)
5001{
2953538e 5002 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5003}
5004
0017f93a 5005static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5006 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5007{
0017f93a 5008 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5009}
5010
dd856efa
AK		 5011static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5012{
5013 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5014}
5015
5016static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5017{
5018 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5019}
5020
801806d9
NA		 5021static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5022{
5023 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5024}
5025
0225fb50 5026static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5027 .read_gpr = emulator_read_gpr,
5028 .write_gpr = emulator_write_gpr,
1871c602 5029 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5030 .write_std = kvm_write_guest_virt_system,
7a036a6f 5031 .read_phys = kvm_read_guest_phys_system,
1871c602 5032 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5033 .read_emulated = emulator_read_emulated,
5034 .write_emulated = emulator_write_emulated,
5035 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5036 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5037 .pio_in_emulated = emulator_pio_in_emulated,
5038 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5039 .get_segment = emulator_get_segment,
5040 .set_segment = emulator_set_segment,
5951c442 5041 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5042 .get_gdt = emulator_get_gdt,
160ce1f1 5043 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5044 .set_gdt = emulator_set_gdt,
5045 .set_idt = emulator_set_idt,
52a46617
GN		 5046 .get_cr = emulator_get_cr,
5047 .set_cr = emulator_set_cr,
9c537244 5048 .cpl = emulator_get_cpl,
35aa5375
GN		 5049 .get_dr = emulator_get_dr,
5050 .set_dr = emulator_set_dr,
64d60670
PB		 5051 .get_smbase = emulator_get_smbase,
5052 .set_smbase = emulator_set_smbase,
717746e3
AK		 5053 .set_msr = emulator_set_msr,
5054 .get_msr = emulator_get_msr,
67f4d428 5055 .check_pmc = emulator_check_pmc,
222d21aa 5056 .read_pmc = emulator_read_pmc,
6c3287f7 5057 .halt = emulator_halt,
bcaf5cc5 5058 .wbinvd = emulator_wbinvd,
d6aa1000 5059 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5060 .get_fpu = emulator_get_fpu,
5061 .put_fpu = emulator_put_fpu,
c4f035c6 5062 .intercept = emulator_intercept,
bdb42f5a 5063 .get_cpuid = emulator_get_cpuid,
801806d9 5064 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5065};
5066
95cb2295
GN		 5067static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5068{
37ccdcbe 5069 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5070 /*
5071 * an sti; sti; sequence only disable interrupts for the first
5072 * instruction. So, if the last instruction, be it emulated or
5073 * not, left the system with the INT_STI flag enabled, it
5074 * means that the last instruction is an sti. We should not
5075 * leave the flag on in this case. The same goes for mov ss
5076 */
37ccdcbe
PB		 5077 if (int_shadow & mask)
5078 mask = 0;
6addfc42 5079 if (unlikely(int_shadow || mask)) {
95cb2295 5080 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5081 if (!mask)
5082 kvm_make_request(KVM_REQ_EVENT, vcpu);
5083 }
95cb2295
GN		 5084}
5085
ef54bcfe 5086static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5087{
5088 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5089 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5090 return kvm_propagate_fault(vcpu, &ctxt->exception);
5091
5092 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5093 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5094 ctxt->exception.error_code);
54b8486f 5095 else
da9cb575 5096 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5097 return false;
54b8486f
GN		 5098}
5099
8ec4722d
MG		 5100static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5101{
adf52235 5102 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5103 int cs_db, cs_l;
5104
8ec4722d
MG		 5105 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5106
adf52235
TY		 5107 ctxt->eflags = kvm_get_rflags(vcpu);
5108 ctxt->eip = kvm_rip_read(vcpu);
5109 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5110 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5111 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5112 cs_db ? X86EMUL_MODE_PROT32 :
5113 X86EMUL_MODE_PROT16;
a584539b 5114 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5115 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5116 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5117 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5118
dd856efa 5119 init_decode_cache(ctxt);
7ae441ea 5120 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5121}
5122
71f9833b 5123int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5124{
9d74191a 5125 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5126 int ret;
5127
5128 init_emulate_ctxt(vcpu);
5129
9dac77fa
AK		 5130 ctxt->op_bytes = 2;
5131 ctxt->ad_bytes = 2;
5132 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5133 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5134
5135 if (ret != X86EMUL_CONTINUE)
5136 return EMULATE_FAIL;
5137
9dac77fa 5138 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5139 kvm_rip_write(vcpu, ctxt->eip);
5140 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5141
5142 if (irq == NMI_VECTOR)
7460fb4a 5143 vcpu->arch.nmi_pending = 0;
63995653
MG		 5144 else
5145 vcpu->arch.interrupt.pending = false;
5146
5147 return EMULATE_DONE;
5148}
5149EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5150
6d77dbfc
GN		 5151static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5152{
fc3a9157
JR		 5153 int r = EMULATE_DONE;
5154
6d77dbfc
GN		 5155 ++vcpu->stat.insn_emulation_fail;
5156 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5157 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5158 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5159 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5160 vcpu->run->internal.ndata = 0;
5161 r = EMULATE_FAIL;
5162 }
6d77dbfc 5163 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5164
5165 return r;
6d77dbfc
GN		 5166}
5167
93c05d3e 5168static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5169 bool write_fault_to_shadow_pgtable,
5170 int emulation_type)
a6f177ef 5171{
95b3cf69 5172 gpa_t gpa = cr2;
ba049e93 5173 kvm_pfn_t pfn;
a6f177ef 5174
991eebf9
GN		 5175 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5176 return false;
5177
95b3cf69
XG		 5178 if (!vcpu->arch.mmu.direct_map) {
5179 /*
5180 * Write permission should be allowed since only
5181 * write access need to be emulated.
5182 */
5183 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5184
95b3cf69
XG		 5185 /*
5186 * If the mapping is invalid in guest, let cpu retry
5187 * it to generate fault.
5188 */
5189 if (gpa == UNMAPPED_GVA)
5190 return true;
5191 }
a6f177ef 5192
8e3d9d06
XG		 5193 /*
5194 * Do not retry the unhandleable instruction if it faults on the
5195 * readonly host memory, otherwise it will goto a infinite loop:
5196 * retry instruction -> write #PF -> emulation fail -> retry
5197 * instruction -> ...
5198 */
5199 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5200
5201 /*
5202 * If the instruction failed on the error pfn, it can not be fixed,
5203 * report the error to userspace.
5204 */
5205 if (is_error_noslot_pfn(pfn))
5206 return false;
5207
5208 kvm_release_pfn_clean(pfn);
5209
5210 /* The instructions are well-emulated on direct mmu. */
5211 if (vcpu->arch.mmu.direct_map) {
5212 unsigned int indirect_shadow_pages;
5213
5214 spin_lock(&vcpu->kvm->mmu_lock);
5215 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5216 spin_unlock(&vcpu->kvm->mmu_lock);
5217
5218 if (indirect_shadow_pages)
5219 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5220
a6f177ef 5221 return true;
8e3d9d06 5222 }
a6f177ef 5223
95b3cf69
XG		 5224 /*
5225 * if emulation was due to access to shadowed page table
5226 * and it failed try to unshadow page and re-enter the
5227 * guest to let CPU execute the instruction.
5228 */
5229 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5230
5231 /*
5232 * If the access faults on its page table, it can not
5233 * be fixed by unprotecting shadow page and it should
5234 * be reported to userspace.
5235 */
5236 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5237}
5238
1cb3f3ae
XG		 5239static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5240 unsigned long cr2, int emulation_type)
5241{
5242 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5243 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5244
5245 last_retry_eip = vcpu->arch.last_retry_eip;
5246 last_retry_addr = vcpu->arch.last_retry_addr;
5247
5248 /*
5249 * If the emulation is caused by #PF and it is non-page_table
5250 * writing instruction, it means the VM-EXIT is caused by shadow
5251 * page protected, we can zap the shadow page and retry this
5252 * instruction directly.
5253 *
5254 * Note: if the guest uses a non-page-table modifying instruction
5255 * on the PDE that points to the instruction, then we will unmap
5256 * the instruction and go to an infinite loop. So, we cache the
5257 * last retried eip and the last fault address, if we meet the eip
5258 * and the address again, we can break out of the potential infinite
5259 * loop.
5260 */
5261 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5262
5263 if (!(emulation_type & EMULTYPE_RETRY))
5264 return false;
5265
5266 if (x86_page_table_writing_insn(ctxt))
5267 return false;
5268
5269 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5270 return false;
5271
5272 vcpu->arch.last_retry_eip = ctxt->eip;
5273 vcpu->arch.last_retry_addr = cr2;
5274
5275 if (!vcpu->arch.mmu.direct_map)
5276 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5277
22368028 5278 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5279
5280 return true;
5281}
5282
716d51ab
GN		 5283static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5284static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5285
64d60670 5286static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5287{
64d60670 5288 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5289 /* This is a good place to trace that we are exiting SMM. */
5290 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5291
64d60670
PB		 5292 if (unlikely(vcpu->arch.smi_pending)) {
5293 kvm_make_request(KVM_REQ_SMI, vcpu);
5294 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5295 } else {
5296 /* Process a latched INIT, if any. */
5297 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5298 }
5299 }
699023e2
PB		 5300
5301 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5302}
5303
5304static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5305{
5306 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5307
a584539b 5308 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5309
5310 if (changed & HF_SMM_MASK)
5311 kvm_smm_changed(vcpu);
a584539b
PB		 5312}
5313
4a1e10d5
PB		 5314static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5315 unsigned long *db)
5316{
5317 u32 dr6 = 0;
5318 int i;
5319 u32 enable, rwlen;
5320
5321 enable = dr7;
5322 rwlen = dr7 >> 16;
5323 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5324 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5325 dr6 |= (1 << i);
5326 return dr6;
5327}
5328
6addfc42 5329static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5330{
5331 struct kvm_run *kvm_run = vcpu->run;
5332
5333 /*
6addfc42
PB		 5334 * rflags is the old, "raw" value of the flags. The new value has
5335 * not been saved yet.
663f4c61
PB		 5336 *
5337 * This is correct even for TF set by the guest, because "the
5338 * processor will not generate this exception after the instruction
5339 * that sets the TF flag".
5340 */
663f4c61
PB		 5341 if (unlikely(rflags & X86_EFLAGS_TF)) {
5342 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5343 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5344 DR6_RTM;
663f4c61
PB		 5345 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5346 kvm_run->debug.arch.exception = DB_VECTOR;
5347 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5348 *r = EMULATE_USER_EXIT;
5349 } else {
5350 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5351 /*
5352 * "Certain debug exceptions may clear bit 0-3. The
5353 * remaining contents of the DR6 register are never
5354 * cleared by the processor".
5355 */
5356 vcpu->arch.dr6 &= ~15;
6f43ed01 5357 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5358 kvm_queue_exception(vcpu, DB_VECTOR);
5359 }
5360 }
5361}
5362
4a1e10d5
PB		 5363static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5364{
4a1e10d5
PB		 5365 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5366 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5367 struct kvm_run *kvm_run = vcpu->run;
5368 unsigned long eip = kvm_get_linear_rip(vcpu);
5369 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5370 vcpu->arch.guest_debug_dr7,
5371 vcpu->arch.eff_db);
5372
5373 if (dr6 != 0) {
6f43ed01 5374 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5375 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5376 kvm_run->debug.arch.exception = DB_VECTOR;
5377 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5378 *r = EMULATE_USER_EXIT;
5379 return true;
5380 }
5381 }
5382
4161a569
NA		 5383 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5384 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5385 unsigned long eip = kvm_get_linear_rip(vcpu);
5386 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5387 vcpu->arch.dr7,
5388 vcpu->arch.db);
5389
5390 if (dr6 != 0) {
5391 vcpu->arch.dr6 &= ~15;
6f43ed01 5392 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5393 kvm_queue_exception(vcpu, DB_VECTOR);
5394 *r = EMULATE_DONE;
5395 return true;
5396 }
5397 }
5398
5399 return false;
5400}
5401
51d8b661
AP		 5402int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5403 unsigned long cr2,
dc25e89e
AP		 5404 int emulation_type,
5405 void *insn,
5406 int insn_len)
bbd9b64e 5407{
95cb2295 5408 int r;
9d74191a 5409 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5410 bool writeback = true;
93c05d3e 5411 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5412
93c05d3e
XG		 5413 /*
5414 * Clear write_fault_to_shadow_pgtable here to ensure it is
5415 * never reused.
5416 */
5417 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5418 kvm_clear_exception_queue(vcpu);
8d7d8102 5419
571008da 5420 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5421 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5422
5423 /*
5424 * We will reenter on the same instruction since
5425 * we do not set complete_userspace_io. This does not
5426 * handle watchpoints yet, those would be handled in
5427 * the emulate_ops.
5428 */
5429 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5430 return r;
5431
9d74191a
TY		 5432 ctxt->interruptibility = 0;
5433 ctxt->have_exception = false;
e0ad0b47 5434 ctxt->exception.vector = -1;
9d74191a 5435 ctxt->perm_ok = false;
bbd9b64e 5436
b51e974f 5437 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5438
9d74191a 5439 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5440
e46479f8 5441 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5442 ++vcpu->stat.insn_emulation;
1d2887e2 5443 if (r != EMULATION_OK) {
4005996e
AK		 5444 if (emulation_type & EMULTYPE_TRAP_UD)
5445 return EMULATE_FAIL;
991eebf9
GN		 5446 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5447 emulation_type))
bbd9b64e 5448 return EMULATE_DONE;
6d77dbfc
GN		 5449 if (emulation_type & EMULTYPE_SKIP)
5450 return EMULATE_FAIL;
5451 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5452 }
5453 }
5454
ba8afb6b 5455 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5456 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5457 if (ctxt->eflags & X86_EFLAGS_RF)
5458 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5459 return EMULATE_DONE;
5460 }
5461
1cb3f3ae
XG		 5462 if (retry_instruction(ctxt, cr2, emulation_type))
5463 return EMULATE_DONE;
5464
7ae441ea 5465 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5466 changes registers values during IO operation */
7ae441ea
GN		 5467 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5468 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5469 emulator_invalidate_register_cache(ctxt);
7ae441ea 5470 }
4d2179e1 5471
5cd21917 5472restart:
9d74191a 5473 r = x86_emulate_insn(ctxt);
bbd9b64e 5474
775fde86
JR		 5475 if (r == EMULATION_INTERCEPTED)
5476 return EMULATE_DONE;
5477
d2ddd1c4 5478 if (r == EMULATION_FAILED) {
991eebf9
GN		 5479 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5480 emulation_type))
c3cd7ffa
GN		 5481 return EMULATE_DONE;
5482
6d77dbfc 5483 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5484 }
5485
9d74191a 5486 if (ctxt->have_exception) {
d2ddd1c4 5487 r = EMULATE_DONE;
ef54bcfe
PB		 5488 if (inject_emulated_exception(vcpu))
5489 return r;
d2ddd1c4 5490 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5491 if (!vcpu->arch.pio.in) {
5492 /* FIXME: return into emulator if single-stepping. */
3457e419 5493 vcpu->arch.pio.count = 0;
0912c977 5494 } else {
7ae441ea 5495 writeback = false;
716d51ab
GN		 5496 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5497 }
ac0a48c3 5498 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5499 } else if (vcpu->mmio_needed) {
5500 if (!vcpu->mmio_is_write)
5501 writeback = false;
ac0a48c3 5502 r = EMULATE_USER_EXIT;
716d51ab 5503 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5504 } else if (r == EMULATION_RESTART)
5cd21917 5505 goto restart;
d2ddd1c4
GN		 5506 else
5507 r = EMULATE_DONE;
f850e2e6 5508
7ae441ea 5509 if (writeback) {
6addfc42 5510 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5511 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5512 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5513 if (vcpu->arch.hflags != ctxt->emul_flags)
5514 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5515 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5516 if (r == EMULATE_DONE)
6addfc42 5517 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5518 if (!ctxt->have_exception ||
5519 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5520 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5521
5522 /*
5523 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5524 * do nothing, and it will be requested again as soon as
5525 * the shadow expires. But we still need to check here,
5526 * because POPF has no interrupt shadow.
5527 */
5528 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5529 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5530 } else
5531 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5532
5533 return r;
de7d789a 5534}
51d8b661 5535EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5536
cf8f70bf 5537int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5538{
cf8f70bf 5539 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5540 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5541 size, port, &val, 1);
cf8f70bf 5542 /* do not return to emulator after return from userspace */
7972995b 5543 vcpu->arch.pio.count = 0;
de7d789a
CO		 5544 return ret;
5545}
cf8f70bf 5546EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5547
8cfdc000
ZA		 5548static void tsc_bad(void *info)
5549{
0a3aee0d 5550 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5551}
5552
5553static void tsc_khz_changed(void *data)
c8076604 5554{
8cfdc000
ZA		 5555 struct cpufreq_freqs *freq = data;
5556 unsigned long khz = 0;
5557
5558 if (data)
5559 khz = freq->new;
5560 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5561 khz = cpufreq_quick_get(raw_smp_processor_id());
5562 if (!khz)
5563 khz = tsc_khz;
0a3aee0d 5564 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5565}
5566
c8076604
GH		 5567static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5568 void *data)
5569{
5570 struct cpufreq_freqs *freq = data;
5571 struct kvm *kvm;
5572 struct kvm_vcpu *vcpu;
5573 int i, send_ipi = 0;
5574
8cfdc000
ZA		 5575 /*
5576 * We allow guests to temporarily run on slowing clocks,
5577 * provided we notify them after, or to run on accelerating
5578 * clocks, provided we notify them before. Thus time never
5579 * goes backwards.
5580 *
5581 * However, we have a problem. We can't atomically update
5582 * the frequency of a given CPU from this function; it is
5583 * merely a notifier, which can be called from any CPU.
5584 * Changing the TSC frequency at arbitrary points in time
5585 * requires a recomputation of local variables related to
5586 * the TSC for each VCPU. We must flag these local variables
5587 * to be updated and be sure the update takes place with the
5588 * new frequency before any guests proceed.
5589 *
5590 * Unfortunately, the combination of hotplug CPU and frequency
5591 * change creates an intractable locking scenario; the order
5592 * of when these callouts happen is undefined with respect to
5593 * CPU hotplug, and they can race with each other. As such,
5594 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5595 * undefined; you can actually have a CPU frequency change take
5596 * place in between the computation of X and the setting of the
5597 * variable. To protect against this problem, all updates of
5598 * the per_cpu tsc_khz variable are done in an interrupt
5599 * protected IPI, and all callers wishing to update the value
5600 * must wait for a synchronous IPI to complete (which is trivial
5601 * if the caller is on the CPU already). This establishes the
5602 * necessary total order on variable updates.
5603 *
5604 * Note that because a guest time update may take place
5605 * anytime after the setting of the VCPU's request bit, the
5606 * correct TSC value must be set before the request. However,
5607 * to ensure the update actually makes it to any guest which
5608 * starts running in hardware virtualization between the set
5609 * and the acquisition of the spinlock, we must also ping the
5610 * CPU after setting the request bit.
5611 *
5612 */
5613
c8076604
GH		 5614 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5615 return 0;
5616 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5617 return 0;
8cfdc000
ZA		 5618
5619 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5620
2f303b74 5621 spin_lock(&kvm_lock);
c8076604 5622 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5623 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5624 if (vcpu->cpu != freq->cpu)
5625 continue;
c285545f 5626 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5627 if (vcpu->cpu != smp_processor_id())
8cfdc000 5628 send_ipi = 1;
c8076604
GH		 5629 }
5630 }
2f303b74 5631 spin_unlock(&kvm_lock);
c8076604
GH		 5632
5633 if (freq->old < freq->new && send_ipi) {
5634 /*
5635 * We upscale the frequency. Must make the guest
5636 * doesn't see old kvmclock values while running with
5637 * the new frequency, otherwise we risk the guest sees
5638 * time go backwards.
5639 *
5640 * In case we update the frequency for another cpu
5641 * (which might be in guest context) send an interrupt
5642 * to kick the cpu out of guest context. Next time
5643 * guest context is entered kvmclock will be updated,
5644 * so the guest will not see stale values.
5645 */
8cfdc000 5646 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5647 }
5648 return 0;
5649}
5650
5651static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5652 .notifier_call = kvmclock_cpufreq_notifier
5653};
5654
5655static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5656 unsigned long action, void *hcpu)
5657{
5658 unsigned int cpu = (unsigned long)hcpu;
5659
5660 switch (action) {
5661 case CPU_ONLINE:
5662 case CPU_DOWN_FAILED:
5663 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5664 break;
5665 case CPU_DOWN_PREPARE:
5666 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5667 break;
5668 }
5669 return NOTIFY_OK;
5670}
5671
5672static struct notifier_block kvmclock_cpu_notifier_block = {
5673 .notifier_call = kvmclock_cpu_notifier,
5674 .priority = -INT_MAX
c8076604
GH		 5675};
5676
b820cc0c
ZA		 5677static void kvm_timer_init(void)
5678{
5679 int cpu;
5680
c285545f 5681 max_tsc_khz = tsc_khz;
460dd42e
SB		 5682
5683 cpu_notifier_register_begin();
b820cc0c 5684 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5685#ifdef CONFIG_CPU_FREQ
5686 struct cpufreq_policy policy;
5687 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5688 cpu = get_cpu();
5689 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5690 if (policy.cpuinfo.max_freq)
5691 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5692 put_cpu();
c285545f 5693#endif
b820cc0c
ZA		 5694 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5695 CPUFREQ_TRANSITION_NOTIFIER);
5696 }
c285545f 5697 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5698 for_each_online_cpu(cpu)
5699 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5700
5701 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5702 cpu_notifier_register_done();
5703
b820cc0c
ZA		 5704}
5705
ff9d07a0
ZY		 5706static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5707
f5132b01 5708int kvm_is_in_guest(void)
ff9d07a0 5709{
086c9855 5710 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5711}
5712
5713static int kvm_is_user_mode(void)
5714{
5715 int user_mode = 3;
dcf46b94 5716
086c9855
AS		 5717 if (__this_cpu_read(current_vcpu))
5718 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5719
ff9d07a0
ZY		 5720 return user_mode != 0;
5721}
5722
5723static unsigned long kvm_get_guest_ip(void)
5724{
5725 unsigned long ip = 0;
dcf46b94 5726
086c9855
AS		 5727 if (__this_cpu_read(current_vcpu))
5728 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5729
ff9d07a0
ZY		 5730 return ip;
5731}
5732
5733static struct perf_guest_info_callbacks kvm_guest_cbs = {
5734 .is_in_guest = kvm_is_in_guest,
5735 .is_user_mode = kvm_is_user_mode,
5736 .get_guest_ip = kvm_get_guest_ip,
5737};
5738
5739void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5740{
086c9855 5741 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5742}
5743EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5744
5745void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5746{
086c9855 5747 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5748}
5749EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5750
ce88decf
XG		 5751static void kvm_set_mmio_spte_mask(void)
5752{
5753 u64 mask;
5754 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5755
5756 /*
5757 * Set the reserved bits and the present bit of an paging-structure
5758 * entry to generate page fault with PFER.RSV = 1.
5759 */
885032b9 5760 /* Mask the reserved physical address bits. */
d1431483 5761 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5762
5763 /* Bit 62 is always reserved for 32bit host. */
5764 mask |= 0x3ull << 62;
5765
5766 /* Set the present bit. */
ce88decf
XG		 5767 mask |= 1ull;
5768
5769#ifdef CONFIG_X86_64
5770 /*
5771 * If reserved bit is not supported, clear the present bit to disable
5772 * mmio page fault.
5773 */
5774 if (maxphyaddr == 52)
5775 mask &= ~1ull;
5776#endif
5777
5778 kvm_mmu_set_mmio_spte_mask(mask);
5779}
5780
16e8d74d
MT		 5781#ifdef CONFIG_X86_64
5782static void pvclock_gtod_update_fn(struct work_struct *work)
5783{
d828199e
MT		 5784 struct kvm *kvm;
5785
5786 struct kvm_vcpu *vcpu;
5787 int i;
5788
2f303b74 5789 spin_lock(&kvm_lock);
d828199e
MT		 5790 list_for_each_entry(kvm, &vm_list, vm_list)
5791 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5792 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5793 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5794 spin_unlock(&kvm_lock);
16e8d74d
MT		 5795}
5796
5797static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5798
5799/*
5800 * Notification about pvclock gtod data update.
5801 */
5802static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5803 void *priv)
5804{
5805 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5806 struct timekeeper *tk = priv;
5807
5808 update_pvclock_gtod(tk);
5809
5810 /* disable master clock if host does not trust, or does not
5811 * use, TSC clocksource
5812 */
5813 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5814 atomic_read(&kvm_guest_has_master_clock) != 0)
5815 queue_work(system_long_wq, &pvclock_gtod_work);
5816
5817 return 0;
5818}
5819
5820static struct notifier_block pvclock_gtod_notifier = {
5821 .notifier_call = pvclock_gtod_notify,
5822};
5823#endif
5824
f8c16bba 5825int kvm_arch_init(void *opaque)
043405e1 5826{
b820cc0c 5827 int r;
6b61edf7 5828 struct kvm_x86_ops *ops = opaque;
f8c16bba 5829
f8c16bba
ZX		 5830 if (kvm_x86_ops) {
5831 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5832 r = -EEXIST;
5833 goto out;
f8c16bba
ZX		 5834 }
5835
5836 if (!ops->cpu_has_kvm_support()) {
5837 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5838 r = -EOPNOTSUPP;
5839 goto out;
f8c16bba
ZX		 5840 }
5841 if (ops->disabled_by_bios()) {
5842 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5843 r = -EOPNOTSUPP;
5844 goto out;
f8c16bba
ZX		 5845 }
5846
013f6a5d
MT		 5847 r = -ENOMEM;
5848 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5849 if (!shared_msrs) {
5850 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5851 goto out;
5852 }
5853
97db56ce
AK		 5854 r = kvm_mmu_module_init();
5855 if (r)
013f6a5d 5856 goto out_free_percpu;
97db56ce 5857
ce88decf 5858 kvm_set_mmio_spte_mask();
97db56ce 5859
f8c16bba 5860 kvm_x86_ops = ops;
920c8377 5861
7b52345e 5862 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5863 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5864
b820cc0c 5865 kvm_timer_init();
c8076604 5866
ff9d07a0
ZY		 5867 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5868
2acf923e
DC		 5869 if (cpu_has_xsave)
5870 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5871
c5cc421b 5872 kvm_lapic_init();
16e8d74d
MT		 5873#ifdef CONFIG_X86_64
5874 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5875#endif
5876
f8c16bba 5877 return 0;
56c6d28a 5878
013f6a5d
MT		 5879out_free_percpu:
5880 free_percpu(shared_msrs);
56c6d28a 5881out:
56c6d28a 5882 return r;
043405e1 5883}
8776e519 5884
f8c16bba
ZX		 5885void kvm_arch_exit(void)
5886{
ff9d07a0
ZY		 5887 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5888
888d256e
JK		 5889 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5890 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5891 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5892 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5893#ifdef CONFIG_X86_64
5894 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5895#endif
f8c16bba 5896 kvm_x86_ops = NULL;
56c6d28a 5897 kvm_mmu_module_exit();
013f6a5d 5898 free_percpu(shared_msrs);
56c6d28a 5899}
f8c16bba 5900
5cb56059 5901int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5902{
5903 ++vcpu->stat.halt_exits;
35754c98 5904 if (lapic_in_kernel(vcpu)) {
a4535290 5905 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5906 return 1;
5907 } else {
5908 vcpu->run->exit_reason = KVM_EXIT_HLT;
5909 return 0;
5910 }
5911}
5cb56059
JS		 5912EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5913
5914int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5915{
5916 kvm_x86_ops->skip_emulated_instruction(vcpu);
5917 return kvm_vcpu_halt(vcpu);
5918}
8776e519
HB		 5919EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5920
6aef266c
SV		 5921/*
5922 * kvm_pv_kick_cpu_op: Kick a vcpu.
5923 *
5924 * @apicid - apicid of vcpu to be kicked.
5925 */
5926static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5927{
24d2166b 5928 struct kvm_lapic_irq lapic_irq;
6aef266c 5929
24d2166b
R		 5930 lapic_irq.shorthand = 0;
5931 lapic_irq.dest_mode = 0;
5932 lapic_irq.dest_id = apicid;
93bbf0b8 5933 lapic_irq.msi_redir_hint = false;
6aef266c 5934
24d2166b 5935 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5936 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5937}
5938
d62caabb
AS		 5939void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5940{
5941 vcpu->arch.apicv_active = false;
5942 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5943}
5944
8776e519
HB		 5945int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5946{
5947 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5948 int op_64_bit, r = 1;
8776e519 5949
5cb56059
JS		 5950 kvm_x86_ops->skip_emulated_instruction(vcpu);
5951
55cd8e5a
GN		 5952 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5953 return kvm_hv_hypercall(vcpu);
5954
5fdbf976
MT		 5955 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5956 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5957 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5958 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5959 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5960
229456fc 5961 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5962
a449c7aa
NA		 5963 op_64_bit = is_64_bit_mode(vcpu);
5964 if (!op_64_bit) {
8776e519
HB		 5965 nr &= 0xFFFFFFFF;
5966 a0 &= 0xFFFFFFFF;
5967 a1 &= 0xFFFFFFFF;
5968 a2 &= 0xFFFFFFFF;
5969 a3 &= 0xFFFFFFFF;
5970 }
5971
07708c4a
JK		 5972 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5973 ret = -KVM_EPERM;
5974 goto out;
5975 }
5976
8776e519 5977 switch (nr) {
b93463aa
AK		 5978 case KVM_HC_VAPIC_POLL_IRQ:
5979 ret = 0;
5980 break;
6aef266c
SV		 5981 case KVM_HC_KICK_CPU:
5982 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5983 ret = 0;
5984 break;
8776e519
HB		 5985 default:
5986 ret = -KVM_ENOSYS;
5987 break;
5988 }
07708c4a 5989out:
a449c7aa
NA		 5990 if (!op_64_bit)
5991 ret = (u32)ret;
5fdbf976 5992 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5993 ++vcpu->stat.hypercalls;
2f333bcb 5994 return r;
8776e519
HB		 5995}
5996EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5997
b6785def 5998static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5999{
d6aa1000 6000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6001 char instruction[3];
5fdbf976 6002 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6003
8776e519 6004 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6005
9d74191a 6006 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6007}
6008
851ba692 6009static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6010{
782d422b
MG		 6011 return vcpu->run->request_interrupt_window &&
6012 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6013}
6014
851ba692 6015static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6016{
851ba692
AK		 6017 struct kvm_run *kvm_run = vcpu->run;
6018
91586a3b 6019 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6020 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6021 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6022 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6023 kvm_run->ready_for_interrupt_injection =
6024 pic_in_kernel(vcpu->kvm) ||
782d422b 6025 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6026}
6027
95ba8273
GN		 6028static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6029{
6030 int max_irr, tpr;
6031
6032 if (!kvm_x86_ops->update_cr8_intercept)
6033 return;
6034
bce87cce 6035 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6036 return;
6037
d62caabb
AS		 6038 if (vcpu->arch.apicv_active)
6039 return;
6040
8db3baa2
GN		 6041 if (!vcpu->arch.apic->vapic_addr)
6042 max_irr = kvm_lapic_find_highest_irr(vcpu);
6043 else
6044 max_irr = -1;
95ba8273
GN		 6045
6046 if (max_irr != -1)
6047 max_irr >>= 4;
6048
6049 tpr = kvm_lapic_get_cr8(vcpu);
6050
6051 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6052}
6053
b6b8a145 6054static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6055{
b6b8a145
JK		 6056 int r;
6057
95ba8273 6058 /* try to reinject previous events if any */
b59bb7bd 6059 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6060 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6061 vcpu->arch.exception.has_error_code,
6062 vcpu->arch.exception.error_code);
d6e8c854
NA		 6063
6064 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6065 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6066 X86_EFLAGS_RF);
6067
6bdf0662
NA		 6068 if (vcpu->arch.exception.nr == DB_VECTOR &&
6069 (vcpu->arch.dr7 & DR7_GD)) {
6070 vcpu->arch.dr7 &= ~DR7_GD;
6071 kvm_update_dr7(vcpu);
6072 }
6073
b59bb7bd
GN		 6074 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6075 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6076 vcpu->arch.exception.error_code,
6077 vcpu->arch.exception.reinject);
b6b8a145 6078 return 0;
b59bb7bd
GN		 6079 }
6080
95ba8273
GN		 6081 if (vcpu->arch.nmi_injected) {
6082 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6083 return 0;
95ba8273
GN		 6084 }
6085
6086 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6087 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6088 return 0;
6089 }
6090
6091 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6092 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6093 if (r != 0)
6094 return r;
95ba8273
GN		 6095 }
6096
6097 /* try to inject new event if pending */
6098 if (vcpu->arch.nmi_pending) {
6099 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6100 --vcpu->arch.nmi_pending;
95ba8273
GN		 6101 vcpu->arch.nmi_injected = true;
6102 kvm_x86_ops->set_nmi(vcpu);
6103 }
c7c9c56c 6104 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6105 /*
6106 * Because interrupts can be injected asynchronously, we are
6107 * calling check_nested_events again here to avoid a race condition.
6108 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6109 * proposal and current concerns. Perhaps we should be setting
6110 * KVM_REQ_EVENT only on certain events and not unconditionally?
6111 */
6112 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6113 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6114 if (r != 0)
6115 return r;
6116 }
95ba8273 6117 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6118 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6119 false);
6120 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6121 }
6122 }
b6b8a145 6123 return 0;
95ba8273
GN		 6124}
6125
7460fb4a
AK		 6126static void process_nmi(struct kvm_vcpu *vcpu)
6127{
6128 unsigned limit = 2;
6129
6130 /*
6131 * x86 is limited to one NMI running, and one NMI pending after it.
6132 * If an NMI is already in progress, limit further NMIs to just one.
6133 * Otherwise, allow two (and we'll inject the first one immediately).
6134 */
6135 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6136 limit = 1;
6137
6138 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6139 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6140 kvm_make_request(KVM_REQ_EVENT, vcpu);
6141}
6142
660a5d51
PB		 6143#define put_smstate(type, buf, offset, val) \
6144 *(type *)((buf) + (offset) - 0x7e00) = val
6145
6146static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6147{
6148 u32 flags = 0;
6149 flags |= seg->g << 23;
6150 flags |= seg->db << 22;
6151 flags |= seg->l << 21;
6152 flags |= seg->avl << 20;
6153 flags |= seg->present << 15;
6154 flags |= seg->dpl << 13;
6155 flags |= seg->s << 12;
6156 flags |= seg->type << 8;
6157 return flags;
6158}
6159
6160static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6161{
6162 struct kvm_segment seg;
6163 int offset;
6164
6165 kvm_get_segment(vcpu, &seg, n);
6166 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6167
6168 if (n < 3)
6169 offset = 0x7f84 + n * 12;
6170 else
6171 offset = 0x7f2c + (n - 3) * 12;
6172
6173 put_smstate(u32, buf, offset + 8, seg.base);
6174 put_smstate(u32, buf, offset + 4, seg.limit);
6175 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6176}
6177
efbb288a 6178#ifdef CONFIG_X86_64
660a5d51
PB		 6179static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6180{
6181 struct kvm_segment seg;
6182 int offset;
6183 u16 flags;
6184
6185 kvm_get_segment(vcpu, &seg, n);
6186 offset = 0x7e00 + n * 16;
6187
6188 flags = process_smi_get_segment_flags(&seg) >> 8;
6189 put_smstate(u16, buf, offset, seg.selector);
6190 put_smstate(u16, buf, offset + 2, flags);
6191 put_smstate(u32, buf, offset + 4, seg.limit);
6192 put_smstate(u64, buf, offset + 8, seg.base);
6193}
efbb288a 6194#endif
660a5d51
PB		 6195
6196static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6197{
6198 struct desc_ptr dt;
6199 struct kvm_segment seg;
6200 unsigned long val;
6201 int i;
6202
6203 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6204 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6205 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6206 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6207
6208 for (i = 0; i < 8; i++)
6209 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6210
6211 kvm_get_dr(vcpu, 6, &val);
6212 put_smstate(u32, buf, 0x7fcc, (u32)val);
6213 kvm_get_dr(vcpu, 7, &val);
6214 put_smstate(u32, buf, 0x7fc8, (u32)val);
6215
6216 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6217 put_smstate(u32, buf, 0x7fc4, seg.selector);
6218 put_smstate(u32, buf, 0x7f64, seg.base);
6219 put_smstate(u32, buf, 0x7f60, seg.limit);
6220 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6221
6222 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6223 put_smstate(u32, buf, 0x7fc0, seg.selector);
6224 put_smstate(u32, buf, 0x7f80, seg.base);
6225 put_smstate(u32, buf, 0x7f7c, seg.limit);
6226 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6227
6228 kvm_x86_ops->get_gdt(vcpu, &dt);
6229 put_smstate(u32, buf, 0x7f74, dt.address);
6230 put_smstate(u32, buf, 0x7f70, dt.size);
6231
6232 kvm_x86_ops->get_idt(vcpu, &dt);
6233 put_smstate(u32, buf, 0x7f58, dt.address);
6234 put_smstate(u32, buf, 0x7f54, dt.size);
6235
6236 for (i = 0; i < 6; i++)
6237 process_smi_save_seg_32(vcpu, buf, i);
6238
6239 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6240
6241 /* revision id */
6242 put_smstate(u32, buf, 0x7efc, 0x00020000);
6243 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6244}
6245
6246static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6247{
6248#ifdef CONFIG_X86_64
6249 struct desc_ptr dt;
6250 struct kvm_segment seg;
6251 unsigned long val;
6252 int i;
6253
6254 for (i = 0; i < 16; i++)
6255 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6256
6257 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6258 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6259
6260 kvm_get_dr(vcpu, 6, &val);
6261 put_smstate(u64, buf, 0x7f68, val);
6262 kvm_get_dr(vcpu, 7, &val);
6263 put_smstate(u64, buf, 0x7f60, val);
6264
6265 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6266 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6267 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6268
6269 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6270
6271 /* revision id */
6272 put_smstate(u32, buf, 0x7efc, 0x00020064);
6273
6274 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6275
6276 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6277 put_smstate(u16, buf, 0x7e90, seg.selector);
6278 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6279 put_smstate(u32, buf, 0x7e94, seg.limit);
6280 put_smstate(u64, buf, 0x7e98, seg.base);
6281
6282 kvm_x86_ops->get_idt(vcpu, &dt);
6283 put_smstate(u32, buf, 0x7e84, dt.size);
6284 put_smstate(u64, buf, 0x7e88, dt.address);
6285
6286 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6287 put_smstate(u16, buf, 0x7e70, seg.selector);
6288 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6289 put_smstate(u32, buf, 0x7e74, seg.limit);
6290 put_smstate(u64, buf, 0x7e78, seg.base);
6291
6292 kvm_x86_ops->get_gdt(vcpu, &dt);
6293 put_smstate(u32, buf, 0x7e64, dt.size);
6294 put_smstate(u64, buf, 0x7e68, dt.address);
6295
6296 for (i = 0; i < 6; i++)
6297 process_smi_save_seg_64(vcpu, buf, i);
6298#else
6299 WARN_ON_ONCE(1);
6300#endif
6301}
6302
64d60670
PB		 6303static void process_smi(struct kvm_vcpu *vcpu)
6304{
660a5d51 6305 struct kvm_segment cs, ds;
18c3626e 6306 struct desc_ptr dt;
660a5d51
PB		 6307 char buf[512];
6308 u32 cr0;
6309
64d60670
PB		 6310 if (is_smm(vcpu)) {
6311 vcpu->arch.smi_pending = true;
6312 return;
6313 }
6314
660a5d51
PB		 6315 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6316 vcpu->arch.hflags |= HF_SMM_MASK;
6317 memset(buf, 0, 512);
6318 if (guest_cpuid_has_longmode(vcpu))
6319 process_smi_save_state_64(vcpu, buf);
6320 else
6321 process_smi_save_state_32(vcpu, buf);
6322
54bf36aa 6323 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6324
6325 if (kvm_x86_ops->get_nmi_mask(vcpu))
6326 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6327 else
6328 kvm_x86_ops->set_nmi_mask(vcpu, true);
6329
6330 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6331 kvm_rip_write(vcpu, 0x8000);
6332
6333 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6334 kvm_x86_ops->set_cr0(vcpu, cr0);
6335 vcpu->arch.cr0 = cr0;
6336
6337 kvm_x86_ops->set_cr4(vcpu, 0);
6338
18c3626e
PB		 6339 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6340 dt.address = dt.size = 0;
6341 kvm_x86_ops->set_idt(vcpu, &dt);
6342
660a5d51
PB		 6343 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6344
6345 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6346 cs.base = vcpu->arch.smbase;
6347
6348 ds.selector = 0;
6349 ds.base = 0;
6350
6351 cs.limit = ds.limit = 0xffffffff;
6352 cs.type = ds.type = 0x3;
6353 cs.dpl = ds.dpl = 0;
6354 cs.db = ds.db = 0;
6355 cs.s = ds.s = 1;
6356 cs.l = ds.l = 0;
6357 cs.g = ds.g = 1;
6358 cs.avl = ds.avl = 0;
6359 cs.present = ds.present = 1;
6360 cs.unusable = ds.unusable = 0;
6361 cs.padding = ds.padding = 0;
6362
6363 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6364 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6365 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6366 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6367 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6368 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6369
6370 if (guest_cpuid_has_longmode(vcpu))
6371 kvm_x86_ops->set_efer(vcpu, 0);
6372
6373 kvm_update_cpuid(vcpu);
6374 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6375}
6376
2860c4b1
PB		 6377void kvm_make_scan_ioapic_request(struct kvm *kvm)
6378{
6379 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6380}
6381
3d81bc7e 6382static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6383{
5c919412
AS		 6384 u64 eoi_exit_bitmap[4];
6385
3d81bc7e
YZ		 6386 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6387 return;
c7c9c56c 6388
6308630b 6389 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6390
b053b2ae 6391 if (irqchip_split(vcpu->kvm))
6308630b 6392 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6393 else {
d62caabb
AS		 6394 if (vcpu->arch.apicv_active)
6395 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6396 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6397 }
5c919412
AS		 6398 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6399 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6400 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6401}
6402
a70656b6
RK		 6403static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6404{
6405 ++vcpu->stat.tlb_flush;
6406 kvm_x86_ops->tlb_flush(vcpu);
6407}
6408
4256f43f
TC		 6409void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6410{
c24ae0dc
TC		 6411 struct page *page = NULL;
6412
35754c98 6413 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6414 return;
6415
4256f43f
TC		 6416 if (!kvm_x86_ops->set_apic_access_page_addr)
6417 return;
6418
c24ae0dc 6419 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6420 if (is_error_page(page))
6421 return;
c24ae0dc
TC		 6422 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6423
6424 /*
6425 * Do not pin apic access page in memory, the MMU notifier
6426 * will call us again if it is migrated or swapped out.
6427 */
6428 put_page(page);
4256f43f
TC		 6429}
6430EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6431
fe71557a
TC		 6432void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6433 unsigned long address)
6434{
c24ae0dc
TC		 6435 /*
6436 * The physical address of apic access page is stored in the VMCS.
6437 * Update it when it becomes invalid.
6438 */
6439 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6440 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6441}
6442
9357d939 6443/*
362c698f 6444 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6445 * exiting to the userspace. Otherwise, the value will be returned to the
6446 * userspace.
6447 */
851ba692 6448static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6449{
6450 int r;
62a193ed
MG		 6451 bool req_int_win =
6452 dm_request_for_irq_injection(vcpu) &&
6453 kvm_cpu_accept_dm_intr(vcpu);
6454
730dca42 6455 bool req_immediate_exit = false;
b6c7a5dc 6456
3e007509 6457 if (vcpu->requests) {
a8eeb04a 6458 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6459 kvm_mmu_unload(vcpu);
a8eeb04a 6460 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6461 __kvm_migrate_timers(vcpu);
d828199e
MT		 6462 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6463 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6464 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6465 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6466 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6467 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6468 if (unlikely(r))
6469 goto out;
6470 }
a8eeb04a 6471 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6472 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6473 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6474 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6475 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6476 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6477 r = 0;
6478 goto out;
6479 }
a8eeb04a 6480 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6481 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6482 r = 0;
6483 goto out;
6484 }
a8eeb04a 6485 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6486 vcpu->fpu_active = 0;
6487 kvm_x86_ops->fpu_deactivate(vcpu);
6488 }
af585b92
GN		 6489 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6490 /* Page is swapped out. Do synthetic halt */
6491 vcpu->arch.apf.halted = true;
6492 r = 1;
6493 goto out;
6494 }
c9aaa895
GC		 6495 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6496 record_steal_time(vcpu);
64d60670
PB		 6497 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6498 process_smi(vcpu);
7460fb4a
AK		 6499 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6500 process_nmi(vcpu);
f5132b01 6501 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6502 kvm_pmu_handle_event(vcpu);
f5132b01 6503 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6504 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6505 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6506 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6507 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6508 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6509 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6510 vcpu->run->eoi.vector =
6511 vcpu->arch.pending_ioapic_eoi;
6512 r = 0;
6513 goto out;
6514 }
6515 }
3d81bc7e
YZ		 6516 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6517 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6518 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6519 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6520 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6521 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6522 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6523 r = 0;
6524 goto out;
6525 }
e516cebb
AS		 6526 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6527 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6528 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6529 r = 0;
6530 goto out;
6531 }
db397571
AS		 6532 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6533 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6534 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6535 r = 0;
6536 goto out;
6537 }
f3b138c5
AS		 6538
6539 /*
6540 * KVM_REQ_HV_STIMER has to be processed after
6541 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6542 * depend on the guest clock being up-to-date
6543 */
1f4b34f8
AS		 6544 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6545 kvm_hv_process_stimers(vcpu);
2f52d58c 6546 }
b93463aa 6547
bf9f6ac8
FW		 6548 /*
6549 * KVM_REQ_EVENT is not set when posted interrupts are set by
6550 * VT-d hardware, so we have to update RVI unconditionally.
6551 */
6552 if (kvm_lapic_enabled(vcpu)) {
6553 /*
6554 * Update architecture specific hints for APIC
6555 * virtual interrupt delivery.
6556 */
d62caabb 6557 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6558 kvm_x86_ops->hwapic_irr_update(vcpu,
6559 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6560 }
b93463aa 6561
b463a6f7 6562 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6563 kvm_apic_accept_events(vcpu);
6564 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6565 r = 1;
6566 goto out;
6567 }
6568
b6b8a145
JK		 6569 if (inject_pending_event(vcpu, req_int_win) != 0)
6570 req_immediate_exit = true;
b463a6f7 6571 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6572 else if (vcpu->arch.nmi_pending)
c9a7953f 6573 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6574 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6575 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6576
6577 if (kvm_lapic_enabled(vcpu)) {
6578 update_cr8_intercept(vcpu);
6579 kvm_lapic_sync_to_vapic(vcpu);
6580 }
6581 }
6582
d8368af8
AK		 6583 r = kvm_mmu_reload(vcpu);
6584 if (unlikely(r)) {
d905c069 6585 goto cancel_injection;
d8368af8
AK		 6586 }
6587
b6c7a5dc
HB		 6588 preempt_disable();
6589
6590 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6591 if (vcpu->fpu_active)
6592 kvm_load_guest_fpu(vcpu);
2acf923e 6593 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6594
6b7e2d09
XG		 6595 vcpu->mode = IN_GUEST_MODE;
6596
01b71917
MT		 6597 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6598
6b7e2d09
XG		 6599 /* We should set ->mode before check ->requests,
6600 * see the comment in make_all_cpus_request.
6601 */
01b71917 6602 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6603
d94e1dc9 6604 local_irq_disable();
32f88400 6605
6b7e2d09 6606 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6607 || need_resched() || signal_pending(current)) {
6b7e2d09 6608 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6609 smp_wmb();
6c142801
AK		 6610 local_irq_enable();
6611 preempt_enable();
01b71917 6612 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6613 r = 1;
d905c069 6614 goto cancel_injection;
6c142801
AK		 6615 }
6616
d6185f20
NHE		 6617 if (req_immediate_exit)
6618 smp_send_reschedule(vcpu->cpu);
6619
8b89fe1f
PB		 6620 trace_kvm_entry(vcpu->vcpu_id);
6621 wait_lapic_expire(vcpu);
ccf73aaf 6622 __kvm_guest_enter();
b6c7a5dc 6623
42dbaa5a 6624 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6625 set_debugreg(0, 7);
6626 set_debugreg(vcpu->arch.eff_db[0], 0);
6627 set_debugreg(vcpu->arch.eff_db[1], 1);
6628 set_debugreg(vcpu->arch.eff_db[2], 2);
6629 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6630 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6631 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6632 }
b6c7a5dc 6633
851ba692 6634 kvm_x86_ops->run(vcpu);
b6c7a5dc 6635
c77fb5fe
PB		 6636 /*
6637 * Do this here before restoring debug registers on the host. And
6638 * since we do this before handling the vmexit, a DR access vmexit
6639 * can (a) read the correct value of the debug registers, (b) set
6640 * KVM_DEBUGREG_WONT_EXIT again.
6641 */
6642 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6643 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6644 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6645 kvm_update_dr0123(vcpu);
6646 kvm_update_dr6(vcpu);
6647 kvm_update_dr7(vcpu);
6648 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6649 }
6650
24f1e32c
FW		 6651 /*
6652 * If the guest has used debug registers, at least dr7
6653 * will be disabled while returning to the host.
6654 * If we don't have active breakpoints in the host, we don't
6655 * care about the messed up debug address registers. But if
6656 * we have some of them active, restore the old state.
6657 */
59d8eb53 6658 if (hw_breakpoint_active())
24f1e32c 6659 hw_breakpoint_restore();
42dbaa5a 6660
4ba76538 6661 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6662
6b7e2d09 6663 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6664 smp_wmb();
a547c6db
YZ		 6665
6666 /* Interrupt is enabled by handle_external_intr() */
6667 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6668
6669 ++vcpu->stat.exits;
6670
6671 /*
6672 * We must have an instruction between local_irq_enable() and
6673 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6674 * the interrupt shadow. The stat.exits increment will do nicely.
6675 * But we need to prevent reordering, hence this barrier():
6676 */
6677 barrier();
6678
6679 kvm_guest_exit();
6680
6681 preempt_enable();
6682
f656ce01 6683 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6684
b6c7a5dc
HB		 6685 /*
6686 * Profile KVM exit RIPs:
6687 */
6688 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6689 unsigned long rip = kvm_rip_read(vcpu);
6690 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6691 }
6692
cc578287
ZA		 6693 if (unlikely(vcpu->arch.tsc_always_catchup))
6694 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6695
5cfb1d5a
MT		 6696 if (vcpu->arch.apic_attention)
6697 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6698
851ba692 6699 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6700 return r;
6701
6702cancel_injection:
6703 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6704 if (unlikely(vcpu->arch.apic_attention))
6705 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6706out:
6707 return r;
6708}
b6c7a5dc 6709
362c698f
PB		 6710static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6711{
bf9f6ac8
FW		 6712 if (!kvm_arch_vcpu_runnable(vcpu) &&
6713 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6714 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6715 kvm_vcpu_block(vcpu);
6716 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6717
6718 if (kvm_x86_ops->post_block)
6719 kvm_x86_ops->post_block(vcpu);
6720
9c8fd1ba
PB		 6721 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6722 return 1;
6723 }
362c698f
PB		 6724
6725 kvm_apic_accept_events(vcpu);
6726 switch(vcpu->arch.mp_state) {
6727 case KVM_MP_STATE_HALTED:
6728 vcpu->arch.pv.pv_unhalted = false;
6729 vcpu->arch.mp_state =
6730 KVM_MP_STATE_RUNNABLE;
6731 case KVM_MP_STATE_RUNNABLE:
6732 vcpu->arch.apf.halted = false;
6733 break;
6734 case KVM_MP_STATE_INIT_RECEIVED:
6735 break;
6736 default:
6737 return -EINTR;
6738 break;
6739 }
6740 return 1;
6741}
09cec754 6742
5d9bc648
PB		 6743static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6744{
6745 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6746 !vcpu->arch.apf.halted);
6747}
6748
362c698f 6749static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6750{
6751 int r;
f656ce01 6752 struct kvm *kvm = vcpu->kvm;
d7690175 6753
f656ce01 6754 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6755
362c698f 6756 for (;;) {
58f800d5 6757 if (kvm_vcpu_running(vcpu)) {
851ba692 6758 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6759 } else {
362c698f 6760 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6761 }
6762
09cec754
GN		 6763 if (r <= 0)
6764 break;
6765
6766 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6767 if (kvm_cpu_has_pending_timer(vcpu))
6768 kvm_inject_pending_timer_irqs(vcpu);
6769
782d422b
MG		 6770 if (dm_request_for_irq_injection(vcpu) &&
6771 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6772 r = 0;
6773 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6774 ++vcpu->stat.request_irq_exits;
362c698f 6775 break;
09cec754 6776 }
af585b92
GN		 6777
6778 kvm_check_async_pf_completion(vcpu);
6779
09cec754
GN		 6780 if (signal_pending(current)) {
6781 r = -EINTR;
851ba692 6782 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6783 ++vcpu->stat.signal_exits;
362c698f 6784 break;
09cec754
GN		 6785 }
6786 if (need_resched()) {
f656ce01 6787 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6788 cond_resched();
f656ce01 6789 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6790 }
b6c7a5dc
HB		 6791 }
6792
f656ce01 6793 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6794
6795 return r;
6796}
6797
716d51ab
GN		 6798static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6799{
6800 int r;
6801 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6802 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6803 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6804 if (r != EMULATE_DONE)
6805 return 0;
6806 return 1;
6807}
6808
6809static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6810{
6811 BUG_ON(!vcpu->arch.pio.count);
6812
6813 return complete_emulated_io(vcpu);
6814}
6815
f78146b0
AK		 6816/*
6817 * Implements the following, as a state machine:
6818 *
6819 * read:
6820 * for each fragment
87da7e66
XG		 6821 * for each mmio piece in the fragment
6822 * write gpa, len
6823 * exit
6824 * copy data
f78146b0
AK		 6825 * execute insn
6826 *
6827 * write:
6828 * for each fragment
87da7e66
XG		 6829 * for each mmio piece in the fragment
6830 * write gpa, len
6831 * copy data
6832 * exit
f78146b0 6833 */
716d51ab 6834static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6835{
6836 struct kvm_run *run = vcpu->run;
f78146b0 6837 struct kvm_mmio_fragment *frag;
87da7e66 6838 unsigned len;
5287f194 6839
716d51ab 6840 BUG_ON(!vcpu->mmio_needed);
5287f194 6841
716d51ab 6842 /* Complete previous fragment */
87da7e66
XG		 6843 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6844 len = min(8u, frag->len);
716d51ab 6845 if (!vcpu->mmio_is_write)
87da7e66
XG		 6846 memcpy(frag->data, run->mmio.data, len);
6847
6848 if (frag->len <= 8) {
6849 /* Switch to the next fragment. */
6850 frag++;
6851 vcpu->mmio_cur_fragment++;
6852 } else {
6853 /* Go forward to the next mmio piece. */
6854 frag->data += len;
6855 frag->gpa += len;
6856 frag->len -= len;
6857 }
6858
a08d3b3b 6859 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6860 vcpu->mmio_needed = 0;
0912c977
PB		 6861
6862 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6863 if (vcpu->mmio_is_write)
716d51ab
GN		 6864 return 1;
6865 vcpu->mmio_read_completed = 1;
6866 return complete_emulated_io(vcpu);
6867 }
87da7e66 6868
716d51ab
GN		 6869 run->exit_reason = KVM_EXIT_MMIO;
6870 run->mmio.phys_addr = frag->gpa;
6871 if (vcpu->mmio_is_write)
87da7e66
XG		 6872 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6873 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6874 run->mmio.is_write = vcpu->mmio_is_write;
6875 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6876 return 0;
5287f194
AK		 6877}
6878
716d51ab 6879
b6c7a5dc
HB		 6880int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6881{
c5bedc68 6882 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6883 int r;
6884 sigset_t sigsaved;
6885
c4d72e2d 6886 fpu__activate_curr(fpu);
e5c30142 6887
ac9f6dc0
AK		 6888 if (vcpu->sigset_active)
6889 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6890
a4535290 6891 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6892 kvm_vcpu_block(vcpu);
66450a21 6893 kvm_apic_accept_events(vcpu);
d7690175 6894 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6895 r = -EAGAIN;
6896 goto out;
b6c7a5dc
HB		 6897 }
6898
b6c7a5dc 6899 /* re-sync apic's tpr */
35754c98 6900 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6901 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6902 r = -EINVAL;
6903 goto out;
6904 }
6905 }
b6c7a5dc 6906
716d51ab
GN		 6907 if (unlikely(vcpu->arch.complete_userspace_io)) {
6908 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6909 vcpu->arch.complete_userspace_io = NULL;
6910 r = cui(vcpu);
6911 if (r <= 0)
6912 goto out;
6913 } else
6914 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6915
362c698f 6916 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6917
6918out:
f1d86e46 6919 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6920 if (vcpu->sigset_active)
6921 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6922
b6c7a5dc
HB		 6923 return r;
6924}
6925
6926int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6927{
7ae441ea
GN		 6928 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6929 /*
6930 * We are here if userspace calls get_regs() in the middle of
6931 * instruction emulation. Registers state needs to be copied
4a969980 6932 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6933 * that usually, but some bad designed PV devices (vmware
6934 * backdoor interface) need this to work
6935 */
dd856efa 6936 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6937 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6938 }
5fdbf976
MT		 6939 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6940 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6941 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6942 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6943 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6944 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6945 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6946 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6947#ifdef CONFIG_X86_64
5fdbf976
MT		 6948 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6949 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6950 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6951 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6952 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6953 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6954 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6955 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6956#endif
6957
5fdbf976 6958 regs->rip = kvm_rip_read(vcpu);
91586a3b 6959 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6960
b6c7a5dc
HB		 6961 return 0;
6962}
6963
6964int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6965{
7ae441ea
GN		 6966 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6967 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6968
5fdbf976
MT		 6969 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6970 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6971 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6972 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6973 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6974 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6975 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6976 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6977#ifdef CONFIG_X86_64
5fdbf976
MT		 6978 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6979 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6980 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6981 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6982 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6983 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6984 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6985 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6986#endif
6987
5fdbf976 6988 kvm_rip_write(vcpu, regs->rip);
91586a3b 6989 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6990
b4f14abd
JK		 6991 vcpu->arch.exception.pending = false;
6992
3842d135
AK		 6993 kvm_make_request(KVM_REQ_EVENT, vcpu);
6994
b6c7a5dc
HB		 6995 return 0;
6996}
6997
b6c7a5dc
HB		 6998void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6999{
7000 struct kvm_segment cs;
7001
3e6e0aab 7002 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7003 *db = cs.db;
7004 *l = cs.l;
7005}
7006EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7007
7008int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7009 struct kvm_sregs *sregs)
7010{
89a27f4d 7011 struct desc_ptr dt;
b6c7a5dc 7012
3e6e0aab
GT		 7013 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7014 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7015 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7016 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7017 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7018 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7019
3e6e0aab
GT		 7020 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7021 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7022
7023 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7024 sregs->idt.limit = dt.size;
7025 sregs->idt.base = dt.address;
b6c7a5dc 7026 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7027 sregs->gdt.limit = dt.size;
7028 sregs->gdt.base = dt.address;
b6c7a5dc 7029
4d4ec087 7030 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7031 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7032 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7033 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7034 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7035 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7036 sregs->apic_base = kvm_get_apic_base(vcpu);
7037
923c61bb 7038 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7039
36752c9b 7040 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7041 set_bit(vcpu->arch.interrupt.nr,
7042 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7043
b6c7a5dc
HB		 7044 return 0;
7045}
7046
62d9f0db
MT		 7047int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7048 struct kvm_mp_state *mp_state)
7049{
66450a21 7050 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7051 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7052 vcpu->arch.pv.pv_unhalted)
7053 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7054 else
7055 mp_state->mp_state = vcpu->arch.mp_state;
7056
62d9f0db
MT		 7057 return 0;
7058}
7059
7060int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7061 struct kvm_mp_state *mp_state)
7062{
bce87cce 7063 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7064 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7065 return -EINVAL;
7066
7067 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7068 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7069 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7070 } else
7071 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7072 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7073 return 0;
7074}
7075
7f3d35fd
KW		 7076int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7077 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7078{
9d74191a 7079 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7080 int ret;
e01c2426 7081
8ec4722d 7082 init_emulate_ctxt(vcpu);
c697518a 7083
7f3d35fd 7084 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7085 has_error_code, error_code);
c697518a 7086
c697518a 7087 if (ret)
19d04437 7088 return EMULATE_FAIL;
37817f29 7089
9d74191a
TY		 7090 kvm_rip_write(vcpu, ctxt->eip);
7091 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7092 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7093 return EMULATE_DONE;
37817f29
IE		 7094}
7095EXPORT_SYMBOL_GPL(kvm_task_switch);
7096
b6c7a5dc
HB		 7097int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7098 struct kvm_sregs *sregs)
7099{
58cb628d 7100 struct msr_data apic_base_msr;
b6c7a5dc 7101 int mmu_reset_needed = 0;
63f42e02 7102 int pending_vec, max_bits, idx;
89a27f4d 7103 struct desc_ptr dt;
b6c7a5dc 7104
6d1068b3
PM		 7105 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7106 return -EINVAL;
7107
89a27f4d
GN		 7108 dt.size = sregs->idt.limit;
7109 dt.address = sregs->idt.base;
b6c7a5dc 7110 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7111 dt.size = sregs->gdt.limit;
7112 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7113 kvm_x86_ops->set_gdt(vcpu, &dt);
7114
ad312c7c 7115 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7116 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7117 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7118 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7119
2d3ad1f4 7120 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7121
f6801dff 7122 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7123 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7124 apic_base_msr.data = sregs->apic_base;
7125 apic_base_msr.host_initiated = true;
7126 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7127
4d4ec087 7128 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7129 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7130 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7131
fc78f519 7132 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7133 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7134 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7135 kvm_update_cpuid(vcpu);
63f42e02
XG		 7136
7137 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7138 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7139 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7140 mmu_reset_needed = 1;
7141 }
63f42e02 7142 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7143
7144 if (mmu_reset_needed)
7145 kvm_mmu_reset_context(vcpu);
7146
a50abc3b 7147 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7148 pending_vec = find_first_bit(
7149 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7150 if (pending_vec < max_bits) {
66fd3f7f 7151 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7152 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7153 }
7154
3e6e0aab
GT		 7155 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7156 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7157 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7158 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7159 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7160 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7161
3e6e0aab
GT		 7162 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7163 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7164
5f0269f5
ME		 7165 update_cr8_intercept(vcpu);
7166
9c3e4aab 7167 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7168 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7169 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7170 !is_protmode(vcpu))
9c3e4aab
MT		 7171 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7172
3842d135
AK		 7173 kvm_make_request(KVM_REQ_EVENT, vcpu);
7174
b6c7a5dc
HB		 7175 return 0;
7176}
7177
d0bfb940
JK		 7178int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7179 struct kvm_guest_debug *dbg)
b6c7a5dc 7180{
355be0b9 7181 unsigned long rflags;
ae675ef0 7182 int i, r;
b6c7a5dc 7183
4f926bf2
JK		 7184 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7185 r = -EBUSY;
7186 if (vcpu->arch.exception.pending)
2122ff5e 7187 goto out;
4f926bf2
JK		 7188 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7189 kvm_queue_exception(vcpu, DB_VECTOR);
7190 else
7191 kvm_queue_exception(vcpu, BP_VECTOR);
7192 }
7193
91586a3b
JK		 7194 /*
7195 * Read rflags as long as potentially injected trace flags are still
7196 * filtered out.
7197 */
7198 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7199
7200 vcpu->guest_debug = dbg->control;
7201 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7202 vcpu->guest_debug = 0;
7203
7204 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7205 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7206 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7207 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7208 } else {
7209 for (i = 0; i < KVM_NR_DB_REGS; i++)
7210 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7211 }
c8639010 7212 kvm_update_dr7(vcpu);
ae675ef0 7213
f92653ee
JK		 7214 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7215 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7216 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7217
91586a3b
JK		 7218 /*
7219 * Trigger an rflags update that will inject or remove the trace
7220 * flags.
7221 */
7222 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7223
a96036b8 7224 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7225
4f926bf2 7226 r = 0;
d0bfb940 7227
2122ff5e 7228out:
b6c7a5dc
HB		 7229
7230 return r;
7231}
7232
8b006791
ZX		 7233/*
7234 * Translate a guest virtual address to a guest physical address.
7235 */
7236int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7237 struct kvm_translation *tr)
7238{
7239 unsigned long vaddr = tr->linear_address;
7240 gpa_t gpa;
f656ce01 7241 int idx;
8b006791 7242
f656ce01 7243 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7244 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7245 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7246 tr->physical_address = gpa;
7247 tr->valid = gpa != UNMAPPED_GVA;
7248 tr->writeable = 1;
7249 tr->usermode = 0;
8b006791
ZX		 7250
7251 return 0;
7252}
7253
d0752060
HB		 7254int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7255{
c47ada30 7256 struct fxregs_state *fxsave =
7366ed77 7257 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7258
d0752060
HB		 7259 memcpy(fpu->fpr, fxsave->st_space, 128);
7260 fpu->fcw = fxsave->cwd;
7261 fpu->fsw = fxsave->swd;
7262 fpu->ftwx = fxsave->twd;
7263 fpu->last_opcode = fxsave->fop;
7264 fpu->last_ip = fxsave->rip;
7265 fpu->last_dp = fxsave->rdp;
7266 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7267
d0752060
HB		 7268 return 0;
7269}
7270
7271int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7272{
c47ada30 7273 struct fxregs_state *fxsave =
7366ed77 7274 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7275
d0752060
HB		 7276 memcpy(fxsave->st_space, fpu->fpr, 128);
7277 fxsave->cwd = fpu->fcw;
7278 fxsave->swd = fpu->fsw;
7279 fxsave->twd = fpu->ftwx;
7280 fxsave->fop = fpu->last_opcode;
7281 fxsave->rip = fpu->last_ip;
7282 fxsave->rdp = fpu->last_dp;
7283 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7284
d0752060
HB		 7285 return 0;
7286}
7287
0ee6a517 7288static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7289{
bf935b0b 7290 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7291 if (cpu_has_xsaves)
7366ed77 7292 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7293 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7294
2acf923e
DC		 7295 /*
7296 * Ensure guest xcr0 is valid for loading
7297 */
d91cab78 7298 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7299
ad312c7c 7300 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7301}
d0752060
HB		 7302
7303void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7304{
2608d7a1 7305 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7306 return;
7307
2acf923e
DC		 7308 /*
7309 * Restore all possible states in the guest,
7310 * and assume host would use all available bits.
7311 * Guest xcr0 would be loaded later.
7312 */
7313 kvm_put_guest_xcr0(vcpu);
d0752060 7314 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7315 __kernel_fpu_begin();
003e2e8b 7316 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7317 trace_kvm_fpu(1);
d0752060 7318}
d0752060
HB		 7319
7320void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7321{
2acf923e
DC		 7322 kvm_put_guest_xcr0(vcpu);
7323
653f52c3
RR		 7324 if (!vcpu->guest_fpu_loaded) {
7325 vcpu->fpu_counter = 0;
d0752060 7326 return;
653f52c3 7327 }
d0752060
HB		 7328
7329 vcpu->guest_fpu_loaded = 0;
4f836347 7330 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7331 __kernel_fpu_end();
f096ed85 7332 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7333 /*
7334 * If using eager FPU mode, or if the guest is a frequent user
7335 * of the FPU, just leave the FPU active for next time.
7336 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7337 * the FPU in bursts will revert to loading it on demand.
7338 */
5a5fbdc0 7339 if (!use_eager_fpu()) {
653f52c3
RR		 7340 if (++vcpu->fpu_counter < 5)
7341 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7342 }
0c04851c 7343 trace_kvm_fpu(0);
d0752060 7344}
e9b11c17
ZX		 7345
7346void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7347{
12f9a48f 7348 kvmclock_reset(vcpu);
7f1ea208 7349
f5f48ee1 7350 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7351 kvm_x86_ops->vcpu_free(vcpu);
7352}
7353
7354struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7355 unsigned int id)
7356{
c447e76b
LL		 7357 struct kvm_vcpu *vcpu;
7358
6755bae8
ZA		 7359 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7360 printk_once(KERN_WARNING
7361 "kvm: SMP vm created on host with unstable TSC; "
7362 "guest TSC will not be reliable\n");
c447e76b
LL		 7363
7364 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7365
c447e76b 7366 return vcpu;
26e5215f 7367}
e9b11c17 7368
26e5215f
AK		 7369int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7370{
7371 int r;
e9b11c17 7372
19efffa2 7373 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7374 r = vcpu_load(vcpu);
7375 if (r)
7376 return r;
d28bc9dd 7377 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7378 kvm_mmu_setup(vcpu);
e9b11c17 7379 vcpu_put(vcpu);
26e5215f 7380 return r;
e9b11c17
ZX		 7381}
7382
31928aa5 7383void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7384{
8fe8ab46 7385 struct msr_data msr;
332967a3 7386 struct kvm *kvm = vcpu->kvm;
42897d86 7387
31928aa5
DD		 7388 if (vcpu_load(vcpu))
7389 return;
8fe8ab46
WA		 7390 msr.data = 0x0;
7391 msr.index = MSR_IA32_TSC;
7392 msr.host_initiated = true;
7393 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7394 vcpu_put(vcpu);
7395
630994b3
MT		 7396 if (!kvmclock_periodic_sync)
7397 return;
7398
332967a3
AJ		 7399 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7400 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7401}
7402
d40ccc62 7403void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7404{
9fc77441 7405 int r;
344d9588
GN		 7406 vcpu->arch.apf.msr_val = 0;
7407
9fc77441
MT		 7408 r = vcpu_load(vcpu);
7409 BUG_ON(r);
e9b11c17
ZX		 7410 kvm_mmu_unload(vcpu);
7411 vcpu_put(vcpu);
7412
7413 kvm_x86_ops->vcpu_free(vcpu);
7414}
7415
d28bc9dd 7416void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7417{
e69fab5d
PB		 7418 vcpu->arch.hflags = 0;
7419
7460fb4a
AK		 7420 atomic_set(&vcpu->arch.nmi_queued, 0);
7421 vcpu->arch.nmi_pending = 0;
448fa4a9 7422 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7423 kvm_clear_interrupt_queue(vcpu);
7424 kvm_clear_exception_queue(vcpu);
448fa4a9 7425
42dbaa5a 7426 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7427 kvm_update_dr0123(vcpu);
6f43ed01 7428 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7429 kvm_update_dr6(vcpu);
42dbaa5a 7430 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7431 kvm_update_dr7(vcpu);
42dbaa5a 7432
1119022c
NA		 7433 vcpu->arch.cr2 = 0;
7434
3842d135 7435 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7436 vcpu->arch.apf.msr_val = 0;
c9aaa895 7437 vcpu->arch.st.msr_val = 0;
3842d135 7438
12f9a48f
GC		 7439 kvmclock_reset(vcpu);
7440
af585b92
GN		 7441 kvm_clear_async_pf_completion_queue(vcpu);
7442 kvm_async_pf_hash_reset(vcpu);
7443 vcpu->arch.apf.halted = false;
3842d135 7444
64d60670 7445 if (!init_event) {
d28bc9dd 7446 kvm_pmu_reset(vcpu);
64d60670
PB		 7447 vcpu->arch.smbase = 0x30000;
7448 }
f5132b01 7449
66f7b72e
JS		 7450 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7451 vcpu->arch.regs_avail = ~0;
7452 vcpu->arch.regs_dirty = ~0;
7453
d28bc9dd 7454 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7455}
7456
2b4a273b 7457void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7458{
7459 struct kvm_segment cs;
7460
7461 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7462 cs.selector = vector << 8;
7463 cs.base = vector << 12;
7464 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7465 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7466}
7467
13a34e06 7468int kvm_arch_hardware_enable(void)
e9b11c17 7469{
ca84d1a2
ZA		 7470 struct kvm *kvm;
7471 struct kvm_vcpu *vcpu;
7472 int i;
0dd6a6ed
ZA		 7473 int ret;
7474 u64 local_tsc;
7475 u64 max_tsc = 0;
7476 bool stable, backwards_tsc = false;
18863bdd
AK		 7477
7478 kvm_shared_msr_cpu_online();
13a34e06 7479 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7480 if (ret != 0)
7481 return ret;
7482
4ea1636b 7483 local_tsc = rdtsc();
0dd6a6ed
ZA		 7484 stable = !check_tsc_unstable();
7485 list_for_each_entry(kvm, &vm_list, vm_list) {
7486 kvm_for_each_vcpu(i, vcpu, kvm) {
7487 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7488 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7489 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7490 backwards_tsc = true;
7491 if (vcpu->arch.last_host_tsc > max_tsc)
7492 max_tsc = vcpu->arch.last_host_tsc;
7493 }
7494 }
7495 }
7496
7497 /*
7498 * Sometimes, even reliable TSCs go backwards. This happens on
7499 * platforms that reset TSC during suspend or hibernate actions, but
7500 * maintain synchronization. We must compensate. Fortunately, we can
7501 * detect that condition here, which happens early in CPU bringup,
7502 * before any KVM threads can be running. Unfortunately, we can't
7503 * bring the TSCs fully up to date with real time, as we aren't yet far
7504 * enough into CPU bringup that we know how much real time has actually
7505 * elapsed; our helper function, get_kernel_ns() will be using boot
7506 * variables that haven't been updated yet.
7507 *
7508 * So we simply find the maximum observed TSC above, then record the
7509 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7510 * the adjustment will be applied. Note that we accumulate
7511 * adjustments, in case multiple suspend cycles happen before some VCPU
7512 * gets a chance to run again. In the event that no KVM threads get a
7513 * chance to run, we will miss the entire elapsed period, as we'll have
7514 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7515 * loose cycle time. This isn't too big a deal, since the loss will be
7516 * uniform across all VCPUs (not to mention the scenario is extremely
7517 * unlikely). It is possible that a second hibernate recovery happens
7518 * much faster than a first, causing the observed TSC here to be
7519 * smaller; this would require additional padding adjustment, which is
7520 * why we set last_host_tsc to the local tsc observed here.
7521 *
7522 * N.B. - this code below runs only on platforms with reliable TSC,
7523 * as that is the only way backwards_tsc is set above. Also note
7524 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7525 * have the same delta_cyc adjustment applied if backwards_tsc
7526 * is detected. Note further, this adjustment is only done once,
7527 * as we reset last_host_tsc on all VCPUs to stop this from being
7528 * called multiple times (one for each physical CPU bringup).
7529 *
4a969980 7530 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7531 * will be compensated by the logic in vcpu_load, which sets the TSC to
7532 * catchup mode. This will catchup all VCPUs to real time, but cannot
7533 * guarantee that they stay in perfect synchronization.
7534 */
7535 if (backwards_tsc) {
7536 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7537 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7538 list_for_each_entry(kvm, &vm_list, vm_list) {
7539 kvm_for_each_vcpu(i, vcpu, kvm) {
7540 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7541 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7542 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7543 }
7544
7545 /*
7546 * We have to disable TSC offset matching.. if you were
7547 * booting a VM while issuing an S4 host suspend....
7548 * you may have some problem. Solving this issue is
7549 * left as an exercise to the reader.
7550 */
7551 kvm->arch.last_tsc_nsec = 0;
7552 kvm->arch.last_tsc_write = 0;
7553 }
7554
7555 }
7556 return 0;
e9b11c17
ZX		 7557}
7558
13a34e06 7559void kvm_arch_hardware_disable(void)
e9b11c17 7560{
13a34e06
RK		 7561 kvm_x86_ops->hardware_disable();
7562 drop_user_return_notifiers();
e9b11c17
ZX		 7563}
7564
7565int kvm_arch_hardware_setup(void)
7566{
9e9c3fe4
NA		 7567 int r;
7568
7569 r = kvm_x86_ops->hardware_setup();
7570 if (r != 0)
7571 return r;
7572
35181e86
HZ		 7573 if (kvm_has_tsc_control) {
7574 /*
7575 * Make sure the user can only configure tsc_khz values that
7576 * fit into a signed integer.
7577 * A min value is not calculated needed because it will always
7578 * be 1 on all machines.
7579 */
7580 u64 max = min(0x7fffffffULL,
7581 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7582 kvm_max_guest_tsc_khz = max;
7583
ad721883 7584 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7585 }
ad721883 7586
9e9c3fe4
NA		 7587 kvm_init_msr_list();
7588 return 0;
e9b11c17
ZX		 7589}
7590
7591void kvm_arch_hardware_unsetup(void)
7592{
7593 kvm_x86_ops->hardware_unsetup();
7594}
7595
7596void kvm_arch_check_processor_compat(void *rtn)
7597{
7598 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7599}
7600
7601bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7602{
7603 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7604}
7605EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7606
7607bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7608{
7609 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7610}
7611
3e515705
AK		 7612bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7613{
35754c98 7614 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7615}
7616
54e9818f 7617struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7618EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7619
e9b11c17
ZX		 7620int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7621{
7622 struct page *page;
7623 struct kvm *kvm;
7624 int r;
7625
7626 BUG_ON(vcpu->kvm == NULL);
7627 kvm = vcpu->kvm;
7628
d62caabb 7629 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7630 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7631 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7632 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7633 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7634 else
a4535290 7635 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7636
7637 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7638 if (!page) {
7639 r = -ENOMEM;
7640 goto fail;
7641 }
ad312c7c 7642 vcpu->arch.pio_data = page_address(page);
e9b11c17 7643
cc578287 7644 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7645
e9b11c17
ZX		 7646 r = kvm_mmu_create(vcpu);
7647 if (r < 0)
7648 goto fail_free_pio_data;
7649
7650 if (irqchip_in_kernel(kvm)) {
7651 r = kvm_create_lapic(vcpu);
7652 if (r < 0)
7653 goto fail_mmu_destroy;
54e9818f
GN		 7654 } else
7655 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7656
890ca9ae
HY		 7657 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7658 GFP_KERNEL);
7659 if (!vcpu->arch.mce_banks) {
7660 r = -ENOMEM;
443c39bc 7661 goto fail_free_lapic;
890ca9ae
HY		 7662 }
7663 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7664
f1797359
WY		 7665 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7666 r = -ENOMEM;
f5f48ee1 7667 goto fail_free_mce_banks;
f1797359 7668 }
f5f48ee1 7669
0ee6a517 7670 fx_init(vcpu);
66f7b72e 7671
ba904635 7672 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7673 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7674
7675 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7676 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7677
5a4f55cd
EK		 7678 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7679
74545705
RK		 7680 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7681
af585b92 7682 kvm_async_pf_hash_reset(vcpu);
f5132b01 7683 kvm_pmu_init(vcpu);
af585b92 7684
1c1a9ce9
SR		 7685 vcpu->arch.pending_external_vector = -1;
7686
5c919412
AS		 7687 kvm_hv_vcpu_init(vcpu);
7688
e9b11c17 7689 return 0;
0ee6a517 7690
f5f48ee1
SY		 7691fail_free_mce_banks:
7692 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7693fail_free_lapic:
7694 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7695fail_mmu_destroy:
7696 kvm_mmu_destroy(vcpu);
7697fail_free_pio_data:
ad312c7c 7698 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7699fail:
7700 return r;
7701}
7702
7703void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7704{
f656ce01
MT		 7705 int idx;
7706
1f4b34f8 7707 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7708 kvm_pmu_destroy(vcpu);
36cb93fd 7709 kfree(vcpu->arch.mce_banks);
e9b11c17 7710 kvm_free_lapic(vcpu);
f656ce01 7711 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7712 kvm_mmu_destroy(vcpu);
f656ce01 7713 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7714 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7715 if (!lapic_in_kernel(vcpu))
54e9818f 7716 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7717}
d19a9cd2 7718
e790d9ef
RK		 7719void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7720{
ae97a3b8 7721 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7722}
7723
e08b9637 7724int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7725{
e08b9637
CO		 7726 if (type)
7727 return -EINVAL;
7728
6ef768fa 7729 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7730 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7731 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7732 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7733 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7734
5550af4d
SY		 7735 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7736 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7737 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7738 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7739 &kvm->arch.irq_sources_bitmap);
5550af4d 7740
038f8c11 7741 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7742 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7743 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7744
7745 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7746
7e44e449 7747 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7748 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7749
0eb05bf2 7750 kvm_page_track_init(kvm);
13d268ca 7751 kvm_mmu_init_vm(kvm);
0eb05bf2 7752
d89f5eff 7753 return 0;
d19a9cd2
ZX		 7754}
7755
7756static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7757{
9fc77441
MT		 7758 int r;
7759 r = vcpu_load(vcpu);
7760 BUG_ON(r);
d19a9cd2
ZX		 7761 kvm_mmu_unload(vcpu);
7762 vcpu_put(vcpu);
7763}
7764
7765static void kvm_free_vcpus(struct kvm *kvm)
7766{
7767 unsigned int i;
988a2cae 7768 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7769
7770 /*
7771 * Unpin any mmu pages first.
7772 */
af585b92
GN		 7773 kvm_for_each_vcpu(i, vcpu, kvm) {
7774 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7775 kvm_unload_vcpu_mmu(vcpu);
af585b92 7776 }
988a2cae
GN		 7777 kvm_for_each_vcpu(i, vcpu, kvm)
7778 kvm_arch_vcpu_free(vcpu);
7779
7780 mutex_lock(&kvm->lock);
7781 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7782 kvm->vcpus[i] = NULL;
d19a9cd2 7783
988a2cae
GN		 7784 atomic_set(&kvm->online_vcpus, 0);
7785 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7786}
7787
ad8ba2cd
SY		 7788void kvm_arch_sync_events(struct kvm *kvm)
7789{
332967a3 7790 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7791 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7792 kvm_free_all_assigned_devices(kvm);
aea924f6 7793 kvm_free_pit(kvm);
ad8ba2cd
SY		 7794}
7795
1d8007bd 7796int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7797{
7798 int i, r;
25188b99 7799 unsigned long hva;
f0d648bd
PB		 7800 struct kvm_memslots *slots = kvm_memslots(kvm);
7801 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7802
7803 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7804 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7805 return -EINVAL;
9da0e4d5 7806
f0d648bd
PB		 7807 slot = id_to_memslot(slots, id);
7808 if (size) {
7809 if (WARN_ON(slot->npages))
7810 return -EEXIST;
7811
7812 /*
7813 * MAP_SHARED to prevent internal slot pages from being moved
7814 * by fork()/COW.
7815 */
7816 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7817 MAP_SHARED | MAP_ANONYMOUS, 0);
7818 if (IS_ERR((void *)hva))
7819 return PTR_ERR((void *)hva);
7820 } else {
7821 if (!slot->npages)
7822 return 0;
7823
7824 hva = 0;
7825 }
7826
7827 old = *slot;
9da0e4d5 7828 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7829 struct kvm_userspace_memory_region m;
9da0e4d5 7830
1d8007bd
PB		 7831 m.slot = id | (i << 16);
7832 m.flags = 0;
7833 m.guest_phys_addr = gpa;
f0d648bd 7834 m.userspace_addr = hva;
1d8007bd 7835 m.memory_size = size;
9da0e4d5
PB		 7836 r = __kvm_set_memory_region(kvm, &m);
7837 if (r < 0)
7838 return r;
7839 }
7840
f0d648bd
PB		 7841 if (!size) {
7842 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7843 WARN_ON(r < 0);
7844 }
7845
9da0e4d5
PB		 7846 return 0;
7847}
7848EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7849
1d8007bd 7850int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7851{
7852 int r;
7853
7854 mutex_lock(&kvm->slots_lock);
1d8007bd 7855 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7856 mutex_unlock(&kvm->slots_lock);
7857
7858 return r;
7859}
7860EXPORT_SYMBOL_GPL(x86_set_memory_region);
7861
d19a9cd2
ZX		 7862void kvm_arch_destroy_vm(struct kvm *kvm)
7863{
27469d29
AH		 7864 if (current->mm == kvm->mm) {
7865 /*
7866 * Free memory regions allocated on behalf of userspace,
7867 * unless the the memory map has changed due to process exit
7868 * or fd copying.
7869 */
1d8007bd
PB		 7870 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7871 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7872 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7873 }
6eb55818 7874 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7875 kfree(kvm->arch.vpic);
7876 kfree(kvm->arch.vioapic);
d19a9cd2 7877 kvm_free_vcpus(kvm);
1e08ec4a 7878 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7879 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7880}
0de10343 7881
5587027c 7882void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7883 struct kvm_memory_slot *dont)
7884{
7885 int i;
7886
d89cc617
TY		 7887 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7888 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7889 kvfree(free->arch.rmap[i]);
d89cc617 7890 free->arch.rmap[i] = NULL;
77d11309 7891 }
d89cc617
TY		 7892 if (i == 0)
7893 continue;
7894
7895 if (!dont || free->arch.lpage_info[i - 1] !=
7896 dont->arch.lpage_info[i - 1]) {
548ef284 7897 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7898 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7899 }
7900 }
21ebbeda
XG		 7901
7902 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7903}
7904
5587027c
AK		 7905int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7906 unsigned long npages)
db3fe4eb
TY		 7907{
7908 int i;
7909
d89cc617 7910 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7911 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7912 unsigned long ugfn;
7913 int lpages;
d89cc617 7914 int level = i + 1;
db3fe4eb
TY		 7915
7916 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7917 slot->base_gfn, level) + 1;
7918
d89cc617
TY		 7919 slot->arch.rmap[i] =
7920 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7921 if (!slot->arch.rmap[i])
77d11309 7922 goto out_free;
d89cc617
TY		 7923 if (i == 0)
7924 continue;
77d11309 7925
92f94f1e
XG		 7926 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7927 if (!linfo)
db3fe4eb
TY		 7928 goto out_free;
7929
92f94f1e
XG		 7930 slot->arch.lpage_info[i - 1] = linfo;
7931
db3fe4eb 7932 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7933 linfo[0].disallow_lpage = 1;
db3fe4eb 7934 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7935 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7936 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7937 /*
7938 * If the gfn and userspace address are not aligned wrt each
7939 * other, or if explicitly asked to, disable large page
7940 * support for this slot
7941 */
7942 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7943 !kvm_largepages_enabled()) {
7944 unsigned long j;
7945
7946 for (j = 0; j < lpages; ++j)
92f94f1e 7947 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7948 }
7949 }
7950
21ebbeda
XG		 7951 if (kvm_page_track_create_memslot(slot, npages))
7952 goto out_free;
7953
db3fe4eb
TY		 7954 return 0;
7955
7956out_free:
d89cc617 7957 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7958 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7959 slot->arch.rmap[i] = NULL;
7960 if (i == 0)
7961 continue;
7962
548ef284 7963 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7964 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7965 }
7966 return -ENOMEM;
7967}
7968
15f46015 7969void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7970{
e6dff7d1
TY		 7971 /*
7972 * memslots->generation has been incremented.
7973 * mmio generation may have reached its maximum value.
7974 */
54bf36aa 7975 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7976}
7977
f7784b8e
MT		 7978int kvm_arch_prepare_memory_region(struct kvm *kvm,
7979 struct kvm_memory_slot *memslot,
09170a49 7980 const struct kvm_userspace_memory_region *mem,
7b6195a9 7981 enum kvm_mr_change change)
0de10343 7982{
f7784b8e
MT		 7983 return 0;
7984}
7985
88178fd4
KH		 7986static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7987 struct kvm_memory_slot *new)
7988{
7989 /* Still write protect RO slot */
7990 if (new->flags & KVM_MEM_READONLY) {
7991 kvm_mmu_slot_remove_write_access(kvm, new);
7992 return;
7993 }
7994
7995 /*
7996 * Call kvm_x86_ops dirty logging hooks when they are valid.
7997 *
7998 * kvm_x86_ops->slot_disable_log_dirty is called when:
7999 *
8000 * - KVM_MR_CREATE with dirty logging is disabled
8001 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8002 *
8003 * The reason is, in case of PML, we need to set D-bit for any slots
8004 * with dirty logging disabled in order to eliminate unnecessary GPA
8005 * logging in PML buffer (and potential PML buffer full VMEXT). This
8006 * guarantees leaving PML enabled during guest's lifetime won't have
8007 * any additonal overhead from PML when guest is running with dirty
8008 * logging disabled for memory slots.
8009 *
8010 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8011 * to dirty logging mode.
8012 *
8013 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8014 *
8015 * In case of write protect:
8016 *
8017 * Write protect all pages for dirty logging.
8018 *
8019 * All the sptes including the large sptes which point to this
8020 * slot are set to readonly. We can not create any new large
8021 * spte on this slot until the end of the logging.
8022 *
8023 * See the comments in fast_page_fault().
8024 */
8025 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8026 if (kvm_x86_ops->slot_enable_log_dirty)
8027 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8028 else
8029 kvm_mmu_slot_remove_write_access(kvm, new);
8030 } else {
8031 if (kvm_x86_ops->slot_disable_log_dirty)
8032 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8033 }
8034}
8035
f7784b8e 8036void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8037 const struct kvm_userspace_memory_region *mem,
8482644a 8038 const struct kvm_memory_slot *old,
f36f3f28 8039 const struct kvm_memory_slot *new,
8482644a 8040 enum kvm_mr_change change)
f7784b8e 8041{
8482644a 8042 int nr_mmu_pages = 0;
f7784b8e 8043
48c0e4e9
XG		 8044 if (!kvm->arch.n_requested_mmu_pages)
8045 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8046
48c0e4e9 8047 if (nr_mmu_pages)
0de10343 8048 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8049
3ea3b7fa
WL		 8050 /*
8051 * Dirty logging tracks sptes in 4k granularity, meaning that large
8052 * sptes have to be split. If live migration is successful, the guest
8053 * in the source machine will be destroyed and large sptes will be
8054 * created in the destination. However, if the guest continues to run
8055 * in the source machine (for example if live migration fails), small
8056 * sptes will remain around and cause bad performance.
8057 *
8058 * Scan sptes if dirty logging has been stopped, dropping those
8059 * which can be collapsed into a single large-page spte. Later
8060 * page faults will create the large-page sptes.
8061 */
8062 if ((change != KVM_MR_DELETE) &&
8063 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8064 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8065 kvm_mmu_zap_collapsible_sptes(kvm, new);
8066
c972f3b1 8067 /*
88178fd4 8068 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8069 *
88178fd4
KH		 8070 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8071 * been zapped so no dirty logging staff is needed for old slot. For
8072 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8073 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8074 *
8075 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8076 */
88178fd4 8077 if (change != KVM_MR_DELETE)
f36f3f28 8078 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8079}
1d737c8a 8080
2df72e9b 8081void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8082{
6ca18b69 8083 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8084}
8085
2df72e9b
MT		 8086void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8087 struct kvm_memory_slot *slot)
8088{
6ca18b69 8089 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8090}
8091
5d9bc648
PB		 8092static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8093{
8094 if (!list_empty_careful(&vcpu->async_pf.done))
8095 return true;
8096
8097 if (kvm_apic_has_events(vcpu))
8098 return true;
8099
8100 if (vcpu->arch.pv.pv_unhalted)
8101 return true;
8102
8103 if (atomic_read(&vcpu->arch.nmi_queued))
8104 return true;
8105
73917739
PB		 8106 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8107 return true;
8108
5d9bc648
PB		 8109 if (kvm_arch_interrupt_allowed(vcpu) &&
8110 kvm_cpu_has_interrupt(vcpu))
8111 return true;
8112
1f4b34f8
AS		 8113 if (kvm_hv_has_stimer_pending(vcpu))
8114 return true;
8115
5d9bc648
PB		 8116 return false;
8117}
8118
1d737c8a
ZX		 8119int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8120{
b6b8a145
JK		 8121 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8122 kvm_x86_ops->check_nested_events(vcpu, false);
8123
5d9bc648 8124 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8125}
5736199a 8126
b6d33834 8127int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8128{
b6d33834 8129 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8130}
78646121
GN		 8131
8132int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8133{
8134 return kvm_x86_ops->interrupt_allowed(vcpu);
8135}
229456fc 8136
82b32774 8137unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8138{
82b32774
NA		 8139 if (is_64_bit_mode(vcpu))
8140 return kvm_rip_read(vcpu);
8141 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8142 kvm_rip_read(vcpu));
8143}
8144EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8145
82b32774
NA		 8146bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8147{
8148 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8149}
8150EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8151
94fe45da
JK		 8152unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8153{
8154 unsigned long rflags;
8155
8156 rflags = kvm_x86_ops->get_rflags(vcpu);
8157 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8158 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8159 return rflags;
8160}
8161EXPORT_SYMBOL_GPL(kvm_get_rflags);
8162
6addfc42 8163static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8164{
8165 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8166 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8167 rflags |= X86_EFLAGS_TF;
94fe45da 8168 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8169}
8170
8171void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8172{
8173 __kvm_set_rflags(vcpu, rflags);
3842d135 8174 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8175}
8176EXPORT_SYMBOL_GPL(kvm_set_rflags);
8177
56028d08
GN		 8178void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8179{
8180 int r;
8181
fb67e14f 8182 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8183 work->wakeup_all)
56028d08
GN		 8184 return;
8185
8186 r = kvm_mmu_reload(vcpu);
8187 if (unlikely(r))
8188 return;
8189
fb67e14f
XG		 8190 if (!vcpu->arch.mmu.direct_map &&
8191 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8192 return;
8193
56028d08
GN		 8194 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8195}
8196
af585b92
GN		 8197static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8198{
8199 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8200}
8201
8202static inline u32 kvm_async_pf_next_probe(u32 key)
8203{
8204 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8205}
8206
8207static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8208{
8209 u32 key = kvm_async_pf_hash_fn(gfn);
8210
8211 while (vcpu->arch.apf.gfns[key] != ~0)
8212 key = kvm_async_pf_next_probe(key);
8213
8214 vcpu->arch.apf.gfns[key] = gfn;
8215}
8216
8217static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8218{
8219 int i;
8220 u32 key = kvm_async_pf_hash_fn(gfn);
8221
8222 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8223 (vcpu->arch.apf.gfns[key] != gfn &&
8224 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8225 key = kvm_async_pf_next_probe(key);
8226
8227 return key;
8228}
8229
8230bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8231{
8232 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8233}
8234
8235static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8236{
8237 u32 i, j, k;
8238
8239 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8240 while (true) {
8241 vcpu->arch.apf.gfns[i] = ~0;
8242 do {
8243 j = kvm_async_pf_next_probe(j);
8244 if (vcpu->arch.apf.gfns[j] == ~0)
8245 return;
8246 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8247 /*
8248 * k lies cyclically in ]i,j]
8249 * | i.k.j |
8250 * |....j i.k.| or |.k..j i...|
8251 */
8252 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8253 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8254 i = j;
8255 }
8256}
8257
7c90705b
GN		 8258static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8259{
8260
8261 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8262 sizeof(val));
8263}
8264
af585b92
GN		 8265void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8266 struct kvm_async_pf *work)
8267{
6389ee94
AK		 8268 struct x86_exception fault;
8269
7c90705b 8270 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8271 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8272
8273 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8274 (vcpu->arch.apf.send_user_only &&
8275 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8276 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8277 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8278 fault.vector = PF_VECTOR;
8279 fault.error_code_valid = true;
8280 fault.error_code = 0;
8281 fault.nested_page_fault = false;
8282 fault.address = work->arch.token;
8283 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8284 }
af585b92
GN		 8285}
8286
8287void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8288 struct kvm_async_pf *work)
8289{
6389ee94
AK		 8290 struct x86_exception fault;
8291
7c90705b 8292 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8293 if (work->wakeup_all)
7c90705b
GN		 8294 work->arch.token = ~0; /* broadcast wakeup */
8295 else
8296 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8297
8298 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8299 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8300 fault.vector = PF_VECTOR;
8301 fault.error_code_valid = true;
8302 fault.error_code = 0;
8303 fault.nested_page_fault = false;
8304 fault.address = work->arch.token;
8305 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8306 }
e6d53e3b 8307 vcpu->arch.apf.halted = false;
a4fa1635 8308 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8309}
8310
8311bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8312{
8313 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8314 return true;
8315 else
8316 return !kvm_event_needs_reinjection(vcpu) &&
8317 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8318}
8319
5544eb9b
PB		 8320void kvm_arch_start_assignment(struct kvm *kvm)
8321{
8322 atomic_inc(&kvm->arch.assigned_device_count);
8323}
8324EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8325
8326void kvm_arch_end_assignment(struct kvm *kvm)
8327{
8328 atomic_dec(&kvm->arch.assigned_device_count);
8329}
8330EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8331
8332bool kvm_arch_has_assigned_device(struct kvm *kvm)
8333{
8334 return atomic_read(&kvm->arch.assigned_device_count);
8335}
8336EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8337
e0f0bbc5
AW		 8338void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8339{
8340 atomic_inc(&kvm->arch.noncoherent_dma_count);
8341}
8342EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8343
8344void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8345{
8346 atomic_dec(&kvm->arch.noncoherent_dma_count);
8347}
8348EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8349
8350bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8351{
8352 return atomic_read(&kvm->arch.noncoherent_dma_count);
8353}
8354EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8355
87276880
FW		 8356int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8357 struct irq_bypass_producer *prod)
8358{
8359 struct kvm_kernel_irqfd *irqfd =
8360 container_of(cons, struct kvm_kernel_irqfd, consumer);
8361
8362 if (kvm_x86_ops->update_pi_irte) {
8363 irqfd->producer = prod;
8364 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8365 prod->irq, irqfd->gsi, 1);
8366 }
8367
8368 return -EINVAL;
8369}
8370
8371void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8372 struct irq_bypass_producer *prod)
8373{
8374 int ret;
8375 struct kvm_kernel_irqfd *irqfd =
8376 container_of(cons, struct kvm_kernel_irqfd, consumer);
8377
8378 if (!kvm_x86_ops->update_pi_irte) {
8379 WARN_ON(irqfd->producer != NULL);
8380 return;
8381 }
8382
8383 WARN_ON(irqfd->producer != prod);
8384 irqfd->producer = NULL;
8385
8386 /*
8387 * When producer of consumer is unregistered, we change back to
8388 * remapped mode, so we can re-use the current implementation
8389 * when the irq is masked/disabed or the consumer side (KVM
8390 * int this case doesn't want to receive the interrupts.
8391 */
8392 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8393 if (ret)
8394 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8395 " fails: %d\n", irqfd->consumer.token, ret);
8396}
8397
8398int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8399 uint32_t guest_irq, bool set)
8400{
8401 if (!kvm_x86_ops->update_pi_irte)
8402 return -EINVAL;
8403
8404 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8405}
8406
52004014
FW		 8407bool kvm_vector_hashing_enabled(void)
8408{
8409 return vector_hashing;
8410}
8411EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8412
229456fc 8413EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8414EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8415EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8416EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8417EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8418EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8419EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8420EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8421EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8422EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8423EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8424EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8425EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8426EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8427EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8428EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8429EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
Linux 6.x block layer and io_uring tree(s)