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KVM: x86: handle hardware breakpoints during emulation
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 123static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
af585b92
GN		 165static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166{
167 int i;
168 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169 vcpu->arch.apf.gfns[i] = ~0;
170}
171
18863bdd
AK		 172static void kvm_on_user_return(struct user_return_notifier *urn)
173{
174 unsigned slot;
18863bdd
AK		 175 struct kvm_shared_msrs *locals
176 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 177 struct kvm_shared_msr_values *values;
18863bdd
AK		 178
179 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 180 values = &locals->values[slot];
181 if (values->host != values->curr) {
182 wrmsrl(shared_msrs_global.msrs[slot], values->host);
183 values->curr = values->host;
18863bdd
AK		 184 }
185 }
186 locals->registered = false;
187 user_return_notifier_unregister(urn);
188}
189
2bf78fa7 190static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 191{
18863bdd 192 u64 value;
013f6a5d
MT		 193 unsigned int cpu = smp_processor_id();
194 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 195
2bf78fa7
SY		 196 /* only read, and nobody should modify it at this time,
197 * so don't need lock */
198 if (slot >= shared_msrs_global.nr) {
199 printk(KERN_ERR "kvm: invalid MSR slot!");
200 return;
201 }
202 rdmsrl_safe(msr, &value);
203 smsr->values[slot].host = value;
204 smsr->values[slot].curr = value;
205}
206
207void kvm_define_shared_msr(unsigned slot, u32 msr)
208{
18863bdd
AK		 209 if (slot >= shared_msrs_global.nr)
210 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 211 shared_msrs_global.msrs[slot] = msr;
212 /* we need ensured the shared_msr_global have been updated */
213 smp_wmb();
18863bdd
AK		 214}
215EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
216
217static void kvm_shared_msr_cpu_online(void)
218{
219 unsigned i;
18863bdd
AK		 220
221 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 222 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 223}
224
d5696725 225void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 226{
013f6a5d
MT		 227 unsigned int cpu = smp_processor_id();
228 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 229
2bf78fa7 230 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 231 return;
2bf78fa7
SY		 232 smsr->values[slot].curr = value;
233 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 234 if (!smsr->registered) {
235 smsr->urn.on_user_return = kvm_on_user_return;
236 user_return_notifier_register(&smsr->urn);
237 smsr->registered = true;
238 }
239}
240EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
241
3548bab5
AK		 242static void drop_user_return_notifiers(void *ignore)
243{
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249}
250
6866b83e
CO		 251u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252{
8a5a87d9 253 return vcpu->arch.apic_base;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258{
259 /* TODO: reserve bits check */
8a5a87d9 260 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
e3ba45b8
GL		 264asmlinkage void kvm_spurious_fault(void)
265{
266 /* Fault while not rebooting. We want the trace. */
267 BUG();
268}
269EXPORT_SYMBOL_GPL(kvm_spurious_fault);
270
3fd28fce
ED		 271#define EXCPT_BENIGN 0
272#define EXCPT_CONTRIBUTORY 1
273#define EXCPT_PF 2
274
275static int exception_class(int vector)
276{
277 switch (vector) {
278 case PF_VECTOR:
279 return EXCPT_PF;
280 case DE_VECTOR:
281 case TS_VECTOR:
282 case NP_VECTOR:
283 case SS_VECTOR:
284 case GP_VECTOR:
285 return EXCPT_CONTRIBUTORY;
286 default:
287 break;
288 }
289 return EXCPT_BENIGN;
290}
291
292static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 293 unsigned nr, bool has_error, u32 error_code,
294 bool reinject)
3fd28fce
ED		 295{
296 u32 prev_nr;
297 int class1, class2;
298
3842d135
AK		 299 kvm_make_request(KVM_REQ_EVENT, vcpu);
300
3fd28fce
ED		 301 if (!vcpu->arch.exception.pending) {
302 queue:
303 vcpu->arch.exception.pending = true;
304 vcpu->arch.exception.has_error_code = has_error;
305 vcpu->arch.exception.nr = nr;
306 vcpu->arch.exception.error_code = error_code;
3f0fd292 307 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 308 return;
309 }
310
311 /* to check exception */
312 prev_nr = vcpu->arch.exception.nr;
313 if (prev_nr == DF_VECTOR) {
314 /* triple fault -> shutdown */
a8eeb04a 315 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 316 return;
317 }
318 class1 = exception_class(prev_nr);
319 class2 = exception_class(nr);
320 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
321 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
322 /* generate double fault per SDM Table 5-5 */
323 vcpu->arch.exception.pending = true;
324 vcpu->arch.exception.has_error_code = true;
325 vcpu->arch.exception.nr = DF_VECTOR;
326 vcpu->arch.exception.error_code = 0;
327 } else
328 /* replace previous exception with a new one in a hope
329 that instruction re-execution will regenerate lost
330 exception */
331 goto queue;
332}
333
298101da
AK		 334void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335{
ce7ddec4 336 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 337}
338EXPORT_SYMBOL_GPL(kvm_queue_exception);
339
ce7ddec4
JR		 340void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
341{
342 kvm_multiple_exception(vcpu, nr, false, 0, true);
343}
344EXPORT_SYMBOL_GPL(kvm_requeue_exception);
345
db8fcefa 346void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 347{
db8fcefa
AP		 348 if (err)
349 kvm_inject_gp(vcpu, 0);
350 else
351 kvm_x86_ops->skip_emulated_instruction(vcpu);
352}
353EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 354
6389ee94 355void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 356{
357 ++vcpu->stat.pf_guest;
6389ee94
AK		 358 vcpu->arch.cr2 = fault->address;
359 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 360}
27d6c865 361EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 362
6389ee94 363void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 364{
6389ee94
AK		 365 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
366 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 367 else
6389ee94 368 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 369}
370
3419ffc8
SY		 371void kvm_inject_nmi(struct kvm_vcpu *vcpu)
372{
7460fb4a
AK		 373 atomic_inc(&vcpu->arch.nmi_queued);
374 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 375}
376EXPORT_SYMBOL_GPL(kvm_inject_nmi);
377
298101da
AK		 378void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379{
ce7ddec4 380 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 381}
382EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
383
ce7ddec4
JR		 384void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
385{
386 kvm_multiple_exception(vcpu, nr, true, error_code, true);
387}
388EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
389
0a79b009
AK		 390/*
391 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
392 * a #GP and return false.
393 */
394bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 395{
0a79b009
AK		 396 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
397 return true;
398 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
399 return false;
298101da 400}
0a79b009 401EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 402
ec92fe44
JR		 403/*
404 * This function will be used to read from the physical memory of the currently
405 * running guest. The difference to kvm_read_guest_page is that this function
406 * can read from guest physical or from the guest's guest physical memory.
407 */
408int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
409 gfn_t ngfn, void *data, int offset, int len,
410 u32 access)
411{
412 gfn_t real_gfn;
413 gpa_t ngpa;
414
415 ngpa = gfn_to_gpa(ngfn);
416 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
417 if (real_gfn == UNMAPPED_GVA)
418 return -EFAULT;
419
420 real_gfn = gpa_to_gfn(real_gfn);
421
422 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
423}
424EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
425
3d06b8bf
JR		 426int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
427 void *data, int offset, int len, u32 access)
428{
429 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
430 data, offset, len, access);
431}
432
a03490ed
CO		 433/*
434 * Load the pae pdptrs. Return true is they are all valid.
435 */
ff03a073 436int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 437{
438 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
439 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
440 int i;
441 int ret;
ff03a073 442 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 443
ff03a073
JR		 444 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
445 offset * sizeof(u64), sizeof(pdpte),
446 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 447 if (ret < 0) {
448 ret = 0;
449 goto out;
450 }
451 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 452 if (is_present_gpte(pdpte[i]) &&
20c466b5 453 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 454 ret = 0;
455 goto out;
456 }
457 }
458 ret = 1;
459
ff03a073 460 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 461 __set_bit(VCPU_EXREG_PDPTR,
462 (unsigned long *)&vcpu->arch.regs_avail);
463 __set_bit(VCPU_EXREG_PDPTR,
464 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 465out:
a03490ed
CO		 466
467 return ret;
468}
cc4b6871 469EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 470
d835dfec
AK		 471static bool pdptrs_changed(struct kvm_vcpu *vcpu)
472{
ff03a073 473 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 474 bool changed = true;
3d06b8bf
JR		 475 int offset;
476 gfn_t gfn;
d835dfec
AK		 477 int r;
478
479 if (is_long_mode(vcpu) || !is_pae(vcpu))
480 return false;
481
6de4f3ad
AK		 482 if (!test_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail))
484 return true;
485
9f8fe504
AK		 486 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
487 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 488 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
489 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 490 if (r < 0)
491 goto out;
ff03a073 492 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 493out:
d835dfec
AK		 494
495 return changed;
496}
497
49a9b07e 498int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 499{
aad82703
SY		 500 unsigned long old_cr0 = kvm_read_cr0(vcpu);
501 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
502 X86_CR0_CD | X86_CR0_NW;
503
f9a48e6a
AK		 504 cr0 |= X86_CR0_ET;
505
ab344828 506#ifdef CONFIG_X86_64
0f12244f
GN		 507 if (cr0 & 0xffffffff00000000UL)
508 return 1;
ab344828
GN		 509#endif
510
511 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 512
0f12244f
GN		 513 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
514 return 1;
a03490ed 515
0f12244f
GN		 516 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
517 return 1;
a03490ed
CO		 518
519 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
520#ifdef CONFIG_X86_64
f6801dff 521 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 522 int cs_db, cs_l;
523
0f12244f
GN		 524 if (!is_pae(vcpu))
525 return 1;
a03490ed 526 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 527 if (cs_l)
528 return 1;
a03490ed
CO		 529 } else
530#endif
ff03a073 531 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 532 kvm_read_cr3(vcpu)))
0f12244f 533 return 1;
a03490ed
CO		 534 }
535
ad756a16
MJ		 536 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
537 return 1;
538
a03490ed 539 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 540
d170c419 541 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 542 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 543 kvm_async_pf_hash_reset(vcpu);
544 }
e5f3f027 545
aad82703
SY		 546 if ((cr0 ^ old_cr0) & update_bits)
547 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 548 return 0;
549}
2d3ad1f4 550EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 551
2d3ad1f4 552void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 553{
49a9b07e 554 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 555}
2d3ad1f4 556EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 557
42bdf991
MT		 558static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
559{
560 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
561 !vcpu->guest_xcr0_loaded) {
562 /* kvm_set_xcr() also depends on this */
563 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
564 vcpu->guest_xcr0_loaded = 1;
565 }
566}
567
568static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
569{
570 if (vcpu->guest_xcr0_loaded) {
571 if (vcpu->arch.xcr0 != host_xcr0)
572 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
573 vcpu->guest_xcr0_loaded = 0;
574 }
575}
576
2acf923e
DC		 577int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
578{
579 u64 xcr0;
580
581 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
582 if (index != XCR_XFEATURE_ENABLED_MASK)
583 return 1;
584 xcr0 = xcr;
2acf923e
DC		 585 if (!(xcr0 & XSTATE_FP))
586 return 1;
587 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
588 return 1;
589 if (xcr0 & ~host_xcr0)
590 return 1;
42bdf991 591 kvm_put_guest_xcr0(vcpu);
2acf923e 592 vcpu->arch.xcr0 = xcr0;
2acf923e
DC		 593 return 0;
594}
595
596int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
764bcbc5
Z		 598 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
599 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 600 kvm_inject_gp(vcpu, 0);
601 return 1;
602 }
603 return 0;
604}
605EXPORT_SYMBOL_GPL(kvm_set_xcr);
606
a83b29c6 607int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 608{
fc78f519 609 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 610 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
611 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 612 if (cr4 & CR4_RESERVED_BITS)
613 return 1;
a03490ed 614
2acf923e
DC		 615 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
616 return 1;
617
c68b734f
YW		 618 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
619 return 1;
620
afcbf13f 621 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 622 return 1;
623
a03490ed 624 if (is_long_mode(vcpu)) {
0f12244f
GN		 625 if (!(cr4 & X86_CR4_PAE))
626 return 1;
a2edf57f
AK		 627 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
628 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 629 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
630 kvm_read_cr3(vcpu)))
0f12244f
GN		 631 return 1;
632
ad756a16
MJ		 633 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
634 if (!guest_cpuid_has_pcid(vcpu))
635 return 1;
636
637 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
638 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
639 return 1;
640 }
641
5e1746d6 642 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 643 return 1;
a03490ed 644
ad756a16
MJ		 645 if (((cr4 ^ old_cr4) & pdptr_bits) ||
646 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 647 kvm_mmu_reset_context(vcpu);
0f12244f 648
2acf923e 649 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 650 kvm_update_cpuid(vcpu);
2acf923e 651
0f12244f
GN		 652 return 0;
653}
2d3ad1f4 654EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 655
2390218b 656int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 657{
9f8fe504 658 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 659 kvm_mmu_sync_roots(vcpu);
d835dfec 660 kvm_mmu_flush_tlb(vcpu);
0f12244f 661 return 0;
d835dfec
AK		 662 }
663
a03490ed 664 if (is_long_mode(vcpu)) {
471842ec 665 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 666 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
667 return 1;
668 } else
669 if (cr3 & CR3_L_MODE_RESERVED_BITS)
670 return 1;
a03490ed
CO		 671 } else {
672 if (is_pae(vcpu)) {
0f12244f
GN		 673 if (cr3 & CR3_PAE_RESERVED_BITS)
674 return 1;
ff03a073
JR		 675 if (is_paging(vcpu) &&
676 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 677 return 1;
a03490ed
CO		 678 }
679 /*
680 * We don't check reserved bits in nonpae mode, because
681 * this isn't enforced, and VMware depends on this.
682 */
683 }
684
a03490ed
CO		 685 /*
686 * Does the new cr3 value map to physical memory? (Note, we
687 * catch an invalid cr3 even in real-mode, because it would
688 * cause trouble later on when we turn on paging anyway.)
689 *
690 * A real CPU would silently accept an invalid cr3 and would
691 * attempt to use it - with largely undefined (and often hard
692 * to debug) behavior on the guest side.
693 */
694 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 695 return 1;
696 vcpu->arch.cr3 = cr3;
aff48baa 697 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 698 vcpu->arch.mmu.new_cr3(vcpu);
699 return 0;
700}
2d3ad1f4 701EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 702
eea1cff9 703int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 704{
0f12244f
GN		 705 if (cr8 & CR8_RESERVED_BITS)
706 return 1;
a03490ed
CO		 707 if (irqchip_in_kernel(vcpu->kvm))
708 kvm_lapic_set_tpr(vcpu, cr8);
709 else
ad312c7c 710 vcpu->arch.cr8 = cr8;
0f12244f
GN		 711 return 0;
712}
2d3ad1f4 713EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 714
2d3ad1f4 715unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 716{
717 if (irqchip_in_kernel(vcpu->kvm))
718 return kvm_lapic_get_cr8(vcpu);
719 else
ad312c7c 720 return vcpu->arch.cr8;
a03490ed 721}
2d3ad1f4 722EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 723
c8639010
JK		 724static void kvm_update_dr7(struct kvm_vcpu *vcpu)
725{
726 unsigned long dr7;
727
728 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
729 dr7 = vcpu->arch.guest_debug_dr7;
730 else
731 dr7 = vcpu->arch.dr7;
732 kvm_x86_ops->set_dr7(vcpu, dr7);
733 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
734}
735
338dbc97 736static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 737{
738 switch (dr) {
739 case 0 ... 3:
740 vcpu->arch.db[dr] = val;
741 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
742 vcpu->arch.eff_db[dr] = val;
743 break;
744 case 4:
338dbc97
GN		 745 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
746 return 1; /* #UD */
020df079
GN		 747 /* fall through */
748 case 6:
338dbc97
GN		 749 if (val & 0xffffffff00000000ULL)
750 return -1; /* #GP */
020df079
GN		 751 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
752 break;
753 case 5:
338dbc97
GN		 754 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
755 return 1; /* #UD */
020df079
GN		 756 /* fall through */
757 default: /* 7 */
338dbc97
GN		 758 if (val & 0xffffffff00000000ULL)
759 return -1; /* #GP */
020df079 760 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 761 kvm_update_dr7(vcpu);
020df079
GN		 762 break;
763 }
764
765 return 0;
766}
338dbc97
GN		 767
768int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
769{
770 int res;
771
772 res = __kvm_set_dr(vcpu, dr, val);
773 if (res > 0)
774 kvm_queue_exception(vcpu, UD_VECTOR);
775 else if (res < 0)
776 kvm_inject_gp(vcpu, 0);
777
778 return res;
779}
020df079
GN		 780EXPORT_SYMBOL_GPL(kvm_set_dr);
781
338dbc97 782static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 783{
784 switch (dr) {
785 case 0 ... 3:
786 *val = vcpu->arch.db[dr];
787 break;
788 case 4:
338dbc97 789 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 790 return 1;
020df079
GN		 791 /* fall through */
792 case 6:
793 *val = vcpu->arch.dr6;
794 break;
795 case 5:
338dbc97 796 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 797 return 1;
020df079
GN		 798 /* fall through */
799 default: /* 7 */
800 *val = vcpu->arch.dr7;
801 break;
802 }
803
804 return 0;
805}
338dbc97
GN		 806
807int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
808{
809 if (_kvm_get_dr(vcpu, dr, val)) {
810 kvm_queue_exception(vcpu, UD_VECTOR);
811 return 1;
812 }
813 return 0;
814}
020df079
GN		 815EXPORT_SYMBOL_GPL(kvm_get_dr);
816
022cd0e8
AK		 817bool kvm_rdpmc(struct kvm_vcpu *vcpu)
818{
819 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
820 u64 data;
821 int err;
822
823 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
824 if (err)
825 return err;
826 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
827 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
828 return err;
829}
830EXPORT_SYMBOL_GPL(kvm_rdpmc);
831
043405e1
CO		 832/*
833 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
834 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
835 *
836 * This list is modified at module load time to reflect the
e3267cbb
GC		 837 * capabilities of the host cpu. This capabilities test skips MSRs that are
838 * kvm-specific. Those are put in the beginning of the list.
043405e1 839 */
e3267cbb 840
439793d4 841#define KVM_SAVE_MSRS_BEGIN 10
043405e1 842static u32 msrs_to_save[] = {
e3267cbb 843 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 844 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 845 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 846 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 847 MSR_KVM_PV_EOI_EN,
043405e1 848 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 849 MSR_STAR,
043405e1
CO		 850#ifdef CONFIG_X86_64
851 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
852#endif
b3897a49
NHE		 853 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
854 MSR_IA32_FEATURE_CONTROL
043405e1
CO		 855};
856
857static unsigned num_msrs_to_save;
858
f1d24831 859static const u32 emulated_msrs[] = {
ba904635 860 MSR_IA32_TSC_ADJUST,
a3e06bbe 861 MSR_IA32_TSCDEADLINE,
043405e1 862 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 863 MSR_IA32_MCG_STATUS,
864 MSR_IA32_MCG_CTL,
043405e1
CO		 865};
866
384bb783 867bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 868{
b69e8cae 869 if (efer & efer_reserved_bits)
384bb783 870 return false;
15c4a640 871
1b2fd70c
AG		 872 if (efer & EFER_FFXSR) {
873 struct kvm_cpuid_entry2 *feat;
874
875 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 876 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 877 return false;
1b2fd70c
AG		 878 }
879
d8017474
AG		 880 if (efer & EFER_SVME) {
881 struct kvm_cpuid_entry2 *feat;
882
883 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 884 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 885 return false;
d8017474
AG		 886 }
887
384bb783
JK		 888 return true;
889}
890EXPORT_SYMBOL_GPL(kvm_valid_efer);
891
892static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
893{
894 u64 old_efer = vcpu->arch.efer;
895
896 if (!kvm_valid_efer(vcpu, efer))
897 return 1;
898
899 if (is_paging(vcpu)
900 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
901 return 1;
902
15c4a640 903 efer &= ~EFER_LMA;
f6801dff 904 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 905
a3d204e2
SY		 906 kvm_x86_ops->set_efer(vcpu, efer);
907
aad82703
SY		 908 /* Update reserved bits */
909 if ((efer ^ old_efer) & EFER_NX)
910 kvm_mmu_reset_context(vcpu);
911
b69e8cae 912 return 0;
15c4a640
CO		 913}
914
f2b4b7dd
JR		 915void kvm_enable_efer_bits(u64 mask)
916{
917 efer_reserved_bits &= ~mask;
918}
919EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
920
921
15c4a640
CO		 922/*
923 * Writes msr value into into the appropriate "register".
924 * Returns 0 on success, non-0 otherwise.
925 * Assumes vcpu_load() was already called.
926 */
8fe8ab46 927int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 928{
8fe8ab46 929 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 930}
931
313a3dc7
CO		 932/*
933 * Adapt set_msr() to msr_io()'s calling convention
934 */
935static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
936{
8fe8ab46
WA		 937 struct msr_data msr;
938
939 msr.data = *data;
940 msr.index = index;
941 msr.host_initiated = true;
942 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 943}
944
16e8d74d
MT		 945#ifdef CONFIG_X86_64
946struct pvclock_gtod_data {
947 seqcount_t seq;
948
949 struct { /* extract of a clocksource struct */
950 int vclock_mode;
951 cycle_t cycle_last;
952 cycle_t mask;
953 u32 mult;
954 u32 shift;
955 } clock;
956
957 /* open coded 'struct timespec' */
958 u64 monotonic_time_snsec;
959 time_t monotonic_time_sec;
960};
961
962static struct pvclock_gtod_data pvclock_gtod_data;
963
964static void update_pvclock_gtod(struct timekeeper *tk)
965{
966 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
967
968 write_seqcount_begin(&vdata->seq);
969
970 /* copy pvclock gtod data */
971 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
972 vdata->clock.cycle_last = tk->clock->cycle_last;
973 vdata->clock.mask = tk->clock->mask;
974 vdata->clock.mult = tk->mult;
975 vdata->clock.shift = tk->shift;
976
977 vdata->monotonic_time_sec = tk->xtime_sec
978 + tk->wall_to_monotonic.tv_sec;
979 vdata->monotonic_time_snsec = tk->xtime_nsec
980 + (tk->wall_to_monotonic.tv_nsec
981 << tk->shift);
982 while (vdata->monotonic_time_snsec >=
983 (((u64)NSEC_PER_SEC) << tk->shift)) {
984 vdata->monotonic_time_snsec -=
985 ((u64)NSEC_PER_SEC) << tk->shift;
986 vdata->monotonic_time_sec++;
987 }
988
989 write_seqcount_end(&vdata->seq);
990}
991#endif
992
993
18068523
GOC		 994static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
995{
9ed3c444
AK		 996 int version;
997 int r;
50d0a0f9 998 struct pvclock_wall_clock wc;
923de3cf 999 struct timespec boot;
18068523
GOC		 1000
1001 if (!wall_clock)
1002 return;
1003
9ed3c444
AK		 1004 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1005 if (r)
1006 return;
1007
1008 if (version & 1)
1009 ++version; /* first time write, random junk */
1010
1011 ++version;
18068523 1012
18068523
GOC		 1013 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1014
50d0a0f9
GH		 1015 /*
1016 * The guest calculates current wall clock time by adding
34c238a1 1017 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1018 * wall clock specified here. guest system time equals host
1019 * system time for us, thus we must fill in host boot time here.
1020 */
923de3cf 1021 getboottime(&boot);
50d0a0f9 1022
4b648665
BR		 1023 if (kvm->arch.kvmclock_offset) {
1024 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1025 boot = timespec_sub(boot, ts);
1026 }
50d0a0f9
GH		 1027 wc.sec = boot.tv_sec;
1028 wc.nsec = boot.tv_nsec;
1029 wc.version = version;
18068523
GOC		 1030
1031 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1032
1033 version++;
1034 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1035}
1036
50d0a0f9
GH		 1037static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1038{
1039 uint32_t quotient, remainder;
1040
1041 /* Don't try to replace with do_div(), this one calculates
1042 * "(dividend << 32) / divisor" */
1043 __asm__ ( "divl %4"
1044 : "=a" (quotient), "=d" (remainder)
1045 : "0" (0), "1" (dividend), "r" (divisor) );
1046 return quotient;
1047}
1048
5f4e3f88
ZA		 1049static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1050 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1051{
5f4e3f88 1052 uint64_t scaled64;
50d0a0f9
GH		 1053 int32_t shift = 0;
1054 uint64_t tps64;
1055 uint32_t tps32;
1056
5f4e3f88
ZA		 1057 tps64 = base_khz * 1000LL;
1058 scaled64 = scaled_khz * 1000LL;
50933623 1059 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1060 tps64 >>= 1;
1061 shift--;
1062 }
1063
1064 tps32 = (uint32_t)tps64;
50933623
JK		 1065 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1066 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1067 scaled64 >>= 1;
1068 else
1069 tps32 <<= 1;
50d0a0f9
GH		 1070 shift++;
1071 }
1072
5f4e3f88
ZA		 1073 *pshift = shift;
1074 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1075
5f4e3f88
ZA		 1076 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1077 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1078}
1079
759379dd
ZA		 1080static inline u64 get_kernel_ns(void)
1081{
1082 struct timespec ts;
1083
1084 WARN_ON(preemptible());
1085 ktime_get_ts(&ts);
1086 monotonic_to_bootbased(&ts);
1087 return timespec_to_ns(&ts);
50d0a0f9
GH		 1088}
1089
d828199e 1090#ifdef CONFIG_X86_64
16e8d74d 1091static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1092#endif
16e8d74d 1093
c8076604 1094static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1095unsigned long max_tsc_khz;
c8076604 1096
cc578287 1097static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1098{
cc578287
ZA		 1099 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1100 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1101}
1102
cc578287 1103static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1104{
cc578287
ZA		 1105 u64 v = (u64)khz * (1000000 + ppm);
1106 do_div(v, 1000000);
1107 return v;
1e993611
JR		 1108}
1109
cc578287 1110static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1111{
cc578287
ZA		 1112 u32 thresh_lo, thresh_hi;
1113 int use_scaling = 0;
217fc9cf 1114
03ba32ca
MT		 1115 /* tsc_khz can be zero if TSC calibration fails */
1116 if (this_tsc_khz == 0)
1117 return;
1118
c285545f
ZA		 1119 /* Compute a scale to convert nanoseconds in TSC cycles */
1120 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1121 &vcpu->arch.virtual_tsc_shift,
1122 &vcpu->arch.virtual_tsc_mult);
1123 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1124
1125 /*
1126 * Compute the variation in TSC rate which is acceptable
1127 * within the range of tolerance and decide if the
1128 * rate being applied is within that bounds of the hardware
1129 * rate. If so, no scaling or compensation need be done.
1130 */
1131 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1132 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1133 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1134 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1135 use_scaling = 1;
1136 }
1137 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1138}
1139
1140static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1141{
e26101b1 1142 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1143 vcpu->arch.virtual_tsc_mult,
1144 vcpu->arch.virtual_tsc_shift);
e26101b1 1145 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1146 return tsc;
1147}
1148
b48aa97e
MT		 1149void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1150{
1151#ifdef CONFIG_X86_64
1152 bool vcpus_matched;
1153 bool do_request = false;
1154 struct kvm_arch *ka = &vcpu->kvm->arch;
1155 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1156
1157 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1158 atomic_read(&vcpu->kvm->online_vcpus));
1159
1160 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1161 if (!ka->use_master_clock)
1162 do_request = 1;
1163
1164 if (!vcpus_matched && ka->use_master_clock)
1165 do_request = 1;
1166
1167 if (do_request)
1168 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1169
1170 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1171 atomic_read(&vcpu->kvm->online_vcpus),
1172 ka->use_master_clock, gtod->clock.vclock_mode);
1173#endif
1174}
1175
ba904635
WA		 1176static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1177{
1178 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1179 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1180}
1181
8fe8ab46 1182void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1183{
1184 struct kvm *kvm = vcpu->kvm;
f38e098f 1185 u64 offset, ns, elapsed;
99e3e30a 1186 unsigned long flags;
02626b6a 1187 s64 usdiff;
b48aa97e 1188 bool matched;
8fe8ab46 1189 u64 data = msr->data;
99e3e30a 1190
038f8c11 1191 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1192 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1193 ns = get_kernel_ns();
f38e098f 1194 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1195
03ba32ca 1196 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1197 int faulted = 0;
1198
03ba32ca
MT		 1199 /* n.b - signed multiplication and division required */
1200 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1201#ifdef CONFIG_X86_64
03ba32ca 1202 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1203#else
03ba32ca 1204 /* do_div() only does unsigned */
8915aa27
MT		 1205 asm("1: idivl %[divisor]\n"
1206 "2: xor %%edx, %%edx\n"
1207 " movl $0, %[faulted]\n"
1208 "3:\n"
1209 ".section .fixup,\"ax\"\n"
1210 "4: movl $1, %[faulted]\n"
1211 " jmp 3b\n"
1212 ".previous\n"
1213
1214 _ASM_EXTABLE(1b, 4b)
1215
1216 : "=A"(usdiff), [faulted] "=r" (faulted)
1217 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1218
5d3cb0f6 1219#endif
03ba32ca
MT		 1220 do_div(elapsed, 1000);
1221 usdiff -= elapsed;
1222 if (usdiff < 0)
1223 usdiff = -usdiff;
8915aa27
MT		 1224
1225 /* idivl overflow => difference is larger than USEC_PER_SEC */
1226 if (faulted)
1227 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1228 } else
1229 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1230
1231 /*
5d3cb0f6
ZA		 1232 * Special case: TSC write with a small delta (1 second) of virtual
1233 * cycle time against real time is interpreted as an attempt to
1234 * synchronize the CPU.
1235 *
1236 * For a reliable TSC, we can match TSC offsets, and for an unstable
1237 * TSC, we add elapsed time in this computation. We could let the
1238 * compensation code attempt to catch up if we fall behind, but
1239 * it's better to try to match offsets from the beginning.
1240 */
02626b6a 1241 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1242 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1243 if (!check_tsc_unstable()) {
e26101b1 1244 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1245 pr_debug("kvm: matched tsc offset for %llu\n", data);
1246 } else {
857e4099 1247 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1248 data += delta;
1249 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1250 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1251 }
b48aa97e 1252 matched = true;
e26101b1
ZA		 1253 } else {
1254 /*
1255 * We split periods of matched TSC writes into generations.
1256 * For each generation, we track the original measured
1257 * nanosecond time, offset, and write, so if TSCs are in
1258 * sync, we can match exact offset, and if not, we can match
4a969980 1259 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1260 *
1261 * These values are tracked in kvm->arch.cur_xxx variables.
1262 */
1263 kvm->arch.cur_tsc_generation++;
1264 kvm->arch.cur_tsc_nsec = ns;
1265 kvm->arch.cur_tsc_write = data;
1266 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1267 matched = false;
e26101b1
ZA		 1268 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1269 kvm->arch.cur_tsc_generation, data);
f38e098f 1270 }
e26101b1
ZA		 1271
1272 /*
1273 * We also track th most recent recorded KHZ, write and time to
1274 * allow the matching interval to be extended at each write.
1275 */
f38e098f
ZA		 1276 kvm->arch.last_tsc_nsec = ns;
1277 kvm->arch.last_tsc_write = data;
5d3cb0f6 1278 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1279
1280 /* Reset of TSC must disable overshoot protection below */
1281 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1282 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1283
1284 /* Keep track of which generation this VCPU has synchronized to */
1285 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1286 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1287 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1288
ba904635
WA		 1289 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1290 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1291 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1292 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1293
1294 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1295 if (matched)
1296 kvm->arch.nr_vcpus_matched_tsc++;
1297 else
1298 kvm->arch.nr_vcpus_matched_tsc = 0;
1299
1300 kvm_track_tsc_matching(vcpu);
1301 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1302}
e26101b1 1303
99e3e30a
ZA		 1304EXPORT_SYMBOL_GPL(kvm_write_tsc);
1305
d828199e
MT		 1306#ifdef CONFIG_X86_64
1307
1308static cycle_t read_tsc(void)
1309{
1310 cycle_t ret;
1311 u64 last;
1312
1313 /*
1314 * Empirically, a fence (of type that depends on the CPU)
1315 * before rdtsc is enough to ensure that rdtsc is ordered
1316 * with respect to loads. The various CPU manuals are unclear
1317 * as to whether rdtsc can be reordered with later loads,
1318 * but no one has ever seen it happen.
1319 */
1320 rdtsc_barrier();
1321 ret = (cycle_t)vget_cycles();
1322
1323 last = pvclock_gtod_data.clock.cycle_last;
1324
1325 if (likely(ret >= last))
1326 return ret;
1327
1328 /*
1329 * GCC likes to generate cmov here, but this branch is extremely
1330 * predictable (it's just a funciton of time and the likely is
1331 * very likely) and there's a data dependence, so force GCC
1332 * to generate a branch instead. I don't barrier() because
1333 * we don't actually need a barrier, and if this function
1334 * ever gets inlined it will generate worse code.
1335 */
1336 asm volatile ("");
1337 return last;
1338}
1339
1340static inline u64 vgettsc(cycle_t *cycle_now)
1341{
1342 long v;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 *cycle_now = read_tsc();
1346
1347 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1348 return v * gtod->clock.mult;
1349}
1350
1351static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1352{
1353 unsigned long seq;
1354 u64 ns;
1355 int mode;
1356 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1357
1358 ts->tv_nsec = 0;
1359 do {
1360 seq = read_seqcount_begin(&gtod->seq);
1361 mode = gtod->clock.vclock_mode;
1362 ts->tv_sec = gtod->monotonic_time_sec;
1363 ns = gtod->monotonic_time_snsec;
1364 ns += vgettsc(cycle_now);
1365 ns >>= gtod->clock.shift;
1366 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1367 timespec_add_ns(ts, ns);
1368
1369 return mode;
1370}
1371
1372/* returns true if host is using tsc clocksource */
1373static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1374{
1375 struct timespec ts;
1376
1377 /* checked again under seqlock below */
1378 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1379 return false;
1380
1381 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1382 return false;
1383
1384 monotonic_to_bootbased(&ts);
1385 *kernel_ns = timespec_to_ns(&ts);
1386
1387 return true;
1388}
1389#endif
1390
1391/*
1392 *
b48aa97e
MT		 1393 * Assuming a stable TSC across physical CPUS, and a stable TSC
1394 * across virtual CPUs, the following condition is possible.
1395 * Each numbered line represents an event visible to both
d828199e
MT		 1396 * CPUs at the next numbered event.
1397 *
1398 * "timespecX" represents host monotonic time. "tscX" represents
1399 * RDTSC value.
1400 *
1401 * VCPU0 on CPU0 | VCPU1 on CPU1
1402 *
1403 * 1. read timespec0,tsc0
1404 * 2. | timespec1 = timespec0 + N
1405 * | tsc1 = tsc0 + M
1406 * 3. transition to guest | transition to guest
1407 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1408 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1409 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1410 *
1411 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1412 *
1413 * - ret0 < ret1
1414 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1415 * ...
1416 * - 0 < N - M => M < N
1417 *
1418 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1419 * always the case (the difference between two distinct xtime instances
1420 * might be smaller then the difference between corresponding TSC reads,
1421 * when updating guest vcpus pvclock areas).
1422 *
1423 * To avoid that problem, do not allow visibility of distinct
1424 * system_timestamp/tsc_timestamp values simultaneously: use a master
1425 * copy of host monotonic time values. Update that master copy
1426 * in lockstep.
1427 *
b48aa97e 1428 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1429 *
1430 */
1431
1432static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1433{
1434#ifdef CONFIG_X86_64
1435 struct kvm_arch *ka = &kvm->arch;
1436 int vclock_mode;
b48aa97e
MT		 1437 bool host_tsc_clocksource, vcpus_matched;
1438
1439 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1440 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1441
1442 /*
1443 * If the host uses TSC clock, then passthrough TSC as stable
1444 * to the guest.
1445 */
b48aa97e 1446 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1447 &ka->master_kernel_ns,
1448 &ka->master_cycle_now);
1449
b48aa97e
MT		 1450 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1451
d828199e
MT		 1452 if (ka->use_master_clock)
1453 atomic_set(&kvm_guest_has_master_clock, 1);
1454
1455 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1456 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1457 vcpus_matched);
d828199e
MT		 1458#endif
1459}
1460
34c238a1 1461static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1462{
d828199e 1463 unsigned long flags, this_tsc_khz;
18068523 1464 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1465 struct kvm_arch *ka = &v->kvm->arch;
1d5f066e 1466 s64 kernel_ns, max_kernel_ns;
d828199e 1467 u64 tsc_timestamp, host_tsc;
0b79459b 1468 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1469 u8 pvclock_flags;
d828199e
MT		 1470 bool use_master_clock;
1471
1472 kernel_ns = 0;
1473 host_tsc = 0;
18068523 1474
d828199e
MT		 1475 /*
1476 * If the host uses TSC clock, then passthrough TSC as stable
1477 * to the guest.
1478 */
1479 spin_lock(&ka->pvclock_gtod_sync_lock);
1480 use_master_clock = ka->use_master_clock;
1481 if (use_master_clock) {
1482 host_tsc = ka->master_cycle_now;
1483 kernel_ns = ka->master_kernel_ns;
1484 }
1485 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1486
1487 /* Keep irq disabled to prevent changes to the clock */
1488 local_irq_save(flags);
1489 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1490 if (unlikely(this_tsc_khz == 0)) {
1491 local_irq_restore(flags);
1492 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1493 return 1;
1494 }
d828199e
MT		 1495 if (!use_master_clock) {
1496 host_tsc = native_read_tsc();
1497 kernel_ns = get_kernel_ns();
1498 }
1499
1500 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1501
c285545f
ZA		 1502 /*
1503 * We may have to catch up the TSC to match elapsed wall clock
1504 * time for two reasons, even if kvmclock is used.
1505 * 1) CPU could have been running below the maximum TSC rate
1506 * 2) Broken TSC compensation resets the base at each VCPU
1507 * entry to avoid unknown leaps of TSC even when running
1508 * again on the same CPU. This may cause apparent elapsed
1509 * time to disappear, and the guest to stand still or run
1510 * very slowly.
1511 */
1512 if (vcpu->tsc_catchup) {
1513 u64 tsc = compute_guest_tsc(v, kernel_ns);
1514 if (tsc > tsc_timestamp) {
f1e2b260 1515 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1516 tsc_timestamp = tsc;
1517 }
50d0a0f9
GH		 1518 }
1519
18068523
GOC		 1520 local_irq_restore(flags);
1521
0b79459b 1522 if (!vcpu->pv_time_enabled)
c285545f 1523 return 0;
18068523 1524
1d5f066e
ZA		 1525 /*
1526 * Time as measured by the TSC may go backwards when resetting the base
1527 * tsc_timestamp. The reason for this is that the TSC resolution is
1528 * higher than the resolution of the other clock scales. Thus, many
1529 * possible measurments of the TSC correspond to one measurement of any
1530 * other clock, and so a spread of values is possible. This is not a
1531 * problem for the computation of the nanosecond clock; with TSC rates
1532 * around 1GHZ, there can only be a few cycles which correspond to one
1533 * nanosecond value, and any path through this code will inevitably
1534 * take longer than that. However, with the kernel_ns value itself,
1535 * the precision may be much lower, down to HZ granularity. If the
1536 * first sampling of TSC against kernel_ns ends in the low part of the
1537 * range, and the second in the high end of the range, we can get:
1538 *
1539 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1540 *
1541 * As the sampling errors potentially range in the thousands of cycles,
1542 * it is possible such a time value has already been observed by the
1543 * guest. To protect against this, we must compute the system time as
1544 * observed by the guest and ensure the new system time is greater.
1545 */
1546 max_kernel_ns = 0;
b183aa58 1547 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1548 max_kernel_ns = vcpu->last_guest_tsc -
1549 vcpu->hv_clock.tsc_timestamp;
1550 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1551 vcpu->hv_clock.tsc_to_system_mul,
1552 vcpu->hv_clock.tsc_shift);
1553 max_kernel_ns += vcpu->last_kernel_ns;
1554 }
afbcf7ab 1555
e48672fa 1556 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1557 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1558 &vcpu->hv_clock.tsc_shift,
1559 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1560 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1561 }
1562
d828199e
MT		 1563 /* with a master <monotonic time, tsc value> tuple,
1564 * pvclock clock reads always increase at the (scaled) rate
1565 * of guest TSC - no need to deal with sampling errors.
1566 */
1567 if (!use_master_clock) {
1568 if (max_kernel_ns > kernel_ns)
1569 kernel_ns = max_kernel_ns;
1570 }
8cfdc000 1571 /* With all the info we got, fill in the values */
1d5f066e 1572 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1573 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1574 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1575 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1576
18068523
GOC		 1577 /*
1578 * The interface expects us to write an even number signaling that the
1579 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1580 * state, we just increase by 2 at the end.
18068523 1581 */
50d0a0f9 1582 vcpu->hv_clock.version += 2;
18068523 1583
0b79459b
AH		 1584 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1585 &guest_hv_clock, sizeof(guest_hv_clock))))
1586 return 0;
78c0337a
MT		 1587
1588 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1589 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1590
1591 if (vcpu->pvclock_set_guest_stopped_request) {
1592 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1593 vcpu->pvclock_set_guest_stopped_request = false;
1594 }
1595
d828199e
MT		 1596 /* If the host uses TSC clocksource, then it is stable */
1597 if (use_master_clock)
1598 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1599
78c0337a
MT		 1600 vcpu->hv_clock.flags = pvclock_flags;
1601
0b79459b
AH		 1602 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1603 &vcpu->hv_clock,
1604 sizeof(vcpu->hv_clock));
8cfdc000 1605 return 0;
c8076604
GH		 1606}
1607
0061d53d
MT		 1608/*
1609 * kvmclock updates which are isolated to a given vcpu, such as
1610 * vcpu->cpu migration, should not allow system_timestamp from
1611 * the rest of the vcpus to remain static. Otherwise ntp frequency
1612 * correction applies to one vcpu's system_timestamp but not
1613 * the others.
1614 *
1615 * So in those cases, request a kvmclock update for all vcpus.
1616 * The worst case for a remote vcpu to update its kvmclock
1617 * is then bounded by maximum nohz sleep latency.
1618 */
1619
1620static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1621{
1622 int i;
1623 struct kvm *kvm = v->kvm;
1624 struct kvm_vcpu *vcpu;
1625
1626 kvm_for_each_vcpu(i, vcpu, kvm) {
1627 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1628 kvm_vcpu_kick(vcpu);
1629 }
1630}
1631
9ba075a6
AK		 1632static bool msr_mtrr_valid(unsigned msr)
1633{
1634 switch (msr) {
1635 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1636 case MSR_MTRRfix64K_00000:
1637 case MSR_MTRRfix16K_80000:
1638 case MSR_MTRRfix16K_A0000:
1639 case MSR_MTRRfix4K_C0000:
1640 case MSR_MTRRfix4K_C8000:
1641 case MSR_MTRRfix4K_D0000:
1642 case MSR_MTRRfix4K_D8000:
1643 case MSR_MTRRfix4K_E0000:
1644 case MSR_MTRRfix4K_E8000:
1645 case MSR_MTRRfix4K_F0000:
1646 case MSR_MTRRfix4K_F8000:
1647 case MSR_MTRRdefType:
1648 case MSR_IA32_CR_PAT:
1649 return true;
1650 case 0x2f8:
1651 return true;
1652 }
1653 return false;
1654}
1655
d6289b93
MT		 1656static bool valid_pat_type(unsigned t)
1657{
1658 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1659}
1660
1661static bool valid_mtrr_type(unsigned t)
1662{
1663 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1664}
1665
1666static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1667{
1668 int i;
1669
1670 if (!msr_mtrr_valid(msr))
1671 return false;
1672
1673 if (msr == MSR_IA32_CR_PAT) {
1674 for (i = 0; i < 8; i++)
1675 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1676 return false;
1677 return true;
1678 } else if (msr == MSR_MTRRdefType) {
1679 if (data & ~0xcff)
1680 return false;
1681 return valid_mtrr_type(data & 0xff);
1682 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1683 for (i = 0; i < 8 ; i++)
1684 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1685 return false;
1686 return true;
1687 }
1688
1689 /* variable MTRRs */
1690 return valid_mtrr_type(data & 0xff);
1691}
1692
9ba075a6
AK		 1693static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1694{
0bed3b56
SY		 1695 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1696
d6289b93 1697 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1698 return 1;
1699
0bed3b56
SY		 1700 if (msr == MSR_MTRRdefType) {
1701 vcpu->arch.mtrr_state.def_type = data;
1702 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1703 } else if (msr == MSR_MTRRfix64K_00000)
1704 p[0] = data;
1705 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1706 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1707 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1708 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1709 else if (msr == MSR_IA32_CR_PAT)
1710 vcpu->arch.pat = data;
1711 else { /* Variable MTRRs */
1712 int idx, is_mtrr_mask;
1713 u64 *pt;
1714
1715 idx = (msr - 0x200) / 2;
1716 is_mtrr_mask = msr - 0x200 - 2 * idx;
1717 if (!is_mtrr_mask)
1718 pt =
1719 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1720 else
1721 pt =
1722 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1723 *pt = data;
1724 }
1725
1726 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1727 return 0;
1728}
15c4a640 1729
890ca9ae 1730static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1731{
890ca9ae
HY		 1732 u64 mcg_cap = vcpu->arch.mcg_cap;
1733 unsigned bank_num = mcg_cap & 0xff;
1734
15c4a640 1735 switch (msr) {
15c4a640 1736 case MSR_IA32_MCG_STATUS:
890ca9ae 1737 vcpu->arch.mcg_status = data;
15c4a640 1738 break;
c7ac679c 1739 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1740 if (!(mcg_cap & MCG_CTL_P))
1741 return 1;
1742 if (data != 0 && data != ~(u64)0)
1743 return -1;
1744 vcpu->arch.mcg_ctl = data;
1745 break;
1746 default:
1747 if (msr >= MSR_IA32_MC0_CTL &&
1748 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1749 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1750 /* only 0 or all 1s can be written to IA32_MCi_CTL
1751 * some Linux kernels though clear bit 10 in bank 4 to
1752 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1753 * this to avoid an uncatched #GP in the guest
1754 */
890ca9ae 1755 if ((offset & 0x3) == 0 &&
114be429 1756 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1757 return -1;
1758 vcpu->arch.mce_banks[offset] = data;
1759 break;
1760 }
1761 return 1;
1762 }
1763 return 0;
1764}
1765
ffde22ac
ES		 1766static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1767{
1768 struct kvm *kvm = vcpu->kvm;
1769 int lm = is_long_mode(vcpu);
1770 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1771 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1772 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1773 : kvm->arch.xen_hvm_config.blob_size_32;
1774 u32 page_num = data & ~PAGE_MASK;
1775 u64 page_addr = data & PAGE_MASK;
1776 u8 *page;
1777 int r;
1778
1779 r = -E2BIG;
1780 if (page_num >= blob_size)
1781 goto out;
1782 r = -ENOMEM;
ff5c2c03
SL		 1783 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1784 if (IS_ERR(page)) {
1785 r = PTR_ERR(page);
ffde22ac 1786 goto out;
ff5c2c03 1787 }
ffde22ac
ES		 1788 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1789 goto out_free;
1790 r = 0;
1791out_free:
1792 kfree(page);
1793out:
1794 return r;
1795}
1796
55cd8e5a
GN		 1797static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1798{
1799 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1800}
1801
1802static bool kvm_hv_msr_partition_wide(u32 msr)
1803{
1804 bool r = false;
1805 switch (msr) {
1806 case HV_X64_MSR_GUEST_OS_ID:
1807 case HV_X64_MSR_HYPERCALL:
1808 r = true;
1809 break;
1810 }
1811
1812 return r;
1813}
1814
1815static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1816{
1817 struct kvm *kvm = vcpu->kvm;
1818
1819 switch (msr) {
1820 case HV_X64_MSR_GUEST_OS_ID:
1821 kvm->arch.hv_guest_os_id = data;
1822 /* setting guest os id to zero disables hypercall page */
1823 if (!kvm->arch.hv_guest_os_id)
1824 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1825 break;
1826 case HV_X64_MSR_HYPERCALL: {
1827 u64 gfn;
1828 unsigned long addr;
1829 u8 instructions[4];
1830
1831 /* if guest os id is not set hypercall should remain disabled */
1832 if (!kvm->arch.hv_guest_os_id)
1833 break;
1834 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1835 kvm->arch.hv_hypercall = data;
1836 break;
1837 }
1838 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1839 addr = gfn_to_hva(kvm, gfn);
1840 if (kvm_is_error_hva(addr))
1841 return 1;
1842 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1843 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1844 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1845 return 1;
1846 kvm->arch.hv_hypercall = data;
1847 break;
1848 }
1849 default:
a737f256
CD		 1850 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1851 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1852 return 1;
1853 }
1854 return 0;
1855}
1856
1857static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1858{
10388a07
GN		 1859 switch (msr) {
1860 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1861 unsigned long addr;
55cd8e5a 1862
10388a07
GN		 1863 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1864 vcpu->arch.hv_vapic = data;
1865 break;
1866 }
1867 addr = gfn_to_hva(vcpu->kvm, data >>
1868 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1869 if (kvm_is_error_hva(addr))
1870 return 1;
8b0cedff 1871 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1872 return 1;
1873 vcpu->arch.hv_vapic = data;
1874 break;
1875 }
1876 case HV_X64_MSR_EOI:
1877 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1878 case HV_X64_MSR_ICR:
1879 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1880 case HV_X64_MSR_TPR:
1881 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1882 default:
a737f256
CD		 1883 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1884 "data 0x%llx\n", msr, data);
10388a07
GN		 1885 return 1;
1886 }
1887
1888 return 0;
55cd8e5a
GN		 1889}
1890
344d9588
GN		 1891static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1892{
1893 gpa_t gpa = data & ~0x3f;
1894
4a969980 1895 /* Bits 2:5 are reserved, Should be zero */
6adba527 1896 if (data & 0x3c)
344d9588
GN		 1897 return 1;
1898
1899 vcpu->arch.apf.msr_val = data;
1900
1901 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1902 kvm_clear_async_pf_completion_queue(vcpu);
1903 kvm_async_pf_hash_reset(vcpu);
1904 return 0;
1905 }
1906
8f964525
AH		 1907 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1908 sizeof(u32)))
344d9588
GN		 1909 return 1;
1910
6adba527 1911 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1912 kvm_async_pf_wakeup_all(vcpu);
1913 return 0;
1914}
1915
12f9a48f
GC		 1916static void kvmclock_reset(struct kvm_vcpu *vcpu)
1917{
0b79459b 1918 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1919}
1920
c9aaa895
GC		 1921static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1922{
1923 u64 delta;
1924
1925 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1926 return;
1927
1928 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1929 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1930 vcpu->arch.st.accum_steal = delta;
1931}
1932
1933static void record_steal_time(struct kvm_vcpu *vcpu)
1934{
1935 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1936 return;
1937
1938 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1939 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1940 return;
1941
1942 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1943 vcpu->arch.st.steal.version += 2;
1944 vcpu->arch.st.accum_steal = 0;
1945
1946 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1947 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1948}
1949
8fe8ab46 1950int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1951{
5753785f 1952 bool pr = false;
8fe8ab46
WA		 1953 u32 msr = msr_info->index;
1954 u64 data = msr_info->data;
5753785f 1955
15c4a640 1956 switch (msr) {
2e32b719
BP		 1957 case MSR_AMD64_NB_CFG:
1958 case MSR_IA32_UCODE_REV:
1959 case MSR_IA32_UCODE_WRITE:
1960 case MSR_VM_HSAVE_PA:
1961 case MSR_AMD64_PATCH_LOADER:
1962 case MSR_AMD64_BU_CFG2:
1963 break;
1964
15c4a640 1965 case MSR_EFER:
b69e8cae 1966 return set_efer(vcpu, data);
8f1589d9
AP		 1967 case MSR_K7_HWCR:
1968 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1969 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1970 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1971 if (data != 0) {
a737f256
CD		 1972 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1973 data);
8f1589d9
AP		 1974 return 1;
1975 }
15c4a640 1976 break;
f7c6d140
AP		 1977 case MSR_FAM10H_MMIO_CONF_BASE:
1978 if (data != 0) {
a737f256
CD		 1979 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1980 "0x%llx\n", data);
f7c6d140
AP		 1981 return 1;
1982 }
15c4a640 1983 break;
b5e2fec0
AG		 1984 case MSR_IA32_DEBUGCTLMSR:
1985 if (!data) {
1986 /* We support the non-activated case already */
1987 break;
1988 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1989 /* Values other than LBR and BTF are vendor-specific,
1990 thus reserved and should throw a #GP */
1991 return 1;
1992 }
a737f256
CD		 1993 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1994 __func__, data);
b5e2fec0 1995 break;
9ba075a6
AK		 1996 case 0x200 ... 0x2ff:
1997 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1998 case MSR_IA32_APICBASE:
1999 kvm_set_apic_base(vcpu, data);
2000 break;
0105d1a5
GN		 2001 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2002 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2003 case MSR_IA32_TSCDEADLINE:
2004 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2005 break;
ba904635
WA		 2006 case MSR_IA32_TSC_ADJUST:
2007 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2008 if (!msr_info->host_initiated) {
2009 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2010 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2011 }
2012 vcpu->arch.ia32_tsc_adjust_msr = data;
2013 }
2014 break;
15c4a640 2015 case MSR_IA32_MISC_ENABLE:
ad312c7c 2016 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2017 break;
11c6bffa 2018 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2019 case MSR_KVM_WALL_CLOCK:
2020 vcpu->kvm->arch.wall_clock = data;
2021 kvm_write_wall_clock(vcpu->kvm, data);
2022 break;
11c6bffa 2023 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2024 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2025 u64 gpa_offset;
12f9a48f 2026 kvmclock_reset(vcpu);
18068523
GOC		 2027
2028 vcpu->arch.time = data;
0061d53d 2029 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2030
2031 /* we verify if the enable bit is set... */
2032 if (!(data & 1))
2033 break;
2034
0b79459b 2035 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2036
0b79459b 2037 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2038 &vcpu->arch.pv_time, data & ~1ULL,
2039 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2040 vcpu->arch.pv_time_enabled = false;
2041 else
2042 vcpu->arch.pv_time_enabled = true;
32cad84f 2043
18068523
GOC		 2044 break;
2045 }
344d9588
GN		 2046 case MSR_KVM_ASYNC_PF_EN:
2047 if (kvm_pv_enable_async_pf(vcpu, data))
2048 return 1;
2049 break;
c9aaa895
GC		 2050 case MSR_KVM_STEAL_TIME:
2051
2052 if (unlikely(!sched_info_on()))
2053 return 1;
2054
2055 if (data & KVM_STEAL_RESERVED_MASK)
2056 return 1;
2057
2058 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2059 data & KVM_STEAL_VALID_BITS,
2060 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2061 return 1;
2062
2063 vcpu->arch.st.msr_val = data;
2064
2065 if (!(data & KVM_MSR_ENABLED))
2066 break;
2067
2068 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2069
2070 preempt_disable();
2071 accumulate_steal_time(vcpu);
2072 preempt_enable();
2073
2074 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2075
2076 break;
ae7a2a3f
MT		 2077 case MSR_KVM_PV_EOI_EN:
2078 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2079 return 1;
2080 break;
c9aaa895 2081
890ca9ae
HY		 2082 case MSR_IA32_MCG_CTL:
2083 case MSR_IA32_MCG_STATUS:
2084 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2085 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2086
2087 /* Performance counters are not protected by a CPUID bit,
2088 * so we should check all of them in the generic path for the sake of
2089 * cross vendor migration.
2090 * Writing a zero into the event select MSRs disables them,
2091 * which we perfectly emulate ;-). Any other value should be at least
2092 * reported, some guests depend on them.
2093 */
71db6023
AP		 2094 case MSR_K7_EVNTSEL0:
2095 case MSR_K7_EVNTSEL1:
2096 case MSR_K7_EVNTSEL2:
2097 case MSR_K7_EVNTSEL3:
2098 if (data != 0)
a737f256
CD		 2099 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2100 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2101 break;
2102 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2103 * so we ignore writes to make it happy.
2104 */
71db6023
AP		 2105 case MSR_K7_PERFCTR0:
2106 case MSR_K7_PERFCTR1:
2107 case MSR_K7_PERFCTR2:
2108 case MSR_K7_PERFCTR3:
a737f256
CD		 2109 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2110 "0x%x data 0x%llx\n", msr, data);
71db6023 2111 break;
5753785f
GN		 2112 case MSR_P6_PERFCTR0:
2113 case MSR_P6_PERFCTR1:
2114 pr = true;
2115 case MSR_P6_EVNTSEL0:
2116 case MSR_P6_EVNTSEL1:
2117 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2118 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2119
2120 if (pr || data != 0)
a737f256
CD		 2121 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2122 "0x%x data 0x%llx\n", msr, data);
5753785f 2123 break;
84e0cefa
JS		 2124 case MSR_K7_CLK_CTL:
2125 /*
2126 * Ignore all writes to this no longer documented MSR.
2127 * Writes are only relevant for old K7 processors,
2128 * all pre-dating SVM, but a recommended workaround from
4a969980 2129 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2130 * affected processor models on the command line, hence
2131 * the need to ignore the workaround.
2132 */
2133 break;
55cd8e5a
GN		 2134 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2135 if (kvm_hv_msr_partition_wide(msr)) {
2136 int r;
2137 mutex_lock(&vcpu->kvm->lock);
2138 r = set_msr_hyperv_pw(vcpu, msr, data);
2139 mutex_unlock(&vcpu->kvm->lock);
2140 return r;
2141 } else
2142 return set_msr_hyperv(vcpu, msr, data);
2143 break;
91c9c3ed 2144 case MSR_IA32_BBL_CR_CTL3:
2145 /* Drop writes to this legacy MSR -- see rdmsr
2146 * counterpart for further detail.
2147 */
a737f256 2148 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2149 break;
2b036c6b
BO		 2150 case MSR_AMD64_OSVW_ID_LENGTH:
2151 if (!guest_cpuid_has_osvw(vcpu))
2152 return 1;
2153 vcpu->arch.osvw.length = data;
2154 break;
2155 case MSR_AMD64_OSVW_STATUS:
2156 if (!guest_cpuid_has_osvw(vcpu))
2157 return 1;
2158 vcpu->arch.osvw.status = data;
2159 break;
15c4a640 2160 default:
ffde22ac
ES		 2161 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2162 return xen_hvm_config(vcpu, data);
f5132b01 2163 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2164 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2165 if (!ignore_msrs) {
a737f256
CD		 2166 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2167 msr, data);
ed85c068
AP		 2168 return 1;
2169 } else {
a737f256
CD		 2170 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2171 msr, data);
ed85c068
AP		 2172 break;
2173 }
15c4a640
CO		 2174 }
2175 return 0;
2176}
2177EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2178
2179
2180/*
2181 * Reads an msr value (of 'msr_index') into 'pdata'.
2182 * Returns 0 on success, non-0 otherwise.
2183 * Assumes vcpu_load() was already called.
2184 */
2185int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2186{
2187 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2188}
2189
9ba075a6
AK		 2190static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2191{
0bed3b56
SY		 2192 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2193
9ba075a6
AK		 2194 if (!msr_mtrr_valid(msr))
2195 return 1;
2196
0bed3b56
SY		 2197 if (msr == MSR_MTRRdefType)
2198 *pdata = vcpu->arch.mtrr_state.def_type +
2199 (vcpu->arch.mtrr_state.enabled << 10);
2200 else if (msr == MSR_MTRRfix64K_00000)
2201 *pdata = p[0];
2202 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2203 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2204 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2205 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2206 else if (msr == MSR_IA32_CR_PAT)
2207 *pdata = vcpu->arch.pat;
2208 else { /* Variable MTRRs */
2209 int idx, is_mtrr_mask;
2210 u64 *pt;
2211
2212 idx = (msr - 0x200) / 2;
2213 is_mtrr_mask = msr - 0x200 - 2 * idx;
2214 if (!is_mtrr_mask)
2215 pt =
2216 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2217 else
2218 pt =
2219 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2220 *pdata = *pt;
2221 }
2222
9ba075a6
AK		 2223 return 0;
2224}
2225
890ca9ae 2226static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2227{
2228 u64 data;
890ca9ae
HY		 2229 u64 mcg_cap = vcpu->arch.mcg_cap;
2230 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2231
2232 switch (msr) {
15c4a640
CO		 2233 case MSR_IA32_P5_MC_ADDR:
2234 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2235 data = 0;
2236 break;
15c4a640 2237 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2238 data = vcpu->arch.mcg_cap;
2239 break;
c7ac679c 2240 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2241 if (!(mcg_cap & MCG_CTL_P))
2242 return 1;
2243 data = vcpu->arch.mcg_ctl;
2244 break;
2245 case MSR_IA32_MCG_STATUS:
2246 data = vcpu->arch.mcg_status;
2247 break;
2248 default:
2249 if (msr >= MSR_IA32_MC0_CTL &&
2250 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2251 u32 offset = msr - MSR_IA32_MC0_CTL;
2252 data = vcpu->arch.mce_banks[offset];
2253 break;
2254 }
2255 return 1;
2256 }
2257 *pdata = data;
2258 return 0;
2259}
2260
55cd8e5a
GN		 2261static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2262{
2263 u64 data = 0;
2264 struct kvm *kvm = vcpu->kvm;
2265
2266 switch (msr) {
2267 case HV_X64_MSR_GUEST_OS_ID:
2268 data = kvm->arch.hv_guest_os_id;
2269 break;
2270 case HV_X64_MSR_HYPERCALL:
2271 data = kvm->arch.hv_hypercall;
2272 break;
2273 default:
a737f256 2274 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2275 return 1;
2276 }
2277
2278 *pdata = data;
2279 return 0;
2280}
2281
2282static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2283{
2284 u64 data = 0;
2285
2286 switch (msr) {
2287 case HV_X64_MSR_VP_INDEX: {
2288 int r;
2289 struct kvm_vcpu *v;
2290 kvm_for_each_vcpu(r, v, vcpu->kvm)
2291 if (v == vcpu)
2292 data = r;
2293 break;
2294 }
10388a07
GN		 2295 case HV_X64_MSR_EOI:
2296 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2297 case HV_X64_MSR_ICR:
2298 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2299 case HV_X64_MSR_TPR:
2300 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2301 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2302 data = vcpu->arch.hv_vapic;
2303 break;
55cd8e5a 2304 default:
a737f256 2305 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2306 return 1;
2307 }
2308 *pdata = data;
2309 return 0;
2310}
2311
890ca9ae
HY		 2312int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2313{
2314 u64 data;
2315
2316 switch (msr) {
890ca9ae 2317 case MSR_IA32_PLATFORM_ID:
15c4a640 2318 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2319 case MSR_IA32_DEBUGCTLMSR:
2320 case MSR_IA32_LASTBRANCHFROMIP:
2321 case MSR_IA32_LASTBRANCHTOIP:
2322 case MSR_IA32_LASTINTFROMIP:
2323 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2324 case MSR_K8_SYSCFG:
2325 case MSR_K7_HWCR:
61a6bd67 2326 case MSR_VM_HSAVE_PA:
9e699624 2327 case MSR_K7_EVNTSEL0:
1f3ee616 2328 case MSR_K7_PERFCTR0:
1fdbd48c 2329 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2330 case MSR_AMD64_NB_CFG:
f7c6d140 2331 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2332 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2333 data = 0;
2334 break;
5753785f
GN		 2335 case MSR_P6_PERFCTR0:
2336 case MSR_P6_PERFCTR1:
2337 case MSR_P6_EVNTSEL0:
2338 case MSR_P6_EVNTSEL1:
2339 if (kvm_pmu_msr(vcpu, msr))
2340 return kvm_pmu_get_msr(vcpu, msr, pdata);
2341 data = 0;
2342 break;
742bc670
MT		 2343 case MSR_IA32_UCODE_REV:
2344 data = 0x100000000ULL;
2345 break;
9ba075a6
AK		 2346 case MSR_MTRRcap:
2347 data = 0x500 | KVM_NR_VAR_MTRR;
2348 break;
2349 case 0x200 ... 0x2ff:
2350 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2351 case 0xcd: /* fsb frequency */
2352 data = 3;
2353 break;
7b914098
JS		 2354 /*
2355 * MSR_EBC_FREQUENCY_ID
2356 * Conservative value valid for even the basic CPU models.
2357 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2358 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2359 * and 266MHz for model 3, or 4. Set Core Clock
2360 * Frequency to System Bus Frequency Ratio to 1 (bits
2361 * 31:24) even though these are only valid for CPU
2362 * models > 2, however guests may end up dividing or
2363 * multiplying by zero otherwise.
2364 */
2365 case MSR_EBC_FREQUENCY_ID:
2366 data = 1 << 24;
2367 break;
15c4a640
CO		 2368 case MSR_IA32_APICBASE:
2369 data = kvm_get_apic_base(vcpu);
2370 break;
0105d1a5
GN		 2371 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2372 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2373 break;
a3e06bbe
LJ		 2374 case MSR_IA32_TSCDEADLINE:
2375 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2376 break;
ba904635
WA		 2377 case MSR_IA32_TSC_ADJUST:
2378 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2379 break;
15c4a640 2380 case MSR_IA32_MISC_ENABLE:
ad312c7c 2381 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2382 break;
847f0ad8
AG		 2383 case MSR_IA32_PERF_STATUS:
2384 /* TSC increment by tick */
2385 data = 1000ULL;
2386 /* CPU multiplier */
2387 data |= (((uint64_t)4ULL) << 40);
2388 break;
15c4a640 2389 case MSR_EFER:
f6801dff 2390 data = vcpu->arch.efer;
15c4a640 2391 break;
18068523 2392 case MSR_KVM_WALL_CLOCK:
11c6bffa 2393 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2394 data = vcpu->kvm->arch.wall_clock;
2395 break;
2396 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2397 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2398 data = vcpu->arch.time;
2399 break;
344d9588
GN		 2400 case MSR_KVM_ASYNC_PF_EN:
2401 data = vcpu->arch.apf.msr_val;
2402 break;
c9aaa895
GC		 2403 case MSR_KVM_STEAL_TIME:
2404 data = vcpu->arch.st.msr_val;
2405 break;
1d92128f
MT		 2406 case MSR_KVM_PV_EOI_EN:
2407 data = vcpu->arch.pv_eoi.msr_val;
2408 break;
890ca9ae
HY		 2409 case MSR_IA32_P5_MC_ADDR:
2410 case MSR_IA32_P5_MC_TYPE:
2411 case MSR_IA32_MCG_CAP:
2412 case MSR_IA32_MCG_CTL:
2413 case MSR_IA32_MCG_STATUS:
2414 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2415 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2416 case MSR_K7_CLK_CTL:
2417 /*
2418 * Provide expected ramp-up count for K7. All other
2419 * are set to zero, indicating minimum divisors for
2420 * every field.
2421 *
2422 * This prevents guest kernels on AMD host with CPU
2423 * type 6, model 8 and higher from exploding due to
2424 * the rdmsr failing.
2425 */
2426 data = 0x20000000;
2427 break;
55cd8e5a
GN		 2428 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2429 if (kvm_hv_msr_partition_wide(msr)) {
2430 int r;
2431 mutex_lock(&vcpu->kvm->lock);
2432 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2433 mutex_unlock(&vcpu->kvm->lock);
2434 return r;
2435 } else
2436 return get_msr_hyperv(vcpu, msr, pdata);
2437 break;
91c9c3ed 2438 case MSR_IA32_BBL_CR_CTL3:
2439 /* This legacy MSR exists but isn't fully documented in current
2440 * silicon. It is however accessed by winxp in very narrow
2441 * scenarios where it sets bit #19, itself documented as
2442 * a "reserved" bit. Best effort attempt to source coherent
2443 * read data here should the balance of the register be
2444 * interpreted by the guest:
2445 *
2446 * L2 cache control register 3: 64GB range, 256KB size,
2447 * enabled, latency 0x1, configured
2448 */
2449 data = 0xbe702111;
2450 break;
2b036c6b
BO		 2451 case MSR_AMD64_OSVW_ID_LENGTH:
2452 if (!guest_cpuid_has_osvw(vcpu))
2453 return 1;
2454 data = vcpu->arch.osvw.length;
2455 break;
2456 case MSR_AMD64_OSVW_STATUS:
2457 if (!guest_cpuid_has_osvw(vcpu))
2458 return 1;
2459 data = vcpu->arch.osvw.status;
2460 break;
15c4a640 2461 default:
f5132b01
GN		 2462 if (kvm_pmu_msr(vcpu, msr))
2463 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2464 if (!ignore_msrs) {
a737f256 2465 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2466 return 1;
2467 } else {
a737f256 2468 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2469 data = 0;
2470 }
2471 break;
15c4a640
CO		 2472 }
2473 *pdata = data;
2474 return 0;
2475}
2476EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2477
313a3dc7
CO		 2478/*
2479 * Read or write a bunch of msrs. All parameters are kernel addresses.
2480 *
2481 * @return number of msrs set successfully.
2482 */
2483static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2484 struct kvm_msr_entry *entries,
2485 int (*do_msr)(struct kvm_vcpu *vcpu,
2486 unsigned index, u64 *data))
2487{
f656ce01 2488 int i, idx;
313a3dc7 2489
f656ce01 2490 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2491 for (i = 0; i < msrs->nmsrs; ++i)
2492 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2493 break;
f656ce01 2494 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2495
313a3dc7
CO		 2496 return i;
2497}
2498
2499/*
2500 * Read or write a bunch of msrs. Parameters are user addresses.
2501 *
2502 * @return number of msrs set successfully.
2503 */
2504static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2505 int (*do_msr)(struct kvm_vcpu *vcpu,
2506 unsigned index, u64 *data),
2507 int writeback)
2508{
2509 struct kvm_msrs msrs;
2510 struct kvm_msr_entry *entries;
2511 int r, n;
2512 unsigned size;
2513
2514 r = -EFAULT;
2515 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2516 goto out;
2517
2518 r = -E2BIG;
2519 if (msrs.nmsrs >= MAX_IO_MSRS)
2520 goto out;
2521
313a3dc7 2522 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2523 entries = memdup_user(user_msrs->entries, size);
2524 if (IS_ERR(entries)) {
2525 r = PTR_ERR(entries);
313a3dc7 2526 goto out;
ff5c2c03 2527 }
313a3dc7
CO		 2528
2529 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2530 if (r < 0)
2531 goto out_free;
2532
2533 r = -EFAULT;
2534 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2535 goto out_free;
2536
2537 r = n;
2538
2539out_free:
7a73c028 2540 kfree(entries);
313a3dc7
CO		 2541out:
2542 return r;
2543}
2544
018d00d2
ZX		 2545int kvm_dev_ioctl_check_extension(long ext)
2546{
2547 int r;
2548
2549 switch (ext) {
2550 case KVM_CAP_IRQCHIP:
2551 case KVM_CAP_HLT:
2552 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2553 case KVM_CAP_SET_TSS_ADDR:
07716717 2554 case KVM_CAP_EXT_CPUID:
c8076604 2555 case KVM_CAP_CLOCKSOURCE:
7837699f 2556 case KVM_CAP_PIT:
a28e4f5a 2557 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2558 case KVM_CAP_MP_STATE:
ed848624 2559 case KVM_CAP_SYNC_MMU:
a355c85c 2560 case KVM_CAP_USER_NMI:
52d939a0 2561 case KVM_CAP_REINJECT_CONTROL:
4925663a 2562 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2563 case KVM_CAP_IRQFD:
d34e6b17 2564 case KVM_CAP_IOEVENTFD:
c5ff41ce 2565 case KVM_CAP_PIT2:
e9f42757 2566 case KVM_CAP_PIT_STATE2:
b927a3ce 2567 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2568 case KVM_CAP_XEN_HVM:
afbcf7ab 2569 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2570 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2571 case KVM_CAP_HYPERV:
10388a07 2572 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2573 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2574 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2575 case KVM_CAP_DEBUGREGS:
d2be1651 2576 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2577 case KVM_CAP_XSAVE:
344d9588 2578 case KVM_CAP_ASYNC_PF:
92a1f12d 2579 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2580 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2581 case KVM_CAP_READONLY_MEM:
2a5bab10
AW		 2582#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2583 case KVM_CAP_ASSIGN_DEV_IRQ:
2584 case KVM_CAP_PCI_2_3:
2585#endif
018d00d2
ZX		 2586 r = 1;
2587 break;
542472b5
LV		 2588 case KVM_CAP_COALESCED_MMIO:
2589 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2590 break;
774ead3a
AK		 2591 case KVM_CAP_VAPIC:
2592 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2593 break;
f725230a 2594 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2595 r = KVM_SOFT_MAX_VCPUS;
2596 break;
2597 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2598 r = KVM_MAX_VCPUS;
2599 break;
a988b910 2600 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2601 r = KVM_USER_MEM_SLOTS;
a988b910 2602 break;
a68a6a72
MT		 2603 case KVM_CAP_PV_MMU: /* obsolete */
2604 r = 0;
2f333bcb 2605 break;
4cee4b72 2606#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2607 case KVM_CAP_IOMMU:
a1b60c1c 2608 r = iommu_present(&pci_bus_type);
62c476c7 2609 break;
4cee4b72 2610#endif
890ca9ae
HY		 2611 case KVM_CAP_MCE:
2612 r = KVM_MAX_MCE_BANKS;
2613 break;
2d5b5a66
SY		 2614 case KVM_CAP_XCRS:
2615 r = cpu_has_xsave;
2616 break;
92a1f12d
JR		 2617 case KVM_CAP_TSC_CONTROL:
2618 r = kvm_has_tsc_control;
2619 break;
4d25a066
JK		 2620 case KVM_CAP_TSC_DEADLINE_TIMER:
2621 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2622 break;
018d00d2
ZX		 2623 default:
2624 r = 0;
2625 break;
2626 }
2627 return r;
2628
2629}
2630
043405e1
CO		 2631long kvm_arch_dev_ioctl(struct file *filp,
2632 unsigned int ioctl, unsigned long arg)
2633{
2634 void __user *argp = (void __user *)arg;
2635 long r;
2636
2637 switch (ioctl) {
2638 case KVM_GET_MSR_INDEX_LIST: {
2639 struct kvm_msr_list __user *user_msr_list = argp;
2640 struct kvm_msr_list msr_list;
2641 unsigned n;
2642
2643 r = -EFAULT;
2644 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2645 goto out;
2646 n = msr_list.nmsrs;
2647 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2648 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2649 goto out;
2650 r = -E2BIG;
e125e7b6 2651 if (n < msr_list.nmsrs)
043405e1
CO		 2652 goto out;
2653 r = -EFAULT;
2654 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2655 num_msrs_to_save * sizeof(u32)))
2656 goto out;
e125e7b6 2657 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2658 &emulated_msrs,
2659 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2660 goto out;
2661 r = 0;
2662 break;
2663 }
674eea0f
AK		 2664 case KVM_GET_SUPPORTED_CPUID: {
2665 struct kvm_cpuid2 __user *cpuid_arg = argp;
2666 struct kvm_cpuid2 cpuid;
2667
2668 r = -EFAULT;
2669 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2670 goto out;
2671 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2672 cpuid_arg->entries);
674eea0f
AK		 2673 if (r)
2674 goto out;
2675
2676 r = -EFAULT;
2677 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2678 goto out;
2679 r = 0;
2680 break;
2681 }
890ca9ae
HY		 2682 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2683 u64 mce_cap;
2684
2685 mce_cap = KVM_MCE_CAP_SUPPORTED;
2686 r = -EFAULT;
2687 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2688 goto out;
2689 r = 0;
2690 break;
2691 }
043405e1
CO		 2692 default:
2693 r = -EINVAL;
2694 }
2695out:
2696 return r;
2697}
2698
f5f48ee1
SY		 2699static void wbinvd_ipi(void *garbage)
2700{
2701 wbinvd();
2702}
2703
2704static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2705{
2706 return vcpu->kvm->arch.iommu_domain &&
2707 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2708}
2709
313a3dc7
CO		 2710void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2711{
f5f48ee1
SY		 2712 /* Address WBINVD may be executed by guest */
2713 if (need_emulate_wbinvd(vcpu)) {
2714 if (kvm_x86_ops->has_wbinvd_exit())
2715 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2716 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2717 smp_call_function_single(vcpu->cpu,
2718 wbinvd_ipi, NULL, 1);
2719 }
2720
313a3dc7 2721 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2722
0dd6a6ed
ZA		 2723 /* Apply any externally detected TSC adjustments (due to suspend) */
2724 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2725 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2726 vcpu->arch.tsc_offset_adjustment = 0;
2727 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2728 }
8f6055cb 2729
48434c20 2730 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2731 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2732 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2733 if (tsc_delta < 0)
2734 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2735 if (check_tsc_unstable()) {
b183aa58
ZA		 2736 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2737 vcpu->arch.last_guest_tsc);
2738 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2739 vcpu->arch.tsc_catchup = 1;
c285545f 2740 }
d98d07ca
MT		 2741 /*
2742 * On a host with synchronized TSC, there is no need to update
2743 * kvmclock on vcpu->cpu migration
2744 */
2745 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2746 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2747 if (vcpu->cpu != cpu)
2748 kvm_migrate_timers(vcpu);
e48672fa 2749 vcpu->cpu = cpu;
6b7d7e76 2750 }
c9aaa895
GC		 2751
2752 accumulate_steal_time(vcpu);
2753 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2754}
2755
2756void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2757{
02daab21 2758 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2759 kvm_put_guest_fpu(vcpu);
6f526ec5 2760 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2761}
2762
313a3dc7
CO		 2763static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2764 struct kvm_lapic_state *s)
2765{
5a71785d 2766 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2767 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2768
2769 return 0;
2770}
2771
2772static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2773 struct kvm_lapic_state *s)
2774{
64eb0620 2775 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2776 update_cr8_intercept(vcpu);
313a3dc7
CO		 2777
2778 return 0;
2779}
2780
f77bc6a4
ZX		 2781static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2782 struct kvm_interrupt *irq)
2783{
02cdb50f 2784 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2785 return -EINVAL;
2786 if (irqchip_in_kernel(vcpu->kvm))
2787 return -ENXIO;
f77bc6a4 2788
66fd3f7f 2789 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2790 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2791
f77bc6a4
ZX		 2792 return 0;
2793}
2794
c4abb7c9
JK		 2795static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2796{
c4abb7c9 2797 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2798
2799 return 0;
2800}
2801
b209749f
AK		 2802static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2803 struct kvm_tpr_access_ctl *tac)
2804{
2805 if (tac->flags)
2806 return -EINVAL;
2807 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2808 return 0;
2809}
2810
890ca9ae
HY		 2811static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2812 u64 mcg_cap)
2813{
2814 int r;
2815 unsigned bank_num = mcg_cap & 0xff, bank;
2816
2817 r = -EINVAL;
a9e38c3e 2818 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2819 goto out;
2820 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2821 goto out;
2822 r = 0;
2823 vcpu->arch.mcg_cap = mcg_cap;
2824 /* Init IA32_MCG_CTL to all 1s */
2825 if (mcg_cap & MCG_CTL_P)
2826 vcpu->arch.mcg_ctl = ~(u64)0;
2827 /* Init IA32_MCi_CTL to all 1s */
2828 for (bank = 0; bank < bank_num; bank++)
2829 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2830out:
2831 return r;
2832}
2833
2834static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2835 struct kvm_x86_mce *mce)
2836{
2837 u64 mcg_cap = vcpu->arch.mcg_cap;
2838 unsigned bank_num = mcg_cap & 0xff;
2839 u64 *banks = vcpu->arch.mce_banks;
2840
2841 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2842 return -EINVAL;
2843 /*
2844 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2845 * reporting is disabled
2846 */
2847 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2848 vcpu->arch.mcg_ctl != ~(u64)0)
2849 return 0;
2850 banks += 4 * mce->bank;
2851 /*
2852 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2853 * reporting is disabled for the bank
2854 */
2855 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2856 return 0;
2857 if (mce->status & MCI_STATUS_UC) {
2858 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2859 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2860 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2861 return 0;
2862 }
2863 if (banks[1] & MCI_STATUS_VAL)
2864 mce->status |= MCI_STATUS_OVER;
2865 banks[2] = mce->addr;
2866 banks[3] = mce->misc;
2867 vcpu->arch.mcg_status = mce->mcg_status;
2868 banks[1] = mce->status;
2869 kvm_queue_exception(vcpu, MC_VECTOR);
2870 } else if (!(banks[1] & MCI_STATUS_VAL)
2871 || !(banks[1] & MCI_STATUS_UC)) {
2872 if (banks[1] & MCI_STATUS_VAL)
2873 mce->status |= MCI_STATUS_OVER;
2874 banks[2] = mce->addr;
2875 banks[3] = mce->misc;
2876 banks[1] = mce->status;
2877 } else
2878 banks[1] |= MCI_STATUS_OVER;
2879 return 0;
2880}
2881
3cfc3092
JK		 2882static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2883 struct kvm_vcpu_events *events)
2884{
7460fb4a 2885 process_nmi(vcpu);
03b82a30
JK		 2886 events->exception.injected =
2887 vcpu->arch.exception.pending &&
2888 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2889 events->exception.nr = vcpu->arch.exception.nr;
2890 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2891 events->exception.pad = 0;
3cfc3092
JK		 2892 events->exception.error_code = vcpu->arch.exception.error_code;
2893
03b82a30
JK		 2894 events->interrupt.injected =
2895 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2896 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2897 events->interrupt.soft = 0;
48005f64
JK		 2898 events->interrupt.shadow =
2899 kvm_x86_ops->get_interrupt_shadow(vcpu,
2900 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2901
2902 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2903 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2904 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2905 events->nmi.pad = 0;
3cfc3092 2906
66450a21 2907 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2908
dab4b911 2909 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2910 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2911 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2912}
2913
2914static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2915 struct kvm_vcpu_events *events)
2916{
dab4b911 2917 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2918 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2919 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2920 return -EINVAL;
2921
7460fb4a 2922 process_nmi(vcpu);
3cfc3092
JK		 2923 vcpu->arch.exception.pending = events->exception.injected;
2924 vcpu->arch.exception.nr = events->exception.nr;
2925 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2926 vcpu->arch.exception.error_code = events->exception.error_code;
2927
2928 vcpu->arch.interrupt.pending = events->interrupt.injected;
2929 vcpu->arch.interrupt.nr = events->interrupt.nr;
2930 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2931 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2932 kvm_x86_ops->set_interrupt_shadow(vcpu,
2933 events->interrupt.shadow);
3cfc3092
JK		 2934
2935 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2936 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2937 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2938 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2939
66450a21
JK		 2940 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2941 kvm_vcpu_has_lapic(vcpu))
2942 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2943
3842d135
AK		 2944 kvm_make_request(KVM_REQ_EVENT, vcpu);
2945
3cfc3092
JK		 2946 return 0;
2947}
2948
a1efbe77
JK		 2949static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2950 struct kvm_debugregs *dbgregs)
2951{
a1efbe77
JK		 2952 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2953 dbgregs->dr6 = vcpu->arch.dr6;
2954 dbgregs->dr7 = vcpu->arch.dr7;
2955 dbgregs->flags = 0;
97e69aa6 2956 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2957}
2958
2959static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2960 struct kvm_debugregs *dbgregs)
2961{
2962 if (dbgregs->flags)
2963 return -EINVAL;
2964
a1efbe77
JK		 2965 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2966 vcpu->arch.dr6 = dbgregs->dr6;
2967 vcpu->arch.dr7 = dbgregs->dr7;
2968
a1efbe77
JK		 2969 return 0;
2970}
2971
2d5b5a66
SY		 2972static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2973 struct kvm_xsave *guest_xsave)
2974{
2975 if (cpu_has_xsave)
2976 memcpy(guest_xsave->region,
2977 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2978 xstate_size);
2d5b5a66
SY		 2979 else {
2980 memcpy(guest_xsave->region,
2981 &vcpu->arch.guest_fpu.state->fxsave,
2982 sizeof(struct i387_fxsave_struct));
2983 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2984 XSTATE_FPSSE;
2985 }
2986}
2987
2988static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2989 struct kvm_xsave *guest_xsave)
2990{
2991 u64 xstate_bv =
2992 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2993
2994 if (cpu_has_xsave)
2995 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2996 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2997 else {
2998 if (xstate_bv & ~XSTATE_FPSSE)
2999 return -EINVAL;
3000 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3001 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3002 }
3003 return 0;
3004}
3005
3006static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3007 struct kvm_xcrs *guest_xcrs)
3008{
3009 if (!cpu_has_xsave) {
3010 guest_xcrs->nr_xcrs = 0;
3011 return;
3012 }
3013
3014 guest_xcrs->nr_xcrs = 1;
3015 guest_xcrs->flags = 0;
3016 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3017 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3018}
3019
3020static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3021 struct kvm_xcrs *guest_xcrs)
3022{
3023 int i, r = 0;
3024
3025 if (!cpu_has_xsave)
3026 return -EINVAL;
3027
3028 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3029 return -EINVAL;
3030
3031 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3032 /* Only support XCR0 currently */
3033 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
3034 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3035 guest_xcrs->xcrs[0].value);
3036 break;
3037 }
3038 if (r)
3039 r = -EINVAL;
3040 return r;
3041}
3042
1c0b28c2
EM		 3043/*
3044 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3045 * stopped by the hypervisor. This function will be called from the host only.
3046 * EINVAL is returned when the host attempts to set the flag for a guest that
3047 * does not support pv clocks.
3048 */
3049static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3050{
0b79459b 3051 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3052 return -EINVAL;
51d59c6b 3053 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3054 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3055 return 0;
3056}
3057
313a3dc7
CO		 3058long kvm_arch_vcpu_ioctl(struct file *filp,
3059 unsigned int ioctl, unsigned long arg)
3060{
3061 struct kvm_vcpu *vcpu = filp->private_data;
3062 void __user *argp = (void __user *)arg;
3063 int r;
d1ac91d8
AK		 3064 union {
3065 struct kvm_lapic_state *lapic;
3066 struct kvm_xsave *xsave;
3067 struct kvm_xcrs *xcrs;
3068 void *buffer;
3069 } u;
3070
3071 u.buffer = NULL;
313a3dc7
CO		 3072 switch (ioctl) {
3073 case KVM_GET_LAPIC: {
2204ae3c
MT		 3074 r = -EINVAL;
3075 if (!vcpu->arch.apic)
3076 goto out;
d1ac91d8 3077 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3078
b772ff36 3079 r = -ENOMEM;
d1ac91d8 3080 if (!u.lapic)
b772ff36 3081 goto out;
d1ac91d8 3082 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3083 if (r)
3084 goto out;
3085 r = -EFAULT;
d1ac91d8 3086 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3087 goto out;
3088 r = 0;
3089 break;
3090 }
3091 case KVM_SET_LAPIC: {
2204ae3c
MT		 3092 r = -EINVAL;
3093 if (!vcpu->arch.apic)
3094 goto out;
ff5c2c03 3095 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3096 if (IS_ERR(u.lapic))
3097 return PTR_ERR(u.lapic);
ff5c2c03 3098
d1ac91d8 3099 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3100 break;
3101 }
f77bc6a4
ZX		 3102 case KVM_INTERRUPT: {
3103 struct kvm_interrupt irq;
3104
3105 r = -EFAULT;
3106 if (copy_from_user(&irq, argp, sizeof irq))
3107 goto out;
3108 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3109 break;
3110 }
c4abb7c9
JK		 3111 case KVM_NMI: {
3112 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3113 break;
3114 }
313a3dc7
CO		 3115 case KVM_SET_CPUID: {
3116 struct kvm_cpuid __user *cpuid_arg = argp;
3117 struct kvm_cpuid cpuid;
3118
3119 r = -EFAULT;
3120 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3121 goto out;
3122 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3123 break;
3124 }
07716717
DK		 3125 case KVM_SET_CPUID2: {
3126 struct kvm_cpuid2 __user *cpuid_arg = argp;
3127 struct kvm_cpuid2 cpuid;
3128
3129 r = -EFAULT;
3130 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3131 goto out;
3132 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3133 cpuid_arg->entries);
07716717
DK		 3134 break;
3135 }
3136 case KVM_GET_CPUID2: {
3137 struct kvm_cpuid2 __user *cpuid_arg = argp;
3138 struct kvm_cpuid2 cpuid;
3139
3140 r = -EFAULT;
3141 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3142 goto out;
3143 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3144 cpuid_arg->entries);
07716717
DK		 3145 if (r)
3146 goto out;
3147 r = -EFAULT;
3148 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3149 goto out;
3150 r = 0;
3151 break;
3152 }
313a3dc7
CO		 3153 case KVM_GET_MSRS:
3154 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3155 break;
3156 case KVM_SET_MSRS:
3157 r = msr_io(vcpu, argp, do_set_msr, 0);
3158 break;
b209749f
AK		 3159 case KVM_TPR_ACCESS_REPORTING: {
3160 struct kvm_tpr_access_ctl tac;
3161
3162 r = -EFAULT;
3163 if (copy_from_user(&tac, argp, sizeof tac))
3164 goto out;
3165 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3166 if (r)
3167 goto out;
3168 r = -EFAULT;
3169 if (copy_to_user(argp, &tac, sizeof tac))
3170 goto out;
3171 r = 0;
3172 break;
3173 };
b93463aa
AK		 3174 case KVM_SET_VAPIC_ADDR: {
3175 struct kvm_vapic_addr va;
3176
3177 r = -EINVAL;
3178 if (!irqchip_in_kernel(vcpu->kvm))
3179 goto out;
3180 r = -EFAULT;
3181 if (copy_from_user(&va, argp, sizeof va))
3182 goto out;
3183 r = 0;
3184 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3185 break;
3186 }
890ca9ae
HY		 3187 case KVM_X86_SETUP_MCE: {
3188 u64 mcg_cap;
3189
3190 r = -EFAULT;
3191 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3192 goto out;
3193 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3194 break;
3195 }
3196 case KVM_X86_SET_MCE: {
3197 struct kvm_x86_mce mce;
3198
3199 r = -EFAULT;
3200 if (copy_from_user(&mce, argp, sizeof mce))
3201 goto out;
3202 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3203 break;
3204 }
3cfc3092
JK		 3205 case KVM_GET_VCPU_EVENTS: {
3206 struct kvm_vcpu_events events;
3207
3208 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3209
3210 r = -EFAULT;
3211 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3212 break;
3213 r = 0;
3214 break;
3215 }
3216 case KVM_SET_VCPU_EVENTS: {
3217 struct kvm_vcpu_events events;
3218
3219 r = -EFAULT;
3220 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3221 break;
3222
3223 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3224 break;
3225 }
a1efbe77
JK		 3226 case KVM_GET_DEBUGREGS: {
3227 struct kvm_debugregs dbgregs;
3228
3229 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3230
3231 r = -EFAULT;
3232 if (copy_to_user(argp, &dbgregs,
3233 sizeof(struct kvm_debugregs)))
3234 break;
3235 r = 0;
3236 break;
3237 }
3238 case KVM_SET_DEBUGREGS: {
3239 struct kvm_debugregs dbgregs;
3240
3241 r = -EFAULT;
3242 if (copy_from_user(&dbgregs, argp,
3243 sizeof(struct kvm_debugregs)))
3244 break;
3245
3246 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3247 break;
3248 }
2d5b5a66 3249 case KVM_GET_XSAVE: {
d1ac91d8 3250 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3251 r = -ENOMEM;
d1ac91d8 3252 if (!u.xsave)
2d5b5a66
SY		 3253 break;
3254
d1ac91d8 3255 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3256
3257 r = -EFAULT;
d1ac91d8 3258 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3259 break;
3260 r = 0;
3261 break;
3262 }
3263 case KVM_SET_XSAVE: {
ff5c2c03 3264 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3265 if (IS_ERR(u.xsave))
3266 return PTR_ERR(u.xsave);
2d5b5a66 3267
d1ac91d8 3268 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3269 break;
3270 }
3271 case KVM_GET_XCRS: {
d1ac91d8 3272 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3273 r = -ENOMEM;
d1ac91d8 3274 if (!u.xcrs)
2d5b5a66
SY		 3275 break;
3276
d1ac91d8 3277 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3278
3279 r = -EFAULT;
d1ac91d8 3280 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3281 sizeof(struct kvm_xcrs)))
3282 break;
3283 r = 0;
3284 break;
3285 }
3286 case KVM_SET_XCRS: {
ff5c2c03 3287 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3288 if (IS_ERR(u.xcrs))
3289 return PTR_ERR(u.xcrs);
2d5b5a66 3290
d1ac91d8 3291 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3292 break;
3293 }
92a1f12d
JR		 3294 case KVM_SET_TSC_KHZ: {
3295 u32 user_tsc_khz;
3296
3297 r = -EINVAL;
92a1f12d
JR		 3298 user_tsc_khz = (u32)arg;
3299
3300 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3301 goto out;
3302
cc578287
ZA		 3303 if (user_tsc_khz == 0)
3304 user_tsc_khz = tsc_khz;
3305
3306 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3307
3308 r = 0;
3309 goto out;
3310 }
3311 case KVM_GET_TSC_KHZ: {
cc578287 3312 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3313 goto out;
3314 }
1c0b28c2
EM		 3315 case KVM_KVMCLOCK_CTRL: {
3316 r = kvm_set_guest_paused(vcpu);
3317 goto out;
3318 }
313a3dc7
CO		 3319 default:
3320 r = -EINVAL;
3321 }
3322out:
d1ac91d8 3323 kfree(u.buffer);
313a3dc7
CO		 3324 return r;
3325}
3326
5b1c1493
CO		 3327int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3328{
3329 return VM_FAULT_SIGBUS;
3330}
3331
1fe779f8
CO		 3332static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3333{
3334 int ret;
3335
3336 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3337 return -EINVAL;
1fe779f8
CO		 3338 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3339 return ret;
3340}
3341
b927a3ce
SY		 3342static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3343 u64 ident_addr)
3344{
3345 kvm->arch.ept_identity_map_addr = ident_addr;
3346 return 0;
3347}
3348
1fe779f8
CO		 3349static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3350 u32 kvm_nr_mmu_pages)
3351{
3352 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3353 return -EINVAL;
3354
79fac95e 3355 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3356
3357 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3358 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3359
79fac95e 3360 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3361 return 0;
3362}
3363
3364static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3365{
39de71ec 3366 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3367}
3368
1fe779f8
CO		 3369static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3370{
3371 int r;
3372
3373 r = 0;
3374 switch (chip->chip_id) {
3375 case KVM_IRQCHIP_PIC_MASTER:
3376 memcpy(&chip->chip.pic,
3377 &pic_irqchip(kvm)->pics[0],
3378 sizeof(struct kvm_pic_state));
3379 break;
3380 case KVM_IRQCHIP_PIC_SLAVE:
3381 memcpy(&chip->chip.pic,
3382 &pic_irqchip(kvm)->pics[1],
3383 sizeof(struct kvm_pic_state));
3384 break;
3385 case KVM_IRQCHIP_IOAPIC:
eba0226b 3386 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3387 break;
3388 default:
3389 r = -EINVAL;
3390 break;
3391 }
3392 return r;
3393}
3394
3395static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3396{
3397 int r;
3398
3399 r = 0;
3400 switch (chip->chip_id) {
3401 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3402 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3403 memcpy(&pic_irqchip(kvm)->pics[0],
3404 &chip->chip.pic,
3405 sizeof(struct kvm_pic_state));
f4f51050 3406 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3407 break;
3408 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3409 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3410 memcpy(&pic_irqchip(kvm)->pics[1],
3411 &chip->chip.pic,
3412 sizeof(struct kvm_pic_state));
f4f51050 3413 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3414 break;
3415 case KVM_IRQCHIP_IOAPIC:
eba0226b 3416 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3417 break;
3418 default:
3419 r = -EINVAL;
3420 break;
3421 }
3422 kvm_pic_update_irq(pic_irqchip(kvm));
3423 return r;
3424}
3425
e0f63cb9
SY		 3426static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3427{
3428 int r = 0;
3429
894a9c55 3430 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3431 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3432 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3433 return r;
3434}
3435
3436static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3437{
3438 int r = 0;
3439
894a9c55 3440 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3441 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3442 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3443 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3444 return r;
3445}
3446
3447static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3448{
3449 int r = 0;
3450
3451 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3452 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3453 sizeof(ps->channels));
3454 ps->flags = kvm->arch.vpit->pit_state.flags;
3455 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3456 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3457 return r;
3458}
3459
3460static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3461{
3462 int r = 0, start = 0;
3463 u32 prev_legacy, cur_legacy;
3464 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3465 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3466 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3467 if (!prev_legacy && cur_legacy)
3468 start = 1;
3469 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3470 sizeof(kvm->arch.vpit->pit_state.channels));
3471 kvm->arch.vpit->pit_state.flags = ps->flags;
3472 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3473 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3474 return r;
3475}
3476
52d939a0
MT		 3477static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3478 struct kvm_reinject_control *control)
3479{
3480 if (!kvm->arch.vpit)
3481 return -ENXIO;
894a9c55 3482 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3483 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3484 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3485 return 0;
3486}
3487
95d4c16c 3488/**
60c34612
TY		 3489 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3490 * @kvm: kvm instance
3491 * @log: slot id and address to which we copy the log
95d4c16c 3492 *
60c34612
TY		 3493 * We need to keep it in mind that VCPU threads can write to the bitmap
3494 * concurrently. So, to avoid losing data, we keep the following order for
3495 * each bit:
95d4c16c 3496 *
60c34612
TY		 3497 * 1. Take a snapshot of the bit and clear it if needed.
3498 * 2. Write protect the corresponding page.
3499 * 3. Flush TLB's if needed.
3500 * 4. Copy the snapshot to the userspace.
95d4c16c 3501 *
60c34612
TY		 3502 * Between 2 and 3, the guest may write to the page using the remaining TLB
3503 * entry. This is not a problem because the page will be reported dirty at
3504 * step 4 using the snapshot taken before and step 3 ensures that successive
3505 * writes will be logged for the next call.
5bb064dc 3506 */
60c34612 3507int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3508{
7850ac54 3509 int r;
5bb064dc 3510 struct kvm_memory_slot *memslot;
60c34612
TY		 3511 unsigned long n, i;
3512 unsigned long *dirty_bitmap;
3513 unsigned long *dirty_bitmap_buffer;
3514 bool is_dirty = false;
5bb064dc 3515
79fac95e 3516 mutex_lock(&kvm->slots_lock);
5bb064dc 3517
b050b015 3518 r = -EINVAL;
bbacc0c1 3519 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3520 goto out;
3521
28a37544 3522 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3523
3524 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3525 r = -ENOENT;
60c34612 3526 if (!dirty_bitmap)
b050b015
MT		 3527 goto out;
3528
87bf6e7d 3529 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3530
60c34612
TY		 3531 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3532 memset(dirty_bitmap_buffer, 0, n);
b050b015 3533
60c34612 3534 spin_lock(&kvm->mmu_lock);
b050b015 3535
60c34612
TY		 3536 for (i = 0; i < n / sizeof(long); i++) {
3537 unsigned long mask;
3538 gfn_t offset;
cdfca7b3 3539
60c34612
TY		 3540 if (!dirty_bitmap[i])
3541 continue;
b050b015 3542
60c34612 3543 is_dirty = true;
914ebccd 3544
60c34612
TY		 3545 mask = xchg(&dirty_bitmap[i], 0);
3546 dirty_bitmap_buffer[i] = mask;
edde99ce 3547
60c34612
TY		 3548 offset = i * BITS_PER_LONG;
3549 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3550 }
60c34612
TY		 3551 if (is_dirty)
3552 kvm_flush_remote_tlbs(kvm);
3553
3554 spin_unlock(&kvm->mmu_lock);
3555
3556 r = -EFAULT;
3557 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3558 goto out;
b050b015 3559
5bb064dc
ZX		 3560 r = 0;
3561out:
79fac95e 3562 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3563 return r;
3564}
3565
aa2fbe6d
YZ		 3566int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3567 bool line_status)
23d43cf9
CD		 3568{
3569 if (!irqchip_in_kernel(kvm))
3570 return -ENXIO;
3571
3572 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3573 irq_event->irq, irq_event->level,
3574 line_status);
23d43cf9
CD		 3575 return 0;
3576}
3577
1fe779f8
CO		 3578long kvm_arch_vm_ioctl(struct file *filp,
3579 unsigned int ioctl, unsigned long arg)
3580{
3581 struct kvm *kvm = filp->private_data;
3582 void __user *argp = (void __user *)arg;
367e1319 3583 int r = -ENOTTY;
f0d66275
DH		 3584 /*
3585 * This union makes it completely explicit to gcc-3.x
3586 * that these two variables' stack usage should be
3587 * combined, not added together.
3588 */
3589 union {
3590 struct kvm_pit_state ps;
e9f42757 3591 struct kvm_pit_state2 ps2;
c5ff41ce 3592 struct kvm_pit_config pit_config;
f0d66275 3593 } u;
1fe779f8
CO		 3594
3595 switch (ioctl) {
3596 case KVM_SET_TSS_ADDR:
3597 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3598 break;
b927a3ce
SY		 3599 case KVM_SET_IDENTITY_MAP_ADDR: {
3600 u64 ident_addr;
3601
3602 r = -EFAULT;
3603 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3604 goto out;
3605 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3606 break;
3607 }
1fe779f8
CO		 3608 case KVM_SET_NR_MMU_PAGES:
3609 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3610 break;
3611 case KVM_GET_NR_MMU_PAGES:
3612 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3613 break;
3ddea128
MT		 3614 case KVM_CREATE_IRQCHIP: {
3615 struct kvm_pic *vpic;
3616
3617 mutex_lock(&kvm->lock);
3618 r = -EEXIST;
3619 if (kvm->arch.vpic)
3620 goto create_irqchip_unlock;
3e515705
AK		 3621 r = -EINVAL;
3622 if (atomic_read(&kvm->online_vcpus))
3623 goto create_irqchip_unlock;
1fe779f8 3624 r = -ENOMEM;
3ddea128
MT		 3625 vpic = kvm_create_pic(kvm);
3626 if (vpic) {
1fe779f8
CO		 3627 r = kvm_ioapic_init(kvm);
3628 if (r) {
175504cd 3629 mutex_lock(&kvm->slots_lock);
72bb2fcd 3630 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3631 &vpic->dev_master);
3632 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3633 &vpic->dev_slave);
3634 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3635 &vpic->dev_eclr);
175504cd 3636 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3637 kfree(vpic);
3638 goto create_irqchip_unlock;
1fe779f8
CO		 3639 }
3640 } else
3ddea128
MT		 3641 goto create_irqchip_unlock;
3642 smp_wmb();
3643 kvm->arch.vpic = vpic;
3644 smp_wmb();
399ec807
AK		 3645 r = kvm_setup_default_irq_routing(kvm);
3646 if (r) {
175504cd 3647 mutex_lock(&kvm->slots_lock);
3ddea128 3648 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3649 kvm_ioapic_destroy(kvm);
3650 kvm_destroy_pic(kvm);
3ddea128 3651 mutex_unlock(&kvm->irq_lock);
175504cd 3652 mutex_unlock(&kvm->slots_lock);
399ec807 3653 }
3ddea128
MT		 3654 create_irqchip_unlock:
3655 mutex_unlock(&kvm->lock);
1fe779f8 3656 break;
3ddea128 3657 }
7837699f 3658 case KVM_CREATE_PIT:
c5ff41ce
JK		 3659 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3660 goto create_pit;
3661 case KVM_CREATE_PIT2:
3662 r = -EFAULT;
3663 if (copy_from_user(&u.pit_config, argp,
3664 sizeof(struct kvm_pit_config)))
3665 goto out;
3666 create_pit:
79fac95e 3667 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3668 r = -EEXIST;
3669 if (kvm->arch.vpit)
3670 goto create_pit_unlock;
7837699f 3671 r = -ENOMEM;
c5ff41ce 3672 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3673 if (kvm->arch.vpit)
3674 r = 0;
269e05e4 3675 create_pit_unlock:
79fac95e 3676 mutex_unlock(&kvm->slots_lock);
7837699f 3677 break;
1fe779f8
CO		 3678 case KVM_GET_IRQCHIP: {
3679 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3680 struct kvm_irqchip *chip;
1fe779f8 3681
ff5c2c03
SL		 3682 chip = memdup_user(argp, sizeof(*chip));
3683 if (IS_ERR(chip)) {
3684 r = PTR_ERR(chip);
1fe779f8 3685 goto out;
ff5c2c03
SL		 3686 }
3687
1fe779f8
CO		 3688 r = -ENXIO;
3689 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3690 goto get_irqchip_out;
3691 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3692 if (r)
f0d66275 3693 goto get_irqchip_out;
1fe779f8 3694 r = -EFAULT;
f0d66275
DH		 3695 if (copy_to_user(argp, chip, sizeof *chip))
3696 goto get_irqchip_out;
1fe779f8 3697 r = 0;
f0d66275
DH		 3698 get_irqchip_out:
3699 kfree(chip);
1fe779f8
CO		 3700 break;
3701 }
3702 case KVM_SET_IRQCHIP: {
3703 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3704 struct kvm_irqchip *chip;
1fe779f8 3705
ff5c2c03
SL		 3706 chip = memdup_user(argp, sizeof(*chip));
3707 if (IS_ERR(chip)) {
3708 r = PTR_ERR(chip);
1fe779f8 3709 goto out;
ff5c2c03
SL		 3710 }
3711
1fe779f8
CO		 3712 r = -ENXIO;
3713 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3714 goto set_irqchip_out;
3715 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3716 if (r)
f0d66275 3717 goto set_irqchip_out;
1fe779f8 3718 r = 0;
f0d66275
DH		 3719 set_irqchip_out:
3720 kfree(chip);
1fe779f8
CO		 3721 break;
3722 }
e0f63cb9 3723 case KVM_GET_PIT: {
e0f63cb9 3724 r = -EFAULT;
f0d66275 3725 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3726 goto out;
3727 r = -ENXIO;
3728 if (!kvm->arch.vpit)
3729 goto out;
f0d66275 3730 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3731 if (r)
3732 goto out;
3733 r = -EFAULT;
f0d66275 3734 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3735 goto out;
3736 r = 0;
3737 break;
3738 }
3739 case KVM_SET_PIT: {
e0f63cb9 3740 r = -EFAULT;
f0d66275 3741 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3742 goto out;
3743 r = -ENXIO;
3744 if (!kvm->arch.vpit)
3745 goto out;
f0d66275 3746 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3747 break;
3748 }
e9f42757
BK		 3749 case KVM_GET_PIT2: {
3750 r = -ENXIO;
3751 if (!kvm->arch.vpit)
3752 goto out;
3753 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3754 if (r)
3755 goto out;
3756 r = -EFAULT;
3757 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3758 goto out;
3759 r = 0;
3760 break;
3761 }
3762 case KVM_SET_PIT2: {
3763 r = -EFAULT;
3764 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3765 goto out;
3766 r = -ENXIO;
3767 if (!kvm->arch.vpit)
3768 goto out;
3769 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3770 break;
3771 }
52d939a0
MT		 3772 case KVM_REINJECT_CONTROL: {
3773 struct kvm_reinject_control control;
3774 r = -EFAULT;
3775 if (copy_from_user(&control, argp, sizeof(control)))
3776 goto out;
3777 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3778 break;
3779 }
ffde22ac
ES		 3780 case KVM_XEN_HVM_CONFIG: {
3781 r = -EFAULT;
3782 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3783 sizeof(struct kvm_xen_hvm_config)))
3784 goto out;
3785 r = -EINVAL;
3786 if (kvm->arch.xen_hvm_config.flags)
3787 goto out;
3788 r = 0;
3789 break;
3790 }
afbcf7ab 3791 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3792 struct kvm_clock_data user_ns;
3793 u64 now_ns;
3794 s64 delta;
3795
3796 r = -EFAULT;
3797 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3798 goto out;
3799
3800 r = -EINVAL;
3801 if (user_ns.flags)
3802 goto out;
3803
3804 r = 0;
395c6b0a 3805 local_irq_disable();
759379dd 3806 now_ns = get_kernel_ns();
afbcf7ab 3807 delta = user_ns.clock - now_ns;
395c6b0a 3808 local_irq_enable();
afbcf7ab
GC		 3809 kvm->arch.kvmclock_offset = delta;
3810 break;
3811 }
3812 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3813 struct kvm_clock_data user_ns;
3814 u64 now_ns;
3815
395c6b0a 3816 local_irq_disable();
759379dd 3817 now_ns = get_kernel_ns();
afbcf7ab 3818 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3819 local_irq_enable();
afbcf7ab 3820 user_ns.flags = 0;
97e69aa6 3821 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3822
3823 r = -EFAULT;
3824 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3825 goto out;
3826 r = 0;
3827 break;
3828 }
3829
1fe779f8
CO		 3830 default:
3831 ;
3832 }
3833out:
3834 return r;
3835}
3836
a16b043c 3837static void kvm_init_msr_list(void)
043405e1
CO		 3838{
3839 u32 dummy[2];
3840 unsigned i, j;
3841
e3267cbb
GC		 3842 /* skip the first msrs in the list. KVM-specific */
3843 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3844 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3845 continue;
3846 if (j < i)
3847 msrs_to_save[j] = msrs_to_save[i];
3848 j++;
3849 }
3850 num_msrs_to_save = j;
3851}
3852
bda9020e
MT		 3853static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3854 const void *v)
bbd9b64e 3855{
70252a10
AK		 3856 int handled = 0;
3857 int n;
3858
3859 do {
3860 n = min(len, 8);
3861 if (!(vcpu->arch.apic &&
3862 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3863 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3864 break;
3865 handled += n;
3866 addr += n;
3867 len -= n;
3868 v += n;
3869 } while (len);
bbd9b64e 3870
70252a10 3871 return handled;
bbd9b64e
CO		 3872}
3873
bda9020e 3874static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3875{
70252a10
AK		 3876 int handled = 0;
3877 int n;
3878
3879 do {
3880 n = min(len, 8);
3881 if (!(vcpu->arch.apic &&
3882 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3883 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3884 break;
3885 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3886 handled += n;
3887 addr += n;
3888 len -= n;
3889 v += n;
3890 } while (len);
bbd9b64e 3891
70252a10 3892 return handled;
bbd9b64e
CO		 3893}
3894
2dafc6c2
GN		 3895static void kvm_set_segment(struct kvm_vcpu *vcpu,
3896 struct kvm_segment *var, int seg)
3897{
3898 kvm_x86_ops->set_segment(vcpu, var, seg);
3899}
3900
3901void kvm_get_segment(struct kvm_vcpu *vcpu,
3902 struct kvm_segment *var, int seg)
3903{
3904 kvm_x86_ops->get_segment(vcpu, var, seg);
3905}
3906
e459e322 3907gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3908{
3909 gpa_t t_gpa;
ab9ae313 3910 struct x86_exception exception;
02f59dc9
JR		 3911
3912 BUG_ON(!mmu_is_nested(vcpu));
3913
3914 /* NPT walks are always user-walks */
3915 access |= PFERR_USER_MASK;
ab9ae313 3916 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3917
3918 return t_gpa;
3919}
3920
ab9ae313
AK		 3921gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3922 struct x86_exception *exception)
1871c602
GN		 3923{
3924 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3925 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3926}
3927
ab9ae313
AK		 3928 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3929 struct x86_exception *exception)
1871c602
GN		 3930{
3931 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3932 access |= PFERR_FETCH_MASK;
ab9ae313 3933 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3934}
3935
ab9ae313
AK		 3936gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3937 struct x86_exception *exception)
1871c602
GN		 3938{
3939 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3940 access |= PFERR_WRITE_MASK;
ab9ae313 3941 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3942}
3943
3944/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3945gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3946 struct x86_exception *exception)
1871c602 3947{
ab9ae313 3948 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3949}
3950
3951static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3952 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3953 struct x86_exception *exception)
bbd9b64e
CO		 3954{
3955 void *data = val;
10589a46 3956 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3957
3958 while (bytes) {
14dfe855 3959 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3960 exception);
bbd9b64e 3961 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3962 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3963 int ret;
3964
bcc55cba 3965 if (gpa == UNMAPPED_GVA)
ab9ae313 3966 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3967 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3968 if (ret < 0) {
c3cd7ffa 3969 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3970 goto out;
3971 }
bbd9b64e 3972
77c2002e
IE		 3973 bytes -= toread;
3974 data += toread;
3975 addr += toread;
bbd9b64e 3976 }
10589a46 3977out:
10589a46 3978 return r;
bbd9b64e 3979}
77c2002e 3980
1871c602 3981/* used for instruction fetching */
0f65dd70
AK		 3982static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3983 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3984 struct x86_exception *exception)
1871c602 3985{
0f65dd70 3986 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3987 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3988
1871c602 3989 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3990 access | PFERR_FETCH_MASK,
3991 exception);
1871c602
GN		 3992}
3993
064aea77 3994int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3995 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3996 struct x86_exception *exception)
1871c602 3997{
0f65dd70 3998 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3999 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4000
1871c602 4001 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4002 exception);
1871c602 4003}
064aea77 4004EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4005
0f65dd70
AK		 4006static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4007 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4008 struct x86_exception *exception)
1871c602 4009{
0f65dd70 4010 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4011 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4012}
4013
6a4d7550 4014int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4015 gva_t addr, void *val,
2dafc6c2 4016 unsigned int bytes,
bcc55cba 4017 struct x86_exception *exception)
77c2002e 4018{
0f65dd70 4019 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4020 void *data = val;
4021 int r = X86EMUL_CONTINUE;
4022
4023 while (bytes) {
14dfe855
JR		 4024 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4025 PFERR_WRITE_MASK,
ab9ae313 4026 exception);
77c2002e
IE		 4027 unsigned offset = addr & (PAGE_SIZE-1);
4028 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4029 int ret;
4030
bcc55cba 4031 if (gpa == UNMAPPED_GVA)
ab9ae313 4032 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4033 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4034 if (ret < 0) {
c3cd7ffa 4035 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4036 goto out;
4037 }
4038
4039 bytes -= towrite;
4040 data += towrite;
4041 addr += towrite;
4042 }
4043out:
4044 return r;
4045}
6a4d7550 4046EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4047
af7cc7d1
XG		 4048static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4049 gpa_t *gpa, struct x86_exception *exception,
4050 bool write)
4051{
97d64b78
AK		 4052 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4053 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4054
97d64b78
AK		 4055 if (vcpu_match_mmio_gva(vcpu, gva)
4056 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4057 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4058 (gva & (PAGE_SIZE - 1));
4f022648 4059 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4060 return 1;
4061 }
4062
af7cc7d1
XG		 4063 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4064
4065 if (*gpa == UNMAPPED_GVA)
4066 return -1;
4067
4068 /* For APIC access vmexit */
4069 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4070 return 1;
4071
4f022648
XG		 4072 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4073 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4074 return 1;
4f022648 4075 }
bebb106a 4076
af7cc7d1
XG		 4077 return 0;
4078}
4079
3200f405 4080int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4081 const void *val, int bytes)
bbd9b64e
CO		 4082{
4083 int ret;
4084
4085 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4086 if (ret < 0)
bbd9b64e 4087 return 0;
f57f2ef5 4088 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4089 return 1;
4090}
4091
77d197b2
XG		 4092struct read_write_emulator_ops {
4093 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4094 int bytes);
4095 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4096 void *val, int bytes);
4097 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4098 int bytes, void *val);
4099 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4100 void *val, int bytes);
4101 bool write;
4102};
4103
4104static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4105{
4106 if (vcpu->mmio_read_completed) {
77d197b2 4107 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4108 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4109 vcpu->mmio_read_completed = 0;
4110 return 1;
4111 }
4112
4113 return 0;
4114}
4115
4116static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4117 void *val, int bytes)
4118{
4119 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4120}
4121
4122static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4123 void *val, int bytes)
4124{
4125 return emulator_write_phys(vcpu, gpa, val, bytes);
4126}
4127
4128static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4129{
4130 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4131 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4132}
4133
4134static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4135 void *val, int bytes)
4136{
4137 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4138 return X86EMUL_IO_NEEDED;
4139}
4140
4141static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4142 void *val, int bytes)
4143{
f78146b0
AK		 4144 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4145
87da7e66 4146 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4147 return X86EMUL_CONTINUE;
4148}
4149
0fbe9b0b 4150static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4151 .read_write_prepare = read_prepare,
4152 .read_write_emulate = read_emulate,
4153 .read_write_mmio = vcpu_mmio_read,
4154 .read_write_exit_mmio = read_exit_mmio,
4155};
4156
0fbe9b0b 4157static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4158 .read_write_emulate = write_emulate,
4159 .read_write_mmio = write_mmio,
4160 .read_write_exit_mmio = write_exit_mmio,
4161 .write = true,
4162};
4163
22388a3c
XG		 4164static int emulator_read_write_onepage(unsigned long addr, void *val,
4165 unsigned int bytes,
4166 struct x86_exception *exception,
4167 struct kvm_vcpu *vcpu,
0fbe9b0b 4168 const struct read_write_emulator_ops *ops)
bbd9b64e 4169{
af7cc7d1
XG		 4170 gpa_t gpa;
4171 int handled, ret;
22388a3c 4172 bool write = ops->write;
f78146b0 4173 struct kvm_mmio_fragment *frag;
10589a46 4174
22388a3c 4175 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4176
af7cc7d1 4177 if (ret < 0)
bbd9b64e 4178 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4179
4180 /* For APIC access vmexit */
af7cc7d1 4181 if (ret)
bbd9b64e
CO		 4182 goto mmio;
4183
22388a3c 4184 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4185 return X86EMUL_CONTINUE;
4186
4187mmio:
4188 /*
4189 * Is this MMIO handled locally?
4190 */
22388a3c 4191 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4192 if (handled == bytes)
bbd9b64e 4193 return X86EMUL_CONTINUE;
bbd9b64e 4194
70252a10
AK		 4195 gpa += handled;
4196 bytes -= handled;
4197 val += handled;
4198
87da7e66
XG		 4199 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4200 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4201 frag->gpa = gpa;
4202 frag->data = val;
4203 frag->len = bytes;
f78146b0 4204 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4205}
4206
22388a3c
XG		 4207int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4208 void *val, unsigned int bytes,
4209 struct x86_exception *exception,
0fbe9b0b 4210 const struct read_write_emulator_ops *ops)
bbd9b64e 4211{
0f65dd70 4212 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4213 gpa_t gpa;
4214 int rc;
4215
4216 if (ops->read_write_prepare &&
4217 ops->read_write_prepare(vcpu, val, bytes))
4218 return X86EMUL_CONTINUE;
4219
4220 vcpu->mmio_nr_fragments = 0;
0f65dd70 4221
bbd9b64e
CO		 4222 /* Crossing a page boundary? */
4223 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4224 int now;
bbd9b64e
CO		 4225
4226 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4227 rc = emulator_read_write_onepage(addr, val, now, exception,
4228 vcpu, ops);
4229
bbd9b64e
CO		 4230 if (rc != X86EMUL_CONTINUE)
4231 return rc;
4232 addr += now;
4233 val += now;
4234 bytes -= now;
4235 }
22388a3c 4236
f78146b0
AK		 4237 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4238 vcpu, ops);
4239 if (rc != X86EMUL_CONTINUE)
4240 return rc;
4241
4242 if (!vcpu->mmio_nr_fragments)
4243 return rc;
4244
4245 gpa = vcpu->mmio_fragments[0].gpa;
4246
4247 vcpu->mmio_needed = 1;
4248 vcpu->mmio_cur_fragment = 0;
4249
87da7e66 4250 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4251 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4252 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4253 vcpu->run->mmio.phys_addr = gpa;
4254
4255 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4256}
4257
4258static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4259 unsigned long addr,
4260 void *val,
4261 unsigned int bytes,
4262 struct x86_exception *exception)
4263{
4264 return emulator_read_write(ctxt, addr, val, bytes,
4265 exception, &read_emultor);
4266}
4267
4268int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4269 unsigned long addr,
4270 const void *val,
4271 unsigned int bytes,
4272 struct x86_exception *exception)
4273{
4274 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4275 exception, &write_emultor);
bbd9b64e 4276}
bbd9b64e 4277
daea3e73
AK		 4278#define CMPXCHG_TYPE(t, ptr, old, new) \
4279 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4280
4281#ifdef CONFIG_X86_64
4282# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4283#else
4284# define CMPXCHG64(ptr, old, new) \
9749a6c0 4285 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4286#endif
4287
0f65dd70
AK		 4288static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4289 unsigned long addr,
bbd9b64e
CO		 4290 const void *old,
4291 const void *new,
4292 unsigned int bytes,
0f65dd70 4293 struct x86_exception *exception)
bbd9b64e 4294{
0f65dd70 4295 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4296 gpa_t gpa;
4297 struct page *page;
4298 char *kaddr;
4299 bool exchanged;
2bacc55c 4300
daea3e73
AK		 4301 /* guests cmpxchg8b have to be emulated atomically */
4302 if (bytes > 8 || (bytes & (bytes - 1)))
4303 goto emul_write;
10589a46 4304
daea3e73 4305 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4306
daea3e73
AK		 4307 if (gpa == UNMAPPED_GVA ||
4308 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4309 goto emul_write;
2bacc55c 4310
daea3e73
AK		 4311 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4312 goto emul_write;
72dc67a6 4313
daea3e73 4314 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4315 if (is_error_page(page))
c19b8bd6 4316 goto emul_write;
72dc67a6 4317
8fd75e12 4318 kaddr = kmap_atomic(page);
daea3e73
AK		 4319 kaddr += offset_in_page(gpa);
4320 switch (bytes) {
4321 case 1:
4322 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4323 break;
4324 case 2:
4325 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4326 break;
4327 case 4:
4328 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4329 break;
4330 case 8:
4331 exchanged = CMPXCHG64(kaddr, old, new);
4332 break;
4333 default:
4334 BUG();
2bacc55c 4335 }
8fd75e12 4336 kunmap_atomic(kaddr);
daea3e73
AK		 4337 kvm_release_page_dirty(page);
4338
4339 if (!exchanged)
4340 return X86EMUL_CMPXCHG_FAILED;
4341
f57f2ef5 4342 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4343
4344 return X86EMUL_CONTINUE;
4a5f48f6 4345
3200f405 4346emul_write:
daea3e73 4347 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4348
0f65dd70 4349 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4350}
4351
cf8f70bf
GN		 4352static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4353{
4354 /* TODO: String I/O for in kernel device */
4355 int r;
4356
4357 if (vcpu->arch.pio.in)
4358 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4359 vcpu->arch.pio.size, pd);
4360 else
4361 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4362 vcpu->arch.pio.port, vcpu->arch.pio.size,
4363 pd);
4364 return r;
4365}
4366
6f6fbe98
XG		 4367static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4368 unsigned short port, void *val,
4369 unsigned int count, bool in)
cf8f70bf 4370{
6f6fbe98 4371 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4372
4373 vcpu->arch.pio.port = port;
6f6fbe98 4374 vcpu->arch.pio.in = in;
7972995b 4375 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4376 vcpu->arch.pio.size = size;
4377
4378 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4379 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4380 return 1;
4381 }
4382
4383 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4384 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4385 vcpu->run->io.size = size;
4386 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4387 vcpu->run->io.count = count;
4388 vcpu->run->io.port = port;
4389
4390 return 0;
4391}
4392
6f6fbe98
XG		 4393static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4394 int size, unsigned short port, void *val,
4395 unsigned int count)
cf8f70bf 4396{
ca1d4a9e 4397 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4398 int ret;
ca1d4a9e 4399
6f6fbe98
XG		 4400 if (vcpu->arch.pio.count)
4401 goto data_avail;
cf8f70bf 4402
6f6fbe98
XG		 4403 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4404 if (ret) {
4405data_avail:
4406 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4407 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4408 return 1;
4409 }
4410
cf8f70bf
GN		 4411 return 0;
4412}
4413
6f6fbe98
XG		 4414static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4415 int size, unsigned short port,
4416 const void *val, unsigned int count)
4417{
4418 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4419
4420 memcpy(vcpu->arch.pio_data, val, size * count);
4421 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4422}
4423
bbd9b64e
CO		 4424static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4425{
4426 return kvm_x86_ops->get_segment_base(vcpu, seg);
4427}
4428
3cb16fe7 4429static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4430{
3cb16fe7 4431 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4432}
4433
f5f48ee1
SY		 4434int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4435{
4436 if (!need_emulate_wbinvd(vcpu))
4437 return X86EMUL_CONTINUE;
4438
4439 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4440 int cpu = get_cpu();
4441
4442 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4443 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4444 wbinvd_ipi, NULL, 1);
2eec7343 4445 put_cpu();
f5f48ee1 4446 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4447 } else
4448 wbinvd();
f5f48ee1
SY		 4449 return X86EMUL_CONTINUE;
4450}
4451EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4452
bcaf5cc5
AK		 4453static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4454{
4455 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4456}
4457
717746e3 4458int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4459{
717746e3 4460 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4461}
4462
717746e3 4463int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4464{
338dbc97 4465
717746e3 4466 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4467}
4468
52a46617 4469static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4470{
52a46617 4471 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4472}
4473
717746e3 4474static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4475{
717746e3 4476 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4477 unsigned long value;
4478
4479 switch (cr) {
4480 case 0:
4481 value = kvm_read_cr0(vcpu);
4482 break;
4483 case 2:
4484 value = vcpu->arch.cr2;
4485 break;
4486 case 3:
9f8fe504 4487 value = kvm_read_cr3(vcpu);
52a46617
GN		 4488 break;
4489 case 4:
4490 value = kvm_read_cr4(vcpu);
4491 break;
4492 case 8:
4493 value = kvm_get_cr8(vcpu);
4494 break;
4495 default:
a737f256 4496 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4497 return 0;
4498 }
4499
4500 return value;
4501}
4502
717746e3 4503static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4504{
717746e3 4505 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4506 int res = 0;
4507
52a46617
GN		 4508 switch (cr) {
4509 case 0:
49a9b07e 4510 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4511 break;
4512 case 2:
4513 vcpu->arch.cr2 = val;
4514 break;
4515 case 3:
2390218b 4516 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4517 break;
4518 case 4:
a83b29c6 4519 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4520 break;
4521 case 8:
eea1cff9 4522 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4523 break;
4524 default:
a737f256 4525 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4526 res = -1;
52a46617 4527 }
0f12244f
GN		 4528
4529 return res;
52a46617
GN		 4530}
4531
4cee4798
KW		 4532static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4533{
4534 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4535}
4536
717746e3 4537static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4538{
717746e3 4539 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4540}
4541
4bff1e86 4542static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4543{
4bff1e86 4544 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4545}
4546
4bff1e86 4547static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4548{
4bff1e86 4549 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4550}
4551
1ac9d0cf
AK		 4552static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4553{
4554 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4555}
4556
4557static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4558{
4559 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4560}
4561
4bff1e86
AK		 4562static unsigned long emulator_get_cached_segment_base(
4563 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4564{
4bff1e86 4565 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4566}
4567
1aa36616
AK		 4568static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4569 struct desc_struct *desc, u32 *base3,
4570 int seg)
2dafc6c2
GN		 4571{
4572 struct kvm_segment var;
4573
4bff1e86 4574 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4575 *selector = var.selector;
2dafc6c2 4576
378a8b09
GN		 4577 if (var.unusable) {
4578 memset(desc, 0, sizeof(*desc));
2dafc6c2 4579 return false;
378a8b09 4580 }
2dafc6c2
GN		 4581
4582 if (var.g)
4583 var.limit >>= 12;
4584 set_desc_limit(desc, var.limit);
4585 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4586#ifdef CONFIG_X86_64
4587 if (base3)
4588 *base3 = var.base >> 32;
4589#endif
2dafc6c2
GN		 4590 desc->type = var.type;
4591 desc->s = var.s;
4592 desc->dpl = var.dpl;
4593 desc->p = var.present;
4594 desc->avl = var.avl;
4595 desc->l = var.l;
4596 desc->d = var.db;
4597 desc->g = var.g;
4598
4599 return true;
4600}
4601
1aa36616
AK		 4602static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4603 struct desc_struct *desc, u32 base3,
4604 int seg)
2dafc6c2 4605{
4bff1e86 4606 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4607 struct kvm_segment var;
4608
1aa36616 4609 var.selector = selector;
2dafc6c2 4610 var.base = get_desc_base(desc);
5601d05b
GN		 4611#ifdef CONFIG_X86_64
4612 var.base |= ((u64)base3) << 32;
4613#endif
2dafc6c2
GN		 4614 var.limit = get_desc_limit(desc);
4615 if (desc->g)
4616 var.limit = (var.limit << 12) | 0xfff;
4617 var.type = desc->type;
4618 var.present = desc->p;
4619 var.dpl = desc->dpl;
4620 var.db = desc->d;
4621 var.s = desc->s;
4622 var.l = desc->l;
4623 var.g = desc->g;
4624 var.avl = desc->avl;
4625 var.present = desc->p;
4626 var.unusable = !var.present;
4627 var.padding = 0;
4628
4629 kvm_set_segment(vcpu, &var, seg);
4630 return;
4631}
4632
717746e3
AK		 4633static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4634 u32 msr_index, u64 *pdata)
4635{
4636 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4637}
4638
4639static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4640 u32 msr_index, u64 data)
4641{
8fe8ab46
WA		 4642 struct msr_data msr;
4643
4644 msr.data = data;
4645 msr.index = msr_index;
4646 msr.host_initiated = false;
4647 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4648}
4649
222d21aa
AK		 4650static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4651 u32 pmc, u64 *pdata)
4652{
4653 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4654}
4655
6c3287f7
AK		 4656static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4657{
4658 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4659}
4660
5037f6f3
AK		 4661static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4662{
4663 preempt_disable();
5197b808 4664 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4665 /*
4666 * CR0.TS may reference the host fpu state, not the guest fpu state,
4667 * so it may be clear at this point.
4668 */
4669 clts();
4670}
4671
4672static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4673{
4674 preempt_enable();
4675}
4676
2953538e 4677static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4678 struct x86_instruction_info *info,
c4f035c6
AK		 4679 enum x86_intercept_stage stage)
4680{
2953538e 4681 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4682}
4683
0017f93a 4684static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4685 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4686{
0017f93a 4687 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4688}
4689
dd856efa
AK		 4690static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4691{
4692 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4693}
4694
4695static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4696{
4697 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4698}
4699
0225fb50 4700static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4701 .read_gpr = emulator_read_gpr,
4702 .write_gpr = emulator_write_gpr,
1871c602 4703 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4704 .write_std = kvm_write_guest_virt_system,
1871c602 4705 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4706 .read_emulated = emulator_read_emulated,
4707 .write_emulated = emulator_write_emulated,
4708 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4709 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4710 .pio_in_emulated = emulator_pio_in_emulated,
4711 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4712 .get_segment = emulator_get_segment,
4713 .set_segment = emulator_set_segment,
5951c442 4714 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4715 .get_gdt = emulator_get_gdt,
160ce1f1 4716 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4717 .set_gdt = emulator_set_gdt,
4718 .set_idt = emulator_set_idt,
52a46617
GN		 4719 .get_cr = emulator_get_cr,
4720 .set_cr = emulator_set_cr,
4cee4798 4721 .set_rflags = emulator_set_rflags,
9c537244 4722 .cpl = emulator_get_cpl,
35aa5375
GN		 4723 .get_dr = emulator_get_dr,
4724 .set_dr = emulator_set_dr,
717746e3
AK		 4725 .set_msr = emulator_set_msr,
4726 .get_msr = emulator_get_msr,
222d21aa 4727 .read_pmc = emulator_read_pmc,
6c3287f7 4728 .halt = emulator_halt,
bcaf5cc5 4729 .wbinvd = emulator_wbinvd,
d6aa1000 4730 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4731 .get_fpu = emulator_get_fpu,
4732 .put_fpu = emulator_put_fpu,
c4f035c6 4733 .intercept = emulator_intercept,
bdb42f5a 4734 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4735};
4736
95cb2295
GN		 4737static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4738{
4739 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4740 /*
4741 * an sti; sti; sequence only disable interrupts for the first
4742 * instruction. So, if the last instruction, be it emulated or
4743 * not, left the system with the INT_STI flag enabled, it
4744 * means that the last instruction is an sti. We should not
4745 * leave the flag on in this case. The same goes for mov ss
4746 */
4747 if (!(int_shadow & mask))
4748 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4749}
4750
54b8486f
GN		 4751static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4752{
4753 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4754 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4755 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4756 else if (ctxt->exception.error_code_valid)
4757 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4758 ctxt->exception.error_code);
54b8486f 4759 else
da9cb575 4760 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4761}
4762
dd856efa 4763static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4764{
9dac77fa 4765 memset(&ctxt->twobyte, 0,
dd856efa 4766 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4767
9dac77fa
AK		 4768 ctxt->fetch.start = 0;
4769 ctxt->fetch.end = 0;
4770 ctxt->io_read.pos = 0;
4771 ctxt->io_read.end = 0;
4772 ctxt->mem_read.pos = 0;
4773 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4774}
4775
8ec4722d
MG		 4776static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4777{
adf52235 4778 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4779 int cs_db, cs_l;
4780
8ec4722d
MG		 4781 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4782
adf52235
TY		 4783 ctxt->eflags = kvm_get_rflags(vcpu);
4784 ctxt->eip = kvm_rip_read(vcpu);
4785 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4786 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4787 cs_l ? X86EMUL_MODE_PROT64 :
4788 cs_db ? X86EMUL_MODE_PROT32 :
4789 X86EMUL_MODE_PROT16;
4790 ctxt->guest_mode = is_guest_mode(vcpu);
4791
dd856efa 4792 init_decode_cache(ctxt);
7ae441ea 4793 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4794}
4795
71f9833b 4796int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4797{
9d74191a 4798 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4799 int ret;
4800
4801 init_emulate_ctxt(vcpu);
4802
9dac77fa
AK		 4803 ctxt->op_bytes = 2;
4804 ctxt->ad_bytes = 2;
4805 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4806 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4807
4808 if (ret != X86EMUL_CONTINUE)
4809 return EMULATE_FAIL;
4810
9dac77fa 4811 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4812 kvm_rip_write(vcpu, ctxt->eip);
4813 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4814
4815 if (irq == NMI_VECTOR)
7460fb4a 4816 vcpu->arch.nmi_pending = 0;
63995653
MG		 4817 else
4818 vcpu->arch.interrupt.pending = false;
4819
4820 return EMULATE_DONE;
4821}
4822EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4823
6d77dbfc
GN		 4824static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4825{
fc3a9157
JR		 4826 int r = EMULATE_DONE;
4827
6d77dbfc
GN		 4828 ++vcpu->stat.insn_emulation_fail;
4829 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4830 if (!is_guest_mode(vcpu)) {
4831 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4832 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4833 vcpu->run->internal.ndata = 0;
4834 r = EMULATE_FAIL;
4835 }
6d77dbfc 4836 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4837
4838 return r;
6d77dbfc
GN		 4839}
4840
93c05d3e 4841static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4842 bool write_fault_to_shadow_pgtable,
4843 int emulation_type)
a6f177ef 4844{
95b3cf69 4845 gpa_t gpa = cr2;
8e3d9d06 4846 pfn_t pfn;
a6f177ef 4847
991eebf9
GN		 4848 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4849 return false;
4850
95b3cf69
XG		 4851 if (!vcpu->arch.mmu.direct_map) {
4852 /*
4853 * Write permission should be allowed since only
4854 * write access need to be emulated.
4855 */
4856 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4857
95b3cf69
XG		 4858 /*
4859 * If the mapping is invalid in guest, let cpu retry
4860 * it to generate fault.
4861 */
4862 if (gpa == UNMAPPED_GVA)
4863 return true;
4864 }
a6f177ef 4865
8e3d9d06
XG		 4866 /*
4867 * Do not retry the unhandleable instruction if it faults on the
4868 * readonly host memory, otherwise it will goto a infinite loop:
4869 * retry instruction -> write #PF -> emulation fail -> retry
4870 * instruction -> ...
4871 */
4872 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4873
4874 /*
4875 * If the instruction failed on the error pfn, it can not be fixed,
4876 * report the error to userspace.
4877 */
4878 if (is_error_noslot_pfn(pfn))
4879 return false;
4880
4881 kvm_release_pfn_clean(pfn);
4882
4883 /* The instructions are well-emulated on direct mmu. */
4884 if (vcpu->arch.mmu.direct_map) {
4885 unsigned int indirect_shadow_pages;
4886
4887 spin_lock(&vcpu->kvm->mmu_lock);
4888 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4889 spin_unlock(&vcpu->kvm->mmu_lock);
4890
4891 if (indirect_shadow_pages)
4892 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4893
a6f177ef 4894 return true;
8e3d9d06 4895 }
a6f177ef 4896
95b3cf69
XG		 4897 /*
4898 * if emulation was due to access to shadowed page table
4899 * and it failed try to unshadow page and re-enter the
4900 * guest to let CPU execute the instruction.
4901 */
4902 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4903
4904 /*
4905 * If the access faults on its page table, it can not
4906 * be fixed by unprotecting shadow page and it should
4907 * be reported to userspace.
4908 */
4909 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4910}
4911
1cb3f3ae
XG		 4912static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4913 unsigned long cr2, int emulation_type)
4914{
4915 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4916 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4917
4918 last_retry_eip = vcpu->arch.last_retry_eip;
4919 last_retry_addr = vcpu->arch.last_retry_addr;
4920
4921 /*
4922 * If the emulation is caused by #PF and it is non-page_table
4923 * writing instruction, it means the VM-EXIT is caused by shadow
4924 * page protected, we can zap the shadow page and retry this
4925 * instruction directly.
4926 *
4927 * Note: if the guest uses a non-page-table modifying instruction
4928 * on the PDE that points to the instruction, then we will unmap
4929 * the instruction and go to an infinite loop. So, we cache the
4930 * last retried eip and the last fault address, if we meet the eip
4931 * and the address again, we can break out of the potential infinite
4932 * loop.
4933 */
4934 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4935
4936 if (!(emulation_type & EMULTYPE_RETRY))
4937 return false;
4938
4939 if (x86_page_table_writing_insn(ctxt))
4940 return false;
4941
4942 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4943 return false;
4944
4945 vcpu->arch.last_retry_eip = ctxt->eip;
4946 vcpu->arch.last_retry_addr = cr2;
4947
4948 if (!vcpu->arch.mmu.direct_map)
4949 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4950
22368028 4951 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4952
4953 return true;
4954}
4955
716d51ab
GN		 4956static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4957static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4958
4a1e10d5
PB		 4959static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
4960 unsigned long *db)
4961{
4962 u32 dr6 = 0;
4963 int i;
4964 u32 enable, rwlen;
4965
4966 enable = dr7;
4967 rwlen = dr7 >> 16;
4968 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
4969 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
4970 dr6 |= (1 << i);
4971 return dr6;
4972}
4973
4974static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
4975{
4976 struct kvm_run *kvm_run = vcpu->run;
4977 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
4978 u32 dr6 = 0;
4979
4980 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
4981 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
4982 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4983 vcpu->arch.guest_debug_dr7,
4984 vcpu->arch.eff_db);
4985
4986 if (dr6 != 0) {
4987 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4988 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
4989 get_segment_base(vcpu, VCPU_SREG_CS);
4990
4991 kvm_run->debug.arch.exception = DB_VECTOR;
4992 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4993 *r = EMULATE_USER_EXIT;
4994 return true;
4995 }
4996 }
4997
4998 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
4999 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5000 vcpu->arch.dr7,
5001 vcpu->arch.db);
5002
5003 if (dr6 != 0) {
5004 vcpu->arch.dr6 &= ~15;
5005 vcpu->arch.dr6 |= dr6;
5006 kvm_queue_exception(vcpu, DB_VECTOR);
5007 *r = EMULATE_DONE;
5008 return true;
5009 }
5010 }
5011
5012 return false;
5013}
5014
51d8b661
AP		 5015int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5016 unsigned long cr2,
dc25e89e
AP		 5017 int emulation_type,
5018 void *insn,
5019 int insn_len)
bbd9b64e 5020{
95cb2295 5021 int r;
9d74191a 5022 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5023 bool writeback = true;
93c05d3e 5024 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5025
93c05d3e
XG		 5026 /*
5027 * Clear write_fault_to_shadow_pgtable here to ensure it is
5028 * never reused.
5029 */
5030 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5031 kvm_clear_exception_queue(vcpu);
8d7d8102 5032
571008da 5033 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5034 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5035
5036 /*
5037 * We will reenter on the same instruction since
5038 * we do not set complete_userspace_io. This does not
5039 * handle watchpoints yet, those would be handled in
5040 * the emulate_ops.
5041 */
5042 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5043 return r;
5044
9d74191a
TY		 5045 ctxt->interruptibility = 0;
5046 ctxt->have_exception = false;
5047 ctxt->perm_ok = false;
bbd9b64e 5048
9d74191a 5049 ctxt->only_vendor_specific_insn
4005996e
AK		 5050 = emulation_type & EMULTYPE_TRAP_UD;
5051
9d74191a 5052 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5053
e46479f8 5054 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5055 ++vcpu->stat.insn_emulation;
1d2887e2 5056 if (r != EMULATION_OK) {
4005996e
AK		 5057 if (emulation_type & EMULTYPE_TRAP_UD)
5058 return EMULATE_FAIL;
991eebf9
GN		 5059 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5060 emulation_type))
bbd9b64e 5061 return EMULATE_DONE;
6d77dbfc
GN		 5062 if (emulation_type & EMULTYPE_SKIP)
5063 return EMULATE_FAIL;
5064 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5065 }
5066 }
5067
ba8afb6b 5068 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5069 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5070 return EMULATE_DONE;
5071 }
5072
1cb3f3ae
XG		 5073 if (retry_instruction(ctxt, cr2, emulation_type))
5074 return EMULATE_DONE;
5075
7ae441ea 5076 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5077 changes registers values during IO operation */
7ae441ea
GN		 5078 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5079 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5080 emulator_invalidate_register_cache(ctxt);
7ae441ea 5081 }
4d2179e1 5082
5cd21917 5083restart:
9d74191a 5084 r = x86_emulate_insn(ctxt);
bbd9b64e 5085
775fde86
JR		 5086 if (r == EMULATION_INTERCEPTED)
5087 return EMULATE_DONE;
5088
d2ddd1c4 5089 if (r == EMULATION_FAILED) {
991eebf9
GN		 5090 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5091 emulation_type))
c3cd7ffa
GN		 5092 return EMULATE_DONE;
5093
6d77dbfc 5094 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5095 }
5096
9d74191a 5097 if (ctxt->have_exception) {
54b8486f 5098 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5099 r = EMULATE_DONE;
5100 } else if (vcpu->arch.pio.count) {
3457e419
GN		 5101 if (!vcpu->arch.pio.in)
5102 vcpu->arch.pio.count = 0;
716d51ab 5103 else {
7ae441ea 5104 writeback = false;
716d51ab
GN		 5105 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5106 }
ac0a48c3 5107 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5108 } else if (vcpu->mmio_needed) {
5109 if (!vcpu->mmio_is_write)
5110 writeback = false;
ac0a48c3 5111 r = EMULATE_USER_EXIT;
716d51ab 5112 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5113 } else if (r == EMULATION_RESTART)
5cd21917 5114 goto restart;
d2ddd1c4
GN		 5115 else
5116 r = EMULATE_DONE;
f850e2e6 5117
7ae441ea 5118 if (writeback) {
9d74191a
TY		 5119 toggle_interruptibility(vcpu, ctxt->interruptibility);
5120 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 5121 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5122 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5123 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 5124 } else
5125 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5126
5127 return r;
de7d789a 5128}
51d8b661 5129EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5130
cf8f70bf 5131int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5132{
cf8f70bf 5133 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5134 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5135 size, port, &val, 1);
cf8f70bf 5136 /* do not return to emulator after return from userspace */
7972995b 5137 vcpu->arch.pio.count = 0;
de7d789a
CO		 5138 return ret;
5139}
cf8f70bf 5140EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5141
8cfdc000
ZA		 5142static void tsc_bad(void *info)
5143{
0a3aee0d 5144 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5145}
5146
5147static void tsc_khz_changed(void *data)
c8076604 5148{
8cfdc000
ZA		 5149 struct cpufreq_freqs *freq = data;
5150 unsigned long khz = 0;
5151
5152 if (data)
5153 khz = freq->new;
5154 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5155 khz = cpufreq_quick_get(raw_smp_processor_id());
5156 if (!khz)
5157 khz = tsc_khz;
0a3aee0d 5158 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5159}
5160
c8076604
GH		 5161static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5162 void *data)
5163{
5164 struct cpufreq_freqs *freq = data;
5165 struct kvm *kvm;
5166 struct kvm_vcpu *vcpu;
5167 int i, send_ipi = 0;
5168
8cfdc000
ZA		 5169 /*
5170 * We allow guests to temporarily run on slowing clocks,
5171 * provided we notify them after, or to run on accelerating
5172 * clocks, provided we notify them before. Thus time never
5173 * goes backwards.
5174 *
5175 * However, we have a problem. We can't atomically update
5176 * the frequency of a given CPU from this function; it is
5177 * merely a notifier, which can be called from any CPU.
5178 * Changing the TSC frequency at arbitrary points in time
5179 * requires a recomputation of local variables related to
5180 * the TSC for each VCPU. We must flag these local variables
5181 * to be updated and be sure the update takes place with the
5182 * new frequency before any guests proceed.
5183 *
5184 * Unfortunately, the combination of hotplug CPU and frequency
5185 * change creates an intractable locking scenario; the order
5186 * of when these callouts happen is undefined with respect to
5187 * CPU hotplug, and they can race with each other. As such,
5188 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5189 * undefined; you can actually have a CPU frequency change take
5190 * place in between the computation of X and the setting of the
5191 * variable. To protect against this problem, all updates of
5192 * the per_cpu tsc_khz variable are done in an interrupt
5193 * protected IPI, and all callers wishing to update the value
5194 * must wait for a synchronous IPI to complete (which is trivial
5195 * if the caller is on the CPU already). This establishes the
5196 * necessary total order on variable updates.
5197 *
5198 * Note that because a guest time update may take place
5199 * anytime after the setting of the VCPU's request bit, the
5200 * correct TSC value must be set before the request. However,
5201 * to ensure the update actually makes it to any guest which
5202 * starts running in hardware virtualization between the set
5203 * and the acquisition of the spinlock, we must also ping the
5204 * CPU after setting the request bit.
5205 *
5206 */
5207
c8076604
GH		 5208 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5209 return 0;
5210 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5211 return 0;
8cfdc000
ZA		 5212
5213 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5214
e935b837 5215 raw_spin_lock(&kvm_lock);
c8076604 5216 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5217 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5218 if (vcpu->cpu != freq->cpu)
5219 continue;
c285545f 5220 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5221 if (vcpu->cpu != smp_processor_id())
8cfdc000 5222 send_ipi = 1;
c8076604
GH		 5223 }
5224 }
e935b837 5225 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5226
5227 if (freq->old < freq->new && send_ipi) {
5228 /*
5229 * We upscale the frequency. Must make the guest
5230 * doesn't see old kvmclock values while running with
5231 * the new frequency, otherwise we risk the guest sees
5232 * time go backwards.
5233 *
5234 * In case we update the frequency for another cpu
5235 * (which might be in guest context) send an interrupt
5236 * to kick the cpu out of guest context. Next time
5237 * guest context is entered kvmclock will be updated,
5238 * so the guest will not see stale values.
5239 */
8cfdc000 5240 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5241 }
5242 return 0;
5243}
5244
5245static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5246 .notifier_call = kvmclock_cpufreq_notifier
5247};
5248
5249static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5250 unsigned long action, void *hcpu)
5251{
5252 unsigned int cpu = (unsigned long)hcpu;
5253
5254 switch (action) {
5255 case CPU_ONLINE:
5256 case CPU_DOWN_FAILED:
5257 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5258 break;
5259 case CPU_DOWN_PREPARE:
5260 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5261 break;
5262 }
5263 return NOTIFY_OK;
5264}
5265
5266static struct notifier_block kvmclock_cpu_notifier_block = {
5267 .notifier_call = kvmclock_cpu_notifier,
5268 .priority = -INT_MAX
c8076604
GH		 5269};
5270
b820cc0c
ZA		 5271static void kvm_timer_init(void)
5272{
5273 int cpu;
5274
c285545f 5275 max_tsc_khz = tsc_khz;
8cfdc000 5276 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5277 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5278#ifdef CONFIG_CPU_FREQ
5279 struct cpufreq_policy policy;
5280 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5281 cpu = get_cpu();
5282 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5283 if (policy.cpuinfo.max_freq)
5284 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5285 put_cpu();
c285545f 5286#endif
b820cc0c
ZA		 5287 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5288 CPUFREQ_TRANSITION_NOTIFIER);
5289 }
c285545f 5290 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5291 for_each_online_cpu(cpu)
5292 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5293}
5294
ff9d07a0
ZY		 5295static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5296
f5132b01 5297int kvm_is_in_guest(void)
ff9d07a0 5298{
086c9855 5299 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5300}
5301
5302static int kvm_is_user_mode(void)
5303{
5304 int user_mode = 3;
dcf46b94 5305
086c9855
AS		 5306 if (__this_cpu_read(current_vcpu))
5307 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5308
ff9d07a0
ZY		 5309 return user_mode != 0;
5310}
5311
5312static unsigned long kvm_get_guest_ip(void)
5313{
5314 unsigned long ip = 0;
dcf46b94 5315
086c9855
AS		 5316 if (__this_cpu_read(current_vcpu))
5317 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5318
ff9d07a0
ZY		 5319 return ip;
5320}
5321
5322static struct perf_guest_info_callbacks kvm_guest_cbs = {
5323 .is_in_guest = kvm_is_in_guest,
5324 .is_user_mode = kvm_is_user_mode,
5325 .get_guest_ip = kvm_get_guest_ip,
5326};
5327
5328void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5329{
086c9855 5330 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5331}
5332EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5333
5334void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5335{
086c9855 5336 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5337}
5338EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5339
ce88decf
XG		 5340static void kvm_set_mmio_spte_mask(void)
5341{
5342 u64 mask;
5343 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5344
5345 /*
5346 * Set the reserved bits and the present bit of an paging-structure
5347 * entry to generate page fault with PFER.RSV = 1.
5348 */
885032b9
XG		 5349 /* Mask the reserved physical address bits. */
5350 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5351
5352 /* Bit 62 is always reserved for 32bit host. */
5353 mask |= 0x3ull << 62;
5354
5355 /* Set the present bit. */
ce88decf
XG		 5356 mask |= 1ull;
5357
5358#ifdef CONFIG_X86_64
5359 /*
5360 * If reserved bit is not supported, clear the present bit to disable
5361 * mmio page fault.
5362 */
5363 if (maxphyaddr == 52)
5364 mask &= ~1ull;
5365#endif
5366
5367 kvm_mmu_set_mmio_spte_mask(mask);
5368}
5369
16e8d74d
MT		 5370#ifdef CONFIG_X86_64
5371static void pvclock_gtod_update_fn(struct work_struct *work)
5372{
d828199e
MT		 5373 struct kvm *kvm;
5374
5375 struct kvm_vcpu *vcpu;
5376 int i;
5377
5378 raw_spin_lock(&kvm_lock);
5379 list_for_each_entry(kvm, &vm_list, vm_list)
5380 kvm_for_each_vcpu(i, vcpu, kvm)
5381 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5382 atomic_set(&kvm_guest_has_master_clock, 0);
5383 raw_spin_unlock(&kvm_lock);
16e8d74d
MT		 5384}
5385
5386static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5387
5388/*
5389 * Notification about pvclock gtod data update.
5390 */
5391static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5392 void *priv)
5393{
5394 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5395 struct timekeeper *tk = priv;
5396
5397 update_pvclock_gtod(tk);
5398
5399 /* disable master clock if host does not trust, or does not
5400 * use, TSC clocksource
5401 */
5402 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5403 atomic_read(&kvm_guest_has_master_clock) != 0)
5404 queue_work(system_long_wq, &pvclock_gtod_work);
5405
5406 return 0;
5407}
5408
5409static struct notifier_block pvclock_gtod_notifier = {
5410 .notifier_call = pvclock_gtod_notify,
5411};
5412#endif
5413
f8c16bba 5414int kvm_arch_init(void *opaque)
043405e1 5415{
b820cc0c 5416 int r;
6b61edf7 5417 struct kvm_x86_ops *ops = opaque;
f8c16bba 5418
f8c16bba
ZX		 5419 if (kvm_x86_ops) {
5420 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5421 r = -EEXIST;
5422 goto out;
f8c16bba
ZX		 5423 }
5424
5425 if (!ops->cpu_has_kvm_support()) {
5426 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5427 r = -EOPNOTSUPP;
5428 goto out;
f8c16bba
ZX		 5429 }
5430 if (ops->disabled_by_bios()) {
5431 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5432 r = -EOPNOTSUPP;
5433 goto out;
f8c16bba
ZX		 5434 }
5435
013f6a5d
MT		 5436 r = -ENOMEM;
5437 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5438 if (!shared_msrs) {
5439 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5440 goto out;
5441 }
5442
97db56ce
AK		 5443 r = kvm_mmu_module_init();
5444 if (r)
013f6a5d 5445 goto out_free_percpu;
97db56ce 5446
ce88decf 5447 kvm_set_mmio_spte_mask();
97db56ce
AK		 5448 kvm_init_msr_list();
5449
f8c16bba 5450 kvm_x86_ops = ops;
7b52345e 5451 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5452 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5453
b820cc0c 5454 kvm_timer_init();
c8076604 5455
ff9d07a0
ZY		 5456 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5457
2acf923e
DC		 5458 if (cpu_has_xsave)
5459 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5460
c5cc421b 5461 kvm_lapic_init();
16e8d74d
MT		 5462#ifdef CONFIG_X86_64
5463 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5464#endif
5465
f8c16bba 5466 return 0;
56c6d28a 5467
013f6a5d
MT		 5468out_free_percpu:
5469 free_percpu(shared_msrs);
56c6d28a 5470out:
56c6d28a 5471 return r;
043405e1 5472}
8776e519 5473
f8c16bba
ZX		 5474void kvm_arch_exit(void)
5475{
ff9d07a0
ZY		 5476 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5477
888d256e
JK		 5478 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5479 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5480 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5481 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5482#ifdef CONFIG_X86_64
5483 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5484#endif
f8c16bba 5485 kvm_x86_ops = NULL;
56c6d28a 5486 kvm_mmu_module_exit();
013f6a5d 5487 free_percpu(shared_msrs);
56c6d28a 5488}
f8c16bba 5489
8776e519
HB		 5490int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5491{
5492 ++vcpu->stat.halt_exits;
5493 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5494 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5495 return 1;
5496 } else {
5497 vcpu->run->exit_reason = KVM_EXIT_HLT;
5498 return 0;
5499 }
5500}
5501EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5502
55cd8e5a
GN		 5503int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5504{
5505 u64 param, ingpa, outgpa, ret;
5506 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5507 bool fast, longmode;
5508 int cs_db, cs_l;
5509
5510 /*
5511 * hypercall generates UD from non zero cpl and real mode
5512 * per HYPER-V spec
5513 */
3eeb3288 5514 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5515 kvm_queue_exception(vcpu, UD_VECTOR);
5516 return 0;
5517 }
5518
5519 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5520 longmode = is_long_mode(vcpu) && cs_l == 1;
5521
5522 if (!longmode) {
ccd46936
GN		 5523 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5524 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5525 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5526 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5527 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5528 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5529 }
5530#ifdef CONFIG_X86_64
5531 else {
5532 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5533 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5534 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5535 }
5536#endif
5537
5538 code = param & 0xffff;
5539 fast = (param >> 16) & 0x1;
5540 rep_cnt = (param >> 32) & 0xfff;
5541 rep_idx = (param >> 48) & 0xfff;
5542
5543 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5544
c25bc163
GN		 5545 switch (code) {
5546 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5547 kvm_vcpu_on_spin(vcpu);
5548 break;
5549 default:
5550 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5551 break;
5552 }
55cd8e5a
GN		 5553
5554 ret = res | (((u64)rep_done & 0xfff) << 32);
5555 if (longmode) {
5556 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5557 } else {
5558 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5559 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5560 }
5561
5562 return 1;
5563}
5564
8776e519
HB		 5565int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5566{
5567 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5568 int r = 1;
8776e519 5569
55cd8e5a
GN		 5570 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5571 return kvm_hv_hypercall(vcpu);
5572
5fdbf976
MT		 5573 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5574 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5575 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5576 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5577 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5578
229456fc 5579 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5580
8776e519
HB		 5581 if (!is_long_mode(vcpu)) {
5582 nr &= 0xFFFFFFFF;
5583 a0 &= 0xFFFFFFFF;
5584 a1 &= 0xFFFFFFFF;
5585 a2 &= 0xFFFFFFFF;
5586 a3 &= 0xFFFFFFFF;
5587 }
5588
07708c4a
JK		 5589 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5590 ret = -KVM_EPERM;
5591 goto out;
5592 }
5593
8776e519 5594 switch (nr) {
b93463aa
AK		 5595 case KVM_HC_VAPIC_POLL_IRQ:
5596 ret = 0;
5597 break;
8776e519
HB		 5598 default:
5599 ret = -KVM_ENOSYS;
5600 break;
5601 }
07708c4a 5602out:
5fdbf976 5603 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5604 ++vcpu->stat.hypercalls;
2f333bcb 5605 return r;
8776e519
HB		 5606}
5607EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5608
b6785def 5609static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5610{
d6aa1000 5611 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5612 char instruction[3];
5fdbf976 5613 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5614
8776e519 5615 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5616
9d74191a 5617 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5618}
5619
b6c7a5dc
HB		 5620/*
5621 * Check if userspace requested an interrupt window, and that the
5622 * interrupt window is open.
5623 *
5624 * No need to exit to userspace if we already have an interrupt queued.
5625 */
851ba692 5626static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5627{
8061823a 5628 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5629 vcpu->run->request_interrupt_window &&
5df56646 5630 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5631}
5632
851ba692 5633static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5634{
851ba692
AK		 5635 struct kvm_run *kvm_run = vcpu->run;
5636
91586a3b 5637 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5638 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5639 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5640 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5641 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5642 else
b6c7a5dc 5643 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5644 kvm_arch_interrupt_allowed(vcpu) &&
5645 !kvm_cpu_has_interrupt(vcpu) &&
5646 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5647}
5648
4484141a 5649static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5650{
5651 struct kvm_lapic *apic = vcpu->arch.apic;
5652 struct page *page;
5653
5654 if (!apic || !apic->vapic_addr)
4484141a 5655 return 0;
b93463aa
AK		 5656
5657 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5658 if (is_error_page(page))
5659 return -EFAULT;
72dc67a6
IE		 5660
5661 vcpu->arch.apic->vapic_page = page;
4484141a 5662 return 0;
b93463aa
AK		 5663}
5664
5665static void vapic_exit(struct kvm_vcpu *vcpu)
5666{
5667 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5668 int idx;
b93463aa
AK		 5669
5670 if (!apic || !apic->vapic_addr)
5671 return;
5672
f656ce01 5673 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5674 kvm_release_page_dirty(apic->vapic_page);
5675 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5676 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5677}
5678
95ba8273
GN		 5679static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5680{
5681 int max_irr, tpr;
5682
5683 if (!kvm_x86_ops->update_cr8_intercept)
5684 return;
5685
88c808fd
AK		 5686 if (!vcpu->arch.apic)
5687 return;
5688
8db3baa2
GN		 5689 if (!vcpu->arch.apic->vapic_addr)
5690 max_irr = kvm_lapic_find_highest_irr(vcpu);
5691 else
5692 max_irr = -1;
95ba8273
GN		 5693
5694 if (max_irr != -1)
5695 max_irr >>= 4;
5696
5697 tpr = kvm_lapic_get_cr8(vcpu);
5698
5699 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5700}
5701
851ba692 5702static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5703{
5704 /* try to reinject previous events if any */
b59bb7bd 5705 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5706 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5707 vcpu->arch.exception.has_error_code,
5708 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5709 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5710 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5711 vcpu->arch.exception.error_code,
5712 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5713 return;
5714 }
5715
95ba8273
GN		 5716 if (vcpu->arch.nmi_injected) {
5717 kvm_x86_ops->set_nmi(vcpu);
5718 return;
5719 }
5720
5721 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5722 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5723 return;
5724 }
5725
5726 /* try to inject new event if pending */
5727 if (vcpu->arch.nmi_pending) {
5728 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5729 --vcpu->arch.nmi_pending;
95ba8273
GN		 5730 vcpu->arch.nmi_injected = true;
5731 kvm_x86_ops->set_nmi(vcpu);
5732 }
c7c9c56c 5733 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5734 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5735 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5736 false);
5737 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5738 }
5739 }
5740}
5741
7460fb4a
AK		 5742static void process_nmi(struct kvm_vcpu *vcpu)
5743{
5744 unsigned limit = 2;
5745
5746 /*
5747 * x86 is limited to one NMI running, and one NMI pending after it.
5748 * If an NMI is already in progress, limit further NMIs to just one.
5749 * Otherwise, allow two (and we'll inject the first one immediately).
5750 */
5751 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5752 limit = 1;
5753
5754 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5755 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5756 kvm_make_request(KVM_REQ_EVENT, vcpu);
5757}
5758
d828199e
MT		 5759static void kvm_gen_update_masterclock(struct kvm *kvm)
5760{
5761#ifdef CONFIG_X86_64
5762 int i;
5763 struct kvm_vcpu *vcpu;
5764 struct kvm_arch *ka = &kvm->arch;
5765
5766 spin_lock(&ka->pvclock_gtod_sync_lock);
5767 kvm_make_mclock_inprogress_request(kvm);
5768 /* no guest entries from this point */
5769 pvclock_update_vm_gtod_copy(kvm);
5770
5771 kvm_for_each_vcpu(i, vcpu, kvm)
5772 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5773
5774 /* guest entries allowed */
5775 kvm_for_each_vcpu(i, vcpu, kvm)
5776 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5777
5778 spin_unlock(&ka->pvclock_gtod_sync_lock);
5779#endif
5780}
5781
3d81bc7e 5782static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5783{
5784 u64 eoi_exit_bitmap[4];
cf9e65b7 5785 u32 tmr[8];
c7c9c56c 5786
3d81bc7e
YZ		 5787 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5788 return;
c7c9c56c
YZ		 5789
5790 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5791 memset(tmr, 0, 32);
c7c9c56c 5792
cf9e65b7 5793 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5794 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5795 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5796}
5797
851ba692 5798static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5799{
5800 int r;
6a8b1d13 5801 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5802 vcpu->run->request_interrupt_window;
730dca42 5803 bool req_immediate_exit = false;
b6c7a5dc 5804
3e007509 5805 if (vcpu->requests) {
a8eeb04a 5806 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5807 kvm_mmu_unload(vcpu);
a8eeb04a 5808 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5809 __kvm_migrate_timers(vcpu);
d828199e
MT		 5810 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5811 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5812 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5813 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5814 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5815 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5816 if (unlikely(r))
5817 goto out;
5818 }
a8eeb04a 5819 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5820 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5821 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5822 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5823 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5824 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5825 r = 0;
5826 goto out;
5827 }
a8eeb04a 5828 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5829 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5830 r = 0;
5831 goto out;
5832 }
a8eeb04a 5833 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5834 vcpu->fpu_active = 0;
5835 kvm_x86_ops->fpu_deactivate(vcpu);
5836 }
af585b92
GN		 5837 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5838 /* Page is swapped out. Do synthetic halt */
5839 vcpu->arch.apf.halted = true;
5840 r = 1;
5841 goto out;
5842 }
c9aaa895
GC		 5843 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5844 record_steal_time(vcpu);
7460fb4a
AK		 5845 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5846 process_nmi(vcpu);
f5132b01
GN		 5847 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5848 kvm_handle_pmu_event(vcpu);
5849 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5850 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5851 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5852 vcpu_scan_ioapic(vcpu);
2f52d58c 5853 }
b93463aa 5854
b463a6f7 5855 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5856 kvm_apic_accept_events(vcpu);
5857 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5858 r = 1;
5859 goto out;
5860 }
5861
b463a6f7
AK		 5862 inject_pending_event(vcpu);
5863
5864 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5865 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5866 req_immediate_exit =
5867 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5868 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5869 req_immediate_exit =
5870 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5871
5872 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5873 /*
5874 * Update architecture specific hints for APIC
5875 * virtual interrupt delivery.
5876 */
5877 if (kvm_x86_ops->hwapic_irr_update)
5878 kvm_x86_ops->hwapic_irr_update(vcpu,
5879 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5880 update_cr8_intercept(vcpu);
5881 kvm_lapic_sync_to_vapic(vcpu);
5882 }
5883 }
5884
d8368af8
AK		 5885 r = kvm_mmu_reload(vcpu);
5886 if (unlikely(r)) {
d905c069 5887 goto cancel_injection;
d8368af8
AK		 5888 }
5889
b6c7a5dc
HB		 5890 preempt_disable();
5891
5892 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5893 if (vcpu->fpu_active)
5894 kvm_load_guest_fpu(vcpu);
2acf923e 5895 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5896
6b7e2d09
XG		 5897 vcpu->mode = IN_GUEST_MODE;
5898
5899 /* We should set ->mode before check ->requests,
5900 * see the comment in make_all_cpus_request.
5901 */
5902 smp_mb();
b6c7a5dc 5903
d94e1dc9 5904 local_irq_disable();
32f88400 5905
6b7e2d09 5906 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5907 || need_resched() || signal_pending(current)) {
6b7e2d09 5908 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5909 smp_wmb();
6c142801
AK		 5910 local_irq_enable();
5911 preempt_enable();
5912 r = 1;
d905c069 5913 goto cancel_injection;
6c142801
AK		 5914 }
5915
f656ce01 5916 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5917
d6185f20
NHE		 5918 if (req_immediate_exit)
5919 smp_send_reschedule(vcpu->cpu);
5920
b6c7a5dc
HB		 5921 kvm_guest_enter();
5922
42dbaa5a 5923 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5924 set_debugreg(0, 7);
5925 set_debugreg(vcpu->arch.eff_db[0], 0);
5926 set_debugreg(vcpu->arch.eff_db[1], 1);
5927 set_debugreg(vcpu->arch.eff_db[2], 2);
5928 set_debugreg(vcpu->arch.eff_db[3], 3);
5929 }
b6c7a5dc 5930
229456fc 5931 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5932 kvm_x86_ops->run(vcpu);
b6c7a5dc 5933
24f1e32c
FW		 5934 /*
5935 * If the guest has used debug registers, at least dr7
5936 * will be disabled while returning to the host.
5937 * If we don't have active breakpoints in the host, we don't
5938 * care about the messed up debug address registers. But if
5939 * we have some of them active, restore the old state.
5940 */
59d8eb53 5941 if (hw_breakpoint_active())
24f1e32c 5942 hw_breakpoint_restore();
42dbaa5a 5943
886b470c
MT		 5944 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5945 native_read_tsc());
1d5f066e 5946
6b7e2d09 5947 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5948 smp_wmb();
a547c6db
YZ		 5949
5950 /* Interrupt is enabled by handle_external_intr() */
5951 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 5952
5953 ++vcpu->stat.exits;
5954
5955 /*
5956 * We must have an instruction between local_irq_enable() and
5957 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5958 * the interrupt shadow. The stat.exits increment will do nicely.
5959 * But we need to prevent reordering, hence this barrier():
5960 */
5961 barrier();
5962
5963 kvm_guest_exit();
5964
5965 preempt_enable();
5966
f656ce01 5967 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5968
b6c7a5dc
HB		 5969 /*
5970 * Profile KVM exit RIPs:
5971 */
5972 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5973 unsigned long rip = kvm_rip_read(vcpu);
5974 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5975 }
5976
cc578287
ZA		 5977 if (unlikely(vcpu->arch.tsc_always_catchup))
5978 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5979
5cfb1d5a
MT		 5980 if (vcpu->arch.apic_attention)
5981 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5982
851ba692 5983 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5984 return r;
5985
5986cancel_injection:
5987 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5988 if (unlikely(vcpu->arch.apic_attention))
5989 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5990out:
5991 return r;
5992}
b6c7a5dc 5993
09cec754 5994
851ba692 5995static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5996{
5997 int r;
f656ce01 5998 struct kvm *kvm = vcpu->kvm;
d7690175 5999
f656ce01 6000 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 6001 r = vapic_enter(vcpu);
6002 if (r) {
6003 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6004 return r;
6005 }
d7690175
MT		 6006
6007 r = 1;
6008 while (r > 0) {
af585b92
GN		 6009 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6010 !vcpu->arch.apf.halted)
851ba692 6011 r = vcpu_enter_guest(vcpu);
d7690175 6012 else {
f656ce01 6013 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6014 kvm_vcpu_block(vcpu);
f656ce01 6015 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6016 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6017 kvm_apic_accept_events(vcpu);
09cec754
GN		 6018 switch(vcpu->arch.mp_state) {
6019 case KVM_MP_STATE_HALTED:
d7690175 6020 vcpu->arch.mp_state =
09cec754
GN		 6021 KVM_MP_STATE_RUNNABLE;
6022 case KVM_MP_STATE_RUNNABLE:
af585b92 6023 vcpu->arch.apf.halted = false;
09cec754 6024 break;
66450a21
JK		 6025 case KVM_MP_STATE_INIT_RECEIVED:
6026 break;
09cec754
GN		 6027 default:
6028 r = -EINTR;
6029 break;
6030 }
6031 }
d7690175
MT		 6032 }
6033
09cec754
GN		 6034 if (r <= 0)
6035 break;
6036
6037 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6038 if (kvm_cpu_has_pending_timer(vcpu))
6039 kvm_inject_pending_timer_irqs(vcpu);
6040
851ba692 6041 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6042 r = -EINTR;
851ba692 6043 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6044 ++vcpu->stat.request_irq_exits;
6045 }
af585b92
GN		 6046
6047 kvm_check_async_pf_completion(vcpu);
6048
09cec754
GN		 6049 if (signal_pending(current)) {
6050 r = -EINTR;
851ba692 6051 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6052 ++vcpu->stat.signal_exits;
6053 }
6054 if (need_resched()) {
f656ce01 6055 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 6056 kvm_resched(vcpu);
f656ce01 6057 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6058 }
b6c7a5dc
HB		 6059 }
6060
f656ce01 6061 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 6062
b93463aa
AK		 6063 vapic_exit(vcpu);
6064
b6c7a5dc
HB		 6065 return r;
6066}
6067
716d51ab
GN		 6068static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6069{
6070 int r;
6071 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6072 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6073 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6074 if (r != EMULATE_DONE)
6075 return 0;
6076 return 1;
6077}
6078
6079static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6080{
6081 BUG_ON(!vcpu->arch.pio.count);
6082
6083 return complete_emulated_io(vcpu);
6084}
6085
f78146b0
AK		 6086/*
6087 * Implements the following, as a state machine:
6088 *
6089 * read:
6090 * for each fragment
87da7e66
XG		 6091 * for each mmio piece in the fragment
6092 * write gpa, len
6093 * exit
6094 * copy data
f78146b0
AK		 6095 * execute insn
6096 *
6097 * write:
6098 * for each fragment
87da7e66
XG		 6099 * for each mmio piece in the fragment
6100 * write gpa, len
6101 * copy data
6102 * exit
f78146b0 6103 */
716d51ab 6104static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6105{
6106 struct kvm_run *run = vcpu->run;
f78146b0 6107 struct kvm_mmio_fragment *frag;
87da7e66 6108 unsigned len;
5287f194 6109
716d51ab 6110 BUG_ON(!vcpu->mmio_needed);
5287f194 6111
716d51ab 6112 /* Complete previous fragment */
87da7e66
XG		 6113 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6114 len = min(8u, frag->len);
716d51ab 6115 if (!vcpu->mmio_is_write)
87da7e66
XG		 6116 memcpy(frag->data, run->mmio.data, len);
6117
6118 if (frag->len <= 8) {
6119 /* Switch to the next fragment. */
6120 frag++;
6121 vcpu->mmio_cur_fragment++;
6122 } else {
6123 /* Go forward to the next mmio piece. */
6124 frag->data += len;
6125 frag->gpa += len;
6126 frag->len -= len;
6127 }
6128
716d51ab
GN		 6129 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6130 vcpu->mmio_needed = 0;
cef4dea0 6131 if (vcpu->mmio_is_write)
716d51ab
GN		 6132 return 1;
6133 vcpu->mmio_read_completed = 1;
6134 return complete_emulated_io(vcpu);
6135 }
87da7e66 6136
716d51ab
GN		 6137 run->exit_reason = KVM_EXIT_MMIO;
6138 run->mmio.phys_addr = frag->gpa;
6139 if (vcpu->mmio_is_write)
87da7e66
XG		 6140 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6141 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6142 run->mmio.is_write = vcpu->mmio_is_write;
6143 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6144 return 0;
5287f194
AK		 6145}
6146
716d51ab 6147
b6c7a5dc
HB		 6148int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6149{
6150 int r;
6151 sigset_t sigsaved;
6152
e5c30142
AK		 6153 if (!tsk_used_math(current) && init_fpu(current))
6154 return -ENOMEM;
6155
ac9f6dc0
AK		 6156 if (vcpu->sigset_active)
6157 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6158
a4535290 6159 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6160 kvm_vcpu_block(vcpu);
66450a21 6161 kvm_apic_accept_events(vcpu);
d7690175 6162 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6163 r = -EAGAIN;
6164 goto out;
b6c7a5dc
HB		 6165 }
6166
b6c7a5dc 6167 /* re-sync apic's tpr */
eea1cff9
AP		 6168 if (!irqchip_in_kernel(vcpu->kvm)) {
6169 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6170 r = -EINVAL;
6171 goto out;
6172 }
6173 }
b6c7a5dc 6174
716d51ab
GN		 6175 if (unlikely(vcpu->arch.complete_userspace_io)) {
6176 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6177 vcpu->arch.complete_userspace_io = NULL;
6178 r = cui(vcpu);
6179 if (r <= 0)
6180 goto out;
6181 } else
6182 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6183
851ba692 6184 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6185
6186out:
f1d86e46 6187 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6188 if (vcpu->sigset_active)
6189 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6190
b6c7a5dc
HB		 6191 return r;
6192}
6193
6194int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6195{
7ae441ea
GN		 6196 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6197 /*
6198 * We are here if userspace calls get_regs() in the middle of
6199 * instruction emulation. Registers state needs to be copied
4a969980 6200 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6201 * that usually, but some bad designed PV devices (vmware
6202 * backdoor interface) need this to work
6203 */
dd856efa 6204 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6205 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6206 }
5fdbf976
MT		 6207 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6208 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6209 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6210 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6211 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6212 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6213 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6214 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6215#ifdef CONFIG_X86_64
5fdbf976
MT		 6216 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6217 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6218 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6219 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6220 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6221 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6222 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6223 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6224#endif
6225
5fdbf976 6226 regs->rip = kvm_rip_read(vcpu);
91586a3b 6227 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6228
b6c7a5dc
HB		 6229 return 0;
6230}
6231
6232int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6233{
7ae441ea
GN		 6234 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6235 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6236
5fdbf976
MT		 6237 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6238 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6239 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6240 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6241 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6242 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6243 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6244 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6245#ifdef CONFIG_X86_64
5fdbf976
MT		 6246 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6247 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6248 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6249 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6250 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6251 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6252 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6253 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6254#endif
6255
5fdbf976 6256 kvm_rip_write(vcpu, regs->rip);
91586a3b 6257 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6258
b4f14abd
JK		 6259 vcpu->arch.exception.pending = false;
6260
3842d135
AK		 6261 kvm_make_request(KVM_REQ_EVENT, vcpu);
6262
b6c7a5dc
HB		 6263 return 0;
6264}
6265
b6c7a5dc
HB		 6266void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6267{
6268 struct kvm_segment cs;
6269
3e6e0aab 6270 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6271 *db = cs.db;
6272 *l = cs.l;
6273}
6274EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6275
6276int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6277 struct kvm_sregs *sregs)
6278{
89a27f4d 6279 struct desc_ptr dt;
b6c7a5dc 6280
3e6e0aab
GT		 6281 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6282 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6283 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6284 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6285 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6286 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6287
3e6e0aab
GT		 6288 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6289 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6290
6291 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6292 sregs->idt.limit = dt.size;
6293 sregs->idt.base = dt.address;
b6c7a5dc 6294 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6295 sregs->gdt.limit = dt.size;
6296 sregs->gdt.base = dt.address;
b6c7a5dc 6297
4d4ec087 6298 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6299 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6300 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6301 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6302 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6303 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6304 sregs->apic_base = kvm_get_apic_base(vcpu);
6305
923c61bb 6306 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6307
36752c9b 6308 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6309 set_bit(vcpu->arch.interrupt.nr,
6310 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6311
b6c7a5dc
HB		 6312 return 0;
6313}
6314
62d9f0db
MT		 6315int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6316 struct kvm_mp_state *mp_state)
6317{
66450a21 6318 kvm_apic_accept_events(vcpu);
62d9f0db 6319 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6320 return 0;
6321}
6322
6323int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6324 struct kvm_mp_state *mp_state)
6325{
66450a21
JK		 6326 if (!kvm_vcpu_has_lapic(vcpu) &&
6327 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6328 return -EINVAL;
6329
6330 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6331 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6332 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6333 } else
6334 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6335 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6336 return 0;
6337}
6338
7f3d35fd
KW		 6339int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6340 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6341{
9d74191a 6342 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6343 int ret;
e01c2426 6344
8ec4722d 6345 init_emulate_ctxt(vcpu);
c697518a 6346
7f3d35fd 6347 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6348 has_error_code, error_code);
c697518a 6349
c697518a 6350 if (ret)
19d04437 6351 return EMULATE_FAIL;
37817f29 6352
9d74191a
TY		 6353 kvm_rip_write(vcpu, ctxt->eip);
6354 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6355 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6356 return EMULATE_DONE;
37817f29
IE		 6357}
6358EXPORT_SYMBOL_GPL(kvm_task_switch);
6359
b6c7a5dc
HB		 6360int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6361 struct kvm_sregs *sregs)
6362{
6363 int mmu_reset_needed = 0;
63f42e02 6364 int pending_vec, max_bits, idx;
89a27f4d 6365 struct desc_ptr dt;
b6c7a5dc 6366
6d1068b3
PM		 6367 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6368 return -EINVAL;
6369
89a27f4d
GN		 6370 dt.size = sregs->idt.limit;
6371 dt.address = sregs->idt.base;
b6c7a5dc 6372 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6373 dt.size = sregs->gdt.limit;
6374 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6375 kvm_x86_ops->set_gdt(vcpu, &dt);
6376
ad312c7c 6377 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6378 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6379 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6380 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6381
2d3ad1f4 6382 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6383
f6801dff 6384 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6385 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6386 kvm_set_apic_base(vcpu, sregs->apic_base);
6387
4d4ec087 6388 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6389 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6390 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6391
fc78f519 6392 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6393 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6394 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6395 kvm_update_cpuid(vcpu);
63f42e02
XG		 6396
6397 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6398 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6399 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6400 mmu_reset_needed = 1;
6401 }
63f42e02 6402 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6403
6404 if (mmu_reset_needed)
6405 kvm_mmu_reset_context(vcpu);
6406
a50abc3b 6407 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6408 pending_vec = find_first_bit(
6409 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6410 if (pending_vec < max_bits) {
66fd3f7f 6411 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6412 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6413 }
6414
3e6e0aab
GT		 6415 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6416 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6417 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6418 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6419 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6420 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6421
3e6e0aab
GT		 6422 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6423 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6424
5f0269f5
ME		 6425 update_cr8_intercept(vcpu);
6426
9c3e4aab 6427 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6428 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6429 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6430 !is_protmode(vcpu))
9c3e4aab
MT		 6431 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6432
3842d135
AK		 6433 kvm_make_request(KVM_REQ_EVENT, vcpu);
6434
b6c7a5dc
HB		 6435 return 0;
6436}
6437
d0bfb940
JK		 6438int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6439 struct kvm_guest_debug *dbg)
b6c7a5dc 6440{
355be0b9 6441 unsigned long rflags;
ae675ef0 6442 int i, r;
b6c7a5dc 6443
4f926bf2
JK		 6444 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6445 r = -EBUSY;
6446 if (vcpu->arch.exception.pending)
2122ff5e 6447 goto out;
4f926bf2
JK		 6448 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6449 kvm_queue_exception(vcpu, DB_VECTOR);
6450 else
6451 kvm_queue_exception(vcpu, BP_VECTOR);
6452 }
6453
91586a3b
JK		 6454 /*
6455 * Read rflags as long as potentially injected trace flags are still
6456 * filtered out.
6457 */
6458 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6459
6460 vcpu->guest_debug = dbg->control;
6461 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6462 vcpu->guest_debug = 0;
6463
6464 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6465 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6466 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6467 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6468 } else {
6469 for (i = 0; i < KVM_NR_DB_REGS; i++)
6470 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6471 }
c8639010 6472 kvm_update_dr7(vcpu);
ae675ef0 6473
f92653ee
JK		 6474 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6475 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6476 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6477
91586a3b
JK		 6478 /*
6479 * Trigger an rflags update that will inject or remove the trace
6480 * flags.
6481 */
6482 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6483
c8639010 6484 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6485
4f926bf2 6486 r = 0;
d0bfb940 6487
2122ff5e 6488out:
b6c7a5dc
HB		 6489
6490 return r;
6491}
6492
8b006791
ZX		 6493/*
6494 * Translate a guest virtual address to a guest physical address.
6495 */
6496int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6497 struct kvm_translation *tr)
6498{
6499 unsigned long vaddr = tr->linear_address;
6500 gpa_t gpa;
f656ce01 6501 int idx;
8b006791 6502
f656ce01 6503 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6504 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6505 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6506 tr->physical_address = gpa;
6507 tr->valid = gpa != UNMAPPED_GVA;
6508 tr->writeable = 1;
6509 tr->usermode = 0;
8b006791
ZX		 6510
6511 return 0;
6512}
6513
d0752060
HB		 6514int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6515{
98918833
SY		 6516 struct i387_fxsave_struct *fxsave =
6517 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6518
d0752060
HB		 6519 memcpy(fpu->fpr, fxsave->st_space, 128);
6520 fpu->fcw = fxsave->cwd;
6521 fpu->fsw = fxsave->swd;
6522 fpu->ftwx = fxsave->twd;
6523 fpu->last_opcode = fxsave->fop;
6524 fpu->last_ip = fxsave->rip;
6525 fpu->last_dp = fxsave->rdp;
6526 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6527
d0752060
HB		 6528 return 0;
6529}
6530
6531int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6532{
98918833
SY		 6533 struct i387_fxsave_struct *fxsave =
6534 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6535
d0752060
HB		 6536 memcpy(fxsave->st_space, fpu->fpr, 128);
6537 fxsave->cwd = fpu->fcw;
6538 fxsave->swd = fpu->fsw;
6539 fxsave->twd = fpu->ftwx;
6540 fxsave->fop = fpu->last_opcode;
6541 fxsave->rip = fpu->last_ip;
6542 fxsave->rdp = fpu->last_dp;
6543 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6544
d0752060
HB		 6545 return 0;
6546}
6547
10ab25cd 6548int fx_init(struct kvm_vcpu *vcpu)
d0752060 6549{
10ab25cd
JK		 6550 int err;
6551
6552 err = fpu_alloc(&vcpu->arch.guest_fpu);
6553 if (err)
6554 return err;
6555
98918833 6556 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6557
2acf923e
DC		 6558 /*
6559 * Ensure guest xcr0 is valid for loading
6560 */
6561 vcpu->arch.xcr0 = XSTATE_FP;
6562
ad312c7c 6563 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6564
6565 return 0;
d0752060
HB		 6566}
6567EXPORT_SYMBOL_GPL(fx_init);
6568
98918833
SY		 6569static void fx_free(struct kvm_vcpu *vcpu)
6570{
6571 fpu_free(&vcpu->arch.guest_fpu);
6572}
6573
d0752060
HB		 6574void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6575{
2608d7a1 6576 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6577 return;
6578
2acf923e
DC		 6579 /*
6580 * Restore all possible states in the guest,
6581 * and assume host would use all available bits.
6582 * Guest xcr0 would be loaded later.
6583 */
6584 kvm_put_guest_xcr0(vcpu);
d0752060 6585 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6586 __kernel_fpu_begin();
98918833 6587 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6588 trace_kvm_fpu(1);
d0752060 6589}
d0752060
HB		 6590
6591void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6592{
2acf923e
DC		 6593 kvm_put_guest_xcr0(vcpu);
6594
d0752060
HB		 6595 if (!vcpu->guest_fpu_loaded)
6596 return;
6597
6598 vcpu->guest_fpu_loaded = 0;
98918833 6599 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6600 __kernel_fpu_end();
f096ed85 6601 ++vcpu->stat.fpu_reload;
a8eeb04a 6602 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6603 trace_kvm_fpu(0);
d0752060 6604}
e9b11c17
ZX		 6605
6606void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6607{
12f9a48f 6608 kvmclock_reset(vcpu);
7f1ea208 6609
f5f48ee1 6610 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6611 fx_free(vcpu);
e9b11c17
ZX		 6612 kvm_x86_ops->vcpu_free(vcpu);
6613}
6614
6615struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6616 unsigned int id)
6617{
6755bae8
ZA		 6618 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6619 printk_once(KERN_WARNING
6620 "kvm: SMP vm created on host with unstable TSC; "
6621 "guest TSC will not be reliable\n");
26e5215f
AK		 6622 return kvm_x86_ops->vcpu_create(kvm, id);
6623}
e9b11c17 6624
26e5215f
AK		 6625int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6626{
6627 int r;
e9b11c17 6628
0bed3b56 6629 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6630 r = vcpu_load(vcpu);
6631 if (r)
6632 return r;
57f252f2
JK		 6633 kvm_vcpu_reset(vcpu);
6634 r = kvm_mmu_setup(vcpu);
e9b11c17 6635 vcpu_put(vcpu);
e9b11c17 6636
26e5215f 6637 return r;
e9b11c17
ZX		 6638}
6639
42897d86
MT		 6640int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6641{
6642 int r;
8fe8ab46 6643 struct msr_data msr;
42897d86
MT		 6644
6645 r = vcpu_load(vcpu);
6646 if (r)
6647 return r;
8fe8ab46
WA		 6648 msr.data = 0x0;
6649 msr.index = MSR_IA32_TSC;
6650 msr.host_initiated = true;
6651 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6652 vcpu_put(vcpu);
6653
6654 return r;
6655}
6656
d40ccc62 6657void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6658{
9fc77441 6659 int r;
344d9588
GN		 6660 vcpu->arch.apf.msr_val = 0;
6661
9fc77441
MT		 6662 r = vcpu_load(vcpu);
6663 BUG_ON(r);
e9b11c17
ZX		 6664 kvm_mmu_unload(vcpu);
6665 vcpu_put(vcpu);
6666
98918833 6667 fx_free(vcpu);
e9b11c17
ZX		 6668 kvm_x86_ops->vcpu_free(vcpu);
6669}
6670
66450a21 6671void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6672{
7460fb4a
AK		 6673 atomic_set(&vcpu->arch.nmi_queued, 0);
6674 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6675 vcpu->arch.nmi_injected = false;
6676
42dbaa5a
JK		 6677 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6678 vcpu->arch.dr6 = DR6_FIXED_1;
6679 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6680 kvm_update_dr7(vcpu);
42dbaa5a 6681
3842d135 6682 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6683 vcpu->arch.apf.msr_val = 0;
c9aaa895 6684 vcpu->arch.st.msr_val = 0;
3842d135 6685
12f9a48f
GC		 6686 kvmclock_reset(vcpu);
6687
af585b92
GN		 6688 kvm_clear_async_pf_completion_queue(vcpu);
6689 kvm_async_pf_hash_reset(vcpu);
6690 vcpu->arch.apf.halted = false;
3842d135 6691
f5132b01
GN		 6692 kvm_pmu_reset(vcpu);
6693
66f7b72e
JS		 6694 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6695 vcpu->arch.regs_avail = ~0;
6696 vcpu->arch.regs_dirty = ~0;
6697
57f252f2 6698 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6699}
6700
66450a21
JK		 6701void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6702{
6703 struct kvm_segment cs;
6704
6705 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6706 cs.selector = vector << 8;
6707 cs.base = vector << 12;
6708 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6709 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6710}
6711
10474ae8 6712int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6713{
ca84d1a2
ZA		 6714 struct kvm *kvm;
6715 struct kvm_vcpu *vcpu;
6716 int i;
0dd6a6ed
ZA		 6717 int ret;
6718 u64 local_tsc;
6719 u64 max_tsc = 0;
6720 bool stable, backwards_tsc = false;
18863bdd
AK		 6721
6722 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6723 ret = kvm_x86_ops->hardware_enable(garbage);
6724 if (ret != 0)
6725 return ret;
6726
6727 local_tsc = native_read_tsc();
6728 stable = !check_tsc_unstable();
6729 list_for_each_entry(kvm, &vm_list, vm_list) {
6730 kvm_for_each_vcpu(i, vcpu, kvm) {
6731 if (!stable && vcpu->cpu == smp_processor_id())
6732 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6733 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6734 backwards_tsc = true;
6735 if (vcpu->arch.last_host_tsc > max_tsc)
6736 max_tsc = vcpu->arch.last_host_tsc;
6737 }
6738 }
6739 }
6740
6741 /*
6742 * Sometimes, even reliable TSCs go backwards. This happens on
6743 * platforms that reset TSC during suspend or hibernate actions, but
6744 * maintain synchronization. We must compensate. Fortunately, we can
6745 * detect that condition here, which happens early in CPU bringup,
6746 * before any KVM threads can be running. Unfortunately, we can't
6747 * bring the TSCs fully up to date with real time, as we aren't yet far
6748 * enough into CPU bringup that we know how much real time has actually
6749 * elapsed; our helper function, get_kernel_ns() will be using boot
6750 * variables that haven't been updated yet.
6751 *
6752 * So we simply find the maximum observed TSC above, then record the
6753 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6754 * the adjustment will be applied. Note that we accumulate
6755 * adjustments, in case multiple suspend cycles happen before some VCPU
6756 * gets a chance to run again. In the event that no KVM threads get a
6757 * chance to run, we will miss the entire elapsed period, as we'll have
6758 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6759 * loose cycle time. This isn't too big a deal, since the loss will be
6760 * uniform across all VCPUs (not to mention the scenario is extremely
6761 * unlikely). It is possible that a second hibernate recovery happens
6762 * much faster than a first, causing the observed TSC here to be
6763 * smaller; this would require additional padding adjustment, which is
6764 * why we set last_host_tsc to the local tsc observed here.
6765 *
6766 * N.B. - this code below runs only on platforms with reliable TSC,
6767 * as that is the only way backwards_tsc is set above. Also note
6768 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6769 * have the same delta_cyc adjustment applied if backwards_tsc
6770 * is detected. Note further, this adjustment is only done once,
6771 * as we reset last_host_tsc on all VCPUs to stop this from being
6772 * called multiple times (one for each physical CPU bringup).
6773 *
4a969980 6774 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6775 * will be compensated by the logic in vcpu_load, which sets the TSC to
6776 * catchup mode. This will catchup all VCPUs to real time, but cannot
6777 * guarantee that they stay in perfect synchronization.
6778 */
6779 if (backwards_tsc) {
6780 u64 delta_cyc = max_tsc - local_tsc;
6781 list_for_each_entry(kvm, &vm_list, vm_list) {
6782 kvm_for_each_vcpu(i, vcpu, kvm) {
6783 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6784 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6785 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6786 &vcpu->requests);
0dd6a6ed
ZA		 6787 }
6788
6789 /*
6790 * We have to disable TSC offset matching.. if you were
6791 * booting a VM while issuing an S4 host suspend....
6792 * you may have some problem. Solving this issue is
6793 * left as an exercise to the reader.
6794 */
6795 kvm->arch.last_tsc_nsec = 0;
6796 kvm->arch.last_tsc_write = 0;
6797 }
6798
6799 }
6800 return 0;
e9b11c17
ZX		 6801}
6802
6803void kvm_arch_hardware_disable(void *garbage)
6804{
6805 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6806 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6807}
6808
6809int kvm_arch_hardware_setup(void)
6810{
6811 return kvm_x86_ops->hardware_setup();
6812}
6813
6814void kvm_arch_hardware_unsetup(void)
6815{
6816 kvm_x86_ops->hardware_unsetup();
6817}
6818
6819void kvm_arch_check_processor_compat(void *rtn)
6820{
6821 kvm_x86_ops->check_processor_compatibility(rtn);
6822}
6823
3e515705
AK		 6824bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6825{
6826 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6827}
6828
54e9818f
GN		 6829struct static_key kvm_no_apic_vcpu __read_mostly;
6830
e9b11c17
ZX		 6831int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6832{
6833 struct page *page;
6834 struct kvm *kvm;
6835 int r;
6836
6837 BUG_ON(vcpu->kvm == NULL);
6838 kvm = vcpu->kvm;
6839
9aabc88f 6840 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6841 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6842 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6843 else
a4535290 6844 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6845
6846 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6847 if (!page) {
6848 r = -ENOMEM;
6849 goto fail;
6850 }
ad312c7c 6851 vcpu->arch.pio_data = page_address(page);
e9b11c17 6852
cc578287 6853 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6854
e9b11c17
ZX		 6855 r = kvm_mmu_create(vcpu);
6856 if (r < 0)
6857 goto fail_free_pio_data;
6858
6859 if (irqchip_in_kernel(kvm)) {
6860 r = kvm_create_lapic(vcpu);
6861 if (r < 0)
6862 goto fail_mmu_destroy;
54e9818f
GN		 6863 } else
6864 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6865
890ca9ae
HY		 6866 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6867 GFP_KERNEL);
6868 if (!vcpu->arch.mce_banks) {
6869 r = -ENOMEM;
443c39bc 6870 goto fail_free_lapic;
890ca9ae
HY		 6871 }
6872 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6873
f1797359
WY		 6874 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6875 r = -ENOMEM;
f5f48ee1 6876 goto fail_free_mce_banks;
f1797359 6877 }
f5f48ee1 6878
66f7b72e
JS		 6879 r = fx_init(vcpu);
6880 if (r)
6881 goto fail_free_wbinvd_dirty_mask;
6882
ba904635 6883 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6884 vcpu->arch.pv_time_enabled = false;
af585b92 6885 kvm_async_pf_hash_reset(vcpu);
f5132b01 6886 kvm_pmu_init(vcpu);
af585b92 6887
e9b11c17 6888 return 0;
66f7b72e
JS		 6889fail_free_wbinvd_dirty_mask:
6890 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6891fail_free_mce_banks:
6892 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6893fail_free_lapic:
6894 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6895fail_mmu_destroy:
6896 kvm_mmu_destroy(vcpu);
6897fail_free_pio_data:
ad312c7c 6898 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6899fail:
6900 return r;
6901}
6902
6903void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6904{
f656ce01
MT		 6905 int idx;
6906
f5132b01 6907 kvm_pmu_destroy(vcpu);
36cb93fd 6908 kfree(vcpu->arch.mce_banks);
e9b11c17 6909 kvm_free_lapic(vcpu);
f656ce01 6910 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6911 kvm_mmu_destroy(vcpu);
f656ce01 6912 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6913 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6914 if (!irqchip_in_kernel(vcpu->kvm))
6915 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6916}
d19a9cd2 6917
e08b9637 6918int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6919{
e08b9637
CO		 6920 if (type)
6921 return -EINVAL;
6922
f05e70ac 6923 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 6924 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 6925 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6926
5550af4d
SY		 6927 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6928 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6929 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6930 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6931 &kvm->arch.irq_sources_bitmap);
5550af4d 6932
038f8c11 6933 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6934 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6935 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6936
6937 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6938
d89f5eff 6939 return 0;
d19a9cd2
ZX		 6940}
6941
6942static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6943{
9fc77441
MT		 6944 int r;
6945 r = vcpu_load(vcpu);
6946 BUG_ON(r);
d19a9cd2
ZX		 6947 kvm_mmu_unload(vcpu);
6948 vcpu_put(vcpu);
6949}
6950
6951static void kvm_free_vcpus(struct kvm *kvm)
6952{
6953 unsigned int i;
988a2cae 6954 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6955
6956 /*
6957 * Unpin any mmu pages first.
6958 */
af585b92
GN		 6959 kvm_for_each_vcpu(i, vcpu, kvm) {
6960 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6961 kvm_unload_vcpu_mmu(vcpu);
af585b92 6962 }
988a2cae
GN		 6963 kvm_for_each_vcpu(i, vcpu, kvm)
6964 kvm_arch_vcpu_free(vcpu);
6965
6966 mutex_lock(&kvm->lock);
6967 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6968 kvm->vcpus[i] = NULL;
d19a9cd2 6969
988a2cae
GN		 6970 atomic_set(&kvm->online_vcpus, 0);
6971 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6972}
6973
ad8ba2cd
SY		 6974void kvm_arch_sync_events(struct kvm *kvm)
6975{
ba4cef31 6976 kvm_free_all_assigned_devices(kvm);
aea924f6 6977 kvm_free_pit(kvm);
ad8ba2cd
SY		 6978}
6979
d19a9cd2
ZX		 6980void kvm_arch_destroy_vm(struct kvm *kvm)
6981{
27469d29
AH		 6982 if (current->mm == kvm->mm) {
6983 /*
6984 * Free memory regions allocated on behalf of userspace,
6985 * unless the the memory map has changed due to process exit
6986 * or fd copying.
6987 */
6988 struct kvm_userspace_memory_region mem;
6989 memset(&mem, 0, sizeof(mem));
6990 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
6991 kvm_set_memory_region(kvm, &mem);
6992
6993 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
6994 kvm_set_memory_region(kvm, &mem);
6995
6996 mem.slot = TSS_PRIVATE_MEMSLOT;
6997 kvm_set_memory_region(kvm, &mem);
6998 }
6eb55818 6999 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7000 kfree(kvm->arch.vpic);
7001 kfree(kvm->arch.vioapic);
d19a9cd2 7002 kvm_free_vcpus(kvm);
3d45830c
AK		 7003 if (kvm->arch.apic_access_page)
7004 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7005 if (kvm->arch.ept_identity_pagetable)
7006 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7007 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7008}
0de10343 7009
db3fe4eb
TY		 7010void kvm_arch_free_memslot(struct kvm_memory_slot *free,
7011 struct kvm_memory_slot *dont)
7012{
7013 int i;
7014
d89cc617
TY		 7015 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7016 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7017 kvm_kvfree(free->arch.rmap[i]);
7018 free->arch.rmap[i] = NULL;
77d11309 7019 }
d89cc617
TY		 7020 if (i == 0)
7021 continue;
7022
7023 if (!dont || free->arch.lpage_info[i - 1] !=
7024 dont->arch.lpage_info[i - 1]) {
7025 kvm_kvfree(free->arch.lpage_info[i - 1]);
7026 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7027 }
7028 }
7029}
7030
7031int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
7032{
7033 int i;
7034
d89cc617 7035 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7036 unsigned long ugfn;
7037 int lpages;
d89cc617 7038 int level = i + 1;
db3fe4eb
TY		 7039
7040 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7041 slot->base_gfn, level) + 1;
7042
d89cc617
TY		 7043 slot->arch.rmap[i] =
7044 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7045 if (!slot->arch.rmap[i])
77d11309 7046 goto out_free;
d89cc617
TY		 7047 if (i == 0)
7048 continue;
77d11309 7049
d89cc617
TY		 7050 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7051 sizeof(*slot->arch.lpage_info[i - 1]));
7052 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7053 goto out_free;
7054
7055 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7056 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7057 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7058 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7059 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7060 /*
7061 * If the gfn and userspace address are not aligned wrt each
7062 * other, or if explicitly asked to, disable large page
7063 * support for this slot
7064 */
7065 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7066 !kvm_largepages_enabled()) {
7067 unsigned long j;
7068
7069 for (j = 0; j < lpages; ++j)
d89cc617 7070 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7071 }
7072 }
7073
7074 return 0;
7075
7076out_free:
d89cc617
TY		 7077 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7078 kvm_kvfree(slot->arch.rmap[i]);
7079 slot->arch.rmap[i] = NULL;
7080 if (i == 0)
7081 continue;
7082
7083 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7084 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7085 }
7086 return -ENOMEM;
7087}
7088
e59dbe09
TY		 7089void kvm_arch_memslots_updated(struct kvm *kvm)
7090{
e6dff7d1
TY		 7091 /*
7092 * memslots->generation has been incremented.
7093 * mmio generation may have reached its maximum value.
7094 */
7095 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7096}
7097
f7784b8e
MT		 7098int kvm_arch_prepare_memory_region(struct kvm *kvm,
7099 struct kvm_memory_slot *memslot,
f7784b8e 7100 struct kvm_userspace_memory_region *mem,
7b6195a9 7101 enum kvm_mr_change change)
0de10343 7102{
7a905b14
TY		 7103 /*
7104 * Only private memory slots need to be mapped here since
7105 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7106 */
7b6195a9 7107 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7108 unsigned long userspace_addr;
604b38ac 7109
7a905b14
TY		 7110 /*
7111 * MAP_SHARED to prevent internal slot pages from being moved
7112 * by fork()/COW.
7113 */
7b6195a9 7114 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7115 PROT_READ | PROT_WRITE,
7116 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7117
7a905b14
TY		 7118 if (IS_ERR((void *)userspace_addr))
7119 return PTR_ERR((void *)userspace_addr);
604b38ac 7120
7a905b14 7121 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7122 }
7123
f7784b8e
MT		 7124 return 0;
7125}
7126
7127void kvm_arch_commit_memory_region(struct kvm *kvm,
7128 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7129 const struct kvm_memory_slot *old,
7130 enum kvm_mr_change change)
f7784b8e
MT		 7131{
7132
8482644a 7133 int nr_mmu_pages = 0;
f7784b8e 7134
8482644a 7135 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7136 int ret;
7137
8482644a
TY		 7138 ret = vm_munmap(old->userspace_addr,
7139 old->npages * PAGE_SIZE);
f7784b8e
MT		 7140 if (ret < 0)
7141 printk(KERN_WARNING
7142 "kvm_vm_ioctl_set_memory_region: "
7143 "failed to munmap memory\n");
7144 }
7145
48c0e4e9
XG		 7146 if (!kvm->arch.n_requested_mmu_pages)
7147 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7148
48c0e4e9 7149 if (nr_mmu_pages)
0de10343 7150 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7151 /*
7152 * Write protect all pages for dirty logging.
7153 * Existing largepage mappings are destroyed here and new ones will
7154 * not be created until the end of the logging.
7155 */
8482644a 7156 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7157 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7158}
1d737c8a 7159
2df72e9b 7160void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7161{
6ca18b69 7162 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7163}
7164
2df72e9b
MT		 7165void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7166 struct kvm_memory_slot *slot)
7167{
6ca18b69 7168 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7169}
7170
1d737c8a
ZX		 7171int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7172{
af585b92
GN		 7173 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7174 !vcpu->arch.apf.halted)
7175 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7176 || kvm_apic_has_events(vcpu)
7460fb4a 7177 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7178 (kvm_arch_interrupt_allowed(vcpu) &&
7179 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7180}
5736199a 7181
b6d33834 7182int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7183{
b6d33834 7184 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7185}
78646121
GN		 7186
7187int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7188{
7189 return kvm_x86_ops->interrupt_allowed(vcpu);
7190}
229456fc 7191
f92653ee
JK		 7192bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7193{
7194 unsigned long current_rip = kvm_rip_read(vcpu) +
7195 get_segment_base(vcpu, VCPU_SREG_CS);
7196
7197 return current_rip == linear_rip;
7198}
7199EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7200
94fe45da
JK		 7201unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7202{
7203 unsigned long rflags;
7204
7205 rflags = kvm_x86_ops->get_rflags(vcpu);
7206 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7207 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7208 return rflags;
7209}
7210EXPORT_SYMBOL_GPL(kvm_get_rflags);
7211
7212void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7213{
7214 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7215 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7216 rflags |= X86_EFLAGS_TF;
94fe45da 7217 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7218 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7219}
7220EXPORT_SYMBOL_GPL(kvm_set_rflags);
7221
56028d08
GN		 7222void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7223{
7224 int r;
7225
fb67e14f 7226 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 7227 is_error_page(work->page))
56028d08
GN		 7228 return;
7229
7230 r = kvm_mmu_reload(vcpu);
7231 if (unlikely(r))
7232 return;
7233
fb67e14f
XG		 7234 if (!vcpu->arch.mmu.direct_map &&
7235 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7236 return;
7237
56028d08
GN		 7238 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7239}
7240
af585b92
GN		 7241static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7242{
7243 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7244}
7245
7246static inline u32 kvm_async_pf_next_probe(u32 key)
7247{
7248 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7249}
7250
7251static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7252{
7253 u32 key = kvm_async_pf_hash_fn(gfn);
7254
7255 while (vcpu->arch.apf.gfns[key] != ~0)
7256 key = kvm_async_pf_next_probe(key);
7257
7258 vcpu->arch.apf.gfns[key] = gfn;
7259}
7260
7261static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7262{
7263 int i;
7264 u32 key = kvm_async_pf_hash_fn(gfn);
7265
7266 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7267 (vcpu->arch.apf.gfns[key] != gfn &&
7268 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7269 key = kvm_async_pf_next_probe(key);
7270
7271 return key;
7272}
7273
7274bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7275{
7276 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7277}
7278
7279static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7280{
7281 u32 i, j, k;
7282
7283 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7284 while (true) {
7285 vcpu->arch.apf.gfns[i] = ~0;
7286 do {
7287 j = kvm_async_pf_next_probe(j);
7288 if (vcpu->arch.apf.gfns[j] == ~0)
7289 return;
7290 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7291 /*
7292 * k lies cyclically in ]i,j]
7293 * | i.k.j |
7294 * |....j i.k.| or |.k..j i...|
7295 */
7296 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7297 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7298 i = j;
7299 }
7300}
7301
7c90705b
GN		 7302static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7303{
7304
7305 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7306 sizeof(val));
7307}
7308
af585b92
GN		 7309void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7310 struct kvm_async_pf *work)
7311{
6389ee94
AK		 7312 struct x86_exception fault;
7313
7c90705b 7314 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7315 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7316
7317 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7318 (vcpu->arch.apf.send_user_only &&
7319 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7320 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7321 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7322 fault.vector = PF_VECTOR;
7323 fault.error_code_valid = true;
7324 fault.error_code = 0;
7325 fault.nested_page_fault = false;
7326 fault.address = work->arch.token;
7327 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7328 }
af585b92
GN		 7329}
7330
7331void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7332 struct kvm_async_pf *work)
7333{
6389ee94
AK		 7334 struct x86_exception fault;
7335
7c90705b
GN		 7336 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7337 if (is_error_page(work->page))
7338 work->arch.token = ~0; /* broadcast wakeup */
7339 else
7340 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7341
7342 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7343 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7344 fault.vector = PF_VECTOR;
7345 fault.error_code_valid = true;
7346 fault.error_code = 0;
7347 fault.nested_page_fault = false;
7348 fault.address = work->arch.token;
7349 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7350 }
e6d53e3b 7351 vcpu->arch.apf.halted = false;
a4fa1635 7352 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7353}
7354
7355bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7356{
7357 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7358 return true;
7359 else
7360 return !kvm_event_needs_reinjection(vcpu) &&
7361 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7362}
7363
229456fc
MT		 7364EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7365EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7366EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7367EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7368EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7369EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7370EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7371EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7372EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7373EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7374EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7375EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7376EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux 6.x block layer and io_uring tree(s)