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KVM: x86: expose ADX feature to guest
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
58cb628d
JK		 260int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261{
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
6866b83e
CO		 280}
281EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
e3ba45b8
GL		 283asmlinkage void kvm_spurious_fault(void)
284{
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287}
288EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
3fd28fce
ED		 290#define EXCPT_BENIGN 0
291#define EXCPT_CONTRIBUTORY 1
292#define EXCPT_PF 2
293
294static int exception_class(int vector)
295{
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309}
310
311static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
3fd28fce
ED		 314{
315 u32 prev_nr;
316 int class1, class2;
317
3842d135
AK		 318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
3fd28fce
ED		 320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
3f0fd292 326 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
a8eeb04a 334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351}
352
298101da
AK		 353void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354{
ce7ddec4 355 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 356}
357EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
ce7ddec4
JR		 359void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360{
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362}
363EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
db8fcefa 365void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 366{
db8fcefa
AP		 367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371}
372EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 373
6389ee94 374void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 375{
376 ++vcpu->stat.pf_guest;
6389ee94
AK		 377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 379}
27d6c865 380EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 381
6389ee94 382void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 383{
6389ee94
AK		 384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 386 else
6389ee94 387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 388}
389
3419ffc8
SY		 390void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391{
7460fb4a
AK		 392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 394}
395EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
298101da
AK		 397void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
ce7ddec4
JR		 403void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404{
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
0a79b009
AK		 409/*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 414{
0a79b009
AK		 415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
298101da 419}
0a79b009 420EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 421
ec92fe44
JR		 422/*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430{
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442}
443EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
3d06b8bf
JR		 445int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447{
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450}
451
a03490ed
CO		 452/*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
ff03a073 455int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 456{
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
ff03a073 461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 462
ff03a073
JR		 463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 471 if (is_present_gpte(pdpte[i]) &&
20c466b5 472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
ff03a073 479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 484out:
a03490ed
CO		 485
486 return ret;
487}
cc4b6871 488EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 489
d835dfec
AK		 490static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491{
ff03a073 492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 493 bool changed = true;
3d06b8bf
JR		 494 int offset;
495 gfn_t gfn;
d835dfec
AK		 496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
6de4f3ad
AK		 501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
9f8fe504
AK		 505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 509 if (r < 0)
510 goto out;
ff03a073 511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 512out:
d835dfec
AK		 513
514 return changed;
515}
516
49a9b07e 517int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 518{
aad82703
SY		 519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
f9a48e6a
AK		 523 cr0 |= X86_CR0_ET;
524
ab344828 525#ifdef CONFIG_X86_64
0f12244f
GN		 526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
ab344828
GN		 528#endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 531
0f12244f
GN		 532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
a03490ed 534
0f12244f
GN		 535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
a03490ed
CO		 537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539#ifdef CONFIG_X86_64
f6801dff 540 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 541 int cs_db, cs_l;
542
0f12244f
GN		 543 if (!is_pae(vcpu))
544 return 1;
a03490ed 545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 546 if (cs_l)
547 return 1;
a03490ed
CO		 548 } else
549#endif
ff03a073 550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 551 kvm_read_cr3(vcpu)))
0f12244f 552 return 1;
a03490ed
CO		 553 }
554
ad756a16
MJ		 555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
a03490ed 558 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 559
d170c419 560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 561 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 562 kvm_async_pf_hash_reset(vcpu);
563 }
e5f3f027 564
aad82703
SY		 565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 567 return 0;
568}
2d3ad1f4 569EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 570
2d3ad1f4 571void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 572{
49a9b07e 573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 574}
2d3ad1f4 575EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 576
42bdf991
MT		 577static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578{
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585}
586
587static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588{
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594}
595
2acf923e
DC		 596int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
598 u64 xcr0;
46c34cb0 599 u64 valid_bits;
2acf923e
DC		 600
601 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
602 if (index != XCR_XFEATURE_ENABLED_MASK)
603 return 1;
604 xcr0 = xcr;
2acf923e
DC		 605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
46c34cb0
PB		 609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
2acf923e 617 return 1;
46c34cb0 618
42bdf991 619 kvm_put_guest_xcr0(vcpu);
2acf923e 620 vcpu->arch.xcr0 = xcr0;
2acf923e
DC		 621 return 0;
622}
623
624int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
625{
764bcbc5
Z		 626 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
627 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 628 kvm_inject_gp(vcpu, 0);
629 return 1;
630 }
631 return 0;
632}
633EXPORT_SYMBOL_GPL(kvm_set_xcr);
634
a83b29c6 635int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 636{
fc78f519 637 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 638 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
639 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 640 if (cr4 & CR4_RESERVED_BITS)
641 return 1;
a03490ed 642
2acf923e
DC		 643 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
644 return 1;
645
c68b734f
YW		 646 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
647 return 1;
648
afcbf13f 649 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 650 return 1;
651
a03490ed 652 if (is_long_mode(vcpu)) {
0f12244f
GN		 653 if (!(cr4 & X86_CR4_PAE))
654 return 1;
a2edf57f
AK		 655 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
656 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 657 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
658 kvm_read_cr3(vcpu)))
0f12244f
GN		 659 return 1;
660
ad756a16
MJ		 661 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
662 if (!guest_cpuid_has_pcid(vcpu))
663 return 1;
664
665 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
666 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
667 return 1;
668 }
669
5e1746d6 670 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 671 return 1;
a03490ed 672
ad756a16
MJ		 673 if (((cr4 ^ old_cr4) & pdptr_bits) ||
674 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 675 kvm_mmu_reset_context(vcpu);
0f12244f 676
2acf923e 677 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 678 kvm_update_cpuid(vcpu);
2acf923e 679
0f12244f
GN		 680 return 0;
681}
2d3ad1f4 682EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 683
2390218b 684int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 685{
9f8fe504 686 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 687 kvm_mmu_sync_roots(vcpu);
d835dfec 688 kvm_mmu_flush_tlb(vcpu);
0f12244f 689 return 0;
d835dfec
AK		 690 }
691
a03490ed 692 if (is_long_mode(vcpu)) {
471842ec 693 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 694 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
695 return 1;
696 } else
697 if (cr3 & CR3_L_MODE_RESERVED_BITS)
698 return 1;
a03490ed
CO		 699 } else {
700 if (is_pae(vcpu)) {
0f12244f
GN		 701 if (cr3 & CR3_PAE_RESERVED_BITS)
702 return 1;
ff03a073
JR		 703 if (is_paging(vcpu) &&
704 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 705 return 1;
a03490ed
CO		 706 }
707 /*
708 * We don't check reserved bits in nonpae mode, because
709 * this isn't enforced, and VMware depends on this.
710 */
711 }
712
0f12244f 713 vcpu->arch.cr3 = cr3;
aff48baa 714 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 715 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 716 return 0;
717}
2d3ad1f4 718EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 719
eea1cff9 720int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 721{
0f12244f
GN		 722 if (cr8 & CR8_RESERVED_BITS)
723 return 1;
a03490ed
CO		 724 if (irqchip_in_kernel(vcpu->kvm))
725 kvm_lapic_set_tpr(vcpu, cr8);
726 else
ad312c7c 727 vcpu->arch.cr8 = cr8;
0f12244f
GN		 728 return 0;
729}
2d3ad1f4 730EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 731
2d3ad1f4 732unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 733{
734 if (irqchip_in_kernel(vcpu->kvm))
735 return kvm_lapic_get_cr8(vcpu);
736 else
ad312c7c 737 return vcpu->arch.cr8;
a03490ed 738}
2d3ad1f4 739EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 740
73aaf249
JK		 741static void kvm_update_dr6(struct kvm_vcpu *vcpu)
742{
743 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
744 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
745}
746
c8639010
JK		 747static void kvm_update_dr7(struct kvm_vcpu *vcpu)
748{
749 unsigned long dr7;
750
751 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
752 dr7 = vcpu->arch.guest_debug_dr7;
753 else
754 dr7 = vcpu->arch.dr7;
755 kvm_x86_ops->set_dr7(vcpu, dr7);
756 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
757}
758
338dbc97 759static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 760{
761 switch (dr) {
762 case 0 ... 3:
763 vcpu->arch.db[dr] = val;
764 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
765 vcpu->arch.eff_db[dr] = val;
766 break;
767 case 4:
338dbc97
GN		 768 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
769 return 1; /* #UD */
020df079
GN		 770 /* fall through */
771 case 6:
338dbc97
GN		 772 if (val & 0xffffffff00000000ULL)
773 return -1; /* #GP */
020df079 774 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 775 kvm_update_dr6(vcpu);
020df079
GN		 776 break;
777 case 5:
338dbc97
GN		 778 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
779 return 1; /* #UD */
020df079
GN		 780 /* fall through */
781 default: /* 7 */
338dbc97
GN		 782 if (val & 0xffffffff00000000ULL)
783 return -1; /* #GP */
020df079 784 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 785 kvm_update_dr7(vcpu);
020df079
GN		 786 break;
787 }
788
789 return 0;
790}
338dbc97
GN		 791
792int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
793{
794 int res;
795
796 res = __kvm_set_dr(vcpu, dr, val);
797 if (res > 0)
798 kvm_queue_exception(vcpu, UD_VECTOR);
799 else if (res < 0)
800 kvm_inject_gp(vcpu, 0);
801
802 return res;
803}
020df079
GN		 804EXPORT_SYMBOL_GPL(kvm_set_dr);
805
338dbc97 806static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 807{
808 switch (dr) {
809 case 0 ... 3:
810 *val = vcpu->arch.db[dr];
811 break;
812 case 4:
338dbc97 813 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 814 return 1;
020df079
GN		 815 /* fall through */
816 case 6:
73aaf249
JK		 817 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
818 *val = vcpu->arch.dr6;
819 else
820 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 821 break;
822 case 5:
338dbc97 823 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 824 return 1;
020df079
GN		 825 /* fall through */
826 default: /* 7 */
827 *val = vcpu->arch.dr7;
828 break;
829 }
830
831 return 0;
832}
338dbc97
GN		 833
834int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
835{
836 if (_kvm_get_dr(vcpu, dr, val)) {
837 kvm_queue_exception(vcpu, UD_VECTOR);
838 return 1;
839 }
840 return 0;
841}
020df079
GN		 842EXPORT_SYMBOL_GPL(kvm_get_dr);
843
022cd0e8
AK		 844bool kvm_rdpmc(struct kvm_vcpu *vcpu)
845{
846 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
847 u64 data;
848 int err;
849
850 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
851 if (err)
852 return err;
853 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
854 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
855 return err;
856}
857EXPORT_SYMBOL_GPL(kvm_rdpmc);
858
043405e1
CO		 859/*
860 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
861 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
862 *
863 * This list is modified at module load time to reflect the
e3267cbb
GC		 864 * capabilities of the host cpu. This capabilities test skips MSRs that are
865 * kvm-specific. Those are put in the beginning of the list.
043405e1 866 */
e3267cbb 867
e984097b 868#define KVM_SAVE_MSRS_BEGIN 12
043405e1 869static u32 msrs_to_save[] = {
e3267cbb 870 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 871 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 872 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 873 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 874 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 875 MSR_KVM_PV_EOI_EN,
043405e1 876 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 877 MSR_STAR,
043405e1
CO		 878#ifdef CONFIG_X86_64
879 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
880#endif
b3897a49
NHE		 881 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
882 MSR_IA32_FEATURE_CONTROL
043405e1
CO		 883};
884
885static unsigned num_msrs_to_save;
886
f1d24831 887static const u32 emulated_msrs[] = {
ba904635 888 MSR_IA32_TSC_ADJUST,
a3e06bbe 889 MSR_IA32_TSCDEADLINE,
043405e1 890 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 891 MSR_IA32_MCG_STATUS,
892 MSR_IA32_MCG_CTL,
043405e1
CO		 893};
894
384bb783 895bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 896{
b69e8cae 897 if (efer & efer_reserved_bits)
384bb783 898 return false;
15c4a640 899
1b2fd70c
AG		 900 if (efer & EFER_FFXSR) {
901 struct kvm_cpuid_entry2 *feat;
902
903 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 904 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 905 return false;
1b2fd70c
AG		 906 }
907
d8017474
AG		 908 if (efer & EFER_SVME) {
909 struct kvm_cpuid_entry2 *feat;
910
911 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 912 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 913 return false;
d8017474
AG		 914 }
915
384bb783
JK		 916 return true;
917}
918EXPORT_SYMBOL_GPL(kvm_valid_efer);
919
920static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
921{
922 u64 old_efer = vcpu->arch.efer;
923
924 if (!kvm_valid_efer(vcpu, efer))
925 return 1;
926
927 if (is_paging(vcpu)
928 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
929 return 1;
930
15c4a640 931 efer &= ~EFER_LMA;
f6801dff 932 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 933
a3d204e2
SY		 934 kvm_x86_ops->set_efer(vcpu, efer);
935
aad82703
SY		 936 /* Update reserved bits */
937 if ((efer ^ old_efer) & EFER_NX)
938 kvm_mmu_reset_context(vcpu);
939
b69e8cae 940 return 0;
15c4a640
CO		 941}
942
f2b4b7dd
JR		 943void kvm_enable_efer_bits(u64 mask)
944{
945 efer_reserved_bits &= ~mask;
946}
947EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
948
949
15c4a640
CO		 950/*
951 * Writes msr value into into the appropriate "register".
952 * Returns 0 on success, non-0 otherwise.
953 * Assumes vcpu_load() was already called.
954 */
8fe8ab46 955int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 956{
8fe8ab46 957 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 958}
959
313a3dc7
CO		 960/*
961 * Adapt set_msr() to msr_io()'s calling convention
962 */
963static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
964{
8fe8ab46
WA		 965 struct msr_data msr;
966
967 msr.data = *data;
968 msr.index = index;
969 msr.host_initiated = true;
970 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 971}
972
16e8d74d
MT		 973#ifdef CONFIG_X86_64
974struct pvclock_gtod_data {
975 seqcount_t seq;
976
977 struct { /* extract of a clocksource struct */
978 int vclock_mode;
979 cycle_t cycle_last;
980 cycle_t mask;
981 u32 mult;
982 u32 shift;
983 } clock;
984
985 /* open coded 'struct timespec' */
986 u64 monotonic_time_snsec;
987 time_t monotonic_time_sec;
988};
989
990static struct pvclock_gtod_data pvclock_gtod_data;
991
992static void update_pvclock_gtod(struct timekeeper *tk)
993{
994 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
995
996 write_seqcount_begin(&vdata->seq);
997
998 /* copy pvclock gtod data */
999 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1000 vdata->clock.cycle_last = tk->clock->cycle_last;
1001 vdata->clock.mask = tk->clock->mask;
1002 vdata->clock.mult = tk->mult;
1003 vdata->clock.shift = tk->shift;
1004
1005 vdata->monotonic_time_sec = tk->xtime_sec
1006 + tk->wall_to_monotonic.tv_sec;
1007 vdata->monotonic_time_snsec = tk->xtime_nsec
1008 + (tk->wall_to_monotonic.tv_nsec
1009 << tk->shift);
1010 while (vdata->monotonic_time_snsec >=
1011 (((u64)NSEC_PER_SEC) << tk->shift)) {
1012 vdata->monotonic_time_snsec -=
1013 ((u64)NSEC_PER_SEC) << tk->shift;
1014 vdata->monotonic_time_sec++;
1015 }
1016
1017 write_seqcount_end(&vdata->seq);
1018}
1019#endif
1020
1021
18068523
GOC		 1022static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1023{
9ed3c444
AK		 1024 int version;
1025 int r;
50d0a0f9 1026 struct pvclock_wall_clock wc;
923de3cf 1027 struct timespec boot;
18068523
GOC		 1028
1029 if (!wall_clock)
1030 return;
1031
9ed3c444
AK		 1032 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1033 if (r)
1034 return;
1035
1036 if (version & 1)
1037 ++version; /* first time write, random junk */
1038
1039 ++version;
18068523 1040
18068523
GOC		 1041 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1042
50d0a0f9
GH		 1043 /*
1044 * The guest calculates current wall clock time by adding
34c238a1 1045 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1046 * wall clock specified here. guest system time equals host
1047 * system time for us, thus we must fill in host boot time here.
1048 */
923de3cf 1049 getboottime(&boot);
50d0a0f9 1050
4b648665
BR		 1051 if (kvm->arch.kvmclock_offset) {
1052 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1053 boot = timespec_sub(boot, ts);
1054 }
50d0a0f9
GH		 1055 wc.sec = boot.tv_sec;
1056 wc.nsec = boot.tv_nsec;
1057 wc.version = version;
18068523
GOC		 1058
1059 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1060
1061 version++;
1062 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1063}
1064
50d0a0f9
GH		 1065static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1066{
1067 uint32_t quotient, remainder;
1068
1069 /* Don't try to replace with do_div(), this one calculates
1070 * "(dividend << 32) / divisor" */
1071 __asm__ ( "divl %4"
1072 : "=a" (quotient), "=d" (remainder)
1073 : "0" (0), "1" (dividend), "r" (divisor) );
1074 return quotient;
1075}
1076
5f4e3f88
ZA		 1077static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1078 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1079{
5f4e3f88 1080 uint64_t scaled64;
50d0a0f9
GH		 1081 int32_t shift = 0;
1082 uint64_t tps64;
1083 uint32_t tps32;
1084
5f4e3f88
ZA		 1085 tps64 = base_khz * 1000LL;
1086 scaled64 = scaled_khz * 1000LL;
50933623 1087 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1088 tps64 >>= 1;
1089 shift--;
1090 }
1091
1092 tps32 = (uint32_t)tps64;
50933623
JK		 1093 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1094 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1095 scaled64 >>= 1;
1096 else
1097 tps32 <<= 1;
50d0a0f9
GH		 1098 shift++;
1099 }
1100
5f4e3f88
ZA		 1101 *pshift = shift;
1102 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1103
5f4e3f88
ZA		 1104 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1105 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1106}
1107
759379dd
ZA		 1108static inline u64 get_kernel_ns(void)
1109{
1110 struct timespec ts;
1111
1112 WARN_ON(preemptible());
1113 ktime_get_ts(&ts);
1114 monotonic_to_bootbased(&ts);
1115 return timespec_to_ns(&ts);
50d0a0f9
GH		 1116}
1117
d828199e 1118#ifdef CONFIG_X86_64
16e8d74d 1119static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1120#endif
16e8d74d 1121
c8076604 1122static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1123unsigned long max_tsc_khz;
c8076604 1124
cc578287 1125static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1126{
cc578287
ZA		 1127 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1128 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1129}
1130
cc578287 1131static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1132{
cc578287
ZA		 1133 u64 v = (u64)khz * (1000000 + ppm);
1134 do_div(v, 1000000);
1135 return v;
1e993611
JR		 1136}
1137
cc578287 1138static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1139{
cc578287
ZA		 1140 u32 thresh_lo, thresh_hi;
1141 int use_scaling = 0;
217fc9cf 1142
03ba32ca
MT		 1143 /* tsc_khz can be zero if TSC calibration fails */
1144 if (this_tsc_khz == 0)
1145 return;
1146
c285545f
ZA		 1147 /* Compute a scale to convert nanoseconds in TSC cycles */
1148 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1149 &vcpu->arch.virtual_tsc_shift,
1150 &vcpu->arch.virtual_tsc_mult);
1151 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1152
1153 /*
1154 * Compute the variation in TSC rate which is acceptable
1155 * within the range of tolerance and decide if the
1156 * rate being applied is within that bounds of the hardware
1157 * rate. If so, no scaling or compensation need be done.
1158 */
1159 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1160 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1161 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1162 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1163 use_scaling = 1;
1164 }
1165 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1166}
1167
1168static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1169{
e26101b1 1170 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1171 vcpu->arch.virtual_tsc_mult,
1172 vcpu->arch.virtual_tsc_shift);
e26101b1 1173 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1174 return tsc;
1175}
1176
b48aa97e
MT		 1177void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1178{
1179#ifdef CONFIG_X86_64
1180 bool vcpus_matched;
1181 bool do_request = false;
1182 struct kvm_arch *ka = &vcpu->kvm->arch;
1183 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1184
1185 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1186 atomic_read(&vcpu->kvm->online_vcpus));
1187
1188 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1189 if (!ka->use_master_clock)
1190 do_request = 1;
1191
1192 if (!vcpus_matched && ka->use_master_clock)
1193 do_request = 1;
1194
1195 if (do_request)
1196 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1197
1198 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1199 atomic_read(&vcpu->kvm->online_vcpus),
1200 ka->use_master_clock, gtod->clock.vclock_mode);
1201#endif
1202}
1203
ba904635
WA		 1204static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1205{
1206 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1207 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1208}
1209
8fe8ab46 1210void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1211{
1212 struct kvm *kvm = vcpu->kvm;
f38e098f 1213 u64 offset, ns, elapsed;
99e3e30a 1214 unsigned long flags;
02626b6a 1215 s64 usdiff;
b48aa97e 1216 bool matched;
8fe8ab46 1217 u64 data = msr->data;
99e3e30a 1218
038f8c11 1219 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1220 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1221 ns = get_kernel_ns();
f38e098f 1222 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1223
03ba32ca 1224 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1225 int faulted = 0;
1226
03ba32ca
MT		 1227 /* n.b - signed multiplication and division required */
1228 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1229#ifdef CONFIG_X86_64
03ba32ca 1230 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1231#else
03ba32ca 1232 /* do_div() only does unsigned */
8915aa27
MT		 1233 asm("1: idivl %[divisor]\n"
1234 "2: xor %%edx, %%edx\n"
1235 " movl $0, %[faulted]\n"
1236 "3:\n"
1237 ".section .fixup,\"ax\"\n"
1238 "4: movl $1, %[faulted]\n"
1239 " jmp 3b\n"
1240 ".previous\n"
1241
1242 _ASM_EXTABLE(1b, 4b)
1243
1244 : "=A"(usdiff), [faulted] "=r" (faulted)
1245 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1246
5d3cb0f6 1247#endif
03ba32ca
MT		 1248 do_div(elapsed, 1000);
1249 usdiff -= elapsed;
1250 if (usdiff < 0)
1251 usdiff = -usdiff;
8915aa27
MT		 1252
1253 /* idivl overflow => difference is larger than USEC_PER_SEC */
1254 if (faulted)
1255 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1256 } else
1257 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1258
1259 /*
5d3cb0f6
ZA		 1260 * Special case: TSC write with a small delta (1 second) of virtual
1261 * cycle time against real time is interpreted as an attempt to
1262 * synchronize the CPU.
1263 *
1264 * For a reliable TSC, we can match TSC offsets, and for an unstable
1265 * TSC, we add elapsed time in this computation. We could let the
1266 * compensation code attempt to catch up if we fall behind, but
1267 * it's better to try to match offsets from the beginning.
1268 */
02626b6a 1269 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1270 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1271 if (!check_tsc_unstable()) {
e26101b1 1272 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1273 pr_debug("kvm: matched tsc offset for %llu\n", data);
1274 } else {
857e4099 1275 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1276 data += delta;
1277 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1278 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1279 }
b48aa97e 1280 matched = true;
e26101b1
ZA		 1281 } else {
1282 /*
1283 * We split periods of matched TSC writes into generations.
1284 * For each generation, we track the original measured
1285 * nanosecond time, offset, and write, so if TSCs are in
1286 * sync, we can match exact offset, and if not, we can match
4a969980 1287 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1288 *
1289 * These values are tracked in kvm->arch.cur_xxx variables.
1290 */
1291 kvm->arch.cur_tsc_generation++;
1292 kvm->arch.cur_tsc_nsec = ns;
1293 kvm->arch.cur_tsc_write = data;
1294 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1295 matched = false;
e26101b1
ZA		 1296 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1297 kvm->arch.cur_tsc_generation, data);
f38e098f 1298 }
e26101b1
ZA		 1299
1300 /*
1301 * We also track th most recent recorded KHZ, write and time to
1302 * allow the matching interval to be extended at each write.
1303 */
f38e098f
ZA		 1304 kvm->arch.last_tsc_nsec = ns;
1305 kvm->arch.last_tsc_write = data;
5d3cb0f6 1306 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1307
b183aa58 1308 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1309
1310 /* Keep track of which generation this VCPU has synchronized to */
1311 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1312 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1313 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1314
ba904635
WA		 1315 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1316 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1317 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1318 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1319
1320 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1321 if (matched)
1322 kvm->arch.nr_vcpus_matched_tsc++;
1323 else
1324 kvm->arch.nr_vcpus_matched_tsc = 0;
1325
1326 kvm_track_tsc_matching(vcpu);
1327 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1328}
e26101b1 1329
99e3e30a
ZA		 1330EXPORT_SYMBOL_GPL(kvm_write_tsc);
1331
d828199e
MT		 1332#ifdef CONFIG_X86_64
1333
1334static cycle_t read_tsc(void)
1335{
1336 cycle_t ret;
1337 u64 last;
1338
1339 /*
1340 * Empirically, a fence (of type that depends on the CPU)
1341 * before rdtsc is enough to ensure that rdtsc is ordered
1342 * with respect to loads. The various CPU manuals are unclear
1343 * as to whether rdtsc can be reordered with later loads,
1344 * but no one has ever seen it happen.
1345 */
1346 rdtsc_barrier();
1347 ret = (cycle_t)vget_cycles();
1348
1349 last = pvclock_gtod_data.clock.cycle_last;
1350
1351 if (likely(ret >= last))
1352 return ret;
1353
1354 /*
1355 * GCC likes to generate cmov here, but this branch is extremely
1356 * predictable (it's just a funciton of time and the likely is
1357 * very likely) and there's a data dependence, so force GCC
1358 * to generate a branch instead. I don't barrier() because
1359 * we don't actually need a barrier, and if this function
1360 * ever gets inlined it will generate worse code.
1361 */
1362 asm volatile ("");
1363 return last;
1364}
1365
1366static inline u64 vgettsc(cycle_t *cycle_now)
1367{
1368 long v;
1369 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1370
1371 *cycle_now = read_tsc();
1372
1373 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1374 return v * gtod->clock.mult;
1375}
1376
1377static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1378{
1379 unsigned long seq;
1380 u64 ns;
1381 int mode;
1382 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1383
1384 ts->tv_nsec = 0;
1385 do {
1386 seq = read_seqcount_begin(&gtod->seq);
1387 mode = gtod->clock.vclock_mode;
1388 ts->tv_sec = gtod->monotonic_time_sec;
1389 ns = gtod->monotonic_time_snsec;
1390 ns += vgettsc(cycle_now);
1391 ns >>= gtod->clock.shift;
1392 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1393 timespec_add_ns(ts, ns);
1394
1395 return mode;
1396}
1397
1398/* returns true if host is using tsc clocksource */
1399static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1400{
1401 struct timespec ts;
1402
1403 /* checked again under seqlock below */
1404 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1405 return false;
1406
1407 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1408 return false;
1409
1410 monotonic_to_bootbased(&ts);
1411 *kernel_ns = timespec_to_ns(&ts);
1412
1413 return true;
1414}
1415#endif
1416
1417/*
1418 *
b48aa97e
MT		 1419 * Assuming a stable TSC across physical CPUS, and a stable TSC
1420 * across virtual CPUs, the following condition is possible.
1421 * Each numbered line represents an event visible to both
d828199e
MT		 1422 * CPUs at the next numbered event.
1423 *
1424 * "timespecX" represents host monotonic time. "tscX" represents
1425 * RDTSC value.
1426 *
1427 * VCPU0 on CPU0 | VCPU1 on CPU1
1428 *
1429 * 1. read timespec0,tsc0
1430 * 2. | timespec1 = timespec0 + N
1431 * | tsc1 = tsc0 + M
1432 * 3. transition to guest | transition to guest
1433 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1434 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1435 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1436 *
1437 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1438 *
1439 * - ret0 < ret1
1440 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1441 * ...
1442 * - 0 < N - M => M < N
1443 *
1444 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1445 * always the case (the difference between two distinct xtime instances
1446 * might be smaller then the difference between corresponding TSC reads,
1447 * when updating guest vcpus pvclock areas).
1448 *
1449 * To avoid that problem, do not allow visibility of distinct
1450 * system_timestamp/tsc_timestamp values simultaneously: use a master
1451 * copy of host monotonic time values. Update that master copy
1452 * in lockstep.
1453 *
b48aa97e 1454 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1455 *
1456 */
1457
1458static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1459{
1460#ifdef CONFIG_X86_64
1461 struct kvm_arch *ka = &kvm->arch;
1462 int vclock_mode;
b48aa97e
MT		 1463 bool host_tsc_clocksource, vcpus_matched;
1464
1465 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1466 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1467
1468 /*
1469 * If the host uses TSC clock, then passthrough TSC as stable
1470 * to the guest.
1471 */
b48aa97e 1472 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1473 &ka->master_kernel_ns,
1474 &ka->master_cycle_now);
1475
b48aa97e
MT		 1476 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1477
d828199e
MT		 1478 if (ka->use_master_clock)
1479 atomic_set(&kvm_guest_has_master_clock, 1);
1480
1481 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1482 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1483 vcpus_matched);
d828199e
MT		 1484#endif
1485}
1486
2e762ff7
MT		 1487static void kvm_gen_update_masterclock(struct kvm *kvm)
1488{
1489#ifdef CONFIG_X86_64
1490 int i;
1491 struct kvm_vcpu *vcpu;
1492 struct kvm_arch *ka = &kvm->arch;
1493
1494 spin_lock(&ka->pvclock_gtod_sync_lock);
1495 kvm_make_mclock_inprogress_request(kvm);
1496 /* no guest entries from this point */
1497 pvclock_update_vm_gtod_copy(kvm);
1498
1499 kvm_for_each_vcpu(i, vcpu, kvm)
1500 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1501
1502 /* guest entries allowed */
1503 kvm_for_each_vcpu(i, vcpu, kvm)
1504 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1505
1506 spin_unlock(&ka->pvclock_gtod_sync_lock);
1507#endif
1508}
1509
34c238a1 1510static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1511{
d828199e 1512 unsigned long flags, this_tsc_khz;
18068523 1513 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1514 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1515 s64 kernel_ns;
d828199e 1516 u64 tsc_timestamp, host_tsc;
0b79459b 1517 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1518 u8 pvclock_flags;
d828199e
MT		 1519 bool use_master_clock;
1520
1521 kernel_ns = 0;
1522 host_tsc = 0;
18068523 1523
d828199e
MT		 1524 /*
1525 * If the host uses TSC clock, then passthrough TSC as stable
1526 * to the guest.
1527 */
1528 spin_lock(&ka->pvclock_gtod_sync_lock);
1529 use_master_clock = ka->use_master_clock;
1530 if (use_master_clock) {
1531 host_tsc = ka->master_cycle_now;
1532 kernel_ns = ka->master_kernel_ns;
1533 }
1534 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1535
1536 /* Keep irq disabled to prevent changes to the clock */
1537 local_irq_save(flags);
1538 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1539 if (unlikely(this_tsc_khz == 0)) {
1540 local_irq_restore(flags);
1541 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1542 return 1;
1543 }
d828199e
MT		 1544 if (!use_master_clock) {
1545 host_tsc = native_read_tsc();
1546 kernel_ns = get_kernel_ns();
1547 }
1548
1549 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1550
c285545f
ZA		 1551 /*
1552 * We may have to catch up the TSC to match elapsed wall clock
1553 * time for two reasons, even if kvmclock is used.
1554 * 1) CPU could have been running below the maximum TSC rate
1555 * 2) Broken TSC compensation resets the base at each VCPU
1556 * entry to avoid unknown leaps of TSC even when running
1557 * again on the same CPU. This may cause apparent elapsed
1558 * time to disappear, and the guest to stand still or run
1559 * very slowly.
1560 */
1561 if (vcpu->tsc_catchup) {
1562 u64 tsc = compute_guest_tsc(v, kernel_ns);
1563 if (tsc > tsc_timestamp) {
f1e2b260 1564 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1565 tsc_timestamp = tsc;
1566 }
50d0a0f9
GH		 1567 }
1568
18068523
GOC		 1569 local_irq_restore(flags);
1570
0b79459b 1571 if (!vcpu->pv_time_enabled)
c285545f 1572 return 0;
18068523 1573
e48672fa 1574 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1575 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1576 &vcpu->hv_clock.tsc_shift,
1577 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1578 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1579 }
1580
1581 /* With all the info we got, fill in the values */
1d5f066e 1582 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1583 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1584 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1585
18068523
GOC		 1586 /*
1587 * The interface expects us to write an even number signaling that the
1588 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1589 * state, we just increase by 2 at the end.
18068523 1590 */
50d0a0f9 1591 vcpu->hv_clock.version += 2;
18068523 1592
0b79459b
AH		 1593 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1594 &guest_hv_clock, sizeof(guest_hv_clock))))
1595 return 0;
78c0337a
MT		 1596
1597 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1598 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1599
1600 if (vcpu->pvclock_set_guest_stopped_request) {
1601 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1602 vcpu->pvclock_set_guest_stopped_request = false;
1603 }
1604
d828199e
MT		 1605 /* If the host uses TSC clocksource, then it is stable */
1606 if (use_master_clock)
1607 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1608
78c0337a
MT		 1609 vcpu->hv_clock.flags = pvclock_flags;
1610
0b79459b
AH		 1611 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1612 &vcpu->hv_clock,
1613 sizeof(vcpu->hv_clock));
8cfdc000 1614 return 0;
c8076604
GH		 1615}
1616
0061d53d
MT		 1617/*
1618 * kvmclock updates which are isolated to a given vcpu, such as
1619 * vcpu->cpu migration, should not allow system_timestamp from
1620 * the rest of the vcpus to remain static. Otherwise ntp frequency
1621 * correction applies to one vcpu's system_timestamp but not
1622 * the others.
1623 *
1624 * So in those cases, request a kvmclock update for all vcpus.
1625 * The worst case for a remote vcpu to update its kvmclock
1626 * is then bounded by maximum nohz sleep latency.
1627 */
1628
1629static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1630{
1631 int i;
1632 struct kvm *kvm = v->kvm;
1633 struct kvm_vcpu *vcpu;
1634
1635 kvm_for_each_vcpu(i, vcpu, kvm) {
1636 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1637 kvm_vcpu_kick(vcpu);
1638 }
1639}
1640
9ba075a6
AK		 1641static bool msr_mtrr_valid(unsigned msr)
1642{
1643 switch (msr) {
1644 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1645 case MSR_MTRRfix64K_00000:
1646 case MSR_MTRRfix16K_80000:
1647 case MSR_MTRRfix16K_A0000:
1648 case MSR_MTRRfix4K_C0000:
1649 case MSR_MTRRfix4K_C8000:
1650 case MSR_MTRRfix4K_D0000:
1651 case MSR_MTRRfix4K_D8000:
1652 case MSR_MTRRfix4K_E0000:
1653 case MSR_MTRRfix4K_E8000:
1654 case MSR_MTRRfix4K_F0000:
1655 case MSR_MTRRfix4K_F8000:
1656 case MSR_MTRRdefType:
1657 case MSR_IA32_CR_PAT:
1658 return true;
1659 case 0x2f8:
1660 return true;
1661 }
1662 return false;
1663}
1664
d6289b93
MT		 1665static bool valid_pat_type(unsigned t)
1666{
1667 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1668}
1669
1670static bool valid_mtrr_type(unsigned t)
1671{
1672 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1673}
1674
1675static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1676{
1677 int i;
1678
1679 if (!msr_mtrr_valid(msr))
1680 return false;
1681
1682 if (msr == MSR_IA32_CR_PAT) {
1683 for (i = 0; i < 8; i++)
1684 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1685 return false;
1686 return true;
1687 } else if (msr == MSR_MTRRdefType) {
1688 if (data & ~0xcff)
1689 return false;
1690 return valid_mtrr_type(data & 0xff);
1691 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1692 for (i = 0; i < 8 ; i++)
1693 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1694 return false;
1695 return true;
1696 }
1697
1698 /* variable MTRRs */
1699 return valid_mtrr_type(data & 0xff);
1700}
1701
9ba075a6
AK		 1702static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1703{
0bed3b56
SY		 1704 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1705
d6289b93 1706 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1707 return 1;
1708
0bed3b56
SY		 1709 if (msr == MSR_MTRRdefType) {
1710 vcpu->arch.mtrr_state.def_type = data;
1711 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1712 } else if (msr == MSR_MTRRfix64K_00000)
1713 p[0] = data;
1714 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1715 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1716 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1717 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1718 else if (msr == MSR_IA32_CR_PAT)
1719 vcpu->arch.pat = data;
1720 else { /* Variable MTRRs */
1721 int idx, is_mtrr_mask;
1722 u64 *pt;
1723
1724 idx = (msr - 0x200) / 2;
1725 is_mtrr_mask = msr - 0x200 - 2 * idx;
1726 if (!is_mtrr_mask)
1727 pt =
1728 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1729 else
1730 pt =
1731 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1732 *pt = data;
1733 }
1734
1735 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1736 return 0;
1737}
15c4a640 1738
890ca9ae 1739static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1740{
890ca9ae
HY		 1741 u64 mcg_cap = vcpu->arch.mcg_cap;
1742 unsigned bank_num = mcg_cap & 0xff;
1743
15c4a640 1744 switch (msr) {
15c4a640 1745 case MSR_IA32_MCG_STATUS:
890ca9ae 1746 vcpu->arch.mcg_status = data;
15c4a640 1747 break;
c7ac679c 1748 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1749 if (!(mcg_cap & MCG_CTL_P))
1750 return 1;
1751 if (data != 0 && data != ~(u64)0)
1752 return -1;
1753 vcpu->arch.mcg_ctl = data;
1754 break;
1755 default:
1756 if (msr >= MSR_IA32_MC0_CTL &&
1757 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1758 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1759 /* only 0 or all 1s can be written to IA32_MCi_CTL
1760 * some Linux kernels though clear bit 10 in bank 4 to
1761 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1762 * this to avoid an uncatched #GP in the guest
1763 */
890ca9ae 1764 if ((offset & 0x3) == 0 &&
114be429 1765 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1766 return -1;
1767 vcpu->arch.mce_banks[offset] = data;
1768 break;
1769 }
1770 return 1;
1771 }
1772 return 0;
1773}
1774
ffde22ac
ES		 1775static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1776{
1777 struct kvm *kvm = vcpu->kvm;
1778 int lm = is_long_mode(vcpu);
1779 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1780 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1781 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1782 : kvm->arch.xen_hvm_config.blob_size_32;
1783 u32 page_num = data & ~PAGE_MASK;
1784 u64 page_addr = data & PAGE_MASK;
1785 u8 *page;
1786 int r;
1787
1788 r = -E2BIG;
1789 if (page_num >= blob_size)
1790 goto out;
1791 r = -ENOMEM;
ff5c2c03
SL		 1792 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1793 if (IS_ERR(page)) {
1794 r = PTR_ERR(page);
ffde22ac 1795 goto out;
ff5c2c03 1796 }
ffde22ac
ES		 1797 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1798 goto out_free;
1799 r = 0;
1800out_free:
1801 kfree(page);
1802out:
1803 return r;
1804}
1805
55cd8e5a
GN		 1806static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1807{
1808 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1809}
1810
1811static bool kvm_hv_msr_partition_wide(u32 msr)
1812{
1813 bool r = false;
1814 switch (msr) {
1815 case HV_X64_MSR_GUEST_OS_ID:
1816 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1817 case HV_X64_MSR_REFERENCE_TSC:
1818 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1819 r = true;
1820 break;
1821 }
1822
1823 return r;
1824}
1825
1826static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1827{
1828 struct kvm *kvm = vcpu->kvm;
1829
1830 switch (msr) {
1831 case HV_X64_MSR_GUEST_OS_ID:
1832 kvm->arch.hv_guest_os_id = data;
1833 /* setting guest os id to zero disables hypercall page */
1834 if (!kvm->arch.hv_guest_os_id)
1835 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1836 break;
1837 case HV_X64_MSR_HYPERCALL: {
1838 u64 gfn;
1839 unsigned long addr;
1840 u8 instructions[4];
1841
1842 /* if guest os id is not set hypercall should remain disabled */
1843 if (!kvm->arch.hv_guest_os_id)
1844 break;
1845 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1846 kvm->arch.hv_hypercall = data;
1847 break;
1848 }
1849 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1850 addr = gfn_to_hva(kvm, gfn);
1851 if (kvm_is_error_hva(addr))
1852 return 1;
1853 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1854 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1855 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1856 return 1;
1857 kvm->arch.hv_hypercall = data;
b94b64c9 1858 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1859 break;
1860 }
e984097b
VR		 1861 case HV_X64_MSR_REFERENCE_TSC: {
1862 u64 gfn;
1863 HV_REFERENCE_TSC_PAGE tsc_ref;
1864 memset(&tsc_ref, 0, sizeof(tsc_ref));
1865 kvm->arch.hv_tsc_page = data;
1866 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1867 break;
1868 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1869 if (kvm_write_guest(kvm, data,
1870 &tsc_ref, sizeof(tsc_ref)))
1871 return 1;
1872 mark_page_dirty(kvm, gfn);
1873 break;
1874 }
55cd8e5a 1875 default:
a737f256
CD		 1876 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1877 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1878 return 1;
1879 }
1880 return 0;
1881}
1882
1883static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1884{
10388a07
GN		 1885 switch (msr) {
1886 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1887 u64 gfn;
10388a07 1888 unsigned long addr;
55cd8e5a 1889
10388a07
GN		 1890 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1891 vcpu->arch.hv_vapic = data;
1892 break;
1893 }
b3af1e88
VR		 1894 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1895 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1896 if (kvm_is_error_hva(addr))
1897 return 1;
8b0cedff 1898 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1899 return 1;
1900 vcpu->arch.hv_vapic = data;
b3af1e88 1901 mark_page_dirty(vcpu->kvm, gfn);
10388a07
GN		 1902 break;
1903 }
1904 case HV_X64_MSR_EOI:
1905 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1906 case HV_X64_MSR_ICR:
1907 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1908 case HV_X64_MSR_TPR:
1909 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1910 default:
a737f256
CD		 1911 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1912 "data 0x%llx\n", msr, data);
10388a07
GN		 1913 return 1;
1914 }
1915
1916 return 0;
55cd8e5a
GN		 1917}
1918
344d9588
GN		 1919static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1920{
1921 gpa_t gpa = data & ~0x3f;
1922
4a969980 1923 /* Bits 2:5 are reserved, Should be zero */
6adba527 1924 if (data & 0x3c)
344d9588
GN		 1925 return 1;
1926
1927 vcpu->arch.apf.msr_val = data;
1928
1929 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1930 kvm_clear_async_pf_completion_queue(vcpu);
1931 kvm_async_pf_hash_reset(vcpu);
1932 return 0;
1933 }
1934
8f964525
AH		 1935 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1936 sizeof(u32)))
344d9588
GN		 1937 return 1;
1938
6adba527 1939 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1940 kvm_async_pf_wakeup_all(vcpu);
1941 return 0;
1942}
1943
12f9a48f
GC		 1944static void kvmclock_reset(struct kvm_vcpu *vcpu)
1945{
0b79459b 1946 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1947}
1948
c9aaa895
GC		 1949static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1950{
1951 u64 delta;
1952
1953 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1954 return;
1955
1956 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1957 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1958 vcpu->arch.st.accum_steal = delta;
1959}
1960
1961static void record_steal_time(struct kvm_vcpu *vcpu)
1962{
1963 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1964 return;
1965
1966 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1967 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1968 return;
1969
1970 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1971 vcpu->arch.st.steal.version += 2;
1972 vcpu->arch.st.accum_steal = 0;
1973
1974 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1975 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1976}
1977
8fe8ab46 1978int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1979{
5753785f 1980 bool pr = false;
8fe8ab46
WA		 1981 u32 msr = msr_info->index;
1982 u64 data = msr_info->data;
5753785f 1983
15c4a640 1984 switch (msr) {
2e32b719
BP		 1985 case MSR_AMD64_NB_CFG:
1986 case MSR_IA32_UCODE_REV:
1987 case MSR_IA32_UCODE_WRITE:
1988 case MSR_VM_HSAVE_PA:
1989 case MSR_AMD64_PATCH_LOADER:
1990 case MSR_AMD64_BU_CFG2:
1991 break;
1992
15c4a640 1993 case MSR_EFER:
b69e8cae 1994 return set_efer(vcpu, data);
8f1589d9
AP		 1995 case MSR_K7_HWCR:
1996 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1997 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1998 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1999 if (data != 0) {
a737f256
CD		 2000 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2001 data);
8f1589d9
AP		 2002 return 1;
2003 }
15c4a640 2004 break;
f7c6d140
AP		 2005 case MSR_FAM10H_MMIO_CONF_BASE:
2006 if (data != 0) {
a737f256
CD		 2007 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2008 "0x%llx\n", data);
f7c6d140
AP		 2009 return 1;
2010 }
15c4a640 2011 break;
b5e2fec0
AG		 2012 case MSR_IA32_DEBUGCTLMSR:
2013 if (!data) {
2014 /* We support the non-activated case already */
2015 break;
2016 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2017 /* Values other than LBR and BTF are vendor-specific,
2018 thus reserved and should throw a #GP */
2019 return 1;
2020 }
a737f256
CD		 2021 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2022 __func__, data);
b5e2fec0 2023 break;
9ba075a6
AK		 2024 case 0x200 ... 0x2ff:
2025 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2026 case MSR_IA32_APICBASE:
58cb628d 2027 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2028 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2029 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2030 case MSR_IA32_TSCDEADLINE:
2031 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2032 break;
ba904635
WA		 2033 case MSR_IA32_TSC_ADJUST:
2034 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2035 if (!msr_info->host_initiated) {
2036 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2037 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2038 }
2039 vcpu->arch.ia32_tsc_adjust_msr = data;
2040 }
2041 break;
15c4a640 2042 case MSR_IA32_MISC_ENABLE:
ad312c7c 2043 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2044 break;
11c6bffa 2045 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2046 case MSR_KVM_WALL_CLOCK:
2047 vcpu->kvm->arch.wall_clock = data;
2048 kvm_write_wall_clock(vcpu->kvm, data);
2049 break;
11c6bffa 2050 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2051 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2052 u64 gpa_offset;
12f9a48f 2053 kvmclock_reset(vcpu);
18068523
GOC		 2054
2055 vcpu->arch.time = data;
0061d53d 2056 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2057
2058 /* we verify if the enable bit is set... */
2059 if (!(data & 1))
2060 break;
2061
0b79459b 2062 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2063
0b79459b 2064 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2065 &vcpu->arch.pv_time, data & ~1ULL,
2066 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2067 vcpu->arch.pv_time_enabled = false;
2068 else
2069 vcpu->arch.pv_time_enabled = true;
32cad84f 2070
18068523
GOC		 2071 break;
2072 }
344d9588
GN		 2073 case MSR_KVM_ASYNC_PF_EN:
2074 if (kvm_pv_enable_async_pf(vcpu, data))
2075 return 1;
2076 break;
c9aaa895
GC		 2077 case MSR_KVM_STEAL_TIME:
2078
2079 if (unlikely(!sched_info_on()))
2080 return 1;
2081
2082 if (data & KVM_STEAL_RESERVED_MASK)
2083 return 1;
2084
2085 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2086 data & KVM_STEAL_VALID_BITS,
2087 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2088 return 1;
2089
2090 vcpu->arch.st.msr_val = data;
2091
2092 if (!(data & KVM_MSR_ENABLED))
2093 break;
2094
2095 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2096
2097 preempt_disable();
2098 accumulate_steal_time(vcpu);
2099 preempt_enable();
2100
2101 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2102
2103 break;
ae7a2a3f
MT		 2104 case MSR_KVM_PV_EOI_EN:
2105 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2106 return 1;
2107 break;
c9aaa895 2108
890ca9ae
HY		 2109 case MSR_IA32_MCG_CTL:
2110 case MSR_IA32_MCG_STATUS:
2111 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2112 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2113
2114 /* Performance counters are not protected by a CPUID bit,
2115 * so we should check all of them in the generic path for the sake of
2116 * cross vendor migration.
2117 * Writing a zero into the event select MSRs disables them,
2118 * which we perfectly emulate ;-). Any other value should be at least
2119 * reported, some guests depend on them.
2120 */
71db6023
AP		 2121 case MSR_K7_EVNTSEL0:
2122 case MSR_K7_EVNTSEL1:
2123 case MSR_K7_EVNTSEL2:
2124 case MSR_K7_EVNTSEL3:
2125 if (data != 0)
a737f256
CD		 2126 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2127 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2128 break;
2129 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2130 * so we ignore writes to make it happy.
2131 */
71db6023
AP		 2132 case MSR_K7_PERFCTR0:
2133 case MSR_K7_PERFCTR1:
2134 case MSR_K7_PERFCTR2:
2135 case MSR_K7_PERFCTR3:
a737f256
CD		 2136 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2137 "0x%x data 0x%llx\n", msr, data);
71db6023 2138 break;
5753785f
GN		 2139 case MSR_P6_PERFCTR0:
2140 case MSR_P6_PERFCTR1:
2141 pr = true;
2142 case MSR_P6_EVNTSEL0:
2143 case MSR_P6_EVNTSEL1:
2144 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2145 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2146
2147 if (pr || data != 0)
a737f256
CD		 2148 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2149 "0x%x data 0x%llx\n", msr, data);
5753785f 2150 break;
84e0cefa
JS		 2151 case MSR_K7_CLK_CTL:
2152 /*
2153 * Ignore all writes to this no longer documented MSR.
2154 * Writes are only relevant for old K7 processors,
2155 * all pre-dating SVM, but a recommended workaround from
4a969980 2156 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2157 * affected processor models on the command line, hence
2158 * the need to ignore the workaround.
2159 */
2160 break;
55cd8e5a
GN		 2161 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2162 if (kvm_hv_msr_partition_wide(msr)) {
2163 int r;
2164 mutex_lock(&vcpu->kvm->lock);
2165 r = set_msr_hyperv_pw(vcpu, msr, data);
2166 mutex_unlock(&vcpu->kvm->lock);
2167 return r;
2168 } else
2169 return set_msr_hyperv(vcpu, msr, data);
2170 break;
91c9c3ed 2171 case MSR_IA32_BBL_CR_CTL3:
2172 /* Drop writes to this legacy MSR -- see rdmsr
2173 * counterpart for further detail.
2174 */
a737f256 2175 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2176 break;
2b036c6b
BO		 2177 case MSR_AMD64_OSVW_ID_LENGTH:
2178 if (!guest_cpuid_has_osvw(vcpu))
2179 return 1;
2180 vcpu->arch.osvw.length = data;
2181 break;
2182 case MSR_AMD64_OSVW_STATUS:
2183 if (!guest_cpuid_has_osvw(vcpu))
2184 return 1;
2185 vcpu->arch.osvw.status = data;
2186 break;
15c4a640 2187 default:
ffde22ac
ES		 2188 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2189 return xen_hvm_config(vcpu, data);
f5132b01 2190 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2191 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2192 if (!ignore_msrs) {
a737f256
CD		 2193 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2194 msr, data);
ed85c068
AP		 2195 return 1;
2196 } else {
a737f256
CD		 2197 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2198 msr, data);
ed85c068
AP		 2199 break;
2200 }
15c4a640
CO		 2201 }
2202 return 0;
2203}
2204EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2205
2206
2207/*
2208 * Reads an msr value (of 'msr_index') into 'pdata'.
2209 * Returns 0 on success, non-0 otherwise.
2210 * Assumes vcpu_load() was already called.
2211 */
2212int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2213{
2214 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2215}
2216
9ba075a6
AK		 2217static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2218{
0bed3b56
SY		 2219 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2220
9ba075a6
AK		 2221 if (!msr_mtrr_valid(msr))
2222 return 1;
2223
0bed3b56
SY		 2224 if (msr == MSR_MTRRdefType)
2225 *pdata = vcpu->arch.mtrr_state.def_type +
2226 (vcpu->arch.mtrr_state.enabled << 10);
2227 else if (msr == MSR_MTRRfix64K_00000)
2228 *pdata = p[0];
2229 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2230 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2231 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2232 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2233 else if (msr == MSR_IA32_CR_PAT)
2234 *pdata = vcpu->arch.pat;
2235 else { /* Variable MTRRs */
2236 int idx, is_mtrr_mask;
2237 u64 *pt;
2238
2239 idx = (msr - 0x200) / 2;
2240 is_mtrr_mask = msr - 0x200 - 2 * idx;
2241 if (!is_mtrr_mask)
2242 pt =
2243 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2244 else
2245 pt =
2246 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2247 *pdata = *pt;
2248 }
2249
9ba075a6
AK		 2250 return 0;
2251}
2252
890ca9ae 2253static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2254{
2255 u64 data;
890ca9ae
HY		 2256 u64 mcg_cap = vcpu->arch.mcg_cap;
2257 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2258
2259 switch (msr) {
15c4a640
CO		 2260 case MSR_IA32_P5_MC_ADDR:
2261 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2262 data = 0;
2263 break;
15c4a640 2264 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2265 data = vcpu->arch.mcg_cap;
2266 break;
c7ac679c 2267 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2268 if (!(mcg_cap & MCG_CTL_P))
2269 return 1;
2270 data = vcpu->arch.mcg_ctl;
2271 break;
2272 case MSR_IA32_MCG_STATUS:
2273 data = vcpu->arch.mcg_status;
2274 break;
2275 default:
2276 if (msr >= MSR_IA32_MC0_CTL &&
2277 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2278 u32 offset = msr - MSR_IA32_MC0_CTL;
2279 data = vcpu->arch.mce_banks[offset];
2280 break;
2281 }
2282 return 1;
2283 }
2284 *pdata = data;
2285 return 0;
2286}
2287
55cd8e5a
GN		 2288static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2289{
2290 u64 data = 0;
2291 struct kvm *kvm = vcpu->kvm;
2292
2293 switch (msr) {
2294 case HV_X64_MSR_GUEST_OS_ID:
2295 data = kvm->arch.hv_guest_os_id;
2296 break;
2297 case HV_X64_MSR_HYPERCALL:
2298 data = kvm->arch.hv_hypercall;
2299 break;
e984097b
VR		 2300 case HV_X64_MSR_TIME_REF_COUNT: {
2301 data =
2302 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2303 break;
2304 }
2305 case HV_X64_MSR_REFERENCE_TSC:
2306 data = kvm->arch.hv_tsc_page;
2307 break;
55cd8e5a 2308 default:
a737f256 2309 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2310 return 1;
2311 }
2312
2313 *pdata = data;
2314 return 0;
2315}
2316
2317static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2318{
2319 u64 data = 0;
2320
2321 switch (msr) {
2322 case HV_X64_MSR_VP_INDEX: {
2323 int r;
2324 struct kvm_vcpu *v;
2325 kvm_for_each_vcpu(r, v, vcpu->kvm)
2326 if (v == vcpu)
2327 data = r;
2328 break;
2329 }
10388a07
GN		 2330 case HV_X64_MSR_EOI:
2331 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2332 case HV_X64_MSR_ICR:
2333 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2334 case HV_X64_MSR_TPR:
2335 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2336 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2337 data = vcpu->arch.hv_vapic;
2338 break;
55cd8e5a 2339 default:
a737f256 2340 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2341 return 1;
2342 }
2343 *pdata = data;
2344 return 0;
2345}
2346
890ca9ae
HY		 2347int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2348{
2349 u64 data;
2350
2351 switch (msr) {
890ca9ae 2352 case MSR_IA32_PLATFORM_ID:
15c4a640 2353 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2354 case MSR_IA32_DEBUGCTLMSR:
2355 case MSR_IA32_LASTBRANCHFROMIP:
2356 case MSR_IA32_LASTBRANCHTOIP:
2357 case MSR_IA32_LASTINTFROMIP:
2358 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2359 case MSR_K8_SYSCFG:
2360 case MSR_K7_HWCR:
61a6bd67 2361 case MSR_VM_HSAVE_PA:
9e699624 2362 case MSR_K7_EVNTSEL0:
1f3ee616 2363 case MSR_K7_PERFCTR0:
1fdbd48c 2364 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2365 case MSR_AMD64_NB_CFG:
f7c6d140 2366 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2367 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2368 data = 0;
2369 break;
5753785f
GN		 2370 case MSR_P6_PERFCTR0:
2371 case MSR_P6_PERFCTR1:
2372 case MSR_P6_EVNTSEL0:
2373 case MSR_P6_EVNTSEL1:
2374 if (kvm_pmu_msr(vcpu, msr))
2375 return kvm_pmu_get_msr(vcpu, msr, pdata);
2376 data = 0;
2377 break;
742bc670
MT		 2378 case MSR_IA32_UCODE_REV:
2379 data = 0x100000000ULL;
2380 break;
9ba075a6
AK		 2381 case MSR_MTRRcap:
2382 data = 0x500 | KVM_NR_VAR_MTRR;
2383 break;
2384 case 0x200 ... 0x2ff:
2385 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2386 case 0xcd: /* fsb frequency */
2387 data = 3;
2388 break;
7b914098
JS		 2389 /*
2390 * MSR_EBC_FREQUENCY_ID
2391 * Conservative value valid for even the basic CPU models.
2392 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2393 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2394 * and 266MHz for model 3, or 4. Set Core Clock
2395 * Frequency to System Bus Frequency Ratio to 1 (bits
2396 * 31:24) even though these are only valid for CPU
2397 * models > 2, however guests may end up dividing or
2398 * multiplying by zero otherwise.
2399 */
2400 case MSR_EBC_FREQUENCY_ID:
2401 data = 1 << 24;
2402 break;
15c4a640
CO		 2403 case MSR_IA32_APICBASE:
2404 data = kvm_get_apic_base(vcpu);
2405 break;
0105d1a5
GN		 2406 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2407 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2408 break;
a3e06bbe
LJ		 2409 case MSR_IA32_TSCDEADLINE:
2410 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2411 break;
ba904635
WA		 2412 case MSR_IA32_TSC_ADJUST:
2413 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2414 break;
15c4a640 2415 case MSR_IA32_MISC_ENABLE:
ad312c7c 2416 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2417 break;
847f0ad8
AG		 2418 case MSR_IA32_PERF_STATUS:
2419 /* TSC increment by tick */
2420 data = 1000ULL;
2421 /* CPU multiplier */
2422 data |= (((uint64_t)4ULL) << 40);
2423 break;
15c4a640 2424 case MSR_EFER:
f6801dff 2425 data = vcpu->arch.efer;
15c4a640 2426 break;
18068523 2427 case MSR_KVM_WALL_CLOCK:
11c6bffa 2428 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2429 data = vcpu->kvm->arch.wall_clock;
2430 break;
2431 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2432 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2433 data = vcpu->arch.time;
2434 break;
344d9588
GN		 2435 case MSR_KVM_ASYNC_PF_EN:
2436 data = vcpu->arch.apf.msr_val;
2437 break;
c9aaa895
GC		 2438 case MSR_KVM_STEAL_TIME:
2439 data = vcpu->arch.st.msr_val;
2440 break;
1d92128f
MT		 2441 case MSR_KVM_PV_EOI_EN:
2442 data = vcpu->arch.pv_eoi.msr_val;
2443 break;
890ca9ae
HY		 2444 case MSR_IA32_P5_MC_ADDR:
2445 case MSR_IA32_P5_MC_TYPE:
2446 case MSR_IA32_MCG_CAP:
2447 case MSR_IA32_MCG_CTL:
2448 case MSR_IA32_MCG_STATUS:
2449 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2450 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2451 case MSR_K7_CLK_CTL:
2452 /*
2453 * Provide expected ramp-up count for K7. All other
2454 * are set to zero, indicating minimum divisors for
2455 * every field.
2456 *
2457 * This prevents guest kernels on AMD host with CPU
2458 * type 6, model 8 and higher from exploding due to
2459 * the rdmsr failing.
2460 */
2461 data = 0x20000000;
2462 break;
55cd8e5a
GN		 2463 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2464 if (kvm_hv_msr_partition_wide(msr)) {
2465 int r;
2466 mutex_lock(&vcpu->kvm->lock);
2467 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2468 mutex_unlock(&vcpu->kvm->lock);
2469 return r;
2470 } else
2471 return get_msr_hyperv(vcpu, msr, pdata);
2472 break;
91c9c3ed 2473 case MSR_IA32_BBL_CR_CTL3:
2474 /* This legacy MSR exists but isn't fully documented in current
2475 * silicon. It is however accessed by winxp in very narrow
2476 * scenarios where it sets bit #19, itself documented as
2477 * a "reserved" bit. Best effort attempt to source coherent
2478 * read data here should the balance of the register be
2479 * interpreted by the guest:
2480 *
2481 * L2 cache control register 3: 64GB range, 256KB size,
2482 * enabled, latency 0x1, configured
2483 */
2484 data = 0xbe702111;
2485 break;
2b036c6b
BO		 2486 case MSR_AMD64_OSVW_ID_LENGTH:
2487 if (!guest_cpuid_has_osvw(vcpu))
2488 return 1;
2489 data = vcpu->arch.osvw.length;
2490 break;
2491 case MSR_AMD64_OSVW_STATUS:
2492 if (!guest_cpuid_has_osvw(vcpu))
2493 return 1;
2494 data = vcpu->arch.osvw.status;
2495 break;
15c4a640 2496 default:
f5132b01
GN		 2497 if (kvm_pmu_msr(vcpu, msr))
2498 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2499 if (!ignore_msrs) {
a737f256 2500 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2501 return 1;
2502 } else {
a737f256 2503 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2504 data = 0;
2505 }
2506 break;
15c4a640
CO		 2507 }
2508 *pdata = data;
2509 return 0;
2510}
2511EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2512
313a3dc7
CO		 2513/*
2514 * Read or write a bunch of msrs. All parameters are kernel addresses.
2515 *
2516 * @return number of msrs set successfully.
2517 */
2518static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2519 struct kvm_msr_entry *entries,
2520 int (*do_msr)(struct kvm_vcpu *vcpu,
2521 unsigned index, u64 *data))
2522{
f656ce01 2523 int i, idx;
313a3dc7 2524
f656ce01 2525 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2526 for (i = 0; i < msrs->nmsrs; ++i)
2527 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2528 break;
f656ce01 2529 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2530
313a3dc7
CO		 2531 return i;
2532}
2533
2534/*
2535 * Read or write a bunch of msrs. Parameters are user addresses.
2536 *
2537 * @return number of msrs set successfully.
2538 */
2539static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2540 int (*do_msr)(struct kvm_vcpu *vcpu,
2541 unsigned index, u64 *data),
2542 int writeback)
2543{
2544 struct kvm_msrs msrs;
2545 struct kvm_msr_entry *entries;
2546 int r, n;
2547 unsigned size;
2548
2549 r = -EFAULT;
2550 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2551 goto out;
2552
2553 r = -E2BIG;
2554 if (msrs.nmsrs >= MAX_IO_MSRS)
2555 goto out;
2556
313a3dc7 2557 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2558 entries = memdup_user(user_msrs->entries, size);
2559 if (IS_ERR(entries)) {
2560 r = PTR_ERR(entries);
313a3dc7 2561 goto out;
ff5c2c03 2562 }
313a3dc7
CO		 2563
2564 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2565 if (r < 0)
2566 goto out_free;
2567
2568 r = -EFAULT;
2569 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2570 goto out_free;
2571
2572 r = n;
2573
2574out_free:
7a73c028 2575 kfree(entries);
313a3dc7
CO		 2576out:
2577 return r;
2578}
2579
018d00d2
ZX		 2580int kvm_dev_ioctl_check_extension(long ext)
2581{
2582 int r;
2583
2584 switch (ext) {
2585 case KVM_CAP_IRQCHIP:
2586 case KVM_CAP_HLT:
2587 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2588 case KVM_CAP_SET_TSS_ADDR:
07716717 2589 case KVM_CAP_EXT_CPUID:
9c15bb1d 2590 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2591 case KVM_CAP_CLOCKSOURCE:
7837699f 2592 case KVM_CAP_PIT:
a28e4f5a 2593 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2594 case KVM_CAP_MP_STATE:
ed848624 2595 case KVM_CAP_SYNC_MMU:
a355c85c 2596 case KVM_CAP_USER_NMI:
52d939a0 2597 case KVM_CAP_REINJECT_CONTROL:
4925663a 2598 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2599 case KVM_CAP_IRQFD:
d34e6b17 2600 case KVM_CAP_IOEVENTFD:
c5ff41ce 2601 case KVM_CAP_PIT2:
e9f42757 2602 case KVM_CAP_PIT_STATE2:
b927a3ce 2603 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2604 case KVM_CAP_XEN_HVM:
afbcf7ab 2605 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2606 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2607 case KVM_CAP_HYPERV:
10388a07 2608 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2609 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2610 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2611 case KVM_CAP_DEBUGREGS:
d2be1651 2612 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2613 case KVM_CAP_XSAVE:
344d9588 2614 case KVM_CAP_ASYNC_PF:
92a1f12d 2615 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2616 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2617 case KVM_CAP_READONLY_MEM:
5f66b620 2618 case KVM_CAP_HYPERV_TIME:
2a5bab10
AW		 2619#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2620 case KVM_CAP_ASSIGN_DEV_IRQ:
2621 case KVM_CAP_PCI_2_3:
2622#endif
018d00d2
ZX		 2623 r = 1;
2624 break;
542472b5
LV		 2625 case KVM_CAP_COALESCED_MMIO:
2626 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2627 break;
774ead3a
AK		 2628 case KVM_CAP_VAPIC:
2629 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2630 break;
f725230a 2631 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2632 r = KVM_SOFT_MAX_VCPUS;
2633 break;
2634 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2635 r = KVM_MAX_VCPUS;
2636 break;
a988b910 2637 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2638 r = KVM_USER_MEM_SLOTS;
a988b910 2639 break;
a68a6a72
MT		 2640 case KVM_CAP_PV_MMU: /* obsolete */
2641 r = 0;
2f333bcb 2642 break;
4cee4b72 2643#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2644 case KVM_CAP_IOMMU:
a1b60c1c 2645 r = iommu_present(&pci_bus_type);
62c476c7 2646 break;
4cee4b72 2647#endif
890ca9ae
HY		 2648 case KVM_CAP_MCE:
2649 r = KVM_MAX_MCE_BANKS;
2650 break;
2d5b5a66
SY		 2651 case KVM_CAP_XCRS:
2652 r = cpu_has_xsave;
2653 break;
92a1f12d
JR		 2654 case KVM_CAP_TSC_CONTROL:
2655 r = kvm_has_tsc_control;
2656 break;
4d25a066
JK		 2657 case KVM_CAP_TSC_DEADLINE_TIMER:
2658 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2659 break;
018d00d2
ZX		 2660 default:
2661 r = 0;
2662 break;
2663 }
2664 return r;
2665
2666}
2667
043405e1
CO		 2668long kvm_arch_dev_ioctl(struct file *filp,
2669 unsigned int ioctl, unsigned long arg)
2670{
2671 void __user *argp = (void __user *)arg;
2672 long r;
2673
2674 switch (ioctl) {
2675 case KVM_GET_MSR_INDEX_LIST: {
2676 struct kvm_msr_list __user *user_msr_list = argp;
2677 struct kvm_msr_list msr_list;
2678 unsigned n;
2679
2680 r = -EFAULT;
2681 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2682 goto out;
2683 n = msr_list.nmsrs;
2684 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2685 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2686 goto out;
2687 r = -E2BIG;
e125e7b6 2688 if (n < msr_list.nmsrs)
043405e1
CO		 2689 goto out;
2690 r = -EFAULT;
2691 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2692 num_msrs_to_save * sizeof(u32)))
2693 goto out;
e125e7b6 2694 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2695 &emulated_msrs,
2696 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2697 goto out;
2698 r = 0;
2699 break;
2700 }
9c15bb1d
BP		 2701 case KVM_GET_SUPPORTED_CPUID:
2702 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2703 struct kvm_cpuid2 __user *cpuid_arg = argp;
2704 struct kvm_cpuid2 cpuid;
2705
2706 r = -EFAULT;
2707 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2708 goto out;
9c15bb1d
BP		 2709
2710 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2711 ioctl);
674eea0f
AK		 2712 if (r)
2713 goto out;
2714
2715 r = -EFAULT;
2716 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2717 goto out;
2718 r = 0;
2719 break;
2720 }
890ca9ae
HY		 2721 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2722 u64 mce_cap;
2723
2724 mce_cap = KVM_MCE_CAP_SUPPORTED;
2725 r = -EFAULT;
2726 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2727 goto out;
2728 r = 0;
2729 break;
2730 }
043405e1
CO		 2731 default:
2732 r = -EINVAL;
2733 }
2734out:
2735 return r;
2736}
2737
f5f48ee1
SY		 2738static void wbinvd_ipi(void *garbage)
2739{
2740 wbinvd();
2741}
2742
2743static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2744{
e0f0bbc5 2745 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2746}
2747
313a3dc7
CO		 2748void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2749{
f5f48ee1
SY		 2750 /* Address WBINVD may be executed by guest */
2751 if (need_emulate_wbinvd(vcpu)) {
2752 if (kvm_x86_ops->has_wbinvd_exit())
2753 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2754 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2755 smp_call_function_single(vcpu->cpu,
2756 wbinvd_ipi, NULL, 1);
2757 }
2758
313a3dc7 2759 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2760
0dd6a6ed
ZA		 2761 /* Apply any externally detected TSC adjustments (due to suspend) */
2762 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2763 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2764 vcpu->arch.tsc_offset_adjustment = 0;
2765 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2766 }
8f6055cb 2767
48434c20 2768 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2769 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2770 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2771 if (tsc_delta < 0)
2772 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2773 if (check_tsc_unstable()) {
b183aa58
ZA		 2774 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2775 vcpu->arch.last_guest_tsc);
2776 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2777 vcpu->arch.tsc_catchup = 1;
c285545f 2778 }
d98d07ca
MT		 2779 /*
2780 * On a host with synchronized TSC, there is no need to update
2781 * kvmclock on vcpu->cpu migration
2782 */
2783 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2784 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2785 if (vcpu->cpu != cpu)
2786 kvm_migrate_timers(vcpu);
e48672fa 2787 vcpu->cpu = cpu;
6b7d7e76 2788 }
c9aaa895
GC		 2789
2790 accumulate_steal_time(vcpu);
2791 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2792}
2793
2794void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2795{
02daab21 2796 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2797 kvm_put_guest_fpu(vcpu);
6f526ec5 2798 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2799}
2800
313a3dc7
CO		 2801static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2802 struct kvm_lapic_state *s)
2803{
5a71785d 2804 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2805 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2806
2807 return 0;
2808}
2809
2810static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2811 struct kvm_lapic_state *s)
2812{
64eb0620 2813 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2814 update_cr8_intercept(vcpu);
313a3dc7
CO		 2815
2816 return 0;
2817}
2818
f77bc6a4
ZX		 2819static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2820 struct kvm_interrupt *irq)
2821{
02cdb50f 2822 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2823 return -EINVAL;
2824 if (irqchip_in_kernel(vcpu->kvm))
2825 return -ENXIO;
f77bc6a4 2826
66fd3f7f 2827 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2828 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2829
f77bc6a4
ZX		 2830 return 0;
2831}
2832
c4abb7c9
JK		 2833static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2834{
c4abb7c9 2835 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2836
2837 return 0;
2838}
2839
b209749f
AK		 2840static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2841 struct kvm_tpr_access_ctl *tac)
2842{
2843 if (tac->flags)
2844 return -EINVAL;
2845 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2846 return 0;
2847}
2848
890ca9ae
HY		 2849static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2850 u64 mcg_cap)
2851{
2852 int r;
2853 unsigned bank_num = mcg_cap & 0xff, bank;
2854
2855 r = -EINVAL;
a9e38c3e 2856 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2857 goto out;
2858 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2859 goto out;
2860 r = 0;
2861 vcpu->arch.mcg_cap = mcg_cap;
2862 /* Init IA32_MCG_CTL to all 1s */
2863 if (mcg_cap & MCG_CTL_P)
2864 vcpu->arch.mcg_ctl = ~(u64)0;
2865 /* Init IA32_MCi_CTL to all 1s */
2866 for (bank = 0; bank < bank_num; bank++)
2867 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2868out:
2869 return r;
2870}
2871
2872static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2873 struct kvm_x86_mce *mce)
2874{
2875 u64 mcg_cap = vcpu->arch.mcg_cap;
2876 unsigned bank_num = mcg_cap & 0xff;
2877 u64 *banks = vcpu->arch.mce_banks;
2878
2879 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2880 return -EINVAL;
2881 /*
2882 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2883 * reporting is disabled
2884 */
2885 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2886 vcpu->arch.mcg_ctl != ~(u64)0)
2887 return 0;
2888 banks += 4 * mce->bank;
2889 /*
2890 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2891 * reporting is disabled for the bank
2892 */
2893 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2894 return 0;
2895 if (mce->status & MCI_STATUS_UC) {
2896 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2897 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2898 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2899 return 0;
2900 }
2901 if (banks[1] & MCI_STATUS_VAL)
2902 mce->status |= MCI_STATUS_OVER;
2903 banks[2] = mce->addr;
2904 banks[3] = mce->misc;
2905 vcpu->arch.mcg_status = mce->mcg_status;
2906 banks[1] = mce->status;
2907 kvm_queue_exception(vcpu, MC_VECTOR);
2908 } else if (!(banks[1] & MCI_STATUS_VAL)
2909 || !(banks[1] & MCI_STATUS_UC)) {
2910 if (banks[1] & MCI_STATUS_VAL)
2911 mce->status |= MCI_STATUS_OVER;
2912 banks[2] = mce->addr;
2913 banks[3] = mce->misc;
2914 banks[1] = mce->status;
2915 } else
2916 banks[1] |= MCI_STATUS_OVER;
2917 return 0;
2918}
2919
3cfc3092
JK		 2920static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2921 struct kvm_vcpu_events *events)
2922{
7460fb4a 2923 process_nmi(vcpu);
03b82a30
JK		 2924 events->exception.injected =
2925 vcpu->arch.exception.pending &&
2926 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2927 events->exception.nr = vcpu->arch.exception.nr;
2928 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2929 events->exception.pad = 0;
3cfc3092
JK		 2930 events->exception.error_code = vcpu->arch.exception.error_code;
2931
03b82a30
JK		 2932 events->interrupt.injected =
2933 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2934 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2935 events->interrupt.soft = 0;
48005f64
JK		 2936 events->interrupt.shadow =
2937 kvm_x86_ops->get_interrupt_shadow(vcpu,
2938 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2939
2940 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2941 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2942 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2943 events->nmi.pad = 0;
3cfc3092 2944
66450a21 2945 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2946
dab4b911 2947 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2948 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2949 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2950}
2951
2952static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2953 struct kvm_vcpu_events *events)
2954{
dab4b911 2955 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2956 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2957 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2958 return -EINVAL;
2959
7460fb4a 2960 process_nmi(vcpu);
3cfc3092
JK		 2961 vcpu->arch.exception.pending = events->exception.injected;
2962 vcpu->arch.exception.nr = events->exception.nr;
2963 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2964 vcpu->arch.exception.error_code = events->exception.error_code;
2965
2966 vcpu->arch.interrupt.pending = events->interrupt.injected;
2967 vcpu->arch.interrupt.nr = events->interrupt.nr;
2968 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2969 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2970 kvm_x86_ops->set_interrupt_shadow(vcpu,
2971 events->interrupt.shadow);
3cfc3092
JK		 2972
2973 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2974 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2975 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2976 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2977
66450a21
JK		 2978 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2979 kvm_vcpu_has_lapic(vcpu))
2980 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2981
3842d135
AK		 2982 kvm_make_request(KVM_REQ_EVENT, vcpu);
2983
3cfc3092
JK		 2984 return 0;
2985}
2986
a1efbe77
JK		 2987static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2988 struct kvm_debugregs *dbgregs)
2989{
73aaf249
JK		 2990 unsigned long val;
2991
a1efbe77 2992 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 2993 _kvm_get_dr(vcpu, 6, &val);
2994 dbgregs->dr6 = val;
a1efbe77
JK		 2995 dbgregs->dr7 = vcpu->arch.dr7;
2996 dbgregs->flags = 0;
97e69aa6 2997 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2998}
2999
3000static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3001 struct kvm_debugregs *dbgregs)
3002{
3003 if (dbgregs->flags)
3004 return -EINVAL;
3005
a1efbe77
JK		 3006 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3007 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3008 kvm_update_dr6(vcpu);
a1efbe77 3009 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3010 kvm_update_dr7(vcpu);
a1efbe77 3011
a1efbe77
JK		 3012 return 0;
3013}
3014
2d5b5a66
SY		 3015static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3016 struct kvm_xsave *guest_xsave)
3017{
4344ee98 3018 if (cpu_has_xsave) {
2d5b5a66
SY		 3019 memcpy(guest_xsave->region,
3020 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3021 vcpu->arch.guest_xstate_size);
3022 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3023 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3024 } else {
2d5b5a66
SY		 3025 memcpy(guest_xsave->region,
3026 &vcpu->arch.guest_fpu.state->fxsave,
3027 sizeof(struct i387_fxsave_struct));
3028 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3029 XSTATE_FPSSE;
3030 }
3031}
3032
3033static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3034 struct kvm_xsave *guest_xsave)
3035{
3036 u64 xstate_bv =
3037 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3038
d7876f1b
PB		 3039 if (cpu_has_xsave) {
3040 /*
3041 * Here we allow setting states that are not present in
3042 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3043 * with old userspace.
3044 */
3045 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3046 return -EINVAL;
3047 if (xstate_bv & ~host_xcr0)
3048 return -EINVAL;
2d5b5a66 3049 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3050 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3051 } else {
2d5b5a66
SY		 3052 if (xstate_bv & ~XSTATE_FPSSE)
3053 return -EINVAL;
3054 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3055 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3056 }
3057 return 0;
3058}
3059
3060static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3061 struct kvm_xcrs *guest_xcrs)
3062{
3063 if (!cpu_has_xsave) {
3064 guest_xcrs->nr_xcrs = 0;
3065 return;
3066 }
3067
3068 guest_xcrs->nr_xcrs = 1;
3069 guest_xcrs->flags = 0;
3070 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3071 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3072}
3073
3074static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3075 struct kvm_xcrs *guest_xcrs)
3076{
3077 int i, r = 0;
3078
3079 if (!cpu_has_xsave)
3080 return -EINVAL;
3081
3082 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3083 return -EINVAL;
3084
3085 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3086 /* Only support XCR0 currently */
c67a04cb 3087 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3088 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3089 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3090 break;
3091 }
3092 if (r)
3093 r = -EINVAL;
3094 return r;
3095}
3096
1c0b28c2
EM		 3097/*
3098 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3099 * stopped by the hypervisor. This function will be called from the host only.
3100 * EINVAL is returned when the host attempts to set the flag for a guest that
3101 * does not support pv clocks.
3102 */
3103static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3104{
0b79459b 3105 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3106 return -EINVAL;
51d59c6b 3107 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3108 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3109 return 0;
3110}
3111
313a3dc7
CO		 3112long kvm_arch_vcpu_ioctl(struct file *filp,
3113 unsigned int ioctl, unsigned long arg)
3114{
3115 struct kvm_vcpu *vcpu = filp->private_data;
3116 void __user *argp = (void __user *)arg;
3117 int r;
d1ac91d8
AK		 3118 union {
3119 struct kvm_lapic_state *lapic;
3120 struct kvm_xsave *xsave;
3121 struct kvm_xcrs *xcrs;
3122 void *buffer;
3123 } u;
3124
3125 u.buffer = NULL;
313a3dc7
CO		 3126 switch (ioctl) {
3127 case KVM_GET_LAPIC: {
2204ae3c
MT		 3128 r = -EINVAL;
3129 if (!vcpu->arch.apic)
3130 goto out;
d1ac91d8 3131 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3132
b772ff36 3133 r = -ENOMEM;
d1ac91d8 3134 if (!u.lapic)
b772ff36 3135 goto out;
d1ac91d8 3136 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3137 if (r)
3138 goto out;
3139 r = -EFAULT;
d1ac91d8 3140 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3141 goto out;
3142 r = 0;
3143 break;
3144 }
3145 case KVM_SET_LAPIC: {
2204ae3c
MT		 3146 r = -EINVAL;
3147 if (!vcpu->arch.apic)
3148 goto out;
ff5c2c03 3149 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3150 if (IS_ERR(u.lapic))
3151 return PTR_ERR(u.lapic);
ff5c2c03 3152
d1ac91d8 3153 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3154 break;
3155 }
f77bc6a4
ZX		 3156 case KVM_INTERRUPT: {
3157 struct kvm_interrupt irq;
3158
3159 r = -EFAULT;
3160 if (copy_from_user(&irq, argp, sizeof irq))
3161 goto out;
3162 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3163 break;
3164 }
c4abb7c9
JK		 3165 case KVM_NMI: {
3166 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3167 break;
3168 }
313a3dc7
CO		 3169 case KVM_SET_CPUID: {
3170 struct kvm_cpuid __user *cpuid_arg = argp;
3171 struct kvm_cpuid cpuid;
3172
3173 r = -EFAULT;
3174 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3175 goto out;
3176 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3177 break;
3178 }
07716717
DK		 3179 case KVM_SET_CPUID2: {
3180 struct kvm_cpuid2 __user *cpuid_arg = argp;
3181 struct kvm_cpuid2 cpuid;
3182
3183 r = -EFAULT;
3184 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3185 goto out;
3186 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3187 cpuid_arg->entries);
07716717
DK		 3188 break;
3189 }
3190 case KVM_GET_CPUID2: {
3191 struct kvm_cpuid2 __user *cpuid_arg = argp;
3192 struct kvm_cpuid2 cpuid;
3193
3194 r = -EFAULT;
3195 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3196 goto out;
3197 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3198 cpuid_arg->entries);
07716717
DK		 3199 if (r)
3200 goto out;
3201 r = -EFAULT;
3202 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3203 goto out;
3204 r = 0;
3205 break;
3206 }
313a3dc7
CO		 3207 case KVM_GET_MSRS:
3208 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3209 break;
3210 case KVM_SET_MSRS:
3211 r = msr_io(vcpu, argp, do_set_msr, 0);
3212 break;
b209749f
AK		 3213 case KVM_TPR_ACCESS_REPORTING: {
3214 struct kvm_tpr_access_ctl tac;
3215
3216 r = -EFAULT;
3217 if (copy_from_user(&tac, argp, sizeof tac))
3218 goto out;
3219 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3220 if (r)
3221 goto out;
3222 r = -EFAULT;
3223 if (copy_to_user(argp, &tac, sizeof tac))
3224 goto out;
3225 r = 0;
3226 break;
3227 };
b93463aa
AK		 3228 case KVM_SET_VAPIC_ADDR: {
3229 struct kvm_vapic_addr va;
3230
3231 r = -EINVAL;
3232 if (!irqchip_in_kernel(vcpu->kvm))
3233 goto out;
3234 r = -EFAULT;
3235 if (copy_from_user(&va, argp, sizeof va))
3236 goto out;
fda4e2e8 3237 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3238 break;
3239 }
890ca9ae
HY		 3240 case KVM_X86_SETUP_MCE: {
3241 u64 mcg_cap;
3242
3243 r = -EFAULT;
3244 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3245 goto out;
3246 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3247 break;
3248 }
3249 case KVM_X86_SET_MCE: {
3250 struct kvm_x86_mce mce;
3251
3252 r = -EFAULT;
3253 if (copy_from_user(&mce, argp, sizeof mce))
3254 goto out;
3255 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3256 break;
3257 }
3cfc3092
JK		 3258 case KVM_GET_VCPU_EVENTS: {
3259 struct kvm_vcpu_events events;
3260
3261 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3262
3263 r = -EFAULT;
3264 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3265 break;
3266 r = 0;
3267 break;
3268 }
3269 case KVM_SET_VCPU_EVENTS: {
3270 struct kvm_vcpu_events events;
3271
3272 r = -EFAULT;
3273 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3274 break;
3275
3276 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3277 break;
3278 }
a1efbe77
JK		 3279 case KVM_GET_DEBUGREGS: {
3280 struct kvm_debugregs dbgregs;
3281
3282 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3283
3284 r = -EFAULT;
3285 if (copy_to_user(argp, &dbgregs,
3286 sizeof(struct kvm_debugregs)))
3287 break;
3288 r = 0;
3289 break;
3290 }
3291 case KVM_SET_DEBUGREGS: {
3292 struct kvm_debugregs dbgregs;
3293
3294 r = -EFAULT;
3295 if (copy_from_user(&dbgregs, argp,
3296 sizeof(struct kvm_debugregs)))
3297 break;
3298
3299 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3300 break;
3301 }
2d5b5a66 3302 case KVM_GET_XSAVE: {
d1ac91d8 3303 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3304 r = -ENOMEM;
d1ac91d8 3305 if (!u.xsave)
2d5b5a66
SY		 3306 break;
3307
d1ac91d8 3308 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3309
3310 r = -EFAULT;
d1ac91d8 3311 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3312 break;
3313 r = 0;
3314 break;
3315 }
3316 case KVM_SET_XSAVE: {
ff5c2c03 3317 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3318 if (IS_ERR(u.xsave))
3319 return PTR_ERR(u.xsave);
2d5b5a66 3320
d1ac91d8 3321 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3322 break;
3323 }
3324 case KVM_GET_XCRS: {
d1ac91d8 3325 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3326 r = -ENOMEM;
d1ac91d8 3327 if (!u.xcrs)
2d5b5a66
SY		 3328 break;
3329
d1ac91d8 3330 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3331
3332 r = -EFAULT;
d1ac91d8 3333 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3334 sizeof(struct kvm_xcrs)))
3335 break;
3336 r = 0;
3337 break;
3338 }
3339 case KVM_SET_XCRS: {
ff5c2c03 3340 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3341 if (IS_ERR(u.xcrs))
3342 return PTR_ERR(u.xcrs);
2d5b5a66 3343
d1ac91d8 3344 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3345 break;
3346 }
92a1f12d
JR		 3347 case KVM_SET_TSC_KHZ: {
3348 u32 user_tsc_khz;
3349
3350 r = -EINVAL;
92a1f12d
JR		 3351 user_tsc_khz = (u32)arg;
3352
3353 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3354 goto out;
3355
cc578287
ZA		 3356 if (user_tsc_khz == 0)
3357 user_tsc_khz = tsc_khz;
3358
3359 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3360
3361 r = 0;
3362 goto out;
3363 }
3364 case KVM_GET_TSC_KHZ: {
cc578287 3365 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3366 goto out;
3367 }
1c0b28c2
EM		 3368 case KVM_KVMCLOCK_CTRL: {
3369 r = kvm_set_guest_paused(vcpu);
3370 goto out;
3371 }
313a3dc7
CO		 3372 default:
3373 r = -EINVAL;
3374 }
3375out:
d1ac91d8 3376 kfree(u.buffer);
313a3dc7
CO		 3377 return r;
3378}
3379
5b1c1493
CO		 3380int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3381{
3382 return VM_FAULT_SIGBUS;
3383}
3384
1fe779f8
CO		 3385static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3386{
3387 int ret;
3388
3389 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3390 return -EINVAL;
1fe779f8
CO		 3391 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3392 return ret;
3393}
3394
b927a3ce
SY		 3395static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3396 u64 ident_addr)
3397{
3398 kvm->arch.ept_identity_map_addr = ident_addr;
3399 return 0;
3400}
3401
1fe779f8
CO		 3402static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3403 u32 kvm_nr_mmu_pages)
3404{
3405 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3406 return -EINVAL;
3407
79fac95e 3408 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3409
3410 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3411 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3412
79fac95e 3413 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3414 return 0;
3415}
3416
3417static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3418{
39de71ec 3419 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3420}
3421
1fe779f8
CO		 3422static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3423{
3424 int r;
3425
3426 r = 0;
3427 switch (chip->chip_id) {
3428 case KVM_IRQCHIP_PIC_MASTER:
3429 memcpy(&chip->chip.pic,
3430 &pic_irqchip(kvm)->pics[0],
3431 sizeof(struct kvm_pic_state));
3432 break;
3433 case KVM_IRQCHIP_PIC_SLAVE:
3434 memcpy(&chip->chip.pic,
3435 &pic_irqchip(kvm)->pics[1],
3436 sizeof(struct kvm_pic_state));
3437 break;
3438 case KVM_IRQCHIP_IOAPIC:
eba0226b 3439 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3440 break;
3441 default:
3442 r = -EINVAL;
3443 break;
3444 }
3445 return r;
3446}
3447
3448static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3449{
3450 int r;
3451
3452 r = 0;
3453 switch (chip->chip_id) {
3454 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3455 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3456 memcpy(&pic_irqchip(kvm)->pics[0],
3457 &chip->chip.pic,
3458 sizeof(struct kvm_pic_state));
f4f51050 3459 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3460 break;
3461 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3462 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3463 memcpy(&pic_irqchip(kvm)->pics[1],
3464 &chip->chip.pic,
3465 sizeof(struct kvm_pic_state));
f4f51050 3466 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3467 break;
3468 case KVM_IRQCHIP_IOAPIC:
eba0226b 3469 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3470 break;
3471 default:
3472 r = -EINVAL;
3473 break;
3474 }
3475 kvm_pic_update_irq(pic_irqchip(kvm));
3476 return r;
3477}
3478
e0f63cb9
SY		 3479static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3480{
3481 int r = 0;
3482
894a9c55 3483 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3484 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3485 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3486 return r;
3487}
3488
3489static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3490{
3491 int r = 0;
3492
894a9c55 3493 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3494 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3495 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3496 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3497 return r;
3498}
3499
3500static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3501{
3502 int r = 0;
3503
3504 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3505 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3506 sizeof(ps->channels));
3507 ps->flags = kvm->arch.vpit->pit_state.flags;
3508 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3509 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3510 return r;
3511}
3512
3513static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3514{
3515 int r = 0, start = 0;
3516 u32 prev_legacy, cur_legacy;
3517 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3518 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3519 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3520 if (!prev_legacy && cur_legacy)
3521 start = 1;
3522 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3523 sizeof(kvm->arch.vpit->pit_state.channels));
3524 kvm->arch.vpit->pit_state.flags = ps->flags;
3525 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3526 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3527 return r;
3528}
3529
52d939a0
MT		 3530static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3531 struct kvm_reinject_control *control)
3532{
3533 if (!kvm->arch.vpit)
3534 return -ENXIO;
894a9c55 3535 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3536 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3537 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3538 return 0;
3539}
3540
95d4c16c 3541/**
60c34612
TY		 3542 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3543 * @kvm: kvm instance
3544 * @log: slot id and address to which we copy the log
95d4c16c 3545 *
60c34612
TY		 3546 * We need to keep it in mind that VCPU threads can write to the bitmap
3547 * concurrently. So, to avoid losing data, we keep the following order for
3548 * each bit:
95d4c16c 3549 *
60c34612
TY		 3550 * 1. Take a snapshot of the bit and clear it if needed.
3551 * 2. Write protect the corresponding page.
3552 * 3. Flush TLB's if needed.
3553 * 4. Copy the snapshot to the userspace.
95d4c16c 3554 *
60c34612
TY		 3555 * Between 2 and 3, the guest may write to the page using the remaining TLB
3556 * entry. This is not a problem because the page will be reported dirty at
3557 * step 4 using the snapshot taken before and step 3 ensures that successive
3558 * writes will be logged for the next call.
5bb064dc 3559 */
60c34612 3560int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3561{
7850ac54 3562 int r;
5bb064dc 3563 struct kvm_memory_slot *memslot;
60c34612
TY		 3564 unsigned long n, i;
3565 unsigned long *dirty_bitmap;
3566 unsigned long *dirty_bitmap_buffer;
3567 bool is_dirty = false;
5bb064dc 3568
79fac95e 3569 mutex_lock(&kvm->slots_lock);
5bb064dc 3570
b050b015 3571 r = -EINVAL;
bbacc0c1 3572 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3573 goto out;
3574
28a37544 3575 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3576
3577 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3578 r = -ENOENT;
60c34612 3579 if (!dirty_bitmap)
b050b015
MT		 3580 goto out;
3581
87bf6e7d 3582 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3583
60c34612
TY		 3584 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3585 memset(dirty_bitmap_buffer, 0, n);
b050b015 3586
60c34612 3587 spin_lock(&kvm->mmu_lock);
b050b015 3588
60c34612
TY		 3589 for (i = 0; i < n / sizeof(long); i++) {
3590 unsigned long mask;
3591 gfn_t offset;
cdfca7b3 3592
60c34612
TY		 3593 if (!dirty_bitmap[i])
3594 continue;
b050b015 3595
60c34612 3596 is_dirty = true;
914ebccd 3597
60c34612
TY		 3598 mask = xchg(&dirty_bitmap[i], 0);
3599 dirty_bitmap_buffer[i] = mask;
edde99ce 3600
60c34612
TY		 3601 offset = i * BITS_PER_LONG;
3602 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3603 }
60c34612
TY		 3604 if (is_dirty)
3605 kvm_flush_remote_tlbs(kvm);
3606
3607 spin_unlock(&kvm->mmu_lock);
3608
3609 r = -EFAULT;
3610 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3611 goto out;
b050b015 3612
5bb064dc
ZX		 3613 r = 0;
3614out:
79fac95e 3615 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3616 return r;
3617}
3618
aa2fbe6d
YZ		 3619int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3620 bool line_status)
23d43cf9
CD		 3621{
3622 if (!irqchip_in_kernel(kvm))
3623 return -ENXIO;
3624
3625 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3626 irq_event->irq, irq_event->level,
3627 line_status);
23d43cf9
CD		 3628 return 0;
3629}
3630
1fe779f8
CO		 3631long kvm_arch_vm_ioctl(struct file *filp,
3632 unsigned int ioctl, unsigned long arg)
3633{
3634 struct kvm *kvm = filp->private_data;
3635 void __user *argp = (void __user *)arg;
367e1319 3636 int r = -ENOTTY;
f0d66275
DH		 3637 /*
3638 * This union makes it completely explicit to gcc-3.x
3639 * that these two variables' stack usage should be
3640 * combined, not added together.
3641 */
3642 union {
3643 struct kvm_pit_state ps;
e9f42757 3644 struct kvm_pit_state2 ps2;
c5ff41ce 3645 struct kvm_pit_config pit_config;
f0d66275 3646 } u;
1fe779f8
CO		 3647
3648 switch (ioctl) {
3649 case KVM_SET_TSS_ADDR:
3650 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3651 break;
b927a3ce
SY		 3652 case KVM_SET_IDENTITY_MAP_ADDR: {
3653 u64 ident_addr;
3654
3655 r = -EFAULT;
3656 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3657 goto out;
3658 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3659 break;
3660 }
1fe779f8
CO		 3661 case KVM_SET_NR_MMU_PAGES:
3662 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3663 break;
3664 case KVM_GET_NR_MMU_PAGES:
3665 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3666 break;
3ddea128
MT		 3667 case KVM_CREATE_IRQCHIP: {
3668 struct kvm_pic *vpic;
3669
3670 mutex_lock(&kvm->lock);
3671 r = -EEXIST;
3672 if (kvm->arch.vpic)
3673 goto create_irqchip_unlock;
3e515705
AK		 3674 r = -EINVAL;
3675 if (atomic_read(&kvm->online_vcpus))
3676 goto create_irqchip_unlock;
1fe779f8 3677 r = -ENOMEM;
3ddea128
MT		 3678 vpic = kvm_create_pic(kvm);
3679 if (vpic) {
1fe779f8
CO		 3680 r = kvm_ioapic_init(kvm);
3681 if (r) {
175504cd 3682 mutex_lock(&kvm->slots_lock);
72bb2fcd 3683 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3684 &vpic->dev_master);
3685 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3686 &vpic->dev_slave);
3687 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3688 &vpic->dev_eclr);
175504cd 3689 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3690 kfree(vpic);
3691 goto create_irqchip_unlock;
1fe779f8
CO		 3692 }
3693 } else
3ddea128
MT		 3694 goto create_irqchip_unlock;
3695 smp_wmb();
3696 kvm->arch.vpic = vpic;
3697 smp_wmb();
399ec807
AK		 3698 r = kvm_setup_default_irq_routing(kvm);
3699 if (r) {
175504cd 3700 mutex_lock(&kvm->slots_lock);
3ddea128 3701 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3702 kvm_ioapic_destroy(kvm);
3703 kvm_destroy_pic(kvm);
3ddea128 3704 mutex_unlock(&kvm->irq_lock);
175504cd 3705 mutex_unlock(&kvm->slots_lock);
399ec807 3706 }
3ddea128
MT		 3707 create_irqchip_unlock:
3708 mutex_unlock(&kvm->lock);
1fe779f8 3709 break;
3ddea128 3710 }
7837699f 3711 case KVM_CREATE_PIT:
c5ff41ce
JK		 3712 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3713 goto create_pit;
3714 case KVM_CREATE_PIT2:
3715 r = -EFAULT;
3716 if (copy_from_user(&u.pit_config, argp,
3717 sizeof(struct kvm_pit_config)))
3718 goto out;
3719 create_pit:
79fac95e 3720 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3721 r = -EEXIST;
3722 if (kvm->arch.vpit)
3723 goto create_pit_unlock;
7837699f 3724 r = -ENOMEM;
c5ff41ce 3725 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3726 if (kvm->arch.vpit)
3727 r = 0;
269e05e4 3728 create_pit_unlock:
79fac95e 3729 mutex_unlock(&kvm->slots_lock);
7837699f 3730 break;
1fe779f8
CO		 3731 case KVM_GET_IRQCHIP: {
3732 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3733 struct kvm_irqchip *chip;
1fe779f8 3734
ff5c2c03
SL		 3735 chip = memdup_user(argp, sizeof(*chip));
3736 if (IS_ERR(chip)) {
3737 r = PTR_ERR(chip);
1fe779f8 3738 goto out;
ff5c2c03
SL		 3739 }
3740
1fe779f8
CO		 3741 r = -ENXIO;
3742 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3743 goto get_irqchip_out;
3744 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3745 if (r)
f0d66275 3746 goto get_irqchip_out;
1fe779f8 3747 r = -EFAULT;
f0d66275
DH		 3748 if (copy_to_user(argp, chip, sizeof *chip))
3749 goto get_irqchip_out;
1fe779f8 3750 r = 0;
f0d66275
DH		 3751 get_irqchip_out:
3752 kfree(chip);
1fe779f8
CO		 3753 break;
3754 }
3755 case KVM_SET_IRQCHIP: {
3756 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3757 struct kvm_irqchip *chip;
1fe779f8 3758
ff5c2c03
SL		 3759 chip = memdup_user(argp, sizeof(*chip));
3760 if (IS_ERR(chip)) {
3761 r = PTR_ERR(chip);
1fe779f8 3762 goto out;
ff5c2c03
SL		 3763 }
3764
1fe779f8
CO		 3765 r = -ENXIO;
3766 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3767 goto set_irqchip_out;
3768 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3769 if (r)
f0d66275 3770 goto set_irqchip_out;
1fe779f8 3771 r = 0;
f0d66275
DH		 3772 set_irqchip_out:
3773 kfree(chip);
1fe779f8
CO		 3774 break;
3775 }
e0f63cb9 3776 case KVM_GET_PIT: {
e0f63cb9 3777 r = -EFAULT;
f0d66275 3778 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3779 goto out;
3780 r = -ENXIO;
3781 if (!kvm->arch.vpit)
3782 goto out;
f0d66275 3783 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3784 if (r)
3785 goto out;
3786 r = -EFAULT;
f0d66275 3787 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3788 goto out;
3789 r = 0;
3790 break;
3791 }
3792 case KVM_SET_PIT: {
e0f63cb9 3793 r = -EFAULT;
f0d66275 3794 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3795 goto out;
3796 r = -ENXIO;
3797 if (!kvm->arch.vpit)
3798 goto out;
f0d66275 3799 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3800 break;
3801 }
e9f42757
BK		 3802 case KVM_GET_PIT2: {
3803 r = -ENXIO;
3804 if (!kvm->arch.vpit)
3805 goto out;
3806 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3807 if (r)
3808 goto out;
3809 r = -EFAULT;
3810 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3811 goto out;
3812 r = 0;
3813 break;
3814 }
3815 case KVM_SET_PIT2: {
3816 r = -EFAULT;
3817 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3818 goto out;
3819 r = -ENXIO;
3820 if (!kvm->arch.vpit)
3821 goto out;
3822 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3823 break;
3824 }
52d939a0
MT		 3825 case KVM_REINJECT_CONTROL: {
3826 struct kvm_reinject_control control;
3827 r = -EFAULT;
3828 if (copy_from_user(&control, argp, sizeof(control)))
3829 goto out;
3830 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3831 break;
3832 }
ffde22ac
ES		 3833 case KVM_XEN_HVM_CONFIG: {
3834 r = -EFAULT;
3835 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3836 sizeof(struct kvm_xen_hvm_config)))
3837 goto out;
3838 r = -EINVAL;
3839 if (kvm->arch.xen_hvm_config.flags)
3840 goto out;
3841 r = 0;
3842 break;
3843 }
afbcf7ab 3844 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3845 struct kvm_clock_data user_ns;
3846 u64 now_ns;
3847 s64 delta;
3848
3849 r = -EFAULT;
3850 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3851 goto out;
3852
3853 r = -EINVAL;
3854 if (user_ns.flags)
3855 goto out;
3856
3857 r = 0;
395c6b0a 3858 local_irq_disable();
759379dd 3859 now_ns = get_kernel_ns();
afbcf7ab 3860 delta = user_ns.clock - now_ns;
395c6b0a 3861 local_irq_enable();
afbcf7ab 3862 kvm->arch.kvmclock_offset = delta;
2e762ff7 3863 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3864 break;
3865 }
3866 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3867 struct kvm_clock_data user_ns;
3868 u64 now_ns;
3869
395c6b0a 3870 local_irq_disable();
759379dd 3871 now_ns = get_kernel_ns();
afbcf7ab 3872 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3873 local_irq_enable();
afbcf7ab 3874 user_ns.flags = 0;
97e69aa6 3875 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3876
3877 r = -EFAULT;
3878 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3879 goto out;
3880 r = 0;
3881 break;
3882 }
3883
1fe779f8
CO		 3884 default:
3885 ;
3886 }
3887out:
3888 return r;
3889}
3890
a16b043c 3891static void kvm_init_msr_list(void)
043405e1
CO		 3892{
3893 u32 dummy[2];
3894 unsigned i, j;
3895
e3267cbb
GC		 3896 /* skip the first msrs in the list. KVM-specific */
3897 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3898 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3899 continue;
3900 if (j < i)
3901 msrs_to_save[j] = msrs_to_save[i];
3902 j++;
3903 }
3904 num_msrs_to_save = j;
3905}
3906
bda9020e
MT		 3907static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3908 const void *v)
bbd9b64e 3909{
70252a10
AK		 3910 int handled = 0;
3911 int n;
3912
3913 do {
3914 n = min(len, 8);
3915 if (!(vcpu->arch.apic &&
3916 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3917 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3918 break;
3919 handled += n;
3920 addr += n;
3921 len -= n;
3922 v += n;
3923 } while (len);
bbd9b64e 3924
70252a10 3925 return handled;
bbd9b64e
CO		 3926}
3927
bda9020e 3928static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3929{
70252a10
AK		 3930 int handled = 0;
3931 int n;
3932
3933 do {
3934 n = min(len, 8);
3935 if (!(vcpu->arch.apic &&
3936 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3937 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3938 break;
3939 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3940 handled += n;
3941 addr += n;
3942 len -= n;
3943 v += n;
3944 } while (len);
bbd9b64e 3945
70252a10 3946 return handled;
bbd9b64e
CO		 3947}
3948
2dafc6c2
GN		 3949static void kvm_set_segment(struct kvm_vcpu *vcpu,
3950 struct kvm_segment *var, int seg)
3951{
3952 kvm_x86_ops->set_segment(vcpu, var, seg);
3953}
3954
3955void kvm_get_segment(struct kvm_vcpu *vcpu,
3956 struct kvm_segment *var, int seg)
3957{
3958 kvm_x86_ops->get_segment(vcpu, var, seg);
3959}
3960
e459e322 3961gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3962{
3963 gpa_t t_gpa;
ab9ae313 3964 struct x86_exception exception;
02f59dc9
JR		 3965
3966 BUG_ON(!mmu_is_nested(vcpu));
3967
3968 /* NPT walks are always user-walks */
3969 access |= PFERR_USER_MASK;
ab9ae313 3970 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3971
3972 return t_gpa;
3973}
3974
ab9ae313
AK		 3975gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3976 struct x86_exception *exception)
1871c602
GN		 3977{
3978 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3979 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3980}
3981
ab9ae313
AK		 3982 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3983 struct x86_exception *exception)
1871c602
GN		 3984{
3985 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3986 access |= PFERR_FETCH_MASK;
ab9ae313 3987 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3988}
3989
ab9ae313
AK		 3990gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3991 struct x86_exception *exception)
1871c602
GN		 3992{
3993 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3994 access |= PFERR_WRITE_MASK;
ab9ae313 3995 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3996}
3997
3998/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3999gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4000 struct x86_exception *exception)
1871c602 4001{
ab9ae313 4002 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4003}
4004
4005static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4006 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4007 struct x86_exception *exception)
bbd9b64e
CO		 4008{
4009 void *data = val;
10589a46 4010 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4011
4012 while (bytes) {
14dfe855 4013 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4014 exception);
bbd9b64e 4015 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4016 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4017 int ret;
4018
bcc55cba 4019 if (gpa == UNMAPPED_GVA)
ab9ae313 4020 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4021 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4022 if (ret < 0) {
c3cd7ffa 4023 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4024 goto out;
4025 }
bbd9b64e 4026
77c2002e
IE		 4027 bytes -= toread;
4028 data += toread;
4029 addr += toread;
bbd9b64e 4030 }
10589a46 4031out:
10589a46 4032 return r;
bbd9b64e 4033}
77c2002e 4034
1871c602 4035/* used for instruction fetching */
0f65dd70
AK		 4036static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4037 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4038 struct x86_exception *exception)
1871c602 4039{
0f65dd70 4040 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4041 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4042
1871c602 4043 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4044 access | PFERR_FETCH_MASK,
4045 exception);
1871c602
GN		 4046}
4047
064aea77 4048int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4049 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4050 struct x86_exception *exception)
1871c602 4051{
0f65dd70 4052 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4053 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4054
1871c602 4055 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4056 exception);
1871c602 4057}
064aea77 4058EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4059
0f65dd70
AK		 4060static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4061 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4062 struct x86_exception *exception)
1871c602 4063{
0f65dd70 4064 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4065 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4066}
4067
6a4d7550 4068int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4069 gva_t addr, void *val,
2dafc6c2 4070 unsigned int bytes,
bcc55cba 4071 struct x86_exception *exception)
77c2002e 4072{
0f65dd70 4073 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4074 void *data = val;
4075 int r = X86EMUL_CONTINUE;
4076
4077 while (bytes) {
14dfe855
JR		 4078 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4079 PFERR_WRITE_MASK,
ab9ae313 4080 exception);
77c2002e
IE		 4081 unsigned offset = addr & (PAGE_SIZE-1);
4082 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4083 int ret;
4084
bcc55cba 4085 if (gpa == UNMAPPED_GVA)
ab9ae313 4086 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4087 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4088 if (ret < 0) {
c3cd7ffa 4089 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4090 goto out;
4091 }
4092
4093 bytes -= towrite;
4094 data += towrite;
4095 addr += towrite;
4096 }
4097out:
4098 return r;
4099}
6a4d7550 4100EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4101
af7cc7d1
XG		 4102static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4103 gpa_t *gpa, struct x86_exception *exception,
4104 bool write)
4105{
97d64b78
AK		 4106 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4107 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4108
97d64b78
AK		 4109 if (vcpu_match_mmio_gva(vcpu, gva)
4110 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4111 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4112 (gva & (PAGE_SIZE - 1));
4f022648 4113 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4114 return 1;
4115 }
4116
af7cc7d1
XG		 4117 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4118
4119 if (*gpa == UNMAPPED_GVA)
4120 return -1;
4121
4122 /* For APIC access vmexit */
4123 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4124 return 1;
4125
4f022648
XG		 4126 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4127 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4128 return 1;
4f022648 4129 }
bebb106a 4130
af7cc7d1
XG		 4131 return 0;
4132}
4133
3200f405 4134int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4135 const void *val, int bytes)
bbd9b64e
CO		 4136{
4137 int ret;
4138
4139 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4140 if (ret < 0)
bbd9b64e 4141 return 0;
f57f2ef5 4142 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4143 return 1;
4144}
4145
77d197b2
XG		 4146struct read_write_emulator_ops {
4147 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4148 int bytes);
4149 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4150 void *val, int bytes);
4151 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4152 int bytes, void *val);
4153 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4154 void *val, int bytes);
4155 bool write;
4156};
4157
4158static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4159{
4160 if (vcpu->mmio_read_completed) {
77d197b2 4161 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4162 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4163 vcpu->mmio_read_completed = 0;
4164 return 1;
4165 }
4166
4167 return 0;
4168}
4169
4170static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4171 void *val, int bytes)
4172{
4173 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4174}
4175
4176static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4177 void *val, int bytes)
4178{
4179 return emulator_write_phys(vcpu, gpa, val, bytes);
4180}
4181
4182static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4183{
4184 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4185 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4186}
4187
4188static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4189 void *val, int bytes)
4190{
4191 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4192 return X86EMUL_IO_NEEDED;
4193}
4194
4195static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4196 void *val, int bytes)
4197{
f78146b0
AK		 4198 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4199
87da7e66 4200 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4201 return X86EMUL_CONTINUE;
4202}
4203
0fbe9b0b 4204static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4205 .read_write_prepare = read_prepare,
4206 .read_write_emulate = read_emulate,
4207 .read_write_mmio = vcpu_mmio_read,
4208 .read_write_exit_mmio = read_exit_mmio,
4209};
4210
0fbe9b0b 4211static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4212 .read_write_emulate = write_emulate,
4213 .read_write_mmio = write_mmio,
4214 .read_write_exit_mmio = write_exit_mmio,
4215 .write = true,
4216};
4217
22388a3c
XG		 4218static int emulator_read_write_onepage(unsigned long addr, void *val,
4219 unsigned int bytes,
4220 struct x86_exception *exception,
4221 struct kvm_vcpu *vcpu,
0fbe9b0b 4222 const struct read_write_emulator_ops *ops)
bbd9b64e 4223{
af7cc7d1
XG		 4224 gpa_t gpa;
4225 int handled, ret;
22388a3c 4226 bool write = ops->write;
f78146b0 4227 struct kvm_mmio_fragment *frag;
10589a46 4228
22388a3c 4229 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4230
af7cc7d1 4231 if (ret < 0)
bbd9b64e 4232 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4233
4234 /* For APIC access vmexit */
af7cc7d1 4235 if (ret)
bbd9b64e
CO		 4236 goto mmio;
4237
22388a3c 4238 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4239 return X86EMUL_CONTINUE;
4240
4241mmio:
4242 /*
4243 * Is this MMIO handled locally?
4244 */
22388a3c 4245 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4246 if (handled == bytes)
bbd9b64e 4247 return X86EMUL_CONTINUE;
bbd9b64e 4248
70252a10
AK		 4249 gpa += handled;
4250 bytes -= handled;
4251 val += handled;
4252
87da7e66
XG		 4253 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4254 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4255 frag->gpa = gpa;
4256 frag->data = val;
4257 frag->len = bytes;
f78146b0 4258 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4259}
4260
22388a3c
XG		 4261int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4262 void *val, unsigned int bytes,
4263 struct x86_exception *exception,
0fbe9b0b 4264 const struct read_write_emulator_ops *ops)
bbd9b64e 4265{
0f65dd70 4266 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4267 gpa_t gpa;
4268 int rc;
4269
4270 if (ops->read_write_prepare &&
4271 ops->read_write_prepare(vcpu, val, bytes))
4272 return X86EMUL_CONTINUE;
4273
4274 vcpu->mmio_nr_fragments = 0;
0f65dd70 4275
bbd9b64e
CO		 4276 /* Crossing a page boundary? */
4277 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4278 int now;
bbd9b64e
CO		 4279
4280 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4281 rc = emulator_read_write_onepage(addr, val, now, exception,
4282 vcpu, ops);
4283
bbd9b64e
CO		 4284 if (rc != X86EMUL_CONTINUE)
4285 return rc;
4286 addr += now;
4287 val += now;
4288 bytes -= now;
4289 }
22388a3c 4290
f78146b0
AK		 4291 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4292 vcpu, ops);
4293 if (rc != X86EMUL_CONTINUE)
4294 return rc;
4295
4296 if (!vcpu->mmio_nr_fragments)
4297 return rc;
4298
4299 gpa = vcpu->mmio_fragments[0].gpa;
4300
4301 vcpu->mmio_needed = 1;
4302 vcpu->mmio_cur_fragment = 0;
4303
87da7e66 4304 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4305 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4306 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4307 vcpu->run->mmio.phys_addr = gpa;
4308
4309 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4310}
4311
4312static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4313 unsigned long addr,
4314 void *val,
4315 unsigned int bytes,
4316 struct x86_exception *exception)
4317{
4318 return emulator_read_write(ctxt, addr, val, bytes,
4319 exception, &read_emultor);
4320}
4321
4322int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4323 unsigned long addr,
4324 const void *val,
4325 unsigned int bytes,
4326 struct x86_exception *exception)
4327{
4328 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4329 exception, &write_emultor);
bbd9b64e 4330}
bbd9b64e 4331
daea3e73
AK		 4332#define CMPXCHG_TYPE(t, ptr, old, new) \
4333 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4334
4335#ifdef CONFIG_X86_64
4336# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4337#else
4338# define CMPXCHG64(ptr, old, new) \
9749a6c0 4339 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4340#endif
4341
0f65dd70
AK		 4342static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4343 unsigned long addr,
bbd9b64e
CO		 4344 const void *old,
4345 const void *new,
4346 unsigned int bytes,
0f65dd70 4347 struct x86_exception *exception)
bbd9b64e 4348{
0f65dd70 4349 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4350 gpa_t gpa;
4351 struct page *page;
4352 char *kaddr;
4353 bool exchanged;
2bacc55c 4354
daea3e73
AK		 4355 /* guests cmpxchg8b have to be emulated atomically */
4356 if (bytes > 8 || (bytes & (bytes - 1)))
4357 goto emul_write;
10589a46 4358
daea3e73 4359 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4360
daea3e73
AK		 4361 if (gpa == UNMAPPED_GVA ||
4362 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4363 goto emul_write;
2bacc55c 4364
daea3e73
AK		 4365 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4366 goto emul_write;
72dc67a6 4367
daea3e73 4368 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4369 if (is_error_page(page))
c19b8bd6 4370 goto emul_write;
72dc67a6 4371
8fd75e12 4372 kaddr = kmap_atomic(page);
daea3e73
AK		 4373 kaddr += offset_in_page(gpa);
4374 switch (bytes) {
4375 case 1:
4376 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4377 break;
4378 case 2:
4379 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4380 break;
4381 case 4:
4382 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4383 break;
4384 case 8:
4385 exchanged = CMPXCHG64(kaddr, old, new);
4386 break;
4387 default:
4388 BUG();
2bacc55c 4389 }
8fd75e12 4390 kunmap_atomic(kaddr);
daea3e73
AK		 4391 kvm_release_page_dirty(page);
4392
4393 if (!exchanged)
4394 return X86EMUL_CMPXCHG_FAILED;
4395
f57f2ef5 4396 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4397
4398 return X86EMUL_CONTINUE;
4a5f48f6 4399
3200f405 4400emul_write:
daea3e73 4401 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4402
0f65dd70 4403 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4404}
4405
cf8f70bf
GN		 4406static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4407{
4408 /* TODO: String I/O for in kernel device */
4409 int r;
4410
4411 if (vcpu->arch.pio.in)
4412 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4413 vcpu->arch.pio.size, pd);
4414 else
4415 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4416 vcpu->arch.pio.port, vcpu->arch.pio.size,
4417 pd);
4418 return r;
4419}
4420
6f6fbe98
XG		 4421static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4422 unsigned short port, void *val,
4423 unsigned int count, bool in)
cf8f70bf 4424{
6f6fbe98 4425 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4426
4427 vcpu->arch.pio.port = port;
6f6fbe98 4428 vcpu->arch.pio.in = in;
7972995b 4429 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4430 vcpu->arch.pio.size = size;
4431
4432 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4433 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4434 return 1;
4435 }
4436
4437 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4438 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4439 vcpu->run->io.size = size;
4440 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4441 vcpu->run->io.count = count;
4442 vcpu->run->io.port = port;
4443
4444 return 0;
4445}
4446
6f6fbe98
XG		 4447static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4448 int size, unsigned short port, void *val,
4449 unsigned int count)
cf8f70bf 4450{
ca1d4a9e 4451 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4452 int ret;
ca1d4a9e 4453
6f6fbe98
XG		 4454 if (vcpu->arch.pio.count)
4455 goto data_avail;
cf8f70bf 4456
6f6fbe98
XG		 4457 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4458 if (ret) {
4459data_avail:
4460 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4461 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4462 return 1;
4463 }
4464
cf8f70bf
GN		 4465 return 0;
4466}
4467
6f6fbe98
XG		 4468static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4469 int size, unsigned short port,
4470 const void *val, unsigned int count)
4471{
4472 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4473
4474 memcpy(vcpu->arch.pio_data, val, size * count);
4475 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4476}
4477
bbd9b64e
CO		 4478static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4479{
4480 return kvm_x86_ops->get_segment_base(vcpu, seg);
4481}
4482
3cb16fe7 4483static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4484{
3cb16fe7 4485 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4486}
4487
f5f48ee1
SY		 4488int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4489{
4490 if (!need_emulate_wbinvd(vcpu))
4491 return X86EMUL_CONTINUE;
4492
4493 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4494 int cpu = get_cpu();
4495
4496 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4497 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4498 wbinvd_ipi, NULL, 1);
2eec7343 4499 put_cpu();
f5f48ee1 4500 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4501 } else
4502 wbinvd();
f5f48ee1
SY		 4503 return X86EMUL_CONTINUE;
4504}
4505EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4506
bcaf5cc5
AK		 4507static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4508{
4509 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4510}
4511
717746e3 4512int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4513{
717746e3 4514 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4515}
4516
717746e3 4517int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4518{
338dbc97 4519
717746e3 4520 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4521}
4522
52a46617 4523static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4524{
52a46617 4525 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4526}
4527
717746e3 4528static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4529{
717746e3 4530 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4531 unsigned long value;
4532
4533 switch (cr) {
4534 case 0:
4535 value = kvm_read_cr0(vcpu);
4536 break;
4537 case 2:
4538 value = vcpu->arch.cr2;
4539 break;
4540 case 3:
9f8fe504 4541 value = kvm_read_cr3(vcpu);
52a46617
GN		 4542 break;
4543 case 4:
4544 value = kvm_read_cr4(vcpu);
4545 break;
4546 case 8:
4547 value = kvm_get_cr8(vcpu);
4548 break;
4549 default:
a737f256 4550 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4551 return 0;
4552 }
4553
4554 return value;
4555}
4556
717746e3 4557static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4558{
717746e3 4559 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4560 int res = 0;
4561
52a46617
GN		 4562 switch (cr) {
4563 case 0:
49a9b07e 4564 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4565 break;
4566 case 2:
4567 vcpu->arch.cr2 = val;
4568 break;
4569 case 3:
2390218b 4570 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4571 break;
4572 case 4:
a83b29c6 4573 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4574 break;
4575 case 8:
eea1cff9 4576 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4577 break;
4578 default:
a737f256 4579 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4580 res = -1;
52a46617 4581 }
0f12244f
GN		 4582
4583 return res;
52a46617
GN		 4584}
4585
4cee4798
KW		 4586static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4587{
4588 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4589}
4590
717746e3 4591static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4592{
717746e3 4593 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4594}
4595
4bff1e86 4596static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4597{
4bff1e86 4598 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4599}
4600
4bff1e86 4601static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4602{
4bff1e86 4603 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4604}
4605
1ac9d0cf
AK		 4606static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4607{
4608 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4609}
4610
4611static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4612{
4613 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4614}
4615
4bff1e86
AK		 4616static unsigned long emulator_get_cached_segment_base(
4617 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4618{
4bff1e86 4619 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4620}
4621
1aa36616
AK		 4622static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4623 struct desc_struct *desc, u32 *base3,
4624 int seg)
2dafc6c2
GN		 4625{
4626 struct kvm_segment var;
4627
4bff1e86 4628 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4629 *selector = var.selector;
2dafc6c2 4630
378a8b09
GN		 4631 if (var.unusable) {
4632 memset(desc, 0, sizeof(*desc));
2dafc6c2 4633 return false;
378a8b09 4634 }
2dafc6c2
GN		 4635
4636 if (var.g)
4637 var.limit >>= 12;
4638 set_desc_limit(desc, var.limit);
4639 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4640#ifdef CONFIG_X86_64
4641 if (base3)
4642 *base3 = var.base >> 32;
4643#endif
2dafc6c2
GN		 4644 desc->type = var.type;
4645 desc->s = var.s;
4646 desc->dpl = var.dpl;
4647 desc->p = var.present;
4648 desc->avl = var.avl;
4649 desc->l = var.l;
4650 desc->d = var.db;
4651 desc->g = var.g;
4652
4653 return true;
4654}
4655
1aa36616
AK		 4656static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4657 struct desc_struct *desc, u32 base3,
4658 int seg)
2dafc6c2 4659{
4bff1e86 4660 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4661 struct kvm_segment var;
4662
1aa36616 4663 var.selector = selector;
2dafc6c2 4664 var.base = get_desc_base(desc);
5601d05b
GN		 4665#ifdef CONFIG_X86_64
4666 var.base |= ((u64)base3) << 32;
4667#endif
2dafc6c2
GN		 4668 var.limit = get_desc_limit(desc);
4669 if (desc->g)
4670 var.limit = (var.limit << 12) | 0xfff;
4671 var.type = desc->type;
4672 var.present = desc->p;
4673 var.dpl = desc->dpl;
4674 var.db = desc->d;
4675 var.s = desc->s;
4676 var.l = desc->l;
4677 var.g = desc->g;
4678 var.avl = desc->avl;
4679 var.present = desc->p;
4680 var.unusable = !var.present;
4681 var.padding = 0;
4682
4683 kvm_set_segment(vcpu, &var, seg);
4684 return;
4685}
4686
717746e3
AK		 4687static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4688 u32 msr_index, u64 *pdata)
4689{
4690 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4691}
4692
4693static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4694 u32 msr_index, u64 data)
4695{
8fe8ab46
WA		 4696 struct msr_data msr;
4697
4698 msr.data = data;
4699 msr.index = msr_index;
4700 msr.host_initiated = false;
4701 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4702}
4703
222d21aa
AK		 4704static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4705 u32 pmc, u64 *pdata)
4706{
4707 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4708}
4709
6c3287f7
AK		 4710static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4711{
4712 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4713}
4714
5037f6f3
AK		 4715static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4716{
4717 preempt_disable();
5197b808 4718 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4719 /*
4720 * CR0.TS may reference the host fpu state, not the guest fpu state,
4721 * so it may be clear at this point.
4722 */
4723 clts();
4724}
4725
4726static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4727{
4728 preempt_enable();
4729}
4730
2953538e 4731static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4732 struct x86_instruction_info *info,
c4f035c6
AK		 4733 enum x86_intercept_stage stage)
4734{
2953538e 4735 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4736}
4737
0017f93a 4738static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4739 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4740{
0017f93a 4741 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4742}
4743
dd856efa
AK		 4744static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4745{
4746 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4747}
4748
4749static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4750{
4751 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4752}
4753
0225fb50 4754static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4755 .read_gpr = emulator_read_gpr,
4756 .write_gpr = emulator_write_gpr,
1871c602 4757 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4758 .write_std = kvm_write_guest_virt_system,
1871c602 4759 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4760 .read_emulated = emulator_read_emulated,
4761 .write_emulated = emulator_write_emulated,
4762 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4763 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4764 .pio_in_emulated = emulator_pio_in_emulated,
4765 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4766 .get_segment = emulator_get_segment,
4767 .set_segment = emulator_set_segment,
5951c442 4768 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4769 .get_gdt = emulator_get_gdt,
160ce1f1 4770 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4771 .set_gdt = emulator_set_gdt,
4772 .set_idt = emulator_set_idt,
52a46617
GN		 4773 .get_cr = emulator_get_cr,
4774 .set_cr = emulator_set_cr,
4cee4798 4775 .set_rflags = emulator_set_rflags,
9c537244 4776 .cpl = emulator_get_cpl,
35aa5375
GN		 4777 .get_dr = emulator_get_dr,
4778 .set_dr = emulator_set_dr,
717746e3
AK		 4779 .set_msr = emulator_set_msr,
4780 .get_msr = emulator_get_msr,
222d21aa 4781 .read_pmc = emulator_read_pmc,
6c3287f7 4782 .halt = emulator_halt,
bcaf5cc5 4783 .wbinvd = emulator_wbinvd,
d6aa1000 4784 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4785 .get_fpu = emulator_get_fpu,
4786 .put_fpu = emulator_put_fpu,
c4f035c6 4787 .intercept = emulator_intercept,
bdb42f5a 4788 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4789};
4790
95cb2295
GN		 4791static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4792{
4793 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4794 /*
4795 * an sti; sti; sequence only disable interrupts for the first
4796 * instruction. So, if the last instruction, be it emulated or
4797 * not, left the system with the INT_STI flag enabled, it
4798 * means that the last instruction is an sti. We should not
4799 * leave the flag on in this case. The same goes for mov ss
4800 */
4801 if (!(int_shadow & mask))
4802 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4803}
4804
54b8486f
GN		 4805static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4806{
4807 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4808 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4809 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4810 else if (ctxt->exception.error_code_valid)
4811 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4812 ctxt->exception.error_code);
54b8486f 4813 else
da9cb575 4814 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4815}
4816
dd856efa 4817static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4818{
1ce19dc1
BP		 4819 memset(&ctxt->opcode_len, 0,
4820 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4821
9dac77fa
AK		 4822 ctxt->fetch.start = 0;
4823 ctxt->fetch.end = 0;
4824 ctxt->io_read.pos = 0;
4825 ctxt->io_read.end = 0;
4826 ctxt->mem_read.pos = 0;
4827 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4828}
4829
8ec4722d
MG		 4830static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4831{
adf52235 4832 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4833 int cs_db, cs_l;
4834
8ec4722d
MG		 4835 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4836
adf52235
TY		 4837 ctxt->eflags = kvm_get_rflags(vcpu);
4838 ctxt->eip = kvm_rip_read(vcpu);
4839 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4840 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4841 cs_l ? X86EMUL_MODE_PROT64 :
4842 cs_db ? X86EMUL_MODE_PROT32 :
4843 X86EMUL_MODE_PROT16;
4844 ctxt->guest_mode = is_guest_mode(vcpu);
4845
dd856efa 4846 init_decode_cache(ctxt);
7ae441ea 4847 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4848}
4849
71f9833b 4850int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4851{
9d74191a 4852 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4853 int ret;
4854
4855 init_emulate_ctxt(vcpu);
4856
9dac77fa
AK		 4857 ctxt->op_bytes = 2;
4858 ctxt->ad_bytes = 2;
4859 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4860 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4861
4862 if (ret != X86EMUL_CONTINUE)
4863 return EMULATE_FAIL;
4864
9dac77fa 4865 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4866 kvm_rip_write(vcpu, ctxt->eip);
4867 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4868
4869 if (irq == NMI_VECTOR)
7460fb4a 4870 vcpu->arch.nmi_pending = 0;
63995653
MG		 4871 else
4872 vcpu->arch.interrupt.pending = false;
4873
4874 return EMULATE_DONE;
4875}
4876EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4877
6d77dbfc
GN		 4878static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4879{
fc3a9157
JR		 4880 int r = EMULATE_DONE;
4881
6d77dbfc
GN		 4882 ++vcpu->stat.insn_emulation_fail;
4883 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4884 if (!is_guest_mode(vcpu)) {
4885 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4886 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4887 vcpu->run->internal.ndata = 0;
4888 r = EMULATE_FAIL;
4889 }
6d77dbfc 4890 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4891
4892 return r;
6d77dbfc
GN		 4893}
4894
93c05d3e 4895static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4896 bool write_fault_to_shadow_pgtable,
4897 int emulation_type)
a6f177ef 4898{
95b3cf69 4899 gpa_t gpa = cr2;
8e3d9d06 4900 pfn_t pfn;
a6f177ef 4901
991eebf9
GN		 4902 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4903 return false;
4904
95b3cf69
XG		 4905 if (!vcpu->arch.mmu.direct_map) {
4906 /*
4907 * Write permission should be allowed since only
4908 * write access need to be emulated.
4909 */
4910 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4911
95b3cf69
XG		 4912 /*
4913 * If the mapping is invalid in guest, let cpu retry
4914 * it to generate fault.
4915 */
4916 if (gpa == UNMAPPED_GVA)
4917 return true;
4918 }
a6f177ef 4919
8e3d9d06
XG		 4920 /*
4921 * Do not retry the unhandleable instruction if it faults on the
4922 * readonly host memory, otherwise it will goto a infinite loop:
4923 * retry instruction -> write #PF -> emulation fail -> retry
4924 * instruction -> ...
4925 */
4926 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4927
4928 /*
4929 * If the instruction failed on the error pfn, it can not be fixed,
4930 * report the error to userspace.
4931 */
4932 if (is_error_noslot_pfn(pfn))
4933 return false;
4934
4935 kvm_release_pfn_clean(pfn);
4936
4937 /* The instructions are well-emulated on direct mmu. */
4938 if (vcpu->arch.mmu.direct_map) {
4939 unsigned int indirect_shadow_pages;
4940
4941 spin_lock(&vcpu->kvm->mmu_lock);
4942 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4943 spin_unlock(&vcpu->kvm->mmu_lock);
4944
4945 if (indirect_shadow_pages)
4946 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4947
a6f177ef 4948 return true;
8e3d9d06 4949 }
a6f177ef 4950
95b3cf69
XG		 4951 /*
4952 * if emulation was due to access to shadowed page table
4953 * and it failed try to unshadow page and re-enter the
4954 * guest to let CPU execute the instruction.
4955 */
4956 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4957
4958 /*
4959 * If the access faults on its page table, it can not
4960 * be fixed by unprotecting shadow page and it should
4961 * be reported to userspace.
4962 */
4963 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4964}
4965
1cb3f3ae
XG		 4966static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4967 unsigned long cr2, int emulation_type)
4968{
4969 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4970 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4971
4972 last_retry_eip = vcpu->arch.last_retry_eip;
4973 last_retry_addr = vcpu->arch.last_retry_addr;
4974
4975 /*
4976 * If the emulation is caused by #PF and it is non-page_table
4977 * writing instruction, it means the VM-EXIT is caused by shadow
4978 * page protected, we can zap the shadow page and retry this
4979 * instruction directly.
4980 *
4981 * Note: if the guest uses a non-page-table modifying instruction
4982 * on the PDE that points to the instruction, then we will unmap
4983 * the instruction and go to an infinite loop. So, we cache the
4984 * last retried eip and the last fault address, if we meet the eip
4985 * and the address again, we can break out of the potential infinite
4986 * loop.
4987 */
4988 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4989
4990 if (!(emulation_type & EMULTYPE_RETRY))
4991 return false;
4992
4993 if (x86_page_table_writing_insn(ctxt))
4994 return false;
4995
4996 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4997 return false;
4998
4999 vcpu->arch.last_retry_eip = ctxt->eip;
5000 vcpu->arch.last_retry_addr = cr2;
5001
5002 if (!vcpu->arch.mmu.direct_map)
5003 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5004
22368028 5005 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5006
5007 return true;
5008}
5009
716d51ab
GN		 5010static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5011static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5012
4a1e10d5
PB		 5013static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5014 unsigned long *db)
5015{
5016 u32 dr6 = 0;
5017 int i;
5018 u32 enable, rwlen;
5019
5020 enable = dr7;
5021 rwlen = dr7 >> 16;
5022 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5023 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5024 dr6 |= (1 << i);
5025 return dr6;
5026}
5027
663f4c61
PB		 5028static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5029{
5030 struct kvm_run *kvm_run = vcpu->run;
5031
5032 /*
5033 * Use the "raw" value to see if TF was passed to the processor.
5034 * Note that the new value of the flags has not been saved yet.
5035 *
5036 * This is correct even for TF set by the guest, because "the
5037 * processor will not generate this exception after the instruction
5038 * that sets the TF flag".
5039 */
5040 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5041
5042 if (unlikely(rflags & X86_EFLAGS_TF)) {
5043 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5044 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5045 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5046 kvm_run->debug.arch.exception = DB_VECTOR;
5047 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5048 *r = EMULATE_USER_EXIT;
5049 } else {
5050 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5051 /*
5052 * "Certain debug exceptions may clear bit 0-3. The
5053 * remaining contents of the DR6 register are never
5054 * cleared by the processor".
5055 */
5056 vcpu->arch.dr6 &= ~15;
5057 vcpu->arch.dr6 |= DR6_BS;
5058 kvm_queue_exception(vcpu, DB_VECTOR);
5059 }
5060 }
5061}
5062
4a1e10d5
PB		 5063static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5064{
5065 struct kvm_run *kvm_run = vcpu->run;
5066 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5067 u32 dr6 = 0;
5068
5069 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5070 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5071 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5072 vcpu->arch.guest_debug_dr7,
5073 vcpu->arch.eff_db);
5074
5075 if (dr6 != 0) {
5076 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5077 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5078 get_segment_base(vcpu, VCPU_SREG_CS);
5079
5080 kvm_run->debug.arch.exception = DB_VECTOR;
5081 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5082 *r = EMULATE_USER_EXIT;
5083 return true;
5084 }
5085 }
5086
5087 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5088 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5089 vcpu->arch.dr7,
5090 vcpu->arch.db);
5091
5092 if (dr6 != 0) {
5093 vcpu->arch.dr6 &= ~15;
5094 vcpu->arch.dr6 |= dr6;
5095 kvm_queue_exception(vcpu, DB_VECTOR);
5096 *r = EMULATE_DONE;
5097 return true;
5098 }
5099 }
5100
5101 return false;
5102}
5103
51d8b661
AP		 5104int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5105 unsigned long cr2,
dc25e89e
AP		 5106 int emulation_type,
5107 void *insn,
5108 int insn_len)
bbd9b64e 5109{
95cb2295 5110 int r;
9d74191a 5111 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5112 bool writeback = true;
93c05d3e 5113 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5114
93c05d3e
XG		 5115 /*
5116 * Clear write_fault_to_shadow_pgtable here to ensure it is
5117 * never reused.
5118 */
5119 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5120 kvm_clear_exception_queue(vcpu);
8d7d8102 5121
571008da 5122 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5123 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5124
5125 /*
5126 * We will reenter on the same instruction since
5127 * we do not set complete_userspace_io. This does not
5128 * handle watchpoints yet, those would be handled in
5129 * the emulate_ops.
5130 */
5131 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5132 return r;
5133
9d74191a
TY		 5134 ctxt->interruptibility = 0;
5135 ctxt->have_exception = false;
5136 ctxt->perm_ok = false;
bbd9b64e 5137
b51e974f 5138 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5139
9d74191a 5140 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5141
e46479f8 5142 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5143 ++vcpu->stat.insn_emulation;
1d2887e2 5144 if (r != EMULATION_OK) {
4005996e
AK		 5145 if (emulation_type & EMULTYPE_TRAP_UD)
5146 return EMULATE_FAIL;
991eebf9
GN		 5147 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5148 emulation_type))
bbd9b64e 5149 return EMULATE_DONE;
6d77dbfc
GN		 5150 if (emulation_type & EMULTYPE_SKIP)
5151 return EMULATE_FAIL;
5152 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5153 }
5154 }
5155
ba8afb6b 5156 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5157 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5158 return EMULATE_DONE;
5159 }
5160
1cb3f3ae
XG		 5161 if (retry_instruction(ctxt, cr2, emulation_type))
5162 return EMULATE_DONE;
5163
7ae441ea 5164 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5165 changes registers values during IO operation */
7ae441ea
GN		 5166 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5167 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5168 emulator_invalidate_register_cache(ctxt);
7ae441ea 5169 }
4d2179e1 5170
5cd21917 5171restart:
9d74191a 5172 r = x86_emulate_insn(ctxt);
bbd9b64e 5173
775fde86
JR		 5174 if (r == EMULATION_INTERCEPTED)
5175 return EMULATE_DONE;
5176
d2ddd1c4 5177 if (r == EMULATION_FAILED) {
991eebf9
GN		 5178 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5179 emulation_type))
c3cd7ffa
GN		 5180 return EMULATE_DONE;
5181
6d77dbfc 5182 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5183 }
5184
9d74191a 5185 if (ctxt->have_exception) {
54b8486f 5186 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5187 r = EMULATE_DONE;
5188 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5189 if (!vcpu->arch.pio.in) {
5190 /* FIXME: return into emulator if single-stepping. */
3457e419 5191 vcpu->arch.pio.count = 0;
0912c977 5192 } else {
7ae441ea 5193 writeback = false;
716d51ab
GN		 5194 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5195 }
ac0a48c3 5196 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5197 } else if (vcpu->mmio_needed) {
5198 if (!vcpu->mmio_is_write)
5199 writeback = false;
ac0a48c3 5200 r = EMULATE_USER_EXIT;
716d51ab 5201 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5202 } else if (r == EMULATION_RESTART)
5cd21917 5203 goto restart;
d2ddd1c4
GN		 5204 else
5205 r = EMULATE_DONE;
f850e2e6 5206
7ae441ea 5207 if (writeback) {
9d74191a 5208 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5209 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5210 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5211 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5212 if (r == EMULATE_DONE)
5213 kvm_vcpu_check_singlestep(vcpu, &r);
5214 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5215 } else
5216 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5217
5218 return r;
de7d789a 5219}
51d8b661 5220EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5221
cf8f70bf 5222int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5223{
cf8f70bf 5224 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5225 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5226 size, port, &val, 1);
cf8f70bf 5227 /* do not return to emulator after return from userspace */
7972995b 5228 vcpu->arch.pio.count = 0;
de7d789a
CO		 5229 return ret;
5230}
cf8f70bf 5231EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5232
8cfdc000
ZA		 5233static void tsc_bad(void *info)
5234{
0a3aee0d 5235 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5236}
5237
5238static void tsc_khz_changed(void *data)
c8076604 5239{
8cfdc000
ZA		 5240 struct cpufreq_freqs *freq = data;
5241 unsigned long khz = 0;
5242
5243 if (data)
5244 khz = freq->new;
5245 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5246 khz = cpufreq_quick_get(raw_smp_processor_id());
5247 if (!khz)
5248 khz = tsc_khz;
0a3aee0d 5249 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5250}
5251
c8076604
GH		 5252static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5253 void *data)
5254{
5255 struct cpufreq_freqs *freq = data;
5256 struct kvm *kvm;
5257 struct kvm_vcpu *vcpu;
5258 int i, send_ipi = 0;
5259
8cfdc000
ZA		 5260 /*
5261 * We allow guests to temporarily run on slowing clocks,
5262 * provided we notify them after, or to run on accelerating
5263 * clocks, provided we notify them before. Thus time never
5264 * goes backwards.
5265 *
5266 * However, we have a problem. We can't atomically update
5267 * the frequency of a given CPU from this function; it is
5268 * merely a notifier, which can be called from any CPU.
5269 * Changing the TSC frequency at arbitrary points in time
5270 * requires a recomputation of local variables related to
5271 * the TSC for each VCPU. We must flag these local variables
5272 * to be updated and be sure the update takes place with the
5273 * new frequency before any guests proceed.
5274 *
5275 * Unfortunately, the combination of hotplug CPU and frequency
5276 * change creates an intractable locking scenario; the order
5277 * of when these callouts happen is undefined with respect to
5278 * CPU hotplug, and they can race with each other. As such,
5279 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5280 * undefined; you can actually have a CPU frequency change take
5281 * place in between the computation of X and the setting of the
5282 * variable. To protect against this problem, all updates of
5283 * the per_cpu tsc_khz variable are done in an interrupt
5284 * protected IPI, and all callers wishing to update the value
5285 * must wait for a synchronous IPI to complete (which is trivial
5286 * if the caller is on the CPU already). This establishes the
5287 * necessary total order on variable updates.
5288 *
5289 * Note that because a guest time update may take place
5290 * anytime after the setting of the VCPU's request bit, the
5291 * correct TSC value must be set before the request. However,
5292 * to ensure the update actually makes it to any guest which
5293 * starts running in hardware virtualization between the set
5294 * and the acquisition of the spinlock, we must also ping the
5295 * CPU after setting the request bit.
5296 *
5297 */
5298
c8076604
GH		 5299 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5300 return 0;
5301 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5302 return 0;
8cfdc000
ZA		 5303
5304 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5305
2f303b74 5306 spin_lock(&kvm_lock);
c8076604 5307 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5308 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5309 if (vcpu->cpu != freq->cpu)
5310 continue;
c285545f 5311 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5312 if (vcpu->cpu != smp_processor_id())
8cfdc000 5313 send_ipi = 1;
c8076604
GH		 5314 }
5315 }
2f303b74 5316 spin_unlock(&kvm_lock);
c8076604
GH		 5317
5318 if (freq->old < freq->new && send_ipi) {
5319 /*
5320 * We upscale the frequency. Must make the guest
5321 * doesn't see old kvmclock values while running with
5322 * the new frequency, otherwise we risk the guest sees
5323 * time go backwards.
5324 *
5325 * In case we update the frequency for another cpu
5326 * (which might be in guest context) send an interrupt
5327 * to kick the cpu out of guest context. Next time
5328 * guest context is entered kvmclock will be updated,
5329 * so the guest will not see stale values.
5330 */
8cfdc000 5331 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5332 }
5333 return 0;
5334}
5335
5336static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5337 .notifier_call = kvmclock_cpufreq_notifier
5338};
5339
5340static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5341 unsigned long action, void *hcpu)
5342{
5343 unsigned int cpu = (unsigned long)hcpu;
5344
5345 switch (action) {
5346 case CPU_ONLINE:
5347 case CPU_DOWN_FAILED:
5348 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5349 break;
5350 case CPU_DOWN_PREPARE:
5351 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5352 break;
5353 }
5354 return NOTIFY_OK;
5355}
5356
5357static struct notifier_block kvmclock_cpu_notifier_block = {
5358 .notifier_call = kvmclock_cpu_notifier,
5359 .priority = -INT_MAX
c8076604
GH		 5360};
5361
b820cc0c
ZA		 5362static void kvm_timer_init(void)
5363{
5364 int cpu;
5365
c285545f 5366 max_tsc_khz = tsc_khz;
8cfdc000 5367 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5368 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5369#ifdef CONFIG_CPU_FREQ
5370 struct cpufreq_policy policy;
5371 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5372 cpu = get_cpu();
5373 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5374 if (policy.cpuinfo.max_freq)
5375 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5376 put_cpu();
c285545f 5377#endif
b820cc0c
ZA		 5378 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5379 CPUFREQ_TRANSITION_NOTIFIER);
5380 }
c285545f 5381 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5382 for_each_online_cpu(cpu)
5383 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5384}
5385
ff9d07a0
ZY		 5386static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5387
f5132b01 5388int kvm_is_in_guest(void)
ff9d07a0 5389{
086c9855 5390 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5391}
5392
5393static int kvm_is_user_mode(void)
5394{
5395 int user_mode = 3;
dcf46b94 5396
086c9855
AS		 5397 if (__this_cpu_read(current_vcpu))
5398 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5399
ff9d07a0
ZY		 5400 return user_mode != 0;
5401}
5402
5403static unsigned long kvm_get_guest_ip(void)
5404{
5405 unsigned long ip = 0;
dcf46b94 5406
086c9855
AS		 5407 if (__this_cpu_read(current_vcpu))
5408 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5409
ff9d07a0
ZY		 5410 return ip;
5411}
5412
5413static struct perf_guest_info_callbacks kvm_guest_cbs = {
5414 .is_in_guest = kvm_is_in_guest,
5415 .is_user_mode = kvm_is_user_mode,
5416 .get_guest_ip = kvm_get_guest_ip,
5417};
5418
5419void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5420{
086c9855 5421 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5422}
5423EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5424
5425void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5426{
086c9855 5427 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5428}
5429EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5430
ce88decf
XG		 5431static void kvm_set_mmio_spte_mask(void)
5432{
5433 u64 mask;
5434 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5435
5436 /*
5437 * Set the reserved bits and the present bit of an paging-structure
5438 * entry to generate page fault with PFER.RSV = 1.
5439 */
885032b9
XG		 5440 /* Mask the reserved physical address bits. */
5441 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5442
5443 /* Bit 62 is always reserved for 32bit host. */
5444 mask |= 0x3ull << 62;
5445
5446 /* Set the present bit. */
ce88decf
XG		 5447 mask |= 1ull;
5448
5449#ifdef CONFIG_X86_64
5450 /*
5451 * If reserved bit is not supported, clear the present bit to disable
5452 * mmio page fault.
5453 */
5454 if (maxphyaddr == 52)
5455 mask &= ~1ull;
5456#endif
5457
5458 kvm_mmu_set_mmio_spte_mask(mask);
5459}
5460
16e8d74d
MT		 5461#ifdef CONFIG_X86_64
5462static void pvclock_gtod_update_fn(struct work_struct *work)
5463{
d828199e
MT		 5464 struct kvm *kvm;
5465
5466 struct kvm_vcpu *vcpu;
5467 int i;
5468
2f303b74 5469 spin_lock(&kvm_lock);
d828199e
MT		 5470 list_for_each_entry(kvm, &vm_list, vm_list)
5471 kvm_for_each_vcpu(i, vcpu, kvm)
5472 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5473 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5474 spin_unlock(&kvm_lock);
16e8d74d
MT		 5475}
5476
5477static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5478
5479/*
5480 * Notification about pvclock gtod data update.
5481 */
5482static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5483 void *priv)
5484{
5485 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5486 struct timekeeper *tk = priv;
5487
5488 update_pvclock_gtod(tk);
5489
5490 /* disable master clock if host does not trust, or does not
5491 * use, TSC clocksource
5492 */
5493 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5494 atomic_read(&kvm_guest_has_master_clock) != 0)
5495 queue_work(system_long_wq, &pvclock_gtod_work);
5496
5497 return 0;
5498}
5499
5500static struct notifier_block pvclock_gtod_notifier = {
5501 .notifier_call = pvclock_gtod_notify,
5502};
5503#endif
5504
f8c16bba 5505int kvm_arch_init(void *opaque)
043405e1 5506{
b820cc0c 5507 int r;
6b61edf7 5508 struct kvm_x86_ops *ops = opaque;
f8c16bba 5509
f8c16bba
ZX		 5510 if (kvm_x86_ops) {
5511 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5512 r = -EEXIST;
5513 goto out;
f8c16bba
ZX		 5514 }
5515
5516 if (!ops->cpu_has_kvm_support()) {
5517 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5518 r = -EOPNOTSUPP;
5519 goto out;
f8c16bba
ZX		 5520 }
5521 if (ops->disabled_by_bios()) {
5522 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5523 r = -EOPNOTSUPP;
5524 goto out;
f8c16bba
ZX		 5525 }
5526
013f6a5d
MT		 5527 r = -ENOMEM;
5528 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5529 if (!shared_msrs) {
5530 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5531 goto out;
5532 }
5533
97db56ce
AK		 5534 r = kvm_mmu_module_init();
5535 if (r)
013f6a5d 5536 goto out_free_percpu;
97db56ce 5537
ce88decf 5538 kvm_set_mmio_spte_mask();
97db56ce
AK		 5539 kvm_init_msr_list();
5540
f8c16bba 5541 kvm_x86_ops = ops;
7b52345e 5542 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5543 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5544
b820cc0c 5545 kvm_timer_init();
c8076604 5546
ff9d07a0
ZY		 5547 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5548
2acf923e
DC		 5549 if (cpu_has_xsave)
5550 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5551
c5cc421b 5552 kvm_lapic_init();
16e8d74d
MT		 5553#ifdef CONFIG_X86_64
5554 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5555#endif
5556
f8c16bba 5557 return 0;
56c6d28a 5558
013f6a5d
MT		 5559out_free_percpu:
5560 free_percpu(shared_msrs);
56c6d28a 5561out:
56c6d28a 5562 return r;
043405e1 5563}
8776e519 5564
f8c16bba
ZX		 5565void kvm_arch_exit(void)
5566{
ff9d07a0
ZY		 5567 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5568
888d256e
JK		 5569 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5570 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5571 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5572 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5573#ifdef CONFIG_X86_64
5574 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5575#endif
f8c16bba 5576 kvm_x86_ops = NULL;
56c6d28a 5577 kvm_mmu_module_exit();
013f6a5d 5578 free_percpu(shared_msrs);
56c6d28a 5579}
f8c16bba 5580
8776e519
HB		 5581int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5582{
5583 ++vcpu->stat.halt_exits;
5584 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5585 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5586 return 1;
5587 } else {
5588 vcpu->run->exit_reason = KVM_EXIT_HLT;
5589 return 0;
5590 }
5591}
5592EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5593
55cd8e5a
GN		 5594int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5595{
5596 u64 param, ingpa, outgpa, ret;
5597 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5598 bool fast, longmode;
5599 int cs_db, cs_l;
5600
5601 /*
5602 * hypercall generates UD from non zero cpl and real mode
5603 * per HYPER-V spec
5604 */
3eeb3288 5605 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5606 kvm_queue_exception(vcpu, UD_VECTOR);
5607 return 0;
5608 }
5609
5610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5611 longmode = is_long_mode(vcpu) && cs_l == 1;
5612
5613 if (!longmode) {
ccd46936
GN		 5614 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5615 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5616 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5617 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5618 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5619 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5620 }
5621#ifdef CONFIG_X86_64
5622 else {
5623 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5624 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5625 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5626 }
5627#endif
5628
5629 code = param & 0xffff;
5630 fast = (param >> 16) & 0x1;
5631 rep_cnt = (param >> 32) & 0xfff;
5632 rep_idx = (param >> 48) & 0xfff;
5633
5634 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5635
c25bc163
GN		 5636 switch (code) {
5637 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5638 kvm_vcpu_on_spin(vcpu);
5639 break;
5640 default:
5641 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5642 break;
5643 }
55cd8e5a
GN		 5644
5645 ret = res | (((u64)rep_done & 0xfff) << 32);
5646 if (longmode) {
5647 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5648 } else {
5649 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5650 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5651 }
5652
5653 return 1;
5654}
5655
6aef266c
SV		 5656/*
5657 * kvm_pv_kick_cpu_op: Kick a vcpu.
5658 *
5659 * @apicid - apicid of vcpu to be kicked.
5660 */
5661static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5662{
24d2166b 5663 struct kvm_lapic_irq lapic_irq;
6aef266c 5664
24d2166b
R		 5665 lapic_irq.shorthand = 0;
5666 lapic_irq.dest_mode = 0;
5667 lapic_irq.dest_id = apicid;
6aef266c 5668
24d2166b
R		 5669 lapic_irq.delivery_mode = APIC_DM_REMRD;
5670 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5671}
5672
8776e519
HB		 5673int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5674{
5675 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5676 int r = 1;
8776e519 5677
55cd8e5a
GN		 5678 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5679 return kvm_hv_hypercall(vcpu);
5680
5fdbf976
MT		 5681 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5682 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5683 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5684 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5685 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5686
229456fc 5687 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5688
8776e519
HB		 5689 if (!is_long_mode(vcpu)) {
5690 nr &= 0xFFFFFFFF;
5691 a0 &= 0xFFFFFFFF;
5692 a1 &= 0xFFFFFFFF;
5693 a2 &= 0xFFFFFFFF;
5694 a3 &= 0xFFFFFFFF;
5695 }
5696
07708c4a
JK		 5697 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5698 ret = -KVM_EPERM;
5699 goto out;
5700 }
5701
8776e519 5702 switch (nr) {
b93463aa
AK		 5703 case KVM_HC_VAPIC_POLL_IRQ:
5704 ret = 0;
5705 break;
6aef266c
SV		 5706 case KVM_HC_KICK_CPU:
5707 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5708 ret = 0;
5709 break;
8776e519
HB		 5710 default:
5711 ret = -KVM_ENOSYS;
5712 break;
5713 }
07708c4a 5714out:
5fdbf976 5715 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5716 ++vcpu->stat.hypercalls;
2f333bcb 5717 return r;
8776e519
HB		 5718}
5719EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5720
b6785def 5721static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5722{
d6aa1000 5723 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5724 char instruction[3];
5fdbf976 5725 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5726
8776e519 5727 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5728
9d74191a 5729 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5730}
5731
b6c7a5dc
HB		 5732/*
5733 * Check if userspace requested an interrupt window, and that the
5734 * interrupt window is open.
5735 *
5736 * No need to exit to userspace if we already have an interrupt queued.
5737 */
851ba692 5738static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5739{
8061823a 5740 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5741 vcpu->run->request_interrupt_window &&
5df56646 5742 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5743}
5744
851ba692 5745static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5746{
851ba692
AK		 5747 struct kvm_run *kvm_run = vcpu->run;
5748
91586a3b 5749 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5750 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5751 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5752 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5753 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5754 else
b6c7a5dc 5755 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5756 kvm_arch_interrupt_allowed(vcpu) &&
5757 !kvm_cpu_has_interrupt(vcpu) &&
5758 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5759}
5760
95ba8273
GN		 5761static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5762{
5763 int max_irr, tpr;
5764
5765 if (!kvm_x86_ops->update_cr8_intercept)
5766 return;
5767
88c808fd
AK		 5768 if (!vcpu->arch.apic)
5769 return;
5770
8db3baa2
GN		 5771 if (!vcpu->arch.apic->vapic_addr)
5772 max_irr = kvm_lapic_find_highest_irr(vcpu);
5773 else
5774 max_irr = -1;
95ba8273
GN		 5775
5776 if (max_irr != -1)
5777 max_irr >>= 4;
5778
5779 tpr = kvm_lapic_get_cr8(vcpu);
5780
5781 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5782}
5783
851ba692 5784static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5785{
5786 /* try to reinject previous events if any */
b59bb7bd 5787 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5788 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5789 vcpu->arch.exception.has_error_code,
5790 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5791 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5792 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5793 vcpu->arch.exception.error_code,
5794 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5795 return;
5796 }
5797
95ba8273
GN		 5798 if (vcpu->arch.nmi_injected) {
5799 kvm_x86_ops->set_nmi(vcpu);
5800 return;
5801 }
5802
5803 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5804 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5805 return;
5806 }
5807
5808 /* try to inject new event if pending */
5809 if (vcpu->arch.nmi_pending) {
5810 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5811 --vcpu->arch.nmi_pending;
95ba8273
GN		 5812 vcpu->arch.nmi_injected = true;
5813 kvm_x86_ops->set_nmi(vcpu);
5814 }
c7c9c56c 5815 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5816 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5817 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5818 false);
5819 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5820 }
5821 }
5822}
5823
7460fb4a
AK		 5824static void process_nmi(struct kvm_vcpu *vcpu)
5825{
5826 unsigned limit = 2;
5827
5828 /*
5829 * x86 is limited to one NMI running, and one NMI pending after it.
5830 * If an NMI is already in progress, limit further NMIs to just one.
5831 * Otherwise, allow two (and we'll inject the first one immediately).
5832 */
5833 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5834 limit = 1;
5835
5836 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5837 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5838 kvm_make_request(KVM_REQ_EVENT, vcpu);
5839}
5840
3d81bc7e 5841static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5842{
5843 u64 eoi_exit_bitmap[4];
cf9e65b7 5844 u32 tmr[8];
c7c9c56c 5845
3d81bc7e
YZ		 5846 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5847 return;
c7c9c56c
YZ		 5848
5849 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5850 memset(tmr, 0, 32);
c7c9c56c 5851
cf9e65b7 5852 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5853 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5854 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5855}
5856
9357d939
TY		 5857/*
5858 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5859 * exiting to the userspace. Otherwise, the value will be returned to the
5860 * userspace.
5861 */
851ba692 5862static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5863{
5864 int r;
6a8b1d13 5865 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5866 vcpu->run->request_interrupt_window;
730dca42 5867 bool req_immediate_exit = false;
b6c7a5dc 5868
3e007509 5869 if (vcpu->requests) {
a8eeb04a 5870 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5871 kvm_mmu_unload(vcpu);
a8eeb04a 5872 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5873 __kvm_migrate_timers(vcpu);
d828199e
MT		 5874 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5875 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5876 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5877 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5878 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5879 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5880 if (unlikely(r))
5881 goto out;
5882 }
a8eeb04a 5883 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5884 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5885 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5886 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5887 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5888 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5889 r = 0;
5890 goto out;
5891 }
a8eeb04a 5892 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5893 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5894 r = 0;
5895 goto out;
5896 }
a8eeb04a 5897 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5898 vcpu->fpu_active = 0;
5899 kvm_x86_ops->fpu_deactivate(vcpu);
5900 }
af585b92
GN		 5901 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5902 /* Page is swapped out. Do synthetic halt */
5903 vcpu->arch.apf.halted = true;
5904 r = 1;
5905 goto out;
5906 }
c9aaa895
GC		 5907 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5908 record_steal_time(vcpu);
7460fb4a
AK		 5909 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5910 process_nmi(vcpu);
f5132b01
GN		 5911 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5912 kvm_handle_pmu_event(vcpu);
5913 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5914 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5915 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5916 vcpu_scan_ioapic(vcpu);
2f52d58c 5917 }
b93463aa 5918
b463a6f7 5919 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5920 kvm_apic_accept_events(vcpu);
5921 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5922 r = 1;
5923 goto out;
5924 }
5925
b463a6f7
AK		 5926 inject_pending_event(vcpu);
5927
5928 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5929 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5930 req_immediate_exit =
5931 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5932 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5933 req_immediate_exit =
5934 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5935
5936 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5937 /*
5938 * Update architecture specific hints for APIC
5939 * virtual interrupt delivery.
5940 */
5941 if (kvm_x86_ops->hwapic_irr_update)
5942 kvm_x86_ops->hwapic_irr_update(vcpu,
5943 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5944 update_cr8_intercept(vcpu);
5945 kvm_lapic_sync_to_vapic(vcpu);
5946 }
5947 }
5948
d8368af8
AK		 5949 r = kvm_mmu_reload(vcpu);
5950 if (unlikely(r)) {
d905c069 5951 goto cancel_injection;
d8368af8
AK		 5952 }
5953
b6c7a5dc
HB		 5954 preempt_disable();
5955
5956 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5957 if (vcpu->fpu_active)
5958 kvm_load_guest_fpu(vcpu);
2acf923e 5959 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5960
6b7e2d09
XG		 5961 vcpu->mode = IN_GUEST_MODE;
5962
01b71917
MT		 5963 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5964
6b7e2d09
XG		 5965 /* We should set ->mode before check ->requests,
5966 * see the comment in make_all_cpus_request.
5967 */
01b71917 5968 smp_mb__after_srcu_read_unlock();
b6c7a5dc 5969
d94e1dc9 5970 local_irq_disable();
32f88400 5971
6b7e2d09 5972 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5973 || need_resched() || signal_pending(current)) {
6b7e2d09 5974 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5975 smp_wmb();
6c142801
AK		 5976 local_irq_enable();
5977 preempt_enable();
01b71917 5978 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 5979 r = 1;
d905c069 5980 goto cancel_injection;
6c142801
AK		 5981 }
5982
d6185f20
NHE		 5983 if (req_immediate_exit)
5984 smp_send_reschedule(vcpu->cpu);
5985
b6c7a5dc
HB		 5986 kvm_guest_enter();
5987
42dbaa5a 5988 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5989 set_debugreg(0, 7);
5990 set_debugreg(vcpu->arch.eff_db[0], 0);
5991 set_debugreg(vcpu->arch.eff_db[1], 1);
5992 set_debugreg(vcpu->arch.eff_db[2], 2);
5993 set_debugreg(vcpu->arch.eff_db[3], 3);
5994 }
b6c7a5dc 5995
229456fc 5996 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5997 kvm_x86_ops->run(vcpu);
b6c7a5dc 5998
24f1e32c
FW		 5999 /*
6000 * If the guest has used debug registers, at least dr7
6001 * will be disabled while returning to the host.
6002 * If we don't have active breakpoints in the host, we don't
6003 * care about the messed up debug address registers. But if
6004 * we have some of them active, restore the old state.
6005 */
59d8eb53 6006 if (hw_breakpoint_active())
24f1e32c 6007 hw_breakpoint_restore();
42dbaa5a 6008
886b470c
MT		 6009 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6010 native_read_tsc());
1d5f066e 6011
6b7e2d09 6012 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6013 smp_wmb();
a547c6db
YZ		 6014
6015 /* Interrupt is enabled by handle_external_intr() */
6016 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6017
6018 ++vcpu->stat.exits;
6019
6020 /*
6021 * We must have an instruction between local_irq_enable() and
6022 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6023 * the interrupt shadow. The stat.exits increment will do nicely.
6024 * But we need to prevent reordering, hence this barrier():
6025 */
6026 barrier();
6027
6028 kvm_guest_exit();
6029
6030 preempt_enable();
6031
f656ce01 6032 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6033
b6c7a5dc
HB		 6034 /*
6035 * Profile KVM exit RIPs:
6036 */
6037 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6038 unsigned long rip = kvm_rip_read(vcpu);
6039 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6040 }
6041
cc578287
ZA		 6042 if (unlikely(vcpu->arch.tsc_always_catchup))
6043 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6044
5cfb1d5a
MT		 6045 if (vcpu->arch.apic_attention)
6046 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6047
851ba692 6048 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6049 return r;
6050
6051cancel_injection:
6052 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6053 if (unlikely(vcpu->arch.apic_attention))
6054 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6055out:
6056 return r;
6057}
b6c7a5dc 6058
09cec754 6059
851ba692 6060static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6061{
6062 int r;
f656ce01 6063 struct kvm *kvm = vcpu->kvm;
d7690175 6064
f656ce01 6065 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6066
6067 r = 1;
6068 while (r > 0) {
af585b92
GN		 6069 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6070 !vcpu->arch.apf.halted)
851ba692 6071 r = vcpu_enter_guest(vcpu);
d7690175 6072 else {
f656ce01 6073 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6074 kvm_vcpu_block(vcpu);
f656ce01 6075 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6076 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6077 kvm_apic_accept_events(vcpu);
09cec754
GN		 6078 switch(vcpu->arch.mp_state) {
6079 case KVM_MP_STATE_HALTED:
6aef266c 6080 vcpu->arch.pv.pv_unhalted = false;
d7690175 6081 vcpu->arch.mp_state =
09cec754
GN		 6082 KVM_MP_STATE_RUNNABLE;
6083 case KVM_MP_STATE_RUNNABLE:
af585b92 6084 vcpu->arch.apf.halted = false;
09cec754 6085 break;
66450a21
JK		 6086 case KVM_MP_STATE_INIT_RECEIVED:
6087 break;
09cec754
GN		 6088 default:
6089 r = -EINTR;
6090 break;
6091 }
6092 }
d7690175
MT		 6093 }
6094
09cec754
GN		 6095 if (r <= 0)
6096 break;
6097
6098 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6099 if (kvm_cpu_has_pending_timer(vcpu))
6100 kvm_inject_pending_timer_irqs(vcpu);
6101
851ba692 6102 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6103 r = -EINTR;
851ba692 6104 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6105 ++vcpu->stat.request_irq_exits;
6106 }
af585b92
GN		 6107
6108 kvm_check_async_pf_completion(vcpu);
6109
09cec754
GN		 6110 if (signal_pending(current)) {
6111 r = -EINTR;
851ba692 6112 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6113 ++vcpu->stat.signal_exits;
6114 }
6115 if (need_resched()) {
f656ce01 6116 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6117 cond_resched();
f656ce01 6118 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6119 }
b6c7a5dc
HB		 6120 }
6121
f656ce01 6122 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6123
6124 return r;
6125}
6126
716d51ab
GN		 6127static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6128{
6129 int r;
6130 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6131 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6132 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6133 if (r != EMULATE_DONE)
6134 return 0;
6135 return 1;
6136}
6137
6138static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6139{
6140 BUG_ON(!vcpu->arch.pio.count);
6141
6142 return complete_emulated_io(vcpu);
6143}
6144
f78146b0
AK		 6145/*
6146 * Implements the following, as a state machine:
6147 *
6148 * read:
6149 * for each fragment
87da7e66
XG		 6150 * for each mmio piece in the fragment
6151 * write gpa, len
6152 * exit
6153 * copy data
f78146b0
AK		 6154 * execute insn
6155 *
6156 * write:
6157 * for each fragment
87da7e66
XG		 6158 * for each mmio piece in the fragment
6159 * write gpa, len
6160 * copy data
6161 * exit
f78146b0 6162 */
716d51ab 6163static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6164{
6165 struct kvm_run *run = vcpu->run;
f78146b0 6166 struct kvm_mmio_fragment *frag;
87da7e66 6167 unsigned len;
5287f194 6168
716d51ab 6169 BUG_ON(!vcpu->mmio_needed);
5287f194 6170
716d51ab 6171 /* Complete previous fragment */
87da7e66
XG		 6172 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6173 len = min(8u, frag->len);
716d51ab 6174 if (!vcpu->mmio_is_write)
87da7e66
XG		 6175 memcpy(frag->data, run->mmio.data, len);
6176
6177 if (frag->len <= 8) {
6178 /* Switch to the next fragment. */
6179 frag++;
6180 vcpu->mmio_cur_fragment++;
6181 } else {
6182 /* Go forward to the next mmio piece. */
6183 frag->data += len;
6184 frag->gpa += len;
6185 frag->len -= len;
6186 }
6187
716d51ab
GN		 6188 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6189 vcpu->mmio_needed = 0;
0912c977
PB		 6190
6191 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6192 if (vcpu->mmio_is_write)
716d51ab
GN		 6193 return 1;
6194 vcpu->mmio_read_completed = 1;
6195 return complete_emulated_io(vcpu);
6196 }
87da7e66 6197
716d51ab
GN		 6198 run->exit_reason = KVM_EXIT_MMIO;
6199 run->mmio.phys_addr = frag->gpa;
6200 if (vcpu->mmio_is_write)
87da7e66
XG		 6201 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6202 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6203 run->mmio.is_write = vcpu->mmio_is_write;
6204 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6205 return 0;
5287f194
AK		 6206}
6207
716d51ab 6208
b6c7a5dc
HB		 6209int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6210{
6211 int r;
6212 sigset_t sigsaved;
6213
e5c30142
AK		 6214 if (!tsk_used_math(current) && init_fpu(current))
6215 return -ENOMEM;
6216
ac9f6dc0
AK		 6217 if (vcpu->sigset_active)
6218 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6219
a4535290 6220 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6221 kvm_vcpu_block(vcpu);
66450a21 6222 kvm_apic_accept_events(vcpu);
d7690175 6223 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6224 r = -EAGAIN;
6225 goto out;
b6c7a5dc
HB		 6226 }
6227
b6c7a5dc 6228 /* re-sync apic's tpr */
eea1cff9
AP		 6229 if (!irqchip_in_kernel(vcpu->kvm)) {
6230 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6231 r = -EINVAL;
6232 goto out;
6233 }
6234 }
b6c7a5dc 6235
716d51ab
GN		 6236 if (unlikely(vcpu->arch.complete_userspace_io)) {
6237 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6238 vcpu->arch.complete_userspace_io = NULL;
6239 r = cui(vcpu);
6240 if (r <= 0)
6241 goto out;
6242 } else
6243 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6244
851ba692 6245 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6246
6247out:
f1d86e46 6248 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6249 if (vcpu->sigset_active)
6250 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6251
b6c7a5dc
HB		 6252 return r;
6253}
6254
6255int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6256{
7ae441ea
GN		 6257 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6258 /*
6259 * We are here if userspace calls get_regs() in the middle of
6260 * instruction emulation. Registers state needs to be copied
4a969980 6261 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6262 * that usually, but some bad designed PV devices (vmware
6263 * backdoor interface) need this to work
6264 */
dd856efa 6265 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6266 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6267 }
5fdbf976
MT		 6268 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6269 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6270 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6271 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6272 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6273 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6274 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6275 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6276#ifdef CONFIG_X86_64
5fdbf976
MT		 6277 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6278 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6279 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6280 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6281 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6282 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6283 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6284 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6285#endif
6286
5fdbf976 6287 regs->rip = kvm_rip_read(vcpu);
91586a3b 6288 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6289
b6c7a5dc
HB		 6290 return 0;
6291}
6292
6293int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6294{
7ae441ea
GN		 6295 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6296 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6297
5fdbf976
MT		 6298 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6299 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6300 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6301 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6302 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6303 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6304 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6305 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6306#ifdef CONFIG_X86_64
5fdbf976
MT		 6307 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6308 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6309 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6310 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6311 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6312 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6313 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6314 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6315#endif
6316
5fdbf976 6317 kvm_rip_write(vcpu, regs->rip);
91586a3b 6318 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6319
b4f14abd
JK		 6320 vcpu->arch.exception.pending = false;
6321
3842d135
AK		 6322 kvm_make_request(KVM_REQ_EVENT, vcpu);
6323
b6c7a5dc
HB		 6324 return 0;
6325}
6326
b6c7a5dc
HB		 6327void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6328{
6329 struct kvm_segment cs;
6330
3e6e0aab 6331 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6332 *db = cs.db;
6333 *l = cs.l;
6334}
6335EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6336
6337int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6338 struct kvm_sregs *sregs)
6339{
89a27f4d 6340 struct desc_ptr dt;
b6c7a5dc 6341
3e6e0aab
GT		 6342 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6343 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6344 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6345 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6346 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6347 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6348
3e6e0aab
GT		 6349 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6350 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6351
6352 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6353 sregs->idt.limit = dt.size;
6354 sregs->idt.base = dt.address;
b6c7a5dc 6355 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6356 sregs->gdt.limit = dt.size;
6357 sregs->gdt.base = dt.address;
b6c7a5dc 6358
4d4ec087 6359 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6360 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6361 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6362 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6363 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6364 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6365 sregs->apic_base = kvm_get_apic_base(vcpu);
6366
923c61bb 6367 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6368
36752c9b 6369 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6370 set_bit(vcpu->arch.interrupt.nr,
6371 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6372
b6c7a5dc
HB		 6373 return 0;
6374}
6375
62d9f0db
MT		 6376int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6377 struct kvm_mp_state *mp_state)
6378{
66450a21 6379 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6380 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6381 vcpu->arch.pv.pv_unhalted)
6382 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6383 else
6384 mp_state->mp_state = vcpu->arch.mp_state;
6385
62d9f0db
MT		 6386 return 0;
6387}
6388
6389int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6390 struct kvm_mp_state *mp_state)
6391{
66450a21
JK		 6392 if (!kvm_vcpu_has_lapic(vcpu) &&
6393 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6394 return -EINVAL;
6395
6396 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6397 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6398 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6399 } else
6400 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6401 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6402 return 0;
6403}
6404
7f3d35fd
KW		 6405int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6406 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6407{
9d74191a 6408 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6409 int ret;
e01c2426 6410
8ec4722d 6411 init_emulate_ctxt(vcpu);
c697518a 6412
7f3d35fd 6413 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6414 has_error_code, error_code);
c697518a 6415
c697518a 6416 if (ret)
19d04437 6417 return EMULATE_FAIL;
37817f29 6418
9d74191a
TY		 6419 kvm_rip_write(vcpu, ctxt->eip);
6420 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6421 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6422 return EMULATE_DONE;
37817f29
IE		 6423}
6424EXPORT_SYMBOL_GPL(kvm_task_switch);
6425
b6c7a5dc
HB		 6426int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6427 struct kvm_sregs *sregs)
6428{
58cb628d 6429 struct msr_data apic_base_msr;
b6c7a5dc 6430 int mmu_reset_needed = 0;
63f42e02 6431 int pending_vec, max_bits, idx;
89a27f4d 6432 struct desc_ptr dt;
b6c7a5dc 6433
6d1068b3
PM		 6434 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6435 return -EINVAL;
6436
89a27f4d
GN		 6437 dt.size = sregs->idt.limit;
6438 dt.address = sregs->idt.base;
b6c7a5dc 6439 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6440 dt.size = sregs->gdt.limit;
6441 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6442 kvm_x86_ops->set_gdt(vcpu, &dt);
6443
ad312c7c 6444 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6445 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6446 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6447 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6448
2d3ad1f4 6449 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6450
f6801dff 6451 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6452 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6453 apic_base_msr.data = sregs->apic_base;
6454 apic_base_msr.host_initiated = true;
6455 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6456
4d4ec087 6457 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6458 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6459 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6460
fc78f519 6461 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6462 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6463 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6464 kvm_update_cpuid(vcpu);
63f42e02
XG		 6465
6466 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6467 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6468 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6469 mmu_reset_needed = 1;
6470 }
63f42e02 6471 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6472
6473 if (mmu_reset_needed)
6474 kvm_mmu_reset_context(vcpu);
6475
a50abc3b 6476 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6477 pending_vec = find_first_bit(
6478 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6479 if (pending_vec < max_bits) {
66fd3f7f 6480 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6481 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6482 }
6483
3e6e0aab
GT		 6484 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6485 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6486 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6487 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6488 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6489 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6490
3e6e0aab
GT		 6491 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6492 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6493
5f0269f5
ME		 6494 update_cr8_intercept(vcpu);
6495
9c3e4aab 6496 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6497 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6498 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6499 !is_protmode(vcpu))
9c3e4aab
MT		 6500 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6501
3842d135
AK		 6502 kvm_make_request(KVM_REQ_EVENT, vcpu);
6503
b6c7a5dc
HB		 6504 return 0;
6505}
6506
d0bfb940
JK		 6507int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6508 struct kvm_guest_debug *dbg)
b6c7a5dc 6509{
355be0b9 6510 unsigned long rflags;
ae675ef0 6511 int i, r;
b6c7a5dc 6512
4f926bf2
JK		 6513 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6514 r = -EBUSY;
6515 if (vcpu->arch.exception.pending)
2122ff5e 6516 goto out;
4f926bf2
JK		 6517 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6518 kvm_queue_exception(vcpu, DB_VECTOR);
6519 else
6520 kvm_queue_exception(vcpu, BP_VECTOR);
6521 }
6522
91586a3b
JK		 6523 /*
6524 * Read rflags as long as potentially injected trace flags are still
6525 * filtered out.
6526 */
6527 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6528
6529 vcpu->guest_debug = dbg->control;
6530 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6531 vcpu->guest_debug = 0;
6532
6533 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6534 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6535 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6536 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6537 } else {
6538 for (i = 0; i < KVM_NR_DB_REGS; i++)
6539 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6540 }
c8639010 6541 kvm_update_dr7(vcpu);
ae675ef0 6542
f92653ee
JK		 6543 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6544 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6545 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6546
91586a3b
JK		 6547 /*
6548 * Trigger an rflags update that will inject or remove the trace
6549 * flags.
6550 */
6551 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6552
c8639010 6553 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6554
4f926bf2 6555 r = 0;
d0bfb940 6556
2122ff5e 6557out:
b6c7a5dc
HB		 6558
6559 return r;
6560}
6561
8b006791
ZX		 6562/*
6563 * Translate a guest virtual address to a guest physical address.
6564 */
6565int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6566 struct kvm_translation *tr)
6567{
6568 unsigned long vaddr = tr->linear_address;
6569 gpa_t gpa;
f656ce01 6570 int idx;
8b006791 6571
f656ce01 6572 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6573 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6574 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6575 tr->physical_address = gpa;
6576 tr->valid = gpa != UNMAPPED_GVA;
6577 tr->writeable = 1;
6578 tr->usermode = 0;
8b006791
ZX		 6579
6580 return 0;
6581}
6582
d0752060
HB		 6583int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6584{
98918833
SY		 6585 struct i387_fxsave_struct *fxsave =
6586 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6587
d0752060
HB		 6588 memcpy(fpu->fpr, fxsave->st_space, 128);
6589 fpu->fcw = fxsave->cwd;
6590 fpu->fsw = fxsave->swd;
6591 fpu->ftwx = fxsave->twd;
6592 fpu->last_opcode = fxsave->fop;
6593 fpu->last_ip = fxsave->rip;
6594 fpu->last_dp = fxsave->rdp;
6595 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6596
d0752060
HB		 6597 return 0;
6598}
6599
6600int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6601{
98918833
SY		 6602 struct i387_fxsave_struct *fxsave =
6603 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6604
d0752060
HB		 6605 memcpy(fxsave->st_space, fpu->fpr, 128);
6606 fxsave->cwd = fpu->fcw;
6607 fxsave->swd = fpu->fsw;
6608 fxsave->twd = fpu->ftwx;
6609 fxsave->fop = fpu->last_opcode;
6610 fxsave->rip = fpu->last_ip;
6611 fxsave->rdp = fpu->last_dp;
6612 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6613
d0752060
HB		 6614 return 0;
6615}
6616
10ab25cd 6617int fx_init(struct kvm_vcpu *vcpu)
d0752060 6618{
10ab25cd
JK		 6619 int err;
6620
6621 err = fpu_alloc(&vcpu->arch.guest_fpu);
6622 if (err)
6623 return err;
6624
98918833 6625 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6626
2acf923e
DC		 6627 /*
6628 * Ensure guest xcr0 is valid for loading
6629 */
6630 vcpu->arch.xcr0 = XSTATE_FP;
6631
ad312c7c 6632 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6633
6634 return 0;
d0752060
HB		 6635}
6636EXPORT_SYMBOL_GPL(fx_init);
6637
98918833
SY		 6638static void fx_free(struct kvm_vcpu *vcpu)
6639{
6640 fpu_free(&vcpu->arch.guest_fpu);
6641}
6642
d0752060
HB		 6643void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6644{
2608d7a1 6645 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6646 return;
6647
2acf923e
DC		 6648 /*
6649 * Restore all possible states in the guest,
6650 * and assume host would use all available bits.
6651 * Guest xcr0 would be loaded later.
6652 */
6653 kvm_put_guest_xcr0(vcpu);
d0752060 6654 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6655 __kernel_fpu_begin();
98918833 6656 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6657 trace_kvm_fpu(1);
d0752060 6658}
d0752060
HB		 6659
6660void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6661{
2acf923e
DC		 6662 kvm_put_guest_xcr0(vcpu);
6663
d0752060
HB		 6664 if (!vcpu->guest_fpu_loaded)
6665 return;
6666
6667 vcpu->guest_fpu_loaded = 0;
98918833 6668 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6669 __kernel_fpu_end();
f096ed85 6670 ++vcpu->stat.fpu_reload;
a8eeb04a 6671 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6672 trace_kvm_fpu(0);
d0752060 6673}
e9b11c17
ZX		 6674
6675void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6676{
12f9a48f 6677 kvmclock_reset(vcpu);
7f1ea208 6678
f5f48ee1 6679 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6680 fx_free(vcpu);
e9b11c17
ZX		 6681 kvm_x86_ops->vcpu_free(vcpu);
6682}
6683
6684struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6685 unsigned int id)
6686{
6755bae8
ZA		 6687 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6688 printk_once(KERN_WARNING
6689 "kvm: SMP vm created on host with unstable TSC; "
6690 "guest TSC will not be reliable\n");
26e5215f
AK		 6691 return kvm_x86_ops->vcpu_create(kvm, id);
6692}
e9b11c17 6693
26e5215f
AK		 6694int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6695{
6696 int r;
e9b11c17 6697
0bed3b56 6698 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6699 r = vcpu_load(vcpu);
6700 if (r)
6701 return r;
57f252f2 6702 kvm_vcpu_reset(vcpu);
8a3c1a33 6703 kvm_mmu_setup(vcpu);
e9b11c17 6704 vcpu_put(vcpu);
e9b11c17 6705
26e5215f 6706 return r;
e9b11c17
ZX		 6707}
6708
42897d86
MT		 6709int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6710{
6711 int r;
8fe8ab46 6712 struct msr_data msr;
42897d86
MT		 6713
6714 r = vcpu_load(vcpu);
6715 if (r)
6716 return r;
8fe8ab46
WA		 6717 msr.data = 0x0;
6718 msr.index = MSR_IA32_TSC;
6719 msr.host_initiated = true;
6720 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6721 vcpu_put(vcpu);
6722
6723 return r;
6724}
6725
d40ccc62 6726void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6727{
9fc77441 6728 int r;
344d9588
GN		 6729 vcpu->arch.apf.msr_val = 0;
6730
9fc77441
MT		 6731 r = vcpu_load(vcpu);
6732 BUG_ON(r);
e9b11c17
ZX		 6733 kvm_mmu_unload(vcpu);
6734 vcpu_put(vcpu);
6735
98918833 6736 fx_free(vcpu);
e9b11c17
ZX		 6737 kvm_x86_ops->vcpu_free(vcpu);
6738}
6739
66450a21 6740void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6741{
7460fb4a
AK		 6742 atomic_set(&vcpu->arch.nmi_queued, 0);
6743 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6744 vcpu->arch.nmi_injected = false;
6745
42dbaa5a
JK		 6746 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6747 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6748 kvm_update_dr6(vcpu);
42dbaa5a 6749 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6750 kvm_update_dr7(vcpu);
42dbaa5a 6751
3842d135 6752 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6753 vcpu->arch.apf.msr_val = 0;
c9aaa895 6754 vcpu->arch.st.msr_val = 0;
3842d135 6755
12f9a48f
GC		 6756 kvmclock_reset(vcpu);
6757
af585b92
GN		 6758 kvm_clear_async_pf_completion_queue(vcpu);
6759 kvm_async_pf_hash_reset(vcpu);
6760 vcpu->arch.apf.halted = false;
3842d135 6761
f5132b01
GN		 6762 kvm_pmu_reset(vcpu);
6763
66f7b72e
JS		 6764 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6765 vcpu->arch.regs_avail = ~0;
6766 vcpu->arch.regs_dirty = ~0;
6767
57f252f2 6768 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6769}
6770
66450a21
JK		 6771void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6772{
6773 struct kvm_segment cs;
6774
6775 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6776 cs.selector = vector << 8;
6777 cs.base = vector << 12;
6778 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6779 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6780}
6781
10474ae8 6782int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6783{
ca84d1a2
ZA		 6784 struct kvm *kvm;
6785 struct kvm_vcpu *vcpu;
6786 int i;
0dd6a6ed
ZA		 6787 int ret;
6788 u64 local_tsc;
6789 u64 max_tsc = 0;
6790 bool stable, backwards_tsc = false;
18863bdd
AK		 6791
6792 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6793 ret = kvm_x86_ops->hardware_enable(garbage);
6794 if (ret != 0)
6795 return ret;
6796
6797 local_tsc = native_read_tsc();
6798 stable = !check_tsc_unstable();
6799 list_for_each_entry(kvm, &vm_list, vm_list) {
6800 kvm_for_each_vcpu(i, vcpu, kvm) {
6801 if (!stable && vcpu->cpu == smp_processor_id())
6802 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6803 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6804 backwards_tsc = true;
6805 if (vcpu->arch.last_host_tsc > max_tsc)
6806 max_tsc = vcpu->arch.last_host_tsc;
6807 }
6808 }
6809 }
6810
6811 /*
6812 * Sometimes, even reliable TSCs go backwards. This happens on
6813 * platforms that reset TSC during suspend or hibernate actions, but
6814 * maintain synchronization. We must compensate. Fortunately, we can
6815 * detect that condition here, which happens early in CPU bringup,
6816 * before any KVM threads can be running. Unfortunately, we can't
6817 * bring the TSCs fully up to date with real time, as we aren't yet far
6818 * enough into CPU bringup that we know how much real time has actually
6819 * elapsed; our helper function, get_kernel_ns() will be using boot
6820 * variables that haven't been updated yet.
6821 *
6822 * So we simply find the maximum observed TSC above, then record the
6823 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6824 * the adjustment will be applied. Note that we accumulate
6825 * adjustments, in case multiple suspend cycles happen before some VCPU
6826 * gets a chance to run again. In the event that no KVM threads get a
6827 * chance to run, we will miss the entire elapsed period, as we'll have
6828 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6829 * loose cycle time. This isn't too big a deal, since the loss will be
6830 * uniform across all VCPUs (not to mention the scenario is extremely
6831 * unlikely). It is possible that a second hibernate recovery happens
6832 * much faster than a first, causing the observed TSC here to be
6833 * smaller; this would require additional padding adjustment, which is
6834 * why we set last_host_tsc to the local tsc observed here.
6835 *
6836 * N.B. - this code below runs only on platforms with reliable TSC,
6837 * as that is the only way backwards_tsc is set above. Also note
6838 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6839 * have the same delta_cyc adjustment applied if backwards_tsc
6840 * is detected. Note further, this adjustment is only done once,
6841 * as we reset last_host_tsc on all VCPUs to stop this from being
6842 * called multiple times (one for each physical CPU bringup).
6843 *
4a969980 6844 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6845 * will be compensated by the logic in vcpu_load, which sets the TSC to
6846 * catchup mode. This will catchup all VCPUs to real time, but cannot
6847 * guarantee that they stay in perfect synchronization.
6848 */
6849 if (backwards_tsc) {
6850 u64 delta_cyc = max_tsc - local_tsc;
6851 list_for_each_entry(kvm, &vm_list, vm_list) {
6852 kvm_for_each_vcpu(i, vcpu, kvm) {
6853 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6854 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6855 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6856 &vcpu->requests);
0dd6a6ed
ZA		 6857 }
6858
6859 /*
6860 * We have to disable TSC offset matching.. if you were
6861 * booting a VM while issuing an S4 host suspend....
6862 * you may have some problem. Solving this issue is
6863 * left as an exercise to the reader.
6864 */
6865 kvm->arch.last_tsc_nsec = 0;
6866 kvm->arch.last_tsc_write = 0;
6867 }
6868
6869 }
6870 return 0;
e9b11c17
ZX		 6871}
6872
6873void kvm_arch_hardware_disable(void *garbage)
6874{
6875 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6876 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6877}
6878
6879int kvm_arch_hardware_setup(void)
6880{
6881 return kvm_x86_ops->hardware_setup();
6882}
6883
6884void kvm_arch_hardware_unsetup(void)
6885{
6886 kvm_x86_ops->hardware_unsetup();
6887}
6888
6889void kvm_arch_check_processor_compat(void *rtn)
6890{
6891 kvm_x86_ops->check_processor_compatibility(rtn);
6892}
6893
3e515705
AK		 6894bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6895{
6896 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6897}
6898
54e9818f
GN		 6899struct static_key kvm_no_apic_vcpu __read_mostly;
6900
e9b11c17
ZX		 6901int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6902{
6903 struct page *page;
6904 struct kvm *kvm;
6905 int r;
6906
6907 BUG_ON(vcpu->kvm == NULL);
6908 kvm = vcpu->kvm;
6909
6aef266c 6910 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6911 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6912 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6913 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6914 else
a4535290 6915 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6916
6917 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6918 if (!page) {
6919 r = -ENOMEM;
6920 goto fail;
6921 }
ad312c7c 6922 vcpu->arch.pio_data = page_address(page);
e9b11c17 6923
cc578287 6924 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6925
e9b11c17
ZX		 6926 r = kvm_mmu_create(vcpu);
6927 if (r < 0)
6928 goto fail_free_pio_data;
6929
6930 if (irqchip_in_kernel(kvm)) {
6931 r = kvm_create_lapic(vcpu);
6932 if (r < 0)
6933 goto fail_mmu_destroy;
54e9818f
GN		 6934 } else
6935 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6936
890ca9ae
HY		 6937 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6938 GFP_KERNEL);
6939 if (!vcpu->arch.mce_banks) {
6940 r = -ENOMEM;
443c39bc 6941 goto fail_free_lapic;
890ca9ae
HY		 6942 }
6943 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6944
f1797359
WY		 6945 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6946 r = -ENOMEM;
f5f48ee1 6947 goto fail_free_mce_banks;
f1797359 6948 }
f5f48ee1 6949
66f7b72e
JS		 6950 r = fx_init(vcpu);
6951 if (r)
6952 goto fail_free_wbinvd_dirty_mask;
6953
ba904635 6954 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6955 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 6956
6957 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 6958 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 6959
af585b92 6960 kvm_async_pf_hash_reset(vcpu);
f5132b01 6961 kvm_pmu_init(vcpu);
af585b92 6962
e9b11c17 6963 return 0;
66f7b72e
JS		 6964fail_free_wbinvd_dirty_mask:
6965 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6966fail_free_mce_banks:
6967 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6968fail_free_lapic:
6969 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6970fail_mmu_destroy:
6971 kvm_mmu_destroy(vcpu);
6972fail_free_pio_data:
ad312c7c 6973 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6974fail:
6975 return r;
6976}
6977
6978void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6979{
f656ce01
MT		 6980 int idx;
6981
f5132b01 6982 kvm_pmu_destroy(vcpu);
36cb93fd 6983 kfree(vcpu->arch.mce_banks);
e9b11c17 6984 kvm_free_lapic(vcpu);
f656ce01 6985 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6986 kvm_mmu_destroy(vcpu);
f656ce01 6987 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6988 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6989 if (!irqchip_in_kernel(vcpu->kvm))
6990 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6991}
d19a9cd2 6992
e08b9637 6993int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6994{
e08b9637
CO		 6995 if (type)
6996 return -EINVAL;
6997
f05e70ac 6998 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 6999 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7000 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7001 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7002
5550af4d
SY		 7003 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7004 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7005 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7006 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7007 &kvm->arch.irq_sources_bitmap);
5550af4d 7008
038f8c11 7009 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7010 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7011 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7012
7013 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7014
d89f5eff 7015 return 0;
d19a9cd2
ZX		 7016}
7017
7018static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7019{
9fc77441
MT		 7020 int r;
7021 r = vcpu_load(vcpu);
7022 BUG_ON(r);
d19a9cd2
ZX		 7023 kvm_mmu_unload(vcpu);
7024 vcpu_put(vcpu);
7025}
7026
7027static void kvm_free_vcpus(struct kvm *kvm)
7028{
7029 unsigned int i;
988a2cae 7030 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7031
7032 /*
7033 * Unpin any mmu pages first.
7034 */
af585b92
GN		 7035 kvm_for_each_vcpu(i, vcpu, kvm) {
7036 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7037 kvm_unload_vcpu_mmu(vcpu);
af585b92 7038 }
988a2cae
GN		 7039 kvm_for_each_vcpu(i, vcpu, kvm)
7040 kvm_arch_vcpu_free(vcpu);
7041
7042 mutex_lock(&kvm->lock);
7043 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7044 kvm->vcpus[i] = NULL;
d19a9cd2 7045
988a2cae
GN		 7046 atomic_set(&kvm->online_vcpus, 0);
7047 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7048}
7049
ad8ba2cd
SY		 7050void kvm_arch_sync_events(struct kvm *kvm)
7051{
ba4cef31 7052 kvm_free_all_assigned_devices(kvm);
aea924f6 7053 kvm_free_pit(kvm);
ad8ba2cd
SY		 7054}
7055
d19a9cd2
ZX		 7056void kvm_arch_destroy_vm(struct kvm *kvm)
7057{
27469d29
AH		 7058 if (current->mm == kvm->mm) {
7059 /*
7060 * Free memory regions allocated on behalf of userspace,
7061 * unless the the memory map has changed due to process exit
7062 * or fd copying.
7063 */
7064 struct kvm_userspace_memory_region mem;
7065 memset(&mem, 0, sizeof(mem));
7066 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7067 kvm_set_memory_region(kvm, &mem);
7068
7069 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7070 kvm_set_memory_region(kvm, &mem);
7071
7072 mem.slot = TSS_PRIVATE_MEMSLOT;
7073 kvm_set_memory_region(kvm, &mem);
7074 }
6eb55818 7075 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7076 kfree(kvm->arch.vpic);
7077 kfree(kvm->arch.vioapic);
d19a9cd2 7078 kvm_free_vcpus(kvm);
3d45830c
AK		 7079 if (kvm->arch.apic_access_page)
7080 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7081 if (kvm->arch.ept_identity_pagetable)
7082 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7083 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7084}
0de10343 7085
5587027c 7086void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7087 struct kvm_memory_slot *dont)
7088{
7089 int i;
7090
d89cc617
TY		 7091 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7092 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7093 kvm_kvfree(free->arch.rmap[i]);
7094 free->arch.rmap[i] = NULL;
77d11309 7095 }
d89cc617
TY		 7096 if (i == 0)
7097 continue;
7098
7099 if (!dont || free->arch.lpage_info[i - 1] !=
7100 dont->arch.lpage_info[i - 1]) {
7101 kvm_kvfree(free->arch.lpage_info[i - 1]);
7102 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7103 }
7104 }
7105}
7106
5587027c
AK		 7107int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7108 unsigned long npages)
db3fe4eb
TY		 7109{
7110 int i;
7111
d89cc617 7112 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7113 unsigned long ugfn;
7114 int lpages;
d89cc617 7115 int level = i + 1;
db3fe4eb
TY		 7116
7117 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7118 slot->base_gfn, level) + 1;
7119
d89cc617
TY		 7120 slot->arch.rmap[i] =
7121 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7122 if (!slot->arch.rmap[i])
77d11309 7123 goto out_free;
d89cc617
TY		 7124 if (i == 0)
7125 continue;
77d11309 7126
d89cc617
TY		 7127 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7128 sizeof(*slot->arch.lpage_info[i - 1]));
7129 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7130 goto out_free;
7131
7132 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7133 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7134 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7135 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7136 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7137 /*
7138 * If the gfn and userspace address are not aligned wrt each
7139 * other, or if explicitly asked to, disable large page
7140 * support for this slot
7141 */
7142 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7143 !kvm_largepages_enabled()) {
7144 unsigned long j;
7145
7146 for (j = 0; j < lpages; ++j)
d89cc617 7147 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7148 }
7149 }
7150
7151 return 0;
7152
7153out_free:
d89cc617
TY		 7154 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7155 kvm_kvfree(slot->arch.rmap[i]);
7156 slot->arch.rmap[i] = NULL;
7157 if (i == 0)
7158 continue;
7159
7160 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7161 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7162 }
7163 return -ENOMEM;
7164}
7165
e59dbe09
TY		 7166void kvm_arch_memslots_updated(struct kvm *kvm)
7167{
e6dff7d1
TY		 7168 /*
7169 * memslots->generation has been incremented.
7170 * mmio generation may have reached its maximum value.
7171 */
7172 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7173}
7174
f7784b8e
MT		 7175int kvm_arch_prepare_memory_region(struct kvm *kvm,
7176 struct kvm_memory_slot *memslot,
f7784b8e 7177 struct kvm_userspace_memory_region *mem,
7b6195a9 7178 enum kvm_mr_change change)
0de10343 7179{
7a905b14
TY		 7180 /*
7181 * Only private memory slots need to be mapped here since
7182 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7183 */
7b6195a9 7184 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7185 unsigned long userspace_addr;
604b38ac 7186
7a905b14
TY		 7187 /*
7188 * MAP_SHARED to prevent internal slot pages from being moved
7189 * by fork()/COW.
7190 */
7b6195a9 7191 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7192 PROT_READ | PROT_WRITE,
7193 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7194
7a905b14
TY		 7195 if (IS_ERR((void *)userspace_addr))
7196 return PTR_ERR((void *)userspace_addr);
604b38ac 7197
7a905b14 7198 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7199 }
7200
f7784b8e
MT		 7201 return 0;
7202}
7203
7204void kvm_arch_commit_memory_region(struct kvm *kvm,
7205 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7206 const struct kvm_memory_slot *old,
7207 enum kvm_mr_change change)
f7784b8e
MT		 7208{
7209
8482644a 7210 int nr_mmu_pages = 0;
f7784b8e 7211
8482644a 7212 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7213 int ret;
7214
8482644a
TY		 7215 ret = vm_munmap(old->userspace_addr,
7216 old->npages * PAGE_SIZE);
f7784b8e
MT		 7217 if (ret < 0)
7218 printk(KERN_WARNING
7219 "kvm_vm_ioctl_set_memory_region: "
7220 "failed to munmap memory\n");
7221 }
7222
48c0e4e9
XG		 7223 if (!kvm->arch.n_requested_mmu_pages)
7224 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7225
48c0e4e9 7226 if (nr_mmu_pages)
0de10343 7227 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7228 /*
7229 * Write protect all pages for dirty logging.
7230 * Existing largepage mappings are destroyed here and new ones will
7231 * not be created until the end of the logging.
7232 */
8482644a 7233 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7234 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7235}
1d737c8a 7236
2df72e9b 7237void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7238{
6ca18b69 7239 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7240}
7241
2df72e9b
MT		 7242void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7243 struct kvm_memory_slot *slot)
7244{
6ca18b69 7245 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7246}
7247
1d737c8a
ZX		 7248int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7249{
af585b92
GN		 7250 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7251 !vcpu->arch.apf.halted)
7252 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7253 || kvm_apic_has_events(vcpu)
6aef266c 7254 || vcpu->arch.pv.pv_unhalted
7460fb4a 7255 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7256 (kvm_arch_interrupt_allowed(vcpu) &&
7257 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7258}
5736199a 7259
b6d33834 7260int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7261{
b6d33834 7262 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7263}
78646121
GN		 7264
7265int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7266{
7267 return kvm_x86_ops->interrupt_allowed(vcpu);
7268}
229456fc 7269
f92653ee
JK		 7270bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7271{
7272 unsigned long current_rip = kvm_rip_read(vcpu) +
7273 get_segment_base(vcpu, VCPU_SREG_CS);
7274
7275 return current_rip == linear_rip;
7276}
7277EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7278
94fe45da
JK		 7279unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7280{
7281 unsigned long rflags;
7282
7283 rflags = kvm_x86_ops->get_rflags(vcpu);
7284 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7285 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7286 return rflags;
7287}
7288EXPORT_SYMBOL_GPL(kvm_get_rflags);
7289
7290void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7291{
7292 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7293 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7294 rflags |= X86_EFLAGS_TF;
94fe45da 7295 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7296 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7297}
7298EXPORT_SYMBOL_GPL(kvm_set_rflags);
7299
56028d08
GN		 7300void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7301{
7302 int r;
7303
fb67e14f 7304 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7305 work->wakeup_all)
56028d08
GN		 7306 return;
7307
7308 r = kvm_mmu_reload(vcpu);
7309 if (unlikely(r))
7310 return;
7311
fb67e14f
XG		 7312 if (!vcpu->arch.mmu.direct_map &&
7313 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7314 return;
7315
56028d08
GN		 7316 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7317}
7318
af585b92
GN		 7319static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7320{
7321 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7322}
7323
7324static inline u32 kvm_async_pf_next_probe(u32 key)
7325{
7326 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7327}
7328
7329static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7330{
7331 u32 key = kvm_async_pf_hash_fn(gfn);
7332
7333 while (vcpu->arch.apf.gfns[key] != ~0)
7334 key = kvm_async_pf_next_probe(key);
7335
7336 vcpu->arch.apf.gfns[key] = gfn;
7337}
7338
7339static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7340{
7341 int i;
7342 u32 key = kvm_async_pf_hash_fn(gfn);
7343
7344 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7345 (vcpu->arch.apf.gfns[key] != gfn &&
7346 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7347 key = kvm_async_pf_next_probe(key);
7348
7349 return key;
7350}
7351
7352bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7353{
7354 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7355}
7356
7357static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7358{
7359 u32 i, j, k;
7360
7361 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7362 while (true) {
7363 vcpu->arch.apf.gfns[i] = ~0;
7364 do {
7365 j = kvm_async_pf_next_probe(j);
7366 if (vcpu->arch.apf.gfns[j] == ~0)
7367 return;
7368 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7369 /*
7370 * k lies cyclically in ]i,j]
7371 * | i.k.j |
7372 * |....j i.k.| or |.k..j i...|
7373 */
7374 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7375 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7376 i = j;
7377 }
7378}
7379
7c90705b
GN		 7380static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7381{
7382
7383 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7384 sizeof(val));
7385}
7386
af585b92
GN		 7387void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7388 struct kvm_async_pf *work)
7389{
6389ee94
AK		 7390 struct x86_exception fault;
7391
7c90705b 7392 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7393 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7394
7395 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7396 (vcpu->arch.apf.send_user_only &&
7397 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7398 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7399 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7400 fault.vector = PF_VECTOR;
7401 fault.error_code_valid = true;
7402 fault.error_code = 0;
7403 fault.nested_page_fault = false;
7404 fault.address = work->arch.token;
7405 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7406 }
af585b92
GN		 7407}
7408
7409void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7410 struct kvm_async_pf *work)
7411{
6389ee94
AK		 7412 struct x86_exception fault;
7413
7c90705b 7414 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7415 if (work->wakeup_all)
7c90705b
GN		 7416 work->arch.token = ~0; /* broadcast wakeup */
7417 else
7418 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7419
7420 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7421 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7422 fault.vector = PF_VECTOR;
7423 fault.error_code_valid = true;
7424 fault.error_code = 0;
7425 fault.nested_page_fault = false;
7426 fault.address = work->arch.token;
7427 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7428 }
e6d53e3b 7429 vcpu->arch.apf.halted = false;
a4fa1635 7430 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7431}
7432
7433bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7434{
7435 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7436 return true;
7437 else
7438 return !kvm_event_needs_reinjection(vcpu) &&
7439 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7440}
7441
e0f0bbc5
AW		 7442void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7443{
7444 atomic_inc(&kvm->arch.noncoherent_dma_count);
7445}
7446EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7447
7448void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7449{
7450 atomic_dec(&kvm->arch.noncoherent_dma_count);
7451}
7452EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7453
7454bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7455{
7456 return atomic_read(&kvm->arch.noncoherent_dma_count);
7457}
7458EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7459
229456fc
MT		 7460EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7461EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7462EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7463EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7464EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7465EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7466EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7467EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7468EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7469EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7470EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7471EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7472EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux 6.x block layer and io_uring tree(s)