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x86/KVM/VMX: Add L1D MSR based flush
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 198 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
199 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
200 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
201 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
202 { "mmu_flooded", VM_STAT(mmu_flooded) },
203 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 204 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 205 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 206 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 207 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 208 { "max_mmu_page_hash_collisions",
209 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 210 { NULL }
211};
212
2acf923e
DC		 213u64 __read_mostly host_xcr0;
214
b6785def 215static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 216
af585b92
GN		 217static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
218{
219 int i;
220 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
221 vcpu->arch.apf.gfns[i] = ~0;
222}
223
18863bdd
AK		 224static void kvm_on_user_return(struct user_return_notifier *urn)
225{
226 unsigned slot;
18863bdd
AK		 227 struct kvm_shared_msrs *locals
228 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 229 struct kvm_shared_msr_values *values;
1650b4eb
IA		 230 unsigned long flags;
231
232 /*
233 * Disabling irqs at this point since the following code could be
234 * interrupted and executed through kvm_arch_hardware_disable()
235 */
236 local_irq_save(flags);
237 if (locals->registered) {
238 locals->registered = false;
239 user_return_notifier_unregister(urn);
240 }
241 local_irq_restore(flags);
18863bdd 242 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 243 values = &locals->values[slot];
244 if (values->host != values->curr) {
245 wrmsrl(shared_msrs_global.msrs[slot], values->host);
246 values->curr = values->host;
18863bdd
AK		 247 }
248 }
18863bdd
AK		 249}
250
2bf78fa7 251static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 252{
18863bdd 253 u64 value;
013f6a5d
MT		 254 unsigned int cpu = smp_processor_id();
255 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 256
2bf78fa7
SY		 257 /* only read, and nobody should modify it at this time,
258 * so don't need lock */
259 if (slot >= shared_msrs_global.nr) {
260 printk(KERN_ERR "kvm: invalid MSR slot!");
261 return;
262 }
263 rdmsrl_safe(msr, &value);
264 smsr->values[slot].host = value;
265 smsr->values[slot].curr = value;
266}
267
268void kvm_define_shared_msr(unsigned slot, u32 msr)
269{
0123be42 270 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 271 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 272 if (slot >= shared_msrs_global.nr)
273 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 274}
275EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
276
277static void kvm_shared_msr_cpu_online(void)
278{
279 unsigned i;
18863bdd
AK		 280
281 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 282 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 283}
284
8b3c3104 285int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 286{
013f6a5d
MT		 287 unsigned int cpu = smp_processor_id();
288 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 289 int err;
18863bdd 290
2bf78fa7 291 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 292 return 0;
2bf78fa7 293 smsr->values[slot].curr = value;
8b3c3104
AH		 294 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
295 if (err)
296 return 1;
297
18863bdd
AK		 298 if (!smsr->registered) {
299 smsr->urn.on_user_return = kvm_on_user_return;
300 user_return_notifier_register(&smsr->urn);
301 smsr->registered = true;
302 }
8b3c3104 303 return 0;
18863bdd
AK		 304}
305EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
306
13a34e06 307static void drop_user_return_notifiers(void)
3548bab5 308{
013f6a5d
MT		 309 unsigned int cpu = smp_processor_id();
310 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 311
312 if (smsr->registered)
313 kvm_on_user_return(&smsr->urn);
314}
315
6866b83e
CO		 316u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
317{
8a5a87d9 318 return vcpu->arch.apic_base;
6866b83e
CO		 319}
320EXPORT_SYMBOL_GPL(kvm_get_apic_base);
321
58871649
JM		 322enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
323{
324 return kvm_apic_mode(kvm_get_apic_base(vcpu));
325}
326EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
327
58cb628d
JK		 328int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
329{
58871649
JM		 330 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
331 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 332 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
333 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 334
58871649 335 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 336 return 1;
58871649
JM		 337 if (!msr_info->host_initiated) {
338 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
339 return 1;
340 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
341 return 1;
342 }
58cb628d
JK		 343
344 kvm_lapic_set_base(vcpu, msr_info->data);
345 return 0;
6866b83e
CO		 346}
347EXPORT_SYMBOL_GPL(kvm_set_apic_base);
348
2605fc21 349asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 350{
351 /* Fault while not rebooting. We want the trace. */
352 BUG();
353}
354EXPORT_SYMBOL_GPL(kvm_spurious_fault);
355
3fd28fce
ED		 356#define EXCPT_BENIGN 0
357#define EXCPT_CONTRIBUTORY 1
358#define EXCPT_PF 2
359
360static int exception_class(int vector)
361{
362 switch (vector) {
363 case PF_VECTOR:
364 return EXCPT_PF;
365 case DE_VECTOR:
366 case TS_VECTOR:
367 case NP_VECTOR:
368 case SS_VECTOR:
369 case GP_VECTOR:
370 return EXCPT_CONTRIBUTORY;
371 default:
372 break;
373 }
374 return EXCPT_BENIGN;
375}
376
d6e8c854
NA		 377#define EXCPT_FAULT 0
378#define EXCPT_TRAP 1
379#define EXCPT_ABORT 2
380#define EXCPT_INTERRUPT 3
381
382static int exception_type(int vector)
383{
384 unsigned int mask;
385
386 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
387 return EXCPT_INTERRUPT;
388
389 mask = 1 << vector;
390
391 /* #DB is trap, as instruction watchpoints are handled elsewhere */
392 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
393 return EXCPT_TRAP;
394
395 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
396 return EXCPT_ABORT;
397
398 /* Reserved exceptions will result in fault */
399 return EXCPT_FAULT;
400}
401
3fd28fce 402static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 403 unsigned nr, bool has_error, u32 error_code,
404 bool reinject)
3fd28fce
ED		 405{
406 u32 prev_nr;
407 int class1, class2;
408
3842d135
AK		 409 kvm_make_request(KVM_REQ_EVENT, vcpu);
410
664f8e26 411 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 412 queue:
3ffb2468
NA		 413 if (has_error && !is_protmode(vcpu))
414 has_error = false;
664f8e26
WL		 415 if (reinject) {
416 /*
417 * On vmentry, vcpu->arch.exception.pending is only
418 * true if an event injection was blocked by
419 * nested_run_pending. In that case, however,
420 * vcpu_enter_guest requests an immediate exit,
421 * and the guest shouldn't proceed far enough to
422 * need reinjection.
423 */
424 WARN_ON_ONCE(vcpu->arch.exception.pending);
425 vcpu->arch.exception.injected = true;
426 } else {
427 vcpu->arch.exception.pending = true;
428 vcpu->arch.exception.injected = false;
429 }
3fd28fce
ED		 430 vcpu->arch.exception.has_error_code = has_error;
431 vcpu->arch.exception.nr = nr;
432 vcpu->arch.exception.error_code = error_code;
433 return;
434 }
435
436 /* to check exception */
437 prev_nr = vcpu->arch.exception.nr;
438 if (prev_nr == DF_VECTOR) {
439 /* triple fault -> shutdown */
a8eeb04a 440 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 441 return;
442 }
443 class1 = exception_class(prev_nr);
444 class2 = exception_class(nr);
445 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
446 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 447 /*
448 * Generate double fault per SDM Table 5-5. Set
449 * exception.pending = true so that the double fault
450 * can trigger a nested vmexit.
451 */
3fd28fce 452 vcpu->arch.exception.pending = true;
664f8e26 453 vcpu->arch.exception.injected = false;
3fd28fce
ED		 454 vcpu->arch.exception.has_error_code = true;
455 vcpu->arch.exception.nr = DF_VECTOR;
456 vcpu->arch.exception.error_code = 0;
457 } else
458 /* replace previous exception with a new one in a hope
459 that instruction re-execution will regenerate lost
460 exception */
461 goto queue;
462}
463
298101da
AK		 464void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
465{
ce7ddec4 466 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 467}
468EXPORT_SYMBOL_GPL(kvm_queue_exception);
469
ce7ddec4
JR		 470void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
471{
472 kvm_multiple_exception(vcpu, nr, false, 0, true);
473}
474EXPORT_SYMBOL_GPL(kvm_requeue_exception);
475
6affcbed 476int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 477{
db8fcefa
AP		 478 if (err)
479 kvm_inject_gp(vcpu, 0);
480 else
6affcbed
KH		 481 return kvm_skip_emulated_instruction(vcpu);
482
483 return 1;
db8fcefa
AP		 484}
485EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 486
6389ee94 487void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 488{
489 ++vcpu->stat.pf_guest;
adfe20fb
WL		 490 vcpu->arch.exception.nested_apf =
491 is_guest_mode(vcpu) && fault->async_page_fault;
492 if (vcpu->arch.exception.nested_apf)
493 vcpu->arch.apf.nested_apf_token = fault->address;
494 else
495 vcpu->arch.cr2 = fault->address;
6389ee94 496 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 497}
27d6c865 498EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 499
ef54bcfe 500static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 501{
6389ee94
AK		 502 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
503 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 504 else
6389ee94 505 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 506
507 return fault->nested_page_fault;
d4f8cf66
JR		 508}
509
3419ffc8
SY		 510void kvm_inject_nmi(struct kvm_vcpu *vcpu)
511{
7460fb4a
AK		 512 atomic_inc(&vcpu->arch.nmi_queued);
513 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 514}
515EXPORT_SYMBOL_GPL(kvm_inject_nmi);
516
298101da
AK		 517void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
518{
ce7ddec4 519 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 520}
521EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
522
ce7ddec4
JR		 523void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
524{
525 kvm_multiple_exception(vcpu, nr, true, error_code, true);
526}
527EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
528
0a79b009
AK		 529/*
530 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
531 * a #GP and return false.
532 */
533bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 534{
0a79b009
AK		 535 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
536 return true;
537 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
538 return false;
298101da 539}
0a79b009 540EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 541
16f8a6f9
NA		 542bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
543{
544 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
545 return true;
546
547 kvm_queue_exception(vcpu, UD_VECTOR);
548 return false;
549}
550EXPORT_SYMBOL_GPL(kvm_require_dr);
551
ec92fe44
JR		 552/*
553 * This function will be used to read from the physical memory of the currently
54bf36aa 554 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 555 * can read from guest physical or from the guest's guest physical memory.
556 */
557int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
558 gfn_t ngfn, void *data, int offset, int len,
559 u32 access)
560{
54987b7a 561 struct x86_exception exception;
ec92fe44
JR		 562 gfn_t real_gfn;
563 gpa_t ngpa;
564
565 ngpa = gfn_to_gpa(ngfn);
54987b7a 566 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 567 if (real_gfn == UNMAPPED_GVA)
568 return -EFAULT;
569
570 real_gfn = gpa_to_gfn(real_gfn);
571
54bf36aa 572 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 573}
574EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
575
69b0049a 576static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 577 void *data, int offset, int len, u32 access)
578{
579 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
580 data, offset, len, access);
581}
582
a03490ed
CO		 583/*
584 * Load the pae pdptrs. Return true is they are all valid.
585 */
ff03a073 586int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 587{
588 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
589 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
590 int i;
591 int ret;
ff03a073 592 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 593
ff03a073
JR		 594 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
595 offset * sizeof(u64), sizeof(pdpte),
596 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 597 if (ret < 0) {
598 ret = 0;
599 goto out;
600 }
601 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 602 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 603 (pdpte[i] &
604 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 605 ret = 0;
606 goto out;
607 }
608 }
609 ret = 1;
610
ff03a073 611 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 612 __set_bit(VCPU_EXREG_PDPTR,
613 (unsigned long *)&vcpu->arch.regs_avail);
614 __set_bit(VCPU_EXREG_PDPTR,
615 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 616out:
a03490ed
CO		 617
618 return ret;
619}
cc4b6871 620EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 621
9ed38ffa 622bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 623{
ff03a073 624 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 625 bool changed = true;
3d06b8bf
JR		 626 int offset;
627 gfn_t gfn;
d835dfec
AK		 628 int r;
629
630 if (is_long_mode(vcpu) || !is_pae(vcpu))
631 return false;
632
6de4f3ad
AK		 633 if (!test_bit(VCPU_EXREG_PDPTR,
634 (unsigned long *)&vcpu->arch.regs_avail))
635 return true;
636
a512177e
PB		 637 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
638 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 639 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
640 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 641 if (r < 0)
642 goto out;
ff03a073 643 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 644out:
d835dfec
AK		 645
646 return changed;
647}
9ed38ffa 648EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 649
49a9b07e 650int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 651{
aad82703 652 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 653 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 654
f9a48e6a
AK		 655 cr0 |= X86_CR0_ET;
656
ab344828 657#ifdef CONFIG_X86_64
0f12244f
GN		 658 if (cr0 & 0xffffffff00000000UL)
659 return 1;
ab344828
GN		 660#endif
661
662 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 663
0f12244f
GN		 664 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
665 return 1;
a03490ed 666
0f12244f
GN		 667 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
668 return 1;
a03490ed
CO		 669
670 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
671#ifdef CONFIG_X86_64
f6801dff 672 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 673 int cs_db, cs_l;
674
0f12244f
GN		 675 if (!is_pae(vcpu))
676 return 1;
a03490ed 677 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 678 if (cs_l)
679 return 1;
a03490ed
CO		 680 } else
681#endif
ff03a073 682 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 683 kvm_read_cr3(vcpu)))
0f12244f 684 return 1;
a03490ed
CO		 685 }
686
ad756a16
MJ		 687 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
688 return 1;
689
a03490ed 690 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 691
d170c419 692 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 693 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 694 kvm_async_pf_hash_reset(vcpu);
695 }
e5f3f027 696
aad82703
SY		 697 if ((cr0 ^ old_cr0) & update_bits)
698 kvm_mmu_reset_context(vcpu);
b18d5431 699
879ae188
LE		 700 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
701 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
702 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 703 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
704
0f12244f
GN		 705 return 0;
706}
2d3ad1f4 707EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 708
2d3ad1f4 709void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 710{
49a9b07e 711 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 712}
2d3ad1f4 713EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 714
42bdf991
MT		 715static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
716{
717 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
718 !vcpu->guest_xcr0_loaded) {
719 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 720 if (vcpu->arch.xcr0 != host_xcr0)
721 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 722 vcpu->guest_xcr0_loaded = 1;
723 }
724}
725
726static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
727{
728 if (vcpu->guest_xcr0_loaded) {
729 if (vcpu->arch.xcr0 != host_xcr0)
730 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
731 vcpu->guest_xcr0_loaded = 0;
732 }
733}
734
69b0049a 735static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 736{
56c103ec
LJ		 737 u64 xcr0 = xcr;
738 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 739 u64 valid_bits;
2acf923e
DC		 740
741 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
742 if (index != XCR_XFEATURE_ENABLED_MASK)
743 return 1;
d91cab78 744 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 745 return 1;
d91cab78 746 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 747 return 1;
46c34cb0
PB		 748
749 /*
750 * Do not allow the guest to set bits that we do not support
751 * saving. However, xcr0 bit 0 is always set, even if the
752 * emulated CPU does not support XSAVE (see fx_init).
753 */
d91cab78 754 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 755 if (xcr0 & ~valid_bits)
2acf923e 756 return 1;
46c34cb0 757
d91cab78
DH		 758 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
759 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 760 return 1;
761
d91cab78
DH		 762 if (xcr0 & XFEATURE_MASK_AVX512) {
763 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 764 return 1;
d91cab78 765 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 766 return 1;
767 }
2acf923e 768 vcpu->arch.xcr0 = xcr0;
56c103ec 769
d91cab78 770 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 771 kvm_update_cpuid(vcpu);
2acf923e
DC		 772 return 0;
773}
774
775int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
776{
764bcbc5
Z		 777 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
778 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 779 kvm_inject_gp(vcpu, 0);
780 return 1;
781 }
782 return 0;
783}
784EXPORT_SYMBOL_GPL(kvm_set_xcr);
785
a83b29c6 786int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 787{
fc78f519 788 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 789 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 790 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 791
0f12244f
GN		 792 if (cr4 & CR4_RESERVED_BITS)
793 return 1;
a03490ed 794
d6321d49 795 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 796 return 1;
797
d6321d49 798 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 799 return 1;
800
d6321d49 801 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 802 return 1;
803
d6321d49 804 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 805 return 1;
806
d6321d49 807 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 808 return 1;
809
fd8cb433 810 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 811 return 1;
812
ae3e61e1
PB		 813 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
814 return 1;
815
a03490ed 816 if (is_long_mode(vcpu)) {
0f12244f
GN		 817 if (!(cr4 & X86_CR4_PAE))
818 return 1;
a2edf57f
AK		 819 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
820 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 821 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
822 kvm_read_cr3(vcpu)))
0f12244f
GN		 823 return 1;
824
ad756a16 825 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 826 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 827 return 1;
828
829 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
830 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
831 return 1;
832 }
833
5e1746d6 834 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 835 return 1;
a03490ed 836
ad756a16
MJ		 837 if (((cr4 ^ old_cr4) & pdptr_bits) ||
838 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 839 kvm_mmu_reset_context(vcpu);
0f12244f 840
b9baba86 841 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 842 kvm_update_cpuid(vcpu);
2acf923e 843
0f12244f
GN		 844 return 0;
845}
2d3ad1f4 846EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 847
2390218b 848int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 849{
ac146235 850#ifdef CONFIG_X86_64
c19986fe
JS		 851 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
852
853 if (pcid_enabled)
854 cr3 &= ~CR3_PCID_INVD;
ac146235 855#endif
9d88fca7 856
9f8fe504 857 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 858 kvm_mmu_sync_roots(vcpu);
77c3913b 859 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 860 return 0;
d835dfec
AK		 861 }
862
d1cd3ce9 863 if (is_long_mode(vcpu) &&
a780a3ea 864 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 865 return 1;
866 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 867 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 868 return 1;
a03490ed 869
0f12244f 870 vcpu->arch.cr3 = cr3;
aff48baa 871 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 872 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 873 return 0;
874}
2d3ad1f4 875EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 876
eea1cff9 877int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 878{
0f12244f
GN		 879 if (cr8 & CR8_RESERVED_BITS)
880 return 1;
35754c98 881 if (lapic_in_kernel(vcpu))
a03490ed
CO		 882 kvm_lapic_set_tpr(vcpu, cr8);
883 else
ad312c7c 884 vcpu->arch.cr8 = cr8;
0f12244f
GN		 885 return 0;
886}
2d3ad1f4 887EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 888
2d3ad1f4 889unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 890{
35754c98 891 if (lapic_in_kernel(vcpu))
a03490ed
CO		 892 return kvm_lapic_get_cr8(vcpu);
893 else
ad312c7c 894 return vcpu->arch.cr8;
a03490ed 895}
2d3ad1f4 896EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 897
ae561ede
NA		 898static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
899{
900 int i;
901
902 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
903 for (i = 0; i < KVM_NR_DB_REGS; i++)
904 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
905 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
906 }
907}
908
73aaf249
JK		 909static void kvm_update_dr6(struct kvm_vcpu *vcpu)
910{
911 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
912 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
913}
914
c8639010
JK		 915static void kvm_update_dr7(struct kvm_vcpu *vcpu)
916{
917 unsigned long dr7;
918
919 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
920 dr7 = vcpu->arch.guest_debug_dr7;
921 else
922 dr7 = vcpu->arch.dr7;
923 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 924 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
925 if (dr7 & DR7_BP_EN_MASK)
926 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 927}
928
6f43ed01
NA		 929static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
930{
931 u64 fixed = DR6_FIXED_1;
932
d6321d49 933 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 934 fixed |= DR6_RTM;
935 return fixed;
936}
937
338dbc97 938static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 939{
940 switch (dr) {
941 case 0 ... 3:
942 vcpu->arch.db[dr] = val;
943 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
944 vcpu->arch.eff_db[dr] = val;
945 break;
946 case 4:
020df079
GN		 947 /* fall through */
948 case 6:
338dbc97
GN		 949 if (val & 0xffffffff00000000ULL)
950 return -1; /* #GP */
6f43ed01 951 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 952 kvm_update_dr6(vcpu);
020df079
GN		 953 break;
954 case 5:
020df079
GN		 955 /* fall through */
956 default: /* 7 */
338dbc97
GN		 957 if (val & 0xffffffff00000000ULL)
958 return -1; /* #GP */
020df079 959 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 960 kvm_update_dr7(vcpu);
020df079
GN		 961 break;
962 }
963
964 return 0;
965}
338dbc97
GN		 966
967int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
968{
16f8a6f9 969 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 970 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 971 return 1;
972 }
973 return 0;
338dbc97 974}
020df079
GN		 975EXPORT_SYMBOL_GPL(kvm_set_dr);
976
16f8a6f9 977int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 978{
979 switch (dr) {
980 case 0 ... 3:
981 *val = vcpu->arch.db[dr];
982 break;
983 case 4:
020df079
GN		 984 /* fall through */
985 case 6:
73aaf249
JK		 986 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
987 *val = vcpu->arch.dr6;
988 else
989 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 990 break;
991 case 5:
020df079
GN		 992 /* fall through */
993 default: /* 7 */
994 *val = vcpu->arch.dr7;
995 break;
996 }
338dbc97
GN		 997 return 0;
998}
020df079
GN		 999EXPORT_SYMBOL_GPL(kvm_get_dr);
1000
022cd0e8
AK		 1001bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1002{
1003 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1004 u64 data;
1005 int err;
1006
c6702c9d 1007 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1008 if (err)
1009 return err;
1010 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1011 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1012 return err;
1013}
1014EXPORT_SYMBOL_GPL(kvm_rdpmc);
1015
043405e1
CO		 1016/*
1017 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1018 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1019 *
1020 * This list is modified at module load time to reflect the
e3267cbb 1021 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1022 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1023 * may depend on host virtualization features rather than host cpu features.
043405e1 1024 */
e3267cbb 1025
043405e1
CO		 1026static u32 msrs_to_save[] = {
1027 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1028 MSR_STAR,
043405e1
CO		 1029#ifdef CONFIG_X86_64
1030 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1031#endif
b3897a49 1032 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1033 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1034 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1035};
1036
1037static unsigned num_msrs_to_save;
1038
62ef68bb
PB		 1039static u32 emulated_msrs[] = {
1040 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1041 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1042 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1043 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1044 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1045 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1046 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1047 HV_X64_MSR_RESET,
11c4b1ca 1048 HV_X64_MSR_VP_INDEX,
9eec50b8 1049 HV_X64_MSR_VP_RUNTIME,
5c919412 1050 HV_X64_MSR_SCONTROL,
1f4b34f8 1051 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1052 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1053 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1054 HV_X64_MSR_TSC_EMULATION_STATUS,
1055
1056 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1057 MSR_KVM_PV_EOI_EN,
1058
ba904635 1059 MSR_IA32_TSC_ADJUST,
a3e06bbe 1060 MSR_IA32_TSCDEADLINE,
043405e1 1061 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1062 MSR_IA32_MCG_STATUS,
1063 MSR_IA32_MCG_CTL,
c45dcc71 1064 MSR_IA32_MCG_EXT_CTL,
64d60670 1065 MSR_IA32_SMBASE,
52797bf9 1066 MSR_SMI_COUNT,
db2336a8
KH		 1067 MSR_PLATFORM_INFO,
1068 MSR_MISC_FEATURES_ENABLES,
bc226f07 1069 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1070};
1071
62ef68bb
PB		 1072static unsigned num_emulated_msrs;
1073
801e459a
TL		 1074/*
1075 * List of msr numbers which are used to expose MSR-based features that
1076 * can be used by a hypervisor to validate requested CPU features.
1077 */
1078static u32 msr_based_features[] = {
1389309c
PB		 1079 MSR_IA32_VMX_BASIC,
1080 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1081 MSR_IA32_VMX_PINBASED_CTLS,
1082 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1083 MSR_IA32_VMX_PROCBASED_CTLS,
1084 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1085 MSR_IA32_VMX_EXIT_CTLS,
1086 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1087 MSR_IA32_VMX_ENTRY_CTLS,
1088 MSR_IA32_VMX_MISC,
1089 MSR_IA32_VMX_CR0_FIXED0,
1090 MSR_IA32_VMX_CR0_FIXED1,
1091 MSR_IA32_VMX_CR4_FIXED0,
1092 MSR_IA32_VMX_CR4_FIXED1,
1093 MSR_IA32_VMX_VMCS_ENUM,
1094 MSR_IA32_VMX_PROCBASED_CTLS2,
1095 MSR_IA32_VMX_EPT_VPID_CAP,
1096 MSR_IA32_VMX_VMFUNC,
1097
d1d93fa9 1098 MSR_F10H_DECFG,
518e7b94 1099 MSR_IA32_UCODE_REV,
801e459a
TL		 1100};
1101
1102static unsigned int num_msr_based_features;
1103
66421c1e
WL		 1104static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1105{
1106 switch (msr->index) {
518e7b94
WL		 1107 case MSR_IA32_UCODE_REV:
1108 rdmsrl(msr->index, msr->data);
1109 break;
66421c1e
WL		 1110 default:
1111 if (kvm_x86_ops->get_msr_feature(msr))
1112 return 1;
1113 }
1114 return 0;
1115}
1116
801e459a
TL		 1117static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1118{
1119 struct kvm_msr_entry msr;
66421c1e 1120 int r;
801e459a
TL		 1121
1122 msr.index = index;
66421c1e
WL		 1123 r = kvm_get_msr_feature(&msr);
1124 if (r)
1125 return r;
801e459a
TL		 1126
1127 *data = msr.data;
1128
1129 return 0;
1130}
1131
384bb783 1132bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1133{
b69e8cae 1134 if (efer & efer_reserved_bits)
384bb783 1135 return false;
15c4a640 1136
1b4d56b8 1137 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1138 return false;
1b2fd70c 1139
1b4d56b8 1140 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1141 return false;
d8017474 1142
384bb783
JK		 1143 return true;
1144}
1145EXPORT_SYMBOL_GPL(kvm_valid_efer);
1146
1147static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1148{
1149 u64 old_efer = vcpu->arch.efer;
1150
1151 if (!kvm_valid_efer(vcpu, efer))
1152 return 1;
1153
1154 if (is_paging(vcpu)
1155 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1156 return 1;
1157
15c4a640 1158 efer &= ~EFER_LMA;
f6801dff 1159 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1160
a3d204e2
SY		 1161 kvm_x86_ops->set_efer(vcpu, efer);
1162
aad82703
SY		 1163 /* Update reserved bits */
1164 if ((efer ^ old_efer) & EFER_NX)
1165 kvm_mmu_reset_context(vcpu);
1166
b69e8cae 1167 return 0;
15c4a640
CO		 1168}
1169
f2b4b7dd
JR		 1170void kvm_enable_efer_bits(u64 mask)
1171{
1172 efer_reserved_bits &= ~mask;
1173}
1174EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1175
15c4a640
CO		 1176/*
1177 * Writes msr value into into the appropriate "register".
1178 * Returns 0 on success, non-0 otherwise.
1179 * Assumes vcpu_load() was already called.
1180 */
8fe8ab46 1181int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1182{
854e8bb1
NA		 1183 switch (msr->index) {
1184 case MSR_FS_BASE:
1185 case MSR_GS_BASE:
1186 case MSR_KERNEL_GS_BASE:
1187 case MSR_CSTAR:
1188 case MSR_LSTAR:
fd8cb433 1189 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1190 return 1;
1191 break;
1192 case MSR_IA32_SYSENTER_EIP:
1193 case MSR_IA32_SYSENTER_ESP:
1194 /*
1195 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1196 * non-canonical address is written on Intel but not on
1197 * AMD (which ignores the top 32-bits, because it does
1198 * not implement 64-bit SYSENTER).
1199 *
1200 * 64-bit code should hence be able to write a non-canonical
1201 * value on AMD. Making the address canonical ensures that
1202 * vmentry does not fail on Intel after writing a non-canonical
1203 * value, and that something deterministic happens if the guest
1204 * invokes 64-bit SYSENTER.
1205 */
fd8cb433 1206 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1207 }
8fe8ab46 1208 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1209}
854e8bb1 1210EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1211
313a3dc7
CO		 1212/*
1213 * Adapt set_msr() to msr_io()'s calling convention
1214 */
609e36d3
PB		 1215static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1216{
1217 struct msr_data msr;
1218 int r;
1219
1220 msr.index = index;
1221 msr.host_initiated = true;
1222 r = kvm_get_msr(vcpu, &msr);
1223 if (r)
1224 return r;
1225
1226 *data = msr.data;
1227 return 0;
1228}
1229
313a3dc7
CO		 1230static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1231{
8fe8ab46
WA		 1232 struct msr_data msr;
1233
1234 msr.data = *data;
1235 msr.index = index;
1236 msr.host_initiated = true;
1237 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1238}
1239
16e8d74d
MT		 1240#ifdef CONFIG_X86_64
1241struct pvclock_gtod_data {
1242 seqcount_t seq;
1243
1244 struct { /* extract of a clocksource struct */
1245 int vclock_mode;
a5a1d1c2
TG		 1246 u64 cycle_last;
1247 u64 mask;
16e8d74d
MT		 1248 u32 mult;
1249 u32 shift;
1250 } clock;
1251
cbcf2dd3
TG		 1252 u64 boot_ns;
1253 u64 nsec_base;
55dd00a7 1254 u64 wall_time_sec;
16e8d74d
MT		 1255};
1256
1257static struct pvclock_gtod_data pvclock_gtod_data;
1258
1259static void update_pvclock_gtod(struct timekeeper *tk)
1260{
1261 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1262 u64 boot_ns;
1263
876e7881 1264 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1265
1266 write_seqcount_begin(&vdata->seq);
1267
1268 /* copy pvclock gtod data */
876e7881
PZ		 1269 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1270 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1271 vdata->clock.mask = tk->tkr_mono.mask;
1272 vdata->clock.mult = tk->tkr_mono.mult;
1273 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1274
cbcf2dd3 1275 vdata->boot_ns = boot_ns;
876e7881 1276 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1277
55dd00a7
MT		 1278 vdata->wall_time_sec = tk->xtime_sec;
1279
16e8d74d
MT		 1280 write_seqcount_end(&vdata->seq);
1281}
1282#endif
1283
bab5bb39
NK		 1284void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1285{
1286 /*
1287 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1288 * vcpu_enter_guest. This function is only called from
1289 * the physical CPU that is running vcpu.
1290 */
1291 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1292}
16e8d74d 1293
18068523
GOC		 1294static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1295{
9ed3c444
AK		 1296 int version;
1297 int r;
50d0a0f9 1298 struct pvclock_wall_clock wc;
87aeb54f 1299 struct timespec64 boot;
18068523
GOC		 1300
1301 if (!wall_clock)
1302 return;
1303
9ed3c444
AK		 1304 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1305 if (r)
1306 return;
1307
1308 if (version & 1)
1309 ++version; /* first time write, random junk */
1310
1311 ++version;
18068523 1312
1dab1345
NK		 1313 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1314 return;
18068523 1315
50d0a0f9
GH		 1316 /*
1317 * The guest calculates current wall clock time by adding
34c238a1 1318 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1319 * wall clock specified here. guest system time equals host
1320 * system time for us, thus we must fill in host boot time here.
1321 */
87aeb54f 1322 getboottime64(&boot);
50d0a0f9 1323
4b648665 1324 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1325 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1326 boot = timespec64_sub(boot, ts);
4b648665 1327 }
87aeb54f 1328 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1329 wc.nsec = boot.tv_nsec;
1330 wc.version = version;
18068523
GOC		 1331
1332 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1333
1334 version++;
1335 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1336}
1337
50d0a0f9
GH		 1338static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1339{
b51012de
PB		 1340 do_shl32_div32(dividend, divisor);
1341 return dividend;
50d0a0f9
GH		 1342}
1343
3ae13faa 1344static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1345 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1346{
5f4e3f88 1347 uint64_t scaled64;
50d0a0f9
GH		 1348 int32_t shift = 0;
1349 uint64_t tps64;
1350 uint32_t tps32;
1351
3ae13faa
PB		 1352 tps64 = base_hz;
1353 scaled64 = scaled_hz;
50933623 1354 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1355 tps64 >>= 1;
1356 shift--;
1357 }
1358
1359 tps32 = (uint32_t)tps64;
50933623
JK		 1360 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1361 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1362 scaled64 >>= 1;
1363 else
1364 tps32 <<= 1;
50d0a0f9
GH		 1365 shift++;
1366 }
1367
5f4e3f88
ZA		 1368 *pshift = shift;
1369 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1370
3ae13faa
PB		 1371 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1372 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1373}
1374
d828199e 1375#ifdef CONFIG_X86_64
16e8d74d 1376static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1377#endif
16e8d74d 1378
c8076604 1379static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1380static unsigned long max_tsc_khz;
c8076604 1381
cc578287 1382static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1383{
cc578287
ZA		 1384 u64 v = (u64)khz * (1000000 + ppm);
1385 do_div(v, 1000000);
1386 return v;
1e993611
JR		 1387}
1388
381d585c
HZ		 1389static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1390{
1391 u64 ratio;
1392
1393 /* Guest TSC same frequency as host TSC? */
1394 if (!scale) {
1395 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1396 return 0;
1397 }
1398
1399 /* TSC scaling supported? */
1400 if (!kvm_has_tsc_control) {
1401 if (user_tsc_khz > tsc_khz) {
1402 vcpu->arch.tsc_catchup = 1;
1403 vcpu->arch.tsc_always_catchup = 1;
1404 return 0;
1405 } else {
1406 WARN(1, "user requested TSC rate below hardware speed\n");
1407 return -1;
1408 }
1409 }
1410
1411 /* TSC scaling required - calculate ratio */
1412 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1413 user_tsc_khz, tsc_khz);
1414
1415 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1416 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1417 user_tsc_khz);
1418 return -1;
1419 }
1420
1421 vcpu->arch.tsc_scaling_ratio = ratio;
1422 return 0;
1423}
1424
4941b8cb 1425static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1426{
cc578287
ZA		 1427 u32 thresh_lo, thresh_hi;
1428 int use_scaling = 0;
217fc9cf 1429
03ba32ca 1430 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1431 if (user_tsc_khz == 0) {
ad721883
HZ		 1432 /* set tsc_scaling_ratio to a safe value */
1433 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1434 return -1;
ad721883 1435 }
03ba32ca 1436
c285545f 1437 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1438 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1439 &vcpu->arch.virtual_tsc_shift,
1440 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1441 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1442
1443 /*
1444 * Compute the variation in TSC rate which is acceptable
1445 * within the range of tolerance and decide if the
1446 * rate being applied is within that bounds of the hardware
1447 * rate. If so, no scaling or compensation need be done.
1448 */
1449 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1450 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1451 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1452 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1453 use_scaling = 1;
1454 }
4941b8cb 1455 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1456}
1457
1458static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1459{
e26101b1 1460 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1461 vcpu->arch.virtual_tsc_mult,
1462 vcpu->arch.virtual_tsc_shift);
e26101b1 1463 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1464 return tsc;
1465}
1466
b0c39dc6
VK		 1467static inline int gtod_is_based_on_tsc(int mode)
1468{
1469 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1470}
1471
69b0049a 1472static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1473{
1474#ifdef CONFIG_X86_64
1475 bool vcpus_matched;
b48aa97e
MT		 1476 struct kvm_arch *ka = &vcpu->kvm->arch;
1477 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1478
1479 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1480 atomic_read(&vcpu->kvm->online_vcpus));
1481
7f187922
MT		 1482 /*
1483 * Once the masterclock is enabled, always perform request in
1484 * order to update it.
1485 *
1486 * In order to enable masterclock, the host clocksource must be TSC
1487 * and the vcpus need to have matched TSCs. When that happens,
1488 * perform request to enable masterclock.
1489 */
1490 if (ka->use_master_clock ||
b0c39dc6 1491 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1492 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1493
1494 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1495 atomic_read(&vcpu->kvm->online_vcpus),
1496 ka->use_master_clock, gtod->clock.vclock_mode);
1497#endif
1498}
1499
ba904635
WA		 1500static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1501{
e79f245d 1502 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1503 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1504}
1505
35181e86
HZ		 1506/*
1507 * Multiply tsc by a fixed point number represented by ratio.
1508 *
1509 * The most significant 64-N bits (mult) of ratio represent the
1510 * integral part of the fixed point number; the remaining N bits
1511 * (frac) represent the fractional part, ie. ratio represents a fixed
1512 * point number (mult + frac * 2^(-N)).
1513 *
1514 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1515 */
1516static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1517{
1518 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1519}
1520
1521u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1522{
1523 u64 _tsc = tsc;
1524 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1525
1526 if (ratio != kvm_default_tsc_scaling_ratio)
1527 _tsc = __scale_tsc(ratio, tsc);
1528
1529 return _tsc;
1530}
1531EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1532
07c1419a
HZ		 1533static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1534{
1535 u64 tsc;
1536
1537 tsc = kvm_scale_tsc(vcpu, rdtsc());
1538
1539 return target_tsc - tsc;
1540}
1541
4ba76538
HZ		 1542u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1543{
e79f245d
KA		 1544 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1545
1546 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1547}
1548EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1549
a545ab6a
LC		 1550static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1551{
1552 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1553 vcpu->arch.tsc_offset = offset;
1554}
1555
b0c39dc6
VK		 1556static inline bool kvm_check_tsc_unstable(void)
1557{
1558#ifdef CONFIG_X86_64
1559 /*
1560 * TSC is marked unstable when we're running on Hyper-V,
1561 * 'TSC page' clocksource is good.
1562 */
1563 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1564 return false;
1565#endif
1566 return check_tsc_unstable();
1567}
1568
8fe8ab46 1569void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1570{
1571 struct kvm *kvm = vcpu->kvm;
f38e098f 1572 u64 offset, ns, elapsed;
99e3e30a 1573 unsigned long flags;
b48aa97e 1574 bool matched;
0d3da0d2 1575 bool already_matched;
8fe8ab46 1576 u64 data = msr->data;
c5e8ec8e 1577 bool synchronizing = false;
99e3e30a 1578
038f8c11 1579 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1580 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1581 ns = ktime_get_boot_ns();
f38e098f 1582 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1583
03ba32ca 1584 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1585 if (data == 0 && msr->host_initiated) {
1586 /*
1587 * detection of vcpu initialization -- need to sync
1588 * with other vCPUs. This particularly helps to keep
1589 * kvm_clock stable after CPU hotplug
1590 */
1591 synchronizing = true;
1592 } else {
1593 u64 tsc_exp = kvm->arch.last_tsc_write +
1594 nsec_to_cycles(vcpu, elapsed);
1595 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1596 /*
1597 * Special case: TSC write with a small delta (1 second)
1598 * of virtual cycle time against real time is
1599 * interpreted as an attempt to synchronize the CPU.
1600 */
1601 synchronizing = data < tsc_exp + tsc_hz &&
1602 data + tsc_hz > tsc_exp;
1603 }
c5e8ec8e 1604 }
f38e098f
ZA		 1605
1606 /*
5d3cb0f6
ZA		 1607 * For a reliable TSC, we can match TSC offsets, and for an unstable
1608 * TSC, we add elapsed time in this computation. We could let the
1609 * compensation code attempt to catch up if we fall behind, but
1610 * it's better to try to match offsets from the beginning.
1611 */
c5e8ec8e 1612 if (synchronizing &&
5d3cb0f6 1613 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1614 if (!kvm_check_tsc_unstable()) {
e26101b1 1615 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1616 pr_debug("kvm: matched tsc offset for %llu\n", data);
1617 } else {
857e4099 1618 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1619 data += delta;
07c1419a 1620 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1621 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1622 }
b48aa97e 1623 matched = true;
0d3da0d2 1624 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1625 } else {
1626 /*
1627 * We split periods of matched TSC writes into generations.
1628 * For each generation, we track the original measured
1629 * nanosecond time, offset, and write, so if TSCs are in
1630 * sync, we can match exact offset, and if not, we can match
4a969980 1631 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1632 *
1633 * These values are tracked in kvm->arch.cur_xxx variables.
1634 */
1635 kvm->arch.cur_tsc_generation++;
1636 kvm->arch.cur_tsc_nsec = ns;
1637 kvm->arch.cur_tsc_write = data;
1638 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1639 matched = false;
0d3da0d2 1640 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1641 kvm->arch.cur_tsc_generation, data);
f38e098f 1642 }
e26101b1
ZA		 1643
1644 /*
1645 * We also track th most recent recorded KHZ, write and time to
1646 * allow the matching interval to be extended at each write.
1647 */
f38e098f
ZA		 1648 kvm->arch.last_tsc_nsec = ns;
1649 kvm->arch.last_tsc_write = data;
5d3cb0f6 1650 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1651
b183aa58 1652 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1653
1654 /* Keep track of which generation this VCPU has synchronized to */
1655 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1656 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1657 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1658
d6321d49 1659 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1660 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1661
a545ab6a 1662 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1663 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1664
1665 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1666 if (!matched) {
b48aa97e 1667 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1668 } else if (!already_matched) {
1669 kvm->arch.nr_vcpus_matched_tsc++;
1670 }
b48aa97e
MT		 1671
1672 kvm_track_tsc_matching(vcpu);
1673 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1674}
e26101b1 1675
99e3e30a
ZA		 1676EXPORT_SYMBOL_GPL(kvm_write_tsc);
1677
58ea6767
HZ		 1678static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1679 s64 adjustment)
1680{
ea26e4ec 1681 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1682}
1683
1684static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1685{
1686 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1687 WARN_ON(adjustment < 0);
1688 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1689 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1690}
1691
d828199e
MT		 1692#ifdef CONFIG_X86_64
1693
a5a1d1c2 1694static u64 read_tsc(void)
d828199e 1695{
a5a1d1c2 1696 u64 ret = (u64)rdtsc_ordered();
03b9730b 1697 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1698
1699 if (likely(ret >= last))
1700 return ret;
1701
1702 /*
1703 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1704 * predictable (it's just a function of time and the likely is
d828199e
MT		 1705 * very likely) and there's a data dependence, so force GCC
1706 * to generate a branch instead. I don't barrier() because
1707 * we don't actually need a barrier, and if this function
1708 * ever gets inlined it will generate worse code.
1709 */
1710 asm volatile ("");
1711 return last;
1712}
1713
b0c39dc6 1714static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1715{
1716 long v;
1717 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1718 u64 tsc_pg_val;
1719
1720 switch (gtod->clock.vclock_mode) {
1721 case VCLOCK_HVCLOCK:
1722 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1723 tsc_timestamp);
1724 if (tsc_pg_val != U64_MAX) {
1725 /* TSC page valid */
1726 *mode = VCLOCK_HVCLOCK;
1727 v = (tsc_pg_val - gtod->clock.cycle_last) &
1728 gtod->clock.mask;
1729 } else {
1730 /* TSC page invalid */
1731 *mode = VCLOCK_NONE;
1732 }
1733 break;
1734 case VCLOCK_TSC:
1735 *mode = VCLOCK_TSC;
1736 *tsc_timestamp = read_tsc();
1737 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1738 gtod->clock.mask;
1739 break;
1740 default:
1741 *mode = VCLOCK_NONE;
1742 }
d828199e 1743
b0c39dc6
VK		 1744 if (*mode == VCLOCK_NONE)
1745 *tsc_timestamp = v = 0;
d828199e 1746
d828199e
MT		 1747 return v * gtod->clock.mult;
1748}
1749
b0c39dc6 1750static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1751{
cbcf2dd3 1752 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1753 unsigned long seq;
d828199e 1754 int mode;
cbcf2dd3 1755 u64 ns;
d828199e 1756
d828199e
MT		 1757 do {
1758 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1759 ns = gtod->nsec_base;
b0c39dc6 1760 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1761 ns >>= gtod->clock.shift;
cbcf2dd3 1762 ns += gtod->boot_ns;
d828199e 1763 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1764 *t = ns;
d828199e
MT		 1765
1766 return mode;
1767}
1768
899a31f5 1769static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1770{
1771 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1772 unsigned long seq;
1773 int mode;
1774 u64 ns;
1775
1776 do {
1777 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1778 ts->tv_sec = gtod->wall_time_sec;
1779 ns = gtod->nsec_base;
b0c39dc6 1780 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1781 ns >>= gtod->clock.shift;
1782 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1783
1784 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1785 ts->tv_nsec = ns;
1786
1787 return mode;
1788}
1789
b0c39dc6
VK		 1790/* returns true if host is using TSC based clocksource */
1791static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1792{
d828199e 1793 /* checked again under seqlock below */
b0c39dc6 1794 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1795 return false;
1796
b0c39dc6
VK		 1797 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1798 tsc_timestamp));
d828199e 1799}
55dd00a7 1800
b0c39dc6 1801/* returns true if host is using TSC based clocksource */
899a31f5 1802static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1803 u64 *tsc_timestamp)
55dd00a7
MT		 1804{
1805 /* checked again under seqlock below */
b0c39dc6 1806 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1807 return false;
1808
b0c39dc6 1809 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1810}
d828199e
MT		 1811#endif
1812
1813/*
1814 *
b48aa97e
MT		 1815 * Assuming a stable TSC across physical CPUS, and a stable TSC
1816 * across virtual CPUs, the following condition is possible.
1817 * Each numbered line represents an event visible to both
d828199e
MT		 1818 * CPUs at the next numbered event.
1819 *
1820 * "timespecX" represents host monotonic time. "tscX" represents
1821 * RDTSC value.
1822 *
1823 * VCPU0 on CPU0 | VCPU1 on CPU1
1824 *
1825 * 1. read timespec0,tsc0
1826 * 2. | timespec1 = timespec0 + N
1827 * | tsc1 = tsc0 + M
1828 * 3. transition to guest | transition to guest
1829 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1830 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1831 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1832 *
1833 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1834 *
1835 * - ret0 < ret1
1836 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1837 * ...
1838 * - 0 < N - M => M < N
1839 *
1840 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1841 * always the case (the difference between two distinct xtime instances
1842 * might be smaller then the difference between corresponding TSC reads,
1843 * when updating guest vcpus pvclock areas).
1844 *
1845 * To avoid that problem, do not allow visibility of distinct
1846 * system_timestamp/tsc_timestamp values simultaneously: use a master
1847 * copy of host monotonic time values. Update that master copy
1848 * in lockstep.
1849 *
b48aa97e 1850 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1851 *
1852 */
1853
1854static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1855{
1856#ifdef CONFIG_X86_64
1857 struct kvm_arch *ka = &kvm->arch;
1858 int vclock_mode;
b48aa97e
MT		 1859 bool host_tsc_clocksource, vcpus_matched;
1860
1861 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1862 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1863
1864 /*
1865 * If the host uses TSC clock, then passthrough TSC as stable
1866 * to the guest.
1867 */
b48aa97e 1868 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1869 &ka->master_kernel_ns,
1870 &ka->master_cycle_now);
1871
16a96021 1872 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1873 && !ka->backwards_tsc_observed
54750f2c 1874 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1875
d828199e
MT		 1876 if (ka->use_master_clock)
1877 atomic_set(&kvm_guest_has_master_clock, 1);
1878
1879 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1880 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1881 vcpus_matched);
d828199e
MT		 1882#endif
1883}
1884
2860c4b1
PB		 1885void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1886{
1887 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1888}
1889
2e762ff7
MT		 1890static void kvm_gen_update_masterclock(struct kvm *kvm)
1891{
1892#ifdef CONFIG_X86_64
1893 int i;
1894 struct kvm_vcpu *vcpu;
1895 struct kvm_arch *ka = &kvm->arch;
1896
1897 spin_lock(&ka->pvclock_gtod_sync_lock);
1898 kvm_make_mclock_inprogress_request(kvm);
1899 /* no guest entries from this point */
1900 pvclock_update_vm_gtod_copy(kvm);
1901
1902 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1903 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1904
1905 /* guest entries allowed */
1906 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1907 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1908
1909 spin_unlock(&ka->pvclock_gtod_sync_lock);
1910#endif
1911}
1912
e891a32e 1913u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1914{
108b249c 1915 struct kvm_arch *ka = &kvm->arch;
8b953440 1916 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1917 u64 ret;
108b249c 1918
8b953440
PB		 1919 spin_lock(&ka->pvclock_gtod_sync_lock);
1920 if (!ka->use_master_clock) {
1921 spin_unlock(&ka->pvclock_gtod_sync_lock);
1922 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1923 }
1924
8b953440
PB		 1925 hv_clock.tsc_timestamp = ka->master_cycle_now;
1926 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1927 spin_unlock(&ka->pvclock_gtod_sync_lock);
1928
e2c2206a
WL		 1929 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1930 get_cpu();
1931
e70b57a6
WL		 1932 if (__this_cpu_read(cpu_tsc_khz)) {
1933 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1934 &hv_clock.tsc_shift,
1935 &hv_clock.tsc_to_system_mul);
1936 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1937 } else
1938 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1939
1940 put_cpu();
1941
1942 return ret;
108b249c
PB		 1943}
1944
0d6dd2ff
PB		 1945static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1946{
1947 struct kvm_vcpu_arch *vcpu = &v->arch;
1948 struct pvclock_vcpu_time_info guest_hv_clock;
1949
4e335d9e 1950 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1951 &guest_hv_clock, sizeof(guest_hv_clock))))
1952 return;
1953
1954 /* This VCPU is paused, but it's legal for a guest to read another
1955 * VCPU's kvmclock, so we really have to follow the specification where
1956 * it says that version is odd if data is being modified, and even after
1957 * it is consistent.
1958 *
1959 * Version field updates must be kept separate. This is because
1960 * kvm_write_guest_cached might use a "rep movs" instruction, and
1961 * writes within a string instruction are weakly ordered. So there
1962 * are three writes overall.
1963 *
1964 * As a small optimization, only write the version field in the first
1965 * and third write. The vcpu->pv_time cache is still valid, because the
1966 * version field is the first in the struct.
1967 */
1968 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1969
51c4b8bb
LA		 1970 if (guest_hv_clock.version & 1)
1971 ++guest_hv_clock.version; /* first time write, random junk */
1972
0d6dd2ff 1973 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1974 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1975 &vcpu->hv_clock,
1976 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1977
1978 smp_wmb();
1979
1980 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1981 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1982
1983 if (vcpu->pvclock_set_guest_stopped_request) {
1984 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1985 vcpu->pvclock_set_guest_stopped_request = false;
1986 }
1987
1988 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1989
4e335d9e
PB		 1990 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1991 &vcpu->hv_clock,
1992 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1993
1994 smp_wmb();
1995
1996 vcpu->hv_clock.version++;
4e335d9e
PB		 1997 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1998 &vcpu->hv_clock,
1999 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2000}
2001
34c238a1 2002static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2003{
78db6a50 2004 unsigned long flags, tgt_tsc_khz;
18068523 2005 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2006 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2007 s64 kernel_ns;
d828199e 2008 u64 tsc_timestamp, host_tsc;
51d59c6b 2009 u8 pvclock_flags;
d828199e
MT		 2010 bool use_master_clock;
2011
2012 kernel_ns = 0;
2013 host_tsc = 0;
18068523 2014
d828199e
MT		 2015 /*
2016 * If the host uses TSC clock, then passthrough TSC as stable
2017 * to the guest.
2018 */
2019 spin_lock(&ka->pvclock_gtod_sync_lock);
2020 use_master_clock = ka->use_master_clock;
2021 if (use_master_clock) {
2022 host_tsc = ka->master_cycle_now;
2023 kernel_ns = ka->master_kernel_ns;
2024 }
2025 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2026
2027 /* Keep irq disabled to prevent changes to the clock */
2028 local_irq_save(flags);
78db6a50
PB		 2029 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2030 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2031 local_irq_restore(flags);
2032 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2033 return 1;
2034 }
d828199e 2035 if (!use_master_clock) {
4ea1636b 2036 host_tsc = rdtsc();
108b249c 2037 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2038 }
2039
4ba76538 2040 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2041
c285545f
ZA		 2042 /*
2043 * We may have to catch up the TSC to match elapsed wall clock
2044 * time for two reasons, even if kvmclock is used.
2045 * 1) CPU could have been running below the maximum TSC rate
2046 * 2) Broken TSC compensation resets the base at each VCPU
2047 * entry to avoid unknown leaps of TSC even when running
2048 * again on the same CPU. This may cause apparent elapsed
2049 * time to disappear, and the guest to stand still or run
2050 * very slowly.
2051 */
2052 if (vcpu->tsc_catchup) {
2053 u64 tsc = compute_guest_tsc(v, kernel_ns);
2054 if (tsc > tsc_timestamp) {
f1e2b260 2055 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2056 tsc_timestamp = tsc;
2057 }
50d0a0f9
GH		 2058 }
2059
18068523
GOC		 2060 local_irq_restore(flags);
2061
0d6dd2ff 2062 /* With all the info we got, fill in the values */
18068523 2063
78db6a50
PB		 2064 if (kvm_has_tsc_control)
2065 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2066
2067 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2068 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2069 &vcpu->hv_clock.tsc_shift,
2070 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2071 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2072 }
2073
1d5f066e 2074 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2075 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2076 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2077
d828199e 2078 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2079 pvclock_flags = 0;
d828199e
MT		 2080 if (use_master_clock)
2081 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2082
78c0337a
MT		 2083 vcpu->hv_clock.flags = pvclock_flags;
2084
095cf55d
PB		 2085 if (vcpu->pv_time_enabled)
2086 kvm_setup_pvclock_page(v);
2087 if (v == kvm_get_vcpu(v->kvm, 0))
2088 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2089 return 0;
c8076604
GH		 2090}
2091
0061d53d
MT		 2092/*
2093 * kvmclock updates which are isolated to a given vcpu, such as
2094 * vcpu->cpu migration, should not allow system_timestamp from
2095 * the rest of the vcpus to remain static. Otherwise ntp frequency
2096 * correction applies to one vcpu's system_timestamp but not
2097 * the others.
2098 *
2099 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2100 * We need to rate-limit these requests though, as they can
2101 * considerably slow guests that have a large number of vcpus.
2102 * The time for a remote vcpu to update its kvmclock is bound
2103 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2104 */
2105
7e44e449
AJ		 2106#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2107
2108static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2109{
2110 int i;
7e44e449
AJ		 2111 struct delayed_work *dwork = to_delayed_work(work);
2112 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2113 kvmclock_update_work);
2114 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2115 struct kvm_vcpu *vcpu;
2116
2117 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2118 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2119 kvm_vcpu_kick(vcpu);
2120 }
2121}
2122
7e44e449
AJ		 2123static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2124{
2125 struct kvm *kvm = v->kvm;
2126
105b21bb 2127 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2128 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2129 KVMCLOCK_UPDATE_DELAY);
2130}
2131
332967a3
AJ		 2132#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2133
2134static void kvmclock_sync_fn(struct work_struct *work)
2135{
2136 struct delayed_work *dwork = to_delayed_work(work);
2137 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2138 kvmclock_sync_work);
2139 struct kvm *kvm = container_of(ka, struct kvm, arch);
2140
630994b3
MT		 2141 if (!kvmclock_periodic_sync)
2142 return;
2143
332967a3
AJ		 2144 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2145 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2146 KVMCLOCK_SYNC_PERIOD);
2147}
2148
9ffd986c 2149static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2150{
890ca9ae
HY		 2151 u64 mcg_cap = vcpu->arch.mcg_cap;
2152 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2153 u32 msr = msr_info->index;
2154 u64 data = msr_info->data;
890ca9ae 2155
15c4a640 2156 switch (msr) {
15c4a640 2157 case MSR_IA32_MCG_STATUS:
890ca9ae 2158 vcpu->arch.mcg_status = data;
15c4a640 2159 break;
c7ac679c 2160 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2161 if (!(mcg_cap & MCG_CTL_P))
2162 return 1;
2163 if (data != 0 && data != ~(u64)0)
2164 return -1;
2165 vcpu->arch.mcg_ctl = data;
2166 break;
2167 default:
2168 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2169 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2170 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2171 /* only 0 or all 1s can be written to IA32_MCi_CTL
2172 * some Linux kernels though clear bit 10 in bank 4 to
2173 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2174 * this to avoid an uncatched #GP in the guest
2175 */
890ca9ae 2176 if ((offset & 0x3) == 0 &&
114be429 2177 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2178 return -1;
9ffd986c
WL		 2179 if (!msr_info->host_initiated &&
2180 (offset & 0x3) == 1 && data != 0)
2181 return -1;
890ca9ae
HY		 2182 vcpu->arch.mce_banks[offset] = data;
2183 break;
2184 }
2185 return 1;
2186 }
2187 return 0;
2188}
2189
ffde22ac
ES		 2190static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2191{
2192 struct kvm *kvm = vcpu->kvm;
2193 int lm = is_long_mode(vcpu);
2194 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2195 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2196 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2197 : kvm->arch.xen_hvm_config.blob_size_32;
2198 u32 page_num = data & ~PAGE_MASK;
2199 u64 page_addr = data & PAGE_MASK;
2200 u8 *page;
2201 int r;
2202
2203 r = -E2BIG;
2204 if (page_num >= blob_size)
2205 goto out;
2206 r = -ENOMEM;
ff5c2c03
SL		 2207 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2208 if (IS_ERR(page)) {
2209 r = PTR_ERR(page);
ffde22ac 2210 goto out;
ff5c2c03 2211 }
54bf36aa 2212 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2213 goto out_free;
2214 r = 0;
2215out_free:
2216 kfree(page);
2217out:
2218 return r;
2219}
2220
344d9588
GN		 2221static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2222{
2223 gpa_t gpa = data & ~0x3f;
2224
52a5c155
WL		 2225 /* Bits 3:5 are reserved, Should be zero */
2226 if (data & 0x38)
344d9588
GN		 2227 return 1;
2228
2229 vcpu->arch.apf.msr_val = data;
2230
2231 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2232 kvm_clear_async_pf_completion_queue(vcpu);
2233 kvm_async_pf_hash_reset(vcpu);
2234 return 0;
2235 }
2236
4e335d9e 2237 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2238 sizeof(u32)))
344d9588
GN		 2239 return 1;
2240
6adba527 2241 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2242 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2243 kvm_async_pf_wakeup_all(vcpu);
2244 return 0;
2245}
2246
12f9a48f
GC		 2247static void kvmclock_reset(struct kvm_vcpu *vcpu)
2248{
0b79459b 2249 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2250}
2251
f38a7b75
WL		 2252static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2253{
2254 ++vcpu->stat.tlb_flush;
2255 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2256}
2257
c9aaa895
GC		 2258static void record_steal_time(struct kvm_vcpu *vcpu)
2259{
2260 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2261 return;
2262
4e335d9e 2263 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2264 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2265 return;
2266
f38a7b75
WL		 2267 /*
2268 * Doing a TLB flush here, on the guest's behalf, can avoid
2269 * expensive IPIs.
2270 */
2271 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2272 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2273
35f3fae1
WL		 2274 if (vcpu->arch.st.steal.version & 1)
2275 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2276
2277 vcpu->arch.st.steal.version += 1;
2278
4e335d9e 2279 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2280 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2281
2282 smp_wmb();
2283
c54cdf14
LC		 2284 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2285 vcpu->arch.st.last_steal;
2286 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2287
4e335d9e 2288 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2289 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2290
2291 smp_wmb();
2292
2293 vcpu->arch.st.steal.version += 1;
c9aaa895 2294
4e335d9e 2295 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2296 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2297}
2298
8fe8ab46 2299int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2300{
5753785f 2301 bool pr = false;
8fe8ab46
WA		 2302 u32 msr = msr_info->index;
2303 u64 data = msr_info->data;
5753785f 2304
15c4a640 2305 switch (msr) {
2e32b719 2306 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2307 case MSR_IA32_UCODE_WRITE:
2308 case MSR_VM_HSAVE_PA:
2309 case MSR_AMD64_PATCH_LOADER:
2310 case MSR_AMD64_BU_CFG2:
405a353a 2311 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2312 break;
2313
518e7b94
WL		 2314 case MSR_IA32_UCODE_REV:
2315 if (msr_info->host_initiated)
2316 vcpu->arch.microcode_version = data;
2317 break;
15c4a640 2318 case MSR_EFER:
b69e8cae 2319 return set_efer(vcpu, data);
8f1589d9
AP		 2320 case MSR_K7_HWCR:
2321 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2322 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2323 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2324 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2325 if (data != 0) {
a737f256
CD		 2326 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2327 data);
8f1589d9
AP		 2328 return 1;
2329 }
15c4a640 2330 break;
f7c6d140
AP		 2331 case MSR_FAM10H_MMIO_CONF_BASE:
2332 if (data != 0) {
a737f256
CD		 2333 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2334 "0x%llx\n", data);
f7c6d140
AP		 2335 return 1;
2336 }
15c4a640 2337 break;
b5e2fec0
AG		 2338 case MSR_IA32_DEBUGCTLMSR:
2339 if (!data) {
2340 /* We support the non-activated case already */
2341 break;
2342 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2343 /* Values other than LBR and BTF are vendor-specific,
2344 thus reserved and should throw a #GP */
2345 return 1;
2346 }
a737f256
CD		 2347 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2348 __func__, data);
b5e2fec0 2349 break;
9ba075a6 2350 case 0x200 ... 0x2ff:
ff53604b 2351 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2352 case MSR_IA32_APICBASE:
58cb628d 2353 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2354 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2355 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2356 case MSR_IA32_TSCDEADLINE:
2357 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2358 break;
ba904635 2359 case MSR_IA32_TSC_ADJUST:
d6321d49 2360 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2361 if (!msr_info->host_initiated) {
d913b904 2362 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2363 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2364 }
2365 vcpu->arch.ia32_tsc_adjust_msr = data;
2366 }
2367 break;
15c4a640 2368 case MSR_IA32_MISC_ENABLE:
ad312c7c 2369 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2370 break;
64d60670
PB		 2371 case MSR_IA32_SMBASE:
2372 if (!msr_info->host_initiated)
2373 return 1;
2374 vcpu->arch.smbase = data;
2375 break;
dd259935
PB		 2376 case MSR_IA32_TSC:
2377 kvm_write_tsc(vcpu, msr_info);
2378 break;
52797bf9
LA		 2379 case MSR_SMI_COUNT:
2380 if (!msr_info->host_initiated)
2381 return 1;
2382 vcpu->arch.smi_count = data;
2383 break;
11c6bffa 2384 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2385 case MSR_KVM_WALL_CLOCK:
2386 vcpu->kvm->arch.wall_clock = data;
2387 kvm_write_wall_clock(vcpu->kvm, data);
2388 break;
11c6bffa 2389 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2390 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2391 struct kvm_arch *ka = &vcpu->kvm->arch;
2392
12f9a48f 2393 kvmclock_reset(vcpu);
18068523 2394
54750f2c
MT		 2395 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2396 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2397
2398 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2399 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2400
2401 ka->boot_vcpu_runs_old_kvmclock = tmp;
2402 }
2403
18068523 2404 vcpu->arch.time = data;
0061d53d 2405 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2406
2407 /* we verify if the enable bit is set... */
2408 if (!(data & 1))
2409 break;
2410
4e335d9e 2411 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2412 &vcpu->arch.pv_time, data & ~1ULL,
2413 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2414 vcpu->arch.pv_time_enabled = false;
2415 else
2416 vcpu->arch.pv_time_enabled = true;
32cad84f 2417
18068523
GOC		 2418 break;
2419 }
344d9588
GN		 2420 case MSR_KVM_ASYNC_PF_EN:
2421 if (kvm_pv_enable_async_pf(vcpu, data))
2422 return 1;
2423 break;
c9aaa895
GC		 2424 case MSR_KVM_STEAL_TIME:
2425
2426 if (unlikely(!sched_info_on()))
2427 return 1;
2428
2429 if (data & KVM_STEAL_RESERVED_MASK)
2430 return 1;
2431
4e335d9e 2432 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2433 data & KVM_STEAL_VALID_BITS,
2434 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2435 return 1;
2436
2437 vcpu->arch.st.msr_val = data;
2438
2439 if (!(data & KVM_MSR_ENABLED))
2440 break;
2441
c9aaa895
GC		 2442 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2443
2444 break;
ae7a2a3f
MT		 2445 case MSR_KVM_PV_EOI_EN:
2446 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2447 return 1;
2448 break;
c9aaa895 2449
890ca9ae
HY		 2450 case MSR_IA32_MCG_CTL:
2451 case MSR_IA32_MCG_STATUS:
81760dcc 2452 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2453 return set_msr_mce(vcpu, msr_info);
71db6023 2454
6912ac32
WH		 2455 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2456 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2457 pr = true; /* fall through */
2458 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2459 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2460 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2461 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2462
2463 if (pr || data != 0)
a737f256
CD		 2464 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2465 "0x%x data 0x%llx\n", msr, data);
5753785f 2466 break;
84e0cefa
JS		 2467 case MSR_K7_CLK_CTL:
2468 /*
2469 * Ignore all writes to this no longer documented MSR.
2470 * Writes are only relevant for old K7 processors,
2471 * all pre-dating SVM, but a recommended workaround from
4a969980 2472 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2473 * affected processor models on the command line, hence
2474 * the need to ignore the workaround.
2475 */
2476 break;
55cd8e5a 2477 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2478 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2479 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2480 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2481 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2482 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2483 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2484 return kvm_hv_set_msr_common(vcpu, msr, data,
2485 msr_info->host_initiated);
91c9c3ed 2486 case MSR_IA32_BBL_CR_CTL3:
2487 /* Drop writes to this legacy MSR -- see rdmsr
2488 * counterpart for further detail.
2489 */
fab0aa3b
EM		 2490 if (report_ignored_msrs)
2491 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2492 msr, data);
91c9c3ed 2493 break;
2b036c6b 2494 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2495 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2496 return 1;
2497 vcpu->arch.osvw.length = data;
2498 break;
2499 case MSR_AMD64_OSVW_STATUS:
d6321d49 2500 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2501 return 1;
2502 vcpu->arch.osvw.status = data;
2503 break;
db2336a8
KH		 2504 case MSR_PLATFORM_INFO:
2505 if (!msr_info->host_initiated ||
2506 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2507 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2508 cpuid_fault_enabled(vcpu)))
2509 return 1;
2510 vcpu->arch.msr_platform_info = data;
2511 break;
2512 case MSR_MISC_FEATURES_ENABLES:
2513 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2514 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2515 !supports_cpuid_fault(vcpu)))
2516 return 1;
2517 vcpu->arch.msr_misc_features_enables = data;
2518 break;
15c4a640 2519 default:
ffde22ac
ES		 2520 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2521 return xen_hvm_config(vcpu, data);
c6702c9d 2522 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2523 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2524 if (!ignore_msrs) {
ae0f5499 2525 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2526 msr, data);
ed85c068
AP		 2527 return 1;
2528 } else {
fab0aa3b
EM		 2529 if (report_ignored_msrs)
2530 vcpu_unimpl(vcpu,
2531 "ignored wrmsr: 0x%x data 0x%llx\n",
2532 msr, data);
ed85c068
AP		 2533 break;
2534 }
15c4a640
CO		 2535 }
2536 return 0;
2537}
2538EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2539
2540
2541/*
2542 * Reads an msr value (of 'msr_index') into 'pdata'.
2543 * Returns 0 on success, non-0 otherwise.
2544 * Assumes vcpu_load() was already called.
2545 */
609e36d3 2546int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2547{
609e36d3 2548 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2549}
ff651cb6 2550EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2551
890ca9ae 2552static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2553{
2554 u64 data;
890ca9ae
HY		 2555 u64 mcg_cap = vcpu->arch.mcg_cap;
2556 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2557
2558 switch (msr) {
15c4a640
CO		 2559 case MSR_IA32_P5_MC_ADDR:
2560 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2561 data = 0;
2562 break;
15c4a640 2563 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2564 data = vcpu->arch.mcg_cap;
2565 break;
c7ac679c 2566 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2567 if (!(mcg_cap & MCG_CTL_P))
2568 return 1;
2569 data = vcpu->arch.mcg_ctl;
2570 break;
2571 case MSR_IA32_MCG_STATUS:
2572 data = vcpu->arch.mcg_status;
2573 break;
2574 default:
2575 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2576 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2577 u32 offset = msr - MSR_IA32_MC0_CTL;
2578 data = vcpu->arch.mce_banks[offset];
2579 break;
2580 }
2581 return 1;
2582 }
2583 *pdata = data;
2584 return 0;
2585}
2586
609e36d3 2587int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2588{
609e36d3 2589 switch (msr_info->index) {
890ca9ae 2590 case MSR_IA32_PLATFORM_ID:
15c4a640 2591 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2592 case MSR_IA32_DEBUGCTLMSR:
2593 case MSR_IA32_LASTBRANCHFROMIP:
2594 case MSR_IA32_LASTBRANCHTOIP:
2595 case MSR_IA32_LASTINTFROMIP:
2596 case MSR_IA32_LASTINTTOIP:
60af2ecd 2597 case MSR_K8_SYSCFG:
3afb1121
PB		 2598 case MSR_K8_TSEG_ADDR:
2599 case MSR_K8_TSEG_MASK:
60af2ecd 2600 case MSR_K7_HWCR:
61a6bd67 2601 case MSR_VM_HSAVE_PA:
1fdbd48c 2602 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2603 case MSR_AMD64_NB_CFG:
f7c6d140 2604 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2605 case MSR_AMD64_BU_CFG2:
0c2df2a1 2606 case MSR_IA32_PERF_CTL:
405a353a 2607 case MSR_AMD64_DC_CFG:
609e36d3 2608 msr_info->data = 0;
15c4a640 2609 break;
c51eb52b 2610 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2611 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2612 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2613 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2614 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2615 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2616 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2617 msr_info->data = 0;
5753785f 2618 break;
742bc670 2619 case MSR_IA32_UCODE_REV:
518e7b94 2620 msr_info->data = vcpu->arch.microcode_version;
742bc670 2621 break;
dd259935
PB		 2622 case MSR_IA32_TSC:
2623 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2624 break;
9ba075a6 2625 case MSR_MTRRcap:
9ba075a6 2626 case 0x200 ... 0x2ff:
ff53604b 2627 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2628 case 0xcd: /* fsb frequency */
609e36d3 2629 msr_info->data = 3;
15c4a640 2630 break;
7b914098
JS		 2631 /*
2632 * MSR_EBC_FREQUENCY_ID
2633 * Conservative value valid for even the basic CPU models.
2634 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2635 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2636 * and 266MHz for model 3, or 4. Set Core Clock
2637 * Frequency to System Bus Frequency Ratio to 1 (bits
2638 * 31:24) even though these are only valid for CPU
2639 * models > 2, however guests may end up dividing or
2640 * multiplying by zero otherwise.
2641 */
2642 case MSR_EBC_FREQUENCY_ID:
609e36d3 2643 msr_info->data = 1 << 24;
7b914098 2644 break;
15c4a640 2645 case MSR_IA32_APICBASE:
609e36d3 2646 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2647 break;
0105d1a5 2648 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2649 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2650 break;
a3e06bbe 2651 case MSR_IA32_TSCDEADLINE:
609e36d3 2652 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2653 break;
ba904635 2654 case MSR_IA32_TSC_ADJUST:
609e36d3 2655 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2656 break;
15c4a640 2657 case MSR_IA32_MISC_ENABLE:
609e36d3 2658 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2659 break;
64d60670
PB		 2660 case MSR_IA32_SMBASE:
2661 if (!msr_info->host_initiated)
2662 return 1;
2663 msr_info->data = vcpu->arch.smbase;
15c4a640 2664 break;
52797bf9
LA		 2665 case MSR_SMI_COUNT:
2666 msr_info->data = vcpu->arch.smi_count;
2667 break;
847f0ad8
AG		 2668 case MSR_IA32_PERF_STATUS:
2669 /* TSC increment by tick */
609e36d3 2670 msr_info->data = 1000ULL;
847f0ad8 2671 /* CPU multiplier */
b0996ae4 2672 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2673 break;
15c4a640 2674 case MSR_EFER:
609e36d3 2675 msr_info->data = vcpu->arch.efer;
15c4a640 2676 break;
18068523 2677 case MSR_KVM_WALL_CLOCK:
11c6bffa 2678 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2679 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2680 break;
2681 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2682 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2683 msr_info->data = vcpu->arch.time;
18068523 2684 break;
344d9588 2685 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2686 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2687 break;
c9aaa895 2688 case MSR_KVM_STEAL_TIME:
609e36d3 2689 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2690 break;
1d92128f 2691 case MSR_KVM_PV_EOI_EN:
609e36d3 2692 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2693 break;
890ca9ae
HY		 2694 case MSR_IA32_P5_MC_ADDR:
2695 case MSR_IA32_P5_MC_TYPE:
2696 case MSR_IA32_MCG_CAP:
2697 case MSR_IA32_MCG_CTL:
2698 case MSR_IA32_MCG_STATUS:
81760dcc 2699 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2700 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2701 case MSR_K7_CLK_CTL:
2702 /*
2703 * Provide expected ramp-up count for K7. All other
2704 * are set to zero, indicating minimum divisors for
2705 * every field.
2706 *
2707 * This prevents guest kernels on AMD host with CPU
2708 * type 6, model 8 and higher from exploding due to
2709 * the rdmsr failing.
2710 */
609e36d3 2711 msr_info->data = 0x20000000;
84e0cefa 2712 break;
55cd8e5a 2713 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2714 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2715 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2716 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2717 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2718 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2719 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887
AS		 2720 return kvm_hv_get_msr_common(vcpu,
2721 msr_info->index, &msr_info->data);
55cd8e5a 2722 break;
91c9c3ed 2723 case MSR_IA32_BBL_CR_CTL3:
2724 /* This legacy MSR exists but isn't fully documented in current
2725 * silicon. It is however accessed by winxp in very narrow
2726 * scenarios where it sets bit #19, itself documented as
2727 * a "reserved" bit. Best effort attempt to source coherent
2728 * read data here should the balance of the register be
2729 * interpreted by the guest:
2730 *
2731 * L2 cache control register 3: 64GB range, 256KB size,
2732 * enabled, latency 0x1, configured
2733 */
609e36d3 2734 msr_info->data = 0xbe702111;
91c9c3ed 2735 break;
2b036c6b 2736 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2737 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2738 return 1;
609e36d3 2739 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2740 break;
2741 case MSR_AMD64_OSVW_STATUS:
d6321d49 2742 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2743 return 1;
609e36d3 2744 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2745 break;
db2336a8
KH		 2746 case MSR_PLATFORM_INFO:
2747 msr_info->data = vcpu->arch.msr_platform_info;
2748 break;
2749 case MSR_MISC_FEATURES_ENABLES:
2750 msr_info->data = vcpu->arch.msr_misc_features_enables;
2751 break;
15c4a640 2752 default:
c6702c9d 2753 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2754 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2755 if (!ignore_msrs) {
ae0f5499
BD		 2756 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2757 msr_info->index);
ed85c068
AP		 2758 return 1;
2759 } else {
fab0aa3b
EM		 2760 if (report_ignored_msrs)
2761 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2762 msr_info->index);
609e36d3 2763 msr_info->data = 0;
ed85c068
AP		 2764 }
2765 break;
15c4a640 2766 }
15c4a640
CO		 2767 return 0;
2768}
2769EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2770
313a3dc7
CO		 2771/*
2772 * Read or write a bunch of msrs. All parameters are kernel addresses.
2773 *
2774 * @return number of msrs set successfully.
2775 */
2776static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2777 struct kvm_msr_entry *entries,
2778 int (*do_msr)(struct kvm_vcpu *vcpu,
2779 unsigned index, u64 *data))
2780{
801e459a 2781 int i;
313a3dc7 2782
313a3dc7
CO		 2783 for (i = 0; i < msrs->nmsrs; ++i)
2784 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2785 break;
2786
313a3dc7
CO		 2787 return i;
2788}
2789
2790/*
2791 * Read or write a bunch of msrs. Parameters are user addresses.
2792 *
2793 * @return number of msrs set successfully.
2794 */
2795static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2796 int (*do_msr)(struct kvm_vcpu *vcpu,
2797 unsigned index, u64 *data),
2798 int writeback)
2799{
2800 struct kvm_msrs msrs;
2801 struct kvm_msr_entry *entries;
2802 int r, n;
2803 unsigned size;
2804
2805 r = -EFAULT;
2806 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2807 goto out;
2808
2809 r = -E2BIG;
2810 if (msrs.nmsrs >= MAX_IO_MSRS)
2811 goto out;
2812
313a3dc7 2813 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2814 entries = memdup_user(user_msrs->entries, size);
2815 if (IS_ERR(entries)) {
2816 r = PTR_ERR(entries);
313a3dc7 2817 goto out;
ff5c2c03 2818 }
313a3dc7
CO		 2819
2820 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2821 if (r < 0)
2822 goto out_free;
2823
2824 r = -EFAULT;
2825 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2826 goto out_free;
2827
2828 r = n;
2829
2830out_free:
7a73c028 2831 kfree(entries);
313a3dc7
CO		 2832out:
2833 return r;
2834}
2835
4d5422ce
WL		 2836static inline bool kvm_can_mwait_in_guest(void)
2837{
2838 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2839 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2840 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2841}
2842
784aa3d7 2843int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2844{
4d5422ce 2845 int r = 0;
018d00d2
ZX		 2846
2847 switch (ext) {
2848 case KVM_CAP_IRQCHIP:
2849 case KVM_CAP_HLT:
2850 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2851 case KVM_CAP_SET_TSS_ADDR:
07716717 2852 case KVM_CAP_EXT_CPUID:
9c15bb1d 2853 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2854 case KVM_CAP_CLOCKSOURCE:
7837699f 2855 case KVM_CAP_PIT:
a28e4f5a 2856 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2857 case KVM_CAP_MP_STATE:
ed848624 2858 case KVM_CAP_SYNC_MMU:
a355c85c 2859 case KVM_CAP_USER_NMI:
52d939a0 2860 case KVM_CAP_REINJECT_CONTROL:
4925663a 2861 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2862 case KVM_CAP_IOEVENTFD:
f848a5a8 2863 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2864 case KVM_CAP_PIT2:
e9f42757 2865 case KVM_CAP_PIT_STATE2:
b927a3ce 2866 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2867 case KVM_CAP_XEN_HVM:
3cfc3092 2868 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2869 case KVM_CAP_HYPERV:
10388a07 2870 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2871 case KVM_CAP_HYPERV_SPIN:
5c919412 2872 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2873 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2874 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2875 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2876 case KVM_CAP_HYPERV_TLBFLUSH:
ab9f4ecb 2877 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2878 case KVM_CAP_DEBUGREGS:
d2be1651 2879 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2880 case KVM_CAP_XSAVE:
344d9588 2881 case KVM_CAP_ASYNC_PF:
92a1f12d 2882 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2883 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2884 case KVM_CAP_READONLY_MEM:
5f66b620 2885 case KVM_CAP_HYPERV_TIME:
100943c5 2886 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2887 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2888 case KVM_CAP_ENABLE_CAP_VM:
2889 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2890 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2891 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2892 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2893 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2894 r = 1;
2895 break;
01643c51
KH		 2896 case KVM_CAP_SYNC_REGS:
2897 r = KVM_SYNC_X86_VALID_FIELDS;
2898 break;
e3fd9a93
PB		 2899 case KVM_CAP_ADJUST_CLOCK:
2900 r = KVM_CLOCK_TSC_STABLE;
2901 break;
4d5422ce 2902 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 2903 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2904 if(kvm_can_mwait_in_guest())
2905 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2906 break;
6d396b55
PB		 2907 case KVM_CAP_X86_SMM:
2908 /* SMBASE is usually relocated above 1M on modern chipsets,
2909 * and SMM handlers might indeed rely on 4G segment limits,
2910 * so do not report SMM to be available if real mode is
2911 * emulated via vm86 mode. Still, do not go to great lengths
2912 * to avoid userspace's usage of the feature, because it is a
2913 * fringe case that is not enabled except via specific settings
2914 * of the module parameters.
2915 */
bc226f07 2916 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 2917 break;
774ead3a
AK		 2918 case KVM_CAP_VAPIC:
2919 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2920 break;
f725230a 2921 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2922 r = KVM_SOFT_MAX_VCPUS;
2923 break;
2924 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2925 r = KVM_MAX_VCPUS;
2926 break;
a988b910 2927 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2928 r = KVM_USER_MEM_SLOTS;
a988b910 2929 break;
a68a6a72
MT		 2930 case KVM_CAP_PV_MMU: /* obsolete */
2931 r = 0;
2f333bcb 2932 break;
890ca9ae
HY		 2933 case KVM_CAP_MCE:
2934 r = KVM_MAX_MCE_BANKS;
2935 break;
2d5b5a66 2936 case KVM_CAP_XCRS:
d366bf7e 2937 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2938 break;
92a1f12d
JR		 2939 case KVM_CAP_TSC_CONTROL:
2940 r = kvm_has_tsc_control;
2941 break;
37131313
RK		 2942 case KVM_CAP_X2APIC_API:
2943 r = KVM_X2APIC_API_VALID_FLAGS;
2944 break;
018d00d2 2945 default:
018d00d2
ZX		 2946 break;
2947 }
2948 return r;
2949
2950}
2951
043405e1
CO		 2952long kvm_arch_dev_ioctl(struct file *filp,
2953 unsigned int ioctl, unsigned long arg)
2954{
2955 void __user *argp = (void __user *)arg;
2956 long r;
2957
2958 switch (ioctl) {
2959 case KVM_GET_MSR_INDEX_LIST: {
2960 struct kvm_msr_list __user *user_msr_list = argp;
2961 struct kvm_msr_list msr_list;
2962 unsigned n;
2963
2964 r = -EFAULT;
2965 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2966 goto out;
2967 n = msr_list.nmsrs;
62ef68bb 2968 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2969 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2970 goto out;
2971 r = -E2BIG;
e125e7b6 2972 if (n < msr_list.nmsrs)
043405e1
CO		 2973 goto out;
2974 r = -EFAULT;
2975 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2976 num_msrs_to_save * sizeof(u32)))
2977 goto out;
e125e7b6 2978 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2979 &emulated_msrs,
62ef68bb 2980 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2981 goto out;
2982 r = 0;
2983 break;
2984 }
9c15bb1d
BP		 2985 case KVM_GET_SUPPORTED_CPUID:
2986 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2987 struct kvm_cpuid2 __user *cpuid_arg = argp;
2988 struct kvm_cpuid2 cpuid;
2989
2990 r = -EFAULT;
2991 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2992 goto out;
9c15bb1d
BP		 2993
2994 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2995 ioctl);
674eea0f
AK		 2996 if (r)
2997 goto out;
2998
2999 r = -EFAULT;
3000 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3001 goto out;
3002 r = 0;
3003 break;
3004 }
890ca9ae 3005 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3006 r = -EFAULT;
c45dcc71
AR		 3007 if (copy_to_user(argp, &kvm_mce_cap_supported,
3008 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3009 goto out;
3010 r = 0;
3011 break;
801e459a
TL		 3012 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3013 struct kvm_msr_list __user *user_msr_list = argp;
3014 struct kvm_msr_list msr_list;
3015 unsigned int n;
3016
3017 r = -EFAULT;
3018 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3019 goto out;
3020 n = msr_list.nmsrs;
3021 msr_list.nmsrs = num_msr_based_features;
3022 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3023 goto out;
3024 r = -E2BIG;
3025 if (n < msr_list.nmsrs)
3026 goto out;
3027 r = -EFAULT;
3028 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3029 num_msr_based_features * sizeof(u32)))
3030 goto out;
3031 r = 0;
3032 break;
3033 }
3034 case KVM_GET_MSRS:
3035 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3036 break;
890ca9ae 3037 }
043405e1
CO		 3038 default:
3039 r = -EINVAL;
3040 }
3041out:
3042 return r;
3043}
3044
f5f48ee1
SY		 3045static void wbinvd_ipi(void *garbage)
3046{
3047 wbinvd();
3048}
3049
3050static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3051{
e0f0bbc5 3052 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3053}
3054
313a3dc7
CO		 3055void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3056{
f5f48ee1
SY		 3057 /* Address WBINVD may be executed by guest */
3058 if (need_emulate_wbinvd(vcpu)) {
3059 if (kvm_x86_ops->has_wbinvd_exit())
3060 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3061 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3062 smp_call_function_single(vcpu->cpu,
3063 wbinvd_ipi, NULL, 1);
3064 }
3065
313a3dc7 3066 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3067
0dd6a6ed
ZA		 3068 /* Apply any externally detected TSC adjustments (due to suspend) */
3069 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3070 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3071 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3072 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3073 }
8f6055cb 3074
b0c39dc6 3075 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3076 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3077 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3078 if (tsc_delta < 0)
3079 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3080
b0c39dc6 3081 if (kvm_check_tsc_unstable()) {
07c1419a 3082 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3083 vcpu->arch.last_guest_tsc);
a545ab6a 3084 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3085 vcpu->arch.tsc_catchup = 1;
c285545f 3086 }
a749e247
PB		 3087
3088 if (kvm_lapic_hv_timer_in_use(vcpu))
3089 kvm_lapic_restart_hv_timer(vcpu);
3090
d98d07ca
MT		 3091 /*
3092 * On a host with synchronized TSC, there is no need to update
3093 * kvmclock on vcpu->cpu migration
3094 */
3095 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3096 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3097 if (vcpu->cpu != cpu)
1bd2009e 3098 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3099 vcpu->cpu = cpu;
6b7d7e76 3100 }
c9aaa895 3101
c9aaa895 3102 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3103}
3104
0b9f6c46
PX		 3105static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3106{
3107 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3108 return;
3109
fa55eedd 3110 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3111
4e335d9e 3112 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3113 &vcpu->arch.st.steal.preempted,
3114 offsetof(struct kvm_steal_time, preempted),
3115 sizeof(vcpu->arch.st.steal.preempted));
3116}
3117
313a3dc7
CO		 3118void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3119{
cc0d907c 3120 int idx;
de63ad4c
LM		 3121
3122 if (vcpu->preempted)
3123 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3124
931f261b
AA		 3125 /*
3126 * Disable page faults because we're in atomic context here.
3127 * kvm_write_guest_offset_cached() would call might_fault()
3128 * that relies on pagefault_disable() to tell if there's a
3129 * bug. NOTE: the write to guest memory may not go through if
3130 * during postcopy live migration or if there's heavy guest
3131 * paging.
3132 */
3133 pagefault_disable();
cc0d907c
AA		 3134 /*
3135 * kvm_memslots() will be called by
3136 * kvm_write_guest_offset_cached() so take the srcu lock.
3137 */
3138 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3139 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3140 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3141 pagefault_enable();
02daab21 3142 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3143 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3144 /*
3145 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3146 * on every vmexit, but if not, we might have a stale dr6 from the
3147 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3148 */
3149 set_debugreg(0, 6);
313a3dc7
CO		 3150}
3151
313a3dc7
CO		 3152static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3153 struct kvm_lapic_state *s)
3154{
fa59cc00 3155 if (vcpu->arch.apicv_active)
d62caabb
AS		 3156 kvm_x86_ops->sync_pir_to_irr(vcpu);
3157
a92e2543 3158 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3159}
3160
3161static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3162 struct kvm_lapic_state *s)
3163{
a92e2543
RK		 3164 int r;
3165
3166 r = kvm_apic_set_state(vcpu, s);
3167 if (r)
3168 return r;
cb142eb7 3169 update_cr8_intercept(vcpu);
313a3dc7
CO		 3170
3171 return 0;
3172}
3173
127a457a
MG		 3174static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3175{
3176 return (!lapic_in_kernel(vcpu) ||
3177 kvm_apic_accept_pic_intr(vcpu));
3178}
3179
782d422b
MG		 3180/*
3181 * if userspace requested an interrupt window, check that the
3182 * interrupt window is open.
3183 *
3184 * No need to exit to userspace if we already have an interrupt queued.
3185 */
3186static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3187{
3188 return kvm_arch_interrupt_allowed(vcpu) &&
3189 !kvm_cpu_has_interrupt(vcpu) &&
3190 !kvm_event_needs_reinjection(vcpu) &&
3191 kvm_cpu_accept_dm_intr(vcpu);
3192}
3193
f77bc6a4
ZX		 3194static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3195 struct kvm_interrupt *irq)
3196{
02cdb50f 3197 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3198 return -EINVAL;
1c1a9ce9
SR		 3199
3200 if (!irqchip_in_kernel(vcpu->kvm)) {
3201 kvm_queue_interrupt(vcpu, irq->irq, false);
3202 kvm_make_request(KVM_REQ_EVENT, vcpu);
3203 return 0;
3204 }
3205
3206 /*
3207 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3208 * fail for in-kernel 8259.
3209 */
3210 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3211 return -ENXIO;
f77bc6a4 3212
1c1a9ce9
SR		 3213 if (vcpu->arch.pending_external_vector != -1)
3214 return -EEXIST;
f77bc6a4 3215
1c1a9ce9 3216 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3217 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3218 return 0;
3219}
3220
c4abb7c9
JK		 3221static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3222{
c4abb7c9 3223 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3224
3225 return 0;
3226}
3227
f077825a
PB		 3228static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3229{
64d60670
PB		 3230 kvm_make_request(KVM_REQ_SMI, vcpu);
3231
f077825a
PB		 3232 return 0;
3233}
3234
b209749f
AK		 3235static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3236 struct kvm_tpr_access_ctl *tac)
3237{
3238 if (tac->flags)
3239 return -EINVAL;
3240 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3241 return 0;
3242}
3243
890ca9ae
HY		 3244static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3245 u64 mcg_cap)
3246{
3247 int r;
3248 unsigned bank_num = mcg_cap & 0xff, bank;
3249
3250 r = -EINVAL;
a9e38c3e 3251 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3252 goto out;
c45dcc71 3253 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3254 goto out;
3255 r = 0;
3256 vcpu->arch.mcg_cap = mcg_cap;
3257 /* Init IA32_MCG_CTL to all 1s */
3258 if (mcg_cap & MCG_CTL_P)
3259 vcpu->arch.mcg_ctl = ~(u64)0;
3260 /* Init IA32_MCi_CTL to all 1s */
3261 for (bank = 0; bank < bank_num; bank++)
3262 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3263
3264 if (kvm_x86_ops->setup_mce)
3265 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3266out:
3267 return r;
3268}
3269
3270static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3271 struct kvm_x86_mce *mce)
3272{
3273 u64 mcg_cap = vcpu->arch.mcg_cap;
3274 unsigned bank_num = mcg_cap & 0xff;
3275 u64 *banks = vcpu->arch.mce_banks;
3276
3277 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3278 return -EINVAL;
3279 /*
3280 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3281 * reporting is disabled
3282 */
3283 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3284 vcpu->arch.mcg_ctl != ~(u64)0)
3285 return 0;
3286 banks += 4 * mce->bank;
3287 /*
3288 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3289 * reporting is disabled for the bank
3290 */
3291 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3292 return 0;
3293 if (mce->status & MCI_STATUS_UC) {
3294 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3295 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3296 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3297 return 0;
3298 }
3299 if (banks[1] & MCI_STATUS_VAL)
3300 mce->status |= MCI_STATUS_OVER;
3301 banks[2] = mce->addr;
3302 banks[3] = mce->misc;
3303 vcpu->arch.mcg_status = mce->mcg_status;
3304 banks[1] = mce->status;
3305 kvm_queue_exception(vcpu, MC_VECTOR);
3306 } else if (!(banks[1] & MCI_STATUS_VAL)
3307 || !(banks[1] & MCI_STATUS_UC)) {
3308 if (banks[1] & MCI_STATUS_VAL)
3309 mce->status |= MCI_STATUS_OVER;
3310 banks[2] = mce->addr;
3311 banks[3] = mce->misc;
3312 banks[1] = mce->status;
3313 } else
3314 banks[1] |= MCI_STATUS_OVER;
3315 return 0;
3316}
3317
3cfc3092
JK		 3318static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3319 struct kvm_vcpu_events *events)
3320{
7460fb4a 3321 process_nmi(vcpu);
664f8e26
WL		 3322 /*
3323 * FIXME: pass injected and pending separately. This is only
3324 * needed for nested virtualization, whose state cannot be
3325 * migrated yet. For now we can combine them.
3326 */
03b82a30 3327 events->exception.injected =
664f8e26
WL		 3328 (vcpu->arch.exception.pending ||
3329 vcpu->arch.exception.injected) &&
03b82a30 3330 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3331 events->exception.nr = vcpu->arch.exception.nr;
3332 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3333 events->exception.pad = 0;
3cfc3092
JK		 3334 events->exception.error_code = vcpu->arch.exception.error_code;
3335
03b82a30 3336 events->interrupt.injected =
04140b41 3337 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3338 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3339 events->interrupt.soft = 0;
37ccdcbe 3340 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3341
3342 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3343 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3344 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3345 events->nmi.pad = 0;
3cfc3092 3346
66450a21 3347 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3348
f077825a
PB		 3349 events->smi.smm = is_smm(vcpu);
3350 events->smi.pending = vcpu->arch.smi_pending;
3351 events->smi.smm_inside_nmi =
3352 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3353 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3354
dab4b911 3355 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3356 | KVM_VCPUEVENT_VALID_SHADOW
3357 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3358 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3359}
3360
6ef4e07e
XG		 3361static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3362
3cfc3092
JK		 3363static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3364 struct kvm_vcpu_events *events)
3365{
dab4b911 3366 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3367 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3368 | KVM_VCPUEVENT_VALID_SHADOW
3369 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3370 return -EINVAL;
3371
78e546c8 3372 if (events->exception.injected &&
28d06353
JM		 3373 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3374 is_guest_mode(vcpu)))
78e546c8
PB		 3375 return -EINVAL;
3376
28bf2888
DH		 3377 /* INITs are latched while in SMM */
3378 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3379 (events->smi.smm || events->smi.pending) &&
3380 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3381 return -EINVAL;
3382
7460fb4a 3383 process_nmi(vcpu);
664f8e26 3384 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3385 vcpu->arch.exception.pending = events->exception.injected;
3386 vcpu->arch.exception.nr = events->exception.nr;
3387 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3388 vcpu->arch.exception.error_code = events->exception.error_code;
3389
04140b41 3390 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3391 vcpu->arch.interrupt.nr = events->interrupt.nr;
3392 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3393 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3394 kvm_x86_ops->set_interrupt_shadow(vcpu,
3395 events->interrupt.shadow);
3cfc3092
JK		 3396
3397 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3398 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3399 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3400 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3401
66450a21 3402 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3403 lapic_in_kernel(vcpu))
66450a21 3404 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3405
f077825a 3406 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3407 u32 hflags = vcpu->arch.hflags;
f077825a 3408 if (events->smi.smm)
6ef4e07e 3409 hflags |= HF_SMM_MASK;
f077825a 3410 else
6ef4e07e
XG		 3411 hflags &= ~HF_SMM_MASK;
3412 kvm_set_hflags(vcpu, hflags);
3413
f077825a 3414 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3415
3416 if (events->smi.smm) {
3417 if (events->smi.smm_inside_nmi)
3418 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3419 else
f4ef1910
WL		 3420 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3421 if (lapic_in_kernel(vcpu)) {
3422 if (events->smi.latched_init)
3423 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3424 else
3425 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3426 }
f077825a
PB		 3427 }
3428 }
3429
3842d135
AK		 3430 kvm_make_request(KVM_REQ_EVENT, vcpu);
3431
3cfc3092
JK		 3432 return 0;
3433}
3434
a1efbe77
JK		 3435static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3436 struct kvm_debugregs *dbgregs)
3437{
73aaf249
JK		 3438 unsigned long val;
3439
a1efbe77 3440 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3441 kvm_get_dr(vcpu, 6, &val);
73aaf249 3442 dbgregs->dr6 = val;
a1efbe77
JK		 3443 dbgregs->dr7 = vcpu->arch.dr7;
3444 dbgregs->flags = 0;
97e69aa6 3445 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3446}
3447
3448static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3449 struct kvm_debugregs *dbgregs)
3450{
3451 if (dbgregs->flags)
3452 return -EINVAL;
3453
d14bdb55
PB		 3454 if (dbgregs->dr6 & ~0xffffffffull)
3455 return -EINVAL;
3456 if (dbgregs->dr7 & ~0xffffffffull)
3457 return -EINVAL;
3458
a1efbe77 3459 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3460 kvm_update_dr0123(vcpu);
a1efbe77 3461 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3462 kvm_update_dr6(vcpu);
a1efbe77 3463 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3464 kvm_update_dr7(vcpu);
a1efbe77 3465
a1efbe77
JK		 3466 return 0;
3467}
3468
df1daba7
PB		 3469#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3470
3471static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3472{
c47ada30 3473 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3474 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3475 u64 valid;
3476
3477 /*
3478 * Copy legacy XSAVE area, to avoid complications with CPUID
3479 * leaves 0 and 1 in the loop below.
3480 */
3481 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3482
3483 /* Set XSTATE_BV */
00c87e9a 3484 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3485 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3486
3487 /*
3488 * Copy each region from the possibly compacted offset to the
3489 * non-compacted offset.
3490 */
d91cab78 3491 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3492 while (valid) {
3493 u64 feature = valid & -valid;
3494 int index = fls64(feature) - 1;
3495 void *src = get_xsave_addr(xsave, feature);
3496
3497 if (src) {
3498 u32 size, offset, ecx, edx;
3499 cpuid_count(XSTATE_CPUID, index,
3500 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3501 if (feature == XFEATURE_MASK_PKRU)
3502 memcpy(dest + offset, &vcpu->arch.pkru,
3503 sizeof(vcpu->arch.pkru));
3504 else
3505 memcpy(dest + offset, src, size);
3506
df1daba7
PB		 3507 }
3508
3509 valid -= feature;
3510 }
3511}
3512
3513static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3514{
c47ada30 3515 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3516 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3517 u64 valid;
3518
3519 /*
3520 * Copy legacy XSAVE area, to avoid complications with CPUID
3521 * leaves 0 and 1 in the loop below.
3522 */
3523 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3524
3525 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3526 xsave->header.xfeatures = xstate_bv;
782511b0 3527 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3528 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3529
3530 /*
3531 * Copy each region from the non-compacted offset to the
3532 * possibly compacted offset.
3533 */
d91cab78 3534 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3535 while (valid) {
3536 u64 feature = valid & -valid;
3537 int index = fls64(feature) - 1;
3538 void *dest = get_xsave_addr(xsave, feature);
3539
3540 if (dest) {
3541 u32 size, offset, ecx, edx;
3542 cpuid_count(XSTATE_CPUID, index,
3543 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3544 if (feature == XFEATURE_MASK_PKRU)
3545 memcpy(&vcpu->arch.pkru, src + offset,
3546 sizeof(vcpu->arch.pkru));
3547 else
3548 memcpy(dest, src + offset, size);
ee4100da 3549 }
df1daba7
PB		 3550
3551 valid -= feature;
3552 }
3553}
3554
2d5b5a66
SY		 3555static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3556 struct kvm_xsave *guest_xsave)
3557{
d366bf7e 3558 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3559 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3560 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3561 } else {
2d5b5a66 3562 memcpy(guest_xsave->region,
7366ed77 3563 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3564 sizeof(struct fxregs_state));
2d5b5a66 3565 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3566 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3567 }
3568}
3569
a575813b
WL		 3570#define XSAVE_MXCSR_OFFSET 24
3571
2d5b5a66
SY		 3572static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3573 struct kvm_xsave *guest_xsave)
3574{
3575 u64 xstate_bv =
3576 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3577 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3578
d366bf7e 3579 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3580 /*
3581 * Here we allow setting states that are not present in
3582 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3583 * with old userspace.
3584 */
a575813b
WL		 3585 if (xstate_bv & ~kvm_supported_xcr0() ||
3586 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3587 return -EINVAL;
df1daba7 3588 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3589 } else {
a575813b
WL		 3590 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3591 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3592 return -EINVAL;
7366ed77 3593 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3594 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3595 }
3596 return 0;
3597}
3598
3599static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3600 struct kvm_xcrs *guest_xcrs)
3601{
d366bf7e 3602 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3603 guest_xcrs->nr_xcrs = 0;
3604 return;
3605 }
3606
3607 guest_xcrs->nr_xcrs = 1;
3608 guest_xcrs->flags = 0;
3609 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3610 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3611}
3612
3613static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3614 struct kvm_xcrs *guest_xcrs)
3615{
3616 int i, r = 0;
3617
d366bf7e 3618 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3619 return -EINVAL;
3620
3621 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3622 return -EINVAL;
3623
3624 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3625 /* Only support XCR0 currently */
c67a04cb 3626 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3627 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3628 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3629 break;
3630 }
3631 if (r)
3632 r = -EINVAL;
3633 return r;
3634}
3635
1c0b28c2
EM		 3636/*
3637 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3638 * stopped by the hypervisor. This function will be called from the host only.
3639 * EINVAL is returned when the host attempts to set the flag for a guest that
3640 * does not support pv clocks.
3641 */
3642static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3643{
0b79459b 3644 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3645 return -EINVAL;
51d59c6b 3646 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3647 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3648 return 0;
3649}
3650
5c919412
AS		 3651static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3652 struct kvm_enable_cap *cap)
3653{
3654 if (cap->flags)
3655 return -EINVAL;
3656
3657 switch (cap->cap) {
efc479e6
RK		 3658 case KVM_CAP_HYPERV_SYNIC2:
3659 if (cap->args[0])
3660 return -EINVAL;
5c919412 3661 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3662 if (!irqchip_in_kernel(vcpu->kvm))
3663 return -EINVAL;
efc479e6
RK		 3664 return kvm_hv_activate_synic(vcpu, cap->cap ==
3665 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3666 default:
3667 return -EINVAL;
3668 }
3669}
3670
313a3dc7
CO		 3671long kvm_arch_vcpu_ioctl(struct file *filp,
3672 unsigned int ioctl, unsigned long arg)
3673{
3674 struct kvm_vcpu *vcpu = filp->private_data;
3675 void __user *argp = (void __user *)arg;
3676 int r;
d1ac91d8
AK		 3677 union {
3678 struct kvm_lapic_state *lapic;
3679 struct kvm_xsave *xsave;
3680 struct kvm_xcrs *xcrs;
3681 void *buffer;
3682 } u;
3683
9b062471
CD		 3684 vcpu_load(vcpu);
3685
d1ac91d8 3686 u.buffer = NULL;
313a3dc7
CO		 3687 switch (ioctl) {
3688 case KVM_GET_LAPIC: {
2204ae3c 3689 r = -EINVAL;
bce87cce 3690 if (!lapic_in_kernel(vcpu))
2204ae3c 3691 goto out;
d1ac91d8 3692 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3693
b772ff36 3694 r = -ENOMEM;
d1ac91d8 3695 if (!u.lapic)
b772ff36 3696 goto out;
d1ac91d8 3697 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3698 if (r)
3699 goto out;
3700 r = -EFAULT;
d1ac91d8 3701 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3702 goto out;
3703 r = 0;
3704 break;
3705 }
3706 case KVM_SET_LAPIC: {
2204ae3c 3707 r = -EINVAL;
bce87cce 3708 if (!lapic_in_kernel(vcpu))
2204ae3c 3709 goto out;
ff5c2c03 3710 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3711 if (IS_ERR(u.lapic)) {
3712 r = PTR_ERR(u.lapic);
3713 goto out_nofree;
3714 }
ff5c2c03 3715
d1ac91d8 3716 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3717 break;
3718 }
f77bc6a4
ZX		 3719 case KVM_INTERRUPT: {
3720 struct kvm_interrupt irq;
3721
3722 r = -EFAULT;
3723 if (copy_from_user(&irq, argp, sizeof irq))
3724 goto out;
3725 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3726 break;
3727 }
c4abb7c9
JK		 3728 case KVM_NMI: {
3729 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3730 break;
3731 }
f077825a
PB		 3732 case KVM_SMI: {
3733 r = kvm_vcpu_ioctl_smi(vcpu);
3734 break;
3735 }
313a3dc7
CO		 3736 case KVM_SET_CPUID: {
3737 struct kvm_cpuid __user *cpuid_arg = argp;
3738 struct kvm_cpuid cpuid;
3739
3740 r = -EFAULT;
3741 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3742 goto out;
3743 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3744 break;
3745 }
07716717
DK		 3746 case KVM_SET_CPUID2: {
3747 struct kvm_cpuid2 __user *cpuid_arg = argp;
3748 struct kvm_cpuid2 cpuid;
3749
3750 r = -EFAULT;
3751 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3752 goto out;
3753 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3754 cpuid_arg->entries);
07716717
DK		 3755 break;
3756 }
3757 case KVM_GET_CPUID2: {
3758 struct kvm_cpuid2 __user *cpuid_arg = argp;
3759 struct kvm_cpuid2 cpuid;
3760
3761 r = -EFAULT;
3762 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3763 goto out;
3764 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3765 cpuid_arg->entries);
07716717
DK		 3766 if (r)
3767 goto out;
3768 r = -EFAULT;
3769 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3770 goto out;
3771 r = 0;
3772 break;
3773 }
801e459a
TL		 3774 case KVM_GET_MSRS: {
3775 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3776 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3777 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3778 break;
801e459a
TL		 3779 }
3780 case KVM_SET_MSRS: {
3781 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3782 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3783 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3784 break;
801e459a 3785 }
b209749f
AK		 3786 case KVM_TPR_ACCESS_REPORTING: {
3787 struct kvm_tpr_access_ctl tac;
3788
3789 r = -EFAULT;
3790 if (copy_from_user(&tac, argp, sizeof tac))
3791 goto out;
3792 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3793 if (r)
3794 goto out;
3795 r = -EFAULT;
3796 if (copy_to_user(argp, &tac, sizeof tac))
3797 goto out;
3798 r = 0;
3799 break;
3800 };
b93463aa
AK		 3801 case KVM_SET_VAPIC_ADDR: {
3802 struct kvm_vapic_addr va;
7301d6ab 3803 int idx;
b93463aa
AK		 3804
3805 r = -EINVAL;
35754c98 3806 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3807 goto out;
3808 r = -EFAULT;
3809 if (copy_from_user(&va, argp, sizeof va))
3810 goto out;
7301d6ab 3811 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3812 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3813 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3814 break;
3815 }
890ca9ae
HY		 3816 case KVM_X86_SETUP_MCE: {
3817 u64 mcg_cap;
3818
3819 r = -EFAULT;
3820 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3821 goto out;
3822 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3823 break;
3824 }
3825 case KVM_X86_SET_MCE: {
3826 struct kvm_x86_mce mce;
3827
3828 r = -EFAULT;
3829 if (copy_from_user(&mce, argp, sizeof mce))
3830 goto out;
3831 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3832 break;
3833 }
3cfc3092
JK		 3834 case KVM_GET_VCPU_EVENTS: {
3835 struct kvm_vcpu_events events;
3836
3837 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3838
3839 r = -EFAULT;
3840 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3841 break;
3842 r = 0;
3843 break;
3844 }
3845 case KVM_SET_VCPU_EVENTS: {
3846 struct kvm_vcpu_events events;
3847
3848 r = -EFAULT;
3849 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3850 break;
3851
3852 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3853 break;
3854 }
a1efbe77
JK		 3855 case KVM_GET_DEBUGREGS: {
3856 struct kvm_debugregs dbgregs;
3857
3858 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3859
3860 r = -EFAULT;
3861 if (copy_to_user(argp, &dbgregs,
3862 sizeof(struct kvm_debugregs)))
3863 break;
3864 r = 0;
3865 break;
3866 }
3867 case KVM_SET_DEBUGREGS: {
3868 struct kvm_debugregs dbgregs;
3869
3870 r = -EFAULT;
3871 if (copy_from_user(&dbgregs, argp,
3872 sizeof(struct kvm_debugregs)))
3873 break;
3874
3875 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3876 break;
3877 }
2d5b5a66 3878 case KVM_GET_XSAVE: {
d1ac91d8 3879 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3880 r = -ENOMEM;
d1ac91d8 3881 if (!u.xsave)
2d5b5a66
SY		 3882 break;
3883
d1ac91d8 3884 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3885
3886 r = -EFAULT;
d1ac91d8 3887 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3888 break;
3889 r = 0;
3890 break;
3891 }
3892 case KVM_SET_XSAVE: {
ff5c2c03 3893 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3894 if (IS_ERR(u.xsave)) {
3895 r = PTR_ERR(u.xsave);
3896 goto out_nofree;
3897 }
2d5b5a66 3898
d1ac91d8 3899 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3900 break;
3901 }
3902 case KVM_GET_XCRS: {
d1ac91d8 3903 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3904 r = -ENOMEM;
d1ac91d8 3905 if (!u.xcrs)
2d5b5a66
SY		 3906 break;
3907
d1ac91d8 3908 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3909
3910 r = -EFAULT;
d1ac91d8 3911 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3912 sizeof(struct kvm_xcrs)))
3913 break;
3914 r = 0;
3915 break;
3916 }
3917 case KVM_SET_XCRS: {
ff5c2c03 3918 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3919 if (IS_ERR(u.xcrs)) {
3920 r = PTR_ERR(u.xcrs);
3921 goto out_nofree;
3922 }
2d5b5a66 3923
d1ac91d8 3924 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3925 break;
3926 }
92a1f12d
JR		 3927 case KVM_SET_TSC_KHZ: {
3928 u32 user_tsc_khz;
3929
3930 r = -EINVAL;
92a1f12d
JR		 3931 user_tsc_khz = (u32)arg;
3932
3933 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3934 goto out;
3935
cc578287
ZA		 3936 if (user_tsc_khz == 0)
3937 user_tsc_khz = tsc_khz;
3938
381d585c
HZ		 3939 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3940 r = 0;
92a1f12d 3941
92a1f12d
JR		 3942 goto out;
3943 }
3944 case KVM_GET_TSC_KHZ: {
cc578287 3945 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3946 goto out;
3947 }
1c0b28c2
EM		 3948 case KVM_KVMCLOCK_CTRL: {
3949 r = kvm_set_guest_paused(vcpu);
3950 goto out;
3951 }
5c919412
AS		 3952 case KVM_ENABLE_CAP: {
3953 struct kvm_enable_cap cap;
3954
3955 r = -EFAULT;
3956 if (copy_from_user(&cap, argp, sizeof(cap)))
3957 goto out;
3958 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3959 break;
3960 }
313a3dc7
CO		 3961 default:
3962 r = -EINVAL;
3963 }
3964out:
d1ac91d8 3965 kfree(u.buffer);
9b062471
CD		 3966out_nofree:
3967 vcpu_put(vcpu);
313a3dc7
CO		 3968 return r;
3969}
3970
1499fa80 3971vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 3972{
3973 return VM_FAULT_SIGBUS;
3974}
3975
1fe779f8
CO		 3976static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3977{
3978 int ret;
3979
3980 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3981 return -EINVAL;
1fe779f8
CO		 3982 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3983 return ret;
3984}
3985
b927a3ce
SY		 3986static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3987 u64 ident_addr)
3988{
2ac52ab8 3989 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3990}
3991
1fe779f8
CO		 3992static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3993 u32 kvm_nr_mmu_pages)
3994{
3995 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3996 return -EINVAL;
3997
79fac95e 3998 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3999
4000 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4001 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4002
79fac95e 4003 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4004 return 0;
4005}
4006
4007static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4008{
39de71ec 4009 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4010}
4011
1fe779f8
CO		 4012static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4013{
90bca052 4014 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4015 int r;
4016
4017 r = 0;
4018 switch (chip->chip_id) {
4019 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4020 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4021 sizeof(struct kvm_pic_state));
4022 break;
4023 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4024 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4025 sizeof(struct kvm_pic_state));
4026 break;
4027 case KVM_IRQCHIP_IOAPIC:
33392b49 4028 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4029 break;
4030 default:
4031 r = -EINVAL;
4032 break;
4033 }
4034 return r;
4035}
4036
4037static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4038{
90bca052 4039 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4040 int r;
4041
4042 r = 0;
4043 switch (chip->chip_id) {
4044 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4045 spin_lock(&pic->lock);
4046 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4047 sizeof(struct kvm_pic_state));
90bca052 4048 spin_unlock(&pic->lock);
1fe779f8
CO		 4049 break;
4050 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4051 spin_lock(&pic->lock);
4052 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4053 sizeof(struct kvm_pic_state));
90bca052 4054 spin_unlock(&pic->lock);
1fe779f8
CO		 4055 break;
4056 case KVM_IRQCHIP_IOAPIC:
33392b49 4057 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4058 break;
4059 default:
4060 r = -EINVAL;
4061 break;
4062 }
90bca052 4063 kvm_pic_update_irq(pic);
1fe779f8
CO		 4064 return r;
4065}
4066
e0f63cb9
SY		 4067static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4068{
34f3941c
RK		 4069 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4070
4071 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4072
4073 mutex_lock(&kps->lock);
4074 memcpy(ps, &kps->channels, sizeof(*ps));
4075 mutex_unlock(&kps->lock);
2da29bcc 4076 return 0;
e0f63cb9
SY		 4077}
4078
4079static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4080{
0185604c 4081 int i;
09edea72
RK		 4082 struct kvm_pit *pit = kvm->arch.vpit;
4083
4084 mutex_lock(&pit->pit_state.lock);
34f3941c 4085 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4086 for (i = 0; i < 3; i++)
09edea72
RK		 4087 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4088 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4089 return 0;
e9f42757
BK		 4090}
4091
4092static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4093{
e9f42757
BK		 4094 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4095 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4096 sizeof(ps->channels));
4097 ps->flags = kvm->arch.vpit->pit_state.flags;
4098 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4099 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4100 return 0;
e9f42757
BK		 4101}
4102
4103static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4104{
2da29bcc 4105 int start = 0;
0185604c 4106 int i;
e9f42757 4107 u32 prev_legacy, cur_legacy;
09edea72
RK		 4108 struct kvm_pit *pit = kvm->arch.vpit;
4109
4110 mutex_lock(&pit->pit_state.lock);
4111 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4112 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4113 if (!prev_legacy && cur_legacy)
4114 start = 1;
09edea72
RK		 4115 memcpy(&pit->pit_state.channels, &ps->channels,
4116 sizeof(pit->pit_state.channels));
4117 pit->pit_state.flags = ps->flags;
0185604c 4118 for (i = 0; i < 3; i++)
09edea72 4119 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4120 start && i == 0);
09edea72 4121 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4122 return 0;
e0f63cb9
SY		 4123}
4124
52d939a0
MT		 4125static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4126 struct kvm_reinject_control *control)
4127{
71474e2f
RK		 4128 struct kvm_pit *pit = kvm->arch.vpit;
4129
4130 if (!pit)
52d939a0 4131 return -ENXIO;
b39c90b6 4132
71474e2f
RK		 4133 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4134 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4135 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4136 */
4137 mutex_lock(&pit->pit_state.lock);
4138 kvm_pit_set_reinject(pit, control->pit_reinject);
4139 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4140
52d939a0
MT		 4141 return 0;
4142}
4143
95d4c16c 4144/**
60c34612
TY		 4145 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4146 * @kvm: kvm instance
4147 * @log: slot id and address to which we copy the log
95d4c16c 4148 *
e108ff2f
PB		 4149 * Steps 1-4 below provide general overview of dirty page logging. See
4150 * kvm_get_dirty_log_protect() function description for additional details.
4151 *
4152 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4153 * always flush the TLB (step 4) even if previous step failed and the dirty
4154 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4155 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4156 * writes will be marked dirty for next log read.
95d4c16c 4157 *
60c34612
TY		 4158 * 1. Take a snapshot of the bit and clear it if needed.
4159 * 2. Write protect the corresponding page.
e108ff2f
PB		 4160 * 3. Copy the snapshot to the userspace.
4161 * 4. Flush TLB's if needed.
5bb064dc 4162 */
60c34612 4163int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4164{
60c34612 4165 bool is_dirty = false;
e108ff2f 4166 int r;
5bb064dc 4167
79fac95e 4168 mutex_lock(&kvm->slots_lock);
5bb064dc 4169
88178fd4
KH		 4170 /*
4171 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4172 */
4173 if (kvm_x86_ops->flush_log_dirty)
4174 kvm_x86_ops->flush_log_dirty(kvm);
4175
e108ff2f 4176 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4177
4178 /*
4179 * All the TLBs can be flushed out of mmu lock, see the comments in
4180 * kvm_mmu_slot_remove_write_access().
4181 */
e108ff2f 4182 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4183 if (is_dirty)
4184 kvm_flush_remote_tlbs(kvm);
4185
79fac95e 4186 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4187 return r;
4188}
4189
aa2fbe6d
YZ		 4190int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4191 bool line_status)
23d43cf9
CD		 4192{
4193 if (!irqchip_in_kernel(kvm))
4194 return -ENXIO;
4195
4196 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4197 irq_event->irq, irq_event->level,
4198 line_status);
23d43cf9
CD		 4199 return 0;
4200}
4201
90de4a18
NA		 4202static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4203 struct kvm_enable_cap *cap)
4204{
4205 int r;
4206
4207 if (cap->flags)
4208 return -EINVAL;
4209
4210 switch (cap->cap) {
4211 case KVM_CAP_DISABLE_QUIRKS:
4212 kvm->arch.disabled_quirks = cap->args[0];
4213 r = 0;
4214 break;
49df6397
SR		 4215 case KVM_CAP_SPLIT_IRQCHIP: {
4216 mutex_lock(&kvm->lock);
b053b2ae
SR		 4217 r = -EINVAL;
4218 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4219 goto split_irqchip_unlock;
49df6397
SR		 4220 r = -EEXIST;
4221 if (irqchip_in_kernel(kvm))
4222 goto split_irqchip_unlock;
557abc40 4223 if (kvm->created_vcpus)
49df6397
SR		 4224 goto split_irqchip_unlock;
4225 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4226 if (r)
49df6397
SR		 4227 goto split_irqchip_unlock;
4228 /* Pairs with irqchip_in_kernel. */
4229 smp_wmb();
49776faf 4230 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4231 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4232 r = 0;
4233split_irqchip_unlock:
4234 mutex_unlock(&kvm->lock);
4235 break;
4236 }
37131313
RK		 4237 case KVM_CAP_X2APIC_API:
4238 r = -EINVAL;
4239 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4240 break;
4241
4242 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4243 kvm->arch.x2apic_format = true;
c519265f
RK		 4244 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4245 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4246
4247 r = 0;
4248 break;
4d5422ce
WL		 4249 case KVM_CAP_X86_DISABLE_EXITS:
4250 r = -EINVAL;
4251 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4252 break;
4253
4254 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4255 kvm_can_mwait_in_guest())
4256 kvm->arch.mwait_in_guest = true;
766d3571 4257 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4258 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4259 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4260 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4261 r = 0;
4262 break;
90de4a18
NA		 4263 default:
4264 r = -EINVAL;
4265 break;
4266 }
4267 return r;
4268}
4269
1fe779f8
CO		 4270long kvm_arch_vm_ioctl(struct file *filp,
4271 unsigned int ioctl, unsigned long arg)
4272{
4273 struct kvm *kvm = filp->private_data;
4274 void __user *argp = (void __user *)arg;
367e1319 4275 int r = -ENOTTY;
f0d66275
DH		 4276 /*
4277 * This union makes it completely explicit to gcc-3.x
4278 * that these two variables' stack usage should be
4279 * combined, not added together.
4280 */
4281 union {
4282 struct kvm_pit_state ps;
e9f42757 4283 struct kvm_pit_state2 ps2;
c5ff41ce 4284 struct kvm_pit_config pit_config;
f0d66275 4285 } u;
1fe779f8
CO		 4286
4287 switch (ioctl) {
4288 case KVM_SET_TSS_ADDR:
4289 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4290 break;
b927a3ce
SY		 4291 case KVM_SET_IDENTITY_MAP_ADDR: {
4292 u64 ident_addr;
4293
1af1ac91
DH		 4294 mutex_lock(&kvm->lock);
4295 r = -EINVAL;
4296 if (kvm->created_vcpus)
4297 goto set_identity_unlock;
b927a3ce
SY		 4298 r = -EFAULT;
4299 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4300 goto set_identity_unlock;
b927a3ce 4301 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4302set_identity_unlock:
4303 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4304 break;
4305 }
1fe779f8
CO		 4306 case KVM_SET_NR_MMU_PAGES:
4307 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4308 break;
4309 case KVM_GET_NR_MMU_PAGES:
4310 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4311 break;
3ddea128 4312 case KVM_CREATE_IRQCHIP: {
3ddea128 4313 mutex_lock(&kvm->lock);
09941366 4314
3ddea128 4315 r = -EEXIST;
35e6eaa3 4316 if (irqchip_in_kernel(kvm))
3ddea128 4317 goto create_irqchip_unlock;
09941366 4318
3e515705 4319 r = -EINVAL;
557abc40 4320 if (kvm->created_vcpus)
3e515705 4321 goto create_irqchip_unlock;
09941366
RK		 4322
4323 r = kvm_pic_init(kvm);
4324 if (r)
3ddea128 4325 goto create_irqchip_unlock;
09941366
RK		 4326
4327 r = kvm_ioapic_init(kvm);
4328 if (r) {
09941366 4329 kvm_pic_destroy(kvm);
3ddea128 4330 goto create_irqchip_unlock;
09941366
RK		 4331 }
4332
399ec807
AK		 4333 r = kvm_setup_default_irq_routing(kvm);
4334 if (r) {
72bb2fcd 4335 kvm_ioapic_destroy(kvm);
09941366 4336 kvm_pic_destroy(kvm);
71ba994c 4337 goto create_irqchip_unlock;
399ec807 4338 }
49776faf 4339 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4340 smp_wmb();
49776faf 4341 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4342 create_irqchip_unlock:
4343 mutex_unlock(&kvm->lock);
1fe779f8 4344 break;
3ddea128 4345 }
7837699f 4346 case KVM_CREATE_PIT:
c5ff41ce
JK		 4347 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4348 goto create_pit;
4349 case KVM_CREATE_PIT2:
4350 r = -EFAULT;
4351 if (copy_from_user(&u.pit_config, argp,
4352 sizeof(struct kvm_pit_config)))
4353 goto out;
4354 create_pit:
250715a6 4355 mutex_lock(&kvm->lock);
269e05e4
AK		 4356 r = -EEXIST;
4357 if (kvm->arch.vpit)
4358 goto create_pit_unlock;
7837699f 4359 r = -ENOMEM;
c5ff41ce 4360 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4361 if (kvm->arch.vpit)
4362 r = 0;
269e05e4 4363 create_pit_unlock:
250715a6 4364 mutex_unlock(&kvm->lock);
7837699f 4365 break;
1fe779f8
CO		 4366 case KVM_GET_IRQCHIP: {
4367 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4368 struct kvm_irqchip *chip;
1fe779f8 4369
ff5c2c03
SL		 4370 chip = memdup_user(argp, sizeof(*chip));
4371 if (IS_ERR(chip)) {
4372 r = PTR_ERR(chip);
1fe779f8 4373 goto out;
ff5c2c03
SL		 4374 }
4375
1fe779f8 4376 r = -ENXIO;
826da321 4377 if (!irqchip_kernel(kvm))
f0d66275
DH		 4378 goto get_irqchip_out;
4379 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4380 if (r)
f0d66275 4381 goto get_irqchip_out;
1fe779f8 4382 r = -EFAULT;
f0d66275
DH		 4383 if (copy_to_user(argp, chip, sizeof *chip))
4384 goto get_irqchip_out;
1fe779f8 4385 r = 0;
f0d66275
DH		 4386 get_irqchip_out:
4387 kfree(chip);
1fe779f8
CO		 4388 break;
4389 }
4390 case KVM_SET_IRQCHIP: {
4391 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4392 struct kvm_irqchip *chip;
1fe779f8 4393
ff5c2c03
SL		 4394 chip = memdup_user(argp, sizeof(*chip));
4395 if (IS_ERR(chip)) {
4396 r = PTR_ERR(chip);
1fe779f8 4397 goto out;
ff5c2c03
SL		 4398 }
4399
1fe779f8 4400 r = -ENXIO;
826da321 4401 if (!irqchip_kernel(kvm))
f0d66275
DH		 4402 goto set_irqchip_out;
4403 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4404 if (r)
f0d66275 4405 goto set_irqchip_out;
1fe779f8 4406 r = 0;
f0d66275
DH		 4407 set_irqchip_out:
4408 kfree(chip);
1fe779f8
CO		 4409 break;
4410 }
e0f63cb9 4411 case KVM_GET_PIT: {
e0f63cb9 4412 r = -EFAULT;
f0d66275 4413 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4414 goto out;
4415 r = -ENXIO;
4416 if (!kvm->arch.vpit)
4417 goto out;
f0d66275 4418 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4419 if (r)
4420 goto out;
4421 r = -EFAULT;
f0d66275 4422 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4423 goto out;
4424 r = 0;
4425 break;
4426 }
4427 case KVM_SET_PIT: {
e0f63cb9 4428 r = -EFAULT;
f0d66275 4429 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4430 goto out;
4431 r = -ENXIO;
4432 if (!kvm->arch.vpit)
4433 goto out;
f0d66275 4434 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4435 break;
4436 }
e9f42757
BK		 4437 case KVM_GET_PIT2: {
4438 r = -ENXIO;
4439 if (!kvm->arch.vpit)
4440 goto out;
4441 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4442 if (r)
4443 goto out;
4444 r = -EFAULT;
4445 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4446 goto out;
4447 r = 0;
4448 break;
4449 }
4450 case KVM_SET_PIT2: {
4451 r = -EFAULT;
4452 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4453 goto out;
4454 r = -ENXIO;
4455 if (!kvm->arch.vpit)
4456 goto out;
4457 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4458 break;
4459 }
52d939a0
MT		 4460 case KVM_REINJECT_CONTROL: {
4461 struct kvm_reinject_control control;
4462 r = -EFAULT;
4463 if (copy_from_user(&control, argp, sizeof(control)))
4464 goto out;
4465 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4466 break;
4467 }
d71ba788
PB		 4468 case KVM_SET_BOOT_CPU_ID:
4469 r = 0;
4470 mutex_lock(&kvm->lock);
557abc40 4471 if (kvm->created_vcpus)
d71ba788
PB		 4472 r = -EBUSY;
4473 else
4474 kvm->arch.bsp_vcpu_id = arg;
4475 mutex_unlock(&kvm->lock);
4476 break;
ffde22ac 4477 case KVM_XEN_HVM_CONFIG: {
51776043 4478 struct kvm_xen_hvm_config xhc;
ffde22ac 4479 r = -EFAULT;
51776043 4480 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4481 goto out;
4482 r = -EINVAL;
51776043 4483 if (xhc.flags)
ffde22ac 4484 goto out;
51776043 4485 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4486 r = 0;
4487 break;
4488 }
afbcf7ab 4489 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4490 struct kvm_clock_data user_ns;
4491 u64 now_ns;
afbcf7ab
GC		 4492
4493 r = -EFAULT;
4494 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4495 goto out;
4496
4497 r = -EINVAL;
4498 if (user_ns.flags)
4499 goto out;
4500
4501 r = 0;
0bc48bea
RK		 4502 /*
4503 * TODO: userspace has to take care of races with VCPU_RUN, so
4504 * kvm_gen_update_masterclock() can be cut down to locked
4505 * pvclock_update_vm_gtod_copy().
4506 */
4507 kvm_gen_update_masterclock(kvm);
e891a32e 4508 now_ns = get_kvmclock_ns(kvm);
108b249c 4509 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4510 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4511 break;
4512 }
4513 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4514 struct kvm_clock_data user_ns;
4515 u64 now_ns;
4516
e891a32e 4517 now_ns = get_kvmclock_ns(kvm);
108b249c 4518 user_ns.clock = now_ns;
e3fd9a93 4519 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4520 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4521
4522 r = -EFAULT;
4523 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4524 goto out;
4525 r = 0;
4526 break;
4527 }
90de4a18
NA		 4528 case KVM_ENABLE_CAP: {
4529 struct kvm_enable_cap cap;
afbcf7ab 4530
90de4a18
NA		 4531 r = -EFAULT;
4532 if (copy_from_user(&cap, argp, sizeof(cap)))
4533 goto out;
4534 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4535 break;
4536 }
5acc5c06
BS		 4537 case KVM_MEMORY_ENCRYPT_OP: {
4538 r = -ENOTTY;
4539 if (kvm_x86_ops->mem_enc_op)
4540 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4541 break;
4542 }
69eaedee
BS		 4543 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4544 struct kvm_enc_region region;
4545
4546 r = -EFAULT;
4547 if (copy_from_user(&region, argp, sizeof(region)))
4548 goto out;
4549
4550 r = -ENOTTY;
4551 if (kvm_x86_ops->mem_enc_reg_region)
4552 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4553 break;
4554 }
4555 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4556 struct kvm_enc_region region;
4557
4558 r = -EFAULT;
4559 if (copy_from_user(&region, argp, sizeof(region)))
4560 goto out;
4561
4562 r = -ENOTTY;
4563 if (kvm_x86_ops->mem_enc_unreg_region)
4564 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4565 break;
4566 }
faeb7833
RK		 4567 case KVM_HYPERV_EVENTFD: {
4568 struct kvm_hyperv_eventfd hvevfd;
4569
4570 r = -EFAULT;
4571 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4572 goto out;
4573 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4574 break;
4575 }
1fe779f8 4576 default:
ad6260da 4577 r = -ENOTTY;
1fe779f8
CO		 4578 }
4579out:
4580 return r;
4581}
4582
a16b043c 4583static void kvm_init_msr_list(void)
043405e1
CO		 4584{
4585 u32 dummy[2];
4586 unsigned i, j;
4587
62ef68bb 4588 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4589 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4590 continue;
93c4adc7
PB		 4591
4592 /*
4593 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4594 * to the guests in some cases.
93c4adc7
PB		 4595 */
4596 switch (msrs_to_save[i]) {
4597 case MSR_IA32_BNDCFGS:
4598 if (!kvm_x86_ops->mpx_supported())
4599 continue;
4600 break;
9dbe6cf9
PB		 4601 case MSR_TSC_AUX:
4602 if (!kvm_x86_ops->rdtscp_supported())
4603 continue;
4604 break;
93c4adc7
PB		 4605 default:
4606 break;
4607 }
4608
043405e1
CO		 4609 if (j < i)
4610 msrs_to_save[j] = msrs_to_save[i];
4611 j++;
4612 }
4613 num_msrs_to_save = j;
62ef68bb
PB		 4614
4615 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4616 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4617 continue;
62ef68bb
PB		 4618
4619 if (j < i)
4620 emulated_msrs[j] = emulated_msrs[i];
4621 j++;
4622 }
4623 num_emulated_msrs = j;
801e459a
TL		 4624
4625 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4626 struct kvm_msr_entry msr;
4627
4628 msr.index = msr_based_features[i];
66421c1e 4629 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4630 continue;
4631
4632 if (j < i)
4633 msr_based_features[j] = msr_based_features[i];
4634 j++;
4635 }
4636 num_msr_based_features = j;
043405e1
CO		 4637}
4638
bda9020e
MT		 4639static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4640 const void *v)
bbd9b64e 4641{
70252a10
AK		 4642 int handled = 0;
4643 int n;
4644
4645 do {
4646 n = min(len, 8);
bce87cce 4647 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4648 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4649 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4650 break;
4651 handled += n;
4652 addr += n;
4653 len -= n;
4654 v += n;
4655 } while (len);
bbd9b64e 4656
70252a10 4657 return handled;
bbd9b64e
CO		 4658}
4659
bda9020e 4660static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4661{
70252a10
AK		 4662 int handled = 0;
4663 int n;
4664
4665 do {
4666 n = min(len, 8);
bce87cce 4667 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4668 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4669 addr, n, v))
4670 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4671 break;
e39d200f 4672 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4673 handled += n;
4674 addr += n;
4675 len -= n;
4676 v += n;
4677 } while (len);
bbd9b64e 4678
70252a10 4679 return handled;
bbd9b64e
CO		 4680}
4681
2dafc6c2
GN		 4682static void kvm_set_segment(struct kvm_vcpu *vcpu,
4683 struct kvm_segment *var, int seg)
4684{
4685 kvm_x86_ops->set_segment(vcpu, var, seg);
4686}
4687
4688void kvm_get_segment(struct kvm_vcpu *vcpu,
4689 struct kvm_segment *var, int seg)
4690{
4691 kvm_x86_ops->get_segment(vcpu, var, seg);
4692}
4693
54987b7a
PB		 4694gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4695 struct x86_exception *exception)
02f59dc9
JR		 4696{
4697 gpa_t t_gpa;
02f59dc9
JR		 4698
4699 BUG_ON(!mmu_is_nested(vcpu));
4700
4701 /* NPT walks are always user-walks */
4702 access |= PFERR_USER_MASK;
54987b7a 4703 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4704
4705 return t_gpa;
4706}
4707
ab9ae313
AK		 4708gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4709 struct x86_exception *exception)
1871c602
GN		 4710{
4711 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4712 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4713}
4714
ab9ae313
AK		 4715 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4716 struct x86_exception *exception)
1871c602
GN		 4717{
4718 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4719 access |= PFERR_FETCH_MASK;
ab9ae313 4720 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4721}
4722
ab9ae313
AK		 4723gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4724 struct x86_exception *exception)
1871c602
GN		 4725{
4726 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4727 access |= PFERR_WRITE_MASK;
ab9ae313 4728 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4729}
4730
4731/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4732gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4733 struct x86_exception *exception)
1871c602 4734{
ab9ae313 4735 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4736}
4737
4738static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4739 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4740 struct x86_exception *exception)
bbd9b64e
CO		 4741{
4742 void *data = val;
10589a46 4743 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4744
4745 while (bytes) {
14dfe855 4746 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4747 exception);
bbd9b64e 4748 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4749 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4750 int ret;
4751
bcc55cba 4752 if (gpa == UNMAPPED_GVA)
ab9ae313 4753 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4754 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4755 offset, toread);
10589a46 4756 if (ret < 0) {
c3cd7ffa 4757 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4758 goto out;
4759 }
bbd9b64e 4760
77c2002e
IE		 4761 bytes -= toread;
4762 data += toread;
4763 addr += toread;
bbd9b64e 4764 }
10589a46 4765out:
10589a46 4766 return r;
bbd9b64e 4767}
77c2002e 4768
1871c602 4769/* used for instruction fetching */
0f65dd70
AK		 4770static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4771 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4772 struct x86_exception *exception)
1871c602 4773{
0f65dd70 4774 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4775 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4776 unsigned offset;
4777 int ret;
0f65dd70 4778
44583cba
PB		 4779 /* Inline kvm_read_guest_virt_helper for speed. */
4780 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4781 exception);
4782 if (unlikely(gpa == UNMAPPED_GVA))
4783 return X86EMUL_PROPAGATE_FAULT;
4784
4785 offset = addr & (PAGE_SIZE-1);
4786 if (WARN_ON(offset + bytes > PAGE_SIZE))
4787 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4788 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4789 offset, bytes);
44583cba
PB		 4790 if (unlikely(ret < 0))
4791 return X86EMUL_IO_NEEDED;
4792
4793 return X86EMUL_CONTINUE;
1871c602
GN		 4794}
4795
ce14e868 4796int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 4797 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4798 struct x86_exception *exception)
1871c602
GN		 4799{
4800 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4801
1871c602 4802 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4803 exception);
1871c602 4804}
064aea77 4805EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4806
ce14e868
PB		 4807static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4808 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 4809 struct x86_exception *exception, bool system)
1871c602 4810{
0f65dd70 4811 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4812 u32 access = 0;
4813
4814 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4815 access |= PFERR_USER_MASK;
4816
4817 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 4818}
4819
7a036a6f
RK		 4820static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4821 unsigned long addr, void *val, unsigned int bytes)
4822{
4823 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4824 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4825
4826 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4827}
4828
ce14e868
PB		 4829static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4830 struct kvm_vcpu *vcpu, u32 access,
4831 struct x86_exception *exception)
77c2002e
IE		 4832{
4833 void *data = val;
4834 int r = X86EMUL_CONTINUE;
4835
4836 while (bytes) {
14dfe855 4837 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 4838 access,
ab9ae313 4839 exception);
77c2002e
IE		 4840 unsigned offset = addr & (PAGE_SIZE-1);
4841 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4842 int ret;
4843
bcc55cba 4844 if (gpa == UNMAPPED_GVA)
ab9ae313 4845 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4846 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4847 if (ret < 0) {
c3cd7ffa 4848 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4849 goto out;
4850 }
4851
4852 bytes -= towrite;
4853 data += towrite;
4854 addr += towrite;
4855 }
4856out:
4857 return r;
4858}
ce14e868
PB		 4859
4860static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 4861 unsigned int bytes, struct x86_exception *exception,
4862 bool system)
ce14e868
PB		 4863{
4864 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4865 u32 access = PFERR_WRITE_MASK;
4866
4867 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4868 access |= PFERR_USER_MASK;
ce14e868
PB		 4869
4870 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 4871 access, exception);
ce14e868
PB		 4872}
4873
4874int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
4875 unsigned int bytes, struct x86_exception *exception)
4876{
4877 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4878 PFERR_WRITE_MASK, exception);
4879}
6a4d7550 4880EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4881
082d06ed
WL		 4882int handle_ud(struct kvm_vcpu *vcpu)
4883{
6c86eedc 4884 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 4885 enum emulation_result er;
6c86eedc
WL		 4886 char sig[5]; /* ud2; .ascii "kvm" */
4887 struct x86_exception e;
4888
4889 if (force_emulation_prefix &&
3c9fa24c
PB		 4890 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
4891 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 4892 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4893 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4894 emul_type = 0;
4895 }
082d06ed 4896
6c86eedc 4897 er = emulate_instruction(vcpu, emul_type);
082d06ed
WL		 4898 if (er == EMULATE_USER_EXIT)
4899 return 0;
4900 if (er != EMULATE_DONE)
4901 kvm_queue_exception(vcpu, UD_VECTOR);
4902 return 1;
4903}
4904EXPORT_SYMBOL_GPL(handle_ud);
4905
0f89b207
TL		 4906static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4907 gpa_t gpa, bool write)
4908{
4909 /* For APIC access vmexit */
4910 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4911 return 1;
4912
4913 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4914 trace_vcpu_match_mmio(gva, gpa, write, true);
4915 return 1;
4916 }
4917
4918 return 0;
4919}
4920
af7cc7d1
XG		 4921static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4922 gpa_t *gpa, struct x86_exception *exception,
4923 bool write)
4924{
97d64b78
AK		 4925 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4926 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4927
be94f6b7
HH		 4928 /*
4929 * currently PKRU is only applied to ept enabled guest so
4930 * there is no pkey in EPT page table for L1 guest or EPT
4931 * shadow page table for L2 guest.
4932 */
97d64b78 4933 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4934 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4935 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4936 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4937 (gva & (PAGE_SIZE - 1));
4f022648 4938 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4939 return 1;
4940 }
4941
af7cc7d1
XG		 4942 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4943
4944 if (*gpa == UNMAPPED_GVA)
4945 return -1;
4946
0f89b207 4947 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4948}
4949
3200f405 4950int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4951 const void *val, int bytes)
bbd9b64e
CO		 4952{
4953 int ret;
4954
54bf36aa 4955 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4956 if (ret < 0)
bbd9b64e 4957 return 0;
0eb05bf2 4958 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4959 return 1;
4960}
4961
77d197b2
XG		 4962struct read_write_emulator_ops {
4963 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4964 int bytes);
4965 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4966 void *val, int bytes);
4967 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4968 int bytes, void *val);
4969 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4970 void *val, int bytes);
4971 bool write;
4972};
4973
4974static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4975{
4976 if (vcpu->mmio_read_completed) {
77d197b2 4977 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4978 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4979 vcpu->mmio_read_completed = 0;
4980 return 1;
4981 }
4982
4983 return 0;
4984}
4985
4986static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4987 void *val, int bytes)
4988{
54bf36aa 4989 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4990}
4991
4992static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4993 void *val, int bytes)
4994{
4995 return emulator_write_phys(vcpu, gpa, val, bytes);
4996}
4997
4998static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4999{
e39d200f 5000 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5001 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5002}
5003
5004static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5005 void *val, int bytes)
5006{
e39d200f 5007 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5008 return X86EMUL_IO_NEEDED;
5009}
5010
5011static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5012 void *val, int bytes)
5013{
f78146b0
AK		 5014 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5015
87da7e66 5016 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5017 return X86EMUL_CONTINUE;
5018}
5019
0fbe9b0b 5020static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5021 .read_write_prepare = read_prepare,
5022 .read_write_emulate = read_emulate,
5023 .read_write_mmio = vcpu_mmio_read,
5024 .read_write_exit_mmio = read_exit_mmio,
5025};
5026
0fbe9b0b 5027static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5028 .read_write_emulate = write_emulate,
5029 .read_write_mmio = write_mmio,
5030 .read_write_exit_mmio = write_exit_mmio,
5031 .write = true,
5032};
5033
22388a3c
XG		 5034static int emulator_read_write_onepage(unsigned long addr, void *val,
5035 unsigned int bytes,
5036 struct x86_exception *exception,
5037 struct kvm_vcpu *vcpu,
0fbe9b0b 5038 const struct read_write_emulator_ops *ops)
bbd9b64e 5039{
af7cc7d1
XG		 5040 gpa_t gpa;
5041 int handled, ret;
22388a3c 5042 bool write = ops->write;
f78146b0 5043 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5044 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5045
5046 /*
5047 * If the exit was due to a NPF we may already have a GPA.
5048 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5049 * Note, this cannot be used on string operations since string
5050 * operation using rep will only have the initial GPA from the NPF
5051 * occurred.
5052 */
5053 if (vcpu->arch.gpa_available &&
5054 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5055 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5056 gpa = vcpu->arch.gpa_val;
5057 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5058 } else {
5059 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5060 if (ret < 0)
5061 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5062 }
10589a46 5063
618232e2 5064 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5065 return X86EMUL_CONTINUE;
5066
bbd9b64e
CO		 5067 /*
5068 * Is this MMIO handled locally?
5069 */
22388a3c 5070 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5071 if (handled == bytes)
bbd9b64e 5072 return X86EMUL_CONTINUE;
bbd9b64e 5073
70252a10
AK		 5074 gpa += handled;
5075 bytes -= handled;
5076 val += handled;
5077
87da7e66
XG		 5078 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5079 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5080 frag->gpa = gpa;
5081 frag->data = val;
5082 frag->len = bytes;
f78146b0 5083 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5084}
5085
52eb5a6d
XL		 5086static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5087 unsigned long addr,
22388a3c
XG		 5088 void *val, unsigned int bytes,
5089 struct x86_exception *exception,
0fbe9b0b 5090 const struct read_write_emulator_ops *ops)
bbd9b64e 5091{
0f65dd70 5092 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5093 gpa_t gpa;
5094 int rc;
5095
5096 if (ops->read_write_prepare &&
5097 ops->read_write_prepare(vcpu, val, bytes))
5098 return X86EMUL_CONTINUE;
5099
5100 vcpu->mmio_nr_fragments = 0;
0f65dd70 5101
bbd9b64e
CO		 5102 /* Crossing a page boundary? */
5103 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5104 int now;
bbd9b64e
CO		 5105
5106 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5107 rc = emulator_read_write_onepage(addr, val, now, exception,
5108 vcpu, ops);
5109
bbd9b64e
CO		 5110 if (rc != X86EMUL_CONTINUE)
5111 return rc;
5112 addr += now;
bac15531
NA		 5113 if (ctxt->mode != X86EMUL_MODE_PROT64)
5114 addr = (u32)addr;
bbd9b64e
CO		 5115 val += now;
5116 bytes -= now;
5117 }
22388a3c 5118
f78146b0
AK		 5119 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5120 vcpu, ops);
5121 if (rc != X86EMUL_CONTINUE)
5122 return rc;
5123
5124 if (!vcpu->mmio_nr_fragments)
5125 return rc;
5126
5127 gpa = vcpu->mmio_fragments[0].gpa;
5128
5129 vcpu->mmio_needed = 1;
5130 vcpu->mmio_cur_fragment = 0;
5131
87da7e66 5132 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5133 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5134 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5135 vcpu->run->mmio.phys_addr = gpa;
5136
5137 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5138}
5139
5140static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5141 unsigned long addr,
5142 void *val,
5143 unsigned int bytes,
5144 struct x86_exception *exception)
5145{
5146 return emulator_read_write(ctxt, addr, val, bytes,
5147 exception, &read_emultor);
5148}
5149
52eb5a6d 5150static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5151 unsigned long addr,
5152 const void *val,
5153 unsigned int bytes,
5154 struct x86_exception *exception)
5155{
5156 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5157 exception, &write_emultor);
bbd9b64e 5158}
bbd9b64e 5159
daea3e73
AK		 5160#define CMPXCHG_TYPE(t, ptr, old, new) \
5161 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5162
5163#ifdef CONFIG_X86_64
5164# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5165#else
5166# define CMPXCHG64(ptr, old, new) \
9749a6c0 5167 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5168#endif
5169
0f65dd70
AK		 5170static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5171 unsigned long addr,
bbd9b64e
CO		 5172 const void *old,
5173 const void *new,
5174 unsigned int bytes,
0f65dd70 5175 struct x86_exception *exception)
bbd9b64e 5176{
0f65dd70 5177 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5178 gpa_t gpa;
5179 struct page *page;
5180 char *kaddr;
5181 bool exchanged;
2bacc55c 5182
daea3e73
AK		 5183 /* guests cmpxchg8b have to be emulated atomically */
5184 if (bytes > 8 || (bytes & (bytes - 1)))
5185 goto emul_write;
10589a46 5186
daea3e73 5187 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5188
daea3e73
AK		 5189 if (gpa == UNMAPPED_GVA ||
5190 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5191 goto emul_write;
2bacc55c 5192
daea3e73
AK		 5193 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5194 goto emul_write;
72dc67a6 5195
54bf36aa 5196 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5197 if (is_error_page(page))
c19b8bd6 5198 goto emul_write;
72dc67a6 5199
8fd75e12 5200 kaddr = kmap_atomic(page);
daea3e73
AK		 5201 kaddr += offset_in_page(gpa);
5202 switch (bytes) {
5203 case 1:
5204 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5205 break;
5206 case 2:
5207 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5208 break;
5209 case 4:
5210 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5211 break;
5212 case 8:
5213 exchanged = CMPXCHG64(kaddr, old, new);
5214 break;
5215 default:
5216 BUG();
2bacc55c 5217 }
8fd75e12 5218 kunmap_atomic(kaddr);
daea3e73
AK		 5219 kvm_release_page_dirty(page);
5220
5221 if (!exchanged)
5222 return X86EMUL_CMPXCHG_FAILED;
5223
54bf36aa 5224 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5225 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5226
5227 return X86EMUL_CONTINUE;
4a5f48f6 5228
3200f405 5229emul_write:
daea3e73 5230 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5231
0f65dd70 5232 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5233}
5234
cf8f70bf
GN		 5235static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5236{
cbfc6c91 5237 int r = 0, i;
cf8f70bf 5238
cbfc6c91
WL		 5239 for (i = 0; i < vcpu->arch.pio.count; i++) {
5240 if (vcpu->arch.pio.in)
5241 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5242 vcpu->arch.pio.size, pd);
5243 else
5244 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5245 vcpu->arch.pio.port, vcpu->arch.pio.size,
5246 pd);
5247 if (r)
5248 break;
5249 pd += vcpu->arch.pio.size;
5250 }
cf8f70bf
GN		 5251 return r;
5252}
5253
6f6fbe98
XG		 5254static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5255 unsigned short port, void *val,
5256 unsigned int count, bool in)
cf8f70bf 5257{
cf8f70bf 5258 vcpu->arch.pio.port = port;
6f6fbe98 5259 vcpu->arch.pio.in = in;
7972995b 5260 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5261 vcpu->arch.pio.size = size;
5262
5263 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5264 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5265 return 1;
5266 }
5267
5268 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5269 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5270 vcpu->run->io.size = size;
5271 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5272 vcpu->run->io.count = count;
5273 vcpu->run->io.port = port;
5274
5275 return 0;
5276}
5277
6f6fbe98
XG		 5278static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5279 int size, unsigned short port, void *val,
5280 unsigned int count)
cf8f70bf 5281{
ca1d4a9e 5282 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5283 int ret;
ca1d4a9e 5284
6f6fbe98
XG		 5285 if (vcpu->arch.pio.count)
5286 goto data_avail;
cf8f70bf 5287
cbfc6c91
WL		 5288 memset(vcpu->arch.pio_data, 0, size * count);
5289
6f6fbe98
XG		 5290 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5291 if (ret) {
5292data_avail:
5293 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5294 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5295 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5296 return 1;
5297 }
5298
cf8f70bf
GN		 5299 return 0;
5300}
5301
6f6fbe98
XG		 5302static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5303 int size, unsigned short port,
5304 const void *val, unsigned int count)
5305{
5306 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5307
5308 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5309 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5310 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5311}
5312
bbd9b64e
CO		 5313static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5314{
5315 return kvm_x86_ops->get_segment_base(vcpu, seg);
5316}
5317
3cb16fe7 5318static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5319{
3cb16fe7 5320 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5321}
5322
ae6a2375 5323static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5324{
5325 if (!need_emulate_wbinvd(vcpu))
5326 return X86EMUL_CONTINUE;
5327
5328 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5329 int cpu = get_cpu();
5330
5331 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5332 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5333 wbinvd_ipi, NULL, 1);
2eec7343 5334 put_cpu();
f5f48ee1 5335 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5336 } else
5337 wbinvd();
f5f48ee1
SY		 5338 return X86EMUL_CONTINUE;
5339}
5cb56059
JS		 5340
5341int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5342{
6affcbed
KH		 5343 kvm_emulate_wbinvd_noskip(vcpu);
5344 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5345}
f5f48ee1
SY		 5346EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5347
5cb56059
JS		 5348
5349
bcaf5cc5
AK		 5350static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5351{
5cb56059 5352 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5353}
5354
52eb5a6d
XL		 5355static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5356 unsigned long *dest)
bbd9b64e 5357{
16f8a6f9 5358 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5359}
5360
52eb5a6d
XL		 5361static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5362 unsigned long value)
bbd9b64e 5363{
338dbc97 5364
717746e3 5365 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5366}
5367
52a46617 5368static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5369{
52a46617 5370 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5371}
5372
717746e3 5373static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5374{
717746e3 5375 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5376 unsigned long value;
5377
5378 switch (cr) {
5379 case 0:
5380 value = kvm_read_cr0(vcpu);
5381 break;
5382 case 2:
5383 value = vcpu->arch.cr2;
5384 break;
5385 case 3:
9f8fe504 5386 value = kvm_read_cr3(vcpu);
52a46617
GN		 5387 break;
5388 case 4:
5389 value = kvm_read_cr4(vcpu);
5390 break;
5391 case 8:
5392 value = kvm_get_cr8(vcpu);
5393 break;
5394 default:
a737f256 5395 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5396 return 0;
5397 }
5398
5399 return value;
5400}
5401
717746e3 5402static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5403{
717746e3 5404 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5405 int res = 0;
5406
52a46617
GN		 5407 switch (cr) {
5408 case 0:
49a9b07e 5409 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5410 break;
5411 case 2:
5412 vcpu->arch.cr2 = val;
5413 break;
5414 case 3:
2390218b 5415 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5416 break;
5417 case 4:
a83b29c6 5418 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5419 break;
5420 case 8:
eea1cff9 5421 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5422 break;
5423 default:
a737f256 5424 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5425 res = -1;
52a46617 5426 }
0f12244f
GN		 5427
5428 return res;
52a46617
GN		 5429}
5430
717746e3 5431static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5432{
717746e3 5433 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5434}
5435
4bff1e86 5436static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5437{
4bff1e86 5438 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5439}
5440
4bff1e86 5441static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5442{
4bff1e86 5443 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5444}
5445
1ac9d0cf
AK		 5446static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5447{
5448 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5449}
5450
5451static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5452{
5453 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5454}
5455
4bff1e86
AK		 5456static unsigned long emulator_get_cached_segment_base(
5457 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5458{
4bff1e86 5459 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5460}
5461
1aa36616
AK		 5462static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5463 struct desc_struct *desc, u32 *base3,
5464 int seg)
2dafc6c2
GN		 5465{
5466 struct kvm_segment var;
5467
4bff1e86 5468 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5469 *selector = var.selector;
2dafc6c2 5470
378a8b09
GN		 5471 if (var.unusable) {
5472 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5473 if (base3)
5474 *base3 = 0;
2dafc6c2 5475 return false;
378a8b09 5476 }
2dafc6c2
GN		 5477
5478 if (var.g)
5479 var.limit >>= 12;
5480 set_desc_limit(desc, var.limit);
5481 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5482#ifdef CONFIG_X86_64
5483 if (base3)
5484 *base3 = var.base >> 32;
5485#endif
2dafc6c2
GN		 5486 desc->type = var.type;
5487 desc->s = var.s;
5488 desc->dpl = var.dpl;
5489 desc->p = var.present;
5490 desc->avl = var.avl;
5491 desc->l = var.l;
5492 desc->d = var.db;
5493 desc->g = var.g;
5494
5495 return true;
5496}
5497
1aa36616
AK		 5498static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5499 struct desc_struct *desc, u32 base3,
5500 int seg)
2dafc6c2 5501{
4bff1e86 5502 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5503 struct kvm_segment var;
5504
1aa36616 5505 var.selector = selector;
2dafc6c2 5506 var.base = get_desc_base(desc);
5601d05b
GN		 5507#ifdef CONFIG_X86_64
5508 var.base |= ((u64)base3) << 32;
5509#endif
2dafc6c2
GN		 5510 var.limit = get_desc_limit(desc);
5511 if (desc->g)
5512 var.limit = (var.limit << 12) | 0xfff;
5513 var.type = desc->type;
2dafc6c2
GN		 5514 var.dpl = desc->dpl;
5515 var.db = desc->d;
5516 var.s = desc->s;
5517 var.l = desc->l;
5518 var.g = desc->g;
5519 var.avl = desc->avl;
5520 var.present = desc->p;
5521 var.unusable = !var.present;
5522 var.padding = 0;
5523
5524 kvm_set_segment(vcpu, &var, seg);
5525 return;
5526}
5527
717746e3
AK		 5528static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5529 u32 msr_index, u64 *pdata)
5530{
609e36d3
PB		 5531 struct msr_data msr;
5532 int r;
5533
5534 msr.index = msr_index;
5535 msr.host_initiated = false;
5536 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5537 if (r)
5538 return r;
5539
5540 *pdata = msr.data;
5541 return 0;
717746e3
AK		 5542}
5543
5544static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5545 u32 msr_index, u64 data)
5546{
8fe8ab46
WA		 5547 struct msr_data msr;
5548
5549 msr.data = data;
5550 msr.index = msr_index;
5551 msr.host_initiated = false;
5552 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5553}
5554
64d60670
PB		 5555static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5556{
5557 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5558
5559 return vcpu->arch.smbase;
5560}
5561
5562static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5563{
5564 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5565
5566 vcpu->arch.smbase = smbase;
5567}
5568
67f4d428
NA		 5569static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5570 u32 pmc)
5571{
c6702c9d 5572 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5573}
5574
222d21aa
AK		 5575static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5576 u32 pmc, u64 *pdata)
5577{
c6702c9d 5578 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5579}
5580
6c3287f7
AK		 5581static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5582{
5583 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5584}
5585
2953538e 5586static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5587 struct x86_instruction_info *info,
c4f035c6
AK		 5588 enum x86_intercept_stage stage)
5589{
2953538e 5590 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5591}
5592
e911eb3b
YZ		 5593static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5594 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5595{
e911eb3b 5596 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5597}
5598
dd856efa
AK		 5599static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5600{
5601 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5602}
5603
5604static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5605{
5606 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5607}
5608
801806d9
NA		 5609static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5610{
5611 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5612}
5613
6ed071f0
LP		 5614static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5615{
5616 return emul_to_vcpu(ctxt)->arch.hflags;
5617}
5618
5619static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5620{
5621 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5622}
5623
0234bf88
LP		 5624static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5625{
5626 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5627}
5628
0225fb50 5629static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5630 .read_gpr = emulator_read_gpr,
5631 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5632 .read_std = emulator_read_std,
5633 .write_std = emulator_write_std,
7a036a6f 5634 .read_phys = kvm_read_guest_phys_system,
1871c602 5635 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5636 .read_emulated = emulator_read_emulated,
5637 .write_emulated = emulator_write_emulated,
5638 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5639 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5640 .pio_in_emulated = emulator_pio_in_emulated,
5641 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5642 .get_segment = emulator_get_segment,
5643 .set_segment = emulator_set_segment,
5951c442 5644 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5645 .get_gdt = emulator_get_gdt,
160ce1f1 5646 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5647 .set_gdt = emulator_set_gdt,
5648 .set_idt = emulator_set_idt,
52a46617
GN		 5649 .get_cr = emulator_get_cr,
5650 .set_cr = emulator_set_cr,
9c537244 5651 .cpl = emulator_get_cpl,
35aa5375
GN		 5652 .get_dr = emulator_get_dr,
5653 .set_dr = emulator_set_dr,
64d60670
PB		 5654 .get_smbase = emulator_get_smbase,
5655 .set_smbase = emulator_set_smbase,
717746e3
AK		 5656 .set_msr = emulator_set_msr,
5657 .get_msr = emulator_get_msr,
67f4d428 5658 .check_pmc = emulator_check_pmc,
222d21aa 5659 .read_pmc = emulator_read_pmc,
6c3287f7 5660 .halt = emulator_halt,
bcaf5cc5 5661 .wbinvd = emulator_wbinvd,
d6aa1000 5662 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5663 .intercept = emulator_intercept,
bdb42f5a 5664 .get_cpuid = emulator_get_cpuid,
801806d9 5665 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5666 .get_hflags = emulator_get_hflags,
5667 .set_hflags = emulator_set_hflags,
0234bf88 5668 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5669};
5670
95cb2295
GN		 5671static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5672{
37ccdcbe 5673 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5674 /*
5675 * an sti; sti; sequence only disable interrupts for the first
5676 * instruction. So, if the last instruction, be it emulated or
5677 * not, left the system with the INT_STI flag enabled, it
5678 * means that the last instruction is an sti. We should not
5679 * leave the flag on in this case. The same goes for mov ss
5680 */
37ccdcbe
PB		 5681 if (int_shadow & mask)
5682 mask = 0;
6addfc42 5683 if (unlikely(int_shadow || mask)) {
95cb2295 5684 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5685 if (!mask)
5686 kvm_make_request(KVM_REQ_EVENT, vcpu);
5687 }
95cb2295
GN		 5688}
5689
ef54bcfe 5690static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5691{
5692 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5693 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5694 return kvm_propagate_fault(vcpu, &ctxt->exception);
5695
5696 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5697 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5698 ctxt->exception.error_code);
54b8486f 5699 else
da9cb575 5700 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5701 return false;
54b8486f
GN		 5702}
5703
8ec4722d
MG		 5704static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5705{
adf52235 5706 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5707 int cs_db, cs_l;
5708
8ec4722d
MG		 5709 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5710
adf52235 5711 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5712 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5713
adf52235
TY		 5714 ctxt->eip = kvm_rip_read(vcpu);
5715 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5716 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5717 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5718 cs_db ? X86EMUL_MODE_PROT32 :
5719 X86EMUL_MODE_PROT16;
a584539b 5720 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5721 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5722 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5723
dd856efa 5724 init_decode_cache(ctxt);
7ae441ea 5725 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5726}
5727
71f9833b 5728int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5729{
9d74191a 5730 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5731 int ret;
5732
5733 init_emulate_ctxt(vcpu);
5734
9dac77fa
AK		 5735 ctxt->op_bytes = 2;
5736 ctxt->ad_bytes = 2;
5737 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5738 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5739
5740 if (ret != X86EMUL_CONTINUE)
5741 return EMULATE_FAIL;
5742
9dac77fa 5743 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5744 kvm_rip_write(vcpu, ctxt->eip);
5745 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5746
63995653
MG		 5747 return EMULATE_DONE;
5748}
5749EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5750
e2366171 5751static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5752{
fc3a9157
JR		 5753 int r = EMULATE_DONE;
5754
6d77dbfc
GN		 5755 ++vcpu->stat.insn_emulation_fail;
5756 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5757
5758 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5759 return EMULATE_FAIL;
5760
a2b9e6c1 5761 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5762 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5763 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5764 vcpu->run->internal.ndata = 0;
1f4dcb3b 5765 r = EMULATE_USER_EXIT;
fc3a9157 5766 }
e2366171 5767
6d77dbfc 5768 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5769
5770 return r;
6d77dbfc
GN		 5771}
5772
93c05d3e 5773static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5774 bool write_fault_to_shadow_pgtable,
5775 int emulation_type)
a6f177ef 5776{
95b3cf69 5777 gpa_t gpa = cr2;
ba049e93 5778 kvm_pfn_t pfn;
a6f177ef 5779
991eebf9
GN		 5780 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5781 return false;
5782
95b3cf69
XG		 5783 if (!vcpu->arch.mmu.direct_map) {
5784 /*
5785 * Write permission should be allowed since only
5786 * write access need to be emulated.
5787 */
5788 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5789
95b3cf69
XG		 5790 /*
5791 * If the mapping is invalid in guest, let cpu retry
5792 * it to generate fault.
5793 */
5794 if (gpa == UNMAPPED_GVA)
5795 return true;
5796 }
a6f177ef 5797
8e3d9d06
XG		 5798 /*
5799 * Do not retry the unhandleable instruction if it faults on the
5800 * readonly host memory, otherwise it will goto a infinite loop:
5801 * retry instruction -> write #PF -> emulation fail -> retry
5802 * instruction -> ...
5803 */
5804 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5805
5806 /*
5807 * If the instruction failed on the error pfn, it can not be fixed,
5808 * report the error to userspace.
5809 */
5810 if (is_error_noslot_pfn(pfn))
5811 return false;
5812
5813 kvm_release_pfn_clean(pfn);
5814
5815 /* The instructions are well-emulated on direct mmu. */
5816 if (vcpu->arch.mmu.direct_map) {
5817 unsigned int indirect_shadow_pages;
5818
5819 spin_lock(&vcpu->kvm->mmu_lock);
5820 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5821 spin_unlock(&vcpu->kvm->mmu_lock);
5822
5823 if (indirect_shadow_pages)
5824 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5825
a6f177ef 5826 return true;
8e3d9d06 5827 }
a6f177ef 5828
95b3cf69
XG		 5829 /*
5830 * if emulation was due to access to shadowed page table
5831 * and it failed try to unshadow page and re-enter the
5832 * guest to let CPU execute the instruction.
5833 */
5834 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5835
5836 /*
5837 * If the access faults on its page table, it can not
5838 * be fixed by unprotecting shadow page and it should
5839 * be reported to userspace.
5840 */
5841 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5842}
5843
1cb3f3ae
XG		 5844static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5845 unsigned long cr2, int emulation_type)
5846{
5847 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5848 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5849
5850 last_retry_eip = vcpu->arch.last_retry_eip;
5851 last_retry_addr = vcpu->arch.last_retry_addr;
5852
5853 /*
5854 * If the emulation is caused by #PF and it is non-page_table
5855 * writing instruction, it means the VM-EXIT is caused by shadow
5856 * page protected, we can zap the shadow page and retry this
5857 * instruction directly.
5858 *
5859 * Note: if the guest uses a non-page-table modifying instruction
5860 * on the PDE that points to the instruction, then we will unmap
5861 * the instruction and go to an infinite loop. So, we cache the
5862 * last retried eip and the last fault address, if we meet the eip
5863 * and the address again, we can break out of the potential infinite
5864 * loop.
5865 */
5866 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5867
5868 if (!(emulation_type & EMULTYPE_RETRY))
5869 return false;
5870
5871 if (x86_page_table_writing_insn(ctxt))
5872 return false;
5873
5874 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5875 return false;
5876
5877 vcpu->arch.last_retry_eip = ctxt->eip;
5878 vcpu->arch.last_retry_addr = cr2;
5879
5880 if (!vcpu->arch.mmu.direct_map)
5881 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5882
22368028 5883 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5884
5885 return true;
5886}
5887
716d51ab
GN		 5888static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5889static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5890
64d60670 5891static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5892{
64d60670 5893 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5894 /* This is a good place to trace that we are exiting SMM. */
5895 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5896
c43203ca
PB		 5897 /* Process a latched INIT or SMI, if any. */
5898 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5899 }
699023e2
PB		 5900
5901 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5902}
5903
5904static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5905{
5906 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5907
a584539b 5908 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5909
5910 if (changed & HF_SMM_MASK)
5911 kvm_smm_changed(vcpu);
a584539b
PB		 5912}
5913
4a1e10d5
PB		 5914static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5915 unsigned long *db)
5916{
5917 u32 dr6 = 0;
5918 int i;
5919 u32 enable, rwlen;
5920
5921 enable = dr7;
5922 rwlen = dr7 >> 16;
5923 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5924 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5925 dr6 |= (1 << i);
5926 return dr6;
5927}
5928
c8401dda 5929static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5930{
5931 struct kvm_run *kvm_run = vcpu->run;
5932
c8401dda
PB		 5933 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5934 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5935 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5936 kvm_run->debug.arch.exception = DB_VECTOR;
5937 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5938 *r = EMULATE_USER_EXIT;
5939 } else {
5940 /*
5941 * "Certain debug exceptions may clear bit 0-3. The
5942 * remaining contents of the DR6 register are never
5943 * cleared by the processor".
5944 */
5945 vcpu->arch.dr6 &= ~15;
5946 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5947 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5948 }
5949}
5950
6affcbed
KH		 5951int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5952{
5953 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5954 int r = EMULATE_DONE;
5955
5956 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5957
5958 /*
5959 * rflags is the old, "raw" value of the flags. The new value has
5960 * not been saved yet.
5961 *
5962 * This is correct even for TF set by the guest, because "the
5963 * processor will not generate this exception after the instruction
5964 * that sets the TF flag".
5965 */
5966 if (unlikely(rflags & X86_EFLAGS_TF))
5967 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5968 return r == EMULATE_DONE;
5969}
5970EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5971
4a1e10d5
PB		 5972static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5973{
4a1e10d5
PB		 5974 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5975 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5976 struct kvm_run *kvm_run = vcpu->run;
5977 unsigned long eip = kvm_get_linear_rip(vcpu);
5978 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5979 vcpu->arch.guest_debug_dr7,
5980 vcpu->arch.eff_db);
5981
5982 if (dr6 != 0) {
6f43ed01 5983 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5984 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5985 kvm_run->debug.arch.exception = DB_VECTOR;
5986 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5987 *r = EMULATE_USER_EXIT;
5988 return true;
5989 }
5990 }
5991
4161a569
NA		 5992 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5993 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5994 unsigned long eip = kvm_get_linear_rip(vcpu);
5995 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5996 vcpu->arch.dr7,
5997 vcpu->arch.db);
5998
5999 if (dr6 != 0) {
6000 vcpu->arch.dr6 &= ~15;
6f43ed01 6001 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6002 kvm_queue_exception(vcpu, DB_VECTOR);
6003 *r = EMULATE_DONE;
6004 return true;
6005 }
6006 }
6007
6008 return false;
6009}
6010
04789b66
LA		 6011static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6012{
2d7921c4
AM		 6013 switch (ctxt->opcode_len) {
6014 case 1:
6015 switch (ctxt->b) {
6016 case 0xe4: /* IN */
6017 case 0xe5:
6018 case 0xec:
6019 case 0xed:
6020 case 0xe6: /* OUT */
6021 case 0xe7:
6022 case 0xee:
6023 case 0xef:
6024 case 0x6c: /* INS */
6025 case 0x6d:
6026 case 0x6e: /* OUTS */
6027 case 0x6f:
6028 return true;
6029 }
6030 break;
6031 case 2:
6032 switch (ctxt->b) {
6033 case 0x33: /* RDPMC */
6034 return true;
6035 }
6036 break;
04789b66
LA		 6037 }
6038
6039 return false;
6040}
6041
51d8b661
AP		 6042int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6043 unsigned long cr2,
dc25e89e
AP		 6044 int emulation_type,
6045 void *insn,
6046 int insn_len)
bbd9b64e 6047{
95cb2295 6048 int r;
9d74191a 6049 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6050 bool writeback = true;
93c05d3e 6051 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6052
93c05d3e
XG		 6053 /*
6054 * Clear write_fault_to_shadow_pgtable here to ensure it is
6055 * never reused.
6056 */
6057 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6058 kvm_clear_exception_queue(vcpu);
8d7d8102 6059
571008da 6060 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6061 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6062
6063 /*
6064 * We will reenter on the same instruction since
6065 * we do not set complete_userspace_io. This does not
6066 * handle watchpoints yet, those would be handled in
6067 * the emulate_ops.
6068 */
d391f120
VK		 6069 if (!(emulation_type & EMULTYPE_SKIP) &&
6070 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6071 return r;
6072
9d74191a
TY		 6073 ctxt->interruptibility = 0;
6074 ctxt->have_exception = false;
e0ad0b47 6075 ctxt->exception.vector = -1;
9d74191a 6076 ctxt->perm_ok = false;
bbd9b64e 6077
b51e974f 6078 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6079
9d74191a 6080 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6081
e46479f8 6082 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6083 ++vcpu->stat.insn_emulation;
1d2887e2 6084 if (r != EMULATION_OK) {
4005996e
AK		 6085 if (emulation_type & EMULTYPE_TRAP_UD)
6086 return EMULATE_FAIL;
991eebf9
GN		 6087 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6088 emulation_type))
bbd9b64e 6089 return EMULATE_DONE;
6ea6e843
PB		 6090 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6091 return EMULATE_DONE;
6d77dbfc
GN		 6092 if (emulation_type & EMULTYPE_SKIP)
6093 return EMULATE_FAIL;
e2366171 6094 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6095 }
6096 }
6097
04789b66
LA		 6098 if ((emulation_type & EMULTYPE_VMWARE) &&
6099 !is_vmware_backdoor_opcode(ctxt))
6100 return EMULATE_FAIL;
6101
ba8afb6b 6102 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6103 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6104 if (ctxt->eflags & X86_EFLAGS_RF)
6105 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6106 return EMULATE_DONE;
6107 }
6108
1cb3f3ae
XG		 6109 if (retry_instruction(ctxt, cr2, emulation_type))
6110 return EMULATE_DONE;
6111
7ae441ea 6112 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6113 changes registers values during IO operation */
7ae441ea
GN		 6114 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6115 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6116 emulator_invalidate_register_cache(ctxt);
7ae441ea 6117 }
4d2179e1 6118
5cd21917 6119restart:
0f89b207
TL		 6120 /* Save the faulting GPA (cr2) in the address field */
6121 ctxt->exception.address = cr2;
6122
9d74191a 6123 r = x86_emulate_insn(ctxt);
bbd9b64e 6124
775fde86
JR		 6125 if (r == EMULATION_INTERCEPTED)
6126 return EMULATE_DONE;
6127
d2ddd1c4 6128 if (r == EMULATION_FAILED) {
991eebf9
GN		 6129 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6130 emulation_type))
c3cd7ffa
GN		 6131 return EMULATE_DONE;
6132
e2366171 6133 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6134 }
6135
9d74191a 6136 if (ctxt->have_exception) {
d2ddd1c4 6137 r = EMULATE_DONE;
ef54bcfe
PB		 6138 if (inject_emulated_exception(vcpu))
6139 return r;
d2ddd1c4 6140 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6141 if (!vcpu->arch.pio.in) {
6142 /* FIXME: return into emulator if single-stepping. */
3457e419 6143 vcpu->arch.pio.count = 0;
0912c977 6144 } else {
7ae441ea 6145 writeback = false;
716d51ab
GN		 6146 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6147 }
ac0a48c3 6148 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6149 } else if (vcpu->mmio_needed) {
6150 if (!vcpu->mmio_is_write)
6151 writeback = false;
ac0a48c3 6152 r = EMULATE_USER_EXIT;
716d51ab 6153 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6154 } else if (r == EMULATION_RESTART)
5cd21917 6155 goto restart;
d2ddd1c4
GN		 6156 else
6157 r = EMULATE_DONE;
f850e2e6 6158
7ae441ea 6159 if (writeback) {
6addfc42 6160 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6161 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6162 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6163 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6164 if (r == EMULATE_DONE &&
6165 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6166 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6167 if (!ctxt->have_exception ||
6168 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6169 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6170
6171 /*
6172 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6173 * do nothing, and it will be requested again as soon as
6174 * the shadow expires. But we still need to check here,
6175 * because POPF has no interrupt shadow.
6176 */
6177 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6178 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6179 } else
6180 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6181
6182 return r;
de7d789a 6183}
51d8b661 6184EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6185
dca7f128
SC		 6186static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6187 unsigned short port)
de7d789a 6188{
cf8f70bf 6189 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6190 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6191 size, port, &val, 1);
cf8f70bf 6192 /* do not return to emulator after return from userspace */
7972995b 6193 vcpu->arch.pio.count = 0;
de7d789a
CO		 6194 return ret;
6195}
de7d789a 6196
8370c3d0
TL		 6197static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6198{
6199 unsigned long val;
6200
6201 /* We should only ever be called with arch.pio.count equal to 1 */
6202 BUG_ON(vcpu->arch.pio.count != 1);
6203
6204 /* For size less than 4 we merge, else we zero extend */
6205 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6206 : 0;
6207
6208 /*
6209 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6210 * the copy and tracing
6211 */
6212 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6213 vcpu->arch.pio.port, &val, 1);
6214 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6215
6216 return 1;
6217}
6218
dca7f128
SC		 6219static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6220 unsigned short port)
8370c3d0
TL		 6221{
6222 unsigned long val;
6223 int ret;
6224
6225 /* For size less than 4 we merge, else we zero extend */
6226 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6227
6228 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6229 &val, 1);
6230 if (ret) {
6231 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6232 return ret;
6233 }
6234
6235 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6236
6237 return 0;
6238}
dca7f128
SC		 6239
6240int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6241{
6242 int ret = kvm_skip_emulated_instruction(vcpu);
6243
6244 /*
6245 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6246 * KVM_EXIT_DEBUG here.
6247 */
6248 if (in)
6249 return kvm_fast_pio_in(vcpu, size, port) && ret;
6250 else
6251 return kvm_fast_pio_out(vcpu, size, port) && ret;
6252}
6253EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6254
251a5fd6 6255static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6256{
0a3aee0d 6257 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6258 return 0;
8cfdc000
ZA		 6259}
6260
6261static void tsc_khz_changed(void *data)
c8076604 6262{
8cfdc000
ZA		 6263 struct cpufreq_freqs *freq = data;
6264 unsigned long khz = 0;
6265
6266 if (data)
6267 khz = freq->new;
6268 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6269 khz = cpufreq_quick_get(raw_smp_processor_id());
6270 if (!khz)
6271 khz = tsc_khz;
0a3aee0d 6272 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6273}
6274
5fa4ec9c 6275#ifdef CONFIG_X86_64
0092e434
VK		 6276static void kvm_hyperv_tsc_notifier(void)
6277{
0092e434
VK		 6278 struct kvm *kvm;
6279 struct kvm_vcpu *vcpu;
6280 int cpu;
6281
6282 spin_lock(&kvm_lock);
6283 list_for_each_entry(kvm, &vm_list, vm_list)
6284 kvm_make_mclock_inprogress_request(kvm);
6285
6286 hyperv_stop_tsc_emulation();
6287
6288 /* TSC frequency always matches when on Hyper-V */
6289 for_each_present_cpu(cpu)
6290 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6291 kvm_max_guest_tsc_khz = tsc_khz;
6292
6293 list_for_each_entry(kvm, &vm_list, vm_list) {
6294 struct kvm_arch *ka = &kvm->arch;
6295
6296 spin_lock(&ka->pvclock_gtod_sync_lock);
6297
6298 pvclock_update_vm_gtod_copy(kvm);
6299
6300 kvm_for_each_vcpu(cpu, vcpu, kvm)
6301 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6302
6303 kvm_for_each_vcpu(cpu, vcpu, kvm)
6304 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6305
6306 spin_unlock(&ka->pvclock_gtod_sync_lock);
6307 }
6308 spin_unlock(&kvm_lock);
0092e434 6309}
5fa4ec9c 6310#endif
0092e434 6311
c8076604
GH		 6312static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6313 void *data)
6314{
6315 struct cpufreq_freqs *freq = data;
6316 struct kvm *kvm;
6317 struct kvm_vcpu *vcpu;
6318 int i, send_ipi = 0;
6319
8cfdc000
ZA		 6320 /*
6321 * We allow guests to temporarily run on slowing clocks,
6322 * provided we notify them after, or to run on accelerating
6323 * clocks, provided we notify them before. Thus time never
6324 * goes backwards.
6325 *
6326 * However, we have a problem. We can't atomically update
6327 * the frequency of a given CPU from this function; it is
6328 * merely a notifier, which can be called from any CPU.
6329 * Changing the TSC frequency at arbitrary points in time
6330 * requires a recomputation of local variables related to
6331 * the TSC for each VCPU. We must flag these local variables
6332 * to be updated and be sure the update takes place with the
6333 * new frequency before any guests proceed.
6334 *
6335 * Unfortunately, the combination of hotplug CPU and frequency
6336 * change creates an intractable locking scenario; the order
6337 * of when these callouts happen is undefined with respect to
6338 * CPU hotplug, and they can race with each other. As such,
6339 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6340 * undefined; you can actually have a CPU frequency change take
6341 * place in between the computation of X and the setting of the
6342 * variable. To protect against this problem, all updates of
6343 * the per_cpu tsc_khz variable are done in an interrupt
6344 * protected IPI, and all callers wishing to update the value
6345 * must wait for a synchronous IPI to complete (which is trivial
6346 * if the caller is on the CPU already). This establishes the
6347 * necessary total order on variable updates.
6348 *
6349 * Note that because a guest time update may take place
6350 * anytime after the setting of the VCPU's request bit, the
6351 * correct TSC value must be set before the request. However,
6352 * to ensure the update actually makes it to any guest which
6353 * starts running in hardware virtualization between the set
6354 * and the acquisition of the spinlock, we must also ping the
6355 * CPU after setting the request bit.
6356 *
6357 */
6358
c8076604
GH		 6359 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6360 return 0;
6361 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6362 return 0;
8cfdc000
ZA		 6363
6364 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6365
2f303b74 6366 spin_lock(&kvm_lock);
c8076604 6367 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6368 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6369 if (vcpu->cpu != freq->cpu)
6370 continue;
c285545f 6371 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6372 if (vcpu->cpu != smp_processor_id())
8cfdc000 6373 send_ipi = 1;
c8076604
GH		 6374 }
6375 }
2f303b74 6376 spin_unlock(&kvm_lock);
c8076604
GH		 6377
6378 if (freq->old < freq->new && send_ipi) {
6379 /*
6380 * We upscale the frequency. Must make the guest
6381 * doesn't see old kvmclock values while running with
6382 * the new frequency, otherwise we risk the guest sees
6383 * time go backwards.
6384 *
6385 * In case we update the frequency for another cpu
6386 * (which might be in guest context) send an interrupt
6387 * to kick the cpu out of guest context. Next time
6388 * guest context is entered kvmclock will be updated,
6389 * so the guest will not see stale values.
6390 */
8cfdc000 6391 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6392 }
6393 return 0;
6394}
6395
6396static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6397 .notifier_call = kvmclock_cpufreq_notifier
6398};
6399
251a5fd6 6400static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6401{
251a5fd6
SAS		 6402 tsc_khz_changed(NULL);
6403 return 0;
8cfdc000
ZA		 6404}
6405
b820cc0c
ZA		 6406static void kvm_timer_init(void)
6407{
c285545f 6408 max_tsc_khz = tsc_khz;
460dd42e 6409
b820cc0c 6410 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6411#ifdef CONFIG_CPU_FREQ
6412 struct cpufreq_policy policy;
758f588d
BP		 6413 int cpu;
6414
c285545f 6415 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6416 cpu = get_cpu();
6417 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6418 if (policy.cpuinfo.max_freq)
6419 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6420 put_cpu();
c285545f 6421#endif
b820cc0c
ZA		 6422 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6423 CPUFREQ_TRANSITION_NOTIFIER);
6424 }
c285545f 6425 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6426
73c1b41e 6427 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6428 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6429}
6430
dd60d217
AK		 6431DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6432EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6433
f5132b01 6434int kvm_is_in_guest(void)
ff9d07a0 6435{
086c9855 6436 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6437}
6438
6439static int kvm_is_user_mode(void)
6440{
6441 int user_mode = 3;
dcf46b94 6442
086c9855
AS		 6443 if (__this_cpu_read(current_vcpu))
6444 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6445
ff9d07a0
ZY		 6446 return user_mode != 0;
6447}
6448
6449static unsigned long kvm_get_guest_ip(void)
6450{
6451 unsigned long ip = 0;
dcf46b94 6452
086c9855
AS		 6453 if (__this_cpu_read(current_vcpu))
6454 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6455
ff9d07a0
ZY		 6456 return ip;
6457}
6458
6459static struct perf_guest_info_callbacks kvm_guest_cbs = {
6460 .is_in_guest = kvm_is_in_guest,
6461 .is_user_mode = kvm_is_user_mode,
6462 .get_guest_ip = kvm_get_guest_ip,
6463};
6464
ce88decf
XG		 6465static void kvm_set_mmio_spte_mask(void)
6466{
6467 u64 mask;
6468 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6469
6470 /*
6471 * Set the reserved bits and the present bit of an paging-structure
6472 * entry to generate page fault with PFER.RSV = 1.
6473 */
885032b9 6474 /* Mask the reserved physical address bits. */
d1431483 6475 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6476
885032b9 6477 /* Set the present bit. */
ce88decf
XG		 6478 mask |= 1ull;
6479
6480#ifdef CONFIG_X86_64
6481 /*
6482 * If reserved bit is not supported, clear the present bit to disable
6483 * mmio page fault.
6484 */
6485 if (maxphyaddr == 52)
6486 mask &= ~1ull;
6487#endif
6488
dcdca5fe 6489 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6490}
6491
16e8d74d
MT		 6492#ifdef CONFIG_X86_64
6493static void pvclock_gtod_update_fn(struct work_struct *work)
6494{
d828199e
MT		 6495 struct kvm *kvm;
6496
6497 struct kvm_vcpu *vcpu;
6498 int i;
6499
2f303b74 6500 spin_lock(&kvm_lock);
d828199e
MT		 6501 list_for_each_entry(kvm, &vm_list, vm_list)
6502 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6503 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6504 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6505 spin_unlock(&kvm_lock);
16e8d74d
MT		 6506}
6507
6508static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6509
6510/*
6511 * Notification about pvclock gtod data update.
6512 */
6513static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6514 void *priv)
6515{
6516 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6517 struct timekeeper *tk = priv;
6518
6519 update_pvclock_gtod(tk);
6520
6521 /* disable master clock if host does not trust, or does not
b0c39dc6 6522 * use, TSC based clocksource.
16e8d74d 6523 */
b0c39dc6 6524 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6525 atomic_read(&kvm_guest_has_master_clock) != 0)
6526 queue_work(system_long_wq, &pvclock_gtod_work);
6527
6528 return 0;
6529}
6530
6531static struct notifier_block pvclock_gtod_notifier = {
6532 .notifier_call = pvclock_gtod_notify,
6533};
6534#endif
6535
f8c16bba 6536int kvm_arch_init(void *opaque)
043405e1 6537{
b820cc0c 6538 int r;
6b61edf7 6539 struct kvm_x86_ops *ops = opaque;
f8c16bba 6540
f8c16bba
ZX		 6541 if (kvm_x86_ops) {
6542 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6543 r = -EEXIST;
6544 goto out;
f8c16bba
ZX		 6545 }
6546
6547 if (!ops->cpu_has_kvm_support()) {
6548 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6549 r = -EOPNOTSUPP;
6550 goto out;
f8c16bba
ZX		 6551 }
6552 if (ops->disabled_by_bios()) {
6553 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6554 r = -EOPNOTSUPP;
6555 goto out;
f8c16bba
ZX		 6556 }
6557
013f6a5d
MT		 6558 r = -ENOMEM;
6559 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6560 if (!shared_msrs) {
6561 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6562 goto out;
6563 }
6564
97db56ce
AK		 6565 r = kvm_mmu_module_init();
6566 if (r)
013f6a5d 6567 goto out_free_percpu;
97db56ce 6568
ce88decf 6569 kvm_set_mmio_spte_mask();
97db56ce 6570
f8c16bba 6571 kvm_x86_ops = ops;
920c8377 6572
7b52345e 6573 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6574 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6575 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6576 kvm_timer_init();
c8076604 6577
ff9d07a0
ZY		 6578 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6579
d366bf7e 6580 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6581 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6582
c5cc421b 6583 kvm_lapic_init();
16e8d74d
MT		 6584#ifdef CONFIG_X86_64
6585 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6586
5fa4ec9c 6587 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6588 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6589#endif
6590
f8c16bba 6591 return 0;
56c6d28a 6592
013f6a5d
MT		 6593out_free_percpu:
6594 free_percpu(shared_msrs);
56c6d28a 6595out:
56c6d28a 6596 return r;
043405e1 6597}
8776e519 6598
f8c16bba
ZX		 6599void kvm_arch_exit(void)
6600{
0092e434 6601#ifdef CONFIG_X86_64
5fa4ec9c 6602 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6603 clear_hv_tscchange_cb();
6604#endif
cef84c30 6605 kvm_lapic_exit();
ff9d07a0
ZY		 6606 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6607
888d256e
JK		 6608 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6609 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6610 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6611 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6612#ifdef CONFIG_X86_64
6613 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6614#endif
f8c16bba 6615 kvm_x86_ops = NULL;
56c6d28a 6616 kvm_mmu_module_exit();
013f6a5d 6617 free_percpu(shared_msrs);
56c6d28a 6618}
f8c16bba 6619
5cb56059 6620int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6621{
6622 ++vcpu->stat.halt_exits;
35754c98 6623 if (lapic_in_kernel(vcpu)) {
a4535290 6624 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6625 return 1;
6626 } else {
6627 vcpu->run->exit_reason = KVM_EXIT_HLT;
6628 return 0;
6629 }
6630}
5cb56059
JS		 6631EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6632
6633int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6634{
6affcbed
KH		 6635 int ret = kvm_skip_emulated_instruction(vcpu);
6636 /*
6637 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6638 * KVM_EXIT_DEBUG here.
6639 */
6640 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6641}
8776e519
HB		 6642EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6643
8ef81a9a 6644#ifdef CONFIG_X86_64
55dd00a7
MT		 6645static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6646 unsigned long clock_type)
6647{
6648 struct kvm_clock_pairing clock_pairing;
899a31f5 6649 struct timespec64 ts;
80fbd89c 6650 u64 cycle;
55dd00a7
MT		 6651 int ret;
6652
6653 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6654 return -KVM_EOPNOTSUPP;
6655
6656 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6657 return -KVM_EOPNOTSUPP;
6658
6659 clock_pairing.sec = ts.tv_sec;
6660 clock_pairing.nsec = ts.tv_nsec;
6661 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6662 clock_pairing.flags = 0;
6663
6664 ret = 0;
6665 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6666 sizeof(struct kvm_clock_pairing)))
6667 ret = -KVM_EFAULT;
6668
6669 return ret;
6670}
8ef81a9a 6671#endif
55dd00a7 6672
6aef266c
SV		 6673/*
6674 * kvm_pv_kick_cpu_op: Kick a vcpu.
6675 *
6676 * @apicid - apicid of vcpu to be kicked.
6677 */
6678static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6679{
24d2166b 6680 struct kvm_lapic_irq lapic_irq;
6aef266c 6681
24d2166b
R		 6682 lapic_irq.shorthand = 0;
6683 lapic_irq.dest_mode = 0;
ebd28fcb 6684 lapic_irq.level = 0;
24d2166b 6685 lapic_irq.dest_id = apicid;
93bbf0b8 6686 lapic_irq.msi_redir_hint = false;
6aef266c 6687
24d2166b 6688 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6689 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6690}
6691
d62caabb
AS		 6692void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6693{
6694 vcpu->arch.apicv_active = false;
6695 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6696}
6697
8776e519
HB		 6698int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6699{
6700 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6701 int op_64_bit;
8776e519 6702
696ca779
RK		 6703 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6704 return kvm_hv_hypercall(vcpu);
55cd8e5a 6705
5fdbf976
MT		 6706 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6707 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6708 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6709 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6710 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6711
229456fc 6712 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6713
a449c7aa
NA		 6714 op_64_bit = is_64_bit_mode(vcpu);
6715 if (!op_64_bit) {
8776e519
HB		 6716 nr &= 0xFFFFFFFF;
6717 a0 &= 0xFFFFFFFF;
6718 a1 &= 0xFFFFFFFF;
6719 a2 &= 0xFFFFFFFF;
6720 a3 &= 0xFFFFFFFF;
6721 }
6722
07708c4a
JK		 6723 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6724 ret = -KVM_EPERM;
696ca779 6725 goto out;
07708c4a
JK		 6726 }
6727
8776e519 6728 switch (nr) {
b93463aa
AK		 6729 case KVM_HC_VAPIC_POLL_IRQ:
6730 ret = 0;
6731 break;
6aef266c
SV		 6732 case KVM_HC_KICK_CPU:
6733 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6734 ret = 0;
6735 break;
8ef81a9a 6736#ifdef CONFIG_X86_64
55dd00a7
MT		 6737 case KVM_HC_CLOCK_PAIRING:
6738 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6739 break;
8ef81a9a 6740#endif
8776e519
HB		 6741 default:
6742 ret = -KVM_ENOSYS;
6743 break;
6744 }
696ca779 6745out:
a449c7aa
NA		 6746 if (!op_64_bit)
6747 ret = (u32)ret;
5fdbf976 6748 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 6749
f11c3a8d 6750 ++vcpu->stat.hypercalls;
6356ee0c 6751 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6752}
6753EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6754
b6785def 6755static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6756{
d6aa1000 6757 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6758 char instruction[3];
5fdbf976 6759 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6760
8776e519 6761 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6762
ce2e852e
DV		 6763 return emulator_write_emulated(ctxt, rip, instruction, 3,
6764 &ctxt->exception);
8776e519
HB		 6765}
6766
851ba692 6767static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6768{
782d422b
MG		 6769 return vcpu->run->request_interrupt_window &&
6770 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6771}
6772
851ba692 6773static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6774{
851ba692
AK		 6775 struct kvm_run *kvm_run = vcpu->run;
6776
91586a3b 6777 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6778 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6779 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6780 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6781 kvm_run->ready_for_interrupt_injection =
6782 pic_in_kernel(vcpu->kvm) ||
782d422b 6783 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6784}
6785
95ba8273
GN		 6786static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6787{
6788 int max_irr, tpr;
6789
6790 if (!kvm_x86_ops->update_cr8_intercept)
6791 return;
6792
bce87cce 6793 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6794 return;
6795
d62caabb
AS		 6796 if (vcpu->arch.apicv_active)
6797 return;
6798
8db3baa2
GN		 6799 if (!vcpu->arch.apic->vapic_addr)
6800 max_irr = kvm_lapic_find_highest_irr(vcpu);
6801 else
6802 max_irr = -1;
95ba8273
GN		 6803
6804 if (max_irr != -1)
6805 max_irr >>= 4;
6806
6807 tpr = kvm_lapic_get_cr8(vcpu);
6808
6809 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6810}
6811
b6b8a145 6812static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6813{
b6b8a145
JK		 6814 int r;
6815
95ba8273 6816 /* try to reinject previous events if any */
664f8e26 6817
1a680e35
LA		 6818 if (vcpu->arch.exception.injected)
6819 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6820 /*
a042c26f
LA		 6821 * Do not inject an NMI or interrupt if there is a pending
6822 * exception. Exceptions and interrupts are recognized at
6823 * instruction boundaries, i.e. the start of an instruction.
6824 * Trap-like exceptions, e.g. #DB, have higher priority than
6825 * NMIs and interrupts, i.e. traps are recognized before an
6826 * NMI/interrupt that's pending on the same instruction.
6827 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6828 * priority, but are only generated (pended) during instruction
6829 * execution, i.e. a pending fault-like exception means the
6830 * fault occurred on the *previous* instruction and must be
6831 * serviced prior to recognizing any new events in order to
6832 * fully complete the previous instruction.
664f8e26 6833 */
1a680e35
LA		 6834 else if (!vcpu->arch.exception.pending) {
6835 if (vcpu->arch.nmi_injected)
664f8e26 6836 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6837 else if (vcpu->arch.interrupt.injected)
664f8e26 6838 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6839 }
6840
1a680e35
LA		 6841 /*
6842 * Call check_nested_events() even if we reinjected a previous event
6843 * in order for caller to determine if it should require immediate-exit
6844 * from L2 to L1 due to pending L1 events which require exit
6845 * from L2 to L1.
6846 */
664f8e26
WL		 6847 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6848 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6849 if (r != 0)
6850 return r;
6851 }
6852
6853 /* try to inject new event if pending */
b59bb7bd 6854 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6855 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6856 vcpu->arch.exception.has_error_code,
6857 vcpu->arch.exception.error_code);
d6e8c854 6858
1a680e35 6859 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 6860 vcpu->arch.exception.pending = false;
6861 vcpu->arch.exception.injected = true;
6862
d6e8c854
NA		 6863 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6864 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6865 X86_EFLAGS_RF);
6866
6bdf0662
NA		 6867 if (vcpu->arch.exception.nr == DB_VECTOR &&
6868 (vcpu->arch.dr7 & DR7_GD)) {
6869 vcpu->arch.dr7 &= ~DR7_GD;
6870 kvm_update_dr7(vcpu);
6871 }
6872
cfcd20e5 6873 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 6874 }
6875
6876 /* Don't consider new event if we re-injected an event */
6877 if (kvm_event_needs_reinjection(vcpu))
6878 return 0;
6879
6880 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6881 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6882 vcpu->arch.smi_pending = false;
52797bf9 6883 ++vcpu->arch.smi_count;
ee2cd4b7 6884 enter_smm(vcpu);
c43203ca 6885 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6886 --vcpu->arch.nmi_pending;
6887 vcpu->arch.nmi_injected = true;
6888 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6889 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6890 /*
6891 * Because interrupts can be injected asynchronously, we are
6892 * calling check_nested_events again here to avoid a race condition.
6893 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6894 * proposal and current concerns. Perhaps we should be setting
6895 * KVM_REQ_EVENT only on certain events and not unconditionally?
6896 */
6897 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6898 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6899 if (r != 0)
6900 return r;
6901 }
95ba8273 6902 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6903 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6904 false);
6905 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6906 }
6907 }
ee2cd4b7 6908
b6b8a145 6909 return 0;
95ba8273
GN		 6910}
6911
7460fb4a
AK		 6912static void process_nmi(struct kvm_vcpu *vcpu)
6913{
6914 unsigned limit = 2;
6915
6916 /*
6917 * x86 is limited to one NMI running, and one NMI pending after it.
6918 * If an NMI is already in progress, limit further NMIs to just one.
6919 * Otherwise, allow two (and we'll inject the first one immediately).
6920 */
6921 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6922 limit = 1;
6923
6924 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6925 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6926 kvm_make_request(KVM_REQ_EVENT, vcpu);
6927}
6928
ee2cd4b7 6929static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6930{
6931 u32 flags = 0;
6932 flags |= seg->g << 23;
6933 flags |= seg->db << 22;
6934 flags |= seg->l << 21;
6935 flags |= seg->avl << 20;
6936 flags |= seg->present << 15;
6937 flags |= seg->dpl << 13;
6938 flags |= seg->s << 12;
6939 flags |= seg->type << 8;
6940 return flags;
6941}
6942
ee2cd4b7 6943static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6944{
6945 struct kvm_segment seg;
6946 int offset;
6947
6948 kvm_get_segment(vcpu, &seg, n);
6949 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6950
6951 if (n < 3)
6952 offset = 0x7f84 + n * 12;
6953 else
6954 offset = 0x7f2c + (n - 3) * 12;
6955
6956 put_smstate(u32, buf, offset + 8, seg.base);
6957 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6958 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6959}
6960
efbb288a 6961#ifdef CONFIG_X86_64
ee2cd4b7 6962static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6963{
6964 struct kvm_segment seg;
6965 int offset;
6966 u16 flags;
6967
6968 kvm_get_segment(vcpu, &seg, n);
6969 offset = 0x7e00 + n * 16;
6970
ee2cd4b7 6971 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6972 put_smstate(u16, buf, offset, seg.selector);
6973 put_smstate(u16, buf, offset + 2, flags);
6974 put_smstate(u32, buf, offset + 4, seg.limit);
6975 put_smstate(u64, buf, offset + 8, seg.base);
6976}
efbb288a 6977#endif
660a5d51 6978
ee2cd4b7 6979static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6980{
6981 struct desc_ptr dt;
6982 struct kvm_segment seg;
6983 unsigned long val;
6984 int i;
6985
6986 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6987 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6988 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6989 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6990
6991 for (i = 0; i < 8; i++)
6992 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6993
6994 kvm_get_dr(vcpu, 6, &val);
6995 put_smstate(u32, buf, 0x7fcc, (u32)val);
6996 kvm_get_dr(vcpu, 7, &val);
6997 put_smstate(u32, buf, 0x7fc8, (u32)val);
6998
6999 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7000 put_smstate(u32, buf, 0x7fc4, seg.selector);
7001 put_smstate(u32, buf, 0x7f64, seg.base);
7002 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7003 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7004
7005 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7006 put_smstate(u32, buf, 0x7fc0, seg.selector);
7007 put_smstate(u32, buf, 0x7f80, seg.base);
7008 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7009 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7010
7011 kvm_x86_ops->get_gdt(vcpu, &dt);
7012 put_smstate(u32, buf, 0x7f74, dt.address);
7013 put_smstate(u32, buf, 0x7f70, dt.size);
7014
7015 kvm_x86_ops->get_idt(vcpu, &dt);
7016 put_smstate(u32, buf, 0x7f58, dt.address);
7017 put_smstate(u32, buf, 0x7f54, dt.size);
7018
7019 for (i = 0; i < 6; i++)
ee2cd4b7 7020 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7021
7022 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7023
7024 /* revision id */
7025 put_smstate(u32, buf, 0x7efc, 0x00020000);
7026 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7027}
7028
ee2cd4b7 7029static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7030{
7031#ifdef CONFIG_X86_64
7032 struct desc_ptr dt;
7033 struct kvm_segment seg;
7034 unsigned long val;
7035 int i;
7036
7037 for (i = 0; i < 16; i++)
7038 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7039
7040 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7041 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7042
7043 kvm_get_dr(vcpu, 6, &val);
7044 put_smstate(u64, buf, 0x7f68, val);
7045 kvm_get_dr(vcpu, 7, &val);
7046 put_smstate(u64, buf, 0x7f60, val);
7047
7048 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7049 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7050 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7051
7052 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7053
7054 /* revision id */
7055 put_smstate(u32, buf, 0x7efc, 0x00020064);
7056
7057 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7058
7059 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7060 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7061 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7062 put_smstate(u32, buf, 0x7e94, seg.limit);
7063 put_smstate(u64, buf, 0x7e98, seg.base);
7064
7065 kvm_x86_ops->get_idt(vcpu, &dt);
7066 put_smstate(u32, buf, 0x7e84, dt.size);
7067 put_smstate(u64, buf, 0x7e88, dt.address);
7068
7069 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7070 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7071 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7072 put_smstate(u32, buf, 0x7e74, seg.limit);
7073 put_smstate(u64, buf, 0x7e78, seg.base);
7074
7075 kvm_x86_ops->get_gdt(vcpu, &dt);
7076 put_smstate(u32, buf, 0x7e64, dt.size);
7077 put_smstate(u64, buf, 0x7e68, dt.address);
7078
7079 for (i = 0; i < 6; i++)
ee2cd4b7 7080 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7081#else
7082 WARN_ON_ONCE(1);
7083#endif
7084}
7085
ee2cd4b7 7086static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7087{
660a5d51 7088 struct kvm_segment cs, ds;
18c3626e 7089 struct desc_ptr dt;
660a5d51
PB		 7090 char buf[512];
7091 u32 cr0;
7092
660a5d51 7093 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7094 memset(buf, 0, 512);
d6321d49 7095 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7096 enter_smm_save_state_64(vcpu, buf);
660a5d51 7097 else
ee2cd4b7 7098 enter_smm_save_state_32(vcpu, buf);
660a5d51 7099
0234bf88
LP		 7100 /*
7101 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7102 * vCPU state (e.g. leave guest mode) after we've saved the state into
7103 * the SMM state-save area.
7104 */
7105 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7106
7107 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7108 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7109
7110 if (kvm_x86_ops->get_nmi_mask(vcpu))
7111 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7112 else
7113 kvm_x86_ops->set_nmi_mask(vcpu, true);
7114
7115 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7116 kvm_rip_write(vcpu, 0x8000);
7117
7118 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7119 kvm_x86_ops->set_cr0(vcpu, cr0);
7120 vcpu->arch.cr0 = cr0;
7121
7122 kvm_x86_ops->set_cr4(vcpu, 0);
7123
18c3626e
PB		 7124 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7125 dt.address = dt.size = 0;
7126 kvm_x86_ops->set_idt(vcpu, &dt);
7127
660a5d51
PB		 7128 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7129
7130 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7131 cs.base = vcpu->arch.smbase;
7132
7133 ds.selector = 0;
7134 ds.base = 0;
7135
7136 cs.limit = ds.limit = 0xffffffff;
7137 cs.type = ds.type = 0x3;
7138 cs.dpl = ds.dpl = 0;
7139 cs.db = ds.db = 0;
7140 cs.s = ds.s = 1;
7141 cs.l = ds.l = 0;
7142 cs.g = ds.g = 1;
7143 cs.avl = ds.avl = 0;
7144 cs.present = ds.present = 1;
7145 cs.unusable = ds.unusable = 0;
7146 cs.padding = ds.padding = 0;
7147
7148 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7149 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7150 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7151 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7152 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7153 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7154
d6321d49 7155 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7156 kvm_x86_ops->set_efer(vcpu, 0);
7157
7158 kvm_update_cpuid(vcpu);
7159 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7160}
7161
ee2cd4b7 7162static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7163{
7164 vcpu->arch.smi_pending = true;
7165 kvm_make_request(KVM_REQ_EVENT, vcpu);
7166}
7167
2860c4b1
PB		 7168void kvm_make_scan_ioapic_request(struct kvm *kvm)
7169{
7170 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7171}
7172
3d81bc7e 7173static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7174{
3d81bc7e
YZ		 7175 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7176 return;
c7c9c56c 7177
6308630b 7178 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7179
b053b2ae 7180 if (irqchip_split(vcpu->kvm))
6308630b 7181 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7182 else {
fa59cc00 7183 if (vcpu->arch.apicv_active)
d62caabb 7184 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7185 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7186 }
e40ff1d6
LA		 7187
7188 if (is_guest_mode(vcpu))
7189 vcpu->arch.load_eoi_exitmap_pending = true;
7190 else
7191 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7192}
7193
7194static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7195{
7196 u64 eoi_exit_bitmap[4];
7197
7198 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7199 return;
7200
5c919412
AS		 7201 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7202 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7203 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7204}
7205
b1394e74
RK		 7206void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7207 unsigned long start, unsigned long end)
7208{
7209 unsigned long apic_address;
7210
7211 /*
7212 * The physical address of apic access page is stored in the VMCS.
7213 * Update it when it becomes invalid.
7214 */
7215 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7216 if (start <= apic_address && apic_address < end)
7217 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7218}
7219
4256f43f
TC		 7220void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7221{
c24ae0dc
TC		 7222 struct page *page = NULL;
7223
35754c98 7224 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7225 return;
7226
4256f43f
TC		 7227 if (!kvm_x86_ops->set_apic_access_page_addr)
7228 return;
7229
c24ae0dc 7230 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7231 if (is_error_page(page))
7232 return;
c24ae0dc
TC		 7233 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7234
7235 /*
7236 * Do not pin apic access page in memory, the MMU notifier
7237 * will call us again if it is migrated or swapped out.
7238 */
7239 put_page(page);
4256f43f
TC		 7240}
7241EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7242
9357d939 7243/*
362c698f 7244 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7245 * exiting to the userspace. Otherwise, the value will be returned to the
7246 * userspace.
7247 */
851ba692 7248static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7249{
7250 int r;
62a193ed
MG		 7251 bool req_int_win =
7252 dm_request_for_irq_injection(vcpu) &&
7253 kvm_cpu_accept_dm_intr(vcpu);
7254
730dca42 7255 bool req_immediate_exit = false;
b6c7a5dc 7256
2fa6e1e1 7257 if (kvm_request_pending(vcpu)) {
a8eeb04a 7258 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7259 kvm_mmu_unload(vcpu);
a8eeb04a 7260 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7261 __kvm_migrate_timers(vcpu);
d828199e
MT		 7262 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7263 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7264 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7265 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7266 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7267 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7268 if (unlikely(r))
7269 goto out;
7270 }
a8eeb04a 7271 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7272 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7273 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7274 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7275 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7276 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7277 r = 0;
7278 goto out;
7279 }
a8eeb04a 7280 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7281 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7282 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7283 r = 0;
7284 goto out;
7285 }
af585b92
GN		 7286 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7287 /* Page is swapped out. Do synthetic halt */
7288 vcpu->arch.apf.halted = true;
7289 r = 1;
7290 goto out;
7291 }
c9aaa895
GC		 7292 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7293 record_steal_time(vcpu);
64d60670
PB		 7294 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7295 process_smi(vcpu);
7460fb4a
AK		 7296 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7297 process_nmi(vcpu);
f5132b01 7298 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7299 kvm_pmu_handle_event(vcpu);
f5132b01 7300 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7301 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7302 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7303 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7304 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7305 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7306 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7307 vcpu->run->eoi.vector =
7308 vcpu->arch.pending_ioapic_eoi;
7309 r = 0;
7310 goto out;
7311 }
7312 }
3d81bc7e
YZ		 7313 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7314 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7315 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7316 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7317 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7318 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7319 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7320 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7321 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7322 r = 0;
7323 goto out;
7324 }
e516cebb
AS		 7325 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7326 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7327 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7328 r = 0;
7329 goto out;
7330 }
db397571
AS		 7331 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7332 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7333 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7334 r = 0;
7335 goto out;
7336 }
f3b138c5
AS		 7337
7338 /*
7339 * KVM_REQ_HV_STIMER has to be processed after
7340 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7341 * depend on the guest clock being up-to-date
7342 */
1f4b34f8
AS		 7343 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7344 kvm_hv_process_stimers(vcpu);
2f52d58c 7345 }
b93463aa 7346
b463a6f7 7347 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7348 ++vcpu->stat.req_event;
66450a21
JK		 7349 kvm_apic_accept_events(vcpu);
7350 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7351 r = 1;
7352 goto out;
7353 }
7354
b6b8a145
JK		 7355 if (inject_pending_event(vcpu, req_int_win) != 0)
7356 req_immediate_exit = true;
321c5658 7357 else {
cc3d967f 7358 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7359 *
cc3d967f
LP		 7360 * SMIs have three cases:
7361 * 1) They can be nested, and then there is nothing to
7362 * do here because RSM will cause a vmexit anyway.
7363 * 2) There is an ISA-specific reason why SMI cannot be
7364 * injected, and the moment when this changes can be
7365 * intercepted.
7366 * 3) Or the SMI can be pending because
7367 * inject_pending_event has completed the injection
7368 * of an IRQ or NMI from the previous vmexit, and
7369 * then we request an immediate exit to inject the
7370 * SMI.
c43203ca
PB		 7371 */
7372 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7373 if (!kvm_x86_ops->enable_smi_window(vcpu))
7374 req_immediate_exit = true;
321c5658
YS		 7375 if (vcpu->arch.nmi_pending)
7376 kvm_x86_ops->enable_nmi_window(vcpu);
7377 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7378 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7379 WARN_ON(vcpu->arch.exception.pending);
321c5658 7380 }
b463a6f7
AK		 7381
7382 if (kvm_lapic_enabled(vcpu)) {
7383 update_cr8_intercept(vcpu);
7384 kvm_lapic_sync_to_vapic(vcpu);
7385 }
7386 }
7387
d8368af8
AK		 7388 r = kvm_mmu_reload(vcpu);
7389 if (unlikely(r)) {
d905c069 7390 goto cancel_injection;
d8368af8
AK		 7391 }
7392
b6c7a5dc
HB		 7393 preempt_disable();
7394
7395 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7396
7397 /*
7398 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7399 * IPI are then delayed after guest entry, which ensures that they
7400 * result in virtual interrupt delivery.
7401 */
7402 local_irq_disable();
6b7e2d09
XG		 7403 vcpu->mode = IN_GUEST_MODE;
7404
01b71917
MT		 7405 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7406
0f127d12 7407 /*
b95234c8 7408 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7409 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7410 *
7411 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7412 * pairs with the memory barrier implicit in pi_test_and_set_on
7413 * (see vmx_deliver_posted_interrupt).
7414 *
7415 * 3) This also orders the write to mode from any reads to the page
7416 * tables done while the VCPU is running. Please see the comment
7417 * in kvm_flush_remote_tlbs.
6b7e2d09 7418 */
01b71917 7419 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7420
b95234c8
PB		 7421 /*
7422 * This handles the case where a posted interrupt was
7423 * notified with kvm_vcpu_kick.
7424 */
fa59cc00
LA		 7425 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7426 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7427
2fa6e1e1 7428 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7429 || need_resched() || signal_pending(current)) {
6b7e2d09 7430 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7431 smp_wmb();
6c142801
AK		 7432 local_irq_enable();
7433 preempt_enable();
01b71917 7434 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7435 r = 1;
d905c069 7436 goto cancel_injection;
6c142801
AK		 7437 }
7438
fc5b7f3b
DM		 7439 kvm_load_guest_xcr0(vcpu);
7440
c43203ca
PB		 7441 if (req_immediate_exit) {
7442 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7443 smp_send_reschedule(vcpu->cpu);
c43203ca 7444 }
d6185f20 7445
8b89fe1f 7446 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7447 if (lapic_timer_advance_ns)
7448 wait_lapic_expire(vcpu);
6edaa530 7449 guest_enter_irqoff();
b6c7a5dc 7450
42dbaa5a 7451 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7452 set_debugreg(0, 7);
7453 set_debugreg(vcpu->arch.eff_db[0], 0);
7454 set_debugreg(vcpu->arch.eff_db[1], 1);
7455 set_debugreg(vcpu->arch.eff_db[2], 2);
7456 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7457 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7458 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7459 }
b6c7a5dc 7460
851ba692 7461 kvm_x86_ops->run(vcpu);
b6c7a5dc 7462
c77fb5fe
PB		 7463 /*
7464 * Do this here before restoring debug registers on the host. And
7465 * since we do this before handling the vmexit, a DR access vmexit
7466 * can (a) read the correct value of the debug registers, (b) set
7467 * KVM_DEBUGREG_WONT_EXIT again.
7468 */
7469 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7470 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7471 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7472 kvm_update_dr0123(vcpu);
7473 kvm_update_dr6(vcpu);
7474 kvm_update_dr7(vcpu);
7475 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7476 }
7477
24f1e32c
FW		 7478 /*
7479 * If the guest has used debug registers, at least dr7
7480 * will be disabled while returning to the host.
7481 * If we don't have active breakpoints in the host, we don't
7482 * care about the messed up debug address registers. But if
7483 * we have some of them active, restore the old state.
7484 */
59d8eb53 7485 if (hw_breakpoint_active())
24f1e32c 7486 hw_breakpoint_restore();
42dbaa5a 7487
4ba76538 7488 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7489
6b7e2d09 7490 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7491 smp_wmb();
a547c6db 7492
fc5b7f3b
DM		 7493 kvm_put_guest_xcr0(vcpu);
7494
dd60d217 7495 kvm_before_interrupt(vcpu);
a547c6db 7496 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7497 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7498
7499 ++vcpu->stat.exits;
7500
f2485b3e 7501 guest_exit_irqoff();
b6c7a5dc 7502
f2485b3e 7503 local_irq_enable();
b6c7a5dc
HB		 7504 preempt_enable();
7505
f656ce01 7506 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7507
b6c7a5dc
HB		 7508 /*
7509 * Profile KVM exit RIPs:
7510 */
7511 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7512 unsigned long rip = kvm_rip_read(vcpu);
7513 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7514 }
7515
cc578287
ZA		 7516 if (unlikely(vcpu->arch.tsc_always_catchup))
7517 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7518
5cfb1d5a
MT		 7519 if (vcpu->arch.apic_attention)
7520 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7521
618232e2 7522 vcpu->arch.gpa_available = false;
851ba692 7523 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7524 return r;
7525
7526cancel_injection:
7527 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7528 if (unlikely(vcpu->arch.apic_attention))
7529 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7530out:
7531 return r;
7532}
b6c7a5dc 7533
362c698f
PB		 7534static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7535{
bf9f6ac8
FW		 7536 if (!kvm_arch_vcpu_runnable(vcpu) &&
7537 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7538 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7539 kvm_vcpu_block(vcpu);
7540 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7541
7542 if (kvm_x86_ops->post_block)
7543 kvm_x86_ops->post_block(vcpu);
7544
9c8fd1ba
PB		 7545 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7546 return 1;
7547 }
362c698f
PB		 7548
7549 kvm_apic_accept_events(vcpu);
7550 switch(vcpu->arch.mp_state) {
7551 case KVM_MP_STATE_HALTED:
7552 vcpu->arch.pv.pv_unhalted = false;
7553 vcpu->arch.mp_state =
7554 KVM_MP_STATE_RUNNABLE;
7555 case KVM_MP_STATE_RUNNABLE:
7556 vcpu->arch.apf.halted = false;
7557 break;
7558 case KVM_MP_STATE_INIT_RECEIVED:
7559 break;
7560 default:
7561 return -EINTR;
7562 break;
7563 }
7564 return 1;
7565}
09cec754 7566
5d9bc648
PB		 7567static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7568{
0ad3bed6
PB		 7569 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7570 kvm_x86_ops->check_nested_events(vcpu, false);
7571
5d9bc648
PB		 7572 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7573 !vcpu->arch.apf.halted);
7574}
7575
362c698f 7576static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7577{
7578 int r;
f656ce01 7579 struct kvm *kvm = vcpu->kvm;
d7690175 7580
f656ce01 7581 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7582
362c698f 7583 for (;;) {
58f800d5 7584 if (kvm_vcpu_running(vcpu)) {
851ba692 7585 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7586 } else {
362c698f 7587 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7588 }
7589
09cec754
GN		 7590 if (r <= 0)
7591 break;
7592
72875d8a 7593 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7594 if (kvm_cpu_has_pending_timer(vcpu))
7595 kvm_inject_pending_timer_irqs(vcpu);
7596
782d422b
MG		 7597 if (dm_request_for_irq_injection(vcpu) &&
7598 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7599 r = 0;
7600 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7601 ++vcpu->stat.request_irq_exits;
362c698f 7602 break;
09cec754 7603 }
af585b92
GN		 7604
7605 kvm_check_async_pf_completion(vcpu);
7606
09cec754
GN		 7607 if (signal_pending(current)) {
7608 r = -EINTR;
851ba692 7609 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7610 ++vcpu->stat.signal_exits;
362c698f 7611 break;
09cec754
GN		 7612 }
7613 if (need_resched()) {
f656ce01 7614 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7615 cond_resched();
f656ce01 7616 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7617 }
b6c7a5dc
HB		 7618 }
7619
f656ce01 7620 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7621
7622 return r;
7623}
7624
716d51ab
GN		 7625static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7626{
7627 int r;
7628 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7629 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7630 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7631 if (r != EMULATE_DONE)
7632 return 0;
7633 return 1;
7634}
7635
7636static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7637{
7638 BUG_ON(!vcpu->arch.pio.count);
7639
7640 return complete_emulated_io(vcpu);
7641}
7642
f78146b0
AK		 7643/*
7644 * Implements the following, as a state machine:
7645 *
7646 * read:
7647 * for each fragment
87da7e66
XG		 7648 * for each mmio piece in the fragment
7649 * write gpa, len
7650 * exit
7651 * copy data
f78146b0
AK		 7652 * execute insn
7653 *
7654 * write:
7655 * for each fragment
87da7e66
XG		 7656 * for each mmio piece in the fragment
7657 * write gpa, len
7658 * copy data
7659 * exit
f78146b0 7660 */
716d51ab 7661static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7662{
7663 struct kvm_run *run = vcpu->run;
f78146b0 7664 struct kvm_mmio_fragment *frag;
87da7e66 7665 unsigned len;
5287f194 7666
716d51ab 7667 BUG_ON(!vcpu->mmio_needed);
5287f194 7668
716d51ab 7669 /* Complete previous fragment */
87da7e66
XG		 7670 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7671 len = min(8u, frag->len);
716d51ab 7672 if (!vcpu->mmio_is_write)
87da7e66
XG		 7673 memcpy(frag->data, run->mmio.data, len);
7674
7675 if (frag->len <= 8) {
7676 /* Switch to the next fragment. */
7677 frag++;
7678 vcpu->mmio_cur_fragment++;
7679 } else {
7680 /* Go forward to the next mmio piece. */
7681 frag->data += len;
7682 frag->gpa += len;
7683 frag->len -= len;
7684 }
7685
a08d3b3b 7686 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7687 vcpu->mmio_needed = 0;
0912c977
PB		 7688
7689 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7690 if (vcpu->mmio_is_write)
716d51ab
GN		 7691 return 1;
7692 vcpu->mmio_read_completed = 1;
7693 return complete_emulated_io(vcpu);
7694 }
87da7e66 7695
716d51ab
GN		 7696 run->exit_reason = KVM_EXIT_MMIO;
7697 run->mmio.phys_addr = frag->gpa;
7698 if (vcpu->mmio_is_write)
87da7e66
XG		 7699 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7700 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7701 run->mmio.is_write = vcpu->mmio_is_write;
7702 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7703 return 0;
5287f194
AK		 7704}
7705
b6c7a5dc
HB		 7706int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7707{
7708 int r;
b6c7a5dc 7709
accb757d 7710 vcpu_load(vcpu);
20b7035c 7711 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7712 kvm_load_guest_fpu(vcpu);
7713
a4535290 7714 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7715 if (kvm_run->immediate_exit) {
7716 r = -EINTR;
7717 goto out;
7718 }
b6c7a5dc 7719 kvm_vcpu_block(vcpu);
66450a21 7720 kvm_apic_accept_events(vcpu);
72875d8a 7721 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7722 r = -EAGAIN;
a0595000
JS		 7723 if (signal_pending(current)) {
7724 r = -EINTR;
7725 vcpu->run->exit_reason = KVM_EXIT_INTR;
7726 ++vcpu->stat.signal_exits;
7727 }
ac9f6dc0 7728 goto out;
b6c7a5dc
HB		 7729 }
7730
01643c51
KH		 7731 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7732 r = -EINVAL;
7733 goto out;
7734 }
7735
7736 if (vcpu->run->kvm_dirty_regs) {
7737 r = sync_regs(vcpu);
7738 if (r != 0)
7739 goto out;
7740 }
7741
b6c7a5dc 7742 /* re-sync apic's tpr */
35754c98 7743 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7744 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7745 r = -EINVAL;
7746 goto out;
7747 }
7748 }
b6c7a5dc 7749
716d51ab
GN		 7750 if (unlikely(vcpu->arch.complete_userspace_io)) {
7751 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7752 vcpu->arch.complete_userspace_io = NULL;
7753 r = cui(vcpu);
7754 if (r <= 0)
5663d8f9 7755 goto out;
716d51ab
GN		 7756 } else
7757 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7758
460df4c1
PB		 7759 if (kvm_run->immediate_exit)
7760 r = -EINTR;
7761 else
7762 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7763
7764out:
5663d8f9 7765 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7766 if (vcpu->run->kvm_valid_regs)
7767 store_regs(vcpu);
f1d86e46 7768 post_kvm_run_save(vcpu);
20b7035c 7769 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7770
accb757d 7771 vcpu_put(vcpu);
b6c7a5dc
HB		 7772 return r;
7773}
7774
01643c51 7775static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7776{
7ae441ea
GN		 7777 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7778 /*
7779 * We are here if userspace calls get_regs() in the middle of
7780 * instruction emulation. Registers state needs to be copied
4a969980 7781 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7782 * that usually, but some bad designed PV devices (vmware
7783 * backdoor interface) need this to work
7784 */
dd856efa 7785 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7786 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7787 }
5fdbf976
MT		 7788 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7789 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7790 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7791 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7792 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7793 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7794 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7795 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7796#ifdef CONFIG_X86_64
5fdbf976
MT		 7797 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7798 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7799 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7800 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7801 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7802 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7803 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7804 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7805#endif
7806
5fdbf976 7807 regs->rip = kvm_rip_read(vcpu);
91586a3b 7808 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7809}
b6c7a5dc 7810
01643c51
KH		 7811int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7812{
7813 vcpu_load(vcpu);
7814 __get_regs(vcpu, regs);
1fc9b76b 7815 vcpu_put(vcpu);
b6c7a5dc
HB		 7816 return 0;
7817}
7818
01643c51 7819static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7820{
7ae441ea
GN		 7821 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7822 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7823
5fdbf976
MT		 7824 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7825 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7826 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7827 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7828 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7829 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7830 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7831 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7832#ifdef CONFIG_X86_64
5fdbf976
MT		 7833 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7834 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7835 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7836 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7837 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7838 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7839 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7840 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7841#endif
7842
5fdbf976 7843 kvm_rip_write(vcpu, regs->rip);
d73235d1 7844 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7845
b4f14abd
JK		 7846 vcpu->arch.exception.pending = false;
7847
3842d135 7848 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7849}
3842d135 7850
01643c51
KH		 7851int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7852{
7853 vcpu_load(vcpu);
7854 __set_regs(vcpu, regs);
875656fe 7855 vcpu_put(vcpu);
b6c7a5dc
HB		 7856 return 0;
7857}
7858
b6c7a5dc
HB		 7859void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7860{
7861 struct kvm_segment cs;
7862
3e6e0aab 7863 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7864 *db = cs.db;
7865 *l = cs.l;
7866}
7867EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7868
01643c51 7869static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7870{
89a27f4d 7871 struct desc_ptr dt;
b6c7a5dc 7872
3e6e0aab
GT		 7873 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7874 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7875 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7876 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7877 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7878 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7879
3e6e0aab
GT		 7880 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7881 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7882
7883 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7884 sregs->idt.limit = dt.size;
7885 sregs->idt.base = dt.address;
b6c7a5dc 7886 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7887 sregs->gdt.limit = dt.size;
7888 sregs->gdt.base = dt.address;
b6c7a5dc 7889
4d4ec087 7890 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7891 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7892 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7893 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7894 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7895 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7896 sregs->apic_base = kvm_get_apic_base(vcpu);
7897
923c61bb 7898 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7899
04140b41 7900 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7901 set_bit(vcpu->arch.interrupt.nr,
7902 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7903}
16d7a191 7904
01643c51
KH		 7905int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7906 struct kvm_sregs *sregs)
7907{
7908 vcpu_load(vcpu);
7909 __get_sregs(vcpu, sregs);
bcdec41c 7910 vcpu_put(vcpu);
b6c7a5dc
HB		 7911 return 0;
7912}
7913
62d9f0db
MT		 7914int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7915 struct kvm_mp_state *mp_state)
7916{
fd232561
CD		 7917 vcpu_load(vcpu);
7918
66450a21 7919 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7920 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7921 vcpu->arch.pv.pv_unhalted)
7922 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7923 else
7924 mp_state->mp_state = vcpu->arch.mp_state;
7925
fd232561 7926 vcpu_put(vcpu);
62d9f0db
MT		 7927 return 0;
7928}
7929
7930int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7931 struct kvm_mp_state *mp_state)
7932{
e83dff5e
CD		 7933 int ret = -EINVAL;
7934
7935 vcpu_load(vcpu);
7936
bce87cce 7937 if (!lapic_in_kernel(vcpu) &&
66450a21 7938 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7939 goto out;
66450a21 7940
28bf2888
DH		 7941 /* INITs are latched while in SMM */
7942 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7943 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7944 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7945 goto out;
28bf2888 7946
66450a21
JK		 7947 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7948 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7949 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7950 } else
7951 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7952 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7953
7954 ret = 0;
7955out:
7956 vcpu_put(vcpu);
7957 return ret;
62d9f0db
MT		 7958}
7959
7f3d35fd
KW		 7960int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7961 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7962{
9d74191a 7963 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7964 int ret;
e01c2426 7965
8ec4722d 7966 init_emulate_ctxt(vcpu);
c697518a 7967
7f3d35fd 7968 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7969 has_error_code, error_code);
c697518a 7970
c697518a 7971 if (ret)
19d04437 7972 return EMULATE_FAIL;
37817f29 7973
9d74191a
TY		 7974 kvm_rip_write(vcpu, ctxt->eip);
7975 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7976 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7977 return EMULATE_DONE;
37817f29
IE		 7978}
7979EXPORT_SYMBOL_GPL(kvm_task_switch);
7980
3140c156 7981static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 7982{
37b95951 7983 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7984 /*
7985 * When EFER.LME and CR0.PG are set, the processor is in
7986 * 64-bit mode (though maybe in a 32-bit code segment).
7987 * CR4.PAE and EFER.LMA must be set.
7988 */
37b95951 7989 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7990 || !(sregs->efer & EFER_LMA))
7991 return -EINVAL;
7992 } else {
7993 /*
7994 * Not in 64-bit mode: EFER.LMA is clear and the code
7995 * segment cannot be 64-bit.
7996 */
7997 if (sregs->efer & EFER_LMA || sregs->cs.l)
7998 return -EINVAL;
7999 }
8000
8001 return 0;
8002}
8003
01643c51 8004static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8005{
58cb628d 8006 struct msr_data apic_base_msr;
b6c7a5dc 8007 int mmu_reset_needed = 0;
c4d21882 8008 int cpuid_update_needed = 0;
63f42e02 8009 int pending_vec, max_bits, idx;
89a27f4d 8010 struct desc_ptr dt;
b4ef9d4e
CD		 8011 int ret = -EINVAL;
8012
d6321d49
RK		 8013 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8014 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 8015 goto out;
6d1068b3 8016
f2981033 8017 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8018 goto out;
f2981033 8019
d3802286
JM		 8020 apic_base_msr.data = sregs->apic_base;
8021 apic_base_msr.host_initiated = true;
8022 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8023 goto out;
6d1068b3 8024
89a27f4d
GN		 8025 dt.size = sregs->idt.limit;
8026 dt.address = sregs->idt.base;
b6c7a5dc 8027 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8028 dt.size = sregs->gdt.limit;
8029 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8030 kvm_x86_ops->set_gdt(vcpu, &dt);
8031
ad312c7c 8032 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8033 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8034 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8035 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8036
2d3ad1f4 8037 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8038
f6801dff 8039 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8040 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8041
4d4ec087 8042 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8043 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8044 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8045
fc78f519 8046 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8047 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8048 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8049 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8050 if (cpuid_update_needed)
00b27a3e 8051 kvm_update_cpuid(vcpu);
63f42e02
XG		 8052
8053 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 8054 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 8055 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8056 mmu_reset_needed = 1;
8057 }
63f42e02 8058 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8059
8060 if (mmu_reset_needed)
8061 kvm_mmu_reset_context(vcpu);
8062
a50abc3b 8063 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8064 pending_vec = find_first_bit(
8065 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8066 if (pending_vec < max_bits) {
66fd3f7f 8067 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8068 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8069 }
8070
3e6e0aab
GT		 8071 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8072 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8073 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8074 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8075 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8076 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8077
3e6e0aab
GT		 8078 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8079 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8080
5f0269f5
ME		 8081 update_cr8_intercept(vcpu);
8082
9c3e4aab 8083 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8084 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8085 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8086 !is_protmode(vcpu))
9c3e4aab
MT		 8087 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8088
3842d135
AK		 8089 kvm_make_request(KVM_REQ_EVENT, vcpu);
8090
b4ef9d4e
CD		 8091 ret = 0;
8092out:
01643c51
KH		 8093 return ret;
8094}
8095
8096int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8097 struct kvm_sregs *sregs)
8098{
8099 int ret;
8100
8101 vcpu_load(vcpu);
8102 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8103 vcpu_put(vcpu);
8104 return ret;
b6c7a5dc
HB		 8105}
8106
d0bfb940
JK		 8107int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8108 struct kvm_guest_debug *dbg)
b6c7a5dc 8109{
355be0b9 8110 unsigned long rflags;
ae675ef0 8111 int i, r;
b6c7a5dc 8112
66b56562
CD		 8113 vcpu_load(vcpu);
8114
4f926bf2
JK		 8115 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8116 r = -EBUSY;
8117 if (vcpu->arch.exception.pending)
2122ff5e 8118 goto out;
4f926bf2
JK		 8119 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8120 kvm_queue_exception(vcpu, DB_VECTOR);
8121 else
8122 kvm_queue_exception(vcpu, BP_VECTOR);
8123 }
8124
91586a3b
JK		 8125 /*
8126 * Read rflags as long as potentially injected trace flags are still
8127 * filtered out.
8128 */
8129 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8130
8131 vcpu->guest_debug = dbg->control;
8132 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8133 vcpu->guest_debug = 0;
8134
8135 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8136 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8137 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8138 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8139 } else {
8140 for (i = 0; i < KVM_NR_DB_REGS; i++)
8141 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8142 }
c8639010 8143 kvm_update_dr7(vcpu);
ae675ef0 8144
f92653ee
JK		 8145 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8146 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8147 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8148
91586a3b
JK		 8149 /*
8150 * Trigger an rflags update that will inject or remove the trace
8151 * flags.
8152 */
8153 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8154
a96036b8 8155 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8156
4f926bf2 8157 r = 0;
d0bfb940 8158
2122ff5e 8159out:
66b56562 8160 vcpu_put(vcpu);
b6c7a5dc
HB		 8161 return r;
8162}
8163
8b006791
ZX		 8164/*
8165 * Translate a guest virtual address to a guest physical address.
8166 */
8167int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8168 struct kvm_translation *tr)
8169{
8170 unsigned long vaddr = tr->linear_address;
8171 gpa_t gpa;
f656ce01 8172 int idx;
8b006791 8173
1da5b61d
CD		 8174 vcpu_load(vcpu);
8175
f656ce01 8176 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8177 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8178 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8179 tr->physical_address = gpa;
8180 tr->valid = gpa != UNMAPPED_GVA;
8181 tr->writeable = 1;
8182 tr->usermode = 0;
8b006791 8183
1da5b61d 8184 vcpu_put(vcpu);
8b006791
ZX		 8185 return 0;
8186}
8187
d0752060
HB		 8188int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8189{
1393123e 8190 struct fxregs_state *fxsave;
d0752060 8191
1393123e 8192 vcpu_load(vcpu);
d0752060 8193
1393123e 8194 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8195 memcpy(fpu->fpr, fxsave->st_space, 128);
8196 fpu->fcw = fxsave->cwd;
8197 fpu->fsw = fxsave->swd;
8198 fpu->ftwx = fxsave->twd;
8199 fpu->last_opcode = fxsave->fop;
8200 fpu->last_ip = fxsave->rip;
8201 fpu->last_dp = fxsave->rdp;
8202 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8203
1393123e 8204 vcpu_put(vcpu);
d0752060
HB		 8205 return 0;
8206}
8207
8208int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8209{
6a96bc7f
CD		 8210 struct fxregs_state *fxsave;
8211
8212 vcpu_load(vcpu);
8213
8214 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8215
d0752060
HB		 8216 memcpy(fxsave->st_space, fpu->fpr, 128);
8217 fxsave->cwd = fpu->fcw;
8218 fxsave->swd = fpu->fsw;
8219 fxsave->twd = fpu->ftwx;
8220 fxsave->fop = fpu->last_opcode;
8221 fxsave->rip = fpu->last_ip;
8222 fxsave->rdp = fpu->last_dp;
8223 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8224
6a96bc7f 8225 vcpu_put(vcpu);
d0752060
HB		 8226 return 0;
8227}
8228
01643c51
KH		 8229static void store_regs(struct kvm_vcpu *vcpu)
8230{
8231 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8232
8233 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8234 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8235
8236 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8237 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8238
8239 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8240 kvm_vcpu_ioctl_x86_get_vcpu_events(
8241 vcpu, &vcpu->run->s.regs.events);
8242}
8243
8244static int sync_regs(struct kvm_vcpu *vcpu)
8245{
8246 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8247 return -EINVAL;
8248
8249 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8250 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8251 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8252 }
8253 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8254 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8255 return -EINVAL;
8256 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8257 }
8258 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8259 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8260 vcpu, &vcpu->run->s.regs.events))
8261 return -EINVAL;
8262 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8263 }
8264
8265 return 0;
8266}
8267
0ee6a517 8268static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8269{
bf935b0b 8270 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8271 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8272 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8273 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8274
2acf923e
DC		 8275 /*
8276 * Ensure guest xcr0 is valid for loading
8277 */
d91cab78 8278 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8279
ad312c7c 8280 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8281}
d0752060 8282
f775b13e 8283/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8284void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8285{
f775b13e
RR		 8286 preempt_disable();
8287 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8288 /* PKRU is separately restored in kvm_x86_ops->run. */
8289 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8290 ~XFEATURE_MASK_PKRU);
f775b13e 8291 preempt_enable();
0c04851c 8292 trace_kvm_fpu(1);
d0752060 8293}
d0752060 8294
f775b13e 8295/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8296void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8297{
f775b13e 8298 preempt_disable();
4f836347 8299 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8300 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8301 preempt_enable();
f096ed85 8302 ++vcpu->stat.fpu_reload;
0c04851c 8303 trace_kvm_fpu(0);
d0752060 8304}
e9b11c17
ZX		 8305
8306void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8307{
bd768e14
IY		 8308 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8309
12f9a48f 8310 kvmclock_reset(vcpu);
7f1ea208 8311
e9b11c17 8312 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8313 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8314}
8315
8316struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8317 unsigned int id)
8318{
c447e76b
LL		 8319 struct kvm_vcpu *vcpu;
8320
b0c39dc6 8321 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8322 printk_once(KERN_WARNING
8323 "kvm: SMP vm created on host with unstable TSC; "
8324 "guest TSC will not be reliable\n");
c447e76b
LL		 8325
8326 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8327
c447e76b 8328 return vcpu;
26e5215f 8329}
e9b11c17 8330
26e5215f
AK		 8331int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8332{
19efffa2 8333 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8334 vcpu_load(vcpu);
d28bc9dd 8335 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8336 kvm_mmu_setup(vcpu);
e9b11c17 8337 vcpu_put(vcpu);
ec7660cc 8338 return 0;
e9b11c17
ZX		 8339}
8340
31928aa5 8341void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8342{
8fe8ab46 8343 struct msr_data msr;
332967a3 8344 struct kvm *kvm = vcpu->kvm;
42897d86 8345
d3457c87
RK		 8346 kvm_hv_vcpu_postcreate(vcpu);
8347
ec7660cc 8348 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8349 return;
ec7660cc 8350 vcpu_load(vcpu);
8fe8ab46
WA		 8351 msr.data = 0x0;
8352 msr.index = MSR_IA32_TSC;
8353 msr.host_initiated = true;
8354 kvm_write_tsc(vcpu, &msr);
42897d86 8355 vcpu_put(vcpu);
ec7660cc 8356 mutex_unlock(&vcpu->mutex);
42897d86 8357
630994b3
MT		 8358 if (!kvmclock_periodic_sync)
8359 return;
8360
332967a3
AJ		 8361 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8362 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8363}
8364
d40ccc62 8365void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8366{
344d9588
GN		 8367 vcpu->arch.apf.msr_val = 0;
8368
ec7660cc 8369 vcpu_load(vcpu);
e9b11c17
ZX		 8370 kvm_mmu_unload(vcpu);
8371 vcpu_put(vcpu);
8372
8373 kvm_x86_ops->vcpu_free(vcpu);
8374}
8375
d28bc9dd 8376void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8377{
b7e31be3
RK		 8378 kvm_lapic_reset(vcpu, init_event);
8379
e69fab5d
PB		 8380 vcpu->arch.hflags = 0;
8381
c43203ca 8382 vcpu->arch.smi_pending = 0;
52797bf9 8383 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8384 atomic_set(&vcpu->arch.nmi_queued, 0);
8385 vcpu->arch.nmi_pending = 0;
448fa4a9 8386 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8387 kvm_clear_interrupt_queue(vcpu);
8388 kvm_clear_exception_queue(vcpu);
664f8e26 8389 vcpu->arch.exception.pending = false;
448fa4a9 8390
42dbaa5a 8391 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8392 kvm_update_dr0123(vcpu);
6f43ed01 8393 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8394 kvm_update_dr6(vcpu);
42dbaa5a 8395 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8396 kvm_update_dr7(vcpu);
42dbaa5a 8397
1119022c
NA		 8398 vcpu->arch.cr2 = 0;
8399
3842d135 8400 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8401 vcpu->arch.apf.msr_val = 0;
c9aaa895 8402 vcpu->arch.st.msr_val = 0;
3842d135 8403
12f9a48f
GC		 8404 kvmclock_reset(vcpu);
8405
af585b92
GN		 8406 kvm_clear_async_pf_completion_queue(vcpu);
8407 kvm_async_pf_hash_reset(vcpu);
8408 vcpu->arch.apf.halted = false;
3842d135 8409
a554d207
WL		 8410 if (kvm_mpx_supported()) {
8411 void *mpx_state_buffer;
8412
8413 /*
8414 * To avoid have the INIT path from kvm_apic_has_events() that be
8415 * called with loaded FPU and does not let userspace fix the state.
8416 */
f775b13e
RR		 8417 if (init_event)
8418 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8419 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8420 XFEATURE_MASK_BNDREGS);
8421 if (mpx_state_buffer)
8422 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8423 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8424 XFEATURE_MASK_BNDCSR);
8425 if (mpx_state_buffer)
8426 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8427 if (init_event)
8428 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8429 }
8430
64d60670 8431 if (!init_event) {
d28bc9dd 8432 kvm_pmu_reset(vcpu);
64d60670 8433 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8434
8435 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8436 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8437
8438 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8439 }
f5132b01 8440
66f7b72e
JS		 8441 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8442 vcpu->arch.regs_avail = ~0;
8443 vcpu->arch.regs_dirty = ~0;
8444
a554d207
WL		 8445 vcpu->arch.ia32_xss = 0;
8446
d28bc9dd 8447 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8448}
8449
2b4a273b 8450void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8451{
8452 struct kvm_segment cs;
8453
8454 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8455 cs.selector = vector << 8;
8456 cs.base = vector << 12;
8457 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8458 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8459}
8460
13a34e06 8461int kvm_arch_hardware_enable(void)
e9b11c17 8462{
ca84d1a2
ZA		 8463 struct kvm *kvm;
8464 struct kvm_vcpu *vcpu;
8465 int i;
0dd6a6ed
ZA		 8466 int ret;
8467 u64 local_tsc;
8468 u64 max_tsc = 0;
8469 bool stable, backwards_tsc = false;
18863bdd
AK		 8470
8471 kvm_shared_msr_cpu_online();
13a34e06 8472 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8473 if (ret != 0)
8474 return ret;
8475
4ea1636b 8476 local_tsc = rdtsc();
b0c39dc6 8477 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8478 list_for_each_entry(kvm, &vm_list, vm_list) {
8479 kvm_for_each_vcpu(i, vcpu, kvm) {
8480 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8481 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8482 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8483 backwards_tsc = true;
8484 if (vcpu->arch.last_host_tsc > max_tsc)
8485 max_tsc = vcpu->arch.last_host_tsc;
8486 }
8487 }
8488 }
8489
8490 /*
8491 * Sometimes, even reliable TSCs go backwards. This happens on
8492 * platforms that reset TSC during suspend or hibernate actions, but
8493 * maintain synchronization. We must compensate. Fortunately, we can
8494 * detect that condition here, which happens early in CPU bringup,
8495 * before any KVM threads can be running. Unfortunately, we can't
8496 * bring the TSCs fully up to date with real time, as we aren't yet far
8497 * enough into CPU bringup that we know how much real time has actually
108b249c 8498 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8499 * variables that haven't been updated yet.
8500 *
8501 * So we simply find the maximum observed TSC above, then record the
8502 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8503 * the adjustment will be applied. Note that we accumulate
8504 * adjustments, in case multiple suspend cycles happen before some VCPU
8505 * gets a chance to run again. In the event that no KVM threads get a
8506 * chance to run, we will miss the entire elapsed period, as we'll have
8507 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8508 * loose cycle time. This isn't too big a deal, since the loss will be
8509 * uniform across all VCPUs (not to mention the scenario is extremely
8510 * unlikely). It is possible that a second hibernate recovery happens
8511 * much faster than a first, causing the observed TSC here to be
8512 * smaller; this would require additional padding adjustment, which is
8513 * why we set last_host_tsc to the local tsc observed here.
8514 *
8515 * N.B. - this code below runs only on platforms with reliable TSC,
8516 * as that is the only way backwards_tsc is set above. Also note
8517 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8518 * have the same delta_cyc adjustment applied if backwards_tsc
8519 * is detected. Note further, this adjustment is only done once,
8520 * as we reset last_host_tsc on all VCPUs to stop this from being
8521 * called multiple times (one for each physical CPU bringup).
8522 *
4a969980 8523 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8524 * will be compensated by the logic in vcpu_load, which sets the TSC to
8525 * catchup mode. This will catchup all VCPUs to real time, but cannot
8526 * guarantee that they stay in perfect synchronization.
8527 */
8528 if (backwards_tsc) {
8529 u64 delta_cyc = max_tsc - local_tsc;
8530 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8531 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8532 kvm_for_each_vcpu(i, vcpu, kvm) {
8533 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8534 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8535 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8536 }
8537
8538 /*
8539 * We have to disable TSC offset matching.. if you were
8540 * booting a VM while issuing an S4 host suspend....
8541 * you may have some problem. Solving this issue is
8542 * left as an exercise to the reader.
8543 */
8544 kvm->arch.last_tsc_nsec = 0;
8545 kvm->arch.last_tsc_write = 0;
8546 }
8547
8548 }
8549 return 0;
e9b11c17
ZX		 8550}
8551
13a34e06 8552void kvm_arch_hardware_disable(void)
e9b11c17 8553{
13a34e06
RK		 8554 kvm_x86_ops->hardware_disable();
8555 drop_user_return_notifiers();
e9b11c17
ZX		 8556}
8557
8558int kvm_arch_hardware_setup(void)
8559{
9e9c3fe4
NA		 8560 int r;
8561
8562 r = kvm_x86_ops->hardware_setup();
8563 if (r != 0)
8564 return r;
8565
35181e86
HZ		 8566 if (kvm_has_tsc_control) {
8567 /*
8568 * Make sure the user can only configure tsc_khz values that
8569 * fit into a signed integer.
273ba457 8570 * A min value is not calculated because it will always
35181e86
HZ		 8571 * be 1 on all machines.
8572 */
8573 u64 max = min(0x7fffffffULL,
8574 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8575 kvm_max_guest_tsc_khz = max;
8576
ad721883 8577 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8578 }
ad721883 8579
9e9c3fe4
NA		 8580 kvm_init_msr_list();
8581 return 0;
e9b11c17
ZX		 8582}
8583
8584void kvm_arch_hardware_unsetup(void)
8585{
8586 kvm_x86_ops->hardware_unsetup();
8587}
8588
8589void kvm_arch_check_processor_compat(void *rtn)
8590{
8591 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8592}
8593
8594bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8595{
8596 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8597}
8598EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8599
8600bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8601{
8602 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8603}
8604
54e9818f 8605struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8606EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8607
e9b11c17
ZX		 8608int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8609{
8610 struct page *page;
e9b11c17
ZX		 8611 int r;
8612
b2a05fef 8613 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8614 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8615 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8616 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8617 else
a4535290 8618 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8619
8620 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8621 if (!page) {
8622 r = -ENOMEM;
8623 goto fail;
8624 }
ad312c7c 8625 vcpu->arch.pio_data = page_address(page);
e9b11c17 8626
cc578287 8627 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8628
e9b11c17
ZX		 8629 r = kvm_mmu_create(vcpu);
8630 if (r < 0)
8631 goto fail_free_pio_data;
8632
26de7988 8633 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8634 r = kvm_create_lapic(vcpu);
8635 if (r < 0)
8636 goto fail_mmu_destroy;
54e9818f
GN		 8637 } else
8638 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8639
890ca9ae
HY		 8640 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8641 GFP_KERNEL);
8642 if (!vcpu->arch.mce_banks) {
8643 r = -ENOMEM;
443c39bc 8644 goto fail_free_lapic;
890ca9ae
HY		 8645 }
8646 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8647
f1797359
WY		 8648 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8649 r = -ENOMEM;
f5f48ee1 8650 goto fail_free_mce_banks;
f1797359 8651 }
f5f48ee1 8652
0ee6a517 8653 fx_init(vcpu);
66f7b72e 8654
4344ee98 8655 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8656
5a4f55cd
EK		 8657 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8658
74545705
RK		 8659 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8660
af585b92 8661 kvm_async_pf_hash_reset(vcpu);
f5132b01 8662 kvm_pmu_init(vcpu);
af585b92 8663
1c1a9ce9 8664 vcpu->arch.pending_external_vector = -1;
de63ad4c 8665 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8666
5c919412
AS		 8667 kvm_hv_vcpu_init(vcpu);
8668
e9b11c17 8669 return 0;
0ee6a517 8670
f5f48ee1
SY		 8671fail_free_mce_banks:
8672 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8673fail_free_lapic:
8674 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8675fail_mmu_destroy:
8676 kvm_mmu_destroy(vcpu);
8677fail_free_pio_data:
ad312c7c 8678 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8679fail:
8680 return r;
8681}
8682
8683void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8684{
f656ce01
MT		 8685 int idx;
8686
1f4b34f8 8687 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8688 kvm_pmu_destroy(vcpu);
36cb93fd 8689 kfree(vcpu->arch.mce_banks);
e9b11c17 8690 kvm_free_lapic(vcpu);
f656ce01 8691 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8692 kvm_mmu_destroy(vcpu);
f656ce01 8693 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8694 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8695 if (!lapic_in_kernel(vcpu))
54e9818f 8696 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8697}
d19a9cd2 8698
e790d9ef
RK		 8699void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8700{
ae97a3b8 8701 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8702}
8703
e08b9637 8704int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8705{
e08b9637
CO		 8706 if (type)
8707 return -EINVAL;
8708
6ef768fa 8709 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8710 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8711 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8712 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8713 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8714
5550af4d
SY		 8715 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8716 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8717 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8718 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8719 &kvm->arch.irq_sources_bitmap);
5550af4d 8720
038f8c11 8721 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8722 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8723 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8724
108b249c 8725 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8726 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8727
7e44e449 8728 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8729 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8730
cbc0236a 8731 kvm_hv_init_vm(kvm);
0eb05bf2 8732 kvm_page_track_init(kvm);
13d268ca 8733 kvm_mmu_init_vm(kvm);
0eb05bf2 8734
03543133
SS		 8735 if (kvm_x86_ops->vm_init)
8736 return kvm_x86_ops->vm_init(kvm);
8737
d89f5eff 8738 return 0;
d19a9cd2
ZX		 8739}
8740
8741static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8742{
ec7660cc 8743 vcpu_load(vcpu);
d19a9cd2
ZX		 8744 kvm_mmu_unload(vcpu);
8745 vcpu_put(vcpu);
8746}
8747
8748static void kvm_free_vcpus(struct kvm *kvm)
8749{
8750 unsigned int i;
988a2cae 8751 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8752
8753 /*
8754 * Unpin any mmu pages first.
8755 */
af585b92
GN		 8756 kvm_for_each_vcpu(i, vcpu, kvm) {
8757 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8758 kvm_unload_vcpu_mmu(vcpu);
af585b92 8759 }
988a2cae
GN		 8760 kvm_for_each_vcpu(i, vcpu, kvm)
8761 kvm_arch_vcpu_free(vcpu);
8762
8763 mutex_lock(&kvm->lock);
8764 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8765 kvm->vcpus[i] = NULL;
d19a9cd2 8766
988a2cae
GN		 8767 atomic_set(&kvm->online_vcpus, 0);
8768 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8769}
8770
ad8ba2cd
SY		 8771void kvm_arch_sync_events(struct kvm *kvm)
8772{
332967a3 8773 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8774 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8775 kvm_free_pit(kvm);
ad8ba2cd
SY		 8776}
8777
1d8007bd 8778int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8779{
8780 int i, r;
25188b99 8781 unsigned long hva;
f0d648bd
PB		 8782 struct kvm_memslots *slots = kvm_memslots(kvm);
8783 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8784
8785 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8786 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8787 return -EINVAL;
9da0e4d5 8788
f0d648bd
PB		 8789 slot = id_to_memslot(slots, id);
8790 if (size) {
b21629da 8791 if (slot->npages)
f0d648bd
PB		 8792 return -EEXIST;
8793
8794 /*
8795 * MAP_SHARED to prevent internal slot pages from being moved
8796 * by fork()/COW.
8797 */
8798 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8799 MAP_SHARED | MAP_ANONYMOUS, 0);
8800 if (IS_ERR((void *)hva))
8801 return PTR_ERR((void *)hva);
8802 } else {
8803 if (!slot->npages)
8804 return 0;
8805
8806 hva = 0;
8807 }
8808
8809 old = *slot;
9da0e4d5 8810 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8811 struct kvm_userspace_memory_region m;
9da0e4d5 8812
1d8007bd
PB		 8813 m.slot = id | (i << 16);
8814 m.flags = 0;
8815 m.guest_phys_addr = gpa;
f0d648bd 8816 m.userspace_addr = hva;
1d8007bd 8817 m.memory_size = size;
9da0e4d5
PB		 8818 r = __kvm_set_memory_region(kvm, &m);
8819 if (r < 0)
8820 return r;
8821 }
8822
103c763c
EB		 8823 if (!size)
8824 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8825
9da0e4d5
PB		 8826 return 0;
8827}
8828EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8829
1d8007bd 8830int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8831{
8832 int r;
8833
8834 mutex_lock(&kvm->slots_lock);
1d8007bd 8835 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8836 mutex_unlock(&kvm->slots_lock);
8837
8838 return r;
8839}
8840EXPORT_SYMBOL_GPL(x86_set_memory_region);
8841
d19a9cd2
ZX		 8842void kvm_arch_destroy_vm(struct kvm *kvm)
8843{
27469d29
AH		 8844 if (current->mm == kvm->mm) {
8845 /*
8846 * Free memory regions allocated on behalf of userspace,
8847 * unless the the memory map has changed due to process exit
8848 * or fd copying.
8849 */
1d8007bd
PB		 8850 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8851 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8852 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8853 }
03543133
SS		 8854 if (kvm_x86_ops->vm_destroy)
8855 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8856 kvm_pic_destroy(kvm);
8857 kvm_ioapic_destroy(kvm);
d19a9cd2 8858 kvm_free_vcpus(kvm);
af1bae54 8859 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8860 kvm_mmu_uninit_vm(kvm);
2beb6dad 8861 kvm_page_track_cleanup(kvm);
cbc0236a 8862 kvm_hv_destroy_vm(kvm);
d19a9cd2 8863}
0de10343 8864
5587027c 8865void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8866 struct kvm_memory_slot *dont)
8867{
8868 int i;
8869
d89cc617
TY		 8870 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8871 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8872 kvfree(free->arch.rmap[i]);
d89cc617 8873 free->arch.rmap[i] = NULL;
77d11309 8874 }
d89cc617
TY		 8875 if (i == 0)
8876 continue;
8877
8878 if (!dont || free->arch.lpage_info[i - 1] !=
8879 dont->arch.lpage_info[i - 1]) {
548ef284 8880 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8881 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8882 }
8883 }
21ebbeda
XG		 8884
8885 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8886}
8887
5587027c
AK		 8888int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8889 unsigned long npages)
db3fe4eb
TY		 8890{
8891 int i;
8892
d89cc617 8893 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8894 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8895 unsigned long ugfn;
8896 int lpages;
d89cc617 8897 int level = i + 1;
db3fe4eb
TY		 8898
8899 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8900 slot->base_gfn, level) + 1;
8901
d89cc617 8902 slot->arch.rmap[i] =
778e1cdd
KC		 8903 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
8904 GFP_KERNEL);
d89cc617 8905 if (!slot->arch.rmap[i])
77d11309 8906 goto out_free;
d89cc617
TY		 8907 if (i == 0)
8908 continue;
77d11309 8909
778e1cdd 8910 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
92f94f1e 8911 if (!linfo)
db3fe4eb
TY		 8912 goto out_free;
8913
92f94f1e
XG		 8914 slot->arch.lpage_info[i - 1] = linfo;
8915
db3fe4eb 8916 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8917 linfo[0].disallow_lpage = 1;
db3fe4eb 8918 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8919 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8920 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8921 /*
8922 * If the gfn and userspace address are not aligned wrt each
8923 * other, or if explicitly asked to, disable large page
8924 * support for this slot
8925 */
8926 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8927 !kvm_largepages_enabled()) {
8928 unsigned long j;
8929
8930 for (j = 0; j < lpages; ++j)
92f94f1e 8931 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8932 }
8933 }
8934
21ebbeda
XG		 8935 if (kvm_page_track_create_memslot(slot, npages))
8936 goto out_free;
8937
db3fe4eb
TY		 8938 return 0;
8939
8940out_free:
d89cc617 8941 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8942 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8943 slot->arch.rmap[i] = NULL;
8944 if (i == 0)
8945 continue;
8946
548ef284 8947 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8948 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8949 }
8950 return -ENOMEM;
8951}
8952
15f46015 8953void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8954{
e6dff7d1
TY		 8955 /*
8956 * memslots->generation has been incremented.
8957 * mmio generation may have reached its maximum value.
8958 */
54bf36aa 8959 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8960}
8961
f7784b8e
MT		 8962int kvm_arch_prepare_memory_region(struct kvm *kvm,
8963 struct kvm_memory_slot *memslot,
09170a49 8964 const struct kvm_userspace_memory_region *mem,
7b6195a9 8965 enum kvm_mr_change change)
0de10343 8966{
f7784b8e
MT		 8967 return 0;
8968}
8969
88178fd4
KH		 8970static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8971 struct kvm_memory_slot *new)
8972{
8973 /* Still write protect RO slot */
8974 if (new->flags & KVM_MEM_READONLY) {
8975 kvm_mmu_slot_remove_write_access(kvm, new);
8976 return;
8977 }
8978
8979 /*
8980 * Call kvm_x86_ops dirty logging hooks when they are valid.
8981 *
8982 * kvm_x86_ops->slot_disable_log_dirty is called when:
8983 *
8984 * - KVM_MR_CREATE with dirty logging is disabled
8985 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8986 *
8987 * The reason is, in case of PML, we need to set D-bit for any slots
8988 * with dirty logging disabled in order to eliminate unnecessary GPA
8989 * logging in PML buffer (and potential PML buffer full VMEXT). This
8990 * guarantees leaving PML enabled during guest's lifetime won't have
8991 * any additonal overhead from PML when guest is running with dirty
8992 * logging disabled for memory slots.
8993 *
8994 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8995 * to dirty logging mode.
8996 *
8997 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8998 *
8999 * In case of write protect:
9000 *
9001 * Write protect all pages for dirty logging.
9002 *
9003 * All the sptes including the large sptes which point to this
9004 * slot are set to readonly. We can not create any new large
9005 * spte on this slot until the end of the logging.
9006 *
9007 * See the comments in fast_page_fault().
9008 */
9009 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9010 if (kvm_x86_ops->slot_enable_log_dirty)
9011 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9012 else
9013 kvm_mmu_slot_remove_write_access(kvm, new);
9014 } else {
9015 if (kvm_x86_ops->slot_disable_log_dirty)
9016 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9017 }
9018}
9019
f7784b8e 9020void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9021 const struct kvm_userspace_memory_region *mem,
8482644a 9022 const struct kvm_memory_slot *old,
f36f3f28 9023 const struct kvm_memory_slot *new,
8482644a 9024 enum kvm_mr_change change)
f7784b8e 9025{
8482644a 9026 int nr_mmu_pages = 0;
f7784b8e 9027
48c0e4e9
XG		 9028 if (!kvm->arch.n_requested_mmu_pages)
9029 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9030
48c0e4e9 9031 if (nr_mmu_pages)
0de10343 9032 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9033
3ea3b7fa
WL		 9034 /*
9035 * Dirty logging tracks sptes in 4k granularity, meaning that large
9036 * sptes have to be split. If live migration is successful, the guest
9037 * in the source machine will be destroyed and large sptes will be
9038 * created in the destination. However, if the guest continues to run
9039 * in the source machine (for example if live migration fails), small
9040 * sptes will remain around and cause bad performance.
9041 *
9042 * Scan sptes if dirty logging has been stopped, dropping those
9043 * which can be collapsed into a single large-page spte. Later
9044 * page faults will create the large-page sptes.
9045 */
9046 if ((change != KVM_MR_DELETE) &&
9047 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9048 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9049 kvm_mmu_zap_collapsible_sptes(kvm, new);
9050
c972f3b1 9051 /*
88178fd4 9052 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9053 *
88178fd4
KH		 9054 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9055 * been zapped so no dirty logging staff is needed for old slot. For
9056 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9057 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9058 *
9059 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9060 */
88178fd4 9061 if (change != KVM_MR_DELETE)
f36f3f28 9062 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9063}
1d737c8a 9064
2df72e9b 9065void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9066{
6ca18b69 9067 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9068}
9069
2df72e9b
MT		 9070void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9071 struct kvm_memory_slot *slot)
9072{
ae7cd873 9073 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9074}
9075
5d9bc648
PB		 9076static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9077{
9078 if (!list_empty_careful(&vcpu->async_pf.done))
9079 return true;
9080
9081 if (kvm_apic_has_events(vcpu))
9082 return true;
9083
9084 if (vcpu->arch.pv.pv_unhalted)
9085 return true;
9086
a5f01f8e
WL		 9087 if (vcpu->arch.exception.pending)
9088 return true;
9089
47a66eed
Z		 9090 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9091 (vcpu->arch.nmi_pending &&
9092 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9093 return true;
9094
47a66eed
Z		 9095 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9096 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9097 return true;
9098
5d9bc648
PB		 9099 if (kvm_arch_interrupt_allowed(vcpu) &&
9100 kvm_cpu_has_interrupt(vcpu))
9101 return true;
9102
1f4b34f8
AS		 9103 if (kvm_hv_has_stimer_pending(vcpu))
9104 return true;
9105
5d9bc648
PB		 9106 return false;
9107}
9108
1d737c8a
ZX		 9109int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9110{
5d9bc648 9111 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9112}
5736199a 9113
199b5763
LM		 9114bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9115{
de63ad4c 9116 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9117}
9118
b6d33834 9119int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9120{
b6d33834 9121 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9122}
78646121
GN		 9123
9124int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9125{
9126 return kvm_x86_ops->interrupt_allowed(vcpu);
9127}
229456fc 9128
82b32774 9129unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9130{
82b32774
NA		 9131 if (is_64_bit_mode(vcpu))
9132 return kvm_rip_read(vcpu);
9133 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9134 kvm_rip_read(vcpu));
9135}
9136EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9137
82b32774
NA		 9138bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9139{
9140 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9141}
9142EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9143
94fe45da
JK		 9144unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9145{
9146 unsigned long rflags;
9147
9148 rflags = kvm_x86_ops->get_rflags(vcpu);
9149 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9150 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9151 return rflags;
9152}
9153EXPORT_SYMBOL_GPL(kvm_get_rflags);
9154
6addfc42 9155static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9156{
9157 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9158 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9159 rflags |= X86_EFLAGS_TF;
94fe45da 9160 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9161}
9162
9163void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9164{
9165 __kvm_set_rflags(vcpu, rflags);
3842d135 9166 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9167}
9168EXPORT_SYMBOL_GPL(kvm_set_rflags);
9169
56028d08
GN		 9170void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9171{
9172 int r;
9173
fb67e14f 9174 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9175 work->wakeup_all)
56028d08
GN		 9176 return;
9177
9178 r = kvm_mmu_reload(vcpu);
9179 if (unlikely(r))
9180 return;
9181
fb67e14f
XG		 9182 if (!vcpu->arch.mmu.direct_map &&
9183 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9184 return;
9185
56028d08
GN		 9186 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9187}
9188
af585b92
GN		 9189static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9190{
9191 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9192}
9193
9194static inline u32 kvm_async_pf_next_probe(u32 key)
9195{
9196 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9197}
9198
9199static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9200{
9201 u32 key = kvm_async_pf_hash_fn(gfn);
9202
9203 while (vcpu->arch.apf.gfns[key] != ~0)
9204 key = kvm_async_pf_next_probe(key);
9205
9206 vcpu->arch.apf.gfns[key] = gfn;
9207}
9208
9209static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9210{
9211 int i;
9212 u32 key = kvm_async_pf_hash_fn(gfn);
9213
9214 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9215 (vcpu->arch.apf.gfns[key] != gfn &&
9216 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9217 key = kvm_async_pf_next_probe(key);
9218
9219 return key;
9220}
9221
9222bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9223{
9224 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9225}
9226
9227static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9228{
9229 u32 i, j, k;
9230
9231 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9232 while (true) {
9233 vcpu->arch.apf.gfns[i] = ~0;
9234 do {
9235 j = kvm_async_pf_next_probe(j);
9236 if (vcpu->arch.apf.gfns[j] == ~0)
9237 return;
9238 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9239 /*
9240 * k lies cyclically in ]i,j]
9241 * | i.k.j |
9242 * |....j i.k.| or |.k..j i...|
9243 */
9244 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9245 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9246 i = j;
9247 }
9248}
9249
7c90705b
GN		 9250static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9251{
4e335d9e
PB		 9252
9253 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9254 sizeof(val));
7c90705b
GN		 9255}
9256
9a6e7c39
WL		 9257static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9258{
9259
9260 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9261 sizeof(u32));
9262}
9263
af585b92
GN		 9264void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9265 struct kvm_async_pf *work)
9266{
6389ee94
AK		 9267 struct x86_exception fault;
9268
7c90705b 9269 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9270 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9271
9272 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9273 (vcpu->arch.apf.send_user_only &&
9274 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9275 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9276 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9277 fault.vector = PF_VECTOR;
9278 fault.error_code_valid = true;
9279 fault.error_code = 0;
9280 fault.nested_page_fault = false;
9281 fault.address = work->arch.token;
adfe20fb 9282 fault.async_page_fault = true;
6389ee94 9283 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9284 }
af585b92
GN		 9285}
9286
9287void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9288 struct kvm_async_pf *work)
9289{
6389ee94 9290 struct x86_exception fault;
9a6e7c39 9291 u32 val;
6389ee94 9292
f2e10669 9293 if (work->wakeup_all)
7c90705b
GN		 9294 work->arch.token = ~0; /* broadcast wakeup */
9295 else
9296 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9297 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9298
9a6e7c39
WL		 9299 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9300 !apf_get_user(vcpu, &val)) {
9301 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9302 vcpu->arch.exception.pending &&
9303 vcpu->arch.exception.nr == PF_VECTOR &&
9304 !apf_put_user(vcpu, 0)) {
9305 vcpu->arch.exception.injected = false;
9306 vcpu->arch.exception.pending = false;
9307 vcpu->arch.exception.nr = 0;
9308 vcpu->arch.exception.has_error_code = false;
9309 vcpu->arch.exception.error_code = 0;
9310 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9311 fault.vector = PF_VECTOR;
9312 fault.error_code_valid = true;
9313 fault.error_code = 0;
9314 fault.nested_page_fault = false;
9315 fault.address = work->arch.token;
9316 fault.async_page_fault = true;
9317 kvm_inject_page_fault(vcpu, &fault);
9318 }
7c90705b 9319 }
e6d53e3b 9320 vcpu->arch.apf.halted = false;
a4fa1635 9321 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9322}
9323
9324bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9325{
9326 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9327 return true;
9328 else
9bc1f09f 9329 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9330}
9331
5544eb9b
PB		 9332void kvm_arch_start_assignment(struct kvm *kvm)
9333{
9334 atomic_inc(&kvm->arch.assigned_device_count);
9335}
9336EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9337
9338void kvm_arch_end_assignment(struct kvm *kvm)
9339{
9340 atomic_dec(&kvm->arch.assigned_device_count);
9341}
9342EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9343
9344bool kvm_arch_has_assigned_device(struct kvm *kvm)
9345{
9346 return atomic_read(&kvm->arch.assigned_device_count);
9347}
9348EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9349
e0f0bbc5
AW		 9350void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9351{
9352 atomic_inc(&kvm->arch.noncoherent_dma_count);
9353}
9354EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9355
9356void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9357{
9358 atomic_dec(&kvm->arch.noncoherent_dma_count);
9359}
9360EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9361
9362bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9363{
9364 return atomic_read(&kvm->arch.noncoherent_dma_count);
9365}
9366EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9367
14717e20
AW		 9368bool kvm_arch_has_irq_bypass(void)
9369{
9370 return kvm_x86_ops->update_pi_irte != NULL;
9371}
9372
87276880
FW		 9373int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9374 struct irq_bypass_producer *prod)
9375{
9376 struct kvm_kernel_irqfd *irqfd =
9377 container_of(cons, struct kvm_kernel_irqfd, consumer);
9378
14717e20 9379 irqfd->producer = prod;
87276880 9380
14717e20
AW		 9381 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9382 prod->irq, irqfd->gsi, 1);
87276880
FW		 9383}
9384
9385void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9386 struct irq_bypass_producer *prod)
9387{
9388 int ret;
9389 struct kvm_kernel_irqfd *irqfd =
9390 container_of(cons, struct kvm_kernel_irqfd, consumer);
9391
87276880
FW		 9392 WARN_ON(irqfd->producer != prod);
9393 irqfd->producer = NULL;
9394
9395 /*
9396 * When producer of consumer is unregistered, we change back to
9397 * remapped mode, so we can re-use the current implementation
bb3541f1 9398 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9399 * int this case doesn't want to receive the interrupts.
9400 */
9401 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9402 if (ret)
9403 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9404 " fails: %d\n", irqfd->consumer.token, ret);
9405}
9406
9407int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9408 uint32_t guest_irq, bool set)
9409{
9410 if (!kvm_x86_ops->update_pi_irte)
9411 return -EINVAL;
9412
9413 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9414}
9415
52004014
FW		 9416bool kvm_vector_hashing_enabled(void)
9417{
9418 return vector_hashing;
9419}
9420EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9421
229456fc 9422EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9423EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9424EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9425EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9426EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9427EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9428EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9429EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9430EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9431EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9432EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9433EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9434EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9435EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9436EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9437EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9438EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9439EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9440EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)