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kvm: vmx: add cpu into VMX preemption timer bug list
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
3b8a5df6 139unsigned int __read_mostly lapic_timer_advance_ns = 1000;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
c595ceee 198 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 199 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
200 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
201 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
202 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
203 { "mmu_flooded", VM_STAT(mmu_flooded) },
204 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 205 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 206 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 207 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 208 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 209 { "max_mmu_page_hash_collisions",
210 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 211 { NULL }
212};
213
2acf923e
DC		 214u64 __read_mostly host_xcr0;
215
b6785def 216static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 217
af585b92
GN		 218static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
219{
220 int i;
221 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
222 vcpu->arch.apf.gfns[i] = ~0;
223}
224
18863bdd
AK		 225static void kvm_on_user_return(struct user_return_notifier *urn)
226{
227 unsigned slot;
18863bdd
AK		 228 struct kvm_shared_msrs *locals
229 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 230 struct kvm_shared_msr_values *values;
1650b4eb
IA		 231 unsigned long flags;
232
233 /*
234 * Disabling irqs at this point since the following code could be
235 * interrupted and executed through kvm_arch_hardware_disable()
236 */
237 local_irq_save(flags);
238 if (locals->registered) {
239 locals->registered = false;
240 user_return_notifier_unregister(urn);
241 }
242 local_irq_restore(flags);
18863bdd 243 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 244 values = &locals->values[slot];
245 if (values->host != values->curr) {
246 wrmsrl(shared_msrs_global.msrs[slot], values->host);
247 values->curr = values->host;
18863bdd
AK		 248 }
249 }
18863bdd
AK		 250}
251
2bf78fa7 252static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 253{
18863bdd 254 u64 value;
013f6a5d
MT		 255 unsigned int cpu = smp_processor_id();
256 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 257
2bf78fa7
SY		 258 /* only read, and nobody should modify it at this time,
259 * so don't need lock */
260 if (slot >= shared_msrs_global.nr) {
261 printk(KERN_ERR "kvm: invalid MSR slot!");
262 return;
263 }
264 rdmsrl_safe(msr, &value);
265 smsr->values[slot].host = value;
266 smsr->values[slot].curr = value;
267}
268
269void kvm_define_shared_msr(unsigned slot, u32 msr)
270{
0123be42 271 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 272 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 273 if (slot >= shared_msrs_global.nr)
274 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 275}
276EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
277
278static void kvm_shared_msr_cpu_online(void)
279{
280 unsigned i;
18863bdd
AK		 281
282 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 283 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 284}
285
8b3c3104 286int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 287{
013f6a5d
MT		 288 unsigned int cpu = smp_processor_id();
289 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 290 int err;
18863bdd 291
2bf78fa7 292 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 293 return 0;
2bf78fa7 294 smsr->values[slot].curr = value;
8b3c3104
AH		 295 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
296 if (err)
297 return 1;
298
18863bdd
AK		 299 if (!smsr->registered) {
300 smsr->urn.on_user_return = kvm_on_user_return;
301 user_return_notifier_register(&smsr->urn);
302 smsr->registered = true;
303 }
8b3c3104 304 return 0;
18863bdd
AK		 305}
306EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
307
13a34e06 308static void drop_user_return_notifiers(void)
3548bab5 309{
013f6a5d
MT		 310 unsigned int cpu = smp_processor_id();
311 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 312
313 if (smsr->registered)
314 kvm_on_user_return(&smsr->urn);
315}
316
6866b83e
CO		 317u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
318{
8a5a87d9 319 return vcpu->arch.apic_base;
6866b83e
CO		 320}
321EXPORT_SYMBOL_GPL(kvm_get_apic_base);
322
58871649
JM		 323enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
324{
325 return kvm_apic_mode(kvm_get_apic_base(vcpu));
326}
327EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
328
58cb628d
JK		 329int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
330{
58871649
JM		 331 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
332 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 333 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
334 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 335
58871649 336 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 337 return 1;
58871649
JM		 338 if (!msr_info->host_initiated) {
339 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
340 return 1;
341 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
342 return 1;
343 }
58cb628d
JK		 344
345 kvm_lapic_set_base(vcpu, msr_info->data);
346 return 0;
6866b83e
CO		 347}
348EXPORT_SYMBOL_GPL(kvm_set_apic_base);
349
2605fc21 350asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 351{
352 /* Fault while not rebooting. We want the trace. */
353 BUG();
354}
355EXPORT_SYMBOL_GPL(kvm_spurious_fault);
356
3fd28fce
ED		 357#define EXCPT_BENIGN 0
358#define EXCPT_CONTRIBUTORY 1
359#define EXCPT_PF 2
360
361static int exception_class(int vector)
362{
363 switch (vector) {
364 case PF_VECTOR:
365 return EXCPT_PF;
366 case DE_VECTOR:
367 case TS_VECTOR:
368 case NP_VECTOR:
369 case SS_VECTOR:
370 case GP_VECTOR:
371 return EXCPT_CONTRIBUTORY;
372 default:
373 break;
374 }
375 return EXCPT_BENIGN;
376}
377
d6e8c854
NA		 378#define EXCPT_FAULT 0
379#define EXCPT_TRAP 1
380#define EXCPT_ABORT 2
381#define EXCPT_INTERRUPT 3
382
383static int exception_type(int vector)
384{
385 unsigned int mask;
386
387 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
388 return EXCPT_INTERRUPT;
389
390 mask = 1 << vector;
391
392 /* #DB is trap, as instruction watchpoints are handled elsewhere */
393 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
394 return EXCPT_TRAP;
395
396 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
397 return EXCPT_ABORT;
398
399 /* Reserved exceptions will result in fault */
400 return EXCPT_FAULT;
401}
402
da998b46
JM		 403void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
404{
405 unsigned nr = vcpu->arch.exception.nr;
406 bool has_payload = vcpu->arch.exception.has_payload;
407 unsigned long payload = vcpu->arch.exception.payload;
408
409 if (!has_payload)
410 return;
411
412 switch (nr) {
f10c729f
JM		 413 case DB_VECTOR:
414 /*
415 * "Certain debug exceptions may clear bit 0-3. The
416 * remaining contents of the DR6 register are never
417 * cleared by the processor".
418 */
419 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
420 /*
421 * DR6.RTM is set by all #DB exceptions that don't clear it.
422 */
423 vcpu->arch.dr6 |= DR6_RTM;
424 vcpu->arch.dr6 |= payload;
425 /*
426 * Bit 16 should be set in the payload whenever the #DB
427 * exception should clear DR6.RTM. This makes the payload
428 * compatible with the pending debug exceptions under VMX.
429 * Though not currently documented in the SDM, this also
430 * makes the payload compatible with the exit qualification
431 * for #DB exceptions under VMX.
432 */
433 vcpu->arch.dr6 ^= payload & DR6_RTM;
434 break;
da998b46
JM		 435 case PF_VECTOR:
436 vcpu->arch.cr2 = payload;
437 break;
438 }
439
440 vcpu->arch.exception.has_payload = false;
441 vcpu->arch.exception.payload = 0;
442}
443EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
444
3fd28fce 445static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 446 unsigned nr, bool has_error, u32 error_code,
91e86d22 447 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 448{
449 u32 prev_nr;
450 int class1, class2;
451
3842d135
AK		 452 kvm_make_request(KVM_REQ_EVENT, vcpu);
453
664f8e26 454 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 455 queue:
3ffb2468
NA		 456 if (has_error && !is_protmode(vcpu))
457 has_error = false;
664f8e26
WL		 458 if (reinject) {
459 /*
460 * On vmentry, vcpu->arch.exception.pending is only
461 * true if an event injection was blocked by
462 * nested_run_pending. In that case, however,
463 * vcpu_enter_guest requests an immediate exit,
464 * and the guest shouldn't proceed far enough to
465 * need reinjection.
466 */
467 WARN_ON_ONCE(vcpu->arch.exception.pending);
468 vcpu->arch.exception.injected = true;
91e86d22
JM		 469 if (WARN_ON_ONCE(has_payload)) {
470 /*
471 * A reinjected event has already
472 * delivered its payload.
473 */
474 has_payload = false;
475 payload = 0;
476 }
664f8e26
WL		 477 } else {
478 vcpu->arch.exception.pending = true;
479 vcpu->arch.exception.injected = false;
480 }
3fd28fce
ED		 481 vcpu->arch.exception.has_error_code = has_error;
482 vcpu->arch.exception.nr = nr;
483 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 484 vcpu->arch.exception.has_payload = has_payload;
485 vcpu->arch.exception.payload = payload;
da998b46
JM		 486 /*
487 * In guest mode, payload delivery should be deferred,
488 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 489 * CR2 is modified (or intercept #DB before DR6 is
490 * modified under nVMX). However, for ABI
491 * compatibility with KVM_GET_VCPU_EVENTS and
492 * KVM_SET_VCPU_EVENTS, we can't delay payload
493 * delivery unless userspace has enabled this
494 * functionality via the per-VM capability,
495 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 496 */
497 if (!vcpu->kvm->arch.exception_payload_enabled ||
498 !is_guest_mode(vcpu))
499 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 500 return;
501 }
502
503 /* to check exception */
504 prev_nr = vcpu->arch.exception.nr;
505 if (prev_nr == DF_VECTOR) {
506 /* triple fault -> shutdown */
a8eeb04a 507 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 508 return;
509 }
510 class1 = exception_class(prev_nr);
511 class2 = exception_class(nr);
512 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
513 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 514 /*
515 * Generate double fault per SDM Table 5-5. Set
516 * exception.pending = true so that the double fault
517 * can trigger a nested vmexit.
518 */
3fd28fce 519 vcpu->arch.exception.pending = true;
664f8e26 520 vcpu->arch.exception.injected = false;
3fd28fce
ED		 521 vcpu->arch.exception.has_error_code = true;
522 vcpu->arch.exception.nr = DF_VECTOR;
523 vcpu->arch.exception.error_code = 0;
c851436a
JM		 524 vcpu->arch.exception.has_payload = false;
525 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 526 } else
527 /* replace previous exception with a new one in a hope
528 that instruction re-execution will regenerate lost
529 exception */
530 goto queue;
531}
532
298101da
AK		 533void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
534{
91e86d22 535 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 536}
537EXPORT_SYMBOL_GPL(kvm_queue_exception);
538
ce7ddec4
JR		 539void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
540{
91e86d22 541 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 542}
543EXPORT_SYMBOL_GPL(kvm_requeue_exception);
544
f10c729f
JM		 545static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
546 unsigned long payload)
547{
548 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
549}
550
da998b46
JM		 551static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
552 u32 error_code, unsigned long payload)
553{
554 kvm_multiple_exception(vcpu, nr, true, error_code,
555 true, payload, false);
556}
557
6affcbed 558int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 559{
db8fcefa
AP		 560 if (err)
561 kvm_inject_gp(vcpu, 0);
562 else
6affcbed
KH		 563 return kvm_skip_emulated_instruction(vcpu);
564
565 return 1;
db8fcefa
AP		 566}
567EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 568
6389ee94 569void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 570{
571 ++vcpu->stat.pf_guest;
adfe20fb
WL		 572 vcpu->arch.exception.nested_apf =
573 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 574 if (vcpu->arch.exception.nested_apf) {
adfe20fb 575 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 576 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
577 } else {
578 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
579 fault->address);
580 }
c3c91fee 581}
27d6c865 582EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 583
ef54bcfe 584static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 585{
6389ee94
AK		 586 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
587 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 588 else
44dd3ffa 589 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 590
591 return fault->nested_page_fault;
d4f8cf66
JR		 592}
593
3419ffc8
SY		 594void kvm_inject_nmi(struct kvm_vcpu *vcpu)
595{
7460fb4a
AK		 596 atomic_inc(&vcpu->arch.nmi_queued);
597 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 598}
599EXPORT_SYMBOL_GPL(kvm_inject_nmi);
600
298101da
AK		 601void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
602{
91e86d22 603 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 604}
605EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
606
ce7ddec4
JR		 607void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
608{
91e86d22 609 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 610}
611EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
612
0a79b009
AK		 613/*
614 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
615 * a #GP and return false.
616 */
617bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 618{
0a79b009
AK		 619 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
620 return true;
621 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
622 return false;
298101da 623}
0a79b009 624EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 625
16f8a6f9
NA		 626bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
627{
628 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
629 return true;
630
631 kvm_queue_exception(vcpu, UD_VECTOR);
632 return false;
633}
634EXPORT_SYMBOL_GPL(kvm_require_dr);
635
ec92fe44
JR		 636/*
637 * This function will be used to read from the physical memory of the currently
54bf36aa 638 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 639 * can read from guest physical or from the guest's guest physical memory.
640 */
641int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
642 gfn_t ngfn, void *data, int offset, int len,
643 u32 access)
644{
54987b7a 645 struct x86_exception exception;
ec92fe44
JR		 646 gfn_t real_gfn;
647 gpa_t ngpa;
648
649 ngpa = gfn_to_gpa(ngfn);
54987b7a 650 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 651 if (real_gfn == UNMAPPED_GVA)
652 return -EFAULT;
653
654 real_gfn = gpa_to_gfn(real_gfn);
655
54bf36aa 656 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 657}
658EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
659
69b0049a 660static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 661 void *data, int offset, int len, u32 access)
662{
663 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
664 data, offset, len, access);
665}
666
a03490ed
CO		 667/*
668 * Load the pae pdptrs. Return true is they are all valid.
669 */
ff03a073 670int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 671{
672 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
673 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
674 int i;
675 int ret;
ff03a073 676 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 677
ff03a073
JR		 678 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
679 offset * sizeof(u64), sizeof(pdpte),
680 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 681 if (ret < 0) {
682 ret = 0;
683 goto out;
684 }
685 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 686 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 687 (pdpte[i] &
44dd3ffa 688 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 689 ret = 0;
690 goto out;
691 }
692 }
693 ret = 1;
694
ff03a073 695 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 696 __set_bit(VCPU_EXREG_PDPTR,
697 (unsigned long *)&vcpu->arch.regs_avail);
698 __set_bit(VCPU_EXREG_PDPTR,
699 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 700out:
a03490ed
CO		 701
702 return ret;
703}
cc4b6871 704EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 705
9ed38ffa 706bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 707{
ff03a073 708 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 709 bool changed = true;
3d06b8bf
JR		 710 int offset;
711 gfn_t gfn;
d835dfec
AK		 712 int r;
713
d35b34a9 714 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
d835dfec
AK		 715 return false;
716
6de4f3ad
AK		 717 if (!test_bit(VCPU_EXREG_PDPTR,
718 (unsigned long *)&vcpu->arch.regs_avail))
719 return true;
720
a512177e
PB		 721 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
722 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 723 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
724 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 725 if (r < 0)
726 goto out;
ff03a073 727 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 728out:
d835dfec
AK		 729
730 return changed;
731}
9ed38ffa 732EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 733
49a9b07e 734int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 735{
aad82703 736 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 737 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 738
f9a48e6a
AK		 739 cr0 |= X86_CR0_ET;
740
ab344828 741#ifdef CONFIG_X86_64
0f12244f
GN		 742 if (cr0 & 0xffffffff00000000UL)
743 return 1;
ab344828
GN		 744#endif
745
746 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 747
0f12244f
GN		 748 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
749 return 1;
a03490ed 750
0f12244f
GN		 751 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
752 return 1;
a03490ed
CO		 753
754 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
755#ifdef CONFIG_X86_64
f6801dff 756 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 757 int cs_db, cs_l;
758
0f12244f
GN		 759 if (!is_pae(vcpu))
760 return 1;
a03490ed 761 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 762 if (cs_l)
763 return 1;
a03490ed
CO		 764 } else
765#endif
ff03a073 766 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 767 kvm_read_cr3(vcpu)))
0f12244f 768 return 1;
a03490ed
CO		 769 }
770
ad756a16
MJ		 771 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
772 return 1;
773
a03490ed 774 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 775
d170c419 776 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 777 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 778 kvm_async_pf_hash_reset(vcpu);
779 }
e5f3f027 780
aad82703
SY		 781 if ((cr0 ^ old_cr0) & update_bits)
782 kvm_mmu_reset_context(vcpu);
b18d5431 783
879ae188
LE		 784 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
785 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
786 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 787 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
788
0f12244f
GN		 789 return 0;
790}
2d3ad1f4 791EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 792
2d3ad1f4 793void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 794{
49a9b07e 795 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 796}
2d3ad1f4 797EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 798
42bdf991
MT		 799static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
800{
801 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
802 !vcpu->guest_xcr0_loaded) {
803 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 804 if (vcpu->arch.xcr0 != host_xcr0)
805 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 806 vcpu->guest_xcr0_loaded = 1;
807 }
808}
809
810static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
811{
812 if (vcpu->guest_xcr0_loaded) {
813 if (vcpu->arch.xcr0 != host_xcr0)
814 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
815 vcpu->guest_xcr0_loaded = 0;
816 }
817}
818
69b0049a 819static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 820{
56c103ec
LJ		 821 u64 xcr0 = xcr;
822 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 823 u64 valid_bits;
2acf923e
DC		 824
825 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
826 if (index != XCR_XFEATURE_ENABLED_MASK)
827 return 1;
d91cab78 828 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 829 return 1;
d91cab78 830 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 831 return 1;
46c34cb0
PB		 832
833 /*
834 * Do not allow the guest to set bits that we do not support
835 * saving. However, xcr0 bit 0 is always set, even if the
836 * emulated CPU does not support XSAVE (see fx_init).
837 */
d91cab78 838 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 839 if (xcr0 & ~valid_bits)
2acf923e 840 return 1;
46c34cb0 841
d91cab78
DH		 842 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
843 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 844 return 1;
845
d91cab78
DH		 846 if (xcr0 & XFEATURE_MASK_AVX512) {
847 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 848 return 1;
d91cab78 849 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 850 return 1;
851 }
2acf923e 852 vcpu->arch.xcr0 = xcr0;
56c103ec 853
d91cab78 854 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 855 kvm_update_cpuid(vcpu);
2acf923e
DC		 856 return 0;
857}
858
859int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
860{
764bcbc5
Z		 861 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
862 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 863 kvm_inject_gp(vcpu, 0);
864 return 1;
865 }
866 return 0;
867}
868EXPORT_SYMBOL_GPL(kvm_set_xcr);
869
a83b29c6 870int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 871{
fc78f519 872 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 873 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 874 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 875
0f12244f
GN		 876 if (cr4 & CR4_RESERVED_BITS)
877 return 1;
a03490ed 878
d6321d49 879 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 880 return 1;
881
d6321d49 882 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 883 return 1;
884
d6321d49 885 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 886 return 1;
887
d6321d49 888 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 889 return 1;
890
d6321d49 891 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 892 return 1;
893
fd8cb433 894 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 895 return 1;
896
ae3e61e1
PB		 897 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
898 return 1;
899
a03490ed 900 if (is_long_mode(vcpu)) {
0f12244f
GN		 901 if (!(cr4 & X86_CR4_PAE))
902 return 1;
a2edf57f
AK		 903 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
904 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 905 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
906 kvm_read_cr3(vcpu)))
0f12244f
GN		 907 return 1;
908
ad756a16 909 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 910 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 911 return 1;
912
913 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
914 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
915 return 1;
916 }
917
5e1746d6 918 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 919 return 1;
a03490ed 920
ad756a16
MJ		 921 if (((cr4 ^ old_cr4) & pdptr_bits) ||
922 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 923 kvm_mmu_reset_context(vcpu);
0f12244f 924
b9baba86 925 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 926 kvm_update_cpuid(vcpu);
2acf923e 927
0f12244f
GN		 928 return 0;
929}
2d3ad1f4 930EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 931
2390218b 932int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 933{
ade61e28 934 bool skip_tlb_flush = false;
ac146235 935#ifdef CONFIG_X86_64
c19986fe
JS		 936 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
937
ade61e28 938 if (pcid_enabled) {
208320ba
JS		 939 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
940 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 941 }
ac146235 942#endif
9d88fca7 943
9f8fe504 944 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 945 if (!skip_tlb_flush) {
946 kvm_mmu_sync_roots(vcpu);
ade61e28 947 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 948 }
0f12244f 949 return 0;
d835dfec
AK		 950 }
951
d1cd3ce9 952 if (is_long_mode(vcpu) &&
a780a3ea 953 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 954 return 1;
955 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 956 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 957 return 1;
a03490ed 958
ade61e28 959 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 960 vcpu->arch.cr3 = cr3;
aff48baa 961 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 962
0f12244f
GN		 963 return 0;
964}
2d3ad1f4 965EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 966
eea1cff9 967int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 968{
0f12244f
GN		 969 if (cr8 & CR8_RESERVED_BITS)
970 return 1;
35754c98 971 if (lapic_in_kernel(vcpu))
a03490ed
CO		 972 kvm_lapic_set_tpr(vcpu, cr8);
973 else
ad312c7c 974 vcpu->arch.cr8 = cr8;
0f12244f
GN		 975 return 0;
976}
2d3ad1f4 977EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 978
2d3ad1f4 979unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 980{
35754c98 981 if (lapic_in_kernel(vcpu))
a03490ed
CO		 982 return kvm_lapic_get_cr8(vcpu);
983 else
ad312c7c 984 return vcpu->arch.cr8;
a03490ed 985}
2d3ad1f4 986EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 987
ae561ede
NA		 988static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
989{
990 int i;
991
992 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
993 for (i = 0; i < KVM_NR_DB_REGS; i++)
994 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
995 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
996 }
997}
998
73aaf249
JK		 999static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1000{
1001 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1002 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1003}
1004
c8639010
JK		 1005static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1006{
1007 unsigned long dr7;
1008
1009 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1010 dr7 = vcpu->arch.guest_debug_dr7;
1011 else
1012 dr7 = vcpu->arch.dr7;
1013 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1014 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1015 if (dr7 & DR7_BP_EN_MASK)
1016 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1017}
1018
6f43ed01
NA		 1019static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1020{
1021 u64 fixed = DR6_FIXED_1;
1022
d6321d49 1023 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1024 fixed |= DR6_RTM;
1025 return fixed;
1026}
1027
338dbc97 1028static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1029{
1030 switch (dr) {
1031 case 0 ... 3:
1032 vcpu->arch.db[dr] = val;
1033 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1034 vcpu->arch.eff_db[dr] = val;
1035 break;
1036 case 4:
020df079
GN		 1037 /* fall through */
1038 case 6:
338dbc97
GN		 1039 if (val & 0xffffffff00000000ULL)
1040 return -1; /* #GP */
6f43ed01 1041 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1042 kvm_update_dr6(vcpu);
020df079
GN		 1043 break;
1044 case 5:
020df079
GN		 1045 /* fall through */
1046 default: /* 7 */
338dbc97
GN		 1047 if (val & 0xffffffff00000000ULL)
1048 return -1; /* #GP */
020df079 1049 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1050 kvm_update_dr7(vcpu);
020df079
GN		 1051 break;
1052 }
1053
1054 return 0;
1055}
338dbc97
GN		 1056
1057int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1058{
16f8a6f9 1059 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1060 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1061 return 1;
1062 }
1063 return 0;
338dbc97 1064}
020df079
GN		 1065EXPORT_SYMBOL_GPL(kvm_set_dr);
1066
16f8a6f9 1067int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1068{
1069 switch (dr) {
1070 case 0 ... 3:
1071 *val = vcpu->arch.db[dr];
1072 break;
1073 case 4:
020df079
GN		 1074 /* fall through */
1075 case 6:
73aaf249
JK		 1076 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1077 *val = vcpu->arch.dr6;
1078 else
1079 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1080 break;
1081 case 5:
020df079
GN		 1082 /* fall through */
1083 default: /* 7 */
1084 *val = vcpu->arch.dr7;
1085 break;
1086 }
338dbc97
GN		 1087 return 0;
1088}
020df079
GN		 1089EXPORT_SYMBOL_GPL(kvm_get_dr);
1090
022cd0e8
AK		 1091bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1092{
1093 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1094 u64 data;
1095 int err;
1096
c6702c9d 1097 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1098 if (err)
1099 return err;
1100 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1101 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1102 return err;
1103}
1104EXPORT_SYMBOL_GPL(kvm_rdpmc);
1105
043405e1
CO		 1106/*
1107 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1108 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1109 *
1110 * This list is modified at module load time to reflect the
e3267cbb 1111 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1112 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1113 * may depend on host virtualization features rather than host cpu features.
043405e1 1114 */
e3267cbb 1115
043405e1
CO		 1116static u32 msrs_to_save[] = {
1117 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1118 MSR_STAR,
043405e1
CO		 1119#ifdef CONFIG_X86_64
1120 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1121#endif
b3897a49 1122 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1123 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1124 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1125};
1126
1127static unsigned num_msrs_to_save;
1128
62ef68bb
PB		 1129static u32 emulated_msrs[] = {
1130 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1131 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1132 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1133 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1134 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1135 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1136 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1137 HV_X64_MSR_RESET,
11c4b1ca 1138 HV_X64_MSR_VP_INDEX,
9eec50b8 1139 HV_X64_MSR_VP_RUNTIME,
5c919412 1140 HV_X64_MSR_SCONTROL,
1f4b34f8 1141 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1142 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1143 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1144 HV_X64_MSR_TSC_EMULATION_STATUS,
1145
1146 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1147 MSR_KVM_PV_EOI_EN,
1148
ba904635 1149 MSR_IA32_TSC_ADJUST,
a3e06bbe 1150 MSR_IA32_TSCDEADLINE,
043405e1 1151 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1152 MSR_IA32_MCG_STATUS,
1153 MSR_IA32_MCG_CTL,
c45dcc71 1154 MSR_IA32_MCG_EXT_CTL,
64d60670 1155 MSR_IA32_SMBASE,
52797bf9 1156 MSR_SMI_COUNT,
db2336a8
KH		 1157 MSR_PLATFORM_INFO,
1158 MSR_MISC_FEATURES_ENABLES,
bc226f07 1159 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1160};
1161
62ef68bb
PB		 1162static unsigned num_emulated_msrs;
1163
801e459a
TL		 1164/*
1165 * List of msr numbers which are used to expose MSR-based features that
1166 * can be used by a hypervisor to validate requested CPU features.
1167 */
1168static u32 msr_based_features[] = {
1389309c
PB		 1169 MSR_IA32_VMX_BASIC,
1170 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1171 MSR_IA32_VMX_PINBASED_CTLS,
1172 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1173 MSR_IA32_VMX_PROCBASED_CTLS,
1174 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1175 MSR_IA32_VMX_EXIT_CTLS,
1176 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1177 MSR_IA32_VMX_ENTRY_CTLS,
1178 MSR_IA32_VMX_MISC,
1179 MSR_IA32_VMX_CR0_FIXED0,
1180 MSR_IA32_VMX_CR0_FIXED1,
1181 MSR_IA32_VMX_CR4_FIXED0,
1182 MSR_IA32_VMX_CR4_FIXED1,
1183 MSR_IA32_VMX_VMCS_ENUM,
1184 MSR_IA32_VMX_PROCBASED_CTLS2,
1185 MSR_IA32_VMX_EPT_VPID_CAP,
1186 MSR_IA32_VMX_VMFUNC,
1187
d1d93fa9 1188 MSR_F10H_DECFG,
518e7b94 1189 MSR_IA32_UCODE_REV,
cd283252 1190 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1191};
1192
1193static unsigned int num_msr_based_features;
1194
5b76a3cf
PB		 1195u64 kvm_get_arch_capabilities(void)
1196{
1197 u64 data;
1198
1199 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1200
1201 /*
1202 * If we're doing cache flushes (either "always" or "cond")
1203 * we will do one whenever the guest does a vmlaunch/vmresume.
1204 * If an outer hypervisor is doing the cache flush for us
1205 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1206 * capability to the guest too, and if EPT is disabled we're not
1207 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1208 * require a nested hypervisor to do a flush of its own.
1209 */
1210 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1211 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1212
1213 return data;
1214}
1215EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1216
66421c1e
WL		 1217static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1218{
1219 switch (msr->index) {
cd283252 1220 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1221 msr->data = kvm_get_arch_capabilities();
1222 break;
1223 case MSR_IA32_UCODE_REV:
cd283252 1224 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1225 break;
66421c1e
WL		 1226 default:
1227 if (kvm_x86_ops->get_msr_feature(msr))
1228 return 1;
1229 }
1230 return 0;
1231}
1232
801e459a
TL		 1233static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1234{
1235 struct kvm_msr_entry msr;
66421c1e 1236 int r;
801e459a
TL		 1237
1238 msr.index = index;
66421c1e
WL		 1239 r = kvm_get_msr_feature(&msr);
1240 if (r)
1241 return r;
801e459a
TL		 1242
1243 *data = msr.data;
1244
1245 return 0;
1246}
1247
384bb783 1248bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1249{
b69e8cae 1250 if (efer & efer_reserved_bits)
384bb783 1251 return false;
15c4a640 1252
1b4d56b8 1253 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1254 return false;
1b2fd70c 1255
1b4d56b8 1256 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1257 return false;
d8017474 1258
384bb783
JK		 1259 return true;
1260}
1261EXPORT_SYMBOL_GPL(kvm_valid_efer);
1262
1263static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1264{
1265 u64 old_efer = vcpu->arch.efer;
1266
1267 if (!kvm_valid_efer(vcpu, efer))
1268 return 1;
1269
1270 if (is_paging(vcpu)
1271 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1272 return 1;
1273
15c4a640 1274 efer &= ~EFER_LMA;
f6801dff 1275 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1276
a3d204e2
SY		 1277 kvm_x86_ops->set_efer(vcpu, efer);
1278
aad82703
SY		 1279 /* Update reserved bits */
1280 if ((efer ^ old_efer) & EFER_NX)
1281 kvm_mmu_reset_context(vcpu);
1282
b69e8cae 1283 return 0;
15c4a640
CO		 1284}
1285
f2b4b7dd
JR		 1286void kvm_enable_efer_bits(u64 mask)
1287{
1288 efer_reserved_bits &= ~mask;
1289}
1290EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1291
15c4a640
CO		 1292/*
1293 * Writes msr value into into the appropriate "register".
1294 * Returns 0 on success, non-0 otherwise.
1295 * Assumes vcpu_load() was already called.
1296 */
8fe8ab46 1297int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1298{
854e8bb1
NA		 1299 switch (msr->index) {
1300 case MSR_FS_BASE:
1301 case MSR_GS_BASE:
1302 case MSR_KERNEL_GS_BASE:
1303 case MSR_CSTAR:
1304 case MSR_LSTAR:
fd8cb433 1305 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1306 return 1;
1307 break;
1308 case MSR_IA32_SYSENTER_EIP:
1309 case MSR_IA32_SYSENTER_ESP:
1310 /*
1311 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1312 * non-canonical address is written on Intel but not on
1313 * AMD (which ignores the top 32-bits, because it does
1314 * not implement 64-bit SYSENTER).
1315 *
1316 * 64-bit code should hence be able to write a non-canonical
1317 * value on AMD. Making the address canonical ensures that
1318 * vmentry does not fail on Intel after writing a non-canonical
1319 * value, and that something deterministic happens if the guest
1320 * invokes 64-bit SYSENTER.
1321 */
fd8cb433 1322 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1323 }
8fe8ab46 1324 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1325}
854e8bb1 1326EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1327
313a3dc7
CO		 1328/*
1329 * Adapt set_msr() to msr_io()'s calling convention
1330 */
609e36d3
PB		 1331static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1332{
1333 struct msr_data msr;
1334 int r;
1335
1336 msr.index = index;
1337 msr.host_initiated = true;
1338 r = kvm_get_msr(vcpu, &msr);
1339 if (r)
1340 return r;
1341
1342 *data = msr.data;
1343 return 0;
1344}
1345
313a3dc7
CO		 1346static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1347{
8fe8ab46
WA		 1348 struct msr_data msr;
1349
1350 msr.data = *data;
1351 msr.index = index;
1352 msr.host_initiated = true;
1353 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1354}
1355
16e8d74d
MT		 1356#ifdef CONFIG_X86_64
1357struct pvclock_gtod_data {
1358 seqcount_t seq;
1359
1360 struct { /* extract of a clocksource struct */
1361 int vclock_mode;
a5a1d1c2
TG		 1362 u64 cycle_last;
1363 u64 mask;
16e8d74d
MT		 1364 u32 mult;
1365 u32 shift;
1366 } clock;
1367
cbcf2dd3
TG		 1368 u64 boot_ns;
1369 u64 nsec_base;
55dd00a7 1370 u64 wall_time_sec;
16e8d74d
MT		 1371};
1372
1373static struct pvclock_gtod_data pvclock_gtod_data;
1374
1375static void update_pvclock_gtod(struct timekeeper *tk)
1376{
1377 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1378 u64 boot_ns;
1379
876e7881 1380 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1381
1382 write_seqcount_begin(&vdata->seq);
1383
1384 /* copy pvclock gtod data */
876e7881
PZ		 1385 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1386 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1387 vdata->clock.mask = tk->tkr_mono.mask;
1388 vdata->clock.mult = tk->tkr_mono.mult;
1389 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1390
cbcf2dd3 1391 vdata->boot_ns = boot_ns;
876e7881 1392 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1393
55dd00a7
MT		 1394 vdata->wall_time_sec = tk->xtime_sec;
1395
16e8d74d
MT		 1396 write_seqcount_end(&vdata->seq);
1397}
1398#endif
1399
bab5bb39
NK		 1400void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1401{
1402 /*
1403 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1404 * vcpu_enter_guest. This function is only called from
1405 * the physical CPU that is running vcpu.
1406 */
1407 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1408}
16e8d74d 1409
18068523
GOC		 1410static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1411{
9ed3c444
AK		 1412 int version;
1413 int r;
50d0a0f9 1414 struct pvclock_wall_clock wc;
87aeb54f 1415 struct timespec64 boot;
18068523
GOC		 1416
1417 if (!wall_clock)
1418 return;
1419
9ed3c444
AK		 1420 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1421 if (r)
1422 return;
1423
1424 if (version & 1)
1425 ++version; /* first time write, random junk */
1426
1427 ++version;
18068523 1428
1dab1345
NK		 1429 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1430 return;
18068523 1431
50d0a0f9
GH		 1432 /*
1433 * The guest calculates current wall clock time by adding
34c238a1 1434 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1435 * wall clock specified here. guest system time equals host
1436 * system time for us, thus we must fill in host boot time here.
1437 */
87aeb54f 1438 getboottime64(&boot);
50d0a0f9 1439
4b648665 1440 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1441 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1442 boot = timespec64_sub(boot, ts);
4b648665 1443 }
87aeb54f 1444 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1445 wc.nsec = boot.tv_nsec;
1446 wc.version = version;
18068523
GOC		 1447
1448 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1449
1450 version++;
1451 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1452}
1453
50d0a0f9
GH		 1454static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1455{
b51012de
PB		 1456 do_shl32_div32(dividend, divisor);
1457 return dividend;
50d0a0f9
GH		 1458}
1459
3ae13faa 1460static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1461 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1462{
5f4e3f88 1463 uint64_t scaled64;
50d0a0f9
GH		 1464 int32_t shift = 0;
1465 uint64_t tps64;
1466 uint32_t tps32;
1467
3ae13faa
PB		 1468 tps64 = base_hz;
1469 scaled64 = scaled_hz;
50933623 1470 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1471 tps64 >>= 1;
1472 shift--;
1473 }
1474
1475 tps32 = (uint32_t)tps64;
50933623
JK		 1476 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1477 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1478 scaled64 >>= 1;
1479 else
1480 tps32 <<= 1;
50d0a0f9
GH		 1481 shift++;
1482 }
1483
5f4e3f88
ZA		 1484 *pshift = shift;
1485 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1486
3ae13faa
PB		 1487 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1488 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1489}
1490
d828199e 1491#ifdef CONFIG_X86_64
16e8d74d 1492static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1493#endif
16e8d74d 1494
c8076604 1495static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1496static unsigned long max_tsc_khz;
c8076604 1497
cc578287 1498static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1499{
cc578287
ZA		 1500 u64 v = (u64)khz * (1000000 + ppm);
1501 do_div(v, 1000000);
1502 return v;
1e993611
JR		 1503}
1504
381d585c
HZ		 1505static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1506{
1507 u64 ratio;
1508
1509 /* Guest TSC same frequency as host TSC? */
1510 if (!scale) {
1511 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1512 return 0;
1513 }
1514
1515 /* TSC scaling supported? */
1516 if (!kvm_has_tsc_control) {
1517 if (user_tsc_khz > tsc_khz) {
1518 vcpu->arch.tsc_catchup = 1;
1519 vcpu->arch.tsc_always_catchup = 1;
1520 return 0;
1521 } else {
1522 WARN(1, "user requested TSC rate below hardware speed\n");
1523 return -1;
1524 }
1525 }
1526
1527 /* TSC scaling required - calculate ratio */
1528 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1529 user_tsc_khz, tsc_khz);
1530
1531 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1532 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1533 user_tsc_khz);
1534 return -1;
1535 }
1536
1537 vcpu->arch.tsc_scaling_ratio = ratio;
1538 return 0;
1539}
1540
4941b8cb 1541static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1542{
cc578287
ZA		 1543 u32 thresh_lo, thresh_hi;
1544 int use_scaling = 0;
217fc9cf 1545
03ba32ca 1546 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1547 if (user_tsc_khz == 0) {
ad721883
HZ		 1548 /* set tsc_scaling_ratio to a safe value */
1549 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1550 return -1;
ad721883 1551 }
03ba32ca 1552
c285545f 1553 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1554 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1555 &vcpu->arch.virtual_tsc_shift,
1556 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1557 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1558
1559 /*
1560 * Compute the variation in TSC rate which is acceptable
1561 * within the range of tolerance and decide if the
1562 * rate being applied is within that bounds of the hardware
1563 * rate. If so, no scaling or compensation need be done.
1564 */
1565 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1566 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1567 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1568 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1569 use_scaling = 1;
1570 }
4941b8cb 1571 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1572}
1573
1574static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1575{
e26101b1 1576 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1577 vcpu->arch.virtual_tsc_mult,
1578 vcpu->arch.virtual_tsc_shift);
e26101b1 1579 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1580 return tsc;
1581}
1582
b0c39dc6
VK		 1583static inline int gtod_is_based_on_tsc(int mode)
1584{
1585 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1586}
1587
69b0049a 1588static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1589{
1590#ifdef CONFIG_X86_64
1591 bool vcpus_matched;
b48aa97e
MT		 1592 struct kvm_arch *ka = &vcpu->kvm->arch;
1593 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1594
1595 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1596 atomic_read(&vcpu->kvm->online_vcpus));
1597
7f187922
MT		 1598 /*
1599 * Once the masterclock is enabled, always perform request in
1600 * order to update it.
1601 *
1602 * In order to enable masterclock, the host clocksource must be TSC
1603 * and the vcpus need to have matched TSCs. When that happens,
1604 * perform request to enable masterclock.
1605 */
1606 if (ka->use_master_clock ||
b0c39dc6 1607 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1608 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1609
1610 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1611 atomic_read(&vcpu->kvm->online_vcpus),
1612 ka->use_master_clock, gtod->clock.vclock_mode);
1613#endif
1614}
1615
ba904635
WA		 1616static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1617{
e79f245d 1618 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1619 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1620}
1621
35181e86
HZ		 1622/*
1623 * Multiply tsc by a fixed point number represented by ratio.
1624 *
1625 * The most significant 64-N bits (mult) of ratio represent the
1626 * integral part of the fixed point number; the remaining N bits
1627 * (frac) represent the fractional part, ie. ratio represents a fixed
1628 * point number (mult + frac * 2^(-N)).
1629 *
1630 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1631 */
1632static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1633{
1634 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1635}
1636
1637u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1638{
1639 u64 _tsc = tsc;
1640 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1641
1642 if (ratio != kvm_default_tsc_scaling_ratio)
1643 _tsc = __scale_tsc(ratio, tsc);
1644
1645 return _tsc;
1646}
1647EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1648
07c1419a
HZ		 1649static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1650{
1651 u64 tsc;
1652
1653 tsc = kvm_scale_tsc(vcpu, rdtsc());
1654
1655 return target_tsc - tsc;
1656}
1657
4ba76538
HZ		 1658u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1659{
e79f245d
KA		 1660 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1661
1662 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1663}
1664EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1665
a545ab6a
LC		 1666static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1667{
326e7425 1668 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1669}
1670
b0c39dc6
VK		 1671static inline bool kvm_check_tsc_unstable(void)
1672{
1673#ifdef CONFIG_X86_64
1674 /*
1675 * TSC is marked unstable when we're running on Hyper-V,
1676 * 'TSC page' clocksource is good.
1677 */
1678 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1679 return false;
1680#endif
1681 return check_tsc_unstable();
1682}
1683
8fe8ab46 1684void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1685{
1686 struct kvm *kvm = vcpu->kvm;
f38e098f 1687 u64 offset, ns, elapsed;
99e3e30a 1688 unsigned long flags;
b48aa97e 1689 bool matched;
0d3da0d2 1690 bool already_matched;
8fe8ab46 1691 u64 data = msr->data;
c5e8ec8e 1692 bool synchronizing = false;
99e3e30a 1693
038f8c11 1694 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1695 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1696 ns = ktime_get_boot_ns();
f38e098f 1697 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1698
03ba32ca 1699 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1700 if (data == 0 && msr->host_initiated) {
1701 /*
1702 * detection of vcpu initialization -- need to sync
1703 * with other vCPUs. This particularly helps to keep
1704 * kvm_clock stable after CPU hotplug
1705 */
1706 synchronizing = true;
1707 } else {
1708 u64 tsc_exp = kvm->arch.last_tsc_write +
1709 nsec_to_cycles(vcpu, elapsed);
1710 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1711 /*
1712 * Special case: TSC write with a small delta (1 second)
1713 * of virtual cycle time against real time is
1714 * interpreted as an attempt to synchronize the CPU.
1715 */
1716 synchronizing = data < tsc_exp + tsc_hz &&
1717 data + tsc_hz > tsc_exp;
1718 }
c5e8ec8e 1719 }
f38e098f
ZA		 1720
1721 /*
5d3cb0f6
ZA		 1722 * For a reliable TSC, we can match TSC offsets, and for an unstable
1723 * TSC, we add elapsed time in this computation. We could let the
1724 * compensation code attempt to catch up if we fall behind, but
1725 * it's better to try to match offsets from the beginning.
1726 */
c5e8ec8e 1727 if (synchronizing &&
5d3cb0f6 1728 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1729 if (!kvm_check_tsc_unstable()) {
e26101b1 1730 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1731 pr_debug("kvm: matched tsc offset for %llu\n", data);
1732 } else {
857e4099 1733 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1734 data += delta;
07c1419a 1735 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1736 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1737 }
b48aa97e 1738 matched = true;
0d3da0d2 1739 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1740 } else {
1741 /*
1742 * We split periods of matched TSC writes into generations.
1743 * For each generation, we track the original measured
1744 * nanosecond time, offset, and write, so if TSCs are in
1745 * sync, we can match exact offset, and if not, we can match
4a969980 1746 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1747 *
1748 * These values are tracked in kvm->arch.cur_xxx variables.
1749 */
1750 kvm->arch.cur_tsc_generation++;
1751 kvm->arch.cur_tsc_nsec = ns;
1752 kvm->arch.cur_tsc_write = data;
1753 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1754 matched = false;
0d3da0d2 1755 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1756 kvm->arch.cur_tsc_generation, data);
f38e098f 1757 }
e26101b1
ZA		 1758
1759 /*
1760 * We also track th most recent recorded KHZ, write and time to
1761 * allow the matching interval to be extended at each write.
1762 */
f38e098f
ZA		 1763 kvm->arch.last_tsc_nsec = ns;
1764 kvm->arch.last_tsc_write = data;
5d3cb0f6 1765 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1766
b183aa58 1767 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1768
1769 /* Keep track of which generation this VCPU has synchronized to */
1770 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1771 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1772 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1773
d6321d49 1774 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1775 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1776
a545ab6a 1777 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1778 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1779
1780 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1781 if (!matched) {
b48aa97e 1782 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1783 } else if (!already_matched) {
1784 kvm->arch.nr_vcpus_matched_tsc++;
1785 }
b48aa97e
MT		 1786
1787 kvm_track_tsc_matching(vcpu);
1788 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1789}
e26101b1 1790
99e3e30a
ZA		 1791EXPORT_SYMBOL_GPL(kvm_write_tsc);
1792
58ea6767
HZ		 1793static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1794 s64 adjustment)
1795{
326e7425
LS		 1796 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1797 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1798}
1799
1800static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1801{
1802 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1803 WARN_ON(adjustment < 0);
1804 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1805 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1806}
1807
d828199e
MT		 1808#ifdef CONFIG_X86_64
1809
a5a1d1c2 1810static u64 read_tsc(void)
d828199e 1811{
a5a1d1c2 1812 u64 ret = (u64)rdtsc_ordered();
03b9730b 1813 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1814
1815 if (likely(ret >= last))
1816 return ret;
1817
1818 /*
1819 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1820 * predictable (it's just a function of time and the likely is
d828199e
MT		 1821 * very likely) and there's a data dependence, so force GCC
1822 * to generate a branch instead. I don't barrier() because
1823 * we don't actually need a barrier, and if this function
1824 * ever gets inlined it will generate worse code.
1825 */
1826 asm volatile ("");
1827 return last;
1828}
1829
b0c39dc6 1830static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1831{
1832 long v;
1833 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1834 u64 tsc_pg_val;
1835
1836 switch (gtod->clock.vclock_mode) {
1837 case VCLOCK_HVCLOCK:
1838 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1839 tsc_timestamp);
1840 if (tsc_pg_val != U64_MAX) {
1841 /* TSC page valid */
1842 *mode = VCLOCK_HVCLOCK;
1843 v = (tsc_pg_val - gtod->clock.cycle_last) &
1844 gtod->clock.mask;
1845 } else {
1846 /* TSC page invalid */
1847 *mode = VCLOCK_NONE;
1848 }
1849 break;
1850 case VCLOCK_TSC:
1851 *mode = VCLOCK_TSC;
1852 *tsc_timestamp = read_tsc();
1853 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1854 gtod->clock.mask;
1855 break;
1856 default:
1857 *mode = VCLOCK_NONE;
1858 }
d828199e 1859
b0c39dc6
VK		 1860 if (*mode == VCLOCK_NONE)
1861 *tsc_timestamp = v = 0;
d828199e 1862
d828199e
MT		 1863 return v * gtod->clock.mult;
1864}
1865
b0c39dc6 1866static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1867{
cbcf2dd3 1868 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1869 unsigned long seq;
d828199e 1870 int mode;
cbcf2dd3 1871 u64 ns;
d828199e 1872
d828199e
MT		 1873 do {
1874 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1875 ns = gtod->nsec_base;
b0c39dc6 1876 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1877 ns >>= gtod->clock.shift;
cbcf2dd3 1878 ns += gtod->boot_ns;
d828199e 1879 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1880 *t = ns;
d828199e
MT		 1881
1882 return mode;
1883}
1884
899a31f5 1885static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1886{
1887 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1888 unsigned long seq;
1889 int mode;
1890 u64 ns;
1891
1892 do {
1893 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1894 ts->tv_sec = gtod->wall_time_sec;
1895 ns = gtod->nsec_base;
b0c39dc6 1896 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1897 ns >>= gtod->clock.shift;
1898 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1899
1900 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1901 ts->tv_nsec = ns;
1902
1903 return mode;
1904}
1905
b0c39dc6
VK		 1906/* returns true if host is using TSC based clocksource */
1907static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1908{
d828199e 1909 /* checked again under seqlock below */
b0c39dc6 1910 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1911 return false;
1912
b0c39dc6
VK		 1913 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1914 tsc_timestamp));
d828199e 1915}
55dd00a7 1916
b0c39dc6 1917/* returns true if host is using TSC based clocksource */
899a31f5 1918static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1919 u64 *tsc_timestamp)
55dd00a7
MT		 1920{
1921 /* checked again under seqlock below */
b0c39dc6 1922 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1923 return false;
1924
b0c39dc6 1925 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1926}
d828199e
MT		 1927#endif
1928
1929/*
1930 *
b48aa97e
MT		 1931 * Assuming a stable TSC across physical CPUS, and a stable TSC
1932 * across virtual CPUs, the following condition is possible.
1933 * Each numbered line represents an event visible to both
d828199e
MT		 1934 * CPUs at the next numbered event.
1935 *
1936 * "timespecX" represents host monotonic time. "tscX" represents
1937 * RDTSC value.
1938 *
1939 * VCPU0 on CPU0 | VCPU1 on CPU1
1940 *
1941 * 1. read timespec0,tsc0
1942 * 2. | timespec1 = timespec0 + N
1943 * | tsc1 = tsc0 + M
1944 * 3. transition to guest | transition to guest
1945 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1946 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1947 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1948 *
1949 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1950 *
1951 * - ret0 < ret1
1952 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1953 * ...
1954 * - 0 < N - M => M < N
1955 *
1956 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1957 * always the case (the difference between two distinct xtime instances
1958 * might be smaller then the difference between corresponding TSC reads,
1959 * when updating guest vcpus pvclock areas).
1960 *
1961 * To avoid that problem, do not allow visibility of distinct
1962 * system_timestamp/tsc_timestamp values simultaneously: use a master
1963 * copy of host monotonic time values. Update that master copy
1964 * in lockstep.
1965 *
b48aa97e 1966 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1967 *
1968 */
1969
1970static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1971{
1972#ifdef CONFIG_X86_64
1973 struct kvm_arch *ka = &kvm->arch;
1974 int vclock_mode;
b48aa97e
MT		 1975 bool host_tsc_clocksource, vcpus_matched;
1976
1977 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1978 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1979
1980 /*
1981 * If the host uses TSC clock, then passthrough TSC as stable
1982 * to the guest.
1983 */
b48aa97e 1984 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1985 &ka->master_kernel_ns,
1986 &ka->master_cycle_now);
1987
16a96021 1988 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1989 && !ka->backwards_tsc_observed
54750f2c 1990 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1991
d828199e
MT		 1992 if (ka->use_master_clock)
1993 atomic_set(&kvm_guest_has_master_clock, 1);
1994
1995 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1996 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1997 vcpus_matched);
d828199e
MT		 1998#endif
1999}
2000
2860c4b1
PB		 2001void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2002{
2003 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2004}
2005
2e762ff7
MT		 2006static void kvm_gen_update_masterclock(struct kvm *kvm)
2007{
2008#ifdef CONFIG_X86_64
2009 int i;
2010 struct kvm_vcpu *vcpu;
2011 struct kvm_arch *ka = &kvm->arch;
2012
2013 spin_lock(&ka->pvclock_gtod_sync_lock);
2014 kvm_make_mclock_inprogress_request(kvm);
2015 /* no guest entries from this point */
2016 pvclock_update_vm_gtod_copy(kvm);
2017
2018 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2019 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2020
2021 /* guest entries allowed */
2022 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2023 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2024
2025 spin_unlock(&ka->pvclock_gtod_sync_lock);
2026#endif
2027}
2028
e891a32e 2029u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2030{
108b249c 2031 struct kvm_arch *ka = &kvm->arch;
8b953440 2032 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2033 u64 ret;
108b249c 2034
8b953440
PB		 2035 spin_lock(&ka->pvclock_gtod_sync_lock);
2036 if (!ka->use_master_clock) {
2037 spin_unlock(&ka->pvclock_gtod_sync_lock);
2038 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 2039 }
2040
8b953440
PB		 2041 hv_clock.tsc_timestamp = ka->master_cycle_now;
2042 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2043 spin_unlock(&ka->pvclock_gtod_sync_lock);
2044
e2c2206a
WL		 2045 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2046 get_cpu();
2047
e70b57a6
WL		 2048 if (__this_cpu_read(cpu_tsc_khz)) {
2049 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2050 &hv_clock.tsc_shift,
2051 &hv_clock.tsc_to_system_mul);
2052 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2053 } else
2054 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2055
2056 put_cpu();
2057
2058 return ret;
108b249c
PB		 2059}
2060
0d6dd2ff
PB		 2061static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2062{
2063 struct kvm_vcpu_arch *vcpu = &v->arch;
2064 struct pvclock_vcpu_time_info guest_hv_clock;
2065
4e335d9e 2066 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2067 &guest_hv_clock, sizeof(guest_hv_clock))))
2068 return;
2069
2070 /* This VCPU is paused, but it's legal for a guest to read another
2071 * VCPU's kvmclock, so we really have to follow the specification where
2072 * it says that version is odd if data is being modified, and even after
2073 * it is consistent.
2074 *
2075 * Version field updates must be kept separate. This is because
2076 * kvm_write_guest_cached might use a "rep movs" instruction, and
2077 * writes within a string instruction are weakly ordered. So there
2078 * are three writes overall.
2079 *
2080 * As a small optimization, only write the version field in the first
2081 * and third write. The vcpu->pv_time cache is still valid, because the
2082 * version field is the first in the struct.
2083 */
2084 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2085
51c4b8bb
LA		 2086 if (guest_hv_clock.version & 1)
2087 ++guest_hv_clock.version; /* first time write, random junk */
2088
0d6dd2ff 2089 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2090 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2091 &vcpu->hv_clock,
2092 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2093
2094 smp_wmb();
2095
2096 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2097 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2098
2099 if (vcpu->pvclock_set_guest_stopped_request) {
2100 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2101 vcpu->pvclock_set_guest_stopped_request = false;
2102 }
2103
2104 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2105
4e335d9e
PB		 2106 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2107 &vcpu->hv_clock,
2108 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2109
2110 smp_wmb();
2111
2112 vcpu->hv_clock.version++;
4e335d9e
PB		 2113 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2114 &vcpu->hv_clock,
2115 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2116}
2117
34c238a1 2118static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2119{
78db6a50 2120 unsigned long flags, tgt_tsc_khz;
18068523 2121 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2122 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2123 s64 kernel_ns;
d828199e 2124 u64 tsc_timestamp, host_tsc;
51d59c6b 2125 u8 pvclock_flags;
d828199e
MT		 2126 bool use_master_clock;
2127
2128 kernel_ns = 0;
2129 host_tsc = 0;
18068523 2130
d828199e
MT		 2131 /*
2132 * If the host uses TSC clock, then passthrough TSC as stable
2133 * to the guest.
2134 */
2135 spin_lock(&ka->pvclock_gtod_sync_lock);
2136 use_master_clock = ka->use_master_clock;
2137 if (use_master_clock) {
2138 host_tsc = ka->master_cycle_now;
2139 kernel_ns = ka->master_kernel_ns;
2140 }
2141 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2142
2143 /* Keep irq disabled to prevent changes to the clock */
2144 local_irq_save(flags);
78db6a50
PB		 2145 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2146 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2147 local_irq_restore(flags);
2148 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2149 return 1;
2150 }
d828199e 2151 if (!use_master_clock) {
4ea1636b 2152 host_tsc = rdtsc();
108b249c 2153 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2154 }
2155
4ba76538 2156 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2157
c285545f
ZA		 2158 /*
2159 * We may have to catch up the TSC to match elapsed wall clock
2160 * time for two reasons, even if kvmclock is used.
2161 * 1) CPU could have been running below the maximum TSC rate
2162 * 2) Broken TSC compensation resets the base at each VCPU
2163 * entry to avoid unknown leaps of TSC even when running
2164 * again on the same CPU. This may cause apparent elapsed
2165 * time to disappear, and the guest to stand still or run
2166 * very slowly.
2167 */
2168 if (vcpu->tsc_catchup) {
2169 u64 tsc = compute_guest_tsc(v, kernel_ns);
2170 if (tsc > tsc_timestamp) {
f1e2b260 2171 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2172 tsc_timestamp = tsc;
2173 }
50d0a0f9
GH		 2174 }
2175
18068523
GOC		 2176 local_irq_restore(flags);
2177
0d6dd2ff 2178 /* With all the info we got, fill in the values */
18068523 2179
78db6a50
PB		 2180 if (kvm_has_tsc_control)
2181 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2182
2183 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2184 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2185 &vcpu->hv_clock.tsc_shift,
2186 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2187 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2188 }
2189
1d5f066e 2190 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2191 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2192 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2193
d828199e 2194 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2195 pvclock_flags = 0;
d828199e
MT		 2196 if (use_master_clock)
2197 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2198
78c0337a
MT		 2199 vcpu->hv_clock.flags = pvclock_flags;
2200
095cf55d
PB		 2201 if (vcpu->pv_time_enabled)
2202 kvm_setup_pvclock_page(v);
2203 if (v == kvm_get_vcpu(v->kvm, 0))
2204 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2205 return 0;
c8076604
GH		 2206}
2207
0061d53d
MT		 2208/*
2209 * kvmclock updates which are isolated to a given vcpu, such as
2210 * vcpu->cpu migration, should not allow system_timestamp from
2211 * the rest of the vcpus to remain static. Otherwise ntp frequency
2212 * correction applies to one vcpu's system_timestamp but not
2213 * the others.
2214 *
2215 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2216 * We need to rate-limit these requests though, as they can
2217 * considerably slow guests that have a large number of vcpus.
2218 * The time for a remote vcpu to update its kvmclock is bound
2219 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2220 */
2221
7e44e449
AJ		 2222#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2223
2224static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2225{
2226 int i;
7e44e449
AJ		 2227 struct delayed_work *dwork = to_delayed_work(work);
2228 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2229 kvmclock_update_work);
2230 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2231 struct kvm_vcpu *vcpu;
2232
2233 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2234 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2235 kvm_vcpu_kick(vcpu);
2236 }
2237}
2238
7e44e449
AJ		 2239static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2240{
2241 struct kvm *kvm = v->kvm;
2242
105b21bb 2243 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2244 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2245 KVMCLOCK_UPDATE_DELAY);
2246}
2247
332967a3
AJ		 2248#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2249
2250static void kvmclock_sync_fn(struct work_struct *work)
2251{
2252 struct delayed_work *dwork = to_delayed_work(work);
2253 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2254 kvmclock_sync_work);
2255 struct kvm *kvm = container_of(ka, struct kvm, arch);
2256
630994b3
MT		 2257 if (!kvmclock_periodic_sync)
2258 return;
2259
332967a3
AJ		 2260 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2261 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2262 KVMCLOCK_SYNC_PERIOD);
2263}
2264
9ffd986c 2265static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2266{
890ca9ae
HY		 2267 u64 mcg_cap = vcpu->arch.mcg_cap;
2268 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2269 u32 msr = msr_info->index;
2270 u64 data = msr_info->data;
890ca9ae 2271
15c4a640 2272 switch (msr) {
15c4a640 2273 case MSR_IA32_MCG_STATUS:
890ca9ae 2274 vcpu->arch.mcg_status = data;
15c4a640 2275 break;
c7ac679c 2276 case MSR_IA32_MCG_CTL:
44883f01
PB		 2277 if (!(mcg_cap & MCG_CTL_P) &&
2278 (data || !msr_info->host_initiated))
890ca9ae
HY		 2279 return 1;
2280 if (data != 0 && data != ~(u64)0)
44883f01 2281 return 1;
890ca9ae
HY		 2282 vcpu->arch.mcg_ctl = data;
2283 break;
2284 default:
2285 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2286 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2287 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2288 /* only 0 or all 1s can be written to IA32_MCi_CTL
2289 * some Linux kernels though clear bit 10 in bank 4 to
2290 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2291 * this to avoid an uncatched #GP in the guest
2292 */
890ca9ae 2293 if ((offset & 0x3) == 0 &&
114be429 2294 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2295 return -1;
9ffd986c
WL		 2296 if (!msr_info->host_initiated &&
2297 (offset & 0x3) == 1 && data != 0)
2298 return -1;
890ca9ae
HY		 2299 vcpu->arch.mce_banks[offset] = data;
2300 break;
2301 }
2302 return 1;
2303 }
2304 return 0;
2305}
2306
ffde22ac
ES		 2307static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2308{
2309 struct kvm *kvm = vcpu->kvm;
2310 int lm = is_long_mode(vcpu);
2311 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2312 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2313 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2314 : kvm->arch.xen_hvm_config.blob_size_32;
2315 u32 page_num = data & ~PAGE_MASK;
2316 u64 page_addr = data & PAGE_MASK;
2317 u8 *page;
2318 int r;
2319
2320 r = -E2BIG;
2321 if (page_num >= blob_size)
2322 goto out;
2323 r = -ENOMEM;
ff5c2c03
SL		 2324 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2325 if (IS_ERR(page)) {
2326 r = PTR_ERR(page);
ffde22ac 2327 goto out;
ff5c2c03 2328 }
54bf36aa 2329 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2330 goto out_free;
2331 r = 0;
2332out_free:
2333 kfree(page);
2334out:
2335 return r;
2336}
2337
344d9588
GN		 2338static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2339{
2340 gpa_t gpa = data & ~0x3f;
2341
52a5c155
WL		 2342 /* Bits 3:5 are reserved, Should be zero */
2343 if (data & 0x38)
344d9588
GN		 2344 return 1;
2345
2346 vcpu->arch.apf.msr_val = data;
2347
2348 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2349 kvm_clear_async_pf_completion_queue(vcpu);
2350 kvm_async_pf_hash_reset(vcpu);
2351 return 0;
2352 }
2353
4e335d9e 2354 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2355 sizeof(u32)))
344d9588
GN		 2356 return 1;
2357
6adba527 2358 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2359 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2360 kvm_async_pf_wakeup_all(vcpu);
2361 return 0;
2362}
2363
12f9a48f
GC		 2364static void kvmclock_reset(struct kvm_vcpu *vcpu)
2365{
0b79459b 2366 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2367}
2368
f38a7b75
WL		 2369static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2370{
2371 ++vcpu->stat.tlb_flush;
2372 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2373}
2374
c9aaa895
GC		 2375static void record_steal_time(struct kvm_vcpu *vcpu)
2376{
2377 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2378 return;
2379
4e335d9e 2380 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2381 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2382 return;
2383
f38a7b75
WL		 2384 /*
2385 * Doing a TLB flush here, on the guest's behalf, can avoid
2386 * expensive IPIs.
2387 */
2388 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2389 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2390
35f3fae1
WL		 2391 if (vcpu->arch.st.steal.version & 1)
2392 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2393
2394 vcpu->arch.st.steal.version += 1;
2395
4e335d9e 2396 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2397 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2398
2399 smp_wmb();
2400
c54cdf14
LC		 2401 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2402 vcpu->arch.st.last_steal;
2403 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2404
4e335d9e 2405 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2406 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2407
2408 smp_wmb();
2409
2410 vcpu->arch.st.steal.version += 1;
c9aaa895 2411
4e335d9e 2412 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2413 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2414}
2415
8fe8ab46 2416int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2417{
5753785f 2418 bool pr = false;
8fe8ab46
WA		 2419 u32 msr = msr_info->index;
2420 u64 data = msr_info->data;
5753785f 2421
15c4a640 2422 switch (msr) {
2e32b719 2423 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2424 case MSR_IA32_UCODE_WRITE:
2425 case MSR_VM_HSAVE_PA:
2426 case MSR_AMD64_PATCH_LOADER:
2427 case MSR_AMD64_BU_CFG2:
405a353a 2428 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2429 break;
2430
518e7b94
WL		 2431 case MSR_IA32_UCODE_REV:
2432 if (msr_info->host_initiated)
2433 vcpu->arch.microcode_version = data;
2434 break;
15c4a640 2435 case MSR_EFER:
b69e8cae 2436 return set_efer(vcpu, data);
8f1589d9
AP		 2437 case MSR_K7_HWCR:
2438 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2439 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2440 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2441 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2442 if (data != 0) {
a737f256
CD		 2443 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2444 data);
8f1589d9
AP		 2445 return 1;
2446 }
15c4a640 2447 break;
f7c6d140
AP		 2448 case MSR_FAM10H_MMIO_CONF_BASE:
2449 if (data != 0) {
a737f256
CD		 2450 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2451 "0x%llx\n", data);
f7c6d140
AP		 2452 return 1;
2453 }
15c4a640 2454 break;
b5e2fec0
AG		 2455 case MSR_IA32_DEBUGCTLMSR:
2456 if (!data) {
2457 /* We support the non-activated case already */
2458 break;
2459 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2460 /* Values other than LBR and BTF are vendor-specific,
2461 thus reserved and should throw a #GP */
2462 return 1;
2463 }
a737f256
CD		 2464 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2465 __func__, data);
b5e2fec0 2466 break;
9ba075a6 2467 case 0x200 ... 0x2ff:
ff53604b 2468 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2469 case MSR_IA32_APICBASE:
58cb628d 2470 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2471 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2472 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2473 case MSR_IA32_TSCDEADLINE:
2474 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2475 break;
ba904635 2476 case MSR_IA32_TSC_ADJUST:
d6321d49 2477 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2478 if (!msr_info->host_initiated) {
d913b904 2479 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2480 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2481 }
2482 vcpu->arch.ia32_tsc_adjust_msr = data;
2483 }
2484 break;
15c4a640 2485 case MSR_IA32_MISC_ENABLE:
ad312c7c 2486 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2487 break;
64d60670
PB		 2488 case MSR_IA32_SMBASE:
2489 if (!msr_info->host_initiated)
2490 return 1;
2491 vcpu->arch.smbase = data;
2492 break;
dd259935
PB		 2493 case MSR_IA32_TSC:
2494 kvm_write_tsc(vcpu, msr_info);
2495 break;
52797bf9
LA		 2496 case MSR_SMI_COUNT:
2497 if (!msr_info->host_initiated)
2498 return 1;
2499 vcpu->arch.smi_count = data;
2500 break;
11c6bffa 2501 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2502 case MSR_KVM_WALL_CLOCK:
2503 vcpu->kvm->arch.wall_clock = data;
2504 kvm_write_wall_clock(vcpu->kvm, data);
2505 break;
11c6bffa 2506 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2507 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2508 struct kvm_arch *ka = &vcpu->kvm->arch;
2509
12f9a48f 2510 kvmclock_reset(vcpu);
18068523 2511
54750f2c
MT		 2512 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2513 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2514
2515 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2516 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2517
2518 ka->boot_vcpu_runs_old_kvmclock = tmp;
2519 }
2520
18068523 2521 vcpu->arch.time = data;
0061d53d 2522 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2523
2524 /* we verify if the enable bit is set... */
2525 if (!(data & 1))
2526 break;
2527
4e335d9e 2528 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2529 &vcpu->arch.pv_time, data & ~1ULL,
2530 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2531 vcpu->arch.pv_time_enabled = false;
2532 else
2533 vcpu->arch.pv_time_enabled = true;
32cad84f 2534
18068523
GOC		 2535 break;
2536 }
344d9588
GN		 2537 case MSR_KVM_ASYNC_PF_EN:
2538 if (kvm_pv_enable_async_pf(vcpu, data))
2539 return 1;
2540 break;
c9aaa895
GC		 2541 case MSR_KVM_STEAL_TIME:
2542
2543 if (unlikely(!sched_info_on()))
2544 return 1;
2545
2546 if (data & KVM_STEAL_RESERVED_MASK)
2547 return 1;
2548
4e335d9e 2549 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2550 data & KVM_STEAL_VALID_BITS,
2551 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2552 return 1;
2553
2554 vcpu->arch.st.msr_val = data;
2555
2556 if (!(data & KVM_MSR_ENABLED))
2557 break;
2558
c9aaa895
GC		 2559 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2560
2561 break;
ae7a2a3f 2562 case MSR_KVM_PV_EOI_EN:
72bbf935 2563 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2564 return 1;
2565 break;
c9aaa895 2566
890ca9ae
HY		 2567 case MSR_IA32_MCG_CTL:
2568 case MSR_IA32_MCG_STATUS:
81760dcc 2569 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2570 return set_msr_mce(vcpu, msr_info);
71db6023 2571
6912ac32
WH		 2572 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2573 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2574 pr = true; /* fall through */
2575 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2576 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2577 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2578 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2579
2580 if (pr || data != 0)
a737f256
CD		 2581 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2582 "0x%x data 0x%llx\n", msr, data);
5753785f 2583 break;
84e0cefa
JS		 2584 case MSR_K7_CLK_CTL:
2585 /*
2586 * Ignore all writes to this no longer documented MSR.
2587 * Writes are only relevant for old K7 processors,
2588 * all pre-dating SVM, but a recommended workaround from
4a969980 2589 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2590 * affected processor models on the command line, hence
2591 * the need to ignore the workaround.
2592 */
2593 break;
55cd8e5a 2594 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2595 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2596 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2597 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2598 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2599 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2600 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2601 return kvm_hv_set_msr_common(vcpu, msr, data,
2602 msr_info->host_initiated);
91c9c3ed 2603 case MSR_IA32_BBL_CR_CTL3:
2604 /* Drop writes to this legacy MSR -- see rdmsr
2605 * counterpart for further detail.
2606 */
fab0aa3b
EM		 2607 if (report_ignored_msrs)
2608 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2609 msr, data);
91c9c3ed 2610 break;
2b036c6b 2611 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2612 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2613 return 1;
2614 vcpu->arch.osvw.length = data;
2615 break;
2616 case MSR_AMD64_OSVW_STATUS:
d6321d49 2617 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2618 return 1;
2619 vcpu->arch.osvw.status = data;
2620 break;
db2336a8
KH		 2621 case MSR_PLATFORM_INFO:
2622 if (!msr_info->host_initiated ||
db2336a8
KH		 2623 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2624 cpuid_fault_enabled(vcpu)))
2625 return 1;
2626 vcpu->arch.msr_platform_info = data;
2627 break;
2628 case MSR_MISC_FEATURES_ENABLES:
2629 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2630 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2631 !supports_cpuid_fault(vcpu)))
2632 return 1;
2633 vcpu->arch.msr_misc_features_enables = data;
2634 break;
15c4a640 2635 default:
ffde22ac
ES		 2636 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2637 return xen_hvm_config(vcpu, data);
c6702c9d 2638 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2639 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2640 if (!ignore_msrs) {
ae0f5499 2641 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2642 msr, data);
ed85c068
AP		 2643 return 1;
2644 } else {
fab0aa3b
EM		 2645 if (report_ignored_msrs)
2646 vcpu_unimpl(vcpu,
2647 "ignored wrmsr: 0x%x data 0x%llx\n",
2648 msr, data);
ed85c068
AP		 2649 break;
2650 }
15c4a640
CO		 2651 }
2652 return 0;
2653}
2654EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2655
2656
2657/*
2658 * Reads an msr value (of 'msr_index') into 'pdata'.
2659 * Returns 0 on success, non-0 otherwise.
2660 * Assumes vcpu_load() was already called.
2661 */
609e36d3 2662int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2663{
609e36d3 2664 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2665}
ff651cb6 2666EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2667
44883f01 2668static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2669{
2670 u64 data;
890ca9ae
HY		 2671 u64 mcg_cap = vcpu->arch.mcg_cap;
2672 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2673
2674 switch (msr) {
15c4a640
CO		 2675 case MSR_IA32_P5_MC_ADDR:
2676 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2677 data = 0;
2678 break;
15c4a640 2679 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2680 data = vcpu->arch.mcg_cap;
2681 break;
c7ac679c 2682 case MSR_IA32_MCG_CTL:
44883f01 2683 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2684 return 1;
2685 data = vcpu->arch.mcg_ctl;
2686 break;
2687 case MSR_IA32_MCG_STATUS:
2688 data = vcpu->arch.mcg_status;
2689 break;
2690 default:
2691 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2692 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2693 u32 offset = msr - MSR_IA32_MC0_CTL;
2694 data = vcpu->arch.mce_banks[offset];
2695 break;
2696 }
2697 return 1;
2698 }
2699 *pdata = data;
2700 return 0;
2701}
2702
609e36d3 2703int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2704{
609e36d3 2705 switch (msr_info->index) {
890ca9ae 2706 case MSR_IA32_PLATFORM_ID:
15c4a640 2707 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2708 case MSR_IA32_DEBUGCTLMSR:
2709 case MSR_IA32_LASTBRANCHFROMIP:
2710 case MSR_IA32_LASTBRANCHTOIP:
2711 case MSR_IA32_LASTINTFROMIP:
2712 case MSR_IA32_LASTINTTOIP:
60af2ecd 2713 case MSR_K8_SYSCFG:
3afb1121
PB		 2714 case MSR_K8_TSEG_ADDR:
2715 case MSR_K8_TSEG_MASK:
60af2ecd 2716 case MSR_K7_HWCR:
61a6bd67 2717 case MSR_VM_HSAVE_PA:
1fdbd48c 2718 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2719 case MSR_AMD64_NB_CFG:
f7c6d140 2720 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2721 case MSR_AMD64_BU_CFG2:
0c2df2a1 2722 case MSR_IA32_PERF_CTL:
405a353a 2723 case MSR_AMD64_DC_CFG:
609e36d3 2724 msr_info->data = 0;
15c4a640 2725 break;
c51eb52b 2726 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2727 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2728 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2729 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2730 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2731 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2732 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2733 msr_info->data = 0;
5753785f 2734 break;
742bc670 2735 case MSR_IA32_UCODE_REV:
518e7b94 2736 msr_info->data = vcpu->arch.microcode_version;
742bc670 2737 break;
dd259935
PB		 2738 case MSR_IA32_TSC:
2739 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2740 break;
9ba075a6 2741 case MSR_MTRRcap:
9ba075a6 2742 case 0x200 ... 0x2ff:
ff53604b 2743 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2744 case 0xcd: /* fsb frequency */
609e36d3 2745 msr_info->data = 3;
15c4a640 2746 break;
7b914098
JS		 2747 /*
2748 * MSR_EBC_FREQUENCY_ID
2749 * Conservative value valid for even the basic CPU models.
2750 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2751 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2752 * and 266MHz for model 3, or 4. Set Core Clock
2753 * Frequency to System Bus Frequency Ratio to 1 (bits
2754 * 31:24) even though these are only valid for CPU
2755 * models > 2, however guests may end up dividing or
2756 * multiplying by zero otherwise.
2757 */
2758 case MSR_EBC_FREQUENCY_ID:
609e36d3 2759 msr_info->data = 1 << 24;
7b914098 2760 break;
15c4a640 2761 case MSR_IA32_APICBASE:
609e36d3 2762 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2763 break;
0105d1a5 2764 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2765 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2766 break;
a3e06bbe 2767 case MSR_IA32_TSCDEADLINE:
609e36d3 2768 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2769 break;
ba904635 2770 case MSR_IA32_TSC_ADJUST:
609e36d3 2771 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2772 break;
15c4a640 2773 case MSR_IA32_MISC_ENABLE:
609e36d3 2774 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2775 break;
64d60670
PB		 2776 case MSR_IA32_SMBASE:
2777 if (!msr_info->host_initiated)
2778 return 1;
2779 msr_info->data = vcpu->arch.smbase;
15c4a640 2780 break;
52797bf9
LA		 2781 case MSR_SMI_COUNT:
2782 msr_info->data = vcpu->arch.smi_count;
2783 break;
847f0ad8
AG		 2784 case MSR_IA32_PERF_STATUS:
2785 /* TSC increment by tick */
609e36d3 2786 msr_info->data = 1000ULL;
847f0ad8 2787 /* CPU multiplier */
b0996ae4 2788 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2789 break;
15c4a640 2790 case MSR_EFER:
609e36d3 2791 msr_info->data = vcpu->arch.efer;
15c4a640 2792 break;
18068523 2793 case MSR_KVM_WALL_CLOCK:
11c6bffa 2794 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2795 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2796 break;
2797 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2798 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2799 msr_info->data = vcpu->arch.time;
18068523 2800 break;
344d9588 2801 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2802 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2803 break;
c9aaa895 2804 case MSR_KVM_STEAL_TIME:
609e36d3 2805 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2806 break;
1d92128f 2807 case MSR_KVM_PV_EOI_EN:
609e36d3 2808 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2809 break;
890ca9ae
HY		 2810 case MSR_IA32_P5_MC_ADDR:
2811 case MSR_IA32_P5_MC_TYPE:
2812 case MSR_IA32_MCG_CAP:
2813 case MSR_IA32_MCG_CTL:
2814 case MSR_IA32_MCG_STATUS:
81760dcc 2815 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2816 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2817 msr_info->host_initiated);
84e0cefa
JS		 2818 case MSR_K7_CLK_CTL:
2819 /*
2820 * Provide expected ramp-up count for K7. All other
2821 * are set to zero, indicating minimum divisors for
2822 * every field.
2823 *
2824 * This prevents guest kernels on AMD host with CPU
2825 * type 6, model 8 and higher from exploding due to
2826 * the rdmsr failing.
2827 */
609e36d3 2828 msr_info->data = 0x20000000;
84e0cefa 2829 break;
55cd8e5a 2830 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2831 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2832 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2833 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2834 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2835 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2836 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2837 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2838 msr_info->index, &msr_info->data,
2839 msr_info->host_initiated);
55cd8e5a 2840 break;
91c9c3ed 2841 case MSR_IA32_BBL_CR_CTL3:
2842 /* This legacy MSR exists but isn't fully documented in current
2843 * silicon. It is however accessed by winxp in very narrow
2844 * scenarios where it sets bit #19, itself documented as
2845 * a "reserved" bit. Best effort attempt to source coherent
2846 * read data here should the balance of the register be
2847 * interpreted by the guest:
2848 *
2849 * L2 cache control register 3: 64GB range, 256KB size,
2850 * enabled, latency 0x1, configured
2851 */
609e36d3 2852 msr_info->data = 0xbe702111;
91c9c3ed 2853 break;
2b036c6b 2854 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2855 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2856 return 1;
609e36d3 2857 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2858 break;
2859 case MSR_AMD64_OSVW_STATUS:
d6321d49 2860 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2861 return 1;
609e36d3 2862 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2863 break;
db2336a8 2864 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2865 if (!msr_info->host_initiated &&
2866 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2867 return 1;
db2336a8
KH		 2868 msr_info->data = vcpu->arch.msr_platform_info;
2869 break;
2870 case MSR_MISC_FEATURES_ENABLES:
2871 msr_info->data = vcpu->arch.msr_misc_features_enables;
2872 break;
15c4a640 2873 default:
c6702c9d 2874 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2875 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2876 if (!ignore_msrs) {
ae0f5499
BD		 2877 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2878 msr_info->index);
ed85c068
AP		 2879 return 1;
2880 } else {
fab0aa3b
EM		 2881 if (report_ignored_msrs)
2882 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2883 msr_info->index);
609e36d3 2884 msr_info->data = 0;
ed85c068
AP		 2885 }
2886 break;
15c4a640 2887 }
15c4a640
CO		 2888 return 0;
2889}
2890EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2891
313a3dc7
CO		 2892/*
2893 * Read or write a bunch of msrs. All parameters are kernel addresses.
2894 *
2895 * @return number of msrs set successfully.
2896 */
2897static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2898 struct kvm_msr_entry *entries,
2899 int (*do_msr)(struct kvm_vcpu *vcpu,
2900 unsigned index, u64 *data))
2901{
801e459a 2902 int i;
313a3dc7 2903
313a3dc7
CO		 2904 for (i = 0; i < msrs->nmsrs; ++i)
2905 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2906 break;
2907
313a3dc7
CO		 2908 return i;
2909}
2910
2911/*
2912 * Read or write a bunch of msrs. Parameters are user addresses.
2913 *
2914 * @return number of msrs set successfully.
2915 */
2916static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2917 int (*do_msr)(struct kvm_vcpu *vcpu,
2918 unsigned index, u64 *data),
2919 int writeback)
2920{
2921 struct kvm_msrs msrs;
2922 struct kvm_msr_entry *entries;
2923 int r, n;
2924 unsigned size;
2925
2926 r = -EFAULT;
0e96f31e 2927 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 2928 goto out;
2929
2930 r = -E2BIG;
2931 if (msrs.nmsrs >= MAX_IO_MSRS)
2932 goto out;
2933
313a3dc7 2934 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2935 entries = memdup_user(user_msrs->entries, size);
2936 if (IS_ERR(entries)) {
2937 r = PTR_ERR(entries);
313a3dc7 2938 goto out;
ff5c2c03 2939 }
313a3dc7
CO		 2940
2941 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2942 if (r < 0)
2943 goto out_free;
2944
2945 r = -EFAULT;
2946 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2947 goto out_free;
2948
2949 r = n;
2950
2951out_free:
7a73c028 2952 kfree(entries);
313a3dc7
CO		 2953out:
2954 return r;
2955}
2956
4d5422ce
WL		 2957static inline bool kvm_can_mwait_in_guest(void)
2958{
2959 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2960 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2961 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2962}
2963
784aa3d7 2964int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2965{
4d5422ce 2966 int r = 0;
018d00d2
ZX		 2967
2968 switch (ext) {
2969 case KVM_CAP_IRQCHIP:
2970 case KVM_CAP_HLT:
2971 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2972 case KVM_CAP_SET_TSS_ADDR:
07716717 2973 case KVM_CAP_EXT_CPUID:
9c15bb1d 2974 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2975 case KVM_CAP_CLOCKSOURCE:
7837699f 2976 case KVM_CAP_PIT:
a28e4f5a 2977 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2978 case KVM_CAP_MP_STATE:
ed848624 2979 case KVM_CAP_SYNC_MMU:
a355c85c 2980 case KVM_CAP_USER_NMI:
52d939a0 2981 case KVM_CAP_REINJECT_CONTROL:
4925663a 2982 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2983 case KVM_CAP_IOEVENTFD:
f848a5a8 2984 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2985 case KVM_CAP_PIT2:
e9f42757 2986 case KVM_CAP_PIT_STATE2:
b927a3ce 2987 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2988 case KVM_CAP_XEN_HVM:
3cfc3092 2989 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2990 case KVM_CAP_HYPERV:
10388a07 2991 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2992 case KVM_CAP_HYPERV_SPIN:
5c919412 2993 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2994 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2995 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2996 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2997 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 2998 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 2999 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
2bc39970 3000 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3001 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3002 case KVM_CAP_DEBUGREGS:
d2be1651 3003 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3004 case KVM_CAP_XSAVE:
344d9588 3005 case KVM_CAP_ASYNC_PF:
92a1f12d 3006 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3007 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3008 case KVM_CAP_READONLY_MEM:
5f66b620 3009 case KVM_CAP_HYPERV_TIME:
100943c5 3010 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3011 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3012 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3013 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3014 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3015 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 3016 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3017 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3018 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3019 r = 1;
3020 break;
01643c51
KH		 3021 case KVM_CAP_SYNC_REGS:
3022 r = KVM_SYNC_X86_VALID_FIELDS;
3023 break;
e3fd9a93
PB		 3024 case KVM_CAP_ADJUST_CLOCK:
3025 r = KVM_CLOCK_TSC_STABLE;
3026 break;
4d5422ce 3027 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 3028 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 3029 if(kvm_can_mwait_in_guest())
3030 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3031 break;
6d396b55
PB		 3032 case KVM_CAP_X86_SMM:
3033 /* SMBASE is usually relocated above 1M on modern chipsets,
3034 * and SMM handlers might indeed rely on 4G segment limits,
3035 * so do not report SMM to be available if real mode is
3036 * emulated via vm86 mode. Still, do not go to great lengths
3037 * to avoid userspace's usage of the feature, because it is a
3038 * fringe case that is not enabled except via specific settings
3039 * of the module parameters.
3040 */
bc226f07 3041 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3042 break;
774ead3a
AK		 3043 case KVM_CAP_VAPIC:
3044 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3045 break;
f725230a 3046 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3047 r = KVM_SOFT_MAX_VCPUS;
3048 break;
3049 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3050 r = KVM_MAX_VCPUS;
3051 break;
a988b910 3052 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 3053 r = KVM_USER_MEM_SLOTS;
a988b910 3054 break;
a68a6a72
MT		 3055 case KVM_CAP_PV_MMU: /* obsolete */
3056 r = 0;
2f333bcb 3057 break;
890ca9ae
HY		 3058 case KVM_CAP_MCE:
3059 r = KVM_MAX_MCE_BANKS;
3060 break;
2d5b5a66 3061 case KVM_CAP_XCRS:
d366bf7e 3062 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3063 break;
92a1f12d
JR		 3064 case KVM_CAP_TSC_CONTROL:
3065 r = kvm_has_tsc_control;
3066 break;
37131313
RK		 3067 case KVM_CAP_X2APIC_API:
3068 r = KVM_X2APIC_API_VALID_FLAGS;
3069 break;
8fcc4b59
JM		 3070 case KVM_CAP_NESTED_STATE:
3071 r = kvm_x86_ops->get_nested_state ?
3072 kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
3073 break;
018d00d2 3074 default:
018d00d2
ZX		 3075 break;
3076 }
3077 return r;
3078
3079}
3080
043405e1
CO		 3081long kvm_arch_dev_ioctl(struct file *filp,
3082 unsigned int ioctl, unsigned long arg)
3083{
3084 void __user *argp = (void __user *)arg;
3085 long r;
3086
3087 switch (ioctl) {
3088 case KVM_GET_MSR_INDEX_LIST: {
3089 struct kvm_msr_list __user *user_msr_list = argp;
3090 struct kvm_msr_list msr_list;
3091 unsigned n;
3092
3093 r = -EFAULT;
0e96f31e 3094 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3095 goto out;
3096 n = msr_list.nmsrs;
62ef68bb 3097 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3098 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3099 goto out;
3100 r = -E2BIG;
e125e7b6 3101 if (n < msr_list.nmsrs)
043405e1
CO		 3102 goto out;
3103 r = -EFAULT;
3104 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3105 num_msrs_to_save * sizeof(u32)))
3106 goto out;
e125e7b6 3107 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3108 &emulated_msrs,
62ef68bb 3109 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3110 goto out;
3111 r = 0;
3112 break;
3113 }
9c15bb1d
BP		 3114 case KVM_GET_SUPPORTED_CPUID:
3115 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3116 struct kvm_cpuid2 __user *cpuid_arg = argp;
3117 struct kvm_cpuid2 cpuid;
3118
3119 r = -EFAULT;
0e96f31e 3120 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3121 goto out;
9c15bb1d
BP		 3122
3123 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3124 ioctl);
674eea0f
AK		 3125 if (r)
3126 goto out;
3127
3128 r = -EFAULT;
0e96f31e 3129 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3130 goto out;
3131 r = 0;
3132 break;
3133 }
890ca9ae 3134 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3135 r = -EFAULT;
c45dcc71
AR		 3136 if (copy_to_user(argp, &kvm_mce_cap_supported,
3137 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3138 goto out;
3139 r = 0;
3140 break;
801e459a
TL		 3141 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3142 struct kvm_msr_list __user *user_msr_list = argp;
3143 struct kvm_msr_list msr_list;
3144 unsigned int n;
3145
3146 r = -EFAULT;
3147 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3148 goto out;
3149 n = msr_list.nmsrs;
3150 msr_list.nmsrs = num_msr_based_features;
3151 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3152 goto out;
3153 r = -E2BIG;
3154 if (n < msr_list.nmsrs)
3155 goto out;
3156 r = -EFAULT;
3157 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3158 num_msr_based_features * sizeof(u32)))
3159 goto out;
3160 r = 0;
3161 break;
3162 }
3163 case KVM_GET_MSRS:
3164 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3165 break;
890ca9ae 3166 }
043405e1
CO		 3167 default:
3168 r = -EINVAL;
3169 }
3170out:
3171 return r;
3172}
3173
f5f48ee1
SY		 3174static void wbinvd_ipi(void *garbage)
3175{
3176 wbinvd();
3177}
3178
3179static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3180{
e0f0bbc5 3181 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3182}
3183
313a3dc7
CO		 3184void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3185{
f5f48ee1
SY		 3186 /* Address WBINVD may be executed by guest */
3187 if (need_emulate_wbinvd(vcpu)) {
3188 if (kvm_x86_ops->has_wbinvd_exit())
3189 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3190 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3191 smp_call_function_single(vcpu->cpu,
3192 wbinvd_ipi, NULL, 1);
3193 }
3194
313a3dc7 3195 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3196
0dd6a6ed
ZA		 3197 /* Apply any externally detected TSC adjustments (due to suspend) */
3198 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3199 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3200 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3201 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3202 }
8f6055cb 3203
b0c39dc6 3204 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3205 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3206 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3207 if (tsc_delta < 0)
3208 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3209
b0c39dc6 3210 if (kvm_check_tsc_unstable()) {
07c1419a 3211 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3212 vcpu->arch.last_guest_tsc);
a545ab6a 3213 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3214 vcpu->arch.tsc_catchup = 1;
c285545f 3215 }
a749e247
PB		 3216
3217 if (kvm_lapic_hv_timer_in_use(vcpu))
3218 kvm_lapic_restart_hv_timer(vcpu);
3219
d98d07ca
MT		 3220 /*
3221 * On a host with synchronized TSC, there is no need to update
3222 * kvmclock on vcpu->cpu migration
3223 */
3224 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3225 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3226 if (vcpu->cpu != cpu)
1bd2009e 3227 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3228 vcpu->cpu = cpu;
6b7d7e76 3229 }
c9aaa895 3230
c9aaa895 3231 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3232}
3233
0b9f6c46
PX		 3234static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3235{
3236 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3237 return;
3238
fa55eedd 3239 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3240
4e335d9e 3241 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3242 &vcpu->arch.st.steal.preempted,
3243 offsetof(struct kvm_steal_time, preempted),
3244 sizeof(vcpu->arch.st.steal.preempted));
3245}
3246
313a3dc7
CO		 3247void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3248{
cc0d907c 3249 int idx;
de63ad4c
LM		 3250
3251 if (vcpu->preempted)
3252 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3253
931f261b
AA		 3254 /*
3255 * Disable page faults because we're in atomic context here.
3256 * kvm_write_guest_offset_cached() would call might_fault()
3257 * that relies on pagefault_disable() to tell if there's a
3258 * bug. NOTE: the write to guest memory may not go through if
3259 * during postcopy live migration or if there's heavy guest
3260 * paging.
3261 */
3262 pagefault_disable();
cc0d907c
AA		 3263 /*
3264 * kvm_memslots() will be called by
3265 * kvm_write_guest_offset_cached() so take the srcu lock.
3266 */
3267 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3268 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3269 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3270 pagefault_enable();
02daab21 3271 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3272 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3273 /*
f9dcf08e
RK		 3274 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3275 * on every vmexit, but if not, we might have a stale dr6 from the
3276 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3277 */
f9dcf08e 3278 set_debugreg(0, 6);
313a3dc7
CO		 3279}
3280
313a3dc7
CO		 3281static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3282 struct kvm_lapic_state *s)
3283{
fa59cc00 3284 if (vcpu->arch.apicv_active)
d62caabb
AS		 3285 kvm_x86_ops->sync_pir_to_irr(vcpu);
3286
a92e2543 3287 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3288}
3289
3290static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3291 struct kvm_lapic_state *s)
3292{
a92e2543
RK		 3293 int r;
3294
3295 r = kvm_apic_set_state(vcpu, s);
3296 if (r)
3297 return r;
cb142eb7 3298 update_cr8_intercept(vcpu);
313a3dc7
CO		 3299
3300 return 0;
3301}
3302
127a457a
MG		 3303static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3304{
3305 return (!lapic_in_kernel(vcpu) ||
3306 kvm_apic_accept_pic_intr(vcpu));
3307}
3308
782d422b
MG		 3309/*
3310 * if userspace requested an interrupt window, check that the
3311 * interrupt window is open.
3312 *
3313 * No need to exit to userspace if we already have an interrupt queued.
3314 */
3315static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3316{
3317 return kvm_arch_interrupt_allowed(vcpu) &&
3318 !kvm_cpu_has_interrupt(vcpu) &&
3319 !kvm_event_needs_reinjection(vcpu) &&
3320 kvm_cpu_accept_dm_intr(vcpu);
3321}
3322
f77bc6a4
ZX		 3323static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3324 struct kvm_interrupt *irq)
3325{
02cdb50f 3326 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3327 return -EINVAL;
1c1a9ce9
SR		 3328
3329 if (!irqchip_in_kernel(vcpu->kvm)) {
3330 kvm_queue_interrupt(vcpu, irq->irq, false);
3331 kvm_make_request(KVM_REQ_EVENT, vcpu);
3332 return 0;
3333 }
3334
3335 /*
3336 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3337 * fail for in-kernel 8259.
3338 */
3339 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3340 return -ENXIO;
f77bc6a4 3341
1c1a9ce9
SR		 3342 if (vcpu->arch.pending_external_vector != -1)
3343 return -EEXIST;
f77bc6a4 3344
1c1a9ce9 3345 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3346 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3347 return 0;
3348}
3349
c4abb7c9
JK		 3350static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3351{
c4abb7c9 3352 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3353
3354 return 0;
3355}
3356
f077825a
PB		 3357static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3358{
64d60670
PB		 3359 kvm_make_request(KVM_REQ_SMI, vcpu);
3360
f077825a
PB		 3361 return 0;
3362}
3363
b209749f
AK		 3364static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3365 struct kvm_tpr_access_ctl *tac)
3366{
3367 if (tac->flags)
3368 return -EINVAL;
3369 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3370 return 0;
3371}
3372
890ca9ae
HY		 3373static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3374 u64 mcg_cap)
3375{
3376 int r;
3377 unsigned bank_num = mcg_cap & 0xff, bank;
3378
3379 r = -EINVAL;
a9e38c3e 3380 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3381 goto out;
c45dcc71 3382 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3383 goto out;
3384 r = 0;
3385 vcpu->arch.mcg_cap = mcg_cap;
3386 /* Init IA32_MCG_CTL to all 1s */
3387 if (mcg_cap & MCG_CTL_P)
3388 vcpu->arch.mcg_ctl = ~(u64)0;
3389 /* Init IA32_MCi_CTL to all 1s */
3390 for (bank = 0; bank < bank_num; bank++)
3391 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3392
3393 if (kvm_x86_ops->setup_mce)
3394 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3395out:
3396 return r;
3397}
3398
3399static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3400 struct kvm_x86_mce *mce)
3401{
3402 u64 mcg_cap = vcpu->arch.mcg_cap;
3403 unsigned bank_num = mcg_cap & 0xff;
3404 u64 *banks = vcpu->arch.mce_banks;
3405
3406 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3407 return -EINVAL;
3408 /*
3409 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3410 * reporting is disabled
3411 */
3412 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3413 vcpu->arch.mcg_ctl != ~(u64)0)
3414 return 0;
3415 banks += 4 * mce->bank;
3416 /*
3417 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3418 * reporting is disabled for the bank
3419 */
3420 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3421 return 0;
3422 if (mce->status & MCI_STATUS_UC) {
3423 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3424 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3425 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3426 return 0;
3427 }
3428 if (banks[1] & MCI_STATUS_VAL)
3429 mce->status |= MCI_STATUS_OVER;
3430 banks[2] = mce->addr;
3431 banks[3] = mce->misc;
3432 vcpu->arch.mcg_status = mce->mcg_status;
3433 banks[1] = mce->status;
3434 kvm_queue_exception(vcpu, MC_VECTOR);
3435 } else if (!(banks[1] & MCI_STATUS_VAL)
3436 || !(banks[1] & MCI_STATUS_UC)) {
3437 if (banks[1] & MCI_STATUS_VAL)
3438 mce->status |= MCI_STATUS_OVER;
3439 banks[2] = mce->addr;
3440 banks[3] = mce->misc;
3441 banks[1] = mce->status;
3442 } else
3443 banks[1] |= MCI_STATUS_OVER;
3444 return 0;
3445}
3446
3cfc3092
JK		 3447static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3448 struct kvm_vcpu_events *events)
3449{
7460fb4a 3450 process_nmi(vcpu);
59073aaf 3451
664f8e26 3452 /*
59073aaf
JM		 3453 * The API doesn't provide the instruction length for software
3454 * exceptions, so don't report them. As long as the guest RIP
3455 * isn't advanced, we should expect to encounter the exception
3456 * again.
664f8e26 3457 */
59073aaf
JM		 3458 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3459 events->exception.injected = 0;
3460 events->exception.pending = 0;
3461 } else {
3462 events->exception.injected = vcpu->arch.exception.injected;
3463 events->exception.pending = vcpu->arch.exception.pending;
3464 /*
3465 * For ABI compatibility, deliberately conflate
3466 * pending and injected exceptions when
3467 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3468 */
3469 if (!vcpu->kvm->arch.exception_payload_enabled)
3470 events->exception.injected |=
3471 vcpu->arch.exception.pending;
3472 }
3cfc3092
JK		 3473 events->exception.nr = vcpu->arch.exception.nr;
3474 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3475 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3476 events->exception_has_payload = vcpu->arch.exception.has_payload;
3477 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3478
03b82a30 3479 events->interrupt.injected =
04140b41 3480 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3481 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3482 events->interrupt.soft = 0;
37ccdcbe 3483 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3484
3485 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3486 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3487 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3488 events->nmi.pad = 0;
3cfc3092 3489
66450a21 3490 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3491
f077825a
PB		 3492 events->smi.smm = is_smm(vcpu);
3493 events->smi.pending = vcpu->arch.smi_pending;
3494 events->smi.smm_inside_nmi =
3495 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3496 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3497
dab4b911 3498 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3499 | KVM_VCPUEVENT_VALID_SHADOW
3500 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3501 if (vcpu->kvm->arch.exception_payload_enabled)
3502 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3503
97e69aa6 3504 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3505}
3506
6ef4e07e
XG		 3507static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3508
3cfc3092
JK		 3509static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3510 struct kvm_vcpu_events *events)
3511{
dab4b911 3512 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3513 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3514 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3515 | KVM_VCPUEVENT_VALID_SMM
3516 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3517 return -EINVAL;
3518
59073aaf
JM		 3519 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3520 if (!vcpu->kvm->arch.exception_payload_enabled)
3521 return -EINVAL;
3522 if (events->exception.pending)
3523 events->exception.injected = 0;
3524 else
3525 events->exception_has_payload = 0;
3526 } else {
3527 events->exception.pending = 0;
3528 events->exception_has_payload = 0;
3529 }
3530
3531 if ((events->exception.injected || events->exception.pending) &&
3532 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3533 return -EINVAL;
3534
28bf2888
DH		 3535 /* INITs are latched while in SMM */
3536 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3537 (events->smi.smm || events->smi.pending) &&
3538 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3539 return -EINVAL;
3540
7460fb4a 3541 process_nmi(vcpu);
59073aaf
JM		 3542 vcpu->arch.exception.injected = events->exception.injected;
3543 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3544 vcpu->arch.exception.nr = events->exception.nr;
3545 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3546 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3547 vcpu->arch.exception.has_payload = events->exception_has_payload;
3548 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3549
04140b41 3550 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3551 vcpu->arch.interrupt.nr = events->interrupt.nr;
3552 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3553 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3554 kvm_x86_ops->set_interrupt_shadow(vcpu,
3555 events->interrupt.shadow);
3cfc3092
JK		 3556
3557 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3558 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3559 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3560 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3561
66450a21 3562 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3563 lapic_in_kernel(vcpu))
66450a21 3564 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3565
f077825a 3566 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3567 u32 hflags = vcpu->arch.hflags;
f077825a 3568 if (events->smi.smm)
6ef4e07e 3569 hflags |= HF_SMM_MASK;
f077825a 3570 else
6ef4e07e
XG		 3571 hflags &= ~HF_SMM_MASK;
3572 kvm_set_hflags(vcpu, hflags);
3573
f077825a 3574 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3575
3576 if (events->smi.smm) {
3577 if (events->smi.smm_inside_nmi)
3578 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3579 else
f4ef1910
WL		 3580 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3581 if (lapic_in_kernel(vcpu)) {
3582 if (events->smi.latched_init)
3583 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3584 else
3585 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3586 }
f077825a
PB		 3587 }
3588 }
3589
3842d135
AK		 3590 kvm_make_request(KVM_REQ_EVENT, vcpu);
3591
3cfc3092
JK		 3592 return 0;
3593}
3594
a1efbe77
JK		 3595static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3596 struct kvm_debugregs *dbgregs)
3597{
73aaf249
JK		 3598 unsigned long val;
3599
a1efbe77 3600 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3601 kvm_get_dr(vcpu, 6, &val);
73aaf249 3602 dbgregs->dr6 = val;
a1efbe77
JK		 3603 dbgregs->dr7 = vcpu->arch.dr7;
3604 dbgregs->flags = 0;
97e69aa6 3605 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3606}
3607
3608static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3609 struct kvm_debugregs *dbgregs)
3610{
3611 if (dbgregs->flags)
3612 return -EINVAL;
3613
d14bdb55
PB		 3614 if (dbgregs->dr6 & ~0xffffffffull)
3615 return -EINVAL;
3616 if (dbgregs->dr7 & ~0xffffffffull)
3617 return -EINVAL;
3618
a1efbe77 3619 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3620 kvm_update_dr0123(vcpu);
a1efbe77 3621 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3622 kvm_update_dr6(vcpu);
a1efbe77 3623 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3624 kvm_update_dr7(vcpu);
a1efbe77 3625
a1efbe77
JK		 3626 return 0;
3627}
3628
df1daba7
PB		 3629#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3630
3631static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3632{
c47ada30 3633 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3634 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3635 u64 valid;
3636
3637 /*
3638 * Copy legacy XSAVE area, to avoid complications with CPUID
3639 * leaves 0 and 1 in the loop below.
3640 */
3641 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3642
3643 /* Set XSTATE_BV */
00c87e9a 3644 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3645 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3646
3647 /*
3648 * Copy each region from the possibly compacted offset to the
3649 * non-compacted offset.
3650 */
d91cab78 3651 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3652 while (valid) {
3653 u64 feature = valid & -valid;
3654 int index = fls64(feature) - 1;
3655 void *src = get_xsave_addr(xsave, feature);
3656
3657 if (src) {
3658 u32 size, offset, ecx, edx;
3659 cpuid_count(XSTATE_CPUID, index,
3660 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3661 if (feature == XFEATURE_MASK_PKRU)
3662 memcpy(dest + offset, &vcpu->arch.pkru,
3663 sizeof(vcpu->arch.pkru));
3664 else
3665 memcpy(dest + offset, src, size);
3666
df1daba7
PB		 3667 }
3668
3669 valid -= feature;
3670 }
3671}
3672
3673static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3674{
c47ada30 3675 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3676 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3677 u64 valid;
3678
3679 /*
3680 * Copy legacy XSAVE area, to avoid complications with CPUID
3681 * leaves 0 and 1 in the loop below.
3682 */
3683 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3684
3685 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3686 xsave->header.xfeatures = xstate_bv;
782511b0 3687 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3688 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3689
3690 /*
3691 * Copy each region from the non-compacted offset to the
3692 * possibly compacted offset.
3693 */
d91cab78 3694 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3695 while (valid) {
3696 u64 feature = valid & -valid;
3697 int index = fls64(feature) - 1;
3698 void *dest = get_xsave_addr(xsave, feature);
3699
3700 if (dest) {
3701 u32 size, offset, ecx, edx;
3702 cpuid_count(XSTATE_CPUID, index,
3703 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3704 if (feature == XFEATURE_MASK_PKRU)
3705 memcpy(&vcpu->arch.pkru, src + offset,
3706 sizeof(vcpu->arch.pkru));
3707 else
3708 memcpy(dest, src + offset, size);
ee4100da 3709 }
df1daba7
PB		 3710
3711 valid -= feature;
3712 }
3713}
3714
2d5b5a66
SY		 3715static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3716 struct kvm_xsave *guest_xsave)
3717{
d366bf7e 3718 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3719 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3720 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3721 } else {
2d5b5a66 3722 memcpy(guest_xsave->region,
7366ed77 3723 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3724 sizeof(struct fxregs_state));
2d5b5a66 3725 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3726 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3727 }
3728}
3729
a575813b
WL		 3730#define XSAVE_MXCSR_OFFSET 24
3731
2d5b5a66
SY		 3732static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3733 struct kvm_xsave *guest_xsave)
3734{
3735 u64 xstate_bv =
3736 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3737 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3738
d366bf7e 3739 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3740 /*
3741 * Here we allow setting states that are not present in
3742 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3743 * with old userspace.
3744 */
a575813b
WL		 3745 if (xstate_bv & ~kvm_supported_xcr0() ||
3746 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3747 return -EINVAL;
df1daba7 3748 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3749 } else {
a575813b
WL		 3750 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3751 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3752 return -EINVAL;
7366ed77 3753 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3754 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3755 }
3756 return 0;
3757}
3758
3759static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3760 struct kvm_xcrs *guest_xcrs)
3761{
d366bf7e 3762 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3763 guest_xcrs->nr_xcrs = 0;
3764 return;
3765 }
3766
3767 guest_xcrs->nr_xcrs = 1;
3768 guest_xcrs->flags = 0;
3769 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3770 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3771}
3772
3773static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3774 struct kvm_xcrs *guest_xcrs)
3775{
3776 int i, r = 0;
3777
d366bf7e 3778 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3779 return -EINVAL;
3780
3781 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3782 return -EINVAL;
3783
3784 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3785 /* Only support XCR0 currently */
c67a04cb 3786 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3787 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3788 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3789 break;
3790 }
3791 if (r)
3792 r = -EINVAL;
3793 return r;
3794}
3795
1c0b28c2
EM		 3796/*
3797 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3798 * stopped by the hypervisor. This function will be called from the host only.
3799 * EINVAL is returned when the host attempts to set the flag for a guest that
3800 * does not support pv clocks.
3801 */
3802static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3803{
0b79459b 3804 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3805 return -EINVAL;
51d59c6b 3806 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3807 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3808 return 0;
3809}
3810
5c919412
AS		 3811static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3812 struct kvm_enable_cap *cap)
3813{
57b119da
VK		 3814 int r;
3815 uint16_t vmcs_version;
3816 void __user *user_ptr;
3817
5c919412
AS		 3818 if (cap->flags)
3819 return -EINVAL;
3820
3821 switch (cap->cap) {
efc479e6
RK		 3822 case KVM_CAP_HYPERV_SYNIC2:
3823 if (cap->args[0])
3824 return -EINVAL;
5c919412 3825 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3826 if (!irqchip_in_kernel(vcpu->kvm))
3827 return -EINVAL;
efc479e6
RK		 3828 return kvm_hv_activate_synic(vcpu, cap->cap ==
3829 KVM_CAP_HYPERV_SYNIC2);
57b119da 3830 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 3831 if (!kvm_x86_ops->nested_enable_evmcs)
3832 return -ENOTTY;
57b119da
VK		 3833 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3834 if (!r) {
3835 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3836 if (copy_to_user(user_ptr, &vmcs_version,
3837 sizeof(vmcs_version)))
3838 r = -EFAULT;
3839 }
3840 return r;
3841
5c919412
AS		 3842 default:
3843 return -EINVAL;
3844 }
3845}
3846
313a3dc7
CO		 3847long kvm_arch_vcpu_ioctl(struct file *filp,
3848 unsigned int ioctl, unsigned long arg)
3849{
3850 struct kvm_vcpu *vcpu = filp->private_data;
3851 void __user *argp = (void __user *)arg;
3852 int r;
d1ac91d8
AK		 3853 union {
3854 struct kvm_lapic_state *lapic;
3855 struct kvm_xsave *xsave;
3856 struct kvm_xcrs *xcrs;
3857 void *buffer;
3858 } u;
3859
9b062471
CD		 3860 vcpu_load(vcpu);
3861
d1ac91d8 3862 u.buffer = NULL;
313a3dc7
CO		 3863 switch (ioctl) {
3864 case KVM_GET_LAPIC: {
2204ae3c 3865 r = -EINVAL;
bce87cce 3866 if (!lapic_in_kernel(vcpu))
2204ae3c 3867 goto out;
d1ac91d8 3868 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3869
b772ff36 3870 r = -ENOMEM;
d1ac91d8 3871 if (!u.lapic)
b772ff36 3872 goto out;
d1ac91d8 3873 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3874 if (r)
3875 goto out;
3876 r = -EFAULT;
d1ac91d8 3877 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3878 goto out;
3879 r = 0;
3880 break;
3881 }
3882 case KVM_SET_LAPIC: {
2204ae3c 3883 r = -EINVAL;
bce87cce 3884 if (!lapic_in_kernel(vcpu))
2204ae3c 3885 goto out;
ff5c2c03 3886 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3887 if (IS_ERR(u.lapic)) {
3888 r = PTR_ERR(u.lapic);
3889 goto out_nofree;
3890 }
ff5c2c03 3891
d1ac91d8 3892 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3893 break;
3894 }
f77bc6a4
ZX		 3895 case KVM_INTERRUPT: {
3896 struct kvm_interrupt irq;
3897
3898 r = -EFAULT;
0e96f31e 3899 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 3900 goto out;
3901 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3902 break;
3903 }
c4abb7c9
JK		 3904 case KVM_NMI: {
3905 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3906 break;
3907 }
f077825a
PB		 3908 case KVM_SMI: {
3909 r = kvm_vcpu_ioctl_smi(vcpu);
3910 break;
3911 }
313a3dc7
CO		 3912 case KVM_SET_CPUID: {
3913 struct kvm_cpuid __user *cpuid_arg = argp;
3914 struct kvm_cpuid cpuid;
3915
3916 r = -EFAULT;
0e96f31e 3917 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 3918 goto out;
3919 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3920 break;
3921 }
07716717
DK		 3922 case KVM_SET_CPUID2: {
3923 struct kvm_cpuid2 __user *cpuid_arg = argp;
3924 struct kvm_cpuid2 cpuid;
3925
3926 r = -EFAULT;
0e96f31e 3927 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 3928 goto out;
3929 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3930 cpuid_arg->entries);
07716717
DK		 3931 break;
3932 }
3933 case KVM_GET_CPUID2: {
3934 struct kvm_cpuid2 __user *cpuid_arg = argp;
3935 struct kvm_cpuid2 cpuid;
3936
3937 r = -EFAULT;
0e96f31e 3938 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 3939 goto out;
3940 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3941 cpuid_arg->entries);
07716717
DK		 3942 if (r)
3943 goto out;
3944 r = -EFAULT;
0e96f31e 3945 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 3946 goto out;
3947 r = 0;
3948 break;
3949 }
801e459a
TL		 3950 case KVM_GET_MSRS: {
3951 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3952 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3953 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3954 break;
801e459a
TL		 3955 }
3956 case KVM_SET_MSRS: {
3957 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3958 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3959 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3960 break;
801e459a 3961 }
b209749f
AK		 3962 case KVM_TPR_ACCESS_REPORTING: {
3963 struct kvm_tpr_access_ctl tac;
3964
3965 r = -EFAULT;
0e96f31e 3966 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 3967 goto out;
3968 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3969 if (r)
3970 goto out;
3971 r = -EFAULT;
0e96f31e 3972 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 3973 goto out;
3974 r = 0;
3975 break;
3976 };
b93463aa
AK		 3977 case KVM_SET_VAPIC_ADDR: {
3978 struct kvm_vapic_addr va;
7301d6ab 3979 int idx;
b93463aa
AK		 3980
3981 r = -EINVAL;
35754c98 3982 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3983 goto out;
3984 r = -EFAULT;
0e96f31e 3985 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 3986 goto out;
7301d6ab 3987 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3988 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3989 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3990 break;
3991 }
890ca9ae
HY		 3992 case KVM_X86_SETUP_MCE: {
3993 u64 mcg_cap;
3994
3995 r = -EFAULT;
0e96f31e 3996 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 3997 goto out;
3998 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3999 break;
4000 }
4001 case KVM_X86_SET_MCE: {
4002 struct kvm_x86_mce mce;
4003
4004 r = -EFAULT;
0e96f31e 4005 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4006 goto out;
4007 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4008 break;
4009 }
3cfc3092
JK		 4010 case KVM_GET_VCPU_EVENTS: {
4011 struct kvm_vcpu_events events;
4012
4013 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4014
4015 r = -EFAULT;
4016 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4017 break;
4018 r = 0;
4019 break;
4020 }
4021 case KVM_SET_VCPU_EVENTS: {
4022 struct kvm_vcpu_events events;
4023
4024 r = -EFAULT;
4025 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4026 break;
4027
4028 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4029 break;
4030 }
a1efbe77
JK		 4031 case KVM_GET_DEBUGREGS: {
4032 struct kvm_debugregs dbgregs;
4033
4034 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4035
4036 r = -EFAULT;
4037 if (copy_to_user(argp, &dbgregs,
4038 sizeof(struct kvm_debugregs)))
4039 break;
4040 r = 0;
4041 break;
4042 }
4043 case KVM_SET_DEBUGREGS: {
4044 struct kvm_debugregs dbgregs;
4045
4046 r = -EFAULT;
4047 if (copy_from_user(&dbgregs, argp,
4048 sizeof(struct kvm_debugregs)))
4049 break;
4050
4051 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4052 break;
4053 }
2d5b5a66 4054 case KVM_GET_XSAVE: {
d1ac91d8 4055 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 4056 r = -ENOMEM;
d1ac91d8 4057 if (!u.xsave)
2d5b5a66
SY		 4058 break;
4059
d1ac91d8 4060 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4061
4062 r = -EFAULT;
d1ac91d8 4063 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4064 break;
4065 r = 0;
4066 break;
4067 }
4068 case KVM_SET_XSAVE: {
ff5c2c03 4069 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4070 if (IS_ERR(u.xsave)) {
4071 r = PTR_ERR(u.xsave);
4072 goto out_nofree;
4073 }
2d5b5a66 4074
d1ac91d8 4075 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4076 break;
4077 }
4078 case KVM_GET_XCRS: {
d1ac91d8 4079 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 4080 r = -ENOMEM;
d1ac91d8 4081 if (!u.xcrs)
2d5b5a66
SY		 4082 break;
4083
d1ac91d8 4084 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4085
4086 r = -EFAULT;
d1ac91d8 4087 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4088 sizeof(struct kvm_xcrs)))
4089 break;
4090 r = 0;
4091 break;
4092 }
4093 case KVM_SET_XCRS: {
ff5c2c03 4094 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4095 if (IS_ERR(u.xcrs)) {
4096 r = PTR_ERR(u.xcrs);
4097 goto out_nofree;
4098 }
2d5b5a66 4099
d1ac91d8 4100 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4101 break;
4102 }
92a1f12d
JR		 4103 case KVM_SET_TSC_KHZ: {
4104 u32 user_tsc_khz;
4105
4106 r = -EINVAL;
92a1f12d
JR		 4107 user_tsc_khz = (u32)arg;
4108
4109 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4110 goto out;
4111
cc578287
ZA		 4112 if (user_tsc_khz == 0)
4113 user_tsc_khz = tsc_khz;
4114
381d585c
HZ		 4115 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4116 r = 0;
92a1f12d 4117
92a1f12d
JR		 4118 goto out;
4119 }
4120 case KVM_GET_TSC_KHZ: {
cc578287 4121 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4122 goto out;
4123 }
1c0b28c2
EM		 4124 case KVM_KVMCLOCK_CTRL: {
4125 r = kvm_set_guest_paused(vcpu);
4126 goto out;
4127 }
5c919412
AS		 4128 case KVM_ENABLE_CAP: {
4129 struct kvm_enable_cap cap;
4130
4131 r = -EFAULT;
4132 if (copy_from_user(&cap, argp, sizeof(cap)))
4133 goto out;
4134 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4135 break;
4136 }
8fcc4b59
JM		 4137 case KVM_GET_NESTED_STATE: {
4138 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4139 u32 user_data_size;
4140
4141 r = -EINVAL;
4142 if (!kvm_x86_ops->get_nested_state)
4143 break;
4144
4145 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4146 r = -EFAULT;
8fcc4b59 4147 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4148 break;
8fcc4b59
JM		 4149
4150 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4151 user_data_size);
4152 if (r < 0)
26b471c7 4153 break;
8fcc4b59
JM		 4154
4155 if (r > user_data_size) {
4156 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4157 r = -EFAULT;
4158 else
4159 r = -E2BIG;
4160 break;
8fcc4b59 4161 }
26b471c7 4162
8fcc4b59
JM		 4163 r = 0;
4164 break;
4165 }
4166 case KVM_SET_NESTED_STATE: {
4167 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4168 struct kvm_nested_state kvm_state;
4169
4170 r = -EINVAL;
4171 if (!kvm_x86_ops->set_nested_state)
4172 break;
4173
26b471c7 4174 r = -EFAULT;
8fcc4b59 4175 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4176 break;
8fcc4b59 4177
26b471c7 4178 r = -EINVAL;
8fcc4b59 4179 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4180 break;
8fcc4b59
JM		 4181
4182 if (kvm_state.flags &
8cab6507
VK		 4183 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4184 | KVM_STATE_NESTED_EVMCS))
26b471c7 4185 break;
8fcc4b59
JM		 4186
4187 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4188 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4189 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4190 break;
8fcc4b59
JM		 4191
4192 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4193 break;
4194 }
2bc39970
VK		 4195 case KVM_GET_SUPPORTED_HV_CPUID: {
4196 struct kvm_cpuid2 __user *cpuid_arg = argp;
4197 struct kvm_cpuid2 cpuid;
4198
4199 r = -EFAULT;
4200 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4201 goto out;
4202
4203 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4204 cpuid_arg->entries);
4205 if (r)
4206 goto out;
4207
4208 r = -EFAULT;
4209 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4210 goto out;
4211 r = 0;
4212 break;
4213 }
313a3dc7
CO		 4214 default:
4215 r = -EINVAL;
4216 }
4217out:
d1ac91d8 4218 kfree(u.buffer);
9b062471
CD		 4219out_nofree:
4220 vcpu_put(vcpu);
313a3dc7
CO		 4221 return r;
4222}
4223
1499fa80 4224vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4225{
4226 return VM_FAULT_SIGBUS;
4227}
4228
1fe779f8
CO		 4229static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4230{
4231 int ret;
4232
4233 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4234 return -EINVAL;
1fe779f8
CO		 4235 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4236 return ret;
4237}
4238
b927a3ce
SY		 4239static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4240 u64 ident_addr)
4241{
2ac52ab8 4242 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4243}
4244
1fe779f8
CO		 4245static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4246 u32 kvm_nr_mmu_pages)
4247{
4248 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4249 return -EINVAL;
4250
79fac95e 4251 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4252
4253 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4254 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4255
79fac95e 4256 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4257 return 0;
4258}
4259
4260static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4261{
39de71ec 4262 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4263}
4264
1fe779f8
CO		 4265static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4266{
90bca052 4267 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4268 int r;
4269
4270 r = 0;
4271 switch (chip->chip_id) {
4272 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4273 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4274 sizeof(struct kvm_pic_state));
4275 break;
4276 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4277 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4278 sizeof(struct kvm_pic_state));
4279 break;
4280 case KVM_IRQCHIP_IOAPIC:
33392b49 4281 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4282 break;
4283 default:
4284 r = -EINVAL;
4285 break;
4286 }
4287 return r;
4288}
4289
4290static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4291{
90bca052 4292 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4293 int r;
4294
4295 r = 0;
4296 switch (chip->chip_id) {
4297 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4298 spin_lock(&pic->lock);
4299 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4300 sizeof(struct kvm_pic_state));
90bca052 4301 spin_unlock(&pic->lock);
1fe779f8
CO		 4302 break;
4303 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4304 spin_lock(&pic->lock);
4305 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4306 sizeof(struct kvm_pic_state));
90bca052 4307 spin_unlock(&pic->lock);
1fe779f8
CO		 4308 break;
4309 case KVM_IRQCHIP_IOAPIC:
33392b49 4310 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4311 break;
4312 default:
4313 r = -EINVAL;
4314 break;
4315 }
90bca052 4316 kvm_pic_update_irq(pic);
1fe779f8
CO		 4317 return r;
4318}
4319
e0f63cb9
SY		 4320static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4321{
34f3941c
RK		 4322 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4323
4324 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4325
4326 mutex_lock(&kps->lock);
4327 memcpy(ps, &kps->channels, sizeof(*ps));
4328 mutex_unlock(&kps->lock);
2da29bcc 4329 return 0;
e0f63cb9
SY		 4330}
4331
4332static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4333{
0185604c 4334 int i;
09edea72
RK		 4335 struct kvm_pit *pit = kvm->arch.vpit;
4336
4337 mutex_lock(&pit->pit_state.lock);
34f3941c 4338 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4339 for (i = 0; i < 3; i++)
09edea72
RK		 4340 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4341 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4342 return 0;
e9f42757
BK		 4343}
4344
4345static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4346{
e9f42757
BK		 4347 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4348 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4349 sizeof(ps->channels));
4350 ps->flags = kvm->arch.vpit->pit_state.flags;
4351 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4352 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4353 return 0;
e9f42757
BK		 4354}
4355
4356static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4357{
2da29bcc 4358 int start = 0;
0185604c 4359 int i;
e9f42757 4360 u32 prev_legacy, cur_legacy;
09edea72
RK		 4361 struct kvm_pit *pit = kvm->arch.vpit;
4362
4363 mutex_lock(&pit->pit_state.lock);
4364 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4365 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4366 if (!prev_legacy && cur_legacy)
4367 start = 1;
09edea72
RK		 4368 memcpy(&pit->pit_state.channels, &ps->channels,
4369 sizeof(pit->pit_state.channels));
4370 pit->pit_state.flags = ps->flags;
0185604c 4371 for (i = 0; i < 3; i++)
09edea72 4372 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4373 start && i == 0);
09edea72 4374 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4375 return 0;
e0f63cb9
SY		 4376}
4377
52d939a0
MT		 4378static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4379 struct kvm_reinject_control *control)
4380{
71474e2f
RK		 4381 struct kvm_pit *pit = kvm->arch.vpit;
4382
4383 if (!pit)
52d939a0 4384 return -ENXIO;
b39c90b6 4385
71474e2f
RK		 4386 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4387 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4388 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4389 */
4390 mutex_lock(&pit->pit_state.lock);
4391 kvm_pit_set_reinject(pit, control->pit_reinject);
4392 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4393
52d939a0
MT		 4394 return 0;
4395}
4396
95d4c16c 4397/**
60c34612
TY		 4398 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4399 * @kvm: kvm instance
4400 * @log: slot id and address to which we copy the log
95d4c16c 4401 *
e108ff2f
PB		 4402 * Steps 1-4 below provide general overview of dirty page logging. See
4403 * kvm_get_dirty_log_protect() function description for additional details.
4404 *
4405 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4406 * always flush the TLB (step 4) even if previous step failed and the dirty
4407 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4408 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4409 * writes will be marked dirty for next log read.
95d4c16c 4410 *
60c34612
TY		 4411 * 1. Take a snapshot of the bit and clear it if needed.
4412 * 2. Write protect the corresponding page.
e108ff2f
PB		 4413 * 3. Copy the snapshot to the userspace.
4414 * 4. Flush TLB's if needed.
5bb064dc 4415 */
60c34612 4416int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4417{
8fe65a82 4418 bool flush = false;
e108ff2f 4419 int r;
5bb064dc 4420
79fac95e 4421 mutex_lock(&kvm->slots_lock);
5bb064dc 4422
88178fd4
KH		 4423 /*
4424 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4425 */
4426 if (kvm_x86_ops->flush_log_dirty)
4427 kvm_x86_ops->flush_log_dirty(kvm);
4428
8fe65a82 4429 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4430
4431 /*
4432 * All the TLBs can be flushed out of mmu lock, see the comments in
4433 * kvm_mmu_slot_remove_write_access().
4434 */
e108ff2f 4435 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4436 if (flush)
2a31b9db
PB		 4437 kvm_flush_remote_tlbs(kvm);
4438
4439 mutex_unlock(&kvm->slots_lock);
4440 return r;
4441}
4442
4443int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4444{
4445 bool flush = false;
4446 int r;
4447
4448 mutex_lock(&kvm->slots_lock);
4449
4450 /*
4451 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4452 */
4453 if (kvm_x86_ops->flush_log_dirty)
4454 kvm_x86_ops->flush_log_dirty(kvm);
4455
4456 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4457
4458 /*
4459 * All the TLBs can be flushed out of mmu lock, see the comments in
4460 * kvm_mmu_slot_remove_write_access().
4461 */
4462 lockdep_assert_held(&kvm->slots_lock);
4463 if (flush)
198c74f4
XG		 4464 kvm_flush_remote_tlbs(kvm);
4465
79fac95e 4466 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4467 return r;
4468}
4469
aa2fbe6d
YZ		 4470int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4471 bool line_status)
23d43cf9
CD		 4472{
4473 if (!irqchip_in_kernel(kvm))
4474 return -ENXIO;
4475
4476 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4477 irq_event->irq, irq_event->level,
4478 line_status);
23d43cf9
CD		 4479 return 0;
4480}
4481
e5d83c74
PB		 4482int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4483 struct kvm_enable_cap *cap)
90de4a18
NA		 4484{
4485 int r;
4486
4487 if (cap->flags)
4488 return -EINVAL;
4489
4490 switch (cap->cap) {
4491 case KVM_CAP_DISABLE_QUIRKS:
4492 kvm->arch.disabled_quirks = cap->args[0];
4493 r = 0;
4494 break;
49df6397
SR		 4495 case KVM_CAP_SPLIT_IRQCHIP: {
4496 mutex_lock(&kvm->lock);
b053b2ae
SR		 4497 r = -EINVAL;
4498 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4499 goto split_irqchip_unlock;
49df6397
SR		 4500 r = -EEXIST;
4501 if (irqchip_in_kernel(kvm))
4502 goto split_irqchip_unlock;
557abc40 4503 if (kvm->created_vcpus)
49df6397
SR		 4504 goto split_irqchip_unlock;
4505 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4506 if (r)
49df6397
SR		 4507 goto split_irqchip_unlock;
4508 /* Pairs with irqchip_in_kernel. */
4509 smp_wmb();
49776faf 4510 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4511 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4512 r = 0;
4513split_irqchip_unlock:
4514 mutex_unlock(&kvm->lock);
4515 break;
4516 }
37131313
RK		 4517 case KVM_CAP_X2APIC_API:
4518 r = -EINVAL;
4519 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4520 break;
4521
4522 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4523 kvm->arch.x2apic_format = true;
c519265f
RK		 4524 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4525 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4526
4527 r = 0;
4528 break;
4d5422ce
WL		 4529 case KVM_CAP_X86_DISABLE_EXITS:
4530 r = -EINVAL;
4531 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4532 break;
4533
4534 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4535 kvm_can_mwait_in_guest())
4536 kvm->arch.mwait_in_guest = true;
766d3571 4537 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4538 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4539 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4540 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4541 r = 0;
4542 break;
6fbbde9a
DS		 4543 case KVM_CAP_MSR_PLATFORM_INFO:
4544 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4545 r = 0;
c4f55198
JM		 4546 break;
4547 case KVM_CAP_EXCEPTION_PAYLOAD:
4548 kvm->arch.exception_payload_enabled = cap->args[0];
4549 r = 0;
6fbbde9a 4550 break;
90de4a18
NA		 4551 default:
4552 r = -EINVAL;
4553 break;
4554 }
4555 return r;
4556}
4557
1fe779f8
CO		 4558long kvm_arch_vm_ioctl(struct file *filp,
4559 unsigned int ioctl, unsigned long arg)
4560{
4561 struct kvm *kvm = filp->private_data;
4562 void __user *argp = (void __user *)arg;
367e1319 4563 int r = -ENOTTY;
f0d66275
DH		 4564 /*
4565 * This union makes it completely explicit to gcc-3.x
4566 * that these two variables' stack usage should be
4567 * combined, not added together.
4568 */
4569 union {
4570 struct kvm_pit_state ps;
e9f42757 4571 struct kvm_pit_state2 ps2;
c5ff41ce 4572 struct kvm_pit_config pit_config;
f0d66275 4573 } u;
1fe779f8
CO		 4574
4575 switch (ioctl) {
4576 case KVM_SET_TSS_ADDR:
4577 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4578 break;
b927a3ce
SY		 4579 case KVM_SET_IDENTITY_MAP_ADDR: {
4580 u64 ident_addr;
4581
1af1ac91
DH		 4582 mutex_lock(&kvm->lock);
4583 r = -EINVAL;
4584 if (kvm->created_vcpus)
4585 goto set_identity_unlock;
b927a3ce 4586 r = -EFAULT;
0e96f31e 4587 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4588 goto set_identity_unlock;
b927a3ce 4589 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4590set_identity_unlock:
4591 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4592 break;
4593 }
1fe779f8
CO		 4594 case KVM_SET_NR_MMU_PAGES:
4595 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4596 break;
4597 case KVM_GET_NR_MMU_PAGES:
4598 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4599 break;
3ddea128 4600 case KVM_CREATE_IRQCHIP: {
3ddea128 4601 mutex_lock(&kvm->lock);
09941366 4602
3ddea128 4603 r = -EEXIST;
35e6eaa3 4604 if (irqchip_in_kernel(kvm))
3ddea128 4605 goto create_irqchip_unlock;
09941366 4606
3e515705 4607 r = -EINVAL;
557abc40 4608 if (kvm->created_vcpus)
3e515705 4609 goto create_irqchip_unlock;
09941366
RK		 4610
4611 r = kvm_pic_init(kvm);
4612 if (r)
3ddea128 4613 goto create_irqchip_unlock;
09941366
RK		 4614
4615 r = kvm_ioapic_init(kvm);
4616 if (r) {
09941366 4617 kvm_pic_destroy(kvm);
3ddea128 4618 goto create_irqchip_unlock;
09941366
RK		 4619 }
4620
399ec807
AK		 4621 r = kvm_setup_default_irq_routing(kvm);
4622 if (r) {
72bb2fcd 4623 kvm_ioapic_destroy(kvm);
09941366 4624 kvm_pic_destroy(kvm);
71ba994c 4625 goto create_irqchip_unlock;
399ec807 4626 }
49776faf 4627 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4628 smp_wmb();
49776faf 4629 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4630 create_irqchip_unlock:
4631 mutex_unlock(&kvm->lock);
1fe779f8 4632 break;
3ddea128 4633 }
7837699f 4634 case KVM_CREATE_PIT:
c5ff41ce
JK		 4635 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4636 goto create_pit;
4637 case KVM_CREATE_PIT2:
4638 r = -EFAULT;
4639 if (copy_from_user(&u.pit_config, argp,
4640 sizeof(struct kvm_pit_config)))
4641 goto out;
4642 create_pit:
250715a6 4643 mutex_lock(&kvm->lock);
269e05e4
AK		 4644 r = -EEXIST;
4645 if (kvm->arch.vpit)
4646 goto create_pit_unlock;
7837699f 4647 r = -ENOMEM;
c5ff41ce 4648 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4649 if (kvm->arch.vpit)
4650 r = 0;
269e05e4 4651 create_pit_unlock:
250715a6 4652 mutex_unlock(&kvm->lock);
7837699f 4653 break;
1fe779f8
CO		 4654 case KVM_GET_IRQCHIP: {
4655 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4656 struct kvm_irqchip *chip;
1fe779f8 4657
ff5c2c03
SL		 4658 chip = memdup_user(argp, sizeof(*chip));
4659 if (IS_ERR(chip)) {
4660 r = PTR_ERR(chip);
1fe779f8 4661 goto out;
ff5c2c03
SL		 4662 }
4663
1fe779f8 4664 r = -ENXIO;
826da321 4665 if (!irqchip_kernel(kvm))
f0d66275
DH		 4666 goto get_irqchip_out;
4667 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4668 if (r)
f0d66275 4669 goto get_irqchip_out;
1fe779f8 4670 r = -EFAULT;
0e96f31e 4671 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4672 goto get_irqchip_out;
1fe779f8 4673 r = 0;
f0d66275
DH		 4674 get_irqchip_out:
4675 kfree(chip);
1fe779f8
CO		 4676 break;
4677 }
4678 case KVM_SET_IRQCHIP: {
4679 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4680 struct kvm_irqchip *chip;
1fe779f8 4681
ff5c2c03
SL		 4682 chip = memdup_user(argp, sizeof(*chip));
4683 if (IS_ERR(chip)) {
4684 r = PTR_ERR(chip);
1fe779f8 4685 goto out;
ff5c2c03
SL		 4686 }
4687
1fe779f8 4688 r = -ENXIO;
826da321 4689 if (!irqchip_kernel(kvm))
f0d66275
DH		 4690 goto set_irqchip_out;
4691 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4692 if (r)
f0d66275 4693 goto set_irqchip_out;
1fe779f8 4694 r = 0;
f0d66275
DH		 4695 set_irqchip_out:
4696 kfree(chip);
1fe779f8
CO		 4697 break;
4698 }
e0f63cb9 4699 case KVM_GET_PIT: {
e0f63cb9 4700 r = -EFAULT;
f0d66275 4701 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4702 goto out;
4703 r = -ENXIO;
4704 if (!kvm->arch.vpit)
4705 goto out;
f0d66275 4706 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4707 if (r)
4708 goto out;
4709 r = -EFAULT;
f0d66275 4710 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4711 goto out;
4712 r = 0;
4713 break;
4714 }
4715 case KVM_SET_PIT: {
e0f63cb9 4716 r = -EFAULT;
0e96f31e 4717 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4718 goto out;
4719 r = -ENXIO;
4720 if (!kvm->arch.vpit)
4721 goto out;
f0d66275 4722 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4723 break;
4724 }
e9f42757
BK		 4725 case KVM_GET_PIT2: {
4726 r = -ENXIO;
4727 if (!kvm->arch.vpit)
4728 goto out;
4729 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4730 if (r)
4731 goto out;
4732 r = -EFAULT;
4733 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4734 goto out;
4735 r = 0;
4736 break;
4737 }
4738 case KVM_SET_PIT2: {
4739 r = -EFAULT;
4740 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4741 goto out;
4742 r = -ENXIO;
4743 if (!kvm->arch.vpit)
4744 goto out;
4745 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4746 break;
4747 }
52d939a0
MT		 4748 case KVM_REINJECT_CONTROL: {
4749 struct kvm_reinject_control control;
4750 r = -EFAULT;
4751 if (copy_from_user(&control, argp, sizeof(control)))
4752 goto out;
4753 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4754 break;
4755 }
d71ba788
PB		 4756 case KVM_SET_BOOT_CPU_ID:
4757 r = 0;
4758 mutex_lock(&kvm->lock);
557abc40 4759 if (kvm->created_vcpus)
d71ba788
PB		 4760 r = -EBUSY;
4761 else
4762 kvm->arch.bsp_vcpu_id = arg;
4763 mutex_unlock(&kvm->lock);
4764 break;
ffde22ac 4765 case KVM_XEN_HVM_CONFIG: {
51776043 4766 struct kvm_xen_hvm_config xhc;
ffde22ac 4767 r = -EFAULT;
51776043 4768 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4769 goto out;
4770 r = -EINVAL;
51776043 4771 if (xhc.flags)
ffde22ac 4772 goto out;
51776043 4773 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4774 r = 0;
4775 break;
4776 }
afbcf7ab 4777 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4778 struct kvm_clock_data user_ns;
4779 u64 now_ns;
afbcf7ab
GC		 4780
4781 r = -EFAULT;
4782 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4783 goto out;
4784
4785 r = -EINVAL;
4786 if (user_ns.flags)
4787 goto out;
4788
4789 r = 0;
0bc48bea
RK		 4790 /*
4791 * TODO: userspace has to take care of races with VCPU_RUN, so
4792 * kvm_gen_update_masterclock() can be cut down to locked
4793 * pvclock_update_vm_gtod_copy().
4794 */
4795 kvm_gen_update_masterclock(kvm);
e891a32e 4796 now_ns = get_kvmclock_ns(kvm);
108b249c 4797 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4798 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4799 break;
4800 }
4801 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4802 struct kvm_clock_data user_ns;
4803 u64 now_ns;
4804
e891a32e 4805 now_ns = get_kvmclock_ns(kvm);
108b249c 4806 user_ns.clock = now_ns;
e3fd9a93 4807 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4808 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4809
4810 r = -EFAULT;
4811 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4812 goto out;
4813 r = 0;
4814 break;
4815 }
5acc5c06
BS		 4816 case KVM_MEMORY_ENCRYPT_OP: {
4817 r = -ENOTTY;
4818 if (kvm_x86_ops->mem_enc_op)
4819 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4820 break;
4821 }
69eaedee
BS		 4822 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4823 struct kvm_enc_region region;
4824
4825 r = -EFAULT;
4826 if (copy_from_user(&region, argp, sizeof(region)))
4827 goto out;
4828
4829 r = -ENOTTY;
4830 if (kvm_x86_ops->mem_enc_reg_region)
4831 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4832 break;
4833 }
4834 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4835 struct kvm_enc_region region;
4836
4837 r = -EFAULT;
4838 if (copy_from_user(&region, argp, sizeof(region)))
4839 goto out;
4840
4841 r = -ENOTTY;
4842 if (kvm_x86_ops->mem_enc_unreg_region)
4843 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4844 break;
4845 }
faeb7833
RK		 4846 case KVM_HYPERV_EVENTFD: {
4847 struct kvm_hyperv_eventfd hvevfd;
4848
4849 r = -EFAULT;
4850 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4851 goto out;
4852 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4853 break;
4854 }
1fe779f8 4855 default:
ad6260da 4856 r = -ENOTTY;
1fe779f8
CO		 4857 }
4858out:
4859 return r;
4860}
4861
a16b043c 4862static void kvm_init_msr_list(void)
043405e1
CO		 4863{
4864 u32 dummy[2];
4865 unsigned i, j;
4866
62ef68bb 4867 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4868 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4869 continue;
93c4adc7
PB		 4870
4871 /*
4872 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4873 * to the guests in some cases.
93c4adc7
PB		 4874 */
4875 switch (msrs_to_save[i]) {
4876 case MSR_IA32_BNDCFGS:
503234b3 4877 if (!kvm_mpx_supported())
93c4adc7
PB		 4878 continue;
4879 break;
9dbe6cf9
PB		 4880 case MSR_TSC_AUX:
4881 if (!kvm_x86_ops->rdtscp_supported())
4882 continue;
4883 break;
93c4adc7
PB		 4884 default:
4885 break;
4886 }
4887
043405e1
CO		 4888 if (j < i)
4889 msrs_to_save[j] = msrs_to_save[i];
4890 j++;
4891 }
4892 num_msrs_to_save = j;
62ef68bb
PB		 4893
4894 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4895 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4896 continue;
62ef68bb
PB		 4897
4898 if (j < i)
4899 emulated_msrs[j] = emulated_msrs[i];
4900 j++;
4901 }
4902 num_emulated_msrs = j;
801e459a
TL		 4903
4904 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4905 struct kvm_msr_entry msr;
4906
4907 msr.index = msr_based_features[i];
66421c1e 4908 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4909 continue;
4910
4911 if (j < i)
4912 msr_based_features[j] = msr_based_features[i];
4913 j++;
4914 }
4915 num_msr_based_features = j;
043405e1
CO		 4916}
4917
bda9020e
MT		 4918static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4919 const void *v)
bbd9b64e 4920{
70252a10
AK		 4921 int handled = 0;
4922 int n;
4923
4924 do {
4925 n = min(len, 8);
bce87cce 4926 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4927 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4928 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4929 break;
4930 handled += n;
4931 addr += n;
4932 len -= n;
4933 v += n;
4934 } while (len);
bbd9b64e 4935
70252a10 4936 return handled;
bbd9b64e
CO		 4937}
4938
bda9020e 4939static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4940{
70252a10
AK		 4941 int handled = 0;
4942 int n;
4943
4944 do {
4945 n = min(len, 8);
bce87cce 4946 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4947 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4948 addr, n, v))
4949 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4950 break;
e39d200f 4951 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4952 handled += n;
4953 addr += n;
4954 len -= n;
4955 v += n;
4956 } while (len);
bbd9b64e 4957
70252a10 4958 return handled;
bbd9b64e
CO		 4959}
4960
2dafc6c2
GN		 4961static void kvm_set_segment(struct kvm_vcpu *vcpu,
4962 struct kvm_segment *var, int seg)
4963{
4964 kvm_x86_ops->set_segment(vcpu, var, seg);
4965}
4966
4967void kvm_get_segment(struct kvm_vcpu *vcpu,
4968 struct kvm_segment *var, int seg)
4969{
4970 kvm_x86_ops->get_segment(vcpu, var, seg);
4971}
4972
54987b7a
PB		 4973gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4974 struct x86_exception *exception)
02f59dc9
JR		 4975{
4976 gpa_t t_gpa;
02f59dc9
JR		 4977
4978 BUG_ON(!mmu_is_nested(vcpu));
4979
4980 /* NPT walks are always user-walks */
4981 access |= PFERR_USER_MASK;
44dd3ffa 4982 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4983
4984 return t_gpa;
4985}
4986
ab9ae313
AK		 4987gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4988 struct x86_exception *exception)
1871c602
GN		 4989{
4990 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4991 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4992}
4993
ab9ae313
AK		 4994 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4995 struct x86_exception *exception)
1871c602
GN		 4996{
4997 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4998 access |= PFERR_FETCH_MASK;
ab9ae313 4999 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5000}
5001
ab9ae313
AK		 5002gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5003 struct x86_exception *exception)
1871c602
GN		 5004{
5005 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5006 access |= PFERR_WRITE_MASK;
ab9ae313 5007 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5008}
5009
5010/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5011gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5012 struct x86_exception *exception)
1871c602 5013{
ab9ae313 5014 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5015}
5016
5017static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5018 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5019 struct x86_exception *exception)
bbd9b64e
CO		 5020{
5021 void *data = val;
10589a46 5022 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5023
5024 while (bytes) {
14dfe855 5025 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5026 exception);
bbd9b64e 5027 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5028 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5029 int ret;
5030
bcc55cba 5031 if (gpa == UNMAPPED_GVA)
ab9ae313 5032 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5033 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5034 offset, toread);
10589a46 5035 if (ret < 0) {
c3cd7ffa 5036 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5037 goto out;
5038 }
bbd9b64e 5039
77c2002e
IE		 5040 bytes -= toread;
5041 data += toread;
5042 addr += toread;
bbd9b64e 5043 }
10589a46 5044out:
10589a46 5045 return r;
bbd9b64e 5046}
77c2002e 5047
1871c602 5048/* used for instruction fetching */
0f65dd70
AK		 5049static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5050 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5051 struct x86_exception *exception)
1871c602 5052{
0f65dd70 5053 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5054 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5055 unsigned offset;
5056 int ret;
0f65dd70 5057
44583cba
PB		 5058 /* Inline kvm_read_guest_virt_helper for speed. */
5059 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5060 exception);
5061 if (unlikely(gpa == UNMAPPED_GVA))
5062 return X86EMUL_PROPAGATE_FAULT;
5063
5064 offset = addr & (PAGE_SIZE-1);
5065 if (WARN_ON(offset + bytes > PAGE_SIZE))
5066 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5067 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5068 offset, bytes);
44583cba
PB		 5069 if (unlikely(ret < 0))
5070 return X86EMUL_IO_NEEDED;
5071
5072 return X86EMUL_CONTINUE;
1871c602
GN		 5073}
5074
ce14e868 5075int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5076 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5077 struct x86_exception *exception)
1871c602
GN		 5078{
5079 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5080
1871c602 5081 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5082 exception);
1871c602 5083}
064aea77 5084EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5085
ce14e868
PB		 5086static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5087 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5088 struct x86_exception *exception, bool system)
1871c602 5089{
0f65dd70 5090 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5091 u32 access = 0;
5092
5093 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5094 access |= PFERR_USER_MASK;
5095
5096 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5097}
5098
7a036a6f
RK		 5099static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5100 unsigned long addr, void *val, unsigned int bytes)
5101{
5102 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5103 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5104
5105 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5106}
5107
ce14e868
PB		 5108static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5109 struct kvm_vcpu *vcpu, u32 access,
5110 struct x86_exception *exception)
77c2002e
IE		 5111{
5112 void *data = val;
5113 int r = X86EMUL_CONTINUE;
5114
5115 while (bytes) {
14dfe855 5116 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5117 access,
ab9ae313 5118 exception);
77c2002e
IE		 5119 unsigned offset = addr & (PAGE_SIZE-1);
5120 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5121 int ret;
5122
bcc55cba 5123 if (gpa == UNMAPPED_GVA)
ab9ae313 5124 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5125 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5126 if (ret < 0) {
c3cd7ffa 5127 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5128 goto out;
5129 }
5130
5131 bytes -= towrite;
5132 data += towrite;
5133 addr += towrite;
5134 }
5135out:
5136 return r;
5137}
ce14e868
PB		 5138
5139static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5140 unsigned int bytes, struct x86_exception *exception,
5141 bool system)
ce14e868
PB		 5142{
5143 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5144 u32 access = PFERR_WRITE_MASK;
5145
5146 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5147 access |= PFERR_USER_MASK;
ce14e868
PB		 5148
5149 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5150 access, exception);
ce14e868
PB		 5151}
5152
5153int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5154 unsigned int bytes, struct x86_exception *exception)
5155{
c595ceee
PB		 5156 /* kvm_write_guest_virt_system can pull in tons of pages. */
5157 vcpu->arch.l1tf_flush_l1d = true;
5158
ce14e868
PB		 5159 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5160 PFERR_WRITE_MASK, exception);
5161}
6a4d7550 5162EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5163
082d06ed
WL		 5164int handle_ud(struct kvm_vcpu *vcpu)
5165{
6c86eedc 5166 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5167 enum emulation_result er;
6c86eedc
WL		 5168 char sig[5]; /* ud2; .ascii "kvm" */
5169 struct x86_exception e;
5170
5171 if (force_emulation_prefix &&
3c9fa24c
PB		 5172 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5173 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5174 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5175 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5176 emul_type = 0;
5177 }
082d06ed 5178
0ce97a2b 5179 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5180 if (er == EMULATE_USER_EXIT)
5181 return 0;
5182 if (er != EMULATE_DONE)
5183 kvm_queue_exception(vcpu, UD_VECTOR);
5184 return 1;
5185}
5186EXPORT_SYMBOL_GPL(handle_ud);
5187
0f89b207
TL		 5188static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5189 gpa_t gpa, bool write)
5190{
5191 /* For APIC access vmexit */
5192 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5193 return 1;
5194
5195 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5196 trace_vcpu_match_mmio(gva, gpa, write, true);
5197 return 1;
5198 }
5199
5200 return 0;
5201}
5202
af7cc7d1
XG		 5203static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5204 gpa_t *gpa, struct x86_exception *exception,
5205 bool write)
5206{
97d64b78
AK		 5207 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5208 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5209
be94f6b7
HH		 5210 /*
5211 * currently PKRU is only applied to ept enabled guest so
5212 * there is no pkey in EPT page table for L1 guest or EPT
5213 * shadow page table for L2 guest.
5214 */
97d64b78 5215 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5216 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5217 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5218 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5219 (gva & (PAGE_SIZE - 1));
4f022648 5220 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5221 return 1;
5222 }
5223
af7cc7d1
XG		 5224 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5225
5226 if (*gpa == UNMAPPED_GVA)
5227 return -1;
5228
0f89b207 5229 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5230}
5231
3200f405 5232int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5233 const void *val, int bytes)
bbd9b64e
CO		 5234{
5235 int ret;
5236
54bf36aa 5237 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5238 if (ret < 0)
bbd9b64e 5239 return 0;
0eb05bf2 5240 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5241 return 1;
5242}
5243
77d197b2
XG		 5244struct read_write_emulator_ops {
5245 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5246 int bytes);
5247 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5248 void *val, int bytes);
5249 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5250 int bytes, void *val);
5251 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5252 void *val, int bytes);
5253 bool write;
5254};
5255
5256static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5257{
5258 if (vcpu->mmio_read_completed) {
77d197b2 5259 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5260 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5261 vcpu->mmio_read_completed = 0;
5262 return 1;
5263 }
5264
5265 return 0;
5266}
5267
5268static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5269 void *val, int bytes)
5270{
54bf36aa 5271 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5272}
5273
5274static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5275 void *val, int bytes)
5276{
5277 return emulator_write_phys(vcpu, gpa, val, bytes);
5278}
5279
5280static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5281{
e39d200f 5282 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5283 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5284}
5285
5286static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5287 void *val, int bytes)
5288{
e39d200f 5289 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5290 return X86EMUL_IO_NEEDED;
5291}
5292
5293static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5294 void *val, int bytes)
5295{
f78146b0
AK		 5296 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5297
87da7e66 5298 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5299 return X86EMUL_CONTINUE;
5300}
5301
0fbe9b0b 5302static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5303 .read_write_prepare = read_prepare,
5304 .read_write_emulate = read_emulate,
5305 .read_write_mmio = vcpu_mmio_read,
5306 .read_write_exit_mmio = read_exit_mmio,
5307};
5308
0fbe9b0b 5309static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5310 .read_write_emulate = write_emulate,
5311 .read_write_mmio = write_mmio,
5312 .read_write_exit_mmio = write_exit_mmio,
5313 .write = true,
5314};
5315
22388a3c
XG		 5316static int emulator_read_write_onepage(unsigned long addr, void *val,
5317 unsigned int bytes,
5318 struct x86_exception *exception,
5319 struct kvm_vcpu *vcpu,
0fbe9b0b 5320 const struct read_write_emulator_ops *ops)
bbd9b64e 5321{
af7cc7d1
XG		 5322 gpa_t gpa;
5323 int handled, ret;
22388a3c 5324 bool write = ops->write;
f78146b0 5325 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5326 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5327
5328 /*
5329 * If the exit was due to a NPF we may already have a GPA.
5330 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5331 * Note, this cannot be used on string operations since string
5332 * operation using rep will only have the initial GPA from the NPF
5333 * occurred.
5334 */
5335 if (vcpu->arch.gpa_available &&
5336 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5337 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5338 gpa = vcpu->arch.gpa_val;
5339 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5340 } else {
5341 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5342 if (ret < 0)
5343 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5344 }
10589a46 5345
618232e2 5346 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5347 return X86EMUL_CONTINUE;
5348
bbd9b64e
CO		 5349 /*
5350 * Is this MMIO handled locally?
5351 */
22388a3c 5352 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5353 if (handled == bytes)
bbd9b64e 5354 return X86EMUL_CONTINUE;
bbd9b64e 5355
70252a10
AK		 5356 gpa += handled;
5357 bytes -= handled;
5358 val += handled;
5359
87da7e66
XG		 5360 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5361 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5362 frag->gpa = gpa;
5363 frag->data = val;
5364 frag->len = bytes;
f78146b0 5365 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5366}
5367
52eb5a6d
XL		 5368static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5369 unsigned long addr,
22388a3c
XG		 5370 void *val, unsigned int bytes,
5371 struct x86_exception *exception,
0fbe9b0b 5372 const struct read_write_emulator_ops *ops)
bbd9b64e 5373{
0f65dd70 5374 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5375 gpa_t gpa;
5376 int rc;
5377
5378 if (ops->read_write_prepare &&
5379 ops->read_write_prepare(vcpu, val, bytes))
5380 return X86EMUL_CONTINUE;
5381
5382 vcpu->mmio_nr_fragments = 0;
0f65dd70 5383
bbd9b64e
CO		 5384 /* Crossing a page boundary? */
5385 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5386 int now;
bbd9b64e
CO		 5387
5388 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5389 rc = emulator_read_write_onepage(addr, val, now, exception,
5390 vcpu, ops);
5391
bbd9b64e
CO		 5392 if (rc != X86EMUL_CONTINUE)
5393 return rc;
5394 addr += now;
bac15531
NA		 5395 if (ctxt->mode != X86EMUL_MODE_PROT64)
5396 addr = (u32)addr;
bbd9b64e
CO		 5397 val += now;
5398 bytes -= now;
5399 }
22388a3c 5400
f78146b0
AK		 5401 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5402 vcpu, ops);
5403 if (rc != X86EMUL_CONTINUE)
5404 return rc;
5405
5406 if (!vcpu->mmio_nr_fragments)
5407 return rc;
5408
5409 gpa = vcpu->mmio_fragments[0].gpa;
5410
5411 vcpu->mmio_needed = 1;
5412 vcpu->mmio_cur_fragment = 0;
5413
87da7e66 5414 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5415 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5416 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5417 vcpu->run->mmio.phys_addr = gpa;
5418
5419 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5420}
5421
5422static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5423 unsigned long addr,
5424 void *val,
5425 unsigned int bytes,
5426 struct x86_exception *exception)
5427{
5428 return emulator_read_write(ctxt, addr, val, bytes,
5429 exception, &read_emultor);
5430}
5431
52eb5a6d 5432static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5433 unsigned long addr,
5434 const void *val,
5435 unsigned int bytes,
5436 struct x86_exception *exception)
5437{
5438 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5439 exception, &write_emultor);
bbd9b64e 5440}
bbd9b64e 5441
daea3e73
AK		 5442#define CMPXCHG_TYPE(t, ptr, old, new) \
5443 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5444
5445#ifdef CONFIG_X86_64
5446# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5447#else
5448# define CMPXCHG64(ptr, old, new) \
9749a6c0 5449 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5450#endif
5451
0f65dd70
AK		 5452static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5453 unsigned long addr,
bbd9b64e
CO		 5454 const void *old,
5455 const void *new,
5456 unsigned int bytes,
0f65dd70 5457 struct x86_exception *exception)
bbd9b64e 5458{
0f65dd70 5459 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5460 gpa_t gpa;
5461 struct page *page;
5462 char *kaddr;
5463 bool exchanged;
2bacc55c 5464
daea3e73
AK		 5465 /* guests cmpxchg8b have to be emulated atomically */
5466 if (bytes > 8 || (bytes & (bytes - 1)))
5467 goto emul_write;
10589a46 5468
daea3e73 5469 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5470
daea3e73
AK		 5471 if (gpa == UNMAPPED_GVA ||
5472 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5473 goto emul_write;
2bacc55c 5474
daea3e73
AK		 5475 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5476 goto emul_write;
72dc67a6 5477
54bf36aa 5478 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5479 if (is_error_page(page))
c19b8bd6 5480 goto emul_write;
72dc67a6 5481
8fd75e12 5482 kaddr = kmap_atomic(page);
daea3e73
AK		 5483 kaddr += offset_in_page(gpa);
5484 switch (bytes) {
5485 case 1:
5486 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5487 break;
5488 case 2:
5489 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5490 break;
5491 case 4:
5492 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5493 break;
5494 case 8:
5495 exchanged = CMPXCHG64(kaddr, old, new);
5496 break;
5497 default:
5498 BUG();
2bacc55c 5499 }
8fd75e12 5500 kunmap_atomic(kaddr);
daea3e73
AK		 5501 kvm_release_page_dirty(page);
5502
5503 if (!exchanged)
5504 return X86EMUL_CMPXCHG_FAILED;
5505
54bf36aa 5506 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5507 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5508
5509 return X86EMUL_CONTINUE;
4a5f48f6 5510
3200f405 5511emul_write:
daea3e73 5512 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5513
0f65dd70 5514 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5515}
5516
cf8f70bf
GN		 5517static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5518{
cbfc6c91 5519 int r = 0, i;
cf8f70bf 5520
cbfc6c91
WL		 5521 for (i = 0; i < vcpu->arch.pio.count; i++) {
5522 if (vcpu->arch.pio.in)
5523 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5524 vcpu->arch.pio.size, pd);
5525 else
5526 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5527 vcpu->arch.pio.port, vcpu->arch.pio.size,
5528 pd);
5529 if (r)
5530 break;
5531 pd += vcpu->arch.pio.size;
5532 }
cf8f70bf
GN		 5533 return r;
5534}
5535
6f6fbe98
XG		 5536static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5537 unsigned short port, void *val,
5538 unsigned int count, bool in)
cf8f70bf 5539{
cf8f70bf 5540 vcpu->arch.pio.port = port;
6f6fbe98 5541 vcpu->arch.pio.in = in;
7972995b 5542 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5543 vcpu->arch.pio.size = size;
5544
5545 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5546 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5547 return 1;
5548 }
5549
5550 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5551 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5552 vcpu->run->io.size = size;
5553 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5554 vcpu->run->io.count = count;
5555 vcpu->run->io.port = port;
5556
5557 return 0;
5558}
5559
6f6fbe98
XG		 5560static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5561 int size, unsigned short port, void *val,
5562 unsigned int count)
cf8f70bf 5563{
ca1d4a9e 5564 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5565 int ret;
ca1d4a9e 5566
6f6fbe98
XG		 5567 if (vcpu->arch.pio.count)
5568 goto data_avail;
cf8f70bf 5569
cbfc6c91
WL		 5570 memset(vcpu->arch.pio_data, 0, size * count);
5571
6f6fbe98
XG		 5572 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5573 if (ret) {
5574data_avail:
5575 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5576 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5577 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5578 return 1;
5579 }
5580
cf8f70bf
GN		 5581 return 0;
5582}
5583
6f6fbe98
XG		 5584static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5585 int size, unsigned short port,
5586 const void *val, unsigned int count)
5587{
5588 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5589
5590 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5591 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5592 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5593}
5594
bbd9b64e
CO		 5595static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5596{
5597 return kvm_x86_ops->get_segment_base(vcpu, seg);
5598}
5599
3cb16fe7 5600static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5601{
3cb16fe7 5602 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5603}
5604
ae6a2375 5605static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5606{
5607 if (!need_emulate_wbinvd(vcpu))
5608 return X86EMUL_CONTINUE;
5609
5610 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5611 int cpu = get_cpu();
5612
5613 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5614 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5615 wbinvd_ipi, NULL, 1);
2eec7343 5616 put_cpu();
f5f48ee1 5617 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5618 } else
5619 wbinvd();
f5f48ee1
SY		 5620 return X86EMUL_CONTINUE;
5621}
5cb56059
JS		 5622
5623int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5624{
6affcbed
KH		 5625 kvm_emulate_wbinvd_noskip(vcpu);
5626 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5627}
f5f48ee1
SY		 5628EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5629
5cb56059
JS		 5630
5631
bcaf5cc5
AK		 5632static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5633{
5cb56059 5634 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5635}
5636
52eb5a6d
XL		 5637static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5638 unsigned long *dest)
bbd9b64e 5639{
16f8a6f9 5640 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5641}
5642
52eb5a6d
XL		 5643static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5644 unsigned long value)
bbd9b64e 5645{
338dbc97 5646
717746e3 5647 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5648}
5649
52a46617 5650static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5651{
52a46617 5652 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5653}
5654
717746e3 5655static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5656{
717746e3 5657 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5658 unsigned long value;
5659
5660 switch (cr) {
5661 case 0:
5662 value = kvm_read_cr0(vcpu);
5663 break;
5664 case 2:
5665 value = vcpu->arch.cr2;
5666 break;
5667 case 3:
9f8fe504 5668 value = kvm_read_cr3(vcpu);
52a46617
GN		 5669 break;
5670 case 4:
5671 value = kvm_read_cr4(vcpu);
5672 break;
5673 case 8:
5674 value = kvm_get_cr8(vcpu);
5675 break;
5676 default:
a737f256 5677 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5678 return 0;
5679 }
5680
5681 return value;
5682}
5683
717746e3 5684static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5685{
717746e3 5686 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5687 int res = 0;
5688
52a46617
GN		 5689 switch (cr) {
5690 case 0:
49a9b07e 5691 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5692 break;
5693 case 2:
5694 vcpu->arch.cr2 = val;
5695 break;
5696 case 3:
2390218b 5697 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5698 break;
5699 case 4:
a83b29c6 5700 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5701 break;
5702 case 8:
eea1cff9 5703 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5704 break;
5705 default:
a737f256 5706 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5707 res = -1;
52a46617 5708 }
0f12244f
GN		 5709
5710 return res;
52a46617
GN		 5711}
5712
717746e3 5713static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5714{
717746e3 5715 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5716}
5717
4bff1e86 5718static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5719{
4bff1e86 5720 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5721}
5722
4bff1e86 5723static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5724{
4bff1e86 5725 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5726}
5727
1ac9d0cf
AK		 5728static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5729{
5730 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5731}
5732
5733static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5734{
5735 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5736}
5737
4bff1e86
AK		 5738static unsigned long emulator_get_cached_segment_base(
5739 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5740{
4bff1e86 5741 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5742}
5743
1aa36616
AK		 5744static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5745 struct desc_struct *desc, u32 *base3,
5746 int seg)
2dafc6c2
GN		 5747{
5748 struct kvm_segment var;
5749
4bff1e86 5750 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5751 *selector = var.selector;
2dafc6c2 5752
378a8b09
GN		 5753 if (var.unusable) {
5754 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5755 if (base3)
5756 *base3 = 0;
2dafc6c2 5757 return false;
378a8b09 5758 }
2dafc6c2
GN		 5759
5760 if (var.g)
5761 var.limit >>= 12;
5762 set_desc_limit(desc, var.limit);
5763 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5764#ifdef CONFIG_X86_64
5765 if (base3)
5766 *base3 = var.base >> 32;
5767#endif
2dafc6c2
GN		 5768 desc->type = var.type;
5769 desc->s = var.s;
5770 desc->dpl = var.dpl;
5771 desc->p = var.present;
5772 desc->avl = var.avl;
5773 desc->l = var.l;
5774 desc->d = var.db;
5775 desc->g = var.g;
5776
5777 return true;
5778}
5779
1aa36616
AK		 5780static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5781 struct desc_struct *desc, u32 base3,
5782 int seg)
2dafc6c2 5783{
4bff1e86 5784 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5785 struct kvm_segment var;
5786
1aa36616 5787 var.selector = selector;
2dafc6c2 5788 var.base = get_desc_base(desc);
5601d05b
GN		 5789#ifdef CONFIG_X86_64
5790 var.base |= ((u64)base3) << 32;
5791#endif
2dafc6c2
GN		 5792 var.limit = get_desc_limit(desc);
5793 if (desc->g)
5794 var.limit = (var.limit << 12) | 0xfff;
5795 var.type = desc->type;
2dafc6c2
GN		 5796 var.dpl = desc->dpl;
5797 var.db = desc->d;
5798 var.s = desc->s;
5799 var.l = desc->l;
5800 var.g = desc->g;
5801 var.avl = desc->avl;
5802 var.present = desc->p;
5803 var.unusable = !var.present;
5804 var.padding = 0;
5805
5806 kvm_set_segment(vcpu, &var, seg);
5807 return;
5808}
5809
717746e3
AK		 5810static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5811 u32 msr_index, u64 *pdata)
5812{
609e36d3
PB		 5813 struct msr_data msr;
5814 int r;
5815
5816 msr.index = msr_index;
5817 msr.host_initiated = false;
5818 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5819 if (r)
5820 return r;
5821
5822 *pdata = msr.data;
5823 return 0;
717746e3
AK		 5824}
5825
5826static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5827 u32 msr_index, u64 data)
5828{
8fe8ab46
WA		 5829 struct msr_data msr;
5830
5831 msr.data = data;
5832 msr.index = msr_index;
5833 msr.host_initiated = false;
5834 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5835}
5836
64d60670
PB		 5837static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5838{
5839 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5840
5841 return vcpu->arch.smbase;
5842}
5843
5844static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5845{
5846 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5847
5848 vcpu->arch.smbase = smbase;
5849}
5850
67f4d428
NA		 5851static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5852 u32 pmc)
5853{
c6702c9d 5854 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5855}
5856
222d21aa
AK		 5857static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5858 u32 pmc, u64 *pdata)
5859{
c6702c9d 5860 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5861}
5862
6c3287f7
AK		 5863static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5864{
5865 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5866}
5867
2953538e 5868static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5869 struct x86_instruction_info *info,
c4f035c6
AK		 5870 enum x86_intercept_stage stage)
5871{
2953538e 5872 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5873}
5874
e911eb3b
YZ		 5875static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5876 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5877{
e911eb3b 5878 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5879}
5880
dd856efa
AK		 5881static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5882{
5883 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5884}
5885
5886static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5887{
5888 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5889}
5890
801806d9
NA		 5891static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5892{
5893 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5894}
5895
6ed071f0
LP		 5896static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5897{
5898 return emul_to_vcpu(ctxt)->arch.hflags;
5899}
5900
5901static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5902{
5903 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5904}
5905
0234bf88
LP		 5906static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5907{
5908 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5909}
5910
0225fb50 5911static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5912 .read_gpr = emulator_read_gpr,
5913 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5914 .read_std = emulator_read_std,
5915 .write_std = emulator_write_std,
7a036a6f 5916 .read_phys = kvm_read_guest_phys_system,
1871c602 5917 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5918 .read_emulated = emulator_read_emulated,
5919 .write_emulated = emulator_write_emulated,
5920 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5921 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5922 .pio_in_emulated = emulator_pio_in_emulated,
5923 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5924 .get_segment = emulator_get_segment,
5925 .set_segment = emulator_set_segment,
5951c442 5926 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5927 .get_gdt = emulator_get_gdt,
160ce1f1 5928 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5929 .set_gdt = emulator_set_gdt,
5930 .set_idt = emulator_set_idt,
52a46617
GN		 5931 .get_cr = emulator_get_cr,
5932 .set_cr = emulator_set_cr,
9c537244 5933 .cpl = emulator_get_cpl,
35aa5375
GN		 5934 .get_dr = emulator_get_dr,
5935 .set_dr = emulator_set_dr,
64d60670
PB		 5936 .get_smbase = emulator_get_smbase,
5937 .set_smbase = emulator_set_smbase,
717746e3
AK		 5938 .set_msr = emulator_set_msr,
5939 .get_msr = emulator_get_msr,
67f4d428 5940 .check_pmc = emulator_check_pmc,
222d21aa 5941 .read_pmc = emulator_read_pmc,
6c3287f7 5942 .halt = emulator_halt,
bcaf5cc5 5943 .wbinvd = emulator_wbinvd,
d6aa1000 5944 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5945 .intercept = emulator_intercept,
bdb42f5a 5946 .get_cpuid = emulator_get_cpuid,
801806d9 5947 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5948 .get_hflags = emulator_get_hflags,
5949 .set_hflags = emulator_set_hflags,
0234bf88 5950 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5951};
5952
95cb2295
GN		 5953static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5954{
37ccdcbe 5955 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5956 /*
5957 * an sti; sti; sequence only disable interrupts for the first
5958 * instruction. So, if the last instruction, be it emulated or
5959 * not, left the system with the INT_STI flag enabled, it
5960 * means that the last instruction is an sti. We should not
5961 * leave the flag on in this case. The same goes for mov ss
5962 */
37ccdcbe
PB		 5963 if (int_shadow & mask)
5964 mask = 0;
6addfc42 5965 if (unlikely(int_shadow || mask)) {
95cb2295 5966 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5967 if (!mask)
5968 kvm_make_request(KVM_REQ_EVENT, vcpu);
5969 }
95cb2295
GN		 5970}
5971
ef54bcfe 5972static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5973{
5974 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5975 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5976 return kvm_propagate_fault(vcpu, &ctxt->exception);
5977
5978 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5979 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5980 ctxt->exception.error_code);
54b8486f 5981 else
da9cb575 5982 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5983 return false;
54b8486f
GN		 5984}
5985
8ec4722d
MG		 5986static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5987{
adf52235 5988 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5989 int cs_db, cs_l;
5990
8ec4722d
MG		 5991 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5992
adf52235 5993 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5994 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5995
adf52235
TY		 5996 ctxt->eip = kvm_rip_read(vcpu);
5997 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5998 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5999 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6000 cs_db ? X86EMUL_MODE_PROT32 :
6001 X86EMUL_MODE_PROT16;
a584539b 6002 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6003 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6004 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6005
dd856efa 6006 init_decode_cache(ctxt);
7ae441ea 6007 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6008}
6009
71f9833b 6010int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6011{
9d74191a 6012 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6013 int ret;
6014
6015 init_emulate_ctxt(vcpu);
6016
9dac77fa
AK		 6017 ctxt->op_bytes = 2;
6018 ctxt->ad_bytes = 2;
6019 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6020 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6021
6022 if (ret != X86EMUL_CONTINUE)
6023 return EMULATE_FAIL;
6024
9dac77fa 6025 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6026 kvm_rip_write(vcpu, ctxt->eip);
6027 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6028
63995653
MG		 6029 return EMULATE_DONE;
6030}
6031EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6032
e2366171 6033static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6034{
fc3a9157
JR		 6035 int r = EMULATE_DONE;
6036
6d77dbfc
GN		 6037 ++vcpu->stat.insn_emulation_fail;
6038 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6039
6040 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6041 return EMULATE_FAIL;
6042
a2b9e6c1 6043 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6044 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6045 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6046 vcpu->run->internal.ndata = 0;
1f4dcb3b 6047 r = EMULATE_USER_EXIT;
fc3a9157 6048 }
e2366171 6049
6d77dbfc 6050 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6051
6052 return r;
6d77dbfc
GN		 6053}
6054
93c05d3e 6055static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6056 bool write_fault_to_shadow_pgtable,
6057 int emulation_type)
a6f177ef 6058{
95b3cf69 6059 gpa_t gpa = cr2;
ba049e93 6060 kvm_pfn_t pfn;
a6f177ef 6061
384bf221 6062 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6063 return false;
6064
6c3dfeb6
SC		 6065 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6066 return false;
6067
44dd3ffa 6068 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6069 /*
6070 * Write permission should be allowed since only
6071 * write access need to be emulated.
6072 */
6073 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6074
95b3cf69
XG		 6075 /*
6076 * If the mapping is invalid in guest, let cpu retry
6077 * it to generate fault.
6078 */
6079 if (gpa == UNMAPPED_GVA)
6080 return true;
6081 }
a6f177ef 6082
8e3d9d06
XG		 6083 /*
6084 * Do not retry the unhandleable instruction if it faults on the
6085 * readonly host memory, otherwise it will goto a infinite loop:
6086 * retry instruction -> write #PF -> emulation fail -> retry
6087 * instruction -> ...
6088 */
6089 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6090
6091 /*
6092 * If the instruction failed on the error pfn, it can not be fixed,
6093 * report the error to userspace.
6094 */
6095 if (is_error_noslot_pfn(pfn))
6096 return false;
6097
6098 kvm_release_pfn_clean(pfn);
6099
6100 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6101 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6102 unsigned int indirect_shadow_pages;
6103
6104 spin_lock(&vcpu->kvm->mmu_lock);
6105 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6106 spin_unlock(&vcpu->kvm->mmu_lock);
6107
6108 if (indirect_shadow_pages)
6109 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6110
a6f177ef 6111 return true;
8e3d9d06 6112 }
a6f177ef 6113
95b3cf69
XG		 6114 /*
6115 * if emulation was due to access to shadowed page table
6116 * and it failed try to unshadow page and re-enter the
6117 * guest to let CPU execute the instruction.
6118 */
6119 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6120
6121 /*
6122 * If the access faults on its page table, it can not
6123 * be fixed by unprotecting shadow page and it should
6124 * be reported to userspace.
6125 */
6126 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6127}
6128
1cb3f3ae
XG		 6129static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6130 unsigned long cr2, int emulation_type)
6131{
6132 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6133 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6134
6135 last_retry_eip = vcpu->arch.last_retry_eip;
6136 last_retry_addr = vcpu->arch.last_retry_addr;
6137
6138 /*
6139 * If the emulation is caused by #PF and it is non-page_table
6140 * writing instruction, it means the VM-EXIT is caused by shadow
6141 * page protected, we can zap the shadow page and retry this
6142 * instruction directly.
6143 *
6144 * Note: if the guest uses a non-page-table modifying instruction
6145 * on the PDE that points to the instruction, then we will unmap
6146 * the instruction and go to an infinite loop. So, we cache the
6147 * last retried eip and the last fault address, if we meet the eip
6148 * and the address again, we can break out of the potential infinite
6149 * loop.
6150 */
6151 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6152
384bf221 6153 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6154 return false;
6155
6c3dfeb6
SC		 6156 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6157 return false;
6158
1cb3f3ae
XG		 6159 if (x86_page_table_writing_insn(ctxt))
6160 return false;
6161
6162 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6163 return false;
6164
6165 vcpu->arch.last_retry_eip = ctxt->eip;
6166 vcpu->arch.last_retry_addr = cr2;
6167
44dd3ffa 6168 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6169 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6170
22368028 6171 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6172
6173 return true;
6174}
6175
716d51ab
GN		 6176static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6177static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6178
64d60670 6179static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6180{
64d60670 6181 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6182 /* This is a good place to trace that we are exiting SMM. */
6183 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6184
c43203ca
PB		 6185 /* Process a latched INIT or SMI, if any. */
6186 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6187 }
699023e2
PB		 6188
6189 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6190}
6191
6192static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6193{
6194 unsigned changed = vcpu->arch.hflags ^ emul_flags;
6195
a584539b 6196 vcpu->arch.hflags = emul_flags;
64d60670
PB		 6197
6198 if (changed & HF_SMM_MASK)
6199 kvm_smm_changed(vcpu);
a584539b
PB		 6200}
6201
4a1e10d5
PB		 6202static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6203 unsigned long *db)
6204{
6205 u32 dr6 = 0;
6206 int i;
6207 u32 enable, rwlen;
6208
6209 enable = dr7;
6210 rwlen = dr7 >> 16;
6211 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6212 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6213 dr6 |= (1 << i);
6214 return dr6;
6215}
6216
c8401dda 6217static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6218{
6219 struct kvm_run *kvm_run = vcpu->run;
6220
c8401dda
PB		 6221 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6222 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6223 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6224 kvm_run->debug.arch.exception = DB_VECTOR;
6225 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6226 *r = EMULATE_USER_EXIT;
6227 } else {
f10c729f 6228 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6229 }
6230}
6231
6affcbed
KH		 6232int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6233{
6234 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6235 int r = EMULATE_DONE;
6236
6237 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6238
6239 /*
6240 * rflags is the old, "raw" value of the flags. The new value has
6241 * not been saved yet.
6242 *
6243 * This is correct even for TF set by the guest, because "the
6244 * processor will not generate this exception after the instruction
6245 * that sets the TF flag".
6246 */
6247 if (unlikely(rflags & X86_EFLAGS_TF))
6248 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6249 return r == EMULATE_DONE;
6250}
6251EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6252
4a1e10d5
PB		 6253static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6254{
4a1e10d5
PB		 6255 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6256 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6257 struct kvm_run *kvm_run = vcpu->run;
6258 unsigned long eip = kvm_get_linear_rip(vcpu);
6259 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6260 vcpu->arch.guest_debug_dr7,
6261 vcpu->arch.eff_db);
6262
6263 if (dr6 != 0) {
6f43ed01 6264 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6265 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6266 kvm_run->debug.arch.exception = DB_VECTOR;
6267 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6268 *r = EMULATE_USER_EXIT;
6269 return true;
6270 }
6271 }
6272
4161a569
NA		 6273 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6274 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6275 unsigned long eip = kvm_get_linear_rip(vcpu);
6276 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6277 vcpu->arch.dr7,
6278 vcpu->arch.db);
6279
6280 if (dr6 != 0) {
6281 vcpu->arch.dr6 &= ~15;
6f43ed01 6282 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6283 kvm_queue_exception(vcpu, DB_VECTOR);
6284 *r = EMULATE_DONE;
6285 return true;
6286 }
6287 }
6288
6289 return false;
6290}
6291
04789b66
LA		 6292static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6293{
2d7921c4
AM		 6294 switch (ctxt->opcode_len) {
6295 case 1:
6296 switch (ctxt->b) {
6297 case 0xe4: /* IN */
6298 case 0xe5:
6299 case 0xec:
6300 case 0xed:
6301 case 0xe6: /* OUT */
6302 case 0xe7:
6303 case 0xee:
6304 case 0xef:
6305 case 0x6c: /* INS */
6306 case 0x6d:
6307 case 0x6e: /* OUTS */
6308 case 0x6f:
6309 return true;
6310 }
6311 break;
6312 case 2:
6313 switch (ctxt->b) {
6314 case 0x33: /* RDPMC */
6315 return true;
6316 }
6317 break;
04789b66
LA		 6318 }
6319
6320 return false;
6321}
6322
51d8b661
AP		 6323int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6324 unsigned long cr2,
dc25e89e
AP		 6325 int emulation_type,
6326 void *insn,
6327 int insn_len)
bbd9b64e 6328{
95cb2295 6329 int r;
9d74191a 6330 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6331 bool writeback = true;
93c05d3e 6332 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6333
c595ceee
PB		 6334 vcpu->arch.l1tf_flush_l1d = true;
6335
93c05d3e
XG		 6336 /*
6337 * Clear write_fault_to_shadow_pgtable here to ensure it is
6338 * never reused.
6339 */
6340 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6341 kvm_clear_exception_queue(vcpu);
8d7d8102 6342
571008da 6343 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6344 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6345
6346 /*
6347 * We will reenter on the same instruction since
6348 * we do not set complete_userspace_io. This does not
6349 * handle watchpoints yet, those would be handled in
6350 * the emulate_ops.
6351 */
d391f120
VK		 6352 if (!(emulation_type & EMULTYPE_SKIP) &&
6353 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6354 return r;
6355
9d74191a
TY		 6356 ctxt->interruptibility = 0;
6357 ctxt->have_exception = false;
e0ad0b47 6358 ctxt->exception.vector = -1;
9d74191a 6359 ctxt->perm_ok = false;
bbd9b64e 6360
b51e974f 6361 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6362
9d74191a 6363 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6364
e46479f8 6365 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6366 ++vcpu->stat.insn_emulation;
1d2887e2 6367 if (r != EMULATION_OK) {
4005996e
AK		 6368 if (emulation_type & EMULTYPE_TRAP_UD)
6369 return EMULATE_FAIL;
991eebf9
GN		 6370 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6371 emulation_type))
bbd9b64e 6372 return EMULATE_DONE;
6ea6e843
PB		 6373 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6374 return EMULATE_DONE;
6d77dbfc
GN		 6375 if (emulation_type & EMULTYPE_SKIP)
6376 return EMULATE_FAIL;
e2366171 6377 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6378 }
6379 }
6380
04789b66
LA		 6381 if ((emulation_type & EMULTYPE_VMWARE) &&
6382 !is_vmware_backdoor_opcode(ctxt))
6383 return EMULATE_FAIL;
6384
ba8afb6b 6385 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6386 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6387 if (ctxt->eflags & X86_EFLAGS_RF)
6388 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6389 return EMULATE_DONE;
6390 }
6391
1cb3f3ae
XG		 6392 if (retry_instruction(ctxt, cr2, emulation_type))
6393 return EMULATE_DONE;
6394
7ae441ea 6395 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6396 changes registers values during IO operation */
7ae441ea
GN		 6397 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6398 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6399 emulator_invalidate_register_cache(ctxt);
7ae441ea 6400 }
4d2179e1 6401
5cd21917 6402restart:
0f89b207
TL		 6403 /* Save the faulting GPA (cr2) in the address field */
6404 ctxt->exception.address = cr2;
6405
9d74191a 6406 r = x86_emulate_insn(ctxt);
bbd9b64e 6407
775fde86
JR		 6408 if (r == EMULATION_INTERCEPTED)
6409 return EMULATE_DONE;
6410
d2ddd1c4 6411 if (r == EMULATION_FAILED) {
991eebf9
GN		 6412 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6413 emulation_type))
c3cd7ffa
GN		 6414 return EMULATE_DONE;
6415
e2366171 6416 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6417 }
6418
9d74191a 6419 if (ctxt->have_exception) {
d2ddd1c4 6420 r = EMULATE_DONE;
ef54bcfe
PB		 6421 if (inject_emulated_exception(vcpu))
6422 return r;
d2ddd1c4 6423 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6424 if (!vcpu->arch.pio.in) {
6425 /* FIXME: return into emulator if single-stepping. */
3457e419 6426 vcpu->arch.pio.count = 0;
0912c977 6427 } else {
7ae441ea 6428 writeback = false;
716d51ab
GN		 6429 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6430 }
ac0a48c3 6431 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6432 } else if (vcpu->mmio_needed) {
6433 if (!vcpu->mmio_is_write)
6434 writeback = false;
ac0a48c3 6435 r = EMULATE_USER_EXIT;
716d51ab 6436 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6437 } else if (r == EMULATION_RESTART)
5cd21917 6438 goto restart;
d2ddd1c4
GN		 6439 else
6440 r = EMULATE_DONE;
f850e2e6 6441
7ae441ea 6442 if (writeback) {
6addfc42 6443 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6444 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6445 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6446 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6447 if (r == EMULATE_DONE &&
6448 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6449 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6450 if (!ctxt->have_exception ||
6451 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6452 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6453
6454 /*
6455 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6456 * do nothing, and it will be requested again as soon as
6457 * the shadow expires. But we still need to check here,
6458 * because POPF has no interrupt shadow.
6459 */
6460 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6461 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6462 } else
6463 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6464
6465 return r;
de7d789a 6466}
c60658d1
SC		 6467
6468int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6469{
6470 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6471}
6472EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6473
6474int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6475 void *insn, int insn_len)
6476{
6477 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6478}
6479EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6480
dca7f128
SC		 6481static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6482 unsigned short port)
de7d789a 6483{
cf8f70bf 6484 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6485 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6486 size, port, &val, 1);
cf8f70bf 6487 /* do not return to emulator after return from userspace */
7972995b 6488 vcpu->arch.pio.count = 0;
de7d789a
CO		 6489 return ret;
6490}
de7d789a 6491
8370c3d0
TL		 6492static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6493{
6494 unsigned long val;
6495
6496 /* We should only ever be called with arch.pio.count equal to 1 */
6497 BUG_ON(vcpu->arch.pio.count != 1);
6498
6499 /* For size less than 4 we merge, else we zero extend */
6500 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6501 : 0;
6502
6503 /*
6504 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6505 * the copy and tracing
6506 */
6507 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6508 vcpu->arch.pio.port, &val, 1);
6509 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6510
6511 return 1;
6512}
6513
dca7f128
SC		 6514static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6515 unsigned short port)
8370c3d0
TL		 6516{
6517 unsigned long val;
6518 int ret;
6519
6520 /* For size less than 4 we merge, else we zero extend */
6521 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6522
6523 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6524 &val, 1);
6525 if (ret) {
6526 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6527 return ret;
6528 }
6529
6530 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6531
6532 return 0;
6533}
dca7f128
SC		 6534
6535int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6536{
6537 int ret = kvm_skip_emulated_instruction(vcpu);
6538
6539 /*
6540 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6541 * KVM_EXIT_DEBUG here.
6542 */
6543 if (in)
6544 return kvm_fast_pio_in(vcpu, size, port) && ret;
6545 else
6546 return kvm_fast_pio_out(vcpu, size, port) && ret;
6547}
6548EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6549
251a5fd6 6550static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6551{
0a3aee0d 6552 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6553 return 0;
8cfdc000
ZA		 6554}
6555
6556static void tsc_khz_changed(void *data)
c8076604 6557{
8cfdc000
ZA		 6558 struct cpufreq_freqs *freq = data;
6559 unsigned long khz = 0;
6560
6561 if (data)
6562 khz = freq->new;
6563 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6564 khz = cpufreq_quick_get(raw_smp_processor_id());
6565 if (!khz)
6566 khz = tsc_khz;
0a3aee0d 6567 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6568}
6569
5fa4ec9c 6570#ifdef CONFIG_X86_64
0092e434
VK		 6571static void kvm_hyperv_tsc_notifier(void)
6572{
0092e434
VK		 6573 struct kvm *kvm;
6574 struct kvm_vcpu *vcpu;
6575 int cpu;
6576
6577 spin_lock(&kvm_lock);
6578 list_for_each_entry(kvm, &vm_list, vm_list)
6579 kvm_make_mclock_inprogress_request(kvm);
6580
6581 hyperv_stop_tsc_emulation();
6582
6583 /* TSC frequency always matches when on Hyper-V */
6584 for_each_present_cpu(cpu)
6585 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6586 kvm_max_guest_tsc_khz = tsc_khz;
6587
6588 list_for_each_entry(kvm, &vm_list, vm_list) {
6589 struct kvm_arch *ka = &kvm->arch;
6590
6591 spin_lock(&ka->pvclock_gtod_sync_lock);
6592
6593 pvclock_update_vm_gtod_copy(kvm);
6594
6595 kvm_for_each_vcpu(cpu, vcpu, kvm)
6596 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6597
6598 kvm_for_each_vcpu(cpu, vcpu, kvm)
6599 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6600
6601 spin_unlock(&ka->pvclock_gtod_sync_lock);
6602 }
6603 spin_unlock(&kvm_lock);
0092e434 6604}
5fa4ec9c 6605#endif
0092e434 6606
c8076604
GH		 6607static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6608 void *data)
6609{
6610 struct cpufreq_freqs *freq = data;
6611 struct kvm *kvm;
6612 struct kvm_vcpu *vcpu;
6613 int i, send_ipi = 0;
6614
8cfdc000
ZA		 6615 /*
6616 * We allow guests to temporarily run on slowing clocks,
6617 * provided we notify them after, or to run on accelerating
6618 * clocks, provided we notify them before. Thus time never
6619 * goes backwards.
6620 *
6621 * However, we have a problem. We can't atomically update
6622 * the frequency of a given CPU from this function; it is
6623 * merely a notifier, which can be called from any CPU.
6624 * Changing the TSC frequency at arbitrary points in time
6625 * requires a recomputation of local variables related to
6626 * the TSC for each VCPU. We must flag these local variables
6627 * to be updated and be sure the update takes place with the
6628 * new frequency before any guests proceed.
6629 *
6630 * Unfortunately, the combination of hotplug CPU and frequency
6631 * change creates an intractable locking scenario; the order
6632 * of when these callouts happen is undefined with respect to
6633 * CPU hotplug, and they can race with each other. As such,
6634 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6635 * undefined; you can actually have a CPU frequency change take
6636 * place in between the computation of X and the setting of the
6637 * variable. To protect against this problem, all updates of
6638 * the per_cpu tsc_khz variable are done in an interrupt
6639 * protected IPI, and all callers wishing to update the value
6640 * must wait for a synchronous IPI to complete (which is trivial
6641 * if the caller is on the CPU already). This establishes the
6642 * necessary total order on variable updates.
6643 *
6644 * Note that because a guest time update may take place
6645 * anytime after the setting of the VCPU's request bit, the
6646 * correct TSC value must be set before the request. However,
6647 * to ensure the update actually makes it to any guest which
6648 * starts running in hardware virtualization between the set
6649 * and the acquisition of the spinlock, we must also ping the
6650 * CPU after setting the request bit.
6651 *
6652 */
6653
c8076604
GH		 6654 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6655 return 0;
6656 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6657 return 0;
8cfdc000
ZA		 6658
6659 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6660
2f303b74 6661 spin_lock(&kvm_lock);
c8076604 6662 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6663 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6664 if (vcpu->cpu != freq->cpu)
6665 continue;
c285545f 6666 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6667 if (vcpu->cpu != smp_processor_id())
8cfdc000 6668 send_ipi = 1;
c8076604
GH		 6669 }
6670 }
2f303b74 6671 spin_unlock(&kvm_lock);
c8076604
GH		 6672
6673 if (freq->old < freq->new && send_ipi) {
6674 /*
6675 * We upscale the frequency. Must make the guest
6676 * doesn't see old kvmclock values while running with
6677 * the new frequency, otherwise we risk the guest sees
6678 * time go backwards.
6679 *
6680 * In case we update the frequency for another cpu
6681 * (which might be in guest context) send an interrupt
6682 * to kick the cpu out of guest context. Next time
6683 * guest context is entered kvmclock will be updated,
6684 * so the guest will not see stale values.
6685 */
8cfdc000 6686 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6687 }
6688 return 0;
6689}
6690
6691static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6692 .notifier_call = kvmclock_cpufreq_notifier
6693};
6694
251a5fd6 6695static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6696{
251a5fd6
SAS		 6697 tsc_khz_changed(NULL);
6698 return 0;
8cfdc000
ZA		 6699}
6700
b820cc0c
ZA		 6701static void kvm_timer_init(void)
6702{
c285545f 6703 max_tsc_khz = tsc_khz;
460dd42e 6704
b820cc0c 6705 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6706#ifdef CONFIG_CPU_FREQ
6707 struct cpufreq_policy policy;
758f588d
BP		 6708 int cpu;
6709
c285545f 6710 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6711 cpu = get_cpu();
6712 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6713 if (policy.cpuinfo.max_freq)
6714 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6715 put_cpu();
c285545f 6716#endif
b820cc0c
ZA		 6717 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6718 CPUFREQ_TRANSITION_NOTIFIER);
6719 }
c285545f 6720 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6721
73c1b41e 6722 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6723 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6724}
6725
dd60d217
AK		 6726DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6727EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6728
f5132b01 6729int kvm_is_in_guest(void)
ff9d07a0 6730{
086c9855 6731 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6732}
6733
6734static int kvm_is_user_mode(void)
6735{
6736 int user_mode = 3;
dcf46b94 6737
086c9855
AS		 6738 if (__this_cpu_read(current_vcpu))
6739 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6740
ff9d07a0
ZY		 6741 return user_mode != 0;
6742}
6743
6744static unsigned long kvm_get_guest_ip(void)
6745{
6746 unsigned long ip = 0;
dcf46b94 6747
086c9855
AS		 6748 if (__this_cpu_read(current_vcpu))
6749 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6750
ff9d07a0
ZY		 6751 return ip;
6752}
6753
6754static struct perf_guest_info_callbacks kvm_guest_cbs = {
6755 .is_in_guest = kvm_is_in_guest,
6756 .is_user_mode = kvm_is_user_mode,
6757 .get_guest_ip = kvm_get_guest_ip,
6758};
6759
ce88decf
XG		 6760static void kvm_set_mmio_spte_mask(void)
6761{
6762 u64 mask;
6763 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6764
6765 /*
6766 * Set the reserved bits and the present bit of an paging-structure
6767 * entry to generate page fault with PFER.RSV = 1.
6768 */
28a1f3ac
JS		 6769
6770 /*
6771 * Mask the uppermost physical address bit, which would be reserved as
6772 * long as the supported physical address width is less than 52.
6773 */
6774 mask = 1ull << 51;
885032b9 6775
885032b9 6776 /* Set the present bit. */
ce88decf
XG		 6777 mask |= 1ull;
6778
ce88decf
XG		 6779 /*
6780 * If reserved bit is not supported, clear the present bit to disable
6781 * mmio page fault.
6782 */
7288bde1 6783 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
ce88decf 6784 mask &= ~1ull;
ce88decf 6785
dcdca5fe 6786 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6787}
6788
16e8d74d
MT		 6789#ifdef CONFIG_X86_64
6790static void pvclock_gtod_update_fn(struct work_struct *work)
6791{
d828199e
MT		 6792 struct kvm *kvm;
6793
6794 struct kvm_vcpu *vcpu;
6795 int i;
6796
2f303b74 6797 spin_lock(&kvm_lock);
d828199e
MT		 6798 list_for_each_entry(kvm, &vm_list, vm_list)
6799 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6800 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6801 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6802 spin_unlock(&kvm_lock);
16e8d74d
MT		 6803}
6804
6805static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6806
6807/*
6808 * Notification about pvclock gtod data update.
6809 */
6810static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6811 void *priv)
6812{
6813 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6814 struct timekeeper *tk = priv;
6815
6816 update_pvclock_gtod(tk);
6817
6818 /* disable master clock if host does not trust, or does not
b0c39dc6 6819 * use, TSC based clocksource.
16e8d74d 6820 */
b0c39dc6 6821 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6822 atomic_read(&kvm_guest_has_master_clock) != 0)
6823 queue_work(system_long_wq, &pvclock_gtod_work);
6824
6825 return 0;
6826}
6827
6828static struct notifier_block pvclock_gtod_notifier = {
6829 .notifier_call = pvclock_gtod_notify,
6830};
6831#endif
6832
f8c16bba 6833int kvm_arch_init(void *opaque)
043405e1 6834{
b820cc0c 6835 int r;
6b61edf7 6836 struct kvm_x86_ops *ops = opaque;
f8c16bba 6837
f8c16bba
ZX		 6838 if (kvm_x86_ops) {
6839 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6840 r = -EEXIST;
6841 goto out;
f8c16bba
ZX		 6842 }
6843
6844 if (!ops->cpu_has_kvm_support()) {
6845 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6846 r = -EOPNOTSUPP;
6847 goto out;
f8c16bba
ZX		 6848 }
6849 if (ops->disabled_by_bios()) {
6850 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6851 r = -EOPNOTSUPP;
6852 goto out;
f8c16bba
ZX		 6853 }
6854
013f6a5d
MT		 6855 r = -ENOMEM;
6856 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6857 if (!shared_msrs) {
6858 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6859 goto out;
6860 }
6861
97db56ce
AK		 6862 r = kvm_mmu_module_init();
6863 if (r)
013f6a5d 6864 goto out_free_percpu;
97db56ce 6865
ce88decf 6866 kvm_set_mmio_spte_mask();
97db56ce 6867
f8c16bba 6868 kvm_x86_ops = ops;
920c8377 6869
7b52345e 6870 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6871 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6872 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6873 kvm_timer_init();
c8076604 6874
ff9d07a0
ZY		 6875 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6876
d366bf7e 6877 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6878 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6879
c5cc421b 6880 kvm_lapic_init();
16e8d74d
MT		 6881#ifdef CONFIG_X86_64
6882 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6883
5fa4ec9c 6884 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6885 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6886#endif
6887
f8c16bba 6888 return 0;
56c6d28a 6889
013f6a5d
MT		 6890out_free_percpu:
6891 free_percpu(shared_msrs);
56c6d28a 6892out:
56c6d28a 6893 return r;
043405e1 6894}
8776e519 6895
f8c16bba
ZX		 6896void kvm_arch_exit(void)
6897{
0092e434 6898#ifdef CONFIG_X86_64
5fa4ec9c 6899 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6900 clear_hv_tscchange_cb();
6901#endif
cef84c30 6902 kvm_lapic_exit();
ff9d07a0
ZY		 6903 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6904
888d256e
JK		 6905 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6906 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6907 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6908 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6909#ifdef CONFIG_X86_64
6910 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6911#endif
f8c16bba 6912 kvm_x86_ops = NULL;
56c6d28a 6913 kvm_mmu_module_exit();
013f6a5d 6914 free_percpu(shared_msrs);
56c6d28a 6915}
f8c16bba 6916
5cb56059 6917int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6918{
6919 ++vcpu->stat.halt_exits;
35754c98 6920 if (lapic_in_kernel(vcpu)) {
a4535290 6921 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6922 return 1;
6923 } else {
6924 vcpu->run->exit_reason = KVM_EXIT_HLT;
6925 return 0;
6926 }
6927}
5cb56059
JS		 6928EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6929
6930int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6931{
6affcbed
KH		 6932 int ret = kvm_skip_emulated_instruction(vcpu);
6933 /*
6934 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6935 * KVM_EXIT_DEBUG here.
6936 */
6937 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6938}
8776e519
HB		 6939EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6940
8ef81a9a 6941#ifdef CONFIG_X86_64
55dd00a7
MT		 6942static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6943 unsigned long clock_type)
6944{
6945 struct kvm_clock_pairing clock_pairing;
899a31f5 6946 struct timespec64 ts;
80fbd89c 6947 u64 cycle;
55dd00a7
MT		 6948 int ret;
6949
6950 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6951 return -KVM_EOPNOTSUPP;
6952
6953 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6954 return -KVM_EOPNOTSUPP;
6955
6956 clock_pairing.sec = ts.tv_sec;
6957 clock_pairing.nsec = ts.tv_nsec;
6958 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6959 clock_pairing.flags = 0;
bcbfbd8e 6960 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 6961
6962 ret = 0;
6963 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6964 sizeof(struct kvm_clock_pairing)))
6965 ret = -KVM_EFAULT;
6966
6967 return ret;
6968}
8ef81a9a 6969#endif
55dd00a7 6970
6aef266c
SV		 6971/*
6972 * kvm_pv_kick_cpu_op: Kick a vcpu.
6973 *
6974 * @apicid - apicid of vcpu to be kicked.
6975 */
6976static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6977{
24d2166b 6978 struct kvm_lapic_irq lapic_irq;
6aef266c 6979
24d2166b
R		 6980 lapic_irq.shorthand = 0;
6981 lapic_irq.dest_mode = 0;
ebd28fcb 6982 lapic_irq.level = 0;
24d2166b 6983 lapic_irq.dest_id = apicid;
93bbf0b8 6984 lapic_irq.msi_redir_hint = false;
6aef266c 6985
24d2166b 6986 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6987 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6988}
6989
d62caabb
AS		 6990void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6991{
6992 vcpu->arch.apicv_active = false;
6993 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6994}
6995
8776e519
HB		 6996int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6997{
6998 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6999 int op_64_bit;
8776e519 7000
696ca779
RK		 7001 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7002 return kvm_hv_hypercall(vcpu);
55cd8e5a 7003
5fdbf976
MT		 7004 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
7005 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
7006 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
7007 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
7008 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 7009
229456fc 7010 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7011
a449c7aa
NA		 7012 op_64_bit = is_64_bit_mode(vcpu);
7013 if (!op_64_bit) {
8776e519
HB		 7014 nr &= 0xFFFFFFFF;
7015 a0 &= 0xFFFFFFFF;
7016 a1 &= 0xFFFFFFFF;
7017 a2 &= 0xFFFFFFFF;
7018 a3 &= 0xFFFFFFFF;
7019 }
7020
07708c4a
JK		 7021 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7022 ret = -KVM_EPERM;
696ca779 7023 goto out;
07708c4a
JK		 7024 }
7025
8776e519 7026 switch (nr) {
b93463aa
AK		 7027 case KVM_HC_VAPIC_POLL_IRQ:
7028 ret = 0;
7029 break;
6aef266c
SV		 7030 case KVM_HC_KICK_CPU:
7031 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7032 ret = 0;
7033 break;
8ef81a9a 7034#ifdef CONFIG_X86_64
55dd00a7
MT		 7035 case KVM_HC_CLOCK_PAIRING:
7036 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7037 break;
4180bf1b
WL		 7038 case KVM_HC_SEND_IPI:
7039 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7040 break;
8ef81a9a 7041#endif
8776e519
HB		 7042 default:
7043 ret = -KVM_ENOSYS;
7044 break;
7045 }
696ca779 7046out:
a449c7aa
NA		 7047 if (!op_64_bit)
7048 ret = (u32)ret;
5fdbf976 7049 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 7050
f11c3a8d 7051 ++vcpu->stat.hypercalls;
6356ee0c 7052 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7053}
7054EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7055
b6785def 7056static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7057{
d6aa1000 7058 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7059 char instruction[3];
5fdbf976 7060 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7061
8776e519 7062 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7063
ce2e852e
DV		 7064 return emulator_write_emulated(ctxt, rip, instruction, 3,
7065 &ctxt->exception);
8776e519
HB		 7066}
7067
851ba692 7068static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7069{
782d422b
MG		 7070 return vcpu->run->request_interrupt_window &&
7071 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7072}
7073
851ba692 7074static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7075{
851ba692
AK		 7076 struct kvm_run *kvm_run = vcpu->run;
7077
91586a3b 7078 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7079 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7080 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7081 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7082 kvm_run->ready_for_interrupt_injection =
7083 pic_in_kernel(vcpu->kvm) ||
782d422b 7084 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7085}
7086
95ba8273
GN		 7087static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7088{
7089 int max_irr, tpr;
7090
7091 if (!kvm_x86_ops->update_cr8_intercept)
7092 return;
7093
bce87cce 7094 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7095 return;
7096
d62caabb
AS		 7097 if (vcpu->arch.apicv_active)
7098 return;
7099
8db3baa2
GN		 7100 if (!vcpu->arch.apic->vapic_addr)
7101 max_irr = kvm_lapic_find_highest_irr(vcpu);
7102 else
7103 max_irr = -1;
95ba8273
GN		 7104
7105 if (max_irr != -1)
7106 max_irr >>= 4;
7107
7108 tpr = kvm_lapic_get_cr8(vcpu);
7109
7110 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7111}
7112
b6b8a145 7113static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7114{
b6b8a145
JK		 7115 int r;
7116
95ba8273 7117 /* try to reinject previous events if any */
664f8e26 7118
1a680e35
LA		 7119 if (vcpu->arch.exception.injected)
7120 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7121 /*
a042c26f
LA		 7122 * Do not inject an NMI or interrupt if there is a pending
7123 * exception. Exceptions and interrupts are recognized at
7124 * instruction boundaries, i.e. the start of an instruction.
7125 * Trap-like exceptions, e.g. #DB, have higher priority than
7126 * NMIs and interrupts, i.e. traps are recognized before an
7127 * NMI/interrupt that's pending on the same instruction.
7128 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7129 * priority, but are only generated (pended) during instruction
7130 * execution, i.e. a pending fault-like exception means the
7131 * fault occurred on the *previous* instruction and must be
7132 * serviced prior to recognizing any new events in order to
7133 * fully complete the previous instruction.
664f8e26 7134 */
1a680e35
LA		 7135 else if (!vcpu->arch.exception.pending) {
7136 if (vcpu->arch.nmi_injected)
664f8e26 7137 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7138 else if (vcpu->arch.interrupt.injected)
664f8e26 7139 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7140 }
7141
1a680e35
LA		 7142 /*
7143 * Call check_nested_events() even if we reinjected a previous event
7144 * in order for caller to determine if it should require immediate-exit
7145 * from L2 to L1 due to pending L1 events which require exit
7146 * from L2 to L1.
7147 */
664f8e26
WL		 7148 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7149 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7150 if (r != 0)
7151 return r;
7152 }
7153
7154 /* try to inject new event if pending */
b59bb7bd 7155 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7156 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7157 vcpu->arch.exception.has_error_code,
7158 vcpu->arch.exception.error_code);
d6e8c854 7159
1a680e35 7160 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7161 vcpu->arch.exception.pending = false;
7162 vcpu->arch.exception.injected = true;
7163
d6e8c854
NA		 7164 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7165 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7166 X86_EFLAGS_RF);
7167
f10c729f
JM		 7168 if (vcpu->arch.exception.nr == DB_VECTOR) {
7169 /*
7170 * This code assumes that nSVM doesn't use
7171 * check_nested_events(). If it does, the
7172 * DR6/DR7 changes should happen before L1
7173 * gets a #VMEXIT for an intercepted #DB in
7174 * L2. (Under VMX, on the other hand, the
7175 * DR6/DR7 changes should not happen in the
7176 * event of a VM-exit to L1 for an intercepted
7177 * #DB in L2.)
7178 */
7179 kvm_deliver_exception_payload(vcpu);
7180 if (vcpu->arch.dr7 & DR7_GD) {
7181 vcpu->arch.dr7 &= ~DR7_GD;
7182 kvm_update_dr7(vcpu);
7183 }
6bdf0662
NA		 7184 }
7185
cfcd20e5 7186 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7187 }
7188
7189 /* Don't consider new event if we re-injected an event */
7190 if (kvm_event_needs_reinjection(vcpu))
7191 return 0;
7192
7193 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7194 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7195 vcpu->arch.smi_pending = false;
52797bf9 7196 ++vcpu->arch.smi_count;
ee2cd4b7 7197 enter_smm(vcpu);
c43203ca 7198 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7199 --vcpu->arch.nmi_pending;
7200 vcpu->arch.nmi_injected = true;
7201 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7202 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7203 /*
7204 * Because interrupts can be injected asynchronously, we are
7205 * calling check_nested_events again here to avoid a race condition.
7206 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7207 * proposal and current concerns. Perhaps we should be setting
7208 * KVM_REQ_EVENT only on certain events and not unconditionally?
7209 */
7210 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7211 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7212 if (r != 0)
7213 return r;
7214 }
95ba8273 7215 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7216 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7217 false);
7218 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7219 }
7220 }
ee2cd4b7 7221
b6b8a145 7222 return 0;
95ba8273
GN		 7223}
7224
7460fb4a
AK		 7225static void process_nmi(struct kvm_vcpu *vcpu)
7226{
7227 unsigned limit = 2;
7228
7229 /*
7230 * x86 is limited to one NMI running, and one NMI pending after it.
7231 * If an NMI is already in progress, limit further NMIs to just one.
7232 * Otherwise, allow two (and we'll inject the first one immediately).
7233 */
7234 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7235 limit = 1;
7236
7237 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7238 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7239 kvm_make_request(KVM_REQ_EVENT, vcpu);
7240}
7241
ee2cd4b7 7242static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7243{
7244 u32 flags = 0;
7245 flags |= seg->g << 23;
7246 flags |= seg->db << 22;
7247 flags |= seg->l << 21;
7248 flags |= seg->avl << 20;
7249 flags |= seg->present << 15;
7250 flags |= seg->dpl << 13;
7251 flags |= seg->s << 12;
7252 flags |= seg->type << 8;
7253 return flags;
7254}
7255
ee2cd4b7 7256static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7257{
7258 struct kvm_segment seg;
7259 int offset;
7260
7261 kvm_get_segment(vcpu, &seg, n);
7262 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7263
7264 if (n < 3)
7265 offset = 0x7f84 + n * 12;
7266 else
7267 offset = 0x7f2c + (n - 3) * 12;
7268
7269 put_smstate(u32, buf, offset + 8, seg.base);
7270 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7271 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7272}
7273
efbb288a 7274#ifdef CONFIG_X86_64
ee2cd4b7 7275static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7276{
7277 struct kvm_segment seg;
7278 int offset;
7279 u16 flags;
7280
7281 kvm_get_segment(vcpu, &seg, n);
7282 offset = 0x7e00 + n * 16;
7283
ee2cd4b7 7284 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7285 put_smstate(u16, buf, offset, seg.selector);
7286 put_smstate(u16, buf, offset + 2, flags);
7287 put_smstate(u32, buf, offset + 4, seg.limit);
7288 put_smstate(u64, buf, offset + 8, seg.base);
7289}
efbb288a 7290#endif
660a5d51 7291
ee2cd4b7 7292static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7293{
7294 struct desc_ptr dt;
7295 struct kvm_segment seg;
7296 unsigned long val;
7297 int i;
7298
7299 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7300 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7301 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7302 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7303
7304 for (i = 0; i < 8; i++)
7305 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7306
7307 kvm_get_dr(vcpu, 6, &val);
7308 put_smstate(u32, buf, 0x7fcc, (u32)val);
7309 kvm_get_dr(vcpu, 7, &val);
7310 put_smstate(u32, buf, 0x7fc8, (u32)val);
7311
7312 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7313 put_smstate(u32, buf, 0x7fc4, seg.selector);
7314 put_smstate(u32, buf, 0x7f64, seg.base);
7315 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7316 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7317
7318 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7319 put_smstate(u32, buf, 0x7fc0, seg.selector);
7320 put_smstate(u32, buf, 0x7f80, seg.base);
7321 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7322 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7323
7324 kvm_x86_ops->get_gdt(vcpu, &dt);
7325 put_smstate(u32, buf, 0x7f74, dt.address);
7326 put_smstate(u32, buf, 0x7f70, dt.size);
7327
7328 kvm_x86_ops->get_idt(vcpu, &dt);
7329 put_smstate(u32, buf, 0x7f58, dt.address);
7330 put_smstate(u32, buf, 0x7f54, dt.size);
7331
7332 for (i = 0; i < 6; i++)
ee2cd4b7 7333 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7334
7335 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7336
7337 /* revision id */
7338 put_smstate(u32, buf, 0x7efc, 0x00020000);
7339 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7340}
7341
ee2cd4b7 7342static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7343{
7344#ifdef CONFIG_X86_64
7345 struct desc_ptr dt;
7346 struct kvm_segment seg;
7347 unsigned long val;
7348 int i;
7349
7350 for (i = 0; i < 16; i++)
7351 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7352
7353 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7354 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7355
7356 kvm_get_dr(vcpu, 6, &val);
7357 put_smstate(u64, buf, 0x7f68, val);
7358 kvm_get_dr(vcpu, 7, &val);
7359 put_smstate(u64, buf, 0x7f60, val);
7360
7361 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7362 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7363 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7364
7365 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7366
7367 /* revision id */
7368 put_smstate(u32, buf, 0x7efc, 0x00020064);
7369
7370 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7371
7372 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7373 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7374 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7375 put_smstate(u32, buf, 0x7e94, seg.limit);
7376 put_smstate(u64, buf, 0x7e98, seg.base);
7377
7378 kvm_x86_ops->get_idt(vcpu, &dt);
7379 put_smstate(u32, buf, 0x7e84, dt.size);
7380 put_smstate(u64, buf, 0x7e88, dt.address);
7381
7382 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7383 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7384 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7385 put_smstate(u32, buf, 0x7e74, seg.limit);
7386 put_smstate(u64, buf, 0x7e78, seg.base);
7387
7388 kvm_x86_ops->get_gdt(vcpu, &dt);
7389 put_smstate(u32, buf, 0x7e64, dt.size);
7390 put_smstate(u64, buf, 0x7e68, dt.address);
7391
7392 for (i = 0; i < 6; i++)
ee2cd4b7 7393 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7394#else
7395 WARN_ON_ONCE(1);
7396#endif
7397}
7398
ee2cd4b7 7399static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7400{
660a5d51 7401 struct kvm_segment cs, ds;
18c3626e 7402 struct desc_ptr dt;
660a5d51
PB		 7403 char buf[512];
7404 u32 cr0;
7405
660a5d51 7406 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7407 memset(buf, 0, 512);
d6321d49 7408 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7409 enter_smm_save_state_64(vcpu, buf);
660a5d51 7410 else
ee2cd4b7 7411 enter_smm_save_state_32(vcpu, buf);
660a5d51 7412
0234bf88
LP		 7413 /*
7414 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7415 * vCPU state (e.g. leave guest mode) after we've saved the state into
7416 * the SMM state-save area.
7417 */
7418 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7419
7420 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7421 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7422
7423 if (kvm_x86_ops->get_nmi_mask(vcpu))
7424 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7425 else
7426 kvm_x86_ops->set_nmi_mask(vcpu, true);
7427
7428 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7429 kvm_rip_write(vcpu, 0x8000);
7430
7431 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7432 kvm_x86_ops->set_cr0(vcpu, cr0);
7433 vcpu->arch.cr0 = cr0;
7434
7435 kvm_x86_ops->set_cr4(vcpu, 0);
7436
18c3626e
PB		 7437 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7438 dt.address = dt.size = 0;
7439 kvm_x86_ops->set_idt(vcpu, &dt);
7440
660a5d51
PB		 7441 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7442
7443 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7444 cs.base = vcpu->arch.smbase;
7445
7446 ds.selector = 0;
7447 ds.base = 0;
7448
7449 cs.limit = ds.limit = 0xffffffff;
7450 cs.type = ds.type = 0x3;
7451 cs.dpl = ds.dpl = 0;
7452 cs.db = ds.db = 0;
7453 cs.s = ds.s = 1;
7454 cs.l = ds.l = 0;
7455 cs.g = ds.g = 1;
7456 cs.avl = ds.avl = 0;
7457 cs.present = ds.present = 1;
7458 cs.unusable = ds.unusable = 0;
7459 cs.padding = ds.padding = 0;
7460
7461 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7462 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7463 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7464 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7465 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7466 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7467
d6321d49 7468 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7469 kvm_x86_ops->set_efer(vcpu, 0);
7470
7471 kvm_update_cpuid(vcpu);
7472 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7473}
7474
ee2cd4b7 7475static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7476{
7477 vcpu->arch.smi_pending = true;
7478 kvm_make_request(KVM_REQ_EVENT, vcpu);
7479}
7480
2860c4b1
PB		 7481void kvm_make_scan_ioapic_request(struct kvm *kvm)
7482{
7483 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7484}
7485
3d81bc7e 7486static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7487{
3d81bc7e
YZ		 7488 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7489 return;
c7c9c56c 7490
6308630b 7491 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7492
b053b2ae 7493 if (irqchip_split(vcpu->kvm))
6308630b 7494 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7495 else {
fa59cc00 7496 if (vcpu->arch.apicv_active)
d62caabb 7497 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7498 if (ioapic_in_kernel(vcpu->kvm))
7499 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7500 }
e40ff1d6
LA		 7501
7502 if (is_guest_mode(vcpu))
7503 vcpu->arch.load_eoi_exitmap_pending = true;
7504 else
7505 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7506}
7507
7508static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7509{
7510 u64 eoi_exit_bitmap[4];
7511
7512 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7513 return;
7514
5c919412
AS		 7515 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7516 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7517 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7518}
7519
93065ac7
MH		 7520int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7521 unsigned long start, unsigned long end,
7522 bool blockable)
b1394e74
RK		 7523{
7524 unsigned long apic_address;
7525
7526 /*
7527 * The physical address of apic access page is stored in the VMCS.
7528 * Update it when it becomes invalid.
7529 */
7530 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7531 if (start <= apic_address && apic_address < end)
7532 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7533
7534 return 0;
b1394e74
RK		 7535}
7536
4256f43f
TC		 7537void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7538{
c24ae0dc
TC		 7539 struct page *page = NULL;
7540
35754c98 7541 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7542 return;
7543
4256f43f
TC		 7544 if (!kvm_x86_ops->set_apic_access_page_addr)
7545 return;
7546
c24ae0dc 7547 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7548 if (is_error_page(page))
7549 return;
c24ae0dc
TC		 7550 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7551
7552 /*
7553 * Do not pin apic access page in memory, the MMU notifier
7554 * will call us again if it is migrated or swapped out.
7555 */
7556 put_page(page);
4256f43f
TC		 7557}
7558EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7559
d264ee0c
SC		 7560void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7561{
7562 smp_send_reschedule(vcpu->cpu);
7563}
7564EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7565
9357d939 7566/*
362c698f 7567 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7568 * exiting to the userspace. Otherwise, the value will be returned to the
7569 * userspace.
7570 */
851ba692 7571static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7572{
7573 int r;
62a193ed
MG		 7574 bool req_int_win =
7575 dm_request_for_irq_injection(vcpu) &&
7576 kvm_cpu_accept_dm_intr(vcpu);
7577
730dca42 7578 bool req_immediate_exit = false;
b6c7a5dc 7579
2fa6e1e1 7580 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7581 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7582 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7583 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7584 kvm_mmu_unload(vcpu);
a8eeb04a 7585 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7586 __kvm_migrate_timers(vcpu);
d828199e
MT		 7587 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7588 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7589 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7590 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7591 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7592 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7593 if (unlikely(r))
7594 goto out;
7595 }
a8eeb04a 7596 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7597 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7598 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7599 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7600 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7601 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7602 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7603 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7604 r = 0;
7605 goto out;
7606 }
a8eeb04a 7607 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7608 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7609 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7610 r = 0;
7611 goto out;
7612 }
af585b92
GN		 7613 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7614 /* Page is swapped out. Do synthetic halt */
7615 vcpu->arch.apf.halted = true;
7616 r = 1;
7617 goto out;
7618 }
c9aaa895
GC		 7619 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7620 record_steal_time(vcpu);
64d60670
PB		 7621 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7622 process_smi(vcpu);
7460fb4a
AK		 7623 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7624 process_nmi(vcpu);
f5132b01 7625 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7626 kvm_pmu_handle_event(vcpu);
f5132b01 7627 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7628 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7629 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7630 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7631 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7632 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7633 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7634 vcpu->run->eoi.vector =
7635 vcpu->arch.pending_ioapic_eoi;
7636 r = 0;
7637 goto out;
7638 }
7639 }
3d81bc7e
YZ		 7640 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7641 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7642 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7643 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7644 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7645 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7646 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7647 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7648 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7649 r = 0;
7650 goto out;
7651 }
e516cebb
AS		 7652 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7653 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7654 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7655 r = 0;
7656 goto out;
7657 }
db397571
AS		 7658 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7659 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7660 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7661 r = 0;
7662 goto out;
7663 }
f3b138c5
AS		 7664
7665 /*
7666 * KVM_REQ_HV_STIMER has to be processed after
7667 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7668 * depend on the guest clock being up-to-date
7669 */
1f4b34f8
AS		 7670 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7671 kvm_hv_process_stimers(vcpu);
2f52d58c 7672 }
b93463aa 7673
b463a6f7 7674 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7675 ++vcpu->stat.req_event;
66450a21
JK		 7676 kvm_apic_accept_events(vcpu);
7677 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7678 r = 1;
7679 goto out;
7680 }
7681
b6b8a145
JK		 7682 if (inject_pending_event(vcpu, req_int_win) != 0)
7683 req_immediate_exit = true;
321c5658 7684 else {
cc3d967f 7685 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7686 *
cc3d967f
LP		 7687 * SMIs have three cases:
7688 * 1) They can be nested, and then there is nothing to
7689 * do here because RSM will cause a vmexit anyway.
7690 * 2) There is an ISA-specific reason why SMI cannot be
7691 * injected, and the moment when this changes can be
7692 * intercepted.
7693 * 3) Or the SMI can be pending because
7694 * inject_pending_event has completed the injection
7695 * of an IRQ or NMI from the previous vmexit, and
7696 * then we request an immediate exit to inject the
7697 * SMI.
c43203ca
PB		 7698 */
7699 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7700 if (!kvm_x86_ops->enable_smi_window(vcpu))
7701 req_immediate_exit = true;
321c5658
YS		 7702 if (vcpu->arch.nmi_pending)
7703 kvm_x86_ops->enable_nmi_window(vcpu);
7704 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7705 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7706 WARN_ON(vcpu->arch.exception.pending);
321c5658 7707 }
b463a6f7
AK		 7708
7709 if (kvm_lapic_enabled(vcpu)) {
7710 update_cr8_intercept(vcpu);
7711 kvm_lapic_sync_to_vapic(vcpu);
7712 }
7713 }
7714
d8368af8
AK		 7715 r = kvm_mmu_reload(vcpu);
7716 if (unlikely(r)) {
d905c069 7717 goto cancel_injection;
d8368af8
AK		 7718 }
7719
b6c7a5dc
HB		 7720 preempt_disable();
7721
7722 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7723
7724 /*
7725 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7726 * IPI are then delayed after guest entry, which ensures that they
7727 * result in virtual interrupt delivery.
7728 */
7729 local_irq_disable();
6b7e2d09
XG		 7730 vcpu->mode = IN_GUEST_MODE;
7731
01b71917
MT		 7732 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7733
0f127d12 7734 /*
b95234c8 7735 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7736 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7737 *
7738 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7739 * pairs with the memory barrier implicit in pi_test_and_set_on
7740 * (see vmx_deliver_posted_interrupt).
7741 *
7742 * 3) This also orders the write to mode from any reads to the page
7743 * tables done while the VCPU is running. Please see the comment
7744 * in kvm_flush_remote_tlbs.
6b7e2d09 7745 */
01b71917 7746 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7747
b95234c8
PB		 7748 /*
7749 * This handles the case where a posted interrupt was
7750 * notified with kvm_vcpu_kick.
7751 */
fa59cc00
LA		 7752 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7753 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7754
2fa6e1e1 7755 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7756 || need_resched() || signal_pending(current)) {
6b7e2d09 7757 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7758 smp_wmb();
6c142801
AK		 7759 local_irq_enable();
7760 preempt_enable();
01b71917 7761 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7762 r = 1;
d905c069 7763 goto cancel_injection;
6c142801
AK		 7764 }
7765
fc5b7f3b
DM		 7766 kvm_load_guest_xcr0(vcpu);
7767
c43203ca
PB		 7768 if (req_immediate_exit) {
7769 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7770 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7771 }
d6185f20 7772
8b89fe1f 7773 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7774 if (lapic_timer_advance_ns)
7775 wait_lapic_expire(vcpu);
6edaa530 7776 guest_enter_irqoff();
b6c7a5dc 7777
42dbaa5a 7778 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7779 set_debugreg(0, 7);
7780 set_debugreg(vcpu->arch.eff_db[0], 0);
7781 set_debugreg(vcpu->arch.eff_db[1], 1);
7782 set_debugreg(vcpu->arch.eff_db[2], 2);
7783 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7784 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7785 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7786 }
b6c7a5dc 7787
851ba692 7788 kvm_x86_ops->run(vcpu);
b6c7a5dc 7789
c77fb5fe
PB		 7790 /*
7791 * Do this here before restoring debug registers on the host. And
7792 * since we do this before handling the vmexit, a DR access vmexit
7793 * can (a) read the correct value of the debug registers, (b) set
7794 * KVM_DEBUGREG_WONT_EXIT again.
7795 */
7796 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7797 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7798 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7799 kvm_update_dr0123(vcpu);
7800 kvm_update_dr6(vcpu);
7801 kvm_update_dr7(vcpu);
7802 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7803 }
7804
24f1e32c
FW		 7805 /*
7806 * If the guest has used debug registers, at least dr7
7807 * will be disabled while returning to the host.
7808 * If we don't have active breakpoints in the host, we don't
7809 * care about the messed up debug address registers. But if
7810 * we have some of them active, restore the old state.
7811 */
59d8eb53 7812 if (hw_breakpoint_active())
24f1e32c 7813 hw_breakpoint_restore();
42dbaa5a 7814
4ba76538 7815 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7816
6b7e2d09 7817 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7818 smp_wmb();
a547c6db 7819
fc5b7f3b
DM		 7820 kvm_put_guest_xcr0(vcpu);
7821
dd60d217 7822 kvm_before_interrupt(vcpu);
a547c6db 7823 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7824 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7825
7826 ++vcpu->stat.exits;
7827
f2485b3e 7828 guest_exit_irqoff();
b6c7a5dc 7829
f2485b3e 7830 local_irq_enable();
b6c7a5dc
HB		 7831 preempt_enable();
7832
f656ce01 7833 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7834
b6c7a5dc
HB		 7835 /*
7836 * Profile KVM exit RIPs:
7837 */
7838 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7839 unsigned long rip = kvm_rip_read(vcpu);
7840 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7841 }
7842
cc578287
ZA		 7843 if (unlikely(vcpu->arch.tsc_always_catchup))
7844 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7845
5cfb1d5a
MT		 7846 if (vcpu->arch.apic_attention)
7847 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7848
618232e2 7849 vcpu->arch.gpa_available = false;
851ba692 7850 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7851 return r;
7852
7853cancel_injection:
7854 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7855 if (unlikely(vcpu->arch.apic_attention))
7856 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7857out:
7858 return r;
7859}
b6c7a5dc 7860
362c698f
PB		 7861static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7862{
bf9f6ac8
FW		 7863 if (!kvm_arch_vcpu_runnable(vcpu) &&
7864 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7865 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7866 kvm_vcpu_block(vcpu);
7867 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7868
7869 if (kvm_x86_ops->post_block)
7870 kvm_x86_ops->post_block(vcpu);
7871
9c8fd1ba
PB		 7872 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7873 return 1;
7874 }
362c698f
PB		 7875
7876 kvm_apic_accept_events(vcpu);
7877 switch(vcpu->arch.mp_state) {
7878 case KVM_MP_STATE_HALTED:
7879 vcpu->arch.pv.pv_unhalted = false;
7880 vcpu->arch.mp_state =
7881 KVM_MP_STATE_RUNNABLE;
7882 case KVM_MP_STATE_RUNNABLE:
7883 vcpu->arch.apf.halted = false;
7884 break;
7885 case KVM_MP_STATE_INIT_RECEIVED:
7886 break;
7887 default:
7888 return -EINTR;
7889 break;
7890 }
7891 return 1;
7892}
09cec754 7893
5d9bc648
PB		 7894static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7895{
0ad3bed6
PB		 7896 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7897 kvm_x86_ops->check_nested_events(vcpu, false);
7898
5d9bc648
PB		 7899 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7900 !vcpu->arch.apf.halted);
7901}
7902
362c698f 7903static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7904{
7905 int r;
f656ce01 7906 struct kvm *kvm = vcpu->kvm;
d7690175 7907
f656ce01 7908 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 7909 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7910
362c698f 7911 for (;;) {
58f800d5 7912 if (kvm_vcpu_running(vcpu)) {
851ba692 7913 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7914 } else {
362c698f 7915 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7916 }
7917
09cec754
GN		 7918 if (r <= 0)
7919 break;
7920
72875d8a 7921 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7922 if (kvm_cpu_has_pending_timer(vcpu))
7923 kvm_inject_pending_timer_irqs(vcpu);
7924
782d422b
MG		 7925 if (dm_request_for_irq_injection(vcpu) &&
7926 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7927 r = 0;
7928 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7929 ++vcpu->stat.request_irq_exits;
362c698f 7930 break;
09cec754 7931 }
af585b92
GN		 7932
7933 kvm_check_async_pf_completion(vcpu);
7934
09cec754
GN		 7935 if (signal_pending(current)) {
7936 r = -EINTR;
851ba692 7937 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7938 ++vcpu->stat.signal_exits;
362c698f 7939 break;
09cec754
GN		 7940 }
7941 if (need_resched()) {
f656ce01 7942 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7943 cond_resched();
f656ce01 7944 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7945 }
b6c7a5dc
HB		 7946 }
7947
f656ce01 7948 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7949
7950 return r;
7951}
7952
716d51ab
GN		 7953static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7954{
7955 int r;
7956 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 7957 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 7958 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7959 if (r != EMULATE_DONE)
7960 return 0;
7961 return 1;
7962}
7963
7964static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7965{
7966 BUG_ON(!vcpu->arch.pio.count);
7967
7968 return complete_emulated_io(vcpu);
7969}
7970
f78146b0
AK		 7971/*
7972 * Implements the following, as a state machine:
7973 *
7974 * read:
7975 * for each fragment
87da7e66
XG		 7976 * for each mmio piece in the fragment
7977 * write gpa, len
7978 * exit
7979 * copy data
f78146b0
AK		 7980 * execute insn
7981 *
7982 * write:
7983 * for each fragment
87da7e66
XG		 7984 * for each mmio piece in the fragment
7985 * write gpa, len
7986 * copy data
7987 * exit
f78146b0 7988 */
716d51ab 7989static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7990{
7991 struct kvm_run *run = vcpu->run;
f78146b0 7992 struct kvm_mmio_fragment *frag;
87da7e66 7993 unsigned len;
5287f194 7994
716d51ab 7995 BUG_ON(!vcpu->mmio_needed);
5287f194 7996
716d51ab 7997 /* Complete previous fragment */
87da7e66
XG		 7998 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7999 len = min(8u, frag->len);
716d51ab 8000 if (!vcpu->mmio_is_write)
87da7e66
XG		 8001 memcpy(frag->data, run->mmio.data, len);
8002
8003 if (frag->len <= 8) {
8004 /* Switch to the next fragment. */
8005 frag++;
8006 vcpu->mmio_cur_fragment++;
8007 } else {
8008 /* Go forward to the next mmio piece. */
8009 frag->data += len;
8010 frag->gpa += len;
8011 frag->len -= len;
8012 }
8013
a08d3b3b 8014 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8015 vcpu->mmio_needed = 0;
0912c977
PB		 8016
8017 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8018 if (vcpu->mmio_is_write)
716d51ab
GN		 8019 return 1;
8020 vcpu->mmio_read_completed = 1;
8021 return complete_emulated_io(vcpu);
8022 }
87da7e66 8023
716d51ab
GN		 8024 run->exit_reason = KVM_EXIT_MMIO;
8025 run->mmio.phys_addr = frag->gpa;
8026 if (vcpu->mmio_is_write)
87da7e66
XG		 8027 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8028 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8029 run->mmio.is_write = vcpu->mmio_is_write;
8030 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8031 return 0;
5287f194
AK		 8032}
8033
822f312d
SAS		 8034/* Swap (qemu) user FPU context for the guest FPU context. */
8035static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8036{
8037 preempt_disable();
8038 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
8039 /* PKRU is separately restored in kvm_x86_ops->run. */
8040 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8041 ~XFEATURE_MASK_PKRU);
8042 preempt_enable();
8043 trace_kvm_fpu(1);
8044}
8045
8046/* When vcpu_run ends, restore user space FPU context. */
8047static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8048{
8049 preempt_disable();
8050 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
8051 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8052 preempt_enable();
8053 ++vcpu->stat.fpu_reload;
8054 trace_kvm_fpu(0);
8055}
8056
b6c7a5dc
HB		 8057int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8058{
8059 int r;
b6c7a5dc 8060
accb757d 8061 vcpu_load(vcpu);
20b7035c 8062 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8063 kvm_load_guest_fpu(vcpu);
8064
a4535290 8065 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8066 if (kvm_run->immediate_exit) {
8067 r = -EINTR;
8068 goto out;
8069 }
b6c7a5dc 8070 kvm_vcpu_block(vcpu);
66450a21 8071 kvm_apic_accept_events(vcpu);
72875d8a 8072 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8073 r = -EAGAIN;
a0595000
JS		 8074 if (signal_pending(current)) {
8075 r = -EINTR;
8076 vcpu->run->exit_reason = KVM_EXIT_INTR;
8077 ++vcpu->stat.signal_exits;
8078 }
ac9f6dc0 8079 goto out;
b6c7a5dc
HB		 8080 }
8081
01643c51
KH		 8082 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8083 r = -EINVAL;
8084 goto out;
8085 }
8086
8087 if (vcpu->run->kvm_dirty_regs) {
8088 r = sync_regs(vcpu);
8089 if (r != 0)
8090 goto out;
8091 }
8092
b6c7a5dc 8093 /* re-sync apic's tpr */
35754c98 8094 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8095 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8096 r = -EINVAL;
8097 goto out;
8098 }
8099 }
b6c7a5dc 8100
716d51ab
GN		 8101 if (unlikely(vcpu->arch.complete_userspace_io)) {
8102 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8103 vcpu->arch.complete_userspace_io = NULL;
8104 r = cui(vcpu);
8105 if (r <= 0)
5663d8f9 8106 goto out;
716d51ab
GN		 8107 } else
8108 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8109
460df4c1
PB		 8110 if (kvm_run->immediate_exit)
8111 r = -EINTR;
8112 else
8113 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8114
8115out:
5663d8f9 8116 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8117 if (vcpu->run->kvm_valid_regs)
8118 store_regs(vcpu);
f1d86e46 8119 post_kvm_run_save(vcpu);
20b7035c 8120 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8121
accb757d 8122 vcpu_put(vcpu);
b6c7a5dc
HB		 8123 return r;
8124}
8125
01643c51 8126static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8127{
7ae441ea
GN		 8128 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8129 /*
8130 * We are here if userspace calls get_regs() in the middle of
8131 * instruction emulation. Registers state needs to be copied
4a969980 8132 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8133 * that usually, but some bad designed PV devices (vmware
8134 * backdoor interface) need this to work
8135 */
dd856efa 8136 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8137 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8138 }
5fdbf976
MT		 8139 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
8140 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
8141 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
8142 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
8143 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
8144 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
8145 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8146 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 8147#ifdef CONFIG_X86_64
5fdbf976
MT		 8148 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
8149 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
8150 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
8151 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
8152 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
8153 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
8154 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
8155 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 8156#endif
8157
5fdbf976 8158 regs->rip = kvm_rip_read(vcpu);
91586a3b 8159 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8160}
b6c7a5dc 8161
01643c51
KH		 8162int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8163{
8164 vcpu_load(vcpu);
8165 __get_regs(vcpu, regs);
1fc9b76b 8166 vcpu_put(vcpu);
b6c7a5dc
HB		 8167 return 0;
8168}
8169
01643c51 8170static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8171{
7ae441ea
GN		 8172 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8173 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8174
5fdbf976
MT		 8175 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
8176 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8177 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8178 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8179 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8180 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8181 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8182 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 8183#ifdef CONFIG_X86_64
5fdbf976
MT		 8184 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8185 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8186 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8187 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8188 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8189 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8190 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8191 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 8192#endif
8193
5fdbf976 8194 kvm_rip_write(vcpu, regs->rip);
d73235d1 8195 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8196
b4f14abd
JK		 8197 vcpu->arch.exception.pending = false;
8198
3842d135 8199 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8200}
3842d135 8201
01643c51
KH		 8202int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8203{
8204 vcpu_load(vcpu);
8205 __set_regs(vcpu, regs);
875656fe 8206 vcpu_put(vcpu);
b6c7a5dc
HB		 8207 return 0;
8208}
8209
b6c7a5dc
HB		 8210void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8211{
8212 struct kvm_segment cs;
8213
3e6e0aab 8214 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8215 *db = cs.db;
8216 *l = cs.l;
8217}
8218EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8219
01643c51 8220static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8221{
89a27f4d 8222 struct desc_ptr dt;
b6c7a5dc 8223
3e6e0aab
GT		 8224 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8225 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8226 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8227 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8228 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8229 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8230
3e6e0aab
GT		 8231 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8232 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8233
8234 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8235 sregs->idt.limit = dt.size;
8236 sregs->idt.base = dt.address;
b6c7a5dc 8237 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8238 sregs->gdt.limit = dt.size;
8239 sregs->gdt.base = dt.address;
b6c7a5dc 8240
4d4ec087 8241 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8242 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8243 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8244 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8245 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8246 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8247 sregs->apic_base = kvm_get_apic_base(vcpu);
8248
0e96f31e 8249 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8250
04140b41 8251 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8252 set_bit(vcpu->arch.interrupt.nr,
8253 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8254}
16d7a191 8255
01643c51
KH		 8256int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8257 struct kvm_sregs *sregs)
8258{
8259 vcpu_load(vcpu);
8260 __get_sregs(vcpu, sregs);
bcdec41c 8261 vcpu_put(vcpu);
b6c7a5dc
HB		 8262 return 0;
8263}
8264
62d9f0db
MT		 8265int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8266 struct kvm_mp_state *mp_state)
8267{
fd232561
CD		 8268 vcpu_load(vcpu);
8269
66450a21 8270 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8271 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8272 vcpu->arch.pv.pv_unhalted)
8273 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8274 else
8275 mp_state->mp_state = vcpu->arch.mp_state;
8276
fd232561 8277 vcpu_put(vcpu);
62d9f0db
MT		 8278 return 0;
8279}
8280
8281int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8282 struct kvm_mp_state *mp_state)
8283{
e83dff5e
CD		 8284 int ret = -EINVAL;
8285
8286 vcpu_load(vcpu);
8287
bce87cce 8288 if (!lapic_in_kernel(vcpu) &&
66450a21 8289 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8290 goto out;
66450a21 8291
28bf2888
DH		 8292 /* INITs are latched while in SMM */
8293 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8294 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8295 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8296 goto out;
28bf2888 8297
66450a21
JK		 8298 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8299 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8300 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8301 } else
8302 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8303 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8304
8305 ret = 0;
8306out:
8307 vcpu_put(vcpu);
8308 return ret;
62d9f0db
MT		 8309}
8310
7f3d35fd
KW		 8311int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8312 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8313{
9d74191a 8314 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8315 int ret;
e01c2426 8316
8ec4722d 8317 init_emulate_ctxt(vcpu);
c697518a 8318
7f3d35fd 8319 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8320 has_error_code, error_code);
c697518a 8321
c697518a 8322 if (ret)
19d04437 8323 return EMULATE_FAIL;
37817f29 8324
9d74191a
TY		 8325 kvm_rip_write(vcpu, ctxt->eip);
8326 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8327 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8328 return EMULATE_DONE;
37817f29
IE		 8329}
8330EXPORT_SYMBOL_GPL(kvm_task_switch);
8331
3140c156 8332static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8333{
74fec5b9
TL		 8334 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8335 (sregs->cr4 & X86_CR4_OSXSAVE))
8336 return -EINVAL;
8337
37b95951 8338 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8339 /*
8340 * When EFER.LME and CR0.PG are set, the processor is in
8341 * 64-bit mode (though maybe in a 32-bit code segment).
8342 * CR4.PAE and EFER.LMA must be set.
8343 */
37b95951 8344 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8345 || !(sregs->efer & EFER_LMA))
8346 return -EINVAL;
8347 } else {
8348 /*
8349 * Not in 64-bit mode: EFER.LMA is clear and the code
8350 * segment cannot be 64-bit.
8351 */
8352 if (sregs->efer & EFER_LMA || sregs->cs.l)
8353 return -EINVAL;
8354 }
8355
8356 return 0;
8357}
8358
01643c51 8359static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8360{
58cb628d 8361 struct msr_data apic_base_msr;
b6c7a5dc 8362 int mmu_reset_needed = 0;
c4d21882 8363 int cpuid_update_needed = 0;
63f42e02 8364 int pending_vec, max_bits, idx;
89a27f4d 8365 struct desc_ptr dt;
b4ef9d4e
CD		 8366 int ret = -EINVAL;
8367
f2981033 8368 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8369 goto out;
f2981033 8370
d3802286
JM		 8371 apic_base_msr.data = sregs->apic_base;
8372 apic_base_msr.host_initiated = true;
8373 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8374 goto out;
6d1068b3 8375
89a27f4d
GN		 8376 dt.size = sregs->idt.limit;
8377 dt.address = sregs->idt.base;
b6c7a5dc 8378 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8379 dt.size = sregs->gdt.limit;
8380 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8381 kvm_x86_ops->set_gdt(vcpu, &dt);
8382
ad312c7c 8383 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8384 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8385 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8386 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8387
2d3ad1f4 8388 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8389
f6801dff 8390 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8391 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8392
4d4ec087 8393 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8394 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8395 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8396
fc78f519 8397 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8398 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8399 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8400 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8401 if (cpuid_update_needed)
00b27a3e 8402 kvm_update_cpuid(vcpu);
63f42e02
XG		 8403
8404 idx = srcu_read_lock(&vcpu->kvm->srcu);
d35b34a9 8405 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
9f8fe504 8406 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8407 mmu_reset_needed = 1;
8408 }
63f42e02 8409 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8410
8411 if (mmu_reset_needed)
8412 kvm_mmu_reset_context(vcpu);
8413
a50abc3b 8414 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8415 pending_vec = find_first_bit(
8416 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8417 if (pending_vec < max_bits) {
66fd3f7f 8418 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8419 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8420 }
8421
3e6e0aab
GT		 8422 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8423 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8424 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8425 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8426 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8427 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8428
3e6e0aab
GT		 8429 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8430 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8431
5f0269f5
ME		 8432 update_cr8_intercept(vcpu);
8433
9c3e4aab 8434 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8435 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8436 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8437 !is_protmode(vcpu))
9c3e4aab
MT		 8438 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8439
3842d135
AK		 8440 kvm_make_request(KVM_REQ_EVENT, vcpu);
8441
b4ef9d4e
CD		 8442 ret = 0;
8443out:
01643c51
KH		 8444 return ret;
8445}
8446
8447int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8448 struct kvm_sregs *sregs)
8449{
8450 int ret;
8451
8452 vcpu_load(vcpu);
8453 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8454 vcpu_put(vcpu);
8455 return ret;
b6c7a5dc
HB		 8456}
8457
d0bfb940
JK		 8458int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8459 struct kvm_guest_debug *dbg)
b6c7a5dc 8460{
355be0b9 8461 unsigned long rflags;
ae675ef0 8462 int i, r;
b6c7a5dc 8463
66b56562
CD		 8464 vcpu_load(vcpu);
8465
4f926bf2
JK		 8466 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8467 r = -EBUSY;
8468 if (vcpu->arch.exception.pending)
2122ff5e 8469 goto out;
4f926bf2
JK		 8470 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8471 kvm_queue_exception(vcpu, DB_VECTOR);
8472 else
8473 kvm_queue_exception(vcpu, BP_VECTOR);
8474 }
8475
91586a3b
JK		 8476 /*
8477 * Read rflags as long as potentially injected trace flags are still
8478 * filtered out.
8479 */
8480 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8481
8482 vcpu->guest_debug = dbg->control;
8483 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8484 vcpu->guest_debug = 0;
8485
8486 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8487 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8488 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8489 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8490 } else {
8491 for (i = 0; i < KVM_NR_DB_REGS; i++)
8492 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8493 }
c8639010 8494 kvm_update_dr7(vcpu);
ae675ef0 8495
f92653ee
JK		 8496 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8497 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8498 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8499
91586a3b
JK		 8500 /*
8501 * Trigger an rflags update that will inject or remove the trace
8502 * flags.
8503 */
8504 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8505
a96036b8 8506 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8507
4f926bf2 8508 r = 0;
d0bfb940 8509
2122ff5e 8510out:
66b56562 8511 vcpu_put(vcpu);
b6c7a5dc
HB		 8512 return r;
8513}
8514
8b006791
ZX		 8515/*
8516 * Translate a guest virtual address to a guest physical address.
8517 */
8518int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8519 struct kvm_translation *tr)
8520{
8521 unsigned long vaddr = tr->linear_address;
8522 gpa_t gpa;
f656ce01 8523 int idx;
8b006791 8524
1da5b61d
CD		 8525 vcpu_load(vcpu);
8526
f656ce01 8527 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8528 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8529 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8530 tr->physical_address = gpa;
8531 tr->valid = gpa != UNMAPPED_GVA;
8532 tr->writeable = 1;
8533 tr->usermode = 0;
8b006791 8534
1da5b61d 8535 vcpu_put(vcpu);
8b006791
ZX		 8536 return 0;
8537}
8538
d0752060
HB		 8539int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8540{
1393123e 8541 struct fxregs_state *fxsave;
d0752060 8542
1393123e 8543 vcpu_load(vcpu);
d0752060 8544
1393123e 8545 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8546 memcpy(fpu->fpr, fxsave->st_space, 128);
8547 fpu->fcw = fxsave->cwd;
8548 fpu->fsw = fxsave->swd;
8549 fpu->ftwx = fxsave->twd;
8550 fpu->last_opcode = fxsave->fop;
8551 fpu->last_ip = fxsave->rip;
8552 fpu->last_dp = fxsave->rdp;
0e96f31e 8553 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8554
1393123e 8555 vcpu_put(vcpu);
d0752060
HB		 8556 return 0;
8557}
8558
8559int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8560{
6a96bc7f
CD		 8561 struct fxregs_state *fxsave;
8562
8563 vcpu_load(vcpu);
8564
8565 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8566
d0752060
HB		 8567 memcpy(fxsave->st_space, fpu->fpr, 128);
8568 fxsave->cwd = fpu->fcw;
8569 fxsave->swd = fpu->fsw;
8570 fxsave->twd = fpu->ftwx;
8571 fxsave->fop = fpu->last_opcode;
8572 fxsave->rip = fpu->last_ip;
8573 fxsave->rdp = fpu->last_dp;
0e96f31e 8574 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8575
6a96bc7f 8576 vcpu_put(vcpu);
d0752060
HB		 8577 return 0;
8578}
8579
01643c51
KH		 8580static void store_regs(struct kvm_vcpu *vcpu)
8581{
8582 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8583
8584 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8585 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8586
8587 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8588 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8589
8590 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8591 kvm_vcpu_ioctl_x86_get_vcpu_events(
8592 vcpu, &vcpu->run->s.regs.events);
8593}
8594
8595static int sync_regs(struct kvm_vcpu *vcpu)
8596{
8597 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8598 return -EINVAL;
8599
8600 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8601 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8602 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8603 }
8604 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8605 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8606 return -EINVAL;
8607 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8608 }
8609 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8610 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8611 vcpu, &vcpu->run->s.regs.events))
8612 return -EINVAL;
8613 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8614 }
8615
8616 return 0;
8617}
8618
0ee6a517 8619static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8620{
bf935b0b 8621 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8622 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8623 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8624 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8625
2acf923e
DC		 8626 /*
8627 * Ensure guest xcr0 is valid for loading
8628 */
d91cab78 8629 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8630
ad312c7c 8631 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8632}
d0752060 8633
e9b11c17
ZX		 8634void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8635{
bd768e14
IY		 8636 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8637
12f9a48f 8638 kvmclock_reset(vcpu);
7f1ea208 8639
e9b11c17 8640 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8641 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8642}
8643
8644struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8645 unsigned int id)
8646{
c447e76b
LL		 8647 struct kvm_vcpu *vcpu;
8648
b0c39dc6 8649 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8650 printk_once(KERN_WARNING
8651 "kvm: SMP vm created on host with unstable TSC; "
8652 "guest TSC will not be reliable\n");
c447e76b
LL		 8653
8654 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8655
c447e76b 8656 return vcpu;
26e5215f 8657}
e9b11c17 8658
26e5215f
AK		 8659int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8660{
19efffa2 8661 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8662 vcpu_load(vcpu);
d28bc9dd 8663 kvm_vcpu_reset(vcpu, false);
e1732991 8664 kvm_init_mmu(vcpu, false);
e9b11c17 8665 vcpu_put(vcpu);
ec7660cc 8666 return 0;
e9b11c17
ZX		 8667}
8668
31928aa5 8669void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8670{
8fe8ab46 8671 struct msr_data msr;
332967a3 8672 struct kvm *kvm = vcpu->kvm;
42897d86 8673
d3457c87
RK		 8674 kvm_hv_vcpu_postcreate(vcpu);
8675
ec7660cc 8676 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8677 return;
ec7660cc 8678 vcpu_load(vcpu);
8fe8ab46
WA		 8679 msr.data = 0x0;
8680 msr.index = MSR_IA32_TSC;
8681 msr.host_initiated = true;
8682 kvm_write_tsc(vcpu, &msr);
42897d86 8683 vcpu_put(vcpu);
ec7660cc 8684 mutex_unlock(&vcpu->mutex);
42897d86 8685
630994b3
MT		 8686 if (!kvmclock_periodic_sync)
8687 return;
8688
332967a3
AJ		 8689 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8690 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8691}
8692
d40ccc62 8693void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8694{
344d9588
GN		 8695 vcpu->arch.apf.msr_val = 0;
8696
ec7660cc 8697 vcpu_load(vcpu);
e9b11c17
ZX		 8698 kvm_mmu_unload(vcpu);
8699 vcpu_put(vcpu);
8700
8701 kvm_x86_ops->vcpu_free(vcpu);
8702}
8703
d28bc9dd 8704void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8705{
b7e31be3
RK		 8706 kvm_lapic_reset(vcpu, init_event);
8707
e69fab5d
PB		 8708 vcpu->arch.hflags = 0;
8709
c43203ca 8710 vcpu->arch.smi_pending = 0;
52797bf9 8711 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8712 atomic_set(&vcpu->arch.nmi_queued, 0);
8713 vcpu->arch.nmi_pending = 0;
448fa4a9 8714 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8715 kvm_clear_interrupt_queue(vcpu);
8716 kvm_clear_exception_queue(vcpu);
664f8e26 8717 vcpu->arch.exception.pending = false;
448fa4a9 8718
42dbaa5a 8719 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8720 kvm_update_dr0123(vcpu);
6f43ed01 8721 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8722 kvm_update_dr6(vcpu);
42dbaa5a 8723 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8724 kvm_update_dr7(vcpu);
42dbaa5a 8725
1119022c
NA		 8726 vcpu->arch.cr2 = 0;
8727
3842d135 8728 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8729 vcpu->arch.apf.msr_val = 0;
c9aaa895 8730 vcpu->arch.st.msr_val = 0;
3842d135 8731
12f9a48f
GC		 8732 kvmclock_reset(vcpu);
8733
af585b92
GN		 8734 kvm_clear_async_pf_completion_queue(vcpu);
8735 kvm_async_pf_hash_reset(vcpu);
8736 vcpu->arch.apf.halted = false;
3842d135 8737
a554d207
WL		 8738 if (kvm_mpx_supported()) {
8739 void *mpx_state_buffer;
8740
8741 /*
8742 * To avoid have the INIT path from kvm_apic_has_events() that be
8743 * called with loaded FPU and does not let userspace fix the state.
8744 */
f775b13e
RR		 8745 if (init_event)
8746 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8747 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8748 XFEATURE_MASK_BNDREGS);
8749 if (mpx_state_buffer)
8750 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8751 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8752 XFEATURE_MASK_BNDCSR);
8753 if (mpx_state_buffer)
8754 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8755 if (init_event)
8756 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8757 }
8758
64d60670 8759 if (!init_event) {
d28bc9dd 8760 kvm_pmu_reset(vcpu);
64d60670 8761 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8762
8763 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8764 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8765
8766 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8767 }
f5132b01 8768
66f7b72e
JS		 8769 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8770 vcpu->arch.regs_avail = ~0;
8771 vcpu->arch.regs_dirty = ~0;
8772
a554d207
WL		 8773 vcpu->arch.ia32_xss = 0;
8774
d28bc9dd 8775 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8776}
8777
2b4a273b 8778void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8779{
8780 struct kvm_segment cs;
8781
8782 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8783 cs.selector = vector << 8;
8784 cs.base = vector << 12;
8785 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8786 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8787}
8788
13a34e06 8789int kvm_arch_hardware_enable(void)
e9b11c17 8790{
ca84d1a2
ZA		 8791 struct kvm *kvm;
8792 struct kvm_vcpu *vcpu;
8793 int i;
0dd6a6ed
ZA		 8794 int ret;
8795 u64 local_tsc;
8796 u64 max_tsc = 0;
8797 bool stable, backwards_tsc = false;
18863bdd
AK		 8798
8799 kvm_shared_msr_cpu_online();
13a34e06 8800 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8801 if (ret != 0)
8802 return ret;
8803
4ea1636b 8804 local_tsc = rdtsc();
b0c39dc6 8805 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8806 list_for_each_entry(kvm, &vm_list, vm_list) {
8807 kvm_for_each_vcpu(i, vcpu, kvm) {
8808 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8809 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8810 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8811 backwards_tsc = true;
8812 if (vcpu->arch.last_host_tsc > max_tsc)
8813 max_tsc = vcpu->arch.last_host_tsc;
8814 }
8815 }
8816 }
8817
8818 /*
8819 * Sometimes, even reliable TSCs go backwards. This happens on
8820 * platforms that reset TSC during suspend or hibernate actions, but
8821 * maintain synchronization. We must compensate. Fortunately, we can
8822 * detect that condition here, which happens early in CPU bringup,
8823 * before any KVM threads can be running. Unfortunately, we can't
8824 * bring the TSCs fully up to date with real time, as we aren't yet far
8825 * enough into CPU bringup that we know how much real time has actually
108b249c 8826 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8827 * variables that haven't been updated yet.
8828 *
8829 * So we simply find the maximum observed TSC above, then record the
8830 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8831 * the adjustment will be applied. Note that we accumulate
8832 * adjustments, in case multiple suspend cycles happen before some VCPU
8833 * gets a chance to run again. In the event that no KVM threads get a
8834 * chance to run, we will miss the entire elapsed period, as we'll have
8835 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8836 * loose cycle time. This isn't too big a deal, since the loss will be
8837 * uniform across all VCPUs (not to mention the scenario is extremely
8838 * unlikely). It is possible that a second hibernate recovery happens
8839 * much faster than a first, causing the observed TSC here to be
8840 * smaller; this would require additional padding adjustment, which is
8841 * why we set last_host_tsc to the local tsc observed here.
8842 *
8843 * N.B. - this code below runs only on platforms with reliable TSC,
8844 * as that is the only way backwards_tsc is set above. Also note
8845 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8846 * have the same delta_cyc adjustment applied if backwards_tsc
8847 * is detected. Note further, this adjustment is only done once,
8848 * as we reset last_host_tsc on all VCPUs to stop this from being
8849 * called multiple times (one for each physical CPU bringup).
8850 *
4a969980 8851 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8852 * will be compensated by the logic in vcpu_load, which sets the TSC to
8853 * catchup mode. This will catchup all VCPUs to real time, but cannot
8854 * guarantee that they stay in perfect synchronization.
8855 */
8856 if (backwards_tsc) {
8857 u64 delta_cyc = max_tsc - local_tsc;
8858 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8859 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8860 kvm_for_each_vcpu(i, vcpu, kvm) {
8861 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8862 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8863 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8864 }
8865
8866 /*
8867 * We have to disable TSC offset matching.. if you were
8868 * booting a VM while issuing an S4 host suspend....
8869 * you may have some problem. Solving this issue is
8870 * left as an exercise to the reader.
8871 */
8872 kvm->arch.last_tsc_nsec = 0;
8873 kvm->arch.last_tsc_write = 0;
8874 }
8875
8876 }
8877 return 0;
e9b11c17
ZX		 8878}
8879
13a34e06 8880void kvm_arch_hardware_disable(void)
e9b11c17 8881{
13a34e06
RK		 8882 kvm_x86_ops->hardware_disable();
8883 drop_user_return_notifiers();
e9b11c17
ZX		 8884}
8885
8886int kvm_arch_hardware_setup(void)
8887{
9e9c3fe4
NA		 8888 int r;
8889
8890 r = kvm_x86_ops->hardware_setup();
8891 if (r != 0)
8892 return r;
8893
35181e86
HZ		 8894 if (kvm_has_tsc_control) {
8895 /*
8896 * Make sure the user can only configure tsc_khz values that
8897 * fit into a signed integer.
273ba457 8898 * A min value is not calculated because it will always
35181e86
HZ		 8899 * be 1 on all machines.
8900 */
8901 u64 max = min(0x7fffffffULL,
8902 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8903 kvm_max_guest_tsc_khz = max;
8904
ad721883 8905 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8906 }
ad721883 8907
9e9c3fe4
NA		 8908 kvm_init_msr_list();
8909 return 0;
e9b11c17
ZX		 8910}
8911
8912void kvm_arch_hardware_unsetup(void)
8913{
8914 kvm_x86_ops->hardware_unsetup();
8915}
8916
8917void kvm_arch_check_processor_compat(void *rtn)
8918{
8919 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8920}
8921
8922bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8923{
8924 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8925}
8926EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8927
8928bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8929{
8930 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8931}
8932
54e9818f 8933struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8934EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8935
e9b11c17
ZX		 8936int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8937{
8938 struct page *page;
e9b11c17
ZX		 8939 int r;
8940
b2a05fef 8941 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8942 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8943 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8944 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8945 else
a4535290 8946 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8947
8948 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8949 if (!page) {
8950 r = -ENOMEM;
8951 goto fail;
8952 }
ad312c7c 8953 vcpu->arch.pio_data = page_address(page);
e9b11c17 8954
cc578287 8955 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8956
e9b11c17
ZX		 8957 r = kvm_mmu_create(vcpu);
8958 if (r < 0)
8959 goto fail_free_pio_data;
8960
26de7988 8961 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8962 r = kvm_create_lapic(vcpu);
8963 if (r < 0)
8964 goto fail_mmu_destroy;
54e9818f
GN		 8965 } else
8966 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8967
890ca9ae
HY		 8968 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8969 GFP_KERNEL);
8970 if (!vcpu->arch.mce_banks) {
8971 r = -ENOMEM;
443c39bc 8972 goto fail_free_lapic;
890ca9ae
HY		 8973 }
8974 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8975
f1797359
WY		 8976 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8977 r = -ENOMEM;
f5f48ee1 8978 goto fail_free_mce_banks;
f1797359 8979 }
f5f48ee1 8980
0ee6a517 8981 fx_init(vcpu);
66f7b72e 8982
4344ee98 8983 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8984
5a4f55cd
EK		 8985 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8986
74545705
RK		 8987 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8988
af585b92 8989 kvm_async_pf_hash_reset(vcpu);
f5132b01 8990 kvm_pmu_init(vcpu);
af585b92 8991
1c1a9ce9 8992 vcpu->arch.pending_external_vector = -1;
de63ad4c 8993 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8994
5c919412
AS		 8995 kvm_hv_vcpu_init(vcpu);
8996
e9b11c17 8997 return 0;
0ee6a517 8998
f5f48ee1
SY		 8999fail_free_mce_banks:
9000 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9001fail_free_lapic:
9002 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9003fail_mmu_destroy:
9004 kvm_mmu_destroy(vcpu);
9005fail_free_pio_data:
ad312c7c 9006 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9007fail:
9008 return r;
9009}
9010
9011void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9012{
f656ce01
MT		 9013 int idx;
9014
1f4b34f8 9015 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9016 kvm_pmu_destroy(vcpu);
36cb93fd 9017 kfree(vcpu->arch.mce_banks);
e9b11c17 9018 kvm_free_lapic(vcpu);
f656ce01 9019 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9020 kvm_mmu_destroy(vcpu);
f656ce01 9021 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9022 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9023 if (!lapic_in_kernel(vcpu))
54e9818f 9024 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9025}
d19a9cd2 9026
e790d9ef
RK		 9027void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9028{
c595ceee 9029 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9030 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9031}
9032
e08b9637 9033int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9034{
e08b9637
CO		 9035 if (type)
9036 return -EINVAL;
9037
6ef768fa 9038 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9039 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 9040 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 9041 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9042 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9043
5550af4d
SY		 9044 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9045 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9046 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9047 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9048 &kvm->arch.irq_sources_bitmap);
5550af4d 9049
038f8c11 9050 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9051 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9052 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9053
108b249c 9054 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 9055 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9056
6fbbde9a
DS		 9057 kvm->arch.guest_can_read_msr_platform_info = true;
9058
7e44e449 9059 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9060 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9061
cbc0236a 9062 kvm_hv_init_vm(kvm);
0eb05bf2 9063 kvm_page_track_init(kvm);
13d268ca 9064 kvm_mmu_init_vm(kvm);
0eb05bf2 9065
03543133
SS		 9066 if (kvm_x86_ops->vm_init)
9067 return kvm_x86_ops->vm_init(kvm);
9068
d89f5eff 9069 return 0;
d19a9cd2
ZX		 9070}
9071
9072static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9073{
ec7660cc 9074 vcpu_load(vcpu);
d19a9cd2
ZX		 9075 kvm_mmu_unload(vcpu);
9076 vcpu_put(vcpu);
9077}
9078
9079static void kvm_free_vcpus(struct kvm *kvm)
9080{
9081 unsigned int i;
988a2cae 9082 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9083
9084 /*
9085 * Unpin any mmu pages first.
9086 */
af585b92
GN		 9087 kvm_for_each_vcpu(i, vcpu, kvm) {
9088 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9089 kvm_unload_vcpu_mmu(vcpu);
af585b92 9090 }
988a2cae
GN		 9091 kvm_for_each_vcpu(i, vcpu, kvm)
9092 kvm_arch_vcpu_free(vcpu);
9093
9094 mutex_lock(&kvm->lock);
9095 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9096 kvm->vcpus[i] = NULL;
d19a9cd2 9097
988a2cae
GN		 9098 atomic_set(&kvm->online_vcpus, 0);
9099 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9100}
9101
ad8ba2cd
SY		 9102void kvm_arch_sync_events(struct kvm *kvm)
9103{
332967a3 9104 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9105 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9106 kvm_free_pit(kvm);
ad8ba2cd
SY		 9107}
9108
1d8007bd 9109int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9110{
9111 int i, r;
25188b99 9112 unsigned long hva;
f0d648bd
PB		 9113 struct kvm_memslots *slots = kvm_memslots(kvm);
9114 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9115
9116 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9117 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9118 return -EINVAL;
9da0e4d5 9119
f0d648bd
PB		 9120 slot = id_to_memslot(slots, id);
9121 if (size) {
b21629da 9122 if (slot->npages)
f0d648bd
PB		 9123 return -EEXIST;
9124
9125 /*
9126 * MAP_SHARED to prevent internal slot pages from being moved
9127 * by fork()/COW.
9128 */
9129 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9130 MAP_SHARED | MAP_ANONYMOUS, 0);
9131 if (IS_ERR((void *)hva))
9132 return PTR_ERR((void *)hva);
9133 } else {
9134 if (!slot->npages)
9135 return 0;
9136
9137 hva = 0;
9138 }
9139
9140 old = *slot;
9da0e4d5 9141 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9142 struct kvm_userspace_memory_region m;
9da0e4d5 9143
1d8007bd
PB		 9144 m.slot = id | (i << 16);
9145 m.flags = 0;
9146 m.guest_phys_addr = gpa;
f0d648bd 9147 m.userspace_addr = hva;
1d8007bd 9148 m.memory_size = size;
9da0e4d5
PB		 9149 r = __kvm_set_memory_region(kvm, &m);
9150 if (r < 0)
9151 return r;
9152 }
9153
103c763c
EB		 9154 if (!size)
9155 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9156
9da0e4d5
PB		 9157 return 0;
9158}
9159EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9160
1d8007bd 9161int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9162{
9163 int r;
9164
9165 mutex_lock(&kvm->slots_lock);
1d8007bd 9166 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9167 mutex_unlock(&kvm->slots_lock);
9168
9169 return r;
9170}
9171EXPORT_SYMBOL_GPL(x86_set_memory_region);
9172
d19a9cd2
ZX		 9173void kvm_arch_destroy_vm(struct kvm *kvm)
9174{
27469d29
AH		 9175 if (current->mm == kvm->mm) {
9176 /*
9177 * Free memory regions allocated on behalf of userspace,
9178 * unless the the memory map has changed due to process exit
9179 * or fd copying.
9180 */
1d8007bd
PB		 9181 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9182 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9183 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9184 }
03543133
SS		 9185 if (kvm_x86_ops->vm_destroy)
9186 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9187 kvm_pic_destroy(kvm);
9188 kvm_ioapic_destroy(kvm);
d19a9cd2 9189 kvm_free_vcpus(kvm);
af1bae54 9190 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 9191 kvm_mmu_uninit_vm(kvm);
2beb6dad 9192 kvm_page_track_cleanup(kvm);
cbc0236a 9193 kvm_hv_destroy_vm(kvm);
d19a9cd2 9194}
0de10343 9195
5587027c 9196void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9197 struct kvm_memory_slot *dont)
9198{
9199 int i;
9200
d89cc617
TY		 9201 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9202 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9203 kvfree(free->arch.rmap[i]);
d89cc617 9204 free->arch.rmap[i] = NULL;
77d11309 9205 }
d89cc617
TY		 9206 if (i == 0)
9207 continue;
9208
9209 if (!dont || free->arch.lpage_info[i - 1] !=
9210 dont->arch.lpage_info[i - 1]) {
548ef284 9211 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9212 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9213 }
9214 }
21ebbeda
XG		 9215
9216 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9217}
9218
5587027c
AK		 9219int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9220 unsigned long npages)
db3fe4eb
TY		 9221{
9222 int i;
9223
d89cc617 9224 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9225 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9226 unsigned long ugfn;
9227 int lpages;
d89cc617 9228 int level = i + 1;
db3fe4eb
TY		 9229
9230 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9231 slot->base_gfn, level) + 1;
9232
d89cc617 9233 slot->arch.rmap[i] =
778e1cdd
KC		 9234 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9235 GFP_KERNEL);
d89cc617 9236 if (!slot->arch.rmap[i])
77d11309 9237 goto out_free;
d89cc617
TY		 9238 if (i == 0)
9239 continue;
77d11309 9240
778e1cdd 9241 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
92f94f1e 9242 if (!linfo)
db3fe4eb
TY		 9243 goto out_free;
9244
92f94f1e
XG		 9245 slot->arch.lpage_info[i - 1] = linfo;
9246
db3fe4eb 9247 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9248 linfo[0].disallow_lpage = 1;
db3fe4eb 9249 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9250 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9251 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9252 /*
9253 * If the gfn and userspace address are not aligned wrt each
9254 * other, or if explicitly asked to, disable large page
9255 * support for this slot
9256 */
9257 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9258 !kvm_largepages_enabled()) {
9259 unsigned long j;
9260
9261 for (j = 0; j < lpages; ++j)
92f94f1e 9262 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9263 }
9264 }
9265
21ebbeda
XG		 9266 if (kvm_page_track_create_memslot(slot, npages))
9267 goto out_free;
9268
db3fe4eb
TY		 9269 return 0;
9270
9271out_free:
d89cc617 9272 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9273 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9274 slot->arch.rmap[i] = NULL;
9275 if (i == 0)
9276 continue;
9277
548ef284 9278 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9279 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9280 }
9281 return -ENOMEM;
9282}
9283
15f46015 9284void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 9285{
e6dff7d1
TY		 9286 /*
9287 * memslots->generation has been incremented.
9288 * mmio generation may have reached its maximum value.
9289 */
54bf36aa 9290 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 9291}
9292
f7784b8e
MT		 9293int kvm_arch_prepare_memory_region(struct kvm *kvm,
9294 struct kvm_memory_slot *memslot,
09170a49 9295 const struct kvm_userspace_memory_region *mem,
7b6195a9 9296 enum kvm_mr_change change)
0de10343 9297{
f7784b8e
MT		 9298 return 0;
9299}
9300
88178fd4
KH		 9301static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9302 struct kvm_memory_slot *new)
9303{
9304 /* Still write protect RO slot */
9305 if (new->flags & KVM_MEM_READONLY) {
9306 kvm_mmu_slot_remove_write_access(kvm, new);
9307 return;
9308 }
9309
9310 /*
9311 * Call kvm_x86_ops dirty logging hooks when they are valid.
9312 *
9313 * kvm_x86_ops->slot_disable_log_dirty is called when:
9314 *
9315 * - KVM_MR_CREATE with dirty logging is disabled
9316 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9317 *
9318 * The reason is, in case of PML, we need to set D-bit for any slots
9319 * with dirty logging disabled in order to eliminate unnecessary GPA
9320 * logging in PML buffer (and potential PML buffer full VMEXT). This
9321 * guarantees leaving PML enabled during guest's lifetime won't have
9322 * any additonal overhead from PML when guest is running with dirty
9323 * logging disabled for memory slots.
9324 *
9325 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9326 * to dirty logging mode.
9327 *
9328 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9329 *
9330 * In case of write protect:
9331 *
9332 * Write protect all pages for dirty logging.
9333 *
9334 * All the sptes including the large sptes which point to this
9335 * slot are set to readonly. We can not create any new large
9336 * spte on this slot until the end of the logging.
9337 *
9338 * See the comments in fast_page_fault().
9339 */
9340 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9341 if (kvm_x86_ops->slot_enable_log_dirty)
9342 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9343 else
9344 kvm_mmu_slot_remove_write_access(kvm, new);
9345 } else {
9346 if (kvm_x86_ops->slot_disable_log_dirty)
9347 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9348 }
9349}
9350
f7784b8e 9351void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9352 const struct kvm_userspace_memory_region *mem,
8482644a 9353 const struct kvm_memory_slot *old,
f36f3f28 9354 const struct kvm_memory_slot *new,
8482644a 9355 enum kvm_mr_change change)
f7784b8e 9356{
8482644a 9357 int nr_mmu_pages = 0;
f7784b8e 9358
48c0e4e9
XG		 9359 if (!kvm->arch.n_requested_mmu_pages)
9360 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9361
48c0e4e9 9362 if (nr_mmu_pages)
0de10343 9363 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9364
3ea3b7fa
WL		 9365 /*
9366 * Dirty logging tracks sptes in 4k granularity, meaning that large
9367 * sptes have to be split. If live migration is successful, the guest
9368 * in the source machine will be destroyed and large sptes will be
9369 * created in the destination. However, if the guest continues to run
9370 * in the source machine (for example if live migration fails), small
9371 * sptes will remain around and cause bad performance.
9372 *
9373 * Scan sptes if dirty logging has been stopped, dropping those
9374 * which can be collapsed into a single large-page spte. Later
9375 * page faults will create the large-page sptes.
9376 */
9377 if ((change != KVM_MR_DELETE) &&
9378 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9379 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9380 kvm_mmu_zap_collapsible_sptes(kvm, new);
9381
c972f3b1 9382 /*
88178fd4 9383 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9384 *
88178fd4
KH		 9385 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9386 * been zapped so no dirty logging staff is needed for old slot. For
9387 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9388 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9389 *
9390 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9391 */
88178fd4 9392 if (change != KVM_MR_DELETE)
f36f3f28 9393 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9394}
1d737c8a 9395
2df72e9b 9396void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9397{
6ca18b69 9398 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9399}
9400
2df72e9b
MT		 9401void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9402 struct kvm_memory_slot *slot)
9403{
ae7cd873 9404 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9405}
9406
e6c67d8c
LA		 9407static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9408{
9409 return (is_guest_mode(vcpu) &&
9410 kvm_x86_ops->guest_apic_has_interrupt &&
9411 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9412}
9413
5d9bc648
PB		 9414static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9415{
9416 if (!list_empty_careful(&vcpu->async_pf.done))
9417 return true;
9418
9419 if (kvm_apic_has_events(vcpu))
9420 return true;
9421
9422 if (vcpu->arch.pv.pv_unhalted)
9423 return true;
9424
a5f01f8e
WL		 9425 if (vcpu->arch.exception.pending)
9426 return true;
9427
47a66eed
Z		 9428 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9429 (vcpu->arch.nmi_pending &&
9430 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9431 return true;
9432
47a66eed
Z		 9433 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9434 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9435 return true;
9436
5d9bc648 9437 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9438 (kvm_cpu_has_interrupt(vcpu) ||
9439 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9440 return true;
9441
1f4b34f8
AS		 9442 if (kvm_hv_has_stimer_pending(vcpu))
9443 return true;
9444
5d9bc648
PB		 9445 return false;
9446}
9447
1d737c8a
ZX		 9448int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9449{
5d9bc648 9450 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9451}
5736199a 9452
199b5763
LM		 9453bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9454{
de63ad4c 9455 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9456}
9457
b6d33834 9458int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9459{
b6d33834 9460 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9461}
78646121
GN		 9462
9463int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9464{
9465 return kvm_x86_ops->interrupt_allowed(vcpu);
9466}
229456fc 9467
82b32774 9468unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9469{
82b32774
NA		 9470 if (is_64_bit_mode(vcpu))
9471 return kvm_rip_read(vcpu);
9472 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9473 kvm_rip_read(vcpu));
9474}
9475EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9476
82b32774
NA		 9477bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9478{
9479 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9480}
9481EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9482
94fe45da
JK		 9483unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9484{
9485 unsigned long rflags;
9486
9487 rflags = kvm_x86_ops->get_rflags(vcpu);
9488 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9489 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9490 return rflags;
9491}
9492EXPORT_SYMBOL_GPL(kvm_get_rflags);
9493
6addfc42 9494static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9495{
9496 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9497 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9498 rflags |= X86_EFLAGS_TF;
94fe45da 9499 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9500}
9501
9502void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9503{
9504 __kvm_set_rflags(vcpu, rflags);
3842d135 9505 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9506}
9507EXPORT_SYMBOL_GPL(kvm_set_rflags);
9508
56028d08
GN		 9509void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9510{
9511 int r;
9512
44dd3ffa 9513 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9514 work->wakeup_all)
56028d08
GN		 9515 return;
9516
9517 r = kvm_mmu_reload(vcpu);
9518 if (unlikely(r))
9519 return;
9520
44dd3ffa
VK		 9521 if (!vcpu->arch.mmu->direct_map &&
9522 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9523 return;
9524
44dd3ffa 9525 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9526}
9527
af585b92
GN		 9528static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9529{
9530 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9531}
9532
9533static inline u32 kvm_async_pf_next_probe(u32 key)
9534{
9535 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9536}
9537
9538static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9539{
9540 u32 key = kvm_async_pf_hash_fn(gfn);
9541
9542 while (vcpu->arch.apf.gfns[key] != ~0)
9543 key = kvm_async_pf_next_probe(key);
9544
9545 vcpu->arch.apf.gfns[key] = gfn;
9546}
9547
9548static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9549{
9550 int i;
9551 u32 key = kvm_async_pf_hash_fn(gfn);
9552
9553 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9554 (vcpu->arch.apf.gfns[key] != gfn &&
9555 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9556 key = kvm_async_pf_next_probe(key);
9557
9558 return key;
9559}
9560
9561bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9562{
9563 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9564}
9565
9566static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9567{
9568 u32 i, j, k;
9569
9570 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9571 while (true) {
9572 vcpu->arch.apf.gfns[i] = ~0;
9573 do {
9574 j = kvm_async_pf_next_probe(j);
9575 if (vcpu->arch.apf.gfns[j] == ~0)
9576 return;
9577 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9578 /*
9579 * k lies cyclically in ]i,j]
9580 * | i.k.j |
9581 * |....j i.k.| or |.k..j i...|
9582 */
9583 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9584 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9585 i = j;
9586 }
9587}
9588
7c90705b
GN		 9589static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9590{
4e335d9e
PB		 9591
9592 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9593 sizeof(val));
7c90705b
GN		 9594}
9595
9a6e7c39
WL		 9596static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9597{
9598
9599 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9600 sizeof(u32));
9601}
9602
af585b92
GN		 9603void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9604 struct kvm_async_pf *work)
9605{
6389ee94
AK		 9606 struct x86_exception fault;
9607
7c90705b 9608 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9609 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9610
9611 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9612 (vcpu->arch.apf.send_user_only &&
9613 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9614 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9615 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9616 fault.vector = PF_VECTOR;
9617 fault.error_code_valid = true;
9618 fault.error_code = 0;
9619 fault.nested_page_fault = false;
9620 fault.address = work->arch.token;
adfe20fb 9621 fault.async_page_fault = true;
6389ee94 9622 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9623 }
af585b92
GN		 9624}
9625
9626void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9627 struct kvm_async_pf *work)
9628{
6389ee94 9629 struct x86_exception fault;
9a6e7c39 9630 u32 val;
6389ee94 9631
f2e10669 9632 if (work->wakeup_all)
7c90705b
GN		 9633 work->arch.token = ~0; /* broadcast wakeup */
9634 else
9635 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9636 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9637
9a6e7c39
WL		 9638 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9639 !apf_get_user(vcpu, &val)) {
9640 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9641 vcpu->arch.exception.pending &&
9642 vcpu->arch.exception.nr == PF_VECTOR &&
9643 !apf_put_user(vcpu, 0)) {
9644 vcpu->arch.exception.injected = false;
9645 vcpu->arch.exception.pending = false;
9646 vcpu->arch.exception.nr = 0;
9647 vcpu->arch.exception.has_error_code = false;
9648 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9649 vcpu->arch.exception.has_payload = false;
9650 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9651 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9652 fault.vector = PF_VECTOR;
9653 fault.error_code_valid = true;
9654 fault.error_code = 0;
9655 fault.nested_page_fault = false;
9656 fault.address = work->arch.token;
9657 fault.async_page_fault = true;
9658 kvm_inject_page_fault(vcpu, &fault);
9659 }
7c90705b 9660 }
e6d53e3b 9661 vcpu->arch.apf.halted = false;
a4fa1635 9662 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9663}
9664
9665bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9666{
9667 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9668 return true;
9669 else
9bc1f09f 9670 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9671}
9672
5544eb9b
PB		 9673void kvm_arch_start_assignment(struct kvm *kvm)
9674{
9675 atomic_inc(&kvm->arch.assigned_device_count);
9676}
9677EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9678
9679void kvm_arch_end_assignment(struct kvm *kvm)
9680{
9681 atomic_dec(&kvm->arch.assigned_device_count);
9682}
9683EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9684
9685bool kvm_arch_has_assigned_device(struct kvm *kvm)
9686{
9687 return atomic_read(&kvm->arch.assigned_device_count);
9688}
9689EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9690
e0f0bbc5
AW		 9691void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9692{
9693 atomic_inc(&kvm->arch.noncoherent_dma_count);
9694}
9695EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9696
9697void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9698{
9699 atomic_dec(&kvm->arch.noncoherent_dma_count);
9700}
9701EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9702
9703bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9704{
9705 return atomic_read(&kvm->arch.noncoherent_dma_count);
9706}
9707EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9708
14717e20
AW		 9709bool kvm_arch_has_irq_bypass(void)
9710{
9711 return kvm_x86_ops->update_pi_irte != NULL;
9712}
9713
87276880
FW		 9714int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9715 struct irq_bypass_producer *prod)
9716{
9717 struct kvm_kernel_irqfd *irqfd =
9718 container_of(cons, struct kvm_kernel_irqfd, consumer);
9719
14717e20 9720 irqfd->producer = prod;
87276880 9721
14717e20
AW		 9722 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9723 prod->irq, irqfd->gsi, 1);
87276880
FW		 9724}
9725
9726void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9727 struct irq_bypass_producer *prod)
9728{
9729 int ret;
9730 struct kvm_kernel_irqfd *irqfd =
9731 container_of(cons, struct kvm_kernel_irqfd, consumer);
9732
87276880
FW		 9733 WARN_ON(irqfd->producer != prod);
9734 irqfd->producer = NULL;
9735
9736 /*
9737 * When producer of consumer is unregistered, we change back to
9738 * remapped mode, so we can re-use the current implementation
bb3541f1 9739 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9740 * int this case doesn't want to receive the interrupts.
9741 */
9742 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9743 if (ret)
9744 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9745 " fails: %d\n", irqfd->consumer.token, ret);
9746}
9747
9748int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9749 uint32_t guest_irq, bool set)
9750{
9751 if (!kvm_x86_ops->update_pi_irte)
9752 return -EINVAL;
9753
9754 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9755}
9756
52004014
FW		 9757bool kvm_vector_hashing_enabled(void)
9758{
9759 return vector_hashing;
9760}
9761EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9762
229456fc 9763EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9764EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9765EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9766EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9767EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9768EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9769EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9770EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9771EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9772EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9773EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9774EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9775EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9776EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9777EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9778EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9779EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9780EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9781EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)