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KVM: lapic: Track lapic timer advance per vCPU
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
bf8c55d8 72#include <asm/intel_pt.h>
043405e1 73
d1898b73
DH		 74#define CREATE_TRACE_POINTS
75#include "trace.h"
76
313a3dc7 77#define MAX_IO_MSRS 256
890ca9ae 78#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 79u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 81
0f65dd70
AK		 82#define emul_to_vcpu(ctxt) \
83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
84
50a37eb4
JR		 85/* EFER defaults:
86 * - enable syscall per default because its emulated by KVM
87 * - enable LME and LMA per default on 64 bit KVM
88 */
89#ifdef CONFIG_X86_64
1260edbe
LJ		 90static
91u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 92#else
1260edbe 93static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 94#endif
313a3dc7 95
ba1389b7
AK		 96#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
97#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 98
c519265f
RK		 99#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
100 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 101
cb142eb7 102static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 103static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 104static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 105static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 106static void store_regs(struct kvm_vcpu *vcpu);
107static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 108
893590c7 109struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 110EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 111
893590c7 112static bool __read_mostly ignore_msrs = 0;
476bc001 113module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 114
fab0aa3b
EM		 115static bool __read_mostly report_ignored_msrs = true;
116module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117
4c27625b 118unsigned int min_timer_period_us = 200;
9ed96e87
MT		 119module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120
630994b3
MT		 121static bool __read_mostly kvmclock_periodic_sync = true;
122module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123
893590c7 124bool __read_mostly kvm_has_tsc_control;
92a1f12d 125EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 126u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 127EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 128u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
129EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
130u64 __read_mostly kvm_max_tsc_scaling_ratio;
131EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 132u64 __read_mostly kvm_default_tsc_scaling_ratio;
133EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 134
cc578287 135/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 136static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 137module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
138
d0659d94 139/* lapic timer advance (tscdeadline mode only) in nanoseconds */
39497d76 140static u32 __read_mostly lapic_timer_advance_ns = 1000;
d0659d94
MT		 141module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
c595ceee 198 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 199 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
200 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
201 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
202 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
203 { "mmu_flooded", VM_STAT(mmu_flooded) },
204 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 205 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 206 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 207 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 208 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 209 { "max_mmu_page_hash_collisions",
210 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 211 { NULL }
212};
213
2acf923e
DC		 214u64 __read_mostly host_xcr0;
215
b666a4b6
MO		 216struct kmem_cache *x86_fpu_cache;
217EXPORT_SYMBOL_GPL(x86_fpu_cache);
218
b6785def 219static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 220
af585b92
GN		 221static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
222{
223 int i;
224 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
225 vcpu->arch.apf.gfns[i] = ~0;
226}
227
18863bdd
AK		 228static void kvm_on_user_return(struct user_return_notifier *urn)
229{
230 unsigned slot;
18863bdd
AK		 231 struct kvm_shared_msrs *locals
232 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 233 struct kvm_shared_msr_values *values;
1650b4eb
IA		 234 unsigned long flags;
235
236 /*
237 * Disabling irqs at this point since the following code could be
238 * interrupted and executed through kvm_arch_hardware_disable()
239 */
240 local_irq_save(flags);
241 if (locals->registered) {
242 locals->registered = false;
243 user_return_notifier_unregister(urn);
244 }
245 local_irq_restore(flags);
18863bdd 246 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 247 values = &locals->values[slot];
248 if (values->host != values->curr) {
249 wrmsrl(shared_msrs_global.msrs[slot], values->host);
250 values->curr = values->host;
18863bdd
AK		 251 }
252 }
18863bdd
AK		 253}
254
2bf78fa7 255static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 256{
18863bdd 257 u64 value;
013f6a5d
MT		 258 unsigned int cpu = smp_processor_id();
259 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 260
2bf78fa7
SY		 261 /* only read, and nobody should modify it at this time,
262 * so don't need lock */
263 if (slot >= shared_msrs_global.nr) {
264 printk(KERN_ERR "kvm: invalid MSR slot!");
265 return;
266 }
267 rdmsrl_safe(msr, &value);
268 smsr->values[slot].host = value;
269 smsr->values[slot].curr = value;
270}
271
272void kvm_define_shared_msr(unsigned slot, u32 msr)
273{
0123be42 274 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 275 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 276 if (slot >= shared_msrs_global.nr)
277 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 278}
279EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
280
281static void kvm_shared_msr_cpu_online(void)
282{
283 unsigned i;
18863bdd
AK		 284
285 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 286 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 287}
288
8b3c3104 289int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 290{
013f6a5d
MT		 291 unsigned int cpu = smp_processor_id();
292 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 293 int err;
18863bdd 294
2bf78fa7 295 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 296 return 0;
2bf78fa7 297 smsr->values[slot].curr = value;
8b3c3104
AH		 298 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
299 if (err)
300 return 1;
301
18863bdd
AK		 302 if (!smsr->registered) {
303 smsr->urn.on_user_return = kvm_on_user_return;
304 user_return_notifier_register(&smsr->urn);
305 smsr->registered = true;
306 }
8b3c3104 307 return 0;
18863bdd
AK		 308}
309EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
310
13a34e06 311static void drop_user_return_notifiers(void)
3548bab5 312{
013f6a5d
MT		 313 unsigned int cpu = smp_processor_id();
314 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 315
316 if (smsr->registered)
317 kvm_on_user_return(&smsr->urn);
318}
319
6866b83e
CO		 320u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
321{
8a5a87d9 322 return vcpu->arch.apic_base;
6866b83e
CO		 323}
324EXPORT_SYMBOL_GPL(kvm_get_apic_base);
325
58871649
JM		 326enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
327{
328 return kvm_apic_mode(kvm_get_apic_base(vcpu));
329}
330EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
331
58cb628d
JK		 332int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
333{
58871649
JM		 334 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
335 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 336 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
337 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 338
58871649 339 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 340 return 1;
58871649
JM		 341 if (!msr_info->host_initiated) {
342 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
343 return 1;
344 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
345 return 1;
346 }
58cb628d
JK		 347
348 kvm_lapic_set_base(vcpu, msr_info->data);
349 return 0;
6866b83e
CO		 350}
351EXPORT_SYMBOL_GPL(kvm_set_apic_base);
352
2605fc21 353asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 354{
355 /* Fault while not rebooting. We want the trace. */
356 BUG();
357}
358EXPORT_SYMBOL_GPL(kvm_spurious_fault);
359
3fd28fce
ED		 360#define EXCPT_BENIGN 0
361#define EXCPT_CONTRIBUTORY 1
362#define EXCPT_PF 2
363
364static int exception_class(int vector)
365{
366 switch (vector) {
367 case PF_VECTOR:
368 return EXCPT_PF;
369 case DE_VECTOR:
370 case TS_VECTOR:
371 case NP_VECTOR:
372 case SS_VECTOR:
373 case GP_VECTOR:
374 return EXCPT_CONTRIBUTORY;
375 default:
376 break;
377 }
378 return EXCPT_BENIGN;
379}
380
d6e8c854
NA		 381#define EXCPT_FAULT 0
382#define EXCPT_TRAP 1
383#define EXCPT_ABORT 2
384#define EXCPT_INTERRUPT 3
385
386static int exception_type(int vector)
387{
388 unsigned int mask;
389
390 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
391 return EXCPT_INTERRUPT;
392
393 mask = 1 << vector;
394
395 /* #DB is trap, as instruction watchpoints are handled elsewhere */
396 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
397 return EXCPT_TRAP;
398
399 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
400 return EXCPT_ABORT;
401
402 /* Reserved exceptions will result in fault */
403 return EXCPT_FAULT;
404}
405
da998b46
JM		 406void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
407{
408 unsigned nr = vcpu->arch.exception.nr;
409 bool has_payload = vcpu->arch.exception.has_payload;
410 unsigned long payload = vcpu->arch.exception.payload;
411
412 if (!has_payload)
413 return;
414
415 switch (nr) {
f10c729f
JM		 416 case DB_VECTOR:
417 /*
418 * "Certain debug exceptions may clear bit 0-3. The
419 * remaining contents of the DR6 register are never
420 * cleared by the processor".
421 */
422 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
423 /*
424 * DR6.RTM is set by all #DB exceptions that don't clear it.
425 */
426 vcpu->arch.dr6 |= DR6_RTM;
427 vcpu->arch.dr6 |= payload;
428 /*
429 * Bit 16 should be set in the payload whenever the #DB
430 * exception should clear DR6.RTM. This makes the payload
431 * compatible with the pending debug exceptions under VMX.
432 * Though not currently documented in the SDM, this also
433 * makes the payload compatible with the exit qualification
434 * for #DB exceptions under VMX.
435 */
436 vcpu->arch.dr6 ^= payload & DR6_RTM;
437 break;
da998b46
JM		 438 case PF_VECTOR:
439 vcpu->arch.cr2 = payload;
440 break;
441 }
442
443 vcpu->arch.exception.has_payload = false;
444 vcpu->arch.exception.payload = 0;
445}
446EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
447
3fd28fce 448static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 449 unsigned nr, bool has_error, u32 error_code,
91e86d22 450 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 451{
452 u32 prev_nr;
453 int class1, class2;
454
3842d135
AK		 455 kvm_make_request(KVM_REQ_EVENT, vcpu);
456
664f8e26 457 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 458 queue:
3ffb2468
NA		 459 if (has_error && !is_protmode(vcpu))
460 has_error = false;
664f8e26
WL		 461 if (reinject) {
462 /*
463 * On vmentry, vcpu->arch.exception.pending is only
464 * true if an event injection was blocked by
465 * nested_run_pending. In that case, however,
466 * vcpu_enter_guest requests an immediate exit,
467 * and the guest shouldn't proceed far enough to
468 * need reinjection.
469 */
470 WARN_ON_ONCE(vcpu->arch.exception.pending);
471 vcpu->arch.exception.injected = true;
91e86d22
JM		 472 if (WARN_ON_ONCE(has_payload)) {
473 /*
474 * A reinjected event has already
475 * delivered its payload.
476 */
477 has_payload = false;
478 payload = 0;
479 }
664f8e26
WL		 480 } else {
481 vcpu->arch.exception.pending = true;
482 vcpu->arch.exception.injected = false;
483 }
3fd28fce
ED		 484 vcpu->arch.exception.has_error_code = has_error;
485 vcpu->arch.exception.nr = nr;
486 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 487 vcpu->arch.exception.has_payload = has_payload;
488 vcpu->arch.exception.payload = payload;
da998b46
JM		 489 /*
490 * In guest mode, payload delivery should be deferred,
491 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 492 * CR2 is modified (or intercept #DB before DR6 is
493 * modified under nVMX). However, for ABI
494 * compatibility with KVM_GET_VCPU_EVENTS and
495 * KVM_SET_VCPU_EVENTS, we can't delay payload
496 * delivery unless userspace has enabled this
497 * functionality via the per-VM capability,
498 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 499 */
500 if (!vcpu->kvm->arch.exception_payload_enabled ||
501 !is_guest_mode(vcpu))
502 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 503 return;
504 }
505
506 /* to check exception */
507 prev_nr = vcpu->arch.exception.nr;
508 if (prev_nr == DF_VECTOR) {
509 /* triple fault -> shutdown */
a8eeb04a 510 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 511 return;
512 }
513 class1 = exception_class(prev_nr);
514 class2 = exception_class(nr);
515 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
516 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 517 /*
518 * Generate double fault per SDM Table 5-5. Set
519 * exception.pending = true so that the double fault
520 * can trigger a nested vmexit.
521 */
3fd28fce 522 vcpu->arch.exception.pending = true;
664f8e26 523 vcpu->arch.exception.injected = false;
3fd28fce
ED		 524 vcpu->arch.exception.has_error_code = true;
525 vcpu->arch.exception.nr = DF_VECTOR;
526 vcpu->arch.exception.error_code = 0;
c851436a
JM		 527 vcpu->arch.exception.has_payload = false;
528 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 529 } else
530 /* replace previous exception with a new one in a hope
531 that instruction re-execution will regenerate lost
532 exception */
533 goto queue;
534}
535
298101da
AK		 536void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
537{
91e86d22 538 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 539}
540EXPORT_SYMBOL_GPL(kvm_queue_exception);
541
ce7ddec4
JR		 542void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
543{
91e86d22 544 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 545}
546EXPORT_SYMBOL_GPL(kvm_requeue_exception);
547
f10c729f
JM		 548static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
549 unsigned long payload)
550{
551 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
552}
553
da998b46
JM		 554static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
555 u32 error_code, unsigned long payload)
556{
557 kvm_multiple_exception(vcpu, nr, true, error_code,
558 true, payload, false);
559}
560
6affcbed 561int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 562{
db8fcefa
AP		 563 if (err)
564 kvm_inject_gp(vcpu, 0);
565 else
6affcbed
KH		 566 return kvm_skip_emulated_instruction(vcpu);
567
568 return 1;
db8fcefa
AP		 569}
570EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 571
6389ee94 572void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 573{
574 ++vcpu->stat.pf_guest;
adfe20fb
WL		 575 vcpu->arch.exception.nested_apf =
576 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 577 if (vcpu->arch.exception.nested_apf) {
adfe20fb 578 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 579 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
580 } else {
581 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
582 fault->address);
583 }
c3c91fee 584}
27d6c865 585EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 586
ef54bcfe 587static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 588{
6389ee94
AK		 589 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
590 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 591 else
44dd3ffa 592 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 593
594 return fault->nested_page_fault;
d4f8cf66
JR		 595}
596
3419ffc8
SY		 597void kvm_inject_nmi(struct kvm_vcpu *vcpu)
598{
7460fb4a
AK		 599 atomic_inc(&vcpu->arch.nmi_queued);
600 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 601}
602EXPORT_SYMBOL_GPL(kvm_inject_nmi);
603
298101da
AK		 604void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
605{
91e86d22 606 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 607}
608EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
609
ce7ddec4
JR		 610void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
611{
91e86d22 612 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 613}
614EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
615
0a79b009
AK		 616/*
617 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
618 * a #GP and return false.
619 */
620bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 621{
0a79b009
AK		 622 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
623 return true;
624 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
625 return false;
298101da 626}
0a79b009 627EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 628
16f8a6f9
NA		 629bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
630{
631 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
632 return true;
633
634 kvm_queue_exception(vcpu, UD_VECTOR);
635 return false;
636}
637EXPORT_SYMBOL_GPL(kvm_require_dr);
638
ec92fe44
JR		 639/*
640 * This function will be used to read from the physical memory of the currently
54bf36aa 641 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 642 * can read from guest physical or from the guest's guest physical memory.
643 */
644int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
645 gfn_t ngfn, void *data, int offset, int len,
646 u32 access)
647{
54987b7a 648 struct x86_exception exception;
ec92fe44
JR		 649 gfn_t real_gfn;
650 gpa_t ngpa;
651
652 ngpa = gfn_to_gpa(ngfn);
54987b7a 653 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 654 if (real_gfn == UNMAPPED_GVA)
655 return -EFAULT;
656
657 real_gfn = gpa_to_gfn(real_gfn);
658
54bf36aa 659 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 660}
661EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
662
69b0049a 663static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 664 void *data, int offset, int len, u32 access)
665{
666 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
667 data, offset, len, access);
668}
669
a03490ed
CO		 670/*
671 * Load the pae pdptrs. Return true is they are all valid.
672 */
ff03a073 673int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 674{
675 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
676 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
677 int i;
678 int ret;
ff03a073 679 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 680
ff03a073
JR		 681 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
682 offset * sizeof(u64), sizeof(pdpte),
683 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 684 if (ret < 0) {
685 ret = 0;
686 goto out;
687 }
688 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 689 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 690 (pdpte[i] &
44dd3ffa 691 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 692 ret = 0;
693 goto out;
694 }
695 }
696 ret = 1;
697
ff03a073 698 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 699 __set_bit(VCPU_EXREG_PDPTR,
700 (unsigned long *)&vcpu->arch.regs_avail);
701 __set_bit(VCPU_EXREG_PDPTR,
702 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 703out:
a03490ed
CO		 704
705 return ret;
706}
cc4b6871 707EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 708
9ed38ffa 709bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 710{
ff03a073 711 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 712 bool changed = true;
3d06b8bf
JR		 713 int offset;
714 gfn_t gfn;
d835dfec
AK		 715 int r;
716
d35b34a9 717 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
d835dfec
AK		 718 return false;
719
6de4f3ad
AK		 720 if (!test_bit(VCPU_EXREG_PDPTR,
721 (unsigned long *)&vcpu->arch.regs_avail))
722 return true;
723
a512177e
PB		 724 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
725 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 726 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
727 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 728 if (r < 0)
729 goto out;
ff03a073 730 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 731out:
d835dfec
AK		 732
733 return changed;
734}
9ed38ffa 735EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 736
49a9b07e 737int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 738{
aad82703 739 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 740 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 741
f9a48e6a
AK		 742 cr0 |= X86_CR0_ET;
743
ab344828 744#ifdef CONFIG_X86_64
0f12244f
GN		 745 if (cr0 & 0xffffffff00000000UL)
746 return 1;
ab344828
GN		 747#endif
748
749 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 750
0f12244f
GN		 751 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
752 return 1;
a03490ed 753
0f12244f
GN		 754 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
755 return 1;
a03490ed
CO		 756
757 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
758#ifdef CONFIG_X86_64
f6801dff 759 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 760 int cs_db, cs_l;
761
0f12244f
GN		 762 if (!is_pae(vcpu))
763 return 1;
a03490ed 764 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 765 if (cs_l)
766 return 1;
a03490ed
CO		 767 } else
768#endif
ff03a073 769 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 770 kvm_read_cr3(vcpu)))
0f12244f 771 return 1;
a03490ed
CO		 772 }
773
ad756a16
MJ		 774 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
775 return 1;
776
a03490ed 777 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 778
d170c419 779 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 780 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 781 kvm_async_pf_hash_reset(vcpu);
782 }
e5f3f027 783
aad82703
SY		 784 if ((cr0 ^ old_cr0) & update_bits)
785 kvm_mmu_reset_context(vcpu);
b18d5431 786
879ae188
LE		 787 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
788 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
789 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 790 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
791
0f12244f
GN		 792 return 0;
793}
2d3ad1f4 794EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 795
2d3ad1f4 796void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 797{
49a9b07e 798 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 799}
2d3ad1f4 800EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 801
1811d979 802void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 803{
804 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
805 !vcpu->guest_xcr0_loaded) {
806 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 807 if (vcpu->arch.xcr0 != host_xcr0)
808 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 809 vcpu->guest_xcr0_loaded = 1;
810 }
811}
1811d979 812EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
42bdf991 813
1811d979 814void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 815{
816 if (vcpu->guest_xcr0_loaded) {
817 if (vcpu->arch.xcr0 != host_xcr0)
818 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
819 vcpu->guest_xcr0_loaded = 0;
820 }
821}
1811d979 822EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
42bdf991 823
69b0049a 824static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 825{
56c103ec
LJ		 826 u64 xcr0 = xcr;
827 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 828 u64 valid_bits;
2acf923e
DC		 829
830 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
831 if (index != XCR_XFEATURE_ENABLED_MASK)
832 return 1;
d91cab78 833 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 834 return 1;
d91cab78 835 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 836 return 1;
46c34cb0
PB		 837
838 /*
839 * Do not allow the guest to set bits that we do not support
840 * saving. However, xcr0 bit 0 is always set, even if the
841 * emulated CPU does not support XSAVE (see fx_init).
842 */
d91cab78 843 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 844 if (xcr0 & ~valid_bits)
2acf923e 845 return 1;
46c34cb0 846
d91cab78
DH		 847 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
848 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 849 return 1;
850
d91cab78
DH		 851 if (xcr0 & XFEATURE_MASK_AVX512) {
852 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 853 return 1;
d91cab78 854 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 855 return 1;
856 }
2acf923e 857 vcpu->arch.xcr0 = xcr0;
56c103ec 858
d91cab78 859 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 860 kvm_update_cpuid(vcpu);
2acf923e
DC		 861 return 0;
862}
863
864int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
865{
764bcbc5
Z		 866 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
867 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 868 kvm_inject_gp(vcpu, 0);
869 return 1;
870 }
871 return 0;
872}
873EXPORT_SYMBOL_GPL(kvm_set_xcr);
874
a83b29c6 875int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 876{
fc78f519 877 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 878 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 879 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 880
0f12244f
GN		 881 if (cr4 & CR4_RESERVED_BITS)
882 return 1;
a03490ed 883
d6321d49 884 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 885 return 1;
886
d6321d49 887 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 888 return 1;
889
d6321d49 890 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 891 return 1;
892
d6321d49 893 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 894 return 1;
895
d6321d49 896 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 897 return 1;
898
fd8cb433 899 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 900 return 1;
901
ae3e61e1
PB		 902 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
903 return 1;
904
a03490ed 905 if (is_long_mode(vcpu)) {
0f12244f
GN		 906 if (!(cr4 & X86_CR4_PAE))
907 return 1;
a2edf57f
AK		 908 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
909 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 910 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
911 kvm_read_cr3(vcpu)))
0f12244f
GN		 912 return 1;
913
ad756a16 914 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 915 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 916 return 1;
917
918 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
919 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
920 return 1;
921 }
922
5e1746d6 923 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 924 return 1;
a03490ed 925
ad756a16
MJ		 926 if (((cr4 ^ old_cr4) & pdptr_bits) ||
927 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 928 kvm_mmu_reset_context(vcpu);
0f12244f 929
b9baba86 930 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 931 kvm_update_cpuid(vcpu);
2acf923e 932
0f12244f
GN		 933 return 0;
934}
2d3ad1f4 935EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 936
2390218b 937int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 938{
ade61e28 939 bool skip_tlb_flush = false;
ac146235 940#ifdef CONFIG_X86_64
c19986fe
JS		 941 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
942
ade61e28 943 if (pcid_enabled) {
208320ba
JS		 944 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
945 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 946 }
ac146235 947#endif
9d88fca7 948
9f8fe504 949 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 950 if (!skip_tlb_flush) {
951 kvm_mmu_sync_roots(vcpu);
ade61e28 952 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 953 }
0f12244f 954 return 0;
d835dfec
AK		 955 }
956
d1cd3ce9 957 if (is_long_mode(vcpu) &&
a780a3ea 958 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 959 return 1;
960 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 961 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 962 return 1;
a03490ed 963
ade61e28 964 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 965 vcpu->arch.cr3 = cr3;
aff48baa 966 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 967
0f12244f
GN		 968 return 0;
969}
2d3ad1f4 970EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 971
eea1cff9 972int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 973{
0f12244f
GN		 974 if (cr8 & CR8_RESERVED_BITS)
975 return 1;
35754c98 976 if (lapic_in_kernel(vcpu))
a03490ed
CO		 977 kvm_lapic_set_tpr(vcpu, cr8);
978 else
ad312c7c 979 vcpu->arch.cr8 = cr8;
0f12244f
GN		 980 return 0;
981}
2d3ad1f4 982EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 983
2d3ad1f4 984unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 985{
35754c98 986 if (lapic_in_kernel(vcpu))
a03490ed
CO		 987 return kvm_lapic_get_cr8(vcpu);
988 else
ad312c7c 989 return vcpu->arch.cr8;
a03490ed 990}
2d3ad1f4 991EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 992
ae561ede
NA		 993static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
994{
995 int i;
996
997 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
998 for (i = 0; i < KVM_NR_DB_REGS; i++)
999 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1000 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1001 }
1002}
1003
73aaf249
JK		 1004static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1005{
1006 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1007 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1008}
1009
c8639010
JK		 1010static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1011{
1012 unsigned long dr7;
1013
1014 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1015 dr7 = vcpu->arch.guest_debug_dr7;
1016 else
1017 dr7 = vcpu->arch.dr7;
1018 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1019 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1020 if (dr7 & DR7_BP_EN_MASK)
1021 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1022}
1023
6f43ed01
NA		 1024static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1025{
1026 u64 fixed = DR6_FIXED_1;
1027
d6321d49 1028 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1029 fixed |= DR6_RTM;
1030 return fixed;
1031}
1032
338dbc97 1033static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1034{
1035 switch (dr) {
1036 case 0 ... 3:
1037 vcpu->arch.db[dr] = val;
1038 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1039 vcpu->arch.eff_db[dr] = val;
1040 break;
1041 case 4:
020df079
GN		 1042 /* fall through */
1043 case 6:
338dbc97
GN		 1044 if (val & 0xffffffff00000000ULL)
1045 return -1; /* #GP */
6f43ed01 1046 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1047 kvm_update_dr6(vcpu);
020df079
GN		 1048 break;
1049 case 5:
020df079
GN		 1050 /* fall through */
1051 default: /* 7 */
338dbc97
GN		 1052 if (val & 0xffffffff00000000ULL)
1053 return -1; /* #GP */
020df079 1054 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1055 kvm_update_dr7(vcpu);
020df079
GN		 1056 break;
1057 }
1058
1059 return 0;
1060}
338dbc97
GN		 1061
1062int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1063{
16f8a6f9 1064 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1065 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1066 return 1;
1067 }
1068 return 0;
338dbc97 1069}
020df079
GN		 1070EXPORT_SYMBOL_GPL(kvm_set_dr);
1071
16f8a6f9 1072int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1073{
1074 switch (dr) {
1075 case 0 ... 3:
1076 *val = vcpu->arch.db[dr];
1077 break;
1078 case 4:
020df079
GN		 1079 /* fall through */
1080 case 6:
73aaf249
JK		 1081 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1082 *val = vcpu->arch.dr6;
1083 else
1084 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1085 break;
1086 case 5:
020df079
GN		 1087 /* fall through */
1088 default: /* 7 */
1089 *val = vcpu->arch.dr7;
1090 break;
1091 }
338dbc97
GN		 1092 return 0;
1093}
020df079
GN		 1094EXPORT_SYMBOL_GPL(kvm_get_dr);
1095
022cd0e8
AK		 1096bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1097{
1098 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1099 u64 data;
1100 int err;
1101
c6702c9d 1102 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1103 if (err)
1104 return err;
1105 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1106 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1107 return err;
1108}
1109EXPORT_SYMBOL_GPL(kvm_rdpmc);
1110
043405e1
CO		 1111/*
1112 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1113 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1114 *
1115 * This list is modified at module load time to reflect the
e3267cbb 1116 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1117 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1118 * may depend on host virtualization features rather than host cpu features.
043405e1 1119 */
e3267cbb 1120
043405e1
CO		 1121static u32 msrs_to_save[] = {
1122 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1123 MSR_STAR,
043405e1
CO		 1124#ifdef CONFIG_X86_64
1125 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1126#endif
b3897a49 1127 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1128 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1129 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1130 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1131 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1132 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1133 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1134 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1135 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
043405e1
CO		 1136};
1137
1138static unsigned num_msrs_to_save;
1139
62ef68bb
PB		 1140static u32 emulated_msrs[] = {
1141 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1142 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1143 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1144 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1145 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1146 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1147 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1148 HV_X64_MSR_RESET,
11c4b1ca 1149 HV_X64_MSR_VP_INDEX,
9eec50b8 1150 HV_X64_MSR_VP_RUNTIME,
5c919412 1151 HV_X64_MSR_SCONTROL,
1f4b34f8 1152 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1153 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1154 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1155 HV_X64_MSR_TSC_EMULATION_STATUS,
1156
1157 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1158 MSR_KVM_PV_EOI_EN,
1159
ba904635 1160 MSR_IA32_TSC_ADJUST,
a3e06bbe 1161 MSR_IA32_TSCDEADLINE,
2bdb76c0 1162 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1163 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1164 MSR_IA32_MCG_STATUS,
1165 MSR_IA32_MCG_CTL,
c45dcc71 1166 MSR_IA32_MCG_EXT_CTL,
64d60670 1167 MSR_IA32_SMBASE,
52797bf9 1168 MSR_SMI_COUNT,
db2336a8
KH		 1169 MSR_PLATFORM_INFO,
1170 MSR_MISC_FEATURES_ENABLES,
bc226f07 1171 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1172};
1173
62ef68bb
PB		 1174static unsigned num_emulated_msrs;
1175
801e459a
TL		 1176/*
1177 * List of msr numbers which are used to expose MSR-based features that
1178 * can be used by a hypervisor to validate requested CPU features.
1179 */
1180static u32 msr_based_features[] = {
1389309c
PB		 1181 MSR_IA32_VMX_BASIC,
1182 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1183 MSR_IA32_VMX_PINBASED_CTLS,
1184 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1185 MSR_IA32_VMX_PROCBASED_CTLS,
1186 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1187 MSR_IA32_VMX_EXIT_CTLS,
1188 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1189 MSR_IA32_VMX_ENTRY_CTLS,
1190 MSR_IA32_VMX_MISC,
1191 MSR_IA32_VMX_CR0_FIXED0,
1192 MSR_IA32_VMX_CR0_FIXED1,
1193 MSR_IA32_VMX_CR4_FIXED0,
1194 MSR_IA32_VMX_CR4_FIXED1,
1195 MSR_IA32_VMX_VMCS_ENUM,
1196 MSR_IA32_VMX_PROCBASED_CTLS2,
1197 MSR_IA32_VMX_EPT_VPID_CAP,
1198 MSR_IA32_VMX_VMFUNC,
1199
d1d93fa9 1200 MSR_F10H_DECFG,
518e7b94 1201 MSR_IA32_UCODE_REV,
cd283252 1202 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1203};
1204
1205static unsigned int num_msr_based_features;
1206
5b76a3cf
PB		 1207u64 kvm_get_arch_capabilities(void)
1208{
1209 u64 data;
1210
1211 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1212
1213 /*
1214 * If we're doing cache flushes (either "always" or "cond")
1215 * we will do one whenever the guest does a vmlaunch/vmresume.
1216 * If an outer hypervisor is doing the cache flush for us
1217 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1218 * capability to the guest too, and if EPT is disabled we're not
1219 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1220 * require a nested hypervisor to do a flush of its own.
1221 */
1222 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1223 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1224
1225 return data;
1226}
1227EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1228
66421c1e
WL		 1229static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1230{
1231 switch (msr->index) {
cd283252 1232 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1233 msr->data = kvm_get_arch_capabilities();
1234 break;
1235 case MSR_IA32_UCODE_REV:
cd283252 1236 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1237 break;
66421c1e
WL		 1238 default:
1239 if (kvm_x86_ops->get_msr_feature(msr))
1240 return 1;
1241 }
1242 return 0;
1243}
1244
801e459a
TL		 1245static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1246{
1247 struct kvm_msr_entry msr;
66421c1e 1248 int r;
801e459a
TL		 1249
1250 msr.index = index;
66421c1e
WL		 1251 r = kvm_get_msr_feature(&msr);
1252 if (r)
1253 return r;
801e459a
TL		 1254
1255 *data = msr.data;
1256
1257 return 0;
1258}
1259
384bb783 1260bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1261{
b69e8cae 1262 if (efer & efer_reserved_bits)
384bb783 1263 return false;
15c4a640 1264
1b4d56b8 1265 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1266 return false;
1b2fd70c 1267
1b4d56b8 1268 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1269 return false;
d8017474 1270
384bb783
JK		 1271 return true;
1272}
1273EXPORT_SYMBOL_GPL(kvm_valid_efer);
1274
1275static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1276{
1277 u64 old_efer = vcpu->arch.efer;
1278
1279 if (!kvm_valid_efer(vcpu, efer))
1280 return 1;
1281
1282 if (is_paging(vcpu)
1283 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1284 return 1;
1285
15c4a640 1286 efer &= ~EFER_LMA;
f6801dff 1287 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1288
a3d204e2
SY		 1289 kvm_x86_ops->set_efer(vcpu, efer);
1290
aad82703
SY		 1291 /* Update reserved bits */
1292 if ((efer ^ old_efer) & EFER_NX)
1293 kvm_mmu_reset_context(vcpu);
1294
b69e8cae 1295 return 0;
15c4a640
CO		 1296}
1297
f2b4b7dd
JR		 1298void kvm_enable_efer_bits(u64 mask)
1299{
1300 efer_reserved_bits &= ~mask;
1301}
1302EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1303
15c4a640
CO		 1304/*
1305 * Writes msr value into into the appropriate "register".
1306 * Returns 0 on success, non-0 otherwise.
1307 * Assumes vcpu_load() was already called.
1308 */
8fe8ab46 1309int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1310{
854e8bb1
NA		 1311 switch (msr->index) {
1312 case MSR_FS_BASE:
1313 case MSR_GS_BASE:
1314 case MSR_KERNEL_GS_BASE:
1315 case MSR_CSTAR:
1316 case MSR_LSTAR:
fd8cb433 1317 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1318 return 1;
1319 break;
1320 case MSR_IA32_SYSENTER_EIP:
1321 case MSR_IA32_SYSENTER_ESP:
1322 /*
1323 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1324 * non-canonical address is written on Intel but not on
1325 * AMD (which ignores the top 32-bits, because it does
1326 * not implement 64-bit SYSENTER).
1327 *
1328 * 64-bit code should hence be able to write a non-canonical
1329 * value on AMD. Making the address canonical ensures that
1330 * vmentry does not fail on Intel after writing a non-canonical
1331 * value, and that something deterministic happens if the guest
1332 * invokes 64-bit SYSENTER.
1333 */
fd8cb433 1334 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1335 }
8fe8ab46 1336 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1337}
854e8bb1 1338EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1339
313a3dc7
CO		 1340/*
1341 * Adapt set_msr() to msr_io()'s calling convention
1342 */
609e36d3
PB		 1343static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1344{
1345 struct msr_data msr;
1346 int r;
1347
1348 msr.index = index;
1349 msr.host_initiated = true;
1350 r = kvm_get_msr(vcpu, &msr);
1351 if (r)
1352 return r;
1353
1354 *data = msr.data;
1355 return 0;
1356}
1357
313a3dc7
CO		 1358static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1359{
8fe8ab46
WA		 1360 struct msr_data msr;
1361
1362 msr.data = *data;
1363 msr.index = index;
1364 msr.host_initiated = true;
1365 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1366}
1367
16e8d74d
MT		 1368#ifdef CONFIG_X86_64
1369struct pvclock_gtod_data {
1370 seqcount_t seq;
1371
1372 struct { /* extract of a clocksource struct */
1373 int vclock_mode;
a5a1d1c2
TG		 1374 u64 cycle_last;
1375 u64 mask;
16e8d74d
MT		 1376 u32 mult;
1377 u32 shift;
1378 } clock;
1379
cbcf2dd3
TG		 1380 u64 boot_ns;
1381 u64 nsec_base;
55dd00a7 1382 u64 wall_time_sec;
16e8d74d
MT		 1383};
1384
1385static struct pvclock_gtod_data pvclock_gtod_data;
1386
1387static void update_pvclock_gtod(struct timekeeper *tk)
1388{
1389 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1390 u64 boot_ns;
1391
876e7881 1392 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1393
1394 write_seqcount_begin(&vdata->seq);
1395
1396 /* copy pvclock gtod data */
876e7881
PZ		 1397 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1398 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1399 vdata->clock.mask = tk->tkr_mono.mask;
1400 vdata->clock.mult = tk->tkr_mono.mult;
1401 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1402
cbcf2dd3 1403 vdata->boot_ns = boot_ns;
876e7881 1404 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1405
55dd00a7
MT		 1406 vdata->wall_time_sec = tk->xtime_sec;
1407
16e8d74d
MT		 1408 write_seqcount_end(&vdata->seq);
1409}
1410#endif
1411
bab5bb39
NK		 1412void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1413{
1414 /*
1415 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1416 * vcpu_enter_guest. This function is only called from
1417 * the physical CPU that is running vcpu.
1418 */
1419 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1420}
16e8d74d 1421
18068523
GOC		 1422static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1423{
9ed3c444
AK		 1424 int version;
1425 int r;
50d0a0f9 1426 struct pvclock_wall_clock wc;
87aeb54f 1427 struct timespec64 boot;
18068523
GOC		 1428
1429 if (!wall_clock)
1430 return;
1431
9ed3c444
AK		 1432 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1433 if (r)
1434 return;
1435
1436 if (version & 1)
1437 ++version; /* first time write, random junk */
1438
1439 ++version;
18068523 1440
1dab1345
NK		 1441 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1442 return;
18068523 1443
50d0a0f9
GH		 1444 /*
1445 * The guest calculates current wall clock time by adding
34c238a1 1446 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1447 * wall clock specified here. guest system time equals host
1448 * system time for us, thus we must fill in host boot time here.
1449 */
87aeb54f 1450 getboottime64(&boot);
50d0a0f9 1451
4b648665 1452 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1453 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1454 boot = timespec64_sub(boot, ts);
4b648665 1455 }
87aeb54f 1456 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1457 wc.nsec = boot.tv_nsec;
1458 wc.version = version;
18068523
GOC		 1459
1460 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1461
1462 version++;
1463 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1464}
1465
50d0a0f9
GH		 1466static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1467{
b51012de
PB		 1468 do_shl32_div32(dividend, divisor);
1469 return dividend;
50d0a0f9
GH		 1470}
1471
3ae13faa 1472static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1473 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1474{
5f4e3f88 1475 uint64_t scaled64;
50d0a0f9
GH		 1476 int32_t shift = 0;
1477 uint64_t tps64;
1478 uint32_t tps32;
1479
3ae13faa
PB		 1480 tps64 = base_hz;
1481 scaled64 = scaled_hz;
50933623 1482 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1483 tps64 >>= 1;
1484 shift--;
1485 }
1486
1487 tps32 = (uint32_t)tps64;
50933623
JK		 1488 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1489 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1490 scaled64 >>= 1;
1491 else
1492 tps32 <<= 1;
50d0a0f9
GH		 1493 shift++;
1494 }
1495
5f4e3f88
ZA		 1496 *pshift = shift;
1497 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1498
3ae13faa
PB		 1499 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1500 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1501}
1502
d828199e 1503#ifdef CONFIG_X86_64
16e8d74d 1504static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1505#endif
16e8d74d 1506
c8076604 1507static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1508static unsigned long max_tsc_khz;
c8076604 1509
cc578287 1510static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1511{
cc578287
ZA		 1512 u64 v = (u64)khz * (1000000 + ppm);
1513 do_div(v, 1000000);
1514 return v;
1e993611
JR		 1515}
1516
381d585c
HZ		 1517static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1518{
1519 u64 ratio;
1520
1521 /* Guest TSC same frequency as host TSC? */
1522 if (!scale) {
1523 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1524 return 0;
1525 }
1526
1527 /* TSC scaling supported? */
1528 if (!kvm_has_tsc_control) {
1529 if (user_tsc_khz > tsc_khz) {
1530 vcpu->arch.tsc_catchup = 1;
1531 vcpu->arch.tsc_always_catchup = 1;
1532 return 0;
1533 } else {
1534 WARN(1, "user requested TSC rate below hardware speed\n");
1535 return -1;
1536 }
1537 }
1538
1539 /* TSC scaling required - calculate ratio */
1540 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1541 user_tsc_khz, tsc_khz);
1542
1543 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1544 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1545 user_tsc_khz);
1546 return -1;
1547 }
1548
1549 vcpu->arch.tsc_scaling_ratio = ratio;
1550 return 0;
1551}
1552
4941b8cb 1553static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1554{
cc578287
ZA		 1555 u32 thresh_lo, thresh_hi;
1556 int use_scaling = 0;
217fc9cf 1557
03ba32ca 1558 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1559 if (user_tsc_khz == 0) {
ad721883
HZ		 1560 /* set tsc_scaling_ratio to a safe value */
1561 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1562 return -1;
ad721883 1563 }
03ba32ca 1564
c285545f 1565 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1566 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1567 &vcpu->arch.virtual_tsc_shift,
1568 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1569 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1570
1571 /*
1572 * Compute the variation in TSC rate which is acceptable
1573 * within the range of tolerance and decide if the
1574 * rate being applied is within that bounds of the hardware
1575 * rate. If so, no scaling or compensation need be done.
1576 */
1577 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1578 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1579 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1580 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1581 use_scaling = 1;
1582 }
4941b8cb 1583 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1584}
1585
1586static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1587{
e26101b1 1588 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1589 vcpu->arch.virtual_tsc_mult,
1590 vcpu->arch.virtual_tsc_shift);
e26101b1 1591 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1592 return tsc;
1593}
1594
b0c39dc6
VK		 1595static inline int gtod_is_based_on_tsc(int mode)
1596{
1597 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1598}
1599
69b0049a 1600static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1601{
1602#ifdef CONFIG_X86_64
1603 bool vcpus_matched;
b48aa97e
MT		 1604 struct kvm_arch *ka = &vcpu->kvm->arch;
1605 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1606
1607 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1608 atomic_read(&vcpu->kvm->online_vcpus));
1609
7f187922
MT		 1610 /*
1611 * Once the masterclock is enabled, always perform request in
1612 * order to update it.
1613 *
1614 * In order to enable masterclock, the host clocksource must be TSC
1615 * and the vcpus need to have matched TSCs. When that happens,
1616 * perform request to enable masterclock.
1617 */
1618 if (ka->use_master_clock ||
b0c39dc6 1619 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1620 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1621
1622 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1623 atomic_read(&vcpu->kvm->online_vcpus),
1624 ka->use_master_clock, gtod->clock.vclock_mode);
1625#endif
1626}
1627
ba904635
WA		 1628static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1629{
e79f245d 1630 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1631 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1632}
1633
35181e86
HZ		 1634/*
1635 * Multiply tsc by a fixed point number represented by ratio.
1636 *
1637 * The most significant 64-N bits (mult) of ratio represent the
1638 * integral part of the fixed point number; the remaining N bits
1639 * (frac) represent the fractional part, ie. ratio represents a fixed
1640 * point number (mult + frac * 2^(-N)).
1641 *
1642 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1643 */
1644static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1645{
1646 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1647}
1648
1649u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1650{
1651 u64 _tsc = tsc;
1652 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1653
1654 if (ratio != kvm_default_tsc_scaling_ratio)
1655 _tsc = __scale_tsc(ratio, tsc);
1656
1657 return _tsc;
1658}
1659EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1660
07c1419a
HZ		 1661static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1662{
1663 u64 tsc;
1664
1665 tsc = kvm_scale_tsc(vcpu, rdtsc());
1666
1667 return target_tsc - tsc;
1668}
1669
4ba76538
HZ		 1670u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1671{
e79f245d
KA		 1672 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1673
1674 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1675}
1676EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1677
a545ab6a
LC		 1678static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1679{
326e7425 1680 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1681}
1682
b0c39dc6
VK		 1683static inline bool kvm_check_tsc_unstable(void)
1684{
1685#ifdef CONFIG_X86_64
1686 /*
1687 * TSC is marked unstable when we're running on Hyper-V,
1688 * 'TSC page' clocksource is good.
1689 */
1690 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1691 return false;
1692#endif
1693 return check_tsc_unstable();
1694}
1695
8fe8ab46 1696void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1697{
1698 struct kvm *kvm = vcpu->kvm;
f38e098f 1699 u64 offset, ns, elapsed;
99e3e30a 1700 unsigned long flags;
b48aa97e 1701 bool matched;
0d3da0d2 1702 bool already_matched;
8fe8ab46 1703 u64 data = msr->data;
c5e8ec8e 1704 bool synchronizing = false;
99e3e30a 1705
038f8c11 1706 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1707 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1708 ns = ktime_get_boot_ns();
f38e098f 1709 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1710
03ba32ca 1711 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1712 if (data == 0 && msr->host_initiated) {
1713 /*
1714 * detection of vcpu initialization -- need to sync
1715 * with other vCPUs. This particularly helps to keep
1716 * kvm_clock stable after CPU hotplug
1717 */
1718 synchronizing = true;
1719 } else {
1720 u64 tsc_exp = kvm->arch.last_tsc_write +
1721 nsec_to_cycles(vcpu, elapsed);
1722 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1723 /*
1724 * Special case: TSC write with a small delta (1 second)
1725 * of virtual cycle time against real time is
1726 * interpreted as an attempt to synchronize the CPU.
1727 */
1728 synchronizing = data < tsc_exp + tsc_hz &&
1729 data + tsc_hz > tsc_exp;
1730 }
c5e8ec8e 1731 }
f38e098f
ZA		 1732
1733 /*
5d3cb0f6
ZA		 1734 * For a reliable TSC, we can match TSC offsets, and for an unstable
1735 * TSC, we add elapsed time in this computation. We could let the
1736 * compensation code attempt to catch up if we fall behind, but
1737 * it's better to try to match offsets from the beginning.
1738 */
c5e8ec8e 1739 if (synchronizing &&
5d3cb0f6 1740 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1741 if (!kvm_check_tsc_unstable()) {
e26101b1 1742 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1743 pr_debug("kvm: matched tsc offset for %llu\n", data);
1744 } else {
857e4099 1745 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1746 data += delta;
07c1419a 1747 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1748 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1749 }
b48aa97e 1750 matched = true;
0d3da0d2 1751 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1752 } else {
1753 /*
1754 * We split periods of matched TSC writes into generations.
1755 * For each generation, we track the original measured
1756 * nanosecond time, offset, and write, so if TSCs are in
1757 * sync, we can match exact offset, and if not, we can match
4a969980 1758 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1759 *
1760 * These values are tracked in kvm->arch.cur_xxx variables.
1761 */
1762 kvm->arch.cur_tsc_generation++;
1763 kvm->arch.cur_tsc_nsec = ns;
1764 kvm->arch.cur_tsc_write = data;
1765 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1766 matched = false;
0d3da0d2 1767 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1768 kvm->arch.cur_tsc_generation, data);
f38e098f 1769 }
e26101b1
ZA		 1770
1771 /*
1772 * We also track th most recent recorded KHZ, write and time to
1773 * allow the matching interval to be extended at each write.
1774 */
f38e098f
ZA		 1775 kvm->arch.last_tsc_nsec = ns;
1776 kvm->arch.last_tsc_write = data;
5d3cb0f6 1777 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1778
b183aa58 1779 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1780
1781 /* Keep track of which generation this VCPU has synchronized to */
1782 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1783 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1784 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1785
d6321d49 1786 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1787 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1788
a545ab6a 1789 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1790 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1791
1792 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1793 if (!matched) {
b48aa97e 1794 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1795 } else if (!already_matched) {
1796 kvm->arch.nr_vcpus_matched_tsc++;
1797 }
b48aa97e
MT		 1798
1799 kvm_track_tsc_matching(vcpu);
1800 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1801}
e26101b1 1802
99e3e30a
ZA		 1803EXPORT_SYMBOL_GPL(kvm_write_tsc);
1804
58ea6767
HZ		 1805static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1806 s64 adjustment)
1807{
326e7425
LS		 1808 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1809 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1810}
1811
1812static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1813{
1814 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1815 WARN_ON(adjustment < 0);
1816 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1817 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1818}
1819
d828199e
MT		 1820#ifdef CONFIG_X86_64
1821
a5a1d1c2 1822static u64 read_tsc(void)
d828199e 1823{
a5a1d1c2 1824 u64 ret = (u64)rdtsc_ordered();
03b9730b 1825 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1826
1827 if (likely(ret >= last))
1828 return ret;
1829
1830 /*
1831 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1832 * predictable (it's just a function of time and the likely is
d828199e
MT		 1833 * very likely) and there's a data dependence, so force GCC
1834 * to generate a branch instead. I don't barrier() because
1835 * we don't actually need a barrier, and if this function
1836 * ever gets inlined it will generate worse code.
1837 */
1838 asm volatile ("");
1839 return last;
1840}
1841
b0c39dc6 1842static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1843{
1844 long v;
1845 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1846 u64 tsc_pg_val;
1847
1848 switch (gtod->clock.vclock_mode) {
1849 case VCLOCK_HVCLOCK:
1850 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1851 tsc_timestamp);
1852 if (tsc_pg_val != U64_MAX) {
1853 /* TSC page valid */
1854 *mode = VCLOCK_HVCLOCK;
1855 v = (tsc_pg_val - gtod->clock.cycle_last) &
1856 gtod->clock.mask;
1857 } else {
1858 /* TSC page invalid */
1859 *mode = VCLOCK_NONE;
1860 }
1861 break;
1862 case VCLOCK_TSC:
1863 *mode = VCLOCK_TSC;
1864 *tsc_timestamp = read_tsc();
1865 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1866 gtod->clock.mask;
1867 break;
1868 default:
1869 *mode = VCLOCK_NONE;
1870 }
d828199e 1871
b0c39dc6
VK		 1872 if (*mode == VCLOCK_NONE)
1873 *tsc_timestamp = v = 0;
d828199e 1874
d828199e
MT		 1875 return v * gtod->clock.mult;
1876}
1877
b0c39dc6 1878static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1879{
cbcf2dd3 1880 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1881 unsigned long seq;
d828199e 1882 int mode;
cbcf2dd3 1883 u64 ns;
d828199e 1884
d828199e
MT		 1885 do {
1886 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1887 ns = gtod->nsec_base;
b0c39dc6 1888 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1889 ns >>= gtod->clock.shift;
cbcf2dd3 1890 ns += gtod->boot_ns;
d828199e 1891 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1892 *t = ns;
d828199e
MT		 1893
1894 return mode;
1895}
1896
899a31f5 1897static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1898{
1899 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1900 unsigned long seq;
1901 int mode;
1902 u64 ns;
1903
1904 do {
1905 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1906 ts->tv_sec = gtod->wall_time_sec;
1907 ns = gtod->nsec_base;
b0c39dc6 1908 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1909 ns >>= gtod->clock.shift;
1910 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1911
1912 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1913 ts->tv_nsec = ns;
1914
1915 return mode;
1916}
1917
b0c39dc6
VK		 1918/* returns true if host is using TSC based clocksource */
1919static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1920{
d828199e 1921 /* checked again under seqlock below */
b0c39dc6 1922 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1923 return false;
1924
b0c39dc6
VK		 1925 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1926 tsc_timestamp));
d828199e 1927}
55dd00a7 1928
b0c39dc6 1929/* returns true if host is using TSC based clocksource */
899a31f5 1930static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1931 u64 *tsc_timestamp)
55dd00a7
MT		 1932{
1933 /* checked again under seqlock below */
b0c39dc6 1934 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1935 return false;
1936
b0c39dc6 1937 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1938}
d828199e
MT		 1939#endif
1940
1941/*
1942 *
b48aa97e
MT		 1943 * Assuming a stable TSC across physical CPUS, and a stable TSC
1944 * across virtual CPUs, the following condition is possible.
1945 * Each numbered line represents an event visible to both
d828199e
MT		 1946 * CPUs at the next numbered event.
1947 *
1948 * "timespecX" represents host monotonic time. "tscX" represents
1949 * RDTSC value.
1950 *
1951 * VCPU0 on CPU0 | VCPU1 on CPU1
1952 *
1953 * 1. read timespec0,tsc0
1954 * 2. | timespec1 = timespec0 + N
1955 * | tsc1 = tsc0 + M
1956 * 3. transition to guest | transition to guest
1957 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1958 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1959 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1960 *
1961 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1962 *
1963 * - ret0 < ret1
1964 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1965 * ...
1966 * - 0 < N - M => M < N
1967 *
1968 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1969 * always the case (the difference between two distinct xtime instances
1970 * might be smaller then the difference between corresponding TSC reads,
1971 * when updating guest vcpus pvclock areas).
1972 *
1973 * To avoid that problem, do not allow visibility of distinct
1974 * system_timestamp/tsc_timestamp values simultaneously: use a master
1975 * copy of host monotonic time values. Update that master copy
1976 * in lockstep.
1977 *
b48aa97e 1978 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1979 *
1980 */
1981
1982static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1983{
1984#ifdef CONFIG_X86_64
1985 struct kvm_arch *ka = &kvm->arch;
1986 int vclock_mode;
b48aa97e
MT		 1987 bool host_tsc_clocksource, vcpus_matched;
1988
1989 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1990 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1991
1992 /*
1993 * If the host uses TSC clock, then passthrough TSC as stable
1994 * to the guest.
1995 */
b48aa97e 1996 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1997 &ka->master_kernel_ns,
1998 &ka->master_cycle_now);
1999
16a96021 2000 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2001 && !ka->backwards_tsc_observed
54750f2c 2002 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2003
d828199e
MT		 2004 if (ka->use_master_clock)
2005 atomic_set(&kvm_guest_has_master_clock, 1);
2006
2007 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2008 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2009 vcpus_matched);
d828199e
MT		 2010#endif
2011}
2012
2860c4b1
PB		 2013void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2014{
2015 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2016}
2017
2e762ff7
MT		 2018static void kvm_gen_update_masterclock(struct kvm *kvm)
2019{
2020#ifdef CONFIG_X86_64
2021 int i;
2022 struct kvm_vcpu *vcpu;
2023 struct kvm_arch *ka = &kvm->arch;
2024
2025 spin_lock(&ka->pvclock_gtod_sync_lock);
2026 kvm_make_mclock_inprogress_request(kvm);
2027 /* no guest entries from this point */
2028 pvclock_update_vm_gtod_copy(kvm);
2029
2030 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2031 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2032
2033 /* guest entries allowed */
2034 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2035 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2036
2037 spin_unlock(&ka->pvclock_gtod_sync_lock);
2038#endif
2039}
2040
e891a32e 2041u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2042{
108b249c 2043 struct kvm_arch *ka = &kvm->arch;
8b953440 2044 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2045 u64 ret;
108b249c 2046
8b953440
PB		 2047 spin_lock(&ka->pvclock_gtod_sync_lock);
2048 if (!ka->use_master_clock) {
2049 spin_unlock(&ka->pvclock_gtod_sync_lock);
2050 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 2051 }
2052
8b953440
PB		 2053 hv_clock.tsc_timestamp = ka->master_cycle_now;
2054 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2055 spin_unlock(&ka->pvclock_gtod_sync_lock);
2056
e2c2206a
WL		 2057 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2058 get_cpu();
2059
e70b57a6
WL		 2060 if (__this_cpu_read(cpu_tsc_khz)) {
2061 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2062 &hv_clock.tsc_shift,
2063 &hv_clock.tsc_to_system_mul);
2064 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2065 } else
2066 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2067
2068 put_cpu();
2069
2070 return ret;
108b249c
PB		 2071}
2072
0d6dd2ff
PB		 2073static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2074{
2075 struct kvm_vcpu_arch *vcpu = &v->arch;
2076 struct pvclock_vcpu_time_info guest_hv_clock;
2077
4e335d9e 2078 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2079 &guest_hv_clock, sizeof(guest_hv_clock))))
2080 return;
2081
2082 /* This VCPU is paused, but it's legal for a guest to read another
2083 * VCPU's kvmclock, so we really have to follow the specification where
2084 * it says that version is odd if data is being modified, and even after
2085 * it is consistent.
2086 *
2087 * Version field updates must be kept separate. This is because
2088 * kvm_write_guest_cached might use a "rep movs" instruction, and
2089 * writes within a string instruction are weakly ordered. So there
2090 * are three writes overall.
2091 *
2092 * As a small optimization, only write the version field in the first
2093 * and third write. The vcpu->pv_time cache is still valid, because the
2094 * version field is the first in the struct.
2095 */
2096 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2097
51c4b8bb
LA		 2098 if (guest_hv_clock.version & 1)
2099 ++guest_hv_clock.version; /* first time write, random junk */
2100
0d6dd2ff 2101 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2102 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2103 &vcpu->hv_clock,
2104 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2105
2106 smp_wmb();
2107
2108 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2109 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2110
2111 if (vcpu->pvclock_set_guest_stopped_request) {
2112 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2113 vcpu->pvclock_set_guest_stopped_request = false;
2114 }
2115
2116 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2117
4e335d9e
PB		 2118 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2119 &vcpu->hv_clock,
2120 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2121
2122 smp_wmb();
2123
2124 vcpu->hv_clock.version++;
4e335d9e
PB		 2125 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2126 &vcpu->hv_clock,
2127 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2128}
2129
34c238a1 2130static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2131{
78db6a50 2132 unsigned long flags, tgt_tsc_khz;
18068523 2133 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2134 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2135 s64 kernel_ns;
d828199e 2136 u64 tsc_timestamp, host_tsc;
51d59c6b 2137 u8 pvclock_flags;
d828199e
MT		 2138 bool use_master_clock;
2139
2140 kernel_ns = 0;
2141 host_tsc = 0;
18068523 2142
d828199e
MT		 2143 /*
2144 * If the host uses TSC clock, then passthrough TSC as stable
2145 * to the guest.
2146 */
2147 spin_lock(&ka->pvclock_gtod_sync_lock);
2148 use_master_clock = ka->use_master_clock;
2149 if (use_master_clock) {
2150 host_tsc = ka->master_cycle_now;
2151 kernel_ns = ka->master_kernel_ns;
2152 }
2153 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2154
2155 /* Keep irq disabled to prevent changes to the clock */
2156 local_irq_save(flags);
78db6a50
PB		 2157 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2158 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2159 local_irq_restore(flags);
2160 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2161 return 1;
2162 }
d828199e 2163 if (!use_master_clock) {
4ea1636b 2164 host_tsc = rdtsc();
108b249c 2165 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2166 }
2167
4ba76538 2168 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2169
c285545f
ZA		 2170 /*
2171 * We may have to catch up the TSC to match elapsed wall clock
2172 * time for two reasons, even if kvmclock is used.
2173 * 1) CPU could have been running below the maximum TSC rate
2174 * 2) Broken TSC compensation resets the base at each VCPU
2175 * entry to avoid unknown leaps of TSC even when running
2176 * again on the same CPU. This may cause apparent elapsed
2177 * time to disappear, and the guest to stand still or run
2178 * very slowly.
2179 */
2180 if (vcpu->tsc_catchup) {
2181 u64 tsc = compute_guest_tsc(v, kernel_ns);
2182 if (tsc > tsc_timestamp) {
f1e2b260 2183 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2184 tsc_timestamp = tsc;
2185 }
50d0a0f9
GH		 2186 }
2187
18068523
GOC		 2188 local_irq_restore(flags);
2189
0d6dd2ff 2190 /* With all the info we got, fill in the values */
18068523 2191
78db6a50
PB		 2192 if (kvm_has_tsc_control)
2193 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2194
2195 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2196 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2197 &vcpu->hv_clock.tsc_shift,
2198 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2199 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2200 }
2201
1d5f066e 2202 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2203 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2204 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2205
d828199e 2206 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2207 pvclock_flags = 0;
d828199e
MT		 2208 if (use_master_clock)
2209 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2210
78c0337a
MT		 2211 vcpu->hv_clock.flags = pvclock_flags;
2212
095cf55d
PB		 2213 if (vcpu->pv_time_enabled)
2214 kvm_setup_pvclock_page(v);
2215 if (v == kvm_get_vcpu(v->kvm, 0))
2216 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2217 return 0;
c8076604
GH		 2218}
2219
0061d53d
MT		 2220/*
2221 * kvmclock updates which are isolated to a given vcpu, such as
2222 * vcpu->cpu migration, should not allow system_timestamp from
2223 * the rest of the vcpus to remain static. Otherwise ntp frequency
2224 * correction applies to one vcpu's system_timestamp but not
2225 * the others.
2226 *
2227 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2228 * We need to rate-limit these requests though, as they can
2229 * considerably slow guests that have a large number of vcpus.
2230 * The time for a remote vcpu to update its kvmclock is bound
2231 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2232 */
2233
7e44e449
AJ		 2234#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2235
2236static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2237{
2238 int i;
7e44e449
AJ		 2239 struct delayed_work *dwork = to_delayed_work(work);
2240 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2241 kvmclock_update_work);
2242 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2243 struct kvm_vcpu *vcpu;
2244
2245 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2246 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2247 kvm_vcpu_kick(vcpu);
2248 }
2249}
2250
7e44e449
AJ		 2251static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2252{
2253 struct kvm *kvm = v->kvm;
2254
105b21bb 2255 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2256 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2257 KVMCLOCK_UPDATE_DELAY);
2258}
2259
332967a3
AJ		 2260#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2261
2262static void kvmclock_sync_fn(struct work_struct *work)
2263{
2264 struct delayed_work *dwork = to_delayed_work(work);
2265 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2266 kvmclock_sync_work);
2267 struct kvm *kvm = container_of(ka, struct kvm, arch);
2268
630994b3
MT		 2269 if (!kvmclock_periodic_sync)
2270 return;
2271
332967a3
AJ		 2272 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2273 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2274 KVMCLOCK_SYNC_PERIOD);
2275}
2276
9ffd986c 2277static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2278{
890ca9ae
HY		 2279 u64 mcg_cap = vcpu->arch.mcg_cap;
2280 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2281 u32 msr = msr_info->index;
2282 u64 data = msr_info->data;
890ca9ae 2283
15c4a640 2284 switch (msr) {
15c4a640 2285 case MSR_IA32_MCG_STATUS:
890ca9ae 2286 vcpu->arch.mcg_status = data;
15c4a640 2287 break;
c7ac679c 2288 case MSR_IA32_MCG_CTL:
44883f01
PB		 2289 if (!(mcg_cap & MCG_CTL_P) &&
2290 (data || !msr_info->host_initiated))
890ca9ae
HY		 2291 return 1;
2292 if (data != 0 && data != ~(u64)0)
44883f01 2293 return 1;
890ca9ae
HY		 2294 vcpu->arch.mcg_ctl = data;
2295 break;
2296 default:
2297 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2298 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2299 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2300 /* only 0 or all 1s can be written to IA32_MCi_CTL
2301 * some Linux kernels though clear bit 10 in bank 4 to
2302 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2303 * this to avoid an uncatched #GP in the guest
2304 */
890ca9ae 2305 if ((offset & 0x3) == 0 &&
114be429 2306 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2307 return -1;
9ffd986c
WL		 2308 if (!msr_info->host_initiated &&
2309 (offset & 0x3) == 1 && data != 0)
2310 return -1;
890ca9ae
HY		 2311 vcpu->arch.mce_banks[offset] = data;
2312 break;
2313 }
2314 return 1;
2315 }
2316 return 0;
2317}
2318
ffde22ac
ES		 2319static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2320{
2321 struct kvm *kvm = vcpu->kvm;
2322 int lm = is_long_mode(vcpu);
2323 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2324 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2325 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2326 : kvm->arch.xen_hvm_config.blob_size_32;
2327 u32 page_num = data & ~PAGE_MASK;
2328 u64 page_addr = data & PAGE_MASK;
2329 u8 *page;
2330 int r;
2331
2332 r = -E2BIG;
2333 if (page_num >= blob_size)
2334 goto out;
2335 r = -ENOMEM;
ff5c2c03
SL		 2336 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2337 if (IS_ERR(page)) {
2338 r = PTR_ERR(page);
ffde22ac 2339 goto out;
ff5c2c03 2340 }
54bf36aa 2341 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2342 goto out_free;
2343 r = 0;
2344out_free:
2345 kfree(page);
2346out:
2347 return r;
2348}
2349
344d9588
GN		 2350static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2351{
2352 gpa_t gpa = data & ~0x3f;
2353
52a5c155
WL		 2354 /* Bits 3:5 are reserved, Should be zero */
2355 if (data & 0x38)
344d9588
GN		 2356 return 1;
2357
2358 vcpu->arch.apf.msr_val = data;
2359
2360 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2361 kvm_clear_async_pf_completion_queue(vcpu);
2362 kvm_async_pf_hash_reset(vcpu);
2363 return 0;
2364 }
2365
4e335d9e 2366 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2367 sizeof(u32)))
344d9588
GN		 2368 return 1;
2369
6adba527 2370 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2371 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2372 kvm_async_pf_wakeup_all(vcpu);
2373 return 0;
2374}
2375
12f9a48f
GC		 2376static void kvmclock_reset(struct kvm_vcpu *vcpu)
2377{
0b79459b 2378 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2379}
2380
f38a7b75
WL		 2381static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2382{
2383 ++vcpu->stat.tlb_flush;
2384 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2385}
2386
c9aaa895
GC		 2387static void record_steal_time(struct kvm_vcpu *vcpu)
2388{
2389 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2390 return;
2391
4e335d9e 2392 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2393 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2394 return;
2395
f38a7b75
WL		 2396 /*
2397 * Doing a TLB flush here, on the guest's behalf, can avoid
2398 * expensive IPIs.
2399 */
2400 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2401 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2402
35f3fae1
WL		 2403 if (vcpu->arch.st.steal.version & 1)
2404 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2405
2406 vcpu->arch.st.steal.version += 1;
2407
4e335d9e 2408 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2409 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2410
2411 smp_wmb();
2412
c54cdf14
LC		 2413 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2414 vcpu->arch.st.last_steal;
2415 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2416
4e335d9e 2417 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2418 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2419
2420 smp_wmb();
2421
2422 vcpu->arch.st.steal.version += 1;
c9aaa895 2423
4e335d9e 2424 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2425 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2426}
2427
8fe8ab46 2428int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2429{
5753785f 2430 bool pr = false;
8fe8ab46
WA		 2431 u32 msr = msr_info->index;
2432 u64 data = msr_info->data;
5753785f 2433
15c4a640 2434 switch (msr) {
2e32b719 2435 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2436 case MSR_IA32_UCODE_WRITE:
2437 case MSR_VM_HSAVE_PA:
2438 case MSR_AMD64_PATCH_LOADER:
2439 case MSR_AMD64_BU_CFG2:
405a353a 2440 case MSR_AMD64_DC_CFG:
0e1b869f 2441 case MSR_F15H_EX_CFG:
2e32b719
BP		 2442 break;
2443
518e7b94
WL		 2444 case MSR_IA32_UCODE_REV:
2445 if (msr_info->host_initiated)
2446 vcpu->arch.microcode_version = data;
2447 break;
0cf9135b
SC		 2448 case MSR_IA32_ARCH_CAPABILITIES:
2449 if (!msr_info->host_initiated)
2450 return 1;
2451 vcpu->arch.arch_capabilities = data;
2452 break;
15c4a640 2453 case MSR_EFER:
b69e8cae 2454 return set_efer(vcpu, data);
8f1589d9
AP		 2455 case MSR_K7_HWCR:
2456 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2457 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2458 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2459 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2460 if (data != 0) {
a737f256
CD		 2461 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2462 data);
8f1589d9
AP		 2463 return 1;
2464 }
15c4a640 2465 break;
f7c6d140
AP		 2466 case MSR_FAM10H_MMIO_CONF_BASE:
2467 if (data != 0) {
a737f256
CD		 2468 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2469 "0x%llx\n", data);
f7c6d140
AP		 2470 return 1;
2471 }
15c4a640 2472 break;
b5e2fec0
AG		 2473 case MSR_IA32_DEBUGCTLMSR:
2474 if (!data) {
2475 /* We support the non-activated case already */
2476 break;
2477 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2478 /* Values other than LBR and BTF are vendor-specific,
2479 thus reserved and should throw a #GP */
2480 return 1;
2481 }
a737f256
CD		 2482 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2483 __func__, data);
b5e2fec0 2484 break;
9ba075a6 2485 case 0x200 ... 0x2ff:
ff53604b 2486 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2487 case MSR_IA32_APICBASE:
58cb628d 2488 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2489 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2490 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2491 case MSR_IA32_TSCDEADLINE:
2492 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2493 break;
ba904635 2494 case MSR_IA32_TSC_ADJUST:
d6321d49 2495 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2496 if (!msr_info->host_initiated) {
d913b904 2497 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2498 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2499 }
2500 vcpu->arch.ia32_tsc_adjust_msr = data;
2501 }
2502 break;
15c4a640 2503 case MSR_IA32_MISC_ENABLE:
ad312c7c 2504 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2505 break;
64d60670
PB		 2506 case MSR_IA32_SMBASE:
2507 if (!msr_info->host_initiated)
2508 return 1;
2509 vcpu->arch.smbase = data;
2510 break;
dd259935
PB		 2511 case MSR_IA32_TSC:
2512 kvm_write_tsc(vcpu, msr_info);
2513 break;
52797bf9
LA		 2514 case MSR_SMI_COUNT:
2515 if (!msr_info->host_initiated)
2516 return 1;
2517 vcpu->arch.smi_count = data;
2518 break;
11c6bffa 2519 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2520 case MSR_KVM_WALL_CLOCK:
2521 vcpu->kvm->arch.wall_clock = data;
2522 kvm_write_wall_clock(vcpu->kvm, data);
2523 break;
11c6bffa 2524 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2525 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2526 struct kvm_arch *ka = &vcpu->kvm->arch;
2527
12f9a48f 2528 kvmclock_reset(vcpu);
18068523 2529
54750f2c
MT		 2530 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2531 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2532
2533 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2534 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2535
2536 ka->boot_vcpu_runs_old_kvmclock = tmp;
2537 }
2538
18068523 2539 vcpu->arch.time = data;
0061d53d 2540 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2541
2542 /* we verify if the enable bit is set... */
2543 if (!(data & 1))
2544 break;
2545
4e335d9e 2546 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2547 &vcpu->arch.pv_time, data & ~1ULL,
2548 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2549 vcpu->arch.pv_time_enabled = false;
2550 else
2551 vcpu->arch.pv_time_enabled = true;
32cad84f 2552
18068523
GOC		 2553 break;
2554 }
344d9588
GN		 2555 case MSR_KVM_ASYNC_PF_EN:
2556 if (kvm_pv_enable_async_pf(vcpu, data))
2557 return 1;
2558 break;
c9aaa895
GC		 2559 case MSR_KVM_STEAL_TIME:
2560
2561 if (unlikely(!sched_info_on()))
2562 return 1;
2563
2564 if (data & KVM_STEAL_RESERVED_MASK)
2565 return 1;
2566
4e335d9e 2567 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2568 data & KVM_STEAL_VALID_BITS,
2569 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2570 return 1;
2571
2572 vcpu->arch.st.msr_val = data;
2573
2574 if (!(data & KVM_MSR_ENABLED))
2575 break;
2576
c9aaa895
GC		 2577 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2578
2579 break;
ae7a2a3f 2580 case MSR_KVM_PV_EOI_EN:
72bbf935 2581 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2582 return 1;
2583 break;
c9aaa895 2584
890ca9ae
HY		 2585 case MSR_IA32_MCG_CTL:
2586 case MSR_IA32_MCG_STATUS:
81760dcc 2587 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2588 return set_msr_mce(vcpu, msr_info);
71db6023 2589
6912ac32
WH		 2590 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2591 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2592 pr = true; /* fall through */
2593 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2594 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2595 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2596 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2597
2598 if (pr || data != 0)
a737f256
CD		 2599 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2600 "0x%x data 0x%llx\n", msr, data);
5753785f 2601 break;
84e0cefa
JS		 2602 case MSR_K7_CLK_CTL:
2603 /*
2604 * Ignore all writes to this no longer documented MSR.
2605 * Writes are only relevant for old K7 processors,
2606 * all pre-dating SVM, but a recommended workaround from
4a969980 2607 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2608 * affected processor models on the command line, hence
2609 * the need to ignore the workaround.
2610 */
2611 break;
55cd8e5a 2612 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2613 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2614 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2615 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2616 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2617 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2618 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2619 return kvm_hv_set_msr_common(vcpu, msr, data,
2620 msr_info->host_initiated);
91c9c3ed 2621 case MSR_IA32_BBL_CR_CTL3:
2622 /* Drop writes to this legacy MSR -- see rdmsr
2623 * counterpart for further detail.
2624 */
fab0aa3b
EM		 2625 if (report_ignored_msrs)
2626 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2627 msr, data);
91c9c3ed 2628 break;
2b036c6b 2629 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2630 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2631 return 1;
2632 vcpu->arch.osvw.length = data;
2633 break;
2634 case MSR_AMD64_OSVW_STATUS:
d6321d49 2635 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2636 return 1;
2637 vcpu->arch.osvw.status = data;
2638 break;
db2336a8
KH		 2639 case MSR_PLATFORM_INFO:
2640 if (!msr_info->host_initiated ||
db2336a8
KH		 2641 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2642 cpuid_fault_enabled(vcpu)))
2643 return 1;
2644 vcpu->arch.msr_platform_info = data;
2645 break;
2646 case MSR_MISC_FEATURES_ENABLES:
2647 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2648 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2649 !supports_cpuid_fault(vcpu)))
2650 return 1;
2651 vcpu->arch.msr_misc_features_enables = data;
2652 break;
15c4a640 2653 default:
ffde22ac
ES		 2654 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2655 return xen_hvm_config(vcpu, data);
c6702c9d 2656 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2657 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2658 if (!ignore_msrs) {
ae0f5499 2659 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2660 msr, data);
ed85c068
AP		 2661 return 1;
2662 } else {
fab0aa3b
EM		 2663 if (report_ignored_msrs)
2664 vcpu_unimpl(vcpu,
2665 "ignored wrmsr: 0x%x data 0x%llx\n",
2666 msr, data);
ed85c068
AP		 2667 break;
2668 }
15c4a640
CO		 2669 }
2670 return 0;
2671}
2672EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2673
2674
2675/*
2676 * Reads an msr value (of 'msr_index') into 'pdata'.
2677 * Returns 0 on success, non-0 otherwise.
2678 * Assumes vcpu_load() was already called.
2679 */
609e36d3 2680int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2681{
609e36d3 2682 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2683}
ff651cb6 2684EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2685
44883f01 2686static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2687{
2688 u64 data;
890ca9ae
HY		 2689 u64 mcg_cap = vcpu->arch.mcg_cap;
2690 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2691
2692 switch (msr) {
15c4a640
CO		 2693 case MSR_IA32_P5_MC_ADDR:
2694 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2695 data = 0;
2696 break;
15c4a640 2697 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2698 data = vcpu->arch.mcg_cap;
2699 break;
c7ac679c 2700 case MSR_IA32_MCG_CTL:
44883f01 2701 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2702 return 1;
2703 data = vcpu->arch.mcg_ctl;
2704 break;
2705 case MSR_IA32_MCG_STATUS:
2706 data = vcpu->arch.mcg_status;
2707 break;
2708 default:
2709 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2710 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2711 u32 offset = msr - MSR_IA32_MC0_CTL;
2712 data = vcpu->arch.mce_banks[offset];
2713 break;
2714 }
2715 return 1;
2716 }
2717 *pdata = data;
2718 return 0;
2719}
2720
609e36d3 2721int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2722{
609e36d3 2723 switch (msr_info->index) {
890ca9ae 2724 case MSR_IA32_PLATFORM_ID:
15c4a640 2725 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2726 case MSR_IA32_DEBUGCTLMSR:
2727 case MSR_IA32_LASTBRANCHFROMIP:
2728 case MSR_IA32_LASTBRANCHTOIP:
2729 case MSR_IA32_LASTINTFROMIP:
2730 case MSR_IA32_LASTINTTOIP:
60af2ecd 2731 case MSR_K8_SYSCFG:
3afb1121
PB		 2732 case MSR_K8_TSEG_ADDR:
2733 case MSR_K8_TSEG_MASK:
60af2ecd 2734 case MSR_K7_HWCR:
61a6bd67 2735 case MSR_VM_HSAVE_PA:
1fdbd48c 2736 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2737 case MSR_AMD64_NB_CFG:
f7c6d140 2738 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2739 case MSR_AMD64_BU_CFG2:
0c2df2a1 2740 case MSR_IA32_PERF_CTL:
405a353a 2741 case MSR_AMD64_DC_CFG:
0e1b869f 2742 case MSR_F15H_EX_CFG:
609e36d3 2743 msr_info->data = 0;
15c4a640 2744 break;
c51eb52b 2745 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2746 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2747 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2748 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2749 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2750 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2751 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2752 msr_info->data = 0;
5753785f 2753 break;
742bc670 2754 case MSR_IA32_UCODE_REV:
518e7b94 2755 msr_info->data = vcpu->arch.microcode_version;
742bc670 2756 break;
0cf9135b
SC		 2757 case MSR_IA32_ARCH_CAPABILITIES:
2758 if (!msr_info->host_initiated &&
2759 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2760 return 1;
2761 msr_info->data = vcpu->arch.arch_capabilities;
2762 break;
dd259935
PB		 2763 case MSR_IA32_TSC:
2764 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2765 break;
9ba075a6 2766 case MSR_MTRRcap:
9ba075a6 2767 case 0x200 ... 0x2ff:
ff53604b 2768 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2769 case 0xcd: /* fsb frequency */
609e36d3 2770 msr_info->data = 3;
15c4a640 2771 break;
7b914098
JS		 2772 /*
2773 * MSR_EBC_FREQUENCY_ID
2774 * Conservative value valid for even the basic CPU models.
2775 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2776 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2777 * and 266MHz for model 3, or 4. Set Core Clock
2778 * Frequency to System Bus Frequency Ratio to 1 (bits
2779 * 31:24) even though these are only valid for CPU
2780 * models > 2, however guests may end up dividing or
2781 * multiplying by zero otherwise.
2782 */
2783 case MSR_EBC_FREQUENCY_ID:
609e36d3 2784 msr_info->data = 1 << 24;
7b914098 2785 break;
15c4a640 2786 case MSR_IA32_APICBASE:
609e36d3 2787 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2788 break;
0105d1a5 2789 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2790 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2791 break;
a3e06bbe 2792 case MSR_IA32_TSCDEADLINE:
609e36d3 2793 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2794 break;
ba904635 2795 case MSR_IA32_TSC_ADJUST:
609e36d3 2796 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2797 break;
15c4a640 2798 case MSR_IA32_MISC_ENABLE:
609e36d3 2799 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2800 break;
64d60670
PB		 2801 case MSR_IA32_SMBASE:
2802 if (!msr_info->host_initiated)
2803 return 1;
2804 msr_info->data = vcpu->arch.smbase;
15c4a640 2805 break;
52797bf9
LA		 2806 case MSR_SMI_COUNT:
2807 msr_info->data = vcpu->arch.smi_count;
2808 break;
847f0ad8
AG		 2809 case MSR_IA32_PERF_STATUS:
2810 /* TSC increment by tick */
609e36d3 2811 msr_info->data = 1000ULL;
847f0ad8 2812 /* CPU multiplier */
b0996ae4 2813 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2814 break;
15c4a640 2815 case MSR_EFER:
609e36d3 2816 msr_info->data = vcpu->arch.efer;
15c4a640 2817 break;
18068523 2818 case MSR_KVM_WALL_CLOCK:
11c6bffa 2819 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2820 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2821 break;
2822 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2823 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2824 msr_info->data = vcpu->arch.time;
18068523 2825 break;
344d9588 2826 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2827 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2828 break;
c9aaa895 2829 case MSR_KVM_STEAL_TIME:
609e36d3 2830 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2831 break;
1d92128f 2832 case MSR_KVM_PV_EOI_EN:
609e36d3 2833 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2834 break;
890ca9ae
HY		 2835 case MSR_IA32_P5_MC_ADDR:
2836 case MSR_IA32_P5_MC_TYPE:
2837 case MSR_IA32_MCG_CAP:
2838 case MSR_IA32_MCG_CTL:
2839 case MSR_IA32_MCG_STATUS:
81760dcc 2840 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2841 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2842 msr_info->host_initiated);
84e0cefa
JS		 2843 case MSR_K7_CLK_CTL:
2844 /*
2845 * Provide expected ramp-up count for K7. All other
2846 * are set to zero, indicating minimum divisors for
2847 * every field.
2848 *
2849 * This prevents guest kernels on AMD host with CPU
2850 * type 6, model 8 and higher from exploding due to
2851 * the rdmsr failing.
2852 */
609e36d3 2853 msr_info->data = 0x20000000;
84e0cefa 2854 break;
55cd8e5a 2855 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2856 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2857 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2858 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2859 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2860 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2861 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2862 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2863 msr_info->index, &msr_info->data,
2864 msr_info->host_initiated);
55cd8e5a 2865 break;
91c9c3ed 2866 case MSR_IA32_BBL_CR_CTL3:
2867 /* This legacy MSR exists but isn't fully documented in current
2868 * silicon. It is however accessed by winxp in very narrow
2869 * scenarios where it sets bit #19, itself documented as
2870 * a "reserved" bit. Best effort attempt to source coherent
2871 * read data here should the balance of the register be
2872 * interpreted by the guest:
2873 *
2874 * L2 cache control register 3: 64GB range, 256KB size,
2875 * enabled, latency 0x1, configured
2876 */
609e36d3 2877 msr_info->data = 0xbe702111;
91c9c3ed 2878 break;
2b036c6b 2879 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2880 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2881 return 1;
609e36d3 2882 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2883 break;
2884 case MSR_AMD64_OSVW_STATUS:
d6321d49 2885 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2886 return 1;
609e36d3 2887 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2888 break;
db2336a8 2889 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2890 if (!msr_info->host_initiated &&
2891 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2892 return 1;
db2336a8
KH		 2893 msr_info->data = vcpu->arch.msr_platform_info;
2894 break;
2895 case MSR_MISC_FEATURES_ENABLES:
2896 msr_info->data = vcpu->arch.msr_misc_features_enables;
2897 break;
15c4a640 2898 default:
c6702c9d 2899 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2900 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2901 if (!ignore_msrs) {
ae0f5499
BD		 2902 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2903 msr_info->index);
ed85c068
AP		 2904 return 1;
2905 } else {
fab0aa3b
EM		 2906 if (report_ignored_msrs)
2907 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2908 msr_info->index);
609e36d3 2909 msr_info->data = 0;
ed85c068
AP		 2910 }
2911 break;
15c4a640 2912 }
15c4a640
CO		 2913 return 0;
2914}
2915EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2916
313a3dc7
CO		 2917/*
2918 * Read or write a bunch of msrs. All parameters are kernel addresses.
2919 *
2920 * @return number of msrs set successfully.
2921 */
2922static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2923 struct kvm_msr_entry *entries,
2924 int (*do_msr)(struct kvm_vcpu *vcpu,
2925 unsigned index, u64 *data))
2926{
801e459a 2927 int i;
313a3dc7 2928
313a3dc7
CO		 2929 for (i = 0; i < msrs->nmsrs; ++i)
2930 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2931 break;
2932
313a3dc7
CO		 2933 return i;
2934}
2935
2936/*
2937 * Read or write a bunch of msrs. Parameters are user addresses.
2938 *
2939 * @return number of msrs set successfully.
2940 */
2941static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2942 int (*do_msr)(struct kvm_vcpu *vcpu,
2943 unsigned index, u64 *data),
2944 int writeback)
2945{
2946 struct kvm_msrs msrs;
2947 struct kvm_msr_entry *entries;
2948 int r, n;
2949 unsigned size;
2950
2951 r = -EFAULT;
0e96f31e 2952 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 2953 goto out;
2954
2955 r = -E2BIG;
2956 if (msrs.nmsrs >= MAX_IO_MSRS)
2957 goto out;
2958
313a3dc7 2959 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2960 entries = memdup_user(user_msrs->entries, size);
2961 if (IS_ERR(entries)) {
2962 r = PTR_ERR(entries);
313a3dc7 2963 goto out;
ff5c2c03 2964 }
313a3dc7
CO		 2965
2966 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2967 if (r < 0)
2968 goto out_free;
2969
2970 r = -EFAULT;
2971 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2972 goto out_free;
2973
2974 r = n;
2975
2976out_free:
7a73c028 2977 kfree(entries);
313a3dc7
CO		 2978out:
2979 return r;
2980}
2981
4d5422ce
WL		 2982static inline bool kvm_can_mwait_in_guest(void)
2983{
2984 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2985 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2986 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2987}
2988
784aa3d7 2989int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2990{
4d5422ce 2991 int r = 0;
018d00d2
ZX		 2992
2993 switch (ext) {
2994 case KVM_CAP_IRQCHIP:
2995 case KVM_CAP_HLT:
2996 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2997 case KVM_CAP_SET_TSS_ADDR:
07716717 2998 case KVM_CAP_EXT_CPUID:
9c15bb1d 2999 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3000 case KVM_CAP_CLOCKSOURCE:
7837699f 3001 case KVM_CAP_PIT:
a28e4f5a 3002 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3003 case KVM_CAP_MP_STATE:
ed848624 3004 case KVM_CAP_SYNC_MMU:
a355c85c 3005 case KVM_CAP_USER_NMI:
52d939a0 3006 case KVM_CAP_REINJECT_CONTROL:
4925663a 3007 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3008 case KVM_CAP_IOEVENTFD:
f848a5a8 3009 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3010 case KVM_CAP_PIT2:
e9f42757 3011 case KVM_CAP_PIT_STATE2:
b927a3ce 3012 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3013 case KVM_CAP_XEN_HVM:
3cfc3092 3014 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3015 case KVM_CAP_HYPERV:
10388a07 3016 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3017 case KVM_CAP_HYPERV_SPIN:
5c919412 3018 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3019 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3020 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3021 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3022 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3023 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 3024 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
2bc39970 3025 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3026 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3027 case KVM_CAP_DEBUGREGS:
d2be1651 3028 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3029 case KVM_CAP_XSAVE:
344d9588 3030 case KVM_CAP_ASYNC_PF:
92a1f12d 3031 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3032 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3033 case KVM_CAP_READONLY_MEM:
5f66b620 3034 case KVM_CAP_HYPERV_TIME:
100943c5 3035 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3036 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3037 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3038 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3039 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3040 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 3041 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3042 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3043 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3044 r = 1;
3045 break;
01643c51
KH		 3046 case KVM_CAP_SYNC_REGS:
3047 r = KVM_SYNC_X86_VALID_FIELDS;
3048 break;
e3fd9a93
PB		 3049 case KVM_CAP_ADJUST_CLOCK:
3050 r = KVM_CLOCK_TSC_STABLE;
3051 break;
4d5422ce 3052 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 3053 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 3054 if(kvm_can_mwait_in_guest())
3055 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3056 break;
6d396b55
PB		 3057 case KVM_CAP_X86_SMM:
3058 /* SMBASE is usually relocated above 1M on modern chipsets,
3059 * and SMM handlers might indeed rely on 4G segment limits,
3060 * so do not report SMM to be available if real mode is
3061 * emulated via vm86 mode. Still, do not go to great lengths
3062 * to avoid userspace's usage of the feature, because it is a
3063 * fringe case that is not enabled except via specific settings
3064 * of the module parameters.
3065 */
bc226f07 3066 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3067 break;
774ead3a
AK		 3068 case KVM_CAP_VAPIC:
3069 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3070 break;
f725230a 3071 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3072 r = KVM_SOFT_MAX_VCPUS;
3073 break;
3074 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3075 r = KVM_MAX_VCPUS;
3076 break;
a988b910 3077 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 3078 r = KVM_USER_MEM_SLOTS;
a988b910 3079 break;
a68a6a72
MT		 3080 case KVM_CAP_PV_MMU: /* obsolete */
3081 r = 0;
2f333bcb 3082 break;
890ca9ae
HY		 3083 case KVM_CAP_MCE:
3084 r = KVM_MAX_MCE_BANKS;
3085 break;
2d5b5a66 3086 case KVM_CAP_XCRS:
d366bf7e 3087 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3088 break;
92a1f12d
JR		 3089 case KVM_CAP_TSC_CONTROL:
3090 r = kvm_has_tsc_control;
3091 break;
37131313
RK		 3092 case KVM_CAP_X2APIC_API:
3093 r = KVM_X2APIC_API_VALID_FLAGS;
3094 break;
8fcc4b59
JM		 3095 case KVM_CAP_NESTED_STATE:
3096 r = kvm_x86_ops->get_nested_state ?
be43c440 3097 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3098 break;
018d00d2 3099 default:
018d00d2
ZX		 3100 break;
3101 }
3102 return r;
3103
3104}
3105
043405e1
CO		 3106long kvm_arch_dev_ioctl(struct file *filp,
3107 unsigned int ioctl, unsigned long arg)
3108{
3109 void __user *argp = (void __user *)arg;
3110 long r;
3111
3112 switch (ioctl) {
3113 case KVM_GET_MSR_INDEX_LIST: {
3114 struct kvm_msr_list __user *user_msr_list = argp;
3115 struct kvm_msr_list msr_list;
3116 unsigned n;
3117
3118 r = -EFAULT;
0e96f31e 3119 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3120 goto out;
3121 n = msr_list.nmsrs;
62ef68bb 3122 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3123 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3124 goto out;
3125 r = -E2BIG;
e125e7b6 3126 if (n < msr_list.nmsrs)
043405e1
CO		 3127 goto out;
3128 r = -EFAULT;
3129 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3130 num_msrs_to_save * sizeof(u32)))
3131 goto out;
e125e7b6 3132 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3133 &emulated_msrs,
62ef68bb 3134 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3135 goto out;
3136 r = 0;
3137 break;
3138 }
9c15bb1d
BP		 3139 case KVM_GET_SUPPORTED_CPUID:
3140 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3141 struct kvm_cpuid2 __user *cpuid_arg = argp;
3142 struct kvm_cpuid2 cpuid;
3143
3144 r = -EFAULT;
0e96f31e 3145 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3146 goto out;
9c15bb1d
BP		 3147
3148 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3149 ioctl);
674eea0f
AK		 3150 if (r)
3151 goto out;
3152
3153 r = -EFAULT;
0e96f31e 3154 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3155 goto out;
3156 r = 0;
3157 break;
3158 }
890ca9ae 3159 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3160 r = -EFAULT;
c45dcc71
AR		 3161 if (copy_to_user(argp, &kvm_mce_cap_supported,
3162 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3163 goto out;
3164 r = 0;
3165 break;
801e459a
TL		 3166 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3167 struct kvm_msr_list __user *user_msr_list = argp;
3168 struct kvm_msr_list msr_list;
3169 unsigned int n;
3170
3171 r = -EFAULT;
3172 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3173 goto out;
3174 n = msr_list.nmsrs;
3175 msr_list.nmsrs = num_msr_based_features;
3176 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3177 goto out;
3178 r = -E2BIG;
3179 if (n < msr_list.nmsrs)
3180 goto out;
3181 r = -EFAULT;
3182 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3183 num_msr_based_features * sizeof(u32)))
3184 goto out;
3185 r = 0;
3186 break;
3187 }
3188 case KVM_GET_MSRS:
3189 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3190 break;
890ca9ae 3191 }
043405e1
CO		 3192 default:
3193 r = -EINVAL;
3194 }
3195out:
3196 return r;
3197}
3198
f5f48ee1
SY		 3199static void wbinvd_ipi(void *garbage)
3200{
3201 wbinvd();
3202}
3203
3204static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3205{
e0f0bbc5 3206 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3207}
3208
313a3dc7
CO		 3209void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3210{
f5f48ee1
SY		 3211 /* Address WBINVD may be executed by guest */
3212 if (need_emulate_wbinvd(vcpu)) {
3213 if (kvm_x86_ops->has_wbinvd_exit())
3214 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3215 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3216 smp_call_function_single(vcpu->cpu,
3217 wbinvd_ipi, NULL, 1);
3218 }
3219
313a3dc7 3220 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3221
0dd6a6ed
ZA		 3222 /* Apply any externally detected TSC adjustments (due to suspend) */
3223 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3224 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3225 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3226 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3227 }
8f6055cb 3228
b0c39dc6 3229 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3230 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3231 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3232 if (tsc_delta < 0)
3233 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3234
b0c39dc6 3235 if (kvm_check_tsc_unstable()) {
07c1419a 3236 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3237 vcpu->arch.last_guest_tsc);
a545ab6a 3238 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3239 vcpu->arch.tsc_catchup = 1;
c285545f 3240 }
a749e247
PB		 3241
3242 if (kvm_lapic_hv_timer_in_use(vcpu))
3243 kvm_lapic_restart_hv_timer(vcpu);
3244
d98d07ca
MT		 3245 /*
3246 * On a host with synchronized TSC, there is no need to update
3247 * kvmclock on vcpu->cpu migration
3248 */
3249 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3250 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3251 if (vcpu->cpu != cpu)
1bd2009e 3252 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3253 vcpu->cpu = cpu;
6b7d7e76 3254 }
c9aaa895 3255
c9aaa895 3256 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3257}
3258
0b9f6c46
PX		 3259static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3260{
3261 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3262 return;
3263
fa55eedd 3264 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3265
4e335d9e 3266 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3267 &vcpu->arch.st.steal.preempted,
3268 offsetof(struct kvm_steal_time, preempted),
3269 sizeof(vcpu->arch.st.steal.preempted));
3270}
3271
313a3dc7
CO		 3272void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3273{
cc0d907c 3274 int idx;
de63ad4c
LM		 3275
3276 if (vcpu->preempted)
3277 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3278
931f261b
AA		 3279 /*
3280 * Disable page faults because we're in atomic context here.
3281 * kvm_write_guest_offset_cached() would call might_fault()
3282 * that relies on pagefault_disable() to tell if there's a
3283 * bug. NOTE: the write to guest memory may not go through if
3284 * during postcopy live migration or if there's heavy guest
3285 * paging.
3286 */
3287 pagefault_disable();
cc0d907c
AA		 3288 /*
3289 * kvm_memslots() will be called by
3290 * kvm_write_guest_offset_cached() so take the srcu lock.
3291 */
3292 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3293 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3294 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3295 pagefault_enable();
02daab21 3296 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3297 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3298 /*
f9dcf08e
RK		 3299 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3300 * on every vmexit, but if not, we might have a stale dr6 from the
3301 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3302 */
f9dcf08e 3303 set_debugreg(0, 6);
313a3dc7
CO		 3304}
3305
313a3dc7
CO		 3306static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3307 struct kvm_lapic_state *s)
3308{
fa59cc00 3309 if (vcpu->arch.apicv_active)
d62caabb
AS		 3310 kvm_x86_ops->sync_pir_to_irr(vcpu);
3311
a92e2543 3312 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3313}
3314
3315static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3316 struct kvm_lapic_state *s)
3317{
a92e2543
RK		 3318 int r;
3319
3320 r = kvm_apic_set_state(vcpu, s);
3321 if (r)
3322 return r;
cb142eb7 3323 update_cr8_intercept(vcpu);
313a3dc7
CO		 3324
3325 return 0;
3326}
3327
127a457a
MG		 3328static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3329{
3330 return (!lapic_in_kernel(vcpu) ||
3331 kvm_apic_accept_pic_intr(vcpu));
3332}
3333
782d422b
MG		 3334/*
3335 * if userspace requested an interrupt window, check that the
3336 * interrupt window is open.
3337 *
3338 * No need to exit to userspace if we already have an interrupt queued.
3339 */
3340static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3341{
3342 return kvm_arch_interrupt_allowed(vcpu) &&
3343 !kvm_cpu_has_interrupt(vcpu) &&
3344 !kvm_event_needs_reinjection(vcpu) &&
3345 kvm_cpu_accept_dm_intr(vcpu);
3346}
3347
f77bc6a4
ZX		 3348static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3349 struct kvm_interrupt *irq)
3350{
02cdb50f 3351 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3352 return -EINVAL;
1c1a9ce9
SR		 3353
3354 if (!irqchip_in_kernel(vcpu->kvm)) {
3355 kvm_queue_interrupt(vcpu, irq->irq, false);
3356 kvm_make_request(KVM_REQ_EVENT, vcpu);
3357 return 0;
3358 }
3359
3360 /*
3361 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3362 * fail for in-kernel 8259.
3363 */
3364 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3365 return -ENXIO;
f77bc6a4 3366
1c1a9ce9
SR		 3367 if (vcpu->arch.pending_external_vector != -1)
3368 return -EEXIST;
f77bc6a4 3369
1c1a9ce9 3370 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3371 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3372 return 0;
3373}
3374
c4abb7c9
JK		 3375static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3376{
c4abb7c9 3377 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3378
3379 return 0;
3380}
3381
f077825a
PB		 3382static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3383{
64d60670
PB		 3384 kvm_make_request(KVM_REQ_SMI, vcpu);
3385
f077825a
PB		 3386 return 0;
3387}
3388
b209749f
AK		 3389static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3390 struct kvm_tpr_access_ctl *tac)
3391{
3392 if (tac->flags)
3393 return -EINVAL;
3394 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3395 return 0;
3396}
3397
890ca9ae
HY		 3398static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3399 u64 mcg_cap)
3400{
3401 int r;
3402 unsigned bank_num = mcg_cap & 0xff, bank;
3403
3404 r = -EINVAL;
a9e38c3e 3405 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3406 goto out;
c45dcc71 3407 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3408 goto out;
3409 r = 0;
3410 vcpu->arch.mcg_cap = mcg_cap;
3411 /* Init IA32_MCG_CTL to all 1s */
3412 if (mcg_cap & MCG_CTL_P)
3413 vcpu->arch.mcg_ctl = ~(u64)0;
3414 /* Init IA32_MCi_CTL to all 1s */
3415 for (bank = 0; bank < bank_num; bank++)
3416 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3417
3418 if (kvm_x86_ops->setup_mce)
3419 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3420out:
3421 return r;
3422}
3423
3424static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3425 struct kvm_x86_mce *mce)
3426{
3427 u64 mcg_cap = vcpu->arch.mcg_cap;
3428 unsigned bank_num = mcg_cap & 0xff;
3429 u64 *banks = vcpu->arch.mce_banks;
3430
3431 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3432 return -EINVAL;
3433 /*
3434 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3435 * reporting is disabled
3436 */
3437 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3438 vcpu->arch.mcg_ctl != ~(u64)0)
3439 return 0;
3440 banks += 4 * mce->bank;
3441 /*
3442 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3443 * reporting is disabled for the bank
3444 */
3445 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3446 return 0;
3447 if (mce->status & MCI_STATUS_UC) {
3448 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3449 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3450 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3451 return 0;
3452 }
3453 if (banks[1] & MCI_STATUS_VAL)
3454 mce->status |= MCI_STATUS_OVER;
3455 banks[2] = mce->addr;
3456 banks[3] = mce->misc;
3457 vcpu->arch.mcg_status = mce->mcg_status;
3458 banks[1] = mce->status;
3459 kvm_queue_exception(vcpu, MC_VECTOR);
3460 } else if (!(banks[1] & MCI_STATUS_VAL)
3461 || !(banks[1] & MCI_STATUS_UC)) {
3462 if (banks[1] & MCI_STATUS_VAL)
3463 mce->status |= MCI_STATUS_OVER;
3464 banks[2] = mce->addr;
3465 banks[3] = mce->misc;
3466 banks[1] = mce->status;
3467 } else
3468 banks[1] |= MCI_STATUS_OVER;
3469 return 0;
3470}
3471
3cfc3092
JK		 3472static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3473 struct kvm_vcpu_events *events)
3474{
7460fb4a 3475 process_nmi(vcpu);
59073aaf 3476
664f8e26 3477 /*
59073aaf
JM		 3478 * The API doesn't provide the instruction length for software
3479 * exceptions, so don't report them. As long as the guest RIP
3480 * isn't advanced, we should expect to encounter the exception
3481 * again.
664f8e26 3482 */
59073aaf
JM		 3483 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3484 events->exception.injected = 0;
3485 events->exception.pending = 0;
3486 } else {
3487 events->exception.injected = vcpu->arch.exception.injected;
3488 events->exception.pending = vcpu->arch.exception.pending;
3489 /*
3490 * For ABI compatibility, deliberately conflate
3491 * pending and injected exceptions when
3492 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3493 */
3494 if (!vcpu->kvm->arch.exception_payload_enabled)
3495 events->exception.injected |=
3496 vcpu->arch.exception.pending;
3497 }
3cfc3092
JK		 3498 events->exception.nr = vcpu->arch.exception.nr;
3499 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3500 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3501 events->exception_has_payload = vcpu->arch.exception.has_payload;
3502 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3503
03b82a30 3504 events->interrupt.injected =
04140b41 3505 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3506 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3507 events->interrupt.soft = 0;
37ccdcbe 3508 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3509
3510 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3511 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3512 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3513 events->nmi.pad = 0;
3cfc3092 3514
66450a21 3515 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3516
f077825a
PB		 3517 events->smi.smm = is_smm(vcpu);
3518 events->smi.pending = vcpu->arch.smi_pending;
3519 events->smi.smm_inside_nmi =
3520 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3521 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3522
dab4b911 3523 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3524 | KVM_VCPUEVENT_VALID_SHADOW
3525 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3526 if (vcpu->kvm->arch.exception_payload_enabled)
3527 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3528
97e69aa6 3529 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3530}
3531
c5833c7a 3532static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3533
3cfc3092
JK		 3534static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3535 struct kvm_vcpu_events *events)
3536{
dab4b911 3537 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3538 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3539 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3540 | KVM_VCPUEVENT_VALID_SMM
3541 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3542 return -EINVAL;
3543
59073aaf
JM		 3544 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3545 if (!vcpu->kvm->arch.exception_payload_enabled)
3546 return -EINVAL;
3547 if (events->exception.pending)
3548 events->exception.injected = 0;
3549 else
3550 events->exception_has_payload = 0;
3551 } else {
3552 events->exception.pending = 0;
3553 events->exception_has_payload = 0;
3554 }
3555
3556 if ((events->exception.injected || events->exception.pending) &&
3557 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3558 return -EINVAL;
3559
28bf2888
DH		 3560 /* INITs are latched while in SMM */
3561 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3562 (events->smi.smm || events->smi.pending) &&
3563 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3564 return -EINVAL;
3565
7460fb4a 3566 process_nmi(vcpu);
59073aaf
JM		 3567 vcpu->arch.exception.injected = events->exception.injected;
3568 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3569 vcpu->arch.exception.nr = events->exception.nr;
3570 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3571 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3572 vcpu->arch.exception.has_payload = events->exception_has_payload;
3573 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3574
04140b41 3575 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3576 vcpu->arch.interrupt.nr = events->interrupt.nr;
3577 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3578 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3579 kvm_x86_ops->set_interrupt_shadow(vcpu,
3580 events->interrupt.shadow);
3cfc3092
JK		 3581
3582 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3583 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3584 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3585 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3586
66450a21 3587 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3588 lapic_in_kernel(vcpu))
66450a21 3589 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3590
f077825a 3591 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3592 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3593 if (events->smi.smm)
3594 vcpu->arch.hflags |= HF_SMM_MASK;
3595 else
3596 vcpu->arch.hflags &= ~HF_SMM_MASK;
3597 kvm_smm_changed(vcpu);
3598 }
6ef4e07e 3599
f077825a 3600 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3601
3602 if (events->smi.smm) {
3603 if (events->smi.smm_inside_nmi)
3604 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3605 else
f4ef1910
WL		 3606 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3607 if (lapic_in_kernel(vcpu)) {
3608 if (events->smi.latched_init)
3609 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3610 else
3611 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3612 }
f077825a
PB		 3613 }
3614 }
3615
3842d135
AK		 3616 kvm_make_request(KVM_REQ_EVENT, vcpu);
3617
3cfc3092
JK		 3618 return 0;
3619}
3620
a1efbe77
JK		 3621static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3622 struct kvm_debugregs *dbgregs)
3623{
73aaf249
JK		 3624 unsigned long val;
3625
a1efbe77 3626 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3627 kvm_get_dr(vcpu, 6, &val);
73aaf249 3628 dbgregs->dr6 = val;
a1efbe77
JK		 3629 dbgregs->dr7 = vcpu->arch.dr7;
3630 dbgregs->flags = 0;
97e69aa6 3631 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3632}
3633
3634static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3635 struct kvm_debugregs *dbgregs)
3636{
3637 if (dbgregs->flags)
3638 return -EINVAL;
3639
d14bdb55
PB		 3640 if (dbgregs->dr6 & ~0xffffffffull)
3641 return -EINVAL;
3642 if (dbgregs->dr7 & ~0xffffffffull)
3643 return -EINVAL;
3644
a1efbe77 3645 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3646 kvm_update_dr0123(vcpu);
a1efbe77 3647 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3648 kvm_update_dr6(vcpu);
a1efbe77 3649 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3650 kvm_update_dr7(vcpu);
a1efbe77 3651
a1efbe77
JK		 3652 return 0;
3653}
3654
df1daba7
PB		 3655#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3656
3657static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3658{
b666a4b6 3659 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3660 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3661 u64 valid;
3662
3663 /*
3664 * Copy legacy XSAVE area, to avoid complications with CPUID
3665 * leaves 0 and 1 in the loop below.
3666 */
3667 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3668
3669 /* Set XSTATE_BV */
00c87e9a 3670 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3671 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3672
3673 /*
3674 * Copy each region from the possibly compacted offset to the
3675 * non-compacted offset.
3676 */
d91cab78 3677 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3678 while (valid) {
3679 u64 feature = valid & -valid;
3680 int index = fls64(feature) - 1;
3681 void *src = get_xsave_addr(xsave, feature);
3682
3683 if (src) {
3684 u32 size, offset, ecx, edx;
3685 cpuid_count(XSTATE_CPUID, index,
3686 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3687 if (feature == XFEATURE_MASK_PKRU)
3688 memcpy(dest + offset, &vcpu->arch.pkru,
3689 sizeof(vcpu->arch.pkru));
3690 else
3691 memcpy(dest + offset, src, size);
3692
df1daba7
PB		 3693 }
3694
3695 valid -= feature;
3696 }
3697}
3698
3699static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3700{
b666a4b6 3701 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3702 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3703 u64 valid;
3704
3705 /*
3706 * Copy legacy XSAVE area, to avoid complications with CPUID
3707 * leaves 0 and 1 in the loop below.
3708 */
3709 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3710
3711 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3712 xsave->header.xfeatures = xstate_bv;
782511b0 3713 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3714 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3715
3716 /*
3717 * Copy each region from the non-compacted offset to the
3718 * possibly compacted offset.
3719 */
d91cab78 3720 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3721 while (valid) {
3722 u64 feature = valid & -valid;
3723 int index = fls64(feature) - 1;
3724 void *dest = get_xsave_addr(xsave, feature);
3725
3726 if (dest) {
3727 u32 size, offset, ecx, edx;
3728 cpuid_count(XSTATE_CPUID, index,
3729 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3730 if (feature == XFEATURE_MASK_PKRU)
3731 memcpy(&vcpu->arch.pkru, src + offset,
3732 sizeof(vcpu->arch.pkru));
3733 else
3734 memcpy(dest, src + offset, size);
ee4100da 3735 }
df1daba7
PB		 3736
3737 valid -= feature;
3738 }
3739}
3740
2d5b5a66
SY		 3741static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3742 struct kvm_xsave *guest_xsave)
3743{
d366bf7e 3744 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3745 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3746 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3747 } else {
2d5b5a66 3748 memcpy(guest_xsave->region,
b666a4b6 3749 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3750 sizeof(struct fxregs_state));
2d5b5a66 3751 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3752 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3753 }
3754}
3755
a575813b
WL		 3756#define XSAVE_MXCSR_OFFSET 24
3757
2d5b5a66
SY		 3758static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3759 struct kvm_xsave *guest_xsave)
3760{
3761 u64 xstate_bv =
3762 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3763 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3764
d366bf7e 3765 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3766 /*
3767 * Here we allow setting states that are not present in
3768 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3769 * with old userspace.
3770 */
a575813b
WL		 3771 if (xstate_bv & ~kvm_supported_xcr0() ||
3772 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3773 return -EINVAL;
df1daba7 3774 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3775 } else {
a575813b
WL		 3776 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3777 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3778 return -EINVAL;
b666a4b6 3779 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3780 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3781 }
3782 return 0;
3783}
3784
3785static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3786 struct kvm_xcrs *guest_xcrs)
3787{
d366bf7e 3788 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3789 guest_xcrs->nr_xcrs = 0;
3790 return;
3791 }
3792
3793 guest_xcrs->nr_xcrs = 1;
3794 guest_xcrs->flags = 0;
3795 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3796 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3797}
3798
3799static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3800 struct kvm_xcrs *guest_xcrs)
3801{
3802 int i, r = 0;
3803
d366bf7e 3804 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3805 return -EINVAL;
3806
3807 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3808 return -EINVAL;
3809
3810 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3811 /* Only support XCR0 currently */
c67a04cb 3812 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3813 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3814 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3815 break;
3816 }
3817 if (r)
3818 r = -EINVAL;
3819 return r;
3820}
3821
1c0b28c2
EM		 3822/*
3823 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3824 * stopped by the hypervisor. This function will be called from the host only.
3825 * EINVAL is returned when the host attempts to set the flag for a guest that
3826 * does not support pv clocks.
3827 */
3828static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3829{
0b79459b 3830 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3831 return -EINVAL;
51d59c6b 3832 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3833 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3834 return 0;
3835}
3836
5c919412
AS		 3837static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3838 struct kvm_enable_cap *cap)
3839{
57b119da
VK		 3840 int r;
3841 uint16_t vmcs_version;
3842 void __user *user_ptr;
3843
5c919412
AS		 3844 if (cap->flags)
3845 return -EINVAL;
3846
3847 switch (cap->cap) {
efc479e6
RK		 3848 case KVM_CAP_HYPERV_SYNIC2:
3849 if (cap->args[0])
3850 return -EINVAL;
b2869f28
GS		 3851 /* fall through */
3852
5c919412 3853 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3854 if (!irqchip_in_kernel(vcpu->kvm))
3855 return -EINVAL;
efc479e6
RK		 3856 return kvm_hv_activate_synic(vcpu, cap->cap ==
3857 KVM_CAP_HYPERV_SYNIC2);
57b119da 3858 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 3859 if (!kvm_x86_ops->nested_enable_evmcs)
3860 return -ENOTTY;
57b119da
VK		 3861 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3862 if (!r) {
3863 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3864 if (copy_to_user(user_ptr, &vmcs_version,
3865 sizeof(vmcs_version)))
3866 r = -EFAULT;
3867 }
3868 return r;
3869
5c919412
AS		 3870 default:
3871 return -EINVAL;
3872 }
3873}
3874
313a3dc7
CO		 3875long kvm_arch_vcpu_ioctl(struct file *filp,
3876 unsigned int ioctl, unsigned long arg)
3877{
3878 struct kvm_vcpu *vcpu = filp->private_data;
3879 void __user *argp = (void __user *)arg;
3880 int r;
d1ac91d8
AK		 3881 union {
3882 struct kvm_lapic_state *lapic;
3883 struct kvm_xsave *xsave;
3884 struct kvm_xcrs *xcrs;
3885 void *buffer;
3886 } u;
3887
9b062471
CD		 3888 vcpu_load(vcpu);
3889
d1ac91d8 3890 u.buffer = NULL;
313a3dc7
CO		 3891 switch (ioctl) {
3892 case KVM_GET_LAPIC: {
2204ae3c 3893 r = -EINVAL;
bce87cce 3894 if (!lapic_in_kernel(vcpu))
2204ae3c 3895 goto out;
254272ce
BG		 3896 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3897 GFP_KERNEL_ACCOUNT);
313a3dc7 3898
b772ff36 3899 r = -ENOMEM;
d1ac91d8 3900 if (!u.lapic)
b772ff36 3901 goto out;
d1ac91d8 3902 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3903 if (r)
3904 goto out;
3905 r = -EFAULT;
d1ac91d8 3906 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3907 goto out;
3908 r = 0;
3909 break;
3910 }
3911 case KVM_SET_LAPIC: {
2204ae3c 3912 r = -EINVAL;
bce87cce 3913 if (!lapic_in_kernel(vcpu))
2204ae3c 3914 goto out;
ff5c2c03 3915 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3916 if (IS_ERR(u.lapic)) {
3917 r = PTR_ERR(u.lapic);
3918 goto out_nofree;
3919 }
ff5c2c03 3920
d1ac91d8 3921 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3922 break;
3923 }
f77bc6a4
ZX		 3924 case KVM_INTERRUPT: {
3925 struct kvm_interrupt irq;
3926
3927 r = -EFAULT;
0e96f31e 3928 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 3929 goto out;
3930 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3931 break;
3932 }
c4abb7c9
JK		 3933 case KVM_NMI: {
3934 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3935 break;
3936 }
f077825a
PB		 3937 case KVM_SMI: {
3938 r = kvm_vcpu_ioctl_smi(vcpu);
3939 break;
3940 }
313a3dc7
CO		 3941 case KVM_SET_CPUID: {
3942 struct kvm_cpuid __user *cpuid_arg = argp;
3943 struct kvm_cpuid cpuid;
3944
3945 r = -EFAULT;
0e96f31e 3946 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 3947 goto out;
3948 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3949 break;
3950 }
07716717
DK		 3951 case KVM_SET_CPUID2: {
3952 struct kvm_cpuid2 __user *cpuid_arg = argp;
3953 struct kvm_cpuid2 cpuid;
3954
3955 r = -EFAULT;
0e96f31e 3956 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 3957 goto out;
3958 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3959 cpuid_arg->entries);
07716717
DK		 3960 break;
3961 }
3962 case KVM_GET_CPUID2: {
3963 struct kvm_cpuid2 __user *cpuid_arg = argp;
3964 struct kvm_cpuid2 cpuid;
3965
3966 r = -EFAULT;
0e96f31e 3967 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 3968 goto out;
3969 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3970 cpuid_arg->entries);
07716717
DK		 3971 if (r)
3972 goto out;
3973 r = -EFAULT;
0e96f31e 3974 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 3975 goto out;
3976 r = 0;
3977 break;
3978 }
801e459a
TL		 3979 case KVM_GET_MSRS: {
3980 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3981 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3982 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3983 break;
801e459a
TL		 3984 }
3985 case KVM_SET_MSRS: {
3986 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3987 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3988 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3989 break;
801e459a 3990 }
b209749f
AK		 3991 case KVM_TPR_ACCESS_REPORTING: {
3992 struct kvm_tpr_access_ctl tac;
3993
3994 r = -EFAULT;
0e96f31e 3995 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 3996 goto out;
3997 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3998 if (r)
3999 goto out;
4000 r = -EFAULT;
0e96f31e 4001 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4002 goto out;
4003 r = 0;
4004 break;
4005 };
b93463aa
AK		 4006 case KVM_SET_VAPIC_ADDR: {
4007 struct kvm_vapic_addr va;
7301d6ab 4008 int idx;
b93463aa
AK		 4009
4010 r = -EINVAL;
35754c98 4011 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4012 goto out;
4013 r = -EFAULT;
0e96f31e 4014 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4015 goto out;
7301d6ab 4016 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4017 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4018 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4019 break;
4020 }
890ca9ae
HY		 4021 case KVM_X86_SETUP_MCE: {
4022 u64 mcg_cap;
4023
4024 r = -EFAULT;
0e96f31e 4025 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4026 goto out;
4027 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4028 break;
4029 }
4030 case KVM_X86_SET_MCE: {
4031 struct kvm_x86_mce mce;
4032
4033 r = -EFAULT;
0e96f31e 4034 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4035 goto out;
4036 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4037 break;
4038 }
3cfc3092
JK		 4039 case KVM_GET_VCPU_EVENTS: {
4040 struct kvm_vcpu_events events;
4041
4042 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4043
4044 r = -EFAULT;
4045 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4046 break;
4047 r = 0;
4048 break;
4049 }
4050 case KVM_SET_VCPU_EVENTS: {
4051 struct kvm_vcpu_events events;
4052
4053 r = -EFAULT;
4054 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4055 break;
4056
4057 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4058 break;
4059 }
a1efbe77
JK		 4060 case KVM_GET_DEBUGREGS: {
4061 struct kvm_debugregs dbgregs;
4062
4063 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4064
4065 r = -EFAULT;
4066 if (copy_to_user(argp, &dbgregs,
4067 sizeof(struct kvm_debugregs)))
4068 break;
4069 r = 0;
4070 break;
4071 }
4072 case KVM_SET_DEBUGREGS: {
4073 struct kvm_debugregs dbgregs;
4074
4075 r = -EFAULT;
4076 if (copy_from_user(&dbgregs, argp,
4077 sizeof(struct kvm_debugregs)))
4078 break;
4079
4080 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4081 break;
4082 }
2d5b5a66 4083 case KVM_GET_XSAVE: {
254272ce 4084 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4085 r = -ENOMEM;
d1ac91d8 4086 if (!u.xsave)
2d5b5a66
SY		 4087 break;
4088
d1ac91d8 4089 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4090
4091 r = -EFAULT;
d1ac91d8 4092 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4093 break;
4094 r = 0;
4095 break;
4096 }
4097 case KVM_SET_XSAVE: {
ff5c2c03 4098 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4099 if (IS_ERR(u.xsave)) {
4100 r = PTR_ERR(u.xsave);
4101 goto out_nofree;
4102 }
2d5b5a66 4103
d1ac91d8 4104 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4105 break;
4106 }
4107 case KVM_GET_XCRS: {
254272ce 4108 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4109 r = -ENOMEM;
d1ac91d8 4110 if (!u.xcrs)
2d5b5a66
SY		 4111 break;
4112
d1ac91d8 4113 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4114
4115 r = -EFAULT;
d1ac91d8 4116 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4117 sizeof(struct kvm_xcrs)))
4118 break;
4119 r = 0;
4120 break;
4121 }
4122 case KVM_SET_XCRS: {
ff5c2c03 4123 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4124 if (IS_ERR(u.xcrs)) {
4125 r = PTR_ERR(u.xcrs);
4126 goto out_nofree;
4127 }
2d5b5a66 4128
d1ac91d8 4129 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4130 break;
4131 }
92a1f12d
JR		 4132 case KVM_SET_TSC_KHZ: {
4133 u32 user_tsc_khz;
4134
4135 r = -EINVAL;
92a1f12d
JR		 4136 user_tsc_khz = (u32)arg;
4137
4138 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4139 goto out;
4140
cc578287
ZA		 4141 if (user_tsc_khz == 0)
4142 user_tsc_khz = tsc_khz;
4143
381d585c
HZ		 4144 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4145 r = 0;
92a1f12d 4146
92a1f12d
JR		 4147 goto out;
4148 }
4149 case KVM_GET_TSC_KHZ: {
cc578287 4150 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4151 goto out;
4152 }
1c0b28c2
EM		 4153 case KVM_KVMCLOCK_CTRL: {
4154 r = kvm_set_guest_paused(vcpu);
4155 goto out;
4156 }
5c919412
AS		 4157 case KVM_ENABLE_CAP: {
4158 struct kvm_enable_cap cap;
4159
4160 r = -EFAULT;
4161 if (copy_from_user(&cap, argp, sizeof(cap)))
4162 goto out;
4163 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4164 break;
4165 }
8fcc4b59
JM		 4166 case KVM_GET_NESTED_STATE: {
4167 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4168 u32 user_data_size;
4169
4170 r = -EINVAL;
4171 if (!kvm_x86_ops->get_nested_state)
4172 break;
4173
4174 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4175 r = -EFAULT;
8fcc4b59 4176 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4177 break;
8fcc4b59
JM		 4178
4179 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4180 user_data_size);
4181 if (r < 0)
26b471c7 4182 break;
8fcc4b59
JM		 4183
4184 if (r > user_data_size) {
4185 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4186 r = -EFAULT;
4187 else
4188 r = -E2BIG;
4189 break;
8fcc4b59 4190 }
26b471c7 4191
8fcc4b59
JM		 4192 r = 0;
4193 break;
4194 }
4195 case KVM_SET_NESTED_STATE: {
4196 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4197 struct kvm_nested_state kvm_state;
4198
4199 r = -EINVAL;
4200 if (!kvm_x86_ops->set_nested_state)
4201 break;
4202
26b471c7 4203 r = -EFAULT;
8fcc4b59 4204 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4205 break;
8fcc4b59 4206
26b471c7 4207 r = -EINVAL;
8fcc4b59 4208 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4209 break;
8fcc4b59
JM		 4210
4211 if (kvm_state.flags &
8cab6507
VK		 4212 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4213 | KVM_STATE_NESTED_EVMCS))
26b471c7 4214 break;
8fcc4b59
JM		 4215
4216 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4217 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4218 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4219 break;
8fcc4b59
JM		 4220
4221 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4222 break;
4223 }
2bc39970
VK		 4224 case KVM_GET_SUPPORTED_HV_CPUID: {
4225 struct kvm_cpuid2 __user *cpuid_arg = argp;
4226 struct kvm_cpuid2 cpuid;
4227
4228 r = -EFAULT;
4229 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4230 goto out;
4231
4232 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4233 cpuid_arg->entries);
4234 if (r)
4235 goto out;
4236
4237 r = -EFAULT;
4238 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4239 goto out;
4240 r = 0;
4241 break;
4242 }
313a3dc7
CO		 4243 default:
4244 r = -EINVAL;
4245 }
4246out:
d1ac91d8 4247 kfree(u.buffer);
9b062471
CD		 4248out_nofree:
4249 vcpu_put(vcpu);
313a3dc7
CO		 4250 return r;
4251}
4252
1499fa80 4253vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4254{
4255 return VM_FAULT_SIGBUS;
4256}
4257
1fe779f8
CO		 4258static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4259{
4260 int ret;
4261
4262 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4263 return -EINVAL;
1fe779f8
CO		 4264 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4265 return ret;
4266}
4267
b927a3ce
SY		 4268static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4269 u64 ident_addr)
4270{
2ac52ab8 4271 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4272}
4273
1fe779f8 4274static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4275 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4276{
4277 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4278 return -EINVAL;
4279
79fac95e 4280 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4281
4282 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4283 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4284
79fac95e 4285 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4286 return 0;
4287}
4288
bc8a3d89 4289static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4290{
39de71ec 4291 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4292}
4293
1fe779f8
CO		 4294static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4295{
90bca052 4296 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4297 int r;
4298
4299 r = 0;
4300 switch (chip->chip_id) {
4301 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4302 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4303 sizeof(struct kvm_pic_state));
4304 break;
4305 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4306 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4307 sizeof(struct kvm_pic_state));
4308 break;
4309 case KVM_IRQCHIP_IOAPIC:
33392b49 4310 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4311 break;
4312 default:
4313 r = -EINVAL;
4314 break;
4315 }
4316 return r;
4317}
4318
4319static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4320{
90bca052 4321 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4322 int r;
4323
4324 r = 0;
4325 switch (chip->chip_id) {
4326 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4327 spin_lock(&pic->lock);
4328 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4329 sizeof(struct kvm_pic_state));
90bca052 4330 spin_unlock(&pic->lock);
1fe779f8
CO		 4331 break;
4332 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4333 spin_lock(&pic->lock);
4334 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4335 sizeof(struct kvm_pic_state));
90bca052 4336 spin_unlock(&pic->lock);
1fe779f8
CO		 4337 break;
4338 case KVM_IRQCHIP_IOAPIC:
33392b49 4339 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4340 break;
4341 default:
4342 r = -EINVAL;
4343 break;
4344 }
90bca052 4345 kvm_pic_update_irq(pic);
1fe779f8
CO		 4346 return r;
4347}
4348
e0f63cb9
SY		 4349static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4350{
34f3941c
RK		 4351 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4352
4353 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4354
4355 mutex_lock(&kps->lock);
4356 memcpy(ps, &kps->channels, sizeof(*ps));
4357 mutex_unlock(&kps->lock);
2da29bcc 4358 return 0;
e0f63cb9
SY		 4359}
4360
4361static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4362{
0185604c 4363 int i;
09edea72
RK		 4364 struct kvm_pit *pit = kvm->arch.vpit;
4365
4366 mutex_lock(&pit->pit_state.lock);
34f3941c 4367 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4368 for (i = 0; i < 3; i++)
09edea72
RK		 4369 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4370 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4371 return 0;
e9f42757
BK		 4372}
4373
4374static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4375{
e9f42757
BK		 4376 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4377 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4378 sizeof(ps->channels));
4379 ps->flags = kvm->arch.vpit->pit_state.flags;
4380 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4381 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4382 return 0;
e9f42757
BK		 4383}
4384
4385static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4386{
2da29bcc 4387 int start = 0;
0185604c 4388 int i;
e9f42757 4389 u32 prev_legacy, cur_legacy;
09edea72
RK		 4390 struct kvm_pit *pit = kvm->arch.vpit;
4391
4392 mutex_lock(&pit->pit_state.lock);
4393 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4394 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4395 if (!prev_legacy && cur_legacy)
4396 start = 1;
09edea72
RK		 4397 memcpy(&pit->pit_state.channels, &ps->channels,
4398 sizeof(pit->pit_state.channels));
4399 pit->pit_state.flags = ps->flags;
0185604c 4400 for (i = 0; i < 3; i++)
09edea72 4401 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4402 start && i == 0);
09edea72 4403 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4404 return 0;
e0f63cb9
SY		 4405}
4406
52d939a0
MT		 4407static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4408 struct kvm_reinject_control *control)
4409{
71474e2f
RK		 4410 struct kvm_pit *pit = kvm->arch.vpit;
4411
4412 if (!pit)
52d939a0 4413 return -ENXIO;
b39c90b6 4414
71474e2f
RK		 4415 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4416 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4417 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4418 */
4419 mutex_lock(&pit->pit_state.lock);
4420 kvm_pit_set_reinject(pit, control->pit_reinject);
4421 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4422
52d939a0
MT		 4423 return 0;
4424}
4425
95d4c16c 4426/**
60c34612
TY		 4427 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4428 * @kvm: kvm instance
4429 * @log: slot id and address to which we copy the log
95d4c16c 4430 *
e108ff2f
PB		 4431 * Steps 1-4 below provide general overview of dirty page logging. See
4432 * kvm_get_dirty_log_protect() function description for additional details.
4433 *
4434 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4435 * always flush the TLB (step 4) even if previous step failed and the dirty
4436 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4437 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4438 * writes will be marked dirty for next log read.
95d4c16c 4439 *
60c34612
TY		 4440 * 1. Take a snapshot of the bit and clear it if needed.
4441 * 2. Write protect the corresponding page.
e108ff2f
PB		 4442 * 3. Copy the snapshot to the userspace.
4443 * 4. Flush TLB's if needed.
5bb064dc 4444 */
60c34612 4445int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4446{
8fe65a82 4447 bool flush = false;
e108ff2f 4448 int r;
5bb064dc 4449
79fac95e 4450 mutex_lock(&kvm->slots_lock);
5bb064dc 4451
88178fd4
KH		 4452 /*
4453 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4454 */
4455 if (kvm_x86_ops->flush_log_dirty)
4456 kvm_x86_ops->flush_log_dirty(kvm);
4457
8fe65a82 4458 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4459
4460 /*
4461 * All the TLBs can be flushed out of mmu lock, see the comments in
4462 * kvm_mmu_slot_remove_write_access().
4463 */
e108ff2f 4464 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4465 if (flush)
2a31b9db
PB		 4466 kvm_flush_remote_tlbs(kvm);
4467
4468 mutex_unlock(&kvm->slots_lock);
4469 return r;
4470}
4471
4472int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4473{
4474 bool flush = false;
4475 int r;
4476
4477 mutex_lock(&kvm->slots_lock);
4478
4479 /*
4480 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4481 */
4482 if (kvm_x86_ops->flush_log_dirty)
4483 kvm_x86_ops->flush_log_dirty(kvm);
4484
4485 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4486
4487 /*
4488 * All the TLBs can be flushed out of mmu lock, see the comments in
4489 * kvm_mmu_slot_remove_write_access().
4490 */
4491 lockdep_assert_held(&kvm->slots_lock);
4492 if (flush)
198c74f4
XG		 4493 kvm_flush_remote_tlbs(kvm);
4494
79fac95e 4495 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4496 return r;
4497}
4498
aa2fbe6d
YZ		 4499int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4500 bool line_status)
23d43cf9
CD		 4501{
4502 if (!irqchip_in_kernel(kvm))
4503 return -ENXIO;
4504
4505 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4506 irq_event->irq, irq_event->level,
4507 line_status);
23d43cf9
CD		 4508 return 0;
4509}
4510
e5d83c74
PB		 4511int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4512 struct kvm_enable_cap *cap)
90de4a18
NA		 4513{
4514 int r;
4515
4516 if (cap->flags)
4517 return -EINVAL;
4518
4519 switch (cap->cap) {
4520 case KVM_CAP_DISABLE_QUIRKS:
4521 kvm->arch.disabled_quirks = cap->args[0];
4522 r = 0;
4523 break;
49df6397
SR		 4524 case KVM_CAP_SPLIT_IRQCHIP: {
4525 mutex_lock(&kvm->lock);
b053b2ae
SR		 4526 r = -EINVAL;
4527 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4528 goto split_irqchip_unlock;
49df6397
SR		 4529 r = -EEXIST;
4530 if (irqchip_in_kernel(kvm))
4531 goto split_irqchip_unlock;
557abc40 4532 if (kvm->created_vcpus)
49df6397
SR		 4533 goto split_irqchip_unlock;
4534 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4535 if (r)
49df6397
SR		 4536 goto split_irqchip_unlock;
4537 /* Pairs with irqchip_in_kernel. */
4538 smp_wmb();
49776faf 4539 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4540 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4541 r = 0;
4542split_irqchip_unlock:
4543 mutex_unlock(&kvm->lock);
4544 break;
4545 }
37131313
RK		 4546 case KVM_CAP_X2APIC_API:
4547 r = -EINVAL;
4548 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4549 break;
4550
4551 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4552 kvm->arch.x2apic_format = true;
c519265f
RK		 4553 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4554 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4555
4556 r = 0;
4557 break;
4d5422ce
WL		 4558 case KVM_CAP_X86_DISABLE_EXITS:
4559 r = -EINVAL;
4560 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4561 break;
4562
4563 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4564 kvm_can_mwait_in_guest())
4565 kvm->arch.mwait_in_guest = true;
766d3571 4566 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4567 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4568 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4569 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4570 r = 0;
4571 break;
6fbbde9a
DS		 4572 case KVM_CAP_MSR_PLATFORM_INFO:
4573 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4574 r = 0;
c4f55198
JM		 4575 break;
4576 case KVM_CAP_EXCEPTION_PAYLOAD:
4577 kvm->arch.exception_payload_enabled = cap->args[0];
4578 r = 0;
6fbbde9a 4579 break;
90de4a18
NA		 4580 default:
4581 r = -EINVAL;
4582 break;
4583 }
4584 return r;
4585}
4586
1fe779f8
CO		 4587long kvm_arch_vm_ioctl(struct file *filp,
4588 unsigned int ioctl, unsigned long arg)
4589{
4590 struct kvm *kvm = filp->private_data;
4591 void __user *argp = (void __user *)arg;
367e1319 4592 int r = -ENOTTY;
f0d66275
DH		 4593 /*
4594 * This union makes it completely explicit to gcc-3.x
4595 * that these two variables' stack usage should be
4596 * combined, not added together.
4597 */
4598 union {
4599 struct kvm_pit_state ps;
e9f42757 4600 struct kvm_pit_state2 ps2;
c5ff41ce 4601 struct kvm_pit_config pit_config;
f0d66275 4602 } u;
1fe779f8
CO		 4603
4604 switch (ioctl) {
4605 case KVM_SET_TSS_ADDR:
4606 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4607 break;
b927a3ce
SY		 4608 case KVM_SET_IDENTITY_MAP_ADDR: {
4609 u64 ident_addr;
4610
1af1ac91
DH		 4611 mutex_lock(&kvm->lock);
4612 r = -EINVAL;
4613 if (kvm->created_vcpus)
4614 goto set_identity_unlock;
b927a3ce 4615 r = -EFAULT;
0e96f31e 4616 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4617 goto set_identity_unlock;
b927a3ce 4618 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4619set_identity_unlock:
4620 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4621 break;
4622 }
1fe779f8
CO		 4623 case KVM_SET_NR_MMU_PAGES:
4624 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4625 break;
4626 case KVM_GET_NR_MMU_PAGES:
4627 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4628 break;
3ddea128 4629 case KVM_CREATE_IRQCHIP: {
3ddea128 4630 mutex_lock(&kvm->lock);
09941366 4631
3ddea128 4632 r = -EEXIST;
35e6eaa3 4633 if (irqchip_in_kernel(kvm))
3ddea128 4634 goto create_irqchip_unlock;
09941366 4635
3e515705 4636 r = -EINVAL;
557abc40 4637 if (kvm->created_vcpus)
3e515705 4638 goto create_irqchip_unlock;
09941366
RK		 4639
4640 r = kvm_pic_init(kvm);
4641 if (r)
3ddea128 4642 goto create_irqchip_unlock;
09941366
RK		 4643
4644 r = kvm_ioapic_init(kvm);
4645 if (r) {
09941366 4646 kvm_pic_destroy(kvm);
3ddea128 4647 goto create_irqchip_unlock;
09941366
RK		 4648 }
4649
399ec807
AK		 4650 r = kvm_setup_default_irq_routing(kvm);
4651 if (r) {
72bb2fcd 4652 kvm_ioapic_destroy(kvm);
09941366 4653 kvm_pic_destroy(kvm);
71ba994c 4654 goto create_irqchip_unlock;
399ec807 4655 }
49776faf 4656 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4657 smp_wmb();
49776faf 4658 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4659 create_irqchip_unlock:
4660 mutex_unlock(&kvm->lock);
1fe779f8 4661 break;
3ddea128 4662 }
7837699f 4663 case KVM_CREATE_PIT:
c5ff41ce
JK		 4664 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4665 goto create_pit;
4666 case KVM_CREATE_PIT2:
4667 r = -EFAULT;
4668 if (copy_from_user(&u.pit_config, argp,
4669 sizeof(struct kvm_pit_config)))
4670 goto out;
4671 create_pit:
250715a6 4672 mutex_lock(&kvm->lock);
269e05e4
AK		 4673 r = -EEXIST;
4674 if (kvm->arch.vpit)
4675 goto create_pit_unlock;
7837699f 4676 r = -ENOMEM;
c5ff41ce 4677 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4678 if (kvm->arch.vpit)
4679 r = 0;
269e05e4 4680 create_pit_unlock:
250715a6 4681 mutex_unlock(&kvm->lock);
7837699f 4682 break;
1fe779f8
CO		 4683 case KVM_GET_IRQCHIP: {
4684 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4685 struct kvm_irqchip *chip;
1fe779f8 4686
ff5c2c03
SL		 4687 chip = memdup_user(argp, sizeof(*chip));
4688 if (IS_ERR(chip)) {
4689 r = PTR_ERR(chip);
1fe779f8 4690 goto out;
ff5c2c03
SL		 4691 }
4692
1fe779f8 4693 r = -ENXIO;
826da321 4694 if (!irqchip_kernel(kvm))
f0d66275
DH		 4695 goto get_irqchip_out;
4696 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4697 if (r)
f0d66275 4698 goto get_irqchip_out;
1fe779f8 4699 r = -EFAULT;
0e96f31e 4700 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4701 goto get_irqchip_out;
1fe779f8 4702 r = 0;
f0d66275
DH		 4703 get_irqchip_out:
4704 kfree(chip);
1fe779f8
CO		 4705 break;
4706 }
4707 case KVM_SET_IRQCHIP: {
4708 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4709 struct kvm_irqchip *chip;
1fe779f8 4710
ff5c2c03
SL		 4711 chip = memdup_user(argp, sizeof(*chip));
4712 if (IS_ERR(chip)) {
4713 r = PTR_ERR(chip);
1fe779f8 4714 goto out;
ff5c2c03
SL		 4715 }
4716
1fe779f8 4717 r = -ENXIO;
826da321 4718 if (!irqchip_kernel(kvm))
f0d66275
DH		 4719 goto set_irqchip_out;
4720 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4721 if (r)
f0d66275 4722 goto set_irqchip_out;
1fe779f8 4723 r = 0;
f0d66275
DH		 4724 set_irqchip_out:
4725 kfree(chip);
1fe779f8
CO		 4726 break;
4727 }
e0f63cb9 4728 case KVM_GET_PIT: {
e0f63cb9 4729 r = -EFAULT;
f0d66275 4730 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4731 goto out;
4732 r = -ENXIO;
4733 if (!kvm->arch.vpit)
4734 goto out;
f0d66275 4735 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4736 if (r)
4737 goto out;
4738 r = -EFAULT;
f0d66275 4739 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4740 goto out;
4741 r = 0;
4742 break;
4743 }
4744 case KVM_SET_PIT: {
e0f63cb9 4745 r = -EFAULT;
0e96f31e 4746 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4747 goto out;
4748 r = -ENXIO;
4749 if (!kvm->arch.vpit)
4750 goto out;
f0d66275 4751 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4752 break;
4753 }
e9f42757
BK		 4754 case KVM_GET_PIT2: {
4755 r = -ENXIO;
4756 if (!kvm->arch.vpit)
4757 goto out;
4758 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4759 if (r)
4760 goto out;
4761 r = -EFAULT;
4762 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4763 goto out;
4764 r = 0;
4765 break;
4766 }
4767 case KVM_SET_PIT2: {
4768 r = -EFAULT;
4769 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4770 goto out;
4771 r = -ENXIO;
4772 if (!kvm->arch.vpit)
4773 goto out;
4774 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4775 break;
4776 }
52d939a0
MT		 4777 case KVM_REINJECT_CONTROL: {
4778 struct kvm_reinject_control control;
4779 r = -EFAULT;
4780 if (copy_from_user(&control, argp, sizeof(control)))
4781 goto out;
4782 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4783 break;
4784 }
d71ba788
PB		 4785 case KVM_SET_BOOT_CPU_ID:
4786 r = 0;
4787 mutex_lock(&kvm->lock);
557abc40 4788 if (kvm->created_vcpus)
d71ba788
PB		 4789 r = -EBUSY;
4790 else
4791 kvm->arch.bsp_vcpu_id = arg;
4792 mutex_unlock(&kvm->lock);
4793 break;
ffde22ac 4794 case KVM_XEN_HVM_CONFIG: {
51776043 4795 struct kvm_xen_hvm_config xhc;
ffde22ac 4796 r = -EFAULT;
51776043 4797 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4798 goto out;
4799 r = -EINVAL;
51776043 4800 if (xhc.flags)
ffde22ac 4801 goto out;
51776043 4802 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4803 r = 0;
4804 break;
4805 }
afbcf7ab 4806 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4807 struct kvm_clock_data user_ns;
4808 u64 now_ns;
afbcf7ab
GC		 4809
4810 r = -EFAULT;
4811 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4812 goto out;
4813
4814 r = -EINVAL;
4815 if (user_ns.flags)
4816 goto out;
4817
4818 r = 0;
0bc48bea
RK		 4819 /*
4820 * TODO: userspace has to take care of races with VCPU_RUN, so
4821 * kvm_gen_update_masterclock() can be cut down to locked
4822 * pvclock_update_vm_gtod_copy().
4823 */
4824 kvm_gen_update_masterclock(kvm);
e891a32e 4825 now_ns = get_kvmclock_ns(kvm);
108b249c 4826 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4827 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4828 break;
4829 }
4830 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4831 struct kvm_clock_data user_ns;
4832 u64 now_ns;
4833
e891a32e 4834 now_ns = get_kvmclock_ns(kvm);
108b249c 4835 user_ns.clock = now_ns;
e3fd9a93 4836 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4837 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4838
4839 r = -EFAULT;
4840 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4841 goto out;
4842 r = 0;
4843 break;
4844 }
5acc5c06
BS		 4845 case KVM_MEMORY_ENCRYPT_OP: {
4846 r = -ENOTTY;
4847 if (kvm_x86_ops->mem_enc_op)
4848 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4849 break;
4850 }
69eaedee
BS		 4851 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4852 struct kvm_enc_region region;
4853
4854 r = -EFAULT;
4855 if (copy_from_user(&region, argp, sizeof(region)))
4856 goto out;
4857
4858 r = -ENOTTY;
4859 if (kvm_x86_ops->mem_enc_reg_region)
4860 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4861 break;
4862 }
4863 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4864 struct kvm_enc_region region;
4865
4866 r = -EFAULT;
4867 if (copy_from_user(&region, argp, sizeof(region)))
4868 goto out;
4869
4870 r = -ENOTTY;
4871 if (kvm_x86_ops->mem_enc_unreg_region)
4872 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4873 break;
4874 }
faeb7833
RK		 4875 case KVM_HYPERV_EVENTFD: {
4876 struct kvm_hyperv_eventfd hvevfd;
4877
4878 r = -EFAULT;
4879 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4880 goto out;
4881 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4882 break;
4883 }
1fe779f8 4884 default:
ad6260da 4885 r = -ENOTTY;
1fe779f8
CO		 4886 }
4887out:
4888 return r;
4889}
4890
a16b043c 4891static void kvm_init_msr_list(void)
043405e1
CO		 4892{
4893 u32 dummy[2];
4894 unsigned i, j;
4895
62ef68bb 4896 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4897 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4898 continue;
93c4adc7
PB		 4899
4900 /*
4901 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4902 * to the guests in some cases.
93c4adc7
PB		 4903 */
4904 switch (msrs_to_save[i]) {
4905 case MSR_IA32_BNDCFGS:
503234b3 4906 if (!kvm_mpx_supported())
93c4adc7
PB		 4907 continue;
4908 break;
9dbe6cf9
PB		 4909 case MSR_TSC_AUX:
4910 if (!kvm_x86_ops->rdtscp_supported())
4911 continue;
4912 break;
bf8c55d8
CP		 4913 case MSR_IA32_RTIT_CTL:
4914 case MSR_IA32_RTIT_STATUS:
4915 if (!kvm_x86_ops->pt_supported())
4916 continue;
4917 break;
4918 case MSR_IA32_RTIT_CR3_MATCH:
4919 if (!kvm_x86_ops->pt_supported() ||
4920 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
4921 continue;
4922 break;
4923 case MSR_IA32_RTIT_OUTPUT_BASE:
4924 case MSR_IA32_RTIT_OUTPUT_MASK:
4925 if (!kvm_x86_ops->pt_supported() ||
4926 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
4927 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
4928 continue;
4929 break;
4930 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
4931 if (!kvm_x86_ops->pt_supported() ||
4932 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
4933 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
4934 continue;
4935 break;
4936 }
93c4adc7
PB		 4937 default:
4938 break;
4939 }
4940
043405e1
CO		 4941 if (j < i)
4942 msrs_to_save[j] = msrs_to_save[i];
4943 j++;
4944 }
4945 num_msrs_to_save = j;
62ef68bb
PB		 4946
4947 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4948 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4949 continue;
62ef68bb
PB		 4950
4951 if (j < i)
4952 emulated_msrs[j] = emulated_msrs[i];
4953 j++;
4954 }
4955 num_emulated_msrs = j;
801e459a
TL		 4956
4957 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4958 struct kvm_msr_entry msr;
4959
4960 msr.index = msr_based_features[i];
66421c1e 4961 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4962 continue;
4963
4964 if (j < i)
4965 msr_based_features[j] = msr_based_features[i];
4966 j++;
4967 }
4968 num_msr_based_features = j;
043405e1
CO		 4969}
4970
bda9020e
MT		 4971static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4972 const void *v)
bbd9b64e 4973{
70252a10
AK		 4974 int handled = 0;
4975 int n;
4976
4977 do {
4978 n = min(len, 8);
bce87cce 4979 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4980 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4981 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4982 break;
4983 handled += n;
4984 addr += n;
4985 len -= n;
4986 v += n;
4987 } while (len);
bbd9b64e 4988
70252a10 4989 return handled;
bbd9b64e
CO		 4990}
4991
bda9020e 4992static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4993{
70252a10
AK		 4994 int handled = 0;
4995 int n;
4996
4997 do {
4998 n = min(len, 8);
bce87cce 4999 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5000 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5001 addr, n, v))
5002 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5003 break;
e39d200f 5004 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5005 handled += n;
5006 addr += n;
5007 len -= n;
5008 v += n;
5009 } while (len);
bbd9b64e 5010
70252a10 5011 return handled;
bbd9b64e
CO		 5012}
5013
2dafc6c2
GN		 5014static void kvm_set_segment(struct kvm_vcpu *vcpu,
5015 struct kvm_segment *var, int seg)
5016{
5017 kvm_x86_ops->set_segment(vcpu, var, seg);
5018}
5019
5020void kvm_get_segment(struct kvm_vcpu *vcpu,
5021 struct kvm_segment *var, int seg)
5022{
5023 kvm_x86_ops->get_segment(vcpu, var, seg);
5024}
5025
54987b7a
PB		 5026gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5027 struct x86_exception *exception)
02f59dc9
JR		 5028{
5029 gpa_t t_gpa;
02f59dc9
JR		 5030
5031 BUG_ON(!mmu_is_nested(vcpu));
5032
5033 /* NPT walks are always user-walks */
5034 access |= PFERR_USER_MASK;
44dd3ffa 5035 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5036
5037 return t_gpa;
5038}
5039
ab9ae313
AK		 5040gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5041 struct x86_exception *exception)
1871c602
GN		 5042{
5043 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5044 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5045}
5046
ab9ae313
AK		 5047 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5048 struct x86_exception *exception)
1871c602
GN		 5049{
5050 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5051 access |= PFERR_FETCH_MASK;
ab9ae313 5052 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5053}
5054
ab9ae313
AK		 5055gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5056 struct x86_exception *exception)
1871c602
GN		 5057{
5058 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5059 access |= PFERR_WRITE_MASK;
ab9ae313 5060 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5061}
5062
5063/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5064gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5065 struct x86_exception *exception)
1871c602 5066{
ab9ae313 5067 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5068}
5069
5070static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5071 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5072 struct x86_exception *exception)
bbd9b64e
CO		 5073{
5074 void *data = val;
10589a46 5075 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5076
5077 while (bytes) {
14dfe855 5078 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5079 exception);
bbd9b64e 5080 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5081 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5082 int ret;
5083
bcc55cba 5084 if (gpa == UNMAPPED_GVA)
ab9ae313 5085 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5086 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5087 offset, toread);
10589a46 5088 if (ret < 0) {
c3cd7ffa 5089 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5090 goto out;
5091 }
bbd9b64e 5092
77c2002e
IE		 5093 bytes -= toread;
5094 data += toread;
5095 addr += toread;
bbd9b64e 5096 }
10589a46 5097out:
10589a46 5098 return r;
bbd9b64e 5099}
77c2002e 5100
1871c602 5101/* used for instruction fetching */
0f65dd70
AK		 5102static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5103 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5104 struct x86_exception *exception)
1871c602 5105{
0f65dd70 5106 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5107 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5108 unsigned offset;
5109 int ret;
0f65dd70 5110
44583cba
PB		 5111 /* Inline kvm_read_guest_virt_helper for speed. */
5112 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5113 exception);
5114 if (unlikely(gpa == UNMAPPED_GVA))
5115 return X86EMUL_PROPAGATE_FAULT;
5116
5117 offset = addr & (PAGE_SIZE-1);
5118 if (WARN_ON(offset + bytes > PAGE_SIZE))
5119 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5120 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5121 offset, bytes);
44583cba
PB		 5122 if (unlikely(ret < 0))
5123 return X86EMUL_IO_NEEDED;
5124
5125 return X86EMUL_CONTINUE;
1871c602
GN		 5126}
5127
ce14e868 5128int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5129 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5130 struct x86_exception *exception)
1871c602
GN		 5131{
5132 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5133
353c0956
PB		 5134 /*
5135 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5136 * is returned, but our callers are not ready for that and they blindly
5137 * call kvm_inject_page_fault. Ensure that they at least do not leak
5138 * uninitialized kernel stack memory into cr2 and error code.
5139 */
5140 memset(exception, 0, sizeof(*exception));
1871c602 5141 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5142 exception);
1871c602 5143}
064aea77 5144EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5145
ce14e868
PB		 5146static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5147 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5148 struct x86_exception *exception, bool system)
1871c602 5149{
0f65dd70 5150 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5151 u32 access = 0;
5152
5153 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5154 access |= PFERR_USER_MASK;
5155
5156 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5157}
5158
7a036a6f
RK		 5159static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5160 unsigned long addr, void *val, unsigned int bytes)
5161{
5162 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5163 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5164
5165 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5166}
5167
ce14e868
PB		 5168static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5169 struct kvm_vcpu *vcpu, u32 access,
5170 struct x86_exception *exception)
77c2002e
IE		 5171{
5172 void *data = val;
5173 int r = X86EMUL_CONTINUE;
5174
5175 while (bytes) {
14dfe855 5176 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5177 access,
ab9ae313 5178 exception);
77c2002e
IE		 5179 unsigned offset = addr & (PAGE_SIZE-1);
5180 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5181 int ret;
5182
bcc55cba 5183 if (gpa == UNMAPPED_GVA)
ab9ae313 5184 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5185 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5186 if (ret < 0) {
c3cd7ffa 5187 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5188 goto out;
5189 }
5190
5191 bytes -= towrite;
5192 data += towrite;
5193 addr += towrite;
5194 }
5195out:
5196 return r;
5197}
ce14e868
PB		 5198
5199static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5200 unsigned int bytes, struct x86_exception *exception,
5201 bool system)
ce14e868
PB		 5202{
5203 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5204 u32 access = PFERR_WRITE_MASK;
5205
5206 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5207 access |= PFERR_USER_MASK;
ce14e868
PB		 5208
5209 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5210 access, exception);
ce14e868
PB		 5211}
5212
5213int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5214 unsigned int bytes, struct x86_exception *exception)
5215{
c595ceee
PB		 5216 /* kvm_write_guest_virt_system can pull in tons of pages. */
5217 vcpu->arch.l1tf_flush_l1d = true;
5218
ce14e868
PB		 5219 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5220 PFERR_WRITE_MASK, exception);
5221}
6a4d7550 5222EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5223
082d06ed
WL		 5224int handle_ud(struct kvm_vcpu *vcpu)
5225{
6c86eedc 5226 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5227 enum emulation_result er;
6c86eedc
WL		 5228 char sig[5]; /* ud2; .ascii "kvm" */
5229 struct x86_exception e;
5230
5231 if (force_emulation_prefix &&
3c9fa24c
PB		 5232 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5233 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5234 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5235 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5236 emul_type = 0;
5237 }
082d06ed 5238
0ce97a2b 5239 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5240 if (er == EMULATE_USER_EXIT)
5241 return 0;
5242 if (er != EMULATE_DONE)
5243 kvm_queue_exception(vcpu, UD_VECTOR);
5244 return 1;
5245}
5246EXPORT_SYMBOL_GPL(handle_ud);
5247
0f89b207
TL		 5248static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5249 gpa_t gpa, bool write)
5250{
5251 /* For APIC access vmexit */
5252 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5253 return 1;
5254
5255 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5256 trace_vcpu_match_mmio(gva, gpa, write, true);
5257 return 1;
5258 }
5259
5260 return 0;
5261}
5262
af7cc7d1
XG		 5263static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5264 gpa_t *gpa, struct x86_exception *exception,
5265 bool write)
5266{
97d64b78
AK		 5267 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5268 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5269
be94f6b7
HH		 5270 /*
5271 * currently PKRU is only applied to ept enabled guest so
5272 * there is no pkey in EPT page table for L1 guest or EPT
5273 * shadow page table for L2 guest.
5274 */
97d64b78 5275 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5276 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5277 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5278 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5279 (gva & (PAGE_SIZE - 1));
4f022648 5280 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5281 return 1;
5282 }
5283
af7cc7d1
XG		 5284 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5285
5286 if (*gpa == UNMAPPED_GVA)
5287 return -1;
5288
0f89b207 5289 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5290}
5291
3200f405 5292int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5293 const void *val, int bytes)
bbd9b64e
CO		 5294{
5295 int ret;
5296
54bf36aa 5297 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5298 if (ret < 0)
bbd9b64e 5299 return 0;
0eb05bf2 5300 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5301 return 1;
5302}
5303
77d197b2
XG		 5304struct read_write_emulator_ops {
5305 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5306 int bytes);
5307 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5308 void *val, int bytes);
5309 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5310 int bytes, void *val);
5311 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5312 void *val, int bytes);
5313 bool write;
5314};
5315
5316static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5317{
5318 if (vcpu->mmio_read_completed) {
77d197b2 5319 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5320 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5321 vcpu->mmio_read_completed = 0;
5322 return 1;
5323 }
5324
5325 return 0;
5326}
5327
5328static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5329 void *val, int bytes)
5330{
54bf36aa 5331 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5332}
5333
5334static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5335 void *val, int bytes)
5336{
5337 return emulator_write_phys(vcpu, gpa, val, bytes);
5338}
5339
5340static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5341{
e39d200f 5342 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5343 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5344}
5345
5346static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5347 void *val, int bytes)
5348{
e39d200f 5349 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5350 return X86EMUL_IO_NEEDED;
5351}
5352
5353static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5354 void *val, int bytes)
5355{
f78146b0
AK		 5356 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5357
87da7e66 5358 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5359 return X86EMUL_CONTINUE;
5360}
5361
0fbe9b0b 5362static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5363 .read_write_prepare = read_prepare,
5364 .read_write_emulate = read_emulate,
5365 .read_write_mmio = vcpu_mmio_read,
5366 .read_write_exit_mmio = read_exit_mmio,
5367};
5368
0fbe9b0b 5369static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5370 .read_write_emulate = write_emulate,
5371 .read_write_mmio = write_mmio,
5372 .read_write_exit_mmio = write_exit_mmio,
5373 .write = true,
5374};
5375
22388a3c
XG		 5376static int emulator_read_write_onepage(unsigned long addr, void *val,
5377 unsigned int bytes,
5378 struct x86_exception *exception,
5379 struct kvm_vcpu *vcpu,
0fbe9b0b 5380 const struct read_write_emulator_ops *ops)
bbd9b64e 5381{
af7cc7d1
XG		 5382 gpa_t gpa;
5383 int handled, ret;
22388a3c 5384 bool write = ops->write;
f78146b0 5385 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5386 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5387
5388 /*
5389 * If the exit was due to a NPF we may already have a GPA.
5390 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5391 * Note, this cannot be used on string operations since string
5392 * operation using rep will only have the initial GPA from the NPF
5393 * occurred.
5394 */
5395 if (vcpu->arch.gpa_available &&
5396 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5397 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5398 gpa = vcpu->arch.gpa_val;
5399 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5400 } else {
5401 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5402 if (ret < 0)
5403 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5404 }
10589a46 5405
618232e2 5406 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5407 return X86EMUL_CONTINUE;
5408
bbd9b64e
CO		 5409 /*
5410 * Is this MMIO handled locally?
5411 */
22388a3c 5412 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5413 if (handled == bytes)
bbd9b64e 5414 return X86EMUL_CONTINUE;
bbd9b64e 5415
70252a10
AK		 5416 gpa += handled;
5417 bytes -= handled;
5418 val += handled;
5419
87da7e66
XG		 5420 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5421 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5422 frag->gpa = gpa;
5423 frag->data = val;
5424 frag->len = bytes;
f78146b0 5425 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5426}
5427
52eb5a6d
XL		 5428static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5429 unsigned long addr,
22388a3c
XG		 5430 void *val, unsigned int bytes,
5431 struct x86_exception *exception,
0fbe9b0b 5432 const struct read_write_emulator_ops *ops)
bbd9b64e 5433{
0f65dd70 5434 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5435 gpa_t gpa;
5436 int rc;
5437
5438 if (ops->read_write_prepare &&
5439 ops->read_write_prepare(vcpu, val, bytes))
5440 return X86EMUL_CONTINUE;
5441
5442 vcpu->mmio_nr_fragments = 0;
0f65dd70 5443
bbd9b64e
CO		 5444 /* Crossing a page boundary? */
5445 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5446 int now;
bbd9b64e
CO		 5447
5448 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5449 rc = emulator_read_write_onepage(addr, val, now, exception,
5450 vcpu, ops);
5451
bbd9b64e
CO		 5452 if (rc != X86EMUL_CONTINUE)
5453 return rc;
5454 addr += now;
bac15531
NA		 5455 if (ctxt->mode != X86EMUL_MODE_PROT64)
5456 addr = (u32)addr;
bbd9b64e
CO		 5457 val += now;
5458 bytes -= now;
5459 }
22388a3c 5460
f78146b0
AK		 5461 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5462 vcpu, ops);
5463 if (rc != X86EMUL_CONTINUE)
5464 return rc;
5465
5466 if (!vcpu->mmio_nr_fragments)
5467 return rc;
5468
5469 gpa = vcpu->mmio_fragments[0].gpa;
5470
5471 vcpu->mmio_needed = 1;
5472 vcpu->mmio_cur_fragment = 0;
5473
87da7e66 5474 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5475 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5476 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5477 vcpu->run->mmio.phys_addr = gpa;
5478
5479 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5480}
5481
5482static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5483 unsigned long addr,
5484 void *val,
5485 unsigned int bytes,
5486 struct x86_exception *exception)
5487{
5488 return emulator_read_write(ctxt, addr, val, bytes,
5489 exception, &read_emultor);
5490}
5491
52eb5a6d 5492static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5493 unsigned long addr,
5494 const void *val,
5495 unsigned int bytes,
5496 struct x86_exception *exception)
5497{
5498 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5499 exception, &write_emultor);
bbd9b64e 5500}
bbd9b64e 5501
daea3e73
AK		 5502#define CMPXCHG_TYPE(t, ptr, old, new) \
5503 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5504
5505#ifdef CONFIG_X86_64
5506# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5507#else
5508# define CMPXCHG64(ptr, old, new) \
9749a6c0 5509 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5510#endif
5511
0f65dd70
AK		 5512static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5513 unsigned long addr,
bbd9b64e
CO		 5514 const void *old,
5515 const void *new,
5516 unsigned int bytes,
0f65dd70 5517 struct x86_exception *exception)
bbd9b64e 5518{
0f65dd70 5519 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5520 gpa_t gpa;
5521 struct page *page;
5522 char *kaddr;
5523 bool exchanged;
2bacc55c 5524
daea3e73
AK		 5525 /* guests cmpxchg8b have to be emulated atomically */
5526 if (bytes > 8 || (bytes & (bytes - 1)))
5527 goto emul_write;
10589a46 5528
daea3e73 5529 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5530
daea3e73
AK		 5531 if (gpa == UNMAPPED_GVA ||
5532 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5533 goto emul_write;
2bacc55c 5534
daea3e73
AK		 5535 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5536 goto emul_write;
72dc67a6 5537
54bf36aa 5538 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5539 if (is_error_page(page))
c19b8bd6 5540 goto emul_write;
72dc67a6 5541
8fd75e12 5542 kaddr = kmap_atomic(page);
daea3e73
AK		 5543 kaddr += offset_in_page(gpa);
5544 switch (bytes) {
5545 case 1:
5546 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5547 break;
5548 case 2:
5549 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5550 break;
5551 case 4:
5552 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5553 break;
5554 case 8:
5555 exchanged = CMPXCHG64(kaddr, old, new);
5556 break;
5557 default:
5558 BUG();
2bacc55c 5559 }
8fd75e12 5560 kunmap_atomic(kaddr);
daea3e73
AK		 5561 kvm_release_page_dirty(page);
5562
5563 if (!exchanged)
5564 return X86EMUL_CMPXCHG_FAILED;
5565
54bf36aa 5566 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5567 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5568
5569 return X86EMUL_CONTINUE;
4a5f48f6 5570
3200f405 5571emul_write:
daea3e73 5572 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5573
0f65dd70 5574 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5575}
5576
cf8f70bf
GN		 5577static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5578{
cbfc6c91 5579 int r = 0, i;
cf8f70bf 5580
cbfc6c91
WL		 5581 for (i = 0; i < vcpu->arch.pio.count; i++) {
5582 if (vcpu->arch.pio.in)
5583 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5584 vcpu->arch.pio.size, pd);
5585 else
5586 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5587 vcpu->arch.pio.port, vcpu->arch.pio.size,
5588 pd);
5589 if (r)
5590 break;
5591 pd += vcpu->arch.pio.size;
5592 }
cf8f70bf
GN		 5593 return r;
5594}
5595
6f6fbe98
XG		 5596static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5597 unsigned short port, void *val,
5598 unsigned int count, bool in)
cf8f70bf 5599{
cf8f70bf 5600 vcpu->arch.pio.port = port;
6f6fbe98 5601 vcpu->arch.pio.in = in;
7972995b 5602 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5603 vcpu->arch.pio.size = size;
5604
5605 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5606 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5607 return 1;
5608 }
5609
5610 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5611 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5612 vcpu->run->io.size = size;
5613 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5614 vcpu->run->io.count = count;
5615 vcpu->run->io.port = port;
5616
5617 return 0;
5618}
5619
6f6fbe98
XG		 5620static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5621 int size, unsigned short port, void *val,
5622 unsigned int count)
cf8f70bf 5623{
ca1d4a9e 5624 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5625 int ret;
ca1d4a9e 5626
6f6fbe98
XG		 5627 if (vcpu->arch.pio.count)
5628 goto data_avail;
cf8f70bf 5629
cbfc6c91
WL		 5630 memset(vcpu->arch.pio_data, 0, size * count);
5631
6f6fbe98
XG		 5632 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5633 if (ret) {
5634data_avail:
5635 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5636 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5637 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5638 return 1;
5639 }
5640
cf8f70bf
GN		 5641 return 0;
5642}
5643
6f6fbe98
XG		 5644static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5645 int size, unsigned short port,
5646 const void *val, unsigned int count)
5647{
5648 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5649
5650 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5651 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5652 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5653}
5654
bbd9b64e
CO		 5655static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5656{
5657 return kvm_x86_ops->get_segment_base(vcpu, seg);
5658}
5659
3cb16fe7 5660static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5661{
3cb16fe7 5662 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5663}
5664
ae6a2375 5665static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5666{
5667 if (!need_emulate_wbinvd(vcpu))
5668 return X86EMUL_CONTINUE;
5669
5670 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5671 int cpu = get_cpu();
5672
5673 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5674 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5675 wbinvd_ipi, NULL, 1);
2eec7343 5676 put_cpu();
f5f48ee1 5677 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5678 } else
5679 wbinvd();
f5f48ee1
SY		 5680 return X86EMUL_CONTINUE;
5681}
5cb56059
JS		 5682
5683int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5684{
6affcbed
KH		 5685 kvm_emulate_wbinvd_noskip(vcpu);
5686 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5687}
f5f48ee1
SY		 5688EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5689
5cb56059
JS		 5690
5691
bcaf5cc5
AK		 5692static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5693{
5cb56059 5694 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5695}
5696
52eb5a6d
XL		 5697static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5698 unsigned long *dest)
bbd9b64e 5699{
16f8a6f9 5700 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5701}
5702
52eb5a6d
XL		 5703static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5704 unsigned long value)
bbd9b64e 5705{
338dbc97 5706
717746e3 5707 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5708}
5709
52a46617 5710static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5711{
52a46617 5712 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5713}
5714
717746e3 5715static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5716{
717746e3 5717 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5718 unsigned long value;
5719
5720 switch (cr) {
5721 case 0:
5722 value = kvm_read_cr0(vcpu);
5723 break;
5724 case 2:
5725 value = vcpu->arch.cr2;
5726 break;
5727 case 3:
9f8fe504 5728 value = kvm_read_cr3(vcpu);
52a46617
GN		 5729 break;
5730 case 4:
5731 value = kvm_read_cr4(vcpu);
5732 break;
5733 case 8:
5734 value = kvm_get_cr8(vcpu);
5735 break;
5736 default:
a737f256 5737 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5738 return 0;
5739 }
5740
5741 return value;
5742}
5743
717746e3 5744static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5745{
717746e3 5746 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5747 int res = 0;
5748
52a46617
GN		 5749 switch (cr) {
5750 case 0:
49a9b07e 5751 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5752 break;
5753 case 2:
5754 vcpu->arch.cr2 = val;
5755 break;
5756 case 3:
2390218b 5757 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5758 break;
5759 case 4:
a83b29c6 5760 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5761 break;
5762 case 8:
eea1cff9 5763 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5764 break;
5765 default:
a737f256 5766 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5767 res = -1;
52a46617 5768 }
0f12244f
GN		 5769
5770 return res;
52a46617
GN		 5771}
5772
717746e3 5773static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5774{
717746e3 5775 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5776}
5777
4bff1e86 5778static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5779{
4bff1e86 5780 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5781}
5782
4bff1e86 5783static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5784{
4bff1e86 5785 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5786}
5787
1ac9d0cf
AK		 5788static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5789{
5790 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5791}
5792
5793static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5794{
5795 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5796}
5797
4bff1e86
AK		 5798static unsigned long emulator_get_cached_segment_base(
5799 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5800{
4bff1e86 5801 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5802}
5803
1aa36616
AK		 5804static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5805 struct desc_struct *desc, u32 *base3,
5806 int seg)
2dafc6c2
GN		 5807{
5808 struct kvm_segment var;
5809
4bff1e86 5810 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5811 *selector = var.selector;
2dafc6c2 5812
378a8b09
GN		 5813 if (var.unusable) {
5814 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5815 if (base3)
5816 *base3 = 0;
2dafc6c2 5817 return false;
378a8b09 5818 }
2dafc6c2
GN		 5819
5820 if (var.g)
5821 var.limit >>= 12;
5822 set_desc_limit(desc, var.limit);
5823 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5824#ifdef CONFIG_X86_64
5825 if (base3)
5826 *base3 = var.base >> 32;
5827#endif
2dafc6c2
GN		 5828 desc->type = var.type;
5829 desc->s = var.s;
5830 desc->dpl = var.dpl;
5831 desc->p = var.present;
5832 desc->avl = var.avl;
5833 desc->l = var.l;
5834 desc->d = var.db;
5835 desc->g = var.g;
5836
5837 return true;
5838}
5839
1aa36616
AK		 5840static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5841 struct desc_struct *desc, u32 base3,
5842 int seg)
2dafc6c2 5843{
4bff1e86 5844 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5845 struct kvm_segment var;
5846
1aa36616 5847 var.selector = selector;
2dafc6c2 5848 var.base = get_desc_base(desc);
5601d05b
GN		 5849#ifdef CONFIG_X86_64
5850 var.base |= ((u64)base3) << 32;
5851#endif
2dafc6c2
GN		 5852 var.limit = get_desc_limit(desc);
5853 if (desc->g)
5854 var.limit = (var.limit << 12) | 0xfff;
5855 var.type = desc->type;
2dafc6c2
GN		 5856 var.dpl = desc->dpl;
5857 var.db = desc->d;
5858 var.s = desc->s;
5859 var.l = desc->l;
5860 var.g = desc->g;
5861 var.avl = desc->avl;
5862 var.present = desc->p;
5863 var.unusable = !var.present;
5864 var.padding = 0;
5865
5866 kvm_set_segment(vcpu, &var, seg);
5867 return;
5868}
5869
717746e3
AK		 5870static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5871 u32 msr_index, u64 *pdata)
5872{
609e36d3
PB		 5873 struct msr_data msr;
5874 int r;
5875
5876 msr.index = msr_index;
5877 msr.host_initiated = false;
5878 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5879 if (r)
5880 return r;
5881
5882 *pdata = msr.data;
5883 return 0;
717746e3
AK		 5884}
5885
5886static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5887 u32 msr_index, u64 data)
5888{
8fe8ab46
WA		 5889 struct msr_data msr;
5890
5891 msr.data = data;
5892 msr.index = msr_index;
5893 msr.host_initiated = false;
5894 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5895}
5896
64d60670
PB		 5897static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5898{
5899 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5900
5901 return vcpu->arch.smbase;
5902}
5903
5904static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5905{
5906 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5907
5908 vcpu->arch.smbase = smbase;
5909}
5910
67f4d428
NA		 5911static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5912 u32 pmc)
5913{
c6702c9d 5914 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5915}
5916
222d21aa
AK		 5917static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5918 u32 pmc, u64 *pdata)
5919{
c6702c9d 5920 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5921}
5922
6c3287f7
AK		 5923static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5924{
5925 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5926}
5927
2953538e 5928static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5929 struct x86_instruction_info *info,
c4f035c6
AK		 5930 enum x86_intercept_stage stage)
5931{
2953538e 5932 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5933}
5934
e911eb3b
YZ		 5935static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5936 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5937{
e911eb3b 5938 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5939}
5940
dd856efa
AK		 5941static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5942{
5943 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5944}
5945
5946static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5947{
5948 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5949}
5950
801806d9
NA		 5951static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5952{
5953 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5954}
5955
6ed071f0
LP		 5956static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5957{
5958 return emul_to_vcpu(ctxt)->arch.hflags;
5959}
5960
5961static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5962{
c5833c7a 5963 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 5964}
5965
ed19321f
SC		 5966static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
5967 const char *smstate)
0234bf88 5968{
ed19321f 5969 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 5970}
5971
c5833c7a
SC		 5972static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
5973{
5974 kvm_smm_changed(emul_to_vcpu(ctxt));
5975}
5976
0225fb50 5977static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5978 .read_gpr = emulator_read_gpr,
5979 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5980 .read_std = emulator_read_std,
5981 .write_std = emulator_write_std,
7a036a6f 5982 .read_phys = kvm_read_guest_phys_system,
1871c602 5983 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5984 .read_emulated = emulator_read_emulated,
5985 .write_emulated = emulator_write_emulated,
5986 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5987 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5988 .pio_in_emulated = emulator_pio_in_emulated,
5989 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5990 .get_segment = emulator_get_segment,
5991 .set_segment = emulator_set_segment,
5951c442 5992 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5993 .get_gdt = emulator_get_gdt,
160ce1f1 5994 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5995 .set_gdt = emulator_set_gdt,
5996 .set_idt = emulator_set_idt,
52a46617
GN		 5997 .get_cr = emulator_get_cr,
5998 .set_cr = emulator_set_cr,
9c537244 5999 .cpl = emulator_get_cpl,
35aa5375
GN		 6000 .get_dr = emulator_get_dr,
6001 .set_dr = emulator_set_dr,
64d60670
PB		 6002 .get_smbase = emulator_get_smbase,
6003 .set_smbase = emulator_set_smbase,
717746e3
AK		 6004 .set_msr = emulator_set_msr,
6005 .get_msr = emulator_get_msr,
67f4d428 6006 .check_pmc = emulator_check_pmc,
222d21aa 6007 .read_pmc = emulator_read_pmc,
6c3287f7 6008 .halt = emulator_halt,
bcaf5cc5 6009 .wbinvd = emulator_wbinvd,
d6aa1000 6010 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6011 .intercept = emulator_intercept,
bdb42f5a 6012 .get_cpuid = emulator_get_cpuid,
801806d9 6013 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6014 .get_hflags = emulator_get_hflags,
6015 .set_hflags = emulator_set_hflags,
0234bf88 6016 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6017 .post_leave_smm = emulator_post_leave_smm,
bbd9b64e
CO		 6018};
6019
95cb2295
GN		 6020static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6021{
37ccdcbe 6022 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6023 /*
6024 * an sti; sti; sequence only disable interrupts for the first
6025 * instruction. So, if the last instruction, be it emulated or
6026 * not, left the system with the INT_STI flag enabled, it
6027 * means that the last instruction is an sti. We should not
6028 * leave the flag on in this case. The same goes for mov ss
6029 */
37ccdcbe
PB		 6030 if (int_shadow & mask)
6031 mask = 0;
6addfc42 6032 if (unlikely(int_shadow || mask)) {
95cb2295 6033 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6034 if (!mask)
6035 kvm_make_request(KVM_REQ_EVENT, vcpu);
6036 }
95cb2295
GN		 6037}
6038
ef54bcfe 6039static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6040{
6041 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6042 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6043 return kvm_propagate_fault(vcpu, &ctxt->exception);
6044
6045 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6046 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6047 ctxt->exception.error_code);
54b8486f 6048 else
da9cb575 6049 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6050 return false;
54b8486f
GN		 6051}
6052
8ec4722d
MG		 6053static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6054{
adf52235 6055 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6056 int cs_db, cs_l;
6057
8ec4722d
MG		 6058 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6059
adf52235 6060 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6061 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6062
adf52235
TY		 6063 ctxt->eip = kvm_rip_read(vcpu);
6064 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6065 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6066 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6067 cs_db ? X86EMUL_MODE_PROT32 :
6068 X86EMUL_MODE_PROT16;
a584539b 6069 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6070 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6071 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6072
dd856efa 6073 init_decode_cache(ctxt);
7ae441ea 6074 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6075}
6076
71f9833b 6077int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6078{
9d74191a 6079 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6080 int ret;
6081
6082 init_emulate_ctxt(vcpu);
6083
9dac77fa
AK		 6084 ctxt->op_bytes = 2;
6085 ctxt->ad_bytes = 2;
6086 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6087 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6088
6089 if (ret != X86EMUL_CONTINUE)
6090 return EMULATE_FAIL;
6091
9dac77fa 6092 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6093 kvm_rip_write(vcpu, ctxt->eip);
6094 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6095
63995653
MG		 6096 return EMULATE_DONE;
6097}
6098EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6099
e2366171 6100static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6101{
fc3a9157
JR		 6102 int r = EMULATE_DONE;
6103
6d77dbfc
GN		 6104 ++vcpu->stat.insn_emulation_fail;
6105 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6106
6107 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6108 return EMULATE_FAIL;
6109
a2b9e6c1 6110 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6111 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6112 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6113 vcpu->run->internal.ndata = 0;
1f4dcb3b 6114 r = EMULATE_USER_EXIT;
fc3a9157 6115 }
e2366171 6116
6d77dbfc 6117 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6118
6119 return r;
6d77dbfc
GN		 6120}
6121
93c05d3e 6122static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6123 bool write_fault_to_shadow_pgtable,
6124 int emulation_type)
a6f177ef 6125{
95b3cf69 6126 gpa_t gpa = cr2;
ba049e93 6127 kvm_pfn_t pfn;
a6f177ef 6128
384bf221 6129 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6130 return false;
6131
6c3dfeb6
SC		 6132 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6133 return false;
6134
44dd3ffa 6135 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6136 /*
6137 * Write permission should be allowed since only
6138 * write access need to be emulated.
6139 */
6140 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6141
95b3cf69
XG		 6142 /*
6143 * If the mapping is invalid in guest, let cpu retry
6144 * it to generate fault.
6145 */
6146 if (gpa == UNMAPPED_GVA)
6147 return true;
6148 }
a6f177ef 6149
8e3d9d06
XG		 6150 /*
6151 * Do not retry the unhandleable instruction if it faults on the
6152 * readonly host memory, otherwise it will goto a infinite loop:
6153 * retry instruction -> write #PF -> emulation fail -> retry
6154 * instruction -> ...
6155 */
6156 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6157
6158 /*
6159 * If the instruction failed on the error pfn, it can not be fixed,
6160 * report the error to userspace.
6161 */
6162 if (is_error_noslot_pfn(pfn))
6163 return false;
6164
6165 kvm_release_pfn_clean(pfn);
6166
6167 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6168 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6169 unsigned int indirect_shadow_pages;
6170
6171 spin_lock(&vcpu->kvm->mmu_lock);
6172 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6173 spin_unlock(&vcpu->kvm->mmu_lock);
6174
6175 if (indirect_shadow_pages)
6176 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6177
a6f177ef 6178 return true;
8e3d9d06 6179 }
a6f177ef 6180
95b3cf69
XG		 6181 /*
6182 * if emulation was due to access to shadowed page table
6183 * and it failed try to unshadow page and re-enter the
6184 * guest to let CPU execute the instruction.
6185 */
6186 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6187
6188 /*
6189 * If the access faults on its page table, it can not
6190 * be fixed by unprotecting shadow page and it should
6191 * be reported to userspace.
6192 */
6193 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6194}
6195
1cb3f3ae
XG		 6196static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6197 unsigned long cr2, int emulation_type)
6198{
6199 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6200 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6201
6202 last_retry_eip = vcpu->arch.last_retry_eip;
6203 last_retry_addr = vcpu->arch.last_retry_addr;
6204
6205 /*
6206 * If the emulation is caused by #PF and it is non-page_table
6207 * writing instruction, it means the VM-EXIT is caused by shadow
6208 * page protected, we can zap the shadow page and retry this
6209 * instruction directly.
6210 *
6211 * Note: if the guest uses a non-page-table modifying instruction
6212 * on the PDE that points to the instruction, then we will unmap
6213 * the instruction and go to an infinite loop. So, we cache the
6214 * last retried eip and the last fault address, if we meet the eip
6215 * and the address again, we can break out of the potential infinite
6216 * loop.
6217 */
6218 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6219
384bf221 6220 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6221 return false;
6222
6c3dfeb6
SC		 6223 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6224 return false;
6225
1cb3f3ae
XG		 6226 if (x86_page_table_writing_insn(ctxt))
6227 return false;
6228
6229 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6230 return false;
6231
6232 vcpu->arch.last_retry_eip = ctxt->eip;
6233 vcpu->arch.last_retry_addr = cr2;
6234
44dd3ffa 6235 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6236 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6237
22368028 6238 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6239
6240 return true;
6241}
6242
716d51ab
GN		 6243static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6244static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6245
64d60670 6246static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6247{
64d60670 6248 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6249 /* This is a good place to trace that we are exiting SMM. */
6250 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6251
c43203ca
PB		 6252 /* Process a latched INIT or SMI, if any. */
6253 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6254 }
699023e2
PB		 6255
6256 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6257}
6258
4a1e10d5
PB		 6259static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6260 unsigned long *db)
6261{
6262 u32 dr6 = 0;
6263 int i;
6264 u32 enable, rwlen;
6265
6266 enable = dr7;
6267 rwlen = dr7 >> 16;
6268 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6269 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6270 dr6 |= (1 << i);
6271 return dr6;
6272}
6273
c8401dda 6274static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6275{
6276 struct kvm_run *kvm_run = vcpu->run;
6277
c8401dda
PB		 6278 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6279 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6280 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6281 kvm_run->debug.arch.exception = DB_VECTOR;
6282 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6283 *r = EMULATE_USER_EXIT;
6284 } else {
f10c729f 6285 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6286 }
6287}
6288
6affcbed
KH		 6289int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6290{
6291 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6292 int r = EMULATE_DONE;
6293
6294 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6295
6296 /*
6297 * rflags is the old, "raw" value of the flags. The new value has
6298 * not been saved yet.
6299 *
6300 * This is correct even for TF set by the guest, because "the
6301 * processor will not generate this exception after the instruction
6302 * that sets the TF flag".
6303 */
6304 if (unlikely(rflags & X86_EFLAGS_TF))
6305 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6306 return r == EMULATE_DONE;
6307}
6308EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6309
4a1e10d5
PB		 6310static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6311{
4a1e10d5
PB		 6312 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6313 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6314 struct kvm_run *kvm_run = vcpu->run;
6315 unsigned long eip = kvm_get_linear_rip(vcpu);
6316 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6317 vcpu->arch.guest_debug_dr7,
6318 vcpu->arch.eff_db);
6319
6320 if (dr6 != 0) {
6f43ed01 6321 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6322 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6323 kvm_run->debug.arch.exception = DB_VECTOR;
6324 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6325 *r = EMULATE_USER_EXIT;
6326 return true;
6327 }
6328 }
6329
4161a569
NA		 6330 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6331 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6332 unsigned long eip = kvm_get_linear_rip(vcpu);
6333 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6334 vcpu->arch.dr7,
6335 vcpu->arch.db);
6336
6337 if (dr6 != 0) {
6338 vcpu->arch.dr6 &= ~15;
6f43ed01 6339 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6340 kvm_queue_exception(vcpu, DB_VECTOR);
6341 *r = EMULATE_DONE;
6342 return true;
6343 }
6344 }
6345
6346 return false;
6347}
6348
04789b66
LA		 6349static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6350{
2d7921c4
AM		 6351 switch (ctxt->opcode_len) {
6352 case 1:
6353 switch (ctxt->b) {
6354 case 0xe4: /* IN */
6355 case 0xe5:
6356 case 0xec:
6357 case 0xed:
6358 case 0xe6: /* OUT */
6359 case 0xe7:
6360 case 0xee:
6361 case 0xef:
6362 case 0x6c: /* INS */
6363 case 0x6d:
6364 case 0x6e: /* OUTS */
6365 case 0x6f:
6366 return true;
6367 }
6368 break;
6369 case 2:
6370 switch (ctxt->b) {
6371 case 0x33: /* RDPMC */
6372 return true;
6373 }
6374 break;
04789b66
LA		 6375 }
6376
6377 return false;
6378}
6379
51d8b661
AP		 6380int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6381 unsigned long cr2,
dc25e89e
AP		 6382 int emulation_type,
6383 void *insn,
6384 int insn_len)
bbd9b64e 6385{
95cb2295 6386 int r;
9d74191a 6387 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6388 bool writeback = true;
93c05d3e 6389 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6390
c595ceee
PB		 6391 vcpu->arch.l1tf_flush_l1d = true;
6392
93c05d3e
XG		 6393 /*
6394 * Clear write_fault_to_shadow_pgtable here to ensure it is
6395 * never reused.
6396 */
6397 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6398 kvm_clear_exception_queue(vcpu);
8d7d8102 6399
571008da 6400 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6401 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6402
6403 /*
6404 * We will reenter on the same instruction since
6405 * we do not set complete_userspace_io. This does not
6406 * handle watchpoints yet, those would be handled in
6407 * the emulate_ops.
6408 */
d391f120
VK		 6409 if (!(emulation_type & EMULTYPE_SKIP) &&
6410 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6411 return r;
6412
9d74191a
TY		 6413 ctxt->interruptibility = 0;
6414 ctxt->have_exception = false;
e0ad0b47 6415 ctxt->exception.vector = -1;
9d74191a 6416 ctxt->perm_ok = false;
bbd9b64e 6417
b51e974f 6418 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6419
9d74191a 6420 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6421
e46479f8 6422 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6423 ++vcpu->stat.insn_emulation;
1d2887e2 6424 if (r != EMULATION_OK) {
4005996e
AK		 6425 if (emulation_type & EMULTYPE_TRAP_UD)
6426 return EMULATE_FAIL;
991eebf9
GN		 6427 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6428 emulation_type))
bbd9b64e 6429 return EMULATE_DONE;
6ea6e843
PB		 6430 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6431 return EMULATE_DONE;
6d77dbfc
GN		 6432 if (emulation_type & EMULTYPE_SKIP)
6433 return EMULATE_FAIL;
e2366171 6434 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6435 }
6436 }
6437
04789b66
LA		 6438 if ((emulation_type & EMULTYPE_VMWARE) &&
6439 !is_vmware_backdoor_opcode(ctxt))
6440 return EMULATE_FAIL;
6441
ba8afb6b 6442 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6443 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6444 if (ctxt->eflags & X86_EFLAGS_RF)
6445 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6446 return EMULATE_DONE;
6447 }
6448
1cb3f3ae
XG		 6449 if (retry_instruction(ctxt, cr2, emulation_type))
6450 return EMULATE_DONE;
6451
7ae441ea 6452 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6453 changes registers values during IO operation */
7ae441ea
GN		 6454 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6455 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6456 emulator_invalidate_register_cache(ctxt);
7ae441ea 6457 }
4d2179e1 6458
5cd21917 6459restart:
0f89b207
TL		 6460 /* Save the faulting GPA (cr2) in the address field */
6461 ctxt->exception.address = cr2;
6462
9d74191a 6463 r = x86_emulate_insn(ctxt);
bbd9b64e 6464
775fde86
JR		 6465 if (r == EMULATION_INTERCEPTED)
6466 return EMULATE_DONE;
6467
d2ddd1c4 6468 if (r == EMULATION_FAILED) {
991eebf9
GN		 6469 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6470 emulation_type))
c3cd7ffa
GN		 6471 return EMULATE_DONE;
6472
e2366171 6473 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6474 }
6475
9d74191a 6476 if (ctxt->have_exception) {
d2ddd1c4 6477 r = EMULATE_DONE;
ef54bcfe
PB		 6478 if (inject_emulated_exception(vcpu))
6479 return r;
d2ddd1c4 6480 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6481 if (!vcpu->arch.pio.in) {
6482 /* FIXME: return into emulator if single-stepping. */
3457e419 6483 vcpu->arch.pio.count = 0;
0912c977 6484 } else {
7ae441ea 6485 writeback = false;
716d51ab
GN		 6486 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6487 }
ac0a48c3 6488 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6489 } else if (vcpu->mmio_needed) {
6490 if (!vcpu->mmio_is_write)
6491 writeback = false;
ac0a48c3 6492 r = EMULATE_USER_EXIT;
716d51ab 6493 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6494 } else if (r == EMULATION_RESTART)
5cd21917 6495 goto restart;
d2ddd1c4
GN		 6496 else
6497 r = EMULATE_DONE;
f850e2e6 6498
7ae441ea 6499 if (writeback) {
6addfc42 6500 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6501 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6502 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6503 kvm_rip_write(vcpu, ctxt->eip);
5cc244a2 6504 if (r == EMULATE_DONE && ctxt->tf)
c8401dda 6505 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6506 if (!ctxt->have_exception ||
6507 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6508 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6509
6510 /*
6511 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6512 * do nothing, and it will be requested again as soon as
6513 * the shadow expires. But we still need to check here,
6514 * because POPF has no interrupt shadow.
6515 */
6516 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6517 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6518 } else
6519 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6520
6521 return r;
de7d789a 6522}
c60658d1
SC		 6523
6524int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6525{
6526 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6527}
6528EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6529
6530int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6531 void *insn, int insn_len)
6532{
6533 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6534}
6535EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6536
45def77e
SC		 6537static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6538{
6539 vcpu->arch.pio.count = 0;
6540
6541 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6542 return 1;
6543
6544 return kvm_skip_emulated_instruction(vcpu);
6545}
6546
dca7f128
SC		 6547static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6548 unsigned short port)
de7d789a 6549{
cf8f70bf 6550 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6551 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6552 size, port, &val, 1);
45def77e
SC		 6553
6554 if (!ret) {
6555 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6556 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6557 }
de7d789a
CO		 6558 return ret;
6559}
de7d789a 6560
8370c3d0
TL		 6561static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6562{
6563 unsigned long val;
6564
6565 /* We should only ever be called with arch.pio.count equal to 1 */
6566 BUG_ON(vcpu->arch.pio.count != 1);
6567
45def77e
SC		 6568 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6569 vcpu->arch.pio.count = 0;
6570 return 1;
6571 }
6572
8370c3d0
TL		 6573 /* For size less than 4 we merge, else we zero extend */
6574 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6575 : 0;
6576
6577 /*
6578 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6579 * the copy and tracing
6580 */
6581 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6582 vcpu->arch.pio.port, &val, 1);
6583 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6584
45def77e 6585 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6586}
6587
dca7f128
SC		 6588static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6589 unsigned short port)
8370c3d0
TL		 6590{
6591 unsigned long val;
6592 int ret;
6593
6594 /* For size less than 4 we merge, else we zero extend */
6595 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6596
6597 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6598 &val, 1);
6599 if (ret) {
6600 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6601 return ret;
6602 }
6603
45def77e 6604 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6605 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6606
6607 return 0;
6608}
dca7f128
SC		 6609
6610int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6611{
45def77e 6612 int ret;
dca7f128 6613
dca7f128 6614 if (in)
45def77e 6615 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6616 else
45def77e
SC		 6617 ret = kvm_fast_pio_out(vcpu, size, port);
6618 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 6619}
6620EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6621
251a5fd6 6622static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6623{
0a3aee0d 6624 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6625 return 0;
8cfdc000
ZA		 6626}
6627
6628static void tsc_khz_changed(void *data)
c8076604 6629{
8cfdc000
ZA		 6630 struct cpufreq_freqs *freq = data;
6631 unsigned long khz = 0;
6632
6633 if (data)
6634 khz = freq->new;
6635 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6636 khz = cpufreq_quick_get(raw_smp_processor_id());
6637 if (!khz)
6638 khz = tsc_khz;
0a3aee0d 6639 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6640}
6641
5fa4ec9c 6642#ifdef CONFIG_X86_64
0092e434
VK		 6643static void kvm_hyperv_tsc_notifier(void)
6644{
0092e434
VK		 6645 struct kvm *kvm;
6646 struct kvm_vcpu *vcpu;
6647 int cpu;
6648
6649 spin_lock(&kvm_lock);
6650 list_for_each_entry(kvm, &vm_list, vm_list)
6651 kvm_make_mclock_inprogress_request(kvm);
6652
6653 hyperv_stop_tsc_emulation();
6654
6655 /* TSC frequency always matches when on Hyper-V */
6656 for_each_present_cpu(cpu)
6657 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6658 kvm_max_guest_tsc_khz = tsc_khz;
6659
6660 list_for_each_entry(kvm, &vm_list, vm_list) {
6661 struct kvm_arch *ka = &kvm->arch;
6662
6663 spin_lock(&ka->pvclock_gtod_sync_lock);
6664
6665 pvclock_update_vm_gtod_copy(kvm);
6666
6667 kvm_for_each_vcpu(cpu, vcpu, kvm)
6668 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6669
6670 kvm_for_each_vcpu(cpu, vcpu, kvm)
6671 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6672
6673 spin_unlock(&ka->pvclock_gtod_sync_lock);
6674 }
6675 spin_unlock(&kvm_lock);
0092e434 6676}
5fa4ec9c 6677#endif
0092e434 6678
c8076604
GH		 6679static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6680 void *data)
6681{
6682 struct cpufreq_freqs *freq = data;
6683 struct kvm *kvm;
6684 struct kvm_vcpu *vcpu;
6685 int i, send_ipi = 0;
6686
8cfdc000
ZA		 6687 /*
6688 * We allow guests to temporarily run on slowing clocks,
6689 * provided we notify them after, or to run on accelerating
6690 * clocks, provided we notify them before. Thus time never
6691 * goes backwards.
6692 *
6693 * However, we have a problem. We can't atomically update
6694 * the frequency of a given CPU from this function; it is
6695 * merely a notifier, which can be called from any CPU.
6696 * Changing the TSC frequency at arbitrary points in time
6697 * requires a recomputation of local variables related to
6698 * the TSC for each VCPU. We must flag these local variables
6699 * to be updated and be sure the update takes place with the
6700 * new frequency before any guests proceed.
6701 *
6702 * Unfortunately, the combination of hotplug CPU and frequency
6703 * change creates an intractable locking scenario; the order
6704 * of when these callouts happen is undefined with respect to
6705 * CPU hotplug, and they can race with each other. As such,
6706 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6707 * undefined; you can actually have a CPU frequency change take
6708 * place in between the computation of X and the setting of the
6709 * variable. To protect against this problem, all updates of
6710 * the per_cpu tsc_khz variable are done in an interrupt
6711 * protected IPI, and all callers wishing to update the value
6712 * must wait for a synchronous IPI to complete (which is trivial
6713 * if the caller is on the CPU already). This establishes the
6714 * necessary total order on variable updates.
6715 *
6716 * Note that because a guest time update may take place
6717 * anytime after the setting of the VCPU's request bit, the
6718 * correct TSC value must be set before the request. However,
6719 * to ensure the update actually makes it to any guest which
6720 * starts running in hardware virtualization between the set
6721 * and the acquisition of the spinlock, we must also ping the
6722 * CPU after setting the request bit.
6723 *
6724 */
6725
c8076604
GH		 6726 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6727 return 0;
6728 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6729 return 0;
8cfdc000
ZA		 6730
6731 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6732
2f303b74 6733 spin_lock(&kvm_lock);
c8076604 6734 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6735 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6736 if (vcpu->cpu != freq->cpu)
6737 continue;
c285545f 6738 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6739 if (vcpu->cpu != smp_processor_id())
8cfdc000 6740 send_ipi = 1;
c8076604
GH		 6741 }
6742 }
2f303b74 6743 spin_unlock(&kvm_lock);
c8076604
GH		 6744
6745 if (freq->old < freq->new && send_ipi) {
6746 /*
6747 * We upscale the frequency. Must make the guest
6748 * doesn't see old kvmclock values while running with
6749 * the new frequency, otherwise we risk the guest sees
6750 * time go backwards.
6751 *
6752 * In case we update the frequency for another cpu
6753 * (which might be in guest context) send an interrupt
6754 * to kick the cpu out of guest context. Next time
6755 * guest context is entered kvmclock will be updated,
6756 * so the guest will not see stale values.
6757 */
8cfdc000 6758 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6759 }
6760 return 0;
6761}
6762
6763static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6764 .notifier_call = kvmclock_cpufreq_notifier
6765};
6766
251a5fd6 6767static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6768{
251a5fd6
SAS		 6769 tsc_khz_changed(NULL);
6770 return 0;
8cfdc000
ZA		 6771}
6772
b820cc0c
ZA		 6773static void kvm_timer_init(void)
6774{
c285545f 6775 max_tsc_khz = tsc_khz;
460dd42e 6776
b820cc0c 6777 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6778#ifdef CONFIG_CPU_FREQ
6779 struct cpufreq_policy policy;
758f588d
BP		 6780 int cpu;
6781
c285545f 6782 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6783 cpu = get_cpu();
6784 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6785 if (policy.cpuinfo.max_freq)
6786 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6787 put_cpu();
c285545f 6788#endif
b820cc0c
ZA		 6789 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6790 CPUFREQ_TRANSITION_NOTIFIER);
6791 }
c285545f 6792 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6793
73c1b41e 6794 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6795 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6796}
6797
dd60d217
AK		 6798DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6799EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6800
f5132b01 6801int kvm_is_in_guest(void)
ff9d07a0 6802{
086c9855 6803 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6804}
6805
6806static int kvm_is_user_mode(void)
6807{
6808 int user_mode = 3;
dcf46b94 6809
086c9855
AS		 6810 if (__this_cpu_read(current_vcpu))
6811 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6812
ff9d07a0
ZY		 6813 return user_mode != 0;
6814}
6815
6816static unsigned long kvm_get_guest_ip(void)
6817{
6818 unsigned long ip = 0;
dcf46b94 6819
086c9855
AS		 6820 if (__this_cpu_read(current_vcpu))
6821 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6822
ff9d07a0
ZY		 6823 return ip;
6824}
6825
6826static struct perf_guest_info_callbacks kvm_guest_cbs = {
6827 .is_in_guest = kvm_is_in_guest,
6828 .is_user_mode = kvm_is_user_mode,
6829 .get_guest_ip = kvm_get_guest_ip,
6830};
6831
ce88decf
XG		 6832static void kvm_set_mmio_spte_mask(void)
6833{
6834 u64 mask;
6835 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6836
6837 /*
6838 * Set the reserved bits and the present bit of an paging-structure
6839 * entry to generate page fault with PFER.RSV = 1.
6840 */
28a1f3ac
JS		 6841
6842 /*
6843 * Mask the uppermost physical address bit, which would be reserved as
6844 * long as the supported physical address width is less than 52.
6845 */
6846 mask = 1ull << 51;
885032b9 6847
885032b9 6848 /* Set the present bit. */
ce88decf
XG		 6849 mask |= 1ull;
6850
ce88decf
XG		 6851 /*
6852 * If reserved bit is not supported, clear the present bit to disable
6853 * mmio page fault.
6854 */
7288bde1 6855 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
ce88decf 6856 mask &= ~1ull;
ce88decf 6857
dcdca5fe 6858 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6859}
6860
16e8d74d
MT		 6861#ifdef CONFIG_X86_64
6862static void pvclock_gtod_update_fn(struct work_struct *work)
6863{
d828199e
MT		 6864 struct kvm *kvm;
6865
6866 struct kvm_vcpu *vcpu;
6867 int i;
6868
2f303b74 6869 spin_lock(&kvm_lock);
d828199e
MT		 6870 list_for_each_entry(kvm, &vm_list, vm_list)
6871 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6872 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6873 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6874 spin_unlock(&kvm_lock);
16e8d74d
MT		 6875}
6876
6877static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6878
6879/*
6880 * Notification about pvclock gtod data update.
6881 */
6882static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6883 void *priv)
6884{
6885 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6886 struct timekeeper *tk = priv;
6887
6888 update_pvclock_gtod(tk);
6889
6890 /* disable master clock if host does not trust, or does not
b0c39dc6 6891 * use, TSC based clocksource.
16e8d74d 6892 */
b0c39dc6 6893 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6894 atomic_read(&kvm_guest_has_master_clock) != 0)
6895 queue_work(system_long_wq, &pvclock_gtod_work);
6896
6897 return 0;
6898}
6899
6900static struct notifier_block pvclock_gtod_notifier = {
6901 .notifier_call = pvclock_gtod_notify,
6902};
6903#endif
6904
f8c16bba 6905int kvm_arch_init(void *opaque)
043405e1 6906{
b820cc0c 6907 int r;
6b61edf7 6908 struct kvm_x86_ops *ops = opaque;
f8c16bba 6909
f8c16bba
ZX		 6910 if (kvm_x86_ops) {
6911 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6912 r = -EEXIST;
6913 goto out;
f8c16bba
ZX		 6914 }
6915
6916 if (!ops->cpu_has_kvm_support()) {
6917 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6918 r = -EOPNOTSUPP;
6919 goto out;
f8c16bba
ZX		 6920 }
6921 if (ops->disabled_by_bios()) {
6922 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6923 r = -EOPNOTSUPP;
6924 goto out;
f8c16bba
ZX		 6925 }
6926
b666a4b6
MO		 6927 /*
6928 * KVM explicitly assumes that the guest has an FPU and
6929 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
6930 * vCPU's FPU state as a fxregs_state struct.
6931 */
6932 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
6933 printk(KERN_ERR "kvm: inadequate fpu\n");
6934 r = -EOPNOTSUPP;
6935 goto out;
6936 }
6937
013f6a5d 6938 r = -ENOMEM;
ed8e4812 6939 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 6940 __alignof__(struct fpu), SLAB_ACCOUNT,
6941 NULL);
6942 if (!x86_fpu_cache) {
6943 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
6944 goto out;
6945 }
6946
013f6a5d
MT		 6947 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6948 if (!shared_msrs) {
6949 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 6950 goto out_free_x86_fpu_cache;
013f6a5d
MT		 6951 }
6952
97db56ce
AK		 6953 r = kvm_mmu_module_init();
6954 if (r)
013f6a5d 6955 goto out_free_percpu;
97db56ce 6956
ce88decf 6957 kvm_set_mmio_spte_mask();
97db56ce 6958
f8c16bba 6959 kvm_x86_ops = ops;
920c8377 6960
7b52345e 6961 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6962 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6963 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6964 kvm_timer_init();
c8076604 6965
ff9d07a0
ZY		 6966 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6967
d366bf7e 6968 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6969 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6970
c5cc421b 6971 kvm_lapic_init();
16e8d74d
MT		 6972#ifdef CONFIG_X86_64
6973 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6974
5fa4ec9c 6975 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6976 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6977#endif
6978
f8c16bba 6979 return 0;
56c6d28a 6980
013f6a5d
MT		 6981out_free_percpu:
6982 free_percpu(shared_msrs);
b666a4b6
MO		 6983out_free_x86_fpu_cache:
6984 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 6985out:
56c6d28a 6986 return r;
043405e1 6987}
8776e519 6988
f8c16bba
ZX		 6989void kvm_arch_exit(void)
6990{
0092e434 6991#ifdef CONFIG_X86_64
5fa4ec9c 6992 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6993 clear_hv_tscchange_cb();
6994#endif
cef84c30 6995 kvm_lapic_exit();
ff9d07a0
ZY		 6996 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6997
888d256e
JK		 6998 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6999 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7000 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7001 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7002#ifdef CONFIG_X86_64
7003 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7004#endif
f8c16bba 7005 kvm_x86_ops = NULL;
56c6d28a 7006 kvm_mmu_module_exit();
013f6a5d 7007 free_percpu(shared_msrs);
b666a4b6 7008 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7009}
f8c16bba 7010
5cb56059 7011int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7012{
7013 ++vcpu->stat.halt_exits;
35754c98 7014 if (lapic_in_kernel(vcpu)) {
a4535290 7015 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7016 return 1;
7017 } else {
7018 vcpu->run->exit_reason = KVM_EXIT_HLT;
7019 return 0;
7020 }
7021}
5cb56059
JS		 7022EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7023
7024int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7025{
6affcbed
KH		 7026 int ret = kvm_skip_emulated_instruction(vcpu);
7027 /*
7028 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7029 * KVM_EXIT_DEBUG here.
7030 */
7031 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7032}
8776e519
HB		 7033EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7034
8ef81a9a 7035#ifdef CONFIG_X86_64
55dd00a7
MT		 7036static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7037 unsigned long clock_type)
7038{
7039 struct kvm_clock_pairing clock_pairing;
899a31f5 7040 struct timespec64 ts;
80fbd89c 7041 u64 cycle;
55dd00a7
MT		 7042 int ret;
7043
7044 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7045 return -KVM_EOPNOTSUPP;
7046
7047 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7048 return -KVM_EOPNOTSUPP;
7049
7050 clock_pairing.sec = ts.tv_sec;
7051 clock_pairing.nsec = ts.tv_nsec;
7052 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7053 clock_pairing.flags = 0;
bcbfbd8e 7054 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7055
7056 ret = 0;
7057 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7058 sizeof(struct kvm_clock_pairing)))
7059 ret = -KVM_EFAULT;
7060
7061 return ret;
7062}
8ef81a9a 7063#endif
55dd00a7 7064
6aef266c
SV		 7065/*
7066 * kvm_pv_kick_cpu_op: Kick a vcpu.
7067 *
7068 * @apicid - apicid of vcpu to be kicked.
7069 */
7070static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7071{
24d2166b 7072 struct kvm_lapic_irq lapic_irq;
6aef266c 7073
24d2166b
R		 7074 lapic_irq.shorthand = 0;
7075 lapic_irq.dest_mode = 0;
ebd28fcb 7076 lapic_irq.level = 0;
24d2166b 7077 lapic_irq.dest_id = apicid;
93bbf0b8 7078 lapic_irq.msi_redir_hint = false;
6aef266c 7079
24d2166b 7080 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7081 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7082}
7083
d62caabb
AS		 7084void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7085{
f7589cca
PB		 7086 if (!lapic_in_kernel(vcpu)) {
7087 WARN_ON_ONCE(vcpu->arch.apicv_active);
7088 return;
7089 }
7090 if (!vcpu->arch.apicv_active)
7091 return;
7092
d62caabb
AS		 7093 vcpu->arch.apicv_active = false;
7094 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7095}
7096
8776e519
HB		 7097int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7098{
7099 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7100 int op_64_bit;
8776e519 7101
696ca779
RK		 7102 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7103 return kvm_hv_hypercall(vcpu);
55cd8e5a 7104
5fdbf976
MT		 7105 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
7106 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
7107 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
7108 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
7109 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 7110
229456fc 7111 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7112
a449c7aa
NA		 7113 op_64_bit = is_64_bit_mode(vcpu);
7114 if (!op_64_bit) {
8776e519
HB		 7115 nr &= 0xFFFFFFFF;
7116 a0 &= 0xFFFFFFFF;
7117 a1 &= 0xFFFFFFFF;
7118 a2 &= 0xFFFFFFFF;
7119 a3 &= 0xFFFFFFFF;
7120 }
7121
07708c4a
JK		 7122 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7123 ret = -KVM_EPERM;
696ca779 7124 goto out;
07708c4a
JK		 7125 }
7126
8776e519 7127 switch (nr) {
b93463aa
AK		 7128 case KVM_HC_VAPIC_POLL_IRQ:
7129 ret = 0;
7130 break;
6aef266c
SV		 7131 case KVM_HC_KICK_CPU:
7132 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7133 ret = 0;
7134 break;
8ef81a9a 7135#ifdef CONFIG_X86_64
55dd00a7
MT		 7136 case KVM_HC_CLOCK_PAIRING:
7137 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7138 break;
1ed199a4 7139#endif
4180bf1b
WL		 7140 case KVM_HC_SEND_IPI:
7141 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7142 break;
8776e519
HB		 7143 default:
7144 ret = -KVM_ENOSYS;
7145 break;
7146 }
696ca779 7147out:
a449c7aa
NA		 7148 if (!op_64_bit)
7149 ret = (u32)ret;
5fdbf976 7150 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 7151
f11c3a8d 7152 ++vcpu->stat.hypercalls;
6356ee0c 7153 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7154}
7155EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7156
b6785def 7157static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7158{
d6aa1000 7159 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7160 char instruction[3];
5fdbf976 7161 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7162
8776e519 7163 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7164
ce2e852e
DV		 7165 return emulator_write_emulated(ctxt, rip, instruction, 3,
7166 &ctxt->exception);
8776e519
HB		 7167}
7168
851ba692 7169static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7170{
782d422b
MG		 7171 return vcpu->run->request_interrupt_window &&
7172 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7173}
7174
851ba692 7175static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7176{
851ba692
AK		 7177 struct kvm_run *kvm_run = vcpu->run;
7178
91586a3b 7179 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7180 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7181 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7182 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7183 kvm_run->ready_for_interrupt_injection =
7184 pic_in_kernel(vcpu->kvm) ||
782d422b 7185 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7186}
7187
95ba8273
GN		 7188static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7189{
7190 int max_irr, tpr;
7191
7192 if (!kvm_x86_ops->update_cr8_intercept)
7193 return;
7194
bce87cce 7195 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7196 return;
7197
d62caabb
AS		 7198 if (vcpu->arch.apicv_active)
7199 return;
7200
8db3baa2
GN		 7201 if (!vcpu->arch.apic->vapic_addr)
7202 max_irr = kvm_lapic_find_highest_irr(vcpu);
7203 else
7204 max_irr = -1;
95ba8273
GN		 7205
7206 if (max_irr != -1)
7207 max_irr >>= 4;
7208
7209 tpr = kvm_lapic_get_cr8(vcpu);
7210
7211 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7212}
7213
b6b8a145 7214static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7215{
b6b8a145
JK		 7216 int r;
7217
95ba8273 7218 /* try to reinject previous events if any */
664f8e26 7219
1a680e35
LA		 7220 if (vcpu->arch.exception.injected)
7221 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7222 /*
a042c26f
LA		 7223 * Do not inject an NMI or interrupt if there is a pending
7224 * exception. Exceptions and interrupts are recognized at
7225 * instruction boundaries, i.e. the start of an instruction.
7226 * Trap-like exceptions, e.g. #DB, have higher priority than
7227 * NMIs and interrupts, i.e. traps are recognized before an
7228 * NMI/interrupt that's pending on the same instruction.
7229 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7230 * priority, but are only generated (pended) during instruction
7231 * execution, i.e. a pending fault-like exception means the
7232 * fault occurred on the *previous* instruction and must be
7233 * serviced prior to recognizing any new events in order to
7234 * fully complete the previous instruction.
664f8e26 7235 */
1a680e35
LA		 7236 else if (!vcpu->arch.exception.pending) {
7237 if (vcpu->arch.nmi_injected)
664f8e26 7238 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7239 else if (vcpu->arch.interrupt.injected)
664f8e26 7240 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7241 }
7242
1a680e35
LA		 7243 /*
7244 * Call check_nested_events() even if we reinjected a previous event
7245 * in order for caller to determine if it should require immediate-exit
7246 * from L2 to L1 due to pending L1 events which require exit
7247 * from L2 to L1.
7248 */
664f8e26
WL		 7249 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7250 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7251 if (r != 0)
7252 return r;
7253 }
7254
7255 /* try to inject new event if pending */
b59bb7bd 7256 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7257 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7258 vcpu->arch.exception.has_error_code,
7259 vcpu->arch.exception.error_code);
d6e8c854 7260
1a680e35 7261 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7262 vcpu->arch.exception.pending = false;
7263 vcpu->arch.exception.injected = true;
7264
d6e8c854
NA		 7265 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7266 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7267 X86_EFLAGS_RF);
7268
f10c729f
JM		 7269 if (vcpu->arch.exception.nr == DB_VECTOR) {
7270 /*
7271 * This code assumes that nSVM doesn't use
7272 * check_nested_events(). If it does, the
7273 * DR6/DR7 changes should happen before L1
7274 * gets a #VMEXIT for an intercepted #DB in
7275 * L2. (Under VMX, on the other hand, the
7276 * DR6/DR7 changes should not happen in the
7277 * event of a VM-exit to L1 for an intercepted
7278 * #DB in L2.)
7279 */
7280 kvm_deliver_exception_payload(vcpu);
7281 if (vcpu->arch.dr7 & DR7_GD) {
7282 vcpu->arch.dr7 &= ~DR7_GD;
7283 kvm_update_dr7(vcpu);
7284 }
6bdf0662
NA		 7285 }
7286
cfcd20e5 7287 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7288 }
7289
7290 /* Don't consider new event if we re-injected an event */
7291 if (kvm_event_needs_reinjection(vcpu))
7292 return 0;
7293
7294 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7295 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7296 vcpu->arch.smi_pending = false;
52797bf9 7297 ++vcpu->arch.smi_count;
ee2cd4b7 7298 enter_smm(vcpu);
c43203ca 7299 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7300 --vcpu->arch.nmi_pending;
7301 vcpu->arch.nmi_injected = true;
7302 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7303 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7304 /*
7305 * Because interrupts can be injected asynchronously, we are
7306 * calling check_nested_events again here to avoid a race condition.
7307 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7308 * proposal and current concerns. Perhaps we should be setting
7309 * KVM_REQ_EVENT only on certain events and not unconditionally?
7310 */
7311 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7312 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7313 if (r != 0)
7314 return r;
7315 }
95ba8273 7316 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7317 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7318 false);
7319 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7320 }
7321 }
ee2cd4b7 7322
b6b8a145 7323 return 0;
95ba8273
GN		 7324}
7325
7460fb4a
AK		 7326static void process_nmi(struct kvm_vcpu *vcpu)
7327{
7328 unsigned limit = 2;
7329
7330 /*
7331 * x86 is limited to one NMI running, and one NMI pending after it.
7332 * If an NMI is already in progress, limit further NMIs to just one.
7333 * Otherwise, allow two (and we'll inject the first one immediately).
7334 */
7335 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7336 limit = 1;
7337
7338 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7339 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7340 kvm_make_request(KVM_REQ_EVENT, vcpu);
7341}
7342
ee2cd4b7 7343static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7344{
7345 u32 flags = 0;
7346 flags |= seg->g << 23;
7347 flags |= seg->db << 22;
7348 flags |= seg->l << 21;
7349 flags |= seg->avl << 20;
7350 flags |= seg->present << 15;
7351 flags |= seg->dpl << 13;
7352 flags |= seg->s << 12;
7353 flags |= seg->type << 8;
7354 return flags;
7355}
7356
ee2cd4b7 7357static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7358{
7359 struct kvm_segment seg;
7360 int offset;
7361
7362 kvm_get_segment(vcpu, &seg, n);
7363 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7364
7365 if (n < 3)
7366 offset = 0x7f84 + n * 12;
7367 else
7368 offset = 0x7f2c + (n - 3) * 12;
7369
7370 put_smstate(u32, buf, offset + 8, seg.base);
7371 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7372 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7373}
7374
efbb288a 7375#ifdef CONFIG_X86_64
ee2cd4b7 7376static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7377{
7378 struct kvm_segment seg;
7379 int offset;
7380 u16 flags;
7381
7382 kvm_get_segment(vcpu, &seg, n);
7383 offset = 0x7e00 + n * 16;
7384
ee2cd4b7 7385 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7386 put_smstate(u16, buf, offset, seg.selector);
7387 put_smstate(u16, buf, offset + 2, flags);
7388 put_smstate(u32, buf, offset + 4, seg.limit);
7389 put_smstate(u64, buf, offset + 8, seg.base);
7390}
efbb288a 7391#endif
660a5d51 7392
ee2cd4b7 7393static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7394{
7395 struct desc_ptr dt;
7396 struct kvm_segment seg;
7397 unsigned long val;
7398 int i;
7399
7400 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7401 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7402 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7403 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7404
7405 for (i = 0; i < 8; i++)
7406 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7407
7408 kvm_get_dr(vcpu, 6, &val);
7409 put_smstate(u32, buf, 0x7fcc, (u32)val);
7410 kvm_get_dr(vcpu, 7, &val);
7411 put_smstate(u32, buf, 0x7fc8, (u32)val);
7412
7413 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7414 put_smstate(u32, buf, 0x7fc4, seg.selector);
7415 put_smstate(u32, buf, 0x7f64, seg.base);
7416 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7417 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7418
7419 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7420 put_smstate(u32, buf, 0x7fc0, seg.selector);
7421 put_smstate(u32, buf, 0x7f80, seg.base);
7422 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7423 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7424
7425 kvm_x86_ops->get_gdt(vcpu, &dt);
7426 put_smstate(u32, buf, 0x7f74, dt.address);
7427 put_smstate(u32, buf, 0x7f70, dt.size);
7428
7429 kvm_x86_ops->get_idt(vcpu, &dt);
7430 put_smstate(u32, buf, 0x7f58, dt.address);
7431 put_smstate(u32, buf, 0x7f54, dt.size);
7432
7433 for (i = 0; i < 6; i++)
ee2cd4b7 7434 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7435
7436 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7437
7438 /* revision id */
7439 put_smstate(u32, buf, 0x7efc, 0x00020000);
7440 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7441}
7442
b68f3cc7 7443#ifdef CONFIG_X86_64
ee2cd4b7 7444static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7445{
660a5d51
PB		 7446 struct desc_ptr dt;
7447 struct kvm_segment seg;
7448 unsigned long val;
7449 int i;
7450
7451 for (i = 0; i < 16; i++)
7452 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7453
7454 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7455 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7456
7457 kvm_get_dr(vcpu, 6, &val);
7458 put_smstate(u64, buf, 0x7f68, val);
7459 kvm_get_dr(vcpu, 7, &val);
7460 put_smstate(u64, buf, 0x7f60, val);
7461
7462 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7463 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7464 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7465
7466 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7467
7468 /* revision id */
7469 put_smstate(u32, buf, 0x7efc, 0x00020064);
7470
7471 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7472
7473 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7474 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7475 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7476 put_smstate(u32, buf, 0x7e94, seg.limit);
7477 put_smstate(u64, buf, 0x7e98, seg.base);
7478
7479 kvm_x86_ops->get_idt(vcpu, &dt);
7480 put_smstate(u32, buf, 0x7e84, dt.size);
7481 put_smstate(u64, buf, 0x7e88, dt.address);
7482
7483 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7484 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7485 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7486 put_smstate(u32, buf, 0x7e74, seg.limit);
7487 put_smstate(u64, buf, 0x7e78, seg.base);
7488
7489 kvm_x86_ops->get_gdt(vcpu, &dt);
7490 put_smstate(u32, buf, 0x7e64, dt.size);
7491 put_smstate(u64, buf, 0x7e68, dt.address);
7492
7493 for (i = 0; i < 6; i++)
ee2cd4b7 7494 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7495}
b68f3cc7 7496#endif
660a5d51 7497
ee2cd4b7 7498static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7499{
660a5d51 7500 struct kvm_segment cs, ds;
18c3626e 7501 struct desc_ptr dt;
660a5d51
PB		 7502 char buf[512];
7503 u32 cr0;
7504
660a5d51 7505 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7506 memset(buf, 0, 512);
b68f3cc7 7507#ifdef CONFIG_X86_64
d6321d49 7508 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7509 enter_smm_save_state_64(vcpu, buf);
660a5d51 7510 else
b68f3cc7 7511#endif
ee2cd4b7 7512 enter_smm_save_state_32(vcpu, buf);
660a5d51 7513
0234bf88
LP		 7514 /*
7515 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7516 * vCPU state (e.g. leave guest mode) after we've saved the state into
7517 * the SMM state-save area.
7518 */
7519 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7520
7521 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7522 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7523
7524 if (kvm_x86_ops->get_nmi_mask(vcpu))
7525 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7526 else
7527 kvm_x86_ops->set_nmi_mask(vcpu, true);
7528
7529 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7530 kvm_rip_write(vcpu, 0x8000);
7531
7532 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7533 kvm_x86_ops->set_cr0(vcpu, cr0);
7534 vcpu->arch.cr0 = cr0;
7535
7536 kvm_x86_ops->set_cr4(vcpu, 0);
7537
18c3626e
PB		 7538 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7539 dt.address = dt.size = 0;
7540 kvm_x86_ops->set_idt(vcpu, &dt);
7541
660a5d51
PB		 7542 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7543
7544 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7545 cs.base = vcpu->arch.smbase;
7546
7547 ds.selector = 0;
7548 ds.base = 0;
7549
7550 cs.limit = ds.limit = 0xffffffff;
7551 cs.type = ds.type = 0x3;
7552 cs.dpl = ds.dpl = 0;
7553 cs.db = ds.db = 0;
7554 cs.s = ds.s = 1;
7555 cs.l = ds.l = 0;
7556 cs.g = ds.g = 1;
7557 cs.avl = ds.avl = 0;
7558 cs.present = ds.present = 1;
7559 cs.unusable = ds.unusable = 0;
7560 cs.padding = ds.padding = 0;
7561
7562 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7563 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7564 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7565 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7566 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7567 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7568
b68f3cc7 7569#ifdef CONFIG_X86_64
d6321d49 7570 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7571 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7572#endif
660a5d51
PB		 7573
7574 kvm_update_cpuid(vcpu);
7575 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7576}
7577
ee2cd4b7 7578static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7579{
7580 vcpu->arch.smi_pending = true;
7581 kvm_make_request(KVM_REQ_EVENT, vcpu);
7582}
7583
2860c4b1
PB		 7584void kvm_make_scan_ioapic_request(struct kvm *kvm)
7585{
7586 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7587}
7588
3d81bc7e 7589static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7590{
dcbd3e49 7591 if (!kvm_apic_present(vcpu))
3d81bc7e 7592 return;
c7c9c56c 7593
6308630b 7594 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7595
b053b2ae 7596 if (irqchip_split(vcpu->kvm))
6308630b 7597 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7598 else {
fa59cc00 7599 if (vcpu->arch.apicv_active)
d62caabb 7600 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7601 if (ioapic_in_kernel(vcpu->kvm))
7602 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7603 }
e40ff1d6
LA		 7604
7605 if (is_guest_mode(vcpu))
7606 vcpu->arch.load_eoi_exitmap_pending = true;
7607 else
7608 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7609}
7610
7611static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7612{
7613 u64 eoi_exit_bitmap[4];
7614
7615 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7616 return;
7617
5c919412
AS		 7618 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7619 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7620 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7621}
7622
93065ac7
MH		 7623int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7624 unsigned long start, unsigned long end,
7625 bool blockable)
b1394e74
RK		 7626{
7627 unsigned long apic_address;
7628
7629 /*
7630 * The physical address of apic access page is stored in the VMCS.
7631 * Update it when it becomes invalid.
7632 */
7633 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7634 if (start <= apic_address && apic_address < end)
7635 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7636
7637 return 0;
b1394e74
RK		 7638}
7639
4256f43f
TC		 7640void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7641{
c24ae0dc
TC		 7642 struct page *page = NULL;
7643
35754c98 7644 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7645 return;
7646
4256f43f
TC		 7647 if (!kvm_x86_ops->set_apic_access_page_addr)
7648 return;
7649
c24ae0dc 7650 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7651 if (is_error_page(page))
7652 return;
c24ae0dc
TC		 7653 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7654
7655 /*
7656 * Do not pin apic access page in memory, the MMU notifier
7657 * will call us again if it is migrated or swapped out.
7658 */
7659 put_page(page);
4256f43f
TC		 7660}
7661EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7662
d264ee0c
SC		 7663void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7664{
7665 smp_send_reschedule(vcpu->cpu);
7666}
7667EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7668
9357d939 7669/*
362c698f 7670 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7671 * exiting to the userspace. Otherwise, the value will be returned to the
7672 * userspace.
7673 */
851ba692 7674static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7675{
7676 int r;
62a193ed
MG		 7677 bool req_int_win =
7678 dm_request_for_irq_injection(vcpu) &&
7679 kvm_cpu_accept_dm_intr(vcpu);
7680
730dca42 7681 bool req_immediate_exit = false;
b6c7a5dc 7682
2fa6e1e1 7683 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7684 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7685 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7686 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7687 kvm_mmu_unload(vcpu);
a8eeb04a 7688 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7689 __kvm_migrate_timers(vcpu);
d828199e
MT		 7690 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7691 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7692 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7693 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7694 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7695 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7696 if (unlikely(r))
7697 goto out;
7698 }
a8eeb04a 7699 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7700 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7701 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7702 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7703 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7704 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7705 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7706 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7707 r = 0;
7708 goto out;
7709 }
a8eeb04a 7710 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7711 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7712 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7713 r = 0;
7714 goto out;
7715 }
af585b92
GN		 7716 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7717 /* Page is swapped out. Do synthetic halt */
7718 vcpu->arch.apf.halted = true;
7719 r = 1;
7720 goto out;
7721 }
c9aaa895
GC		 7722 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7723 record_steal_time(vcpu);
64d60670
PB		 7724 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7725 process_smi(vcpu);
7460fb4a
AK		 7726 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7727 process_nmi(vcpu);
f5132b01 7728 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7729 kvm_pmu_handle_event(vcpu);
f5132b01 7730 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7731 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7732 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7733 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7734 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7735 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7736 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7737 vcpu->run->eoi.vector =
7738 vcpu->arch.pending_ioapic_eoi;
7739 r = 0;
7740 goto out;
7741 }
7742 }
3d81bc7e
YZ		 7743 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7744 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7745 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7746 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7747 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7748 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7749 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7750 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7751 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7752 r = 0;
7753 goto out;
7754 }
e516cebb
AS		 7755 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7756 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7757 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7758 r = 0;
7759 goto out;
7760 }
db397571
AS		 7761 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7762 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7763 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7764 r = 0;
7765 goto out;
7766 }
f3b138c5
AS		 7767
7768 /*
7769 * KVM_REQ_HV_STIMER has to be processed after
7770 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7771 * depend on the guest clock being up-to-date
7772 */
1f4b34f8
AS		 7773 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7774 kvm_hv_process_stimers(vcpu);
2f52d58c 7775 }
b93463aa 7776
b463a6f7 7777 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7778 ++vcpu->stat.req_event;
66450a21
JK		 7779 kvm_apic_accept_events(vcpu);
7780 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7781 r = 1;
7782 goto out;
7783 }
7784
b6b8a145
JK		 7785 if (inject_pending_event(vcpu, req_int_win) != 0)
7786 req_immediate_exit = true;
321c5658 7787 else {
cc3d967f 7788 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7789 *
cc3d967f
LP		 7790 * SMIs have three cases:
7791 * 1) They can be nested, and then there is nothing to
7792 * do here because RSM will cause a vmexit anyway.
7793 * 2) There is an ISA-specific reason why SMI cannot be
7794 * injected, and the moment when this changes can be
7795 * intercepted.
7796 * 3) Or the SMI can be pending because
7797 * inject_pending_event has completed the injection
7798 * of an IRQ or NMI from the previous vmexit, and
7799 * then we request an immediate exit to inject the
7800 * SMI.
c43203ca
PB		 7801 */
7802 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7803 if (!kvm_x86_ops->enable_smi_window(vcpu))
7804 req_immediate_exit = true;
321c5658
YS		 7805 if (vcpu->arch.nmi_pending)
7806 kvm_x86_ops->enable_nmi_window(vcpu);
7807 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7808 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7809 WARN_ON(vcpu->arch.exception.pending);
321c5658 7810 }
b463a6f7
AK		 7811
7812 if (kvm_lapic_enabled(vcpu)) {
7813 update_cr8_intercept(vcpu);
7814 kvm_lapic_sync_to_vapic(vcpu);
7815 }
7816 }
7817
d8368af8
AK		 7818 r = kvm_mmu_reload(vcpu);
7819 if (unlikely(r)) {
d905c069 7820 goto cancel_injection;
d8368af8
AK		 7821 }
7822
b6c7a5dc
HB		 7823 preempt_disable();
7824
7825 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7826
7827 /*
7828 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7829 * IPI are then delayed after guest entry, which ensures that they
7830 * result in virtual interrupt delivery.
7831 */
7832 local_irq_disable();
6b7e2d09
XG		 7833 vcpu->mode = IN_GUEST_MODE;
7834
01b71917
MT		 7835 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7836
0f127d12 7837 /*
b95234c8 7838 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7839 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 7840 *
81b01667 7841 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 7842 * pairs with the memory barrier implicit in pi_test_and_set_on
7843 * (see vmx_deliver_posted_interrupt).
7844 *
7845 * 3) This also orders the write to mode from any reads to the page
7846 * tables done while the VCPU is running. Please see the comment
7847 * in kvm_flush_remote_tlbs.
6b7e2d09 7848 */
01b71917 7849 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7850
b95234c8
PB		 7851 /*
7852 * This handles the case where a posted interrupt was
7853 * notified with kvm_vcpu_kick.
7854 */
fa59cc00
LA		 7855 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7856 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7857
2fa6e1e1 7858 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7859 || need_resched() || signal_pending(current)) {
6b7e2d09 7860 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7861 smp_wmb();
6c142801
AK		 7862 local_irq_enable();
7863 preempt_enable();
01b71917 7864 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7865 r = 1;
d905c069 7866 goto cancel_injection;
6c142801
AK		 7867 }
7868
c43203ca
PB		 7869 if (req_immediate_exit) {
7870 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7871 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7872 }
d6185f20 7873
8b89fe1f 7874 trace_kvm_entry(vcpu->vcpu_id);
39497d76 7875 if (vcpu->arch.apic->lapic_timer.timer_advance_ns)
9c48d517 7876 wait_lapic_expire(vcpu);
6edaa530 7877 guest_enter_irqoff();
b6c7a5dc 7878
42dbaa5a 7879 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7880 set_debugreg(0, 7);
7881 set_debugreg(vcpu->arch.eff_db[0], 0);
7882 set_debugreg(vcpu->arch.eff_db[1], 1);
7883 set_debugreg(vcpu->arch.eff_db[2], 2);
7884 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7885 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7886 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7887 }
b6c7a5dc 7888
851ba692 7889 kvm_x86_ops->run(vcpu);
b6c7a5dc 7890
c77fb5fe
PB		 7891 /*
7892 * Do this here before restoring debug registers on the host. And
7893 * since we do this before handling the vmexit, a DR access vmexit
7894 * can (a) read the correct value of the debug registers, (b) set
7895 * KVM_DEBUGREG_WONT_EXIT again.
7896 */
7897 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7898 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7899 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7900 kvm_update_dr0123(vcpu);
7901 kvm_update_dr6(vcpu);
7902 kvm_update_dr7(vcpu);
7903 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7904 }
7905
24f1e32c
FW		 7906 /*
7907 * If the guest has used debug registers, at least dr7
7908 * will be disabled while returning to the host.
7909 * If we don't have active breakpoints in the host, we don't
7910 * care about the messed up debug address registers. But if
7911 * we have some of them active, restore the old state.
7912 */
59d8eb53 7913 if (hw_breakpoint_active())
24f1e32c 7914 hw_breakpoint_restore();
42dbaa5a 7915
4ba76538 7916 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7917
6b7e2d09 7918 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7919 smp_wmb();
a547c6db 7920
dd60d217 7921 kvm_before_interrupt(vcpu);
a547c6db 7922 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7923 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7924
7925 ++vcpu->stat.exits;
7926
f2485b3e 7927 guest_exit_irqoff();
b6c7a5dc 7928
f2485b3e 7929 local_irq_enable();
b6c7a5dc
HB		 7930 preempt_enable();
7931
f656ce01 7932 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7933
b6c7a5dc
HB		 7934 /*
7935 * Profile KVM exit RIPs:
7936 */
7937 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7938 unsigned long rip = kvm_rip_read(vcpu);
7939 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7940 }
7941
cc578287
ZA		 7942 if (unlikely(vcpu->arch.tsc_always_catchup))
7943 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7944
5cfb1d5a
MT		 7945 if (vcpu->arch.apic_attention)
7946 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7947
618232e2 7948 vcpu->arch.gpa_available = false;
851ba692 7949 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7950 return r;
7951
7952cancel_injection:
7953 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7954 if (unlikely(vcpu->arch.apic_attention))
7955 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7956out:
7957 return r;
7958}
b6c7a5dc 7959
362c698f
PB		 7960static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7961{
bf9f6ac8
FW		 7962 if (!kvm_arch_vcpu_runnable(vcpu) &&
7963 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7964 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7965 kvm_vcpu_block(vcpu);
7966 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7967
7968 if (kvm_x86_ops->post_block)
7969 kvm_x86_ops->post_block(vcpu);
7970
9c8fd1ba
PB		 7971 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7972 return 1;
7973 }
362c698f
PB		 7974
7975 kvm_apic_accept_events(vcpu);
7976 switch(vcpu->arch.mp_state) {
7977 case KVM_MP_STATE_HALTED:
7978 vcpu->arch.pv.pv_unhalted = false;
7979 vcpu->arch.mp_state =
7980 KVM_MP_STATE_RUNNABLE;
b2869f28 7981 /* fall through */
362c698f
PB		 7982 case KVM_MP_STATE_RUNNABLE:
7983 vcpu->arch.apf.halted = false;
7984 break;
7985 case KVM_MP_STATE_INIT_RECEIVED:
7986 break;
7987 default:
7988 return -EINTR;
7989 break;
7990 }
7991 return 1;
7992}
09cec754 7993
5d9bc648
PB		 7994static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7995{
0ad3bed6
PB		 7996 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7997 kvm_x86_ops->check_nested_events(vcpu, false);
7998
5d9bc648
PB		 7999 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8000 !vcpu->arch.apf.halted);
8001}
8002
362c698f 8003static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8004{
8005 int r;
f656ce01 8006 struct kvm *kvm = vcpu->kvm;
d7690175 8007
f656ce01 8008 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8009 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8010
362c698f 8011 for (;;) {
58f800d5 8012 if (kvm_vcpu_running(vcpu)) {
851ba692 8013 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8014 } else {
362c698f 8015 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8016 }
8017
09cec754
GN		 8018 if (r <= 0)
8019 break;
8020
72875d8a 8021 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8022 if (kvm_cpu_has_pending_timer(vcpu))
8023 kvm_inject_pending_timer_irqs(vcpu);
8024
782d422b
MG		 8025 if (dm_request_for_irq_injection(vcpu) &&
8026 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8027 r = 0;
8028 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8029 ++vcpu->stat.request_irq_exits;
362c698f 8030 break;
09cec754 8031 }
af585b92
GN		 8032
8033 kvm_check_async_pf_completion(vcpu);
8034
09cec754
GN		 8035 if (signal_pending(current)) {
8036 r = -EINTR;
851ba692 8037 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8038 ++vcpu->stat.signal_exits;
362c698f 8039 break;
09cec754
GN		 8040 }
8041 if (need_resched()) {
f656ce01 8042 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8043 cond_resched();
f656ce01 8044 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8045 }
b6c7a5dc
HB		 8046 }
8047
f656ce01 8048 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8049
8050 return r;
8051}
8052
716d51ab
GN		 8053static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8054{
8055 int r;
8056 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8057 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 8058 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8059 if (r != EMULATE_DONE)
8060 return 0;
8061 return 1;
8062}
8063
8064static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8065{
8066 BUG_ON(!vcpu->arch.pio.count);
8067
8068 return complete_emulated_io(vcpu);
8069}
8070
f78146b0
AK		 8071/*
8072 * Implements the following, as a state machine:
8073 *
8074 * read:
8075 * for each fragment
87da7e66
XG		 8076 * for each mmio piece in the fragment
8077 * write gpa, len
8078 * exit
8079 * copy data
f78146b0
AK		 8080 * execute insn
8081 *
8082 * write:
8083 * for each fragment
87da7e66
XG		 8084 * for each mmio piece in the fragment
8085 * write gpa, len
8086 * copy data
8087 * exit
f78146b0 8088 */
716d51ab 8089static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8090{
8091 struct kvm_run *run = vcpu->run;
f78146b0 8092 struct kvm_mmio_fragment *frag;
87da7e66 8093 unsigned len;
5287f194 8094
716d51ab 8095 BUG_ON(!vcpu->mmio_needed);
5287f194 8096
716d51ab 8097 /* Complete previous fragment */
87da7e66
XG		 8098 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8099 len = min(8u, frag->len);
716d51ab 8100 if (!vcpu->mmio_is_write)
87da7e66
XG		 8101 memcpy(frag->data, run->mmio.data, len);
8102
8103 if (frag->len <= 8) {
8104 /* Switch to the next fragment. */
8105 frag++;
8106 vcpu->mmio_cur_fragment++;
8107 } else {
8108 /* Go forward to the next mmio piece. */
8109 frag->data += len;
8110 frag->gpa += len;
8111 frag->len -= len;
8112 }
8113
a08d3b3b 8114 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8115 vcpu->mmio_needed = 0;
0912c977
PB		 8116
8117 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8118 if (vcpu->mmio_is_write)
716d51ab
GN		 8119 return 1;
8120 vcpu->mmio_read_completed = 1;
8121 return complete_emulated_io(vcpu);
8122 }
87da7e66 8123
716d51ab
GN		 8124 run->exit_reason = KVM_EXIT_MMIO;
8125 run->mmio.phys_addr = frag->gpa;
8126 if (vcpu->mmio_is_write)
87da7e66
XG		 8127 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8128 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8129 run->mmio.is_write = vcpu->mmio_is_write;
8130 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8131 return 0;
5287f194
AK		 8132}
8133
822f312d
SAS		 8134/* Swap (qemu) user FPU context for the guest FPU context. */
8135static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8136{
8137 preempt_disable();
240c35a3 8138 copy_fpregs_to_fpstate(&current->thread.fpu);
822f312d 8139 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8140 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d
SAS		 8141 ~XFEATURE_MASK_PKRU);
8142 preempt_enable();
8143 trace_kvm_fpu(1);
8144}
8145
8146/* When vcpu_run ends, restore user space FPU context. */
8147static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8148{
8149 preempt_disable();
b666a4b6 8150 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
240c35a3 8151 copy_kernel_to_fpregs(&current->thread.fpu.state);
822f312d
SAS		 8152 preempt_enable();
8153 ++vcpu->stat.fpu_reload;
8154 trace_kvm_fpu(0);
8155}
8156
b6c7a5dc
HB		 8157int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8158{
8159 int r;
b6c7a5dc 8160
accb757d 8161 vcpu_load(vcpu);
20b7035c 8162 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8163 kvm_load_guest_fpu(vcpu);
8164
a4535290 8165 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8166 if (kvm_run->immediate_exit) {
8167 r = -EINTR;
8168 goto out;
8169 }
b6c7a5dc 8170 kvm_vcpu_block(vcpu);
66450a21 8171 kvm_apic_accept_events(vcpu);
72875d8a 8172 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8173 r = -EAGAIN;
a0595000
JS		 8174 if (signal_pending(current)) {
8175 r = -EINTR;
8176 vcpu->run->exit_reason = KVM_EXIT_INTR;
8177 ++vcpu->stat.signal_exits;
8178 }
ac9f6dc0 8179 goto out;
b6c7a5dc
HB		 8180 }
8181
01643c51
KH		 8182 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8183 r = -EINVAL;
8184 goto out;
8185 }
8186
8187 if (vcpu->run->kvm_dirty_regs) {
8188 r = sync_regs(vcpu);
8189 if (r != 0)
8190 goto out;
8191 }
8192
b6c7a5dc 8193 /* re-sync apic's tpr */
35754c98 8194 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8195 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8196 r = -EINVAL;
8197 goto out;
8198 }
8199 }
b6c7a5dc 8200
716d51ab
GN		 8201 if (unlikely(vcpu->arch.complete_userspace_io)) {
8202 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8203 vcpu->arch.complete_userspace_io = NULL;
8204 r = cui(vcpu);
8205 if (r <= 0)
5663d8f9 8206 goto out;
716d51ab
GN		 8207 } else
8208 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8209
460df4c1
PB		 8210 if (kvm_run->immediate_exit)
8211 r = -EINTR;
8212 else
8213 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8214
8215out:
5663d8f9 8216 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8217 if (vcpu->run->kvm_valid_regs)
8218 store_regs(vcpu);
f1d86e46 8219 post_kvm_run_save(vcpu);
20b7035c 8220 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8221
accb757d 8222 vcpu_put(vcpu);
b6c7a5dc
HB		 8223 return r;
8224}
8225
01643c51 8226static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8227{
7ae441ea
GN		 8228 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8229 /*
8230 * We are here if userspace calls get_regs() in the middle of
8231 * instruction emulation. Registers state needs to be copied
4a969980 8232 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8233 * that usually, but some bad designed PV devices (vmware
8234 * backdoor interface) need this to work
8235 */
dd856efa 8236 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8237 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8238 }
5fdbf976
MT		 8239 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
8240 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
8241 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
8242 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
8243 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
8244 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
8245 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8246 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 8247#ifdef CONFIG_X86_64
5fdbf976
MT		 8248 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
8249 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
8250 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
8251 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
8252 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
8253 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
8254 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
8255 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 8256#endif
8257
5fdbf976 8258 regs->rip = kvm_rip_read(vcpu);
91586a3b 8259 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8260}
b6c7a5dc 8261
01643c51
KH		 8262int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8263{
8264 vcpu_load(vcpu);
8265 __get_regs(vcpu, regs);
1fc9b76b 8266 vcpu_put(vcpu);
b6c7a5dc
HB		 8267 return 0;
8268}
8269
01643c51 8270static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8271{
7ae441ea
GN		 8272 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8273 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8274
5fdbf976
MT		 8275 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
8276 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8277 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8278 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8279 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8280 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8281 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8282 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 8283#ifdef CONFIG_X86_64
5fdbf976
MT		 8284 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8285 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8286 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8287 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8288 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8289 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8290 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8291 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 8292#endif
8293
5fdbf976 8294 kvm_rip_write(vcpu, regs->rip);
d73235d1 8295 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8296
b4f14abd
JK		 8297 vcpu->arch.exception.pending = false;
8298
3842d135 8299 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8300}
3842d135 8301
01643c51
KH		 8302int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8303{
8304 vcpu_load(vcpu);
8305 __set_regs(vcpu, regs);
875656fe 8306 vcpu_put(vcpu);
b6c7a5dc
HB		 8307 return 0;
8308}
8309
b6c7a5dc
HB		 8310void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8311{
8312 struct kvm_segment cs;
8313
3e6e0aab 8314 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8315 *db = cs.db;
8316 *l = cs.l;
8317}
8318EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8319
01643c51 8320static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8321{
89a27f4d 8322 struct desc_ptr dt;
b6c7a5dc 8323
3e6e0aab
GT		 8324 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8325 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8326 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8327 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8328 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8329 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8330
3e6e0aab
GT		 8331 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8332 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8333
8334 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8335 sregs->idt.limit = dt.size;
8336 sregs->idt.base = dt.address;
b6c7a5dc 8337 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8338 sregs->gdt.limit = dt.size;
8339 sregs->gdt.base = dt.address;
b6c7a5dc 8340
4d4ec087 8341 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8342 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8343 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8344 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8345 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8346 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8347 sregs->apic_base = kvm_get_apic_base(vcpu);
8348
0e96f31e 8349 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8350
04140b41 8351 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8352 set_bit(vcpu->arch.interrupt.nr,
8353 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8354}
16d7a191 8355
01643c51
KH		 8356int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8357 struct kvm_sregs *sregs)
8358{
8359 vcpu_load(vcpu);
8360 __get_sregs(vcpu, sregs);
bcdec41c 8361 vcpu_put(vcpu);
b6c7a5dc
HB		 8362 return 0;
8363}
8364
62d9f0db
MT		 8365int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8366 struct kvm_mp_state *mp_state)
8367{
fd232561
CD		 8368 vcpu_load(vcpu);
8369
66450a21 8370 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8371 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8372 vcpu->arch.pv.pv_unhalted)
8373 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8374 else
8375 mp_state->mp_state = vcpu->arch.mp_state;
8376
fd232561 8377 vcpu_put(vcpu);
62d9f0db
MT		 8378 return 0;
8379}
8380
8381int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8382 struct kvm_mp_state *mp_state)
8383{
e83dff5e
CD		 8384 int ret = -EINVAL;
8385
8386 vcpu_load(vcpu);
8387
bce87cce 8388 if (!lapic_in_kernel(vcpu) &&
66450a21 8389 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8390 goto out;
66450a21 8391
28bf2888
DH		 8392 /* INITs are latched while in SMM */
8393 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8394 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8395 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8396 goto out;
28bf2888 8397
66450a21
JK		 8398 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8399 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8400 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8401 } else
8402 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8403 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8404
8405 ret = 0;
8406out:
8407 vcpu_put(vcpu);
8408 return ret;
62d9f0db
MT		 8409}
8410
7f3d35fd
KW		 8411int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8412 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8413{
9d74191a 8414 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8415 int ret;
e01c2426 8416
8ec4722d 8417 init_emulate_ctxt(vcpu);
c697518a 8418
7f3d35fd 8419 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8420 has_error_code, error_code);
c697518a 8421
c697518a 8422 if (ret)
19d04437 8423 return EMULATE_FAIL;
37817f29 8424
9d74191a
TY		 8425 kvm_rip_write(vcpu, ctxt->eip);
8426 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8427 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8428 return EMULATE_DONE;
37817f29
IE		 8429}
8430EXPORT_SYMBOL_GPL(kvm_task_switch);
8431
3140c156 8432static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8433{
74fec5b9
TL		 8434 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8435 (sregs->cr4 & X86_CR4_OSXSAVE))
8436 return -EINVAL;
8437
37b95951 8438 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8439 /*
8440 * When EFER.LME and CR0.PG are set, the processor is in
8441 * 64-bit mode (though maybe in a 32-bit code segment).
8442 * CR4.PAE and EFER.LMA must be set.
8443 */
37b95951 8444 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8445 || !(sregs->efer & EFER_LMA))
8446 return -EINVAL;
8447 } else {
8448 /*
8449 * Not in 64-bit mode: EFER.LMA is clear and the code
8450 * segment cannot be 64-bit.
8451 */
8452 if (sregs->efer & EFER_LMA || sregs->cs.l)
8453 return -EINVAL;
8454 }
8455
8456 return 0;
8457}
8458
01643c51 8459static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8460{
58cb628d 8461 struct msr_data apic_base_msr;
b6c7a5dc 8462 int mmu_reset_needed = 0;
c4d21882 8463 int cpuid_update_needed = 0;
63f42e02 8464 int pending_vec, max_bits, idx;
89a27f4d 8465 struct desc_ptr dt;
b4ef9d4e
CD		 8466 int ret = -EINVAL;
8467
f2981033 8468 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8469 goto out;
f2981033 8470
d3802286
JM		 8471 apic_base_msr.data = sregs->apic_base;
8472 apic_base_msr.host_initiated = true;
8473 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8474 goto out;
6d1068b3 8475
89a27f4d
GN		 8476 dt.size = sregs->idt.limit;
8477 dt.address = sregs->idt.base;
b6c7a5dc 8478 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8479 dt.size = sregs->gdt.limit;
8480 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8481 kvm_x86_ops->set_gdt(vcpu, &dt);
8482
ad312c7c 8483 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8484 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8485 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8486 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8487
2d3ad1f4 8488 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8489
f6801dff 8490 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8491 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8492
4d4ec087 8493 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8494 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8495 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8496
fc78f519 8497 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8498 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8499 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8500 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8501 if (cpuid_update_needed)
00b27a3e 8502 kvm_update_cpuid(vcpu);
63f42e02
XG		 8503
8504 idx = srcu_read_lock(&vcpu->kvm->srcu);
d35b34a9 8505 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
9f8fe504 8506 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8507 mmu_reset_needed = 1;
8508 }
63f42e02 8509 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8510
8511 if (mmu_reset_needed)
8512 kvm_mmu_reset_context(vcpu);
8513
a50abc3b 8514 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8515 pending_vec = find_first_bit(
8516 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8517 if (pending_vec < max_bits) {
66fd3f7f 8518 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8519 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8520 }
8521
3e6e0aab
GT		 8522 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8523 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8524 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8525 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8526 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8527 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8528
3e6e0aab
GT		 8529 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8530 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8531
5f0269f5
ME		 8532 update_cr8_intercept(vcpu);
8533
9c3e4aab 8534 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8535 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8536 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8537 !is_protmode(vcpu))
9c3e4aab
MT		 8538 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8539
3842d135
AK		 8540 kvm_make_request(KVM_REQ_EVENT, vcpu);
8541
b4ef9d4e
CD		 8542 ret = 0;
8543out:
01643c51
KH		 8544 return ret;
8545}
8546
8547int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8548 struct kvm_sregs *sregs)
8549{
8550 int ret;
8551
8552 vcpu_load(vcpu);
8553 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8554 vcpu_put(vcpu);
8555 return ret;
b6c7a5dc
HB		 8556}
8557
d0bfb940
JK		 8558int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8559 struct kvm_guest_debug *dbg)
b6c7a5dc 8560{
355be0b9 8561 unsigned long rflags;
ae675ef0 8562 int i, r;
b6c7a5dc 8563
66b56562
CD		 8564 vcpu_load(vcpu);
8565
4f926bf2
JK		 8566 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8567 r = -EBUSY;
8568 if (vcpu->arch.exception.pending)
2122ff5e 8569 goto out;
4f926bf2
JK		 8570 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8571 kvm_queue_exception(vcpu, DB_VECTOR);
8572 else
8573 kvm_queue_exception(vcpu, BP_VECTOR);
8574 }
8575
91586a3b
JK		 8576 /*
8577 * Read rflags as long as potentially injected trace flags are still
8578 * filtered out.
8579 */
8580 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8581
8582 vcpu->guest_debug = dbg->control;
8583 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8584 vcpu->guest_debug = 0;
8585
8586 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8587 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8588 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8589 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8590 } else {
8591 for (i = 0; i < KVM_NR_DB_REGS; i++)
8592 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8593 }
c8639010 8594 kvm_update_dr7(vcpu);
ae675ef0 8595
f92653ee
JK		 8596 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8597 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8598 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8599
91586a3b
JK		 8600 /*
8601 * Trigger an rflags update that will inject or remove the trace
8602 * flags.
8603 */
8604 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8605
a96036b8 8606 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8607
4f926bf2 8608 r = 0;
d0bfb940 8609
2122ff5e 8610out:
66b56562 8611 vcpu_put(vcpu);
b6c7a5dc
HB		 8612 return r;
8613}
8614
8b006791
ZX		 8615/*
8616 * Translate a guest virtual address to a guest physical address.
8617 */
8618int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8619 struct kvm_translation *tr)
8620{
8621 unsigned long vaddr = tr->linear_address;
8622 gpa_t gpa;
f656ce01 8623 int idx;
8b006791 8624
1da5b61d
CD		 8625 vcpu_load(vcpu);
8626
f656ce01 8627 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8628 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8629 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8630 tr->physical_address = gpa;
8631 tr->valid = gpa != UNMAPPED_GVA;
8632 tr->writeable = 1;
8633 tr->usermode = 0;
8b006791 8634
1da5b61d 8635 vcpu_put(vcpu);
8b006791
ZX		 8636 return 0;
8637}
8638
d0752060
HB		 8639int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8640{
1393123e 8641 struct fxregs_state *fxsave;
d0752060 8642
1393123e 8643 vcpu_load(vcpu);
d0752060 8644
b666a4b6 8645 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8646 memcpy(fpu->fpr, fxsave->st_space, 128);
8647 fpu->fcw = fxsave->cwd;
8648 fpu->fsw = fxsave->swd;
8649 fpu->ftwx = fxsave->twd;
8650 fpu->last_opcode = fxsave->fop;
8651 fpu->last_ip = fxsave->rip;
8652 fpu->last_dp = fxsave->rdp;
0e96f31e 8653 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8654
1393123e 8655 vcpu_put(vcpu);
d0752060
HB		 8656 return 0;
8657}
8658
8659int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8660{
6a96bc7f
CD		 8661 struct fxregs_state *fxsave;
8662
8663 vcpu_load(vcpu);
8664
b666a4b6 8665 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8666
d0752060
HB		 8667 memcpy(fxsave->st_space, fpu->fpr, 128);
8668 fxsave->cwd = fpu->fcw;
8669 fxsave->swd = fpu->fsw;
8670 fxsave->twd = fpu->ftwx;
8671 fxsave->fop = fpu->last_opcode;
8672 fxsave->rip = fpu->last_ip;
8673 fxsave->rdp = fpu->last_dp;
0e96f31e 8674 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8675
6a96bc7f 8676 vcpu_put(vcpu);
d0752060
HB		 8677 return 0;
8678}
8679
01643c51
KH		 8680static void store_regs(struct kvm_vcpu *vcpu)
8681{
8682 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8683
8684 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8685 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8686
8687 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8688 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8689
8690 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8691 kvm_vcpu_ioctl_x86_get_vcpu_events(
8692 vcpu, &vcpu->run->s.regs.events);
8693}
8694
8695static int sync_regs(struct kvm_vcpu *vcpu)
8696{
8697 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8698 return -EINVAL;
8699
8700 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8701 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8702 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8703 }
8704 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8705 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8706 return -EINVAL;
8707 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8708 }
8709 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8710 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8711 vcpu, &vcpu->run->s.regs.events))
8712 return -EINVAL;
8713 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8714 }
8715
8716 return 0;
8717}
8718
0ee6a517 8719static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8720{
b666a4b6 8721 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 8722 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 8723 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 8724 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8725
2acf923e
DC		 8726 /*
8727 * Ensure guest xcr0 is valid for loading
8728 */
d91cab78 8729 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8730
ad312c7c 8731 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8732}
d0752060 8733
e9b11c17
ZX		 8734void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8735{
bd768e14
IY		 8736 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8737
12f9a48f 8738 kvmclock_reset(vcpu);
7f1ea208 8739
e9b11c17 8740 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8741 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8742}
8743
8744struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8745 unsigned int id)
8746{
c447e76b
LL		 8747 struct kvm_vcpu *vcpu;
8748
b0c39dc6 8749 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8750 printk_once(KERN_WARNING
8751 "kvm: SMP vm created on host with unstable TSC; "
8752 "guest TSC will not be reliable\n");
c447e76b
LL		 8753
8754 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8755
c447e76b 8756 return vcpu;
26e5215f 8757}
e9b11c17 8758
26e5215f
AK		 8759int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8760{
0cf9135b 8761 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 8762 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 8763 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8764 vcpu_load(vcpu);
d28bc9dd 8765 kvm_vcpu_reset(vcpu, false);
e1732991 8766 kvm_init_mmu(vcpu, false);
e9b11c17 8767 vcpu_put(vcpu);
ec7660cc 8768 return 0;
e9b11c17
ZX		 8769}
8770
31928aa5 8771void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8772{
8fe8ab46 8773 struct msr_data msr;
332967a3 8774 struct kvm *kvm = vcpu->kvm;
42897d86 8775
d3457c87
RK		 8776 kvm_hv_vcpu_postcreate(vcpu);
8777
ec7660cc 8778 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8779 return;
ec7660cc 8780 vcpu_load(vcpu);
8fe8ab46
WA		 8781 msr.data = 0x0;
8782 msr.index = MSR_IA32_TSC;
8783 msr.host_initiated = true;
8784 kvm_write_tsc(vcpu, &msr);
42897d86 8785 vcpu_put(vcpu);
ec7660cc 8786 mutex_unlock(&vcpu->mutex);
42897d86 8787
630994b3
MT		 8788 if (!kvmclock_periodic_sync)
8789 return;
8790
332967a3
AJ		 8791 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8792 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8793}
8794
d40ccc62 8795void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8796{
344d9588
GN		 8797 vcpu->arch.apf.msr_val = 0;
8798
ec7660cc 8799 vcpu_load(vcpu);
e9b11c17
ZX		 8800 kvm_mmu_unload(vcpu);
8801 vcpu_put(vcpu);
8802
8803 kvm_x86_ops->vcpu_free(vcpu);
8804}
8805
d28bc9dd 8806void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8807{
b7e31be3
RK		 8808 kvm_lapic_reset(vcpu, init_event);
8809
e69fab5d
PB		 8810 vcpu->arch.hflags = 0;
8811
c43203ca 8812 vcpu->arch.smi_pending = 0;
52797bf9 8813 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8814 atomic_set(&vcpu->arch.nmi_queued, 0);
8815 vcpu->arch.nmi_pending = 0;
448fa4a9 8816 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8817 kvm_clear_interrupt_queue(vcpu);
8818 kvm_clear_exception_queue(vcpu);
664f8e26 8819 vcpu->arch.exception.pending = false;
448fa4a9 8820
42dbaa5a 8821 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8822 kvm_update_dr0123(vcpu);
6f43ed01 8823 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8824 kvm_update_dr6(vcpu);
42dbaa5a 8825 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8826 kvm_update_dr7(vcpu);
42dbaa5a 8827
1119022c
NA		 8828 vcpu->arch.cr2 = 0;
8829
3842d135 8830 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8831 vcpu->arch.apf.msr_val = 0;
c9aaa895 8832 vcpu->arch.st.msr_val = 0;
3842d135 8833
12f9a48f
GC		 8834 kvmclock_reset(vcpu);
8835
af585b92
GN		 8836 kvm_clear_async_pf_completion_queue(vcpu);
8837 kvm_async_pf_hash_reset(vcpu);
8838 vcpu->arch.apf.halted = false;
3842d135 8839
a554d207
WL		 8840 if (kvm_mpx_supported()) {
8841 void *mpx_state_buffer;
8842
8843 /*
8844 * To avoid have the INIT path from kvm_apic_has_events() that be
8845 * called with loaded FPU and does not let userspace fix the state.
8846 */
f775b13e
RR		 8847 if (init_event)
8848 kvm_put_guest_fpu(vcpu);
b666a4b6 8849 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
a554d207
WL		 8850 XFEATURE_MASK_BNDREGS);
8851 if (mpx_state_buffer)
8852 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 8853 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
a554d207
WL		 8854 XFEATURE_MASK_BNDCSR);
8855 if (mpx_state_buffer)
8856 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8857 if (init_event)
8858 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8859 }
8860
64d60670 8861 if (!init_event) {
d28bc9dd 8862 kvm_pmu_reset(vcpu);
64d60670 8863 vcpu->arch.smbase = 0x30000;
db2336a8 8864
db2336a8 8865 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8866
8867 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8868 }
f5132b01 8869
66f7b72e
JS		 8870 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8871 vcpu->arch.regs_avail = ~0;
8872 vcpu->arch.regs_dirty = ~0;
8873
a554d207
WL		 8874 vcpu->arch.ia32_xss = 0;
8875
d28bc9dd 8876 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8877}
8878
2b4a273b 8879void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8880{
8881 struct kvm_segment cs;
8882
8883 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8884 cs.selector = vector << 8;
8885 cs.base = vector << 12;
8886 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8887 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8888}
8889
13a34e06 8890int kvm_arch_hardware_enable(void)
e9b11c17 8891{
ca84d1a2
ZA		 8892 struct kvm *kvm;
8893 struct kvm_vcpu *vcpu;
8894 int i;
0dd6a6ed
ZA		 8895 int ret;
8896 u64 local_tsc;
8897 u64 max_tsc = 0;
8898 bool stable, backwards_tsc = false;
18863bdd
AK		 8899
8900 kvm_shared_msr_cpu_online();
13a34e06 8901 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8902 if (ret != 0)
8903 return ret;
8904
4ea1636b 8905 local_tsc = rdtsc();
b0c39dc6 8906 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8907 list_for_each_entry(kvm, &vm_list, vm_list) {
8908 kvm_for_each_vcpu(i, vcpu, kvm) {
8909 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8910 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8911 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8912 backwards_tsc = true;
8913 if (vcpu->arch.last_host_tsc > max_tsc)
8914 max_tsc = vcpu->arch.last_host_tsc;
8915 }
8916 }
8917 }
8918
8919 /*
8920 * Sometimes, even reliable TSCs go backwards. This happens on
8921 * platforms that reset TSC during suspend or hibernate actions, but
8922 * maintain synchronization. We must compensate. Fortunately, we can
8923 * detect that condition here, which happens early in CPU bringup,
8924 * before any KVM threads can be running. Unfortunately, we can't
8925 * bring the TSCs fully up to date with real time, as we aren't yet far
8926 * enough into CPU bringup that we know how much real time has actually
108b249c 8927 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8928 * variables that haven't been updated yet.
8929 *
8930 * So we simply find the maximum observed TSC above, then record the
8931 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8932 * the adjustment will be applied. Note that we accumulate
8933 * adjustments, in case multiple suspend cycles happen before some VCPU
8934 * gets a chance to run again. In the event that no KVM threads get a
8935 * chance to run, we will miss the entire elapsed period, as we'll have
8936 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8937 * loose cycle time. This isn't too big a deal, since the loss will be
8938 * uniform across all VCPUs (not to mention the scenario is extremely
8939 * unlikely). It is possible that a second hibernate recovery happens
8940 * much faster than a first, causing the observed TSC here to be
8941 * smaller; this would require additional padding adjustment, which is
8942 * why we set last_host_tsc to the local tsc observed here.
8943 *
8944 * N.B. - this code below runs only on platforms with reliable TSC,
8945 * as that is the only way backwards_tsc is set above. Also note
8946 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8947 * have the same delta_cyc adjustment applied if backwards_tsc
8948 * is detected. Note further, this adjustment is only done once,
8949 * as we reset last_host_tsc on all VCPUs to stop this from being
8950 * called multiple times (one for each physical CPU bringup).
8951 *
4a969980 8952 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8953 * will be compensated by the logic in vcpu_load, which sets the TSC to
8954 * catchup mode. This will catchup all VCPUs to real time, but cannot
8955 * guarantee that they stay in perfect synchronization.
8956 */
8957 if (backwards_tsc) {
8958 u64 delta_cyc = max_tsc - local_tsc;
8959 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8960 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8961 kvm_for_each_vcpu(i, vcpu, kvm) {
8962 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8963 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8964 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8965 }
8966
8967 /*
8968 * We have to disable TSC offset matching.. if you were
8969 * booting a VM while issuing an S4 host suspend....
8970 * you may have some problem. Solving this issue is
8971 * left as an exercise to the reader.
8972 */
8973 kvm->arch.last_tsc_nsec = 0;
8974 kvm->arch.last_tsc_write = 0;
8975 }
8976
8977 }
8978 return 0;
e9b11c17
ZX		 8979}
8980
13a34e06 8981void kvm_arch_hardware_disable(void)
e9b11c17 8982{
13a34e06
RK		 8983 kvm_x86_ops->hardware_disable();
8984 drop_user_return_notifiers();
e9b11c17
ZX		 8985}
8986
8987int kvm_arch_hardware_setup(void)
8988{
9e9c3fe4
NA		 8989 int r;
8990
8991 r = kvm_x86_ops->hardware_setup();
8992 if (r != 0)
8993 return r;
8994
35181e86
HZ		 8995 if (kvm_has_tsc_control) {
8996 /*
8997 * Make sure the user can only configure tsc_khz values that
8998 * fit into a signed integer.
273ba457 8999 * A min value is not calculated because it will always
35181e86
HZ		 9000 * be 1 on all machines.
9001 */
9002 u64 max = min(0x7fffffffULL,
9003 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9004 kvm_max_guest_tsc_khz = max;
9005
ad721883 9006 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9007 }
ad721883 9008
9e9c3fe4
NA		 9009 kvm_init_msr_list();
9010 return 0;
e9b11c17
ZX		 9011}
9012
9013void kvm_arch_hardware_unsetup(void)
9014{
9015 kvm_x86_ops->hardware_unsetup();
9016}
9017
9018void kvm_arch_check_processor_compat(void *rtn)
9019{
9020 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 9021}
9022
9023bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9024{
9025 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9026}
9027EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9028
9029bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9030{
9031 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9032}
9033
54e9818f 9034struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9035EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9036
e9b11c17
ZX		 9037int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9038{
9039 struct page *page;
e9b11c17
ZX		 9040 int r;
9041
9aabc88f 9042 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9043 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9044 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9045 else
a4535290 9046 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9047
9048 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9049 if (!page) {
9050 r = -ENOMEM;
9051 goto fail;
9052 }
ad312c7c 9053 vcpu->arch.pio_data = page_address(page);
e9b11c17 9054
cc578287 9055 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9056
e9b11c17
ZX		 9057 r = kvm_mmu_create(vcpu);
9058 if (r < 0)
9059 goto fail_free_pio_data;
9060
26de7988 9061 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9062 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
39497d76 9063 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
e9b11c17
ZX		 9064 if (r < 0)
9065 goto fail_mmu_destroy;
54e9818f
GN		 9066 } else
9067 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9068
890ca9ae 9069 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
254272ce 9070 GFP_KERNEL_ACCOUNT);
890ca9ae
HY		 9071 if (!vcpu->arch.mce_banks) {
9072 r = -ENOMEM;
443c39bc 9073 goto fail_free_lapic;
890ca9ae
HY		 9074 }
9075 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9076
254272ce
BG		 9077 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9078 GFP_KERNEL_ACCOUNT)) {
f1797359 9079 r = -ENOMEM;
f5f48ee1 9080 goto fail_free_mce_banks;
f1797359 9081 }
f5f48ee1 9082
0ee6a517 9083 fx_init(vcpu);
66f7b72e 9084
4344ee98 9085 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9086
5a4f55cd
EK		 9087 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9088
74545705
RK		 9089 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9090
af585b92 9091 kvm_async_pf_hash_reset(vcpu);
f5132b01 9092 kvm_pmu_init(vcpu);
af585b92 9093
1c1a9ce9 9094 vcpu->arch.pending_external_vector = -1;
de63ad4c 9095 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9096
5c919412
AS		 9097 kvm_hv_vcpu_init(vcpu);
9098
e9b11c17 9099 return 0;
0ee6a517 9100
f5f48ee1
SY		 9101fail_free_mce_banks:
9102 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9103fail_free_lapic:
9104 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9105fail_mmu_destroy:
9106 kvm_mmu_destroy(vcpu);
9107fail_free_pio_data:
ad312c7c 9108 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9109fail:
9110 return r;
9111}
9112
9113void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9114{
f656ce01
MT		 9115 int idx;
9116
1f4b34f8 9117 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9118 kvm_pmu_destroy(vcpu);
36cb93fd 9119 kfree(vcpu->arch.mce_banks);
e9b11c17 9120 kvm_free_lapic(vcpu);
f656ce01 9121 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9122 kvm_mmu_destroy(vcpu);
f656ce01 9123 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9124 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9125 if (!lapic_in_kernel(vcpu))
54e9818f 9126 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9127}
d19a9cd2 9128
e790d9ef
RK		 9129void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9130{
c595ceee 9131 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9132 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9133}
9134
e08b9637 9135int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9136{
e08b9637
CO		 9137 if (type)
9138 return -EINVAL;
9139
6ef768fa 9140 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9141 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 9142 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9143 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9144
5550af4d
SY		 9145 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9146 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9147 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9148 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9149 &kvm->arch.irq_sources_bitmap);
5550af4d 9150
038f8c11 9151 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9152 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9153 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9154
108b249c 9155 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 9156 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9157
6fbbde9a
DS		 9158 kvm->arch.guest_can_read_msr_platform_info = true;
9159
7e44e449 9160 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9161 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9162
cbc0236a 9163 kvm_hv_init_vm(kvm);
0eb05bf2 9164 kvm_page_track_init(kvm);
13d268ca 9165 kvm_mmu_init_vm(kvm);
0eb05bf2 9166
03543133
SS		 9167 if (kvm_x86_ops->vm_init)
9168 return kvm_x86_ops->vm_init(kvm);
9169
d89f5eff 9170 return 0;
d19a9cd2
ZX		 9171}
9172
9173static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9174{
ec7660cc 9175 vcpu_load(vcpu);
d19a9cd2
ZX		 9176 kvm_mmu_unload(vcpu);
9177 vcpu_put(vcpu);
9178}
9179
9180static void kvm_free_vcpus(struct kvm *kvm)
9181{
9182 unsigned int i;
988a2cae 9183 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9184
9185 /*
9186 * Unpin any mmu pages first.
9187 */
af585b92
GN		 9188 kvm_for_each_vcpu(i, vcpu, kvm) {
9189 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9190 kvm_unload_vcpu_mmu(vcpu);
af585b92 9191 }
988a2cae
GN		 9192 kvm_for_each_vcpu(i, vcpu, kvm)
9193 kvm_arch_vcpu_free(vcpu);
9194
9195 mutex_lock(&kvm->lock);
9196 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9197 kvm->vcpus[i] = NULL;
d19a9cd2 9198
988a2cae
GN		 9199 atomic_set(&kvm->online_vcpus, 0);
9200 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9201}
9202
ad8ba2cd
SY		 9203void kvm_arch_sync_events(struct kvm *kvm)
9204{
332967a3 9205 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9206 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9207 kvm_free_pit(kvm);
ad8ba2cd
SY		 9208}
9209
1d8007bd 9210int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9211{
9212 int i, r;
25188b99 9213 unsigned long hva;
f0d648bd
PB		 9214 struct kvm_memslots *slots = kvm_memslots(kvm);
9215 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9216
9217 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9218 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9219 return -EINVAL;
9da0e4d5 9220
f0d648bd
PB		 9221 slot = id_to_memslot(slots, id);
9222 if (size) {
b21629da 9223 if (slot->npages)
f0d648bd
PB		 9224 return -EEXIST;
9225
9226 /*
9227 * MAP_SHARED to prevent internal slot pages from being moved
9228 * by fork()/COW.
9229 */
9230 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9231 MAP_SHARED | MAP_ANONYMOUS, 0);
9232 if (IS_ERR((void *)hva))
9233 return PTR_ERR((void *)hva);
9234 } else {
9235 if (!slot->npages)
9236 return 0;
9237
9238 hva = 0;
9239 }
9240
9241 old = *slot;
9da0e4d5 9242 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9243 struct kvm_userspace_memory_region m;
9da0e4d5 9244
1d8007bd
PB		 9245 m.slot = id | (i << 16);
9246 m.flags = 0;
9247 m.guest_phys_addr = gpa;
f0d648bd 9248 m.userspace_addr = hva;
1d8007bd 9249 m.memory_size = size;
9da0e4d5
PB		 9250 r = __kvm_set_memory_region(kvm, &m);
9251 if (r < 0)
9252 return r;
9253 }
9254
103c763c
EB		 9255 if (!size)
9256 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9257
9da0e4d5
PB		 9258 return 0;
9259}
9260EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9261
1d8007bd 9262int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9263{
9264 int r;
9265
9266 mutex_lock(&kvm->slots_lock);
1d8007bd 9267 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9268 mutex_unlock(&kvm->slots_lock);
9269
9270 return r;
9271}
9272EXPORT_SYMBOL_GPL(x86_set_memory_region);
9273
d19a9cd2
ZX		 9274void kvm_arch_destroy_vm(struct kvm *kvm)
9275{
27469d29
AH		 9276 if (current->mm == kvm->mm) {
9277 /*
9278 * Free memory regions allocated on behalf of userspace,
9279 * unless the the memory map has changed due to process exit
9280 * or fd copying.
9281 */
1d8007bd
PB		 9282 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9283 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9284 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9285 }
03543133
SS		 9286 if (kvm_x86_ops->vm_destroy)
9287 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9288 kvm_pic_destroy(kvm);
9289 kvm_ioapic_destroy(kvm);
d19a9cd2 9290 kvm_free_vcpus(kvm);
af1bae54 9291 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 9292 kvm_mmu_uninit_vm(kvm);
2beb6dad 9293 kvm_page_track_cleanup(kvm);
cbc0236a 9294 kvm_hv_destroy_vm(kvm);
d19a9cd2 9295}
0de10343 9296
5587027c 9297void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9298 struct kvm_memory_slot *dont)
9299{
9300 int i;
9301
d89cc617
TY		 9302 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9303 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9304 kvfree(free->arch.rmap[i]);
d89cc617 9305 free->arch.rmap[i] = NULL;
77d11309 9306 }
d89cc617
TY		 9307 if (i == 0)
9308 continue;
9309
9310 if (!dont || free->arch.lpage_info[i - 1] !=
9311 dont->arch.lpage_info[i - 1]) {
548ef284 9312 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9313 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9314 }
9315 }
21ebbeda
XG		 9316
9317 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9318}
9319
5587027c
AK		 9320int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9321 unsigned long npages)
db3fe4eb
TY		 9322{
9323 int i;
9324
d89cc617 9325 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9326 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9327 unsigned long ugfn;
9328 int lpages;
d89cc617 9329 int level = i + 1;
db3fe4eb
TY		 9330
9331 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9332 slot->base_gfn, level) + 1;
9333
d89cc617 9334 slot->arch.rmap[i] =
778e1cdd 9335 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9336 GFP_KERNEL_ACCOUNT);
d89cc617 9337 if (!slot->arch.rmap[i])
77d11309 9338 goto out_free;
d89cc617
TY		 9339 if (i == 0)
9340 continue;
77d11309 9341
254272ce 9342 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9343 if (!linfo)
db3fe4eb
TY		 9344 goto out_free;
9345
92f94f1e
XG		 9346 slot->arch.lpage_info[i - 1] = linfo;
9347
db3fe4eb 9348 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9349 linfo[0].disallow_lpage = 1;
db3fe4eb 9350 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9351 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9352 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9353 /*
9354 * If the gfn and userspace address are not aligned wrt each
9355 * other, or if explicitly asked to, disable large page
9356 * support for this slot
9357 */
9358 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9359 !kvm_largepages_enabled()) {
9360 unsigned long j;
9361
9362 for (j = 0; j < lpages; ++j)
92f94f1e 9363 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9364 }
9365 }
9366
21ebbeda
XG		 9367 if (kvm_page_track_create_memslot(slot, npages))
9368 goto out_free;
9369
db3fe4eb
TY		 9370 return 0;
9371
9372out_free:
d89cc617 9373 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9374 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9375 slot->arch.rmap[i] = NULL;
9376 if (i == 0)
9377 continue;
9378
548ef284 9379 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9380 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9381 }
9382 return -ENOMEM;
9383}
9384
15248258 9385void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9386{
e6dff7d1
TY		 9387 /*
9388 * memslots->generation has been incremented.
9389 * mmio generation may have reached its maximum value.
9390 */
15248258 9391 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9392}
9393
f7784b8e
MT		 9394int kvm_arch_prepare_memory_region(struct kvm *kvm,
9395 struct kvm_memory_slot *memslot,
09170a49 9396 const struct kvm_userspace_memory_region *mem,
7b6195a9 9397 enum kvm_mr_change change)
0de10343 9398{
f7784b8e
MT		 9399 return 0;
9400}
9401
88178fd4
KH		 9402static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9403 struct kvm_memory_slot *new)
9404{
9405 /* Still write protect RO slot */
9406 if (new->flags & KVM_MEM_READONLY) {
9407 kvm_mmu_slot_remove_write_access(kvm, new);
9408 return;
9409 }
9410
9411 /*
9412 * Call kvm_x86_ops dirty logging hooks when they are valid.
9413 *
9414 * kvm_x86_ops->slot_disable_log_dirty is called when:
9415 *
9416 * - KVM_MR_CREATE with dirty logging is disabled
9417 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9418 *
9419 * The reason is, in case of PML, we need to set D-bit for any slots
9420 * with dirty logging disabled in order to eliminate unnecessary GPA
9421 * logging in PML buffer (and potential PML buffer full VMEXT). This
9422 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9423 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9424 * logging disabled for memory slots.
9425 *
9426 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9427 * to dirty logging mode.
9428 *
9429 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9430 *
9431 * In case of write protect:
9432 *
9433 * Write protect all pages for dirty logging.
9434 *
9435 * All the sptes including the large sptes which point to this
9436 * slot are set to readonly. We can not create any new large
9437 * spte on this slot until the end of the logging.
9438 *
9439 * See the comments in fast_page_fault().
9440 */
9441 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9442 if (kvm_x86_ops->slot_enable_log_dirty)
9443 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9444 else
9445 kvm_mmu_slot_remove_write_access(kvm, new);
9446 } else {
9447 if (kvm_x86_ops->slot_disable_log_dirty)
9448 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9449 }
9450}
9451
f7784b8e 9452void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9453 const struct kvm_userspace_memory_region *mem,
8482644a 9454 const struct kvm_memory_slot *old,
f36f3f28 9455 const struct kvm_memory_slot *new,
8482644a 9456 enum kvm_mr_change change)
f7784b8e 9457{
48c0e4e9 9458 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9459 kvm_mmu_change_mmu_pages(kvm,
9460 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9461
3ea3b7fa
WL		 9462 /*
9463 * Dirty logging tracks sptes in 4k granularity, meaning that large
9464 * sptes have to be split. If live migration is successful, the guest
9465 * in the source machine will be destroyed and large sptes will be
9466 * created in the destination. However, if the guest continues to run
9467 * in the source machine (for example if live migration fails), small
9468 * sptes will remain around and cause bad performance.
9469 *
9470 * Scan sptes if dirty logging has been stopped, dropping those
9471 * which can be collapsed into a single large-page spte. Later
9472 * page faults will create the large-page sptes.
9473 */
9474 if ((change != KVM_MR_DELETE) &&
9475 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9476 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9477 kvm_mmu_zap_collapsible_sptes(kvm, new);
9478
c972f3b1 9479 /*
88178fd4 9480 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9481 *
88178fd4
KH		 9482 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9483 * been zapped so no dirty logging staff is needed for old slot. For
9484 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9485 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9486 *
9487 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9488 */
88178fd4 9489 if (change != KVM_MR_DELETE)
f36f3f28 9490 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9491}
1d737c8a 9492
2df72e9b 9493void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9494{
7390de1e 9495 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9496}
9497
2df72e9b
MT		 9498void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9499 struct kvm_memory_slot *slot)
9500{
ae7cd873 9501 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9502}
9503
e6c67d8c
LA		 9504static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9505{
9506 return (is_guest_mode(vcpu) &&
9507 kvm_x86_ops->guest_apic_has_interrupt &&
9508 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9509}
9510
5d9bc648
PB		 9511static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9512{
9513 if (!list_empty_careful(&vcpu->async_pf.done))
9514 return true;
9515
9516 if (kvm_apic_has_events(vcpu))
9517 return true;
9518
9519 if (vcpu->arch.pv.pv_unhalted)
9520 return true;
9521
a5f01f8e
WL		 9522 if (vcpu->arch.exception.pending)
9523 return true;
9524
47a66eed
Z		 9525 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9526 (vcpu->arch.nmi_pending &&
9527 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9528 return true;
9529
47a66eed
Z		 9530 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9531 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9532 return true;
9533
5d9bc648 9534 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9535 (kvm_cpu_has_interrupt(vcpu) ||
9536 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9537 return true;
9538
1f4b34f8
AS		 9539 if (kvm_hv_has_stimer_pending(vcpu))
9540 return true;
9541
5d9bc648
PB		 9542 return false;
9543}
9544
1d737c8a
ZX		 9545int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9546{
5d9bc648 9547 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9548}
5736199a 9549
199b5763
LM		 9550bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9551{
de63ad4c 9552 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9553}
9554
b6d33834 9555int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9556{
b6d33834 9557 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9558}
78646121
GN		 9559
9560int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9561{
9562 return kvm_x86_ops->interrupt_allowed(vcpu);
9563}
229456fc 9564
82b32774 9565unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9566{
82b32774
NA		 9567 if (is_64_bit_mode(vcpu))
9568 return kvm_rip_read(vcpu);
9569 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9570 kvm_rip_read(vcpu));
9571}
9572EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9573
82b32774
NA		 9574bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9575{
9576 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9577}
9578EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9579
94fe45da
JK		 9580unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9581{
9582 unsigned long rflags;
9583
9584 rflags = kvm_x86_ops->get_rflags(vcpu);
9585 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9586 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9587 return rflags;
9588}
9589EXPORT_SYMBOL_GPL(kvm_get_rflags);
9590
6addfc42 9591static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9592{
9593 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9594 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9595 rflags |= X86_EFLAGS_TF;
94fe45da 9596 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9597}
9598
9599void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9600{
9601 __kvm_set_rflags(vcpu, rflags);
3842d135 9602 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9603}
9604EXPORT_SYMBOL_GPL(kvm_set_rflags);
9605
56028d08
GN		 9606void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9607{
9608 int r;
9609
44dd3ffa 9610 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9611 work->wakeup_all)
56028d08
GN		 9612 return;
9613
9614 r = kvm_mmu_reload(vcpu);
9615 if (unlikely(r))
9616 return;
9617
44dd3ffa
VK		 9618 if (!vcpu->arch.mmu->direct_map &&
9619 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9620 return;
9621
44dd3ffa 9622 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9623}
9624
af585b92
GN		 9625static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9626{
9627 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9628}
9629
9630static inline u32 kvm_async_pf_next_probe(u32 key)
9631{
9632 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9633}
9634
9635static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9636{
9637 u32 key = kvm_async_pf_hash_fn(gfn);
9638
9639 while (vcpu->arch.apf.gfns[key] != ~0)
9640 key = kvm_async_pf_next_probe(key);
9641
9642 vcpu->arch.apf.gfns[key] = gfn;
9643}
9644
9645static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9646{
9647 int i;
9648 u32 key = kvm_async_pf_hash_fn(gfn);
9649
9650 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9651 (vcpu->arch.apf.gfns[key] != gfn &&
9652 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9653 key = kvm_async_pf_next_probe(key);
9654
9655 return key;
9656}
9657
9658bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9659{
9660 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9661}
9662
9663static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9664{
9665 u32 i, j, k;
9666
9667 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9668 while (true) {
9669 vcpu->arch.apf.gfns[i] = ~0;
9670 do {
9671 j = kvm_async_pf_next_probe(j);
9672 if (vcpu->arch.apf.gfns[j] == ~0)
9673 return;
9674 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9675 /*
9676 * k lies cyclically in ]i,j]
9677 * | i.k.j |
9678 * |....j i.k.| or |.k..j i...|
9679 */
9680 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9681 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9682 i = j;
9683 }
9684}
9685
7c90705b
GN		 9686static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9687{
4e335d9e
PB		 9688
9689 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9690 sizeof(val));
7c90705b
GN		 9691}
9692
9a6e7c39
WL		 9693static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9694{
9695
9696 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9697 sizeof(u32));
9698}
9699
af585b92
GN		 9700void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9701 struct kvm_async_pf *work)
9702{
6389ee94
AK		 9703 struct x86_exception fault;
9704
7c90705b 9705 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9706 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9707
9708 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9709 (vcpu->arch.apf.send_user_only &&
9710 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9711 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9712 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9713 fault.vector = PF_VECTOR;
9714 fault.error_code_valid = true;
9715 fault.error_code = 0;
9716 fault.nested_page_fault = false;
9717 fault.address = work->arch.token;
adfe20fb 9718 fault.async_page_fault = true;
6389ee94 9719 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9720 }
af585b92
GN		 9721}
9722
9723void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9724 struct kvm_async_pf *work)
9725{
6389ee94 9726 struct x86_exception fault;
9a6e7c39 9727 u32 val;
6389ee94 9728
f2e10669 9729 if (work->wakeup_all)
7c90705b
GN		 9730 work->arch.token = ~0; /* broadcast wakeup */
9731 else
9732 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9733 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9734
9a6e7c39
WL		 9735 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9736 !apf_get_user(vcpu, &val)) {
9737 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9738 vcpu->arch.exception.pending &&
9739 vcpu->arch.exception.nr == PF_VECTOR &&
9740 !apf_put_user(vcpu, 0)) {
9741 vcpu->arch.exception.injected = false;
9742 vcpu->arch.exception.pending = false;
9743 vcpu->arch.exception.nr = 0;
9744 vcpu->arch.exception.has_error_code = false;
9745 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9746 vcpu->arch.exception.has_payload = false;
9747 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9748 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9749 fault.vector = PF_VECTOR;
9750 fault.error_code_valid = true;
9751 fault.error_code = 0;
9752 fault.nested_page_fault = false;
9753 fault.address = work->arch.token;
9754 fault.async_page_fault = true;
9755 kvm_inject_page_fault(vcpu, &fault);
9756 }
7c90705b 9757 }
e6d53e3b 9758 vcpu->arch.apf.halted = false;
a4fa1635 9759 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9760}
9761
9762bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9763{
9764 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9765 return true;
9766 else
9bc1f09f 9767 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9768}
9769
5544eb9b
PB		 9770void kvm_arch_start_assignment(struct kvm *kvm)
9771{
9772 atomic_inc(&kvm->arch.assigned_device_count);
9773}
9774EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9775
9776void kvm_arch_end_assignment(struct kvm *kvm)
9777{
9778 atomic_dec(&kvm->arch.assigned_device_count);
9779}
9780EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9781
9782bool kvm_arch_has_assigned_device(struct kvm *kvm)
9783{
9784 return atomic_read(&kvm->arch.assigned_device_count);
9785}
9786EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9787
e0f0bbc5
AW		 9788void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9789{
9790 atomic_inc(&kvm->arch.noncoherent_dma_count);
9791}
9792EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9793
9794void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9795{
9796 atomic_dec(&kvm->arch.noncoherent_dma_count);
9797}
9798EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9799
9800bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9801{
9802 return atomic_read(&kvm->arch.noncoherent_dma_count);
9803}
9804EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9805
14717e20
AW		 9806bool kvm_arch_has_irq_bypass(void)
9807{
9808 return kvm_x86_ops->update_pi_irte != NULL;
9809}
9810
87276880
FW		 9811int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9812 struct irq_bypass_producer *prod)
9813{
9814 struct kvm_kernel_irqfd *irqfd =
9815 container_of(cons, struct kvm_kernel_irqfd, consumer);
9816
14717e20 9817 irqfd->producer = prod;
87276880 9818
14717e20
AW		 9819 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9820 prod->irq, irqfd->gsi, 1);
87276880
FW		 9821}
9822
9823void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9824 struct irq_bypass_producer *prod)
9825{
9826 int ret;
9827 struct kvm_kernel_irqfd *irqfd =
9828 container_of(cons, struct kvm_kernel_irqfd, consumer);
9829
87276880
FW		 9830 WARN_ON(irqfd->producer != prod);
9831 irqfd->producer = NULL;
9832
9833 /*
9834 * When producer of consumer is unregistered, we change back to
9835 * remapped mode, so we can re-use the current implementation
bb3541f1 9836 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9837 * int this case doesn't want to receive the interrupts.
9838 */
9839 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9840 if (ret)
9841 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9842 " fails: %d\n", irqfd->consumer.token, ret);
9843}
9844
9845int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9846 uint32_t guest_irq, bool set)
9847{
9848 if (!kvm_x86_ops->update_pi_irte)
9849 return -EINVAL;
9850
9851 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9852}
9853
52004014
FW		 9854bool kvm_vector_hashing_enabled(void)
9855{
9856 return vector_hashing;
9857}
9858EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9859
229456fc 9860EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9861EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9862EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9863EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9864EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9865EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9866EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9867EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9868EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9869EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9870EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9871EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9872EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9873EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9874EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9875EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9876EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9877EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9878EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)