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perf: Enhance perf to allow for guest statistic collection from host
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
aec51dc4
AK		 43#include <trace/events/kvm.h>
44#undef TRACE_INCLUDE_FILE
229456fc
MT		 45#define CREATE_TRACE_POINTS
46#include "trace.h"
043405e1 47
24f1e32c 48#include <asm/debugreg.h>
043405e1 49#include <asm/uaccess.h>
d825ed0a 50#include <asm/msr.h>
a5f61300 51#include <asm/desc.h>
0bed3b56 52#include <asm/mtrr.h>
890ca9ae 53#include <asm/mce.h>
043405e1 54
313a3dc7 55#define MAX_IO_MSRS 256
a03490ed
CO		 56#define CR0_RESERVED_BITS \
57 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
58 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
59 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
60#define CR4_RESERVED_BITS \
61 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
62 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
63 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
64 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
65
66#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 67
68#define KVM_MAX_MCE_BANKS 32
69#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
76static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
77#else
78static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
79#endif
313a3dc7 80
ba1389b7
AK		 81#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 83
cb142eb7 84static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 85static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
ed85c068
AP		 91int ignore_msrs = 0;
92module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
93
18863bdd
AK		 94#define KVM_NR_SHARED_MSRS 16
95
96struct kvm_shared_msrs_global {
97 int nr;
2bf78fa7 98 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 99};
100
101struct kvm_shared_msrs {
102 struct user_return_notifier urn;
103 bool registered;
2bf78fa7
SY		 104 struct kvm_shared_msr_values {
105 u64 host;
106 u64 curr;
107 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 108};
109
110static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
111static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
112
417bc304 113struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 114 { "pf_fixed", VCPU_STAT(pf_fixed) },
115 { "pf_guest", VCPU_STAT(pf_guest) },
116 { "tlb_flush", VCPU_STAT(tlb_flush) },
117 { "invlpg", VCPU_STAT(invlpg) },
118 { "exits", VCPU_STAT(exits) },
119 { "io_exits", VCPU_STAT(io_exits) },
120 { "mmio_exits", VCPU_STAT(mmio_exits) },
121 { "signal_exits", VCPU_STAT(signal_exits) },
122 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 123 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 124 { "halt_exits", VCPU_STAT(halt_exits) },
125 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 126 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 127 { "request_irq", VCPU_STAT(request_irq_exits) },
128 { "irq_exits", VCPU_STAT(irq_exits) },
129 { "host_state_reload", VCPU_STAT(host_state_reload) },
130 { "efer_reload", VCPU_STAT(efer_reload) },
131 { "fpu_reload", VCPU_STAT(fpu_reload) },
132 { "insn_emulation", VCPU_STAT(insn_emulation) },
133 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 134 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 135 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 136 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
137 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
138 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
139 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
140 { "mmu_flooded", VM_STAT(mmu_flooded) },
141 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 142 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 143 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 144 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 145 { "largepages", VM_STAT(lpages) },
417bc304
HB		 146 { NULL }
147};
148
18863bdd
AK		 149static void kvm_on_user_return(struct user_return_notifier *urn)
150{
151 unsigned slot;
18863bdd
AK		 152 struct kvm_shared_msrs *locals
153 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 154 struct kvm_shared_msr_values *values;
18863bdd
AK		 155
156 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 157 values = &locals->values[slot];
158 if (values->host != values->curr) {
159 wrmsrl(shared_msrs_global.msrs[slot], values->host);
160 values->curr = values->host;
18863bdd
AK		 161 }
162 }
163 locals->registered = false;
164 user_return_notifier_unregister(urn);
165}
166
2bf78fa7 167static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 168{
2bf78fa7 169 struct kvm_shared_msrs *smsr;
18863bdd
AK		 170 u64 value;
171
2bf78fa7
SY		 172 smsr = &__get_cpu_var(shared_msrs);
173 /* only read, and nobody should modify it at this time,
174 * so don't need lock */
175 if (slot >= shared_msrs_global.nr) {
176 printk(KERN_ERR "kvm: invalid MSR slot!");
177 return;
178 }
179 rdmsrl_safe(msr, &value);
180 smsr->values[slot].host = value;
181 smsr->values[slot].curr = value;
182}
183
184void kvm_define_shared_msr(unsigned slot, u32 msr)
185{
18863bdd
AK		 186 if (slot >= shared_msrs_global.nr)
187 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 188 shared_msrs_global.msrs[slot] = msr;
189 /* we need ensured the shared_msr_global have been updated */
190 smp_wmb();
18863bdd
AK		 191}
192EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
193
194static void kvm_shared_msr_cpu_online(void)
195{
196 unsigned i;
18863bdd
AK		 197
198 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 199 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 200}
201
d5696725 202void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 203{
204 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
205
2bf78fa7 206 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 207 return;
2bf78fa7
SY		 208 smsr->values[slot].curr = value;
209 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 210 if (!smsr->registered) {
211 smsr->urn.on_user_return = kvm_on_user_return;
212 user_return_notifier_register(&smsr->urn);
213 smsr->registered = true;
214 }
215}
216EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
217
3548bab5
AK		 218static void drop_user_return_notifiers(void *ignore)
219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
222 if (smsr->registered)
223 kvm_on_user_return(&smsr->urn);
224}
225
5fb76f9b
CO		 226unsigned long segment_base(u16 selector)
227{
228 struct descriptor_table gdt;
a5f61300 229 struct desc_struct *d;
5fb76f9b
CO		 230 unsigned long table_base;
231 unsigned long v;
232
233 if (selector == 0)
234 return 0;
235
b792c344 236 kvm_get_gdt(&gdt);
5fb76f9b
CO		 237 table_base = gdt.base;
238
239 if (selector & 4) { /* from ldt */
b792c344 240 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 241
5fb76f9b
CO		 242 table_base = segment_base(ldt_selector);
243 }
a5f61300 244 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 245 v = get_desc_base(d);
5fb76f9b 246#ifdef CONFIG_X86_64
a5f61300
AK		 247 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
248 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 249#endif
250 return v;
251}
252EXPORT_SYMBOL_GPL(segment_base);
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
256 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 257 return vcpu->arch.apic_base;
6866b83e 258 else
ad312c7c 259 return vcpu->arch.apic_base;
6866b83e
CO		 260}
261EXPORT_SYMBOL_GPL(kvm_get_apic_base);
262
263void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
264{
265 /* TODO: reserve bits check */
266 if (irqchip_in_kernel(vcpu->kvm))
267 kvm_lapic_set_base(vcpu, data);
268 else
ad312c7c 269 vcpu->arch.apic_base = data;
6866b83e
CO		 270}
271EXPORT_SYMBOL_GPL(kvm_set_apic_base);
272
3fd28fce
ED		 273#define EXCPT_BENIGN 0
274#define EXCPT_CONTRIBUTORY 1
275#define EXCPT_PF 2
276
277static int exception_class(int vector)
278{
279 switch (vector) {
280 case PF_VECTOR:
281 return EXCPT_PF;
282 case DE_VECTOR:
283 case TS_VECTOR:
284 case NP_VECTOR:
285 case SS_VECTOR:
286 case GP_VECTOR:
287 return EXCPT_CONTRIBUTORY;
288 default:
289 break;
290 }
291 return EXCPT_BENIGN;
292}
293
294static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
295 unsigned nr, bool has_error, u32 error_code)
296{
297 u32 prev_nr;
298 int class1, class2;
299
300 if (!vcpu->arch.exception.pending) {
301 queue:
302 vcpu->arch.exception.pending = true;
303 vcpu->arch.exception.has_error_code = has_error;
304 vcpu->arch.exception.nr = nr;
305 vcpu->arch.exception.error_code = error_code;
306 return;
307 }
308
309 /* to check exception */
310 prev_nr = vcpu->arch.exception.nr;
311 if (prev_nr == DF_VECTOR) {
312 /* triple fault -> shutdown */
313 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
314 return;
315 }
316 class1 = exception_class(prev_nr);
317 class2 = exception_class(nr);
318 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
319 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
320 /* generate double fault per SDM Table 5-5 */
321 vcpu->arch.exception.pending = true;
322 vcpu->arch.exception.has_error_code = true;
323 vcpu->arch.exception.nr = DF_VECTOR;
324 vcpu->arch.exception.error_code = 0;
325 } else
326 /* replace previous exception with a new one in a hope
327 that instruction re-execution will regenerate lost
328 exception */
329 goto queue;
330}
331
298101da
AK		 332void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
333{
3fd28fce 334 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 335}
336EXPORT_SYMBOL_GPL(kvm_queue_exception);
337
c3c91fee
AK		 338void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
339 u32 error_code)
340{
341 ++vcpu->stat.pf_guest;
ad312c7c 342 vcpu->arch.cr2 = addr;
c3c91fee
AK		 343 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
344}
345
3419ffc8
SY		 346void kvm_inject_nmi(struct kvm_vcpu *vcpu)
347{
348 vcpu->arch.nmi_pending = 1;
349}
350EXPORT_SYMBOL_GPL(kvm_inject_nmi);
351
298101da
AK		 352void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
353{
3fd28fce 354 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 355}
356EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
357
0a79b009
AK		 358/*
359 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
360 * a #GP and return false.
361 */
362bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 363{
0a79b009
AK		 364 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
365 return true;
366 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
367 return false;
298101da 368}
0a79b009 369EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 370
a03490ed
CO		 371/*
372 * Load the pae pdptrs. Return true is they are all valid.
373 */
374int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
375{
376 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
377 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
378 int i;
379 int ret;
ad312c7c 380 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 381
a03490ed
CO		 382 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
383 offset * sizeof(u64), sizeof(pdpte));
384 if (ret < 0) {
385 ret = 0;
386 goto out;
387 }
388 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 389 if (is_present_gpte(pdpte[i]) &&
20c466b5 390 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 391 ret = 0;
392 goto out;
393 }
394 }
395 ret = 1;
396
ad312c7c 397 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_avail);
400 __set_bit(VCPU_EXREG_PDPTR,
401 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 402out:
a03490ed
CO		 403
404 return ret;
405}
cc4b6871 406EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 407
d835dfec
AK		 408static bool pdptrs_changed(struct kvm_vcpu *vcpu)
409{
ad312c7c 410 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 411 bool changed = true;
412 int r;
413
414 if (is_long_mode(vcpu) || !is_pae(vcpu))
415 return false;
416
6de4f3ad
AK		 417 if (!test_bit(VCPU_EXREG_PDPTR,
418 (unsigned long *)&vcpu->arch.regs_avail))
419 return true;
420
ad312c7c 421 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 422 if (r < 0)
423 goto out;
ad312c7c 424 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 425out:
d835dfec
AK		 426
427 return changed;
428}
429
2d3ad1f4 430void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 431{
f9a48e6a
AK		 432 cr0 |= X86_CR0_ET;
433
ab344828
GN		 434#ifdef CONFIG_X86_64
435 if (cr0 & 0xffffffff00000000UL) {
a03490ed 436 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
4d4ec087 437 cr0, kvm_read_cr0(vcpu));
c1a5d4f9 438 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 439 return;
440 }
ab344828
GN		 441#endif
442
443 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 444
445 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
446 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 447 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 448 return;
449 }
450
451 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
452 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
453 "and a clear PE flag\n");
c1a5d4f9 454 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 455 return;
456 }
457
458 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
459#ifdef CONFIG_X86_64
f6801dff 460 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 461 int cs_db, cs_l;
462
463 if (!is_pae(vcpu)) {
464 printk(KERN_DEBUG "set_cr0: #GP, start paging "
465 "in long mode while PAE is disabled\n");
c1a5d4f9 466 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 467 return;
468 }
469 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
470 if (cs_l) {
471 printk(KERN_DEBUG "set_cr0: #GP, start paging "
472 "in long mode while CS.L == 1\n");
c1a5d4f9 473 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 474 return;
475
476 }
477 } else
478#endif
ad312c7c 479 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 480 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
481 "reserved bits\n");
c1a5d4f9 482 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 483 return;
484 }
485
486 }
487
488 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 489 vcpu->arch.cr0 = cr0;
a03490ed 490
a03490ed 491 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 492 return;
493}
2d3ad1f4 494EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 495
2d3ad1f4 496void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 497{
4d4ec087 498 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 499}
2d3ad1f4 500EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 501
2d3ad1f4 502void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 503{
fc78f519 504 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 505 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
506
a03490ed
CO		 507 if (cr4 & CR4_RESERVED_BITS) {
508 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 509 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 510 return;
511 }
512
513 if (is_long_mode(vcpu)) {
514 if (!(cr4 & X86_CR4_PAE)) {
515 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
516 "in long mode\n");
c1a5d4f9 517 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 518 return;
519 }
a2edf57f
AK		 520 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
521 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 522 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 523 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 524 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 525 return;
526 }
527
528 if (cr4 & X86_CR4_VMXE) {
529 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 530 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 531 return;
532 }
533 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 534 vcpu->arch.cr4 = cr4;
5a41accd 535 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 536 kvm_mmu_reset_context(vcpu);
a03490ed 537}
2d3ad1f4 538EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 539
2d3ad1f4 540void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 541{
ad312c7c 542 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 543 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 544 kvm_mmu_flush_tlb(vcpu);
545 return;
546 }
547
a03490ed
CO		 548 if (is_long_mode(vcpu)) {
549 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
550 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 551 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 552 return;
553 }
554 } else {
555 if (is_pae(vcpu)) {
556 if (cr3 & CR3_PAE_RESERVED_BITS) {
557 printk(KERN_DEBUG
558 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 559 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 560 return;
561 }
562 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
563 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
564 "reserved bits\n");
c1a5d4f9 565 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 566 return;
567 }
568 }
569 /*
570 * We don't check reserved bits in nonpae mode, because
571 * this isn't enforced, and VMware depends on this.
572 */
573 }
574
a03490ed
CO		 575 /*
576 * Does the new cr3 value map to physical memory? (Note, we
577 * catch an invalid cr3 even in real-mode, because it would
578 * cause trouble later on when we turn on paging anyway.)
579 *
580 * A real CPU would silently accept an invalid cr3 and would
581 * attempt to use it - with largely undefined (and often hard
582 * to debug) behavior on the guest side.
583 */
584 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 585 kvm_inject_gp(vcpu, 0);
a03490ed 586 else {
ad312c7c
ZX		 587 vcpu->arch.cr3 = cr3;
588 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 589 }
a03490ed 590}
2d3ad1f4 591EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 592
2d3ad1f4 593void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 594{
595 if (cr8 & CR8_RESERVED_BITS) {
596 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 597 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 598 return;
599 }
600 if (irqchip_in_kernel(vcpu->kvm))
601 kvm_lapic_set_tpr(vcpu, cr8);
602 else
ad312c7c 603 vcpu->arch.cr8 = cr8;
a03490ed 604}
2d3ad1f4 605EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 606
2d3ad1f4 607unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 608{
609 if (irqchip_in_kernel(vcpu->kvm))
610 return kvm_lapic_get_cr8(vcpu);
611 else
ad312c7c 612 return vcpu->arch.cr8;
a03490ed 613}
2d3ad1f4 614EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 615
d8017474
AG		 616static inline u32 bit(int bitno)
617{
618 return 1 << (bitno & 31);
619}
620
043405e1
CO		 621/*
622 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
623 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
624 *
625 * This list is modified at module load time to reflect the
e3267cbb
GC		 626 * capabilities of the host cpu. This capabilities test skips MSRs that are
627 * kvm-specific. Those are put in the beginning of the list.
043405e1 628 */
e3267cbb 629
10388a07 630#define KVM_SAVE_MSRS_BEGIN 5
043405e1 631static u32 msrs_to_save[] = {
e3267cbb 632 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 633 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 634 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 635 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
636 MSR_K6_STAR,
637#ifdef CONFIG_X86_64
638 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
639#endif
e3267cbb 640 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 641};
642
643static unsigned num_msrs_to_save;
644
645static u32 emulated_msrs[] = {
646 MSR_IA32_MISC_ENABLE,
647};
648
15c4a640
CO		 649static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
650{
f2b4b7dd 651 if (efer & efer_reserved_bits) {
15c4a640
CO		 652 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
653 efer);
c1a5d4f9 654 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 655 return;
656 }
657
658 if (is_paging(vcpu)
f6801dff 659 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 660 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 661 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 662 return;
663 }
664
1b2fd70c
AG		 665 if (efer & EFER_FFXSR) {
666 struct kvm_cpuid_entry2 *feat;
667
668 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
669 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
670 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
671 kvm_inject_gp(vcpu, 0);
672 return;
673 }
674 }
675
d8017474
AG		 676 if (efer & EFER_SVME) {
677 struct kvm_cpuid_entry2 *feat;
678
679 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
680 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
681 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
682 kvm_inject_gp(vcpu, 0);
683 return;
684 }
685 }
686
15c4a640
CO		 687 kvm_x86_ops->set_efer(vcpu, efer);
688
689 efer &= ~EFER_LMA;
f6801dff 690 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 691
f6801dff 692 vcpu->arch.efer = efer;
9645bb56
AK		 693
694 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
695 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 696}
697
f2b4b7dd
JR		 698void kvm_enable_efer_bits(u64 mask)
699{
700 efer_reserved_bits &= ~mask;
701}
702EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
703
704
15c4a640
CO		 705/*
706 * Writes msr value into into the appropriate "register".
707 * Returns 0 on success, non-0 otherwise.
708 * Assumes vcpu_load() was already called.
709 */
710int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
711{
712 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
713}
714
313a3dc7
CO		 715/*
716 * Adapt set_msr() to msr_io()'s calling convention
717 */
718static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
719{
720 return kvm_set_msr(vcpu, index, *data);
721}
722
18068523
GOC		 723static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
724{
725 static int version;
50d0a0f9 726 struct pvclock_wall_clock wc;
923de3cf 727 struct timespec boot;
18068523
GOC		 728
729 if (!wall_clock)
730 return;
731
732 version++;
733
18068523
GOC		 734 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
735
50d0a0f9
GH		 736 /*
737 * The guest calculates current wall clock time by adding
738 * system time (updated by kvm_write_guest_time below) to the
739 * wall clock specified here. guest system time equals host
740 * system time for us, thus we must fill in host boot time here.
741 */
923de3cf 742 getboottime(&boot);
50d0a0f9
GH		 743
744 wc.sec = boot.tv_sec;
745 wc.nsec = boot.tv_nsec;
746 wc.version = version;
18068523
GOC		 747
748 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
749
750 version++;
751 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 752}
753
50d0a0f9
GH		 754static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
755{
756 uint32_t quotient, remainder;
757
758 /* Don't try to replace with do_div(), this one calculates
759 * "(dividend << 32) / divisor" */
760 __asm__ ( "divl %4"
761 : "=a" (quotient), "=d" (remainder)
762 : "0" (0), "1" (dividend), "r" (divisor) );
763 return quotient;
764}
765
766static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
767{
768 uint64_t nsecs = 1000000000LL;
769 int32_t shift = 0;
770 uint64_t tps64;
771 uint32_t tps32;
772
773 tps64 = tsc_khz * 1000LL;
774 while (tps64 > nsecs*2) {
775 tps64 >>= 1;
776 shift--;
777 }
778
779 tps32 = (uint32_t)tps64;
780 while (tps32 <= (uint32_t)nsecs) {
781 tps32 <<= 1;
782 shift++;
783 }
784
785 hv_clock->tsc_shift = shift;
786 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
787
788 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 789 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 790 hv_clock->tsc_to_system_mul);
791}
792
c8076604
GH		 793static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
794
18068523
GOC		 795static void kvm_write_guest_time(struct kvm_vcpu *v)
796{
797 struct timespec ts;
798 unsigned long flags;
799 struct kvm_vcpu_arch *vcpu = &v->arch;
800 void *shared_kaddr;
463656c0 801 unsigned long this_tsc_khz;
18068523
GOC		 802
803 if ((!vcpu->time_page))
804 return;
805
463656c0
AK		 806 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
807 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
808 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
809 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 810 }
463656c0 811 put_cpu_var(cpu_tsc_khz);
50d0a0f9 812
18068523
GOC		 813 /* Keep irq disabled to prevent changes to the clock */
814 local_irq_save(flags);
af24a4e4 815 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 816 ktime_get_ts(&ts);
923de3cf 817 monotonic_to_bootbased(&ts);
18068523
GOC		 818 local_irq_restore(flags);
819
820 /* With all the info we got, fill in the values */
821
822 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 823 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
824
18068523
GOC		 825 /*
826 * The interface expects us to write an even number signaling that the
827 * update is finished. Since the guest won't see the intermediate
50d0a0f9 828 * state, we just increase by 2 at the end.
18068523 829 */
50d0a0f9 830 vcpu->hv_clock.version += 2;
18068523
GOC		 831
832 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
833
834 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 835 sizeof(vcpu->hv_clock));
18068523
GOC		 836
837 kunmap_atomic(shared_kaddr, KM_USER0);
838
839 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
840}
841
c8076604
GH		 842static int kvm_request_guest_time_update(struct kvm_vcpu *v)
843{
844 struct kvm_vcpu_arch *vcpu = &v->arch;
845
846 if (!vcpu->time_page)
847 return 0;
848 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
849 return 1;
850}
851
9ba075a6
AK		 852static bool msr_mtrr_valid(unsigned msr)
853{
854 switch (msr) {
855 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
856 case MSR_MTRRfix64K_00000:
857 case MSR_MTRRfix16K_80000:
858 case MSR_MTRRfix16K_A0000:
859 case MSR_MTRRfix4K_C0000:
860 case MSR_MTRRfix4K_C8000:
861 case MSR_MTRRfix4K_D0000:
862 case MSR_MTRRfix4K_D8000:
863 case MSR_MTRRfix4K_E0000:
864 case MSR_MTRRfix4K_E8000:
865 case MSR_MTRRfix4K_F0000:
866 case MSR_MTRRfix4K_F8000:
867 case MSR_MTRRdefType:
868 case MSR_IA32_CR_PAT:
869 return true;
870 case 0x2f8:
871 return true;
872 }
873 return false;
874}
875
d6289b93
MT		 876static bool valid_pat_type(unsigned t)
877{
878 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
879}
880
881static bool valid_mtrr_type(unsigned t)
882{
883 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
884}
885
886static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
887{
888 int i;
889
890 if (!msr_mtrr_valid(msr))
891 return false;
892
893 if (msr == MSR_IA32_CR_PAT) {
894 for (i = 0; i < 8; i++)
895 if (!valid_pat_type((data >> (i * 8)) & 0xff))
896 return false;
897 return true;
898 } else if (msr == MSR_MTRRdefType) {
899 if (data & ~0xcff)
900 return false;
901 return valid_mtrr_type(data & 0xff);
902 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
903 for (i = 0; i < 8 ; i++)
904 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
905 return false;
906 return true;
907 }
908
909 /* variable MTRRs */
910 return valid_mtrr_type(data & 0xff);
911}
912
9ba075a6
AK		 913static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
914{
0bed3b56
SY		 915 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
916
d6289b93 917 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 918 return 1;
919
0bed3b56
SY		 920 if (msr == MSR_MTRRdefType) {
921 vcpu->arch.mtrr_state.def_type = data;
922 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
923 } else if (msr == MSR_MTRRfix64K_00000)
924 p[0] = data;
925 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
926 p[1 + msr - MSR_MTRRfix16K_80000] = data;
927 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
928 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
929 else if (msr == MSR_IA32_CR_PAT)
930 vcpu->arch.pat = data;
931 else { /* Variable MTRRs */
932 int idx, is_mtrr_mask;
933 u64 *pt;
934
935 idx = (msr - 0x200) / 2;
936 is_mtrr_mask = msr - 0x200 - 2 * idx;
937 if (!is_mtrr_mask)
938 pt =
939 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
940 else
941 pt =
942 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
943 *pt = data;
944 }
945
946 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 947 return 0;
948}
15c4a640 949
890ca9ae 950static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 951{
890ca9ae
HY		 952 u64 mcg_cap = vcpu->arch.mcg_cap;
953 unsigned bank_num = mcg_cap & 0xff;
954
15c4a640 955 switch (msr) {
15c4a640 956 case MSR_IA32_MCG_STATUS:
890ca9ae 957 vcpu->arch.mcg_status = data;
15c4a640 958 break;
c7ac679c 959 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 960 if (!(mcg_cap & MCG_CTL_P))
961 return 1;
962 if (data != 0 && data != ~(u64)0)
963 return -1;
964 vcpu->arch.mcg_ctl = data;
965 break;
966 default:
967 if (msr >= MSR_IA32_MC0_CTL &&
968 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
969 u32 offset = msr - MSR_IA32_MC0_CTL;
970 /* only 0 or all 1s can be written to IA32_MCi_CTL */
971 if ((offset & 0x3) == 0 &&
972 data != 0 && data != ~(u64)0)
973 return -1;
974 vcpu->arch.mce_banks[offset] = data;
975 break;
976 }
977 return 1;
978 }
979 return 0;
980}
981
ffde22ac
ES		 982static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
983{
984 struct kvm *kvm = vcpu->kvm;
985 int lm = is_long_mode(vcpu);
986 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
987 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
988 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
989 : kvm->arch.xen_hvm_config.blob_size_32;
990 u32 page_num = data & ~PAGE_MASK;
991 u64 page_addr = data & PAGE_MASK;
992 u8 *page;
993 int r;
994
995 r = -E2BIG;
996 if (page_num >= blob_size)
997 goto out;
998 r = -ENOMEM;
999 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1000 if (!page)
1001 goto out;
1002 r = -EFAULT;
1003 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1004 goto out_free;
1005 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1006 goto out_free;
1007 r = 0;
1008out_free:
1009 kfree(page);
1010out:
1011 return r;
1012}
1013
55cd8e5a
GN		 1014static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1015{
1016 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1017}
1018
1019static bool kvm_hv_msr_partition_wide(u32 msr)
1020{
1021 bool r = false;
1022 switch (msr) {
1023 case HV_X64_MSR_GUEST_OS_ID:
1024 case HV_X64_MSR_HYPERCALL:
1025 r = true;
1026 break;
1027 }
1028
1029 return r;
1030}
1031
1032static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1033{
1034 struct kvm *kvm = vcpu->kvm;
1035
1036 switch (msr) {
1037 case HV_X64_MSR_GUEST_OS_ID:
1038 kvm->arch.hv_guest_os_id = data;
1039 /* setting guest os id to zero disables hypercall page */
1040 if (!kvm->arch.hv_guest_os_id)
1041 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1042 break;
1043 case HV_X64_MSR_HYPERCALL: {
1044 u64 gfn;
1045 unsigned long addr;
1046 u8 instructions[4];
1047
1048 /* if guest os id is not set hypercall should remain disabled */
1049 if (!kvm->arch.hv_guest_os_id)
1050 break;
1051 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1052 kvm->arch.hv_hypercall = data;
1053 break;
1054 }
1055 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1056 addr = gfn_to_hva(kvm, gfn);
1057 if (kvm_is_error_hva(addr))
1058 return 1;
1059 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1060 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1061 if (copy_to_user((void __user *)addr, instructions, 4))
1062 return 1;
1063 kvm->arch.hv_hypercall = data;
1064 break;
1065 }
1066 default:
1067 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1068 "data 0x%llx\n", msr, data);
1069 return 1;
1070 }
1071 return 0;
1072}
1073
1074static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1075{
10388a07
GN		 1076 switch (msr) {
1077 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1078 unsigned long addr;
55cd8e5a 1079
10388a07
GN		 1080 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1081 vcpu->arch.hv_vapic = data;
1082 break;
1083 }
1084 addr = gfn_to_hva(vcpu->kvm, data >>
1085 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1086 if (kvm_is_error_hva(addr))
1087 return 1;
1088 if (clear_user((void __user *)addr, PAGE_SIZE))
1089 return 1;
1090 vcpu->arch.hv_vapic = data;
1091 break;
1092 }
1093 case HV_X64_MSR_EOI:
1094 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1095 case HV_X64_MSR_ICR:
1096 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1097 case HV_X64_MSR_TPR:
1098 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1099 default:
1100 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1101 "data 0x%llx\n", msr, data);
1102 return 1;
1103 }
1104
1105 return 0;
55cd8e5a
GN		 1106}
1107
15c4a640
CO		 1108int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1109{
1110 switch (msr) {
15c4a640
CO		 1111 case MSR_EFER:
1112 set_efer(vcpu, data);
1113 break;
8f1589d9
AP		 1114 case MSR_K7_HWCR:
1115 data &= ~(u64)0x40; /* ignore flush filter disable */
1116 if (data != 0) {
1117 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1118 data);
1119 return 1;
1120 }
15c4a640 1121 break;
f7c6d140
AP		 1122 case MSR_FAM10H_MMIO_CONF_BASE:
1123 if (data != 0) {
1124 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1125 "0x%llx\n", data);
1126 return 1;
1127 }
15c4a640 1128 break;
c323c0e5 1129 case MSR_AMD64_NB_CFG:
c7ac679c 1130 break;
b5e2fec0
AG		 1131 case MSR_IA32_DEBUGCTLMSR:
1132 if (!data) {
1133 /* We support the non-activated case already */
1134 break;
1135 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1136 /* Values other than LBR and BTF are vendor-specific,
1137 thus reserved and should throw a #GP */
1138 return 1;
1139 }
1140 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1141 __func__, data);
1142 break;
15c4a640
CO		 1143 case MSR_IA32_UCODE_REV:
1144 case MSR_IA32_UCODE_WRITE:
61a6bd67 1145 case MSR_VM_HSAVE_PA:
6098ca93 1146 case MSR_AMD64_PATCH_LOADER:
15c4a640 1147 break;
9ba075a6
AK		 1148 case 0x200 ... 0x2ff:
1149 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1150 case MSR_IA32_APICBASE:
1151 kvm_set_apic_base(vcpu, data);
1152 break;
0105d1a5
GN		 1153 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1154 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1155 case MSR_IA32_MISC_ENABLE:
ad312c7c 1156 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1157 break;
18068523
GOC		 1158 case MSR_KVM_WALL_CLOCK:
1159 vcpu->kvm->arch.wall_clock = data;
1160 kvm_write_wall_clock(vcpu->kvm, data);
1161 break;
1162 case MSR_KVM_SYSTEM_TIME: {
1163 if (vcpu->arch.time_page) {
1164 kvm_release_page_dirty(vcpu->arch.time_page);
1165 vcpu->arch.time_page = NULL;
1166 }
1167
1168 vcpu->arch.time = data;
1169
1170 /* we verify if the enable bit is set... */
1171 if (!(data & 1))
1172 break;
1173
1174 /* ...but clean it before doing the actual write */
1175 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1176
18068523
GOC		 1177 vcpu->arch.time_page =
1178 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1179
1180 if (is_error_page(vcpu->arch.time_page)) {
1181 kvm_release_page_clean(vcpu->arch.time_page);
1182 vcpu->arch.time_page = NULL;
1183 }
1184
c8076604 1185 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1186 break;
1187 }
890ca9ae
HY		 1188 case MSR_IA32_MCG_CTL:
1189 case MSR_IA32_MCG_STATUS:
1190 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1191 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1192
1193 /* Performance counters are not protected by a CPUID bit,
1194 * so we should check all of them in the generic path for the sake of
1195 * cross vendor migration.
1196 * Writing a zero into the event select MSRs disables them,
1197 * which we perfectly emulate ;-). Any other value should be at least
1198 * reported, some guests depend on them.
1199 */
1200 case MSR_P6_EVNTSEL0:
1201 case MSR_P6_EVNTSEL1:
1202 case MSR_K7_EVNTSEL0:
1203 case MSR_K7_EVNTSEL1:
1204 case MSR_K7_EVNTSEL2:
1205 case MSR_K7_EVNTSEL3:
1206 if (data != 0)
1207 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1208 "0x%x data 0x%llx\n", msr, data);
1209 break;
1210 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1211 * so we ignore writes to make it happy.
1212 */
1213 case MSR_P6_PERFCTR0:
1214 case MSR_P6_PERFCTR1:
1215 case MSR_K7_PERFCTR0:
1216 case MSR_K7_PERFCTR1:
1217 case MSR_K7_PERFCTR2:
1218 case MSR_K7_PERFCTR3:
1219 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1220 "0x%x data 0x%llx\n", msr, data);
1221 break;
55cd8e5a
GN		 1222 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1223 if (kvm_hv_msr_partition_wide(msr)) {
1224 int r;
1225 mutex_lock(&vcpu->kvm->lock);
1226 r = set_msr_hyperv_pw(vcpu, msr, data);
1227 mutex_unlock(&vcpu->kvm->lock);
1228 return r;
1229 } else
1230 return set_msr_hyperv(vcpu, msr, data);
1231 break;
15c4a640 1232 default:
ffde22ac
ES		 1233 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1234 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1235 if (!ignore_msrs) {
1236 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1237 msr, data);
1238 return 1;
1239 } else {
1240 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1241 msr, data);
1242 break;
1243 }
15c4a640
CO		 1244 }
1245 return 0;
1246}
1247EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1248
1249
1250/*
1251 * Reads an msr value (of 'msr_index') into 'pdata'.
1252 * Returns 0 on success, non-0 otherwise.
1253 * Assumes vcpu_load() was already called.
1254 */
1255int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1256{
1257 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1258}
1259
9ba075a6
AK		 1260static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1261{
0bed3b56
SY		 1262 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1263
9ba075a6
AK		 1264 if (!msr_mtrr_valid(msr))
1265 return 1;
1266
0bed3b56
SY		 1267 if (msr == MSR_MTRRdefType)
1268 *pdata = vcpu->arch.mtrr_state.def_type +
1269 (vcpu->arch.mtrr_state.enabled << 10);
1270 else if (msr == MSR_MTRRfix64K_00000)
1271 *pdata = p[0];
1272 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1273 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1274 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1275 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1276 else if (msr == MSR_IA32_CR_PAT)
1277 *pdata = vcpu->arch.pat;
1278 else { /* Variable MTRRs */
1279 int idx, is_mtrr_mask;
1280 u64 *pt;
1281
1282 idx = (msr - 0x200) / 2;
1283 is_mtrr_mask = msr - 0x200 - 2 * idx;
1284 if (!is_mtrr_mask)
1285 pt =
1286 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1287 else
1288 pt =
1289 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1290 *pdata = *pt;
1291 }
1292
9ba075a6
AK		 1293 return 0;
1294}
1295
890ca9ae 1296static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1297{
1298 u64 data;
890ca9ae
HY		 1299 u64 mcg_cap = vcpu->arch.mcg_cap;
1300 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1301
1302 switch (msr) {
15c4a640
CO		 1303 case MSR_IA32_P5_MC_ADDR:
1304 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1305 data = 0;
1306 break;
15c4a640 1307 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1308 data = vcpu->arch.mcg_cap;
1309 break;
c7ac679c 1310 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1311 if (!(mcg_cap & MCG_CTL_P))
1312 return 1;
1313 data = vcpu->arch.mcg_ctl;
1314 break;
1315 case MSR_IA32_MCG_STATUS:
1316 data = vcpu->arch.mcg_status;
1317 break;
1318 default:
1319 if (msr >= MSR_IA32_MC0_CTL &&
1320 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1321 u32 offset = msr - MSR_IA32_MC0_CTL;
1322 data = vcpu->arch.mce_banks[offset];
1323 break;
1324 }
1325 return 1;
1326 }
1327 *pdata = data;
1328 return 0;
1329}
1330
55cd8e5a
GN		 1331static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1332{
1333 u64 data = 0;
1334 struct kvm *kvm = vcpu->kvm;
1335
1336 switch (msr) {
1337 case HV_X64_MSR_GUEST_OS_ID:
1338 data = kvm->arch.hv_guest_os_id;
1339 break;
1340 case HV_X64_MSR_HYPERCALL:
1341 data = kvm->arch.hv_hypercall;
1342 break;
1343 default:
1344 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1345 return 1;
1346 }
1347
1348 *pdata = data;
1349 return 0;
1350}
1351
1352static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1353{
1354 u64 data = 0;
1355
1356 switch (msr) {
1357 case HV_X64_MSR_VP_INDEX: {
1358 int r;
1359 struct kvm_vcpu *v;
1360 kvm_for_each_vcpu(r, v, vcpu->kvm)
1361 if (v == vcpu)
1362 data = r;
1363 break;
1364 }
10388a07
GN		 1365 case HV_X64_MSR_EOI:
1366 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1367 case HV_X64_MSR_ICR:
1368 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1369 case HV_X64_MSR_TPR:
1370 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1371 default:
1372 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1373 return 1;
1374 }
1375 *pdata = data;
1376 return 0;
1377}
1378
890ca9ae
HY		 1379int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1380{
1381 u64 data;
1382
1383 switch (msr) {
890ca9ae 1384 case MSR_IA32_PLATFORM_ID:
15c4a640 1385 case MSR_IA32_UCODE_REV:
15c4a640 1386 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1387 case MSR_IA32_DEBUGCTLMSR:
1388 case MSR_IA32_LASTBRANCHFROMIP:
1389 case MSR_IA32_LASTBRANCHTOIP:
1390 case MSR_IA32_LASTINTFROMIP:
1391 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1392 case MSR_K8_SYSCFG:
1393 case MSR_K7_HWCR:
61a6bd67 1394 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1395 case MSR_P6_PERFCTR0:
1396 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1397 case MSR_P6_EVNTSEL0:
1398 case MSR_P6_EVNTSEL1:
9e699624 1399 case MSR_K7_EVNTSEL0:
1f3ee616 1400 case MSR_K7_PERFCTR0:
1fdbd48c 1401 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1402 case MSR_AMD64_NB_CFG:
f7c6d140 1403 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1404 data = 0;
1405 break;
9ba075a6
AK		 1406 case MSR_MTRRcap:
1407 data = 0x500 | KVM_NR_VAR_MTRR;
1408 break;
1409 case 0x200 ... 0x2ff:
1410 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1411 case 0xcd: /* fsb frequency */
1412 data = 3;
1413 break;
1414 case MSR_IA32_APICBASE:
1415 data = kvm_get_apic_base(vcpu);
1416 break;
0105d1a5
GN		 1417 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1418 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1419 break;
15c4a640 1420 case MSR_IA32_MISC_ENABLE:
ad312c7c 1421 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1422 break;
847f0ad8
AG		 1423 case MSR_IA32_PERF_STATUS:
1424 /* TSC increment by tick */
1425 data = 1000ULL;
1426 /* CPU multiplier */
1427 data |= (((uint64_t)4ULL) << 40);
1428 break;
15c4a640 1429 case MSR_EFER:
f6801dff 1430 data = vcpu->arch.efer;
15c4a640 1431 break;
18068523
GOC		 1432 case MSR_KVM_WALL_CLOCK:
1433 data = vcpu->kvm->arch.wall_clock;
1434 break;
1435 case MSR_KVM_SYSTEM_TIME:
1436 data = vcpu->arch.time;
1437 break;
890ca9ae
HY		 1438 case MSR_IA32_P5_MC_ADDR:
1439 case MSR_IA32_P5_MC_TYPE:
1440 case MSR_IA32_MCG_CAP:
1441 case MSR_IA32_MCG_CTL:
1442 case MSR_IA32_MCG_STATUS:
1443 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1444 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1445 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1446 if (kvm_hv_msr_partition_wide(msr)) {
1447 int r;
1448 mutex_lock(&vcpu->kvm->lock);
1449 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1450 mutex_unlock(&vcpu->kvm->lock);
1451 return r;
1452 } else
1453 return get_msr_hyperv(vcpu, msr, pdata);
1454 break;
15c4a640 1455 default:
ed85c068
AP		 1456 if (!ignore_msrs) {
1457 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1458 return 1;
1459 } else {
1460 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1461 data = 0;
1462 }
1463 break;
15c4a640
CO		 1464 }
1465 *pdata = data;
1466 return 0;
1467}
1468EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1469
313a3dc7
CO		 1470/*
1471 * Read or write a bunch of msrs. All parameters are kernel addresses.
1472 *
1473 * @return number of msrs set successfully.
1474 */
1475static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1476 struct kvm_msr_entry *entries,
1477 int (*do_msr)(struct kvm_vcpu *vcpu,
1478 unsigned index, u64 *data))
1479{
f656ce01 1480 int i, idx;
313a3dc7
CO		 1481
1482 vcpu_load(vcpu);
1483
f656ce01 1484 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1485 for (i = 0; i < msrs->nmsrs; ++i)
1486 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1487 break;
f656ce01 1488 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1489
1490 vcpu_put(vcpu);
1491
1492 return i;
1493}
1494
1495/*
1496 * Read or write a bunch of msrs. Parameters are user addresses.
1497 *
1498 * @return number of msrs set successfully.
1499 */
1500static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1501 int (*do_msr)(struct kvm_vcpu *vcpu,
1502 unsigned index, u64 *data),
1503 int writeback)
1504{
1505 struct kvm_msrs msrs;
1506 struct kvm_msr_entry *entries;
1507 int r, n;
1508 unsigned size;
1509
1510 r = -EFAULT;
1511 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1512 goto out;
1513
1514 r = -E2BIG;
1515 if (msrs.nmsrs >= MAX_IO_MSRS)
1516 goto out;
1517
1518 r = -ENOMEM;
1519 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1520 entries = vmalloc(size);
1521 if (!entries)
1522 goto out;
1523
1524 r = -EFAULT;
1525 if (copy_from_user(entries, user_msrs->entries, size))
1526 goto out_free;
1527
1528 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1529 if (r < 0)
1530 goto out_free;
1531
1532 r = -EFAULT;
1533 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1534 goto out_free;
1535
1536 r = n;
1537
1538out_free:
1539 vfree(entries);
1540out:
1541 return r;
1542}
1543
018d00d2
ZX		 1544int kvm_dev_ioctl_check_extension(long ext)
1545{
1546 int r;
1547
1548 switch (ext) {
1549 case KVM_CAP_IRQCHIP:
1550 case KVM_CAP_HLT:
1551 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1552 case KVM_CAP_SET_TSS_ADDR:
07716717 1553 case KVM_CAP_EXT_CPUID:
c8076604 1554 case KVM_CAP_CLOCKSOURCE:
7837699f 1555 case KVM_CAP_PIT:
a28e4f5a 1556 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1557 case KVM_CAP_MP_STATE:
ed848624 1558 case KVM_CAP_SYNC_MMU:
52d939a0 1559 case KVM_CAP_REINJECT_CONTROL:
4925663a 1560 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1561 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1562 case KVM_CAP_IRQFD:
d34e6b17 1563 case KVM_CAP_IOEVENTFD:
c5ff41ce 1564 case KVM_CAP_PIT2:
e9f42757 1565 case KVM_CAP_PIT_STATE2:
b927a3ce 1566 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1567 case KVM_CAP_XEN_HVM:
afbcf7ab 1568 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1569 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1570 case KVM_CAP_HYPERV:
10388a07 1571 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1572 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1573 case KVM_CAP_PCI_SEGMENT:
d2be1651 1574 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1575 r = 1;
1576 break;
542472b5
LV		 1577 case KVM_CAP_COALESCED_MMIO:
1578 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1579 break;
774ead3a
AK		 1580 case KVM_CAP_VAPIC:
1581 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1582 break;
f725230a
AK		 1583 case KVM_CAP_NR_VCPUS:
1584 r = KVM_MAX_VCPUS;
1585 break;
a988b910
AK		 1586 case KVM_CAP_NR_MEMSLOTS:
1587 r = KVM_MEMORY_SLOTS;
1588 break;
a68a6a72
MT		 1589 case KVM_CAP_PV_MMU: /* obsolete */
1590 r = 0;
2f333bcb 1591 break;
62c476c7 1592 case KVM_CAP_IOMMU:
19de40a8 1593 r = iommu_found();
62c476c7 1594 break;
890ca9ae
HY		 1595 case KVM_CAP_MCE:
1596 r = KVM_MAX_MCE_BANKS;
1597 break;
018d00d2
ZX		 1598 default:
1599 r = 0;
1600 break;
1601 }
1602 return r;
1603
1604}
1605
043405e1
CO		 1606long kvm_arch_dev_ioctl(struct file *filp,
1607 unsigned int ioctl, unsigned long arg)
1608{
1609 void __user *argp = (void __user *)arg;
1610 long r;
1611
1612 switch (ioctl) {
1613 case KVM_GET_MSR_INDEX_LIST: {
1614 struct kvm_msr_list __user *user_msr_list = argp;
1615 struct kvm_msr_list msr_list;
1616 unsigned n;
1617
1618 r = -EFAULT;
1619 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1620 goto out;
1621 n = msr_list.nmsrs;
1622 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1623 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1624 goto out;
1625 r = -E2BIG;
e125e7b6 1626 if (n < msr_list.nmsrs)
043405e1
CO		 1627 goto out;
1628 r = -EFAULT;
1629 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1630 num_msrs_to_save * sizeof(u32)))
1631 goto out;
e125e7b6 1632 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1633 &emulated_msrs,
1634 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1635 goto out;
1636 r = 0;
1637 break;
1638 }
674eea0f
AK		 1639 case KVM_GET_SUPPORTED_CPUID: {
1640 struct kvm_cpuid2 __user *cpuid_arg = argp;
1641 struct kvm_cpuid2 cpuid;
1642
1643 r = -EFAULT;
1644 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1645 goto out;
1646 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1647 cpuid_arg->entries);
674eea0f
AK		 1648 if (r)
1649 goto out;
1650
1651 r = -EFAULT;
1652 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1653 goto out;
1654 r = 0;
1655 break;
1656 }
890ca9ae
HY		 1657 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1658 u64 mce_cap;
1659
1660 mce_cap = KVM_MCE_CAP_SUPPORTED;
1661 r = -EFAULT;
1662 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1663 goto out;
1664 r = 0;
1665 break;
1666 }
043405e1
CO		 1667 default:
1668 r = -EINVAL;
1669 }
1670out:
1671 return r;
1672}
1673
313a3dc7
CO		 1674void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1675{
1676 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1677 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1678 unsigned long khz = cpufreq_quick_get(cpu);
1679 if (!khz)
1680 khz = tsc_khz;
1681 per_cpu(cpu_tsc_khz, cpu) = khz;
1682 }
c8076604 1683 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1684}
1685
1686void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1687{
9327fd11 1688 kvm_put_guest_fpu(vcpu);
02daab21 1689 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1690}
1691
07716717 1692static int is_efer_nx(void)
313a3dc7 1693{
e286e86e 1694 unsigned long long efer = 0;
313a3dc7 1695
e286e86e 1696 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1697 return efer & EFER_NX;
1698}
1699
1700static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1701{
1702 int i;
1703 struct kvm_cpuid_entry2 *e, *entry;
1704
313a3dc7 1705 entry = NULL;
ad312c7c
ZX		 1706 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1707 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1708 if (e->function == 0x80000001) {
1709 entry = e;
1710 break;
1711 }
1712 }
07716717 1713 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1714 entry->edx &= ~(1 << 20);
1715 printk(KERN_INFO "kvm: guest NX capability removed\n");
1716 }
1717}
1718
07716717 1719/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1720static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1721 struct kvm_cpuid *cpuid,
1722 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1723{
1724 int r, i;
1725 struct kvm_cpuid_entry *cpuid_entries;
1726
1727 r = -E2BIG;
1728 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1729 goto out;
1730 r = -ENOMEM;
1731 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1732 if (!cpuid_entries)
1733 goto out;
1734 r = -EFAULT;
1735 if (copy_from_user(cpuid_entries, entries,
1736 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1737 goto out_free;
1738 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1739 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1740 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1741 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1742 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1743 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1744 vcpu->arch.cpuid_entries[i].index = 0;
1745 vcpu->arch.cpuid_entries[i].flags = 0;
1746 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1747 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1748 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1749 }
1750 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1751 cpuid_fix_nx_cap(vcpu);
1752 r = 0;
fc61b800 1753 kvm_apic_set_version(vcpu);
0e851880 1754 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1755
1756out_free:
1757 vfree(cpuid_entries);
1758out:
1759 return r;
1760}
1761
1762static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1763 struct kvm_cpuid2 *cpuid,
1764 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1765{
1766 int r;
1767
1768 r = -E2BIG;
1769 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1770 goto out;
1771 r = -EFAULT;
ad312c7c 1772 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1773 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1774 goto out;
ad312c7c 1775 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1776 kvm_apic_set_version(vcpu);
0e851880 1777 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1778 return 0;
1779
1780out:
1781 return r;
1782}
1783
07716717 1784static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1785 struct kvm_cpuid2 *cpuid,
1786 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1787{
1788 int r;
1789
1790 r = -E2BIG;
ad312c7c 1791 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1792 goto out;
1793 r = -EFAULT;
ad312c7c 1794 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1795 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1796 goto out;
1797 return 0;
1798
1799out:
ad312c7c 1800 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1801 return r;
1802}
1803
07716717 1804static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1805 u32 index)
07716717
DK		 1806{
1807 entry->function = function;
1808 entry->index = index;
1809 cpuid_count(entry->function, entry->index,
19355475 1810 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1811 entry->flags = 0;
1812}
1813
7faa4ee1
AK		 1814#define F(x) bit(X86_FEATURE_##x)
1815
07716717
DK		 1816static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1817 u32 index, int *nent, int maxnent)
1818{
7faa4ee1 1819 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1820#ifdef CONFIG_X86_64
17cc3935
SY		 1821 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1822 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1823 unsigned f_lm = F(LM);
1824#else
17cc3935 1825 unsigned f_gbpages = 0;
7faa4ee1 1826 unsigned f_lm = 0;
07716717 1827#endif
4e47c7a6 1828 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1829
1830 /* cpuid 1.edx */
1831 const u32 kvm_supported_word0_x86_features =
1832 F(FPU) | F(VME) | F(DE) | F(PSE) |
1833 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1834 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1835 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1836 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1837 0 /* Reserved, DS, ACPI */ | F(MMX) |
1838 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1839 0 /* HTT, TM, Reserved, PBE */;
1840 /* cpuid 0x80000001.edx */
1841 const u32 kvm_supported_word1_x86_features =
1842 F(FPU) | F(VME) | F(DE) | F(PSE) |
1843 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1844 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1845 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1846 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1847 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1848 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1849 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1850 /* cpuid 1.ecx */
1851 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1852 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1853 0 /* DS-CPL, VMX, SMX, EST */ |
1854 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1855 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1856 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1857 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1858 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1859 /* cpuid 0x80000001.ecx */
07716717 1860 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1861 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1862 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1863 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1864 0 /* SKINIT */ | 0 /* WDT */;
07716717 1865
19355475 1866 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1867 get_cpu();
1868 do_cpuid_1_ent(entry, function, index);
1869 ++*nent;
1870
1871 switch (function) {
1872 case 0:
1873 entry->eax = min(entry->eax, (u32)0xb);
1874 break;
1875 case 1:
1876 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1877 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1878 /* we support x2apic emulation even if host does not support
1879 * it since we emulate x2apic in software */
1880 entry->ecx |= F(X2APIC);
07716717
DK		 1881 break;
1882 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1883 * may return different values. This forces us to get_cpu() before
1884 * issuing the first command, and also to emulate this annoying behavior
1885 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1886 case 2: {
1887 int t, times = entry->eax & 0xff;
1888
1889 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1890 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1891 for (t = 1; t < times && *nent < maxnent; ++t) {
1892 do_cpuid_1_ent(&entry[t], function, 0);
1893 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1894 ++*nent;
1895 }
1896 break;
1897 }
1898 /* function 4 and 0xb have additional index. */
1899 case 4: {
14af3f3c 1900 int i, cache_type;
07716717
DK		 1901
1902 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1903 /* read more entries until cache_type is zero */
14af3f3c
HH		 1904 for (i = 1; *nent < maxnent; ++i) {
1905 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1906 if (!cache_type)
1907 break;
14af3f3c
HH		 1908 do_cpuid_1_ent(&entry[i], function, i);
1909 entry[i].flags |=
07716717
DK		 1910 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1911 ++*nent;
1912 }
1913 break;
1914 }
1915 case 0xb: {
14af3f3c 1916 int i, level_type;
07716717
DK		 1917
1918 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1919 /* read more entries until level_type is zero */
14af3f3c 1920 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1921 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1922 if (!level_type)
1923 break;
14af3f3c
HH		 1924 do_cpuid_1_ent(&entry[i], function, i);
1925 entry[i].flags |=
07716717
DK		 1926 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1927 ++*nent;
1928 }
1929 break;
1930 }
1931 case 0x80000000:
1932 entry->eax = min(entry->eax, 0x8000001a);
1933 break;
1934 case 0x80000001:
1935 entry->edx &= kvm_supported_word1_x86_features;
1936 entry->ecx &= kvm_supported_word6_x86_features;
1937 break;
1938 }
1939 put_cpu();
1940}
1941
7faa4ee1
AK		 1942#undef F
1943
674eea0f 1944static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1945 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1946{
1947 struct kvm_cpuid_entry2 *cpuid_entries;
1948 int limit, nent = 0, r = -E2BIG;
1949 u32 func;
1950
1951 if (cpuid->nent < 1)
1952 goto out;
6a544355
AK		 1953 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1954 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1955 r = -ENOMEM;
1956 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1957 if (!cpuid_entries)
1958 goto out;
1959
1960 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1961 limit = cpuid_entries[0].eax;
1962 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1963 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1964 &nent, cpuid->nent);
07716717
DK		 1965 r = -E2BIG;
1966 if (nent >= cpuid->nent)
1967 goto out_free;
1968
1969 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1970 limit = cpuid_entries[nent - 1].eax;
1971 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1972 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1973 &nent, cpuid->nent);
cb007648
MM		 1974 r = -E2BIG;
1975 if (nent >= cpuid->nent)
1976 goto out_free;
1977
07716717
DK		 1978 r = -EFAULT;
1979 if (copy_to_user(entries, cpuid_entries,
19355475 1980 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1981 goto out_free;
1982 cpuid->nent = nent;
1983 r = 0;
1984
1985out_free:
1986 vfree(cpuid_entries);
1987out:
1988 return r;
1989}
1990
313a3dc7
CO		 1991static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1992 struct kvm_lapic_state *s)
1993{
1994 vcpu_load(vcpu);
ad312c7c 1995 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1996 vcpu_put(vcpu);
1997
1998 return 0;
1999}
2000
2001static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2002 struct kvm_lapic_state *s)
2003{
2004 vcpu_load(vcpu);
ad312c7c 2005 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2006 kvm_apic_post_state_restore(vcpu);
cb142eb7 2007 update_cr8_intercept(vcpu);
313a3dc7
CO		 2008 vcpu_put(vcpu);
2009
2010 return 0;
2011}
2012
f77bc6a4
ZX		 2013static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2014 struct kvm_interrupt *irq)
2015{
2016 if (irq->irq < 0 || irq->irq >= 256)
2017 return -EINVAL;
2018 if (irqchip_in_kernel(vcpu->kvm))
2019 return -ENXIO;
2020 vcpu_load(vcpu);
2021
66fd3f7f 2022 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2023
2024 vcpu_put(vcpu);
2025
2026 return 0;
2027}
2028
c4abb7c9
JK		 2029static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2030{
2031 vcpu_load(vcpu);
2032 kvm_inject_nmi(vcpu);
2033 vcpu_put(vcpu);
2034
2035 return 0;
2036}
2037
b209749f
AK		 2038static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2039 struct kvm_tpr_access_ctl *tac)
2040{
2041 if (tac->flags)
2042 return -EINVAL;
2043 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2044 return 0;
2045}
2046
890ca9ae
HY		 2047static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2048 u64 mcg_cap)
2049{
2050 int r;
2051 unsigned bank_num = mcg_cap & 0xff, bank;
2052
2053 r = -EINVAL;
a9e38c3e 2054 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2055 goto out;
2056 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2057 goto out;
2058 r = 0;
2059 vcpu->arch.mcg_cap = mcg_cap;
2060 /* Init IA32_MCG_CTL to all 1s */
2061 if (mcg_cap & MCG_CTL_P)
2062 vcpu->arch.mcg_ctl = ~(u64)0;
2063 /* Init IA32_MCi_CTL to all 1s */
2064 for (bank = 0; bank < bank_num; bank++)
2065 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2066out:
2067 return r;
2068}
2069
2070static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2071 struct kvm_x86_mce *mce)
2072{
2073 u64 mcg_cap = vcpu->arch.mcg_cap;
2074 unsigned bank_num = mcg_cap & 0xff;
2075 u64 *banks = vcpu->arch.mce_banks;
2076
2077 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2078 return -EINVAL;
2079 /*
2080 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2081 * reporting is disabled
2082 */
2083 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2084 vcpu->arch.mcg_ctl != ~(u64)0)
2085 return 0;
2086 banks += 4 * mce->bank;
2087 /*
2088 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2089 * reporting is disabled for the bank
2090 */
2091 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2092 return 0;
2093 if (mce->status & MCI_STATUS_UC) {
2094 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2095 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2096 printk(KERN_DEBUG "kvm: set_mce: "
2097 "injects mce exception while "
2098 "previous one is in progress!\n");
2099 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2100 return 0;
2101 }
2102 if (banks[1] & MCI_STATUS_VAL)
2103 mce->status |= MCI_STATUS_OVER;
2104 banks[2] = mce->addr;
2105 banks[3] = mce->misc;
2106 vcpu->arch.mcg_status = mce->mcg_status;
2107 banks[1] = mce->status;
2108 kvm_queue_exception(vcpu, MC_VECTOR);
2109 } else if (!(banks[1] & MCI_STATUS_VAL)
2110 || !(banks[1] & MCI_STATUS_UC)) {
2111 if (banks[1] & MCI_STATUS_VAL)
2112 mce->status |= MCI_STATUS_OVER;
2113 banks[2] = mce->addr;
2114 banks[3] = mce->misc;
2115 banks[1] = mce->status;
2116 } else
2117 banks[1] |= MCI_STATUS_OVER;
2118 return 0;
2119}
2120
3cfc3092
JK		 2121static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2122 struct kvm_vcpu_events *events)
2123{
2124 vcpu_load(vcpu);
2125
2126 events->exception.injected = vcpu->arch.exception.pending;
2127 events->exception.nr = vcpu->arch.exception.nr;
2128 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2129 events->exception.error_code = vcpu->arch.exception.error_code;
2130
2131 events->interrupt.injected = vcpu->arch.interrupt.pending;
2132 events->interrupt.nr = vcpu->arch.interrupt.nr;
2133 events->interrupt.soft = vcpu->arch.interrupt.soft;
2134
2135 events->nmi.injected = vcpu->arch.nmi_injected;
2136 events->nmi.pending = vcpu->arch.nmi_pending;
2137 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2138
2139 events->sipi_vector = vcpu->arch.sipi_vector;
2140
dab4b911
JK		 2141 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2142 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
3cfc3092
JK		 2143
2144 vcpu_put(vcpu);
2145}
2146
2147static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2148 struct kvm_vcpu_events *events)
2149{
dab4b911
JK		 2150 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2151 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
3cfc3092
JK		 2152 return -EINVAL;
2153
2154 vcpu_load(vcpu);
2155
2156 vcpu->arch.exception.pending = events->exception.injected;
2157 vcpu->arch.exception.nr = events->exception.nr;
2158 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2159 vcpu->arch.exception.error_code = events->exception.error_code;
2160
2161 vcpu->arch.interrupt.pending = events->interrupt.injected;
2162 vcpu->arch.interrupt.nr = events->interrupt.nr;
2163 vcpu->arch.interrupt.soft = events->interrupt.soft;
2164 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2165 kvm_pic_clear_isr_ack(vcpu->kvm);
2166
2167 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2168 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2169 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2170 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2171
dab4b911
JK		 2172 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2173 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2174
2175 vcpu_put(vcpu);
2176
2177 return 0;
2178}
2179
313a3dc7
CO		 2180long kvm_arch_vcpu_ioctl(struct file *filp,
2181 unsigned int ioctl, unsigned long arg)
2182{
2183 struct kvm_vcpu *vcpu = filp->private_data;
2184 void __user *argp = (void __user *)arg;
2185 int r;
b772ff36 2186 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2187
2188 switch (ioctl) {
2189 case KVM_GET_LAPIC: {
2204ae3c
MT		 2190 r = -EINVAL;
2191 if (!vcpu->arch.apic)
2192 goto out;
b772ff36 2193 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2194
b772ff36
DH		 2195 r = -ENOMEM;
2196 if (!lapic)
2197 goto out;
2198 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2199 if (r)
2200 goto out;
2201 r = -EFAULT;
b772ff36 2202 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2203 goto out;
2204 r = 0;
2205 break;
2206 }
2207 case KVM_SET_LAPIC: {
2204ae3c
MT		 2208 r = -EINVAL;
2209 if (!vcpu->arch.apic)
2210 goto out;
b772ff36
DH		 2211 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2212 r = -ENOMEM;
2213 if (!lapic)
2214 goto out;
313a3dc7 2215 r = -EFAULT;
b772ff36 2216 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2217 goto out;
b772ff36 2218 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2219 if (r)
2220 goto out;
2221 r = 0;
2222 break;
2223 }
f77bc6a4
ZX		 2224 case KVM_INTERRUPT: {
2225 struct kvm_interrupt irq;
2226
2227 r = -EFAULT;
2228 if (copy_from_user(&irq, argp, sizeof irq))
2229 goto out;
2230 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2231 if (r)
2232 goto out;
2233 r = 0;
2234 break;
2235 }
c4abb7c9
JK		 2236 case KVM_NMI: {
2237 r = kvm_vcpu_ioctl_nmi(vcpu);
2238 if (r)
2239 goto out;
2240 r = 0;
2241 break;
2242 }
313a3dc7
CO		 2243 case KVM_SET_CPUID: {
2244 struct kvm_cpuid __user *cpuid_arg = argp;
2245 struct kvm_cpuid cpuid;
2246
2247 r = -EFAULT;
2248 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2249 goto out;
2250 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2251 if (r)
2252 goto out;
2253 break;
2254 }
07716717
DK		 2255 case KVM_SET_CPUID2: {
2256 struct kvm_cpuid2 __user *cpuid_arg = argp;
2257 struct kvm_cpuid2 cpuid;
2258
2259 r = -EFAULT;
2260 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2261 goto out;
2262 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2263 cpuid_arg->entries);
07716717
DK		 2264 if (r)
2265 goto out;
2266 break;
2267 }
2268 case KVM_GET_CPUID2: {
2269 struct kvm_cpuid2 __user *cpuid_arg = argp;
2270 struct kvm_cpuid2 cpuid;
2271
2272 r = -EFAULT;
2273 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2274 goto out;
2275 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2276 cpuid_arg->entries);
07716717
DK		 2277 if (r)
2278 goto out;
2279 r = -EFAULT;
2280 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2281 goto out;
2282 r = 0;
2283 break;
2284 }
313a3dc7
CO		 2285 case KVM_GET_MSRS:
2286 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2287 break;
2288 case KVM_SET_MSRS:
2289 r = msr_io(vcpu, argp, do_set_msr, 0);
2290 break;
b209749f
AK		 2291 case KVM_TPR_ACCESS_REPORTING: {
2292 struct kvm_tpr_access_ctl tac;
2293
2294 r = -EFAULT;
2295 if (copy_from_user(&tac, argp, sizeof tac))
2296 goto out;
2297 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2298 if (r)
2299 goto out;
2300 r = -EFAULT;
2301 if (copy_to_user(argp, &tac, sizeof tac))
2302 goto out;
2303 r = 0;
2304 break;
2305 };
b93463aa
AK		 2306 case KVM_SET_VAPIC_ADDR: {
2307 struct kvm_vapic_addr va;
2308
2309 r = -EINVAL;
2310 if (!irqchip_in_kernel(vcpu->kvm))
2311 goto out;
2312 r = -EFAULT;
2313 if (copy_from_user(&va, argp, sizeof va))
2314 goto out;
2315 r = 0;
2316 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2317 break;
2318 }
890ca9ae
HY		 2319 case KVM_X86_SETUP_MCE: {
2320 u64 mcg_cap;
2321
2322 r = -EFAULT;
2323 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2324 goto out;
2325 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2326 break;
2327 }
2328 case KVM_X86_SET_MCE: {
2329 struct kvm_x86_mce mce;
2330
2331 r = -EFAULT;
2332 if (copy_from_user(&mce, argp, sizeof mce))
2333 goto out;
2334 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2335 break;
2336 }
3cfc3092
JK		 2337 case KVM_GET_VCPU_EVENTS: {
2338 struct kvm_vcpu_events events;
2339
2340 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2341
2342 r = -EFAULT;
2343 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2344 break;
2345 r = 0;
2346 break;
2347 }
2348 case KVM_SET_VCPU_EVENTS: {
2349 struct kvm_vcpu_events events;
2350
2351 r = -EFAULT;
2352 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2353 break;
2354
2355 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2356 break;
2357 }
313a3dc7
CO		 2358 default:
2359 r = -EINVAL;
2360 }
2361out:
7a6ce84c 2362 kfree(lapic);
313a3dc7
CO		 2363 return r;
2364}
2365
1fe779f8
CO		 2366static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2367{
2368 int ret;
2369
2370 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2371 return -1;
2372 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2373 return ret;
2374}
2375
b927a3ce
SY		 2376static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2377 u64 ident_addr)
2378{
2379 kvm->arch.ept_identity_map_addr = ident_addr;
2380 return 0;
2381}
2382
1fe779f8
CO		 2383static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2384 u32 kvm_nr_mmu_pages)
2385{
2386 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2387 return -EINVAL;
2388
79fac95e 2389 mutex_lock(&kvm->slots_lock);
7c8a83b7 2390 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2391
2392 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2393 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2394
7c8a83b7 2395 spin_unlock(&kvm->mmu_lock);
79fac95e 2396 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2397 return 0;
2398}
2399
2400static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2401{
f05e70ac 2402 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2403}
2404
a983fb23
MT		 2405gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2406{
2407 int i;
2408 struct kvm_mem_alias *alias;
2409 struct kvm_mem_aliases *aliases;
2410
2411 aliases = rcu_dereference(kvm->arch.aliases);
2412
2413 for (i = 0; i < aliases->naliases; ++i) {
2414 alias = &aliases->aliases[i];
2415 if (alias->flags & KVM_ALIAS_INVALID)
2416 continue;
2417 if (gfn >= alias->base_gfn
2418 && gfn < alias->base_gfn + alias->npages)
2419 return alias->target_gfn + gfn - alias->base_gfn;
2420 }
2421 return gfn;
2422}
2423
e9f85cde
ZX		 2424gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2425{
2426 int i;
2427 struct kvm_mem_alias *alias;
a983fb23
MT		 2428 struct kvm_mem_aliases *aliases;
2429
2430 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2431
fef9cce0
MT		 2432 for (i = 0; i < aliases->naliases; ++i) {
2433 alias = &aliases->aliases[i];
e9f85cde
ZX		 2434 if (gfn >= alias->base_gfn
2435 && gfn < alias->base_gfn + alias->npages)
2436 return alias->target_gfn + gfn - alias->base_gfn;
2437 }
2438 return gfn;
2439}
2440
1fe779f8
CO		 2441/*
2442 * Set a new alias region. Aliases map a portion of physical memory into
2443 * another portion. This is useful for memory windows, for example the PC
2444 * VGA region.
2445 */
2446static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2447 struct kvm_memory_alias *alias)
2448{
2449 int r, n;
2450 struct kvm_mem_alias *p;
a983fb23 2451 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2452
2453 r = -EINVAL;
2454 /* General sanity checks */
2455 if (alias->memory_size & (PAGE_SIZE - 1))
2456 goto out;
2457 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2458 goto out;
2459 if (alias->slot >= KVM_ALIAS_SLOTS)
2460 goto out;
2461 if (alias->guest_phys_addr + alias->memory_size
2462 < alias->guest_phys_addr)
2463 goto out;
2464 if (alias->target_phys_addr + alias->memory_size
2465 < alias->target_phys_addr)
2466 goto out;
2467
a983fb23
MT		 2468 r = -ENOMEM;
2469 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2470 if (!aliases)
2471 goto out;
2472
79fac95e 2473 mutex_lock(&kvm->slots_lock);
1fe779f8 2474
a983fb23
MT		 2475 /* invalidate any gfn reference in case of deletion/shrinking */
2476 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2477 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2478 old_aliases = kvm->arch.aliases;
2479 rcu_assign_pointer(kvm->arch.aliases, aliases);
2480 synchronize_srcu_expedited(&kvm->srcu);
2481 kvm_mmu_zap_all(kvm);
2482 kfree(old_aliases);
2483
2484 r = -ENOMEM;
2485 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2486 if (!aliases)
2487 goto out_unlock;
2488
2489 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2490
2491 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2492 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2493 p->npages = alias->memory_size >> PAGE_SHIFT;
2494 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2495 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2496
2497 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2498 if (aliases->aliases[n - 1].npages)
1fe779f8 2499 break;
fef9cce0 2500 aliases->naliases = n;
1fe779f8 2501
a983fb23
MT		 2502 old_aliases = kvm->arch.aliases;
2503 rcu_assign_pointer(kvm->arch.aliases, aliases);
2504 synchronize_srcu_expedited(&kvm->srcu);
2505 kfree(old_aliases);
2506 r = 0;
1fe779f8 2507
a983fb23 2508out_unlock:
79fac95e 2509 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2510out:
2511 return r;
2512}
2513
2514static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2515{
2516 int r;
2517
2518 r = 0;
2519 switch (chip->chip_id) {
2520 case KVM_IRQCHIP_PIC_MASTER:
2521 memcpy(&chip->chip.pic,
2522 &pic_irqchip(kvm)->pics[0],
2523 sizeof(struct kvm_pic_state));
2524 break;
2525 case KVM_IRQCHIP_PIC_SLAVE:
2526 memcpy(&chip->chip.pic,
2527 &pic_irqchip(kvm)->pics[1],
2528 sizeof(struct kvm_pic_state));
2529 break;
2530 case KVM_IRQCHIP_IOAPIC:
eba0226b 2531 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2532 break;
2533 default:
2534 r = -EINVAL;
2535 break;
2536 }
2537 return r;
2538}
2539
2540static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2541{
2542 int r;
2543
2544 r = 0;
2545 switch (chip->chip_id) {
2546 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2547 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2548 memcpy(&pic_irqchip(kvm)->pics[0],
2549 &chip->chip.pic,
2550 sizeof(struct kvm_pic_state));
fa8273e9 2551 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2552 break;
2553 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2554 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2555 memcpy(&pic_irqchip(kvm)->pics[1],
2556 &chip->chip.pic,
2557 sizeof(struct kvm_pic_state));
fa8273e9 2558 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2559 break;
2560 case KVM_IRQCHIP_IOAPIC:
eba0226b 2561 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2562 break;
2563 default:
2564 r = -EINVAL;
2565 break;
2566 }
2567 kvm_pic_update_irq(pic_irqchip(kvm));
2568 return r;
2569}
2570
e0f63cb9
SY		 2571static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2572{
2573 int r = 0;
2574
894a9c55 2575 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2576 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2577 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2578 return r;
2579}
2580
2581static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2582{
2583 int r = 0;
2584
894a9c55 2585 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2586 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2587 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2588 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2589 return r;
2590}
2591
2592static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2593{
2594 int r = 0;
2595
2596 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2597 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2598 sizeof(ps->channels));
2599 ps->flags = kvm->arch.vpit->pit_state.flags;
2600 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2601 return r;
2602}
2603
2604static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2605{
2606 int r = 0, start = 0;
2607 u32 prev_legacy, cur_legacy;
2608 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2609 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2610 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2611 if (!prev_legacy && cur_legacy)
2612 start = 1;
2613 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2614 sizeof(kvm->arch.vpit->pit_state.channels));
2615 kvm->arch.vpit->pit_state.flags = ps->flags;
2616 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2617 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2618 return r;
2619}
2620
52d939a0
MT		 2621static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2622 struct kvm_reinject_control *control)
2623{
2624 if (!kvm->arch.vpit)
2625 return -ENXIO;
894a9c55 2626 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2627 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2628 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2629 return 0;
2630}
2631
5bb064dc
ZX		 2632/*
2633 * Get (and clear) the dirty memory log for a memory slot.
2634 */
2635int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2636 struct kvm_dirty_log *log)
2637{
b050b015 2638 int r, n, i;
5bb064dc 2639 struct kvm_memory_slot *memslot;
b050b015
MT		 2640 unsigned long is_dirty = 0;
2641 unsigned long *dirty_bitmap = NULL;
5bb064dc 2642
79fac95e 2643 mutex_lock(&kvm->slots_lock);
5bb064dc 2644
b050b015
MT		 2645 r = -EINVAL;
2646 if (log->slot >= KVM_MEMORY_SLOTS)
2647 goto out;
2648
2649 memslot = &kvm->memslots->memslots[log->slot];
2650 r = -ENOENT;
2651 if (!memslot->dirty_bitmap)
2652 goto out;
2653
2654 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2655
2656 r = -ENOMEM;
2657 dirty_bitmap = vmalloc(n);
2658 if (!dirty_bitmap)
5bb064dc 2659 goto out;
b050b015
MT		 2660 memset(dirty_bitmap, 0, n);
2661
2662 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2663 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2664
2665 /* If nothing is dirty, don't bother messing with page tables. */
2666 if (is_dirty) {
b050b015
MT		 2667 struct kvm_memslots *slots, *old_slots;
2668
7c8a83b7 2669 spin_lock(&kvm->mmu_lock);
5bb064dc 2670 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2671 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2672
2673 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2674 if (!slots)
2675 goto out_free;
2676
2677 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2678 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2679
2680 old_slots = kvm->memslots;
2681 rcu_assign_pointer(kvm->memslots, slots);
2682 synchronize_srcu_expedited(&kvm->srcu);
2683 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2684 kfree(old_slots);
5bb064dc 2685 }
b050b015 2686
5bb064dc 2687 r = 0;
b050b015
MT		 2688 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2689 r = -EFAULT;
2690out_free:
2691 vfree(dirty_bitmap);
5bb064dc 2692out:
79fac95e 2693 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2694 return r;
2695}
2696
1fe779f8
CO		 2697long kvm_arch_vm_ioctl(struct file *filp,
2698 unsigned int ioctl, unsigned long arg)
2699{
2700 struct kvm *kvm = filp->private_data;
2701 void __user *argp = (void __user *)arg;
367e1319 2702 int r = -ENOTTY;
f0d66275
DH		 2703 /*
2704 * This union makes it completely explicit to gcc-3.x
2705 * that these two variables' stack usage should be
2706 * combined, not added together.
2707 */
2708 union {
2709 struct kvm_pit_state ps;
e9f42757 2710 struct kvm_pit_state2 ps2;
f0d66275 2711 struct kvm_memory_alias alias;
c5ff41ce 2712 struct kvm_pit_config pit_config;
f0d66275 2713 } u;
1fe779f8
CO		 2714
2715 switch (ioctl) {
2716 case KVM_SET_TSS_ADDR:
2717 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2718 if (r < 0)
2719 goto out;
2720 break;
b927a3ce
SY		 2721 case KVM_SET_IDENTITY_MAP_ADDR: {
2722 u64 ident_addr;
2723
2724 r = -EFAULT;
2725 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2726 goto out;
2727 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2728 if (r < 0)
2729 goto out;
2730 break;
2731 }
1fe779f8
CO		 2732 case KVM_SET_MEMORY_REGION: {
2733 struct kvm_memory_region kvm_mem;
2734 struct kvm_userspace_memory_region kvm_userspace_mem;
2735
2736 r = -EFAULT;
2737 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2738 goto out;
2739 kvm_userspace_mem.slot = kvm_mem.slot;
2740 kvm_userspace_mem.flags = kvm_mem.flags;
2741 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2742 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2743 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2744 if (r)
2745 goto out;
2746 break;
2747 }
2748 case KVM_SET_NR_MMU_PAGES:
2749 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2750 if (r)
2751 goto out;
2752 break;
2753 case KVM_GET_NR_MMU_PAGES:
2754 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2755 break;
f0d66275 2756 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2757 r = -EFAULT;
f0d66275 2758 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2759 goto out;
f0d66275 2760 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2761 if (r)
2762 goto out;
2763 break;
3ddea128
MT		 2764 case KVM_CREATE_IRQCHIP: {
2765 struct kvm_pic *vpic;
2766
2767 mutex_lock(&kvm->lock);
2768 r = -EEXIST;
2769 if (kvm->arch.vpic)
2770 goto create_irqchip_unlock;
1fe779f8 2771 r = -ENOMEM;
3ddea128
MT		 2772 vpic = kvm_create_pic(kvm);
2773 if (vpic) {
1fe779f8
CO		 2774 r = kvm_ioapic_init(kvm);
2775 if (r) {
72bb2fcd
WY		 2776 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2777 &vpic->dev);
3ddea128
MT		 2778 kfree(vpic);
2779 goto create_irqchip_unlock;
1fe779f8
CO		 2780 }
2781 } else
3ddea128
MT		 2782 goto create_irqchip_unlock;
2783 smp_wmb();
2784 kvm->arch.vpic = vpic;
2785 smp_wmb();
399ec807
AK		 2786 r = kvm_setup_default_irq_routing(kvm);
2787 if (r) {
3ddea128 2788 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2789 kvm_ioapic_destroy(kvm);
2790 kvm_destroy_pic(kvm);
3ddea128 2791 mutex_unlock(&kvm->irq_lock);
399ec807 2792 }
3ddea128
MT		 2793 create_irqchip_unlock:
2794 mutex_unlock(&kvm->lock);
1fe779f8 2795 break;
3ddea128 2796 }
7837699f 2797 case KVM_CREATE_PIT:
c5ff41ce
JK		 2798 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2799 goto create_pit;
2800 case KVM_CREATE_PIT2:
2801 r = -EFAULT;
2802 if (copy_from_user(&u.pit_config, argp,
2803 sizeof(struct kvm_pit_config)))
2804 goto out;
2805 create_pit:
79fac95e 2806 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2807 r = -EEXIST;
2808 if (kvm->arch.vpit)
2809 goto create_pit_unlock;
7837699f 2810 r = -ENOMEM;
c5ff41ce 2811 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2812 if (kvm->arch.vpit)
2813 r = 0;
269e05e4 2814 create_pit_unlock:
79fac95e 2815 mutex_unlock(&kvm->slots_lock);
7837699f 2816 break;
4925663a 2817 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2818 case KVM_IRQ_LINE: {
2819 struct kvm_irq_level irq_event;
2820
2821 r = -EFAULT;
2822 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2823 goto out;
2824 if (irqchip_in_kernel(kvm)) {
4925663a 2825 __s32 status;
4925663a
GN		 2826 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2827 irq_event.irq, irq_event.level);
4925663a
GN		 2828 if (ioctl == KVM_IRQ_LINE_STATUS) {
2829 irq_event.status = status;
2830 if (copy_to_user(argp, &irq_event,
2831 sizeof irq_event))
2832 goto out;
2833 }
1fe779f8
CO		 2834 r = 0;
2835 }
2836 break;
2837 }
2838 case KVM_GET_IRQCHIP: {
2839 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2840 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2841
f0d66275
DH		 2842 r = -ENOMEM;
2843 if (!chip)
1fe779f8 2844 goto out;
f0d66275
DH		 2845 r = -EFAULT;
2846 if (copy_from_user(chip, argp, sizeof *chip))
2847 goto get_irqchip_out;
1fe779f8
CO		 2848 r = -ENXIO;
2849 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2850 goto get_irqchip_out;
2851 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2852 if (r)
f0d66275 2853 goto get_irqchip_out;
1fe779f8 2854 r = -EFAULT;
f0d66275
DH		 2855 if (copy_to_user(argp, chip, sizeof *chip))
2856 goto get_irqchip_out;
1fe779f8 2857 r = 0;
f0d66275
DH		 2858 get_irqchip_out:
2859 kfree(chip);
2860 if (r)
2861 goto out;
1fe779f8
CO		 2862 break;
2863 }
2864 case KVM_SET_IRQCHIP: {
2865 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2866 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2867
f0d66275
DH		 2868 r = -ENOMEM;
2869 if (!chip)
1fe779f8 2870 goto out;
f0d66275
DH		 2871 r = -EFAULT;
2872 if (copy_from_user(chip, argp, sizeof *chip))
2873 goto set_irqchip_out;
1fe779f8
CO		 2874 r = -ENXIO;
2875 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2876 goto set_irqchip_out;
2877 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2878 if (r)
f0d66275 2879 goto set_irqchip_out;
1fe779f8 2880 r = 0;
f0d66275
DH		 2881 set_irqchip_out:
2882 kfree(chip);
2883 if (r)
2884 goto out;
1fe779f8
CO		 2885 break;
2886 }
e0f63cb9 2887 case KVM_GET_PIT: {
e0f63cb9 2888 r = -EFAULT;
f0d66275 2889 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2890 goto out;
2891 r = -ENXIO;
2892 if (!kvm->arch.vpit)
2893 goto out;
f0d66275 2894 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2895 if (r)
2896 goto out;
2897 r = -EFAULT;
f0d66275 2898 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2899 goto out;
2900 r = 0;
2901 break;
2902 }
2903 case KVM_SET_PIT: {
e0f63cb9 2904 r = -EFAULT;
f0d66275 2905 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2906 goto out;
2907 r = -ENXIO;
2908 if (!kvm->arch.vpit)
2909 goto out;
f0d66275 2910 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2911 if (r)
2912 goto out;
2913 r = 0;
2914 break;
2915 }
e9f42757
BK		 2916 case KVM_GET_PIT2: {
2917 r = -ENXIO;
2918 if (!kvm->arch.vpit)
2919 goto out;
2920 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2921 if (r)
2922 goto out;
2923 r = -EFAULT;
2924 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2925 goto out;
2926 r = 0;
2927 break;
2928 }
2929 case KVM_SET_PIT2: {
2930 r = -EFAULT;
2931 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2932 goto out;
2933 r = -ENXIO;
2934 if (!kvm->arch.vpit)
2935 goto out;
2936 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2937 if (r)
2938 goto out;
2939 r = 0;
2940 break;
2941 }
52d939a0
MT		 2942 case KVM_REINJECT_CONTROL: {
2943 struct kvm_reinject_control control;
2944 r = -EFAULT;
2945 if (copy_from_user(&control, argp, sizeof(control)))
2946 goto out;
2947 r = kvm_vm_ioctl_reinject(kvm, &control);
2948 if (r)
2949 goto out;
2950 r = 0;
2951 break;
2952 }
ffde22ac
ES		 2953 case KVM_XEN_HVM_CONFIG: {
2954 r = -EFAULT;
2955 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2956 sizeof(struct kvm_xen_hvm_config)))
2957 goto out;
2958 r = -EINVAL;
2959 if (kvm->arch.xen_hvm_config.flags)
2960 goto out;
2961 r = 0;
2962 break;
2963 }
afbcf7ab
GC		 2964 case KVM_SET_CLOCK: {
2965 struct timespec now;
2966 struct kvm_clock_data user_ns;
2967 u64 now_ns;
2968 s64 delta;
2969
2970 r = -EFAULT;
2971 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2972 goto out;
2973
2974 r = -EINVAL;
2975 if (user_ns.flags)
2976 goto out;
2977
2978 r = 0;
2979 ktime_get_ts(&now);
2980 now_ns = timespec_to_ns(&now);
2981 delta = user_ns.clock - now_ns;
2982 kvm->arch.kvmclock_offset = delta;
2983 break;
2984 }
2985 case KVM_GET_CLOCK: {
2986 struct timespec now;
2987 struct kvm_clock_data user_ns;
2988 u64 now_ns;
2989
2990 ktime_get_ts(&now);
2991 now_ns = timespec_to_ns(&now);
2992 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2993 user_ns.flags = 0;
2994
2995 r = -EFAULT;
2996 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2997 goto out;
2998 r = 0;
2999 break;
3000 }
3001
1fe779f8
CO		 3002 default:
3003 ;
3004 }
3005out:
3006 return r;
3007}
3008
a16b043c 3009static void kvm_init_msr_list(void)
043405e1
CO		 3010{
3011 u32 dummy[2];
3012 unsigned i, j;
3013
e3267cbb
GC		 3014 /* skip the first msrs in the list. KVM-specific */
3015 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3016 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3017 continue;
3018 if (j < i)
3019 msrs_to_save[j] = msrs_to_save[i];
3020 j++;
3021 }
3022 num_msrs_to_save = j;
3023}
3024
bda9020e
MT		 3025static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3026 const void *v)
bbd9b64e 3027{
bda9020e
MT		 3028 if (vcpu->arch.apic &&
3029 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3030 return 0;
bbd9b64e 3031
e93f8a0f 3032 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3033}
3034
bda9020e 3035static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3036{
bda9020e
MT		 3037 if (vcpu->arch.apic &&
3038 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3039 return 0;
bbd9b64e 3040
e93f8a0f 3041 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3042}
3043
1871c602
GN		 3044gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3045{
3046 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3047 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3048}
3049
3050 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3051{
3052 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3053 access |= PFERR_FETCH_MASK;
3054 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3055}
3056
3057gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3058{
3059 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3060 access |= PFERR_WRITE_MASK;
3061 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3062}
3063
3064/* uses this to access any guest's mapped memory without checking CPL */
3065gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3066{
3067 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3068}
3069
3070static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3071 struct kvm_vcpu *vcpu, u32 access,
3072 u32 *error)
bbd9b64e
CO		 3073{
3074 void *data = val;
10589a46 3075 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3076
3077 while (bytes) {
1871c602 3078 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3079 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3080 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3081 int ret;
3082
10589a46
MT		 3083 if (gpa == UNMAPPED_GVA) {
3084 r = X86EMUL_PROPAGATE_FAULT;
3085 goto out;
3086 }
77c2002e 3087 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3088 if (ret < 0) {
3089 r = X86EMUL_UNHANDLEABLE;
3090 goto out;
3091 }
bbd9b64e 3092
77c2002e
IE		 3093 bytes -= toread;
3094 data += toread;
3095 addr += toread;
bbd9b64e 3096 }
10589a46 3097out:
10589a46 3098 return r;
bbd9b64e 3099}
77c2002e 3100
1871c602
GN		 3101/* used for instruction fetching */
3102static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3103 struct kvm_vcpu *vcpu, u32 *error)
3104{
3105 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3106 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3107 access | PFERR_FETCH_MASK, error);
3108}
3109
3110static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3111 struct kvm_vcpu *vcpu, u32 *error)
3112{
3113 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3114 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3115 error);
3116}
3117
3118static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3119 struct kvm_vcpu *vcpu, u32 *error)
3120{
3121 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3122}
3123
cded19f3 3124static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
1871c602 3125 struct kvm_vcpu *vcpu, u32 *error)
77c2002e
IE		 3126{
3127 void *data = val;
3128 int r = X86EMUL_CONTINUE;
3129
3130 while (bytes) {
1871c602 3131 gpa_t gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error);
77c2002e
IE		 3132 unsigned offset = addr & (PAGE_SIZE-1);
3133 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3134 int ret;
3135
3136 if (gpa == UNMAPPED_GVA) {
3137 r = X86EMUL_PROPAGATE_FAULT;
3138 goto out;
3139 }
3140 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3141 if (ret < 0) {
3142 r = X86EMUL_UNHANDLEABLE;
3143 goto out;
3144 }
3145
3146 bytes -= towrite;
3147 data += towrite;
3148 addr += towrite;
3149 }
3150out:
3151 return r;
3152}
3153
bbd9b64e 3154
bbd9b64e
CO		 3155static int emulator_read_emulated(unsigned long addr,
3156 void *val,
3157 unsigned int bytes,
3158 struct kvm_vcpu *vcpu)
3159{
bbd9b64e 3160 gpa_t gpa;
1871c602 3161 u32 error_code;
bbd9b64e
CO		 3162
3163 if (vcpu->mmio_read_completed) {
3164 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3165 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3166 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3167 vcpu->mmio_read_completed = 0;
3168 return X86EMUL_CONTINUE;
3169 }
3170
1871c602
GN		 3171 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3172
3173 if (gpa == UNMAPPED_GVA) {
3174 kvm_inject_page_fault(vcpu, addr, error_code);
3175 return X86EMUL_PROPAGATE_FAULT;
3176 }
bbd9b64e
CO		 3177
3178 /* For APIC access vmexit */
3179 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3180 goto mmio;
3181
1871c602 3182 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3183 == X86EMUL_CONTINUE)
bbd9b64e 3184 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3185
3186mmio:
3187 /*
3188 * Is this MMIO handled locally?
3189 */
aec51dc4
AK		 3190 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3191 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3192 return X86EMUL_CONTINUE;
3193 }
aec51dc4
AK		 3194
3195 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3196
3197 vcpu->mmio_needed = 1;
3198 vcpu->mmio_phys_addr = gpa;
3199 vcpu->mmio_size = bytes;
3200 vcpu->mmio_is_write = 0;
3201
3202 return X86EMUL_UNHANDLEABLE;
3203}
3204
3200f405 3205int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3206 const void *val, int bytes)
bbd9b64e
CO		 3207{
3208 int ret;
3209
3210 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3211 if (ret < 0)
bbd9b64e 3212 return 0;
ad218f85 3213 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3214 return 1;
3215}
3216
3217static int emulator_write_emulated_onepage(unsigned long addr,
3218 const void *val,
3219 unsigned int bytes,
3220 struct kvm_vcpu *vcpu)
3221{
10589a46 3222 gpa_t gpa;
1871c602 3223 u32 error_code;
10589a46 3224
1871c602 3225 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3226
3227 if (gpa == UNMAPPED_GVA) {
1871c602 3228 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3229 return X86EMUL_PROPAGATE_FAULT;
3230 }
3231
3232 /* For APIC access vmexit */
3233 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3234 goto mmio;
3235
3236 if (emulator_write_phys(vcpu, gpa, val, bytes))
3237 return X86EMUL_CONTINUE;
3238
3239mmio:
aec51dc4 3240 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3241 /*
3242 * Is this MMIO handled locally?
3243 */
bda9020e 3244 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3245 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3246
3247 vcpu->mmio_needed = 1;
3248 vcpu->mmio_phys_addr = gpa;
3249 vcpu->mmio_size = bytes;
3250 vcpu->mmio_is_write = 1;
3251 memcpy(vcpu->mmio_data, val, bytes);
3252
3253 return X86EMUL_CONTINUE;
3254}
3255
3256int emulator_write_emulated(unsigned long addr,
3257 const void *val,
3258 unsigned int bytes,
3259 struct kvm_vcpu *vcpu)
3260{
3261 /* Crossing a page boundary? */
3262 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3263 int rc, now;
3264
3265 now = -addr & ~PAGE_MASK;
3266 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3267 if (rc != X86EMUL_CONTINUE)
3268 return rc;
3269 addr += now;
3270 val += now;
3271 bytes -= now;
3272 }
3273 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3274}
3275EXPORT_SYMBOL_GPL(emulator_write_emulated);
3276
3277static int emulator_cmpxchg_emulated(unsigned long addr,
3278 const void *old,
3279 const void *new,
3280 unsigned int bytes,
3281 struct kvm_vcpu *vcpu)
3282{
9f51e24e 3283 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3284#ifndef CONFIG_X86_64
3285 /* guests cmpxchg8b have to be emulated atomically */
3286 if (bytes == 8) {
10589a46 3287 gpa_t gpa;
2bacc55c 3288 struct page *page;
c0b49b0d 3289 char *kaddr;
2bacc55c
MT		 3290 u64 val;
3291
1871c602 3292 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
10589a46 3293
2bacc55c
MT		 3294 if (gpa == UNMAPPED_GVA ||
3295 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3296 goto emul_write;
3297
3298 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3299 goto emul_write;
3300
3301 val = *(u64 *)new;
72dc67a6 3302
2bacc55c 3303 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3304
c0b49b0d
AM		 3305 kaddr = kmap_atomic(page, KM_USER0);
3306 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3307 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3308 kvm_release_page_dirty(page);
3309 }
3200f405 3310emul_write:
2bacc55c
MT		 3311#endif
3312
bbd9b64e
CO		 3313 return emulator_write_emulated(addr, new, bytes, vcpu);
3314}
3315
3316static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3317{
3318 return kvm_x86_ops->get_segment_base(vcpu, seg);
3319}
3320
3321int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3322{
a7052897 3323 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3324 return X86EMUL_CONTINUE;
3325}
3326
3327int emulate_clts(struct kvm_vcpu *vcpu)
3328{
4d4ec087 3329 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3330 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3331 return X86EMUL_CONTINUE;
3332}
3333
3334int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3335{
c76de350 3336 return kvm_x86_ops->get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3337}
3338
3339int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3340{
3341 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3342
c76de350 3343 return kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3344}
3345
3346void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3347{
bbd9b64e 3348 u8 opcodes[4];
5fdbf976 3349 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3350 unsigned long rip_linear;
3351
f76c710d 3352 if (!printk_ratelimit())
bbd9b64e
CO		 3353 return;
3354
25be4608
GC		 3355 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3356
1871c602 3357 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3358
3359 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3360 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3361}
3362EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3363
14af3f3c 3364static struct x86_emulate_ops emulate_ops = {
1871c602
GN		 3365 .read_std = kvm_read_guest_virt_system,
3366 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3367 .read_emulated = emulator_read_emulated,
3368 .write_emulated = emulator_write_emulated,
3369 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3370};
3371
5fdbf976
MT		 3372static void cache_all_regs(struct kvm_vcpu *vcpu)
3373{
3374 kvm_register_read(vcpu, VCPU_REGS_RAX);
3375 kvm_register_read(vcpu, VCPU_REGS_RSP);
3376 kvm_register_read(vcpu, VCPU_REGS_RIP);
3377 vcpu->arch.regs_dirty = ~0;
3378}
3379
bbd9b64e 3380int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3381 unsigned long cr2,
3382 u16 error_code,
571008da 3383 int emulation_type)
bbd9b64e 3384{
310b5d30 3385 int r, shadow_mask;
571008da 3386 struct decode_cache *c;
851ba692 3387 struct kvm_run *run = vcpu->run;
bbd9b64e 3388
26eef70c 3389 kvm_clear_exception_queue(vcpu);
ad312c7c 3390 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3391 /*
56e82318 3392 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3393 * instead of direct ->regs accesses, can save hundred cycles
3394 * on Intel for instructions that don't read/change RSP, for
3395 * for example.
3396 */
3397 cache_all_regs(vcpu);
bbd9b64e
CO		 3398
3399 vcpu->mmio_is_write = 0;
ad312c7c 3400 vcpu->arch.pio.string = 0;
bbd9b64e 3401
571008da 3402 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3403 int cs_db, cs_l;
3404 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3405
ad312c7c 3406 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3407 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c 3408 vcpu->arch.emulate_ctxt.mode =
a0044755 3409 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3410 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3411 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3412 ? X86EMUL_MODE_PROT64 : cs_db
3413 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3414
ad312c7c 3415 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3416
0cb5762e
AP		 3417 /* Only allow emulation of specific instructions on #UD
3418 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3419 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3420 if (emulation_type & EMULTYPE_TRAP_UD) {
3421 if (!c->twobyte)
3422 return EMULATE_FAIL;
3423 switch (c->b) {
3424 case 0x01: /* VMMCALL */
3425 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3426 return EMULATE_FAIL;
3427 break;
3428 case 0x34: /* sysenter */
3429 case 0x35: /* sysexit */
3430 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3431 return EMULATE_FAIL;
3432 break;
3433 case 0x05: /* syscall */
3434 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3435 return EMULATE_FAIL;
3436 break;
3437 default:
3438 return EMULATE_FAIL;
3439 }
3440
3441 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3442 return EMULATE_FAIL;
3443 }
571008da 3444
f2b5756b 3445 ++vcpu->stat.insn_emulation;
bbd9b64e 3446 if (r) {
f2b5756b 3447 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3448 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3449 return EMULATE_DONE;
3450 return EMULATE_FAIL;
3451 }
3452 }
3453
ba8afb6b
GN		 3454 if (emulation_type & EMULTYPE_SKIP) {
3455 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3456 return EMULATE_DONE;
3457 }
3458
ad312c7c 3459 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3460 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3461
3462 if (r == 0)
3463 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3464
ad312c7c 3465 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3466 return EMULATE_DO_MMIO;
3467
3468 if ((r || vcpu->mmio_is_write) && run) {
3469 run->exit_reason = KVM_EXIT_MMIO;
3470 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3471 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3472 run->mmio.len = vcpu->mmio_size;
3473 run->mmio.is_write = vcpu->mmio_is_write;
3474 }
3475
3476 if (r) {
3477 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3478 return EMULATE_DONE;
3479 if (!vcpu->mmio_needed) {
3480 kvm_report_emulation_failure(vcpu, "mmio");
3481 return EMULATE_FAIL;
3482 }
3483 return EMULATE_DO_MMIO;
3484 }
3485
91586a3b 3486 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3487
3488 if (vcpu->mmio_is_write) {
3489 vcpu->mmio_needed = 0;
3490 return EMULATE_DO_MMIO;
3491 }
3492
3493 return EMULATE_DONE;
3494}
3495EXPORT_SYMBOL_GPL(emulate_instruction);
3496
de7d789a
CO		 3497static int pio_copy_data(struct kvm_vcpu *vcpu)
3498{
ad312c7c 3499 void *p = vcpu->arch.pio_data;
0f346074 3500 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3501 unsigned bytes;
0f346074 3502 int ret;
1871c602 3503 u32 error_code;
de7d789a 3504
ad312c7c
ZX		 3505 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3506 if (vcpu->arch.pio.in)
1871c602 3507 ret = kvm_write_guest_virt(q, p, bytes, vcpu, &error_code);
de7d789a 3508 else
1871c602
GN		 3509 ret = kvm_read_guest_virt(q, p, bytes, vcpu, &error_code);
3510
3511 if (ret == X86EMUL_PROPAGATE_FAULT)
3512 kvm_inject_page_fault(vcpu, q, error_code);
3513
0f346074 3514 return ret;
de7d789a
CO		 3515}
3516
3517int complete_pio(struct kvm_vcpu *vcpu)
3518{
ad312c7c 3519 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3520 long delta;
3521 int r;
5fdbf976 3522 unsigned long val;
de7d789a
CO		 3523
3524 if (!io->string) {
5fdbf976
MT		 3525 if (io->in) {
3526 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3527 memcpy(&val, vcpu->arch.pio_data, io->size);
3528 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3529 }
de7d789a
CO		 3530 } else {
3531 if (io->in) {
3532 r = pio_copy_data(vcpu);
5fdbf976 3533 if (r)
1871c602 3534 goto out;
de7d789a
CO		 3535 }
3536
3537 delta = 1;
3538 if (io->rep) {
3539 delta *= io->cur_count;
3540 /*
3541 * The size of the register should really depend on
3542 * current address size.
3543 */
5fdbf976
MT		 3544 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3545 val -= delta;
3546 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3547 }
3548 if (io->down)
3549 delta = -delta;
3550 delta *= io->size;
5fdbf976
MT		 3551 if (io->in) {
3552 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3553 val += delta;
3554 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3555 } else {
3556 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3557 val += delta;
3558 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3559 }
de7d789a 3560 }
1871c602 3561out:
de7d789a
CO		 3562 io->count -= io->cur_count;
3563 io->cur_count = 0;
3564
3565 return 0;
3566}
3567
bda9020e 3568static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3569{
3570 /* TODO: String I/O for in kernel device */
bda9020e 3571 int r;
de7d789a 3572
ad312c7c 3573 if (vcpu->arch.pio.in)
e93f8a0f 3574 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3575 vcpu->arch.pio.size, pd);
de7d789a 3576 else
e93f8a0f
MT		 3577 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3578 vcpu->arch.pio.port, vcpu->arch.pio.size,
3579 pd);
bda9020e 3580 return r;
de7d789a
CO		 3581}
3582
bda9020e 3583static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3584{
ad312c7c
ZX		 3585 struct kvm_pio_request *io = &vcpu->arch.pio;
3586 void *pd = vcpu->arch.pio_data;
bda9020e 3587 int i, r = 0;
de7d789a 3588
de7d789a 3589 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3590 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3591 io->port, io->size, pd)) {
3592 r = -EOPNOTSUPP;
3593 break;
3594 }
de7d789a
CO		 3595 pd += io->size;
3596 }
bda9020e 3597 return r;
de7d789a
CO		 3598}
3599
851ba692 3600int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3601{
5fdbf976 3602 unsigned long val;
de7d789a 3603
f850e2e6
GN		 3604 trace_kvm_pio(!in, port, size, 1);
3605
de7d789a
CO		 3606 vcpu->run->exit_reason = KVM_EXIT_IO;
3607 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3608 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3609 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3610 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3611 vcpu->run->io.port = vcpu->arch.pio.port = port;
3612 vcpu->arch.pio.in = in;
3613 vcpu->arch.pio.string = 0;
3614 vcpu->arch.pio.down = 0;
ad312c7c 3615 vcpu->arch.pio.rep = 0;
de7d789a 3616
1976d2d2
TY		 3617 if (!vcpu->arch.pio.in) {
3618 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3619 memcpy(vcpu->arch.pio_data, &val, 4);
3620 }
de7d789a 3621
bda9020e 3622 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3623 complete_pio(vcpu);
3624 return 1;
3625 }
3626 return 0;
3627}
3628EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3629
851ba692 3630int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3631 int size, unsigned long count, int down,
3632 gva_t address, int rep, unsigned port)
3633{
3634 unsigned now, in_page;
0f346074 3635 int ret = 0;
de7d789a 3636
f850e2e6
GN		 3637 trace_kvm_pio(!in, port, size, count);
3638
de7d789a
CO		 3639 vcpu->run->exit_reason = KVM_EXIT_IO;
3640 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3641 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3642 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3643 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3644 vcpu->run->io.port = vcpu->arch.pio.port = port;
3645 vcpu->arch.pio.in = in;
3646 vcpu->arch.pio.string = 1;
3647 vcpu->arch.pio.down = down;
ad312c7c 3648 vcpu->arch.pio.rep = rep;
de7d789a
CO		 3649
3650 if (!count) {
3651 kvm_x86_ops->skip_emulated_instruction(vcpu);
3652 return 1;
3653 }
3654
3655 if (!down)
3656 in_page = PAGE_SIZE - offset_in_page(address);
3657 else
3658 in_page = offset_in_page(address) + size;
3659 now = min(count, (unsigned long)in_page / size);
0f346074 3660 if (!now)
de7d789a 3661 now = 1;
de7d789a
CO		 3662 if (down) {
3663 /*
3664 * String I/O in reverse. Yuck. Kill the guest, fix later.
3665 */
3666 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3667 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3668 return 1;
3669 }
3670 vcpu->run->io.count = now;
ad312c7c 3671 vcpu->arch.pio.cur_count = now;
de7d789a 3672
ad312c7c 3673 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3674 kvm_x86_ops->skip_emulated_instruction(vcpu);
3675
0f346074 3676 vcpu->arch.pio.guest_gva = address;
de7d789a 3677
ad312c7c 3678 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3679 /* string PIO write */
3680 ret = pio_copy_data(vcpu);
1871c602 3681 if (ret == X86EMUL_PROPAGATE_FAULT)
0f346074 3682 return 1;
bda9020e 3683 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3684 complete_pio(vcpu);
ad312c7c 3685 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3686 ret = 1;
3687 }
bda9020e
MT		 3688 }
3689 /* no string PIO read support yet */
de7d789a
CO		 3690
3691 return ret;
3692}
3693EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3694
c8076604
GH		 3695static void bounce_off(void *info)
3696{
3697 /* nothing */
3698}
3699
c8076604
GH		 3700static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3701 void *data)
3702{
3703 struct cpufreq_freqs *freq = data;
3704 struct kvm *kvm;
3705 struct kvm_vcpu *vcpu;
3706 int i, send_ipi = 0;
3707
c8076604
GH		 3708 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3709 return 0;
3710 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3711 return 0;
0cca7907 3712 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3713
3714 spin_lock(&kvm_lock);
3715 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3716 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3717 if (vcpu->cpu != freq->cpu)
3718 continue;
3719 if (!kvm_request_guest_time_update(vcpu))
3720 continue;
3721 if (vcpu->cpu != smp_processor_id())
3722 send_ipi++;
3723 }
3724 }
3725 spin_unlock(&kvm_lock);
3726
3727 if (freq->old < freq->new && send_ipi) {
3728 /*
3729 * We upscale the frequency. Must make the guest
3730 * doesn't see old kvmclock values while running with
3731 * the new frequency, otherwise we risk the guest sees
3732 * time go backwards.
3733 *
3734 * In case we update the frequency for another cpu
3735 * (which might be in guest context) send an interrupt
3736 * to kick the cpu out of guest context. Next time
3737 * guest context is entered kvmclock will be updated,
3738 * so the guest will not see stale values.
3739 */
3740 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3741 }
3742 return 0;
3743}
3744
3745static struct notifier_block kvmclock_cpufreq_notifier_block = {
3746 .notifier_call = kvmclock_cpufreq_notifier
3747};
3748
b820cc0c
ZA		 3749static void kvm_timer_init(void)
3750{
3751 int cpu;
3752
b820cc0c 3753 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3754 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3755 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3756 for_each_online_cpu(cpu) {
3757 unsigned long khz = cpufreq_get(cpu);
3758 if (!khz)
3759 khz = tsc_khz;
3760 per_cpu(cpu_tsc_khz, cpu) = khz;
3761 }
0cca7907
ZA		 3762 } else {
3763 for_each_possible_cpu(cpu)
3764 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3765 }
3766}
3767
f8c16bba 3768int kvm_arch_init(void *opaque)
043405e1 3769{
b820cc0c 3770 int r;
f8c16bba
ZX		 3771 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3772
f8c16bba
ZX		 3773 if (kvm_x86_ops) {
3774 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3775 r = -EEXIST;
3776 goto out;
f8c16bba
ZX		 3777 }
3778
3779 if (!ops->cpu_has_kvm_support()) {
3780 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3781 r = -EOPNOTSUPP;
3782 goto out;
f8c16bba
ZX		 3783 }
3784 if (ops->disabled_by_bios()) {
3785 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3786 r = -EOPNOTSUPP;
3787 goto out;
f8c16bba
ZX		 3788 }
3789
97db56ce
AK		 3790 r = kvm_mmu_module_init();
3791 if (r)
3792 goto out;
3793
3794 kvm_init_msr_list();
3795
f8c16bba 3796 kvm_x86_ops = ops;
56c6d28a 3797 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3798 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3799 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3800 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3801
b820cc0c 3802 kvm_timer_init();
c8076604 3803
f8c16bba 3804 return 0;
56c6d28a
ZX		 3805
3806out:
56c6d28a 3807 return r;
043405e1 3808}
8776e519 3809
f8c16bba
ZX		 3810void kvm_arch_exit(void)
3811{
888d256e
JK		 3812 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3813 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3814 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3815 kvm_x86_ops = NULL;
56c6d28a
ZX		 3816 kvm_mmu_module_exit();
3817}
f8c16bba 3818
8776e519
HB		 3819int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3820{
3821 ++vcpu->stat.halt_exits;
3822 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3823 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3824 return 1;
3825 } else {
3826 vcpu->run->exit_reason = KVM_EXIT_HLT;
3827 return 0;
3828 }
3829}
3830EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3831
2f333bcb
MT		 3832static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3833 unsigned long a1)
3834{
3835 if (is_long_mode(vcpu))
3836 return a0;
3837 else
3838 return a0 | ((gpa_t)a1 << 32);
3839}
3840
55cd8e5a
GN		 3841int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
3842{
3843 u64 param, ingpa, outgpa, ret;
3844 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
3845 bool fast, longmode;
3846 int cs_db, cs_l;
3847
3848 /*
3849 * hypercall generates UD from non zero cpl and real mode
3850 * per HYPER-V spec
3851 */
3eeb3288 3852 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 3853 kvm_queue_exception(vcpu, UD_VECTOR);
3854 return 0;
3855 }
3856
3857 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3858 longmode = is_long_mode(vcpu) && cs_l == 1;
3859
3860 if (!longmode) {
ccd46936
GN		 3861 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
3862 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
3863 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
3864 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
3865 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
3866 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 3867 }
3868#ifdef CONFIG_X86_64
3869 else {
3870 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
3871 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
3872 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
3873 }
3874#endif
3875
3876 code = param & 0xffff;
3877 fast = (param >> 16) & 0x1;
3878 rep_cnt = (param >> 32) & 0xfff;
3879 rep_idx = (param >> 48) & 0xfff;
3880
3881 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
3882
c25bc163
GN		 3883 switch (code) {
3884 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
3885 kvm_vcpu_on_spin(vcpu);
3886 break;
3887 default:
3888 res = HV_STATUS_INVALID_HYPERCALL_CODE;
3889 break;
3890 }
55cd8e5a
GN		 3891
3892 ret = res | (((u64)rep_done & 0xfff) << 32);
3893 if (longmode) {
3894 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3895 } else {
3896 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
3897 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
3898 }
3899
3900 return 1;
3901}
3902
8776e519
HB		 3903int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3904{
3905 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3906 int r = 1;
8776e519 3907
55cd8e5a
GN		 3908 if (kvm_hv_hypercall_enabled(vcpu->kvm))
3909 return kvm_hv_hypercall(vcpu);
3910
5fdbf976
MT		 3911 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3912 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3913 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3914 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3915 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3916
229456fc 3917 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3918
8776e519
HB		 3919 if (!is_long_mode(vcpu)) {
3920 nr &= 0xFFFFFFFF;
3921 a0 &= 0xFFFFFFFF;
3922 a1 &= 0xFFFFFFFF;
3923 a2 &= 0xFFFFFFFF;
3924 a3 &= 0xFFFFFFFF;
3925 }
3926
07708c4a
JK		 3927 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3928 ret = -KVM_EPERM;
3929 goto out;
3930 }
3931
8776e519 3932 switch (nr) {
b93463aa
AK		 3933 case KVM_HC_VAPIC_POLL_IRQ:
3934 ret = 0;
3935 break;
2f333bcb
MT		 3936 case KVM_HC_MMU_OP:
3937 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3938 break;
8776e519
HB		 3939 default:
3940 ret = -KVM_ENOSYS;
3941 break;
3942 }
07708c4a 3943out:
5fdbf976 3944 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3945 ++vcpu->stat.hypercalls;
2f333bcb 3946 return r;
8776e519
HB		 3947}
3948EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3949
3950int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3951{
3952 char instruction[3];
5fdbf976 3953 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3954
8776e519
HB		 3955 /*
3956 * Blow out the MMU to ensure that no other VCPU has an active mapping
3957 * to ensure that the updated hypercall appears atomically across all
3958 * VCPUs.
3959 */
3960 kvm_mmu_zap_all(vcpu->kvm);
3961
8776e519 3962 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 3963
7edcface 3964 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 3965}
3966
3967static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3968{
3969 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3970}
3971
3972void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3973{
3974 struct descriptor_table dt = { limit, base };
3975
3976 kvm_x86_ops->set_gdt(vcpu, &dt);
3977}
3978
3979void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3980{
3981 struct descriptor_table dt = { limit, base };
3982
3983 kvm_x86_ops->set_idt(vcpu, &dt);
3984}
3985
3986void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3987 unsigned long *rflags)
3988{
2d3ad1f4 3989 kvm_lmsw(vcpu, msw);
91586a3b 3990 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3991}
3992
3993unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3994{
54e445ca
JR		 3995 unsigned long value;
3996
8776e519
HB		 3997 switch (cr) {
3998 case 0:
4d4ec087 3999 value = kvm_read_cr0(vcpu);
54e445ca 4000 break;
8776e519 4001 case 2:
54e445ca
JR		 4002 value = vcpu->arch.cr2;
4003 break;
8776e519 4004 case 3:
54e445ca
JR		 4005 value = vcpu->arch.cr3;
4006 break;
8776e519 4007 case 4:
fc78f519 4008 value = kvm_read_cr4(vcpu);
54e445ca 4009 break;
152ff9be 4010 case 8:
54e445ca
JR		 4011 value = kvm_get_cr8(vcpu);
4012 break;
8776e519 4013 default:
b8688d51 4014 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4015 return 0;
4016 }
54e445ca
JR		 4017
4018 return value;
8776e519
HB		 4019}
4020
4021void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
4022 unsigned long *rflags)
4023{
4024 switch (cr) {
4025 case 0:
4d4ec087 4026 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
91586a3b 4027 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 4028 break;
4029 case 2:
ad312c7c 4030 vcpu->arch.cr2 = val;
8776e519
HB		 4031 break;
4032 case 3:
2d3ad1f4 4033 kvm_set_cr3(vcpu, val);
8776e519
HB		 4034 break;
4035 case 4:
fc78f519 4036 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 4037 break;
152ff9be 4038 case 8:
2d3ad1f4 4039 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 4040 break;
8776e519 4041 default:
b8688d51 4042 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4043 }
4044}
4045
07716717
DK		 4046static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4047{
ad312c7c
ZX		 4048 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4049 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4050
4051 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4052 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4053 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4054 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4055 if (ej->function == e->function) {
4056 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4057 return j;
4058 }
4059 }
4060 return 0; /* silence gcc, even though control never reaches here */
4061}
4062
4063/* find an entry with matching function, matching index (if needed), and that
4064 * should be read next (if it's stateful) */
4065static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4066 u32 function, u32 index)
4067{
4068 if (e->function != function)
4069 return 0;
4070 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4071 return 0;
4072 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4073 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4074 return 0;
4075 return 1;
4076}
4077
d8017474
AG		 4078struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4079 u32 function, u32 index)
8776e519
HB		 4080{
4081 int i;
d8017474 4082 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4083
ad312c7c 4084 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4085 struct kvm_cpuid_entry2 *e;
4086
ad312c7c 4087 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4088 if (is_matching_cpuid_entry(e, function, index)) {
4089 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4090 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4091 best = e;
4092 break;
4093 }
4094 /*
4095 * Both basic or both extended?
4096 */
4097 if (((e->function ^ function) & 0x80000000) == 0)
4098 if (!best || e->function > best->function)
4099 best = e;
4100 }
d8017474
AG		 4101 return best;
4102}
0e851880 4103EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4104
82725b20
DE		 4105int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4106{
4107 struct kvm_cpuid_entry2 *best;
4108
4109 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4110 if (best)
4111 return best->eax & 0xff;
4112 return 36;
4113}
4114
d8017474
AG		 4115void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4116{
4117 u32 function, index;
4118 struct kvm_cpuid_entry2 *best;
4119
4120 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4121 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4122 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4123 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4124 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4125 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4126 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4127 if (best) {
5fdbf976
MT		 4128 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4129 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4130 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4131 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4132 }
8776e519 4133 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4134 trace_kvm_cpuid(function,
4135 kvm_register_read(vcpu, VCPU_REGS_RAX),
4136 kvm_register_read(vcpu, VCPU_REGS_RBX),
4137 kvm_register_read(vcpu, VCPU_REGS_RCX),
4138 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4139}
4140EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4141
b6c7a5dc
HB		 4142/*
4143 * Check if userspace requested an interrupt window, and that the
4144 * interrupt window is open.
4145 *
4146 * No need to exit to userspace if we already have an interrupt queued.
4147 */
851ba692 4148static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4149{
8061823a 4150 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4151 vcpu->run->request_interrupt_window &&
5df56646 4152 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4153}
4154
851ba692 4155static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4156{
851ba692
AK		 4157 struct kvm_run *kvm_run = vcpu->run;
4158
91586a3b 4159 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4160 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4161 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4162 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4163 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4164 else
b6c7a5dc 4165 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4166 kvm_arch_interrupt_allowed(vcpu) &&
4167 !kvm_cpu_has_interrupt(vcpu) &&
4168 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4169}
4170
b93463aa
AK		 4171static void vapic_enter(struct kvm_vcpu *vcpu)
4172{
4173 struct kvm_lapic *apic = vcpu->arch.apic;
4174 struct page *page;
4175
4176 if (!apic || !apic->vapic_addr)
4177 return;
4178
4179 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4180
4181 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4182}
4183
4184static void vapic_exit(struct kvm_vcpu *vcpu)
4185{
4186 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4187 int idx;
b93463aa
AK		 4188
4189 if (!apic || !apic->vapic_addr)
4190 return;
4191
f656ce01 4192 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4193 kvm_release_page_dirty(apic->vapic_page);
4194 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4195 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4196}
4197
95ba8273
GN		 4198static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4199{
4200 int max_irr, tpr;
4201
4202 if (!kvm_x86_ops->update_cr8_intercept)
4203 return;
4204
88c808fd
AK		 4205 if (!vcpu->arch.apic)
4206 return;
4207
8db3baa2
GN		 4208 if (!vcpu->arch.apic->vapic_addr)
4209 max_irr = kvm_lapic_find_highest_irr(vcpu);
4210 else
4211 max_irr = -1;
95ba8273
GN		 4212
4213 if (max_irr != -1)
4214 max_irr >>= 4;
4215
4216 tpr = kvm_lapic_get_cr8(vcpu);
4217
4218 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4219}
4220
851ba692 4221static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4222{
4223 /* try to reinject previous events if any */
b59bb7bd
GN		 4224 if (vcpu->arch.exception.pending) {
4225 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4226 vcpu->arch.exception.has_error_code,
4227 vcpu->arch.exception.error_code);
4228 return;
4229 }
4230
95ba8273
GN		 4231 if (vcpu->arch.nmi_injected) {
4232 kvm_x86_ops->set_nmi(vcpu);
4233 return;
4234 }
4235
4236 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4237 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4238 return;
4239 }
4240
4241 /* try to inject new event if pending */
4242 if (vcpu->arch.nmi_pending) {
4243 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4244 vcpu->arch.nmi_pending = false;
4245 vcpu->arch.nmi_injected = true;
4246 kvm_x86_ops->set_nmi(vcpu);
4247 }
4248 } else if (kvm_cpu_has_interrupt(vcpu)) {
4249 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4250 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4251 false);
4252 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4253 }
4254 }
4255}
4256
851ba692 4257static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4258{
4259 int r;
6a8b1d13 4260 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4261 vcpu->run->request_interrupt_window;
b6c7a5dc 4262
2e53d63a
MT		 4263 if (vcpu->requests)
4264 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4265 kvm_mmu_unload(vcpu);
4266
b6c7a5dc
HB		 4267 r = kvm_mmu_reload(vcpu);
4268 if (unlikely(r))
4269 goto out;
4270
2f52d58c
AK		 4271 if (vcpu->requests) {
4272 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4273 __kvm_migrate_timers(vcpu);
c8076604
GH		 4274 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4275 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4276 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4277 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4278 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4279 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4280 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4281 &vcpu->requests)) {
851ba692 4282 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4283 r = 0;
4284 goto out;
4285 }
71c4dfaf 4286 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4287 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4288 r = 0;
4289 goto out;
4290 }
02daab21
AK		 4291 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4292 vcpu->fpu_active = 0;
4293 kvm_x86_ops->fpu_deactivate(vcpu);
4294 }
2f52d58c 4295 }
b93463aa 4296
b6c7a5dc
HB		 4297 preempt_disable();
4298
4299 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4300 if (vcpu->fpu_active)
4301 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4302
4303 local_irq_disable();
4304
32f88400
MT		 4305 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4306 smp_mb__after_clear_bit();
4307
d7690175 4308 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4309 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4310 local_irq_enable();
4311 preempt_enable();
4312 r = 1;
4313 goto out;
4314 }
4315
851ba692 4316 inject_pending_event(vcpu);
b6c7a5dc 4317
6a8b1d13
GN		 4318 /* enable NMI/IRQ window open exits if needed */
4319 if (vcpu->arch.nmi_pending)
4320 kvm_x86_ops->enable_nmi_window(vcpu);
4321 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4322 kvm_x86_ops->enable_irq_window(vcpu);
4323
95ba8273 4324 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4325 update_cr8_intercept(vcpu);
4326 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4327 }
b93463aa 4328
f656ce01 4329 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4330
b6c7a5dc
HB		 4331 kvm_guest_enter();
4332
42dbaa5a 4333 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4334 set_debugreg(0, 7);
4335 set_debugreg(vcpu->arch.eff_db[0], 0);
4336 set_debugreg(vcpu->arch.eff_db[1], 1);
4337 set_debugreg(vcpu->arch.eff_db[2], 2);
4338 set_debugreg(vcpu->arch.eff_db[3], 3);
4339 }
b6c7a5dc 4340
229456fc 4341 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4342 kvm_x86_ops->run(vcpu);
b6c7a5dc 4343
24f1e32c
FW		 4344 /*
4345 * If the guest has used debug registers, at least dr7
4346 * will be disabled while returning to the host.
4347 * If we don't have active breakpoints in the host, we don't
4348 * care about the messed up debug address registers. But if
4349 * we have some of them active, restore the old state.
4350 */
59d8eb53 4351 if (hw_breakpoint_active())
24f1e32c 4352 hw_breakpoint_restore();
42dbaa5a 4353
32f88400 4354 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4355 local_irq_enable();
4356
4357 ++vcpu->stat.exits;
4358
4359 /*
4360 * We must have an instruction between local_irq_enable() and
4361 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4362 * the interrupt shadow. The stat.exits increment will do nicely.
4363 * But we need to prevent reordering, hence this barrier():
4364 */
4365 barrier();
4366
4367 kvm_guest_exit();
4368
4369 preempt_enable();
4370
f656ce01 4371 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4372
b6c7a5dc
HB		 4373 /*
4374 * Profile KVM exit RIPs:
4375 */
4376 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4377 unsigned long rip = kvm_rip_read(vcpu);
4378 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4379 }
4380
298101da 4381
b93463aa
AK		 4382 kvm_lapic_sync_from_vapic(vcpu);
4383
851ba692 4384 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4385out:
4386 return r;
4387}
b6c7a5dc 4388
09cec754 4389
851ba692 4390static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4391{
4392 int r;
f656ce01 4393 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4394
4395 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4396 pr_debug("vcpu %d received sipi with vector # %x\n",
4397 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4398 kvm_lapic_reset(vcpu);
5f179287 4399 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4400 if (r)
4401 return r;
4402 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4403 }
4404
f656ce01 4405 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4406 vapic_enter(vcpu);
4407
4408 r = 1;
4409 while (r > 0) {
af2152f5 4410 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4411 r = vcpu_enter_guest(vcpu);
d7690175 4412 else {
f656ce01 4413 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4414 kvm_vcpu_block(vcpu);
f656ce01 4415 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4416 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4417 {
4418 switch(vcpu->arch.mp_state) {
4419 case KVM_MP_STATE_HALTED:
d7690175 4420 vcpu->arch.mp_state =
09cec754
GN		 4421 KVM_MP_STATE_RUNNABLE;
4422 case KVM_MP_STATE_RUNNABLE:
4423 break;
4424 case KVM_MP_STATE_SIPI_RECEIVED:
4425 default:
4426 r = -EINTR;
4427 break;
4428 }
4429 }
d7690175
MT		 4430 }
4431
09cec754
GN		 4432 if (r <= 0)
4433 break;
4434
4435 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4436 if (kvm_cpu_has_pending_timer(vcpu))
4437 kvm_inject_pending_timer_irqs(vcpu);
4438
851ba692 4439 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4440 r = -EINTR;
851ba692 4441 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4442 ++vcpu->stat.request_irq_exits;
4443 }
4444 if (signal_pending(current)) {
4445 r = -EINTR;
851ba692 4446 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4447 ++vcpu->stat.signal_exits;
4448 }
4449 if (need_resched()) {
f656ce01 4450 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4451 kvm_resched(vcpu);
f656ce01 4452 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4453 }
b6c7a5dc
HB		 4454 }
4455
f656ce01 4456 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4457 post_kvm_run_save(vcpu);
b6c7a5dc 4458
b93463aa
AK		 4459 vapic_exit(vcpu);
4460
b6c7a5dc
HB		 4461 return r;
4462}
4463
4464int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4465{
4466 int r;
4467 sigset_t sigsaved;
4468
4469 vcpu_load(vcpu);
4470
ac9f6dc0
AK		 4471 if (vcpu->sigset_active)
4472 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4473
a4535290 4474 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4475 kvm_vcpu_block(vcpu);
d7690175 4476 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4477 r = -EAGAIN;
4478 goto out;
b6c7a5dc
HB		 4479 }
4480
b6c7a5dc
HB		 4481 /* re-sync apic's tpr */
4482 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4483 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4484
ad312c7c 4485 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 4486 r = complete_pio(vcpu);
4487 if (r)
4488 goto out;
4489 }
b6c7a5dc
HB		 4490 if (vcpu->mmio_needed) {
4491 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4492 vcpu->mmio_read_completed = 1;
4493 vcpu->mmio_needed = 0;
3200f405 4494
f656ce01 4495 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
851ba692 4496 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4497 EMULTYPE_NO_DECODE);
f656ce01 4498 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4499 if (r == EMULATE_DO_MMIO) {
4500 /*
4501 * Read-modify-write. Back to userspace.
4502 */
4503 r = 0;
4504 goto out;
4505 }
4506 }
5fdbf976
MT		 4507 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4508 kvm_register_write(vcpu, VCPU_REGS_RAX,
4509 kvm_run->hypercall.ret);
b6c7a5dc 4510
851ba692 4511 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4512
4513out:
4514 if (vcpu->sigset_active)
4515 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4516
4517 vcpu_put(vcpu);
4518 return r;
4519}
4520
4521int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4522{
4523 vcpu_load(vcpu);
4524
5fdbf976
MT		 4525 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4526 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4527 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4528 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4529 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4530 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4531 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4532 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4533#ifdef CONFIG_X86_64
5fdbf976
MT		 4534 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4535 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4536 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4537 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4538 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4539 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4540 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4541 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4542#endif
4543
5fdbf976 4544 regs->rip = kvm_rip_read(vcpu);
91586a3b 4545 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4546
4547 vcpu_put(vcpu);
4548
4549 return 0;
4550}
4551
4552int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4553{
4554 vcpu_load(vcpu);
4555
5fdbf976
MT		 4556 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4557 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4558 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4559 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4560 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4561 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4562 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4563 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4564#ifdef CONFIG_X86_64
5fdbf976
MT		 4565 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4566 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4567 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4568 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4569 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4570 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4571 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4572 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4573#endif
4574
5fdbf976 4575 kvm_rip_write(vcpu, regs->rip);
91586a3b 4576 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4577
b4f14abd
JK		 4578 vcpu->arch.exception.pending = false;
4579
b6c7a5dc
HB		 4580 vcpu_put(vcpu);
4581
4582 return 0;
4583}
4584
3e6e0aab
GT		 4585void kvm_get_segment(struct kvm_vcpu *vcpu,
4586 struct kvm_segment *var, int seg)
b6c7a5dc 4587{
14af3f3c 4588 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4589}
4590
4591void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4592{
4593 struct kvm_segment cs;
4594
3e6e0aab 4595 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4596 *db = cs.db;
4597 *l = cs.l;
4598}
4599EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4600
4601int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4602 struct kvm_sregs *sregs)
4603{
4604 struct descriptor_table dt;
b6c7a5dc
HB		 4605
4606 vcpu_load(vcpu);
4607
3e6e0aab
GT		 4608 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4609 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4610 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4611 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4612 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4613 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4614
3e6e0aab
GT		 4615 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4616 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4617
4618 kvm_x86_ops->get_idt(vcpu, &dt);
4619 sregs->idt.limit = dt.limit;
4620 sregs->idt.base = dt.base;
4621 kvm_x86_ops->get_gdt(vcpu, &dt);
4622 sregs->gdt.limit = dt.limit;
4623 sregs->gdt.base = dt.base;
4624
4d4ec087 4625 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4626 sregs->cr2 = vcpu->arch.cr2;
4627 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4628 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4629 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4630 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4631 sregs->apic_base = kvm_get_apic_base(vcpu);
4632
923c61bb 4633 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4634
36752c9b 4635 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4636 set_bit(vcpu->arch.interrupt.nr,
4637 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4638
b6c7a5dc
HB		 4639 vcpu_put(vcpu);
4640
4641 return 0;
4642}
4643
62d9f0db
MT		 4644int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4645 struct kvm_mp_state *mp_state)
4646{
4647 vcpu_load(vcpu);
4648 mp_state->mp_state = vcpu->arch.mp_state;
4649 vcpu_put(vcpu);
4650 return 0;
4651}
4652
4653int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4654 struct kvm_mp_state *mp_state)
4655{
4656 vcpu_load(vcpu);
4657 vcpu->arch.mp_state = mp_state->mp_state;
4658 vcpu_put(vcpu);
4659 return 0;
4660}
4661
3e6e0aab 4662static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4663 struct kvm_segment *var, int seg)
4664{
14af3f3c 4665 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4666}
4667
37817f29
IE		 4668static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4669 struct kvm_segment *kvm_desct)
4670{
46a359e7
AM		 4671 kvm_desct->base = get_desc_base(seg_desc);
4672 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4673 if (seg_desc->g) {
4674 kvm_desct->limit <<= 12;
4675 kvm_desct->limit |= 0xfff;
4676 }
37817f29
IE		 4677 kvm_desct->selector = selector;
4678 kvm_desct->type = seg_desc->type;
4679 kvm_desct->present = seg_desc->p;
4680 kvm_desct->dpl = seg_desc->dpl;
4681 kvm_desct->db = seg_desc->d;
4682 kvm_desct->s = seg_desc->s;
4683 kvm_desct->l = seg_desc->l;
4684 kvm_desct->g = seg_desc->g;
4685 kvm_desct->avl = seg_desc->avl;
4686 if (!selector)
4687 kvm_desct->unusable = 1;
4688 else
4689 kvm_desct->unusable = 0;
4690 kvm_desct->padding = 0;
4691}
4692
b8222ad2
AS		 4693static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4694 u16 selector,
4695 struct descriptor_table *dtable)
37817f29
IE		 4696{
4697 if (selector & 1 << 2) {
4698 struct kvm_segment kvm_seg;
4699
3e6e0aab 4700 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4701
4702 if (kvm_seg.unusable)
4703 dtable->limit = 0;
4704 else
4705 dtable->limit = kvm_seg.limit;
4706 dtable->base = kvm_seg.base;
4707 }
4708 else
4709 kvm_x86_ops->get_gdt(vcpu, dtable);
4710}
4711
4712/* allowed just for 8 bytes segments */
4713static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4714 struct desc_struct *seg_desc)
4715{
4716 struct descriptor_table dtable;
4717 u16 index = selector >> 3;
6f550484
TY		 4718 int ret;
4719 u32 err;
4720 gva_t addr;
37817f29 4721
b8222ad2 4722 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4723
4724 if (dtable.limit < index * 8 + 7) {
4725 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
c125c607 4726 return X86EMUL_PROPAGATE_FAULT;
37817f29 4727 }
6f550484
TY		 4728 addr = dtable.base + index * 8;
4729 ret = kvm_read_guest_virt_system(addr, seg_desc, sizeof(*seg_desc),
4730 vcpu, &err);
4731 if (ret == X86EMUL_PROPAGATE_FAULT)
4732 kvm_inject_page_fault(vcpu, addr, err);
4733
4734 return ret;
37817f29
IE		 4735}
4736
4737/* allowed just for 8 bytes segments */
4738static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4739 struct desc_struct *seg_desc)
4740{
4741 struct descriptor_table dtable;
4742 u16 index = selector >> 3;
4743
b8222ad2 4744 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4745
4746 if (dtable.limit < index * 8 + 7)
4747 return 1;
1871c602
GN		 4748 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu, NULL);
4749}
4750
4751static gpa_t get_tss_base_addr_write(struct kvm_vcpu *vcpu,
4752 struct desc_struct *seg_desc)
4753{
4754 u32 base_addr = get_desc_base(seg_desc);
4755
4756 return kvm_mmu_gva_to_gpa_write(vcpu, base_addr, NULL);
37817f29
IE		 4757}
4758
1871c602 4759static gpa_t get_tss_base_addr_read(struct kvm_vcpu *vcpu,
37817f29
IE		 4760 struct desc_struct *seg_desc)
4761{
46a359e7 4762 u32 base_addr = get_desc_base(seg_desc);
37817f29 4763
1871c602 4764 return kvm_mmu_gva_to_gpa_read(vcpu, base_addr, NULL);
37817f29
IE		 4765}
4766
37817f29
IE		 4767static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4768{
4769 struct kvm_segment kvm_seg;
4770
3e6e0aab 4771 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4772 return kvm_seg.selector;
4773}
4774
2259e3a7 4775static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4776{
4777 struct kvm_segment segvar = {
4778 .base = selector << 4,
4779 .limit = 0xffff,
4780 .selector = selector,
4781 .type = 3,
4782 .present = 1,
4783 .dpl = 3,
4784 .db = 0,
4785 .s = 1,
4786 .l = 0,
4787 .g = 0,
4788 .avl = 0,
4789 .unusable = 0,
4790 };
4791 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
c697518a 4792 return X86EMUL_CONTINUE;
f4bbd9aa
AK		 4793}
4794
c0c7c04b
AL		 4795static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4796{
4797 return (seg != VCPU_SREG_LDTR) &&
4798 (seg != VCPU_SREG_TR) &&
91586a3b 4799 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4800}
4801
c697518a 4802int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg)
37817f29
IE		 4803{
4804 struct kvm_segment kvm_seg;
e01c2426 4805 struct desc_struct seg_desc;
c697518a
GN		 4806 u8 dpl, rpl, cpl;
4807 unsigned err_vec = GP_VECTOR;
4808 u32 err_code = 0;
4809 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
4810 int ret;
37817f29 4811
3eeb3288 4812 if (is_vm86_segment(vcpu, seg) || !is_protmode(vcpu))
f4bbd9aa 4813 return kvm_load_realmode_segment(vcpu, selector, seg);
e01c2426 4814
c697518a
GN		 4815 /* NULL selector is not valid for TR, CS and SS */
4816 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
4817 && null_selector)
4818 goto exception;
4819
4820 /* TR should be in GDT only */
4821 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
4822 goto exception;
4823
4824 ret = load_guest_segment_descriptor(vcpu, selector, &seg_desc);
4825 if (ret)
4826 return ret;
4827
e01c2426 4828 seg_desct_to_kvm_desct(&seg_desc, selector, &kvm_seg);
cb84b55f 4829
c697518a
GN		 4830 if (null_selector) { /* for NULL selector skip all following checks */
4831 kvm_seg.unusable = 1;
4832 goto load;
4833 }
37817f29 4834
c697518a
GN		 4835 err_code = selector & 0xfffc;
4836 err_vec = GP_VECTOR;
37817f29 4837
c697518a
GN		 4838 /* can't load system descriptor into segment selecor */
4839 if (seg <= VCPU_SREG_GS && !kvm_seg.s)
4840 goto exception;
4841
4842 if (!kvm_seg.present) {
4843 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
4844 goto exception;
4845 }
4846
4847 rpl = selector & 3;
4848 dpl = kvm_seg.dpl;
4849 cpl = kvm_x86_ops->get_cpl(vcpu);
4850
4851 switch (seg) {
4852 case VCPU_SREG_SS:
4853 /*
4854 * segment is not a writable data segment or segment
4855 * selector's RPL != CPL or segment selector's RPL != CPL
4856 */
4857 if (rpl != cpl || (kvm_seg.type & 0xa) != 0x2 || dpl != cpl)
4858 goto exception;
4859 break;
4860 case VCPU_SREG_CS:
4861 if (!(kvm_seg.type & 8))
4862 goto exception;
4863
4864 if (kvm_seg.type & 4) {
4865 /* conforming */
4866 if (dpl > cpl)
4867 goto exception;
4868 } else {
4869 /* nonconforming */
4870 if (rpl > cpl || dpl != cpl)
4871 goto exception;
4872 }
4873 /* CS(RPL) <- CPL */
4874 selector = (selector & 0xfffc) | cpl;
4875 break;
4876 case VCPU_SREG_TR:
4877 if (kvm_seg.s || (kvm_seg.type != 1 && kvm_seg.type != 9))
4878 goto exception;
4879 break;
4880 case VCPU_SREG_LDTR:
4881 if (kvm_seg.s || kvm_seg.type != 2)
4882 goto exception;
4883 break;
4884 default: /* DS, ES, FS, or GS */
4885 /*
4886 * segment is not a data or readable code segment or
4887 * ((segment is a data or nonconforming code segment)
4888 * and (both RPL and CPL > DPL))
4889 */
4890 if ((kvm_seg.type & 0xa) == 0x8 ||
4891 (((kvm_seg.type & 0xc) != 0xc) && (rpl > dpl && cpl > dpl)))
4892 goto exception;
4893 break;
4894 }
4895
4896 if (!kvm_seg.unusable && kvm_seg.s) {
e01c2426 4897 /* mark segment as accessed */
c697518a 4898 kvm_seg.type |= 1;
e01c2426
GN		 4899 seg_desc.type |= 1;
4900 save_guest_segment_descriptor(vcpu, selector, &seg_desc);
4901 }
c697518a
GN		 4902load:
4903 kvm_set_segment(vcpu, &kvm_seg, seg);
4904 return X86EMUL_CONTINUE;
4905exception:
4906 kvm_queue_exception_e(vcpu, err_vec, err_code);
4907 return X86EMUL_PROPAGATE_FAULT;
37817f29
IE		 4908}
4909
4910static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4911 struct tss_segment_32 *tss)
4912{
4913 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4914 tss->eip = kvm_rip_read(vcpu);
91586a3b 4915 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4916 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4917 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4918 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4919 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4920 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4921 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4922 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4923 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4924 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4925 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4926 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4927 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4928 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4929 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4930 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4931}
4932
c697518a
GN		 4933static void kvm_load_segment_selector(struct kvm_vcpu *vcpu, u16 sel, int seg)
4934{
4935 struct kvm_segment kvm_seg;
4936 kvm_get_segment(vcpu, &kvm_seg, seg);
4937 kvm_seg.selector = sel;
4938 kvm_set_segment(vcpu, &kvm_seg, seg);
4939}
4940
37817f29
IE		 4941static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4942 struct tss_segment_32 *tss)
4943{
4944 kvm_set_cr3(vcpu, tss->cr3);
4945
5fdbf976 4946 kvm_rip_write(vcpu, tss->eip);
91586a3b 4947 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4948
5fdbf976
MT		 4949 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4950 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4951 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4952 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4953 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4954 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4955 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4956 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4957
c697518a
GN		 4958 /*
4959 * SDM says that segment selectors are loaded before segment
4960 * descriptors
4961 */
4962 kvm_load_segment_selector(vcpu, tss->ldt_selector, VCPU_SREG_LDTR);
4963 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
4964 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
4965 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
4966 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
4967 kvm_load_segment_selector(vcpu, tss->fs, VCPU_SREG_FS);
4968 kvm_load_segment_selector(vcpu, tss->gs, VCPU_SREG_GS);
4969
4970 /*
4971 * Now load segment descriptors. If fault happenes at this stage
4972 * it is handled in a context of new task
4973 */
4974 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, VCPU_SREG_LDTR))
37817f29
IE		 4975 return 1;
4976
c697518a 4977 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 4978 return 1;
4979
c697518a 4980 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 4981 return 1;
4982
c697518a 4983 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 4984 return 1;
4985
c697518a 4986 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 4987 return 1;
4988
c697518a 4989 if (kvm_load_segment_descriptor(vcpu, tss->fs, VCPU_SREG_FS))
37817f29
IE		 4990 return 1;
4991
c697518a 4992 if (kvm_load_segment_descriptor(vcpu, tss->gs, VCPU_SREG_GS))
37817f29
IE		 4993 return 1;
4994 return 0;
4995}
4996
4997static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4998 struct tss_segment_16 *tss)
4999{
5fdbf976 5000 tss->ip = kvm_rip_read(vcpu);
91586a3b 5001 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 5002 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5003 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5004 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5005 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5006 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5007 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5008 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
5009 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 5010
5011 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
5012 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
5013 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
5014 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
5015 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 5016}
5017
5018static int load_state_from_tss16(struct kvm_vcpu *vcpu,
5019 struct tss_segment_16 *tss)
5020{
5fdbf976 5021 kvm_rip_write(vcpu, tss->ip);
91586a3b 5022 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 5023 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
5024 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
5025 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
5026 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
5027 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
5028 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
5029 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
5030 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 5031
c697518a
GN		 5032 /*
5033 * SDM says that segment selectors are loaded before segment
5034 * descriptors
5035 */
5036 kvm_load_segment_selector(vcpu, tss->ldt, VCPU_SREG_LDTR);
5037 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5038 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5039 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5040 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5041
5042 /*
5043 * Now load segment descriptors. If fault happenes at this stage
5044 * it is handled in a context of new task
5045 */
5046 if (kvm_load_segment_descriptor(vcpu, tss->ldt, VCPU_SREG_LDTR))
37817f29
IE		 5047 return 1;
5048
c697518a 5049 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5050 return 1;
5051
c697518a 5052 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5053 return 1;
5054
c697518a 5055 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5056 return 1;
5057
c697518a 5058 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5059 return 1;
5060 return 0;
5061}
5062
8b2cf73c 5063static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 5064 u16 old_tss_sel, u32 old_tss_base,
5065 struct desc_struct *nseg_desc)
37817f29
IE		 5066{
5067 struct tss_segment_16 tss_segment_16;
5068 int ret = 0;
5069
34198bf8
MT		 5070 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5071 sizeof tss_segment_16))
37817f29
IE		 5072 goto out;
5073
5074 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 5075
34198bf8
MT		 5076 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5077 sizeof tss_segment_16))
37817f29 5078 goto out;
34198bf8 5079
1871c602 5080 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8
MT		 5081 &tss_segment_16, sizeof tss_segment_16))
5082 goto out;
5083
b237ac37
GN		 5084 if (old_tss_sel != 0xffff) {
5085 tss_segment_16.prev_task_link = old_tss_sel;
5086
5087 if (kvm_write_guest(vcpu->kvm,
1871c602 5088 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5089 &tss_segment_16.prev_task_link,
5090 sizeof tss_segment_16.prev_task_link))
5091 goto out;
5092 }
5093
37817f29
IE		 5094 if (load_state_from_tss16(vcpu, &tss_segment_16))
5095 goto out;
5096
5097 ret = 1;
5098out:
5099 return ret;
5100}
5101
8b2cf73c 5102static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 5103 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 5104 struct desc_struct *nseg_desc)
5105{
5106 struct tss_segment_32 tss_segment_32;
5107 int ret = 0;
5108
34198bf8
MT		 5109 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5110 sizeof tss_segment_32))
37817f29
IE		 5111 goto out;
5112
5113 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 5114
34198bf8
MT		 5115 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5116 sizeof tss_segment_32))
5117 goto out;
5118
1871c602 5119 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8 5120 &tss_segment_32, sizeof tss_segment_32))
37817f29 5121 goto out;
34198bf8 5122
b237ac37
GN		 5123 if (old_tss_sel != 0xffff) {
5124 tss_segment_32.prev_task_link = old_tss_sel;
5125
5126 if (kvm_write_guest(vcpu->kvm,
1871c602 5127 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5128 &tss_segment_32.prev_task_link,
5129 sizeof tss_segment_32.prev_task_link))
5130 goto out;
5131 }
5132
37817f29
IE		 5133 if (load_state_from_tss32(vcpu, &tss_segment_32))
5134 goto out;
5135
5136 ret = 1;
5137out:
5138 return ret;
5139}
5140
5141int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
5142{
5143 struct kvm_segment tr_seg;
5144 struct desc_struct cseg_desc;
5145 struct desc_struct nseg_desc;
5146 int ret = 0;
34198bf8
MT		 5147 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
5148 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 5149
1871c602 5150 old_tss_base = kvm_mmu_gva_to_gpa_write(vcpu, old_tss_base, NULL);
37817f29 5151
34198bf8
MT		 5152 /* FIXME: Handle errors. Failure to read either TSS or their
5153 * descriptors should generate a pagefault.
5154 */
37817f29
IE		 5155 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
5156 goto out;
5157
34198bf8 5158 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 5159 goto out;
5160
37817f29
IE		 5161 if (reason != TASK_SWITCH_IRET) {
5162 int cpl;
5163
5164 cpl = kvm_x86_ops->get_cpl(vcpu);
5165 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
5166 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
5167 return 1;
5168 }
5169 }
5170
46a359e7 5171 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 5172 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
5173 return 1;
5174 }
5175
5176 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 5177 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 5178 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 5179 }
5180
5181 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 5182 u32 eflags = kvm_get_rflags(vcpu);
5183 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 5184 }
5185
b237ac37
GN		 5186 /* set back link to prev task only if NT bit is set in eflags
5187 note that old_tss_sel is not used afetr this point */
5188 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
5189 old_tss_sel = 0xffff;
5190
37817f29 5191 if (nseg_desc.type & 8)
b237ac37
GN		 5192 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
5193 old_tss_base, &nseg_desc);
37817f29 5194 else
b237ac37
GN		 5195 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
5196 old_tss_base, &nseg_desc);
37817f29
IE		 5197
5198 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 5199 u32 eflags = kvm_get_rflags(vcpu);
5200 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 5201 }
5202
5203 if (reason != TASK_SWITCH_IRET) {
3fe913e7 5204 nseg_desc.type |= (1 << 1);
37817f29
IE		 5205 save_guest_segment_descriptor(vcpu, tss_selector,
5206 &nseg_desc);
5207 }
5208
4d4ec087 5209 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS);
37817f29
IE		 5210 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
5211 tr_seg.type = 11;
3e6e0aab 5212 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 5213out:
37817f29
IE		 5214 return ret;
5215}
5216EXPORT_SYMBOL_GPL(kvm_task_switch);
5217
b6c7a5dc
HB		 5218int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5219 struct kvm_sregs *sregs)
5220{
5221 int mmu_reset_needed = 0;
923c61bb 5222 int pending_vec, max_bits;
b6c7a5dc
HB		 5223 struct descriptor_table dt;
5224
5225 vcpu_load(vcpu);
5226
5227 dt.limit = sregs->idt.limit;
5228 dt.base = sregs->idt.base;
5229 kvm_x86_ops->set_idt(vcpu, &dt);
5230 dt.limit = sregs->gdt.limit;
5231 dt.base = sregs->gdt.base;
5232 kvm_x86_ops->set_gdt(vcpu, &dt);
5233
ad312c7c
ZX		 5234 vcpu->arch.cr2 = sregs->cr2;
5235 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5236 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5237
2d3ad1f4 5238 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5239
f6801dff 5240 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5241 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5242 kvm_set_apic_base(vcpu, sregs->apic_base);
5243
4d4ec087 5244 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5245 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5246 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5247
fc78f519 5248 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5249 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5250 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5251 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5252 mmu_reset_needed = 1;
5253 }
b6c7a5dc
HB		 5254
5255 if (mmu_reset_needed)
5256 kvm_mmu_reset_context(vcpu);
5257
923c61bb
GN		 5258 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5259 pending_vec = find_first_bit(
5260 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5261 if (pending_vec < max_bits) {
66fd3f7f 5262 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5263 pr_debug("Set back pending irq %d\n", pending_vec);
5264 if (irqchip_in_kernel(vcpu->kvm))
5265 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5266 }
5267
3e6e0aab
GT		 5268 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5269 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5270 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5271 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5272 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5273 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5274
3e6e0aab
GT		 5275 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5276 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5277
5f0269f5
ME		 5278 update_cr8_intercept(vcpu);
5279
9c3e4aab 5280 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5281 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5282 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5283 !is_protmode(vcpu))
9c3e4aab
MT		 5284 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5285
b6c7a5dc
HB		 5286 vcpu_put(vcpu);
5287
5288 return 0;
5289}
5290
d0bfb940
JK		 5291int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5292 struct kvm_guest_debug *dbg)
b6c7a5dc 5293{
355be0b9 5294 unsigned long rflags;
ae675ef0 5295 int i, r;
b6c7a5dc
HB		 5296
5297 vcpu_load(vcpu);
5298
4f926bf2
JK		 5299 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5300 r = -EBUSY;
5301 if (vcpu->arch.exception.pending)
5302 goto unlock_out;
5303 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5304 kvm_queue_exception(vcpu, DB_VECTOR);
5305 else
5306 kvm_queue_exception(vcpu, BP_VECTOR);
5307 }
5308
91586a3b
JK		 5309 /*
5310 * Read rflags as long as potentially injected trace flags are still
5311 * filtered out.
5312 */
5313 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5314
5315 vcpu->guest_debug = dbg->control;
5316 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5317 vcpu->guest_debug = 0;
5318
5319 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5320 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5321 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5322 vcpu->arch.switch_db_regs =
5323 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5324 } else {
5325 for (i = 0; i < KVM_NR_DB_REGS; i++)
5326 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5327 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5328 }
5329
94fe45da
JK		 5330 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5331 vcpu->arch.singlestep_cs =
5332 get_segment_selector(vcpu, VCPU_SREG_CS);
5333 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
5334 }
5335
91586a3b
JK		 5336 /*
5337 * Trigger an rflags update that will inject or remove the trace
5338 * flags.
5339 */
5340 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5341
355be0b9 5342 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5343
4f926bf2 5344 r = 0;
d0bfb940 5345
4f926bf2 5346unlock_out:
b6c7a5dc
HB		 5347 vcpu_put(vcpu);
5348
5349 return r;
5350}
5351
d0752060
HB		 5352/*
5353 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5354 * we have asm/x86/processor.h
5355 */
5356struct fxsave {
5357 u16 cwd;
5358 u16 swd;
5359 u16 twd;
5360 u16 fop;
5361 u64 rip;
5362 u64 rdp;
5363 u32 mxcsr;
5364 u32 mxcsr_mask;
5365 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5366#ifdef CONFIG_X86_64
5367 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5368#else
5369 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5370#endif
5371};
5372
8b006791
ZX		 5373/*
5374 * Translate a guest virtual address to a guest physical address.
5375 */
5376int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5377 struct kvm_translation *tr)
5378{
5379 unsigned long vaddr = tr->linear_address;
5380 gpa_t gpa;
f656ce01 5381 int idx;
8b006791
ZX		 5382
5383 vcpu_load(vcpu);
f656ce01 5384 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5385 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5386 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5387 tr->physical_address = gpa;
5388 tr->valid = gpa != UNMAPPED_GVA;
5389 tr->writeable = 1;
5390 tr->usermode = 0;
8b006791
ZX		 5391 vcpu_put(vcpu);
5392
5393 return 0;
5394}
5395
d0752060
HB		 5396int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5397{
ad312c7c 5398 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5399
5400 vcpu_load(vcpu);
5401
5402 memcpy(fpu->fpr, fxsave->st_space, 128);
5403 fpu->fcw = fxsave->cwd;
5404 fpu->fsw = fxsave->swd;
5405 fpu->ftwx = fxsave->twd;
5406 fpu->last_opcode = fxsave->fop;
5407 fpu->last_ip = fxsave->rip;
5408 fpu->last_dp = fxsave->rdp;
5409 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5410
5411 vcpu_put(vcpu);
5412
5413 return 0;
5414}
5415
5416int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5417{
ad312c7c 5418 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5419
5420 vcpu_load(vcpu);
5421
5422 memcpy(fxsave->st_space, fpu->fpr, 128);
5423 fxsave->cwd = fpu->fcw;
5424 fxsave->swd = fpu->fsw;
5425 fxsave->twd = fpu->ftwx;
5426 fxsave->fop = fpu->last_opcode;
5427 fxsave->rip = fpu->last_ip;
5428 fxsave->rdp = fpu->last_dp;
5429 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5430
5431 vcpu_put(vcpu);
5432
5433 return 0;
5434}
5435
5436void fx_init(struct kvm_vcpu *vcpu)
5437{
5438 unsigned after_mxcsr_mask;
5439
bc1a34f1
AA		 5440 /*
5441 * Touch the fpu the first time in non atomic context as if
5442 * this is the first fpu instruction the exception handler
5443 * will fire before the instruction returns and it'll have to
5444 * allocate ram with GFP_KERNEL.
5445 */
5446 if (!used_math())
d6e88aec 5447 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5448
d0752060
HB		 5449 /* Initialize guest FPU by resetting ours and saving into guest's */
5450 preempt_disable();
d6e88aec
AK		 5451 kvm_fx_save(&vcpu->arch.host_fx_image);
5452 kvm_fx_finit();
5453 kvm_fx_save(&vcpu->arch.guest_fx_image);
5454 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5455 preempt_enable();
5456
ad312c7c 5457 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5458 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5459 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5460 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5461 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5462}
5463EXPORT_SYMBOL_GPL(fx_init);
5464
5465void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5466{
2608d7a1 5467 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5468 return;
5469
5470 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5471 kvm_fx_save(&vcpu->arch.host_fx_image);
5472 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5473 trace_kvm_fpu(1);
d0752060 5474}
d0752060
HB		 5475
5476void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5477{
5478 if (!vcpu->guest_fpu_loaded)
5479 return;
5480
5481 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5482 kvm_fx_save(&vcpu->arch.guest_fx_image);
5483 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5484 ++vcpu->stat.fpu_reload;
02daab21 5485 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5486 trace_kvm_fpu(0);
d0752060 5487}
e9b11c17
ZX		 5488
5489void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5490{
7f1ea208
JR		 5491 if (vcpu->arch.time_page) {
5492 kvm_release_page_dirty(vcpu->arch.time_page);
5493 vcpu->arch.time_page = NULL;
5494 }
5495
e9b11c17
ZX		 5496 kvm_x86_ops->vcpu_free(vcpu);
5497}
5498
5499struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5500 unsigned int id)
5501{
26e5215f
AK		 5502 return kvm_x86_ops->vcpu_create(kvm, id);
5503}
e9b11c17 5504
26e5215f
AK		 5505int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5506{
5507 int r;
e9b11c17
ZX		 5508
5509 /* We do fxsave: this must be aligned. */
ad312c7c 5510 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5511
0bed3b56 5512 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5513 vcpu_load(vcpu);
5514 r = kvm_arch_vcpu_reset(vcpu);
5515 if (r == 0)
5516 r = kvm_mmu_setup(vcpu);
5517 vcpu_put(vcpu);
5518 if (r < 0)
5519 goto free_vcpu;
5520
26e5215f 5521 return 0;
e9b11c17
ZX		 5522free_vcpu:
5523 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5524 return r;
e9b11c17
ZX		 5525}
5526
d40ccc62 5527void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5528{
5529 vcpu_load(vcpu);
5530 kvm_mmu_unload(vcpu);
5531 vcpu_put(vcpu);
5532
5533 kvm_x86_ops->vcpu_free(vcpu);
5534}
5535
5536int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5537{
448fa4a9
JK		 5538 vcpu->arch.nmi_pending = false;
5539 vcpu->arch.nmi_injected = false;
5540
42dbaa5a
JK		 5541 vcpu->arch.switch_db_regs = 0;
5542 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5543 vcpu->arch.dr6 = DR6_FIXED_1;
5544 vcpu->arch.dr7 = DR7_FIXED_1;
5545
e9b11c17
ZX		 5546 return kvm_x86_ops->vcpu_reset(vcpu);
5547}
5548
10474ae8 5549int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5550{
0cca7907
ZA		 5551 /*
5552 * Since this may be called from a hotplug notifcation,
5553 * we can't get the CPU frequency directly.
5554 */
5555 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5556 int cpu = raw_smp_processor_id();
5557 per_cpu(cpu_tsc_khz, cpu) = 0;
5558 }
18863bdd
AK		 5559
5560 kvm_shared_msr_cpu_online();
5561
10474ae8 5562 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5563}
5564
5565void kvm_arch_hardware_disable(void *garbage)
5566{
5567 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5568 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5569}
5570
5571int kvm_arch_hardware_setup(void)
5572{
5573 return kvm_x86_ops->hardware_setup();
5574}
5575
5576void kvm_arch_hardware_unsetup(void)
5577{
5578 kvm_x86_ops->hardware_unsetup();
5579}
5580
5581void kvm_arch_check_processor_compat(void *rtn)
5582{
5583 kvm_x86_ops->check_processor_compatibility(rtn);
5584}
5585
5586int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5587{
5588 struct page *page;
5589 struct kvm *kvm;
5590 int r;
5591
5592 BUG_ON(vcpu->kvm == NULL);
5593 kvm = vcpu->kvm;
5594
ad312c7c 5595 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5596 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5597 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5598 else
a4535290 5599 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5600
5601 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5602 if (!page) {
5603 r = -ENOMEM;
5604 goto fail;
5605 }
ad312c7c 5606 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5607
5608 r = kvm_mmu_create(vcpu);
5609 if (r < 0)
5610 goto fail_free_pio_data;
5611
5612 if (irqchip_in_kernel(kvm)) {
5613 r = kvm_create_lapic(vcpu);
5614 if (r < 0)
5615 goto fail_mmu_destroy;
5616 }
5617
890ca9ae
HY		 5618 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5619 GFP_KERNEL);
5620 if (!vcpu->arch.mce_banks) {
5621 r = -ENOMEM;
443c39bc 5622 goto fail_free_lapic;
890ca9ae
HY		 5623 }
5624 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5625
e9b11c17 5626 return 0;
443c39bc
WY		 5627fail_free_lapic:
5628 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5629fail_mmu_destroy:
5630 kvm_mmu_destroy(vcpu);
5631fail_free_pio_data:
ad312c7c 5632 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5633fail:
5634 return r;
5635}
5636
5637void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5638{
f656ce01
MT		 5639 int idx;
5640
36cb93fd 5641 kfree(vcpu->arch.mce_banks);
e9b11c17 5642 kvm_free_lapic(vcpu);
f656ce01 5643 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5644 kvm_mmu_destroy(vcpu);
f656ce01 5645 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5646 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5647}
d19a9cd2
ZX		 5648
5649struct kvm *kvm_arch_create_vm(void)
5650{
5651 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5652
5653 if (!kvm)
5654 return ERR_PTR(-ENOMEM);
5655
fef9cce0
MT		 5656 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5657 if (!kvm->arch.aliases) {
5658 kfree(kvm);
5659 return ERR_PTR(-ENOMEM);
5660 }
5661
f05e70ac 5662 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5663 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5664
5550af4d
SY		 5665 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5666 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5667
53f658b3
MT		 5668 rdtscll(kvm->arch.vm_init_tsc);
5669
d19a9cd2
ZX		 5670 return kvm;
5671}
5672
5673static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5674{
5675 vcpu_load(vcpu);
5676 kvm_mmu_unload(vcpu);
5677 vcpu_put(vcpu);
5678}
5679
5680static void kvm_free_vcpus(struct kvm *kvm)
5681{
5682 unsigned int i;
988a2cae 5683 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5684
5685 /*
5686 * Unpin any mmu pages first.
5687 */
988a2cae
GN		 5688 kvm_for_each_vcpu(i, vcpu, kvm)
5689 kvm_unload_vcpu_mmu(vcpu);
5690 kvm_for_each_vcpu(i, vcpu, kvm)
5691 kvm_arch_vcpu_free(vcpu);
5692
5693 mutex_lock(&kvm->lock);
5694 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5695 kvm->vcpus[i] = NULL;
d19a9cd2 5696
988a2cae
GN		 5697 atomic_set(&kvm->online_vcpus, 0);
5698 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5699}
5700
ad8ba2cd
SY		 5701void kvm_arch_sync_events(struct kvm *kvm)
5702{
ba4cef31 5703 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5704}
5705
d19a9cd2
ZX		 5706void kvm_arch_destroy_vm(struct kvm *kvm)
5707{
6eb55818 5708 kvm_iommu_unmap_guest(kvm);
7837699f 5709 kvm_free_pit(kvm);
d7deeeb0
ZX		 5710 kfree(kvm->arch.vpic);
5711 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5712 kvm_free_vcpus(kvm);
5713 kvm_free_physmem(kvm);
3d45830c
AK		 5714 if (kvm->arch.apic_access_page)
5715 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5716 if (kvm->arch.ept_identity_pagetable)
5717 put_page(kvm->arch.ept_identity_pagetable);
64749204 5718 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5719 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5720 kfree(kvm);
5721}
0de10343 5722
f7784b8e
MT		 5723int kvm_arch_prepare_memory_region(struct kvm *kvm,
5724 struct kvm_memory_slot *memslot,
0de10343 5725 struct kvm_memory_slot old,
f7784b8e 5726 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5727 int user_alloc)
5728{
f7784b8e 5729 int npages = memslot->npages;
0de10343
ZX		 5730
5731 /*To keep backward compatibility with older userspace,
5732 *x86 needs to hanlde !user_alloc case.
5733 */
5734 if (!user_alloc) {
5735 if (npages && !old.rmap) {
604b38ac
AA		 5736 unsigned long userspace_addr;
5737
72dc67a6 5738 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5739 userspace_addr = do_mmap(NULL, 0,
5740 npages * PAGE_SIZE,
5741 PROT_READ | PROT_WRITE,
acee3c04 5742 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5743 0);
72dc67a6 5744 up_write(&current->mm->mmap_sem);
0de10343 5745
604b38ac
AA		 5746 if (IS_ERR((void *)userspace_addr))
5747 return PTR_ERR((void *)userspace_addr);
5748
604b38ac 5749 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5750 }
5751 }
5752
f7784b8e
MT		 5753
5754 return 0;
5755}
5756
5757void kvm_arch_commit_memory_region(struct kvm *kvm,
5758 struct kvm_userspace_memory_region *mem,
5759 struct kvm_memory_slot old,
5760 int user_alloc)
5761{
5762
5763 int npages = mem->memory_size >> PAGE_SHIFT;
5764
5765 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5766 int ret;
5767
5768 down_write(&current->mm->mmap_sem);
5769 ret = do_munmap(current->mm, old.userspace_addr,
5770 old.npages * PAGE_SIZE);
5771 up_write(&current->mm->mmap_sem);
5772 if (ret < 0)
5773 printk(KERN_WARNING
5774 "kvm_vm_ioctl_set_memory_region: "
5775 "failed to munmap memory\n");
5776 }
5777
7c8a83b7 5778 spin_lock(&kvm->mmu_lock);
f05e70ac 5779 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5780 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5781 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5782 }
5783
5784 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5785 spin_unlock(&kvm->mmu_lock);
0de10343 5786}
1d737c8a 5787
34d4cb8f
MT		 5788void kvm_arch_flush_shadow(struct kvm *kvm)
5789{
5790 kvm_mmu_zap_all(kvm);
8986ecc0 5791 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5792}
5793
1d737c8a
ZX		 5794int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5795{
a4535290 5796 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5797 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5798 || vcpu->arch.nmi_pending ||
5799 (kvm_arch_interrupt_allowed(vcpu) &&
5800 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5801}
5736199a 5802
5736199a
ZX		 5803void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5804{
32f88400
MT		 5805 int me;
5806 int cpu = vcpu->cpu;
5736199a
ZX		 5807
5808 if (waitqueue_active(&vcpu->wq)) {
5809 wake_up_interruptible(&vcpu->wq);
5810 ++vcpu->stat.halt_wakeup;
5811 }
32f88400
MT		 5812
5813 me = get_cpu();
5814 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5815 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5816 smp_send_reschedule(cpu);
e9571ed5 5817 put_cpu();
5736199a 5818}
78646121
GN		 5819
5820int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5821{
5822 return kvm_x86_ops->interrupt_allowed(vcpu);
5823}
229456fc 5824
94fe45da
JK		 5825unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5826{
5827 unsigned long rflags;
5828
5829 rflags = kvm_x86_ops->get_rflags(vcpu);
5830 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5831 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5832 return rflags;
5833}
5834EXPORT_SYMBOL_GPL(kvm_get_rflags);
5835
5836void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5837{
5838 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5839 vcpu->arch.singlestep_cs ==
5840 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5841 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5842 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5843 kvm_x86_ops->set_rflags(vcpu, rflags);
5844}
5845EXPORT_SYMBOL_GPL(kvm_set_rflags);
5846
229456fc
MT		 5847EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5848EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5849EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5850EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5851EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5852EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5853EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5854EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5855EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5856EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5857EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
Linux 6.x block layer and io_uring tree(s)