projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Revert "KVM: x86: Add a WARN on TIF_NEED_FPU_LOAD in kvm_load_guest_fpu()"
[linux-block.git] / arch / x86 / kvm / x86.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
043405e1
CO		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 17 */
18
edf88417 19#include <linux/kvm_host.h>
313a3dc7 20#include "irq.h"
1d737c8a 21#include "mmu.h"
7837699f 22#include "i8254.h"
37817f29 23#include "tss.h"
5fdbf976 24#include "kvm_cache_regs.h"
26eef70c 25#include "x86.h"
00b27a3e 26#include "cpuid.h"
474a5bb9 27#include "pmu.h"
e83d5887 28#include "hyperv.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
1767e931
PG		 35#include <linux/export.h>
36#include <linux/moduleparam.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
87276880
FW		 51#include <linux/kvm_irqfd.h>
52#include <linux/irqbypass.h>
3905f9ad 53#include <linux/sched/stat.h>
0c5f81da 54#include <linux/sched/isolation.h>
d0ec49d4 55#include <linux/mem_encrypt.h>
3905f9ad 56
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
b0c39dc6 68#include <asm/mshyperv.h>
0092e434 69#include <asm/hypervisor.h>
bf8c55d8 70#include <asm/intel_pt.h>
b3dc0695 71#include <asm/emulate_prefix.h>
dd2cb348 72#include <clocksource/hyperv_timer.h>
043405e1 73
d1898b73
DH		 74#define CREATE_TRACE_POINTS
75#include "trace.h"
76
313a3dc7 77#define MAX_IO_MSRS 256
890ca9ae 78#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 79u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 81
0f65dd70
AK		 82#define emul_to_vcpu(ctxt) \
83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
84
50a37eb4
JR		 85/* EFER defaults:
86 * - enable syscall per default because its emulated by KVM
87 * - enable LME and LMA per default on 64 bit KVM
88 */
89#ifdef CONFIG_X86_64
1260edbe
LJ		 90static
91u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 92#else
1260edbe 93static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 94#endif
313a3dc7 95
b11306b5
SC		 96static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
97
833b45de
PB		 98#define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
99#define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
417bc304 100
c519265f
RK		 101#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
102 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 103
cb142eb7 104static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 105static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 106static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 107static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 108static void store_regs(struct kvm_vcpu *vcpu);
109static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 110
893590c7 111struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 112EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 113
893590c7 114static bool __read_mostly ignore_msrs = 0;
476bc001 115module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 116
fab0aa3b
EM		 117static bool __read_mostly report_ignored_msrs = true;
118module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
119
4c27625b 120unsigned int min_timer_period_us = 200;
9ed96e87
MT		 121module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
122
630994b3
MT		 123static bool __read_mostly kvmclock_periodic_sync = true;
124module_param(kvmclock_periodic_sync, bool, S_IRUGO);
125
893590c7 126bool __read_mostly kvm_has_tsc_control;
92a1f12d 127EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 128u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 129EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 130u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
131EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
132u64 __read_mostly kvm_max_tsc_scaling_ratio;
133EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 134u64 __read_mostly kvm_default_tsc_scaling_ratio;
135EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 136
cc578287 137/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 138static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 139module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
140
c3941d9e
SC		 141/*
142 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
143 * adaptive tuning starting from default advancment of 1000ns. '0' disables
144 * advancement entirely. Any other value is used as-is and disables adaptive
145 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
146 */
147static int __read_mostly lapic_timer_advance_ns = -1;
0e6edceb 148module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
d0659d94 149
52004014
FW		 150static bool __read_mostly vector_hashing = true;
151module_param(vector_hashing, bool, S_IRUGO);
152
c4ae60e4
LA		 153bool __read_mostly enable_vmware_backdoor = false;
154module_param(enable_vmware_backdoor, bool, S_IRUGO);
155EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
156
6c86eedc
WL		 157static bool __read_mostly force_emulation_prefix = false;
158module_param(force_emulation_prefix, bool, S_IRUGO);
159
0c5f81da
WL		 160int __read_mostly pi_inject_timer = -1;
161module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
162
18863bdd
AK		 163#define KVM_NR_SHARED_MSRS 16
164
165struct kvm_shared_msrs_global {
166 int nr;
2bf78fa7 167 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 168};
169
170struct kvm_shared_msrs {
171 struct user_return_notifier urn;
172 bool registered;
2bf78fa7
SY		 173 struct kvm_shared_msr_values {
174 u64 host;
175 u64 curr;
176 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 177};
178
179static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 180static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 181
139a12cf
AL		 182static u64 __read_mostly host_xss;
183
417bc304 184struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 185 { "pf_fixed", VCPU_STAT(pf_fixed) },
186 { "pf_guest", VCPU_STAT(pf_guest) },
187 { "tlb_flush", VCPU_STAT(tlb_flush) },
188 { "invlpg", VCPU_STAT(invlpg) },
189 { "exits", VCPU_STAT(exits) },
190 { "io_exits", VCPU_STAT(io_exits) },
191 { "mmio_exits", VCPU_STAT(mmio_exits) },
192 { "signal_exits", VCPU_STAT(signal_exits) },
193 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 194 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 195 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 196 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 197 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 198 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 199 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 200 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 201 { "request_irq", VCPU_STAT(request_irq_exits) },
202 { "irq_exits", VCPU_STAT(irq_exits) },
203 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 204 { "fpu_reload", VCPU_STAT(fpu_reload) },
205 { "insn_emulation", VCPU_STAT(insn_emulation) },
206 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 207 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 208 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 209 { "req_event", VCPU_STAT(req_event) },
c595ceee 210 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 211 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
212 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
213 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
214 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
215 { "mmu_flooded", VM_STAT(mmu_flooded) },
216 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 217 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 218 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 219 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
833b45de 220 { "largepages", VM_STAT(lpages, .mode = 0444) },
b8e8c830 221 { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
f3414bc7
DM		 222 { "max_mmu_page_hash_collisions",
223 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 224 { NULL }
225};
226
2acf923e
DC		 227u64 __read_mostly host_xcr0;
228
b666a4b6
MO		 229struct kmem_cache *x86_fpu_cache;
230EXPORT_SYMBOL_GPL(x86_fpu_cache);
231
b6785def 232static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 233
af585b92
GN		 234static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
235{
236 int i;
237 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
238 vcpu->arch.apf.gfns[i] = ~0;
239}
240
18863bdd
AK		 241static void kvm_on_user_return(struct user_return_notifier *urn)
242{
243 unsigned slot;
18863bdd
AK		 244 struct kvm_shared_msrs *locals
245 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 246 struct kvm_shared_msr_values *values;
1650b4eb
IA		 247 unsigned long flags;
248
249 /*
250 * Disabling irqs at this point since the following code could be
251 * interrupted and executed through kvm_arch_hardware_disable()
252 */
253 local_irq_save(flags);
254 if (locals->registered) {
255 locals->registered = false;
256 user_return_notifier_unregister(urn);
257 }
258 local_irq_restore(flags);
18863bdd 259 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 260 values = &locals->values[slot];
261 if (values->host != values->curr) {
262 wrmsrl(shared_msrs_global.msrs[slot], values->host);
263 values->curr = values->host;
18863bdd
AK		 264 }
265 }
18863bdd
AK		 266}
267
2bf78fa7
SY		 268void kvm_define_shared_msr(unsigned slot, u32 msr)
269{
0123be42 270 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 271 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 272 if (slot >= shared_msrs_global.nr)
273 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 274}
275EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
276
277static void kvm_shared_msr_cpu_online(void)
278{
05c19c2f
SC		 279 unsigned int cpu = smp_processor_id();
280 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
281 u64 value;
282 int i;
18863bdd 283
05c19c2f
SC		 284 for (i = 0; i < shared_msrs_global.nr; ++i) {
285 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
286 smsr->values[i].host = value;
287 smsr->values[i].curr = value;
288 }
18863bdd
AK		 289}
290
8b3c3104 291int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 292{
013f6a5d
MT		 293 unsigned int cpu = smp_processor_id();
294 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 295 int err;
18863bdd 296
de1fca5d
PB		 297 value = (value & mask) | (smsr->values[slot].host & ~mask);
298 if (value == smsr->values[slot].curr)
8b3c3104 299 return 0;
8b3c3104
AH		 300 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
301 if (err)
302 return 1;
303
de1fca5d 304 smsr->values[slot].curr = value;
18863bdd
AK		 305 if (!smsr->registered) {
306 smsr->urn.on_user_return = kvm_on_user_return;
307 user_return_notifier_register(&smsr->urn);
308 smsr->registered = true;
309 }
8b3c3104 310 return 0;
18863bdd
AK		 311}
312EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
313
13a34e06 314static void drop_user_return_notifiers(void)
3548bab5 315{
013f6a5d
MT		 316 unsigned int cpu = smp_processor_id();
317 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 318
319 if (smsr->registered)
320 kvm_on_user_return(&smsr->urn);
321}
322
6866b83e
CO		 323u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
324{
8a5a87d9 325 return vcpu->arch.apic_base;
6866b83e
CO		 326}
327EXPORT_SYMBOL_GPL(kvm_get_apic_base);
328
58871649
JM		 329enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
330{
331 return kvm_apic_mode(kvm_get_apic_base(vcpu));
332}
333EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
334
58cb628d
JK		 335int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
336{
58871649
JM		 337 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
338 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 339 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
340 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 341
58871649 342 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 343 return 1;
58871649
JM		 344 if (!msr_info->host_initiated) {
345 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
346 return 1;
347 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
348 return 1;
349 }
58cb628d
JK		 350
351 kvm_lapic_set_base(vcpu, msr_info->data);
352 return 0;
6866b83e
CO		 353}
354EXPORT_SYMBOL_GPL(kvm_set_apic_base);
355
2605fc21 356asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 357{
358 /* Fault while not rebooting. We want the trace. */
b4fdcf60 359 BUG_ON(!kvm_rebooting);
e3ba45b8
GL		 360}
361EXPORT_SYMBOL_GPL(kvm_spurious_fault);
362
3fd28fce
ED		 363#define EXCPT_BENIGN 0
364#define EXCPT_CONTRIBUTORY 1
365#define EXCPT_PF 2
366
367static int exception_class(int vector)
368{
369 switch (vector) {
370 case PF_VECTOR:
371 return EXCPT_PF;
372 case DE_VECTOR:
373 case TS_VECTOR:
374 case NP_VECTOR:
375 case SS_VECTOR:
376 case GP_VECTOR:
377 return EXCPT_CONTRIBUTORY;
378 default:
379 break;
380 }
381 return EXCPT_BENIGN;
382}
383
d6e8c854
NA		 384#define EXCPT_FAULT 0
385#define EXCPT_TRAP 1
386#define EXCPT_ABORT 2
387#define EXCPT_INTERRUPT 3
388
389static int exception_type(int vector)
390{
391 unsigned int mask;
392
393 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
394 return EXCPT_INTERRUPT;
395
396 mask = 1 << vector;
397
398 /* #DB is trap, as instruction watchpoints are handled elsewhere */
399 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
400 return EXCPT_TRAP;
401
402 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
403 return EXCPT_ABORT;
404
405 /* Reserved exceptions will result in fault */
406 return EXCPT_FAULT;
407}
408
da998b46
JM		 409void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
410{
411 unsigned nr = vcpu->arch.exception.nr;
412 bool has_payload = vcpu->arch.exception.has_payload;
413 unsigned long payload = vcpu->arch.exception.payload;
414
415 if (!has_payload)
416 return;
417
418 switch (nr) {
f10c729f
JM		 419 case DB_VECTOR:
420 /*
421 * "Certain debug exceptions may clear bit 0-3. The
422 * remaining contents of the DR6 register are never
423 * cleared by the processor".
424 */
425 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
426 /*
427 * DR6.RTM is set by all #DB exceptions that don't clear it.
428 */
429 vcpu->arch.dr6 |= DR6_RTM;
430 vcpu->arch.dr6 |= payload;
431 /*
432 * Bit 16 should be set in the payload whenever the #DB
433 * exception should clear DR6.RTM. This makes the payload
434 * compatible with the pending debug exceptions under VMX.
435 * Though not currently documented in the SDM, this also
436 * makes the payload compatible with the exit qualification
437 * for #DB exceptions under VMX.
438 */
439 vcpu->arch.dr6 ^= payload & DR6_RTM;
440 break;
da998b46
JM		 441 case PF_VECTOR:
442 vcpu->arch.cr2 = payload;
443 break;
444 }
445
446 vcpu->arch.exception.has_payload = false;
447 vcpu->arch.exception.payload = 0;
448}
449EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
450
3fd28fce 451static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 452 unsigned nr, bool has_error, u32 error_code,
91e86d22 453 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 454{
455 u32 prev_nr;
456 int class1, class2;
457
3842d135
AK		 458 kvm_make_request(KVM_REQ_EVENT, vcpu);
459
664f8e26 460 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 461 queue:
3ffb2468
NA		 462 if (has_error && !is_protmode(vcpu))
463 has_error = false;
664f8e26
WL		 464 if (reinject) {
465 /*
466 * On vmentry, vcpu->arch.exception.pending is only
467 * true if an event injection was blocked by
468 * nested_run_pending. In that case, however,
469 * vcpu_enter_guest requests an immediate exit,
470 * and the guest shouldn't proceed far enough to
471 * need reinjection.
472 */
473 WARN_ON_ONCE(vcpu->arch.exception.pending);
474 vcpu->arch.exception.injected = true;
91e86d22
JM		 475 if (WARN_ON_ONCE(has_payload)) {
476 /*
477 * A reinjected event has already
478 * delivered its payload.
479 */
480 has_payload = false;
481 payload = 0;
482 }
664f8e26
WL		 483 } else {
484 vcpu->arch.exception.pending = true;
485 vcpu->arch.exception.injected = false;
486 }
3fd28fce
ED		 487 vcpu->arch.exception.has_error_code = has_error;
488 vcpu->arch.exception.nr = nr;
489 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 490 vcpu->arch.exception.has_payload = has_payload;
491 vcpu->arch.exception.payload = payload;
da998b46
JM		 492 /*
493 * In guest mode, payload delivery should be deferred,
494 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 495 * CR2 is modified (or intercept #DB before DR6 is
496 * modified under nVMX). However, for ABI
497 * compatibility with KVM_GET_VCPU_EVENTS and
498 * KVM_SET_VCPU_EVENTS, we can't delay payload
499 * delivery unless userspace has enabled this
500 * functionality via the per-VM capability,
501 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 502 */
503 if (!vcpu->kvm->arch.exception_payload_enabled ||
504 !is_guest_mode(vcpu))
505 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 506 return;
507 }
508
509 /* to check exception */
510 prev_nr = vcpu->arch.exception.nr;
511 if (prev_nr == DF_VECTOR) {
512 /* triple fault -> shutdown */
a8eeb04a 513 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 514 return;
515 }
516 class1 = exception_class(prev_nr);
517 class2 = exception_class(nr);
518 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
519 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 520 /*
521 * Generate double fault per SDM Table 5-5. Set
522 * exception.pending = true so that the double fault
523 * can trigger a nested vmexit.
524 */
3fd28fce 525 vcpu->arch.exception.pending = true;
664f8e26 526 vcpu->arch.exception.injected = false;
3fd28fce
ED		 527 vcpu->arch.exception.has_error_code = true;
528 vcpu->arch.exception.nr = DF_VECTOR;
529 vcpu->arch.exception.error_code = 0;
c851436a
JM		 530 vcpu->arch.exception.has_payload = false;
531 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 532 } else
533 /* replace previous exception with a new one in a hope
534 that instruction re-execution will regenerate lost
535 exception */
536 goto queue;
537}
538
298101da
AK		 539void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
540{
91e86d22 541 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 542}
543EXPORT_SYMBOL_GPL(kvm_queue_exception);
544
ce7ddec4
JR		 545void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
546{
91e86d22 547 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 548}
549EXPORT_SYMBOL_GPL(kvm_requeue_exception);
550
f10c729f
JM		 551static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
552 unsigned long payload)
553{
554 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
555}
556
da998b46
JM		 557static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
558 u32 error_code, unsigned long payload)
559{
560 kvm_multiple_exception(vcpu, nr, true, error_code,
561 true, payload, false);
562}
563
6affcbed 564int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 565{
db8fcefa
AP		 566 if (err)
567 kvm_inject_gp(vcpu, 0);
568 else
6affcbed
KH		 569 return kvm_skip_emulated_instruction(vcpu);
570
571 return 1;
db8fcefa
AP		 572}
573EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 574
6389ee94 575void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 576{
577 ++vcpu->stat.pf_guest;
adfe20fb
WL		 578 vcpu->arch.exception.nested_apf =
579 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 580 if (vcpu->arch.exception.nested_apf) {
adfe20fb 581 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 582 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
583 } else {
584 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
585 fault->address);
586 }
c3c91fee 587}
27d6c865 588EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 589
ef54bcfe 590static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 591{
6389ee94
AK		 592 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
593 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 594 else
44dd3ffa 595 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 596
597 return fault->nested_page_fault;
d4f8cf66
JR		 598}
599
3419ffc8
SY		 600void kvm_inject_nmi(struct kvm_vcpu *vcpu)
601{
7460fb4a
AK		 602 atomic_inc(&vcpu->arch.nmi_queued);
603 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 604}
605EXPORT_SYMBOL_GPL(kvm_inject_nmi);
606
298101da
AK		 607void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
608{
91e86d22 609 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 610}
611EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
612
ce7ddec4
JR		 613void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
614{
91e86d22 615 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 616}
617EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
618
0a79b009
AK		 619/*
620 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
621 * a #GP and return false.
622 */
623bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 624{
0a79b009
AK		 625 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
626 return true;
627 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
628 return false;
298101da 629}
0a79b009 630EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 631
16f8a6f9
NA		 632bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
633{
634 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
635 return true;
636
637 kvm_queue_exception(vcpu, UD_VECTOR);
638 return false;
639}
640EXPORT_SYMBOL_GPL(kvm_require_dr);
641
ec92fe44
JR		 642/*
643 * This function will be used to read from the physical memory of the currently
54bf36aa 644 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 645 * can read from guest physical or from the guest's guest physical memory.
646 */
647int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
648 gfn_t ngfn, void *data, int offset, int len,
649 u32 access)
650{
54987b7a 651 struct x86_exception exception;
ec92fe44
JR		 652 gfn_t real_gfn;
653 gpa_t ngpa;
654
655 ngpa = gfn_to_gpa(ngfn);
54987b7a 656 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 657 if (real_gfn == UNMAPPED_GVA)
658 return -EFAULT;
659
660 real_gfn = gpa_to_gfn(real_gfn);
661
54bf36aa 662 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 663}
664EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
665
69b0049a 666static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 667 void *data, int offset, int len, u32 access)
668{
669 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
670 data, offset, len, access);
671}
672
16cfacc8
SC		 673static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
674{
675 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
676 rsvd_bits(1, 2);
677}
678
a03490ed 679/*
16cfacc8 680 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
a03490ed 681 */
ff03a073 682int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 683{
684 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
685 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
686 int i;
687 int ret;
ff03a073 688 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 689
ff03a073
JR		 690 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
691 offset * sizeof(u64), sizeof(pdpte),
692 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 693 if (ret < 0) {
694 ret = 0;
695 goto out;
696 }
697 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 698 if ((pdpte[i] & PT_PRESENT_MASK) &&
16cfacc8 699 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
a03490ed
CO		 700 ret = 0;
701 goto out;
702 }
703 }
704 ret = 1;
705
ff03a073 706 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
cb3c1e2f
SC		 707 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
708
a03490ed 709out:
a03490ed
CO		 710
711 return ret;
712}
cc4b6871 713EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 714
9ed38ffa 715bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 716{
ff03a073 717 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
3d06b8bf
JR		 718 int offset;
719 gfn_t gfn;
d835dfec
AK		 720 int r;
721
bf03d4f9 722 if (!is_pae_paging(vcpu))
d835dfec
AK		 723 return false;
724
cb3c1e2f 725 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
6de4f3ad
AK		 726 return true;
727
a512177e
PB		 728 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
729 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 730 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
731 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec 732 if (r < 0)
7f7f0d9c 733 return true;
d835dfec 734
7f7f0d9c 735 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 736}
9ed38ffa 737EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 738
49a9b07e 739int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 740{
aad82703 741 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 742 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 743
f9a48e6a
AK		 744 cr0 |= X86_CR0_ET;
745
ab344828 746#ifdef CONFIG_X86_64
0f12244f
GN		 747 if (cr0 & 0xffffffff00000000UL)
748 return 1;
ab344828
GN		 749#endif
750
751 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 752
0f12244f
GN		 753 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
754 return 1;
a03490ed 755
0f12244f
GN		 756 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
757 return 1;
a03490ed
CO		 758
759 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
760#ifdef CONFIG_X86_64
f6801dff 761 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 762 int cs_db, cs_l;
763
0f12244f
GN		 764 if (!is_pae(vcpu))
765 return 1;
a03490ed 766 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 767 if (cs_l)
768 return 1;
a03490ed
CO		 769 } else
770#endif
ff03a073 771 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 772 kvm_read_cr3(vcpu)))
0f12244f 773 return 1;
a03490ed
CO		 774 }
775
ad756a16
MJ		 776 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
777 return 1;
778
a03490ed 779 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 780
d170c419 781 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 782 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 783 kvm_async_pf_hash_reset(vcpu);
784 }
e5f3f027 785
aad82703
SY		 786 if ((cr0 ^ old_cr0) & update_bits)
787 kvm_mmu_reset_context(vcpu);
b18d5431 788
879ae188
LE		 789 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
790 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
791 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 792 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
793
0f12244f
GN		 794 return 0;
795}
2d3ad1f4 796EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 797
2d3ad1f4 798void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 799{
49a9b07e 800 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 803
139a12cf 804void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
42bdf991 805{
139a12cf
AL		 806 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
807
808 if (vcpu->arch.xcr0 != host_xcr0)
809 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
810
811 if (vcpu->arch.xsaves_enabled &&
812 vcpu->arch.ia32_xss != host_xss)
813 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
814 }
42bdf991 815}
139a12cf 816EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
42bdf991 817
139a12cf 818void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
42bdf991 819{
139a12cf
AL		 820 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
821
822 if (vcpu->arch.xcr0 != host_xcr0)
823 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
824
825 if (vcpu->arch.xsaves_enabled &&
826 vcpu->arch.ia32_xss != host_xss)
827 wrmsrl(MSR_IA32_XSS, host_xss);
828 }
829
42bdf991 830}
139a12cf 831EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
42bdf991 832
69b0049a 833static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 834{
56c103ec
LJ		 835 u64 xcr0 = xcr;
836 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 837 u64 valid_bits;
2acf923e
DC		 838
839 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
840 if (index != XCR_XFEATURE_ENABLED_MASK)
841 return 1;
d91cab78 842 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 843 return 1;
d91cab78 844 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 845 return 1;
46c34cb0
PB		 846
847 /*
848 * Do not allow the guest to set bits that we do not support
849 * saving. However, xcr0 bit 0 is always set, even if the
850 * emulated CPU does not support XSAVE (see fx_init).
851 */
d91cab78 852 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 853 if (xcr0 & ~valid_bits)
2acf923e 854 return 1;
46c34cb0 855
d91cab78
DH		 856 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
857 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 858 return 1;
859
d91cab78
DH		 860 if (xcr0 & XFEATURE_MASK_AVX512) {
861 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 862 return 1;
d91cab78 863 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 864 return 1;
865 }
2acf923e 866 vcpu->arch.xcr0 = xcr0;
56c103ec 867
d91cab78 868 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 869 kvm_update_cpuid(vcpu);
2acf923e
DC		 870 return 0;
871}
872
873int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
874{
764bcbc5
Z		 875 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
876 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 877 kvm_inject_gp(vcpu, 0);
878 return 1;
879 }
880 return 0;
881}
882EXPORT_SYMBOL_GPL(kvm_set_xcr);
883
345599f9
SC		 884#define __cr4_reserved_bits(__cpu_has, __c) \
885({ \
886 u64 __reserved_bits = CR4_RESERVED_BITS; \
887 \
888 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
889 __reserved_bits |= X86_CR4_OSXSAVE; \
890 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
891 __reserved_bits |= X86_CR4_SMEP; \
892 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
893 __reserved_bits |= X86_CR4_SMAP; \
894 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
895 __reserved_bits |= X86_CR4_FSGSBASE; \
896 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
897 __reserved_bits |= X86_CR4_PKE; \
898 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
899 __reserved_bits |= X86_CR4_LA57; \
900 __reserved_bits; \
901})
902
b11306b5
SC		 903static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c)
904{
345599f9 905 u64 reserved_bits = __cr4_reserved_bits(cpu_has, c);
b11306b5 906
87382003 907 if (cpuid_ecx(0x7) & feature_bit(LA57))
345599f9 908 reserved_bits &= ~X86_CR4_LA57;
b11306b5 909
345599f9
SC		 910 if (kvm_x86_ops->umip_emulated())
911 reserved_bits &= ~X86_CR4_UMIP;
b11306b5
SC		 912
913 return reserved_bits;
914}
915
3ca94192 916static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 917{
b11306b5 918 if (cr4 & cr4_reserved_bits)
3ca94192 919 return -EINVAL;
a03490ed 920
345599f9 921 if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
3ca94192
WL		 922 return -EINVAL;
923
924 return 0;
925}
926
927int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
928{
929 unsigned long old_cr4 = kvm_read_cr4(vcpu);
930 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
931 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
932
933 if (kvm_valid_cr4(vcpu, cr4))
ae3e61e1
PB		 934 return 1;
935
a03490ed 936 if (is_long_mode(vcpu)) {
0f12244f
GN		 937 if (!(cr4 & X86_CR4_PAE))
938 return 1;
a2edf57f
AK		 939 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
940 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 941 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
942 kvm_read_cr3(vcpu)))
0f12244f
GN		 943 return 1;
944
ad756a16 945 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 946 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 947 return 1;
948
949 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
950 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
951 return 1;
952 }
953
5e1746d6 954 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 955 return 1;
a03490ed 956
ad756a16
MJ		 957 if (((cr4 ^ old_cr4) & pdptr_bits) ||
958 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 959 kvm_mmu_reset_context(vcpu);
0f12244f 960
b9baba86 961 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 962 kvm_update_cpuid(vcpu);
2acf923e 963
0f12244f
GN		 964 return 0;
965}
2d3ad1f4 966EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 967
2390218b 968int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 969{
ade61e28 970 bool skip_tlb_flush = false;
ac146235 971#ifdef CONFIG_X86_64
c19986fe
JS		 972 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
973
ade61e28 974 if (pcid_enabled) {
208320ba
JS		 975 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
976 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 977 }
ac146235 978#endif
9d88fca7 979
9f8fe504 980 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 981 if (!skip_tlb_flush) {
982 kvm_mmu_sync_roots(vcpu);
ade61e28 983 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 984 }
0f12244f 985 return 0;
d835dfec
AK		 986 }
987
d1cd3ce9 988 if (is_long_mode(vcpu) &&
a780a3ea 989 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9 990 return 1;
bf03d4f9
PB		 991 else if (is_pae_paging(vcpu) &&
992 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 993 return 1;
a03490ed 994
ade61e28 995 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 996 vcpu->arch.cr3 = cr3;
cb3c1e2f 997 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
7c390d35 998
0f12244f
GN		 999 return 0;
1000}
2d3ad1f4 1001EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 1002
eea1cff9 1003int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 1004{
0f12244f
GN		 1005 if (cr8 & CR8_RESERVED_BITS)
1006 return 1;
35754c98 1007 if (lapic_in_kernel(vcpu))
a03490ed
CO		 1008 kvm_lapic_set_tpr(vcpu, cr8);
1009 else
ad312c7c 1010 vcpu->arch.cr8 = cr8;
0f12244f
GN		 1011 return 0;
1012}
2d3ad1f4 1013EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 1014
2d3ad1f4 1015unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 1016{
35754c98 1017 if (lapic_in_kernel(vcpu))
a03490ed
CO		 1018 return kvm_lapic_get_cr8(vcpu);
1019 else
ad312c7c 1020 return vcpu->arch.cr8;
a03490ed 1021}
2d3ad1f4 1022EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 1023
ae561ede
NA		 1024static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1025{
1026 int i;
1027
1028 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1029 for (i = 0; i < KVM_NR_DB_REGS; i++)
1030 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1031 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1032 }
1033}
1034
73aaf249
JK		 1035static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1036{
1037 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1038 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1039}
1040
c8639010
JK		 1041static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1042{
1043 unsigned long dr7;
1044
1045 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1046 dr7 = vcpu->arch.guest_debug_dr7;
1047 else
1048 dr7 = vcpu->arch.dr7;
1049 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1050 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1051 if (dr7 & DR7_BP_EN_MASK)
1052 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1053}
1054
6f43ed01
NA		 1055static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1056{
1057 u64 fixed = DR6_FIXED_1;
1058
d6321d49 1059 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1060 fixed |= DR6_RTM;
1061 return fixed;
1062}
1063
338dbc97 1064static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079 1065{
ea740059
MP		 1066 size_t size = ARRAY_SIZE(vcpu->arch.db);
1067
020df079
GN		 1068 switch (dr) {
1069 case 0 ... 3:
ea740059 1070 vcpu->arch.db[array_index_nospec(dr, size)] = val;
020df079
GN		 1071 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1072 vcpu->arch.eff_db[dr] = val;
1073 break;
1074 case 4:
020df079
GN		 1075 /* fall through */
1076 case 6:
338dbc97
GN		 1077 if (val & 0xffffffff00000000ULL)
1078 return -1; /* #GP */
6f43ed01 1079 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1080 kvm_update_dr6(vcpu);
020df079
GN		 1081 break;
1082 case 5:
020df079
GN		 1083 /* fall through */
1084 default: /* 7 */
338dbc97
GN		 1085 if (val & 0xffffffff00000000ULL)
1086 return -1; /* #GP */
020df079 1087 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1088 kvm_update_dr7(vcpu);
020df079
GN		 1089 break;
1090 }
1091
1092 return 0;
1093}
338dbc97
GN		 1094
1095int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1096{
16f8a6f9 1097 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1098 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1099 return 1;
1100 }
1101 return 0;
338dbc97 1102}
020df079
GN		 1103EXPORT_SYMBOL_GPL(kvm_set_dr);
1104
16f8a6f9 1105int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079 1106{
ea740059
MP		 1107 size_t size = ARRAY_SIZE(vcpu->arch.db);
1108
020df079
GN		 1109 switch (dr) {
1110 case 0 ... 3:
ea740059 1111 *val = vcpu->arch.db[array_index_nospec(dr, size)];
020df079
GN		 1112 break;
1113 case 4:
020df079
GN		 1114 /* fall through */
1115 case 6:
73aaf249
JK		 1116 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1117 *val = vcpu->arch.dr6;
1118 else
1119 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1120 break;
1121 case 5:
020df079
GN		 1122 /* fall through */
1123 default: /* 7 */
1124 *val = vcpu->arch.dr7;
1125 break;
1126 }
338dbc97
GN		 1127 return 0;
1128}
020df079
GN		 1129EXPORT_SYMBOL_GPL(kvm_get_dr);
1130
022cd0e8
AK		 1131bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1132{
de3cd117 1133 u32 ecx = kvm_rcx_read(vcpu);
022cd0e8
AK		 1134 u64 data;
1135 int err;
1136
c6702c9d 1137 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1138 if (err)
1139 return err;
de3cd117
SC		 1140 kvm_rax_write(vcpu, (u32)data);
1141 kvm_rdx_write(vcpu, data >> 32);
022cd0e8
AK		 1142 return err;
1143}
1144EXPORT_SYMBOL_GPL(kvm_rdpmc);
1145
043405e1
CO		 1146/*
1147 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1148 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1149 *
7a5ee6ed
CQ		 1150 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1151 * extract the supported MSRs from the related const lists.
1152 * msrs_to_save is selected from the msrs_to_save_all to reflect the
e3267cbb 1153 * capabilities of the host cpu. This capabilities test skips MSRs that are
7a5ee6ed 1154 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
62ef68bb 1155 * may depend on host virtualization features rather than host cpu features.
043405e1 1156 */
e3267cbb 1157
7a5ee6ed 1158static const u32 msrs_to_save_all[] = {
043405e1 1159 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1160 MSR_STAR,
043405e1
CO		 1161#ifdef CONFIG_X86_64
1162 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1163#endif
b3897a49 1164 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1165 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1166 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1167 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1168 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1169 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1170 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1171 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1172 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
6e3ba4ab
TX		 1173 MSR_IA32_UMWAIT_CONTROL,
1174
e2ada66e
JM		 1175 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1176 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1177 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1178 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1179 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1180 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1181 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1182 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1183 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1184 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1185 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1186 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1187 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
e2ada66e
JM		 1188 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1189 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1190 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1191 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1192 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1193 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1194 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1195 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1196 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
043405e1
CO		 1197};
1198
7a5ee6ed 1199static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
043405e1
CO		 1200static unsigned num_msrs_to_save;
1201
7a5ee6ed 1202static const u32 emulated_msrs_all[] = {
62ef68bb
PB		 1203 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1204 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1205 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1206 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1207 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1208 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1209 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1210 HV_X64_MSR_RESET,
11c4b1ca 1211 HV_X64_MSR_VP_INDEX,
9eec50b8 1212 HV_X64_MSR_VP_RUNTIME,
5c919412 1213 HV_X64_MSR_SCONTROL,
1f4b34f8 1214 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1215 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1216 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1217 HV_X64_MSR_TSC_EMULATION_STATUS,
1218
1219 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1220 MSR_KVM_PV_EOI_EN,
1221
ba904635 1222 MSR_IA32_TSC_ADJUST,
a3e06bbe 1223 MSR_IA32_TSCDEADLINE,
2bdb76c0 1224 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1225 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1226 MSR_IA32_MCG_STATUS,
1227 MSR_IA32_MCG_CTL,
c45dcc71 1228 MSR_IA32_MCG_EXT_CTL,
64d60670 1229 MSR_IA32_SMBASE,
52797bf9 1230 MSR_SMI_COUNT,
db2336a8
KH		 1231 MSR_PLATFORM_INFO,
1232 MSR_MISC_FEATURES_ENABLES,
bc226f07 1233 MSR_AMD64_VIRT_SPEC_CTRL,
6c6a2ab9 1234 MSR_IA32_POWER_CTL,
99634e3e 1235 MSR_IA32_UCODE_REV,
191c8137 1236
95c5c7c7
PB		 1237 /*
1238 * The following list leaves out MSRs whose values are determined
1239 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1240 * We always support the "true" VMX control MSRs, even if the host
1241 * processor does not, so I am putting these registers here rather
7a5ee6ed 1242 * than in msrs_to_save_all.
95c5c7c7
PB		 1243 */
1244 MSR_IA32_VMX_BASIC,
1245 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1246 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1247 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1248 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1249 MSR_IA32_VMX_MISC,
1250 MSR_IA32_VMX_CR0_FIXED0,
1251 MSR_IA32_VMX_CR4_FIXED0,
1252 MSR_IA32_VMX_VMCS_ENUM,
1253 MSR_IA32_VMX_PROCBASED_CTLS2,
1254 MSR_IA32_VMX_EPT_VPID_CAP,
1255 MSR_IA32_VMX_VMFUNC,
1256
191c8137 1257 MSR_K7_HWCR,
2d5ba19b 1258 MSR_KVM_POLL_CONTROL,
043405e1
CO		 1259};
1260
7a5ee6ed 1261static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
62ef68bb
PB		 1262static unsigned num_emulated_msrs;
1263
801e459a
TL		 1264/*
1265 * List of msr numbers which are used to expose MSR-based features that
1266 * can be used by a hypervisor to validate requested CPU features.
1267 */
7a5ee6ed 1268static const u32 msr_based_features_all[] = {
1389309c
PB		 1269 MSR_IA32_VMX_BASIC,
1270 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1271 MSR_IA32_VMX_PINBASED_CTLS,
1272 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1273 MSR_IA32_VMX_PROCBASED_CTLS,
1274 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1275 MSR_IA32_VMX_EXIT_CTLS,
1276 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1277 MSR_IA32_VMX_ENTRY_CTLS,
1278 MSR_IA32_VMX_MISC,
1279 MSR_IA32_VMX_CR0_FIXED0,
1280 MSR_IA32_VMX_CR0_FIXED1,
1281 MSR_IA32_VMX_CR4_FIXED0,
1282 MSR_IA32_VMX_CR4_FIXED1,
1283 MSR_IA32_VMX_VMCS_ENUM,
1284 MSR_IA32_VMX_PROCBASED_CTLS2,
1285 MSR_IA32_VMX_EPT_VPID_CAP,
1286 MSR_IA32_VMX_VMFUNC,
1287
d1d93fa9 1288 MSR_F10H_DECFG,
518e7b94 1289 MSR_IA32_UCODE_REV,
cd283252 1290 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1291};
1292
7a5ee6ed 1293static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
801e459a
TL		 1294static unsigned int num_msr_based_features;
1295
4d22c17c 1296static u64 kvm_get_arch_capabilities(void)
5b76a3cf 1297{
4d22c17c 1298 u64 data = 0;
5b76a3cf 1299
4d22c17c
XL		 1300 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1301 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
5b76a3cf 1302
b8e8c830
PB		 1303 /*
1304 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1305 * the nested hypervisor runs with NX huge pages. If it is not,
1306 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1307 * L1 guests, so it need not worry about its own (L2) guests.
1308 */
1309 data |= ARCH_CAP_PSCHANGE_MC_NO;
1310
5b76a3cf
PB		 1311 /*
1312 * If we're doing cache flushes (either "always" or "cond")
1313 * we will do one whenever the guest does a vmlaunch/vmresume.
1314 * If an outer hypervisor is doing the cache flush for us
1315 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1316 * capability to the guest too, and if EPT is disabled we're not
1317 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1318 * require a nested hypervisor to do a flush of its own.
1319 */
1320 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1321 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1322
0c54914d
PB		 1323 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1324 data |= ARCH_CAP_RDCL_NO;
1325 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1326 data |= ARCH_CAP_SSB_NO;
1327 if (!boot_cpu_has_bug(X86_BUG_MDS))
1328 data |= ARCH_CAP_MDS_NO;
1329
e1d38b63 1330 /*
c11f83e0
PB		 1331 * On TAA affected systems:
1332 * - nothing to do if TSX is disabled on the host.
1333 * - we emulate TSX_CTRL if present on the host.
1334 * This lets the guest use VERW to clear CPU buffers.
e1d38b63 1335 */
cbbaa272 1336 if (!boot_cpu_has(X86_FEATURE_RTM))
c11f83e0 1337 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
cbbaa272
PB		 1338 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1339 data |= ARCH_CAP_TAA_NO;
e1d38b63 1340
5b76a3cf
PB		 1341 return data;
1342}
5b76a3cf 1343
66421c1e
WL		 1344static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1345{
1346 switch (msr->index) {
cd283252 1347 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1348 msr->data = kvm_get_arch_capabilities();
1349 break;
1350 case MSR_IA32_UCODE_REV:
cd283252 1351 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1352 break;
66421c1e
WL		 1353 default:
1354 if (kvm_x86_ops->get_msr_feature(msr))
1355 return 1;
1356 }
1357 return 0;
1358}
1359
801e459a
TL		 1360static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1361{
1362 struct kvm_msr_entry msr;
66421c1e 1363 int r;
801e459a
TL		 1364
1365 msr.index = index;
66421c1e
WL		 1366 r = kvm_get_msr_feature(&msr);
1367 if (r)
1368 return r;
801e459a
TL		 1369
1370 *data = msr.data;
1371
1372 return 0;
1373}
1374
11988499 1375static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1376{
1b4d56b8 1377 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
11988499 1378 return false;
1b2fd70c 1379
1b4d56b8 1380 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
11988499 1381 return false;
d8017474 1382
0a629563
SC		 1383 if (efer & (EFER_LME | EFER_LMA) &&
1384 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1385 return false;
1386
1387 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1388 return false;
d8017474 1389
384bb783 1390 return true;
11988499
SC		 1391
1392}
1393bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1394{
1395 if (efer & efer_reserved_bits)
1396 return false;
1397
1398 return __kvm_valid_efer(vcpu, efer);
384bb783
JK		 1399}
1400EXPORT_SYMBOL_GPL(kvm_valid_efer);
1401
11988499 1402static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
384bb783
JK		 1403{
1404 u64 old_efer = vcpu->arch.efer;
11988499 1405 u64 efer = msr_info->data;
384bb783 1406
11988499 1407 if (efer & efer_reserved_bits)
66f61c92 1408 return 1;
384bb783 1409
11988499
SC		 1410 if (!msr_info->host_initiated) {
1411 if (!__kvm_valid_efer(vcpu, efer))
1412 return 1;
1413
1414 if (is_paging(vcpu) &&
1415 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1416 return 1;
1417 }
384bb783 1418
15c4a640 1419 efer &= ~EFER_LMA;
f6801dff 1420 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1421
a3d204e2
SY		 1422 kvm_x86_ops->set_efer(vcpu, efer);
1423
aad82703
SY		 1424 /* Update reserved bits */
1425 if ((efer ^ old_efer) & EFER_NX)
1426 kvm_mmu_reset_context(vcpu);
1427
b69e8cae 1428 return 0;
15c4a640
CO		 1429}
1430
f2b4b7dd
JR		 1431void kvm_enable_efer_bits(u64 mask)
1432{
1433 efer_reserved_bits &= ~mask;
1434}
1435EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1436
15c4a640 1437/*
f20935d8
SC		 1438 * Write @data into the MSR specified by @index. Select MSR specific fault
1439 * checks are bypassed if @host_initiated is %true.
15c4a640
CO		 1440 * Returns 0 on success, non-0 otherwise.
1441 * Assumes vcpu_load() was already called.
1442 */
f20935d8
SC		 1443static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1444 bool host_initiated)
15c4a640 1445{
f20935d8
SC		 1446 struct msr_data msr;
1447
1448 switch (index) {
854e8bb1
NA		 1449 case MSR_FS_BASE:
1450 case MSR_GS_BASE:
1451 case MSR_KERNEL_GS_BASE:
1452 case MSR_CSTAR:
1453 case MSR_LSTAR:
f20935d8 1454 if (is_noncanonical_address(data, vcpu))
854e8bb1
NA		 1455 return 1;
1456 break;
1457 case MSR_IA32_SYSENTER_EIP:
1458 case MSR_IA32_SYSENTER_ESP:
1459 /*
1460 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1461 * non-canonical address is written on Intel but not on
1462 * AMD (which ignores the top 32-bits, because it does
1463 * not implement 64-bit SYSENTER).
1464 *
1465 * 64-bit code should hence be able to write a non-canonical
1466 * value on AMD. Making the address canonical ensures that
1467 * vmentry does not fail on Intel after writing a non-canonical
1468 * value, and that something deterministic happens if the guest
1469 * invokes 64-bit SYSENTER.
1470 */
f20935d8 1471 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1472 }
f20935d8
SC		 1473
1474 msr.data = data;
1475 msr.index = index;
1476 msr.host_initiated = host_initiated;
1477
1478 return kvm_x86_ops->set_msr(vcpu, &msr);
15c4a640
CO		 1479}
1480
313a3dc7 1481/*
f20935d8
SC		 1482 * Read the MSR specified by @index into @data. Select MSR specific fault
1483 * checks are bypassed if @host_initiated is %true.
1484 * Returns 0 on success, non-0 otherwise.
1485 * Assumes vcpu_load() was already called.
313a3dc7 1486 */
edef5c36
PB		 1487int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1488 bool host_initiated)
609e36d3
PB		 1489{
1490 struct msr_data msr;
f20935d8 1491 int ret;
609e36d3
PB		 1492
1493 msr.index = index;
f20935d8 1494 msr.host_initiated = host_initiated;
609e36d3 1495
f20935d8
SC		 1496 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1497 if (!ret)
1498 *data = msr.data;
1499 return ret;
609e36d3
PB		 1500}
1501
f20935d8 1502int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
313a3dc7 1503{
f20935d8
SC		 1504 return __kvm_get_msr(vcpu, index, data, false);
1505}
1506EXPORT_SYMBOL_GPL(kvm_get_msr);
8fe8ab46 1507
f20935d8
SC		 1508int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1509{
1510 return __kvm_set_msr(vcpu, index, data, false);
1511}
1512EXPORT_SYMBOL_GPL(kvm_set_msr);
1513
1edce0a9
SC		 1514int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1515{
1516 u32 ecx = kvm_rcx_read(vcpu);
1517 u64 data;
1518
1519 if (kvm_get_msr(vcpu, ecx, &data)) {
1520 trace_kvm_msr_read_ex(ecx);
1521 kvm_inject_gp(vcpu, 0);
1522 return 1;
1523 }
1524
1525 trace_kvm_msr_read(ecx, data);
1526
1527 kvm_rax_write(vcpu, data & -1u);
1528 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1529 return kvm_skip_emulated_instruction(vcpu);
1530}
1531EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1532
1533int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1534{
1535 u32 ecx = kvm_rcx_read(vcpu);
1536 u64 data = kvm_read_edx_eax(vcpu);
1537
1538 if (kvm_set_msr(vcpu, ecx, data)) {
1539 trace_kvm_msr_write_ex(ecx, data);
1540 kvm_inject_gp(vcpu, 0);
1541 return 1;
1542 }
1543
1544 trace_kvm_msr_write(ecx, data);
1545 return kvm_skip_emulated_instruction(vcpu);
1546}
1547EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1548
1e9e2622
WL		 1549/*
1550 * The fast path for frequent and performance sensitive wrmsr emulation,
1551 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1552 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1553 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1554 * other cases which must be called after interrupts are enabled on the host.
1555 */
1556static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1557{
1558 if (lapic_in_kernel(vcpu) && apic_x2apic_mode(vcpu->arch.apic) &&
1559 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1560 ((data & APIC_MODE_MASK) == APIC_DM_FIXED)) {
1561
1562 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1563 return kvm_lapic_reg_write(vcpu->arch.apic, APIC_ICR, (u32)data);
1564 }
1565
1566 return 1;
1567}
1568
1569enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1570{
1571 u32 msr = kvm_rcx_read(vcpu);
1572 u64 data = kvm_read_edx_eax(vcpu);
1573 int ret = 0;
1574
1575 switch (msr) {
1576 case APIC_BASE_MSR + (APIC_ICR >> 4):
1577 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1578 break;
1579 default:
1580 return EXIT_FASTPATH_NONE;
1581 }
1582
1583 if (!ret) {
1584 trace_kvm_msr_write(msr, data);
1585 return EXIT_FASTPATH_SKIP_EMUL_INS;
1586 }
1587
1588 return EXIT_FASTPATH_NONE;
1589}
1590EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1591
f20935d8
SC		 1592/*
1593 * Adapt set_msr() to msr_io()'s calling convention
1594 */
1595static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1596{
1597 return __kvm_get_msr(vcpu, index, data, true);
1598}
1599
1600static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1601{
1602 return __kvm_set_msr(vcpu, index, *data, true);
313a3dc7
CO		 1603}
1604
16e8d74d 1605#ifdef CONFIG_X86_64
53fafdbb
MT		 1606struct pvclock_clock {
1607 int vclock_mode;
1608 u64 cycle_last;
1609 u64 mask;
1610 u32 mult;
1611 u32 shift;
1612};
1613
16e8d74d
MT		 1614struct pvclock_gtod_data {
1615 seqcount_t seq;
1616
53fafdbb
MT		 1617 struct pvclock_clock clock; /* extract of a clocksource struct */
1618 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
16e8d74d 1619
53fafdbb 1620 u64 boot_ns_raw;
cbcf2dd3
TG		 1621 u64 boot_ns;
1622 u64 nsec_base;
55dd00a7 1623 u64 wall_time_sec;
53fafdbb 1624 u64 monotonic_raw_nsec;
16e8d74d
MT		 1625};
1626
1627static struct pvclock_gtod_data pvclock_gtod_data;
1628
1629static void update_pvclock_gtod(struct timekeeper *tk)
1630{
1631 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
53fafdbb 1632 u64 boot_ns, boot_ns_raw;
cbcf2dd3 1633
876e7881 1634 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
53fafdbb 1635 boot_ns_raw = ktime_to_ns(ktime_add(tk->tkr_raw.base, tk->offs_boot));
16e8d74d
MT		 1636
1637 write_seqcount_begin(&vdata->seq);
1638
1639 /* copy pvclock gtod data */
876e7881
PZ		 1640 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1641 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1642 vdata->clock.mask = tk->tkr_mono.mask;
1643 vdata->clock.mult = tk->tkr_mono.mult;
1644 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1645
53fafdbb
MT		 1646 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->archdata.vclock_mode;
1647 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1648 vdata->raw_clock.mask = tk->tkr_raw.mask;
1649 vdata->raw_clock.mult = tk->tkr_raw.mult;
1650 vdata->raw_clock.shift = tk->tkr_raw.shift;
1651
cbcf2dd3 1652 vdata->boot_ns = boot_ns;
876e7881 1653 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1654
55dd00a7
MT		 1655 vdata->wall_time_sec = tk->xtime_sec;
1656
53fafdbb
MT		 1657 vdata->boot_ns_raw = boot_ns_raw;
1658 vdata->monotonic_raw_nsec = tk->tkr_raw.xtime_nsec;
1659
16e8d74d
MT		 1660 write_seqcount_end(&vdata->seq);
1661}
1662#endif
1663
bab5bb39
NK		 1664void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1665{
bab5bb39 1666 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
4d151bf3 1667 kvm_vcpu_kick(vcpu);
bab5bb39 1668}
16e8d74d 1669
18068523
GOC		 1670static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1671{
9ed3c444
AK		 1672 int version;
1673 int r;
50d0a0f9 1674 struct pvclock_wall_clock wc;
87aeb54f 1675 struct timespec64 boot;
18068523
GOC		 1676
1677 if (!wall_clock)
1678 return;
1679
9ed3c444
AK		 1680 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1681 if (r)
1682 return;
1683
1684 if (version & 1)
1685 ++version; /* first time write, random junk */
1686
1687 ++version;
18068523 1688
1dab1345
NK		 1689 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1690 return;
18068523 1691
50d0a0f9
GH		 1692 /*
1693 * The guest calculates current wall clock time by adding
34c238a1 1694 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1695 * wall clock specified here. guest system time equals host
1696 * system time for us, thus we must fill in host boot time here.
1697 */
87aeb54f 1698 getboottime64(&boot);
50d0a0f9 1699
4b648665 1700 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1701 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1702 boot = timespec64_sub(boot, ts);
4b648665 1703 }
87aeb54f 1704 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1705 wc.nsec = boot.tv_nsec;
1706 wc.version = version;
18068523
GOC		 1707
1708 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1709
1710 version++;
1711 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1712}
1713
50d0a0f9
GH		 1714static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1715{
b51012de
PB		 1716 do_shl32_div32(dividend, divisor);
1717 return dividend;
50d0a0f9
GH		 1718}
1719
3ae13faa 1720static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1721 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1722{
5f4e3f88 1723 uint64_t scaled64;
50d0a0f9
GH		 1724 int32_t shift = 0;
1725 uint64_t tps64;
1726 uint32_t tps32;
1727
3ae13faa
PB		 1728 tps64 = base_hz;
1729 scaled64 = scaled_hz;
50933623 1730 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1731 tps64 >>= 1;
1732 shift--;
1733 }
1734
1735 tps32 = (uint32_t)tps64;
50933623
JK		 1736 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1737 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1738 scaled64 >>= 1;
1739 else
1740 tps32 <<= 1;
50d0a0f9
GH		 1741 shift++;
1742 }
1743
5f4e3f88
ZA		 1744 *pshift = shift;
1745 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9
GH		 1746}
1747
d828199e 1748#ifdef CONFIG_X86_64
16e8d74d 1749static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1750#endif
16e8d74d 1751
c8076604 1752static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1753static unsigned long max_tsc_khz;
c8076604 1754
cc578287 1755static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1756{
cc578287
ZA		 1757 u64 v = (u64)khz * (1000000 + ppm);
1758 do_div(v, 1000000);
1759 return v;
1e993611
JR		 1760}
1761
381d585c
HZ		 1762static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1763{
1764 u64 ratio;
1765
1766 /* Guest TSC same frequency as host TSC? */
1767 if (!scale) {
1768 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1769 return 0;
1770 }
1771
1772 /* TSC scaling supported? */
1773 if (!kvm_has_tsc_control) {
1774 if (user_tsc_khz > tsc_khz) {
1775 vcpu->arch.tsc_catchup = 1;
1776 vcpu->arch.tsc_always_catchup = 1;
1777 return 0;
1778 } else {
3f16a5c3 1779 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
381d585c
HZ		 1780 return -1;
1781 }
1782 }
1783
1784 /* TSC scaling required - calculate ratio */
1785 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1786 user_tsc_khz, tsc_khz);
1787
1788 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
3f16a5c3
PB		 1789 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1790 user_tsc_khz);
381d585c
HZ		 1791 return -1;
1792 }
1793
1794 vcpu->arch.tsc_scaling_ratio = ratio;
1795 return 0;
1796}
1797
4941b8cb 1798static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1799{
cc578287
ZA		 1800 u32 thresh_lo, thresh_hi;
1801 int use_scaling = 0;
217fc9cf 1802
03ba32ca 1803 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1804 if (user_tsc_khz == 0) {
ad721883
HZ		 1805 /* set tsc_scaling_ratio to a safe value */
1806 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1807 return -1;
ad721883 1808 }
03ba32ca 1809
c285545f 1810 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1811 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1812 &vcpu->arch.virtual_tsc_shift,
1813 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1814 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1815
1816 /*
1817 * Compute the variation in TSC rate which is acceptable
1818 * within the range of tolerance and decide if the
1819 * rate being applied is within that bounds of the hardware
1820 * rate. If so, no scaling or compensation need be done.
1821 */
1822 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1823 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1824 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1825 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1826 use_scaling = 1;
1827 }
4941b8cb 1828 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1829}
1830
1831static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1832{
e26101b1 1833 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1834 vcpu->arch.virtual_tsc_mult,
1835 vcpu->arch.virtual_tsc_shift);
e26101b1 1836 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1837 return tsc;
1838}
1839
b0c39dc6
VK		 1840static inline int gtod_is_based_on_tsc(int mode)
1841{
1842 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1843}
1844
69b0049a 1845static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1846{
1847#ifdef CONFIG_X86_64
1848 bool vcpus_matched;
b48aa97e
MT		 1849 struct kvm_arch *ka = &vcpu->kvm->arch;
1850 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1851
1852 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1853 atomic_read(&vcpu->kvm->online_vcpus));
1854
7f187922
MT		 1855 /*
1856 * Once the masterclock is enabled, always perform request in
1857 * order to update it.
1858 *
1859 * In order to enable masterclock, the host clocksource must be TSC
1860 * and the vcpus need to have matched TSCs. When that happens,
1861 * perform request to enable masterclock.
1862 */
1863 if (ka->use_master_clock ||
b0c39dc6 1864 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1865 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1866
1867 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1868 atomic_read(&vcpu->kvm->online_vcpus),
1869 ka->use_master_clock, gtod->clock.vclock_mode);
1870#endif
1871}
1872
ba904635
WA		 1873static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1874{
e79f245d 1875 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1876 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1877}
1878
35181e86
HZ		 1879/*
1880 * Multiply tsc by a fixed point number represented by ratio.
1881 *
1882 * The most significant 64-N bits (mult) of ratio represent the
1883 * integral part of the fixed point number; the remaining N bits
1884 * (frac) represent the fractional part, ie. ratio represents a fixed
1885 * point number (mult + frac * 2^(-N)).
1886 *
1887 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1888 */
1889static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1890{
1891 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1892}
1893
1894u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1895{
1896 u64 _tsc = tsc;
1897 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1898
1899 if (ratio != kvm_default_tsc_scaling_ratio)
1900 _tsc = __scale_tsc(ratio, tsc);
1901
1902 return _tsc;
1903}
1904EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1905
07c1419a
HZ		 1906static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1907{
1908 u64 tsc;
1909
1910 tsc = kvm_scale_tsc(vcpu, rdtsc());
1911
1912 return target_tsc - tsc;
1913}
1914
4ba76538
HZ		 1915u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1916{
e79f245d
KA		 1917 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1918
1919 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1920}
1921EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1922
a545ab6a
LC		 1923static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1924{
326e7425 1925 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1926}
1927
b0c39dc6
VK		 1928static inline bool kvm_check_tsc_unstable(void)
1929{
1930#ifdef CONFIG_X86_64
1931 /*
1932 * TSC is marked unstable when we're running on Hyper-V,
1933 * 'TSC page' clocksource is good.
1934 */
1935 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1936 return false;
1937#endif
1938 return check_tsc_unstable();
1939}
1940
8fe8ab46 1941void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1942{
1943 struct kvm *kvm = vcpu->kvm;
f38e098f 1944 u64 offset, ns, elapsed;
99e3e30a 1945 unsigned long flags;
b48aa97e 1946 bool matched;
0d3da0d2 1947 bool already_matched;
8fe8ab46 1948 u64 data = msr->data;
c5e8ec8e 1949 bool synchronizing = false;
99e3e30a 1950
038f8c11 1951 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1952 offset = kvm_compute_tsc_offset(vcpu, data);
9285ec4c 1953 ns = ktime_get_boottime_ns();
f38e098f 1954 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1955
03ba32ca 1956 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1957 if (data == 0 && msr->host_initiated) {
1958 /*
1959 * detection of vcpu initialization -- need to sync
1960 * with other vCPUs. This particularly helps to keep
1961 * kvm_clock stable after CPU hotplug
1962 */
1963 synchronizing = true;
1964 } else {
1965 u64 tsc_exp = kvm->arch.last_tsc_write +
1966 nsec_to_cycles(vcpu, elapsed);
1967 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1968 /*
1969 * Special case: TSC write with a small delta (1 second)
1970 * of virtual cycle time against real time is
1971 * interpreted as an attempt to synchronize the CPU.
1972 */
1973 synchronizing = data < tsc_exp + tsc_hz &&
1974 data + tsc_hz > tsc_exp;
1975 }
c5e8ec8e 1976 }
f38e098f
ZA		 1977
1978 /*
5d3cb0f6
ZA		 1979 * For a reliable TSC, we can match TSC offsets, and for an unstable
1980 * TSC, we add elapsed time in this computation. We could let the
1981 * compensation code attempt to catch up if we fall behind, but
1982 * it's better to try to match offsets from the beginning.
1983 */
c5e8ec8e 1984 if (synchronizing &&
5d3cb0f6 1985 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1986 if (!kvm_check_tsc_unstable()) {
e26101b1 1987 offset = kvm->arch.cur_tsc_offset;
f38e098f 1988 } else {
857e4099 1989 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1990 data += delta;
07c1419a 1991 offset = kvm_compute_tsc_offset(vcpu, data);
f38e098f 1992 }
b48aa97e 1993 matched = true;
0d3da0d2 1994 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1995 } else {
1996 /*
1997 * We split periods of matched TSC writes into generations.
1998 * For each generation, we track the original measured
1999 * nanosecond time, offset, and write, so if TSCs are in
2000 * sync, we can match exact offset, and if not, we can match
4a969980 2001 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 2002 *
2003 * These values are tracked in kvm->arch.cur_xxx variables.
2004 */
2005 kvm->arch.cur_tsc_generation++;
2006 kvm->arch.cur_tsc_nsec = ns;
2007 kvm->arch.cur_tsc_write = data;
2008 kvm->arch.cur_tsc_offset = offset;
b48aa97e 2009 matched = false;
f38e098f 2010 }
e26101b1
ZA		 2011
2012 /*
2013 * We also track th most recent recorded KHZ, write and time to
2014 * allow the matching interval to be extended at each write.
2015 */
f38e098f
ZA		 2016 kvm->arch.last_tsc_nsec = ns;
2017 kvm->arch.last_tsc_write = data;
5d3cb0f6 2018 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 2019
b183aa58 2020 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 2021
2022 /* Keep track of which generation this VCPU has synchronized to */
2023 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2024 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2025 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2026
d6321d49 2027 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 2028 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 2029
a545ab6a 2030 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 2031 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 2032
2033 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 2034 if (!matched) {
b48aa97e 2035 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 2036 } else if (!already_matched) {
2037 kvm->arch.nr_vcpus_matched_tsc++;
2038 }
b48aa97e
MT		 2039
2040 kvm_track_tsc_matching(vcpu);
2041 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 2042}
e26101b1 2043
99e3e30a
ZA		 2044EXPORT_SYMBOL_GPL(kvm_write_tsc);
2045
58ea6767
HZ		 2046static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2047 s64 adjustment)
2048{
326e7425
LS		 2049 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
2050 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 2051}
2052
2053static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2054{
2055 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2056 WARN_ON(adjustment < 0);
2057 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 2058 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 2059}
2060
d828199e
MT		 2061#ifdef CONFIG_X86_64
2062
a5a1d1c2 2063static u64 read_tsc(void)
d828199e 2064{
a5a1d1c2 2065 u64 ret = (u64)rdtsc_ordered();
03b9730b 2066 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 2067
2068 if (likely(ret >= last))
2069 return ret;
2070
2071 /*
2072 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 2073 * predictable (it's just a function of time and the likely is
d828199e
MT		 2074 * very likely) and there's a data dependence, so force GCC
2075 * to generate a branch instead. I don't barrier() because
2076 * we don't actually need a barrier, and if this function
2077 * ever gets inlined it will generate worse code.
2078 */
2079 asm volatile ("");
2080 return last;
2081}
2082
53fafdbb
MT		 2083static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2084 int *mode)
d828199e
MT		 2085{
2086 long v;
b0c39dc6
VK		 2087 u64 tsc_pg_val;
2088
53fafdbb 2089 switch (clock->vclock_mode) {
b0c39dc6
VK		 2090 case VCLOCK_HVCLOCK:
2091 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2092 tsc_timestamp);
2093 if (tsc_pg_val != U64_MAX) {
2094 /* TSC page valid */
2095 *mode = VCLOCK_HVCLOCK;
53fafdbb
MT		 2096 v = (tsc_pg_val - clock->cycle_last) &
2097 clock->mask;
b0c39dc6
VK		 2098 } else {
2099 /* TSC page invalid */
2100 *mode = VCLOCK_NONE;
2101 }
2102 break;
2103 case VCLOCK_TSC:
2104 *mode = VCLOCK_TSC;
2105 *tsc_timestamp = read_tsc();
53fafdbb
MT		 2106 v = (*tsc_timestamp - clock->cycle_last) &
2107 clock->mask;
b0c39dc6
VK		 2108 break;
2109 default:
2110 *mode = VCLOCK_NONE;
2111 }
d828199e 2112
b0c39dc6
VK		 2113 if (*mode == VCLOCK_NONE)
2114 *tsc_timestamp = v = 0;
d828199e 2115
53fafdbb 2116 return v * clock->mult;
d828199e
MT		 2117}
2118
53fafdbb 2119static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
d828199e 2120{
cbcf2dd3 2121 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 2122 unsigned long seq;
d828199e 2123 int mode;
cbcf2dd3 2124 u64 ns;
d828199e 2125
d828199e
MT		 2126 do {
2127 seq = read_seqcount_begin(&gtod->seq);
53fafdbb
MT		 2128 ns = gtod->monotonic_raw_nsec;
2129 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
d828199e 2130 ns >>= gtod->clock.shift;
53fafdbb 2131 ns += gtod->boot_ns_raw;
d828199e 2132 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 2133 *t = ns;
d828199e
MT		 2134
2135 return mode;
2136}
2137
899a31f5 2138static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 2139{
2140 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2141 unsigned long seq;
2142 int mode;
2143 u64 ns;
2144
2145 do {
2146 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 2147 ts->tv_sec = gtod->wall_time_sec;
2148 ns = gtod->nsec_base;
53fafdbb 2149 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
55dd00a7
MT		 2150 ns >>= gtod->clock.shift;
2151 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2152
2153 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2154 ts->tv_nsec = ns;
2155
2156 return mode;
2157}
2158
b0c39dc6
VK		 2159/* returns true if host is using TSC based clocksource */
2160static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 2161{
d828199e 2162 /* checked again under seqlock below */
b0c39dc6 2163 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 2164 return false;
2165
53fafdbb 2166 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
b0c39dc6 2167 tsc_timestamp));
d828199e 2168}
55dd00a7 2169
b0c39dc6 2170/* returns true if host is using TSC based clocksource */
899a31f5 2171static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 2172 u64 *tsc_timestamp)
55dd00a7
MT		 2173{
2174 /* checked again under seqlock below */
b0c39dc6 2175 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 2176 return false;
2177
b0c39dc6 2178 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 2179}
d828199e
MT		 2180#endif
2181
2182/*
2183 *
b48aa97e
MT		 2184 * Assuming a stable TSC across physical CPUS, and a stable TSC
2185 * across virtual CPUs, the following condition is possible.
2186 * Each numbered line represents an event visible to both
d828199e
MT		 2187 * CPUs at the next numbered event.
2188 *
2189 * "timespecX" represents host monotonic time. "tscX" represents
2190 * RDTSC value.
2191 *
2192 * VCPU0 on CPU0 | VCPU1 on CPU1
2193 *
2194 * 1. read timespec0,tsc0
2195 * 2. | timespec1 = timespec0 + N
2196 * | tsc1 = tsc0 + M
2197 * 3. transition to guest | transition to guest
2198 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2199 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2200 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2201 *
2202 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2203 *
2204 * - ret0 < ret1
2205 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2206 * ...
2207 * - 0 < N - M => M < N
2208 *
2209 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2210 * always the case (the difference between two distinct xtime instances
2211 * might be smaller then the difference between corresponding TSC reads,
2212 * when updating guest vcpus pvclock areas).
2213 *
2214 * To avoid that problem, do not allow visibility of distinct
2215 * system_timestamp/tsc_timestamp values simultaneously: use a master
2216 * copy of host monotonic time values. Update that master copy
2217 * in lockstep.
2218 *
b48aa97e 2219 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 2220 *
2221 */
2222
2223static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2224{
2225#ifdef CONFIG_X86_64
2226 struct kvm_arch *ka = &kvm->arch;
2227 int vclock_mode;
b48aa97e
MT		 2228 bool host_tsc_clocksource, vcpus_matched;
2229
2230 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2231 atomic_read(&kvm->online_vcpus));
d828199e
MT		 2232
2233 /*
2234 * If the host uses TSC clock, then passthrough TSC as stable
2235 * to the guest.
2236 */
b48aa97e 2237 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 2238 &ka->master_kernel_ns,
2239 &ka->master_cycle_now);
2240
16a96021 2241 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2242 && !ka->backwards_tsc_observed
54750f2c 2243 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2244
d828199e
MT		 2245 if (ka->use_master_clock)
2246 atomic_set(&kvm_guest_has_master_clock, 1);
2247
2248 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2249 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2250 vcpus_matched);
d828199e
MT		 2251#endif
2252}
2253
2860c4b1
PB		 2254void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2255{
2256 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2257}
2258
2e762ff7
MT		 2259static void kvm_gen_update_masterclock(struct kvm *kvm)
2260{
2261#ifdef CONFIG_X86_64
2262 int i;
2263 struct kvm_vcpu *vcpu;
2264 struct kvm_arch *ka = &kvm->arch;
2265
2266 spin_lock(&ka->pvclock_gtod_sync_lock);
2267 kvm_make_mclock_inprogress_request(kvm);
2268 /* no guest entries from this point */
2269 pvclock_update_vm_gtod_copy(kvm);
2270
2271 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2272 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2273
2274 /* guest entries allowed */
2275 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2276 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2277
2278 spin_unlock(&ka->pvclock_gtod_sync_lock);
2279#endif
2280}
2281
e891a32e 2282u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2283{
108b249c 2284 struct kvm_arch *ka = &kvm->arch;
8b953440 2285 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2286 u64 ret;
108b249c 2287
8b953440
PB		 2288 spin_lock(&ka->pvclock_gtod_sync_lock);
2289 if (!ka->use_master_clock) {
2290 spin_unlock(&ka->pvclock_gtod_sync_lock);
9285ec4c 2291 return ktime_get_boottime_ns() + ka->kvmclock_offset;
108b249c
PB		 2292 }
2293
8b953440
PB		 2294 hv_clock.tsc_timestamp = ka->master_cycle_now;
2295 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2296 spin_unlock(&ka->pvclock_gtod_sync_lock);
2297
e2c2206a
WL		 2298 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2299 get_cpu();
2300
e70b57a6
WL		 2301 if (__this_cpu_read(cpu_tsc_khz)) {
2302 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2303 &hv_clock.tsc_shift,
2304 &hv_clock.tsc_to_system_mul);
2305 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2306 } else
9285ec4c 2307 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2308
2309 put_cpu();
2310
2311 return ret;
108b249c
PB		 2312}
2313
0d6dd2ff
PB		 2314static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2315{
2316 struct kvm_vcpu_arch *vcpu = &v->arch;
2317 struct pvclock_vcpu_time_info guest_hv_clock;
2318
4e335d9e 2319 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2320 &guest_hv_clock, sizeof(guest_hv_clock))))
2321 return;
2322
2323 /* This VCPU is paused, but it's legal for a guest to read another
2324 * VCPU's kvmclock, so we really have to follow the specification where
2325 * it says that version is odd if data is being modified, and even after
2326 * it is consistent.
2327 *
2328 * Version field updates must be kept separate. This is because
2329 * kvm_write_guest_cached might use a "rep movs" instruction, and
2330 * writes within a string instruction are weakly ordered. So there
2331 * are three writes overall.
2332 *
2333 * As a small optimization, only write the version field in the first
2334 * and third write. The vcpu->pv_time cache is still valid, because the
2335 * version field is the first in the struct.
2336 */
2337 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2338
51c4b8bb
LA		 2339 if (guest_hv_clock.version & 1)
2340 ++guest_hv_clock.version; /* first time write, random junk */
2341
0d6dd2ff 2342 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2343 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2344 &vcpu->hv_clock,
2345 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2346
2347 smp_wmb();
2348
2349 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2350 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2351
2352 if (vcpu->pvclock_set_guest_stopped_request) {
2353 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2354 vcpu->pvclock_set_guest_stopped_request = false;
2355 }
2356
2357 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2358
4e335d9e
PB		 2359 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2360 &vcpu->hv_clock,
2361 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2362
2363 smp_wmb();
2364
2365 vcpu->hv_clock.version++;
4e335d9e
PB		 2366 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2367 &vcpu->hv_clock,
2368 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2369}
2370
34c238a1 2371static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2372{
78db6a50 2373 unsigned long flags, tgt_tsc_khz;
18068523 2374 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2375 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2376 s64 kernel_ns;
d828199e 2377 u64 tsc_timestamp, host_tsc;
51d59c6b 2378 u8 pvclock_flags;
d828199e
MT		 2379 bool use_master_clock;
2380
2381 kernel_ns = 0;
2382 host_tsc = 0;
18068523 2383
d828199e
MT		 2384 /*
2385 * If the host uses TSC clock, then passthrough TSC as stable
2386 * to the guest.
2387 */
2388 spin_lock(&ka->pvclock_gtod_sync_lock);
2389 use_master_clock = ka->use_master_clock;
2390 if (use_master_clock) {
2391 host_tsc = ka->master_cycle_now;
2392 kernel_ns = ka->master_kernel_ns;
2393 }
2394 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2395
2396 /* Keep irq disabled to prevent changes to the clock */
2397 local_irq_save(flags);
78db6a50
PB		 2398 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2399 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2400 local_irq_restore(flags);
2401 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2402 return 1;
2403 }
d828199e 2404 if (!use_master_clock) {
4ea1636b 2405 host_tsc = rdtsc();
9285ec4c 2406 kernel_ns = ktime_get_boottime_ns();
d828199e
MT		 2407 }
2408
4ba76538 2409 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2410
c285545f
ZA		 2411 /*
2412 * We may have to catch up the TSC to match elapsed wall clock
2413 * time for two reasons, even if kvmclock is used.
2414 * 1) CPU could have been running below the maximum TSC rate
2415 * 2) Broken TSC compensation resets the base at each VCPU
2416 * entry to avoid unknown leaps of TSC even when running
2417 * again on the same CPU. This may cause apparent elapsed
2418 * time to disappear, and the guest to stand still or run
2419 * very slowly.
2420 */
2421 if (vcpu->tsc_catchup) {
2422 u64 tsc = compute_guest_tsc(v, kernel_ns);
2423 if (tsc > tsc_timestamp) {
f1e2b260 2424 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2425 tsc_timestamp = tsc;
2426 }
50d0a0f9
GH		 2427 }
2428
18068523
GOC		 2429 local_irq_restore(flags);
2430
0d6dd2ff 2431 /* With all the info we got, fill in the values */
18068523 2432
78db6a50
PB		 2433 if (kvm_has_tsc_control)
2434 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2435
2436 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2437 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2438 &vcpu->hv_clock.tsc_shift,
2439 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2440 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2441 }
2442
1d5f066e 2443 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2444 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2445 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2446
d828199e 2447 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2448 pvclock_flags = 0;
d828199e
MT		 2449 if (use_master_clock)
2450 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2451
78c0337a
MT		 2452 vcpu->hv_clock.flags = pvclock_flags;
2453
095cf55d
PB		 2454 if (vcpu->pv_time_enabled)
2455 kvm_setup_pvclock_page(v);
2456 if (v == kvm_get_vcpu(v->kvm, 0))
2457 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2458 return 0;
c8076604
GH		 2459}
2460
0061d53d
MT		 2461/*
2462 * kvmclock updates which are isolated to a given vcpu, such as
2463 * vcpu->cpu migration, should not allow system_timestamp from
2464 * the rest of the vcpus to remain static. Otherwise ntp frequency
2465 * correction applies to one vcpu's system_timestamp but not
2466 * the others.
2467 *
2468 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2469 * We need to rate-limit these requests though, as they can
2470 * considerably slow guests that have a large number of vcpus.
2471 * The time for a remote vcpu to update its kvmclock is bound
2472 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2473 */
2474
7e44e449
AJ		 2475#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2476
2477static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2478{
2479 int i;
7e44e449
AJ		 2480 struct delayed_work *dwork = to_delayed_work(work);
2481 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2482 kvmclock_update_work);
2483 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2484 struct kvm_vcpu *vcpu;
2485
2486 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2487 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2488 kvm_vcpu_kick(vcpu);
2489 }
2490}
2491
7e44e449
AJ		 2492static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2493{
2494 struct kvm *kvm = v->kvm;
2495
105b21bb 2496 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2497 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2498 KVMCLOCK_UPDATE_DELAY);
2499}
2500
332967a3
AJ		 2501#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2502
2503static void kvmclock_sync_fn(struct work_struct *work)
2504{
2505 struct delayed_work *dwork = to_delayed_work(work);
2506 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2507 kvmclock_sync_work);
2508 struct kvm *kvm = container_of(ka, struct kvm, arch);
2509
630994b3
MT		 2510 if (!kvmclock_periodic_sync)
2511 return;
2512
332967a3
AJ		 2513 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2514 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2515 KVMCLOCK_SYNC_PERIOD);
2516}
2517
191c8137
BP		 2518/*
2519 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2520 */
2521static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2522{
2523 /* McStatusWrEn enabled? */
2524 if (guest_cpuid_is_amd(vcpu))
2525 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2526
2527 return false;
2528}
2529
9ffd986c 2530static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2531{
890ca9ae
HY		 2532 u64 mcg_cap = vcpu->arch.mcg_cap;
2533 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2534 u32 msr = msr_info->index;
2535 u64 data = msr_info->data;
890ca9ae 2536
15c4a640 2537 switch (msr) {
15c4a640 2538 case MSR_IA32_MCG_STATUS:
890ca9ae 2539 vcpu->arch.mcg_status = data;
15c4a640 2540 break;
c7ac679c 2541 case MSR_IA32_MCG_CTL:
44883f01
PB		 2542 if (!(mcg_cap & MCG_CTL_P) &&
2543 (data || !msr_info->host_initiated))
890ca9ae
HY		 2544 return 1;
2545 if (data != 0 && data != ~(u64)0)
44883f01 2546 return 1;
890ca9ae
HY		 2547 vcpu->arch.mcg_ctl = data;
2548 break;
2549 default:
2550 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2551 msr < MSR_IA32_MCx_CTL(bank_num)) {
6ec4c5ee
MP		 2552 u32 offset = array_index_nospec(
2553 msr - MSR_IA32_MC0_CTL,
2554 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2555
114be429
AP		 2556 /* only 0 or all 1s can be written to IA32_MCi_CTL
2557 * some Linux kernels though clear bit 10 in bank 4 to
2558 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2559 * this to avoid an uncatched #GP in the guest
2560 */
890ca9ae 2561 if ((offset & 0x3) == 0 &&
114be429 2562 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2563 return -1;
191c8137
BP		 2564
2565 /* MCi_STATUS */
9ffd986c 2566 if (!msr_info->host_initiated &&
191c8137
BP		 2567 (offset & 0x3) == 1 && data != 0) {
2568 if (!can_set_mci_status(vcpu))
2569 return -1;
2570 }
2571
890ca9ae
HY		 2572 vcpu->arch.mce_banks[offset] = data;
2573 break;
2574 }
2575 return 1;
2576 }
2577 return 0;
2578}
2579
ffde22ac
ES		 2580static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2581{
2582 struct kvm *kvm = vcpu->kvm;
2583 int lm = is_long_mode(vcpu);
2584 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2585 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2586 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2587 : kvm->arch.xen_hvm_config.blob_size_32;
2588 u32 page_num = data & ~PAGE_MASK;
2589 u64 page_addr = data & PAGE_MASK;
2590 u8 *page;
2591 int r;
2592
2593 r = -E2BIG;
2594 if (page_num >= blob_size)
2595 goto out;
2596 r = -ENOMEM;
ff5c2c03
SL		 2597 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2598 if (IS_ERR(page)) {
2599 r = PTR_ERR(page);
ffde22ac 2600 goto out;
ff5c2c03 2601 }
54bf36aa 2602 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2603 goto out_free;
2604 r = 0;
2605out_free:
2606 kfree(page);
2607out:
2608 return r;
2609}
2610
344d9588
GN		 2611static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2612{
2613 gpa_t gpa = data & ~0x3f;
2614
52a5c155
WL		 2615 /* Bits 3:5 are reserved, Should be zero */
2616 if (data & 0x38)
344d9588
GN		 2617 return 1;
2618
2619 vcpu->arch.apf.msr_val = data;
2620
2621 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2622 kvm_clear_async_pf_completion_queue(vcpu);
2623 kvm_async_pf_hash_reset(vcpu);
2624 return 0;
2625 }
2626
4e335d9e 2627 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2628 sizeof(u32)))
344d9588
GN		 2629 return 1;
2630
6adba527 2631 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2632 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2633 kvm_async_pf_wakeup_all(vcpu);
2634 return 0;
2635}
2636
12f9a48f
GC		 2637static void kvmclock_reset(struct kvm_vcpu *vcpu)
2638{
0b79459b 2639 vcpu->arch.pv_time_enabled = false;
49dedf0d 2640 vcpu->arch.time = 0;
12f9a48f
GC		 2641}
2642
f38a7b75
WL		 2643static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2644{
2645 ++vcpu->stat.tlb_flush;
2646 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2647}
2648
c9aaa895
GC		 2649static void record_steal_time(struct kvm_vcpu *vcpu)
2650{
2651 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2652 return;
2653
4e335d9e 2654 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2655 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2656 return;
2657
f38a7b75
WL		 2658 /*
2659 * Doing a TLB flush here, on the guest's behalf, can avoid
2660 * expensive IPIs.
2661 */
b382f44e
WL		 2662 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2663 vcpu->arch.st.steal.preempted & KVM_VCPU_FLUSH_TLB);
f38a7b75
WL		 2664 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2665 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2666
35f3fae1
WL		 2667 if (vcpu->arch.st.steal.version & 1)
2668 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2669
2670 vcpu->arch.st.steal.version += 1;
2671
4e335d9e 2672 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2673 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2674
2675 smp_wmb();
2676
c54cdf14
LC		 2677 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2678 vcpu->arch.st.last_steal;
2679 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2680
4e335d9e 2681 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2682 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2683
2684 smp_wmb();
2685
2686 vcpu->arch.st.steal.version += 1;
c9aaa895 2687
4e335d9e 2688 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2689 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2690}
2691
8fe8ab46 2692int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2693{
5753785f 2694 bool pr = false;
8fe8ab46
WA		 2695 u32 msr = msr_info->index;
2696 u64 data = msr_info->data;
5753785f 2697
15c4a640 2698 switch (msr) {
2e32b719 2699 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2700 case MSR_IA32_UCODE_WRITE:
2701 case MSR_VM_HSAVE_PA:
2702 case MSR_AMD64_PATCH_LOADER:
2703 case MSR_AMD64_BU_CFG2:
405a353a 2704 case MSR_AMD64_DC_CFG:
0e1b869f 2705 case MSR_F15H_EX_CFG:
2e32b719
BP		 2706 break;
2707
518e7b94
WL		 2708 case MSR_IA32_UCODE_REV:
2709 if (msr_info->host_initiated)
2710 vcpu->arch.microcode_version = data;
2711 break;
0cf9135b
SC		 2712 case MSR_IA32_ARCH_CAPABILITIES:
2713 if (!msr_info->host_initiated)
2714 return 1;
2715 vcpu->arch.arch_capabilities = data;
2716 break;
15c4a640 2717 case MSR_EFER:
11988499 2718 return set_efer(vcpu, msr_info);
8f1589d9
AP		 2719 case MSR_K7_HWCR:
2720 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2721 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2722 data &= ~(u64)0x8; /* ignore TLB cache disable */
191c8137
BP		 2723
2724 /* Handle McStatusWrEn */
2725 if (data == BIT_ULL(18)) {
2726 vcpu->arch.msr_hwcr = data;
2727 } else if (data != 0) {
a737f256
CD		 2728 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2729 data);
8f1589d9
AP		 2730 return 1;
2731 }
15c4a640 2732 break;
f7c6d140
AP		 2733 case MSR_FAM10H_MMIO_CONF_BASE:
2734 if (data != 0) {
a737f256
CD		 2735 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2736 "0x%llx\n", data);
f7c6d140
AP		 2737 return 1;
2738 }
15c4a640 2739 break;
b5e2fec0
AG		 2740 case MSR_IA32_DEBUGCTLMSR:
2741 if (!data) {
2742 /* We support the non-activated case already */
2743 break;
2744 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2745 /* Values other than LBR and BTF are vendor-specific,
2746 thus reserved and should throw a #GP */
2747 return 1;
2748 }
a737f256
CD		 2749 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2750 __func__, data);
b5e2fec0 2751 break;
9ba075a6 2752 case 0x200 ... 0x2ff:
ff53604b 2753 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2754 case MSR_IA32_APICBASE:
58cb628d 2755 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2756 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2757 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2758 case MSR_IA32_TSCDEADLINE:
2759 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2760 break;
ba904635 2761 case MSR_IA32_TSC_ADJUST:
d6321d49 2762 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2763 if (!msr_info->host_initiated) {
d913b904 2764 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2765 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2766 }
2767 vcpu->arch.ia32_tsc_adjust_msr = data;
2768 }
2769 break;
15c4a640 2770 case MSR_IA32_MISC_ENABLE:
511a8556
WL		 2771 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2772 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2773 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2774 return 1;
2775 vcpu->arch.ia32_misc_enable_msr = data;
2776 kvm_update_cpuid(vcpu);
2777 } else {
2778 vcpu->arch.ia32_misc_enable_msr = data;
2779 }
15c4a640 2780 break;
64d60670
PB		 2781 case MSR_IA32_SMBASE:
2782 if (!msr_info->host_initiated)
2783 return 1;
2784 vcpu->arch.smbase = data;
2785 break;
73f624f4
PB		 2786 case MSR_IA32_POWER_CTL:
2787 vcpu->arch.msr_ia32_power_ctl = data;
2788 break;
dd259935
PB		 2789 case MSR_IA32_TSC:
2790 kvm_write_tsc(vcpu, msr_info);
2791 break;
864e2ab2
AL		 2792 case MSR_IA32_XSS:
2793 if (!msr_info->host_initiated &&
2794 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2795 return 1;
2796 /*
2797 * We do support PT if kvm_x86_ops->pt_supported(), but we do
2798 * not support IA32_XSS[bit 8]. Guests will have to use
2799 * RDMSR/WRMSR rather than XSAVES/XRSTORS to save/restore PT
2800 * MSRs.
2801 */
2802 if (data != 0)
2803 return 1;
2804 vcpu->arch.ia32_xss = data;
2805 break;
52797bf9
LA		 2806 case MSR_SMI_COUNT:
2807 if (!msr_info->host_initiated)
2808 return 1;
2809 vcpu->arch.smi_count = data;
2810 break;
11c6bffa 2811 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2812 case MSR_KVM_WALL_CLOCK:
2813 vcpu->kvm->arch.wall_clock = data;
2814 kvm_write_wall_clock(vcpu->kvm, data);
2815 break;
11c6bffa 2816 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2817 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2818 struct kvm_arch *ka = &vcpu->kvm->arch;
2819
54750f2c
MT		 2820 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2821 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2822
2823 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2824 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2825
2826 ka->boot_vcpu_runs_old_kvmclock = tmp;
2827 }
2828
18068523 2829 vcpu->arch.time = data;
0061d53d 2830 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2831
2832 /* we verify if the enable bit is set... */
49dedf0d 2833 vcpu->arch.pv_time_enabled = false;
18068523
GOC		 2834 if (!(data & 1))
2835 break;
2836
49dedf0d 2837 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2838 &vcpu->arch.pv_time, data & ~1ULL,
2839 sizeof(struct pvclock_vcpu_time_info)))
0b79459b 2840 vcpu->arch.pv_time_enabled = true;
32cad84f 2841
18068523
GOC		 2842 break;
2843 }
344d9588
GN		 2844 case MSR_KVM_ASYNC_PF_EN:
2845 if (kvm_pv_enable_async_pf(vcpu, data))
2846 return 1;
2847 break;
c9aaa895
GC		 2848 case MSR_KVM_STEAL_TIME:
2849
2850 if (unlikely(!sched_info_on()))
2851 return 1;
2852
2853 if (data & KVM_STEAL_RESERVED_MASK)
2854 return 1;
2855
4e335d9e 2856 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2857 data & KVM_STEAL_VALID_BITS,
2858 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2859 return 1;
2860
2861 vcpu->arch.st.msr_val = data;
2862
2863 if (!(data & KVM_MSR_ENABLED))
2864 break;
2865
c9aaa895
GC		 2866 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2867
2868 break;
ae7a2a3f 2869 case MSR_KVM_PV_EOI_EN:
72bbf935 2870 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2871 return 1;
2872 break;
c9aaa895 2873
2d5ba19b
MT		 2874 case MSR_KVM_POLL_CONTROL:
2875 /* only enable bit supported */
2876 if (data & (-1ULL << 1))
2877 return 1;
2878
2879 vcpu->arch.msr_kvm_poll_control = data;
2880 break;
2881
890ca9ae
HY		 2882 case MSR_IA32_MCG_CTL:
2883 case MSR_IA32_MCG_STATUS:
81760dcc 2884 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2885 return set_msr_mce(vcpu, msr_info);
71db6023 2886
6912ac32
WH		 2887 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2888 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2889 pr = true; /* fall through */
2890 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2891 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2892 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2893 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2894
2895 if (pr || data != 0)
a737f256
CD		 2896 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2897 "0x%x data 0x%llx\n", msr, data);
5753785f 2898 break;
84e0cefa
JS		 2899 case MSR_K7_CLK_CTL:
2900 /*
2901 * Ignore all writes to this no longer documented MSR.
2902 * Writes are only relevant for old K7 processors,
2903 * all pre-dating SVM, but a recommended workaround from
4a969980 2904 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2905 * affected processor models on the command line, hence
2906 * the need to ignore the workaround.
2907 */
2908 break;
55cd8e5a 2909 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2910 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2911 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2912 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2913 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2914 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2915 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2916 return kvm_hv_set_msr_common(vcpu, msr, data,
2917 msr_info->host_initiated);
91c9c3ed 2918 case MSR_IA32_BBL_CR_CTL3:
2919 /* Drop writes to this legacy MSR -- see rdmsr
2920 * counterpart for further detail.
2921 */
fab0aa3b
EM		 2922 if (report_ignored_msrs)
2923 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2924 msr, data);
91c9c3ed 2925 break;
2b036c6b 2926 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2927 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2928 return 1;
2929 vcpu->arch.osvw.length = data;
2930 break;
2931 case MSR_AMD64_OSVW_STATUS:
d6321d49 2932 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2933 return 1;
2934 vcpu->arch.osvw.status = data;
2935 break;
db2336a8
KH		 2936 case MSR_PLATFORM_INFO:
2937 if (!msr_info->host_initiated ||
db2336a8
KH		 2938 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2939 cpuid_fault_enabled(vcpu)))
2940 return 1;
2941 vcpu->arch.msr_platform_info = data;
2942 break;
2943 case MSR_MISC_FEATURES_ENABLES:
2944 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2945 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2946 !supports_cpuid_fault(vcpu)))
2947 return 1;
2948 vcpu->arch.msr_misc_features_enables = data;
2949 break;
15c4a640 2950 default:
ffde22ac
ES		 2951 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2952 return xen_hvm_config(vcpu, data);
c6702c9d 2953 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2954 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2955 if (!ignore_msrs) {
ae0f5499 2956 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2957 msr, data);
ed85c068
AP		 2958 return 1;
2959 } else {
fab0aa3b
EM		 2960 if (report_ignored_msrs)
2961 vcpu_unimpl(vcpu,
2962 "ignored wrmsr: 0x%x data 0x%llx\n",
2963 msr, data);
ed85c068
AP		 2964 break;
2965 }
15c4a640
CO		 2966 }
2967 return 0;
2968}
2969EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2970
44883f01 2971static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2972{
2973 u64 data;
890ca9ae
HY		 2974 u64 mcg_cap = vcpu->arch.mcg_cap;
2975 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2976
2977 switch (msr) {
15c4a640
CO		 2978 case MSR_IA32_P5_MC_ADDR:
2979 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2980 data = 0;
2981 break;
15c4a640 2982 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2983 data = vcpu->arch.mcg_cap;
2984 break;
c7ac679c 2985 case MSR_IA32_MCG_CTL:
44883f01 2986 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2987 return 1;
2988 data = vcpu->arch.mcg_ctl;
2989 break;
2990 case MSR_IA32_MCG_STATUS:
2991 data = vcpu->arch.mcg_status;
2992 break;
2993 default:
2994 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2995 msr < MSR_IA32_MCx_CTL(bank_num)) {
6ec4c5ee
MP		 2996 u32 offset = array_index_nospec(
2997 msr - MSR_IA32_MC0_CTL,
2998 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2999
890ca9ae
HY		 3000 data = vcpu->arch.mce_banks[offset];
3001 break;
3002 }
3003 return 1;
3004 }
3005 *pdata = data;
3006 return 0;
3007}
3008
609e36d3 3009int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 3010{
609e36d3 3011 switch (msr_info->index) {
890ca9ae 3012 case MSR_IA32_PLATFORM_ID:
15c4a640 3013 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 3014 case MSR_IA32_DEBUGCTLMSR:
3015 case MSR_IA32_LASTBRANCHFROMIP:
3016 case MSR_IA32_LASTBRANCHTOIP:
3017 case MSR_IA32_LASTINTFROMIP:
3018 case MSR_IA32_LASTINTTOIP:
60af2ecd 3019 case MSR_K8_SYSCFG:
3afb1121
PB		 3020 case MSR_K8_TSEG_ADDR:
3021 case MSR_K8_TSEG_MASK:
61a6bd67 3022 case MSR_VM_HSAVE_PA:
1fdbd48c 3023 case MSR_K8_INT_PENDING_MSG:
c323c0e5 3024 case MSR_AMD64_NB_CFG:
f7c6d140 3025 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 3026 case MSR_AMD64_BU_CFG2:
0c2df2a1 3027 case MSR_IA32_PERF_CTL:
405a353a 3028 case MSR_AMD64_DC_CFG:
0e1b869f 3029 case MSR_F15H_EX_CFG:
609e36d3 3030 msr_info->data = 0;
15c4a640 3031 break;
c51eb52b 3032 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 3033 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3034 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3035 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3036 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 3037 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 3038 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3039 msr_info->data = 0;
5753785f 3040 break;
742bc670 3041 case MSR_IA32_UCODE_REV:
518e7b94 3042 msr_info->data = vcpu->arch.microcode_version;
742bc670 3043 break;
0cf9135b
SC		 3044 case MSR_IA32_ARCH_CAPABILITIES:
3045 if (!msr_info->host_initiated &&
3046 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3047 return 1;
3048 msr_info->data = vcpu->arch.arch_capabilities;
3049 break;
73f624f4
PB		 3050 case MSR_IA32_POWER_CTL:
3051 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3052 break;
dd259935
PB		 3053 case MSR_IA32_TSC:
3054 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3055 break;
9ba075a6 3056 case MSR_MTRRcap:
9ba075a6 3057 case 0x200 ... 0x2ff:
ff53604b 3058 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 3059 case 0xcd: /* fsb frequency */
609e36d3 3060 msr_info->data = 3;
15c4a640 3061 break;
7b914098
JS		 3062 /*
3063 * MSR_EBC_FREQUENCY_ID
3064 * Conservative value valid for even the basic CPU models.
3065 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3066 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3067 * and 266MHz for model 3, or 4. Set Core Clock
3068 * Frequency to System Bus Frequency Ratio to 1 (bits
3069 * 31:24) even though these are only valid for CPU
3070 * models > 2, however guests may end up dividing or
3071 * multiplying by zero otherwise.
3072 */
3073 case MSR_EBC_FREQUENCY_ID:
609e36d3 3074 msr_info->data = 1 << 24;
7b914098 3075 break;
15c4a640 3076 case MSR_IA32_APICBASE:
609e36d3 3077 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 3078 break;
0105d1a5 3079 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 3080 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 3081 break;
a3e06bbe 3082 case MSR_IA32_TSCDEADLINE:
609e36d3 3083 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 3084 break;
ba904635 3085 case MSR_IA32_TSC_ADJUST:
609e36d3 3086 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 3087 break;
15c4a640 3088 case MSR_IA32_MISC_ENABLE:
609e36d3 3089 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 3090 break;
64d60670
PB		 3091 case MSR_IA32_SMBASE:
3092 if (!msr_info->host_initiated)
3093 return 1;
3094 msr_info->data = vcpu->arch.smbase;
15c4a640 3095 break;
52797bf9
LA		 3096 case MSR_SMI_COUNT:
3097 msr_info->data = vcpu->arch.smi_count;
3098 break;
847f0ad8
AG		 3099 case MSR_IA32_PERF_STATUS:
3100 /* TSC increment by tick */
609e36d3 3101 msr_info->data = 1000ULL;
847f0ad8 3102 /* CPU multiplier */
b0996ae4 3103 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 3104 break;
15c4a640 3105 case MSR_EFER:
609e36d3 3106 msr_info->data = vcpu->arch.efer;
15c4a640 3107 break;
18068523 3108 case MSR_KVM_WALL_CLOCK:
11c6bffa 3109 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 3110 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 3111 break;
3112 case MSR_KVM_SYSTEM_TIME:
11c6bffa 3113 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 3114 msr_info->data = vcpu->arch.time;
18068523 3115 break;
344d9588 3116 case MSR_KVM_ASYNC_PF_EN:
609e36d3 3117 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 3118 break;
c9aaa895 3119 case MSR_KVM_STEAL_TIME:
609e36d3 3120 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 3121 break;
1d92128f 3122 case MSR_KVM_PV_EOI_EN:
609e36d3 3123 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 3124 break;
2d5ba19b
MT		 3125 case MSR_KVM_POLL_CONTROL:
3126 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3127 break;
890ca9ae
HY		 3128 case MSR_IA32_P5_MC_ADDR:
3129 case MSR_IA32_P5_MC_TYPE:
3130 case MSR_IA32_MCG_CAP:
3131 case MSR_IA32_MCG_CTL:
3132 case MSR_IA32_MCG_STATUS:
81760dcc 3133 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 3134 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3135 msr_info->host_initiated);
864e2ab2
AL		 3136 case MSR_IA32_XSS:
3137 if (!msr_info->host_initiated &&
3138 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3139 return 1;
3140 msr_info->data = vcpu->arch.ia32_xss;
3141 break;
84e0cefa
JS		 3142 case MSR_K7_CLK_CTL:
3143 /*
3144 * Provide expected ramp-up count for K7. All other
3145 * are set to zero, indicating minimum divisors for
3146 * every field.
3147 *
3148 * This prevents guest kernels on AMD host with CPU
3149 * type 6, model 8 and higher from exploding due to
3150 * the rdmsr failing.
3151 */
609e36d3 3152 msr_info->data = 0x20000000;
84e0cefa 3153 break;
55cd8e5a 3154 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 3155 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3156 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 3157 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 3158 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3159 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3160 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 3161 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 3162 msr_info->index, &msr_info->data,
3163 msr_info->host_initiated);
55cd8e5a 3164 break;
91c9c3ed 3165 case MSR_IA32_BBL_CR_CTL3:
3166 /* This legacy MSR exists but isn't fully documented in current
3167 * silicon. It is however accessed by winxp in very narrow
3168 * scenarios where it sets bit #19, itself documented as
3169 * a "reserved" bit. Best effort attempt to source coherent
3170 * read data here should the balance of the register be
3171 * interpreted by the guest:
3172 *
3173 * L2 cache control register 3: 64GB range, 256KB size,
3174 * enabled, latency 0x1, configured
3175 */
609e36d3 3176 msr_info->data = 0xbe702111;
91c9c3ed 3177 break;
2b036c6b 3178 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 3179 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 3180 return 1;
609e36d3 3181 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 3182 break;
3183 case MSR_AMD64_OSVW_STATUS:
d6321d49 3184 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 3185 return 1;
609e36d3 3186 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 3187 break;
db2336a8 3188 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 3189 if (!msr_info->host_initiated &&
3190 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3191 return 1;
db2336a8
KH		 3192 msr_info->data = vcpu->arch.msr_platform_info;
3193 break;
3194 case MSR_MISC_FEATURES_ENABLES:
3195 msr_info->data = vcpu->arch.msr_misc_features_enables;
3196 break;
191c8137
BP		 3197 case MSR_K7_HWCR:
3198 msr_info->data = vcpu->arch.msr_hwcr;
3199 break;
15c4a640 3200 default:
c6702c9d 3201 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 3202 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 3203 if (!ignore_msrs) {
ae0f5499
BD		 3204 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3205 msr_info->index);
ed85c068
AP		 3206 return 1;
3207 } else {
fab0aa3b
EM		 3208 if (report_ignored_msrs)
3209 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3210 msr_info->index);
609e36d3 3211 msr_info->data = 0;
ed85c068
AP		 3212 }
3213 break;
15c4a640 3214 }
15c4a640
CO		 3215 return 0;
3216}
3217EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3218
313a3dc7
CO		 3219/*
3220 * Read or write a bunch of msrs. All parameters are kernel addresses.
3221 *
3222 * @return number of msrs set successfully.
3223 */
3224static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3225 struct kvm_msr_entry *entries,
3226 int (*do_msr)(struct kvm_vcpu *vcpu,
3227 unsigned index, u64 *data))
3228{
801e459a 3229 int i;
313a3dc7 3230
313a3dc7
CO		 3231 for (i = 0; i < msrs->nmsrs; ++i)
3232 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3233 break;
3234
313a3dc7
CO		 3235 return i;
3236}
3237
3238/*
3239 * Read or write a bunch of msrs. Parameters are user addresses.
3240 *
3241 * @return number of msrs set successfully.
3242 */
3243static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3244 int (*do_msr)(struct kvm_vcpu *vcpu,
3245 unsigned index, u64 *data),
3246 int writeback)
3247{
3248 struct kvm_msrs msrs;
3249 struct kvm_msr_entry *entries;
3250 int r, n;
3251 unsigned size;
3252
3253 r = -EFAULT;
0e96f31e 3254 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 3255 goto out;
3256
3257 r = -E2BIG;
3258 if (msrs.nmsrs >= MAX_IO_MSRS)
3259 goto out;
3260
313a3dc7 3261 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 3262 entries = memdup_user(user_msrs->entries, size);
3263 if (IS_ERR(entries)) {
3264 r = PTR_ERR(entries);
313a3dc7 3265 goto out;
ff5c2c03 3266 }
313a3dc7
CO		 3267
3268 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3269 if (r < 0)
3270 goto out_free;
3271
3272 r = -EFAULT;
3273 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3274 goto out_free;
3275
3276 r = n;
3277
3278out_free:
7a73c028 3279 kfree(entries);
313a3dc7
CO		 3280out:
3281 return r;
3282}
3283
4d5422ce
WL		 3284static inline bool kvm_can_mwait_in_guest(void)
3285{
3286 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 3287 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3288 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 3289}
3290
784aa3d7 3291int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 3292{
4d5422ce 3293 int r = 0;
018d00d2
ZX		 3294
3295 switch (ext) {
3296 case KVM_CAP_IRQCHIP:
3297 case KVM_CAP_HLT:
3298 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 3299 case KVM_CAP_SET_TSS_ADDR:
07716717 3300 case KVM_CAP_EXT_CPUID:
9c15bb1d 3301 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3302 case KVM_CAP_CLOCKSOURCE:
7837699f 3303 case KVM_CAP_PIT:
a28e4f5a 3304 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3305 case KVM_CAP_MP_STATE:
ed848624 3306 case KVM_CAP_SYNC_MMU:
a355c85c 3307 case KVM_CAP_USER_NMI:
52d939a0 3308 case KVM_CAP_REINJECT_CONTROL:
4925663a 3309 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3310 case KVM_CAP_IOEVENTFD:
f848a5a8 3311 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3312 case KVM_CAP_PIT2:
e9f42757 3313 case KVM_CAP_PIT_STATE2:
b927a3ce 3314 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3315 case KVM_CAP_XEN_HVM:
3cfc3092 3316 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3317 case KVM_CAP_HYPERV:
10388a07 3318 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3319 case KVM_CAP_HYPERV_SPIN:
5c919412 3320 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3321 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3322 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3323 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3324 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3325 case KVM_CAP_HYPERV_SEND_IPI:
2bc39970 3326 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3327 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3328 case KVM_CAP_DEBUGREGS:
d2be1651 3329 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3330 case KVM_CAP_XSAVE:
344d9588 3331 case KVM_CAP_ASYNC_PF:
92a1f12d 3332 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3333 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3334 case KVM_CAP_READONLY_MEM:
5f66b620 3335 case KVM_CAP_HYPERV_TIME:
100943c5 3336 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3337 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3338 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3339 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3340 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3341 case KVM_CAP_IMMEDIATE_EXIT:
66bb8a06 3342 case KVM_CAP_PMU_EVENT_FILTER:
801e459a 3343 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3344 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3345 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3346 r = 1;
3347 break;
01643c51
KH		 3348 case KVM_CAP_SYNC_REGS:
3349 r = KVM_SYNC_X86_VALID_FIELDS;
3350 break;
e3fd9a93
PB		 3351 case KVM_CAP_ADJUST_CLOCK:
3352 r = KVM_CLOCK_TSC_STABLE;
3353 break;
4d5422ce 3354 case KVM_CAP_X86_DISABLE_EXITS:
b5170063
WL		 3355 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3356 KVM_X86_DISABLE_EXITS_CSTATE;
4d5422ce
WL		 3357 if(kvm_can_mwait_in_guest())
3358 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3359 break;
6d396b55
PB		 3360 case KVM_CAP_X86_SMM:
3361 /* SMBASE is usually relocated above 1M on modern chipsets,
3362 * and SMM handlers might indeed rely on 4G segment limits,
3363 * so do not report SMM to be available if real mode is
3364 * emulated via vm86 mode. Still, do not go to great lengths
3365 * to avoid userspace's usage of the feature, because it is a
3366 * fringe case that is not enabled except via specific settings
3367 * of the module parameters.
3368 */
bc226f07 3369 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3370 break;
774ead3a
AK		 3371 case KVM_CAP_VAPIC:
3372 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3373 break;
f725230a 3374 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3375 r = KVM_SOFT_MAX_VCPUS;
3376 break;
3377 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3378 r = KVM_MAX_VCPUS;
3379 break;
a86cb413
TH		 3380 case KVM_CAP_MAX_VCPU_ID:
3381 r = KVM_MAX_VCPU_ID;
3382 break;
a68a6a72
MT		 3383 case KVM_CAP_PV_MMU: /* obsolete */
3384 r = 0;
2f333bcb 3385 break;
890ca9ae
HY		 3386 case KVM_CAP_MCE:
3387 r = KVM_MAX_MCE_BANKS;
3388 break;
2d5b5a66 3389 case KVM_CAP_XCRS:
d366bf7e 3390 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3391 break;
92a1f12d
JR		 3392 case KVM_CAP_TSC_CONTROL:
3393 r = kvm_has_tsc_control;
3394 break;
37131313
RK		 3395 case KVM_CAP_X2APIC_API:
3396 r = KVM_X2APIC_API_VALID_FLAGS;
3397 break;
8fcc4b59
JM		 3398 case KVM_CAP_NESTED_STATE:
3399 r = kvm_x86_ops->get_nested_state ?
be43c440 3400 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3401 break;
344c6c80 3402 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5a0165f6
VK		 3403 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3404 break;
3405 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3406 r = kvm_x86_ops->nested_enable_evmcs != NULL;
344c6c80 3407 break;
018d00d2 3408 default:
018d00d2
ZX		 3409 break;
3410 }
3411 return r;
3412
3413}
3414
043405e1
CO		 3415long kvm_arch_dev_ioctl(struct file *filp,
3416 unsigned int ioctl, unsigned long arg)
3417{
3418 void __user *argp = (void __user *)arg;
3419 long r;
3420
3421 switch (ioctl) {
3422 case KVM_GET_MSR_INDEX_LIST: {
3423 struct kvm_msr_list __user *user_msr_list = argp;
3424 struct kvm_msr_list msr_list;
3425 unsigned n;
3426
3427 r = -EFAULT;
0e96f31e 3428 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3429 goto out;
3430 n = msr_list.nmsrs;
62ef68bb 3431 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3432 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3433 goto out;
3434 r = -E2BIG;
e125e7b6 3435 if (n < msr_list.nmsrs)
043405e1
CO		 3436 goto out;
3437 r = -EFAULT;
3438 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3439 num_msrs_to_save * sizeof(u32)))
3440 goto out;
e125e7b6 3441 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3442 &emulated_msrs,
62ef68bb 3443 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3444 goto out;
3445 r = 0;
3446 break;
3447 }
9c15bb1d
BP		 3448 case KVM_GET_SUPPORTED_CPUID:
3449 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3450 struct kvm_cpuid2 __user *cpuid_arg = argp;
3451 struct kvm_cpuid2 cpuid;
3452
3453 r = -EFAULT;
0e96f31e 3454 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3455 goto out;
9c15bb1d
BP		 3456
3457 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3458 ioctl);
674eea0f
AK		 3459 if (r)
3460 goto out;
3461
3462 r = -EFAULT;
0e96f31e 3463 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3464 goto out;
3465 r = 0;
3466 break;
3467 }
890ca9ae 3468 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3469 r = -EFAULT;
c45dcc71
AR		 3470 if (copy_to_user(argp, &kvm_mce_cap_supported,
3471 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3472 goto out;
3473 r = 0;
3474 break;
801e459a
TL		 3475 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3476 struct kvm_msr_list __user *user_msr_list = argp;
3477 struct kvm_msr_list msr_list;
3478 unsigned int n;
3479
3480 r = -EFAULT;
3481 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3482 goto out;
3483 n = msr_list.nmsrs;
3484 msr_list.nmsrs = num_msr_based_features;
3485 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3486 goto out;
3487 r = -E2BIG;
3488 if (n < msr_list.nmsrs)
3489 goto out;
3490 r = -EFAULT;
3491 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3492 num_msr_based_features * sizeof(u32)))
3493 goto out;
3494 r = 0;
3495 break;
3496 }
3497 case KVM_GET_MSRS:
3498 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3499 break;
890ca9ae 3500 }
043405e1
CO		 3501 default:
3502 r = -EINVAL;
3503 }
3504out:
3505 return r;
3506}
3507
f5f48ee1
SY		 3508static void wbinvd_ipi(void *garbage)
3509{
3510 wbinvd();
3511}
3512
3513static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3514{
e0f0bbc5 3515 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3516}
3517
313a3dc7
CO		 3518void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3519{
f5f48ee1
SY		 3520 /* Address WBINVD may be executed by guest */
3521 if (need_emulate_wbinvd(vcpu)) {
3522 if (kvm_x86_ops->has_wbinvd_exit())
3523 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3524 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3525 smp_call_function_single(vcpu->cpu,
3526 wbinvd_ipi, NULL, 1);
3527 }
3528
313a3dc7 3529 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3530
e7517324
WL		 3531 fpregs_assert_state_consistent();
3532 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3533 switch_fpu_return();
3534
0dd6a6ed
ZA		 3535 /* Apply any externally detected TSC adjustments (due to suspend) */
3536 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3537 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3538 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3539 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3540 }
8f6055cb 3541
b0c39dc6 3542 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3543 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3544 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3545 if (tsc_delta < 0)
3546 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3547
b0c39dc6 3548 if (kvm_check_tsc_unstable()) {
07c1419a 3549 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3550 vcpu->arch.last_guest_tsc);
a545ab6a 3551 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3552 vcpu->arch.tsc_catchup = 1;
c285545f 3553 }
a749e247
PB		 3554
3555 if (kvm_lapic_hv_timer_in_use(vcpu))
3556 kvm_lapic_restart_hv_timer(vcpu);
3557
d98d07ca
MT		 3558 /*
3559 * On a host with synchronized TSC, there is no need to update
3560 * kvmclock on vcpu->cpu migration
3561 */
3562 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3563 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3564 if (vcpu->cpu != cpu)
1bd2009e 3565 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3566 vcpu->cpu = cpu;
6b7d7e76 3567 }
c9aaa895 3568
c9aaa895 3569 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3570}
3571
0b9f6c46
PX		 3572static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3573{
3574 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3575 return;
3576
fa55eedd 3577 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3578
4e335d9e 3579 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3580 &vcpu->arch.st.steal.preempted,
3581 offsetof(struct kvm_steal_time, preempted),
3582 sizeof(vcpu->arch.st.steal.preempted));
3583}
3584
313a3dc7
CO		 3585void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3586{
cc0d907c 3587 int idx;
de63ad4c
LM		 3588
3589 if (vcpu->preempted)
3590 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3591
931f261b
AA		 3592 /*
3593 * Disable page faults because we're in atomic context here.
3594 * kvm_write_guest_offset_cached() would call might_fault()
3595 * that relies on pagefault_disable() to tell if there's a
3596 * bug. NOTE: the write to guest memory may not go through if
3597 * during postcopy live migration or if there's heavy guest
3598 * paging.
3599 */
3600 pagefault_disable();
cc0d907c
AA		 3601 /*
3602 * kvm_memslots() will be called by
3603 * kvm_write_guest_offset_cached() so take the srcu lock.
3604 */
3605 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3606 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3607 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3608 pagefault_enable();
02daab21 3609 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3610 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3611 /*
f9dcf08e
RK		 3612 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3613 * on every vmexit, but if not, we might have a stale dr6 from the
3614 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3615 */
f9dcf08e 3616 set_debugreg(0, 6);
313a3dc7
CO		 3617}
3618
313a3dc7
CO		 3619static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3620 struct kvm_lapic_state *s)
3621{
fa59cc00 3622 if (vcpu->arch.apicv_active)
d62caabb
AS		 3623 kvm_x86_ops->sync_pir_to_irr(vcpu);
3624
a92e2543 3625 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3626}
3627
3628static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3629 struct kvm_lapic_state *s)
3630{
a92e2543
RK		 3631 int r;
3632
3633 r = kvm_apic_set_state(vcpu, s);
3634 if (r)
3635 return r;
cb142eb7 3636 update_cr8_intercept(vcpu);
313a3dc7
CO		 3637
3638 return 0;
3639}
3640
127a457a
MG		 3641static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3642{
3643 return (!lapic_in_kernel(vcpu) ||
3644 kvm_apic_accept_pic_intr(vcpu));
3645}
3646
782d422b
MG		 3647/*
3648 * if userspace requested an interrupt window, check that the
3649 * interrupt window is open.
3650 *
3651 * No need to exit to userspace if we already have an interrupt queued.
3652 */
3653static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3654{
3655 return kvm_arch_interrupt_allowed(vcpu) &&
3656 !kvm_cpu_has_interrupt(vcpu) &&
3657 !kvm_event_needs_reinjection(vcpu) &&
3658 kvm_cpu_accept_dm_intr(vcpu);
3659}
3660
f77bc6a4
ZX		 3661static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3662 struct kvm_interrupt *irq)
3663{
02cdb50f 3664 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3665 return -EINVAL;
1c1a9ce9
SR		 3666
3667 if (!irqchip_in_kernel(vcpu->kvm)) {
3668 kvm_queue_interrupt(vcpu, irq->irq, false);
3669 kvm_make_request(KVM_REQ_EVENT, vcpu);
3670 return 0;
3671 }
3672
3673 /*
3674 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3675 * fail for in-kernel 8259.
3676 */
3677 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3678 return -ENXIO;
f77bc6a4 3679
1c1a9ce9
SR		 3680 if (vcpu->arch.pending_external_vector != -1)
3681 return -EEXIST;
f77bc6a4 3682
1c1a9ce9 3683 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3684 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3685 return 0;
3686}
3687
c4abb7c9
JK		 3688static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3689{
c4abb7c9 3690 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3691
3692 return 0;
3693}
3694
f077825a
PB		 3695static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3696{
64d60670
PB		 3697 kvm_make_request(KVM_REQ_SMI, vcpu);
3698
f077825a
PB		 3699 return 0;
3700}
3701
b209749f
AK		 3702static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3703 struct kvm_tpr_access_ctl *tac)
3704{
3705 if (tac->flags)
3706 return -EINVAL;
3707 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3708 return 0;
3709}
3710
890ca9ae
HY		 3711static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3712 u64 mcg_cap)
3713{
3714 int r;
3715 unsigned bank_num = mcg_cap & 0xff, bank;
3716
3717 r = -EINVAL;
a9e38c3e 3718 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3719 goto out;
c45dcc71 3720 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3721 goto out;
3722 r = 0;
3723 vcpu->arch.mcg_cap = mcg_cap;
3724 /* Init IA32_MCG_CTL to all 1s */
3725 if (mcg_cap & MCG_CTL_P)
3726 vcpu->arch.mcg_ctl = ~(u64)0;
3727 /* Init IA32_MCi_CTL to all 1s */
3728 for (bank = 0; bank < bank_num; bank++)
3729 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71 3730
92735b1b 3731 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3732out:
3733 return r;
3734}
3735
3736static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3737 struct kvm_x86_mce *mce)
3738{
3739 u64 mcg_cap = vcpu->arch.mcg_cap;
3740 unsigned bank_num = mcg_cap & 0xff;
3741 u64 *banks = vcpu->arch.mce_banks;
3742
3743 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3744 return -EINVAL;
3745 /*
3746 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3747 * reporting is disabled
3748 */
3749 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3750 vcpu->arch.mcg_ctl != ~(u64)0)
3751 return 0;
3752 banks += 4 * mce->bank;
3753 /*
3754 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3755 * reporting is disabled for the bank
3756 */
3757 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3758 return 0;
3759 if (mce->status & MCI_STATUS_UC) {
3760 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3761 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3762 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3763 return 0;
3764 }
3765 if (banks[1] & MCI_STATUS_VAL)
3766 mce->status |= MCI_STATUS_OVER;
3767 banks[2] = mce->addr;
3768 banks[3] = mce->misc;
3769 vcpu->arch.mcg_status = mce->mcg_status;
3770 banks[1] = mce->status;
3771 kvm_queue_exception(vcpu, MC_VECTOR);
3772 } else if (!(banks[1] & MCI_STATUS_VAL)
3773 || !(banks[1] & MCI_STATUS_UC)) {
3774 if (banks[1] & MCI_STATUS_VAL)
3775 mce->status |= MCI_STATUS_OVER;
3776 banks[2] = mce->addr;
3777 banks[3] = mce->misc;
3778 banks[1] = mce->status;
3779 } else
3780 banks[1] |= MCI_STATUS_OVER;
3781 return 0;
3782}
3783
3cfc3092
JK		 3784static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3785 struct kvm_vcpu_events *events)
3786{
7460fb4a 3787 process_nmi(vcpu);
59073aaf 3788
664f8e26 3789 /*
59073aaf
JM		 3790 * The API doesn't provide the instruction length for software
3791 * exceptions, so don't report them. As long as the guest RIP
3792 * isn't advanced, we should expect to encounter the exception
3793 * again.
664f8e26 3794 */
59073aaf
JM		 3795 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3796 events->exception.injected = 0;
3797 events->exception.pending = 0;
3798 } else {
3799 events->exception.injected = vcpu->arch.exception.injected;
3800 events->exception.pending = vcpu->arch.exception.pending;
3801 /*
3802 * For ABI compatibility, deliberately conflate
3803 * pending and injected exceptions when
3804 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3805 */
3806 if (!vcpu->kvm->arch.exception_payload_enabled)
3807 events->exception.injected |=
3808 vcpu->arch.exception.pending;
3809 }
3cfc3092
JK		 3810 events->exception.nr = vcpu->arch.exception.nr;
3811 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3812 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3813 events->exception_has_payload = vcpu->arch.exception.has_payload;
3814 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3815
03b82a30 3816 events->interrupt.injected =
04140b41 3817 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3818 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3819 events->interrupt.soft = 0;
37ccdcbe 3820 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3821
3822 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3823 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3824 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3825 events->nmi.pad = 0;
3cfc3092 3826
66450a21 3827 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3828
f077825a
PB		 3829 events->smi.smm = is_smm(vcpu);
3830 events->smi.pending = vcpu->arch.smi_pending;
3831 events->smi.smm_inside_nmi =
3832 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3833 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3834
dab4b911 3835 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3836 | KVM_VCPUEVENT_VALID_SHADOW
3837 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3838 if (vcpu->kvm->arch.exception_payload_enabled)
3839 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3840
97e69aa6 3841 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3842}
3843
c5833c7a 3844static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3845
3cfc3092
JK		 3846static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3847 struct kvm_vcpu_events *events)
3848{
dab4b911 3849 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3850 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3851 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3852 | KVM_VCPUEVENT_VALID_SMM
3853 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3854 return -EINVAL;
3855
59073aaf
JM		 3856 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3857 if (!vcpu->kvm->arch.exception_payload_enabled)
3858 return -EINVAL;
3859 if (events->exception.pending)
3860 events->exception.injected = 0;
3861 else
3862 events->exception_has_payload = 0;
3863 } else {
3864 events->exception.pending = 0;
3865 events->exception_has_payload = 0;
3866 }
3867
3868 if ((events->exception.injected || events->exception.pending) &&
3869 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3870 return -EINVAL;
3871
28bf2888
DH		 3872 /* INITs are latched while in SMM */
3873 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3874 (events->smi.smm || events->smi.pending) &&
3875 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3876 return -EINVAL;
3877
7460fb4a 3878 process_nmi(vcpu);
59073aaf
JM		 3879 vcpu->arch.exception.injected = events->exception.injected;
3880 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3881 vcpu->arch.exception.nr = events->exception.nr;
3882 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3883 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3884 vcpu->arch.exception.has_payload = events->exception_has_payload;
3885 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3886
04140b41 3887 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3888 vcpu->arch.interrupt.nr = events->interrupt.nr;
3889 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3890 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3891 kvm_x86_ops->set_interrupt_shadow(vcpu,
3892 events->interrupt.shadow);
3cfc3092
JK		 3893
3894 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3895 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3896 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3897 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3898
66450a21 3899 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3900 lapic_in_kernel(vcpu))
66450a21 3901 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3902
f077825a 3903 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3904 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3905 if (events->smi.smm)
3906 vcpu->arch.hflags |= HF_SMM_MASK;
3907 else
3908 vcpu->arch.hflags &= ~HF_SMM_MASK;
3909 kvm_smm_changed(vcpu);
3910 }
6ef4e07e 3911
f077825a 3912 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3913
3914 if (events->smi.smm) {
3915 if (events->smi.smm_inside_nmi)
3916 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3917 else
f4ef1910 3918 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
ff90afa7
LA		 3919 }
3920
3921 if (lapic_in_kernel(vcpu)) {
3922 if (events->smi.latched_init)
3923 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3924 else
3925 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
f077825a
PB		 3926 }
3927 }
3928
3842d135
AK		 3929 kvm_make_request(KVM_REQ_EVENT, vcpu);
3930
3cfc3092
JK		 3931 return 0;
3932}
3933
a1efbe77
JK		 3934static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3935 struct kvm_debugregs *dbgregs)
3936{
73aaf249
JK		 3937 unsigned long val;
3938
a1efbe77 3939 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3940 kvm_get_dr(vcpu, 6, &val);
73aaf249 3941 dbgregs->dr6 = val;
a1efbe77
JK		 3942 dbgregs->dr7 = vcpu->arch.dr7;
3943 dbgregs->flags = 0;
97e69aa6 3944 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3945}
3946
3947static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3948 struct kvm_debugregs *dbgregs)
3949{
3950 if (dbgregs->flags)
3951 return -EINVAL;
3952
d14bdb55
PB		 3953 if (dbgregs->dr6 & ~0xffffffffull)
3954 return -EINVAL;
3955 if (dbgregs->dr7 & ~0xffffffffull)
3956 return -EINVAL;
3957
a1efbe77 3958 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3959 kvm_update_dr0123(vcpu);
a1efbe77 3960 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3961 kvm_update_dr6(vcpu);
a1efbe77 3962 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3963 kvm_update_dr7(vcpu);
a1efbe77 3964
a1efbe77
JK		 3965 return 0;
3966}
3967
df1daba7
PB		 3968#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3969
3970static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3971{
b666a4b6 3972 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3973 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3974 u64 valid;
3975
3976 /*
3977 * Copy legacy XSAVE area, to avoid complications with CPUID
3978 * leaves 0 and 1 in the loop below.
3979 */
3980 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3981
3982 /* Set XSTATE_BV */
00c87e9a 3983 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3984 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3985
3986 /*
3987 * Copy each region from the possibly compacted offset to the
3988 * non-compacted offset.
3989 */
d91cab78 3990 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3991 while (valid) {
abd16d68
SAS		 3992 u64 xfeature_mask = valid & -valid;
3993 int xfeature_nr = fls64(xfeature_mask) - 1;
3994 void *src = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3995
3996 if (src) {
3997 u32 size, offset, ecx, edx;
abd16d68 3998 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3999 &size, &offset, &ecx, &edx);
abd16d68 4000 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 4001 memcpy(dest + offset, &vcpu->arch.pkru,
4002 sizeof(vcpu->arch.pkru));
4003 else
4004 memcpy(dest + offset, src, size);
4005
df1daba7
PB		 4006 }
4007
abd16d68 4008 valid -= xfeature_mask;
df1daba7
PB		 4009 }
4010}
4011
4012static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4013{
b666a4b6 4014 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 4015 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4016 u64 valid;
4017
4018 /*
4019 * Copy legacy XSAVE area, to avoid complications with CPUID
4020 * leaves 0 and 1 in the loop below.
4021 */
4022 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4023
4024 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 4025 xsave->header.xfeatures = xstate_bv;
782511b0 4026 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 4027 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 4028
4029 /*
4030 * Copy each region from the non-compacted offset to the
4031 * possibly compacted offset.
4032 */
d91cab78 4033 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 4034 while (valid) {
abd16d68
SAS		 4035 u64 xfeature_mask = valid & -valid;
4036 int xfeature_nr = fls64(xfeature_mask) - 1;
4037 void *dest = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 4038
4039 if (dest) {
4040 u32 size, offset, ecx, edx;
abd16d68 4041 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 4042 &size, &offset, &ecx, &edx);
abd16d68 4043 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 4044 memcpy(&vcpu->arch.pkru, src + offset,
4045 sizeof(vcpu->arch.pkru));
4046 else
4047 memcpy(dest, src + offset, size);
ee4100da 4048 }
df1daba7 4049
abd16d68 4050 valid -= xfeature_mask;
df1daba7
PB		 4051 }
4052}
4053
2d5b5a66
SY		 4054static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4055 struct kvm_xsave *guest_xsave)
4056{
d366bf7e 4057 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 4058 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4059 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 4060 } else {
2d5b5a66 4061 memcpy(guest_xsave->region,
b666a4b6 4062 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 4063 sizeof(struct fxregs_state));
2d5b5a66 4064 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 4065 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 4066 }
4067}
4068
a575813b
WL		 4069#define XSAVE_MXCSR_OFFSET 24
4070
2d5b5a66
SY		 4071static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4072 struct kvm_xsave *guest_xsave)
4073{
4074 u64 xstate_bv =
4075 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 4076 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 4077
d366bf7e 4078 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 4079 /*
4080 * Here we allow setting states that are not present in
4081 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4082 * with old userspace.
4083 */
a575813b
WL		 4084 if (xstate_bv & ~kvm_supported_xcr0() ||
4085 mxcsr & ~mxcsr_feature_mask)
d7876f1b 4086 return -EINVAL;
df1daba7 4087 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 4088 } else {
a575813b
WL		 4089 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4090 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 4091 return -EINVAL;
b666a4b6 4092 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 4093 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 4094 }
4095 return 0;
4096}
4097
4098static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4099 struct kvm_xcrs *guest_xcrs)
4100{
d366bf7e 4101 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 4102 guest_xcrs->nr_xcrs = 0;
4103 return;
4104 }
4105
4106 guest_xcrs->nr_xcrs = 1;
4107 guest_xcrs->flags = 0;
4108 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4109 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4110}
4111
4112static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4113 struct kvm_xcrs *guest_xcrs)
4114{
4115 int i, r = 0;
4116
d366bf7e 4117 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 4118 return -EINVAL;
4119
4120 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4121 return -EINVAL;
4122
4123 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4124 /* Only support XCR0 currently */
c67a04cb 4125 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 4126 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 4127 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 4128 break;
4129 }
4130 if (r)
4131 r = -EINVAL;
4132 return r;
4133}
4134
1c0b28c2
EM		 4135/*
4136 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4137 * stopped by the hypervisor. This function will be called from the host only.
4138 * EINVAL is returned when the host attempts to set the flag for a guest that
4139 * does not support pv clocks.
4140 */
4141static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4142{
0b79459b 4143 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 4144 return -EINVAL;
51d59c6b 4145 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 4146 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4147 return 0;
4148}
4149
5c919412
AS		 4150static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4151 struct kvm_enable_cap *cap)
4152{
57b119da
VK		 4153 int r;
4154 uint16_t vmcs_version;
4155 void __user *user_ptr;
4156
5c919412
AS		 4157 if (cap->flags)
4158 return -EINVAL;
4159
4160 switch (cap->cap) {
efc479e6
RK		 4161 case KVM_CAP_HYPERV_SYNIC2:
4162 if (cap->args[0])
4163 return -EINVAL;
b2869f28
GS		 4164 /* fall through */
4165
5c919412 4166 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 4167 if (!irqchip_in_kernel(vcpu->kvm))
4168 return -EINVAL;
efc479e6
RK		 4169 return kvm_hv_activate_synic(vcpu, cap->cap ==
4170 KVM_CAP_HYPERV_SYNIC2);
57b119da 4171 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 4172 if (!kvm_x86_ops->nested_enable_evmcs)
4173 return -ENOTTY;
57b119da
VK		 4174 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4175 if (!r) {
4176 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4177 if (copy_to_user(user_ptr, &vmcs_version,
4178 sizeof(vmcs_version)))
4179 r = -EFAULT;
4180 }
4181 return r;
344c6c80
TL		 4182 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4183 if (!kvm_x86_ops->enable_direct_tlbflush)
4184 return -ENOTTY;
4185
4186 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
57b119da 4187
5c919412
AS		 4188 default:
4189 return -EINVAL;
4190 }
4191}
4192
313a3dc7
CO		 4193long kvm_arch_vcpu_ioctl(struct file *filp,
4194 unsigned int ioctl, unsigned long arg)
4195{
4196 struct kvm_vcpu *vcpu = filp->private_data;
4197 void __user *argp = (void __user *)arg;
4198 int r;
d1ac91d8
AK		 4199 union {
4200 struct kvm_lapic_state *lapic;
4201 struct kvm_xsave *xsave;
4202 struct kvm_xcrs *xcrs;
4203 void *buffer;
4204 } u;
4205
9b062471
CD		 4206 vcpu_load(vcpu);
4207
d1ac91d8 4208 u.buffer = NULL;
313a3dc7
CO		 4209 switch (ioctl) {
4210 case KVM_GET_LAPIC: {
2204ae3c 4211 r = -EINVAL;
bce87cce 4212 if (!lapic_in_kernel(vcpu))
2204ae3c 4213 goto out;
254272ce
BG		 4214 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4215 GFP_KERNEL_ACCOUNT);
313a3dc7 4216
b772ff36 4217 r = -ENOMEM;
d1ac91d8 4218 if (!u.lapic)
b772ff36 4219 goto out;
d1ac91d8 4220 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 4221 if (r)
4222 goto out;
4223 r = -EFAULT;
d1ac91d8 4224 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 4225 goto out;
4226 r = 0;
4227 break;
4228 }
4229 case KVM_SET_LAPIC: {
2204ae3c 4230 r = -EINVAL;
bce87cce 4231 if (!lapic_in_kernel(vcpu))
2204ae3c 4232 goto out;
ff5c2c03 4233 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 4234 if (IS_ERR(u.lapic)) {
4235 r = PTR_ERR(u.lapic);
4236 goto out_nofree;
4237 }
ff5c2c03 4238
d1ac91d8 4239 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 4240 break;
4241 }
f77bc6a4
ZX		 4242 case KVM_INTERRUPT: {
4243 struct kvm_interrupt irq;
4244
4245 r = -EFAULT;
0e96f31e 4246 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 4247 goto out;
4248 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 4249 break;
4250 }
c4abb7c9
JK		 4251 case KVM_NMI: {
4252 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 4253 break;
4254 }
f077825a
PB		 4255 case KVM_SMI: {
4256 r = kvm_vcpu_ioctl_smi(vcpu);
4257 break;
4258 }
313a3dc7
CO		 4259 case KVM_SET_CPUID: {
4260 struct kvm_cpuid __user *cpuid_arg = argp;
4261 struct kvm_cpuid cpuid;
4262
4263 r = -EFAULT;
0e96f31e 4264 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 4265 goto out;
4266 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 4267 break;
4268 }
07716717
DK		 4269 case KVM_SET_CPUID2: {
4270 struct kvm_cpuid2 __user *cpuid_arg = argp;
4271 struct kvm_cpuid2 cpuid;
4272
4273 r = -EFAULT;
0e96f31e 4274 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4275 goto out;
4276 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 4277 cpuid_arg->entries);
07716717
DK		 4278 break;
4279 }
4280 case KVM_GET_CPUID2: {
4281 struct kvm_cpuid2 __user *cpuid_arg = argp;
4282 struct kvm_cpuid2 cpuid;
4283
4284 r = -EFAULT;
0e96f31e 4285 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4286 goto out;
4287 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 4288 cpuid_arg->entries);
07716717
DK		 4289 if (r)
4290 goto out;
4291 r = -EFAULT;
0e96f31e 4292 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 4293 goto out;
4294 r = 0;
4295 break;
4296 }
801e459a
TL		 4297 case KVM_GET_MSRS: {
4298 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 4299 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 4300 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4301 break;
801e459a
TL		 4302 }
4303 case KVM_SET_MSRS: {
4304 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 4305 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 4306 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4307 break;
801e459a 4308 }
b209749f
AK		 4309 case KVM_TPR_ACCESS_REPORTING: {
4310 struct kvm_tpr_access_ctl tac;
4311
4312 r = -EFAULT;
0e96f31e 4313 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 4314 goto out;
4315 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4316 if (r)
4317 goto out;
4318 r = -EFAULT;
0e96f31e 4319 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4320 goto out;
4321 r = 0;
4322 break;
4323 };
b93463aa
AK		 4324 case KVM_SET_VAPIC_ADDR: {
4325 struct kvm_vapic_addr va;
7301d6ab 4326 int idx;
b93463aa
AK		 4327
4328 r = -EINVAL;
35754c98 4329 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4330 goto out;
4331 r = -EFAULT;
0e96f31e 4332 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4333 goto out;
7301d6ab 4334 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4335 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4336 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4337 break;
4338 }
890ca9ae
HY		 4339 case KVM_X86_SETUP_MCE: {
4340 u64 mcg_cap;
4341
4342 r = -EFAULT;
0e96f31e 4343 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4344 goto out;
4345 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4346 break;
4347 }
4348 case KVM_X86_SET_MCE: {
4349 struct kvm_x86_mce mce;
4350
4351 r = -EFAULT;
0e96f31e 4352 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4353 goto out;
4354 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4355 break;
4356 }
3cfc3092
JK		 4357 case KVM_GET_VCPU_EVENTS: {
4358 struct kvm_vcpu_events events;
4359
4360 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4361
4362 r = -EFAULT;
4363 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4364 break;
4365 r = 0;
4366 break;
4367 }
4368 case KVM_SET_VCPU_EVENTS: {
4369 struct kvm_vcpu_events events;
4370
4371 r = -EFAULT;
4372 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4373 break;
4374
4375 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4376 break;
4377 }
a1efbe77
JK		 4378 case KVM_GET_DEBUGREGS: {
4379 struct kvm_debugregs dbgregs;
4380
4381 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4382
4383 r = -EFAULT;
4384 if (copy_to_user(argp, &dbgregs,
4385 sizeof(struct kvm_debugregs)))
4386 break;
4387 r = 0;
4388 break;
4389 }
4390 case KVM_SET_DEBUGREGS: {
4391 struct kvm_debugregs dbgregs;
4392
4393 r = -EFAULT;
4394 if (copy_from_user(&dbgregs, argp,
4395 sizeof(struct kvm_debugregs)))
4396 break;
4397
4398 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4399 break;
4400 }
2d5b5a66 4401 case KVM_GET_XSAVE: {
254272ce 4402 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4403 r = -ENOMEM;
d1ac91d8 4404 if (!u.xsave)
2d5b5a66
SY		 4405 break;
4406
d1ac91d8 4407 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4408
4409 r = -EFAULT;
d1ac91d8 4410 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4411 break;
4412 r = 0;
4413 break;
4414 }
4415 case KVM_SET_XSAVE: {
ff5c2c03 4416 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4417 if (IS_ERR(u.xsave)) {
4418 r = PTR_ERR(u.xsave);
4419 goto out_nofree;
4420 }
2d5b5a66 4421
d1ac91d8 4422 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4423 break;
4424 }
4425 case KVM_GET_XCRS: {
254272ce 4426 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4427 r = -ENOMEM;
d1ac91d8 4428 if (!u.xcrs)
2d5b5a66
SY		 4429 break;
4430
d1ac91d8 4431 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4432
4433 r = -EFAULT;
d1ac91d8 4434 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4435 sizeof(struct kvm_xcrs)))
4436 break;
4437 r = 0;
4438 break;
4439 }
4440 case KVM_SET_XCRS: {
ff5c2c03 4441 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4442 if (IS_ERR(u.xcrs)) {
4443 r = PTR_ERR(u.xcrs);
4444 goto out_nofree;
4445 }
2d5b5a66 4446
d1ac91d8 4447 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4448 break;
4449 }
92a1f12d
JR		 4450 case KVM_SET_TSC_KHZ: {
4451 u32 user_tsc_khz;
4452
4453 r = -EINVAL;
92a1f12d
JR		 4454 user_tsc_khz = (u32)arg;
4455
4456 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4457 goto out;
4458
cc578287
ZA		 4459 if (user_tsc_khz == 0)
4460 user_tsc_khz = tsc_khz;
4461
381d585c
HZ		 4462 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4463 r = 0;
92a1f12d 4464
92a1f12d
JR		 4465 goto out;
4466 }
4467 case KVM_GET_TSC_KHZ: {
cc578287 4468 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4469 goto out;
4470 }
1c0b28c2
EM		 4471 case KVM_KVMCLOCK_CTRL: {
4472 r = kvm_set_guest_paused(vcpu);
4473 goto out;
4474 }
5c919412
AS		 4475 case KVM_ENABLE_CAP: {
4476 struct kvm_enable_cap cap;
4477
4478 r = -EFAULT;
4479 if (copy_from_user(&cap, argp, sizeof(cap)))
4480 goto out;
4481 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4482 break;
4483 }
8fcc4b59
JM		 4484 case KVM_GET_NESTED_STATE: {
4485 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4486 u32 user_data_size;
4487
4488 r = -EINVAL;
4489 if (!kvm_x86_ops->get_nested_state)
4490 break;
4491
4492 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4493 r = -EFAULT;
8fcc4b59 4494 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4495 break;
8fcc4b59
JM		 4496
4497 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4498 user_data_size);
4499 if (r < 0)
26b471c7 4500 break;
8fcc4b59
JM		 4501
4502 if (r > user_data_size) {
4503 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4504 r = -EFAULT;
4505 else
4506 r = -E2BIG;
4507 break;
8fcc4b59 4508 }
26b471c7 4509
8fcc4b59
JM		 4510 r = 0;
4511 break;
4512 }
4513 case KVM_SET_NESTED_STATE: {
4514 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4515 struct kvm_nested_state kvm_state;
ad5996d9 4516 int idx;
8fcc4b59
JM		 4517
4518 r = -EINVAL;
4519 if (!kvm_x86_ops->set_nested_state)
4520 break;
4521
26b471c7 4522 r = -EFAULT;
8fcc4b59 4523 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4524 break;
8fcc4b59 4525
26b471c7 4526 r = -EINVAL;
8fcc4b59 4527 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4528 break;
8fcc4b59
JM		 4529
4530 if (kvm_state.flags &
8cab6507
VK		 4531 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4532 | KVM_STATE_NESTED_EVMCS))
26b471c7 4533 break;
8fcc4b59
JM		 4534
4535 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4536 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4537 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4538 break;
8fcc4b59 4539
ad5996d9 4540 idx = srcu_read_lock(&vcpu->kvm->srcu);
8fcc4b59 4541 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
ad5996d9 4542 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8fcc4b59
JM		 4543 break;
4544 }
2bc39970
VK		 4545 case KVM_GET_SUPPORTED_HV_CPUID: {
4546 struct kvm_cpuid2 __user *cpuid_arg = argp;
4547 struct kvm_cpuid2 cpuid;
4548
4549 r = -EFAULT;
4550 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4551 goto out;
4552
4553 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4554 cpuid_arg->entries);
4555 if (r)
4556 goto out;
4557
4558 r = -EFAULT;
4559 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4560 goto out;
4561 r = 0;
4562 break;
4563 }
313a3dc7
CO		 4564 default:
4565 r = -EINVAL;
4566 }
4567out:
d1ac91d8 4568 kfree(u.buffer);
9b062471
CD		 4569out_nofree:
4570 vcpu_put(vcpu);
313a3dc7
CO		 4571 return r;
4572}
4573
1499fa80 4574vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4575{
4576 return VM_FAULT_SIGBUS;
4577}
4578
1fe779f8
CO		 4579static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4580{
4581 int ret;
4582
4583 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4584 return -EINVAL;
1fe779f8
CO		 4585 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4586 return ret;
4587}
4588
b927a3ce
SY		 4589static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4590 u64 ident_addr)
4591{
2ac52ab8 4592 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4593}
4594
1fe779f8 4595static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4596 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4597{
4598 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4599 return -EINVAL;
4600
79fac95e 4601 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4602
4603 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4604 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4605
79fac95e 4606 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4607 return 0;
4608}
4609
bc8a3d89 4610static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4611{
39de71ec 4612 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4613}
4614
1fe779f8
CO		 4615static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4616{
90bca052 4617 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4618 int r;
4619
4620 r = 0;
4621 switch (chip->chip_id) {
4622 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4623 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4624 sizeof(struct kvm_pic_state));
4625 break;
4626 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4627 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4628 sizeof(struct kvm_pic_state));
4629 break;
4630 case KVM_IRQCHIP_IOAPIC:
33392b49 4631 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4632 break;
4633 default:
4634 r = -EINVAL;
4635 break;
4636 }
4637 return r;
4638}
4639
4640static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4641{
90bca052 4642 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4643 int r;
4644
4645 r = 0;
4646 switch (chip->chip_id) {
4647 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4648 spin_lock(&pic->lock);
4649 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4650 sizeof(struct kvm_pic_state));
90bca052 4651 spin_unlock(&pic->lock);
1fe779f8
CO		 4652 break;
4653 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4654 spin_lock(&pic->lock);
4655 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4656 sizeof(struct kvm_pic_state));
90bca052 4657 spin_unlock(&pic->lock);
1fe779f8
CO		 4658 break;
4659 case KVM_IRQCHIP_IOAPIC:
33392b49 4660 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4661 break;
4662 default:
4663 r = -EINVAL;
4664 break;
4665 }
90bca052 4666 kvm_pic_update_irq(pic);
1fe779f8
CO		 4667 return r;
4668}
4669
e0f63cb9
SY		 4670static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4671{
34f3941c
RK		 4672 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4673
4674 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4675
4676 mutex_lock(&kps->lock);
4677 memcpy(ps, &kps->channels, sizeof(*ps));
4678 mutex_unlock(&kps->lock);
2da29bcc 4679 return 0;
e0f63cb9
SY		 4680}
4681
4682static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4683{
0185604c 4684 int i;
09edea72
RK		 4685 struct kvm_pit *pit = kvm->arch.vpit;
4686
4687 mutex_lock(&pit->pit_state.lock);
34f3941c 4688 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4689 for (i = 0; i < 3; i++)
09edea72
RK		 4690 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4691 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4692 return 0;
e9f42757
BK		 4693}
4694
4695static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4696{
e9f42757
BK		 4697 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4698 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4699 sizeof(ps->channels));
4700 ps->flags = kvm->arch.vpit->pit_state.flags;
4701 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4702 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4703 return 0;
e9f42757
BK		 4704}
4705
4706static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4707{
2da29bcc 4708 int start = 0;
0185604c 4709 int i;
e9f42757 4710 u32 prev_legacy, cur_legacy;
09edea72
RK		 4711 struct kvm_pit *pit = kvm->arch.vpit;
4712
4713 mutex_lock(&pit->pit_state.lock);
4714 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4715 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4716 if (!prev_legacy && cur_legacy)
4717 start = 1;
09edea72
RK		 4718 memcpy(&pit->pit_state.channels, &ps->channels,
4719 sizeof(pit->pit_state.channels));
4720 pit->pit_state.flags = ps->flags;
0185604c 4721 for (i = 0; i < 3; i++)
09edea72 4722 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4723 start && i == 0);
09edea72 4724 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4725 return 0;
e0f63cb9
SY		 4726}
4727
52d939a0
MT		 4728static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4729 struct kvm_reinject_control *control)
4730{
71474e2f
RK		 4731 struct kvm_pit *pit = kvm->arch.vpit;
4732
71474e2f
RK		 4733 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4734 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4735 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4736 */
4737 mutex_lock(&pit->pit_state.lock);
4738 kvm_pit_set_reinject(pit, control->pit_reinject);
4739 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4740
52d939a0
MT		 4741 return 0;
4742}
4743
95d4c16c 4744/**
60c34612
TY		 4745 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4746 * @kvm: kvm instance
4747 * @log: slot id and address to which we copy the log
95d4c16c 4748 *
e108ff2f
PB		 4749 * Steps 1-4 below provide general overview of dirty page logging. See
4750 * kvm_get_dirty_log_protect() function description for additional details.
4751 *
4752 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4753 * always flush the TLB (step 4) even if previous step failed and the dirty
4754 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4755 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4756 * writes will be marked dirty for next log read.
95d4c16c 4757 *
60c34612
TY		 4758 * 1. Take a snapshot of the bit and clear it if needed.
4759 * 2. Write protect the corresponding page.
e108ff2f
PB		 4760 * 3. Copy the snapshot to the userspace.
4761 * 4. Flush TLB's if needed.
5bb064dc 4762 */
60c34612 4763int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4764{
8fe65a82 4765 bool flush = false;
e108ff2f 4766 int r;
5bb064dc 4767
79fac95e 4768 mutex_lock(&kvm->slots_lock);
5bb064dc 4769
88178fd4
KH		 4770 /*
4771 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4772 */
4773 if (kvm_x86_ops->flush_log_dirty)
4774 kvm_x86_ops->flush_log_dirty(kvm);
4775
8fe65a82 4776 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4777
4778 /*
4779 * All the TLBs can be flushed out of mmu lock, see the comments in
4780 * kvm_mmu_slot_remove_write_access().
4781 */
e108ff2f 4782 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4783 if (flush)
2a31b9db
PB		 4784 kvm_flush_remote_tlbs(kvm);
4785
4786 mutex_unlock(&kvm->slots_lock);
4787 return r;
4788}
4789
4790int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4791{
4792 bool flush = false;
4793 int r;
4794
4795 mutex_lock(&kvm->slots_lock);
4796
4797 /*
4798 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4799 */
4800 if (kvm_x86_ops->flush_log_dirty)
4801 kvm_x86_ops->flush_log_dirty(kvm);
4802
4803 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4804
4805 /*
4806 * All the TLBs can be flushed out of mmu lock, see the comments in
4807 * kvm_mmu_slot_remove_write_access().
4808 */
4809 lockdep_assert_held(&kvm->slots_lock);
4810 if (flush)
198c74f4
XG		 4811 kvm_flush_remote_tlbs(kvm);
4812
79fac95e 4813 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4814 return r;
4815}
4816
aa2fbe6d
YZ		 4817int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4818 bool line_status)
23d43cf9
CD		 4819{
4820 if (!irqchip_in_kernel(kvm))
4821 return -ENXIO;
4822
4823 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4824 irq_event->irq, irq_event->level,
4825 line_status);
23d43cf9
CD		 4826 return 0;
4827}
4828
e5d83c74
PB		 4829int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4830 struct kvm_enable_cap *cap)
90de4a18
NA		 4831{
4832 int r;
4833
4834 if (cap->flags)
4835 return -EINVAL;
4836
4837 switch (cap->cap) {
4838 case KVM_CAP_DISABLE_QUIRKS:
4839 kvm->arch.disabled_quirks = cap->args[0];
4840 r = 0;
4841 break;
49df6397
SR		 4842 case KVM_CAP_SPLIT_IRQCHIP: {
4843 mutex_lock(&kvm->lock);
b053b2ae
SR		 4844 r = -EINVAL;
4845 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4846 goto split_irqchip_unlock;
49df6397
SR		 4847 r = -EEXIST;
4848 if (irqchip_in_kernel(kvm))
4849 goto split_irqchip_unlock;
557abc40 4850 if (kvm->created_vcpus)
49df6397
SR		 4851 goto split_irqchip_unlock;
4852 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4853 if (r)
49df6397
SR		 4854 goto split_irqchip_unlock;
4855 /* Pairs with irqchip_in_kernel. */
4856 smp_wmb();
49776faf 4857 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4858 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4859 r = 0;
4860split_irqchip_unlock:
4861 mutex_unlock(&kvm->lock);
4862 break;
4863 }
37131313
RK		 4864 case KVM_CAP_X2APIC_API:
4865 r = -EINVAL;
4866 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4867 break;
4868
4869 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4870 kvm->arch.x2apic_format = true;
c519265f
RK		 4871 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4872 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4873
4874 r = 0;
4875 break;
4d5422ce
WL		 4876 case KVM_CAP_X86_DISABLE_EXITS:
4877 r = -EINVAL;
4878 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4879 break;
4880
4881 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4882 kvm_can_mwait_in_guest())
4883 kvm->arch.mwait_in_guest = true;
766d3571 4884 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4885 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4886 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4887 kvm->arch.pause_in_guest = true;
b5170063
WL		 4888 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4889 kvm->arch.cstate_in_guest = true;
4d5422ce
WL		 4890 r = 0;
4891 break;
6fbbde9a
DS		 4892 case KVM_CAP_MSR_PLATFORM_INFO:
4893 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4894 r = 0;
c4f55198
JM		 4895 break;
4896 case KVM_CAP_EXCEPTION_PAYLOAD:
4897 kvm->arch.exception_payload_enabled = cap->args[0];
4898 r = 0;
6fbbde9a 4899 break;
90de4a18
NA		 4900 default:
4901 r = -EINVAL;
4902 break;
4903 }
4904 return r;
4905}
4906
1fe779f8
CO		 4907long kvm_arch_vm_ioctl(struct file *filp,
4908 unsigned int ioctl, unsigned long arg)
4909{
4910 struct kvm *kvm = filp->private_data;
4911 void __user *argp = (void __user *)arg;
367e1319 4912 int r = -ENOTTY;
f0d66275
DH		 4913 /*
4914 * This union makes it completely explicit to gcc-3.x
4915 * that these two variables' stack usage should be
4916 * combined, not added together.
4917 */
4918 union {
4919 struct kvm_pit_state ps;
e9f42757 4920 struct kvm_pit_state2 ps2;
c5ff41ce 4921 struct kvm_pit_config pit_config;
f0d66275 4922 } u;
1fe779f8
CO		 4923
4924 switch (ioctl) {
4925 case KVM_SET_TSS_ADDR:
4926 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4927 break;
b927a3ce
SY		 4928 case KVM_SET_IDENTITY_MAP_ADDR: {
4929 u64 ident_addr;
4930
1af1ac91
DH		 4931 mutex_lock(&kvm->lock);
4932 r = -EINVAL;
4933 if (kvm->created_vcpus)
4934 goto set_identity_unlock;
b927a3ce 4935 r = -EFAULT;
0e96f31e 4936 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4937 goto set_identity_unlock;
b927a3ce 4938 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4939set_identity_unlock:
4940 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4941 break;
4942 }
1fe779f8
CO		 4943 case KVM_SET_NR_MMU_PAGES:
4944 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4945 break;
4946 case KVM_GET_NR_MMU_PAGES:
4947 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4948 break;
3ddea128 4949 case KVM_CREATE_IRQCHIP: {
3ddea128 4950 mutex_lock(&kvm->lock);
09941366 4951
3ddea128 4952 r = -EEXIST;
35e6eaa3 4953 if (irqchip_in_kernel(kvm))
3ddea128 4954 goto create_irqchip_unlock;
09941366 4955
3e515705 4956 r = -EINVAL;
557abc40 4957 if (kvm->created_vcpus)
3e515705 4958 goto create_irqchip_unlock;
09941366
RK		 4959
4960 r = kvm_pic_init(kvm);
4961 if (r)
3ddea128 4962 goto create_irqchip_unlock;
09941366
RK		 4963
4964 r = kvm_ioapic_init(kvm);
4965 if (r) {
09941366 4966 kvm_pic_destroy(kvm);
3ddea128 4967 goto create_irqchip_unlock;
09941366
RK		 4968 }
4969
399ec807
AK		 4970 r = kvm_setup_default_irq_routing(kvm);
4971 if (r) {
72bb2fcd 4972 kvm_ioapic_destroy(kvm);
09941366 4973 kvm_pic_destroy(kvm);
71ba994c 4974 goto create_irqchip_unlock;
399ec807 4975 }
49776faf 4976 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4977 smp_wmb();
49776faf 4978 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4979 create_irqchip_unlock:
4980 mutex_unlock(&kvm->lock);
1fe779f8 4981 break;
3ddea128 4982 }
7837699f 4983 case KVM_CREATE_PIT:
c5ff41ce
JK		 4984 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4985 goto create_pit;
4986 case KVM_CREATE_PIT2:
4987 r = -EFAULT;
4988 if (copy_from_user(&u.pit_config, argp,
4989 sizeof(struct kvm_pit_config)))
4990 goto out;
4991 create_pit:
250715a6 4992 mutex_lock(&kvm->lock);
269e05e4
AK		 4993 r = -EEXIST;
4994 if (kvm->arch.vpit)
4995 goto create_pit_unlock;
7837699f 4996 r = -ENOMEM;
c5ff41ce 4997 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4998 if (kvm->arch.vpit)
4999 r = 0;
269e05e4 5000 create_pit_unlock:
250715a6 5001 mutex_unlock(&kvm->lock);
7837699f 5002 break;
1fe779f8
CO		 5003 case KVM_GET_IRQCHIP: {
5004 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 5005 struct kvm_irqchip *chip;
1fe779f8 5006
ff5c2c03
SL		 5007 chip = memdup_user(argp, sizeof(*chip));
5008 if (IS_ERR(chip)) {
5009 r = PTR_ERR(chip);
1fe779f8 5010 goto out;
ff5c2c03
SL		 5011 }
5012
1fe779f8 5013 r = -ENXIO;
826da321 5014 if (!irqchip_kernel(kvm))
f0d66275
DH		 5015 goto get_irqchip_out;
5016 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 5017 if (r)
f0d66275 5018 goto get_irqchip_out;
1fe779f8 5019 r = -EFAULT;
0e96f31e 5020 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 5021 goto get_irqchip_out;
1fe779f8 5022 r = 0;
f0d66275
DH		 5023 get_irqchip_out:
5024 kfree(chip);
1fe779f8
CO		 5025 break;
5026 }
5027 case KVM_SET_IRQCHIP: {
5028 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 5029 struct kvm_irqchip *chip;
1fe779f8 5030
ff5c2c03
SL		 5031 chip = memdup_user(argp, sizeof(*chip));
5032 if (IS_ERR(chip)) {
5033 r = PTR_ERR(chip);
1fe779f8 5034 goto out;
ff5c2c03
SL		 5035 }
5036
1fe779f8 5037 r = -ENXIO;
826da321 5038 if (!irqchip_kernel(kvm))
f0d66275
DH		 5039 goto set_irqchip_out;
5040 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
f0d66275
DH		 5041 set_irqchip_out:
5042 kfree(chip);
1fe779f8
CO		 5043 break;
5044 }
e0f63cb9 5045 case KVM_GET_PIT: {
e0f63cb9 5046 r = -EFAULT;
f0d66275 5047 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 5048 goto out;
5049 r = -ENXIO;
5050 if (!kvm->arch.vpit)
5051 goto out;
f0d66275 5052 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 5053 if (r)
5054 goto out;
5055 r = -EFAULT;
f0d66275 5056 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 5057 goto out;
5058 r = 0;
5059 break;
5060 }
5061 case KVM_SET_PIT: {
e0f63cb9 5062 r = -EFAULT;
0e96f31e 5063 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 5064 goto out;
5065 r = -ENXIO;
5066 if (!kvm->arch.vpit)
5067 goto out;
f0d66275 5068 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 5069 break;
5070 }
e9f42757
BK		 5071 case KVM_GET_PIT2: {
5072 r = -ENXIO;
5073 if (!kvm->arch.vpit)
5074 goto out;
5075 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5076 if (r)
5077 goto out;
5078 r = -EFAULT;
5079 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5080 goto out;
5081 r = 0;
5082 break;
5083 }
5084 case KVM_SET_PIT2: {
5085 r = -EFAULT;
5086 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5087 goto out;
5088 r = -ENXIO;
5089 if (!kvm->arch.vpit)
5090 goto out;
5091 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 5092 break;
5093 }
52d939a0
MT		 5094 case KVM_REINJECT_CONTROL: {
5095 struct kvm_reinject_control control;
5096 r = -EFAULT;
5097 if (copy_from_user(&control, argp, sizeof(control)))
5098 goto out;
cad23e72
ML		 5099 r = -ENXIO;
5100 if (!kvm->arch.vpit)
5101 goto out;
52d939a0 5102 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 5103 break;
5104 }
d71ba788
PB		 5105 case KVM_SET_BOOT_CPU_ID:
5106 r = 0;
5107 mutex_lock(&kvm->lock);
557abc40 5108 if (kvm->created_vcpus)
d71ba788
PB		 5109 r = -EBUSY;
5110 else
5111 kvm->arch.bsp_vcpu_id = arg;
5112 mutex_unlock(&kvm->lock);
5113 break;
ffde22ac 5114 case KVM_XEN_HVM_CONFIG: {
51776043 5115 struct kvm_xen_hvm_config xhc;
ffde22ac 5116 r = -EFAULT;
51776043 5117 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 5118 goto out;
5119 r = -EINVAL;
51776043 5120 if (xhc.flags)
ffde22ac 5121 goto out;
51776043 5122 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 5123 r = 0;
5124 break;
5125 }
afbcf7ab 5126 case KVM_SET_CLOCK: {
afbcf7ab
GC		 5127 struct kvm_clock_data user_ns;
5128 u64 now_ns;
afbcf7ab
GC		 5129
5130 r = -EFAULT;
5131 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5132 goto out;
5133
5134 r = -EINVAL;
5135 if (user_ns.flags)
5136 goto out;
5137
5138 r = 0;
0bc48bea
RK		 5139 /*
5140 * TODO: userspace has to take care of races with VCPU_RUN, so
5141 * kvm_gen_update_masterclock() can be cut down to locked
5142 * pvclock_update_vm_gtod_copy().
5143 */
5144 kvm_gen_update_masterclock(kvm);
e891a32e 5145 now_ns = get_kvmclock_ns(kvm);
108b249c 5146 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 5147 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 5148 break;
5149 }
5150 case KVM_GET_CLOCK: {
afbcf7ab
GC		 5151 struct kvm_clock_data user_ns;
5152 u64 now_ns;
5153
e891a32e 5154 now_ns = get_kvmclock_ns(kvm);
108b249c 5155 user_ns.clock = now_ns;
e3fd9a93 5156 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 5157 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 5158
5159 r = -EFAULT;
5160 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5161 goto out;
5162 r = 0;
5163 break;
5164 }
5acc5c06
BS		 5165 case KVM_MEMORY_ENCRYPT_OP: {
5166 r = -ENOTTY;
5167 if (kvm_x86_ops->mem_enc_op)
5168 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5169 break;
5170 }
69eaedee
BS		 5171 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5172 struct kvm_enc_region region;
5173
5174 r = -EFAULT;
5175 if (copy_from_user(&region, argp, sizeof(region)))
5176 goto out;
5177
5178 r = -ENOTTY;
5179 if (kvm_x86_ops->mem_enc_reg_region)
5180 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5181 break;
5182 }
5183 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5184 struct kvm_enc_region region;
5185
5186 r = -EFAULT;
5187 if (copy_from_user(&region, argp, sizeof(region)))
5188 goto out;
5189
5190 r = -ENOTTY;
5191 if (kvm_x86_ops->mem_enc_unreg_region)
5192 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5193 break;
5194 }
faeb7833
RK		 5195 case KVM_HYPERV_EVENTFD: {
5196 struct kvm_hyperv_eventfd hvevfd;
5197
5198 r = -EFAULT;
5199 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5200 goto out;
5201 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5202 break;
5203 }
66bb8a06
EH		 5204 case KVM_SET_PMU_EVENT_FILTER:
5205 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5206 break;
1fe779f8 5207 default:
ad6260da 5208 r = -ENOTTY;
1fe779f8
CO		 5209 }
5210out:
5211 return r;
5212}
5213
a16b043c 5214static void kvm_init_msr_list(void)
043405e1 5215{
24c29b7a 5216 struct x86_pmu_capability x86_pmu;
043405e1 5217 u32 dummy[2];
7a5ee6ed 5218 unsigned i;
043405e1 5219
e2ada66e 5220 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
7a5ee6ed 5221 "Please update the fixed PMCs in msrs_to_saved_all[]");
24c29b7a
PB		 5222
5223 perf_get_x86_pmu_capability(&x86_pmu);
e2ada66e 5224
6cbee2b9
XL		 5225 num_msrs_to_save = 0;
5226 num_emulated_msrs = 0;
5227 num_msr_based_features = 0;
5228
7a5ee6ed
CQ		 5229 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5230 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
043405e1 5231 continue;
93c4adc7
PB		 5232
5233 /*
5234 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 5235 * to the guests in some cases.
93c4adc7 5236 */
7a5ee6ed 5237 switch (msrs_to_save_all[i]) {
93c4adc7 5238 case MSR_IA32_BNDCFGS:
503234b3 5239 if (!kvm_mpx_supported())
93c4adc7
PB		 5240 continue;
5241 break;
9dbe6cf9
PB		 5242 case MSR_TSC_AUX:
5243 if (!kvm_x86_ops->rdtscp_supported())
5244 continue;
5245 break;
bf8c55d8
CP		 5246 case MSR_IA32_RTIT_CTL:
5247 case MSR_IA32_RTIT_STATUS:
5248 if (!kvm_x86_ops->pt_supported())
5249 continue;
5250 break;
5251 case MSR_IA32_RTIT_CR3_MATCH:
5252 if (!kvm_x86_ops->pt_supported() ||
5253 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5254 continue;
5255 break;
5256 case MSR_IA32_RTIT_OUTPUT_BASE:
5257 case MSR_IA32_RTIT_OUTPUT_MASK:
5258 if (!kvm_x86_ops->pt_supported() ||
5259 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5260 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5261 continue;
5262 break;
5263 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5264 if (!kvm_x86_ops->pt_supported() ||
7a5ee6ed 5265 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
bf8c55d8
CP		 5266 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5267 continue;
5268 break;
cf05a67b 5269 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
7a5ee6ed 5270 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
24c29b7a
PB		 5271 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5272 continue;
5273 break;
cf05a67b 5274 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
7a5ee6ed 5275 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
24c29b7a
PB		 5276 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5277 continue;
bf8c55d8 5278 }
93c4adc7
PB		 5279 default:
5280 break;
5281 }
5282
7a5ee6ed 5283 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
043405e1 5284 }
62ef68bb 5285
7a5ee6ed
CQ		 5286 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5287 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs_all[i]))
bc226f07 5288 continue;
62ef68bb 5289
7a5ee6ed 5290 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
62ef68bb 5291 }
801e459a 5292
7a5ee6ed 5293 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
801e459a
TL		 5294 struct kvm_msr_entry msr;
5295
7a5ee6ed 5296 msr.index = msr_based_features_all[i];
66421c1e 5297 if (kvm_get_msr_feature(&msr))
801e459a
TL		 5298 continue;
5299
7a5ee6ed 5300 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
801e459a 5301 }
043405e1
CO		 5302}
5303
bda9020e
MT		 5304static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5305 const void *v)
bbd9b64e 5306{
70252a10
AK		 5307 int handled = 0;
5308 int n;
5309
5310 do {
5311 n = min(len, 8);
bce87cce 5312 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5313 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5314 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 5315 break;
5316 handled += n;
5317 addr += n;
5318 len -= n;
5319 v += n;
5320 } while (len);
bbd9b64e 5321
70252a10 5322 return handled;
bbd9b64e
CO		 5323}
5324
bda9020e 5325static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 5326{
70252a10
AK		 5327 int handled = 0;
5328 int n;
5329
5330 do {
5331 n = min(len, 8);
bce87cce 5332 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5333 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5334 addr, n, v))
5335 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5336 break;
e39d200f 5337 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5338 handled += n;
5339 addr += n;
5340 len -= n;
5341 v += n;
5342 } while (len);
bbd9b64e 5343
70252a10 5344 return handled;
bbd9b64e
CO		 5345}
5346
2dafc6c2
GN		 5347static void kvm_set_segment(struct kvm_vcpu *vcpu,
5348 struct kvm_segment *var, int seg)
5349{
5350 kvm_x86_ops->set_segment(vcpu, var, seg);
5351}
5352
5353void kvm_get_segment(struct kvm_vcpu *vcpu,
5354 struct kvm_segment *var, int seg)
5355{
5356 kvm_x86_ops->get_segment(vcpu, var, seg);
5357}
5358
54987b7a
PB		 5359gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5360 struct x86_exception *exception)
02f59dc9
JR		 5361{
5362 gpa_t t_gpa;
02f59dc9
JR		 5363
5364 BUG_ON(!mmu_is_nested(vcpu));
5365
5366 /* NPT walks are always user-walks */
5367 access |= PFERR_USER_MASK;
44dd3ffa 5368 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5369
5370 return t_gpa;
5371}
5372
ab9ae313
AK		 5373gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5374 struct x86_exception *exception)
1871c602
GN		 5375{
5376 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5377 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5378}
5379
ab9ae313
AK		 5380 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5381 struct x86_exception *exception)
1871c602
GN		 5382{
5383 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5384 access |= PFERR_FETCH_MASK;
ab9ae313 5385 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5386}
5387
ab9ae313
AK		 5388gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5389 struct x86_exception *exception)
1871c602
GN		 5390{
5391 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5392 access |= PFERR_WRITE_MASK;
ab9ae313 5393 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5394}
5395
5396/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5397gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5398 struct x86_exception *exception)
1871c602 5399{
ab9ae313 5400 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5401}
5402
5403static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5404 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5405 struct x86_exception *exception)
bbd9b64e
CO		 5406{
5407 void *data = val;
10589a46 5408 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5409
5410 while (bytes) {
14dfe855 5411 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5412 exception);
bbd9b64e 5413 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5414 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5415 int ret;
5416
bcc55cba 5417 if (gpa == UNMAPPED_GVA)
ab9ae313 5418 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5419 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5420 offset, toread);
10589a46 5421 if (ret < 0) {
c3cd7ffa 5422 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5423 goto out;
5424 }
bbd9b64e 5425
77c2002e
IE		 5426 bytes -= toread;
5427 data += toread;
5428 addr += toread;
bbd9b64e 5429 }
10589a46 5430out:
10589a46 5431 return r;
bbd9b64e 5432}
77c2002e 5433
1871c602 5434/* used for instruction fetching */
0f65dd70
AK		 5435static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5436 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5437 struct x86_exception *exception)
1871c602 5438{
0f65dd70 5439 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5440 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5441 unsigned offset;
5442 int ret;
0f65dd70 5443
44583cba
PB		 5444 /* Inline kvm_read_guest_virt_helper for speed. */
5445 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5446 exception);
5447 if (unlikely(gpa == UNMAPPED_GVA))
5448 return X86EMUL_PROPAGATE_FAULT;
5449
5450 offset = addr & (PAGE_SIZE-1);
5451 if (WARN_ON(offset + bytes > PAGE_SIZE))
5452 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5453 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5454 offset, bytes);
44583cba
PB		 5455 if (unlikely(ret < 0))
5456 return X86EMUL_IO_NEEDED;
5457
5458 return X86EMUL_CONTINUE;
1871c602
GN		 5459}
5460
ce14e868 5461int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5462 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5463 struct x86_exception *exception)
1871c602
GN		 5464{
5465 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5466
353c0956
PB		 5467 /*
5468 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5469 * is returned, but our callers are not ready for that and they blindly
5470 * call kvm_inject_page_fault. Ensure that they at least do not leak
5471 * uninitialized kernel stack memory into cr2 and error code.
5472 */
5473 memset(exception, 0, sizeof(*exception));
1871c602 5474 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5475 exception);
1871c602 5476}
064aea77 5477EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5478
ce14e868
PB		 5479static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5480 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5481 struct x86_exception *exception, bool system)
1871c602 5482{
0f65dd70 5483 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5484 u32 access = 0;
5485
5486 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5487 access |= PFERR_USER_MASK;
5488
5489 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5490}
5491
7a036a6f
RK		 5492static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5493 unsigned long addr, void *val, unsigned int bytes)
5494{
5495 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5496 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5497
5498 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5499}
5500
ce14e868
PB		 5501static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5502 struct kvm_vcpu *vcpu, u32 access,
5503 struct x86_exception *exception)
77c2002e
IE		 5504{
5505 void *data = val;
5506 int r = X86EMUL_CONTINUE;
5507
5508 while (bytes) {
14dfe855 5509 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5510 access,
ab9ae313 5511 exception);
77c2002e
IE		 5512 unsigned offset = addr & (PAGE_SIZE-1);
5513 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5514 int ret;
5515
bcc55cba 5516 if (gpa == UNMAPPED_GVA)
ab9ae313 5517 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5518 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5519 if (ret < 0) {
c3cd7ffa 5520 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5521 goto out;
5522 }
5523
5524 bytes -= towrite;
5525 data += towrite;
5526 addr += towrite;
5527 }
5528out:
5529 return r;
5530}
ce14e868
PB		 5531
5532static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5533 unsigned int bytes, struct x86_exception *exception,
5534 bool system)
ce14e868
PB		 5535{
5536 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5537 u32 access = PFERR_WRITE_MASK;
5538
5539 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5540 access |= PFERR_USER_MASK;
ce14e868
PB		 5541
5542 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5543 access, exception);
ce14e868
PB		 5544}
5545
5546int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5547 unsigned int bytes, struct x86_exception *exception)
5548{
c595ceee
PB		 5549 /* kvm_write_guest_virt_system can pull in tons of pages. */
5550 vcpu->arch.l1tf_flush_l1d = true;
5551
541ab2ae
FH		 5552 /*
5553 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5554 * is returned, but our callers are not ready for that and they blindly
5555 * call kvm_inject_page_fault. Ensure that they at least do not leak
5556 * uninitialized kernel stack memory into cr2 and error code.
5557 */
5558 memset(exception, 0, sizeof(*exception));
ce14e868
PB		 5559 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5560 PFERR_WRITE_MASK, exception);
5561}
6a4d7550 5562EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5563
082d06ed
WL		 5564int handle_ud(struct kvm_vcpu *vcpu)
5565{
b3dc0695 5566 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6c86eedc 5567 int emul_type = EMULTYPE_TRAP_UD;
6c86eedc
WL		 5568 char sig[5]; /* ud2; .ascii "kvm" */
5569 struct x86_exception e;
5570
5571 if (force_emulation_prefix &&
3c9fa24c
PB		 5572 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5573 sig, sizeof(sig), &e) == 0 &&
b3dc0695 5574 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6c86eedc 5575 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
b4000606 5576 emul_type = EMULTYPE_TRAP_UD_FORCED;
6c86eedc 5577 }
082d06ed 5578
60fc3d02 5579 return kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5580}
5581EXPORT_SYMBOL_GPL(handle_ud);
5582
0f89b207
TL		 5583static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5584 gpa_t gpa, bool write)
5585{
5586 /* For APIC access vmexit */
5587 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5588 return 1;
5589
5590 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5591 trace_vcpu_match_mmio(gva, gpa, write, true);
5592 return 1;
5593 }
5594
5595 return 0;
5596}
5597
af7cc7d1
XG		 5598static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5599 gpa_t *gpa, struct x86_exception *exception,
5600 bool write)
5601{
97d64b78
AK		 5602 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5603 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5604
be94f6b7
HH		 5605 /*
5606 * currently PKRU is only applied to ept enabled guest so
5607 * there is no pkey in EPT page table for L1 guest or EPT
5608 * shadow page table for L2 guest.
5609 */
97d64b78 5610 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5611 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
871bd034 5612 vcpu->arch.mmio_access, 0, access)) {
bebb106a
XG		 5613 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5614 (gva & (PAGE_SIZE - 1));
4f022648 5615 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5616 return 1;
5617 }
5618
af7cc7d1
XG		 5619 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5620
5621 if (*gpa == UNMAPPED_GVA)
5622 return -1;
5623
0f89b207 5624 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5625}
5626
3200f405 5627int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5628 const void *val, int bytes)
bbd9b64e
CO		 5629{
5630 int ret;
5631
54bf36aa 5632 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5633 if (ret < 0)
bbd9b64e 5634 return 0;
0eb05bf2 5635 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5636 return 1;
5637}
5638
77d197b2
XG		 5639struct read_write_emulator_ops {
5640 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5641 int bytes);
5642 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5643 void *val, int bytes);
5644 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5645 int bytes, void *val);
5646 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5647 void *val, int bytes);
5648 bool write;
5649};
5650
5651static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5652{
5653 if (vcpu->mmio_read_completed) {
77d197b2 5654 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5655 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5656 vcpu->mmio_read_completed = 0;
5657 return 1;
5658 }
5659
5660 return 0;
5661}
5662
5663static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5664 void *val, int bytes)
5665{
54bf36aa 5666 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5667}
5668
5669static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5670 void *val, int bytes)
5671{
5672 return emulator_write_phys(vcpu, gpa, val, bytes);
5673}
5674
5675static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5676{
e39d200f 5677 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5678 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5679}
5680
5681static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5682 void *val, int bytes)
5683{
e39d200f 5684 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5685 return X86EMUL_IO_NEEDED;
5686}
5687
5688static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5689 void *val, int bytes)
5690{
f78146b0
AK		 5691 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5692
87da7e66 5693 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5694 return X86EMUL_CONTINUE;
5695}
5696
0fbe9b0b 5697static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5698 .read_write_prepare = read_prepare,
5699 .read_write_emulate = read_emulate,
5700 .read_write_mmio = vcpu_mmio_read,
5701 .read_write_exit_mmio = read_exit_mmio,
5702};
5703
0fbe9b0b 5704static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5705 .read_write_emulate = write_emulate,
5706 .read_write_mmio = write_mmio,
5707 .read_write_exit_mmio = write_exit_mmio,
5708 .write = true,
5709};
5710
22388a3c
XG		 5711static int emulator_read_write_onepage(unsigned long addr, void *val,
5712 unsigned int bytes,
5713 struct x86_exception *exception,
5714 struct kvm_vcpu *vcpu,
0fbe9b0b 5715 const struct read_write_emulator_ops *ops)
bbd9b64e 5716{
af7cc7d1
XG		 5717 gpa_t gpa;
5718 int handled, ret;
22388a3c 5719 bool write = ops->write;
f78146b0 5720 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5721 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5722
5723 /*
5724 * If the exit was due to a NPF we may already have a GPA.
5725 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5726 * Note, this cannot be used on string operations since string
5727 * operation using rep will only have the initial GPA from the NPF
5728 * occurred.
5729 */
5730 if (vcpu->arch.gpa_available &&
5731 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5732 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5733 gpa = vcpu->arch.gpa_val;
5734 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5735 } else {
5736 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5737 if (ret < 0)
5738 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5739 }
10589a46 5740
618232e2 5741 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5742 return X86EMUL_CONTINUE;
5743
bbd9b64e
CO		 5744 /*
5745 * Is this MMIO handled locally?
5746 */
22388a3c 5747 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5748 if (handled == bytes)
bbd9b64e 5749 return X86EMUL_CONTINUE;
bbd9b64e 5750
70252a10
AK		 5751 gpa += handled;
5752 bytes -= handled;
5753 val += handled;
5754
87da7e66
XG		 5755 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5756 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5757 frag->gpa = gpa;
5758 frag->data = val;
5759 frag->len = bytes;
f78146b0 5760 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5761}
5762
52eb5a6d
XL		 5763static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5764 unsigned long addr,
22388a3c
XG		 5765 void *val, unsigned int bytes,
5766 struct x86_exception *exception,
0fbe9b0b 5767 const struct read_write_emulator_ops *ops)
bbd9b64e 5768{
0f65dd70 5769 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5770 gpa_t gpa;
5771 int rc;
5772
5773 if (ops->read_write_prepare &&
5774 ops->read_write_prepare(vcpu, val, bytes))
5775 return X86EMUL_CONTINUE;
5776
5777 vcpu->mmio_nr_fragments = 0;
0f65dd70 5778
bbd9b64e
CO		 5779 /* Crossing a page boundary? */
5780 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5781 int now;
bbd9b64e
CO		 5782
5783 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5784 rc = emulator_read_write_onepage(addr, val, now, exception,
5785 vcpu, ops);
5786
bbd9b64e
CO		 5787 if (rc != X86EMUL_CONTINUE)
5788 return rc;
5789 addr += now;
bac15531
NA		 5790 if (ctxt->mode != X86EMUL_MODE_PROT64)
5791 addr = (u32)addr;
bbd9b64e
CO		 5792 val += now;
5793 bytes -= now;
5794 }
22388a3c 5795
f78146b0
AK		 5796 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5797 vcpu, ops);
5798 if (rc != X86EMUL_CONTINUE)
5799 return rc;
5800
5801 if (!vcpu->mmio_nr_fragments)
5802 return rc;
5803
5804 gpa = vcpu->mmio_fragments[0].gpa;
5805
5806 vcpu->mmio_needed = 1;
5807 vcpu->mmio_cur_fragment = 0;
5808
87da7e66 5809 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5810 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5811 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5812 vcpu->run->mmio.phys_addr = gpa;
5813
5814 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5815}
5816
5817static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5818 unsigned long addr,
5819 void *val,
5820 unsigned int bytes,
5821 struct x86_exception *exception)
5822{
5823 return emulator_read_write(ctxt, addr, val, bytes,
5824 exception, &read_emultor);
5825}
5826
52eb5a6d 5827static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5828 unsigned long addr,
5829 const void *val,
5830 unsigned int bytes,
5831 struct x86_exception *exception)
5832{
5833 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5834 exception, &write_emultor);
bbd9b64e 5835}
bbd9b64e 5836
daea3e73
AK		 5837#define CMPXCHG_TYPE(t, ptr, old, new) \
5838 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5839
5840#ifdef CONFIG_X86_64
5841# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5842#else
5843# define CMPXCHG64(ptr, old, new) \
9749a6c0 5844 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5845#endif
5846
0f65dd70
AK		 5847static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5848 unsigned long addr,
bbd9b64e
CO		 5849 const void *old,
5850 const void *new,
5851 unsigned int bytes,
0f65dd70 5852 struct x86_exception *exception)
bbd9b64e 5853{
42e35f80 5854 struct kvm_host_map map;
0f65dd70 5855 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73 5856 gpa_t gpa;
daea3e73
AK		 5857 char *kaddr;
5858 bool exchanged;
2bacc55c 5859
daea3e73
AK		 5860 /* guests cmpxchg8b have to be emulated atomically */
5861 if (bytes > 8 || (bytes & (bytes - 1)))
5862 goto emul_write;
10589a46 5863
daea3e73 5864 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5865
daea3e73
AK		 5866 if (gpa == UNMAPPED_GVA ||
5867 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5868 goto emul_write;
2bacc55c 5869
daea3e73
AK		 5870 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5871 goto emul_write;
72dc67a6 5872
42e35f80 5873 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
c19b8bd6 5874 goto emul_write;
72dc67a6 5875
42e35f80
KA		 5876 kaddr = map.hva + offset_in_page(gpa);
5877
daea3e73
AK		 5878 switch (bytes) {
5879 case 1:
5880 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5881 break;
5882 case 2:
5883 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5884 break;
5885 case 4:
5886 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5887 break;
5888 case 8:
5889 exchanged = CMPXCHG64(kaddr, old, new);
5890 break;
5891 default:
5892 BUG();
2bacc55c 5893 }
42e35f80
KA		 5894
5895 kvm_vcpu_unmap(vcpu, &map, true);
daea3e73
AK		 5896
5897 if (!exchanged)
5898 return X86EMUL_CMPXCHG_FAILED;
5899
0eb05bf2 5900 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5901
5902 return X86EMUL_CONTINUE;
4a5f48f6 5903
3200f405 5904emul_write:
daea3e73 5905 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5906
0f65dd70 5907 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5908}
5909
cf8f70bf
GN		 5910static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5911{
cbfc6c91 5912 int r = 0, i;
cf8f70bf 5913
cbfc6c91
WL		 5914 for (i = 0; i < vcpu->arch.pio.count; i++) {
5915 if (vcpu->arch.pio.in)
5916 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5917 vcpu->arch.pio.size, pd);
5918 else
5919 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5920 vcpu->arch.pio.port, vcpu->arch.pio.size,
5921 pd);
5922 if (r)
5923 break;
5924 pd += vcpu->arch.pio.size;
5925 }
cf8f70bf
GN		 5926 return r;
5927}
5928
6f6fbe98
XG		 5929static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5930 unsigned short port, void *val,
5931 unsigned int count, bool in)
cf8f70bf 5932{
cf8f70bf 5933 vcpu->arch.pio.port = port;
6f6fbe98 5934 vcpu->arch.pio.in = in;
7972995b 5935 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5936 vcpu->arch.pio.size = size;
5937
5938 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5939 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5940 return 1;
5941 }
5942
5943 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5944 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5945 vcpu->run->io.size = size;
5946 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5947 vcpu->run->io.count = count;
5948 vcpu->run->io.port = port;
5949
5950 return 0;
5951}
5952
6f6fbe98
XG		 5953static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5954 int size, unsigned short port, void *val,
5955 unsigned int count)
cf8f70bf 5956{
ca1d4a9e 5957 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5958 int ret;
ca1d4a9e 5959
6f6fbe98
XG		 5960 if (vcpu->arch.pio.count)
5961 goto data_avail;
cf8f70bf 5962
cbfc6c91
WL		 5963 memset(vcpu->arch.pio_data, 0, size * count);
5964
6f6fbe98
XG		 5965 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5966 if (ret) {
5967data_avail:
5968 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5969 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5970 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5971 return 1;
5972 }
5973
cf8f70bf
GN		 5974 return 0;
5975}
5976
6f6fbe98
XG		 5977static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5978 int size, unsigned short port,
5979 const void *val, unsigned int count)
5980{
5981 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5982
5983 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5984 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5985 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5986}
5987
bbd9b64e
CO		 5988static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5989{
5990 return kvm_x86_ops->get_segment_base(vcpu, seg);
5991}
5992
3cb16fe7 5993static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5994{
3cb16fe7 5995 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5996}
5997
ae6a2375 5998static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5999{
6000 if (!need_emulate_wbinvd(vcpu))
6001 return X86EMUL_CONTINUE;
6002
6003 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 6004 int cpu = get_cpu();
6005
6006 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6007 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6008 wbinvd_ipi, NULL, 1);
2eec7343 6009 put_cpu();
f5f48ee1 6010 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 6011 } else
6012 wbinvd();
f5f48ee1
SY		 6013 return X86EMUL_CONTINUE;
6014}
5cb56059
JS		 6015
6016int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6017{
6affcbed
KH		 6018 kvm_emulate_wbinvd_noskip(vcpu);
6019 return kvm_skip_emulated_instruction(vcpu);
5cb56059 6020}
f5f48ee1
SY		 6021EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6022
5cb56059
JS		 6023
6024
bcaf5cc5
AK		 6025static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6026{
5cb56059 6027 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 6028}
6029
52eb5a6d
XL		 6030static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6031 unsigned long *dest)
bbd9b64e 6032{
16f8a6f9 6033 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 6034}
6035
52eb5a6d
XL		 6036static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6037 unsigned long value)
bbd9b64e 6038{
338dbc97 6039
717746e3 6040 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 6041}
6042
52a46617 6043static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 6044{
52a46617 6045 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 6046}
6047
717746e3 6048static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 6049{
717746e3 6050 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 6051 unsigned long value;
6052
6053 switch (cr) {
6054 case 0:
6055 value = kvm_read_cr0(vcpu);
6056 break;
6057 case 2:
6058 value = vcpu->arch.cr2;
6059 break;
6060 case 3:
9f8fe504 6061 value = kvm_read_cr3(vcpu);
52a46617
GN		 6062 break;
6063 case 4:
6064 value = kvm_read_cr4(vcpu);
6065 break;
6066 case 8:
6067 value = kvm_get_cr8(vcpu);
6068 break;
6069 default:
a737f256 6070 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 6071 return 0;
6072 }
6073
6074 return value;
6075}
6076
717746e3 6077static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 6078{
717746e3 6079 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 6080 int res = 0;
6081
52a46617
GN		 6082 switch (cr) {
6083 case 0:
49a9b07e 6084 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 6085 break;
6086 case 2:
6087 vcpu->arch.cr2 = val;
6088 break;
6089 case 3:
2390218b 6090 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 6091 break;
6092 case 4:
a83b29c6 6093 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 6094 break;
6095 case 8:
eea1cff9 6096 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 6097 break;
6098 default:
a737f256 6099 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 6100 res = -1;
52a46617 6101 }
0f12244f
GN		 6102
6103 return res;
52a46617
GN		 6104}
6105
717746e3 6106static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 6107{
717746e3 6108 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 6109}
6110
4bff1e86 6111static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 6112{
4bff1e86 6113 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 6114}
6115
4bff1e86 6116static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 6117{
4bff1e86 6118 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 6119}
6120
1ac9d0cf
AK		 6121static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6122{
6123 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6124}
6125
6126static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6127{
6128 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6129}
6130
4bff1e86
AK		 6131static unsigned long emulator_get_cached_segment_base(
6132 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 6133{
4bff1e86 6134 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 6135}
6136
1aa36616
AK		 6137static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6138 struct desc_struct *desc, u32 *base3,
6139 int seg)
2dafc6c2
GN		 6140{
6141 struct kvm_segment var;
6142
4bff1e86 6143 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 6144 *selector = var.selector;
2dafc6c2 6145
378a8b09
GN		 6146 if (var.unusable) {
6147 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 6148 if (base3)
6149 *base3 = 0;
2dafc6c2 6150 return false;
378a8b09 6151 }
2dafc6c2
GN		 6152
6153 if (var.g)
6154 var.limit >>= 12;
6155 set_desc_limit(desc, var.limit);
6156 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 6157#ifdef CONFIG_X86_64
6158 if (base3)
6159 *base3 = var.base >> 32;
6160#endif
2dafc6c2
GN		 6161 desc->type = var.type;
6162 desc->s = var.s;
6163 desc->dpl = var.dpl;
6164 desc->p = var.present;
6165 desc->avl = var.avl;
6166 desc->l = var.l;
6167 desc->d = var.db;
6168 desc->g = var.g;
6169
6170 return true;
6171}
6172
1aa36616
AK		 6173static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6174 struct desc_struct *desc, u32 base3,
6175 int seg)
2dafc6c2 6176{
4bff1e86 6177 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 6178 struct kvm_segment var;
6179
1aa36616 6180 var.selector = selector;
2dafc6c2 6181 var.base = get_desc_base(desc);
5601d05b
GN		 6182#ifdef CONFIG_X86_64
6183 var.base |= ((u64)base3) << 32;
6184#endif
2dafc6c2
GN		 6185 var.limit = get_desc_limit(desc);
6186 if (desc->g)
6187 var.limit = (var.limit << 12) | 0xfff;
6188 var.type = desc->type;
2dafc6c2
GN		 6189 var.dpl = desc->dpl;
6190 var.db = desc->d;
6191 var.s = desc->s;
6192 var.l = desc->l;
6193 var.g = desc->g;
6194 var.avl = desc->avl;
6195 var.present = desc->p;
6196 var.unusable = !var.present;
6197 var.padding = 0;
6198
6199 kvm_set_segment(vcpu, &var, seg);
6200 return;
6201}
6202
717746e3
AK		 6203static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6204 u32 msr_index, u64 *pdata)
6205{
f20935d8 6206 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
717746e3
AK		 6207}
6208
6209static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6210 u32 msr_index, u64 data)
6211{
f20935d8 6212 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
717746e3
AK		 6213}
6214
64d60670
PB		 6215static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6216{
6217 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6218
6219 return vcpu->arch.smbase;
6220}
6221
6222static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6223{
6224 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6225
6226 vcpu->arch.smbase = smbase;
6227}
6228
67f4d428
NA		 6229static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6230 u32 pmc)
6231{
98ff80f5 6232 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 6233}
6234
222d21aa
AK		 6235static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6236 u32 pmc, u64 *pdata)
6237{
c6702c9d 6238 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 6239}
6240
6c3287f7
AK		 6241static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6242{
6243 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6244}
6245
2953538e 6246static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 6247 struct x86_instruction_info *info,
c4f035c6
AK		 6248 enum x86_intercept_stage stage)
6249{
2953538e 6250 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 6251}
6252
e911eb3b
YZ		 6253static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6254 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 6255{
e911eb3b 6256 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 6257}
6258
5ae78e95
SC		 6259static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6260{
6261 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6262}
6263
6264static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6265{
6266 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6267}
6268
6269static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6270{
6271 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6272}
6273
dd856efa
AK		 6274static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6275{
6276 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6277}
6278
6279static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6280{
6281 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6282}
6283
801806d9
NA		 6284static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6285{
6286 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6287}
6288
6ed071f0
LP		 6289static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6290{
6291 return emul_to_vcpu(ctxt)->arch.hflags;
6292}
6293
6294static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6295{
c5833c7a 6296 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 6297}
6298
ed19321f
SC		 6299static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6300 const char *smstate)
0234bf88 6301{
ed19321f 6302 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 6303}
6304
c5833c7a
SC		 6305static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6306{
6307 kvm_smm_changed(emul_to_vcpu(ctxt));
6308}
6309
02d4160f
VK		 6310static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6311{
6312 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6313}
6314
0225fb50 6315static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 6316 .read_gpr = emulator_read_gpr,
6317 .write_gpr = emulator_write_gpr,
ce14e868
PB		 6318 .read_std = emulator_read_std,
6319 .write_std = emulator_write_std,
7a036a6f 6320 .read_phys = kvm_read_guest_phys_system,
1871c602 6321 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 6322 .read_emulated = emulator_read_emulated,
6323 .write_emulated = emulator_write_emulated,
6324 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 6325 .invlpg = emulator_invlpg,
cf8f70bf
GN		 6326 .pio_in_emulated = emulator_pio_in_emulated,
6327 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 6328 .get_segment = emulator_get_segment,
6329 .set_segment = emulator_set_segment,
5951c442 6330 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 6331 .get_gdt = emulator_get_gdt,
160ce1f1 6332 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 6333 .set_gdt = emulator_set_gdt,
6334 .set_idt = emulator_set_idt,
52a46617
GN		 6335 .get_cr = emulator_get_cr,
6336 .set_cr = emulator_set_cr,
9c537244 6337 .cpl = emulator_get_cpl,
35aa5375
GN		 6338 .get_dr = emulator_get_dr,
6339 .set_dr = emulator_set_dr,
64d60670
PB		 6340 .get_smbase = emulator_get_smbase,
6341 .set_smbase = emulator_set_smbase,
717746e3
AK		 6342 .set_msr = emulator_set_msr,
6343 .get_msr = emulator_get_msr,
67f4d428 6344 .check_pmc = emulator_check_pmc,
222d21aa 6345 .read_pmc = emulator_read_pmc,
6c3287f7 6346 .halt = emulator_halt,
bcaf5cc5 6347 .wbinvd = emulator_wbinvd,
d6aa1000 6348 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6349 .intercept = emulator_intercept,
bdb42f5a 6350 .get_cpuid = emulator_get_cpuid,
5ae78e95
SC		 6351 .guest_has_long_mode = emulator_guest_has_long_mode,
6352 .guest_has_movbe = emulator_guest_has_movbe,
6353 .guest_has_fxsr = emulator_guest_has_fxsr,
801806d9 6354 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6355 .get_hflags = emulator_get_hflags,
6356 .set_hflags = emulator_set_hflags,
0234bf88 6357 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6358 .post_leave_smm = emulator_post_leave_smm,
02d4160f 6359 .set_xcr = emulator_set_xcr,
bbd9b64e
CO		 6360};
6361
95cb2295
GN		 6362static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6363{
37ccdcbe 6364 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6365 /*
6366 * an sti; sti; sequence only disable interrupts for the first
6367 * instruction. So, if the last instruction, be it emulated or
6368 * not, left the system with the INT_STI flag enabled, it
6369 * means that the last instruction is an sti. We should not
6370 * leave the flag on in this case. The same goes for mov ss
6371 */
37ccdcbe
PB		 6372 if (int_shadow & mask)
6373 mask = 0;
6addfc42 6374 if (unlikely(int_shadow || mask)) {
95cb2295 6375 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6376 if (!mask)
6377 kvm_make_request(KVM_REQ_EVENT, vcpu);
6378 }
95cb2295
GN		 6379}
6380
ef54bcfe 6381static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6382{
6383 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6384 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6385 return kvm_propagate_fault(vcpu, &ctxt->exception);
6386
6387 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6388 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6389 ctxt->exception.error_code);
54b8486f 6390 else
da9cb575 6391 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6392 return false;
54b8486f
GN		 6393}
6394
8ec4722d
MG		 6395static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6396{
adf52235 6397 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6398 int cs_db, cs_l;
6399
8ec4722d
MG		 6400 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6401
adf52235 6402 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6403 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6404
adf52235
TY		 6405 ctxt->eip = kvm_rip_read(vcpu);
6406 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6407 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6408 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6409 cs_db ? X86EMUL_MODE_PROT32 :
6410 X86EMUL_MODE_PROT16;
a584539b 6411 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6412 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6413 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6414
dd856efa 6415 init_decode_cache(ctxt);
7ae441ea 6416 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6417}
6418
9497e1f2 6419void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6420{
9d74191a 6421 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6422 int ret;
6423
6424 init_emulate_ctxt(vcpu);
6425
9dac77fa
AK		 6426 ctxt->op_bytes = 2;
6427 ctxt->ad_bytes = 2;
6428 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6429 ret = emulate_int_real(ctxt, irq);
63995653 6430
9497e1f2
SC		 6431 if (ret != X86EMUL_CONTINUE) {
6432 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6433 } else {
6434 ctxt->eip = ctxt->_eip;
6435 kvm_rip_write(vcpu, ctxt->eip);
6436 kvm_set_rflags(vcpu, ctxt->eflags);
6437 }
63995653
MG		 6438}
6439EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6440
e2366171 6441static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6442{
6d77dbfc
GN		 6443 ++vcpu->stat.insn_emulation_fail;
6444 trace_kvm_emulate_insn_failed(vcpu);
e2366171 6445
42cbf068
SC		 6446 if (emulation_type & EMULTYPE_VMWARE_GP) {
6447 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
60fc3d02 6448 return 1;
42cbf068 6449 }
e2366171 6450
738fece4
SC		 6451 if (emulation_type & EMULTYPE_SKIP) {
6452 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6453 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6454 vcpu->run->internal.ndata = 0;
60fc3d02 6455 return 0;
738fece4
SC		 6456 }
6457
22da61c9
SC		 6458 kvm_queue_exception(vcpu, UD_VECTOR);
6459
a2b9e6c1 6460 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6461 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6462 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6463 vcpu->run->internal.ndata = 0;
60fc3d02 6464 return 0;
fc3a9157 6465 }
e2366171 6466
60fc3d02 6467 return 1;
6d77dbfc
GN		 6468}
6469
736c291c 6470static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
991eebf9
GN		 6471 bool write_fault_to_shadow_pgtable,
6472 int emulation_type)
a6f177ef 6473{
736c291c 6474 gpa_t gpa = cr2_or_gpa;
ba049e93 6475 kvm_pfn_t pfn;
a6f177ef 6476
384bf221 6477 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6478 return false;
6479
6c3dfeb6
SC		 6480 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6481 return false;
6482
44dd3ffa 6483 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6484 /*
6485 * Write permission should be allowed since only
6486 * write access need to be emulated.
6487 */
736c291c 6488 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
a6f177ef 6489
95b3cf69
XG		 6490 /*
6491 * If the mapping is invalid in guest, let cpu retry
6492 * it to generate fault.
6493 */
6494 if (gpa == UNMAPPED_GVA)
6495 return true;
6496 }
a6f177ef 6497
8e3d9d06
XG		 6498 /*
6499 * Do not retry the unhandleable instruction if it faults on the
6500 * readonly host memory, otherwise it will goto a infinite loop:
6501 * retry instruction -> write #PF -> emulation fail -> retry
6502 * instruction -> ...
6503 */
6504 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6505
6506 /*
6507 * If the instruction failed on the error pfn, it can not be fixed,
6508 * report the error to userspace.
6509 */
6510 if (is_error_noslot_pfn(pfn))
6511 return false;
6512
6513 kvm_release_pfn_clean(pfn);
6514
6515 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6516 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6517 unsigned int indirect_shadow_pages;
6518
6519 spin_lock(&vcpu->kvm->mmu_lock);
6520 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6521 spin_unlock(&vcpu->kvm->mmu_lock);
6522
6523 if (indirect_shadow_pages)
6524 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6525
a6f177ef 6526 return true;
8e3d9d06 6527 }
a6f177ef 6528
95b3cf69
XG		 6529 /*
6530 * if emulation was due to access to shadowed page table
6531 * and it failed try to unshadow page and re-enter the
6532 * guest to let CPU execute the instruction.
6533 */
6534 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6535
6536 /*
6537 * If the access faults on its page table, it can not
6538 * be fixed by unprotecting shadow page and it should
6539 * be reported to userspace.
6540 */
6541 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6542}
6543
1cb3f3ae 6544static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
736c291c 6545 gpa_t cr2_or_gpa, int emulation_type)
1cb3f3ae
XG		 6546{
6547 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
736c291c 6548 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
1cb3f3ae
XG		 6549
6550 last_retry_eip = vcpu->arch.last_retry_eip;
6551 last_retry_addr = vcpu->arch.last_retry_addr;
6552
6553 /*
6554 * If the emulation is caused by #PF and it is non-page_table
6555 * writing instruction, it means the VM-EXIT is caused by shadow
6556 * page protected, we can zap the shadow page and retry this
6557 * instruction directly.
6558 *
6559 * Note: if the guest uses a non-page-table modifying instruction
6560 * on the PDE that points to the instruction, then we will unmap
6561 * the instruction and go to an infinite loop. So, we cache the
6562 * last retried eip and the last fault address, if we meet the eip
6563 * and the address again, we can break out of the potential infinite
6564 * loop.
6565 */
6566 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6567
384bf221 6568 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6569 return false;
6570
6c3dfeb6
SC		 6571 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6572 return false;
6573
1cb3f3ae
XG		 6574 if (x86_page_table_writing_insn(ctxt))
6575 return false;
6576
736c291c 6577 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
1cb3f3ae
XG		 6578 return false;
6579
6580 vcpu->arch.last_retry_eip = ctxt->eip;
736c291c 6581 vcpu->arch.last_retry_addr = cr2_or_gpa;
1cb3f3ae 6582
44dd3ffa 6583 if (!vcpu->arch.mmu->direct_map)
736c291c 6584 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
1cb3f3ae 6585
22368028 6586 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6587
6588 return true;
6589}
6590
716d51ab
GN		 6591static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6592static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6593
64d60670 6594static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6595{
64d60670 6596 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6597 /* This is a good place to trace that we are exiting SMM. */
6598 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6599
c43203ca
PB		 6600 /* Process a latched INIT or SMI, if any. */
6601 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6602 }
699023e2
PB		 6603
6604 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6605}
6606
4a1e10d5
PB		 6607static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6608 unsigned long *db)
6609{
6610 u32 dr6 = 0;
6611 int i;
6612 u32 enable, rwlen;
6613
6614 enable = dr7;
6615 rwlen = dr7 >> 16;
6616 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6617 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6618 dr6 |= (1 << i);
6619 return dr6;
6620}
6621
120c2c4f 6622static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
663f4c61
PB		 6623{
6624 struct kvm_run *kvm_run = vcpu->run;
6625
c8401dda
PB		 6626 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6627 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6628 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6629 kvm_run->debug.arch.exception = DB_VECTOR;
6630 kvm_run->exit_reason = KVM_EXIT_DEBUG;
60fc3d02 6631 return 0;
663f4c61 6632 }
120c2c4f 6633 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
60fc3d02 6634 return 1;
663f4c61
PB		 6635}
6636
6affcbed
KH		 6637int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6638{
6639 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
f8ea7c60 6640 int r;
6affcbed 6641
f8ea7c60 6642 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
60fc3d02 6643 if (unlikely(!r))
f8ea7c60 6644 return 0;
c8401dda
PB		 6645
6646 /*
6647 * rflags is the old, "raw" value of the flags. The new value has
6648 * not been saved yet.
6649 *
6650 * This is correct even for TF set by the guest, because "the
6651 * processor will not generate this exception after the instruction
6652 * that sets the TF flag".
6653 */
6654 if (unlikely(rflags & X86_EFLAGS_TF))
120c2c4f 6655 r = kvm_vcpu_do_singlestep(vcpu);
60fc3d02 6656 return r;
6affcbed
KH		 6657}
6658EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6659
4a1e10d5
PB		 6660static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6661{
4a1e10d5
PB		 6662 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6663 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6664 struct kvm_run *kvm_run = vcpu->run;
6665 unsigned long eip = kvm_get_linear_rip(vcpu);
6666 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6667 vcpu->arch.guest_debug_dr7,
6668 vcpu->arch.eff_db);
6669
6670 if (dr6 != 0) {
6f43ed01 6671 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6672 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6673 kvm_run->debug.arch.exception = DB_VECTOR;
6674 kvm_run->exit_reason = KVM_EXIT_DEBUG;
60fc3d02 6675 *r = 0;
4a1e10d5
PB		 6676 return true;
6677 }
6678 }
6679
4161a569
NA		 6680 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6681 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6682 unsigned long eip = kvm_get_linear_rip(vcpu);
6683 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6684 vcpu->arch.dr7,
6685 vcpu->arch.db);
6686
6687 if (dr6 != 0) {
1fc5d194 6688 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 6689 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5 6690 kvm_queue_exception(vcpu, DB_VECTOR);
60fc3d02 6691 *r = 1;
4a1e10d5
PB		 6692 return true;
6693 }
6694 }
6695
6696 return false;
6697}
6698
04789b66
LA		 6699static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6700{
2d7921c4
AM		 6701 switch (ctxt->opcode_len) {
6702 case 1:
6703 switch (ctxt->b) {
6704 case 0xe4: /* IN */
6705 case 0xe5:
6706 case 0xec:
6707 case 0xed:
6708 case 0xe6: /* OUT */
6709 case 0xe7:
6710 case 0xee:
6711 case 0xef:
6712 case 0x6c: /* INS */
6713 case 0x6d:
6714 case 0x6e: /* OUTS */
6715 case 0x6f:
6716 return true;
6717 }
6718 break;
6719 case 2:
6720 switch (ctxt->b) {
6721 case 0x33: /* RDPMC */
6722 return true;
6723 }
6724 break;
04789b66
LA		 6725 }
6726
6727 return false;
6728}
6729
736c291c
SC		 6730int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6731 int emulation_type, void *insn, int insn_len)
bbd9b64e 6732{
95cb2295 6733 int r;
9d74191a 6734 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6735 bool writeback = true;
93c05d3e 6736 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6737
c595ceee
PB		 6738 vcpu->arch.l1tf_flush_l1d = true;
6739
93c05d3e
XG		 6740 /*
6741 * Clear write_fault_to_shadow_pgtable here to ensure it is
6742 * never reused.
6743 */
6744 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6745 kvm_clear_exception_queue(vcpu);
8d7d8102 6746
571008da 6747 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6748 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6749
6750 /*
6751 * We will reenter on the same instruction since
6752 * we do not set complete_userspace_io. This does not
6753 * handle watchpoints yet, those would be handled in
6754 * the emulate_ops.
6755 */
d391f120
VK		 6756 if (!(emulation_type & EMULTYPE_SKIP) &&
6757 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6758 return r;
6759
9d74191a
TY		 6760 ctxt->interruptibility = 0;
6761 ctxt->have_exception = false;
e0ad0b47 6762 ctxt->exception.vector = -1;
9d74191a 6763 ctxt->perm_ok = false;
bbd9b64e 6764
b51e974f 6765 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6766
9d74191a 6767 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6768
e46479f8 6769 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6770 ++vcpu->stat.insn_emulation;
1d2887e2 6771 if (r != EMULATION_OK) {
b4000606 6772 if ((emulation_type & EMULTYPE_TRAP_UD) ||
c83fad65
SC		 6773 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6774 kvm_queue_exception(vcpu, UD_VECTOR);
60fc3d02 6775 return 1;
c83fad65 6776 }
736c291c
SC		 6777 if (reexecute_instruction(vcpu, cr2_or_gpa,
6778 write_fault_to_spt,
6779 emulation_type))
60fc3d02 6780 return 1;
8530a79c 6781 if (ctxt->have_exception) {
c8848cee
JD		 6782 /*
6783 * #UD should result in just EMULATION_FAILED, and trap-like
6784 * exception should not be encountered during decode.
6785 */
6786 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6787 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8530a79c 6788 inject_emulated_exception(vcpu);
60fc3d02 6789 return 1;
8530a79c 6790 }
e2366171 6791 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6792 }
6793 }
6794
42cbf068
SC		 6795 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6796 !is_vmware_backdoor_opcode(ctxt)) {
6797 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
60fc3d02 6798 return 1;
42cbf068 6799 }
04789b66 6800
1957aa63
SC		 6801 /*
6802 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6803 * for kvm_skip_emulated_instruction(). The caller is responsible for
6804 * updating interruptibility state and injecting single-step #DBs.
6805 */
ba8afb6b 6806 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6807 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6808 if (ctxt->eflags & X86_EFLAGS_RF)
6809 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
60fc3d02 6810 return 1;
ba8afb6b
GN		 6811 }
6812
736c291c 6813 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
60fc3d02 6814 return 1;
1cb3f3ae 6815
7ae441ea 6816 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6817 changes registers values during IO operation */
7ae441ea
GN		 6818 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6819 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6820 emulator_invalidate_register_cache(ctxt);
7ae441ea 6821 }
4d2179e1 6822
5cd21917 6823restart:
0f89b207 6824 /* Save the faulting GPA (cr2) in the address field */
736c291c 6825 ctxt->exception.address = cr2_or_gpa;
0f89b207 6826
9d74191a 6827 r = x86_emulate_insn(ctxt);
bbd9b64e 6828
775fde86 6829 if (r == EMULATION_INTERCEPTED)
60fc3d02 6830 return 1;
775fde86 6831
d2ddd1c4 6832 if (r == EMULATION_FAILED) {
736c291c 6833 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
991eebf9 6834 emulation_type))
60fc3d02 6835 return 1;
c3cd7ffa 6836
e2366171 6837 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6838 }
6839
9d74191a 6840 if (ctxt->have_exception) {
60fc3d02 6841 r = 1;
ef54bcfe
PB		 6842 if (inject_emulated_exception(vcpu))
6843 return r;
d2ddd1c4 6844 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6845 if (!vcpu->arch.pio.in) {
6846 /* FIXME: return into emulator if single-stepping. */
3457e419 6847 vcpu->arch.pio.count = 0;
0912c977 6848 } else {
7ae441ea 6849 writeback = false;
716d51ab
GN		 6850 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6851 }
60fc3d02 6852 r = 0;
7ae441ea 6853 } else if (vcpu->mmio_needed) {
bc8a0aaf
SC		 6854 ++vcpu->stat.mmio_exits;
6855
7ae441ea
GN		 6856 if (!vcpu->mmio_is_write)
6857 writeback = false;
60fc3d02 6858 r = 0;
716d51ab 6859 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6860 } else if (r == EMULATION_RESTART)
5cd21917 6861 goto restart;
d2ddd1c4 6862 else
60fc3d02 6863 r = 1;
f850e2e6 6864
7ae441ea 6865 if (writeback) {
6addfc42 6866 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6867 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6868 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
38827dbd 6869 if (!ctxt->have_exception ||
75ee23b3
SC		 6870 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6871 kvm_rip_write(vcpu, ctxt->eip);
60fc3d02 6872 if (r && ctxt->tf)
120c2c4f 6873 r = kvm_vcpu_do_singlestep(vcpu);
38827dbd 6874 __kvm_set_rflags(vcpu, ctxt->eflags);
75ee23b3 6875 }
6addfc42
PB		 6876
6877 /*
6878 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6879 * do nothing, and it will be requested again as soon as
6880 * the shadow expires. But we still need to check here,
6881 * because POPF has no interrupt shadow.
6882 */
6883 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6884 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6885 } else
6886 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6887
6888 return r;
de7d789a 6889}
c60658d1
SC		 6890
6891int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6892{
6893 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6894}
6895EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6896
6897int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6898 void *insn, int insn_len)
6899{
6900 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6901}
6902EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6903
8764ed55
SC		 6904static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6905{
6906 vcpu->arch.pio.count = 0;
6907 return 1;
6908}
6909
45def77e
SC		 6910static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6911{
6912 vcpu->arch.pio.count = 0;
6913
6914 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6915 return 1;
6916
6917 return kvm_skip_emulated_instruction(vcpu);
6918}
6919
dca7f128
SC		 6920static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6921 unsigned short port)
de7d789a 6922{
de3cd117 6923 unsigned long val = kvm_rax_read(vcpu);
ca1d4a9e
AK		 6924 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6925 size, port, &val, 1);
8764ed55
SC		 6926 if (ret)
6927 return ret;
45def77e 6928
8764ed55
SC		 6929 /*
6930 * Workaround userspace that relies on old KVM behavior of %rip being
6931 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6932 */
6933 if (port == 0x7e &&
6934 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6935 vcpu->arch.complete_userspace_io =
6936 complete_fast_pio_out_port_0x7e;
6937 kvm_skip_emulated_instruction(vcpu);
6938 } else {
45def77e
SC		 6939 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6940 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6941 }
8764ed55 6942 return 0;
de7d789a 6943}
de7d789a 6944
8370c3d0
TL		 6945static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6946{
6947 unsigned long val;
6948
6949 /* We should only ever be called with arch.pio.count equal to 1 */
6950 BUG_ON(vcpu->arch.pio.count != 1);
6951
45def77e
SC		 6952 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6953 vcpu->arch.pio.count = 0;
6954 return 1;
6955 }
6956
8370c3d0 6957 /* For size less than 4 we merge, else we zero extend */
de3cd117 6958 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6959
6960 /*
6961 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6962 * the copy and tracing
6963 */
6964 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6965 vcpu->arch.pio.port, &val, 1);
de3cd117 6966 kvm_rax_write(vcpu, val);
8370c3d0 6967
45def77e 6968 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6969}
6970
dca7f128
SC		 6971static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6972 unsigned short port)
8370c3d0
TL		 6973{
6974 unsigned long val;
6975 int ret;
6976
6977 /* For size less than 4 we merge, else we zero extend */
de3cd117 6978 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6979
6980 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6981 &val, 1);
6982 if (ret) {
de3cd117 6983 kvm_rax_write(vcpu, val);
8370c3d0
TL		 6984 return ret;
6985 }
6986
45def77e 6987 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6988 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6989
6990 return 0;
6991}
dca7f128
SC		 6992
6993int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6994{
45def77e 6995 int ret;
dca7f128 6996
dca7f128 6997 if (in)
45def77e 6998 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6999 else
45def77e
SC		 7000 ret = kvm_fast_pio_out(vcpu, size, port);
7001 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 7002}
7003EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 7004
251a5fd6 7005static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 7006{
0a3aee0d 7007 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 7008 return 0;
8cfdc000
ZA		 7009}
7010
7011static void tsc_khz_changed(void *data)
c8076604 7012{
8cfdc000
ZA		 7013 struct cpufreq_freqs *freq = data;
7014 unsigned long khz = 0;
7015
7016 if (data)
7017 khz = freq->new;
7018 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7019 khz = cpufreq_quick_get(raw_smp_processor_id());
7020 if (!khz)
7021 khz = tsc_khz;
0a3aee0d 7022 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 7023}
7024
5fa4ec9c 7025#ifdef CONFIG_X86_64
0092e434
VK		 7026static void kvm_hyperv_tsc_notifier(void)
7027{
0092e434
VK		 7028 struct kvm *kvm;
7029 struct kvm_vcpu *vcpu;
7030 int cpu;
7031
0d9ce162 7032 mutex_lock(&kvm_lock);
0092e434
VK		 7033 list_for_each_entry(kvm, &vm_list, vm_list)
7034 kvm_make_mclock_inprogress_request(kvm);
7035
7036 hyperv_stop_tsc_emulation();
7037
7038 /* TSC frequency always matches when on Hyper-V */
7039 for_each_present_cpu(cpu)
7040 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7041 kvm_max_guest_tsc_khz = tsc_khz;
7042
7043 list_for_each_entry(kvm, &vm_list, vm_list) {
7044 struct kvm_arch *ka = &kvm->arch;
7045
7046 spin_lock(&ka->pvclock_gtod_sync_lock);
7047
7048 pvclock_update_vm_gtod_copy(kvm);
7049
7050 kvm_for_each_vcpu(cpu, vcpu, kvm)
7051 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7052
7053 kvm_for_each_vcpu(cpu, vcpu, kvm)
7054 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7055
7056 spin_unlock(&ka->pvclock_gtod_sync_lock);
7057 }
0d9ce162 7058 mutex_unlock(&kvm_lock);
0092e434 7059}
5fa4ec9c 7060#endif
0092e434 7061
df24014a 7062static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
c8076604 7063{
c8076604
GH		 7064 struct kvm *kvm;
7065 struct kvm_vcpu *vcpu;
7066 int i, send_ipi = 0;
7067
8cfdc000
ZA		 7068 /*
7069 * We allow guests to temporarily run on slowing clocks,
7070 * provided we notify them after, or to run on accelerating
7071 * clocks, provided we notify them before. Thus time never
7072 * goes backwards.
7073 *
7074 * However, we have a problem. We can't atomically update
7075 * the frequency of a given CPU from this function; it is
7076 * merely a notifier, which can be called from any CPU.
7077 * Changing the TSC frequency at arbitrary points in time
7078 * requires a recomputation of local variables related to
7079 * the TSC for each VCPU. We must flag these local variables
7080 * to be updated and be sure the update takes place with the
7081 * new frequency before any guests proceed.
7082 *
7083 * Unfortunately, the combination of hotplug CPU and frequency
7084 * change creates an intractable locking scenario; the order
7085 * of when these callouts happen is undefined with respect to
7086 * CPU hotplug, and they can race with each other. As such,
7087 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7088 * undefined; you can actually have a CPU frequency change take
7089 * place in between the computation of X and the setting of the
7090 * variable. To protect against this problem, all updates of
7091 * the per_cpu tsc_khz variable are done in an interrupt
7092 * protected IPI, and all callers wishing to update the value
7093 * must wait for a synchronous IPI to complete (which is trivial
7094 * if the caller is on the CPU already). This establishes the
7095 * necessary total order on variable updates.
7096 *
7097 * Note that because a guest time update may take place
7098 * anytime after the setting of the VCPU's request bit, the
7099 * correct TSC value must be set before the request. However,
7100 * to ensure the update actually makes it to any guest which
7101 * starts running in hardware virtualization between the set
7102 * and the acquisition of the spinlock, we must also ping the
7103 * CPU after setting the request bit.
7104 *
7105 */
7106
df24014a 7107 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 7108
0d9ce162 7109 mutex_lock(&kvm_lock);
c8076604 7110 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 7111 kvm_for_each_vcpu(i, vcpu, kvm) {
df24014a 7112 if (vcpu->cpu != cpu)
c8076604 7113 continue;
c285545f 7114 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0d9ce162 7115 if (vcpu->cpu != raw_smp_processor_id())
8cfdc000 7116 send_ipi = 1;
c8076604
GH		 7117 }
7118 }
0d9ce162 7119 mutex_unlock(&kvm_lock);
c8076604
GH		 7120
7121 if (freq->old < freq->new && send_ipi) {
7122 /*
7123 * We upscale the frequency. Must make the guest
7124 * doesn't see old kvmclock values while running with
7125 * the new frequency, otherwise we risk the guest sees
7126 * time go backwards.
7127 *
7128 * In case we update the frequency for another cpu
7129 * (which might be in guest context) send an interrupt
7130 * to kick the cpu out of guest context. Next time
7131 * guest context is entered kvmclock will be updated,
7132 * so the guest will not see stale values.
7133 */
df24014a 7134 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 7135 }
df24014a
VK		 7136}
7137
7138static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7139 void *data)
7140{
7141 struct cpufreq_freqs *freq = data;
7142 int cpu;
7143
7144 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7145 return 0;
7146 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7147 return 0;
7148
7149 for_each_cpu(cpu, freq->policy->cpus)
7150 __kvmclock_cpufreq_notifier(freq, cpu);
7151
c8076604
GH		 7152 return 0;
7153}
7154
7155static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 7156 .notifier_call = kvmclock_cpufreq_notifier
7157};
7158
251a5fd6 7159static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 7160{
251a5fd6
SAS		 7161 tsc_khz_changed(NULL);
7162 return 0;
8cfdc000
ZA		 7163}
7164
b820cc0c
ZA		 7165static void kvm_timer_init(void)
7166{
c285545f 7167 max_tsc_khz = tsc_khz;
460dd42e 7168
b820cc0c 7169 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 7170#ifdef CONFIG_CPU_FREQ
7171 struct cpufreq_policy policy;
758f588d
BP		 7172 int cpu;
7173
c285545f 7174 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 7175 cpu = get_cpu();
7176 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 7177 if (policy.cpuinfo.max_freq)
7178 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 7179 put_cpu();
c285545f 7180#endif
b820cc0c
ZA		 7181 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7182 CPUFREQ_TRANSITION_NOTIFIER);
7183 }
460dd42e 7184
73c1b41e 7185 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 7186 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 7187}
7188
dd60d217
AK		 7189DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7190EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 7191
f5132b01 7192int kvm_is_in_guest(void)
ff9d07a0 7193{
086c9855 7194 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 7195}
7196
7197static int kvm_is_user_mode(void)
7198{
7199 int user_mode = 3;
dcf46b94 7200
086c9855
AS		 7201 if (__this_cpu_read(current_vcpu))
7202 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 7203
ff9d07a0
ZY		 7204 return user_mode != 0;
7205}
7206
7207static unsigned long kvm_get_guest_ip(void)
7208{
7209 unsigned long ip = 0;
dcf46b94 7210
086c9855
AS		 7211 if (__this_cpu_read(current_vcpu))
7212 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 7213
ff9d07a0
ZY		 7214 return ip;
7215}
7216
8479e04e
LK		 7217static void kvm_handle_intel_pt_intr(void)
7218{
7219 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7220
7221 kvm_make_request(KVM_REQ_PMI, vcpu);
7222 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7223 (unsigned long *)&vcpu->arch.pmu.global_status);
7224}
7225
ff9d07a0
ZY		 7226static struct perf_guest_info_callbacks kvm_guest_cbs = {
7227 .is_in_guest = kvm_is_in_guest,
7228 .is_user_mode = kvm_is_user_mode,
7229 .get_guest_ip = kvm_get_guest_ip,
8479e04e 7230 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
ff9d07a0
ZY		 7231};
7232
16e8d74d
MT		 7233#ifdef CONFIG_X86_64
7234static void pvclock_gtod_update_fn(struct work_struct *work)
7235{
d828199e
MT		 7236 struct kvm *kvm;
7237
7238 struct kvm_vcpu *vcpu;
7239 int i;
7240
0d9ce162 7241 mutex_lock(&kvm_lock);
d828199e
MT		 7242 list_for_each_entry(kvm, &vm_list, vm_list)
7243 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 7244 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 7245 atomic_set(&kvm_guest_has_master_clock, 0);
0d9ce162 7246 mutex_unlock(&kvm_lock);
16e8d74d
MT		 7247}
7248
7249static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7250
7251/*
7252 * Notification about pvclock gtod data update.
7253 */
7254static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7255 void *priv)
7256{
7257 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7258 struct timekeeper *tk = priv;
7259
7260 update_pvclock_gtod(tk);
7261
7262 /* disable master clock if host does not trust, or does not
b0c39dc6 7263 * use, TSC based clocksource.
16e8d74d 7264 */
b0c39dc6 7265 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 7266 atomic_read(&kvm_guest_has_master_clock) != 0)
7267 queue_work(system_long_wq, &pvclock_gtod_work);
7268
7269 return 0;
7270}
7271
7272static struct notifier_block pvclock_gtod_notifier = {
7273 .notifier_call = pvclock_gtod_notify,
7274};
7275#endif
7276
f8c16bba 7277int kvm_arch_init(void *opaque)
043405e1 7278{
b820cc0c 7279 int r;
6b61edf7 7280 struct kvm_x86_ops *ops = opaque;
f8c16bba 7281
f8c16bba
ZX		 7282 if (kvm_x86_ops) {
7283 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 7284 r = -EEXIST;
7285 goto out;
f8c16bba
ZX		 7286 }
7287
7288 if (!ops->cpu_has_kvm_support()) {
7289 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 7290 r = -EOPNOTSUPP;
7291 goto out;
f8c16bba
ZX		 7292 }
7293 if (ops->disabled_by_bios()) {
7294 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 7295 r = -EOPNOTSUPP;
7296 goto out;
f8c16bba
ZX		 7297 }
7298
b666a4b6
MO		 7299 /*
7300 * KVM explicitly assumes that the guest has an FPU and
7301 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7302 * vCPU's FPU state as a fxregs_state struct.
7303 */
7304 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7305 printk(KERN_ERR "kvm: inadequate fpu\n");
7306 r = -EOPNOTSUPP;
7307 goto out;
7308 }
7309
013f6a5d 7310 r = -ENOMEM;
ed8e4812 7311 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 7312 __alignof__(struct fpu), SLAB_ACCOUNT,
7313 NULL);
7314 if (!x86_fpu_cache) {
7315 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7316 goto out;
7317 }
7318
013f6a5d
MT		 7319 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7320 if (!shared_msrs) {
7321 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 7322 goto out_free_x86_fpu_cache;
013f6a5d
MT		 7323 }
7324
97db56ce
AK		 7325 r = kvm_mmu_module_init();
7326 if (r)
013f6a5d 7327 goto out_free_percpu;
97db56ce 7328
f8c16bba 7329 kvm_x86_ops = ops;
920c8377 7330
7b52345e 7331 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 7332 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 7333 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 7334 kvm_timer_init();
c8076604 7335
ff9d07a0
ZY		 7336 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7337
d366bf7e 7338 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 7339 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7340
c5cc421b 7341 kvm_lapic_init();
0c5f81da
WL		 7342 if (pi_inject_timer == -1)
7343 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
16e8d74d
MT		 7344#ifdef CONFIG_X86_64
7345 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 7346
5fa4ec9c 7347 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 7348 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 7349#endif
7350
f8c16bba 7351 return 0;
56c6d28a 7352
013f6a5d
MT		 7353out_free_percpu:
7354 free_percpu(shared_msrs);
b666a4b6
MO		 7355out_free_x86_fpu_cache:
7356 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7357out:
56c6d28a 7358 return r;
043405e1 7359}
8776e519 7360
f8c16bba
ZX		 7361void kvm_arch_exit(void)
7362{
0092e434 7363#ifdef CONFIG_X86_64
5fa4ec9c 7364 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 7365 clear_hv_tscchange_cb();
7366#endif
cef84c30 7367 kvm_lapic_exit();
ff9d07a0
ZY		 7368 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7369
888d256e
JK		 7370 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7371 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7372 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7373 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7374#ifdef CONFIG_X86_64
7375 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7376#endif
f8c16bba 7377 kvm_x86_ops = NULL;
56c6d28a 7378 kvm_mmu_module_exit();
013f6a5d 7379 free_percpu(shared_msrs);
b666a4b6 7380 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7381}
f8c16bba 7382
5cb56059 7383int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7384{
7385 ++vcpu->stat.halt_exits;
35754c98 7386 if (lapic_in_kernel(vcpu)) {
a4535290 7387 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7388 return 1;
7389 } else {
7390 vcpu->run->exit_reason = KVM_EXIT_HLT;
7391 return 0;
7392 }
7393}
5cb56059
JS		 7394EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7395
7396int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7397{
6affcbed
KH		 7398 int ret = kvm_skip_emulated_instruction(vcpu);
7399 /*
7400 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7401 * KVM_EXIT_DEBUG here.
7402 */
7403 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7404}
8776e519
HB		 7405EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7406
8ef81a9a 7407#ifdef CONFIG_X86_64
55dd00a7
MT		 7408static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7409 unsigned long clock_type)
7410{
7411 struct kvm_clock_pairing clock_pairing;
899a31f5 7412 struct timespec64 ts;
80fbd89c 7413 u64 cycle;
55dd00a7
MT		 7414 int ret;
7415
7416 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7417 return -KVM_EOPNOTSUPP;
7418
7419 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7420 return -KVM_EOPNOTSUPP;
7421
7422 clock_pairing.sec = ts.tv_sec;
7423 clock_pairing.nsec = ts.tv_nsec;
7424 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7425 clock_pairing.flags = 0;
bcbfbd8e 7426 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7427
7428 ret = 0;
7429 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7430 sizeof(struct kvm_clock_pairing)))
7431 ret = -KVM_EFAULT;
7432
7433 return ret;
7434}
8ef81a9a 7435#endif
55dd00a7 7436
6aef266c
SV		 7437/*
7438 * kvm_pv_kick_cpu_op: Kick a vcpu.
7439 *
7440 * @apicid - apicid of vcpu to be kicked.
7441 */
7442static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7443{
24d2166b 7444 struct kvm_lapic_irq lapic_irq;
6aef266c 7445
150a84fe 7446 lapic_irq.shorthand = APIC_DEST_NOSHORT;
c96001c5 7447 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
ebd28fcb 7448 lapic_irq.level = 0;
24d2166b 7449 lapic_irq.dest_id = apicid;
93bbf0b8 7450 lapic_irq.msi_redir_hint = false;
6aef266c 7451
24d2166b 7452 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7453 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7454}
7455
d62caabb
AS		 7456void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7457{
f7589cca
PB		 7458 if (!lapic_in_kernel(vcpu)) {
7459 WARN_ON_ONCE(vcpu->arch.apicv_active);
7460 return;
7461 }
7462 if (!vcpu->arch.apicv_active)
7463 return;
7464
d62caabb
AS		 7465 vcpu->arch.apicv_active = false;
7466 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7467}
7468
71506297
WL		 7469static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7470{
7471 struct kvm_vcpu *target = NULL;
7472 struct kvm_apic_map *map;
7473
7474 rcu_read_lock();
7475 map = rcu_dereference(kvm->arch.apic_map);
7476
7477 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7478 target = map->phys_map[dest_id]->vcpu;
7479
7480 rcu_read_unlock();
7481
266e85a5 7482 if (target && READ_ONCE(target->ready))
71506297
WL		 7483 kvm_vcpu_yield_to(target);
7484}
7485
8776e519
HB		 7486int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7487{
7488 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7489 int op_64_bit;
8776e519 7490
696ca779
RK		 7491 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7492 return kvm_hv_hypercall(vcpu);
55cd8e5a 7493
de3cd117
SC		 7494 nr = kvm_rax_read(vcpu);
7495 a0 = kvm_rbx_read(vcpu);
7496 a1 = kvm_rcx_read(vcpu);
7497 a2 = kvm_rdx_read(vcpu);
7498 a3 = kvm_rsi_read(vcpu);
8776e519 7499
229456fc 7500 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7501
a449c7aa
NA		 7502 op_64_bit = is_64_bit_mode(vcpu);
7503 if (!op_64_bit) {
8776e519
HB		 7504 nr &= 0xFFFFFFFF;
7505 a0 &= 0xFFFFFFFF;
7506 a1 &= 0xFFFFFFFF;
7507 a2 &= 0xFFFFFFFF;
7508 a3 &= 0xFFFFFFFF;
7509 }
7510
07708c4a
JK		 7511 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7512 ret = -KVM_EPERM;
696ca779 7513 goto out;
07708c4a
JK		 7514 }
7515
8776e519 7516 switch (nr) {
b93463aa
AK		 7517 case KVM_HC_VAPIC_POLL_IRQ:
7518 ret = 0;
7519 break;
6aef266c
SV		 7520 case KVM_HC_KICK_CPU:
7521 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
266e85a5 7522 kvm_sched_yield(vcpu->kvm, a1);
6aef266c
SV		 7523 ret = 0;
7524 break;
8ef81a9a 7525#ifdef CONFIG_X86_64
55dd00a7
MT		 7526 case KVM_HC_CLOCK_PAIRING:
7527 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7528 break;
1ed199a4 7529#endif
4180bf1b
WL		 7530 case KVM_HC_SEND_IPI:
7531 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7532 break;
71506297
WL		 7533 case KVM_HC_SCHED_YIELD:
7534 kvm_sched_yield(vcpu->kvm, a0);
7535 ret = 0;
7536 break;
8776e519
HB		 7537 default:
7538 ret = -KVM_ENOSYS;
7539 break;
7540 }
696ca779 7541out:
a449c7aa
NA		 7542 if (!op_64_bit)
7543 ret = (u32)ret;
de3cd117 7544 kvm_rax_write(vcpu, ret);
6356ee0c 7545
f11c3a8d 7546 ++vcpu->stat.hypercalls;
6356ee0c 7547 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7548}
7549EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7550
b6785def 7551static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7552{
d6aa1000 7553 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7554 char instruction[3];
5fdbf976 7555 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7556
8776e519 7557 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7558
ce2e852e
DV		 7559 return emulator_write_emulated(ctxt, rip, instruction, 3,
7560 &ctxt->exception);
8776e519
HB		 7561}
7562
851ba692 7563static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7564{
782d422b
MG		 7565 return vcpu->run->request_interrupt_window &&
7566 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7567}
7568
851ba692 7569static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7570{
851ba692
AK		 7571 struct kvm_run *kvm_run = vcpu->run;
7572
91586a3b 7573 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7574 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7575 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7576 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7577 kvm_run->ready_for_interrupt_injection =
7578 pic_in_kernel(vcpu->kvm) ||
782d422b 7579 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7580}
7581
95ba8273
GN		 7582static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7583{
7584 int max_irr, tpr;
7585
7586 if (!kvm_x86_ops->update_cr8_intercept)
7587 return;
7588
bce87cce 7589 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7590 return;
7591
d62caabb
AS		 7592 if (vcpu->arch.apicv_active)
7593 return;
7594
8db3baa2
GN		 7595 if (!vcpu->arch.apic->vapic_addr)
7596 max_irr = kvm_lapic_find_highest_irr(vcpu);
7597 else
7598 max_irr = -1;
95ba8273
GN		 7599
7600 if (max_irr != -1)
7601 max_irr >>= 4;
7602
7603 tpr = kvm_lapic_get_cr8(vcpu);
7604
7605 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7606}
7607
b6b8a145 7608static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7609{
b6b8a145
JK		 7610 int r;
7611
95ba8273 7612 /* try to reinject previous events if any */
664f8e26 7613
1a680e35
LA		 7614 if (vcpu->arch.exception.injected)
7615 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7616 /*
a042c26f
LA		 7617 * Do not inject an NMI or interrupt if there is a pending
7618 * exception. Exceptions and interrupts are recognized at
7619 * instruction boundaries, i.e. the start of an instruction.
7620 * Trap-like exceptions, e.g. #DB, have higher priority than
7621 * NMIs and interrupts, i.e. traps are recognized before an
7622 * NMI/interrupt that's pending on the same instruction.
7623 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7624 * priority, but are only generated (pended) during instruction
7625 * execution, i.e. a pending fault-like exception means the
7626 * fault occurred on the *previous* instruction and must be
7627 * serviced prior to recognizing any new events in order to
7628 * fully complete the previous instruction.
664f8e26 7629 */
1a680e35
LA		 7630 else if (!vcpu->arch.exception.pending) {
7631 if (vcpu->arch.nmi_injected)
664f8e26 7632 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7633 else if (vcpu->arch.interrupt.injected)
664f8e26 7634 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7635 }
7636
1a680e35
LA		 7637 /*
7638 * Call check_nested_events() even if we reinjected a previous event
7639 * in order for caller to determine if it should require immediate-exit
7640 * from L2 to L1 due to pending L1 events which require exit
7641 * from L2 to L1.
7642 */
664f8e26
WL		 7643 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7644 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7645 if (r != 0)
7646 return r;
7647 }
7648
7649 /* try to inject new event if pending */
b59bb7bd 7650 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7651 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7652 vcpu->arch.exception.has_error_code,
7653 vcpu->arch.exception.error_code);
d6e8c854 7654
1a680e35 7655 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7656 vcpu->arch.exception.pending = false;
7657 vcpu->arch.exception.injected = true;
7658
d6e8c854
NA		 7659 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7660 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7661 X86_EFLAGS_RF);
7662
f10c729f
JM		 7663 if (vcpu->arch.exception.nr == DB_VECTOR) {
7664 /*
7665 * This code assumes that nSVM doesn't use
7666 * check_nested_events(). If it does, the
7667 * DR6/DR7 changes should happen before L1
7668 * gets a #VMEXIT for an intercepted #DB in
7669 * L2. (Under VMX, on the other hand, the
7670 * DR6/DR7 changes should not happen in the
7671 * event of a VM-exit to L1 for an intercepted
7672 * #DB in L2.)
7673 */
7674 kvm_deliver_exception_payload(vcpu);
7675 if (vcpu->arch.dr7 & DR7_GD) {
7676 vcpu->arch.dr7 &= ~DR7_GD;
7677 kvm_update_dr7(vcpu);
7678 }
6bdf0662
NA		 7679 }
7680
cfcd20e5 7681 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7682 }
7683
7684 /* Don't consider new event if we re-injected an event */
7685 if (kvm_event_needs_reinjection(vcpu))
7686 return 0;
7687
7688 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7689 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7690 vcpu->arch.smi_pending = false;
52797bf9 7691 ++vcpu->arch.smi_count;
ee2cd4b7 7692 enter_smm(vcpu);
c43203ca 7693 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7694 --vcpu->arch.nmi_pending;
7695 vcpu->arch.nmi_injected = true;
7696 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7697 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7698 /*
7699 * Because interrupts can be injected asynchronously, we are
7700 * calling check_nested_events again here to avoid a race condition.
7701 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7702 * proposal and current concerns. Perhaps we should be setting
7703 * KVM_REQ_EVENT only on certain events and not unconditionally?
7704 */
7705 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7706 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7707 if (r != 0)
7708 return r;
7709 }
95ba8273 7710 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7711 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7712 false);
7713 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7714 }
7715 }
ee2cd4b7 7716
b6b8a145 7717 return 0;
95ba8273
GN		 7718}
7719
7460fb4a
AK		 7720static void process_nmi(struct kvm_vcpu *vcpu)
7721{
7722 unsigned limit = 2;
7723
7724 /*
7725 * x86 is limited to one NMI running, and one NMI pending after it.
7726 * If an NMI is already in progress, limit further NMIs to just one.
7727 * Otherwise, allow two (and we'll inject the first one immediately).
7728 */
7729 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7730 limit = 1;
7731
7732 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7733 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7734 kvm_make_request(KVM_REQ_EVENT, vcpu);
7735}
7736
ee2cd4b7 7737static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7738{
7739 u32 flags = 0;
7740 flags |= seg->g << 23;
7741 flags |= seg->db << 22;
7742 flags |= seg->l << 21;
7743 flags |= seg->avl << 20;
7744 flags |= seg->present << 15;
7745 flags |= seg->dpl << 13;
7746 flags |= seg->s << 12;
7747 flags |= seg->type << 8;
7748 return flags;
7749}
7750
ee2cd4b7 7751static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7752{
7753 struct kvm_segment seg;
7754 int offset;
7755
7756 kvm_get_segment(vcpu, &seg, n);
7757 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7758
7759 if (n < 3)
7760 offset = 0x7f84 + n * 12;
7761 else
7762 offset = 0x7f2c + (n - 3) * 12;
7763
7764 put_smstate(u32, buf, offset + 8, seg.base);
7765 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7766 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7767}
7768
efbb288a 7769#ifdef CONFIG_X86_64
ee2cd4b7 7770static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7771{
7772 struct kvm_segment seg;
7773 int offset;
7774 u16 flags;
7775
7776 kvm_get_segment(vcpu, &seg, n);
7777 offset = 0x7e00 + n * 16;
7778
ee2cd4b7 7779 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7780 put_smstate(u16, buf, offset, seg.selector);
7781 put_smstate(u16, buf, offset + 2, flags);
7782 put_smstate(u32, buf, offset + 4, seg.limit);
7783 put_smstate(u64, buf, offset + 8, seg.base);
7784}
efbb288a 7785#endif
660a5d51 7786
ee2cd4b7 7787static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7788{
7789 struct desc_ptr dt;
7790 struct kvm_segment seg;
7791 unsigned long val;
7792 int i;
7793
7794 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7795 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7796 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7797 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7798
7799 for (i = 0; i < 8; i++)
7800 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7801
7802 kvm_get_dr(vcpu, 6, &val);
7803 put_smstate(u32, buf, 0x7fcc, (u32)val);
7804 kvm_get_dr(vcpu, 7, &val);
7805 put_smstate(u32, buf, 0x7fc8, (u32)val);
7806
7807 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7808 put_smstate(u32, buf, 0x7fc4, seg.selector);
7809 put_smstate(u32, buf, 0x7f64, seg.base);
7810 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7811 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7812
7813 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7814 put_smstate(u32, buf, 0x7fc0, seg.selector);
7815 put_smstate(u32, buf, 0x7f80, seg.base);
7816 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7817 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7818
7819 kvm_x86_ops->get_gdt(vcpu, &dt);
7820 put_smstate(u32, buf, 0x7f74, dt.address);
7821 put_smstate(u32, buf, 0x7f70, dt.size);
7822
7823 kvm_x86_ops->get_idt(vcpu, &dt);
7824 put_smstate(u32, buf, 0x7f58, dt.address);
7825 put_smstate(u32, buf, 0x7f54, dt.size);
7826
7827 for (i = 0; i < 6; i++)
ee2cd4b7 7828 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7829
7830 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7831
7832 /* revision id */
7833 put_smstate(u32, buf, 0x7efc, 0x00020000);
7834 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7835}
7836
b68f3cc7 7837#ifdef CONFIG_X86_64
ee2cd4b7 7838static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7839{
660a5d51
PB		 7840 struct desc_ptr dt;
7841 struct kvm_segment seg;
7842 unsigned long val;
7843 int i;
7844
7845 for (i = 0; i < 16; i++)
7846 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7847
7848 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7849 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7850
7851 kvm_get_dr(vcpu, 6, &val);
7852 put_smstate(u64, buf, 0x7f68, val);
7853 kvm_get_dr(vcpu, 7, &val);
7854 put_smstate(u64, buf, 0x7f60, val);
7855
7856 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7857 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7858 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7859
7860 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7861
7862 /* revision id */
7863 put_smstate(u32, buf, 0x7efc, 0x00020064);
7864
7865 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7866
7867 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7868 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7869 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7870 put_smstate(u32, buf, 0x7e94, seg.limit);
7871 put_smstate(u64, buf, 0x7e98, seg.base);
7872
7873 kvm_x86_ops->get_idt(vcpu, &dt);
7874 put_smstate(u32, buf, 0x7e84, dt.size);
7875 put_smstate(u64, buf, 0x7e88, dt.address);
7876
7877 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7878 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7879 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7880 put_smstate(u32, buf, 0x7e74, seg.limit);
7881 put_smstate(u64, buf, 0x7e78, seg.base);
7882
7883 kvm_x86_ops->get_gdt(vcpu, &dt);
7884 put_smstate(u32, buf, 0x7e64, dt.size);
7885 put_smstate(u64, buf, 0x7e68, dt.address);
7886
7887 for (i = 0; i < 6; i++)
ee2cd4b7 7888 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7889}
b68f3cc7 7890#endif
660a5d51 7891
ee2cd4b7 7892static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7893{
660a5d51 7894 struct kvm_segment cs, ds;
18c3626e 7895 struct desc_ptr dt;
660a5d51
PB		 7896 char buf[512];
7897 u32 cr0;
7898
660a5d51 7899 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7900 memset(buf, 0, 512);
b68f3cc7 7901#ifdef CONFIG_X86_64
d6321d49 7902 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7903 enter_smm_save_state_64(vcpu, buf);
660a5d51 7904 else
b68f3cc7 7905#endif
ee2cd4b7 7906 enter_smm_save_state_32(vcpu, buf);
660a5d51 7907
0234bf88
LP		 7908 /*
7909 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7910 * vCPU state (e.g. leave guest mode) after we've saved the state into
7911 * the SMM state-save area.
7912 */
7913 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7914
7915 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7916 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7917
7918 if (kvm_x86_ops->get_nmi_mask(vcpu))
7919 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7920 else
7921 kvm_x86_ops->set_nmi_mask(vcpu, true);
7922
7923 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7924 kvm_rip_write(vcpu, 0x8000);
7925
7926 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7927 kvm_x86_ops->set_cr0(vcpu, cr0);
7928 vcpu->arch.cr0 = cr0;
7929
7930 kvm_x86_ops->set_cr4(vcpu, 0);
7931
18c3626e
PB		 7932 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7933 dt.address = dt.size = 0;
7934 kvm_x86_ops->set_idt(vcpu, &dt);
7935
660a5d51
PB		 7936 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7937
7938 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7939 cs.base = vcpu->arch.smbase;
7940
7941 ds.selector = 0;
7942 ds.base = 0;
7943
7944 cs.limit = ds.limit = 0xffffffff;
7945 cs.type = ds.type = 0x3;
7946 cs.dpl = ds.dpl = 0;
7947 cs.db = ds.db = 0;
7948 cs.s = ds.s = 1;
7949 cs.l = ds.l = 0;
7950 cs.g = ds.g = 1;
7951 cs.avl = ds.avl = 0;
7952 cs.present = ds.present = 1;
7953 cs.unusable = ds.unusable = 0;
7954 cs.padding = ds.padding = 0;
7955
7956 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7957 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7958 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7959 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7960 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7961 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7962
b68f3cc7 7963#ifdef CONFIG_X86_64
d6321d49 7964 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7965 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7966#endif
660a5d51
PB		 7967
7968 kvm_update_cpuid(vcpu);
7969 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7970}
7971
ee2cd4b7 7972static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7973{
7974 vcpu->arch.smi_pending = true;
7975 kvm_make_request(KVM_REQ_EVENT, vcpu);
7976}
7977
7ee30bc1
NNL		 7978void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
7979 unsigned long *vcpu_bitmap)
7980{
7981 cpumask_var_t cpus;
7ee30bc1
NNL		 7982
7983 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
7984
db5a95ec
MW		 7985 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
7986 vcpu_bitmap, cpus);
7ee30bc1
NNL		 7987
7988 free_cpumask_var(cpus);
7989}
7990
2860c4b1
PB		 7991void kvm_make_scan_ioapic_request(struct kvm *kvm)
7992{
7993 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7994}
7995
3d81bc7e 7996static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7997{
dcbd3e49 7998 if (!kvm_apic_present(vcpu))
3d81bc7e 7999 return;
c7c9c56c 8000
6308630b 8001 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 8002
b053b2ae 8003 if (irqchip_split(vcpu->kvm))
6308630b 8004 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 8005 else {
fa59cc00 8006 if (vcpu->arch.apicv_active)
d62caabb 8007 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 8008 if (ioapic_in_kernel(vcpu->kvm))
8009 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 8010 }
e40ff1d6
LA		 8011
8012 if (is_guest_mode(vcpu))
8013 vcpu->arch.load_eoi_exitmap_pending = true;
8014 else
8015 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8016}
8017
8018static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8019{
8020 u64 eoi_exit_bitmap[4];
8021
8022 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8023 return;
8024
5c919412
AS		 8025 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8026 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8027 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 8028}
8029
93065ac7
MH		 8030int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8031 unsigned long start, unsigned long end,
8032 bool blockable)
b1394e74
RK		 8033{
8034 unsigned long apic_address;
8035
8036 /*
8037 * The physical address of apic access page is stored in the VMCS.
8038 * Update it when it becomes invalid.
8039 */
8040 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8041 if (start <= apic_address && apic_address < end)
8042 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 8043
8044 return 0;
b1394e74
RK		 8045}
8046
4256f43f
TC		 8047void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8048{
c24ae0dc
TC		 8049 struct page *page = NULL;
8050
35754c98 8051 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 8052 return;
8053
4256f43f
TC		 8054 if (!kvm_x86_ops->set_apic_access_page_addr)
8055 return;
8056
c24ae0dc 8057 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 8058 if (is_error_page(page))
8059 return;
c24ae0dc
TC		 8060 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
8061
8062 /*
8063 * Do not pin apic access page in memory, the MMU notifier
8064 * will call us again if it is migrated or swapped out.
8065 */
8066 put_page(page);
4256f43f 8067}
4256f43f 8068
d264ee0c
SC		 8069void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8070{
8071 smp_send_reschedule(vcpu->cpu);
8072}
8073EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8074
9357d939 8075/*
362c698f 8076 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 8077 * exiting to the userspace. Otherwise, the value will be returned to the
8078 * userspace.
8079 */
851ba692 8080static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 8081{
8082 int r;
62a193ed
MG		 8083 bool req_int_win =
8084 dm_request_for_irq_injection(vcpu) &&
8085 kvm_cpu_accept_dm_intr(vcpu);
1e9e2622 8086 enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE;
62a193ed 8087
730dca42 8088 bool req_immediate_exit = false;
b6c7a5dc 8089
2fa6e1e1 8090 if (kvm_request_pending(vcpu)) {
671ddc70
JM		 8091 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8092 if (unlikely(!kvm_x86_ops->get_vmcs12_pages(vcpu))) {
8093 r = 0;
8094 goto out;
8095 }
8096 }
a8eeb04a 8097 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 8098 kvm_mmu_unload(vcpu);
a8eeb04a 8099 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 8100 __kvm_migrate_timers(vcpu);
d828199e
MT		 8101 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8102 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 8103 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8104 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 8105 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8106 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 8107 if (unlikely(r))
8108 goto out;
8109 }
a8eeb04a 8110 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 8111 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 8112 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
8113 kvm_mmu_load_cr3(vcpu);
a8eeb04a 8114 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 8115 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 8116 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 8117 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 8118 r = 0;
8119 goto out;
8120 }
a8eeb04a 8121 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 8122 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 8123 vcpu->mmio_needed = 0;
71c4dfaf
JR		 8124 r = 0;
8125 goto out;
8126 }
af585b92
GN		 8127 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8128 /* Page is swapped out. Do synthetic halt */
8129 vcpu->arch.apf.halted = true;
8130 r = 1;
8131 goto out;
8132 }
c9aaa895
GC		 8133 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8134 record_steal_time(vcpu);
64d60670
PB		 8135 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8136 process_smi(vcpu);
7460fb4a
AK		 8137 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8138 process_nmi(vcpu);
f5132b01 8139 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 8140 kvm_pmu_handle_event(vcpu);
f5132b01 8141 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 8142 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 8143 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8144 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8145 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 8146 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 8147 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8148 vcpu->run->eoi.vector =
8149 vcpu->arch.pending_ioapic_eoi;
8150 r = 0;
8151 goto out;
8152 }
8153 }
3d81bc7e
YZ		 8154 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8155 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 8156 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8157 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 8158 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8159 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 8160 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8161 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8162 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8163 r = 0;
8164 goto out;
8165 }
e516cebb
AS		 8166 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8167 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8168 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8169 r = 0;
8170 goto out;
8171 }
db397571
AS		 8172 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8173 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8174 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8175 r = 0;
8176 goto out;
8177 }
f3b138c5
AS		 8178
8179 /*
8180 * KVM_REQ_HV_STIMER has to be processed after
8181 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8182 * depend on the guest clock being up-to-date
8183 */
1f4b34f8
AS		 8184 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8185 kvm_hv_process_stimers(vcpu);
2f52d58c 8186 }
b93463aa 8187
b463a6f7 8188 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 8189 ++vcpu->stat.req_event;
66450a21
JK		 8190 kvm_apic_accept_events(vcpu);
8191 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8192 r = 1;
8193 goto out;
8194 }
8195
b6b8a145
JK		 8196 if (inject_pending_event(vcpu, req_int_win) != 0)
8197 req_immediate_exit = true;
321c5658 8198 else {
cc3d967f 8199 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 8200 *
cc3d967f
LP		 8201 * SMIs have three cases:
8202 * 1) They can be nested, and then there is nothing to
8203 * do here because RSM will cause a vmexit anyway.
8204 * 2) There is an ISA-specific reason why SMI cannot be
8205 * injected, and the moment when this changes can be
8206 * intercepted.
8207 * 3) Or the SMI can be pending because
8208 * inject_pending_event has completed the injection
8209 * of an IRQ or NMI from the previous vmexit, and
8210 * then we request an immediate exit to inject the
8211 * SMI.
c43203ca
PB		 8212 */
8213 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 8214 if (!kvm_x86_ops->enable_smi_window(vcpu))
8215 req_immediate_exit = true;
321c5658
YS		 8216 if (vcpu->arch.nmi_pending)
8217 kvm_x86_ops->enable_nmi_window(vcpu);
8218 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8219 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 8220 WARN_ON(vcpu->arch.exception.pending);
321c5658 8221 }
b463a6f7
AK		 8222
8223 if (kvm_lapic_enabled(vcpu)) {
8224 update_cr8_intercept(vcpu);
8225 kvm_lapic_sync_to_vapic(vcpu);
8226 }
8227 }
8228
d8368af8
AK		 8229 r = kvm_mmu_reload(vcpu);
8230 if (unlikely(r)) {
d905c069 8231 goto cancel_injection;
d8368af8
AK		 8232 }
8233
b6c7a5dc
HB		 8234 preempt_disable();
8235
8236 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 8237
8238 /*
8239 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8240 * IPI are then delayed after guest entry, which ensures that they
8241 * result in virtual interrupt delivery.
8242 */
8243 local_irq_disable();
6b7e2d09
XG		 8244 vcpu->mode = IN_GUEST_MODE;
8245
01b71917
MT		 8246 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8247
0f127d12 8248 /*
b95234c8 8249 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 8250 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 8251 *
81b01667 8252 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 8253 * pairs with the memory barrier implicit in pi_test_and_set_on
8254 * (see vmx_deliver_posted_interrupt).
8255 *
8256 * 3) This also orders the write to mode from any reads to the page
8257 * tables done while the VCPU is running. Please see the comment
8258 * in kvm_flush_remote_tlbs.
6b7e2d09 8259 */
01b71917 8260 smp_mb__after_srcu_read_unlock();
b6c7a5dc 8261
b95234c8
PB		 8262 /*
8263 * This handles the case where a posted interrupt was
8264 * notified with kvm_vcpu_kick.
8265 */
fa59cc00
LA		 8266 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8267 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 8268
2fa6e1e1 8269 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 8270 || need_resched() || signal_pending(current)) {
6b7e2d09 8271 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8272 smp_wmb();
6c142801
AK		 8273 local_irq_enable();
8274 preempt_enable();
01b71917 8275 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 8276 r = 1;
d905c069 8277 goto cancel_injection;
6c142801
AK		 8278 }
8279
c43203ca
PB		 8280 if (req_immediate_exit) {
8281 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 8282 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 8283 }
d6185f20 8284
8b89fe1f 8285 trace_kvm_entry(vcpu->vcpu_id);
6edaa530 8286 guest_enter_irqoff();
b6c7a5dc 8287
e7517324
WL		 8288 /* The preempt notifier should have taken care of the FPU already. */
8289 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
5f409e20 8290
42dbaa5a 8291 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 8292 set_debugreg(0, 7);
8293 set_debugreg(vcpu->arch.eff_db[0], 0);
8294 set_debugreg(vcpu->arch.eff_db[1], 1);
8295 set_debugreg(vcpu->arch.eff_db[2], 2);
8296 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 8297 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 8298 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 8299 }
b6c7a5dc 8300
851ba692 8301 kvm_x86_ops->run(vcpu);
b6c7a5dc 8302
c77fb5fe
PB		 8303 /*
8304 * Do this here before restoring debug registers on the host. And
8305 * since we do this before handling the vmexit, a DR access vmexit
8306 * can (a) read the correct value of the debug registers, (b) set
8307 * KVM_DEBUGREG_WONT_EXIT again.
8308 */
8309 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 8310 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8311 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 8312 kvm_update_dr0123(vcpu);
8313 kvm_update_dr6(vcpu);
8314 kvm_update_dr7(vcpu);
8315 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 8316 }
8317
24f1e32c
FW		 8318 /*
8319 * If the guest has used debug registers, at least dr7
8320 * will be disabled while returning to the host.
8321 * If we don't have active breakpoints in the host, we don't
8322 * care about the messed up debug address registers. But if
8323 * we have some of them active, restore the old state.
8324 */
59d8eb53 8325 if (hw_breakpoint_active())
24f1e32c 8326 hw_breakpoint_restore();
42dbaa5a 8327
4ba76538 8328 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 8329
6b7e2d09 8330 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8331 smp_wmb();
a547c6db 8332
1e9e2622 8333 kvm_x86_ops->handle_exit_irqoff(vcpu, &exit_fastpath);
b6c7a5dc 8334
d7a08882
SC		 8335 /*
8336 * Consume any pending interrupts, including the possible source of
8337 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8338 * An instruction is required after local_irq_enable() to fully unblock
8339 * interrupts on processors that implement an interrupt shadow, the
8340 * stat.exits increment will do nicely.
8341 */
8342 kvm_before_interrupt(vcpu);
8343 local_irq_enable();
b6c7a5dc 8344 ++vcpu->stat.exits;
d7a08882
SC		 8345 local_irq_disable();
8346 kvm_after_interrupt(vcpu);
b6c7a5dc 8347
f2485b3e 8348 guest_exit_irqoff();
ec0671d5
WL		 8349 if (lapic_in_kernel(vcpu)) {
8350 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8351 if (delta != S64_MIN) {
8352 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8353 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8354 }
8355 }
b6c7a5dc 8356
f2485b3e 8357 local_irq_enable();
b6c7a5dc
HB		 8358 preempt_enable();
8359
f656ce01 8360 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 8361
b6c7a5dc
HB		 8362 /*
8363 * Profile KVM exit RIPs:
8364 */
8365 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 8366 unsigned long rip = kvm_rip_read(vcpu);
8367 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 8368 }
8369
cc578287
ZA		 8370 if (unlikely(vcpu->arch.tsc_always_catchup))
8371 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 8372
5cfb1d5a
MT		 8373 if (vcpu->arch.apic_attention)
8374 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 8375
618232e2 8376 vcpu->arch.gpa_available = false;
1e9e2622 8377 r = kvm_x86_ops->handle_exit(vcpu, exit_fastpath);
d905c069
MT		 8378 return r;
8379
8380cancel_injection:
8381 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 8382 if (unlikely(vcpu->arch.apic_attention))
8383 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 8384out:
8385 return r;
8386}
b6c7a5dc 8387
362c698f
PB		 8388static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8389{
bf9f6ac8
FW		 8390 if (!kvm_arch_vcpu_runnable(vcpu) &&
8391 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 8392 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8393 kvm_vcpu_block(vcpu);
8394 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 8395
8396 if (kvm_x86_ops->post_block)
8397 kvm_x86_ops->post_block(vcpu);
8398
9c8fd1ba
PB		 8399 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8400 return 1;
8401 }
362c698f
PB		 8402
8403 kvm_apic_accept_events(vcpu);
8404 switch(vcpu->arch.mp_state) {
8405 case KVM_MP_STATE_HALTED:
8406 vcpu->arch.pv.pv_unhalted = false;
8407 vcpu->arch.mp_state =
8408 KVM_MP_STATE_RUNNABLE;
b2869f28 8409 /* fall through */
362c698f
PB		 8410 case KVM_MP_STATE_RUNNABLE:
8411 vcpu->arch.apf.halted = false;
8412 break;
8413 case KVM_MP_STATE_INIT_RECEIVED:
8414 break;
8415 default:
8416 return -EINTR;
8417 break;
8418 }
8419 return 1;
8420}
09cec754 8421
5d9bc648
PB		 8422static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8423{
0ad3bed6
PB		 8424 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8425 kvm_x86_ops->check_nested_events(vcpu, false);
8426
5d9bc648
PB		 8427 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8428 !vcpu->arch.apf.halted);
8429}
8430
362c698f 8431static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8432{
8433 int r;
f656ce01 8434 struct kvm *kvm = vcpu->kvm;
d7690175 8435
f656ce01 8436 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8437 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8438
362c698f 8439 for (;;) {
58f800d5 8440 if (kvm_vcpu_running(vcpu)) {
851ba692 8441 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8442 } else {
362c698f 8443 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8444 }
8445
09cec754
GN		 8446 if (r <= 0)
8447 break;
8448
72875d8a 8449 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8450 if (kvm_cpu_has_pending_timer(vcpu))
8451 kvm_inject_pending_timer_irqs(vcpu);
8452
782d422b
MG		 8453 if (dm_request_for_irq_injection(vcpu) &&
8454 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8455 r = 0;
8456 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8457 ++vcpu->stat.request_irq_exits;
362c698f 8458 break;
09cec754 8459 }
af585b92
GN		 8460
8461 kvm_check_async_pf_completion(vcpu);
8462
09cec754
GN		 8463 if (signal_pending(current)) {
8464 r = -EINTR;
851ba692 8465 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8466 ++vcpu->stat.signal_exits;
362c698f 8467 break;
09cec754
GN		 8468 }
8469 if (need_resched()) {
f656ce01 8470 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8471 cond_resched();
f656ce01 8472 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8473 }
b6c7a5dc
HB		 8474 }
8475
f656ce01 8476 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8477
8478 return r;
8479}
8480
716d51ab
GN		 8481static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8482{
8483 int r;
60fc3d02 8484
716d51ab 8485 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8486 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab 8487 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
60fc3d02 8488 return r;
716d51ab
GN		 8489}
8490
8491static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8492{
8493 BUG_ON(!vcpu->arch.pio.count);
8494
8495 return complete_emulated_io(vcpu);
8496}
8497
f78146b0
AK		 8498/*
8499 * Implements the following, as a state machine:
8500 *
8501 * read:
8502 * for each fragment
87da7e66
XG		 8503 * for each mmio piece in the fragment
8504 * write gpa, len
8505 * exit
8506 * copy data
f78146b0
AK		 8507 * execute insn
8508 *
8509 * write:
8510 * for each fragment
87da7e66
XG		 8511 * for each mmio piece in the fragment
8512 * write gpa, len
8513 * copy data
8514 * exit
f78146b0 8515 */
716d51ab 8516static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8517{
8518 struct kvm_run *run = vcpu->run;
f78146b0 8519 struct kvm_mmio_fragment *frag;
87da7e66 8520 unsigned len;
5287f194 8521
716d51ab 8522 BUG_ON(!vcpu->mmio_needed);
5287f194 8523
716d51ab 8524 /* Complete previous fragment */
87da7e66
XG		 8525 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8526 len = min(8u, frag->len);
716d51ab 8527 if (!vcpu->mmio_is_write)
87da7e66
XG		 8528 memcpy(frag->data, run->mmio.data, len);
8529
8530 if (frag->len <= 8) {
8531 /* Switch to the next fragment. */
8532 frag++;
8533 vcpu->mmio_cur_fragment++;
8534 } else {
8535 /* Go forward to the next mmio piece. */
8536 frag->data += len;
8537 frag->gpa += len;
8538 frag->len -= len;
8539 }
8540
a08d3b3b 8541 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8542 vcpu->mmio_needed = 0;
0912c977
PB		 8543
8544 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8545 if (vcpu->mmio_is_write)
716d51ab
GN		 8546 return 1;
8547 vcpu->mmio_read_completed = 1;
8548 return complete_emulated_io(vcpu);
8549 }
87da7e66 8550
716d51ab
GN		 8551 run->exit_reason = KVM_EXIT_MMIO;
8552 run->mmio.phys_addr = frag->gpa;
8553 if (vcpu->mmio_is_write)
87da7e66
XG		 8554 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8555 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8556 run->mmio.is_write = vcpu->mmio_is_write;
8557 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8558 return 0;
5287f194
AK		 8559}
8560
822f312d
SAS		 8561/* Swap (qemu) user FPU context for the guest FPU context. */
8562static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8563{
5f409e20
RR		 8564 fpregs_lock();
8565
d9a710e5 8566 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
822f312d 8567 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8568 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d 8569 ~XFEATURE_MASK_PKRU);
5f409e20
RR		 8570
8571 fpregs_mark_activate();
8572 fpregs_unlock();
8573
822f312d
SAS		 8574 trace_kvm_fpu(1);
8575}
8576
8577/* When vcpu_run ends, restore user space FPU context. */
8578static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8579{
5f409e20
RR		 8580 fpregs_lock();
8581
b666a4b6 8582 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
d9a710e5 8583 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
5f409e20
RR		 8584
8585 fpregs_mark_activate();
8586 fpregs_unlock();
8587
822f312d
SAS		 8588 ++vcpu->stat.fpu_reload;
8589 trace_kvm_fpu(0);
8590}
8591
b6c7a5dc
HB		 8592int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8593{
8594 int r;
b6c7a5dc 8595
accb757d 8596 vcpu_load(vcpu);
20b7035c 8597 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8598 kvm_load_guest_fpu(vcpu);
8599
a4535290 8600 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8601 if (kvm_run->immediate_exit) {
8602 r = -EINTR;
8603 goto out;
8604 }
b6c7a5dc 8605 kvm_vcpu_block(vcpu);
66450a21 8606 kvm_apic_accept_events(vcpu);
72875d8a 8607 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8608 r = -EAGAIN;
a0595000
JS		 8609 if (signal_pending(current)) {
8610 r = -EINTR;
8611 vcpu->run->exit_reason = KVM_EXIT_INTR;
8612 ++vcpu->stat.signal_exits;
8613 }
ac9f6dc0 8614 goto out;
b6c7a5dc
HB		 8615 }
8616
01643c51
KH		 8617 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8618 r = -EINVAL;
8619 goto out;
8620 }
8621
8622 if (vcpu->run->kvm_dirty_regs) {
8623 r = sync_regs(vcpu);
8624 if (r != 0)
8625 goto out;
8626 }
8627
b6c7a5dc 8628 /* re-sync apic's tpr */
35754c98 8629 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8630 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8631 r = -EINVAL;
8632 goto out;
8633 }
8634 }
b6c7a5dc 8635
716d51ab
GN		 8636 if (unlikely(vcpu->arch.complete_userspace_io)) {
8637 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8638 vcpu->arch.complete_userspace_io = NULL;
8639 r = cui(vcpu);
8640 if (r <= 0)
5663d8f9 8641 goto out;
716d51ab
GN		 8642 } else
8643 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8644
460df4c1
PB		 8645 if (kvm_run->immediate_exit)
8646 r = -EINTR;
8647 else
8648 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8649
8650out:
5663d8f9 8651 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8652 if (vcpu->run->kvm_valid_regs)
8653 store_regs(vcpu);
f1d86e46 8654 post_kvm_run_save(vcpu);
20b7035c 8655 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8656
accb757d 8657 vcpu_put(vcpu);
b6c7a5dc
HB		 8658 return r;
8659}
8660
01643c51 8661static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8662{
7ae441ea
GN		 8663 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8664 /*
8665 * We are here if userspace calls get_regs() in the middle of
8666 * instruction emulation. Registers state needs to be copied
4a969980 8667 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8668 * that usually, but some bad designed PV devices (vmware
8669 * backdoor interface) need this to work
8670 */
dd856efa 8671 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8672 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8673 }
de3cd117
SC		 8674 regs->rax = kvm_rax_read(vcpu);
8675 regs->rbx = kvm_rbx_read(vcpu);
8676 regs->rcx = kvm_rcx_read(vcpu);
8677 regs->rdx = kvm_rdx_read(vcpu);
8678 regs->rsi = kvm_rsi_read(vcpu);
8679 regs->rdi = kvm_rdi_read(vcpu);
e9c16c78 8680 regs->rsp = kvm_rsp_read(vcpu);
de3cd117 8681 regs->rbp = kvm_rbp_read(vcpu);
b6c7a5dc 8682#ifdef CONFIG_X86_64
de3cd117
SC		 8683 regs->r8 = kvm_r8_read(vcpu);
8684 regs->r9 = kvm_r9_read(vcpu);
8685 regs->r10 = kvm_r10_read(vcpu);
8686 regs->r11 = kvm_r11_read(vcpu);
8687 regs->r12 = kvm_r12_read(vcpu);
8688 regs->r13 = kvm_r13_read(vcpu);
8689 regs->r14 = kvm_r14_read(vcpu);
8690 regs->r15 = kvm_r15_read(vcpu);
b6c7a5dc
HB		 8691#endif
8692
5fdbf976 8693 regs->rip = kvm_rip_read(vcpu);
91586a3b 8694 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8695}
b6c7a5dc 8696
01643c51
KH		 8697int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8698{
8699 vcpu_load(vcpu);
8700 __get_regs(vcpu, regs);
1fc9b76b 8701 vcpu_put(vcpu);
b6c7a5dc
HB		 8702 return 0;
8703}
8704
01643c51 8705static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8706{
7ae441ea
GN		 8707 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8708 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8709
de3cd117
SC		 8710 kvm_rax_write(vcpu, regs->rax);
8711 kvm_rbx_write(vcpu, regs->rbx);
8712 kvm_rcx_write(vcpu, regs->rcx);
8713 kvm_rdx_write(vcpu, regs->rdx);
8714 kvm_rsi_write(vcpu, regs->rsi);
8715 kvm_rdi_write(vcpu, regs->rdi);
e9c16c78 8716 kvm_rsp_write(vcpu, regs->rsp);
de3cd117 8717 kvm_rbp_write(vcpu, regs->rbp);
b6c7a5dc 8718#ifdef CONFIG_X86_64
de3cd117
SC		 8719 kvm_r8_write(vcpu, regs->r8);
8720 kvm_r9_write(vcpu, regs->r9);
8721 kvm_r10_write(vcpu, regs->r10);
8722 kvm_r11_write(vcpu, regs->r11);
8723 kvm_r12_write(vcpu, regs->r12);
8724 kvm_r13_write(vcpu, regs->r13);
8725 kvm_r14_write(vcpu, regs->r14);
8726 kvm_r15_write(vcpu, regs->r15);
b6c7a5dc
HB		 8727#endif
8728
5fdbf976 8729 kvm_rip_write(vcpu, regs->rip);
d73235d1 8730 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8731
b4f14abd
JK		 8732 vcpu->arch.exception.pending = false;
8733
3842d135 8734 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8735}
3842d135 8736
01643c51
KH		 8737int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8738{
8739 vcpu_load(vcpu);
8740 __set_regs(vcpu, regs);
875656fe 8741 vcpu_put(vcpu);
b6c7a5dc
HB		 8742 return 0;
8743}
8744
b6c7a5dc
HB		 8745void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8746{
8747 struct kvm_segment cs;
8748
3e6e0aab 8749 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8750 *db = cs.db;
8751 *l = cs.l;
8752}
8753EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8754
01643c51 8755static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8756{
89a27f4d 8757 struct desc_ptr dt;
b6c7a5dc 8758
3e6e0aab
GT		 8759 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8760 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8761 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8762 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8763 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8764 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8765
3e6e0aab
GT		 8766 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8767 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8768
8769 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8770 sregs->idt.limit = dt.size;
8771 sregs->idt.base = dt.address;
b6c7a5dc 8772 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8773 sregs->gdt.limit = dt.size;
8774 sregs->gdt.base = dt.address;
b6c7a5dc 8775
4d4ec087 8776 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8777 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8778 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8779 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8780 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8781 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8782 sregs->apic_base = kvm_get_apic_base(vcpu);
8783
0e96f31e 8784 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8785
04140b41 8786 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8787 set_bit(vcpu->arch.interrupt.nr,
8788 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8789}
16d7a191 8790
01643c51
KH		 8791int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8792 struct kvm_sregs *sregs)
8793{
8794 vcpu_load(vcpu);
8795 __get_sregs(vcpu, sregs);
bcdec41c 8796 vcpu_put(vcpu);
b6c7a5dc
HB		 8797 return 0;
8798}
8799
62d9f0db
MT		 8800int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8801 struct kvm_mp_state *mp_state)
8802{
fd232561 8803 vcpu_load(vcpu);
f958bd23
SC		 8804 if (kvm_mpx_supported())
8805 kvm_load_guest_fpu(vcpu);
fd232561 8806
66450a21 8807 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8808 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8809 vcpu->arch.pv.pv_unhalted)
8810 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8811 else
8812 mp_state->mp_state = vcpu->arch.mp_state;
8813
f958bd23
SC		 8814 if (kvm_mpx_supported())
8815 kvm_put_guest_fpu(vcpu);
fd232561 8816 vcpu_put(vcpu);
62d9f0db
MT		 8817 return 0;
8818}
8819
8820int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8821 struct kvm_mp_state *mp_state)
8822{
e83dff5e
CD		 8823 int ret = -EINVAL;
8824
8825 vcpu_load(vcpu);
8826
bce87cce 8827 if (!lapic_in_kernel(vcpu) &&
66450a21 8828 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8829 goto out;
66450a21 8830
27cbe7d6
LA		 8831 /*
8832 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8833 * INIT state; latched init should be reported using
8834 * KVM_SET_VCPU_EVENTS, so reject it here.
8835 */
8836 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
28bf2888
DH		 8837 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8838 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8839 goto out;
28bf2888 8840
66450a21
JK		 8841 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8842 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8843 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8844 } else
8845 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8846 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8847
8848 ret = 0;
8849out:
8850 vcpu_put(vcpu);
8851 return ret;
62d9f0db
MT		 8852}
8853
7f3d35fd
KW		 8854int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8855 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8856{
9d74191a 8857 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8858 int ret;
e01c2426 8859
8ec4722d 8860 init_emulate_ctxt(vcpu);
c697518a 8861
7f3d35fd 8862 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8863 has_error_code, error_code);
1051778f
SC		 8864 if (ret) {
8865 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8866 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8867 vcpu->run->internal.ndata = 0;
60fc3d02 8868 return 0;
1051778f 8869 }
37817f29 8870
9d74191a
TY		 8871 kvm_rip_write(vcpu, ctxt->eip);
8872 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8873 kvm_make_request(KVM_REQ_EVENT, vcpu);
60fc3d02 8874 return 1;
37817f29
IE		 8875}
8876EXPORT_SYMBOL_GPL(kvm_task_switch);
8877
3140c156 8878static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8879{
37b95951 8880 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8881 /*
8882 * When EFER.LME and CR0.PG are set, the processor is in
8883 * 64-bit mode (though maybe in a 32-bit code segment).
8884 * CR4.PAE and EFER.LMA must be set.
8885 */
37b95951 8886 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8887 || !(sregs->efer & EFER_LMA))
8888 return -EINVAL;
8889 } else {
8890 /*
8891 * Not in 64-bit mode: EFER.LMA is clear and the code
8892 * segment cannot be 64-bit.
8893 */
8894 if (sregs->efer & EFER_LMA || sregs->cs.l)
8895 return -EINVAL;
8896 }
8897
3ca94192 8898 return kvm_valid_cr4(vcpu, sregs->cr4);
f2981033
LT		 8899}
8900
01643c51 8901static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8902{
58cb628d 8903 struct msr_data apic_base_msr;
b6c7a5dc 8904 int mmu_reset_needed = 0;
c4d21882 8905 int cpuid_update_needed = 0;
63f42e02 8906 int pending_vec, max_bits, idx;
89a27f4d 8907 struct desc_ptr dt;
b4ef9d4e
CD		 8908 int ret = -EINVAL;
8909
f2981033 8910 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8911 goto out;
f2981033 8912
d3802286
JM		 8913 apic_base_msr.data = sregs->apic_base;
8914 apic_base_msr.host_initiated = true;
8915 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8916 goto out;
6d1068b3 8917
89a27f4d
GN		 8918 dt.size = sregs->idt.limit;
8919 dt.address = sregs->idt.base;
b6c7a5dc 8920 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8921 dt.size = sregs->gdt.limit;
8922 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8923 kvm_x86_ops->set_gdt(vcpu, &dt);
8924
ad312c7c 8925 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8926 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8927 vcpu->arch.cr3 = sregs->cr3;
cb3c1e2f 8928 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
b6c7a5dc 8929
2d3ad1f4 8930 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8931
f6801dff 8932 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8933 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8934
4d4ec087 8935 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8936 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8937 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8938
fc78f519 8939 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8940 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8941 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8942 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8943 if (cpuid_update_needed)
00b27a3e 8944 kvm_update_cpuid(vcpu);
63f42e02
XG		 8945
8946 idx = srcu_read_lock(&vcpu->kvm->srcu);
bf03d4f9 8947 if (is_pae_paging(vcpu)) {
9f8fe504 8948 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8949 mmu_reset_needed = 1;
8950 }
63f42e02 8951 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8952
8953 if (mmu_reset_needed)
8954 kvm_mmu_reset_context(vcpu);
8955
a50abc3b 8956 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8957 pending_vec = find_first_bit(
8958 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8959 if (pending_vec < max_bits) {
66fd3f7f 8960 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8961 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8962 }
8963
3e6e0aab
GT		 8964 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8965 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8966 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8967 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8968 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8969 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8970
3e6e0aab
GT		 8971 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8972 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8973
5f0269f5
ME		 8974 update_cr8_intercept(vcpu);
8975
9c3e4aab 8976 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8977 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8978 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8979 !is_protmode(vcpu))
9c3e4aab
MT		 8980 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8981
3842d135
AK		 8982 kvm_make_request(KVM_REQ_EVENT, vcpu);
8983
b4ef9d4e
CD		 8984 ret = 0;
8985out:
01643c51
KH		 8986 return ret;
8987}
8988
8989int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8990 struct kvm_sregs *sregs)
8991{
8992 int ret;
8993
8994 vcpu_load(vcpu);
8995 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8996 vcpu_put(vcpu);
8997 return ret;
b6c7a5dc
HB		 8998}
8999
d0bfb940
JK		 9000int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9001 struct kvm_guest_debug *dbg)
b6c7a5dc 9002{
355be0b9 9003 unsigned long rflags;
ae675ef0 9004 int i, r;
b6c7a5dc 9005
66b56562
CD		 9006 vcpu_load(vcpu);
9007
4f926bf2
JK		 9008 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9009 r = -EBUSY;
9010 if (vcpu->arch.exception.pending)
2122ff5e 9011 goto out;
4f926bf2
JK		 9012 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9013 kvm_queue_exception(vcpu, DB_VECTOR);
9014 else
9015 kvm_queue_exception(vcpu, BP_VECTOR);
9016 }
9017
91586a3b
JK		 9018 /*
9019 * Read rflags as long as potentially injected trace flags are still
9020 * filtered out.
9021 */
9022 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 9023
9024 vcpu->guest_debug = dbg->control;
9025 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9026 vcpu->guest_debug = 0;
9027
9028 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 9029 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9030 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 9031 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 9032 } else {
9033 for (i = 0; i < KVM_NR_DB_REGS; i++)
9034 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 9035 }
c8639010 9036 kvm_update_dr7(vcpu);
ae675ef0 9037
f92653ee
JK		 9038 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9039 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9040 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 9041
91586a3b
JK		 9042 /*
9043 * Trigger an rflags update that will inject or remove the trace
9044 * flags.
9045 */
9046 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 9047
a96036b8 9048 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 9049
4f926bf2 9050 r = 0;
d0bfb940 9051
2122ff5e 9052out:
66b56562 9053 vcpu_put(vcpu);
b6c7a5dc
HB		 9054 return r;
9055}
9056
8b006791
ZX		 9057/*
9058 * Translate a guest virtual address to a guest physical address.
9059 */
9060int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9061 struct kvm_translation *tr)
9062{
9063 unsigned long vaddr = tr->linear_address;
9064 gpa_t gpa;
f656ce01 9065 int idx;
8b006791 9066
1da5b61d
CD		 9067 vcpu_load(vcpu);
9068
f656ce01 9069 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 9070 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 9071 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 9072 tr->physical_address = gpa;
9073 tr->valid = gpa != UNMAPPED_GVA;
9074 tr->writeable = 1;
9075 tr->usermode = 0;
8b006791 9076
1da5b61d 9077 vcpu_put(vcpu);
8b006791
ZX		 9078 return 0;
9079}
9080
d0752060
HB		 9081int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9082{
1393123e 9083 struct fxregs_state *fxsave;
d0752060 9084
1393123e 9085 vcpu_load(vcpu);
d0752060 9086
b666a4b6 9087 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 9088 memcpy(fpu->fpr, fxsave->st_space, 128);
9089 fpu->fcw = fxsave->cwd;
9090 fpu->fsw = fxsave->swd;
9091 fpu->ftwx = fxsave->twd;
9092 fpu->last_opcode = fxsave->fop;
9093 fpu->last_ip = fxsave->rip;
9094 fpu->last_dp = fxsave->rdp;
0e96f31e 9095 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 9096
1393123e 9097 vcpu_put(vcpu);
d0752060
HB		 9098 return 0;
9099}
9100
9101int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9102{
6a96bc7f
CD		 9103 struct fxregs_state *fxsave;
9104
9105 vcpu_load(vcpu);
9106
b666a4b6 9107 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 9108
d0752060
HB		 9109 memcpy(fxsave->st_space, fpu->fpr, 128);
9110 fxsave->cwd = fpu->fcw;
9111 fxsave->swd = fpu->fsw;
9112 fxsave->twd = fpu->ftwx;
9113 fxsave->fop = fpu->last_opcode;
9114 fxsave->rip = fpu->last_ip;
9115 fxsave->rdp = fpu->last_dp;
0e96f31e 9116 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 9117
6a96bc7f 9118 vcpu_put(vcpu);
d0752060
HB		 9119 return 0;
9120}
9121
01643c51
KH		 9122static void store_regs(struct kvm_vcpu *vcpu)
9123{
9124 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9125
9126 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9127 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9128
9129 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9130 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9131
9132 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9133 kvm_vcpu_ioctl_x86_get_vcpu_events(
9134 vcpu, &vcpu->run->s.regs.events);
9135}
9136
9137static int sync_regs(struct kvm_vcpu *vcpu)
9138{
9139 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9140 return -EINVAL;
9141
9142 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9143 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9144 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9145 }
9146 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9147 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9148 return -EINVAL;
9149 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9150 }
9151 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9152 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9153 vcpu, &vcpu->run->s.regs.events))
9154 return -EINVAL;
9155 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9156 }
9157
9158 return 0;
9159}
9160
0ee6a517 9161static void fx_init(struct kvm_vcpu *vcpu)
d0752060 9162{
b666a4b6 9163 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 9164 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 9165 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 9166 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 9167
2acf923e
DC		 9168 /*
9169 * Ensure guest xcr0 is valid for loading
9170 */
d91cab78 9171 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 9172
ad312c7c 9173 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 9174}
d0752060 9175
897cc38e
SC		 9176int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9177{
9178 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9179 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9180 "guest TSC will not be reliable\n");
9181
9182 return 0;
9183}
9184
e529ef66 9185int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
e9b11c17 9186{
95a0d01e
SC		 9187 struct page *page;
9188 int r;
5f73db11 9189
95a0d01e
SC		 9190 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9191 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9192 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9193 else
9194 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9195
9196 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9197
9198 r = kvm_mmu_create(vcpu);
9199 if (r < 0)
9200 return r;
9201
9202 if (irqchip_in_kernel(vcpu->kvm)) {
9203 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu->kvm);
9204 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9205 if (r < 0)
9206 goto fail_mmu_destroy;
9207 } else
9208 static_key_slow_inc(&kvm_no_apic_vcpu);
9209
9210 r = -ENOMEM;
9211
9212 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9213 if (!page)
9214 goto fail_free_lapic;
9215 vcpu->arch.pio_data = page_address(page);
9216
9217 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9218 GFP_KERNEL_ACCOUNT);
9219 if (!vcpu->arch.mce_banks)
9220 goto fail_free_pio_data;
9221 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9222
9223 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9224 GFP_KERNEL_ACCOUNT))
9225 goto fail_free_mce_banks;
9226
9227 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9228 GFP_KERNEL_ACCOUNT);
9229 if (!vcpu->arch.user_fpu) {
9230 pr_err("kvm: failed to allocate userspace's fpu\n");
9231 goto free_wbinvd_dirty_mask;
9232 }
9233
9234 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9235 GFP_KERNEL_ACCOUNT);
9236 if (!vcpu->arch.guest_fpu) {
9237 pr_err("kvm: failed to allocate vcpu's fpu\n");
9238 goto free_user_fpu;
9239 }
9240 fx_init(vcpu);
9241
9242 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9243
9244 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9245
9246 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9247
9248 kvm_async_pf_hash_reset(vcpu);
9249 kvm_pmu_init(vcpu);
9250
9251 vcpu->arch.pending_external_vector = -1;
9252 vcpu->arch.preempted_in_kernel = false;
9253
9254 kvm_hv_vcpu_init(vcpu);
9255
9256 r = kvm_x86_ops->vcpu_create(vcpu);
9257 if (r)
9258 goto free_guest_fpu;
e9b11c17 9259
0cf9135b 9260 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 9261 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 9262 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 9263 vcpu_load(vcpu);
d28bc9dd 9264 kvm_vcpu_reset(vcpu, false);
e1732991 9265 kvm_init_mmu(vcpu, false);
e9b11c17 9266 vcpu_put(vcpu);
ec7660cc 9267 return 0;
95a0d01e
SC		 9268
9269free_guest_fpu:
9270 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9271free_user_fpu:
9272 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9273free_wbinvd_dirty_mask:
9274 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9275fail_free_mce_banks:
9276 kfree(vcpu->arch.mce_banks);
9277fail_free_pio_data:
9278 free_page((unsigned long)vcpu->arch.pio_data);
9279fail_free_lapic:
9280 kvm_free_lapic(vcpu);
9281fail_mmu_destroy:
9282 kvm_mmu_destroy(vcpu);
9283 return r;
e9b11c17
ZX		 9284}
9285
31928aa5 9286void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 9287{
8fe8ab46 9288 struct msr_data msr;
332967a3 9289 struct kvm *kvm = vcpu->kvm;
42897d86 9290
d3457c87
RK		 9291 kvm_hv_vcpu_postcreate(vcpu);
9292
ec7660cc 9293 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 9294 return;
ec7660cc 9295 vcpu_load(vcpu);
8fe8ab46
WA		 9296 msr.data = 0x0;
9297 msr.index = MSR_IA32_TSC;
9298 msr.host_initiated = true;
9299 kvm_write_tsc(vcpu, &msr);
42897d86 9300 vcpu_put(vcpu);
2d5ba19b
MT		 9301
9302 /* poll control enabled by default */
9303 vcpu->arch.msr_kvm_poll_control = 1;
9304
ec7660cc 9305 mutex_unlock(&vcpu->mutex);
42897d86 9306
630994b3
MT		 9307 if (!kvmclock_periodic_sync)
9308 return;
9309
332967a3
AJ		 9310 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9311 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 9312}
9313
d40ccc62 9314void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 9315{
95a0d01e
SC		 9316 int idx;
9317
50b143e1
SC		 9318 kvmclock_reset(vcpu);
9319
9320 kvm_x86_ops->vcpu_free(vcpu);
9321
50b143e1
SC		 9322 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9323 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9324 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
95a0d01e
SC		 9325
9326 kvm_hv_vcpu_uninit(vcpu);
9327 kvm_pmu_destroy(vcpu);
9328 kfree(vcpu->arch.mce_banks);
9329 kvm_free_lapic(vcpu);
9330 idx = srcu_read_lock(&vcpu->kvm->srcu);
9331 kvm_mmu_destroy(vcpu);
9332 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9333 free_page((unsigned long)vcpu->arch.pio_data);
9334 if (!lapic_in_kernel(vcpu))
9335 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17
ZX		 9336}
9337
d28bc9dd 9338void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 9339{
b7e31be3
RK		 9340 kvm_lapic_reset(vcpu, init_event);
9341
e69fab5d
PB		 9342 vcpu->arch.hflags = 0;
9343
c43203ca 9344 vcpu->arch.smi_pending = 0;
52797bf9 9345 vcpu->arch.smi_count = 0;
7460fb4a
AK		 9346 atomic_set(&vcpu->arch.nmi_queued, 0);
9347 vcpu->arch.nmi_pending = 0;
448fa4a9 9348 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 9349 kvm_clear_interrupt_queue(vcpu);
9350 kvm_clear_exception_queue(vcpu);
448fa4a9 9351
42dbaa5a 9352 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 9353 kvm_update_dr0123(vcpu);
6f43ed01 9354 vcpu->arch.dr6 = DR6_INIT;
73aaf249 9355 kvm_update_dr6(vcpu);
42dbaa5a 9356 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 9357 kvm_update_dr7(vcpu);
42dbaa5a 9358
1119022c
NA		 9359 vcpu->arch.cr2 = 0;
9360
3842d135 9361 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 9362 vcpu->arch.apf.msr_val = 0;
c9aaa895 9363 vcpu->arch.st.msr_val = 0;
3842d135 9364
12f9a48f
GC		 9365 kvmclock_reset(vcpu);
9366
af585b92
GN		 9367 kvm_clear_async_pf_completion_queue(vcpu);
9368 kvm_async_pf_hash_reset(vcpu);
9369 vcpu->arch.apf.halted = false;
3842d135 9370
a554d207
WL		 9371 if (kvm_mpx_supported()) {
9372 void *mpx_state_buffer;
9373
9374 /*
9375 * To avoid have the INIT path from kvm_apic_has_events() that be
9376 * called with loaded FPU and does not let userspace fix the state.
9377 */
f775b13e
RR		 9378 if (init_event)
9379 kvm_put_guest_fpu(vcpu);
b666a4b6 9380 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9381 XFEATURE_BNDREGS);
a554d207
WL		 9382 if (mpx_state_buffer)
9383 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 9384 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9385 XFEATURE_BNDCSR);
a554d207
WL		 9386 if (mpx_state_buffer)
9387 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 9388 if (init_event)
9389 kvm_load_guest_fpu(vcpu);
a554d207
WL		 9390 }
9391
64d60670 9392 if (!init_event) {
d28bc9dd 9393 kvm_pmu_reset(vcpu);
64d60670 9394 vcpu->arch.smbase = 0x30000;
db2336a8 9395
db2336a8 9396 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 9397
9398 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 9399 }
f5132b01 9400
66f7b72e
JS		 9401 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9402 vcpu->arch.regs_avail = ~0;
9403 vcpu->arch.regs_dirty = ~0;
9404
a554d207
WL		 9405 vcpu->arch.ia32_xss = 0;
9406
d28bc9dd 9407 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 9408}
9409
2b4a273b 9410void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 9411{
9412 struct kvm_segment cs;
9413
9414 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9415 cs.selector = vector << 8;
9416 cs.base = vector << 12;
9417 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9418 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 9419}
9420
13a34e06 9421int kvm_arch_hardware_enable(void)
e9b11c17 9422{
ca84d1a2
ZA		 9423 struct kvm *kvm;
9424 struct kvm_vcpu *vcpu;
9425 int i;
0dd6a6ed
ZA		 9426 int ret;
9427 u64 local_tsc;
9428 u64 max_tsc = 0;
9429 bool stable, backwards_tsc = false;
18863bdd
AK		 9430
9431 kvm_shared_msr_cpu_online();
13a34e06 9432 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 9433 if (ret != 0)
9434 return ret;
9435
4ea1636b 9436 local_tsc = rdtsc();
b0c39dc6 9437 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 9438 list_for_each_entry(kvm, &vm_list, vm_list) {
9439 kvm_for_each_vcpu(i, vcpu, kvm) {
9440 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 9441 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9442 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9443 backwards_tsc = true;
9444 if (vcpu->arch.last_host_tsc > max_tsc)
9445 max_tsc = vcpu->arch.last_host_tsc;
9446 }
9447 }
9448 }
9449
9450 /*
9451 * Sometimes, even reliable TSCs go backwards. This happens on
9452 * platforms that reset TSC during suspend or hibernate actions, but
9453 * maintain synchronization. We must compensate. Fortunately, we can
9454 * detect that condition here, which happens early in CPU bringup,
9455 * before any KVM threads can be running. Unfortunately, we can't
9456 * bring the TSCs fully up to date with real time, as we aren't yet far
9457 * enough into CPU bringup that we know how much real time has actually
9285ec4c 9458 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
0dd6a6ed
ZA		 9459 * variables that haven't been updated yet.
9460 *
9461 * So we simply find the maximum observed TSC above, then record the
9462 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9463 * the adjustment will be applied. Note that we accumulate
9464 * adjustments, in case multiple suspend cycles happen before some VCPU
9465 * gets a chance to run again. In the event that no KVM threads get a
9466 * chance to run, we will miss the entire elapsed period, as we'll have
9467 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9468 * loose cycle time. This isn't too big a deal, since the loss will be
9469 * uniform across all VCPUs (not to mention the scenario is extremely
9470 * unlikely). It is possible that a second hibernate recovery happens
9471 * much faster than a first, causing the observed TSC here to be
9472 * smaller; this would require additional padding adjustment, which is
9473 * why we set last_host_tsc to the local tsc observed here.
9474 *
9475 * N.B. - this code below runs only on platforms with reliable TSC,
9476 * as that is the only way backwards_tsc is set above. Also note
9477 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9478 * have the same delta_cyc adjustment applied if backwards_tsc
9479 * is detected. Note further, this adjustment is only done once,
9480 * as we reset last_host_tsc on all VCPUs to stop this from being
9481 * called multiple times (one for each physical CPU bringup).
9482 *
4a969980 9483 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 9484 * will be compensated by the logic in vcpu_load, which sets the TSC to
9485 * catchup mode. This will catchup all VCPUs to real time, but cannot
9486 * guarantee that they stay in perfect synchronization.
9487 */
9488 if (backwards_tsc) {
9489 u64 delta_cyc = max_tsc - local_tsc;
9490 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 9491 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 9492 kvm_for_each_vcpu(i, vcpu, kvm) {
9493 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9494 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 9495 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9496 }
9497
9498 /*
9499 * We have to disable TSC offset matching.. if you were
9500 * booting a VM while issuing an S4 host suspend....
9501 * you may have some problem. Solving this issue is
9502 * left as an exercise to the reader.
9503 */
9504 kvm->arch.last_tsc_nsec = 0;
9505 kvm->arch.last_tsc_write = 0;
9506 }
9507
9508 }
9509 return 0;
e9b11c17
ZX		 9510}
9511
13a34e06 9512void kvm_arch_hardware_disable(void)
e9b11c17 9513{
13a34e06
RK		 9514 kvm_x86_ops->hardware_disable();
9515 drop_user_return_notifiers();
e9b11c17
ZX		 9516}
9517
9518int kvm_arch_hardware_setup(void)
9519{
9e9c3fe4
NA		 9520 int r;
9521
9522 r = kvm_x86_ops->hardware_setup();
9523 if (r != 0)
9524 return r;
9525
b11306b5
SC		 9526 cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data);
9527
35181e86
HZ		 9528 if (kvm_has_tsc_control) {
9529 /*
9530 * Make sure the user can only configure tsc_khz values that
9531 * fit into a signed integer.
273ba457 9532 * A min value is not calculated because it will always
35181e86
HZ		 9533 * be 1 on all machines.
9534 */
9535 u64 max = min(0x7fffffffULL,
9536 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9537 kvm_max_guest_tsc_khz = max;
9538
ad721883 9539 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9540 }
ad721883 9541
139a12cf
AL		 9542 if (boot_cpu_has(X86_FEATURE_XSAVES))
9543 rdmsrl(MSR_IA32_XSS, host_xss);
9544
9e9c3fe4
NA		 9545 kvm_init_msr_list();
9546 return 0;
e9b11c17
ZX		 9547}
9548
9549void kvm_arch_hardware_unsetup(void)
9550{
9551 kvm_x86_ops->hardware_unsetup();
9552}
9553
f257d6dc 9554int kvm_arch_check_processor_compat(void)
e9b11c17 9555{
f1cdecf5
SC		 9556 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9557
9558 WARN_ON(!irqs_disabled());
9559
9560 if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits)
9561 return -EIO;
9562
f257d6dc 9563 return kvm_x86_ops->check_processor_compatibility();
d71ba788
PB		 9564}
9565
9566bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9567{
9568 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9569}
9570EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9571
9572bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9573{
9574 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9575}
9576
54e9818f 9577struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9578EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9579
e790d9ef
RK		 9580void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9581{
b35e5548
LX		 9582 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9583
c595ceee 9584 vcpu->arch.l1tf_flush_l1d = true;
b35e5548
LX		 9585 if (pmu->version && unlikely(pmu->event_count)) {
9586 pmu->need_cleanup = true;
9587 kvm_make_request(KVM_REQ_PMU, vcpu);
9588 }
ae97a3b8 9589 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9590}
9591
e08b9637 9592int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9593{
e08b9637
CO		 9594 if (type)
9595 return -EINVAL;
9596
6ef768fa 9597 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9598 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10605204 9599 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
1aa9b957 9600 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
4d5c5d0f 9601 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9602 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9603
5550af4d
SY		 9604 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9605 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9606 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9607 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9608 &kvm->arch.irq_sources_bitmap);
5550af4d 9609
038f8c11 9610 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9611 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9612 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9613
9285ec4c 9614 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
d828199e 9615 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9616
6fbbde9a
DS		 9617 kvm->arch.guest_can_read_msr_platform_info = true;
9618
7e44e449 9619 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9620 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9621
cbc0236a 9622 kvm_hv_init_vm(kvm);
0eb05bf2 9623 kvm_page_track_init(kvm);
13d268ca 9624 kvm_mmu_init_vm(kvm);
0eb05bf2 9625
92735b1b 9626 return kvm_x86_ops->vm_init(kvm);
d19a9cd2
ZX		 9627}
9628
1aa9b957
JS		 9629int kvm_arch_post_init_vm(struct kvm *kvm)
9630{
9631 return kvm_mmu_post_init_vm(kvm);
9632}
9633
d19a9cd2
ZX		 9634static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9635{
ec7660cc 9636 vcpu_load(vcpu);
d19a9cd2
ZX		 9637 kvm_mmu_unload(vcpu);
9638 vcpu_put(vcpu);
9639}
9640
9641static void kvm_free_vcpus(struct kvm *kvm)
9642{
9643 unsigned int i;
988a2cae 9644 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9645
9646 /*
9647 * Unpin any mmu pages first.
9648 */
af585b92
GN		 9649 kvm_for_each_vcpu(i, vcpu, kvm) {
9650 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9651 kvm_unload_vcpu_mmu(vcpu);
af585b92 9652 }
988a2cae 9653 kvm_for_each_vcpu(i, vcpu, kvm)
4543bdc0 9654 kvm_vcpu_destroy(vcpu);
988a2cae
GN		 9655
9656 mutex_lock(&kvm->lock);
9657 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9658 kvm->vcpus[i] = NULL;
d19a9cd2 9659
988a2cae
GN		 9660 atomic_set(&kvm->online_vcpus, 0);
9661 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9662}
9663
ad8ba2cd
SY		 9664void kvm_arch_sync_events(struct kvm *kvm)
9665{
332967a3 9666 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9667 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9668 kvm_free_pit(kvm);
ad8ba2cd
SY		 9669}
9670
1d8007bd 9671int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9672{
9673 int i, r;
25188b99 9674 unsigned long hva;
f0d648bd
PB		 9675 struct kvm_memslots *slots = kvm_memslots(kvm);
9676 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9677
9678 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9679 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9680 return -EINVAL;
9da0e4d5 9681
f0d648bd
PB		 9682 slot = id_to_memslot(slots, id);
9683 if (size) {
b21629da 9684 if (slot->npages)
f0d648bd
PB		 9685 return -EEXIST;
9686
9687 /*
9688 * MAP_SHARED to prevent internal slot pages from being moved
9689 * by fork()/COW.
9690 */
9691 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9692 MAP_SHARED | MAP_ANONYMOUS, 0);
9693 if (IS_ERR((void *)hva))
9694 return PTR_ERR((void *)hva);
9695 } else {
9696 if (!slot->npages)
9697 return 0;
9698
9699 hva = 0;
9700 }
9701
9702 old = *slot;
9da0e4d5 9703 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9704 struct kvm_userspace_memory_region m;
9da0e4d5 9705
1d8007bd
PB		 9706 m.slot = id | (i << 16);
9707 m.flags = 0;
9708 m.guest_phys_addr = gpa;
f0d648bd 9709 m.userspace_addr = hva;
1d8007bd 9710 m.memory_size = size;
9da0e4d5
PB		 9711 r = __kvm_set_memory_region(kvm, &m);
9712 if (r < 0)
9713 return r;
9714 }
9715
103c763c
EB		 9716 if (!size)
9717 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9718
9da0e4d5
PB		 9719 return 0;
9720}
9721EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9722
1d8007bd 9723int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9724{
9725 int r;
9726
9727 mutex_lock(&kvm->slots_lock);
1d8007bd 9728 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9729 mutex_unlock(&kvm->slots_lock);
9730
9731 return r;
9732}
9733EXPORT_SYMBOL_GPL(x86_set_memory_region);
9734
1aa9b957
JS		 9735void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9736{
9737 kvm_mmu_pre_destroy_vm(kvm);
9738}
9739
d19a9cd2
ZX		 9740void kvm_arch_destroy_vm(struct kvm *kvm)
9741{
27469d29
AH		 9742 if (current->mm == kvm->mm) {
9743 /*
9744 * Free memory regions allocated on behalf of userspace,
9745 * unless the the memory map has changed due to process exit
9746 * or fd copying.
9747 */
1d8007bd
PB		 9748 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9749 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9750 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9751 }
03543133
SS		 9752 if (kvm_x86_ops->vm_destroy)
9753 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9754 kvm_pic_destroy(kvm);
9755 kvm_ioapic_destroy(kvm);
d19a9cd2 9756 kvm_free_vcpus(kvm);
af1bae54 9757 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
66bb8a06 9758 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
13d268ca 9759 kvm_mmu_uninit_vm(kvm);
2beb6dad 9760 kvm_page_track_cleanup(kvm);
cbc0236a 9761 kvm_hv_destroy_vm(kvm);
d19a9cd2 9762}
0de10343 9763
5587027c 9764void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9765 struct kvm_memory_slot *dont)
9766{
9767 int i;
9768
d89cc617
TY		 9769 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9770 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9771 kvfree(free->arch.rmap[i]);
d89cc617 9772 free->arch.rmap[i] = NULL;
77d11309 9773 }
d89cc617
TY		 9774 if (i == 0)
9775 continue;
9776
9777 if (!dont || free->arch.lpage_info[i - 1] !=
9778 dont->arch.lpage_info[i - 1]) {
548ef284 9779 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9780 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9781 }
9782 }
21ebbeda
XG		 9783
9784 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9785}
9786
5587027c
AK		 9787int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9788 unsigned long npages)
db3fe4eb
TY		 9789{
9790 int i;
9791
d89cc617 9792 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9793 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9794 unsigned long ugfn;
9795 int lpages;
d89cc617 9796 int level = i + 1;
db3fe4eb
TY		 9797
9798 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9799 slot->base_gfn, level) + 1;
9800
d89cc617 9801 slot->arch.rmap[i] =
778e1cdd 9802 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9803 GFP_KERNEL_ACCOUNT);
d89cc617 9804 if (!slot->arch.rmap[i])
77d11309 9805 goto out_free;
d89cc617
TY		 9806 if (i == 0)
9807 continue;
77d11309 9808
254272ce 9809 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9810 if (!linfo)
db3fe4eb
TY		 9811 goto out_free;
9812
92f94f1e
XG		 9813 slot->arch.lpage_info[i - 1] = linfo;
9814
db3fe4eb 9815 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9816 linfo[0].disallow_lpage = 1;
db3fe4eb 9817 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9818 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9819 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9820 /*
9821 * If the gfn and userspace address are not aligned wrt each
9822 * other, or if explicitly asked to, disable large page
9823 * support for this slot
9824 */
9825 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9826 !kvm_largepages_enabled()) {
9827 unsigned long j;
9828
9829 for (j = 0; j < lpages; ++j)
92f94f1e 9830 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9831 }
9832 }
9833
21ebbeda
XG		 9834 if (kvm_page_track_create_memslot(slot, npages))
9835 goto out_free;
9836
db3fe4eb
TY		 9837 return 0;
9838
9839out_free:
d89cc617 9840 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9841 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9842 slot->arch.rmap[i] = NULL;
9843 if (i == 0)
9844 continue;
9845
548ef284 9846 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9847 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9848 }
9849 return -ENOMEM;
9850}
9851
15248258 9852void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9853{
e6dff7d1
TY		 9854 /*
9855 * memslots->generation has been incremented.
9856 * mmio generation may have reached its maximum value.
9857 */
15248258 9858 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9859}
9860
f7784b8e
MT		 9861int kvm_arch_prepare_memory_region(struct kvm *kvm,
9862 struct kvm_memory_slot *memslot,
09170a49 9863 const struct kvm_userspace_memory_region *mem,
7b6195a9 9864 enum kvm_mr_change change)
0de10343 9865{
f7784b8e
MT		 9866 return 0;
9867}
9868
88178fd4
KH		 9869static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9870 struct kvm_memory_slot *new)
9871{
9872 /* Still write protect RO slot */
9873 if (new->flags & KVM_MEM_READONLY) {
9874 kvm_mmu_slot_remove_write_access(kvm, new);
9875 return;
9876 }
9877
9878 /*
9879 * Call kvm_x86_ops dirty logging hooks when they are valid.
9880 *
9881 * kvm_x86_ops->slot_disable_log_dirty is called when:
9882 *
9883 * - KVM_MR_CREATE with dirty logging is disabled
9884 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9885 *
9886 * The reason is, in case of PML, we need to set D-bit for any slots
9887 * with dirty logging disabled in order to eliminate unnecessary GPA
0a03cbda 9888 * logging in PML buffer (and potential PML buffer full VMEXIT). This
88178fd4 9889 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9890 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9891 * logging disabled for memory slots.
9892 *
9893 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9894 * to dirty logging mode.
9895 *
9896 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9897 *
9898 * In case of write protect:
9899 *
9900 * Write protect all pages for dirty logging.
9901 *
9902 * All the sptes including the large sptes which point to this
9903 * slot are set to readonly. We can not create any new large
9904 * spte on this slot until the end of the logging.
9905 *
9906 * See the comments in fast_page_fault().
9907 */
9908 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9909 if (kvm_x86_ops->slot_enable_log_dirty)
9910 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9911 else
9912 kvm_mmu_slot_remove_write_access(kvm, new);
9913 } else {
9914 if (kvm_x86_ops->slot_disable_log_dirty)
9915 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9916 }
9917}
9918
f7784b8e 9919void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9920 const struct kvm_userspace_memory_region *mem,
8482644a 9921 const struct kvm_memory_slot *old,
f36f3f28 9922 const struct kvm_memory_slot *new,
8482644a 9923 enum kvm_mr_change change)
f7784b8e 9924{
48c0e4e9 9925 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9926 kvm_mmu_change_mmu_pages(kvm,
9927 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9928
3ea3b7fa
WL		 9929 /*
9930 * Dirty logging tracks sptes in 4k granularity, meaning that large
9931 * sptes have to be split. If live migration is successful, the guest
9932 * in the source machine will be destroyed and large sptes will be
9933 * created in the destination. However, if the guest continues to run
9934 * in the source machine (for example if live migration fails), small
9935 * sptes will remain around and cause bad performance.
9936 *
9937 * Scan sptes if dirty logging has been stopped, dropping those
9938 * which can be collapsed into a single large-page spte. Later
9939 * page faults will create the large-page sptes.
319109a2
SC		 9940 *
9941 * There is no need to do this in any of the following cases:
9942 * CREATE: No dirty mappings will already exist.
9943 * MOVE/DELETE: The old mappings will already have been cleaned up by
9944 * kvm_arch_flush_shadow_memslot()
3ea3b7fa 9945 */
319109a2 9946 if (change == KVM_MR_FLAGS_ONLY &&
3ea3b7fa
WL		 9947 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9948 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9949 kvm_mmu_zap_collapsible_sptes(kvm, new);
9950
c972f3b1 9951 /*
88178fd4 9952 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9953 *
88178fd4
KH		 9954 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9955 * been zapped so no dirty logging staff is needed for old slot. For
9956 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9957 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9958 *
9959 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9960 */
88178fd4 9961 if (change != KVM_MR_DELETE)
f36f3f28 9962 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9963}
1d737c8a 9964
2df72e9b 9965void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9966{
7390de1e 9967 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9968}
9969
2df72e9b
MT		 9970void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9971 struct kvm_memory_slot *slot)
9972{
ae7cd873 9973 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9974}
9975
e6c67d8c
LA		 9976static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9977{
9978 return (is_guest_mode(vcpu) &&
9979 kvm_x86_ops->guest_apic_has_interrupt &&
9980 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9981}
9982
5d9bc648
PB		 9983static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9984{
9985 if (!list_empty_careful(&vcpu->async_pf.done))
9986 return true;
9987
9988 if (kvm_apic_has_events(vcpu))
9989 return true;
9990
9991 if (vcpu->arch.pv.pv_unhalted)
9992 return true;
9993
a5f01f8e
WL		 9994 if (vcpu->arch.exception.pending)
9995 return true;
9996
47a66eed
Z		 9997 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9998 (vcpu->arch.nmi_pending &&
9999 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 10000 return true;
10001
47a66eed
Z		 10002 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10003 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 10004 return true;
10005
5d9bc648 10006 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 10007 (kvm_cpu_has_interrupt(vcpu) ||
10008 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 10009 return true;
10010
1f4b34f8
AS		 10011 if (kvm_hv_has_stimer_pending(vcpu))
10012 return true;
10013
5d9bc648
PB		 10014 return false;
10015}
10016
1d737c8a
ZX		 10017int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10018{
5d9bc648 10019 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 10020}
5736199a 10021
17e433b5
WL		 10022bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10023{
10024 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10025 return true;
10026
10027 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10028 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10029 kvm_test_request(KVM_REQ_EVENT, vcpu))
10030 return true;
10031
10032 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
10033 return true;
10034
10035 return false;
10036}
10037
199b5763
LM		 10038bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10039{
de63ad4c 10040 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 10041}
10042
b6d33834 10043int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 10044{
b6d33834 10045 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 10046}
78646121
GN		 10047
10048int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10049{
10050 return kvm_x86_ops->interrupt_allowed(vcpu);
10051}
229456fc 10052
82b32774 10053unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 10054{
82b32774
NA		 10055 if (is_64_bit_mode(vcpu))
10056 return kvm_rip_read(vcpu);
10057 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10058 kvm_rip_read(vcpu));
10059}
10060EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 10061
82b32774
NA		 10062bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10063{
10064 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 10065}
10066EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10067
94fe45da
JK		 10068unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10069{
10070 unsigned long rflags;
10071
10072 rflags = kvm_x86_ops->get_rflags(vcpu);
10073 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 10074 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 10075 return rflags;
10076}
10077EXPORT_SYMBOL_GPL(kvm_get_rflags);
10078
6addfc42 10079static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 10080{
10081 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 10082 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 10083 rflags |= X86_EFLAGS_TF;
94fe45da 10084 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 10085}
10086
10087void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10088{
10089 __kvm_set_rflags(vcpu, rflags);
3842d135 10090 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 10091}
10092EXPORT_SYMBOL_GPL(kvm_set_rflags);
10093
56028d08
GN		 10094void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10095{
10096 int r;
10097
44dd3ffa 10098 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 10099 work->wakeup_all)
56028d08
GN		 10100 return;
10101
10102 r = kvm_mmu_reload(vcpu);
10103 if (unlikely(r))
10104 return;
10105
44dd3ffa
VK		 10106 if (!vcpu->arch.mmu->direct_map &&
10107 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 10108 return;
10109
736c291c 10110 vcpu->arch.mmu->page_fault(vcpu, work->cr2_or_gpa, 0, true);
56028d08
GN		 10111}
10112
af585b92
GN		 10113static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10114{
10115 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10116}
10117
10118static inline u32 kvm_async_pf_next_probe(u32 key)
10119{
10120 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10121}
10122
10123static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10124{
10125 u32 key = kvm_async_pf_hash_fn(gfn);
10126
10127 while (vcpu->arch.apf.gfns[key] != ~0)
10128 key = kvm_async_pf_next_probe(key);
10129
10130 vcpu->arch.apf.gfns[key] = gfn;
10131}
10132
10133static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10134{
10135 int i;
10136 u32 key = kvm_async_pf_hash_fn(gfn);
10137
10138 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 10139 (vcpu->arch.apf.gfns[key] != gfn &&
10140 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 10141 key = kvm_async_pf_next_probe(key);
10142
10143 return key;
10144}
10145
10146bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10147{
10148 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10149}
10150
10151static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10152{
10153 u32 i, j, k;
10154
10155 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10156 while (true) {
10157 vcpu->arch.apf.gfns[i] = ~0;
10158 do {
10159 j = kvm_async_pf_next_probe(j);
10160 if (vcpu->arch.apf.gfns[j] == ~0)
10161 return;
10162 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10163 /*
10164 * k lies cyclically in ]i,j]
10165 * | i.k.j |
10166 * |....j i.k.| or |.k..j i...|
10167 */
10168 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10169 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10170 i = j;
10171 }
10172}
10173
7c90705b
GN		 10174static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10175{
4e335d9e
PB		 10176
10177 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10178 sizeof(val));
7c90705b
GN		 10179}
10180
9a6e7c39
WL		 10181static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10182{
10183
10184 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10185 sizeof(u32));
10186}
10187
1dfdb45e
PB		 10188static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10189{
10190 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10191 return false;
10192
10193 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10194 (vcpu->arch.apf.send_user_only &&
10195 kvm_x86_ops->get_cpl(vcpu) == 0))
10196 return false;
10197
10198 return true;
10199}
10200
10201bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10202{
10203 if (unlikely(!lapic_in_kernel(vcpu) ||
10204 kvm_event_needs_reinjection(vcpu) ||
10205 vcpu->arch.exception.pending))
10206 return false;
10207
10208 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10209 return false;
10210
10211 /*
10212 * If interrupts are off we cannot even use an artificial
10213 * halt state.
10214 */
10215 return kvm_x86_ops->interrupt_allowed(vcpu);
10216}
10217
af585b92
GN		 10218void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10219 struct kvm_async_pf *work)
10220{
6389ee94
AK		 10221 struct x86_exception fault;
10222
736c291c 10223 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
af585b92 10224 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b 10225
1dfdb45e
PB		 10226 if (kvm_can_deliver_async_pf(vcpu) &&
10227 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 10228 fault.vector = PF_VECTOR;
10229 fault.error_code_valid = true;
10230 fault.error_code = 0;
10231 fault.nested_page_fault = false;
10232 fault.address = work->arch.token;
adfe20fb 10233 fault.async_page_fault = true;
6389ee94 10234 kvm_inject_page_fault(vcpu, &fault);
1dfdb45e
PB		 10235 } else {
10236 /*
10237 * It is not possible to deliver a paravirtualized asynchronous
10238 * page fault, but putting the guest in an artificial halt state
10239 * can be beneficial nevertheless: if an interrupt arrives, we
10240 * can deliver it timely and perhaps the guest will schedule
10241 * another process. When the instruction that triggered a page
10242 * fault is retried, hopefully the page will be ready in the host.
10243 */
10244 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7c90705b 10245 }
af585b92
GN		 10246}
10247
10248void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10249 struct kvm_async_pf *work)
10250{
6389ee94 10251 struct x86_exception fault;
9a6e7c39 10252 u32 val;
6389ee94 10253
f2e10669 10254 if (work->wakeup_all)
7c90705b
GN		 10255 work->arch.token = ~0; /* broadcast wakeup */
10256 else
10257 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
736c291c 10258 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
7c90705b 10259
9a6e7c39
WL		 10260 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10261 !apf_get_user(vcpu, &val)) {
10262 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10263 vcpu->arch.exception.pending &&
10264 vcpu->arch.exception.nr == PF_VECTOR &&
10265 !apf_put_user(vcpu, 0)) {
10266 vcpu->arch.exception.injected = false;
10267 vcpu->arch.exception.pending = false;
10268 vcpu->arch.exception.nr = 0;
10269 vcpu->arch.exception.has_error_code = false;
10270 vcpu->arch.exception.error_code = 0;
c851436a
JM		 10271 vcpu->arch.exception.has_payload = false;
10272 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 10273 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10274 fault.vector = PF_VECTOR;
10275 fault.error_code_valid = true;
10276 fault.error_code = 0;
10277 fault.nested_page_fault = false;
10278 fault.address = work->arch.token;
10279 fault.async_page_fault = true;
10280 kvm_inject_page_fault(vcpu, &fault);
10281 }
7c90705b 10282 }
e6d53e3b 10283 vcpu->arch.apf.halted = false;
a4fa1635 10284 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 10285}
10286
10287bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10288{
10289 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10290 return true;
10291 else
9bc1f09f 10292 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 10293}
10294
5544eb9b
PB		 10295void kvm_arch_start_assignment(struct kvm *kvm)
10296{
10297 atomic_inc(&kvm->arch.assigned_device_count);
10298}
10299EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10300
10301void kvm_arch_end_assignment(struct kvm *kvm)
10302{
10303 atomic_dec(&kvm->arch.assigned_device_count);
10304}
10305EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10306
10307bool kvm_arch_has_assigned_device(struct kvm *kvm)
10308{
10309 return atomic_read(&kvm->arch.assigned_device_count);
10310}
10311EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10312
e0f0bbc5
AW		 10313void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10314{
10315 atomic_inc(&kvm->arch.noncoherent_dma_count);
10316}
10317EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10318
10319void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10320{
10321 atomic_dec(&kvm->arch.noncoherent_dma_count);
10322}
10323EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10324
10325bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10326{
10327 return atomic_read(&kvm->arch.noncoherent_dma_count);
10328}
10329EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10330
14717e20
AW		 10331bool kvm_arch_has_irq_bypass(void)
10332{
92735b1b 10333 return true;
14717e20
AW		 10334}
10335
87276880
FW		 10336int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10337 struct irq_bypass_producer *prod)
10338{
10339 struct kvm_kernel_irqfd *irqfd =
10340 container_of(cons, struct kvm_kernel_irqfd, consumer);
10341
14717e20 10342 irqfd->producer = prod;
87276880 10343
14717e20
AW		 10344 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10345 prod->irq, irqfd->gsi, 1);
87276880
FW		 10346}
10347
10348void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10349 struct irq_bypass_producer *prod)
10350{
10351 int ret;
10352 struct kvm_kernel_irqfd *irqfd =
10353 container_of(cons, struct kvm_kernel_irqfd, consumer);
10354
87276880
FW		 10355 WARN_ON(irqfd->producer != prod);
10356 irqfd->producer = NULL;
10357
10358 /*
10359 * When producer of consumer is unregistered, we change back to
10360 * remapped mode, so we can re-use the current implementation
bb3541f1 10361 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 10362 * int this case doesn't want to receive the interrupts.
10363 */
10364 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10365 if (ret)
10366 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10367 " fails: %d\n", irqfd->consumer.token, ret);
10368}
10369
10370int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10371 uint32_t guest_irq, bool set)
10372{
87276880
FW		 10373 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10374}
10375
52004014
FW		 10376bool kvm_vector_hashing_enabled(void)
10377{
10378 return vector_hashing;
10379}
10380EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10381
2d5ba19b
MT		 10382bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10383{
10384 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10385}
10386EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10387
6441fa61
PB		 10388u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10389{
10390 uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10391
10392 /* The STIBP bit doesn't fault even if it's not advertised */
10393 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10394 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10395 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10396 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10397 !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10398 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10399
10400 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10401 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10402 bits &= ~SPEC_CTRL_SSBD;
10403 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10404 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10405 bits &= ~SPEC_CTRL_SSBD;
10406
10407 return bits;
10408}
10409EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
2d5ba19b 10410
229456fc 10411EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 10412EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 10413EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10414EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10415EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10416EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 10417EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 10418EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 10419EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 10420EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
5497b955 10421EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
ec1ff790 10422EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 10423EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 10424EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 10425EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
4f75bcc3 10426EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
843e4330 10427EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 10428EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 10429EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10430EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)