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KVM: make 'lapic_timer_ops' and 'kpit_ops' static
[linux-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
043405e1
CO		 40
41#include <asm/uaccess.h>
d825ed0a 42#include <asm/msr.h>
a5f61300 43#include <asm/desc.h>
0bed3b56 44#include <asm/mtrr.h>
043405e1 45
313a3dc7 46#define MAX_IO_MSRS 256
a03490ed
CO		 47#define CR0_RESERVED_BITS \
48 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
49 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
50 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
51#define CR4_RESERVED_BITS \
52 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
53 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
54 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
55 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
56
57#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 58/* EFER defaults:
59 * - enable syscall per default because its emulated by KVM
60 * - enable LME and LMA per default on 64 bit KVM
61 */
62#ifdef CONFIG_X86_64
63static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
64#else
65static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
66#endif
313a3dc7 67
ba1389b7
AK		 68#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
69#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 70
674eea0f
AK		 71static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
72 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 73struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
74 u32 function, u32 index);
674eea0f 75
97896d04 76struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 77EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 78
417bc304 79struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 80 { "pf_fixed", VCPU_STAT(pf_fixed) },
81 { "pf_guest", VCPU_STAT(pf_guest) },
82 { "tlb_flush", VCPU_STAT(tlb_flush) },
83 { "invlpg", VCPU_STAT(invlpg) },
84 { "exits", VCPU_STAT(exits) },
85 { "io_exits", VCPU_STAT(io_exits) },
86 { "mmio_exits", VCPU_STAT(mmio_exits) },
87 { "signal_exits", VCPU_STAT(signal_exits) },
88 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 89 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 90 { "halt_exits", VCPU_STAT(halt_exits) },
91 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 92 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7 93 { "request_irq", VCPU_STAT(request_irq_exits) },
c4abb7c9 94 { "request_nmi", VCPU_STAT(request_nmi_exits) },
ba1389b7
AK		 95 { "irq_exits", VCPU_STAT(irq_exits) },
96 { "host_state_reload", VCPU_STAT(host_state_reload) },
97 { "efer_reload", VCPU_STAT(efer_reload) },
98 { "fpu_reload", VCPU_STAT(fpu_reload) },
99 { "insn_emulation", VCPU_STAT(insn_emulation) },
100 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 101 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 102 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 103 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
104 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
105 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
106 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
107 { "mmu_flooded", VM_STAT(mmu_flooded) },
108 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 109 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 110 { "mmu_unsync", VM_STAT(mmu_unsync) },
6cffe8ca 111 { "mmu_unsync_global", VM_STAT(mmu_unsync_global) },
0f74a24c 112 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 113 { "largepages", VM_STAT(lpages) },
417bc304
HB		 114 { NULL }
115};
116
5fb76f9b
CO		 117unsigned long segment_base(u16 selector)
118{
119 struct descriptor_table gdt;
a5f61300 120 struct desc_struct *d;
5fb76f9b
CO		 121 unsigned long table_base;
122 unsigned long v;
123
124 if (selector == 0)
125 return 0;
126
127 asm("sgdt %0" : "=m"(gdt));
128 table_base = gdt.base;
129
130 if (selector & 4) { /* from ldt */
131 u16 ldt_selector;
132
133 asm("sldt %0" : "=g"(ldt_selector));
134 table_base = segment_base(ldt_selector);
135 }
a5f61300
AK		 136 d = (struct desc_struct *)(table_base + (selector & ~7));
137 v = d->base0 | ((unsigned long)d->base1 << 16) |
138 ((unsigned long)d->base2 << 24);
5fb76f9b 139#ifdef CONFIG_X86_64
a5f61300
AK		 140 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
141 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 142#endif
143 return v;
144}
145EXPORT_SYMBOL_GPL(segment_base);
146
6866b83e
CO		 147u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
148{
149 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 150 return vcpu->arch.apic_base;
6866b83e 151 else
ad312c7c 152 return vcpu->arch.apic_base;
6866b83e
CO		 153}
154EXPORT_SYMBOL_GPL(kvm_get_apic_base);
155
156void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
157{
158 /* TODO: reserve bits check */
159 if (irqchip_in_kernel(vcpu->kvm))
160 kvm_lapic_set_base(vcpu, data);
161 else
ad312c7c 162 vcpu->arch.apic_base = data;
6866b83e
CO		 163}
164EXPORT_SYMBOL_GPL(kvm_set_apic_base);
165
298101da
AK		 166void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
167{
ad312c7c
ZX		 168 WARN_ON(vcpu->arch.exception.pending);
169 vcpu->arch.exception.pending = true;
170 vcpu->arch.exception.has_error_code = false;
171 vcpu->arch.exception.nr = nr;
298101da
AK		 172}
173EXPORT_SYMBOL_GPL(kvm_queue_exception);
174
c3c91fee
AK		 175void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
176 u32 error_code)
177{
178 ++vcpu->stat.pf_guest;
d8017474 179
71c4dfaf
JR		 180 if (vcpu->arch.exception.pending) {
181 if (vcpu->arch.exception.nr == PF_VECTOR) {
182 printk(KERN_DEBUG "kvm: inject_page_fault:"
183 " double fault 0x%lx\n", addr);
184 vcpu->arch.exception.nr = DF_VECTOR;
185 vcpu->arch.exception.error_code = 0;
186 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
187 /* triple fault -> shutdown */
188 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
189 }
c3c91fee
AK		 190 return;
191 }
ad312c7c 192 vcpu->arch.cr2 = addr;
c3c91fee
AK		 193 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
194}
195
3419ffc8
SY		 196void kvm_inject_nmi(struct kvm_vcpu *vcpu)
197{
198 vcpu->arch.nmi_pending = 1;
199}
200EXPORT_SYMBOL_GPL(kvm_inject_nmi);
201
298101da
AK		 202void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
203{
ad312c7c
ZX		 204 WARN_ON(vcpu->arch.exception.pending);
205 vcpu->arch.exception.pending = true;
206 vcpu->arch.exception.has_error_code = true;
207 vcpu->arch.exception.nr = nr;
208 vcpu->arch.exception.error_code = error_code;
298101da
AK		 209}
210EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
211
212static void __queue_exception(struct kvm_vcpu *vcpu)
213{
ad312c7c
ZX		 214 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
215 vcpu->arch.exception.has_error_code,
216 vcpu->arch.exception.error_code);
298101da
AK		 217}
218
a03490ed
CO		 219/*
220 * Load the pae pdptrs. Return true is they are all valid.
221 */
222int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
223{
224 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
225 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
226 int i;
227 int ret;
ad312c7c 228 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 229
a03490ed
CO		 230 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
231 offset * sizeof(u64), sizeof(pdpte));
232 if (ret < 0) {
233 ret = 0;
234 goto out;
235 }
236 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
237 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
238 ret = 0;
239 goto out;
240 }
241 }
242 ret = 1;
243
ad312c7c 244 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 245out:
a03490ed
CO		 246
247 return ret;
248}
cc4b6871 249EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 250
d835dfec
AK		 251static bool pdptrs_changed(struct kvm_vcpu *vcpu)
252{
ad312c7c 253 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 254 bool changed = true;
255 int r;
256
257 if (is_long_mode(vcpu) || !is_pae(vcpu))
258 return false;
259
ad312c7c 260 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 261 if (r < 0)
262 goto out;
ad312c7c 263 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 264out:
d835dfec
AK		 265
266 return changed;
267}
268
2d3ad1f4 269void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 270{
271 if (cr0 & CR0_RESERVED_BITS) {
272 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 273 cr0, vcpu->arch.cr0);
c1a5d4f9 274 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 275 return;
276 }
277
278 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
279 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 280 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 281 return;
282 }
283
284 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
285 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
286 "and a clear PE flag\n");
c1a5d4f9 287 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 288 return;
289 }
290
291 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
292#ifdef CONFIG_X86_64
ad312c7c 293 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 294 int cs_db, cs_l;
295
296 if (!is_pae(vcpu)) {
297 printk(KERN_DEBUG "set_cr0: #GP, start paging "
298 "in long mode while PAE is disabled\n");
c1a5d4f9 299 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 300 return;
301 }
302 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
303 if (cs_l) {
304 printk(KERN_DEBUG "set_cr0: #GP, start paging "
305 "in long mode while CS.L == 1\n");
c1a5d4f9 306 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 307 return;
308
309 }
310 } else
311#endif
ad312c7c 312 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 313 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
314 "reserved bits\n");
c1a5d4f9 315 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 316 return;
317 }
318
319 }
320
321 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 322 vcpu->arch.cr0 = cr0;
a03490ed 323
6cffe8ca 324 kvm_mmu_sync_global(vcpu);
a03490ed 325 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 326 return;
327}
2d3ad1f4 328EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 329
2d3ad1f4 330void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 331{
2d3ad1f4 332 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 333 KVMTRACE_1D(LMSW, vcpu,
334 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
335 handler);
a03490ed 336}
2d3ad1f4 337EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 338
2d3ad1f4 339void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 340{
a2edf57f
AK		 341 unsigned long old_cr4 = vcpu->arch.cr4;
342 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
343
a03490ed
CO		 344 if (cr4 & CR4_RESERVED_BITS) {
345 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 346 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 347 return;
348 }
349
350 if (is_long_mode(vcpu)) {
351 if (!(cr4 & X86_CR4_PAE)) {
352 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
353 "in long mode\n");
c1a5d4f9 354 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 355 return;
356 }
a2edf57f
AK		 357 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
358 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 359 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 360 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 361 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 362 return;
363 }
364
365 if (cr4 & X86_CR4_VMXE) {
366 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 367 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 368 return;
369 }
370 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 371 vcpu->arch.cr4 = cr4;
5a41accd 372 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
6cffe8ca 373 kvm_mmu_sync_global(vcpu);
a03490ed 374 kvm_mmu_reset_context(vcpu);
a03490ed 375}
2d3ad1f4 376EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 377
2d3ad1f4 378void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 379{
ad312c7c 380 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 381 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 382 kvm_mmu_flush_tlb(vcpu);
383 return;
384 }
385
a03490ed
CO		 386 if (is_long_mode(vcpu)) {
387 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
388 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 389 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 390 return;
391 }
392 } else {
393 if (is_pae(vcpu)) {
394 if (cr3 & CR3_PAE_RESERVED_BITS) {
395 printk(KERN_DEBUG
396 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 397 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 398 return;
399 }
400 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
401 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
402 "reserved bits\n");
c1a5d4f9 403 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 404 return;
405 }
406 }
407 /*
408 * We don't check reserved bits in nonpae mode, because
409 * this isn't enforced, and VMware depends on this.
410 */
411 }
412
a03490ed
CO		 413 /*
414 * Does the new cr3 value map to physical memory? (Note, we
415 * catch an invalid cr3 even in real-mode, because it would
416 * cause trouble later on when we turn on paging anyway.)
417 *
418 * A real CPU would silently accept an invalid cr3 and would
419 * attempt to use it - with largely undefined (and often hard
420 * to debug) behavior on the guest side.
421 */
422 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 423 kvm_inject_gp(vcpu, 0);
a03490ed 424 else {
ad312c7c
ZX		 425 vcpu->arch.cr3 = cr3;
426 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 427 }
a03490ed 428}
2d3ad1f4 429EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 430
2d3ad1f4 431void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 432{
433 if (cr8 & CR8_RESERVED_BITS) {
434 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 435 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 436 return;
437 }
438 if (irqchip_in_kernel(vcpu->kvm))
439 kvm_lapic_set_tpr(vcpu, cr8);
440 else
ad312c7c 441 vcpu->arch.cr8 = cr8;
a03490ed 442}
2d3ad1f4 443EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 444
2d3ad1f4 445unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 446{
447 if (irqchip_in_kernel(vcpu->kvm))
448 return kvm_lapic_get_cr8(vcpu);
449 else
ad312c7c 450 return vcpu->arch.cr8;
a03490ed 451}
2d3ad1f4 452EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 453
d8017474
AG		 454static inline u32 bit(int bitno)
455{
456 return 1 << (bitno & 31);
457}
458
043405e1
CO		 459/*
460 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
461 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
462 *
463 * This list is modified at module load time to reflect the
464 * capabilities of the host cpu.
465 */
466static u32 msrs_to_save[] = {
467 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
468 MSR_K6_STAR,
469#ifdef CONFIG_X86_64
470 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
471#endif
18068523 472 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 473 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 474};
475
476static unsigned num_msrs_to_save;
477
478static u32 emulated_msrs[] = {
479 MSR_IA32_MISC_ENABLE,
480};
481
15c4a640
CO		 482static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
483{
f2b4b7dd 484 if (efer & efer_reserved_bits) {
15c4a640
CO		 485 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
486 efer);
c1a5d4f9 487 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 488 return;
489 }
490
491 if (is_paging(vcpu)
ad312c7c 492 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 493 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 494 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 495 return;
496 }
497
1b2fd70c
AG		 498 if (efer & EFER_FFXSR) {
499 struct kvm_cpuid_entry2 *feat;
500
501 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
502 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
503 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
504 kvm_inject_gp(vcpu, 0);
505 return;
506 }
507 }
508
d8017474
AG		 509 if (efer & EFER_SVME) {
510 struct kvm_cpuid_entry2 *feat;
511
512 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
513 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
514 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
515 kvm_inject_gp(vcpu, 0);
516 return;
517 }
518 }
519
15c4a640
CO		 520 kvm_x86_ops->set_efer(vcpu, efer);
521
522 efer &= ~EFER_LMA;
ad312c7c 523 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 524
ad312c7c 525 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 526}
527
f2b4b7dd
JR		 528void kvm_enable_efer_bits(u64 mask)
529{
530 efer_reserved_bits &= ~mask;
531}
532EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
533
534
15c4a640
CO		 535/*
536 * Writes msr value into into the appropriate "register".
537 * Returns 0 on success, non-0 otherwise.
538 * Assumes vcpu_load() was already called.
539 */
540int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
541{
542 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
543}
544
313a3dc7
CO		 545/*
546 * Adapt set_msr() to msr_io()'s calling convention
547 */
548static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
549{
550 return kvm_set_msr(vcpu, index, *data);
551}
552
18068523
GOC		 553static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
554{
555 static int version;
50d0a0f9
GH		 556 struct pvclock_wall_clock wc;
557 struct timespec now, sys, boot;
18068523
GOC		 558
559 if (!wall_clock)
560 return;
561
562 version++;
563
18068523
GOC		 564 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
565
50d0a0f9
GH		 566 /*
567 * The guest calculates current wall clock time by adding
568 * system time (updated by kvm_write_guest_time below) to the
569 * wall clock specified here. guest system time equals host
570 * system time for us, thus we must fill in host boot time here.
571 */
572 now = current_kernel_time();
573 ktime_get_ts(&sys);
574 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
575
576 wc.sec = boot.tv_sec;
577 wc.nsec = boot.tv_nsec;
578 wc.version = version;
18068523
GOC		 579
580 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
581
582 version++;
583 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 584}
585
50d0a0f9
GH		 586static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
587{
588 uint32_t quotient, remainder;
589
590 /* Don't try to replace with do_div(), this one calculates
591 * "(dividend << 32) / divisor" */
592 __asm__ ( "divl %4"
593 : "=a" (quotient), "=d" (remainder)
594 : "0" (0), "1" (dividend), "r" (divisor) );
595 return quotient;
596}
597
598static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
599{
600 uint64_t nsecs = 1000000000LL;
601 int32_t shift = 0;
602 uint64_t tps64;
603 uint32_t tps32;
604
605 tps64 = tsc_khz * 1000LL;
606 while (tps64 > nsecs*2) {
607 tps64 >>= 1;
608 shift--;
609 }
610
611 tps32 = (uint32_t)tps64;
612 while (tps32 <= (uint32_t)nsecs) {
613 tps32 <<= 1;
614 shift++;
615 }
616
617 hv_clock->tsc_shift = shift;
618 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
619
620 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 621 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 622 hv_clock->tsc_to_system_mul);
623}
624
c8076604
GH		 625static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
626
18068523
GOC		 627static void kvm_write_guest_time(struct kvm_vcpu *v)
628{
629 struct timespec ts;
630 unsigned long flags;
631 struct kvm_vcpu_arch *vcpu = &v->arch;
632 void *shared_kaddr;
633
634 if ((!vcpu->time_page))
635 return;
636
2dea4c84 637 preempt_disable();
c8076604
GH		 638 if (unlikely(vcpu->hv_clock_tsc_khz != __get_cpu_var(cpu_tsc_khz))) {
639 kvm_set_time_scale(__get_cpu_var(cpu_tsc_khz), &vcpu->hv_clock);
640 vcpu->hv_clock_tsc_khz = __get_cpu_var(cpu_tsc_khz);
50d0a0f9 641 }
2dea4c84 642 preempt_enable();
50d0a0f9 643
18068523
GOC		 644 /* Keep irq disabled to prevent changes to the clock */
645 local_irq_save(flags);
646 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
647 &vcpu->hv_clock.tsc_timestamp);
648 ktime_get_ts(&ts);
649 local_irq_restore(flags);
650
651 /* With all the info we got, fill in the values */
652
653 vcpu->hv_clock.system_time = ts.tv_nsec +
654 (NSEC_PER_SEC * (u64)ts.tv_sec);
655 /*
656 * The interface expects us to write an even number signaling that the
657 * update is finished. Since the guest won't see the intermediate
50d0a0f9 658 * state, we just increase by 2 at the end.
18068523 659 */
50d0a0f9 660 vcpu->hv_clock.version += 2;
18068523
GOC		 661
662 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
663
664 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 665 sizeof(vcpu->hv_clock));
18068523
GOC		 666
667 kunmap_atomic(shared_kaddr, KM_USER0);
668
669 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
670}
671
c8076604
GH		 672static int kvm_request_guest_time_update(struct kvm_vcpu *v)
673{
674 struct kvm_vcpu_arch *vcpu = &v->arch;
675
676 if (!vcpu->time_page)
677 return 0;
678 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
679 return 1;
680}
681
9ba075a6
AK		 682static bool msr_mtrr_valid(unsigned msr)
683{
684 switch (msr) {
685 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
686 case MSR_MTRRfix64K_00000:
687 case MSR_MTRRfix16K_80000:
688 case MSR_MTRRfix16K_A0000:
689 case MSR_MTRRfix4K_C0000:
690 case MSR_MTRRfix4K_C8000:
691 case MSR_MTRRfix4K_D0000:
692 case MSR_MTRRfix4K_D8000:
693 case MSR_MTRRfix4K_E0000:
694 case MSR_MTRRfix4K_E8000:
695 case MSR_MTRRfix4K_F0000:
696 case MSR_MTRRfix4K_F8000:
697 case MSR_MTRRdefType:
698 case MSR_IA32_CR_PAT:
699 return true;
700 case 0x2f8:
701 return true;
702 }
703 return false;
704}
705
706static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
707{
0bed3b56
SY		 708 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
709
9ba075a6
AK		 710 if (!msr_mtrr_valid(msr))
711 return 1;
712
0bed3b56
SY		 713 if (msr == MSR_MTRRdefType) {
714 vcpu->arch.mtrr_state.def_type = data;
715 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
716 } else if (msr == MSR_MTRRfix64K_00000)
717 p[0] = data;
718 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
719 p[1 + msr - MSR_MTRRfix16K_80000] = data;
720 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
721 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
722 else if (msr == MSR_IA32_CR_PAT)
723 vcpu->arch.pat = data;
724 else { /* Variable MTRRs */
725 int idx, is_mtrr_mask;
726 u64 *pt;
727
728 idx = (msr - 0x200) / 2;
729 is_mtrr_mask = msr - 0x200 - 2 * idx;
730 if (!is_mtrr_mask)
731 pt =
732 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
733 else
734 pt =
735 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
736 *pt = data;
737 }
738
739 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 740 return 0;
741}
15c4a640
CO		 742
743int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
744{
745 switch (msr) {
15c4a640
CO		 746 case MSR_EFER:
747 set_efer(vcpu, data);
748 break;
15c4a640
CO		 749 case MSR_IA32_MC0_STATUS:
750 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 751 __func__, data);
15c4a640
CO		 752 break;
753 case MSR_IA32_MCG_STATUS:
754 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 755 __func__, data);
15c4a640 756 break;
c7ac679c
JR		 757 case MSR_IA32_MCG_CTL:
758 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 759 __func__, data);
c7ac679c 760 break;
b5e2fec0
AG		 761 case MSR_IA32_DEBUGCTLMSR:
762 if (!data) {
763 /* We support the non-activated case already */
764 break;
765 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
766 /* Values other than LBR and BTF are vendor-specific,
767 thus reserved and should throw a #GP */
768 return 1;
769 }
770 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
771 __func__, data);
772 break;
15c4a640
CO		 773 case MSR_IA32_UCODE_REV:
774 case MSR_IA32_UCODE_WRITE:
61a6bd67 775 case MSR_VM_HSAVE_PA:
15c4a640 776 break;
9ba075a6
AK		 777 case 0x200 ... 0x2ff:
778 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 779 case MSR_IA32_APICBASE:
780 kvm_set_apic_base(vcpu, data);
781 break;
782 case MSR_IA32_MISC_ENABLE:
ad312c7c 783 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 784 break;
18068523
GOC		 785 case MSR_KVM_WALL_CLOCK:
786 vcpu->kvm->arch.wall_clock = data;
787 kvm_write_wall_clock(vcpu->kvm, data);
788 break;
789 case MSR_KVM_SYSTEM_TIME: {
790 if (vcpu->arch.time_page) {
791 kvm_release_page_dirty(vcpu->arch.time_page);
792 vcpu->arch.time_page = NULL;
793 }
794
795 vcpu->arch.time = data;
796
797 /* we verify if the enable bit is set... */
798 if (!(data & 1))
799 break;
800
801 /* ...but clean it before doing the actual write */
802 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
803
18068523
GOC		 804 vcpu->arch.time_page =
805 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 806
807 if (is_error_page(vcpu->arch.time_page)) {
808 kvm_release_page_clean(vcpu->arch.time_page);
809 vcpu->arch.time_page = NULL;
810 }
811
c8076604 812 kvm_request_guest_time_update(vcpu);
18068523
GOC		 813 break;
814 }
15c4a640 815 default:
565f1fbd 816 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 817 return 1;
818 }
819 return 0;
820}
821EXPORT_SYMBOL_GPL(kvm_set_msr_common);
822
823
824/*
825 * Reads an msr value (of 'msr_index') into 'pdata'.
826 * Returns 0 on success, non-0 otherwise.
827 * Assumes vcpu_load() was already called.
828 */
829int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
830{
831 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
832}
833
9ba075a6
AK		 834static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
835{
0bed3b56
SY		 836 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
837
9ba075a6
AK		 838 if (!msr_mtrr_valid(msr))
839 return 1;
840
0bed3b56
SY		 841 if (msr == MSR_MTRRdefType)
842 *pdata = vcpu->arch.mtrr_state.def_type +
843 (vcpu->arch.mtrr_state.enabled << 10);
844 else if (msr == MSR_MTRRfix64K_00000)
845 *pdata = p[0];
846 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
847 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
848 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
849 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
850 else if (msr == MSR_IA32_CR_PAT)
851 *pdata = vcpu->arch.pat;
852 else { /* Variable MTRRs */
853 int idx, is_mtrr_mask;
854 u64 *pt;
855
856 idx = (msr - 0x200) / 2;
857 is_mtrr_mask = msr - 0x200 - 2 * idx;
858 if (!is_mtrr_mask)
859 pt =
860 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
861 else
862 pt =
863 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
864 *pdata = *pt;
865 }
866
9ba075a6
AK		 867 return 0;
868}
869
15c4a640
CO		 870int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
871{
872 u64 data;
873
874 switch (msr) {
875 case 0xc0010010: /* SYSCFG */
876 case 0xc0010015: /* HWCR */
877 case MSR_IA32_PLATFORM_ID:
878 case MSR_IA32_P5_MC_ADDR:
879 case MSR_IA32_P5_MC_TYPE:
880 case MSR_IA32_MC0_CTL:
881 case MSR_IA32_MCG_STATUS:
882 case MSR_IA32_MCG_CAP:
c7ac679c 883 case MSR_IA32_MCG_CTL:
15c4a640
CO		 884 case MSR_IA32_MC0_MISC:
885 case MSR_IA32_MC0_MISC+4:
886 case MSR_IA32_MC0_MISC+8:
887 case MSR_IA32_MC0_MISC+12:
888 case MSR_IA32_MC0_MISC+16:
a89c1ad2 889 case MSR_IA32_MC0_MISC+20:
15c4a640 890 case MSR_IA32_UCODE_REV:
15c4a640 891 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 892 case MSR_IA32_DEBUGCTLMSR:
893 case MSR_IA32_LASTBRANCHFROMIP:
894 case MSR_IA32_LASTBRANCHTOIP:
895 case MSR_IA32_LASTINTFROMIP:
896 case MSR_IA32_LASTINTTOIP:
61a6bd67 897 case MSR_VM_HSAVE_PA:
15c4a640
CO		 898 data = 0;
899 break;
9ba075a6
AK		 900 case MSR_MTRRcap:
901 data = 0x500 | KVM_NR_VAR_MTRR;
902 break;
903 case 0x200 ... 0x2ff:
904 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 905 case 0xcd: /* fsb frequency */
906 data = 3;
907 break;
908 case MSR_IA32_APICBASE:
909 data = kvm_get_apic_base(vcpu);
910 break;
911 case MSR_IA32_MISC_ENABLE:
ad312c7c 912 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 913 break;
847f0ad8
AG		 914 case MSR_IA32_PERF_STATUS:
915 /* TSC increment by tick */
916 data = 1000ULL;
917 /* CPU multiplier */
918 data |= (((uint64_t)4ULL) << 40);
919 break;
15c4a640 920 case MSR_EFER:
ad312c7c 921 data = vcpu->arch.shadow_efer;
15c4a640 922 break;
18068523
GOC		 923 case MSR_KVM_WALL_CLOCK:
924 data = vcpu->kvm->arch.wall_clock;
925 break;
926 case MSR_KVM_SYSTEM_TIME:
927 data = vcpu->arch.time;
928 break;
15c4a640
CO		 929 default:
930 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
931 return 1;
932 }
933 *pdata = data;
934 return 0;
935}
936EXPORT_SYMBOL_GPL(kvm_get_msr_common);
937
313a3dc7
CO		 938/*
939 * Read or write a bunch of msrs. All parameters are kernel addresses.
940 *
941 * @return number of msrs set successfully.
942 */
943static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
944 struct kvm_msr_entry *entries,
945 int (*do_msr)(struct kvm_vcpu *vcpu,
946 unsigned index, u64 *data))
947{
948 int i;
949
950 vcpu_load(vcpu);
951
3200f405 952 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 953 for (i = 0; i < msrs->nmsrs; ++i)
954 if (do_msr(vcpu, entries[i].index, &entries[i].data))
955 break;
3200f405 956 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 957
958 vcpu_put(vcpu);
959
960 return i;
961}
962
963/*
964 * Read or write a bunch of msrs. Parameters are user addresses.
965 *
966 * @return number of msrs set successfully.
967 */
968static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
969 int (*do_msr)(struct kvm_vcpu *vcpu,
970 unsigned index, u64 *data),
971 int writeback)
972{
973 struct kvm_msrs msrs;
974 struct kvm_msr_entry *entries;
975 int r, n;
976 unsigned size;
977
978 r = -EFAULT;
979 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
980 goto out;
981
982 r = -E2BIG;
983 if (msrs.nmsrs >= MAX_IO_MSRS)
984 goto out;
985
986 r = -ENOMEM;
987 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
988 entries = vmalloc(size);
989 if (!entries)
990 goto out;
991
992 r = -EFAULT;
993 if (copy_from_user(entries, user_msrs->entries, size))
994 goto out_free;
995
996 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
997 if (r < 0)
998 goto out_free;
999
1000 r = -EFAULT;
1001 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1002 goto out_free;
1003
1004 r = n;
1005
1006out_free:
1007 vfree(entries);
1008out:
1009 return r;
1010}
1011
018d00d2
ZX		 1012int kvm_dev_ioctl_check_extension(long ext)
1013{
1014 int r;
1015
1016 switch (ext) {
1017 case KVM_CAP_IRQCHIP:
1018 case KVM_CAP_HLT:
1019 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1020 case KVM_CAP_SET_TSS_ADDR:
07716717 1021 case KVM_CAP_EXT_CPUID:
c8076604 1022 case KVM_CAP_CLOCKSOURCE:
7837699f 1023 case KVM_CAP_PIT:
a28e4f5a 1024 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1025 case KVM_CAP_MP_STATE:
ed848624 1026 case KVM_CAP_SYNC_MMU:
52d939a0 1027 case KVM_CAP_REINJECT_CONTROL:
4925663a 1028 case KVM_CAP_IRQ_INJECT_STATUS:
018d00d2
ZX		 1029 r = 1;
1030 break;
542472b5
LV		 1031 case KVM_CAP_COALESCED_MMIO:
1032 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1033 break;
774ead3a
AK		 1034 case KVM_CAP_VAPIC:
1035 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1036 break;
f725230a
AK		 1037 case KVM_CAP_NR_VCPUS:
1038 r = KVM_MAX_VCPUS;
1039 break;
a988b910
AK		 1040 case KVM_CAP_NR_MEMSLOTS:
1041 r = KVM_MEMORY_SLOTS;
1042 break;
2f333bcb
MT		 1043 case KVM_CAP_PV_MMU:
1044 r = !tdp_enabled;
1045 break;
62c476c7 1046 case KVM_CAP_IOMMU:
19de40a8 1047 r = iommu_found();
62c476c7 1048 break;
018d00d2
ZX		 1049 default:
1050 r = 0;
1051 break;
1052 }
1053 return r;
1054
1055}
1056
043405e1
CO		 1057long kvm_arch_dev_ioctl(struct file *filp,
1058 unsigned int ioctl, unsigned long arg)
1059{
1060 void __user *argp = (void __user *)arg;
1061 long r;
1062
1063 switch (ioctl) {
1064 case KVM_GET_MSR_INDEX_LIST: {
1065 struct kvm_msr_list __user *user_msr_list = argp;
1066 struct kvm_msr_list msr_list;
1067 unsigned n;
1068
1069 r = -EFAULT;
1070 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1071 goto out;
1072 n = msr_list.nmsrs;
1073 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1074 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1075 goto out;
1076 r = -E2BIG;
1077 if (n < num_msrs_to_save)
1078 goto out;
1079 r = -EFAULT;
1080 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1081 num_msrs_to_save * sizeof(u32)))
1082 goto out;
1083 if (copy_to_user(user_msr_list->indices
1084 + num_msrs_to_save * sizeof(u32),
1085 &emulated_msrs,
1086 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1087 goto out;
1088 r = 0;
1089 break;
1090 }
674eea0f
AK		 1091 case KVM_GET_SUPPORTED_CPUID: {
1092 struct kvm_cpuid2 __user *cpuid_arg = argp;
1093 struct kvm_cpuid2 cpuid;
1094
1095 r = -EFAULT;
1096 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1097 goto out;
1098 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1099 cpuid_arg->entries);
674eea0f
AK		 1100 if (r)
1101 goto out;
1102
1103 r = -EFAULT;
1104 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1105 goto out;
1106 r = 0;
1107 break;
1108 }
043405e1
CO		 1109 default:
1110 r = -EINVAL;
1111 }
1112out:
1113 return r;
1114}
1115
313a3dc7
CO		 1116void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1117{
1118 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1119 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1120}
1121
1122void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1123{
1124 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1125 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1126}
1127
07716717 1128static int is_efer_nx(void)
313a3dc7 1129{
e286e86e 1130 unsigned long long efer = 0;
313a3dc7 1131
e286e86e 1132 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1133 return efer & EFER_NX;
1134}
1135
1136static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1137{
1138 int i;
1139 struct kvm_cpuid_entry2 *e, *entry;
1140
313a3dc7 1141 entry = NULL;
ad312c7c
ZX		 1142 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1143 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1144 if (e->function == 0x80000001) {
1145 entry = e;
1146 break;
1147 }
1148 }
07716717 1149 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1150 entry->edx &= ~(1 << 20);
1151 printk(KERN_INFO "kvm: guest NX capability removed\n");
1152 }
1153}
1154
07716717 1155/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1156static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1157 struct kvm_cpuid *cpuid,
1158 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1159{
1160 int r, i;
1161 struct kvm_cpuid_entry *cpuid_entries;
1162
1163 r = -E2BIG;
1164 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1165 goto out;
1166 r = -ENOMEM;
1167 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1168 if (!cpuid_entries)
1169 goto out;
1170 r = -EFAULT;
1171 if (copy_from_user(cpuid_entries, entries,
1172 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1173 goto out_free;
1174 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1175 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1176 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1177 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1178 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1179 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1180 vcpu->arch.cpuid_entries[i].index = 0;
1181 vcpu->arch.cpuid_entries[i].flags = 0;
1182 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1183 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1184 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1185 }
1186 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1187 cpuid_fix_nx_cap(vcpu);
1188 r = 0;
1189
1190out_free:
1191 vfree(cpuid_entries);
1192out:
1193 return r;
1194}
1195
1196static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1197 struct kvm_cpuid2 *cpuid,
1198 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1199{
1200 int r;
1201
1202 r = -E2BIG;
1203 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1204 goto out;
1205 r = -EFAULT;
ad312c7c 1206 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1207 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1208 goto out;
ad312c7c 1209 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1210 return 0;
1211
1212out:
1213 return r;
1214}
1215
07716717 1216static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1217 struct kvm_cpuid2 *cpuid,
1218 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1219{
1220 int r;
1221
1222 r = -E2BIG;
ad312c7c 1223 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1224 goto out;
1225 r = -EFAULT;
ad312c7c 1226 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1227 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1228 goto out;
1229 return 0;
1230
1231out:
ad312c7c 1232 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1233 return r;
1234}
1235
07716717 1236static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1237 u32 index)
07716717
DK		 1238{
1239 entry->function = function;
1240 entry->index = index;
1241 cpuid_count(entry->function, entry->index,
19355475 1242 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1243 entry->flags = 0;
1244}
1245
1246static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1247 u32 index, int *nent, int maxnent)
1248{
1249 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1250 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1251 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1252 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1253 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1254 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1255 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1256 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1257 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1258 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1259 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1260 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1261 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1262 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1263 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1264 bit(X86_FEATURE_PGE) |
1265 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1266 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1267 bit(X86_FEATURE_SYSCALL) |
334b8ad7 1268 (is_efer_nx() ? bit(X86_FEATURE_NX) : 0) |
07716717
DK		 1269#ifdef CONFIG_X86_64
1270 bit(X86_FEATURE_LM) |
1271#endif
1b2fd70c 1272 bit(X86_FEATURE_FXSR_OPT) |
07716717
DK		 1273 bit(X86_FEATURE_MMXEXT) |
1274 bit(X86_FEATURE_3DNOWEXT) |
1275 bit(X86_FEATURE_3DNOW);
1276 const u32 kvm_supported_word3_x86_features =
1277 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1278 const u32 kvm_supported_word6_x86_features =
d8017474
AG		 1279 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY) |
1280 bit(X86_FEATURE_SVM);
07716717 1281
19355475 1282 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1283 get_cpu();
1284 do_cpuid_1_ent(entry, function, index);
1285 ++*nent;
1286
1287 switch (function) {
1288 case 0:
1289 entry->eax = min(entry->eax, (u32)0xb);
1290 break;
1291 case 1:
1292 entry->edx &= kvm_supported_word0_x86_features;
1293 entry->ecx &= kvm_supported_word3_x86_features;
1294 break;
1295 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1296 * may return different values. This forces us to get_cpu() before
1297 * issuing the first command, and also to emulate this annoying behavior
1298 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1299 case 2: {
1300 int t, times = entry->eax & 0xff;
1301
1302 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1303 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1304 for (t = 1; t < times && *nent < maxnent; ++t) {
1305 do_cpuid_1_ent(&entry[t], function, 0);
1306 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1307 ++*nent;
1308 }
1309 break;
1310 }
1311 /* function 4 and 0xb have additional index. */
1312 case 4: {
14af3f3c 1313 int i, cache_type;
07716717
DK		 1314
1315 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1316 /* read more entries until cache_type is zero */
14af3f3c
HH		 1317 for (i = 1; *nent < maxnent; ++i) {
1318 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1319 if (!cache_type)
1320 break;
14af3f3c
HH		 1321 do_cpuid_1_ent(&entry[i], function, i);
1322 entry[i].flags |=
07716717
DK		 1323 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1324 ++*nent;
1325 }
1326 break;
1327 }
1328 case 0xb: {
14af3f3c 1329 int i, level_type;
07716717
DK		 1330
1331 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1332 /* read more entries until level_type is zero */
14af3f3c 1333 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1334 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1335 if (!level_type)
1336 break;
14af3f3c
HH		 1337 do_cpuid_1_ent(&entry[i], function, i);
1338 entry[i].flags |=
07716717
DK		 1339 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1340 ++*nent;
1341 }
1342 break;
1343 }
1344 case 0x80000000:
1345 entry->eax = min(entry->eax, 0x8000001a);
1346 break;
1347 case 0x80000001:
1348 entry->edx &= kvm_supported_word1_x86_features;
1349 entry->ecx &= kvm_supported_word6_x86_features;
1350 break;
1351 }
1352 put_cpu();
1353}
1354
674eea0f 1355static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1356 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1357{
1358 struct kvm_cpuid_entry2 *cpuid_entries;
1359 int limit, nent = 0, r = -E2BIG;
1360 u32 func;
1361
1362 if (cpuid->nent < 1)
1363 goto out;
1364 r = -ENOMEM;
1365 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1366 if (!cpuid_entries)
1367 goto out;
1368
1369 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1370 limit = cpuid_entries[0].eax;
1371 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1372 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1373 &nent, cpuid->nent);
07716717
DK		 1374 r = -E2BIG;
1375 if (nent >= cpuid->nent)
1376 goto out_free;
1377
1378 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1379 limit = cpuid_entries[nent - 1].eax;
1380 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1381 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1382 &nent, cpuid->nent);
07716717
DK		 1383 r = -EFAULT;
1384 if (copy_to_user(entries, cpuid_entries,
19355475 1385 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1386 goto out_free;
1387 cpuid->nent = nent;
1388 r = 0;
1389
1390out_free:
1391 vfree(cpuid_entries);
1392out:
1393 return r;
1394}
1395
313a3dc7
CO		 1396static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1397 struct kvm_lapic_state *s)
1398{
1399 vcpu_load(vcpu);
ad312c7c 1400 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1401 vcpu_put(vcpu);
1402
1403 return 0;
1404}
1405
1406static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1407 struct kvm_lapic_state *s)
1408{
1409 vcpu_load(vcpu);
ad312c7c 1410 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1411 kvm_apic_post_state_restore(vcpu);
1412 vcpu_put(vcpu);
1413
1414 return 0;
1415}
1416
f77bc6a4
ZX		 1417static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1418 struct kvm_interrupt *irq)
1419{
1420 if (irq->irq < 0 || irq->irq >= 256)
1421 return -EINVAL;
1422 if (irqchip_in_kernel(vcpu->kvm))
1423 return -ENXIO;
1424 vcpu_load(vcpu);
1425
ad312c7c
ZX		 1426 set_bit(irq->irq, vcpu->arch.irq_pending);
1427 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1428
1429 vcpu_put(vcpu);
1430
1431 return 0;
1432}
1433
c4abb7c9
JK		 1434static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1435{
1436 vcpu_load(vcpu);
1437 kvm_inject_nmi(vcpu);
1438 vcpu_put(vcpu);
1439
1440 return 0;
1441}
1442
b209749f
AK		 1443static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1444 struct kvm_tpr_access_ctl *tac)
1445{
1446 if (tac->flags)
1447 return -EINVAL;
1448 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1449 return 0;
1450}
1451
313a3dc7
CO		 1452long kvm_arch_vcpu_ioctl(struct file *filp,
1453 unsigned int ioctl, unsigned long arg)
1454{
1455 struct kvm_vcpu *vcpu = filp->private_data;
1456 void __user *argp = (void __user *)arg;
1457 int r;
b772ff36 1458 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1459
1460 switch (ioctl) {
1461 case KVM_GET_LAPIC: {
b772ff36 1462 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1463
b772ff36
DH		 1464 r = -ENOMEM;
1465 if (!lapic)
1466 goto out;
1467 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1468 if (r)
1469 goto out;
1470 r = -EFAULT;
b772ff36 1471 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1472 goto out;
1473 r = 0;
1474 break;
1475 }
1476 case KVM_SET_LAPIC: {
b772ff36
DH		 1477 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1478 r = -ENOMEM;
1479 if (!lapic)
1480 goto out;
313a3dc7 1481 r = -EFAULT;
b772ff36 1482 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1483 goto out;
b772ff36 1484 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1485 if (r)
1486 goto out;
1487 r = 0;
1488 break;
1489 }
f77bc6a4
ZX		 1490 case KVM_INTERRUPT: {
1491 struct kvm_interrupt irq;
1492
1493 r = -EFAULT;
1494 if (copy_from_user(&irq, argp, sizeof irq))
1495 goto out;
1496 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1497 if (r)
1498 goto out;
1499 r = 0;
1500 break;
1501 }
c4abb7c9
JK		 1502 case KVM_NMI: {
1503 r = kvm_vcpu_ioctl_nmi(vcpu);
1504 if (r)
1505 goto out;
1506 r = 0;
1507 break;
1508 }
313a3dc7
CO		 1509 case KVM_SET_CPUID: {
1510 struct kvm_cpuid __user *cpuid_arg = argp;
1511 struct kvm_cpuid cpuid;
1512
1513 r = -EFAULT;
1514 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1515 goto out;
1516 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1517 if (r)
1518 goto out;
1519 break;
1520 }
07716717
DK		 1521 case KVM_SET_CPUID2: {
1522 struct kvm_cpuid2 __user *cpuid_arg = argp;
1523 struct kvm_cpuid2 cpuid;
1524
1525 r = -EFAULT;
1526 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1527 goto out;
1528 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1529 cpuid_arg->entries);
07716717
DK		 1530 if (r)
1531 goto out;
1532 break;
1533 }
1534 case KVM_GET_CPUID2: {
1535 struct kvm_cpuid2 __user *cpuid_arg = argp;
1536 struct kvm_cpuid2 cpuid;
1537
1538 r = -EFAULT;
1539 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1540 goto out;
1541 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1542 cpuid_arg->entries);
07716717
DK		 1543 if (r)
1544 goto out;
1545 r = -EFAULT;
1546 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1547 goto out;
1548 r = 0;
1549 break;
1550 }
313a3dc7
CO		 1551 case KVM_GET_MSRS:
1552 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1553 break;
1554 case KVM_SET_MSRS:
1555 r = msr_io(vcpu, argp, do_set_msr, 0);
1556 break;
b209749f
AK		 1557 case KVM_TPR_ACCESS_REPORTING: {
1558 struct kvm_tpr_access_ctl tac;
1559
1560 r = -EFAULT;
1561 if (copy_from_user(&tac, argp, sizeof tac))
1562 goto out;
1563 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1564 if (r)
1565 goto out;
1566 r = -EFAULT;
1567 if (copy_to_user(argp, &tac, sizeof tac))
1568 goto out;
1569 r = 0;
1570 break;
1571 };
b93463aa
AK		 1572 case KVM_SET_VAPIC_ADDR: {
1573 struct kvm_vapic_addr va;
1574
1575 r = -EINVAL;
1576 if (!irqchip_in_kernel(vcpu->kvm))
1577 goto out;
1578 r = -EFAULT;
1579 if (copy_from_user(&va, argp, sizeof va))
1580 goto out;
1581 r = 0;
1582 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1583 break;
1584 }
313a3dc7
CO		 1585 default:
1586 r = -EINVAL;
1587 }
1588out:
b772ff36
DH		 1589 if (lapic)
1590 kfree(lapic);
313a3dc7
CO		 1591 return r;
1592}
1593
1fe779f8
CO		 1594static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1595{
1596 int ret;
1597
1598 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1599 return -1;
1600 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1601 return ret;
1602}
1603
1604static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1605 u32 kvm_nr_mmu_pages)
1606{
1607 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1608 return -EINVAL;
1609
72dc67a6 1610 down_write(&kvm->slots_lock);
1fe779f8
CO		 1611
1612 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1613 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1614
72dc67a6 1615 up_write(&kvm->slots_lock);
1fe779f8
CO		 1616 return 0;
1617}
1618
1619static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1620{
f05e70ac 1621 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1622}
1623
e9f85cde
ZX		 1624gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1625{
1626 int i;
1627 struct kvm_mem_alias *alias;
1628
d69fb81f
ZX		 1629 for (i = 0; i < kvm->arch.naliases; ++i) {
1630 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1631 if (gfn >= alias->base_gfn
1632 && gfn < alias->base_gfn + alias->npages)
1633 return alias->target_gfn + gfn - alias->base_gfn;
1634 }
1635 return gfn;
1636}
1637
1fe779f8
CO		 1638/*
1639 * Set a new alias region. Aliases map a portion of physical memory into
1640 * another portion. This is useful for memory windows, for example the PC
1641 * VGA region.
1642 */
1643static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1644 struct kvm_memory_alias *alias)
1645{
1646 int r, n;
1647 struct kvm_mem_alias *p;
1648
1649 r = -EINVAL;
1650 /* General sanity checks */
1651 if (alias->memory_size & (PAGE_SIZE - 1))
1652 goto out;
1653 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1654 goto out;
1655 if (alias->slot >= KVM_ALIAS_SLOTS)
1656 goto out;
1657 if (alias->guest_phys_addr + alias->memory_size
1658 < alias->guest_phys_addr)
1659 goto out;
1660 if (alias->target_phys_addr + alias->memory_size
1661 < alias->target_phys_addr)
1662 goto out;
1663
72dc67a6 1664 down_write(&kvm->slots_lock);
a1708ce8 1665 spin_lock(&kvm->mmu_lock);
1fe779f8 1666
d69fb81f 1667 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1668 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1669 p->npages = alias->memory_size >> PAGE_SHIFT;
1670 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1671
1672 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1673 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1674 break;
d69fb81f 1675 kvm->arch.naliases = n;
1fe779f8 1676
a1708ce8 1677 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1678 kvm_mmu_zap_all(kvm);
1679
72dc67a6 1680 up_write(&kvm->slots_lock);
1fe779f8
CO		 1681
1682 return 0;
1683
1684out:
1685 return r;
1686}
1687
1688static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1689{
1690 int r;
1691
1692 r = 0;
1693 switch (chip->chip_id) {
1694 case KVM_IRQCHIP_PIC_MASTER:
1695 memcpy(&chip->chip.pic,
1696 &pic_irqchip(kvm)->pics[0],
1697 sizeof(struct kvm_pic_state));
1698 break;
1699 case KVM_IRQCHIP_PIC_SLAVE:
1700 memcpy(&chip->chip.pic,
1701 &pic_irqchip(kvm)->pics[1],
1702 sizeof(struct kvm_pic_state));
1703 break;
1704 case KVM_IRQCHIP_IOAPIC:
1705 memcpy(&chip->chip.ioapic,
1706 ioapic_irqchip(kvm),
1707 sizeof(struct kvm_ioapic_state));
1708 break;
1709 default:
1710 r = -EINVAL;
1711 break;
1712 }
1713 return r;
1714}
1715
1716static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1717{
1718 int r;
1719
1720 r = 0;
1721 switch (chip->chip_id) {
1722 case KVM_IRQCHIP_PIC_MASTER:
1723 memcpy(&pic_irqchip(kvm)->pics[0],
1724 &chip->chip.pic,
1725 sizeof(struct kvm_pic_state));
1726 break;
1727 case KVM_IRQCHIP_PIC_SLAVE:
1728 memcpy(&pic_irqchip(kvm)->pics[1],
1729 &chip->chip.pic,
1730 sizeof(struct kvm_pic_state));
1731 break;
1732 case KVM_IRQCHIP_IOAPIC:
1733 memcpy(ioapic_irqchip(kvm),
1734 &chip->chip.ioapic,
1735 sizeof(struct kvm_ioapic_state));
1736 break;
1737 default:
1738 r = -EINVAL;
1739 break;
1740 }
1741 kvm_pic_update_irq(pic_irqchip(kvm));
1742 return r;
1743}
1744
e0f63cb9
SY		 1745static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1746{
1747 int r = 0;
1748
1749 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1750 return r;
1751}
1752
1753static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1754{
1755 int r = 0;
1756
1757 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1758 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1759 return r;
1760}
1761
52d939a0
MT		 1762static int kvm_vm_ioctl_reinject(struct kvm *kvm,
1763 struct kvm_reinject_control *control)
1764{
1765 if (!kvm->arch.vpit)
1766 return -ENXIO;
1767 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
1768 return 0;
1769}
1770
5bb064dc
ZX		 1771/*
1772 * Get (and clear) the dirty memory log for a memory slot.
1773 */
1774int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1775 struct kvm_dirty_log *log)
1776{
1777 int r;
1778 int n;
1779 struct kvm_memory_slot *memslot;
1780 int is_dirty = 0;
1781
72dc67a6 1782 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1783
1784 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1785 if (r)
1786 goto out;
1787
1788 /* If nothing is dirty, don't bother messing with page tables. */
1789 if (is_dirty) {
1790 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1791 kvm_flush_remote_tlbs(kvm);
1792 memslot = &kvm->memslots[log->slot];
1793 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1794 memset(memslot->dirty_bitmap, 0, n);
1795 }
1796 r = 0;
1797out:
72dc67a6 1798 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1799 return r;
1800}
1801
1fe779f8
CO		 1802long kvm_arch_vm_ioctl(struct file *filp,
1803 unsigned int ioctl, unsigned long arg)
1804{
1805 struct kvm *kvm = filp->private_data;
1806 void __user *argp = (void __user *)arg;
1807 int r = -EINVAL;
f0d66275
DH		 1808 /*
1809 * This union makes it completely explicit to gcc-3.x
1810 * that these two variables' stack usage should be
1811 * combined, not added together.
1812 */
1813 union {
1814 struct kvm_pit_state ps;
1815 struct kvm_memory_alias alias;
1816 } u;
1fe779f8
CO		 1817
1818 switch (ioctl) {
1819 case KVM_SET_TSS_ADDR:
1820 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1821 if (r < 0)
1822 goto out;
1823 break;
1824 case KVM_SET_MEMORY_REGION: {
1825 struct kvm_memory_region kvm_mem;
1826 struct kvm_userspace_memory_region kvm_userspace_mem;
1827
1828 r = -EFAULT;
1829 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1830 goto out;
1831 kvm_userspace_mem.slot = kvm_mem.slot;
1832 kvm_userspace_mem.flags = kvm_mem.flags;
1833 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1834 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1835 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1836 if (r)
1837 goto out;
1838 break;
1839 }
1840 case KVM_SET_NR_MMU_PAGES:
1841 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1842 if (r)
1843 goto out;
1844 break;
1845 case KVM_GET_NR_MMU_PAGES:
1846 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1847 break;
f0d66275 1848 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1849 r = -EFAULT;
f0d66275 1850 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1851 goto out;
f0d66275 1852 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1853 if (r)
1854 goto out;
1855 break;
1fe779f8
CO		 1856 case KVM_CREATE_IRQCHIP:
1857 r = -ENOMEM;
d7deeeb0
ZX		 1858 kvm->arch.vpic = kvm_create_pic(kvm);
1859 if (kvm->arch.vpic) {
1fe779f8
CO		 1860 r = kvm_ioapic_init(kvm);
1861 if (r) {
d7deeeb0
ZX		 1862 kfree(kvm->arch.vpic);
1863 kvm->arch.vpic = NULL;
1fe779f8
CO		 1864 goto out;
1865 }
1866 } else
1867 goto out;
399ec807
AK		 1868 r = kvm_setup_default_irq_routing(kvm);
1869 if (r) {
1870 kfree(kvm->arch.vpic);
1871 kfree(kvm->arch.vioapic);
1872 goto out;
1873 }
1fe779f8 1874 break;
7837699f 1875 case KVM_CREATE_PIT:
269e05e4
AK		 1876 mutex_lock(&kvm->lock);
1877 r = -EEXIST;
1878 if (kvm->arch.vpit)
1879 goto create_pit_unlock;
7837699f
SY		 1880 r = -ENOMEM;
1881 kvm->arch.vpit = kvm_create_pit(kvm);
1882 if (kvm->arch.vpit)
1883 r = 0;
269e05e4
AK		 1884 create_pit_unlock:
1885 mutex_unlock(&kvm->lock);
7837699f 1886 break;
4925663a 1887 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 1888 case KVM_IRQ_LINE: {
1889 struct kvm_irq_level irq_event;
1890
1891 r = -EFAULT;
1892 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1893 goto out;
1894 if (irqchip_in_kernel(kvm)) {
4925663a 1895 __s32 status;
1fe779f8 1896 mutex_lock(&kvm->lock);
4925663a
GN		 1897 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
1898 irq_event.irq, irq_event.level);
1fe779f8 1899 mutex_unlock(&kvm->lock);
4925663a
GN		 1900 if (ioctl == KVM_IRQ_LINE_STATUS) {
1901 irq_event.status = status;
1902 if (copy_to_user(argp, &irq_event,
1903 sizeof irq_event))
1904 goto out;
1905 }
1fe779f8
CO		 1906 r = 0;
1907 }
1908 break;
1909 }
1910 case KVM_GET_IRQCHIP: {
1911 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1912 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1913
f0d66275
DH		 1914 r = -ENOMEM;
1915 if (!chip)
1fe779f8 1916 goto out;
f0d66275
DH		 1917 r = -EFAULT;
1918 if (copy_from_user(chip, argp, sizeof *chip))
1919 goto get_irqchip_out;
1fe779f8
CO		 1920 r = -ENXIO;
1921 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1922 goto get_irqchip_out;
1923 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1924 if (r)
f0d66275 1925 goto get_irqchip_out;
1fe779f8 1926 r = -EFAULT;
f0d66275
DH		 1927 if (copy_to_user(argp, chip, sizeof *chip))
1928 goto get_irqchip_out;
1fe779f8 1929 r = 0;
f0d66275
DH		 1930 get_irqchip_out:
1931 kfree(chip);
1932 if (r)
1933 goto out;
1fe779f8
CO		 1934 break;
1935 }
1936 case KVM_SET_IRQCHIP: {
1937 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1938 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1939
f0d66275
DH		 1940 r = -ENOMEM;
1941 if (!chip)
1fe779f8 1942 goto out;
f0d66275
DH		 1943 r = -EFAULT;
1944 if (copy_from_user(chip, argp, sizeof *chip))
1945 goto set_irqchip_out;
1fe779f8
CO		 1946 r = -ENXIO;
1947 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1948 goto set_irqchip_out;
1949 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 1950 if (r)
f0d66275 1951 goto set_irqchip_out;
1fe779f8 1952 r = 0;
f0d66275
DH		 1953 set_irqchip_out:
1954 kfree(chip);
1955 if (r)
1956 goto out;
1fe779f8
CO		 1957 break;
1958 }
e0f63cb9 1959 case KVM_GET_PIT: {
e0f63cb9 1960 r = -EFAULT;
f0d66275 1961 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1962 goto out;
1963 r = -ENXIO;
1964 if (!kvm->arch.vpit)
1965 goto out;
f0d66275 1966 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 1967 if (r)
1968 goto out;
1969 r = -EFAULT;
f0d66275 1970 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1971 goto out;
1972 r = 0;
1973 break;
1974 }
1975 case KVM_SET_PIT: {
e0f63cb9 1976 r = -EFAULT;
f0d66275 1977 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 1978 goto out;
1979 r = -ENXIO;
1980 if (!kvm->arch.vpit)
1981 goto out;
f0d66275 1982 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 1983 if (r)
1984 goto out;
1985 r = 0;
1986 break;
1987 }
52d939a0
MT		 1988 case KVM_REINJECT_CONTROL: {
1989 struct kvm_reinject_control control;
1990 r = -EFAULT;
1991 if (copy_from_user(&control, argp, sizeof(control)))
1992 goto out;
1993 r = kvm_vm_ioctl_reinject(kvm, &control);
1994 if (r)
1995 goto out;
1996 r = 0;
1997 break;
1998 }
1fe779f8
CO		 1999 default:
2000 ;
2001 }
2002out:
2003 return r;
2004}
2005
a16b043c 2006static void kvm_init_msr_list(void)
043405e1
CO		 2007{
2008 u32 dummy[2];
2009 unsigned i, j;
2010
2011 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2012 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2013 continue;
2014 if (j < i)
2015 msrs_to_save[j] = msrs_to_save[i];
2016 j++;
2017 }
2018 num_msrs_to_save = j;
2019}
2020
bbd9b64e
CO		 2021/*
2022 * Only apic need an MMIO device hook, so shortcut now..
2023 */
2024static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2025 gpa_t addr, int len,
2026 int is_write)
bbd9b64e
CO		 2027{
2028 struct kvm_io_device *dev;
2029
ad312c7c
ZX		 2030 if (vcpu->arch.apic) {
2031 dev = &vcpu->arch.apic->dev;
92760499 2032 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 2033 return dev;
2034 }
2035 return NULL;
2036}
2037
2038
2039static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2040 gpa_t addr, int len,
2041 int is_write)
bbd9b64e
CO		 2042{
2043 struct kvm_io_device *dev;
2044
92760499 2045 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 2046 if (dev == NULL)
92760499
LV		 2047 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
2048 is_write);
bbd9b64e
CO		 2049 return dev;
2050}
2051
cded19f3
HE		 2052static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2053 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2054{
2055 void *data = val;
10589a46 2056 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2057
2058 while (bytes) {
ad312c7c 2059 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2060 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2061 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2062 int ret;
2063
10589a46
MT		 2064 if (gpa == UNMAPPED_GVA) {
2065 r = X86EMUL_PROPAGATE_FAULT;
2066 goto out;
2067 }
77c2002e 2068 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2069 if (ret < 0) {
2070 r = X86EMUL_UNHANDLEABLE;
2071 goto out;
2072 }
bbd9b64e 2073
77c2002e
IE		 2074 bytes -= toread;
2075 data += toread;
2076 addr += toread;
bbd9b64e 2077 }
10589a46 2078out:
10589a46 2079 return r;
bbd9b64e 2080}
77c2002e 2081
cded19f3
HE		 2082static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2083 struct kvm_vcpu *vcpu)
77c2002e
IE		 2084{
2085 void *data = val;
2086 int r = X86EMUL_CONTINUE;
2087
2088 while (bytes) {
2089 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2090 unsigned offset = addr & (PAGE_SIZE-1);
2091 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2092 int ret;
2093
2094 if (gpa == UNMAPPED_GVA) {
2095 r = X86EMUL_PROPAGATE_FAULT;
2096 goto out;
2097 }
2098 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2099 if (ret < 0) {
2100 r = X86EMUL_UNHANDLEABLE;
2101 goto out;
2102 }
2103
2104 bytes -= towrite;
2105 data += towrite;
2106 addr += towrite;
2107 }
2108out:
2109 return r;
2110}
2111
bbd9b64e 2112
bbd9b64e
CO		 2113static int emulator_read_emulated(unsigned long addr,
2114 void *val,
2115 unsigned int bytes,
2116 struct kvm_vcpu *vcpu)
2117{
2118 struct kvm_io_device *mmio_dev;
2119 gpa_t gpa;
2120
2121 if (vcpu->mmio_read_completed) {
2122 memcpy(val, vcpu->mmio_data, bytes);
2123 vcpu->mmio_read_completed = 0;
2124 return X86EMUL_CONTINUE;
2125 }
2126
ad312c7c 2127 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2128
2129 /* For APIC access vmexit */
2130 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2131 goto mmio;
2132
77c2002e
IE		 2133 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2134 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2135 return X86EMUL_CONTINUE;
2136 if (gpa == UNMAPPED_GVA)
2137 return X86EMUL_PROPAGATE_FAULT;
2138
2139mmio:
2140 /*
2141 * Is this MMIO handled locally?
2142 */
10589a46 2143 mutex_lock(&vcpu->kvm->lock);
92760499 2144 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2145 if (mmio_dev) {
2146 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2147 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2148 return X86EMUL_CONTINUE;
2149 }
10589a46 2150 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2151
2152 vcpu->mmio_needed = 1;
2153 vcpu->mmio_phys_addr = gpa;
2154 vcpu->mmio_size = bytes;
2155 vcpu->mmio_is_write = 0;
2156
2157 return X86EMUL_UNHANDLEABLE;
2158}
2159
3200f405 2160int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2161 const void *val, int bytes)
bbd9b64e
CO		 2162{
2163 int ret;
2164
2165 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2166 if (ret < 0)
bbd9b64e 2167 return 0;
ad218f85 2168 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2169 return 1;
2170}
2171
2172static int emulator_write_emulated_onepage(unsigned long addr,
2173 const void *val,
2174 unsigned int bytes,
2175 struct kvm_vcpu *vcpu)
2176{
2177 struct kvm_io_device *mmio_dev;
10589a46
MT		 2178 gpa_t gpa;
2179
10589a46 2180 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2181
2182 if (gpa == UNMAPPED_GVA) {
c3c91fee 2183 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2184 return X86EMUL_PROPAGATE_FAULT;
2185 }
2186
2187 /* For APIC access vmexit */
2188 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2189 goto mmio;
2190
2191 if (emulator_write_phys(vcpu, gpa, val, bytes))
2192 return X86EMUL_CONTINUE;
2193
2194mmio:
2195 /*
2196 * Is this MMIO handled locally?
2197 */
10589a46 2198 mutex_lock(&vcpu->kvm->lock);
92760499 2199 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2200 if (mmio_dev) {
2201 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2202 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2203 return X86EMUL_CONTINUE;
2204 }
10589a46 2205 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2206
2207 vcpu->mmio_needed = 1;
2208 vcpu->mmio_phys_addr = gpa;
2209 vcpu->mmio_size = bytes;
2210 vcpu->mmio_is_write = 1;
2211 memcpy(vcpu->mmio_data, val, bytes);
2212
2213 return X86EMUL_CONTINUE;
2214}
2215
2216int emulator_write_emulated(unsigned long addr,
2217 const void *val,
2218 unsigned int bytes,
2219 struct kvm_vcpu *vcpu)
2220{
2221 /* Crossing a page boundary? */
2222 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2223 int rc, now;
2224
2225 now = -addr & ~PAGE_MASK;
2226 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2227 if (rc != X86EMUL_CONTINUE)
2228 return rc;
2229 addr += now;
2230 val += now;
2231 bytes -= now;
2232 }
2233 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2234}
2235EXPORT_SYMBOL_GPL(emulator_write_emulated);
2236
2237static int emulator_cmpxchg_emulated(unsigned long addr,
2238 const void *old,
2239 const void *new,
2240 unsigned int bytes,
2241 struct kvm_vcpu *vcpu)
2242{
2243 static int reported;
2244
2245 if (!reported) {
2246 reported = 1;
2247 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2248 }
2bacc55c
MT		 2249#ifndef CONFIG_X86_64
2250 /* guests cmpxchg8b have to be emulated atomically */
2251 if (bytes == 8) {
10589a46 2252 gpa_t gpa;
2bacc55c 2253 struct page *page;
c0b49b0d 2254 char *kaddr;
2bacc55c
MT		 2255 u64 val;
2256
10589a46
MT		 2257 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2258
2bacc55c
MT		 2259 if (gpa == UNMAPPED_GVA ||
2260 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2261 goto emul_write;
2262
2263 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2264 goto emul_write;
2265
2266 val = *(u64 *)new;
72dc67a6 2267
2bacc55c 2268 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2269
c0b49b0d
AM		 2270 kaddr = kmap_atomic(page, KM_USER0);
2271 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2272 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2273 kvm_release_page_dirty(page);
2274 }
3200f405 2275emul_write:
2bacc55c
MT		 2276#endif
2277
bbd9b64e
CO		 2278 return emulator_write_emulated(addr, new, bytes, vcpu);
2279}
2280
2281static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2282{
2283 return kvm_x86_ops->get_segment_base(vcpu, seg);
2284}
2285
2286int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2287{
a7052897 2288 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2289 return X86EMUL_CONTINUE;
2290}
2291
2292int emulate_clts(struct kvm_vcpu *vcpu)
2293{
54e445ca 2294 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2295 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2296 return X86EMUL_CONTINUE;
2297}
2298
2299int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2300{
2301 struct kvm_vcpu *vcpu = ctxt->vcpu;
2302
2303 switch (dr) {
2304 case 0 ... 3:
2305 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2306 return X86EMUL_CONTINUE;
2307 default:
b8688d51 2308 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2309 return X86EMUL_UNHANDLEABLE;
2310 }
2311}
2312
2313int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2314{
2315 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2316 int exception;
2317
2318 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2319 if (exception) {
2320 /* FIXME: better handling */
2321 return X86EMUL_UNHANDLEABLE;
2322 }
2323 return X86EMUL_CONTINUE;
2324}
2325
2326void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2327{
bbd9b64e 2328 u8 opcodes[4];
5fdbf976 2329 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2330 unsigned long rip_linear;
2331
f76c710d 2332 if (!printk_ratelimit())
bbd9b64e
CO		 2333 return;
2334
25be4608
GC		 2335 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2336
77c2002e 2337 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2338
2339 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2340 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2341}
2342EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2343
14af3f3c 2344static struct x86_emulate_ops emulate_ops = {
77c2002e 2345 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2346 .read_emulated = emulator_read_emulated,
2347 .write_emulated = emulator_write_emulated,
2348 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2349};
2350
5fdbf976
MT		 2351static void cache_all_regs(struct kvm_vcpu *vcpu)
2352{
2353 kvm_register_read(vcpu, VCPU_REGS_RAX);
2354 kvm_register_read(vcpu, VCPU_REGS_RSP);
2355 kvm_register_read(vcpu, VCPU_REGS_RIP);
2356 vcpu->arch.regs_dirty = ~0;
2357}
2358
bbd9b64e
CO		 2359int emulate_instruction(struct kvm_vcpu *vcpu,
2360 struct kvm_run *run,
2361 unsigned long cr2,
2362 u16 error_code,
571008da 2363 int emulation_type)
bbd9b64e
CO		 2364{
2365 int r;
571008da 2366 struct decode_cache *c;
bbd9b64e 2367
26eef70c 2368 kvm_clear_exception_queue(vcpu);
ad312c7c 2369 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2370 /*
2371 * TODO: fix x86_emulate.c to use guest_read/write_register
2372 * instead of direct ->regs accesses, can save hundred cycles
2373 * on Intel for instructions that don't read/change RSP, for
2374 * for example.
2375 */
2376 cache_all_regs(vcpu);
bbd9b64e
CO		 2377
2378 vcpu->mmio_is_write = 0;
ad312c7c 2379 vcpu->arch.pio.string = 0;
bbd9b64e 2380
571008da 2381 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2382 int cs_db, cs_l;
2383 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2384
ad312c7c
ZX		 2385 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2386 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2387 vcpu->arch.emulate_ctxt.mode =
2388 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2389 ? X86EMUL_MODE_REAL : cs_l
2390 ? X86EMUL_MODE_PROT64 : cs_db
2391 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2392
ad312c7c 2393 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2394
2395 /* Reject the instructions other than VMCALL/VMMCALL when
2396 * try to emulate invalid opcode */
2397 c = &vcpu->arch.emulate_ctxt.decode;
2398 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2399 (!(c->twobyte && c->b == 0x01 &&
2400 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2401 c->modrm_mod == 3 && c->modrm_rm == 1)))
2402 return EMULATE_FAIL;
2403
f2b5756b 2404 ++vcpu->stat.insn_emulation;
bbd9b64e 2405 if (r) {
f2b5756b 2406 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2407 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2408 return EMULATE_DONE;
2409 return EMULATE_FAIL;
2410 }
2411 }
2412
ad312c7c 2413 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2414
ad312c7c 2415 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2416 return EMULATE_DO_MMIO;
2417
2418 if ((r || vcpu->mmio_is_write) && run) {
2419 run->exit_reason = KVM_EXIT_MMIO;
2420 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2421 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2422 run->mmio.len = vcpu->mmio_size;
2423 run->mmio.is_write = vcpu->mmio_is_write;
2424 }
2425
2426 if (r) {
2427 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2428 return EMULATE_DONE;
2429 if (!vcpu->mmio_needed) {
2430 kvm_report_emulation_failure(vcpu, "mmio");
2431 return EMULATE_FAIL;
2432 }
2433 return EMULATE_DO_MMIO;
2434 }
2435
ad312c7c 2436 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2437
2438 if (vcpu->mmio_is_write) {
2439 vcpu->mmio_needed = 0;
2440 return EMULATE_DO_MMIO;
2441 }
2442
2443 return EMULATE_DONE;
2444}
2445EXPORT_SYMBOL_GPL(emulate_instruction);
2446
de7d789a
CO		 2447static int pio_copy_data(struct kvm_vcpu *vcpu)
2448{
ad312c7c 2449 void *p = vcpu->arch.pio_data;
0f346074 2450 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2451 unsigned bytes;
0f346074 2452 int ret;
de7d789a 2453
ad312c7c
ZX		 2454 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2455 if (vcpu->arch.pio.in)
0f346074 2456 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2457 else
0f346074
IE		 2458 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2459 return ret;
de7d789a
CO		 2460}
2461
2462int complete_pio(struct kvm_vcpu *vcpu)
2463{
ad312c7c 2464 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2465 long delta;
2466 int r;
5fdbf976 2467 unsigned long val;
de7d789a
CO		 2468
2469 if (!io->string) {
5fdbf976
MT		 2470 if (io->in) {
2471 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2472 memcpy(&val, vcpu->arch.pio_data, io->size);
2473 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2474 }
de7d789a
CO		 2475 } else {
2476 if (io->in) {
2477 r = pio_copy_data(vcpu);
5fdbf976 2478 if (r)
de7d789a 2479 return r;
de7d789a
CO		 2480 }
2481
2482 delta = 1;
2483 if (io->rep) {
2484 delta *= io->cur_count;
2485 /*
2486 * The size of the register should really depend on
2487 * current address size.
2488 */
5fdbf976
MT		 2489 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2490 val -= delta;
2491 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2492 }
2493 if (io->down)
2494 delta = -delta;
2495 delta *= io->size;
5fdbf976
MT		 2496 if (io->in) {
2497 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2498 val += delta;
2499 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2500 } else {
2501 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2502 val += delta;
2503 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2504 }
de7d789a
CO		 2505 }
2506
de7d789a
CO		 2507 io->count -= io->cur_count;
2508 io->cur_count = 0;
2509
2510 return 0;
2511}
2512
2513static void kernel_pio(struct kvm_io_device *pio_dev,
2514 struct kvm_vcpu *vcpu,
2515 void *pd)
2516{
2517 /* TODO: String I/O for in kernel device */
2518
2519 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2520 if (vcpu->arch.pio.in)
2521 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2522 vcpu->arch.pio.size,
de7d789a
CO		 2523 pd);
2524 else
ad312c7c
ZX		 2525 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2526 vcpu->arch.pio.size,
de7d789a
CO		 2527 pd);
2528 mutex_unlock(&vcpu->kvm->lock);
2529}
2530
2531static void pio_string_write(struct kvm_io_device *pio_dev,
2532 struct kvm_vcpu *vcpu)
2533{
ad312c7c
ZX		 2534 struct kvm_pio_request *io = &vcpu->arch.pio;
2535 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2536 int i;
2537
2538 mutex_lock(&vcpu->kvm->lock);
2539 for (i = 0; i < io->cur_count; i++) {
2540 kvm_iodevice_write(pio_dev, io->port,
2541 io->size,
2542 pd);
2543 pd += io->size;
2544 }
2545 mutex_unlock(&vcpu->kvm->lock);
2546}
2547
2548static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2549 gpa_t addr, int len,
2550 int is_write)
de7d789a 2551{
92760499 2552 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2553}
2554
2555int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2556 int size, unsigned port)
2557{
2558 struct kvm_io_device *pio_dev;
5fdbf976 2559 unsigned long val;
de7d789a
CO		 2560
2561 vcpu->run->exit_reason = KVM_EXIT_IO;
2562 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2563 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2564 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2565 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2566 vcpu->run->io.port = vcpu->arch.pio.port = port;
2567 vcpu->arch.pio.in = in;
2568 vcpu->arch.pio.string = 0;
2569 vcpu->arch.pio.down = 0;
ad312c7c 2570 vcpu->arch.pio.rep = 0;
de7d789a 2571
2714d1d3
FEL		 2572 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2573 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2574 handler);
2575 else
2576 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2577 handler);
2578
5fdbf976
MT		 2579 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2580 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2581
92760499 2582 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2583 if (pio_dev) {
ad312c7c 2584 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2585 complete_pio(vcpu);
2586 return 1;
2587 }
2588 return 0;
2589}
2590EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2591
2592int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2593 int size, unsigned long count, int down,
2594 gva_t address, int rep, unsigned port)
2595{
2596 unsigned now, in_page;
0f346074 2597 int ret = 0;
de7d789a
CO		 2598 struct kvm_io_device *pio_dev;
2599
2600 vcpu->run->exit_reason = KVM_EXIT_IO;
2601 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2602 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2603 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2604 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2605 vcpu->run->io.port = vcpu->arch.pio.port = port;
2606 vcpu->arch.pio.in = in;
2607 vcpu->arch.pio.string = 1;
2608 vcpu->arch.pio.down = down;
ad312c7c 2609 vcpu->arch.pio.rep = rep;
de7d789a 2610
2714d1d3
FEL		 2611 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2612 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2613 handler);
2614 else
2615 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2616 handler);
2617
de7d789a
CO		 2618 if (!count) {
2619 kvm_x86_ops->skip_emulated_instruction(vcpu);
2620 return 1;
2621 }
2622
2623 if (!down)
2624 in_page = PAGE_SIZE - offset_in_page(address);
2625 else
2626 in_page = offset_in_page(address) + size;
2627 now = min(count, (unsigned long)in_page / size);
0f346074 2628 if (!now)
de7d789a 2629 now = 1;
de7d789a
CO		 2630 if (down) {
2631 /*
2632 * String I/O in reverse. Yuck. Kill the guest, fix later.
2633 */
2634 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2635 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2636 return 1;
2637 }
2638 vcpu->run->io.count = now;
ad312c7c 2639 vcpu->arch.pio.cur_count = now;
de7d789a 2640
ad312c7c 2641 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2642 kvm_x86_ops->skip_emulated_instruction(vcpu);
2643
0f346074 2644 vcpu->arch.pio.guest_gva = address;
de7d789a 2645
92760499
LV		 2646 pio_dev = vcpu_find_pio_dev(vcpu, port,
2647 vcpu->arch.pio.cur_count,
2648 !vcpu->arch.pio.in);
ad312c7c 2649 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2650 /* string PIO write */
2651 ret = pio_copy_data(vcpu);
0f346074
IE		 2652 if (ret == X86EMUL_PROPAGATE_FAULT) {
2653 kvm_inject_gp(vcpu, 0);
2654 return 1;
2655 }
2656 if (ret == 0 && pio_dev) {
de7d789a
CO		 2657 pio_string_write(pio_dev, vcpu);
2658 complete_pio(vcpu);
ad312c7c 2659 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2660 ret = 1;
2661 }
2662 } else if (pio_dev)
2663 pr_unimpl(vcpu, "no string pio read support yet, "
2664 "port %x size %d count %ld\n",
2665 port, size, count);
2666
2667 return ret;
2668}
2669EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2670
c8076604
GH		 2671static void bounce_off(void *info)
2672{
2673 /* nothing */
2674}
2675
2676static unsigned int ref_freq;
2677static unsigned long tsc_khz_ref;
2678
2679static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2680 void *data)
2681{
2682 struct cpufreq_freqs *freq = data;
2683 struct kvm *kvm;
2684 struct kvm_vcpu *vcpu;
2685 int i, send_ipi = 0;
2686
2687 if (!ref_freq)
2688 ref_freq = freq->old;
2689
2690 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
2691 return 0;
2692 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
2693 return 0;
2694 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
2695
2696 spin_lock(&kvm_lock);
2697 list_for_each_entry(kvm, &vm_list, vm_list) {
2698 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
2699 vcpu = kvm->vcpus[i];
2700 if (!vcpu)
2701 continue;
2702 if (vcpu->cpu != freq->cpu)
2703 continue;
2704 if (!kvm_request_guest_time_update(vcpu))
2705 continue;
2706 if (vcpu->cpu != smp_processor_id())
2707 send_ipi++;
2708 }
2709 }
2710 spin_unlock(&kvm_lock);
2711
2712 if (freq->old < freq->new && send_ipi) {
2713 /*
2714 * We upscale the frequency. Must make the guest
2715 * doesn't see old kvmclock values while running with
2716 * the new frequency, otherwise we risk the guest sees
2717 * time go backwards.
2718 *
2719 * In case we update the frequency for another cpu
2720 * (which might be in guest context) send an interrupt
2721 * to kick the cpu out of guest context. Next time
2722 * guest context is entered kvmclock will be updated,
2723 * so the guest will not see stale values.
2724 */
2725 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
2726 }
2727 return 0;
2728}
2729
2730static struct notifier_block kvmclock_cpufreq_notifier_block = {
2731 .notifier_call = kvmclock_cpufreq_notifier
2732};
2733
f8c16bba 2734int kvm_arch_init(void *opaque)
043405e1 2735{
c8076604 2736 int r, cpu;
f8c16bba
ZX		 2737 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2738
f8c16bba
ZX		 2739 if (kvm_x86_ops) {
2740 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2741 r = -EEXIST;
2742 goto out;
f8c16bba
ZX		 2743 }
2744
2745 if (!ops->cpu_has_kvm_support()) {
2746 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2747 r = -EOPNOTSUPP;
2748 goto out;
f8c16bba
ZX		 2749 }
2750 if (ops->disabled_by_bios()) {
2751 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2752 r = -EOPNOTSUPP;
2753 goto out;
f8c16bba
ZX		 2754 }
2755
97db56ce
AK		 2756 r = kvm_mmu_module_init();
2757 if (r)
2758 goto out;
2759
2760 kvm_init_msr_list();
2761
f8c16bba 2762 kvm_x86_ops = ops;
56c6d28a 2763 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2764 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2765 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
64d4d521 2766 PT_DIRTY_MASK, PT64_NX_MASK, 0, 0);
c8076604
GH		 2767
2768 for_each_possible_cpu(cpu)
2769 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
2770 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
2771 tsc_khz_ref = tsc_khz;
2772 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
2773 CPUFREQ_TRANSITION_NOTIFIER);
2774 }
2775
f8c16bba 2776 return 0;
56c6d28a
ZX		 2777
2778out:
56c6d28a 2779 return r;
043405e1 2780}
8776e519 2781
f8c16bba
ZX		 2782void kvm_arch_exit(void)
2783{
888d256e
JK		 2784 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
2785 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
2786 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 2787 kvm_x86_ops = NULL;
56c6d28a
ZX		 2788 kvm_mmu_module_exit();
2789}
f8c16bba 2790
8776e519
HB		 2791int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2792{
2793 ++vcpu->stat.halt_exits;
2714d1d3 2794 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2795 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2796 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2797 return 1;
2798 } else {
2799 vcpu->run->exit_reason = KVM_EXIT_HLT;
2800 return 0;
2801 }
2802}
2803EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2804
2f333bcb
MT		 2805static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2806 unsigned long a1)
2807{
2808 if (is_long_mode(vcpu))
2809 return a0;
2810 else
2811 return a0 | ((gpa_t)a1 << 32);
2812}
2813
8776e519
HB		 2814int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2815{
2816 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2817 int r = 1;
8776e519 2818
5fdbf976
MT		 2819 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2820 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2821 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2822 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2823 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2824
2714d1d3
FEL		 2825 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2826
8776e519
HB		 2827 if (!is_long_mode(vcpu)) {
2828 nr &= 0xFFFFFFFF;
2829 a0 &= 0xFFFFFFFF;
2830 a1 &= 0xFFFFFFFF;
2831 a2 &= 0xFFFFFFFF;
2832 a3 &= 0xFFFFFFFF;
2833 }
2834
2835 switch (nr) {
b93463aa
AK		 2836 case KVM_HC_VAPIC_POLL_IRQ:
2837 ret = 0;
2838 break;
2f333bcb
MT		 2839 case KVM_HC_MMU_OP:
2840 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2841 break;
8776e519
HB		 2842 default:
2843 ret = -KVM_ENOSYS;
2844 break;
2845 }
5fdbf976 2846 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2847 ++vcpu->stat.hypercalls;
2f333bcb 2848 return r;
8776e519
HB		 2849}
2850EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2851
2852int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2853{
2854 char instruction[3];
2855 int ret = 0;
5fdbf976 2856 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2857
8776e519
HB		 2858
2859 /*
2860 * Blow out the MMU to ensure that no other VCPU has an active mapping
2861 * to ensure that the updated hypercall appears atomically across all
2862 * VCPUs.
2863 */
2864 kvm_mmu_zap_all(vcpu->kvm);
2865
8776e519 2866 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2867 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2868 != X86EMUL_CONTINUE)
2869 ret = -EFAULT;
2870
8776e519
HB		 2871 return ret;
2872}
2873
2874static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2875{
2876 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2877}
2878
2879void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2880{
2881 struct descriptor_table dt = { limit, base };
2882
2883 kvm_x86_ops->set_gdt(vcpu, &dt);
2884}
2885
2886void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2887{
2888 struct descriptor_table dt = { limit, base };
2889
2890 kvm_x86_ops->set_idt(vcpu, &dt);
2891}
2892
2893void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2894 unsigned long *rflags)
2895{
2d3ad1f4 2896 kvm_lmsw(vcpu, msw);
8776e519
HB		 2897 *rflags = kvm_x86_ops->get_rflags(vcpu);
2898}
2899
2900unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2901{
54e445ca
JR		 2902 unsigned long value;
2903
8776e519
HB		 2904 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2905 switch (cr) {
2906 case 0:
54e445ca
JR		 2907 value = vcpu->arch.cr0;
2908 break;
8776e519 2909 case 2:
54e445ca
JR		 2910 value = vcpu->arch.cr2;
2911 break;
8776e519 2912 case 3:
54e445ca
JR		 2913 value = vcpu->arch.cr3;
2914 break;
8776e519 2915 case 4:
54e445ca
JR		 2916 value = vcpu->arch.cr4;
2917 break;
152ff9be 2918 case 8:
54e445ca
JR		 2919 value = kvm_get_cr8(vcpu);
2920 break;
8776e519 2921 default:
b8688d51 2922 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2923 return 0;
2924 }
54e445ca
JR		 2925 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2926 (u32)((u64)value >> 32), handler);
2927
2928 return value;
8776e519
HB		 2929}
2930
2931void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2932 unsigned long *rflags)
2933{
54e445ca
JR		 2934 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2935 (u32)((u64)val >> 32), handler);
2936
8776e519
HB		 2937 switch (cr) {
2938 case 0:
2d3ad1f4 2939 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2940 *rflags = kvm_x86_ops->get_rflags(vcpu);
2941 break;
2942 case 2:
ad312c7c 2943 vcpu->arch.cr2 = val;
8776e519
HB		 2944 break;
2945 case 3:
2d3ad1f4 2946 kvm_set_cr3(vcpu, val);
8776e519
HB		 2947 break;
2948 case 4:
2d3ad1f4 2949 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2950 break;
152ff9be 2951 case 8:
2d3ad1f4 2952 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2953 break;
8776e519 2954 default:
b8688d51 2955 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2956 }
2957}
2958
07716717
DK		 2959static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2960{
ad312c7c
ZX		 2961 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2962 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2963
2964 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2965 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 2966 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 2967 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2968 if (ej->function == e->function) {
2969 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2970 return j;
2971 }
2972 }
2973 return 0; /* silence gcc, even though control never reaches here */
2974}
2975
2976/* find an entry with matching function, matching index (if needed), and that
2977 * should be read next (if it's stateful) */
2978static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2979 u32 function, u32 index)
2980{
2981 if (e->function != function)
2982 return 0;
2983 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2984 return 0;
2985 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 2986 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 2987 return 0;
2988 return 1;
2989}
2990
d8017474
AG		 2991struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
2992 u32 function, u32 index)
8776e519
HB		 2993{
2994 int i;
d8017474 2995 struct kvm_cpuid_entry2 *best = NULL;
8776e519 2996
ad312c7c 2997 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 2998 struct kvm_cpuid_entry2 *e;
2999
ad312c7c 3000 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3001 if (is_matching_cpuid_entry(e, function, index)) {
3002 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3003 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3004 best = e;
3005 break;
3006 }
3007 /*
3008 * Both basic or both extended?
3009 */
3010 if (((e->function ^ function) & 0x80000000) == 0)
3011 if (!best || e->function > best->function)
3012 best = e;
3013 }
d8017474
AG		 3014 return best;
3015}
3016
3017void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3018{
3019 u32 function, index;
3020 struct kvm_cpuid_entry2 *best;
3021
3022 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3023 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3024 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3025 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3026 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3027 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3028 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3029 if (best) {
5fdbf976
MT		 3030 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3031 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3032 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3033 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3034 }
8776e519 3035 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 3036 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 3037 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
3038 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
3039 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
3040 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 3041}
3042EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3043
b6c7a5dc
HB		 3044/*
3045 * Check if userspace requested an interrupt window, and that the
3046 * interrupt window is open.
3047 *
3048 * No need to exit to userspace if we already have an interrupt queued.
3049 */
3050static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3051 struct kvm_run *kvm_run)
3052{
ad312c7c 3053 return (!vcpu->arch.irq_summary &&
b6c7a5dc 3054 kvm_run->request_interrupt_window &&
ad312c7c 3055 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 3056 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
3057}
3058
3059static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3060 struct kvm_run *kvm_run)
3061{
3062 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3063 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3064 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3065 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3066 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3067 else
b6c7a5dc 3068 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 3069 (vcpu->arch.interrupt_window_open &&
3070 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 3071}
3072
b93463aa
AK		 3073static void vapic_enter(struct kvm_vcpu *vcpu)
3074{
3075 struct kvm_lapic *apic = vcpu->arch.apic;
3076 struct page *page;
3077
3078 if (!apic || !apic->vapic_addr)
3079 return;
3080
3081 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3082
3083 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3084}
3085
3086static void vapic_exit(struct kvm_vcpu *vcpu)
3087{
3088 struct kvm_lapic *apic = vcpu->arch.apic;
3089
3090 if (!apic || !apic->vapic_addr)
3091 return;
3092
f8b78fa3 3093 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3094 kvm_release_page_dirty(apic->vapic_page);
3095 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3096 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3097}
3098
d7690175 3099static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3100{
3101 int r;
3102
2e53d63a
MT		 3103 if (vcpu->requests)
3104 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3105 kvm_mmu_unload(vcpu);
3106
b6c7a5dc
HB		 3107 r = kvm_mmu_reload(vcpu);
3108 if (unlikely(r))
3109 goto out;
3110
2f52d58c
AK		 3111 if (vcpu->requests) {
3112 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3113 __kvm_migrate_timers(vcpu);
c8076604
GH		 3114 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3115 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3116 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3117 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3118 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3119 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3120 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3121 &vcpu->requests)) {
3122 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3123 r = 0;
3124 goto out;
3125 }
71c4dfaf
JR		 3126 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3127 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3128 r = 0;
3129 goto out;
3130 }
2f52d58c 3131 }
b93463aa 3132
06e05645 3133 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 3134 kvm_inject_pending_timer_irqs(vcpu);
3135
3136 preempt_disable();
3137
3138 kvm_x86_ops->prepare_guest_switch(vcpu);
3139 kvm_load_guest_fpu(vcpu);
3140
3141 local_irq_disable();
3142
d7690175 3143 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3144 local_irq_enable();
3145 preempt_enable();
3146 r = 1;
3147 goto out;
3148 }
3149
e9571ed5
MT		 3150 vcpu->guest_mode = 1;
3151 /*
3152 * Make sure that guest_mode assignment won't happen after
3153 * testing the pending IRQ vector bitmap.
3154 */
3155 smp_wmb();
3156
ad312c7c 3157 if (vcpu->arch.exception.pending)
298101da
AK		 3158 __queue_exception(vcpu);
3159 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3160 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 3161 else
b6c7a5dc
HB		 3162 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
3163
b93463aa
AK		 3164 kvm_lapic_sync_to_vapic(vcpu);
3165
3200f405
MT		 3166 up_read(&vcpu->kvm->slots_lock);
3167
b6c7a5dc
HB		 3168 kvm_guest_enter();
3169
42dbaa5a
JK		 3170 get_debugreg(vcpu->arch.host_dr6, 6);
3171 get_debugreg(vcpu->arch.host_dr7, 7);
3172 if (unlikely(vcpu->arch.switch_db_regs)) {
3173 get_debugreg(vcpu->arch.host_db[0], 0);
3174 get_debugreg(vcpu->arch.host_db[1], 1);
3175 get_debugreg(vcpu->arch.host_db[2], 2);
3176 get_debugreg(vcpu->arch.host_db[3], 3);
3177
3178 set_debugreg(0, 7);
3179 set_debugreg(vcpu->arch.eff_db[0], 0);
3180 set_debugreg(vcpu->arch.eff_db[1], 1);
3181 set_debugreg(vcpu->arch.eff_db[2], 2);
3182 set_debugreg(vcpu->arch.eff_db[3], 3);
3183 }
b6c7a5dc 3184
2714d1d3 3185 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3186 kvm_x86_ops->run(vcpu, kvm_run);
3187
42dbaa5a
JK		 3188 if (unlikely(vcpu->arch.switch_db_regs)) {
3189 set_debugreg(0, 7);
3190 set_debugreg(vcpu->arch.host_db[0], 0);
3191 set_debugreg(vcpu->arch.host_db[1], 1);
3192 set_debugreg(vcpu->arch.host_db[2], 2);
3193 set_debugreg(vcpu->arch.host_db[3], 3);
3194 }
3195 set_debugreg(vcpu->arch.host_dr6, 6);
3196 set_debugreg(vcpu->arch.host_dr7, 7);
3197
b6c7a5dc
HB		 3198 vcpu->guest_mode = 0;
3199 local_irq_enable();
3200
3201 ++vcpu->stat.exits;
3202
3203 /*
3204 * We must have an instruction between local_irq_enable() and
3205 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3206 * the interrupt shadow. The stat.exits increment will do nicely.
3207 * But we need to prevent reordering, hence this barrier():
3208 */
3209 barrier();
3210
3211 kvm_guest_exit();
3212
3213 preempt_enable();
3214
3200f405
MT		 3215 down_read(&vcpu->kvm->slots_lock);
3216
b6c7a5dc
HB		 3217 /*
3218 * Profile KVM exit RIPs:
3219 */
3220 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3221 unsigned long rip = kvm_rip_read(vcpu);
3222 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3223 }
3224
ad312c7c
ZX		 3225 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
3226 vcpu->arch.exception.pending = false;
298101da 3227
b93463aa
AK		 3228 kvm_lapic_sync_from_vapic(vcpu);
3229
b6c7a5dc 3230 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3231out:
3232 return r;
3233}
b6c7a5dc 3234
d7690175
MT		 3235static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3236{
3237 int r;
3238
3239 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3240 pr_debug("vcpu %d received sipi with vector # %x\n",
3241 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3242 kvm_lapic_reset(vcpu);
5f179287 3243 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3244 if (r)
3245 return r;
3246 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3247 }
3248
d7690175
MT		 3249 down_read(&vcpu->kvm->slots_lock);
3250 vapic_enter(vcpu);
3251
3252 r = 1;
3253 while (r > 0) {
af2152f5 3254 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3255 r = vcpu_enter_guest(vcpu, kvm_run);
3256 else {
3257 up_read(&vcpu->kvm->slots_lock);
3258 kvm_vcpu_block(vcpu);
3259 down_read(&vcpu->kvm->slots_lock);
3260 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3261 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
3262 vcpu->arch.mp_state =
3263 KVM_MP_STATE_RUNNABLE;
3264 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
3265 r = -EINTR;
3266 }
3267
3268 if (r > 0) {
3269 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3270 r = -EINTR;
3271 kvm_run->exit_reason = KVM_EXIT_INTR;
3272 ++vcpu->stat.request_irq_exits;
3273 }
3274 if (signal_pending(current)) {
3275 r = -EINTR;
3276 kvm_run->exit_reason = KVM_EXIT_INTR;
3277 ++vcpu->stat.signal_exits;
3278 }
3279 if (need_resched()) {
3280 up_read(&vcpu->kvm->slots_lock);
3281 kvm_resched(vcpu);
3282 down_read(&vcpu->kvm->slots_lock);
3283 }
3284 }
b6c7a5dc
HB		 3285 }
3286
d7690175 3287 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3288 post_kvm_run_save(vcpu, kvm_run);
3289
b93463aa
AK		 3290 vapic_exit(vcpu);
3291
b6c7a5dc
HB		 3292 return r;
3293}
3294
3295int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3296{
3297 int r;
3298 sigset_t sigsaved;
3299
3300 vcpu_load(vcpu);
3301
ac9f6dc0
AK		 3302 if (vcpu->sigset_active)
3303 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3304
a4535290 3305 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3306 kvm_vcpu_block(vcpu);
d7690175 3307 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3308 r = -EAGAIN;
3309 goto out;
b6c7a5dc
HB		 3310 }
3311
b6c7a5dc
HB		 3312 /* re-sync apic's tpr */
3313 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3314 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3315
ad312c7c 3316 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3317 r = complete_pio(vcpu);
3318 if (r)
3319 goto out;
3320 }
3321#if CONFIG_HAS_IOMEM
3322 if (vcpu->mmio_needed) {
3323 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3324 vcpu->mmio_read_completed = 1;
3325 vcpu->mmio_needed = 0;
3200f405
MT		 3326
3327 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3328 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3329 vcpu->arch.mmio_fault_cr2, 0,
3330 EMULTYPE_NO_DECODE);
3200f405 3331 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3332 if (r == EMULATE_DO_MMIO) {
3333 /*
3334 * Read-modify-write. Back to userspace.
3335 */
3336 r = 0;
3337 goto out;
3338 }
3339 }
3340#endif
5fdbf976
MT		 3341 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3342 kvm_register_write(vcpu, VCPU_REGS_RAX,
3343 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3344
3345 r = __vcpu_run(vcpu, kvm_run);
3346
3347out:
3348 if (vcpu->sigset_active)
3349 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3350
3351 vcpu_put(vcpu);
3352 return r;
3353}
3354
3355int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3356{
3357 vcpu_load(vcpu);
3358
5fdbf976
MT		 3359 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3360 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3361 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3362 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3363 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3364 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3365 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3366 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3367#ifdef CONFIG_X86_64
5fdbf976
MT		 3368 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3369 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3370 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3371 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3372 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3373 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3374 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3375 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3376#endif
3377
5fdbf976 3378 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3379 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3380
3381 /*
3382 * Don't leak debug flags in case they were set for guest debugging
3383 */
d0bfb940 3384 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3385 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3386
3387 vcpu_put(vcpu);
3388
3389 return 0;
3390}
3391
3392int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3393{
3394 vcpu_load(vcpu);
3395
5fdbf976
MT		 3396 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3397 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3398 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3399 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3400 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3401 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3402 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3403 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3404#ifdef CONFIG_X86_64
5fdbf976
MT		 3405 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3406 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3407 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3408 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3409 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3410 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3411 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3412 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3413
b6c7a5dc
HB		 3414#endif
3415
5fdbf976 3416 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3417 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3418
b6c7a5dc 3419
b4f14abd
JK		 3420 vcpu->arch.exception.pending = false;
3421
b6c7a5dc
HB		 3422 vcpu_put(vcpu);
3423
3424 return 0;
3425}
3426
3e6e0aab
GT		 3427void kvm_get_segment(struct kvm_vcpu *vcpu,
3428 struct kvm_segment *var, int seg)
b6c7a5dc 3429{
14af3f3c 3430 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3431}
3432
3433void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3434{
3435 struct kvm_segment cs;
3436
3e6e0aab 3437 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3438 *db = cs.db;
3439 *l = cs.l;
3440}
3441EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3442
3443int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3444 struct kvm_sregs *sregs)
3445{
3446 struct descriptor_table dt;
3447 int pending_vec;
3448
3449 vcpu_load(vcpu);
3450
3e6e0aab
GT		 3451 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3452 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3453 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3454 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3455 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3456 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3457
3e6e0aab
GT		 3458 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3459 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3460
3461 kvm_x86_ops->get_idt(vcpu, &dt);
3462 sregs->idt.limit = dt.limit;
3463 sregs->idt.base = dt.base;
3464 kvm_x86_ops->get_gdt(vcpu, &dt);
3465 sregs->gdt.limit = dt.limit;
3466 sregs->gdt.base = dt.base;
3467
3468 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3469 sregs->cr0 = vcpu->arch.cr0;
3470 sregs->cr2 = vcpu->arch.cr2;
3471 sregs->cr3 = vcpu->arch.cr3;
3472 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3473 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3474 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3475 sregs->apic_base = kvm_get_apic_base(vcpu);
3476
3477 if (irqchip_in_kernel(vcpu->kvm)) {
3478 memset(sregs->interrupt_bitmap, 0,
3479 sizeof sregs->interrupt_bitmap);
3480 pending_vec = kvm_x86_ops->get_irq(vcpu);
3481 if (pending_vec >= 0)
3482 set_bit(pending_vec,
3483 (unsigned long *)sregs->interrupt_bitmap);
3484 } else
ad312c7c 3485 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3486 sizeof sregs->interrupt_bitmap);
3487
3488 vcpu_put(vcpu);
3489
3490 return 0;
3491}
3492
62d9f0db
MT		 3493int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3494 struct kvm_mp_state *mp_state)
3495{
3496 vcpu_load(vcpu);
3497 mp_state->mp_state = vcpu->arch.mp_state;
3498 vcpu_put(vcpu);
3499 return 0;
3500}
3501
3502int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3503 struct kvm_mp_state *mp_state)
3504{
3505 vcpu_load(vcpu);
3506 vcpu->arch.mp_state = mp_state->mp_state;
3507 vcpu_put(vcpu);
3508 return 0;
3509}
3510
3e6e0aab 3511static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3512 struct kvm_segment *var, int seg)
3513{
14af3f3c 3514 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3515}
3516
37817f29
IE		 3517static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3518 struct kvm_segment *kvm_desct)
3519{
3520 kvm_desct->base = seg_desc->base0;
3521 kvm_desct->base |= seg_desc->base1 << 16;
3522 kvm_desct->base |= seg_desc->base2 << 24;
3523 kvm_desct->limit = seg_desc->limit0;
3524 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3525 if (seg_desc->g) {
3526 kvm_desct->limit <<= 12;
3527 kvm_desct->limit |= 0xfff;
3528 }
37817f29
IE		 3529 kvm_desct->selector = selector;
3530 kvm_desct->type = seg_desc->type;
3531 kvm_desct->present = seg_desc->p;
3532 kvm_desct->dpl = seg_desc->dpl;
3533 kvm_desct->db = seg_desc->d;
3534 kvm_desct->s = seg_desc->s;
3535 kvm_desct->l = seg_desc->l;
3536 kvm_desct->g = seg_desc->g;
3537 kvm_desct->avl = seg_desc->avl;
3538 if (!selector)
3539 kvm_desct->unusable = 1;
3540 else
3541 kvm_desct->unusable = 0;
3542 kvm_desct->padding = 0;
3543}
3544
b8222ad2
AS		 3545static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3546 u16 selector,
3547 struct descriptor_table *dtable)
37817f29
IE		 3548{
3549 if (selector & 1 << 2) {
3550 struct kvm_segment kvm_seg;
3551
3e6e0aab 3552 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3553
3554 if (kvm_seg.unusable)
3555 dtable->limit = 0;
3556 else
3557 dtable->limit = kvm_seg.limit;
3558 dtable->base = kvm_seg.base;
3559 }
3560 else
3561 kvm_x86_ops->get_gdt(vcpu, dtable);
3562}
3563
3564/* allowed just for 8 bytes segments */
3565static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3566 struct desc_struct *seg_desc)
3567{
98899aa0 3568 gpa_t gpa;
37817f29
IE		 3569 struct descriptor_table dtable;
3570 u16 index = selector >> 3;
3571
b8222ad2 3572 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3573
3574 if (dtable.limit < index * 8 + 7) {
3575 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3576 return 1;
3577 }
98899aa0
MT		 3578 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3579 gpa += index * 8;
3580 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3581}
3582
3583/* allowed just for 8 bytes segments */
3584static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3585 struct desc_struct *seg_desc)
3586{
98899aa0 3587 gpa_t gpa;
37817f29
IE		 3588 struct descriptor_table dtable;
3589 u16 index = selector >> 3;
3590
b8222ad2 3591 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3592
3593 if (dtable.limit < index * 8 + 7)
3594 return 1;
98899aa0
MT		 3595 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3596 gpa += index * 8;
3597 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3598}
3599
3600static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3601 struct desc_struct *seg_desc)
3602{
3603 u32 base_addr;
3604
3605 base_addr = seg_desc->base0;
3606 base_addr |= (seg_desc->base1 << 16);
3607 base_addr |= (seg_desc->base2 << 24);
3608
98899aa0 3609 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3610}
3611
37817f29
IE		 3612static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3613{
3614 struct kvm_segment kvm_seg;
3615
3e6e0aab 3616 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3617 return kvm_seg.selector;
3618}
3619
3620static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3621 u16 selector,
3622 struct kvm_segment *kvm_seg)
3623{
3624 struct desc_struct seg_desc;
3625
3626 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3627 return 1;
3628 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3629 return 0;
3630}
3631
2259e3a7 3632static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3633{
3634 struct kvm_segment segvar = {
3635 .base = selector << 4,
3636 .limit = 0xffff,
3637 .selector = selector,
3638 .type = 3,
3639 .present = 1,
3640 .dpl = 3,
3641 .db = 0,
3642 .s = 1,
3643 .l = 0,
3644 .g = 0,
3645 .avl = 0,
3646 .unusable = 0,
3647 };
3648 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3649 return 0;
3650}
3651
3e6e0aab
GT		 3652int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3653 int type_bits, int seg)
37817f29
IE		 3654{
3655 struct kvm_segment kvm_seg;
3656
f4bbd9aa
AK		 3657 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3658 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3659 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3660 return 1;
3661 kvm_seg.type |= type_bits;
3662
3663 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3664 seg != VCPU_SREG_LDTR)
3665 if (!kvm_seg.s)
3666 kvm_seg.unusable = 1;
3667
3e6e0aab 3668 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3669 return 0;
3670}
3671
3672static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3673 struct tss_segment_32 *tss)
3674{
3675 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3676 tss->eip = kvm_rip_read(vcpu);
37817f29 3677 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3678 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3679 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3680 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3681 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3682 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3683 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3684 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3685 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3686 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3687 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3688 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3689 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3690 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3691 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3692 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3693 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3694}
3695
3696static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3697 struct tss_segment_32 *tss)
3698{
3699 kvm_set_cr3(vcpu, tss->cr3);
3700
5fdbf976 3701 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3702 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3703
5fdbf976
MT		 3704 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3705 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3706 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3707 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3708 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3709 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3710 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3711 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3712
3e6e0aab 3713 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3714 return 1;
3715
3e6e0aab 3716 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3717 return 1;
3718
3e6e0aab 3719 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3720 return 1;
3721
3e6e0aab 3722 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3723 return 1;
3724
3e6e0aab 3725 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3726 return 1;
3727
3e6e0aab 3728 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3729 return 1;
3730
3e6e0aab 3731 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3732 return 1;
3733 return 0;
3734}
3735
3736static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3737 struct tss_segment_16 *tss)
3738{
5fdbf976 3739 tss->ip = kvm_rip_read(vcpu);
37817f29 3740 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3741 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3742 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3743 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3744 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3745 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3746 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3747 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3748 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3749
3750 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3751 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3752 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3753 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3754 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3755 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3756}
3757
3758static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3759 struct tss_segment_16 *tss)
3760{
5fdbf976 3761 kvm_rip_write(vcpu, tss->ip);
37817f29 3762 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3763 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3764 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3765 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3766 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3767 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3768 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3769 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3770 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3771
3e6e0aab 3772 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3773 return 1;
3774
3e6e0aab 3775 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3776 return 1;
3777
3e6e0aab 3778 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3779 return 1;
3780
3e6e0aab 3781 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3782 return 1;
3783
3e6e0aab 3784 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3785 return 1;
3786 return 0;
3787}
3788
8b2cf73c 3789static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3790 u32 old_tss_base,
37817f29
IE		 3791 struct desc_struct *nseg_desc)
3792{
3793 struct tss_segment_16 tss_segment_16;
3794 int ret = 0;
3795
34198bf8
MT		 3796 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3797 sizeof tss_segment_16))
37817f29
IE		 3798 goto out;
3799
3800 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3801
34198bf8
MT		 3802 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3803 sizeof tss_segment_16))
37817f29 3804 goto out;
34198bf8
MT		 3805
3806 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3807 &tss_segment_16, sizeof tss_segment_16))
3808 goto out;
3809
37817f29
IE		 3810 if (load_state_from_tss16(vcpu, &tss_segment_16))
3811 goto out;
3812
3813 ret = 1;
3814out:
3815 return ret;
3816}
3817
8b2cf73c 3818static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3819 u32 old_tss_base,
37817f29
IE		 3820 struct desc_struct *nseg_desc)
3821{
3822 struct tss_segment_32 tss_segment_32;
3823 int ret = 0;
3824
34198bf8
MT		 3825 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3826 sizeof tss_segment_32))
37817f29
IE		 3827 goto out;
3828
3829 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3830
34198bf8
MT		 3831 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3832 sizeof tss_segment_32))
3833 goto out;
3834
3835 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3836 &tss_segment_32, sizeof tss_segment_32))
37817f29 3837 goto out;
34198bf8 3838
37817f29
IE		 3839 if (load_state_from_tss32(vcpu, &tss_segment_32))
3840 goto out;
3841
3842 ret = 1;
3843out:
3844 return ret;
3845}
3846
3847int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3848{
3849 struct kvm_segment tr_seg;
3850 struct desc_struct cseg_desc;
3851 struct desc_struct nseg_desc;
3852 int ret = 0;
34198bf8
MT		 3853 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3854 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3855
34198bf8 3856 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3857
34198bf8
MT		 3858 /* FIXME: Handle errors. Failure to read either TSS or their
3859 * descriptors should generate a pagefault.
3860 */
37817f29
IE		 3861 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3862 goto out;
3863
34198bf8 3864 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3865 goto out;
3866
37817f29
IE		 3867 if (reason != TASK_SWITCH_IRET) {
3868 int cpl;
3869
3870 cpl = kvm_x86_ops->get_cpl(vcpu);
3871 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3872 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3873 return 1;
3874 }
3875 }
3876
3877 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3878 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3879 return 1;
3880 }
3881
3882 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3883 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3884 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3885 }
3886
3887 if (reason == TASK_SWITCH_IRET) {
3888 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3889 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3890 }
3891
3892 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3893
3894 if (nseg_desc.type & 8)
34198bf8 3895 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3896 &nseg_desc);
3897 else
34198bf8 3898 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3899 &nseg_desc);
3900
3901 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3902 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3903 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3904 }
3905
3906 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3907 nseg_desc.type |= (1 << 1);
37817f29
IE		 3908 save_guest_segment_descriptor(vcpu, tss_selector,
3909 &nseg_desc);
3910 }
3911
3912 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3913 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3914 tr_seg.type = 11;
3e6e0aab 3915 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3916out:
37817f29
IE		 3917 return ret;
3918}
3919EXPORT_SYMBOL_GPL(kvm_task_switch);
3920
b6c7a5dc
HB		 3921int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3922 struct kvm_sregs *sregs)
3923{
3924 int mmu_reset_needed = 0;
3925 int i, pending_vec, max_bits;
3926 struct descriptor_table dt;
3927
3928 vcpu_load(vcpu);
3929
3930 dt.limit = sregs->idt.limit;
3931 dt.base = sregs->idt.base;
3932 kvm_x86_ops->set_idt(vcpu, &dt);
3933 dt.limit = sregs->gdt.limit;
3934 dt.base = sregs->gdt.base;
3935 kvm_x86_ops->set_gdt(vcpu, &dt);
3936
ad312c7c
ZX		 3937 vcpu->arch.cr2 = sregs->cr2;
3938 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3939 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3940
2d3ad1f4 3941 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3942
ad312c7c 3943 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3944 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3945 kvm_set_apic_base(vcpu, sregs->apic_base);
3946
3947 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3948
ad312c7c 3949 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3950 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3951 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3952
ad312c7c 3953 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3954 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3955 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3956 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3957
3958 if (mmu_reset_needed)
3959 kvm_mmu_reset_context(vcpu);
3960
3961 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3962 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3963 sizeof vcpu->arch.irq_pending);
3964 vcpu->arch.irq_summary = 0;
3965 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3966 if (vcpu->arch.irq_pending[i])
3967 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3968 } else {
3969 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3970 pending_vec = find_first_bit(
3971 (const unsigned long *)sregs->interrupt_bitmap,
3972 max_bits);
3973 /* Only pending external irq is handled here */
3974 if (pending_vec < max_bits) {
3975 kvm_x86_ops->set_irq(vcpu, pending_vec);
3976 pr_debug("Set back pending irq %d\n",
3977 pending_vec);
3978 }
e4825800 3979 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 3980 }
3981
3e6e0aab
GT		 3982 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3983 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3984 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3985 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3986 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3987 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3988
3e6e0aab
GT		 3989 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3990 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 3991
9c3e4aab
MT		 3992 /* Older userspace won't unhalt the vcpu on reset. */
3993 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
3994 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3995 !(vcpu->arch.cr0 & X86_CR0_PE))
3996 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3997
b6c7a5dc
HB		 3998 vcpu_put(vcpu);
3999
4000 return 0;
4001}
4002
d0bfb940
JK		 4003int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4004 struct kvm_guest_debug *dbg)
b6c7a5dc 4005{
ae675ef0 4006 int i, r;
b6c7a5dc
HB		 4007
4008 vcpu_load(vcpu);
4009
ae675ef0
JK		 4010 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4011 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4012 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4013 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4014 vcpu->arch.switch_db_regs =
4015 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4016 } else {
4017 for (i = 0; i < KVM_NR_DB_REGS; i++)
4018 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4019 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4020 }
4021
b6c7a5dc
HB		 4022 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4023
d0bfb940
JK		 4024 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4025 kvm_queue_exception(vcpu, DB_VECTOR);
4026 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4027 kvm_queue_exception(vcpu, BP_VECTOR);
4028
b6c7a5dc
HB		 4029 vcpu_put(vcpu);
4030
4031 return r;
4032}
4033
d0752060
HB		 4034/*
4035 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4036 * we have asm/x86/processor.h
4037 */
4038struct fxsave {
4039 u16 cwd;
4040 u16 swd;
4041 u16 twd;
4042 u16 fop;
4043 u64 rip;
4044 u64 rdp;
4045 u32 mxcsr;
4046 u32 mxcsr_mask;
4047 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4048#ifdef CONFIG_X86_64
4049 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4050#else
4051 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4052#endif
4053};
4054
8b006791
ZX		 4055/*
4056 * Translate a guest virtual address to a guest physical address.
4057 */
4058int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4059 struct kvm_translation *tr)
4060{
4061 unsigned long vaddr = tr->linear_address;
4062 gpa_t gpa;
4063
4064 vcpu_load(vcpu);
72dc67a6 4065 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4066 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4067 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4068 tr->physical_address = gpa;
4069 tr->valid = gpa != UNMAPPED_GVA;
4070 tr->writeable = 1;
4071 tr->usermode = 0;
8b006791
ZX		 4072 vcpu_put(vcpu);
4073
4074 return 0;
4075}
4076
d0752060
HB		 4077int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4078{
ad312c7c 4079 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4080
4081 vcpu_load(vcpu);
4082
4083 memcpy(fpu->fpr, fxsave->st_space, 128);
4084 fpu->fcw = fxsave->cwd;
4085 fpu->fsw = fxsave->swd;
4086 fpu->ftwx = fxsave->twd;
4087 fpu->last_opcode = fxsave->fop;
4088 fpu->last_ip = fxsave->rip;
4089 fpu->last_dp = fxsave->rdp;
4090 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4091
4092 vcpu_put(vcpu);
4093
4094 return 0;
4095}
4096
4097int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4098{
ad312c7c 4099 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4100
4101 vcpu_load(vcpu);
4102
4103 memcpy(fxsave->st_space, fpu->fpr, 128);
4104 fxsave->cwd = fpu->fcw;
4105 fxsave->swd = fpu->fsw;
4106 fxsave->twd = fpu->ftwx;
4107 fxsave->fop = fpu->last_opcode;
4108 fxsave->rip = fpu->last_ip;
4109 fxsave->rdp = fpu->last_dp;
4110 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4111
4112 vcpu_put(vcpu);
4113
4114 return 0;
4115}
4116
4117void fx_init(struct kvm_vcpu *vcpu)
4118{
4119 unsigned after_mxcsr_mask;
4120
bc1a34f1
AA		 4121 /*
4122 * Touch the fpu the first time in non atomic context as if
4123 * this is the first fpu instruction the exception handler
4124 * will fire before the instruction returns and it'll have to
4125 * allocate ram with GFP_KERNEL.
4126 */
4127 if (!used_math())
d6e88aec 4128 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4129
d0752060
HB		 4130 /* Initialize guest FPU by resetting ours and saving into guest's */
4131 preempt_disable();
d6e88aec
AK		 4132 kvm_fx_save(&vcpu->arch.host_fx_image);
4133 kvm_fx_finit();
4134 kvm_fx_save(&vcpu->arch.guest_fx_image);
4135 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4136 preempt_enable();
4137
ad312c7c 4138 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4139 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4140 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4141 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4142 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4143}
4144EXPORT_SYMBOL_GPL(fx_init);
4145
4146void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4147{
4148 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4149 return;
4150
4151 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4152 kvm_fx_save(&vcpu->arch.host_fx_image);
4153 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4154}
4155EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4156
4157void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4158{
4159 if (!vcpu->guest_fpu_loaded)
4160 return;
4161
4162 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4163 kvm_fx_save(&vcpu->arch.guest_fx_image);
4164 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4165 ++vcpu->stat.fpu_reload;
d0752060
HB		 4166}
4167EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4168
4169void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4170{
7f1ea208
JR		 4171 if (vcpu->arch.time_page) {
4172 kvm_release_page_dirty(vcpu->arch.time_page);
4173 vcpu->arch.time_page = NULL;
4174 }
4175
e9b11c17
ZX		 4176 kvm_x86_ops->vcpu_free(vcpu);
4177}
4178
4179struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4180 unsigned int id)
4181{
26e5215f
AK		 4182 return kvm_x86_ops->vcpu_create(kvm, id);
4183}
e9b11c17 4184
26e5215f
AK		 4185int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4186{
4187 int r;
e9b11c17
ZX		 4188
4189 /* We do fxsave: this must be aligned. */
ad312c7c 4190 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4191
0bed3b56 4192 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4193 vcpu_load(vcpu);
4194 r = kvm_arch_vcpu_reset(vcpu);
4195 if (r == 0)
4196 r = kvm_mmu_setup(vcpu);
4197 vcpu_put(vcpu);
4198 if (r < 0)
4199 goto free_vcpu;
4200
26e5215f 4201 return 0;
e9b11c17
ZX		 4202free_vcpu:
4203 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4204 return r;
e9b11c17
ZX		 4205}
4206
d40ccc62 4207void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4208{
4209 vcpu_load(vcpu);
4210 kvm_mmu_unload(vcpu);
4211 vcpu_put(vcpu);
4212
4213 kvm_x86_ops->vcpu_free(vcpu);
4214}
4215
4216int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4217{
448fa4a9
JK		 4218 vcpu->arch.nmi_pending = false;
4219 vcpu->arch.nmi_injected = false;
4220
42dbaa5a
JK		 4221 vcpu->arch.switch_db_regs = 0;
4222 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4223 vcpu->arch.dr6 = DR6_FIXED_1;
4224 vcpu->arch.dr7 = DR7_FIXED_1;
4225
e9b11c17
ZX		 4226 return kvm_x86_ops->vcpu_reset(vcpu);
4227}
4228
4229void kvm_arch_hardware_enable(void *garbage)
4230{
4231 kvm_x86_ops->hardware_enable(garbage);
4232}
4233
4234void kvm_arch_hardware_disable(void *garbage)
4235{
4236 kvm_x86_ops->hardware_disable(garbage);
4237}
4238
4239int kvm_arch_hardware_setup(void)
4240{
4241 return kvm_x86_ops->hardware_setup();
4242}
4243
4244void kvm_arch_hardware_unsetup(void)
4245{
4246 kvm_x86_ops->hardware_unsetup();
4247}
4248
4249void kvm_arch_check_processor_compat(void *rtn)
4250{
4251 kvm_x86_ops->check_processor_compatibility(rtn);
4252}
4253
4254int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4255{
4256 struct page *page;
4257 struct kvm *kvm;
4258 int r;
4259
4260 BUG_ON(vcpu->kvm == NULL);
4261 kvm = vcpu->kvm;
4262
ad312c7c 4263 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4264 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4265 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4266 else
a4535290 4267 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4268
4269 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4270 if (!page) {
4271 r = -ENOMEM;
4272 goto fail;
4273 }
ad312c7c 4274 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4275
4276 r = kvm_mmu_create(vcpu);
4277 if (r < 0)
4278 goto fail_free_pio_data;
4279
4280 if (irqchip_in_kernel(kvm)) {
4281 r = kvm_create_lapic(vcpu);
4282 if (r < 0)
4283 goto fail_mmu_destroy;
4284 }
4285
4286 return 0;
4287
4288fail_mmu_destroy:
4289 kvm_mmu_destroy(vcpu);
4290fail_free_pio_data:
ad312c7c 4291 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4292fail:
4293 return r;
4294}
4295
4296void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4297{
4298 kvm_free_lapic(vcpu);
3200f405 4299 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4300 kvm_mmu_destroy(vcpu);
3200f405 4301 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4302 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4303}
d19a9cd2
ZX		 4304
4305struct kvm *kvm_arch_create_vm(void)
4306{
4307 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4308
4309 if (!kvm)
4310 return ERR_PTR(-ENOMEM);
4311
f05e70ac 4312 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6cffe8ca 4313 INIT_LIST_HEAD(&kvm->arch.oos_global_pages);
4d5c5d0f 4314 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4315
5550af4d
SY		 4316 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4317 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4318
53f658b3
MT		 4319 rdtscll(kvm->arch.vm_init_tsc);
4320
d19a9cd2
ZX		 4321 return kvm;
4322}
4323
4324static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4325{
4326 vcpu_load(vcpu);
4327 kvm_mmu_unload(vcpu);
4328 vcpu_put(vcpu);
4329}
4330
4331static void kvm_free_vcpus(struct kvm *kvm)
4332{
4333 unsigned int i;
4334
4335 /*
4336 * Unpin any mmu pages first.
4337 */
4338 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4339 if (kvm->vcpus[i])
4340 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4341 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4342 if (kvm->vcpus[i]) {
4343 kvm_arch_vcpu_free(kvm->vcpus[i]);
4344 kvm->vcpus[i] = NULL;
4345 }
4346 }
4347
4348}
4349
ad8ba2cd
SY		 4350void kvm_arch_sync_events(struct kvm *kvm)
4351{
ba4cef31 4352 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4353}
4354
d19a9cd2
ZX		 4355void kvm_arch_destroy_vm(struct kvm *kvm)
4356{
6eb55818 4357 kvm_iommu_unmap_guest(kvm);
7837699f 4358 kvm_free_pit(kvm);
d7deeeb0
ZX		 4359 kfree(kvm->arch.vpic);
4360 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4361 kvm_free_vcpus(kvm);
4362 kvm_free_physmem(kvm);
3d45830c
AK		 4363 if (kvm->arch.apic_access_page)
4364 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4365 if (kvm->arch.ept_identity_pagetable)
4366 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4367 kfree(kvm);
4368}
0de10343
ZX		 4369
4370int kvm_arch_set_memory_region(struct kvm *kvm,
4371 struct kvm_userspace_memory_region *mem,
4372 struct kvm_memory_slot old,
4373 int user_alloc)
4374{
4375 int npages = mem->memory_size >> PAGE_SHIFT;
4376 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4377
4378 /*To keep backward compatibility with older userspace,
4379 *x86 needs to hanlde !user_alloc case.
4380 */
4381 if (!user_alloc) {
4382 if (npages && !old.rmap) {
604b38ac
AA		 4383 unsigned long userspace_addr;
4384
72dc67a6 4385 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4386 userspace_addr = do_mmap(NULL, 0,
4387 npages * PAGE_SIZE,
4388 PROT_READ | PROT_WRITE,
acee3c04 4389 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4390 0);
72dc67a6 4391 up_write(&current->mm->mmap_sem);
0de10343 4392
604b38ac
AA		 4393 if (IS_ERR((void *)userspace_addr))
4394 return PTR_ERR((void *)userspace_addr);
4395
4396 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4397 spin_lock(&kvm->mmu_lock);
4398 memslot->userspace_addr = userspace_addr;
4399 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4400 } else {
4401 if (!old.user_alloc && old.rmap) {
4402 int ret;
4403
72dc67a6 4404 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4405 ret = do_munmap(current->mm, old.userspace_addr,
4406 old.npages * PAGE_SIZE);
72dc67a6 4407 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4408 if (ret < 0)
4409 printk(KERN_WARNING
4410 "kvm_vm_ioctl_set_memory_region: "
4411 "failed to munmap memory\n");
4412 }
4413 }
4414 }
4415
f05e70ac 4416 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4417 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4418 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4419 }
4420
4421 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4422 kvm_flush_remote_tlbs(kvm);
4423
4424 return 0;
4425}
1d737c8a 4426
34d4cb8f
MT		 4427void kvm_arch_flush_shadow(struct kvm *kvm)
4428{
4429 kvm_mmu_zap_all(kvm);
4430}
4431
1d737c8a
ZX		 4432int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4433{
a4535290 4434 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4435 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4436 || vcpu->arch.nmi_pending;
1d737c8a 4437}
5736199a
ZX		 4438
4439static void vcpu_kick_intr(void *info)
4440{
4441#ifdef DEBUG
4442 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4443 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4444#endif
4445}
4446
4447void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4448{
4449 int ipi_pcpu = vcpu->cpu;
e9571ed5 4450 int cpu = get_cpu();
5736199a
ZX		 4451
4452 if (waitqueue_active(&vcpu->wq)) {
4453 wake_up_interruptible(&vcpu->wq);
4454 ++vcpu->stat.halt_wakeup;
4455 }
e9571ed5
MT		 4456 /*
4457 * We may be called synchronously with irqs disabled in guest mode,
4458 * So need not to call smp_call_function_single() in that case.
4459 */
4460 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4461 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4462 put_cpu();
5736199a 4463}
Linux 6.x block layer and io_uring tree(s)