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KVM: x86: add KVM_CAP_X2APIC_API
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 73u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
74EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 75
0f65dd70
AK		 76#define emul_to_vcpu(ctxt) \
77 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
78
50a37eb4
JR		 79/* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83#ifdef CONFIG_X86_64
1260edbe
LJ		 84static
85u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 86#else
1260edbe 87static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 88#endif
313a3dc7 89
ba1389b7
AK		 90#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
91#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 92
37131313
RK		 93#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS)
94
cb142eb7 95static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 96static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 97static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 98static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 99
893590c7 100struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 101EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 102
893590c7 103static bool __read_mostly ignore_msrs = 0;
476bc001 104module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 105
9ed96e87
MT		 106unsigned int min_timer_period_us = 500;
107module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
108
630994b3
MT		 109static bool __read_mostly kvmclock_periodic_sync = true;
110module_param(kvmclock_periodic_sync, bool, S_IRUGO);
111
893590c7 112bool __read_mostly kvm_has_tsc_control;
92a1f12d 113EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 114u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 115EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 116u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
117EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
118u64 __read_mostly kvm_max_tsc_scaling_ratio;
119EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 120u64 __read_mostly kvm_default_tsc_scaling_ratio;
121EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 122
cc578287 123/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 124static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 125module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
126
d0659d94 127/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 128unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 129module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
130
52004014
FW		 131static bool __read_mostly vector_hashing = true;
132module_param(vector_hashing, bool, S_IRUGO);
133
893590c7 134static bool __read_mostly backwards_tsc_observed = false;
16a96021 135
18863bdd
AK		 136#define KVM_NR_SHARED_MSRS 16
137
138struct kvm_shared_msrs_global {
139 int nr;
2bf78fa7 140 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 141};
142
143struct kvm_shared_msrs {
144 struct user_return_notifier urn;
145 bool registered;
2bf78fa7
SY		 146 struct kvm_shared_msr_values {
147 u64 host;
148 u64 curr;
149 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 150};
151
152static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 153static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 154
417bc304 155struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 156 { "pf_fixed", VCPU_STAT(pf_fixed) },
157 { "pf_guest", VCPU_STAT(pf_guest) },
158 { "tlb_flush", VCPU_STAT(tlb_flush) },
159 { "invlpg", VCPU_STAT(invlpg) },
160 { "exits", VCPU_STAT(exits) },
161 { "io_exits", VCPU_STAT(io_exits) },
162 { "mmio_exits", VCPU_STAT(mmio_exits) },
163 { "signal_exits", VCPU_STAT(signal_exits) },
164 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 165 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 166 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 167 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 168 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 169 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 170 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 171 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 172 { "request_irq", VCPU_STAT(request_irq_exits) },
173 { "irq_exits", VCPU_STAT(irq_exits) },
174 { "host_state_reload", VCPU_STAT(host_state_reload) },
175 { "efer_reload", VCPU_STAT(efer_reload) },
176 { "fpu_reload", VCPU_STAT(fpu_reload) },
177 { "insn_emulation", VCPU_STAT(insn_emulation) },
178 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 179 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 180 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 181 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
182 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
183 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
184 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
185 { "mmu_flooded", VM_STAT(mmu_flooded) },
186 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 187 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 188 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 189 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 190 { "largepages", VM_STAT(lpages) },
417bc304
HB		 191 { NULL }
192};
193
2acf923e
DC		 194u64 __read_mostly host_xcr0;
195
b6785def 196static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 197
af585b92
GN		 198static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
199{
200 int i;
201 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
202 vcpu->arch.apf.gfns[i] = ~0;
203}
204
18863bdd
AK		 205static void kvm_on_user_return(struct user_return_notifier *urn)
206{
207 unsigned slot;
18863bdd
AK		 208 struct kvm_shared_msrs *locals
209 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 210 struct kvm_shared_msr_values *values;
18863bdd
AK		 211
212 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 213 values = &locals->values[slot];
214 if (values->host != values->curr) {
215 wrmsrl(shared_msrs_global.msrs[slot], values->host);
216 values->curr = values->host;
18863bdd
AK		 217 }
218 }
219 locals->registered = false;
220 user_return_notifier_unregister(urn);
221}
222
2bf78fa7 223static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 224{
18863bdd 225 u64 value;
013f6a5d
MT		 226 unsigned int cpu = smp_processor_id();
227 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 228
2bf78fa7
SY		 229 /* only read, and nobody should modify it at this time,
230 * so don't need lock */
231 if (slot >= shared_msrs_global.nr) {
232 printk(KERN_ERR "kvm: invalid MSR slot!");
233 return;
234 }
235 rdmsrl_safe(msr, &value);
236 smsr->values[slot].host = value;
237 smsr->values[slot].curr = value;
238}
239
240void kvm_define_shared_msr(unsigned slot, u32 msr)
241{
0123be42 242 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 243 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 244 if (slot >= shared_msrs_global.nr)
245 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 246}
247EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
248
249static void kvm_shared_msr_cpu_online(void)
250{
251 unsigned i;
18863bdd
AK		 252
253 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 254 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 255}
256
8b3c3104 257int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 258{
013f6a5d
MT		 259 unsigned int cpu = smp_processor_id();
260 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 261 int err;
18863bdd 262
2bf78fa7 263 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 264 return 0;
2bf78fa7 265 smsr->values[slot].curr = value;
8b3c3104
AH		 266 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
267 if (err)
268 return 1;
269
18863bdd
AK		 270 if (!smsr->registered) {
271 smsr->urn.on_user_return = kvm_on_user_return;
272 user_return_notifier_register(&smsr->urn);
273 smsr->registered = true;
274 }
8b3c3104 275 return 0;
18863bdd
AK		 276}
277EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
278
13a34e06 279static void drop_user_return_notifiers(void)
3548bab5 280{
013f6a5d
MT		 281 unsigned int cpu = smp_processor_id();
282 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 283
284 if (smsr->registered)
285 kvm_on_user_return(&smsr->urn);
286}
287
6866b83e
CO		 288u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
289{
8a5a87d9 290 return vcpu->arch.apic_base;
6866b83e
CO		 291}
292EXPORT_SYMBOL_GPL(kvm_get_apic_base);
293
58cb628d
JK		 294int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
295{
296 u64 old_state = vcpu->arch.apic_base &
297 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
298 u64 new_state = msr_info->data &
299 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
300 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
301 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
302
303 if (!msr_info->host_initiated &&
304 ((msr_info->data & reserved_bits) != 0 ||
305 new_state == X2APIC_ENABLE ||
306 (new_state == MSR_IA32_APICBASE_ENABLE &&
307 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
308 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
309 old_state == 0)))
310 return 1;
311
312 kvm_lapic_set_base(vcpu, msr_info->data);
313 return 0;
6866b83e
CO		 314}
315EXPORT_SYMBOL_GPL(kvm_set_apic_base);
316
2605fc21 317asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 318{
319 /* Fault while not rebooting. We want the trace. */
320 BUG();
321}
322EXPORT_SYMBOL_GPL(kvm_spurious_fault);
323
3fd28fce
ED		 324#define EXCPT_BENIGN 0
325#define EXCPT_CONTRIBUTORY 1
326#define EXCPT_PF 2
327
328static int exception_class(int vector)
329{
330 switch (vector) {
331 case PF_VECTOR:
332 return EXCPT_PF;
333 case DE_VECTOR:
334 case TS_VECTOR:
335 case NP_VECTOR:
336 case SS_VECTOR:
337 case GP_VECTOR:
338 return EXCPT_CONTRIBUTORY;
339 default:
340 break;
341 }
342 return EXCPT_BENIGN;
343}
344
d6e8c854
NA		 345#define EXCPT_FAULT 0
346#define EXCPT_TRAP 1
347#define EXCPT_ABORT 2
348#define EXCPT_INTERRUPT 3
349
350static int exception_type(int vector)
351{
352 unsigned int mask;
353
354 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
355 return EXCPT_INTERRUPT;
356
357 mask = 1 << vector;
358
359 /* #DB is trap, as instruction watchpoints are handled elsewhere */
360 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
361 return EXCPT_TRAP;
362
363 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
364 return EXCPT_ABORT;
365
366 /* Reserved exceptions will result in fault */
367 return EXCPT_FAULT;
368}
369
3fd28fce 370static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 371 unsigned nr, bool has_error, u32 error_code,
372 bool reinject)
3fd28fce
ED		 373{
374 u32 prev_nr;
375 int class1, class2;
376
3842d135
AK		 377 kvm_make_request(KVM_REQ_EVENT, vcpu);
378
3fd28fce
ED		 379 if (!vcpu->arch.exception.pending) {
380 queue:
3ffb2468
NA		 381 if (has_error && !is_protmode(vcpu))
382 has_error = false;
3fd28fce
ED		 383 vcpu->arch.exception.pending = true;
384 vcpu->arch.exception.has_error_code = has_error;
385 vcpu->arch.exception.nr = nr;
386 vcpu->arch.exception.error_code = error_code;
3f0fd292 387 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 388 return;
389 }
390
391 /* to check exception */
392 prev_nr = vcpu->arch.exception.nr;
393 if (prev_nr == DF_VECTOR) {
394 /* triple fault -> shutdown */
a8eeb04a 395 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 396 return;
397 }
398 class1 = exception_class(prev_nr);
399 class2 = exception_class(nr);
400 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
401 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
402 /* generate double fault per SDM Table 5-5 */
403 vcpu->arch.exception.pending = true;
404 vcpu->arch.exception.has_error_code = true;
405 vcpu->arch.exception.nr = DF_VECTOR;
406 vcpu->arch.exception.error_code = 0;
407 } else
408 /* replace previous exception with a new one in a hope
409 that instruction re-execution will regenerate lost
410 exception */
411 goto queue;
412}
413
298101da
AK		 414void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
415{
ce7ddec4 416 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 417}
418EXPORT_SYMBOL_GPL(kvm_queue_exception);
419
ce7ddec4
JR		 420void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
421{
422 kvm_multiple_exception(vcpu, nr, false, 0, true);
423}
424EXPORT_SYMBOL_GPL(kvm_requeue_exception);
425
db8fcefa 426void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 427{
db8fcefa
AP		 428 if (err)
429 kvm_inject_gp(vcpu, 0);
430 else
431 kvm_x86_ops->skip_emulated_instruction(vcpu);
432}
433EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 434
6389ee94 435void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 436{
437 ++vcpu->stat.pf_guest;
6389ee94
AK		 438 vcpu->arch.cr2 = fault->address;
439 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 440}
27d6c865 441EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 442
ef54bcfe 443static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 444{
6389ee94
AK		 445 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
446 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 447 else
6389ee94 448 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 449
450 return fault->nested_page_fault;
d4f8cf66
JR		 451}
452
3419ffc8
SY		 453void kvm_inject_nmi(struct kvm_vcpu *vcpu)
454{
7460fb4a
AK		 455 atomic_inc(&vcpu->arch.nmi_queued);
456 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 457}
458EXPORT_SYMBOL_GPL(kvm_inject_nmi);
459
298101da
AK		 460void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
461{
ce7ddec4 462 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 463}
464EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
465
ce7ddec4
JR		 466void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
467{
468 kvm_multiple_exception(vcpu, nr, true, error_code, true);
469}
470EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
471
0a79b009
AK		 472/*
473 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
474 * a #GP and return false.
475 */
476bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 477{
0a79b009
AK		 478 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
479 return true;
480 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
481 return false;
298101da 482}
0a79b009 483EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 484
16f8a6f9
NA		 485bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
486{
487 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
488 return true;
489
490 kvm_queue_exception(vcpu, UD_VECTOR);
491 return false;
492}
493EXPORT_SYMBOL_GPL(kvm_require_dr);
494
ec92fe44
JR		 495/*
496 * This function will be used to read from the physical memory of the currently
54bf36aa 497 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 498 * can read from guest physical or from the guest's guest physical memory.
499 */
500int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
501 gfn_t ngfn, void *data, int offset, int len,
502 u32 access)
503{
54987b7a 504 struct x86_exception exception;
ec92fe44
JR		 505 gfn_t real_gfn;
506 gpa_t ngpa;
507
508 ngpa = gfn_to_gpa(ngfn);
54987b7a 509 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 510 if (real_gfn == UNMAPPED_GVA)
511 return -EFAULT;
512
513 real_gfn = gpa_to_gfn(real_gfn);
514
54bf36aa 515 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 516}
517EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
518
69b0049a 519static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 520 void *data, int offset, int len, u32 access)
521{
522 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
523 data, offset, len, access);
524}
525
a03490ed
CO		 526/*
527 * Load the pae pdptrs. Return true is they are all valid.
528 */
ff03a073 529int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 530{
531 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
532 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
533 int i;
534 int ret;
ff03a073 535 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 536
ff03a073
JR		 537 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
538 offset * sizeof(u64), sizeof(pdpte),
539 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 540 if (ret < 0) {
541 ret = 0;
542 goto out;
543 }
544 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 545 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 546 (pdpte[i] &
547 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 548 ret = 0;
549 goto out;
550 }
551 }
552 ret = 1;
553
ff03a073 554 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 555 __set_bit(VCPU_EXREG_PDPTR,
556 (unsigned long *)&vcpu->arch.regs_avail);
557 __set_bit(VCPU_EXREG_PDPTR,
558 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 559out:
a03490ed
CO		 560
561 return ret;
562}
cc4b6871 563EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 564
d835dfec
AK		 565static bool pdptrs_changed(struct kvm_vcpu *vcpu)
566{
ff03a073 567 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 568 bool changed = true;
3d06b8bf
JR		 569 int offset;
570 gfn_t gfn;
d835dfec
AK		 571 int r;
572
573 if (is_long_mode(vcpu) || !is_pae(vcpu))
574 return false;
575
6de4f3ad
AK		 576 if (!test_bit(VCPU_EXREG_PDPTR,
577 (unsigned long *)&vcpu->arch.regs_avail))
578 return true;
579
9f8fe504
AK		 580 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
581 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 582 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
583 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 584 if (r < 0)
585 goto out;
ff03a073 586 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 587out:
d835dfec
AK		 588
589 return changed;
590}
591
49a9b07e 592int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 593{
aad82703 594 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 595 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 596
f9a48e6a
AK		 597 cr0 |= X86_CR0_ET;
598
ab344828 599#ifdef CONFIG_X86_64
0f12244f
GN		 600 if (cr0 & 0xffffffff00000000UL)
601 return 1;
ab344828
GN		 602#endif
603
604 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 605
0f12244f
GN		 606 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
607 return 1;
a03490ed 608
0f12244f
GN		 609 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
610 return 1;
a03490ed
CO		 611
612 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
613#ifdef CONFIG_X86_64
f6801dff 614 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 615 int cs_db, cs_l;
616
0f12244f
GN		 617 if (!is_pae(vcpu))
618 return 1;
a03490ed 619 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 620 if (cs_l)
621 return 1;
a03490ed
CO		 622 } else
623#endif
ff03a073 624 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 625 kvm_read_cr3(vcpu)))
0f12244f 626 return 1;
a03490ed
CO		 627 }
628
ad756a16
MJ		 629 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
630 return 1;
631
a03490ed 632 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 633
d170c419 634 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 635 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 636 kvm_async_pf_hash_reset(vcpu);
637 }
e5f3f027 638
aad82703
SY		 639 if ((cr0 ^ old_cr0) & update_bits)
640 kvm_mmu_reset_context(vcpu);
b18d5431 641
879ae188
LE		 642 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
643 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
644 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 645 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
646
0f12244f
GN		 647 return 0;
648}
2d3ad1f4 649EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 650
2d3ad1f4 651void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 652{
49a9b07e 653 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 654}
2d3ad1f4 655EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 656
42bdf991
MT		 657static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
658{
659 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
660 !vcpu->guest_xcr0_loaded) {
661 /* kvm_set_xcr() also depends on this */
662 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
663 vcpu->guest_xcr0_loaded = 1;
664 }
665}
666
667static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
668{
669 if (vcpu->guest_xcr0_loaded) {
670 if (vcpu->arch.xcr0 != host_xcr0)
671 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
672 vcpu->guest_xcr0_loaded = 0;
673 }
674}
675
69b0049a 676static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 677{
56c103ec
LJ		 678 u64 xcr0 = xcr;
679 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 680 u64 valid_bits;
2acf923e
DC		 681
682 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
683 if (index != XCR_XFEATURE_ENABLED_MASK)
684 return 1;
d91cab78 685 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 686 return 1;
d91cab78 687 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 688 return 1;
46c34cb0
PB		 689
690 /*
691 * Do not allow the guest to set bits that we do not support
692 * saving. However, xcr0 bit 0 is always set, even if the
693 * emulated CPU does not support XSAVE (see fx_init).
694 */
d91cab78 695 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 696 if (xcr0 & ~valid_bits)
2acf923e 697 return 1;
46c34cb0 698
d91cab78
DH		 699 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
700 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 701 return 1;
702
d91cab78
DH		 703 if (xcr0 & XFEATURE_MASK_AVX512) {
704 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 705 return 1;
d91cab78 706 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 707 return 1;
708 }
2acf923e 709 vcpu->arch.xcr0 = xcr0;
56c103ec 710
d91cab78 711 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 712 kvm_update_cpuid(vcpu);
2acf923e
DC		 713 return 0;
714}
715
716int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
717{
764bcbc5
Z		 718 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
719 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 720 kvm_inject_gp(vcpu, 0);
721 return 1;
722 }
723 return 0;
724}
725EXPORT_SYMBOL_GPL(kvm_set_xcr);
726
a83b29c6 727int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 728{
fc78f519 729 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 730 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 731 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 732
0f12244f
GN		 733 if (cr4 & CR4_RESERVED_BITS)
734 return 1;
a03490ed 735
2acf923e
DC		 736 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
737 return 1;
738
c68b734f
YW		 739 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
740 return 1;
741
97ec8c06
FW		 742 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
743 return 1;
744
afcbf13f 745 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 746 return 1;
747
b9baba86
HH		 748 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
749 return 1;
750
a03490ed 751 if (is_long_mode(vcpu)) {
0f12244f
GN		 752 if (!(cr4 & X86_CR4_PAE))
753 return 1;
a2edf57f
AK		 754 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
755 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 756 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
757 kvm_read_cr3(vcpu)))
0f12244f
GN		 758 return 1;
759
ad756a16
MJ		 760 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
761 if (!guest_cpuid_has_pcid(vcpu))
762 return 1;
763
764 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
765 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
766 return 1;
767 }
768
5e1746d6 769 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 770 return 1;
a03490ed 771
ad756a16
MJ		 772 if (((cr4 ^ old_cr4) & pdptr_bits) ||
773 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 774 kvm_mmu_reset_context(vcpu);
0f12244f 775
b9baba86 776 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 777 kvm_update_cpuid(vcpu);
2acf923e 778
0f12244f
GN		 779 return 0;
780}
2d3ad1f4 781EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 782
2390218b 783int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 784{
ac146235 785#ifdef CONFIG_X86_64
9d88fca7 786 cr3 &= ~CR3_PCID_INVD;
ac146235 787#endif
9d88fca7 788
9f8fe504 789 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 790 kvm_mmu_sync_roots(vcpu);
77c3913b 791 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 792 return 0;
d835dfec
AK		 793 }
794
a03490ed 795 if (is_long_mode(vcpu)) {
d9f89b88
JK		 796 if (cr3 & CR3_L_MODE_RESERVED_BITS)
797 return 1;
798 } else if (is_pae(vcpu) && is_paging(vcpu) &&
799 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 800 return 1;
a03490ed 801
0f12244f 802 vcpu->arch.cr3 = cr3;
aff48baa 803 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 804 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 805 return 0;
806}
2d3ad1f4 807EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 808
eea1cff9 809int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 810{
0f12244f
GN		 811 if (cr8 & CR8_RESERVED_BITS)
812 return 1;
35754c98 813 if (lapic_in_kernel(vcpu))
a03490ed
CO		 814 kvm_lapic_set_tpr(vcpu, cr8);
815 else
ad312c7c 816 vcpu->arch.cr8 = cr8;
0f12244f
GN		 817 return 0;
818}
2d3ad1f4 819EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 820
2d3ad1f4 821unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 822{
35754c98 823 if (lapic_in_kernel(vcpu))
a03490ed
CO		 824 return kvm_lapic_get_cr8(vcpu);
825 else
ad312c7c 826 return vcpu->arch.cr8;
a03490ed 827}
2d3ad1f4 828EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 829
ae561ede
NA		 830static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
831{
832 int i;
833
834 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
835 for (i = 0; i < KVM_NR_DB_REGS; i++)
836 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
837 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
838 }
839}
840
73aaf249
JK		 841static void kvm_update_dr6(struct kvm_vcpu *vcpu)
842{
843 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
844 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
845}
846
c8639010
JK		 847static void kvm_update_dr7(struct kvm_vcpu *vcpu)
848{
849 unsigned long dr7;
850
851 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
852 dr7 = vcpu->arch.guest_debug_dr7;
853 else
854 dr7 = vcpu->arch.dr7;
855 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 856 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
857 if (dr7 & DR7_BP_EN_MASK)
858 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 859}
860
6f43ed01
NA		 861static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
862{
863 u64 fixed = DR6_FIXED_1;
864
865 if (!guest_cpuid_has_rtm(vcpu))
866 fixed |= DR6_RTM;
867 return fixed;
868}
869
338dbc97 870static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 871{
872 switch (dr) {
873 case 0 ... 3:
874 vcpu->arch.db[dr] = val;
875 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
876 vcpu->arch.eff_db[dr] = val;
877 break;
878 case 4:
020df079
GN		 879 /* fall through */
880 case 6:
338dbc97
GN		 881 if (val & 0xffffffff00000000ULL)
882 return -1; /* #GP */
6f43ed01 883 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 884 kvm_update_dr6(vcpu);
020df079
GN		 885 break;
886 case 5:
020df079
GN		 887 /* fall through */
888 default: /* 7 */
338dbc97
GN		 889 if (val & 0xffffffff00000000ULL)
890 return -1; /* #GP */
020df079 891 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 892 kvm_update_dr7(vcpu);
020df079
GN		 893 break;
894 }
895
896 return 0;
897}
338dbc97
GN		 898
899int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
900{
16f8a6f9 901 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 902 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 903 return 1;
904 }
905 return 0;
338dbc97 906}
020df079
GN		 907EXPORT_SYMBOL_GPL(kvm_set_dr);
908
16f8a6f9 909int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 910{
911 switch (dr) {
912 case 0 ... 3:
913 *val = vcpu->arch.db[dr];
914 break;
915 case 4:
020df079
GN		 916 /* fall through */
917 case 6:
73aaf249
JK		 918 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
919 *val = vcpu->arch.dr6;
920 else
921 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 922 break;
923 case 5:
020df079
GN		 924 /* fall through */
925 default: /* 7 */
926 *val = vcpu->arch.dr7;
927 break;
928 }
338dbc97
GN		 929 return 0;
930}
020df079
GN		 931EXPORT_SYMBOL_GPL(kvm_get_dr);
932
022cd0e8
AK		 933bool kvm_rdpmc(struct kvm_vcpu *vcpu)
934{
935 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
936 u64 data;
937 int err;
938
c6702c9d 939 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 940 if (err)
941 return err;
942 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
943 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
944 return err;
945}
946EXPORT_SYMBOL_GPL(kvm_rdpmc);
947
043405e1
CO		 948/*
949 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
950 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
951 *
952 * This list is modified at module load time to reflect the
e3267cbb 953 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 954 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
955 * may depend on host virtualization features rather than host cpu features.
043405e1 956 */
e3267cbb 957
043405e1
CO		 958static u32 msrs_to_save[] = {
959 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 960 MSR_STAR,
043405e1
CO		 961#ifdef CONFIG_X86_64
962 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
963#endif
b3897a49 964 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 965 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 966};
967
968static unsigned num_msrs_to_save;
969
62ef68bb
PB		 970static u32 emulated_msrs[] = {
971 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
972 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
973 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
974 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 975 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
976 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 977 HV_X64_MSR_RESET,
11c4b1ca 978 HV_X64_MSR_VP_INDEX,
9eec50b8 979 HV_X64_MSR_VP_RUNTIME,
5c919412 980 HV_X64_MSR_SCONTROL,
1f4b34f8 981 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 982 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
983 MSR_KVM_PV_EOI_EN,
984
ba904635 985 MSR_IA32_TSC_ADJUST,
a3e06bbe 986 MSR_IA32_TSCDEADLINE,
043405e1 987 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 988 MSR_IA32_MCG_STATUS,
989 MSR_IA32_MCG_CTL,
c45dcc71 990 MSR_IA32_MCG_EXT_CTL,
64d60670 991 MSR_IA32_SMBASE,
043405e1
CO		 992};
993
62ef68bb
PB		 994static unsigned num_emulated_msrs;
995
384bb783 996bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 997{
b69e8cae 998 if (efer & efer_reserved_bits)
384bb783 999 return false;
15c4a640 1000
1b2fd70c
AG		 1001 if (efer & EFER_FFXSR) {
1002 struct kvm_cpuid_entry2 *feat;
1003
1004 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1005 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1006 return false;
1b2fd70c
AG		 1007 }
1008
d8017474
AG		 1009 if (efer & EFER_SVME) {
1010 struct kvm_cpuid_entry2 *feat;
1011
1012 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1013 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1014 return false;
d8017474
AG		 1015 }
1016
384bb783
JK		 1017 return true;
1018}
1019EXPORT_SYMBOL_GPL(kvm_valid_efer);
1020
1021static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1022{
1023 u64 old_efer = vcpu->arch.efer;
1024
1025 if (!kvm_valid_efer(vcpu, efer))
1026 return 1;
1027
1028 if (is_paging(vcpu)
1029 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1030 return 1;
1031
15c4a640 1032 efer &= ~EFER_LMA;
f6801dff 1033 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1034
a3d204e2
SY		 1035 kvm_x86_ops->set_efer(vcpu, efer);
1036
aad82703
SY		 1037 /* Update reserved bits */
1038 if ((efer ^ old_efer) & EFER_NX)
1039 kvm_mmu_reset_context(vcpu);
1040
b69e8cae 1041 return 0;
15c4a640
CO		 1042}
1043
f2b4b7dd
JR		 1044void kvm_enable_efer_bits(u64 mask)
1045{
1046 efer_reserved_bits &= ~mask;
1047}
1048EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1049
15c4a640
CO		 1050/*
1051 * Writes msr value into into the appropriate "register".
1052 * Returns 0 on success, non-0 otherwise.
1053 * Assumes vcpu_load() was already called.
1054 */
8fe8ab46 1055int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1056{
854e8bb1
NA		 1057 switch (msr->index) {
1058 case MSR_FS_BASE:
1059 case MSR_GS_BASE:
1060 case MSR_KERNEL_GS_BASE:
1061 case MSR_CSTAR:
1062 case MSR_LSTAR:
1063 if (is_noncanonical_address(msr->data))
1064 return 1;
1065 break;
1066 case MSR_IA32_SYSENTER_EIP:
1067 case MSR_IA32_SYSENTER_ESP:
1068 /*
1069 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1070 * non-canonical address is written on Intel but not on
1071 * AMD (which ignores the top 32-bits, because it does
1072 * not implement 64-bit SYSENTER).
1073 *
1074 * 64-bit code should hence be able to write a non-canonical
1075 * value on AMD. Making the address canonical ensures that
1076 * vmentry does not fail on Intel after writing a non-canonical
1077 * value, and that something deterministic happens if the guest
1078 * invokes 64-bit SYSENTER.
1079 */
1080 msr->data = get_canonical(msr->data);
1081 }
8fe8ab46 1082 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1083}
854e8bb1 1084EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1085
313a3dc7
CO		 1086/*
1087 * Adapt set_msr() to msr_io()'s calling convention
1088 */
609e36d3
PB		 1089static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1090{
1091 struct msr_data msr;
1092 int r;
1093
1094 msr.index = index;
1095 msr.host_initiated = true;
1096 r = kvm_get_msr(vcpu, &msr);
1097 if (r)
1098 return r;
1099
1100 *data = msr.data;
1101 return 0;
1102}
1103
313a3dc7
CO		 1104static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1105{
8fe8ab46
WA		 1106 struct msr_data msr;
1107
1108 msr.data = *data;
1109 msr.index = index;
1110 msr.host_initiated = true;
1111 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1112}
1113
16e8d74d
MT		 1114#ifdef CONFIG_X86_64
1115struct pvclock_gtod_data {
1116 seqcount_t seq;
1117
1118 struct { /* extract of a clocksource struct */
1119 int vclock_mode;
1120 cycle_t cycle_last;
1121 cycle_t mask;
1122 u32 mult;
1123 u32 shift;
1124 } clock;
1125
cbcf2dd3
TG		 1126 u64 boot_ns;
1127 u64 nsec_base;
16e8d74d
MT		 1128};
1129
1130static struct pvclock_gtod_data pvclock_gtod_data;
1131
1132static void update_pvclock_gtod(struct timekeeper *tk)
1133{
1134 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1135 u64 boot_ns;
1136
876e7881 1137 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1138
1139 write_seqcount_begin(&vdata->seq);
1140
1141 /* copy pvclock gtod data */
876e7881
PZ		 1142 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1143 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1144 vdata->clock.mask = tk->tkr_mono.mask;
1145 vdata->clock.mult = tk->tkr_mono.mult;
1146 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1147
cbcf2dd3 1148 vdata->boot_ns = boot_ns;
876e7881 1149 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1150
1151 write_seqcount_end(&vdata->seq);
1152}
1153#endif
1154
bab5bb39
NK		 1155void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1156{
1157 /*
1158 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1159 * vcpu_enter_guest. This function is only called from
1160 * the physical CPU that is running vcpu.
1161 */
1162 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1163}
16e8d74d 1164
18068523
GOC		 1165static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1166{
9ed3c444
AK		 1167 int version;
1168 int r;
50d0a0f9 1169 struct pvclock_wall_clock wc;
87aeb54f 1170 struct timespec64 boot;
18068523
GOC		 1171
1172 if (!wall_clock)
1173 return;
1174
9ed3c444
AK		 1175 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1176 if (r)
1177 return;
1178
1179 if (version & 1)
1180 ++version; /* first time write, random junk */
1181
1182 ++version;
18068523 1183
1dab1345
NK		 1184 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1185 return;
18068523 1186
50d0a0f9
GH		 1187 /*
1188 * The guest calculates current wall clock time by adding
34c238a1 1189 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1190 * wall clock specified here. guest system time equals host
1191 * system time for us, thus we must fill in host boot time here.
1192 */
87aeb54f 1193 getboottime64(&boot);
50d0a0f9 1194
4b648665 1195 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1196 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1197 boot = timespec64_sub(boot, ts);
4b648665 1198 }
87aeb54f 1199 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1200 wc.nsec = boot.tv_nsec;
1201 wc.version = version;
18068523
GOC		 1202
1203 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1204
1205 version++;
1206 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1207}
1208
50d0a0f9
GH		 1209static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1210{
b51012de
PB		 1211 do_shl32_div32(dividend, divisor);
1212 return dividend;
50d0a0f9
GH		 1213}
1214
3ae13faa 1215static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1216 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1217{
5f4e3f88 1218 uint64_t scaled64;
50d0a0f9
GH		 1219 int32_t shift = 0;
1220 uint64_t tps64;
1221 uint32_t tps32;
1222
3ae13faa
PB		 1223 tps64 = base_hz;
1224 scaled64 = scaled_hz;
50933623 1225 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1226 tps64 >>= 1;
1227 shift--;
1228 }
1229
1230 tps32 = (uint32_t)tps64;
50933623
JK		 1231 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1232 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1233 scaled64 >>= 1;
1234 else
1235 tps32 <<= 1;
50d0a0f9
GH		 1236 shift++;
1237 }
1238
5f4e3f88
ZA		 1239 *pshift = shift;
1240 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1241
3ae13faa
PB		 1242 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1243 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1244}
1245
d828199e 1246#ifdef CONFIG_X86_64
16e8d74d 1247static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1248#endif
16e8d74d 1249
c8076604 1250static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1251static unsigned long max_tsc_khz;
c8076604 1252
cc578287 1253static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1254{
cc578287
ZA		 1255 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1256 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1257}
1258
cc578287 1259static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1260{
cc578287
ZA		 1261 u64 v = (u64)khz * (1000000 + ppm);
1262 do_div(v, 1000000);
1263 return v;
1e993611
JR		 1264}
1265
381d585c
HZ		 1266static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1267{
1268 u64 ratio;
1269
1270 /* Guest TSC same frequency as host TSC? */
1271 if (!scale) {
1272 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1273 return 0;
1274 }
1275
1276 /* TSC scaling supported? */
1277 if (!kvm_has_tsc_control) {
1278 if (user_tsc_khz > tsc_khz) {
1279 vcpu->arch.tsc_catchup = 1;
1280 vcpu->arch.tsc_always_catchup = 1;
1281 return 0;
1282 } else {
1283 WARN(1, "user requested TSC rate below hardware speed\n");
1284 return -1;
1285 }
1286 }
1287
1288 /* TSC scaling required - calculate ratio */
1289 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1290 user_tsc_khz, tsc_khz);
1291
1292 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1293 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1294 user_tsc_khz);
1295 return -1;
1296 }
1297
1298 vcpu->arch.tsc_scaling_ratio = ratio;
1299 return 0;
1300}
1301
4941b8cb 1302static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1303{
cc578287
ZA		 1304 u32 thresh_lo, thresh_hi;
1305 int use_scaling = 0;
217fc9cf 1306
03ba32ca 1307 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1308 if (user_tsc_khz == 0) {
ad721883
HZ		 1309 /* set tsc_scaling_ratio to a safe value */
1310 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1311 return -1;
ad721883 1312 }
03ba32ca 1313
c285545f 1314 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1315 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1316 &vcpu->arch.virtual_tsc_shift,
1317 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1318 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1319
1320 /*
1321 * Compute the variation in TSC rate which is acceptable
1322 * within the range of tolerance and decide if the
1323 * rate being applied is within that bounds of the hardware
1324 * rate. If so, no scaling or compensation need be done.
1325 */
1326 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1327 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1328 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1329 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1330 use_scaling = 1;
1331 }
4941b8cb 1332 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1333}
1334
1335static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1336{
e26101b1 1337 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1338 vcpu->arch.virtual_tsc_mult,
1339 vcpu->arch.virtual_tsc_shift);
e26101b1 1340 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1341 return tsc;
1342}
1343
69b0049a 1344static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1345{
1346#ifdef CONFIG_X86_64
1347 bool vcpus_matched;
b48aa97e
MT		 1348 struct kvm_arch *ka = &vcpu->kvm->arch;
1349 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1350
1351 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1352 atomic_read(&vcpu->kvm->online_vcpus));
1353
7f187922
MT		 1354 /*
1355 * Once the masterclock is enabled, always perform request in
1356 * order to update it.
1357 *
1358 * In order to enable masterclock, the host clocksource must be TSC
1359 * and the vcpus need to have matched TSCs. When that happens,
1360 * perform request to enable masterclock.
1361 */
1362 if (ka->use_master_clock ||
1363 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1364 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1365
1366 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1367 atomic_read(&vcpu->kvm->online_vcpus),
1368 ka->use_master_clock, gtod->clock.vclock_mode);
1369#endif
1370}
1371
ba904635
WA		 1372static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1373{
1374 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1375 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1376}
1377
35181e86
HZ		 1378/*
1379 * Multiply tsc by a fixed point number represented by ratio.
1380 *
1381 * The most significant 64-N bits (mult) of ratio represent the
1382 * integral part of the fixed point number; the remaining N bits
1383 * (frac) represent the fractional part, ie. ratio represents a fixed
1384 * point number (mult + frac * 2^(-N)).
1385 *
1386 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1387 */
1388static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1389{
1390 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1391}
1392
1393u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1394{
1395 u64 _tsc = tsc;
1396 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1397
1398 if (ratio != kvm_default_tsc_scaling_ratio)
1399 _tsc = __scale_tsc(ratio, tsc);
1400
1401 return _tsc;
1402}
1403EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1404
07c1419a
HZ		 1405static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1406{
1407 u64 tsc;
1408
1409 tsc = kvm_scale_tsc(vcpu, rdtsc());
1410
1411 return target_tsc - tsc;
1412}
1413
4ba76538
HZ		 1414u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1415{
1416 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1417}
1418EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1419
8fe8ab46 1420void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1421{
1422 struct kvm *kvm = vcpu->kvm;
f38e098f 1423 u64 offset, ns, elapsed;
99e3e30a 1424 unsigned long flags;
02626b6a 1425 s64 usdiff;
b48aa97e 1426 bool matched;
0d3da0d2 1427 bool already_matched;
8fe8ab46 1428 u64 data = msr->data;
99e3e30a 1429
038f8c11 1430 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1431 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1432 ns = get_kernel_ns();
f38e098f 1433 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1434
03ba32ca 1435 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1436 int faulted = 0;
1437
03ba32ca
MT		 1438 /* n.b - signed multiplication and division required */
1439 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1440#ifdef CONFIG_X86_64
03ba32ca 1441 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1442#else
03ba32ca 1443 /* do_div() only does unsigned */
8915aa27
MT		 1444 asm("1: idivl %[divisor]\n"
1445 "2: xor %%edx, %%edx\n"
1446 " movl $0, %[faulted]\n"
1447 "3:\n"
1448 ".section .fixup,\"ax\"\n"
1449 "4: movl $1, %[faulted]\n"
1450 " jmp 3b\n"
1451 ".previous\n"
1452
1453 _ASM_EXTABLE(1b, 4b)
1454
1455 : "=A"(usdiff), [faulted] "=r" (faulted)
1456 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1457
5d3cb0f6 1458#endif
03ba32ca
MT		 1459 do_div(elapsed, 1000);
1460 usdiff -= elapsed;
1461 if (usdiff < 0)
1462 usdiff = -usdiff;
8915aa27
MT		 1463
1464 /* idivl overflow => difference is larger than USEC_PER_SEC */
1465 if (faulted)
1466 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1467 } else
1468 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1469
1470 /*
5d3cb0f6
ZA		 1471 * Special case: TSC write with a small delta (1 second) of virtual
1472 * cycle time against real time is interpreted as an attempt to
1473 * synchronize the CPU.
1474 *
1475 * For a reliable TSC, we can match TSC offsets, and for an unstable
1476 * TSC, we add elapsed time in this computation. We could let the
1477 * compensation code attempt to catch up if we fall behind, but
1478 * it's better to try to match offsets from the beginning.
1479 */
02626b6a 1480 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1481 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1482 if (!check_tsc_unstable()) {
e26101b1 1483 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1484 pr_debug("kvm: matched tsc offset for %llu\n", data);
1485 } else {
857e4099 1486 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1487 data += delta;
07c1419a 1488 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1489 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1490 }
b48aa97e 1491 matched = true;
0d3da0d2 1492 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1493 } else {
1494 /*
1495 * We split periods of matched TSC writes into generations.
1496 * For each generation, we track the original measured
1497 * nanosecond time, offset, and write, so if TSCs are in
1498 * sync, we can match exact offset, and if not, we can match
4a969980 1499 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1500 *
1501 * These values are tracked in kvm->arch.cur_xxx variables.
1502 */
1503 kvm->arch.cur_tsc_generation++;
1504 kvm->arch.cur_tsc_nsec = ns;
1505 kvm->arch.cur_tsc_write = data;
1506 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1507 matched = false;
0d3da0d2 1508 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1509 kvm->arch.cur_tsc_generation, data);
f38e098f 1510 }
e26101b1
ZA		 1511
1512 /*
1513 * We also track th most recent recorded KHZ, write and time to
1514 * allow the matching interval to be extended at each write.
1515 */
f38e098f
ZA		 1516 kvm->arch.last_tsc_nsec = ns;
1517 kvm->arch.last_tsc_write = data;
5d3cb0f6 1518 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1519
b183aa58 1520 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1521
1522 /* Keep track of which generation this VCPU has synchronized to */
1523 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1524 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1525 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1526
ba904635
WA		 1527 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1528 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1529 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1530 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1531
1532 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1533 if (!matched) {
b48aa97e 1534 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1535 } else if (!already_matched) {
1536 kvm->arch.nr_vcpus_matched_tsc++;
1537 }
b48aa97e
MT		 1538
1539 kvm_track_tsc_matching(vcpu);
1540 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1541}
e26101b1 1542
99e3e30a
ZA		 1543EXPORT_SYMBOL_GPL(kvm_write_tsc);
1544
58ea6767
HZ		 1545static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1546 s64 adjustment)
1547{
1548 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1549}
1550
1551static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1552{
1553 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1554 WARN_ON(adjustment < 0);
1555 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1556 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1557}
1558
d828199e
MT		 1559#ifdef CONFIG_X86_64
1560
1561static cycle_t read_tsc(void)
1562{
03b9730b
AL		 1563 cycle_t ret = (cycle_t)rdtsc_ordered();
1564 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1565
1566 if (likely(ret >= last))
1567 return ret;
1568
1569 /*
1570 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1571 * predictable (it's just a function of time and the likely is
d828199e
MT		 1572 * very likely) and there's a data dependence, so force GCC
1573 * to generate a branch instead. I don't barrier() because
1574 * we don't actually need a barrier, and if this function
1575 * ever gets inlined it will generate worse code.
1576 */
1577 asm volatile ("");
1578 return last;
1579}
1580
1581static inline u64 vgettsc(cycle_t *cycle_now)
1582{
1583 long v;
1584 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1585
1586 *cycle_now = read_tsc();
1587
1588 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1589 return v * gtod->clock.mult;
1590}
1591
cbcf2dd3 1592static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1593{
cbcf2dd3 1594 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1595 unsigned long seq;
d828199e 1596 int mode;
cbcf2dd3 1597 u64 ns;
d828199e 1598
d828199e
MT		 1599 do {
1600 seq = read_seqcount_begin(&gtod->seq);
1601 mode = gtod->clock.vclock_mode;
cbcf2dd3 1602 ns = gtod->nsec_base;
d828199e
MT		 1603 ns += vgettsc(cycle_now);
1604 ns >>= gtod->clock.shift;
cbcf2dd3 1605 ns += gtod->boot_ns;
d828199e 1606 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1607 *t = ns;
d828199e
MT		 1608
1609 return mode;
1610}
1611
1612/* returns true if host is using tsc clocksource */
1613static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1614{
d828199e
MT		 1615 /* checked again under seqlock below */
1616 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1617 return false;
1618
cbcf2dd3 1619 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1620}
1621#endif
1622
1623/*
1624 *
b48aa97e
MT		 1625 * Assuming a stable TSC across physical CPUS, and a stable TSC
1626 * across virtual CPUs, the following condition is possible.
1627 * Each numbered line represents an event visible to both
d828199e
MT		 1628 * CPUs at the next numbered event.
1629 *
1630 * "timespecX" represents host monotonic time. "tscX" represents
1631 * RDTSC value.
1632 *
1633 * VCPU0 on CPU0 | VCPU1 on CPU1
1634 *
1635 * 1. read timespec0,tsc0
1636 * 2. | timespec1 = timespec0 + N
1637 * | tsc1 = tsc0 + M
1638 * 3. transition to guest | transition to guest
1639 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1640 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1641 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1642 *
1643 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1644 *
1645 * - ret0 < ret1
1646 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1647 * ...
1648 * - 0 < N - M => M < N
1649 *
1650 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1651 * always the case (the difference between two distinct xtime instances
1652 * might be smaller then the difference between corresponding TSC reads,
1653 * when updating guest vcpus pvclock areas).
1654 *
1655 * To avoid that problem, do not allow visibility of distinct
1656 * system_timestamp/tsc_timestamp values simultaneously: use a master
1657 * copy of host monotonic time values. Update that master copy
1658 * in lockstep.
1659 *
b48aa97e 1660 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1661 *
1662 */
1663
1664static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1665{
1666#ifdef CONFIG_X86_64
1667 struct kvm_arch *ka = &kvm->arch;
1668 int vclock_mode;
b48aa97e
MT		 1669 bool host_tsc_clocksource, vcpus_matched;
1670
1671 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1672 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1673
1674 /*
1675 * If the host uses TSC clock, then passthrough TSC as stable
1676 * to the guest.
1677 */
b48aa97e 1678 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1679 &ka->master_kernel_ns,
1680 &ka->master_cycle_now);
1681
16a96021 1682 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1683 && !backwards_tsc_observed
1684 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1685
d828199e
MT		 1686 if (ka->use_master_clock)
1687 atomic_set(&kvm_guest_has_master_clock, 1);
1688
1689 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1690 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1691 vcpus_matched);
d828199e
MT		 1692#endif
1693}
1694
2860c4b1
PB		 1695void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1696{
1697 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1698}
1699
2e762ff7
MT		 1700static void kvm_gen_update_masterclock(struct kvm *kvm)
1701{
1702#ifdef CONFIG_X86_64
1703 int i;
1704 struct kvm_vcpu *vcpu;
1705 struct kvm_arch *ka = &kvm->arch;
1706
1707 spin_lock(&ka->pvclock_gtod_sync_lock);
1708 kvm_make_mclock_inprogress_request(kvm);
1709 /* no guest entries from this point */
1710 pvclock_update_vm_gtod_copy(kvm);
1711
1712 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1713 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1714
1715 /* guest entries allowed */
1716 kvm_for_each_vcpu(i, vcpu, kvm)
1717 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1718
1719 spin_unlock(&ka->pvclock_gtod_sync_lock);
1720#endif
1721}
1722
34c238a1 1723static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1724{
78db6a50 1725 unsigned long flags, tgt_tsc_khz;
18068523 1726 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1727 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1728 s64 kernel_ns;
d828199e 1729 u64 tsc_timestamp, host_tsc;
0b79459b 1730 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1731 u8 pvclock_flags;
d828199e
MT		 1732 bool use_master_clock;
1733
1734 kernel_ns = 0;
1735 host_tsc = 0;
18068523 1736
d828199e
MT		 1737 /*
1738 * If the host uses TSC clock, then passthrough TSC as stable
1739 * to the guest.
1740 */
1741 spin_lock(&ka->pvclock_gtod_sync_lock);
1742 use_master_clock = ka->use_master_clock;
1743 if (use_master_clock) {
1744 host_tsc = ka->master_cycle_now;
1745 kernel_ns = ka->master_kernel_ns;
1746 }
1747 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1748
1749 /* Keep irq disabled to prevent changes to the clock */
1750 local_irq_save(flags);
78db6a50
PB		 1751 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1752 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1753 local_irq_restore(flags);
1754 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1755 return 1;
1756 }
d828199e 1757 if (!use_master_clock) {
4ea1636b 1758 host_tsc = rdtsc();
d828199e
MT		 1759 kernel_ns = get_kernel_ns();
1760 }
1761
4ba76538 1762 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1763
c285545f
ZA		 1764 /*
1765 * We may have to catch up the TSC to match elapsed wall clock
1766 * time for two reasons, even if kvmclock is used.
1767 * 1) CPU could have been running below the maximum TSC rate
1768 * 2) Broken TSC compensation resets the base at each VCPU
1769 * entry to avoid unknown leaps of TSC even when running
1770 * again on the same CPU. This may cause apparent elapsed
1771 * time to disappear, and the guest to stand still or run
1772 * very slowly.
1773 */
1774 if (vcpu->tsc_catchup) {
1775 u64 tsc = compute_guest_tsc(v, kernel_ns);
1776 if (tsc > tsc_timestamp) {
f1e2b260 1777 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1778 tsc_timestamp = tsc;
1779 }
50d0a0f9
GH		 1780 }
1781
18068523
GOC		 1782 local_irq_restore(flags);
1783
0b79459b 1784 if (!vcpu->pv_time_enabled)
c285545f 1785 return 0;
18068523 1786
78db6a50
PB		 1787 if (kvm_has_tsc_control)
1788 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1789
1790 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1791 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1792 &vcpu->hv_clock.tsc_shift,
1793 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1794 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1795 }
1796
1797 /* With all the info we got, fill in the values */
1d5f066e 1798 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1799 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1800 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1801
09a0c3f1
OH		 1802 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1803 &guest_hv_clock, sizeof(guest_hv_clock))))
1804 return 0;
1805
5dca0d91
RK		 1806 /* This VCPU is paused, but it's legal for a guest to read another
1807 * VCPU's kvmclock, so we really have to follow the specification where
1808 * it says that version is odd if data is being modified, and even after
1809 * it is consistent.
1810 *
1811 * Version field updates must be kept separate. This is because
1812 * kvm_write_guest_cached might use a "rep movs" instruction, and
1813 * writes within a string instruction are weakly ordered. So there
1814 * are three writes overall.
1815 *
1816 * As a small optimization, only write the version field in the first
1817 * and third write. The vcpu->pv_time cache is still valid, because the
1818 * version field is the first in the struct.
18068523 1819 */
5dca0d91
RK		 1820 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1821
1822 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1823 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1824 &vcpu->hv_clock,
1825 sizeof(vcpu->hv_clock.version));
1826
1827 smp_wmb();
78c0337a
MT		 1828
1829 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1830 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1831
1832 if (vcpu->pvclock_set_guest_stopped_request) {
1833 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1834 vcpu->pvclock_set_guest_stopped_request = false;
1835 }
1836
d828199e
MT		 1837 /* If the host uses TSC clocksource, then it is stable */
1838 if (use_master_clock)
1839 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1840
78c0337a
MT		 1841 vcpu->hv_clock.flags = pvclock_flags;
1842
ce1a5e60
DM		 1843 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1844
0b79459b
AH		 1845 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1846 &vcpu->hv_clock,
1847 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1848
1849 smp_wmb();
1850
1851 vcpu->hv_clock.version++;
1852 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1853 &vcpu->hv_clock,
1854 sizeof(vcpu->hv_clock.version));
8cfdc000 1855 return 0;
c8076604
GH		 1856}
1857
0061d53d
MT		 1858/*
1859 * kvmclock updates which are isolated to a given vcpu, such as
1860 * vcpu->cpu migration, should not allow system_timestamp from
1861 * the rest of the vcpus to remain static. Otherwise ntp frequency
1862 * correction applies to one vcpu's system_timestamp but not
1863 * the others.
1864 *
1865 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1866 * We need to rate-limit these requests though, as they can
1867 * considerably slow guests that have a large number of vcpus.
1868 * The time for a remote vcpu to update its kvmclock is bound
1869 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1870 */
1871
7e44e449
AJ		 1872#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1873
1874static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1875{
1876 int i;
7e44e449
AJ		 1877 struct delayed_work *dwork = to_delayed_work(work);
1878 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1879 kvmclock_update_work);
1880 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1881 struct kvm_vcpu *vcpu;
1882
1883 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1884 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1885 kvm_vcpu_kick(vcpu);
1886 }
1887}
1888
7e44e449
AJ		 1889static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1890{
1891 struct kvm *kvm = v->kvm;
1892
105b21bb 1893 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1894 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1895 KVMCLOCK_UPDATE_DELAY);
1896}
1897
332967a3
AJ		 1898#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1899
1900static void kvmclock_sync_fn(struct work_struct *work)
1901{
1902 struct delayed_work *dwork = to_delayed_work(work);
1903 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1904 kvmclock_sync_work);
1905 struct kvm *kvm = container_of(ka, struct kvm, arch);
1906
630994b3
MT		 1907 if (!kvmclock_periodic_sync)
1908 return;
1909
332967a3
AJ		 1910 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1911 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1912 KVMCLOCK_SYNC_PERIOD);
1913}
1914
890ca9ae 1915static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1916{
890ca9ae
HY		 1917 u64 mcg_cap = vcpu->arch.mcg_cap;
1918 unsigned bank_num = mcg_cap & 0xff;
1919
15c4a640 1920 switch (msr) {
15c4a640 1921 case MSR_IA32_MCG_STATUS:
890ca9ae 1922 vcpu->arch.mcg_status = data;
15c4a640 1923 break;
c7ac679c 1924 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1925 if (!(mcg_cap & MCG_CTL_P))
1926 return 1;
1927 if (data != 0 && data != ~(u64)0)
1928 return -1;
1929 vcpu->arch.mcg_ctl = data;
1930 break;
1931 default:
1932 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1933 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1934 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1935 /* only 0 or all 1s can be written to IA32_MCi_CTL
1936 * some Linux kernels though clear bit 10 in bank 4 to
1937 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1938 * this to avoid an uncatched #GP in the guest
1939 */
890ca9ae 1940 if ((offset & 0x3) == 0 &&
114be429 1941 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1942 return -1;
1943 vcpu->arch.mce_banks[offset] = data;
1944 break;
1945 }
1946 return 1;
1947 }
1948 return 0;
1949}
1950
ffde22ac
ES		 1951static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1952{
1953 struct kvm *kvm = vcpu->kvm;
1954 int lm = is_long_mode(vcpu);
1955 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1956 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1957 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1958 : kvm->arch.xen_hvm_config.blob_size_32;
1959 u32 page_num = data & ~PAGE_MASK;
1960 u64 page_addr = data & PAGE_MASK;
1961 u8 *page;
1962 int r;
1963
1964 r = -E2BIG;
1965 if (page_num >= blob_size)
1966 goto out;
1967 r = -ENOMEM;
ff5c2c03
SL		 1968 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1969 if (IS_ERR(page)) {
1970 r = PTR_ERR(page);
ffde22ac 1971 goto out;
ff5c2c03 1972 }
54bf36aa 1973 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1974 goto out_free;
1975 r = 0;
1976out_free:
1977 kfree(page);
1978out:
1979 return r;
1980}
1981
344d9588
GN		 1982static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1983{
1984 gpa_t gpa = data & ~0x3f;
1985
4a969980 1986 /* Bits 2:5 are reserved, Should be zero */
6adba527 1987 if (data & 0x3c)
344d9588
GN		 1988 return 1;
1989
1990 vcpu->arch.apf.msr_val = data;
1991
1992 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1993 kvm_clear_async_pf_completion_queue(vcpu);
1994 kvm_async_pf_hash_reset(vcpu);
1995 return 0;
1996 }
1997
8f964525
AH		 1998 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1999 sizeof(u32)))
344d9588
GN		 2000 return 1;
2001
6adba527 2002 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2003 kvm_async_pf_wakeup_all(vcpu);
2004 return 0;
2005}
2006
12f9a48f
GC		 2007static void kvmclock_reset(struct kvm_vcpu *vcpu)
2008{
0b79459b 2009 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2010}
2011
c9aaa895
GC		 2012static void record_steal_time(struct kvm_vcpu *vcpu)
2013{
2014 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2015 return;
2016
2017 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2018 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2019 return;
2020
35f3fae1
WL		 2021 if (vcpu->arch.st.steal.version & 1)
2022 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2023
2024 vcpu->arch.st.steal.version += 1;
2025
2026 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2027 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2028
2029 smp_wmb();
2030
c54cdf14
LC		 2031 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2032 vcpu->arch.st.last_steal;
2033 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2034
2035 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2036 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2037
2038 smp_wmb();
2039
2040 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2041
2042 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2043 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2044}
2045
8fe8ab46 2046int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2047{
5753785f 2048 bool pr = false;
8fe8ab46
WA		 2049 u32 msr = msr_info->index;
2050 u64 data = msr_info->data;
5753785f 2051
15c4a640 2052 switch (msr) {
2e32b719
BP		 2053 case MSR_AMD64_NB_CFG:
2054 case MSR_IA32_UCODE_REV:
2055 case MSR_IA32_UCODE_WRITE:
2056 case MSR_VM_HSAVE_PA:
2057 case MSR_AMD64_PATCH_LOADER:
2058 case MSR_AMD64_BU_CFG2:
2059 break;
2060
15c4a640 2061 case MSR_EFER:
b69e8cae 2062 return set_efer(vcpu, data);
8f1589d9
AP		 2063 case MSR_K7_HWCR:
2064 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2065 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2066 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2067 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2068 if (data != 0) {
a737f256
CD		 2069 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2070 data);
8f1589d9
AP		 2071 return 1;
2072 }
15c4a640 2073 break;
f7c6d140
AP		 2074 case MSR_FAM10H_MMIO_CONF_BASE:
2075 if (data != 0) {
a737f256
CD		 2076 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2077 "0x%llx\n", data);
f7c6d140
AP		 2078 return 1;
2079 }
15c4a640 2080 break;
b5e2fec0
AG		 2081 case MSR_IA32_DEBUGCTLMSR:
2082 if (!data) {
2083 /* We support the non-activated case already */
2084 break;
2085 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2086 /* Values other than LBR and BTF are vendor-specific,
2087 thus reserved and should throw a #GP */
2088 return 1;
2089 }
a737f256
CD		 2090 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2091 __func__, data);
b5e2fec0 2092 break;
9ba075a6 2093 case 0x200 ... 0x2ff:
ff53604b 2094 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2095 case MSR_IA32_APICBASE:
58cb628d 2096 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2097 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2098 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2099 case MSR_IA32_TSCDEADLINE:
2100 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2101 break;
ba904635
WA		 2102 case MSR_IA32_TSC_ADJUST:
2103 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2104 if (!msr_info->host_initiated) {
d913b904 2105 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2106 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2107 }
2108 vcpu->arch.ia32_tsc_adjust_msr = data;
2109 }
2110 break;
15c4a640 2111 case MSR_IA32_MISC_ENABLE:
ad312c7c 2112 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2113 break;
64d60670
PB		 2114 case MSR_IA32_SMBASE:
2115 if (!msr_info->host_initiated)
2116 return 1;
2117 vcpu->arch.smbase = data;
2118 break;
11c6bffa 2119 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2120 case MSR_KVM_WALL_CLOCK:
2121 vcpu->kvm->arch.wall_clock = data;
2122 kvm_write_wall_clock(vcpu->kvm, data);
2123 break;
11c6bffa 2124 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2125 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2126 u64 gpa_offset;
54750f2c
MT		 2127 struct kvm_arch *ka = &vcpu->kvm->arch;
2128
12f9a48f 2129 kvmclock_reset(vcpu);
18068523 2130
54750f2c
MT		 2131 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2132 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2133
2134 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2135 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2136 &vcpu->requests);
2137
2138 ka->boot_vcpu_runs_old_kvmclock = tmp;
2139 }
2140
18068523 2141 vcpu->arch.time = data;
0061d53d 2142 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2143
2144 /* we verify if the enable bit is set... */
2145 if (!(data & 1))
2146 break;
2147
0b79459b 2148 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2149
0b79459b 2150 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2151 &vcpu->arch.pv_time, data & ~1ULL,
2152 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2153 vcpu->arch.pv_time_enabled = false;
2154 else
2155 vcpu->arch.pv_time_enabled = true;
32cad84f 2156
18068523
GOC		 2157 break;
2158 }
344d9588
GN		 2159 case MSR_KVM_ASYNC_PF_EN:
2160 if (kvm_pv_enable_async_pf(vcpu, data))
2161 return 1;
2162 break;
c9aaa895
GC		 2163 case MSR_KVM_STEAL_TIME:
2164
2165 if (unlikely(!sched_info_on()))
2166 return 1;
2167
2168 if (data & KVM_STEAL_RESERVED_MASK)
2169 return 1;
2170
2171 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2172 data & KVM_STEAL_VALID_BITS,
2173 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2174 return 1;
2175
2176 vcpu->arch.st.msr_val = data;
2177
2178 if (!(data & KVM_MSR_ENABLED))
2179 break;
2180
c9aaa895
GC		 2181 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2182
2183 break;
ae7a2a3f
MT		 2184 case MSR_KVM_PV_EOI_EN:
2185 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2186 return 1;
2187 break;
c9aaa895 2188
890ca9ae
HY		 2189 case MSR_IA32_MCG_CTL:
2190 case MSR_IA32_MCG_STATUS:
81760dcc 2191 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2192 return set_msr_mce(vcpu, msr, data);
71db6023 2193
6912ac32
WH		 2194 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2195 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2196 pr = true; /* fall through */
2197 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2198 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2199 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2200 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2201
2202 if (pr || data != 0)
a737f256
CD		 2203 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2204 "0x%x data 0x%llx\n", msr, data);
5753785f 2205 break;
84e0cefa
JS		 2206 case MSR_K7_CLK_CTL:
2207 /*
2208 * Ignore all writes to this no longer documented MSR.
2209 * Writes are only relevant for old K7 processors,
2210 * all pre-dating SVM, but a recommended workaround from
4a969980 2211 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2212 * affected processor models on the command line, hence
2213 * the need to ignore the workaround.
2214 */
2215 break;
55cd8e5a 2216 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2217 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2218 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2219 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2220 return kvm_hv_set_msr_common(vcpu, msr, data,
2221 msr_info->host_initiated);
91c9c3ed 2222 case MSR_IA32_BBL_CR_CTL3:
2223 /* Drop writes to this legacy MSR -- see rdmsr
2224 * counterpart for further detail.
2225 */
a737f256 2226 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2227 break;
2b036c6b
BO		 2228 case MSR_AMD64_OSVW_ID_LENGTH:
2229 if (!guest_cpuid_has_osvw(vcpu))
2230 return 1;
2231 vcpu->arch.osvw.length = data;
2232 break;
2233 case MSR_AMD64_OSVW_STATUS:
2234 if (!guest_cpuid_has_osvw(vcpu))
2235 return 1;
2236 vcpu->arch.osvw.status = data;
2237 break;
15c4a640 2238 default:
ffde22ac
ES		 2239 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2240 return xen_hvm_config(vcpu, data);
c6702c9d 2241 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2242 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2243 if (!ignore_msrs) {
a737f256
CD		 2244 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2245 msr, data);
ed85c068
AP		 2246 return 1;
2247 } else {
a737f256
CD		 2248 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2249 msr, data);
ed85c068
AP		 2250 break;
2251 }
15c4a640
CO		 2252 }
2253 return 0;
2254}
2255EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2256
2257
2258/*
2259 * Reads an msr value (of 'msr_index') into 'pdata'.
2260 * Returns 0 on success, non-0 otherwise.
2261 * Assumes vcpu_load() was already called.
2262 */
609e36d3 2263int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2264{
609e36d3 2265 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2266}
ff651cb6 2267EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2268
890ca9ae 2269static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2270{
2271 u64 data;
890ca9ae
HY		 2272 u64 mcg_cap = vcpu->arch.mcg_cap;
2273 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2274
2275 switch (msr) {
15c4a640
CO		 2276 case MSR_IA32_P5_MC_ADDR:
2277 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2278 data = 0;
2279 break;
15c4a640 2280 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2281 data = vcpu->arch.mcg_cap;
2282 break;
c7ac679c 2283 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2284 if (!(mcg_cap & MCG_CTL_P))
2285 return 1;
2286 data = vcpu->arch.mcg_ctl;
2287 break;
2288 case MSR_IA32_MCG_STATUS:
2289 data = vcpu->arch.mcg_status;
2290 break;
2291 default:
2292 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2293 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2294 u32 offset = msr - MSR_IA32_MC0_CTL;
2295 data = vcpu->arch.mce_banks[offset];
2296 break;
2297 }
2298 return 1;
2299 }
2300 *pdata = data;
2301 return 0;
2302}
2303
609e36d3 2304int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2305{
609e36d3 2306 switch (msr_info->index) {
890ca9ae 2307 case MSR_IA32_PLATFORM_ID:
15c4a640 2308 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2309 case MSR_IA32_DEBUGCTLMSR:
2310 case MSR_IA32_LASTBRANCHFROMIP:
2311 case MSR_IA32_LASTBRANCHTOIP:
2312 case MSR_IA32_LASTINTFROMIP:
2313 case MSR_IA32_LASTINTTOIP:
60af2ecd 2314 case MSR_K8_SYSCFG:
3afb1121
PB		 2315 case MSR_K8_TSEG_ADDR:
2316 case MSR_K8_TSEG_MASK:
60af2ecd 2317 case MSR_K7_HWCR:
61a6bd67 2318 case MSR_VM_HSAVE_PA:
1fdbd48c 2319 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2320 case MSR_AMD64_NB_CFG:
f7c6d140 2321 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2322 case MSR_AMD64_BU_CFG2:
0c2df2a1 2323 case MSR_IA32_PERF_CTL:
609e36d3 2324 msr_info->data = 0;
15c4a640 2325 break;
6912ac32
WH		 2326 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2327 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2328 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2329 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2330 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2331 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2332 msr_info->data = 0;
5753785f 2333 break;
742bc670 2334 case MSR_IA32_UCODE_REV:
609e36d3 2335 msr_info->data = 0x100000000ULL;
742bc670 2336 break;
9ba075a6 2337 case MSR_MTRRcap:
9ba075a6 2338 case 0x200 ... 0x2ff:
ff53604b 2339 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2340 case 0xcd: /* fsb frequency */
609e36d3 2341 msr_info->data = 3;
15c4a640 2342 break;
7b914098
JS		 2343 /*
2344 * MSR_EBC_FREQUENCY_ID
2345 * Conservative value valid for even the basic CPU models.
2346 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2347 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2348 * and 266MHz for model 3, or 4. Set Core Clock
2349 * Frequency to System Bus Frequency Ratio to 1 (bits
2350 * 31:24) even though these are only valid for CPU
2351 * models > 2, however guests may end up dividing or
2352 * multiplying by zero otherwise.
2353 */
2354 case MSR_EBC_FREQUENCY_ID:
609e36d3 2355 msr_info->data = 1 << 24;
7b914098 2356 break;
15c4a640 2357 case MSR_IA32_APICBASE:
609e36d3 2358 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2359 break;
0105d1a5 2360 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2361 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2362 break;
a3e06bbe 2363 case MSR_IA32_TSCDEADLINE:
609e36d3 2364 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2365 break;
ba904635 2366 case MSR_IA32_TSC_ADJUST:
609e36d3 2367 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2368 break;
15c4a640 2369 case MSR_IA32_MISC_ENABLE:
609e36d3 2370 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2371 break;
64d60670
PB		 2372 case MSR_IA32_SMBASE:
2373 if (!msr_info->host_initiated)
2374 return 1;
2375 msr_info->data = vcpu->arch.smbase;
15c4a640 2376 break;
847f0ad8
AG		 2377 case MSR_IA32_PERF_STATUS:
2378 /* TSC increment by tick */
609e36d3 2379 msr_info->data = 1000ULL;
847f0ad8 2380 /* CPU multiplier */
b0996ae4 2381 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2382 break;
15c4a640 2383 case MSR_EFER:
609e36d3 2384 msr_info->data = vcpu->arch.efer;
15c4a640 2385 break;
18068523 2386 case MSR_KVM_WALL_CLOCK:
11c6bffa 2387 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2388 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2389 break;
2390 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2391 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2392 msr_info->data = vcpu->arch.time;
18068523 2393 break;
344d9588 2394 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2395 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2396 break;
c9aaa895 2397 case MSR_KVM_STEAL_TIME:
609e36d3 2398 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2399 break;
1d92128f 2400 case MSR_KVM_PV_EOI_EN:
609e36d3 2401 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2402 break;
890ca9ae
HY		 2403 case MSR_IA32_P5_MC_ADDR:
2404 case MSR_IA32_P5_MC_TYPE:
2405 case MSR_IA32_MCG_CAP:
2406 case MSR_IA32_MCG_CTL:
2407 case MSR_IA32_MCG_STATUS:
81760dcc 2408 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2409 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2410 case MSR_K7_CLK_CTL:
2411 /*
2412 * Provide expected ramp-up count for K7. All other
2413 * are set to zero, indicating minimum divisors for
2414 * every field.
2415 *
2416 * This prevents guest kernels on AMD host with CPU
2417 * type 6, model 8 and higher from exploding due to
2418 * the rdmsr failing.
2419 */
609e36d3 2420 msr_info->data = 0x20000000;
84e0cefa 2421 break;
55cd8e5a 2422 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2423 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2424 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2425 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2426 return kvm_hv_get_msr_common(vcpu,
2427 msr_info->index, &msr_info->data);
55cd8e5a 2428 break;
91c9c3ed 2429 case MSR_IA32_BBL_CR_CTL3:
2430 /* This legacy MSR exists but isn't fully documented in current
2431 * silicon. It is however accessed by winxp in very narrow
2432 * scenarios where it sets bit #19, itself documented as
2433 * a "reserved" bit. Best effort attempt to source coherent
2434 * read data here should the balance of the register be
2435 * interpreted by the guest:
2436 *
2437 * L2 cache control register 3: 64GB range, 256KB size,
2438 * enabled, latency 0x1, configured
2439 */
609e36d3 2440 msr_info->data = 0xbe702111;
91c9c3ed 2441 break;
2b036c6b
BO		 2442 case MSR_AMD64_OSVW_ID_LENGTH:
2443 if (!guest_cpuid_has_osvw(vcpu))
2444 return 1;
609e36d3 2445 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2446 break;
2447 case MSR_AMD64_OSVW_STATUS:
2448 if (!guest_cpuid_has_osvw(vcpu))
2449 return 1;
609e36d3 2450 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2451 break;
15c4a640 2452 default:
c6702c9d 2453 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2454 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2455 if (!ignore_msrs) {
609e36d3 2456 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2457 return 1;
2458 } else {
609e36d3
PB		 2459 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2460 msr_info->data = 0;
ed85c068
AP		 2461 }
2462 break;
15c4a640 2463 }
15c4a640
CO		 2464 return 0;
2465}
2466EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2467
313a3dc7
CO		 2468/*
2469 * Read or write a bunch of msrs. All parameters are kernel addresses.
2470 *
2471 * @return number of msrs set successfully.
2472 */
2473static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2474 struct kvm_msr_entry *entries,
2475 int (*do_msr)(struct kvm_vcpu *vcpu,
2476 unsigned index, u64 *data))
2477{
f656ce01 2478 int i, idx;
313a3dc7 2479
f656ce01 2480 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2481 for (i = 0; i < msrs->nmsrs; ++i)
2482 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2483 break;
f656ce01 2484 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2485
313a3dc7
CO		 2486 return i;
2487}
2488
2489/*
2490 * Read or write a bunch of msrs. Parameters are user addresses.
2491 *
2492 * @return number of msrs set successfully.
2493 */
2494static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2495 int (*do_msr)(struct kvm_vcpu *vcpu,
2496 unsigned index, u64 *data),
2497 int writeback)
2498{
2499 struct kvm_msrs msrs;
2500 struct kvm_msr_entry *entries;
2501 int r, n;
2502 unsigned size;
2503
2504 r = -EFAULT;
2505 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2506 goto out;
2507
2508 r = -E2BIG;
2509 if (msrs.nmsrs >= MAX_IO_MSRS)
2510 goto out;
2511
313a3dc7 2512 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2513 entries = memdup_user(user_msrs->entries, size);
2514 if (IS_ERR(entries)) {
2515 r = PTR_ERR(entries);
313a3dc7 2516 goto out;
ff5c2c03 2517 }
313a3dc7
CO		 2518
2519 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2520 if (r < 0)
2521 goto out_free;
2522
2523 r = -EFAULT;
2524 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2525 goto out_free;
2526
2527 r = n;
2528
2529out_free:
7a73c028 2530 kfree(entries);
313a3dc7
CO		 2531out:
2532 return r;
2533}
2534
784aa3d7 2535int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2536{
2537 int r;
2538
2539 switch (ext) {
2540 case KVM_CAP_IRQCHIP:
2541 case KVM_CAP_HLT:
2542 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2543 case KVM_CAP_SET_TSS_ADDR:
07716717 2544 case KVM_CAP_EXT_CPUID:
9c15bb1d 2545 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2546 case KVM_CAP_CLOCKSOURCE:
7837699f 2547 case KVM_CAP_PIT:
a28e4f5a 2548 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2549 case KVM_CAP_MP_STATE:
ed848624 2550 case KVM_CAP_SYNC_MMU:
a355c85c 2551 case KVM_CAP_USER_NMI:
52d939a0 2552 case KVM_CAP_REINJECT_CONTROL:
4925663a 2553 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2554 case KVM_CAP_IOEVENTFD:
f848a5a8 2555 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2556 case KVM_CAP_PIT2:
e9f42757 2557 case KVM_CAP_PIT_STATE2:
b927a3ce 2558 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2559 case KVM_CAP_XEN_HVM:
afbcf7ab 2560 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2561 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2562 case KVM_CAP_HYPERV:
10388a07 2563 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2564 case KVM_CAP_HYPERV_SPIN:
5c919412 2565 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2566 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2567 case KVM_CAP_DEBUGREGS:
d2be1651 2568 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2569 case KVM_CAP_XSAVE:
344d9588 2570 case KVM_CAP_ASYNC_PF:
92a1f12d 2571 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2572 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2573 case KVM_CAP_READONLY_MEM:
5f66b620 2574 case KVM_CAP_HYPERV_TIME:
100943c5 2575 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2576 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2577 case KVM_CAP_ENABLE_CAP_VM:
2578 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2579 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2580 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2581#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2582 case KVM_CAP_ASSIGN_DEV_IRQ:
2583 case KVM_CAP_PCI_2_3:
2584#endif
018d00d2
ZX		 2585 r = 1;
2586 break;
6d396b55
PB		 2587 case KVM_CAP_X86_SMM:
2588 /* SMBASE is usually relocated above 1M on modern chipsets,
2589 * and SMM handlers might indeed rely on 4G segment limits,
2590 * so do not report SMM to be available if real mode is
2591 * emulated via vm86 mode. Still, do not go to great lengths
2592 * to avoid userspace's usage of the feature, because it is a
2593 * fringe case that is not enabled except via specific settings
2594 * of the module parameters.
2595 */
2596 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2597 break;
542472b5
LV		 2598 case KVM_CAP_COALESCED_MMIO:
2599 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2600 break;
774ead3a
AK		 2601 case KVM_CAP_VAPIC:
2602 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2603 break;
f725230a 2604 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2605 r = KVM_SOFT_MAX_VCPUS;
2606 break;
2607 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2608 r = KVM_MAX_VCPUS;
2609 break;
a988b910 2610 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2611 r = KVM_USER_MEM_SLOTS;
a988b910 2612 break;
a68a6a72
MT		 2613 case KVM_CAP_PV_MMU: /* obsolete */
2614 r = 0;
2f333bcb 2615 break;
4cee4b72 2616#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2617 case KVM_CAP_IOMMU:
a1b60c1c 2618 r = iommu_present(&pci_bus_type);
62c476c7 2619 break;
4cee4b72 2620#endif
890ca9ae
HY		 2621 case KVM_CAP_MCE:
2622 r = KVM_MAX_MCE_BANKS;
2623 break;
2d5b5a66 2624 case KVM_CAP_XCRS:
d366bf7e 2625 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2626 break;
92a1f12d
JR		 2627 case KVM_CAP_TSC_CONTROL:
2628 r = kvm_has_tsc_control;
2629 break;
37131313
RK		 2630 case KVM_CAP_X2APIC_API:
2631 r = KVM_X2APIC_API_VALID_FLAGS;
2632 break;
018d00d2
ZX		 2633 default:
2634 r = 0;
2635 break;
2636 }
2637 return r;
2638
2639}
2640
043405e1
CO		 2641long kvm_arch_dev_ioctl(struct file *filp,
2642 unsigned int ioctl, unsigned long arg)
2643{
2644 void __user *argp = (void __user *)arg;
2645 long r;
2646
2647 switch (ioctl) {
2648 case KVM_GET_MSR_INDEX_LIST: {
2649 struct kvm_msr_list __user *user_msr_list = argp;
2650 struct kvm_msr_list msr_list;
2651 unsigned n;
2652
2653 r = -EFAULT;
2654 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2655 goto out;
2656 n = msr_list.nmsrs;
62ef68bb 2657 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2658 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2659 goto out;
2660 r = -E2BIG;
e125e7b6 2661 if (n < msr_list.nmsrs)
043405e1
CO		 2662 goto out;
2663 r = -EFAULT;
2664 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2665 num_msrs_to_save * sizeof(u32)))
2666 goto out;
e125e7b6 2667 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2668 &emulated_msrs,
62ef68bb 2669 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2670 goto out;
2671 r = 0;
2672 break;
2673 }
9c15bb1d
BP		 2674 case KVM_GET_SUPPORTED_CPUID:
2675 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2676 struct kvm_cpuid2 __user *cpuid_arg = argp;
2677 struct kvm_cpuid2 cpuid;
2678
2679 r = -EFAULT;
2680 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2681 goto out;
9c15bb1d
BP		 2682
2683 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2684 ioctl);
674eea0f
AK		 2685 if (r)
2686 goto out;
2687
2688 r = -EFAULT;
2689 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2690 goto out;
2691 r = 0;
2692 break;
2693 }
890ca9ae 2694 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2695 r = -EFAULT;
c45dcc71
AR		 2696 if (copy_to_user(argp, &kvm_mce_cap_supported,
2697 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2698 goto out;
2699 r = 0;
2700 break;
2701 }
043405e1
CO		 2702 default:
2703 r = -EINVAL;
2704 }
2705out:
2706 return r;
2707}
2708
f5f48ee1
SY		 2709static void wbinvd_ipi(void *garbage)
2710{
2711 wbinvd();
2712}
2713
2714static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2715{
e0f0bbc5 2716 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2717}
2718
2860c4b1
PB		 2719static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2720{
2721 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2722}
2723
313a3dc7
CO		 2724void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2725{
f5f48ee1
SY		 2726 /* Address WBINVD may be executed by guest */
2727 if (need_emulate_wbinvd(vcpu)) {
2728 if (kvm_x86_ops->has_wbinvd_exit())
2729 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2730 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2731 smp_call_function_single(vcpu->cpu,
2732 wbinvd_ipi, NULL, 1);
2733 }
2734
313a3dc7 2735 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2736
0dd6a6ed
ZA		 2737 /* Apply any externally detected TSC adjustments (due to suspend) */
2738 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2739 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2740 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2741 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2742 }
8f6055cb 2743
48434c20 2744 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2745 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2746 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2747 if (tsc_delta < 0)
2748 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a
YJ		 2749
2750 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2751 kvm_x86_ops->set_hv_timer(vcpu,
2752 kvm_get_lapic_tscdeadline_msr(vcpu)))
2753 kvm_lapic_switch_to_sw_timer(vcpu);
c285545f 2754 if (check_tsc_unstable()) {
07c1419a 2755 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2756 vcpu->arch.last_guest_tsc);
2757 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2758 vcpu->arch.tsc_catchup = 1;
c285545f 2759 }
d98d07ca
MT		 2760 /*
2761 * On a host with synchronized TSC, there is no need to update
2762 * kvmclock on vcpu->cpu migration
2763 */
2764 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2765 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2766 if (vcpu->cpu != cpu)
2767 kvm_migrate_timers(vcpu);
e48672fa 2768 vcpu->cpu = cpu;
6b7d7e76 2769 }
c9aaa895 2770
c9aaa895 2771 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2772}
2773
2774void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2775{
02daab21 2776 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2777 kvm_put_guest_fpu(vcpu);
4ea1636b 2778 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2779}
2780
313a3dc7
CO		 2781static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2782 struct kvm_lapic_state *s)
2783{
d62caabb
AS		 2784 if (vcpu->arch.apicv_active)
2785 kvm_x86_ops->sync_pir_to_irr(vcpu);
2786
a92e2543 2787 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2788}
2789
2790static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2791 struct kvm_lapic_state *s)
2792{
a92e2543
RK		 2793 int r;
2794
2795 r = kvm_apic_set_state(vcpu, s);
2796 if (r)
2797 return r;
cb142eb7 2798 update_cr8_intercept(vcpu);
313a3dc7
CO		 2799
2800 return 0;
2801}
2802
127a457a
MG		 2803static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2804{
2805 return (!lapic_in_kernel(vcpu) ||
2806 kvm_apic_accept_pic_intr(vcpu));
2807}
2808
782d422b
MG		 2809/*
2810 * if userspace requested an interrupt window, check that the
2811 * interrupt window is open.
2812 *
2813 * No need to exit to userspace if we already have an interrupt queued.
2814 */
2815static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2816{
2817 return kvm_arch_interrupt_allowed(vcpu) &&
2818 !kvm_cpu_has_interrupt(vcpu) &&
2819 !kvm_event_needs_reinjection(vcpu) &&
2820 kvm_cpu_accept_dm_intr(vcpu);
2821}
2822
f77bc6a4
ZX		 2823static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2824 struct kvm_interrupt *irq)
2825{
02cdb50f 2826 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2827 return -EINVAL;
1c1a9ce9
SR		 2828
2829 if (!irqchip_in_kernel(vcpu->kvm)) {
2830 kvm_queue_interrupt(vcpu, irq->irq, false);
2831 kvm_make_request(KVM_REQ_EVENT, vcpu);
2832 return 0;
2833 }
2834
2835 /*
2836 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2837 * fail for in-kernel 8259.
2838 */
2839 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2840 return -ENXIO;
f77bc6a4 2841
1c1a9ce9
SR		 2842 if (vcpu->arch.pending_external_vector != -1)
2843 return -EEXIST;
f77bc6a4 2844
1c1a9ce9 2845 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2846 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2847 return 0;
2848}
2849
c4abb7c9
JK		 2850static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2851{
c4abb7c9 2852 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2853
2854 return 0;
2855}
2856
f077825a
PB		 2857static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2858{
64d60670
PB		 2859 kvm_make_request(KVM_REQ_SMI, vcpu);
2860
f077825a
PB		 2861 return 0;
2862}
2863
b209749f
AK		 2864static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2865 struct kvm_tpr_access_ctl *tac)
2866{
2867 if (tac->flags)
2868 return -EINVAL;
2869 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2870 return 0;
2871}
2872
890ca9ae
HY		 2873static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2874 u64 mcg_cap)
2875{
2876 int r;
2877 unsigned bank_num = mcg_cap & 0xff, bank;
2878
2879 r = -EINVAL;
a9e38c3e 2880 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2881 goto out;
c45dcc71 2882 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 2883 goto out;
2884 r = 0;
2885 vcpu->arch.mcg_cap = mcg_cap;
2886 /* Init IA32_MCG_CTL to all 1s */
2887 if (mcg_cap & MCG_CTL_P)
2888 vcpu->arch.mcg_ctl = ~(u64)0;
2889 /* Init IA32_MCi_CTL to all 1s */
2890 for (bank = 0; bank < bank_num; bank++)
2891 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 2892
2893 if (kvm_x86_ops->setup_mce)
2894 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 2895out:
2896 return r;
2897}
2898
2899static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2900 struct kvm_x86_mce *mce)
2901{
2902 u64 mcg_cap = vcpu->arch.mcg_cap;
2903 unsigned bank_num = mcg_cap & 0xff;
2904 u64 *banks = vcpu->arch.mce_banks;
2905
2906 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2907 return -EINVAL;
2908 /*
2909 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2910 * reporting is disabled
2911 */
2912 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2913 vcpu->arch.mcg_ctl != ~(u64)0)
2914 return 0;
2915 banks += 4 * mce->bank;
2916 /*
2917 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2918 * reporting is disabled for the bank
2919 */
2920 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2921 return 0;
2922 if (mce->status & MCI_STATUS_UC) {
2923 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2924 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2925 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2926 return 0;
2927 }
2928 if (banks[1] & MCI_STATUS_VAL)
2929 mce->status |= MCI_STATUS_OVER;
2930 banks[2] = mce->addr;
2931 banks[3] = mce->misc;
2932 vcpu->arch.mcg_status = mce->mcg_status;
2933 banks[1] = mce->status;
2934 kvm_queue_exception(vcpu, MC_VECTOR);
2935 } else if (!(banks[1] & MCI_STATUS_VAL)
2936 || !(banks[1] & MCI_STATUS_UC)) {
2937 if (banks[1] & MCI_STATUS_VAL)
2938 mce->status |= MCI_STATUS_OVER;
2939 banks[2] = mce->addr;
2940 banks[3] = mce->misc;
2941 banks[1] = mce->status;
2942 } else
2943 banks[1] |= MCI_STATUS_OVER;
2944 return 0;
2945}
2946
3cfc3092
JK		 2947static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2948 struct kvm_vcpu_events *events)
2949{
7460fb4a 2950 process_nmi(vcpu);
03b82a30
JK		 2951 events->exception.injected =
2952 vcpu->arch.exception.pending &&
2953 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2954 events->exception.nr = vcpu->arch.exception.nr;
2955 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2956 events->exception.pad = 0;
3cfc3092
JK		 2957 events->exception.error_code = vcpu->arch.exception.error_code;
2958
03b82a30
JK		 2959 events->interrupt.injected =
2960 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2961 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2962 events->interrupt.soft = 0;
37ccdcbe 2963 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2964
2965 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2966 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2967 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2968 events->nmi.pad = 0;
3cfc3092 2969
66450a21 2970 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2971
f077825a
PB		 2972 events->smi.smm = is_smm(vcpu);
2973 events->smi.pending = vcpu->arch.smi_pending;
2974 events->smi.smm_inside_nmi =
2975 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2976 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2977
dab4b911 2978 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2979 | KVM_VCPUEVENT_VALID_SHADOW
2980 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2981 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2982}
2983
2984static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2985 struct kvm_vcpu_events *events)
2986{
dab4b911 2987 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2988 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2989 | KVM_VCPUEVENT_VALID_SHADOW
2990 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2991 return -EINVAL;
2992
78e546c8
PB		 2993 if (events->exception.injected &&
2994 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
2995 return -EINVAL;
2996
7460fb4a 2997 process_nmi(vcpu);
3cfc3092
JK		 2998 vcpu->arch.exception.pending = events->exception.injected;
2999 vcpu->arch.exception.nr = events->exception.nr;
3000 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3001 vcpu->arch.exception.error_code = events->exception.error_code;
3002
3003 vcpu->arch.interrupt.pending = events->interrupt.injected;
3004 vcpu->arch.interrupt.nr = events->interrupt.nr;
3005 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3006 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3007 kvm_x86_ops->set_interrupt_shadow(vcpu,
3008 events->interrupt.shadow);
3cfc3092
JK		 3009
3010 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3011 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3012 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3013 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3014
66450a21 3015 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3016 lapic_in_kernel(vcpu))
66450a21 3017 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3018
f077825a
PB		 3019 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3020 if (events->smi.smm)
3021 vcpu->arch.hflags |= HF_SMM_MASK;
3022 else
3023 vcpu->arch.hflags &= ~HF_SMM_MASK;
3024 vcpu->arch.smi_pending = events->smi.pending;
3025 if (events->smi.smm_inside_nmi)
3026 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3027 else
3028 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3029 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3030 if (events->smi.latched_init)
3031 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3032 else
3033 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3034 }
3035 }
3036
3842d135
AK		 3037 kvm_make_request(KVM_REQ_EVENT, vcpu);
3038
3cfc3092
JK		 3039 return 0;
3040}
3041
a1efbe77
JK		 3042static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3043 struct kvm_debugregs *dbgregs)
3044{
73aaf249
JK		 3045 unsigned long val;
3046
a1efbe77 3047 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3048 kvm_get_dr(vcpu, 6, &val);
73aaf249 3049 dbgregs->dr6 = val;
a1efbe77
JK		 3050 dbgregs->dr7 = vcpu->arch.dr7;
3051 dbgregs->flags = 0;
97e69aa6 3052 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3053}
3054
3055static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3056 struct kvm_debugregs *dbgregs)
3057{
3058 if (dbgregs->flags)
3059 return -EINVAL;
3060
d14bdb55
PB		 3061 if (dbgregs->dr6 & ~0xffffffffull)
3062 return -EINVAL;
3063 if (dbgregs->dr7 & ~0xffffffffull)
3064 return -EINVAL;
3065
a1efbe77 3066 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3067 kvm_update_dr0123(vcpu);
a1efbe77 3068 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3069 kvm_update_dr6(vcpu);
a1efbe77 3070 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3071 kvm_update_dr7(vcpu);
a1efbe77 3072
a1efbe77
JK		 3073 return 0;
3074}
3075
df1daba7
PB		 3076#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3077
3078static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3079{
c47ada30 3080 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3081 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3082 u64 valid;
3083
3084 /*
3085 * Copy legacy XSAVE area, to avoid complications with CPUID
3086 * leaves 0 and 1 in the loop below.
3087 */
3088 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3089
3090 /* Set XSTATE_BV */
3091 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3092
3093 /*
3094 * Copy each region from the possibly compacted offset to the
3095 * non-compacted offset.
3096 */
d91cab78 3097 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3098 while (valid) {
3099 u64 feature = valid & -valid;
3100 int index = fls64(feature) - 1;
3101 void *src = get_xsave_addr(xsave, feature);
3102
3103 if (src) {
3104 u32 size, offset, ecx, edx;
3105 cpuid_count(XSTATE_CPUID, index,
3106 &size, &offset, &ecx, &edx);
3107 memcpy(dest + offset, src, size);
3108 }
3109
3110 valid -= feature;
3111 }
3112}
3113
3114static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3115{
c47ada30 3116 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3117 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3118 u64 valid;
3119
3120 /*
3121 * Copy legacy XSAVE area, to avoid complications with CPUID
3122 * leaves 0 and 1 in the loop below.
3123 */
3124 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3125
3126 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3127 xsave->header.xfeatures = xstate_bv;
782511b0 3128 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3129 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3130
3131 /*
3132 * Copy each region from the non-compacted offset to the
3133 * possibly compacted offset.
3134 */
d91cab78 3135 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3136 while (valid) {
3137 u64 feature = valid & -valid;
3138 int index = fls64(feature) - 1;
3139 void *dest = get_xsave_addr(xsave, feature);
3140
3141 if (dest) {
3142 u32 size, offset, ecx, edx;
3143 cpuid_count(XSTATE_CPUID, index,
3144 &size, &offset, &ecx, &edx);
3145 memcpy(dest, src + offset, size);
ee4100da 3146 }
df1daba7
PB		 3147
3148 valid -= feature;
3149 }
3150}
3151
2d5b5a66
SY		 3152static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3153 struct kvm_xsave *guest_xsave)
3154{
d366bf7e 3155 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3156 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3157 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3158 } else {
2d5b5a66 3159 memcpy(guest_xsave->region,
7366ed77 3160 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3161 sizeof(struct fxregs_state));
2d5b5a66 3162 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3163 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3164 }
3165}
3166
3167static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3168 struct kvm_xsave *guest_xsave)
3169{
3170 u64 xstate_bv =
3171 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3172
d366bf7e 3173 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3174 /*
3175 * Here we allow setting states that are not present in
3176 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3177 * with old userspace.
3178 */
4ff41732 3179 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3180 return -EINVAL;
df1daba7 3181 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3182 } else {
d91cab78 3183 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3184 return -EINVAL;
7366ed77 3185 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3186 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3187 }
3188 return 0;
3189}
3190
3191static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3192 struct kvm_xcrs *guest_xcrs)
3193{
d366bf7e 3194 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3195 guest_xcrs->nr_xcrs = 0;
3196 return;
3197 }
3198
3199 guest_xcrs->nr_xcrs = 1;
3200 guest_xcrs->flags = 0;
3201 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3202 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3203}
3204
3205static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3206 struct kvm_xcrs *guest_xcrs)
3207{
3208 int i, r = 0;
3209
d366bf7e 3210 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3211 return -EINVAL;
3212
3213 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3214 return -EINVAL;
3215
3216 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3217 /* Only support XCR0 currently */
c67a04cb 3218 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3219 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3220 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3221 break;
3222 }
3223 if (r)
3224 r = -EINVAL;
3225 return r;
3226}
3227
1c0b28c2
EM		 3228/*
3229 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3230 * stopped by the hypervisor. This function will be called from the host only.
3231 * EINVAL is returned when the host attempts to set the flag for a guest that
3232 * does not support pv clocks.
3233 */
3234static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3235{
0b79459b 3236 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3237 return -EINVAL;
51d59c6b 3238 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3239 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3240 return 0;
3241}
3242
5c919412
AS		 3243static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3244 struct kvm_enable_cap *cap)
3245{
3246 if (cap->flags)
3247 return -EINVAL;
3248
3249 switch (cap->cap) {
3250 case KVM_CAP_HYPERV_SYNIC:
3251 return kvm_hv_activate_synic(vcpu);
3252 default:
3253 return -EINVAL;
3254 }
3255}
3256
313a3dc7
CO		 3257long kvm_arch_vcpu_ioctl(struct file *filp,
3258 unsigned int ioctl, unsigned long arg)
3259{
3260 struct kvm_vcpu *vcpu = filp->private_data;
3261 void __user *argp = (void __user *)arg;
3262 int r;
d1ac91d8
AK		 3263 union {
3264 struct kvm_lapic_state *lapic;
3265 struct kvm_xsave *xsave;
3266 struct kvm_xcrs *xcrs;
3267 void *buffer;
3268 } u;
3269
3270 u.buffer = NULL;
313a3dc7
CO		 3271 switch (ioctl) {
3272 case KVM_GET_LAPIC: {
2204ae3c 3273 r = -EINVAL;
bce87cce 3274 if (!lapic_in_kernel(vcpu))
2204ae3c 3275 goto out;
d1ac91d8 3276 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3277
b772ff36 3278 r = -ENOMEM;
d1ac91d8 3279 if (!u.lapic)
b772ff36 3280 goto out;
d1ac91d8 3281 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3282 if (r)
3283 goto out;
3284 r = -EFAULT;
d1ac91d8 3285 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3286 goto out;
3287 r = 0;
3288 break;
3289 }
3290 case KVM_SET_LAPIC: {
2204ae3c 3291 r = -EINVAL;
bce87cce 3292 if (!lapic_in_kernel(vcpu))
2204ae3c 3293 goto out;
ff5c2c03 3294 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3295 if (IS_ERR(u.lapic))
3296 return PTR_ERR(u.lapic);
ff5c2c03 3297
d1ac91d8 3298 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3299 break;
3300 }
f77bc6a4
ZX		 3301 case KVM_INTERRUPT: {
3302 struct kvm_interrupt irq;
3303
3304 r = -EFAULT;
3305 if (copy_from_user(&irq, argp, sizeof irq))
3306 goto out;
3307 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3308 break;
3309 }
c4abb7c9
JK		 3310 case KVM_NMI: {
3311 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3312 break;
3313 }
f077825a
PB		 3314 case KVM_SMI: {
3315 r = kvm_vcpu_ioctl_smi(vcpu);
3316 break;
3317 }
313a3dc7
CO		 3318 case KVM_SET_CPUID: {
3319 struct kvm_cpuid __user *cpuid_arg = argp;
3320 struct kvm_cpuid cpuid;
3321
3322 r = -EFAULT;
3323 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3324 goto out;
3325 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3326 break;
3327 }
07716717
DK		 3328 case KVM_SET_CPUID2: {
3329 struct kvm_cpuid2 __user *cpuid_arg = argp;
3330 struct kvm_cpuid2 cpuid;
3331
3332 r = -EFAULT;
3333 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3334 goto out;
3335 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3336 cpuid_arg->entries);
07716717
DK		 3337 break;
3338 }
3339 case KVM_GET_CPUID2: {
3340 struct kvm_cpuid2 __user *cpuid_arg = argp;
3341 struct kvm_cpuid2 cpuid;
3342
3343 r = -EFAULT;
3344 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3345 goto out;
3346 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3347 cpuid_arg->entries);
07716717
DK		 3348 if (r)
3349 goto out;
3350 r = -EFAULT;
3351 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3352 goto out;
3353 r = 0;
3354 break;
3355 }
313a3dc7 3356 case KVM_GET_MSRS:
609e36d3 3357 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3358 break;
3359 case KVM_SET_MSRS:
3360 r = msr_io(vcpu, argp, do_set_msr, 0);
3361 break;
b209749f
AK		 3362 case KVM_TPR_ACCESS_REPORTING: {
3363 struct kvm_tpr_access_ctl tac;
3364
3365 r = -EFAULT;
3366 if (copy_from_user(&tac, argp, sizeof tac))
3367 goto out;
3368 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3369 if (r)
3370 goto out;
3371 r = -EFAULT;
3372 if (copy_to_user(argp, &tac, sizeof tac))
3373 goto out;
3374 r = 0;
3375 break;
3376 };
b93463aa
AK		 3377 case KVM_SET_VAPIC_ADDR: {
3378 struct kvm_vapic_addr va;
3379
3380 r = -EINVAL;
35754c98 3381 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3382 goto out;
3383 r = -EFAULT;
3384 if (copy_from_user(&va, argp, sizeof va))
3385 goto out;
fda4e2e8 3386 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3387 break;
3388 }
890ca9ae
HY		 3389 case KVM_X86_SETUP_MCE: {
3390 u64 mcg_cap;
3391
3392 r = -EFAULT;
3393 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3394 goto out;
3395 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3396 break;
3397 }
3398 case KVM_X86_SET_MCE: {
3399 struct kvm_x86_mce mce;
3400
3401 r = -EFAULT;
3402 if (copy_from_user(&mce, argp, sizeof mce))
3403 goto out;
3404 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3405 break;
3406 }
3cfc3092
JK		 3407 case KVM_GET_VCPU_EVENTS: {
3408 struct kvm_vcpu_events events;
3409
3410 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3411
3412 r = -EFAULT;
3413 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3414 break;
3415 r = 0;
3416 break;
3417 }
3418 case KVM_SET_VCPU_EVENTS: {
3419 struct kvm_vcpu_events events;
3420
3421 r = -EFAULT;
3422 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3423 break;
3424
3425 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3426 break;
3427 }
a1efbe77
JK		 3428 case KVM_GET_DEBUGREGS: {
3429 struct kvm_debugregs dbgregs;
3430
3431 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3432
3433 r = -EFAULT;
3434 if (copy_to_user(argp, &dbgregs,
3435 sizeof(struct kvm_debugregs)))
3436 break;
3437 r = 0;
3438 break;
3439 }
3440 case KVM_SET_DEBUGREGS: {
3441 struct kvm_debugregs dbgregs;
3442
3443 r = -EFAULT;
3444 if (copy_from_user(&dbgregs, argp,
3445 sizeof(struct kvm_debugregs)))
3446 break;
3447
3448 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3449 break;
3450 }
2d5b5a66 3451 case KVM_GET_XSAVE: {
d1ac91d8 3452 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3453 r = -ENOMEM;
d1ac91d8 3454 if (!u.xsave)
2d5b5a66
SY		 3455 break;
3456
d1ac91d8 3457 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3458
3459 r = -EFAULT;
d1ac91d8 3460 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3461 break;
3462 r = 0;
3463 break;
3464 }
3465 case KVM_SET_XSAVE: {
ff5c2c03 3466 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3467 if (IS_ERR(u.xsave))
3468 return PTR_ERR(u.xsave);
2d5b5a66 3469
d1ac91d8 3470 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3471 break;
3472 }
3473 case KVM_GET_XCRS: {
d1ac91d8 3474 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3475 r = -ENOMEM;
d1ac91d8 3476 if (!u.xcrs)
2d5b5a66
SY		 3477 break;
3478
d1ac91d8 3479 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3480
3481 r = -EFAULT;
d1ac91d8 3482 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3483 sizeof(struct kvm_xcrs)))
3484 break;
3485 r = 0;
3486 break;
3487 }
3488 case KVM_SET_XCRS: {
ff5c2c03 3489 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3490 if (IS_ERR(u.xcrs))
3491 return PTR_ERR(u.xcrs);
2d5b5a66 3492
d1ac91d8 3493 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3494 break;
3495 }
92a1f12d
JR		 3496 case KVM_SET_TSC_KHZ: {
3497 u32 user_tsc_khz;
3498
3499 r = -EINVAL;
92a1f12d
JR		 3500 user_tsc_khz = (u32)arg;
3501
3502 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3503 goto out;
3504
cc578287
ZA		 3505 if (user_tsc_khz == 0)
3506 user_tsc_khz = tsc_khz;
3507
381d585c
HZ		 3508 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3509 r = 0;
92a1f12d 3510
92a1f12d
JR		 3511 goto out;
3512 }
3513 case KVM_GET_TSC_KHZ: {
cc578287 3514 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3515 goto out;
3516 }
1c0b28c2
EM		 3517 case KVM_KVMCLOCK_CTRL: {
3518 r = kvm_set_guest_paused(vcpu);
3519 goto out;
3520 }
5c919412
AS		 3521 case KVM_ENABLE_CAP: {
3522 struct kvm_enable_cap cap;
3523
3524 r = -EFAULT;
3525 if (copy_from_user(&cap, argp, sizeof(cap)))
3526 goto out;
3527 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3528 break;
3529 }
313a3dc7
CO		 3530 default:
3531 r = -EINVAL;
3532 }
3533out:
d1ac91d8 3534 kfree(u.buffer);
313a3dc7
CO		 3535 return r;
3536}
3537
5b1c1493
CO		 3538int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3539{
3540 return VM_FAULT_SIGBUS;
3541}
3542
1fe779f8
CO		 3543static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3544{
3545 int ret;
3546
3547 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3548 return -EINVAL;
1fe779f8
CO		 3549 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3550 return ret;
3551}
3552
b927a3ce
SY		 3553static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3554 u64 ident_addr)
3555{
3556 kvm->arch.ept_identity_map_addr = ident_addr;
3557 return 0;
3558}
3559
1fe779f8
CO		 3560static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3561 u32 kvm_nr_mmu_pages)
3562{
3563 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3564 return -EINVAL;
3565
79fac95e 3566 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3567
3568 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3569 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3570
79fac95e 3571 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3572 return 0;
3573}
3574
3575static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3576{
39de71ec 3577 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3578}
3579
1fe779f8
CO		 3580static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3581{
3582 int r;
3583
3584 r = 0;
3585 switch (chip->chip_id) {
3586 case KVM_IRQCHIP_PIC_MASTER:
3587 memcpy(&chip->chip.pic,
3588 &pic_irqchip(kvm)->pics[0],
3589 sizeof(struct kvm_pic_state));
3590 break;
3591 case KVM_IRQCHIP_PIC_SLAVE:
3592 memcpy(&chip->chip.pic,
3593 &pic_irqchip(kvm)->pics[1],
3594 sizeof(struct kvm_pic_state));
3595 break;
3596 case KVM_IRQCHIP_IOAPIC:
eba0226b 3597 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3598 break;
3599 default:
3600 r = -EINVAL;
3601 break;
3602 }
3603 return r;
3604}
3605
3606static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3607{
3608 int r;
3609
3610 r = 0;
3611 switch (chip->chip_id) {
3612 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3613 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3614 memcpy(&pic_irqchip(kvm)->pics[0],
3615 &chip->chip.pic,
3616 sizeof(struct kvm_pic_state));
f4f51050 3617 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3618 break;
3619 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3620 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3621 memcpy(&pic_irqchip(kvm)->pics[1],
3622 &chip->chip.pic,
3623 sizeof(struct kvm_pic_state));
f4f51050 3624 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3625 break;
3626 case KVM_IRQCHIP_IOAPIC:
eba0226b 3627 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3628 break;
3629 default:
3630 r = -EINVAL;
3631 break;
3632 }
3633 kvm_pic_update_irq(pic_irqchip(kvm));
3634 return r;
3635}
3636
e0f63cb9
SY		 3637static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3638{
34f3941c
RK		 3639 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3640
3641 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3642
3643 mutex_lock(&kps->lock);
3644 memcpy(ps, &kps->channels, sizeof(*ps));
3645 mutex_unlock(&kps->lock);
2da29bcc 3646 return 0;
e0f63cb9
SY		 3647}
3648
3649static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3650{
0185604c 3651 int i;
09edea72
RK		 3652 struct kvm_pit *pit = kvm->arch.vpit;
3653
3654 mutex_lock(&pit->pit_state.lock);
34f3941c 3655 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3656 for (i = 0; i < 3; i++)
09edea72
RK		 3657 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3658 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3659 return 0;
e9f42757
BK		 3660}
3661
3662static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3663{
e9f42757
BK		 3664 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3665 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3666 sizeof(ps->channels));
3667 ps->flags = kvm->arch.vpit->pit_state.flags;
3668 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3669 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3670 return 0;
e9f42757
BK		 3671}
3672
3673static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3674{
2da29bcc 3675 int start = 0;
0185604c 3676 int i;
e9f42757 3677 u32 prev_legacy, cur_legacy;
09edea72
RK		 3678 struct kvm_pit *pit = kvm->arch.vpit;
3679
3680 mutex_lock(&pit->pit_state.lock);
3681 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3682 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3683 if (!prev_legacy && cur_legacy)
3684 start = 1;
09edea72
RK		 3685 memcpy(&pit->pit_state.channels, &ps->channels,
3686 sizeof(pit->pit_state.channels));
3687 pit->pit_state.flags = ps->flags;
0185604c 3688 for (i = 0; i < 3; i++)
09edea72 3689 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3690 start && i == 0);
09edea72 3691 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3692 return 0;
e0f63cb9
SY		 3693}
3694
52d939a0
MT		 3695static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3696 struct kvm_reinject_control *control)
3697{
71474e2f
RK		 3698 struct kvm_pit *pit = kvm->arch.vpit;
3699
3700 if (!pit)
52d939a0 3701 return -ENXIO;
b39c90b6 3702
71474e2f
RK		 3703 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3704 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3705 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3706 */
3707 mutex_lock(&pit->pit_state.lock);
3708 kvm_pit_set_reinject(pit, control->pit_reinject);
3709 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3710
52d939a0
MT		 3711 return 0;
3712}
3713
95d4c16c 3714/**
60c34612
TY		 3715 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3716 * @kvm: kvm instance
3717 * @log: slot id and address to which we copy the log
95d4c16c 3718 *
e108ff2f
PB		 3719 * Steps 1-4 below provide general overview of dirty page logging. See
3720 * kvm_get_dirty_log_protect() function description for additional details.
3721 *
3722 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3723 * always flush the TLB (step 4) even if previous step failed and the dirty
3724 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3725 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3726 * writes will be marked dirty for next log read.
95d4c16c 3727 *
60c34612
TY		 3728 * 1. Take a snapshot of the bit and clear it if needed.
3729 * 2. Write protect the corresponding page.
e108ff2f
PB		 3730 * 3. Copy the snapshot to the userspace.
3731 * 4. Flush TLB's if needed.
5bb064dc 3732 */
60c34612 3733int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3734{
60c34612 3735 bool is_dirty = false;
e108ff2f 3736 int r;
5bb064dc 3737
79fac95e 3738 mutex_lock(&kvm->slots_lock);
5bb064dc 3739
88178fd4
KH		 3740 /*
3741 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3742 */
3743 if (kvm_x86_ops->flush_log_dirty)
3744 kvm_x86_ops->flush_log_dirty(kvm);
3745
e108ff2f 3746 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3747
3748 /*
3749 * All the TLBs can be flushed out of mmu lock, see the comments in
3750 * kvm_mmu_slot_remove_write_access().
3751 */
e108ff2f 3752 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3753 if (is_dirty)
3754 kvm_flush_remote_tlbs(kvm);
3755
79fac95e 3756 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3757 return r;
3758}
3759
aa2fbe6d
YZ		 3760int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3761 bool line_status)
23d43cf9
CD		 3762{
3763 if (!irqchip_in_kernel(kvm))
3764 return -ENXIO;
3765
3766 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3767 irq_event->irq, irq_event->level,
3768 line_status);
23d43cf9
CD		 3769 return 0;
3770}
3771
90de4a18
NA		 3772static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3773 struct kvm_enable_cap *cap)
3774{
3775 int r;
3776
3777 if (cap->flags)
3778 return -EINVAL;
3779
3780 switch (cap->cap) {
3781 case KVM_CAP_DISABLE_QUIRKS:
3782 kvm->arch.disabled_quirks = cap->args[0];
3783 r = 0;
3784 break;
49df6397
SR		 3785 case KVM_CAP_SPLIT_IRQCHIP: {
3786 mutex_lock(&kvm->lock);
b053b2ae
SR		 3787 r = -EINVAL;
3788 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3789 goto split_irqchip_unlock;
49df6397
SR		 3790 r = -EEXIST;
3791 if (irqchip_in_kernel(kvm))
3792 goto split_irqchip_unlock;
557abc40 3793 if (kvm->created_vcpus)
49df6397
SR		 3794 goto split_irqchip_unlock;
3795 r = kvm_setup_empty_irq_routing(kvm);
3796 if (r)
3797 goto split_irqchip_unlock;
3798 /* Pairs with irqchip_in_kernel. */
3799 smp_wmb();
3800 kvm->arch.irqchip_split = true;
b053b2ae 3801 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3802 r = 0;
3803split_irqchip_unlock:
3804 mutex_unlock(&kvm->lock);
3805 break;
3806 }
37131313
RK		 3807 case KVM_CAP_X2APIC_API:
3808 r = -EINVAL;
3809 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3810 break;
3811
3812 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3813 kvm->arch.x2apic_format = true;
3814
3815 r = 0;
3816 break;
90de4a18
NA		 3817 default:
3818 r = -EINVAL;
3819 break;
3820 }
3821 return r;
3822}
3823
1fe779f8
CO		 3824long kvm_arch_vm_ioctl(struct file *filp,
3825 unsigned int ioctl, unsigned long arg)
3826{
3827 struct kvm *kvm = filp->private_data;
3828 void __user *argp = (void __user *)arg;
367e1319 3829 int r = -ENOTTY;
f0d66275
DH		 3830 /*
3831 * This union makes it completely explicit to gcc-3.x
3832 * that these two variables' stack usage should be
3833 * combined, not added together.
3834 */
3835 union {
3836 struct kvm_pit_state ps;
e9f42757 3837 struct kvm_pit_state2 ps2;
c5ff41ce 3838 struct kvm_pit_config pit_config;
f0d66275 3839 } u;
1fe779f8
CO		 3840
3841 switch (ioctl) {
3842 case KVM_SET_TSS_ADDR:
3843 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3844 break;
b927a3ce
SY		 3845 case KVM_SET_IDENTITY_MAP_ADDR: {
3846 u64 ident_addr;
3847
3848 r = -EFAULT;
3849 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3850 goto out;
3851 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3852 break;
3853 }
1fe779f8
CO		 3854 case KVM_SET_NR_MMU_PAGES:
3855 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3856 break;
3857 case KVM_GET_NR_MMU_PAGES:
3858 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3859 break;
3ddea128
MT		 3860 case KVM_CREATE_IRQCHIP: {
3861 struct kvm_pic *vpic;
3862
3863 mutex_lock(&kvm->lock);
3864 r = -EEXIST;
3865 if (kvm->arch.vpic)
3866 goto create_irqchip_unlock;
3e515705 3867 r = -EINVAL;
557abc40 3868 if (kvm->created_vcpus)
3e515705 3869 goto create_irqchip_unlock;
1fe779f8 3870 r = -ENOMEM;
3ddea128
MT		 3871 vpic = kvm_create_pic(kvm);
3872 if (vpic) {
1fe779f8
CO		 3873 r = kvm_ioapic_init(kvm);
3874 if (r) {
175504cd 3875 mutex_lock(&kvm->slots_lock);
71ba994c 3876 kvm_destroy_pic(vpic);
175504cd 3877 mutex_unlock(&kvm->slots_lock);
3ddea128 3878 goto create_irqchip_unlock;
1fe779f8
CO		 3879 }
3880 } else
3ddea128 3881 goto create_irqchip_unlock;
399ec807
AK		 3882 r = kvm_setup_default_irq_routing(kvm);
3883 if (r) {
175504cd 3884 mutex_lock(&kvm->slots_lock);
3ddea128 3885 mutex_lock(&kvm->irq_lock);
72bb2fcd 3886 kvm_ioapic_destroy(kvm);
71ba994c 3887 kvm_destroy_pic(vpic);
3ddea128 3888 mutex_unlock(&kvm->irq_lock);
175504cd 3889 mutex_unlock(&kvm->slots_lock);
71ba994c 3890 goto create_irqchip_unlock;
399ec807 3891 }
71ba994c
PB		 3892 /* Write kvm->irq_routing before kvm->arch.vpic. */
3893 smp_wmb();
3894 kvm->arch.vpic = vpic;
3ddea128
MT		 3895 create_irqchip_unlock:
3896 mutex_unlock(&kvm->lock);
1fe779f8 3897 break;
3ddea128 3898 }
7837699f 3899 case KVM_CREATE_PIT:
c5ff41ce
JK		 3900 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3901 goto create_pit;
3902 case KVM_CREATE_PIT2:
3903 r = -EFAULT;
3904 if (copy_from_user(&u.pit_config, argp,
3905 sizeof(struct kvm_pit_config)))
3906 goto out;
3907 create_pit:
250715a6 3908 mutex_lock(&kvm->lock);
269e05e4
AK		 3909 r = -EEXIST;
3910 if (kvm->arch.vpit)
3911 goto create_pit_unlock;
7837699f 3912 r = -ENOMEM;
c5ff41ce 3913 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3914 if (kvm->arch.vpit)
3915 r = 0;
269e05e4 3916 create_pit_unlock:
250715a6 3917 mutex_unlock(&kvm->lock);
7837699f 3918 break;
1fe779f8
CO		 3919 case KVM_GET_IRQCHIP: {
3920 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3921 struct kvm_irqchip *chip;
1fe779f8 3922
ff5c2c03
SL		 3923 chip = memdup_user(argp, sizeof(*chip));
3924 if (IS_ERR(chip)) {
3925 r = PTR_ERR(chip);
1fe779f8 3926 goto out;
ff5c2c03
SL		 3927 }
3928
1fe779f8 3929 r = -ENXIO;
49df6397 3930 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3931 goto get_irqchip_out;
3932 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3933 if (r)
f0d66275 3934 goto get_irqchip_out;
1fe779f8 3935 r = -EFAULT;
f0d66275
DH		 3936 if (copy_to_user(argp, chip, sizeof *chip))
3937 goto get_irqchip_out;
1fe779f8 3938 r = 0;
f0d66275
DH		 3939 get_irqchip_out:
3940 kfree(chip);
1fe779f8
CO		 3941 break;
3942 }
3943 case KVM_SET_IRQCHIP: {
3944 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3945 struct kvm_irqchip *chip;
1fe779f8 3946
ff5c2c03
SL		 3947 chip = memdup_user(argp, sizeof(*chip));
3948 if (IS_ERR(chip)) {
3949 r = PTR_ERR(chip);
1fe779f8 3950 goto out;
ff5c2c03
SL		 3951 }
3952
1fe779f8 3953 r = -ENXIO;
49df6397 3954 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3955 goto set_irqchip_out;
3956 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3957 if (r)
f0d66275 3958 goto set_irqchip_out;
1fe779f8 3959 r = 0;
f0d66275
DH		 3960 set_irqchip_out:
3961 kfree(chip);
1fe779f8
CO		 3962 break;
3963 }
e0f63cb9 3964 case KVM_GET_PIT: {
e0f63cb9 3965 r = -EFAULT;
f0d66275 3966 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3967 goto out;
3968 r = -ENXIO;
3969 if (!kvm->arch.vpit)
3970 goto out;
f0d66275 3971 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3972 if (r)
3973 goto out;
3974 r = -EFAULT;
f0d66275 3975 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3976 goto out;
3977 r = 0;
3978 break;
3979 }
3980 case KVM_SET_PIT: {
e0f63cb9 3981 r = -EFAULT;
f0d66275 3982 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3983 goto out;
3984 r = -ENXIO;
3985 if (!kvm->arch.vpit)
3986 goto out;
f0d66275 3987 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3988 break;
3989 }
e9f42757
BK		 3990 case KVM_GET_PIT2: {
3991 r = -ENXIO;
3992 if (!kvm->arch.vpit)
3993 goto out;
3994 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3995 if (r)
3996 goto out;
3997 r = -EFAULT;
3998 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3999 goto out;
4000 r = 0;
4001 break;
4002 }
4003 case KVM_SET_PIT2: {
4004 r = -EFAULT;
4005 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4006 goto out;
4007 r = -ENXIO;
4008 if (!kvm->arch.vpit)
4009 goto out;
4010 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4011 break;
4012 }
52d939a0
MT		 4013 case KVM_REINJECT_CONTROL: {
4014 struct kvm_reinject_control control;
4015 r = -EFAULT;
4016 if (copy_from_user(&control, argp, sizeof(control)))
4017 goto out;
4018 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4019 break;
4020 }
d71ba788
PB		 4021 case KVM_SET_BOOT_CPU_ID:
4022 r = 0;
4023 mutex_lock(&kvm->lock);
557abc40 4024 if (kvm->created_vcpus)
d71ba788
PB		 4025 r = -EBUSY;
4026 else
4027 kvm->arch.bsp_vcpu_id = arg;
4028 mutex_unlock(&kvm->lock);
4029 break;
ffde22ac
ES		 4030 case KVM_XEN_HVM_CONFIG: {
4031 r = -EFAULT;
4032 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4033 sizeof(struct kvm_xen_hvm_config)))
4034 goto out;
4035 r = -EINVAL;
4036 if (kvm->arch.xen_hvm_config.flags)
4037 goto out;
4038 r = 0;
4039 break;
4040 }
afbcf7ab 4041 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4042 struct kvm_clock_data user_ns;
4043 u64 now_ns;
4044 s64 delta;
4045
4046 r = -EFAULT;
4047 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4048 goto out;
4049
4050 r = -EINVAL;
4051 if (user_ns.flags)
4052 goto out;
4053
4054 r = 0;
395c6b0a 4055 local_irq_disable();
759379dd 4056 now_ns = get_kernel_ns();
afbcf7ab 4057 delta = user_ns.clock - now_ns;
395c6b0a 4058 local_irq_enable();
afbcf7ab 4059 kvm->arch.kvmclock_offset = delta;
2e762ff7 4060 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4061 break;
4062 }
4063 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4064 struct kvm_clock_data user_ns;
4065 u64 now_ns;
4066
395c6b0a 4067 local_irq_disable();
759379dd 4068 now_ns = get_kernel_ns();
afbcf7ab 4069 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4070 local_irq_enable();
afbcf7ab 4071 user_ns.flags = 0;
97e69aa6 4072 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4073
4074 r = -EFAULT;
4075 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4076 goto out;
4077 r = 0;
4078 break;
4079 }
90de4a18
NA		 4080 case KVM_ENABLE_CAP: {
4081 struct kvm_enable_cap cap;
afbcf7ab 4082
90de4a18
NA		 4083 r = -EFAULT;
4084 if (copy_from_user(&cap, argp, sizeof(cap)))
4085 goto out;
4086 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4087 break;
4088 }
1fe779f8 4089 default:
c274e03a 4090 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4091 }
4092out:
4093 return r;
4094}
4095
a16b043c 4096static void kvm_init_msr_list(void)
043405e1
CO		 4097{
4098 u32 dummy[2];
4099 unsigned i, j;
4100
62ef68bb 4101 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4102 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4103 continue;
93c4adc7
PB		 4104
4105 /*
4106 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4107 * to the guests in some cases.
93c4adc7
PB		 4108 */
4109 switch (msrs_to_save[i]) {
4110 case MSR_IA32_BNDCFGS:
4111 if (!kvm_x86_ops->mpx_supported())
4112 continue;
4113 break;
9dbe6cf9
PB		 4114 case MSR_TSC_AUX:
4115 if (!kvm_x86_ops->rdtscp_supported())
4116 continue;
4117 break;
93c4adc7
PB		 4118 default:
4119 break;
4120 }
4121
043405e1
CO		 4122 if (j < i)
4123 msrs_to_save[j] = msrs_to_save[i];
4124 j++;
4125 }
4126 num_msrs_to_save = j;
62ef68bb
PB		 4127
4128 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4129 switch (emulated_msrs[i]) {
6d396b55
PB		 4130 case MSR_IA32_SMBASE:
4131 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4132 continue;
4133 break;
62ef68bb
PB		 4134 default:
4135 break;
4136 }
4137
4138 if (j < i)
4139 emulated_msrs[j] = emulated_msrs[i];
4140 j++;
4141 }
4142 num_emulated_msrs = j;
043405e1
CO		 4143}
4144
bda9020e
MT		 4145static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4146 const void *v)
bbd9b64e 4147{
70252a10
AK		 4148 int handled = 0;
4149 int n;
4150
4151 do {
4152 n = min(len, 8);
bce87cce 4153 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4154 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4155 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4156 break;
4157 handled += n;
4158 addr += n;
4159 len -= n;
4160 v += n;
4161 } while (len);
bbd9b64e 4162
70252a10 4163 return handled;
bbd9b64e
CO		 4164}
4165
bda9020e 4166static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4167{
70252a10
AK		 4168 int handled = 0;
4169 int n;
4170
4171 do {
4172 n = min(len, 8);
bce87cce 4173 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4174 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4175 addr, n, v))
4176 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4177 break;
4178 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4179 handled += n;
4180 addr += n;
4181 len -= n;
4182 v += n;
4183 } while (len);
bbd9b64e 4184
70252a10 4185 return handled;
bbd9b64e
CO		 4186}
4187
2dafc6c2
GN		 4188static void kvm_set_segment(struct kvm_vcpu *vcpu,
4189 struct kvm_segment *var, int seg)
4190{
4191 kvm_x86_ops->set_segment(vcpu, var, seg);
4192}
4193
4194void kvm_get_segment(struct kvm_vcpu *vcpu,
4195 struct kvm_segment *var, int seg)
4196{
4197 kvm_x86_ops->get_segment(vcpu, var, seg);
4198}
4199
54987b7a
PB		 4200gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4201 struct x86_exception *exception)
02f59dc9
JR		 4202{
4203 gpa_t t_gpa;
02f59dc9
JR		 4204
4205 BUG_ON(!mmu_is_nested(vcpu));
4206
4207 /* NPT walks are always user-walks */
4208 access |= PFERR_USER_MASK;
54987b7a 4209 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4210
4211 return t_gpa;
4212}
4213
ab9ae313
AK		 4214gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4215 struct x86_exception *exception)
1871c602
GN		 4216{
4217 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4218 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4219}
4220
ab9ae313
AK		 4221 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4222 struct x86_exception *exception)
1871c602
GN		 4223{
4224 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4225 access |= PFERR_FETCH_MASK;
ab9ae313 4226 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4227}
4228
ab9ae313
AK		 4229gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4230 struct x86_exception *exception)
1871c602
GN		 4231{
4232 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4233 access |= PFERR_WRITE_MASK;
ab9ae313 4234 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4235}
4236
4237/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4238gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4239 struct x86_exception *exception)
1871c602 4240{
ab9ae313 4241 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4242}
4243
4244static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4245 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4246 struct x86_exception *exception)
bbd9b64e
CO		 4247{
4248 void *data = val;
10589a46 4249 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4250
4251 while (bytes) {
14dfe855 4252 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4253 exception);
bbd9b64e 4254 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4255 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4256 int ret;
4257
bcc55cba 4258 if (gpa == UNMAPPED_GVA)
ab9ae313 4259 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4260 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4261 offset, toread);
10589a46 4262 if (ret < 0) {
c3cd7ffa 4263 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4264 goto out;
4265 }
bbd9b64e 4266
77c2002e
IE		 4267 bytes -= toread;
4268 data += toread;
4269 addr += toread;
bbd9b64e 4270 }
10589a46 4271out:
10589a46 4272 return r;
bbd9b64e 4273}
77c2002e 4274
1871c602 4275/* used for instruction fetching */
0f65dd70
AK		 4276static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4277 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4278 struct x86_exception *exception)
1871c602 4279{
0f65dd70 4280 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4281 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4282 unsigned offset;
4283 int ret;
0f65dd70 4284
44583cba
PB		 4285 /* Inline kvm_read_guest_virt_helper for speed. */
4286 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4287 exception);
4288 if (unlikely(gpa == UNMAPPED_GVA))
4289 return X86EMUL_PROPAGATE_FAULT;
4290
4291 offset = addr & (PAGE_SIZE-1);
4292 if (WARN_ON(offset + bytes > PAGE_SIZE))
4293 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4294 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4295 offset, bytes);
44583cba
PB		 4296 if (unlikely(ret < 0))
4297 return X86EMUL_IO_NEEDED;
4298
4299 return X86EMUL_CONTINUE;
1871c602
GN		 4300}
4301
064aea77 4302int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4303 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4304 struct x86_exception *exception)
1871c602 4305{
0f65dd70 4306 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4307 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4308
1871c602 4309 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4310 exception);
1871c602 4311}
064aea77 4312EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4313
0f65dd70
AK		 4314static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4315 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4316 struct x86_exception *exception)
1871c602 4317{
0f65dd70 4318 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4319 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4320}
4321
7a036a6f
RK		 4322static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4323 unsigned long addr, void *val, unsigned int bytes)
4324{
4325 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4326 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4327
4328 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4329}
4330
6a4d7550 4331int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4332 gva_t addr, void *val,
2dafc6c2 4333 unsigned int bytes,
bcc55cba 4334 struct x86_exception *exception)
77c2002e 4335{
0f65dd70 4336 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4337 void *data = val;
4338 int r = X86EMUL_CONTINUE;
4339
4340 while (bytes) {
14dfe855
JR		 4341 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4342 PFERR_WRITE_MASK,
ab9ae313 4343 exception);
77c2002e
IE		 4344 unsigned offset = addr & (PAGE_SIZE-1);
4345 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4346 int ret;
4347
bcc55cba 4348 if (gpa == UNMAPPED_GVA)
ab9ae313 4349 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4350 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4351 if (ret < 0) {
c3cd7ffa 4352 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4353 goto out;
4354 }
4355
4356 bytes -= towrite;
4357 data += towrite;
4358 addr += towrite;
4359 }
4360out:
4361 return r;
4362}
6a4d7550 4363EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4364
af7cc7d1
XG		 4365static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4366 gpa_t *gpa, struct x86_exception *exception,
4367 bool write)
4368{
97d64b78
AK		 4369 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4370 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4371
be94f6b7
HH		 4372 /*
4373 * currently PKRU is only applied to ept enabled guest so
4374 * there is no pkey in EPT page table for L1 guest or EPT
4375 * shadow page table for L2 guest.
4376 */
97d64b78 4377 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4378 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4379 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4380 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4381 (gva & (PAGE_SIZE - 1));
4f022648 4382 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4383 return 1;
4384 }
4385
af7cc7d1
XG		 4386 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4387
4388 if (*gpa == UNMAPPED_GVA)
4389 return -1;
4390
4391 /* For APIC access vmexit */
4392 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4393 return 1;
4394
4f022648
XG		 4395 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4396 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4397 return 1;
4f022648 4398 }
bebb106a 4399
af7cc7d1
XG		 4400 return 0;
4401}
4402
3200f405 4403int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4404 const void *val, int bytes)
bbd9b64e
CO		 4405{
4406 int ret;
4407
54bf36aa 4408 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4409 if (ret < 0)
bbd9b64e 4410 return 0;
0eb05bf2 4411 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4412 return 1;
4413}
4414
77d197b2
XG		 4415struct read_write_emulator_ops {
4416 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4417 int bytes);
4418 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4419 void *val, int bytes);
4420 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4421 int bytes, void *val);
4422 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4423 void *val, int bytes);
4424 bool write;
4425};
4426
4427static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4428{
4429 if (vcpu->mmio_read_completed) {
77d197b2 4430 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4431 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4432 vcpu->mmio_read_completed = 0;
4433 return 1;
4434 }
4435
4436 return 0;
4437}
4438
4439static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4440 void *val, int bytes)
4441{
54bf36aa 4442 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4443}
4444
4445static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4446 void *val, int bytes)
4447{
4448 return emulator_write_phys(vcpu, gpa, val, bytes);
4449}
4450
4451static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4452{
4453 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4454 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4455}
4456
4457static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4458 void *val, int bytes)
4459{
4460 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4461 return X86EMUL_IO_NEEDED;
4462}
4463
4464static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4465 void *val, int bytes)
4466{
f78146b0
AK		 4467 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4468
87da7e66 4469 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4470 return X86EMUL_CONTINUE;
4471}
4472
0fbe9b0b 4473static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4474 .read_write_prepare = read_prepare,
4475 .read_write_emulate = read_emulate,
4476 .read_write_mmio = vcpu_mmio_read,
4477 .read_write_exit_mmio = read_exit_mmio,
4478};
4479
0fbe9b0b 4480static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4481 .read_write_emulate = write_emulate,
4482 .read_write_mmio = write_mmio,
4483 .read_write_exit_mmio = write_exit_mmio,
4484 .write = true,
4485};
4486
22388a3c
XG		 4487static int emulator_read_write_onepage(unsigned long addr, void *val,
4488 unsigned int bytes,
4489 struct x86_exception *exception,
4490 struct kvm_vcpu *vcpu,
0fbe9b0b 4491 const struct read_write_emulator_ops *ops)
bbd9b64e 4492{
af7cc7d1
XG		 4493 gpa_t gpa;
4494 int handled, ret;
22388a3c 4495 bool write = ops->write;
f78146b0 4496 struct kvm_mmio_fragment *frag;
10589a46 4497
22388a3c 4498 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4499
af7cc7d1 4500 if (ret < 0)
bbd9b64e 4501 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4502
4503 /* For APIC access vmexit */
af7cc7d1 4504 if (ret)
bbd9b64e
CO		 4505 goto mmio;
4506
22388a3c 4507 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4508 return X86EMUL_CONTINUE;
4509
4510mmio:
4511 /*
4512 * Is this MMIO handled locally?
4513 */
22388a3c 4514 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4515 if (handled == bytes)
bbd9b64e 4516 return X86EMUL_CONTINUE;
bbd9b64e 4517
70252a10
AK		 4518 gpa += handled;
4519 bytes -= handled;
4520 val += handled;
4521
87da7e66
XG		 4522 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4523 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4524 frag->gpa = gpa;
4525 frag->data = val;
4526 frag->len = bytes;
f78146b0 4527 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4528}
4529
52eb5a6d
XL		 4530static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4531 unsigned long addr,
22388a3c
XG		 4532 void *val, unsigned int bytes,
4533 struct x86_exception *exception,
0fbe9b0b 4534 const struct read_write_emulator_ops *ops)
bbd9b64e 4535{
0f65dd70 4536 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4537 gpa_t gpa;
4538 int rc;
4539
4540 if (ops->read_write_prepare &&
4541 ops->read_write_prepare(vcpu, val, bytes))
4542 return X86EMUL_CONTINUE;
4543
4544 vcpu->mmio_nr_fragments = 0;
0f65dd70 4545
bbd9b64e
CO		 4546 /* Crossing a page boundary? */
4547 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4548 int now;
bbd9b64e
CO		 4549
4550 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4551 rc = emulator_read_write_onepage(addr, val, now, exception,
4552 vcpu, ops);
4553
bbd9b64e
CO		 4554 if (rc != X86EMUL_CONTINUE)
4555 return rc;
4556 addr += now;
bac15531
NA		 4557 if (ctxt->mode != X86EMUL_MODE_PROT64)
4558 addr = (u32)addr;
bbd9b64e
CO		 4559 val += now;
4560 bytes -= now;
4561 }
22388a3c 4562
f78146b0
AK		 4563 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4564 vcpu, ops);
4565 if (rc != X86EMUL_CONTINUE)
4566 return rc;
4567
4568 if (!vcpu->mmio_nr_fragments)
4569 return rc;
4570
4571 gpa = vcpu->mmio_fragments[0].gpa;
4572
4573 vcpu->mmio_needed = 1;
4574 vcpu->mmio_cur_fragment = 0;
4575
87da7e66 4576 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4577 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4578 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4579 vcpu->run->mmio.phys_addr = gpa;
4580
4581 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4582}
4583
4584static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4585 unsigned long addr,
4586 void *val,
4587 unsigned int bytes,
4588 struct x86_exception *exception)
4589{
4590 return emulator_read_write(ctxt, addr, val, bytes,
4591 exception, &read_emultor);
4592}
4593
52eb5a6d 4594static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4595 unsigned long addr,
4596 const void *val,
4597 unsigned int bytes,
4598 struct x86_exception *exception)
4599{
4600 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4601 exception, &write_emultor);
bbd9b64e 4602}
bbd9b64e 4603
daea3e73
AK		 4604#define CMPXCHG_TYPE(t, ptr, old, new) \
4605 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4606
4607#ifdef CONFIG_X86_64
4608# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4609#else
4610# define CMPXCHG64(ptr, old, new) \
9749a6c0 4611 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4612#endif
4613
0f65dd70
AK		 4614static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4615 unsigned long addr,
bbd9b64e
CO		 4616 const void *old,
4617 const void *new,
4618 unsigned int bytes,
0f65dd70 4619 struct x86_exception *exception)
bbd9b64e 4620{
0f65dd70 4621 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4622 gpa_t gpa;
4623 struct page *page;
4624 char *kaddr;
4625 bool exchanged;
2bacc55c 4626
daea3e73
AK		 4627 /* guests cmpxchg8b have to be emulated atomically */
4628 if (bytes > 8 || (bytes & (bytes - 1)))
4629 goto emul_write;
10589a46 4630
daea3e73 4631 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4632
daea3e73
AK		 4633 if (gpa == UNMAPPED_GVA ||
4634 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4635 goto emul_write;
2bacc55c 4636
daea3e73
AK		 4637 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4638 goto emul_write;
72dc67a6 4639
54bf36aa 4640 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4641 if (is_error_page(page))
c19b8bd6 4642 goto emul_write;
72dc67a6 4643
8fd75e12 4644 kaddr = kmap_atomic(page);
daea3e73
AK		 4645 kaddr += offset_in_page(gpa);
4646 switch (bytes) {
4647 case 1:
4648 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4649 break;
4650 case 2:
4651 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4652 break;
4653 case 4:
4654 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4655 break;
4656 case 8:
4657 exchanged = CMPXCHG64(kaddr, old, new);
4658 break;
4659 default:
4660 BUG();
2bacc55c 4661 }
8fd75e12 4662 kunmap_atomic(kaddr);
daea3e73
AK		 4663 kvm_release_page_dirty(page);
4664
4665 if (!exchanged)
4666 return X86EMUL_CMPXCHG_FAILED;
4667
54bf36aa 4668 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4669 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4670
4671 return X86EMUL_CONTINUE;
4a5f48f6 4672
3200f405 4673emul_write:
daea3e73 4674 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4675
0f65dd70 4676 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4677}
4678
cf8f70bf
GN		 4679static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4680{
4681 /* TODO: String I/O for in kernel device */
4682 int r;
4683
4684 if (vcpu->arch.pio.in)
e32edf4f 4685 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4686 vcpu->arch.pio.size, pd);
4687 else
e32edf4f 4688 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4689 vcpu->arch.pio.port, vcpu->arch.pio.size,
4690 pd);
4691 return r;
4692}
4693
6f6fbe98
XG		 4694static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4695 unsigned short port, void *val,
4696 unsigned int count, bool in)
cf8f70bf 4697{
cf8f70bf 4698 vcpu->arch.pio.port = port;
6f6fbe98 4699 vcpu->arch.pio.in = in;
7972995b 4700 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4701 vcpu->arch.pio.size = size;
4702
4703 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4704 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4705 return 1;
4706 }
4707
4708 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4709 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4710 vcpu->run->io.size = size;
4711 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4712 vcpu->run->io.count = count;
4713 vcpu->run->io.port = port;
4714
4715 return 0;
4716}
4717
6f6fbe98
XG		 4718static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4719 int size, unsigned short port, void *val,
4720 unsigned int count)
cf8f70bf 4721{
ca1d4a9e 4722 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4723 int ret;
ca1d4a9e 4724
6f6fbe98
XG		 4725 if (vcpu->arch.pio.count)
4726 goto data_avail;
cf8f70bf 4727
6f6fbe98
XG		 4728 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4729 if (ret) {
4730data_avail:
4731 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4732 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4733 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4734 return 1;
4735 }
4736
cf8f70bf
GN		 4737 return 0;
4738}
4739
6f6fbe98
XG		 4740static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4741 int size, unsigned short port,
4742 const void *val, unsigned int count)
4743{
4744 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4745
4746 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4747 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4748 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4749}
4750
bbd9b64e
CO		 4751static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4752{
4753 return kvm_x86_ops->get_segment_base(vcpu, seg);
4754}
4755
3cb16fe7 4756static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4757{
3cb16fe7 4758 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4759}
4760
5cb56059 4761int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4762{
4763 if (!need_emulate_wbinvd(vcpu))
4764 return X86EMUL_CONTINUE;
4765
4766 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4767 int cpu = get_cpu();
4768
4769 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4770 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4771 wbinvd_ipi, NULL, 1);
2eec7343 4772 put_cpu();
f5f48ee1 4773 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4774 } else
4775 wbinvd();
f5f48ee1
SY		 4776 return X86EMUL_CONTINUE;
4777}
5cb56059
JS		 4778
4779int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4780{
4781 kvm_x86_ops->skip_emulated_instruction(vcpu);
4782 return kvm_emulate_wbinvd_noskip(vcpu);
4783}
f5f48ee1
SY		 4784EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4785
5cb56059
JS		 4786
4787
bcaf5cc5
AK		 4788static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4789{
5cb56059 4790 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4791}
4792
52eb5a6d
XL		 4793static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4794 unsigned long *dest)
bbd9b64e 4795{
16f8a6f9 4796 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4797}
4798
52eb5a6d
XL		 4799static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4800 unsigned long value)
bbd9b64e 4801{
338dbc97 4802
717746e3 4803 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4804}
4805
52a46617 4806static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4807{
52a46617 4808 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4809}
4810
717746e3 4811static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4812{
717746e3 4813 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4814 unsigned long value;
4815
4816 switch (cr) {
4817 case 0:
4818 value = kvm_read_cr0(vcpu);
4819 break;
4820 case 2:
4821 value = vcpu->arch.cr2;
4822 break;
4823 case 3:
9f8fe504 4824 value = kvm_read_cr3(vcpu);
52a46617
GN		 4825 break;
4826 case 4:
4827 value = kvm_read_cr4(vcpu);
4828 break;
4829 case 8:
4830 value = kvm_get_cr8(vcpu);
4831 break;
4832 default:
a737f256 4833 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4834 return 0;
4835 }
4836
4837 return value;
4838}
4839
717746e3 4840static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4841{
717746e3 4842 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4843 int res = 0;
4844
52a46617
GN		 4845 switch (cr) {
4846 case 0:
49a9b07e 4847 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4848 break;
4849 case 2:
4850 vcpu->arch.cr2 = val;
4851 break;
4852 case 3:
2390218b 4853 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4854 break;
4855 case 4:
a83b29c6 4856 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4857 break;
4858 case 8:
eea1cff9 4859 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4860 break;
4861 default:
a737f256 4862 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4863 res = -1;
52a46617 4864 }
0f12244f
GN		 4865
4866 return res;
52a46617
GN		 4867}
4868
717746e3 4869static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4870{
717746e3 4871 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4872}
4873
4bff1e86 4874static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4875{
4bff1e86 4876 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4877}
4878
4bff1e86 4879static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4880{
4bff1e86 4881 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4882}
4883
1ac9d0cf
AK		 4884static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4885{
4886 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4887}
4888
4889static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4890{
4891 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4892}
4893
4bff1e86
AK		 4894static unsigned long emulator_get_cached_segment_base(
4895 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4896{
4bff1e86 4897 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4898}
4899
1aa36616
AK		 4900static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4901 struct desc_struct *desc, u32 *base3,
4902 int seg)
2dafc6c2
GN		 4903{
4904 struct kvm_segment var;
4905
4bff1e86 4906 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4907 *selector = var.selector;
2dafc6c2 4908
378a8b09
GN		 4909 if (var.unusable) {
4910 memset(desc, 0, sizeof(*desc));
2dafc6c2 4911 return false;
378a8b09 4912 }
2dafc6c2
GN		 4913
4914 if (var.g)
4915 var.limit >>= 12;
4916 set_desc_limit(desc, var.limit);
4917 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4918#ifdef CONFIG_X86_64
4919 if (base3)
4920 *base3 = var.base >> 32;
4921#endif
2dafc6c2
GN		 4922 desc->type = var.type;
4923 desc->s = var.s;
4924 desc->dpl = var.dpl;
4925 desc->p = var.present;
4926 desc->avl = var.avl;
4927 desc->l = var.l;
4928 desc->d = var.db;
4929 desc->g = var.g;
4930
4931 return true;
4932}
4933
1aa36616
AK		 4934static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4935 struct desc_struct *desc, u32 base3,
4936 int seg)
2dafc6c2 4937{
4bff1e86 4938 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4939 struct kvm_segment var;
4940
1aa36616 4941 var.selector = selector;
2dafc6c2 4942 var.base = get_desc_base(desc);
5601d05b
GN		 4943#ifdef CONFIG_X86_64
4944 var.base |= ((u64)base3) << 32;
4945#endif
2dafc6c2
GN		 4946 var.limit = get_desc_limit(desc);
4947 if (desc->g)
4948 var.limit = (var.limit << 12) | 0xfff;
4949 var.type = desc->type;
2dafc6c2
GN		 4950 var.dpl = desc->dpl;
4951 var.db = desc->d;
4952 var.s = desc->s;
4953 var.l = desc->l;
4954 var.g = desc->g;
4955 var.avl = desc->avl;
4956 var.present = desc->p;
4957 var.unusable = !var.present;
4958 var.padding = 0;
4959
4960 kvm_set_segment(vcpu, &var, seg);
4961 return;
4962}
4963
717746e3
AK		 4964static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4965 u32 msr_index, u64 *pdata)
4966{
609e36d3
PB		 4967 struct msr_data msr;
4968 int r;
4969
4970 msr.index = msr_index;
4971 msr.host_initiated = false;
4972 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4973 if (r)
4974 return r;
4975
4976 *pdata = msr.data;
4977 return 0;
717746e3
AK		 4978}
4979
4980static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4981 u32 msr_index, u64 data)
4982{
8fe8ab46
WA		 4983 struct msr_data msr;
4984
4985 msr.data = data;
4986 msr.index = msr_index;
4987 msr.host_initiated = false;
4988 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4989}
4990
64d60670
PB		 4991static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4992{
4993 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4994
4995 return vcpu->arch.smbase;
4996}
4997
4998static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4999{
5000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5001
5002 vcpu->arch.smbase = smbase;
5003}
5004
67f4d428
NA		 5005static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5006 u32 pmc)
5007{
c6702c9d 5008 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5009}
5010
222d21aa
AK		 5011static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5012 u32 pmc, u64 *pdata)
5013{
c6702c9d 5014 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5015}
5016
6c3287f7
AK		 5017static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5018{
5019 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5020}
5021
5037f6f3
AK		 5022static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5023{
5024 preempt_disable();
5197b808 5025 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5026 /*
5027 * CR0.TS may reference the host fpu state, not the guest fpu state,
5028 * so it may be clear at this point.
5029 */
5030 clts();
5031}
5032
5033static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5034{
5035 preempt_enable();
5036}
5037
2953538e 5038static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5039 struct x86_instruction_info *info,
c4f035c6
AK		 5040 enum x86_intercept_stage stage)
5041{
2953538e 5042 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5043}
5044
0017f93a 5045static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5046 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5047{
0017f93a 5048 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5049}
5050
dd856efa
AK		 5051static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5052{
5053 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5054}
5055
5056static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5057{
5058 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5059}
5060
801806d9
NA		 5061static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5062{
5063 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5064}
5065
0225fb50 5066static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5067 .read_gpr = emulator_read_gpr,
5068 .write_gpr = emulator_write_gpr,
1871c602 5069 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5070 .write_std = kvm_write_guest_virt_system,
7a036a6f 5071 .read_phys = kvm_read_guest_phys_system,
1871c602 5072 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5073 .read_emulated = emulator_read_emulated,
5074 .write_emulated = emulator_write_emulated,
5075 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5076 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5077 .pio_in_emulated = emulator_pio_in_emulated,
5078 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5079 .get_segment = emulator_get_segment,
5080 .set_segment = emulator_set_segment,
5951c442 5081 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5082 .get_gdt = emulator_get_gdt,
160ce1f1 5083 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5084 .set_gdt = emulator_set_gdt,
5085 .set_idt = emulator_set_idt,
52a46617
GN		 5086 .get_cr = emulator_get_cr,
5087 .set_cr = emulator_set_cr,
9c537244 5088 .cpl = emulator_get_cpl,
35aa5375
GN		 5089 .get_dr = emulator_get_dr,
5090 .set_dr = emulator_set_dr,
64d60670
PB		 5091 .get_smbase = emulator_get_smbase,
5092 .set_smbase = emulator_set_smbase,
717746e3
AK		 5093 .set_msr = emulator_set_msr,
5094 .get_msr = emulator_get_msr,
67f4d428 5095 .check_pmc = emulator_check_pmc,
222d21aa 5096 .read_pmc = emulator_read_pmc,
6c3287f7 5097 .halt = emulator_halt,
bcaf5cc5 5098 .wbinvd = emulator_wbinvd,
d6aa1000 5099 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5100 .get_fpu = emulator_get_fpu,
5101 .put_fpu = emulator_put_fpu,
c4f035c6 5102 .intercept = emulator_intercept,
bdb42f5a 5103 .get_cpuid = emulator_get_cpuid,
801806d9 5104 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5105};
5106
95cb2295
GN		 5107static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5108{
37ccdcbe 5109 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5110 /*
5111 * an sti; sti; sequence only disable interrupts for the first
5112 * instruction. So, if the last instruction, be it emulated or
5113 * not, left the system with the INT_STI flag enabled, it
5114 * means that the last instruction is an sti. We should not
5115 * leave the flag on in this case. The same goes for mov ss
5116 */
37ccdcbe
PB		 5117 if (int_shadow & mask)
5118 mask = 0;
6addfc42 5119 if (unlikely(int_shadow || mask)) {
95cb2295 5120 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5121 if (!mask)
5122 kvm_make_request(KVM_REQ_EVENT, vcpu);
5123 }
95cb2295
GN		 5124}
5125
ef54bcfe 5126static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5127{
5128 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5129 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5130 return kvm_propagate_fault(vcpu, &ctxt->exception);
5131
5132 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5133 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5134 ctxt->exception.error_code);
54b8486f 5135 else
da9cb575 5136 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5137 return false;
54b8486f
GN		 5138}
5139
8ec4722d
MG		 5140static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5141{
adf52235 5142 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5143 int cs_db, cs_l;
5144
8ec4722d
MG		 5145 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5146
adf52235
TY		 5147 ctxt->eflags = kvm_get_rflags(vcpu);
5148 ctxt->eip = kvm_rip_read(vcpu);
5149 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5150 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5151 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5152 cs_db ? X86EMUL_MODE_PROT32 :
5153 X86EMUL_MODE_PROT16;
a584539b 5154 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5155 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5156 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5157 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5158
dd856efa 5159 init_decode_cache(ctxt);
7ae441ea 5160 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5161}
5162
71f9833b 5163int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5164{
9d74191a 5165 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5166 int ret;
5167
5168 init_emulate_ctxt(vcpu);
5169
9dac77fa
AK		 5170 ctxt->op_bytes = 2;
5171 ctxt->ad_bytes = 2;
5172 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5173 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5174
5175 if (ret != X86EMUL_CONTINUE)
5176 return EMULATE_FAIL;
5177
9dac77fa 5178 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5179 kvm_rip_write(vcpu, ctxt->eip);
5180 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5181
5182 if (irq == NMI_VECTOR)
7460fb4a 5183 vcpu->arch.nmi_pending = 0;
63995653
MG		 5184 else
5185 vcpu->arch.interrupt.pending = false;
5186
5187 return EMULATE_DONE;
5188}
5189EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5190
6d77dbfc
GN		 5191static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5192{
fc3a9157
JR		 5193 int r = EMULATE_DONE;
5194
6d77dbfc
GN		 5195 ++vcpu->stat.insn_emulation_fail;
5196 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5197 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5198 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5199 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5200 vcpu->run->internal.ndata = 0;
5201 r = EMULATE_FAIL;
5202 }
6d77dbfc 5203 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5204
5205 return r;
6d77dbfc
GN		 5206}
5207
93c05d3e 5208static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5209 bool write_fault_to_shadow_pgtable,
5210 int emulation_type)
a6f177ef 5211{
95b3cf69 5212 gpa_t gpa = cr2;
ba049e93 5213 kvm_pfn_t pfn;
a6f177ef 5214
991eebf9
GN		 5215 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5216 return false;
5217
95b3cf69
XG		 5218 if (!vcpu->arch.mmu.direct_map) {
5219 /*
5220 * Write permission should be allowed since only
5221 * write access need to be emulated.
5222 */
5223 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5224
95b3cf69
XG		 5225 /*
5226 * If the mapping is invalid in guest, let cpu retry
5227 * it to generate fault.
5228 */
5229 if (gpa == UNMAPPED_GVA)
5230 return true;
5231 }
a6f177ef 5232
8e3d9d06
XG		 5233 /*
5234 * Do not retry the unhandleable instruction if it faults on the
5235 * readonly host memory, otherwise it will goto a infinite loop:
5236 * retry instruction -> write #PF -> emulation fail -> retry
5237 * instruction -> ...
5238 */
5239 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5240
5241 /*
5242 * If the instruction failed on the error pfn, it can not be fixed,
5243 * report the error to userspace.
5244 */
5245 if (is_error_noslot_pfn(pfn))
5246 return false;
5247
5248 kvm_release_pfn_clean(pfn);
5249
5250 /* The instructions are well-emulated on direct mmu. */
5251 if (vcpu->arch.mmu.direct_map) {
5252 unsigned int indirect_shadow_pages;
5253
5254 spin_lock(&vcpu->kvm->mmu_lock);
5255 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5256 spin_unlock(&vcpu->kvm->mmu_lock);
5257
5258 if (indirect_shadow_pages)
5259 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5260
a6f177ef 5261 return true;
8e3d9d06 5262 }
a6f177ef 5263
95b3cf69
XG		 5264 /*
5265 * if emulation was due to access to shadowed page table
5266 * and it failed try to unshadow page and re-enter the
5267 * guest to let CPU execute the instruction.
5268 */
5269 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5270
5271 /*
5272 * If the access faults on its page table, it can not
5273 * be fixed by unprotecting shadow page and it should
5274 * be reported to userspace.
5275 */
5276 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5277}
5278
1cb3f3ae
XG		 5279static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5280 unsigned long cr2, int emulation_type)
5281{
5282 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5283 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5284
5285 last_retry_eip = vcpu->arch.last_retry_eip;
5286 last_retry_addr = vcpu->arch.last_retry_addr;
5287
5288 /*
5289 * If the emulation is caused by #PF and it is non-page_table
5290 * writing instruction, it means the VM-EXIT is caused by shadow
5291 * page protected, we can zap the shadow page and retry this
5292 * instruction directly.
5293 *
5294 * Note: if the guest uses a non-page-table modifying instruction
5295 * on the PDE that points to the instruction, then we will unmap
5296 * the instruction and go to an infinite loop. So, we cache the
5297 * last retried eip and the last fault address, if we meet the eip
5298 * and the address again, we can break out of the potential infinite
5299 * loop.
5300 */
5301 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5302
5303 if (!(emulation_type & EMULTYPE_RETRY))
5304 return false;
5305
5306 if (x86_page_table_writing_insn(ctxt))
5307 return false;
5308
5309 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5310 return false;
5311
5312 vcpu->arch.last_retry_eip = ctxt->eip;
5313 vcpu->arch.last_retry_addr = cr2;
5314
5315 if (!vcpu->arch.mmu.direct_map)
5316 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5317
22368028 5318 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5319
5320 return true;
5321}
5322
716d51ab
GN		 5323static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5324static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5325
64d60670 5326static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5327{
64d60670 5328 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5329 /* This is a good place to trace that we are exiting SMM. */
5330 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5331
c43203ca
PB		 5332 /* Process a latched INIT or SMI, if any. */
5333 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5334 }
699023e2
PB		 5335
5336 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5337}
5338
5339static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5340{
5341 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5342
a584539b 5343 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5344
5345 if (changed & HF_SMM_MASK)
5346 kvm_smm_changed(vcpu);
a584539b
PB		 5347}
5348
4a1e10d5
PB		 5349static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5350 unsigned long *db)
5351{
5352 u32 dr6 = 0;
5353 int i;
5354 u32 enable, rwlen;
5355
5356 enable = dr7;
5357 rwlen = dr7 >> 16;
5358 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5359 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5360 dr6 |= (1 << i);
5361 return dr6;
5362}
5363
6addfc42 5364static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5365{
5366 struct kvm_run *kvm_run = vcpu->run;
5367
5368 /*
6addfc42
PB		 5369 * rflags is the old, "raw" value of the flags. The new value has
5370 * not been saved yet.
663f4c61
PB		 5371 *
5372 * This is correct even for TF set by the guest, because "the
5373 * processor will not generate this exception after the instruction
5374 * that sets the TF flag".
5375 */
663f4c61
PB		 5376 if (unlikely(rflags & X86_EFLAGS_TF)) {
5377 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5378 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5379 DR6_RTM;
663f4c61
PB		 5380 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5381 kvm_run->debug.arch.exception = DB_VECTOR;
5382 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5383 *r = EMULATE_USER_EXIT;
5384 } else {
5385 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5386 /*
5387 * "Certain debug exceptions may clear bit 0-3. The
5388 * remaining contents of the DR6 register are never
5389 * cleared by the processor".
5390 */
5391 vcpu->arch.dr6 &= ~15;
6f43ed01 5392 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5393 kvm_queue_exception(vcpu, DB_VECTOR);
5394 }
5395 }
5396}
5397
4a1e10d5
PB		 5398static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5399{
4a1e10d5
PB		 5400 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5401 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5402 struct kvm_run *kvm_run = vcpu->run;
5403 unsigned long eip = kvm_get_linear_rip(vcpu);
5404 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5405 vcpu->arch.guest_debug_dr7,
5406 vcpu->arch.eff_db);
5407
5408 if (dr6 != 0) {
6f43ed01 5409 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5410 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5411 kvm_run->debug.arch.exception = DB_VECTOR;
5412 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5413 *r = EMULATE_USER_EXIT;
5414 return true;
5415 }
5416 }
5417
4161a569
NA		 5418 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5419 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5420 unsigned long eip = kvm_get_linear_rip(vcpu);
5421 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5422 vcpu->arch.dr7,
5423 vcpu->arch.db);
5424
5425 if (dr6 != 0) {
5426 vcpu->arch.dr6 &= ~15;
6f43ed01 5427 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5428 kvm_queue_exception(vcpu, DB_VECTOR);
5429 *r = EMULATE_DONE;
5430 return true;
5431 }
5432 }
5433
5434 return false;
5435}
5436
51d8b661
AP		 5437int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5438 unsigned long cr2,
dc25e89e
AP		 5439 int emulation_type,
5440 void *insn,
5441 int insn_len)
bbd9b64e 5442{
95cb2295 5443 int r;
9d74191a 5444 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5445 bool writeback = true;
93c05d3e 5446 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5447
93c05d3e
XG		 5448 /*
5449 * Clear write_fault_to_shadow_pgtable here to ensure it is
5450 * never reused.
5451 */
5452 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5453 kvm_clear_exception_queue(vcpu);
8d7d8102 5454
571008da 5455 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5456 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5457
5458 /*
5459 * We will reenter on the same instruction since
5460 * we do not set complete_userspace_io. This does not
5461 * handle watchpoints yet, those would be handled in
5462 * the emulate_ops.
5463 */
5464 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5465 return r;
5466
9d74191a
TY		 5467 ctxt->interruptibility = 0;
5468 ctxt->have_exception = false;
e0ad0b47 5469 ctxt->exception.vector = -1;
9d74191a 5470 ctxt->perm_ok = false;
bbd9b64e 5471
b51e974f 5472 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5473
9d74191a 5474 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5475
e46479f8 5476 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5477 ++vcpu->stat.insn_emulation;
1d2887e2 5478 if (r != EMULATION_OK) {
4005996e
AK		 5479 if (emulation_type & EMULTYPE_TRAP_UD)
5480 return EMULATE_FAIL;
991eebf9
GN		 5481 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5482 emulation_type))
bbd9b64e 5483 return EMULATE_DONE;
6d77dbfc
GN		 5484 if (emulation_type & EMULTYPE_SKIP)
5485 return EMULATE_FAIL;
5486 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5487 }
5488 }
5489
ba8afb6b 5490 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5491 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5492 if (ctxt->eflags & X86_EFLAGS_RF)
5493 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5494 return EMULATE_DONE;
5495 }
5496
1cb3f3ae
XG		 5497 if (retry_instruction(ctxt, cr2, emulation_type))
5498 return EMULATE_DONE;
5499
7ae441ea 5500 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5501 changes registers values during IO operation */
7ae441ea
GN		 5502 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5503 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5504 emulator_invalidate_register_cache(ctxt);
7ae441ea 5505 }
4d2179e1 5506
5cd21917 5507restart:
9d74191a 5508 r = x86_emulate_insn(ctxt);
bbd9b64e 5509
775fde86
JR		 5510 if (r == EMULATION_INTERCEPTED)
5511 return EMULATE_DONE;
5512
d2ddd1c4 5513 if (r == EMULATION_FAILED) {
991eebf9
GN		 5514 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5515 emulation_type))
c3cd7ffa
GN		 5516 return EMULATE_DONE;
5517
6d77dbfc 5518 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5519 }
5520
9d74191a 5521 if (ctxt->have_exception) {
d2ddd1c4 5522 r = EMULATE_DONE;
ef54bcfe
PB		 5523 if (inject_emulated_exception(vcpu))
5524 return r;
d2ddd1c4 5525 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5526 if (!vcpu->arch.pio.in) {
5527 /* FIXME: return into emulator if single-stepping. */
3457e419 5528 vcpu->arch.pio.count = 0;
0912c977 5529 } else {
7ae441ea 5530 writeback = false;
716d51ab
GN		 5531 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5532 }
ac0a48c3 5533 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5534 } else if (vcpu->mmio_needed) {
5535 if (!vcpu->mmio_is_write)
5536 writeback = false;
ac0a48c3 5537 r = EMULATE_USER_EXIT;
716d51ab 5538 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5539 } else if (r == EMULATION_RESTART)
5cd21917 5540 goto restart;
d2ddd1c4
GN		 5541 else
5542 r = EMULATE_DONE;
f850e2e6 5543
7ae441ea 5544 if (writeback) {
6addfc42 5545 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5546 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5547 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5548 if (vcpu->arch.hflags != ctxt->emul_flags)
5549 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5550 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5551 if (r == EMULATE_DONE)
6addfc42 5552 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5553 if (!ctxt->have_exception ||
5554 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5555 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5556
5557 /*
5558 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5559 * do nothing, and it will be requested again as soon as
5560 * the shadow expires. But we still need to check here,
5561 * because POPF has no interrupt shadow.
5562 */
5563 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5564 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5565 } else
5566 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5567
5568 return r;
de7d789a 5569}
51d8b661 5570EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5571
cf8f70bf 5572int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5573{
cf8f70bf 5574 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5575 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5576 size, port, &val, 1);
cf8f70bf 5577 /* do not return to emulator after return from userspace */
7972995b 5578 vcpu->arch.pio.count = 0;
de7d789a
CO		 5579 return ret;
5580}
cf8f70bf 5581EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5582
8cfdc000
ZA		 5583static void tsc_bad(void *info)
5584{
0a3aee0d 5585 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5586}
5587
5588static void tsc_khz_changed(void *data)
c8076604 5589{
8cfdc000
ZA		 5590 struct cpufreq_freqs *freq = data;
5591 unsigned long khz = 0;
5592
5593 if (data)
5594 khz = freq->new;
5595 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5596 khz = cpufreq_quick_get(raw_smp_processor_id());
5597 if (!khz)
5598 khz = tsc_khz;
0a3aee0d 5599 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5600}
5601
c8076604
GH		 5602static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5603 void *data)
5604{
5605 struct cpufreq_freqs *freq = data;
5606 struct kvm *kvm;
5607 struct kvm_vcpu *vcpu;
5608 int i, send_ipi = 0;
5609
8cfdc000
ZA		 5610 /*
5611 * We allow guests to temporarily run on slowing clocks,
5612 * provided we notify them after, or to run on accelerating
5613 * clocks, provided we notify them before. Thus time never
5614 * goes backwards.
5615 *
5616 * However, we have a problem. We can't atomically update
5617 * the frequency of a given CPU from this function; it is
5618 * merely a notifier, which can be called from any CPU.
5619 * Changing the TSC frequency at arbitrary points in time
5620 * requires a recomputation of local variables related to
5621 * the TSC for each VCPU. We must flag these local variables
5622 * to be updated and be sure the update takes place with the
5623 * new frequency before any guests proceed.
5624 *
5625 * Unfortunately, the combination of hotplug CPU and frequency
5626 * change creates an intractable locking scenario; the order
5627 * of when these callouts happen is undefined with respect to
5628 * CPU hotplug, and they can race with each other. As such,
5629 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5630 * undefined; you can actually have a CPU frequency change take
5631 * place in between the computation of X and the setting of the
5632 * variable. To protect against this problem, all updates of
5633 * the per_cpu tsc_khz variable are done in an interrupt
5634 * protected IPI, and all callers wishing to update the value
5635 * must wait for a synchronous IPI to complete (which is trivial
5636 * if the caller is on the CPU already). This establishes the
5637 * necessary total order on variable updates.
5638 *
5639 * Note that because a guest time update may take place
5640 * anytime after the setting of the VCPU's request bit, the
5641 * correct TSC value must be set before the request. However,
5642 * to ensure the update actually makes it to any guest which
5643 * starts running in hardware virtualization between the set
5644 * and the acquisition of the spinlock, we must also ping the
5645 * CPU after setting the request bit.
5646 *
5647 */
5648
c8076604
GH		 5649 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5650 return 0;
5651 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5652 return 0;
8cfdc000
ZA		 5653
5654 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5655
2f303b74 5656 spin_lock(&kvm_lock);
c8076604 5657 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5658 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5659 if (vcpu->cpu != freq->cpu)
5660 continue;
c285545f 5661 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5662 if (vcpu->cpu != smp_processor_id())
8cfdc000 5663 send_ipi = 1;
c8076604
GH		 5664 }
5665 }
2f303b74 5666 spin_unlock(&kvm_lock);
c8076604
GH		 5667
5668 if (freq->old < freq->new && send_ipi) {
5669 /*
5670 * We upscale the frequency. Must make the guest
5671 * doesn't see old kvmclock values while running with
5672 * the new frequency, otherwise we risk the guest sees
5673 * time go backwards.
5674 *
5675 * In case we update the frequency for another cpu
5676 * (which might be in guest context) send an interrupt
5677 * to kick the cpu out of guest context. Next time
5678 * guest context is entered kvmclock will be updated,
5679 * so the guest will not see stale values.
5680 */
8cfdc000 5681 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5682 }
5683 return 0;
5684}
5685
5686static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5687 .notifier_call = kvmclock_cpufreq_notifier
5688};
5689
5690static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5691 unsigned long action, void *hcpu)
5692{
5693 unsigned int cpu = (unsigned long)hcpu;
5694
5695 switch (action) {
5696 case CPU_ONLINE:
5697 case CPU_DOWN_FAILED:
5698 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5699 break;
5700 case CPU_DOWN_PREPARE:
5701 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5702 break;
5703 }
5704 return NOTIFY_OK;
5705}
5706
5707static struct notifier_block kvmclock_cpu_notifier_block = {
5708 .notifier_call = kvmclock_cpu_notifier,
5709 .priority = -INT_MAX
c8076604
GH		 5710};
5711
b820cc0c
ZA		 5712static void kvm_timer_init(void)
5713{
5714 int cpu;
5715
c285545f 5716 max_tsc_khz = tsc_khz;
460dd42e
SB		 5717
5718 cpu_notifier_register_begin();
b820cc0c 5719 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5720#ifdef CONFIG_CPU_FREQ
5721 struct cpufreq_policy policy;
5722 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5723 cpu = get_cpu();
5724 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5725 if (policy.cpuinfo.max_freq)
5726 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5727 put_cpu();
c285545f 5728#endif
b820cc0c
ZA		 5729 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5730 CPUFREQ_TRANSITION_NOTIFIER);
5731 }
c285545f 5732 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5733 for_each_online_cpu(cpu)
5734 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5735
5736 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5737 cpu_notifier_register_done();
5738
b820cc0c
ZA		 5739}
5740
ff9d07a0
ZY		 5741static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5742
f5132b01 5743int kvm_is_in_guest(void)
ff9d07a0 5744{
086c9855 5745 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5746}
5747
5748static int kvm_is_user_mode(void)
5749{
5750 int user_mode = 3;
dcf46b94 5751
086c9855
AS		 5752 if (__this_cpu_read(current_vcpu))
5753 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5754
ff9d07a0
ZY		 5755 return user_mode != 0;
5756}
5757
5758static unsigned long kvm_get_guest_ip(void)
5759{
5760 unsigned long ip = 0;
dcf46b94 5761
086c9855
AS		 5762 if (__this_cpu_read(current_vcpu))
5763 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5764
ff9d07a0
ZY		 5765 return ip;
5766}
5767
5768static struct perf_guest_info_callbacks kvm_guest_cbs = {
5769 .is_in_guest = kvm_is_in_guest,
5770 .is_user_mode = kvm_is_user_mode,
5771 .get_guest_ip = kvm_get_guest_ip,
5772};
5773
5774void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5775{
086c9855 5776 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5777}
5778EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5779
5780void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5781{
086c9855 5782 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5783}
5784EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5785
ce88decf
XG		 5786static void kvm_set_mmio_spte_mask(void)
5787{
5788 u64 mask;
5789 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5790
5791 /*
5792 * Set the reserved bits and the present bit of an paging-structure
5793 * entry to generate page fault with PFER.RSV = 1.
5794 */
885032b9 5795 /* Mask the reserved physical address bits. */
d1431483 5796 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5797
5798 /* Bit 62 is always reserved for 32bit host. */
5799 mask |= 0x3ull << 62;
5800
5801 /* Set the present bit. */
ce88decf
XG		 5802 mask |= 1ull;
5803
5804#ifdef CONFIG_X86_64
5805 /*
5806 * If reserved bit is not supported, clear the present bit to disable
5807 * mmio page fault.
5808 */
5809 if (maxphyaddr == 52)
5810 mask &= ~1ull;
5811#endif
5812
5813 kvm_mmu_set_mmio_spte_mask(mask);
5814}
5815
16e8d74d
MT		 5816#ifdef CONFIG_X86_64
5817static void pvclock_gtod_update_fn(struct work_struct *work)
5818{
d828199e
MT		 5819 struct kvm *kvm;
5820
5821 struct kvm_vcpu *vcpu;
5822 int i;
5823
2f303b74 5824 spin_lock(&kvm_lock);
d828199e
MT		 5825 list_for_each_entry(kvm, &vm_list, vm_list)
5826 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5827 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5828 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5829 spin_unlock(&kvm_lock);
16e8d74d
MT		 5830}
5831
5832static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5833
5834/*
5835 * Notification about pvclock gtod data update.
5836 */
5837static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5838 void *priv)
5839{
5840 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5841 struct timekeeper *tk = priv;
5842
5843 update_pvclock_gtod(tk);
5844
5845 /* disable master clock if host does not trust, or does not
5846 * use, TSC clocksource
5847 */
5848 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5849 atomic_read(&kvm_guest_has_master_clock) != 0)
5850 queue_work(system_long_wq, &pvclock_gtod_work);
5851
5852 return 0;
5853}
5854
5855static struct notifier_block pvclock_gtod_notifier = {
5856 .notifier_call = pvclock_gtod_notify,
5857};
5858#endif
5859
f8c16bba 5860int kvm_arch_init(void *opaque)
043405e1 5861{
b820cc0c 5862 int r;
6b61edf7 5863 struct kvm_x86_ops *ops = opaque;
f8c16bba 5864
f8c16bba
ZX		 5865 if (kvm_x86_ops) {
5866 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5867 r = -EEXIST;
5868 goto out;
f8c16bba
ZX		 5869 }
5870
5871 if (!ops->cpu_has_kvm_support()) {
5872 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5873 r = -EOPNOTSUPP;
5874 goto out;
f8c16bba
ZX		 5875 }
5876 if (ops->disabled_by_bios()) {
5877 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5878 r = -EOPNOTSUPP;
5879 goto out;
f8c16bba
ZX		 5880 }
5881
013f6a5d
MT		 5882 r = -ENOMEM;
5883 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5884 if (!shared_msrs) {
5885 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5886 goto out;
5887 }
5888
97db56ce
AK		 5889 r = kvm_mmu_module_init();
5890 if (r)
013f6a5d 5891 goto out_free_percpu;
97db56ce 5892
ce88decf 5893 kvm_set_mmio_spte_mask();
97db56ce 5894
f8c16bba 5895 kvm_x86_ops = ops;
920c8377 5896
7b52345e 5897 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8
BD		 5898 PT_DIRTY_MASK, PT64_NX_MASK, 0,
5899 PT_PRESENT_MASK);
b820cc0c 5900 kvm_timer_init();
c8076604 5901
ff9d07a0
ZY		 5902 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5903
d366bf7e 5904 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 5905 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5906
c5cc421b 5907 kvm_lapic_init();
16e8d74d
MT		 5908#ifdef CONFIG_X86_64
5909 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5910#endif
5911
f8c16bba 5912 return 0;
56c6d28a 5913
013f6a5d
MT		 5914out_free_percpu:
5915 free_percpu(shared_msrs);
56c6d28a 5916out:
56c6d28a 5917 return r;
043405e1 5918}
8776e519 5919
f8c16bba
ZX		 5920void kvm_arch_exit(void)
5921{
ff9d07a0
ZY		 5922 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5923
888d256e
JK		 5924 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5925 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5926 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5927 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5928#ifdef CONFIG_X86_64
5929 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5930#endif
f8c16bba 5931 kvm_x86_ops = NULL;
56c6d28a 5932 kvm_mmu_module_exit();
013f6a5d 5933 free_percpu(shared_msrs);
56c6d28a 5934}
f8c16bba 5935
5cb56059 5936int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5937{
5938 ++vcpu->stat.halt_exits;
35754c98 5939 if (lapic_in_kernel(vcpu)) {
a4535290 5940 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5941 return 1;
5942 } else {
5943 vcpu->run->exit_reason = KVM_EXIT_HLT;
5944 return 0;
5945 }
5946}
5cb56059
JS		 5947EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5948
5949int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5950{
5951 kvm_x86_ops->skip_emulated_instruction(vcpu);
5952 return kvm_vcpu_halt(vcpu);
5953}
8776e519
HB		 5954EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5955
6aef266c
SV		 5956/*
5957 * kvm_pv_kick_cpu_op: Kick a vcpu.
5958 *
5959 * @apicid - apicid of vcpu to be kicked.
5960 */
5961static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5962{
24d2166b 5963 struct kvm_lapic_irq lapic_irq;
6aef266c 5964
24d2166b
R		 5965 lapic_irq.shorthand = 0;
5966 lapic_irq.dest_mode = 0;
5967 lapic_irq.dest_id = apicid;
93bbf0b8 5968 lapic_irq.msi_redir_hint = false;
6aef266c 5969
24d2166b 5970 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5971 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5972}
5973
d62caabb
AS		 5974void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5975{
5976 vcpu->arch.apicv_active = false;
5977 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5978}
5979
8776e519
HB		 5980int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5981{
5982 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5983 int op_64_bit, r = 1;
8776e519 5984
5cb56059
JS		 5985 kvm_x86_ops->skip_emulated_instruction(vcpu);
5986
55cd8e5a
GN		 5987 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5988 return kvm_hv_hypercall(vcpu);
5989
5fdbf976
MT		 5990 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5991 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5992 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5993 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5994 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5995
229456fc 5996 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5997
a449c7aa
NA		 5998 op_64_bit = is_64_bit_mode(vcpu);
5999 if (!op_64_bit) {
8776e519
HB		 6000 nr &= 0xFFFFFFFF;
6001 a0 &= 0xFFFFFFFF;
6002 a1 &= 0xFFFFFFFF;
6003 a2 &= 0xFFFFFFFF;
6004 a3 &= 0xFFFFFFFF;
6005 }
6006
07708c4a
JK		 6007 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6008 ret = -KVM_EPERM;
6009 goto out;
6010 }
6011
8776e519 6012 switch (nr) {
b93463aa
AK		 6013 case KVM_HC_VAPIC_POLL_IRQ:
6014 ret = 0;
6015 break;
6aef266c
SV		 6016 case KVM_HC_KICK_CPU:
6017 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6018 ret = 0;
6019 break;
8776e519
HB		 6020 default:
6021 ret = -KVM_ENOSYS;
6022 break;
6023 }
07708c4a 6024out:
a449c7aa
NA		 6025 if (!op_64_bit)
6026 ret = (u32)ret;
5fdbf976 6027 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6028 ++vcpu->stat.hypercalls;
2f333bcb 6029 return r;
8776e519
HB		 6030}
6031EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6032
b6785def 6033static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6034{
d6aa1000 6035 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6036 char instruction[3];
5fdbf976 6037 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6038
8776e519 6039 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6040
9d74191a 6041 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6042}
6043
851ba692 6044static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6045{
782d422b
MG		 6046 return vcpu->run->request_interrupt_window &&
6047 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6048}
6049
851ba692 6050static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6051{
851ba692
AK		 6052 struct kvm_run *kvm_run = vcpu->run;
6053
91586a3b 6054 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6055 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6056 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6057 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6058 kvm_run->ready_for_interrupt_injection =
6059 pic_in_kernel(vcpu->kvm) ||
782d422b 6060 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6061}
6062
95ba8273
GN		 6063static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6064{
6065 int max_irr, tpr;
6066
6067 if (!kvm_x86_ops->update_cr8_intercept)
6068 return;
6069
bce87cce 6070 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6071 return;
6072
d62caabb
AS		 6073 if (vcpu->arch.apicv_active)
6074 return;
6075
8db3baa2
GN		 6076 if (!vcpu->arch.apic->vapic_addr)
6077 max_irr = kvm_lapic_find_highest_irr(vcpu);
6078 else
6079 max_irr = -1;
95ba8273
GN		 6080
6081 if (max_irr != -1)
6082 max_irr >>= 4;
6083
6084 tpr = kvm_lapic_get_cr8(vcpu);
6085
6086 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6087}
6088
b6b8a145 6089static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6090{
b6b8a145
JK		 6091 int r;
6092
95ba8273 6093 /* try to reinject previous events if any */
b59bb7bd 6094 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6095 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6096 vcpu->arch.exception.has_error_code,
6097 vcpu->arch.exception.error_code);
d6e8c854
NA		 6098
6099 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6100 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6101 X86_EFLAGS_RF);
6102
6bdf0662
NA		 6103 if (vcpu->arch.exception.nr == DB_VECTOR &&
6104 (vcpu->arch.dr7 & DR7_GD)) {
6105 vcpu->arch.dr7 &= ~DR7_GD;
6106 kvm_update_dr7(vcpu);
6107 }
6108
b59bb7bd
GN		 6109 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6110 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6111 vcpu->arch.exception.error_code,
6112 vcpu->arch.exception.reinject);
b6b8a145 6113 return 0;
b59bb7bd
GN		 6114 }
6115
95ba8273
GN		 6116 if (vcpu->arch.nmi_injected) {
6117 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6118 return 0;
95ba8273
GN		 6119 }
6120
6121 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6122 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6123 return 0;
6124 }
6125
6126 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6127 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6128 if (r != 0)
6129 return r;
95ba8273
GN		 6130 }
6131
6132 /* try to inject new event if pending */
c43203ca
PB		 6133 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6134 vcpu->arch.smi_pending = false;
ee2cd4b7 6135 enter_smm(vcpu);
c43203ca 6136 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6137 --vcpu->arch.nmi_pending;
6138 vcpu->arch.nmi_injected = true;
6139 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6140 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6141 /*
6142 * Because interrupts can be injected asynchronously, we are
6143 * calling check_nested_events again here to avoid a race condition.
6144 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6145 * proposal and current concerns. Perhaps we should be setting
6146 * KVM_REQ_EVENT only on certain events and not unconditionally?
6147 */
6148 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6149 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6150 if (r != 0)
6151 return r;
6152 }
95ba8273 6153 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6154 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6155 false);
6156 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6157 }
6158 }
ee2cd4b7 6159
b6b8a145 6160 return 0;
95ba8273
GN		 6161}
6162
7460fb4a
AK		 6163static void process_nmi(struct kvm_vcpu *vcpu)
6164{
6165 unsigned limit = 2;
6166
6167 /*
6168 * x86 is limited to one NMI running, and one NMI pending after it.
6169 * If an NMI is already in progress, limit further NMIs to just one.
6170 * Otherwise, allow two (and we'll inject the first one immediately).
6171 */
6172 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6173 limit = 1;
6174
6175 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6176 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6177 kvm_make_request(KVM_REQ_EVENT, vcpu);
6178}
6179
660a5d51
PB		 6180#define put_smstate(type, buf, offset, val) \
6181 *(type *)((buf) + (offset) - 0x7e00) = val
6182
ee2cd4b7 6183static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6184{
6185 u32 flags = 0;
6186 flags |= seg->g << 23;
6187 flags |= seg->db << 22;
6188 flags |= seg->l << 21;
6189 flags |= seg->avl << 20;
6190 flags |= seg->present << 15;
6191 flags |= seg->dpl << 13;
6192 flags |= seg->s << 12;
6193 flags |= seg->type << 8;
6194 return flags;
6195}
6196
ee2cd4b7 6197static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6198{
6199 struct kvm_segment seg;
6200 int offset;
6201
6202 kvm_get_segment(vcpu, &seg, n);
6203 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6204
6205 if (n < 3)
6206 offset = 0x7f84 + n * 12;
6207 else
6208 offset = 0x7f2c + (n - 3) * 12;
6209
6210 put_smstate(u32, buf, offset + 8, seg.base);
6211 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6212 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6213}
6214
efbb288a 6215#ifdef CONFIG_X86_64
ee2cd4b7 6216static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6217{
6218 struct kvm_segment seg;
6219 int offset;
6220 u16 flags;
6221
6222 kvm_get_segment(vcpu, &seg, n);
6223 offset = 0x7e00 + n * 16;
6224
ee2cd4b7 6225 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6226 put_smstate(u16, buf, offset, seg.selector);
6227 put_smstate(u16, buf, offset + 2, flags);
6228 put_smstate(u32, buf, offset + 4, seg.limit);
6229 put_smstate(u64, buf, offset + 8, seg.base);
6230}
efbb288a 6231#endif
660a5d51 6232
ee2cd4b7 6233static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6234{
6235 struct desc_ptr dt;
6236 struct kvm_segment seg;
6237 unsigned long val;
6238 int i;
6239
6240 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6241 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6242 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6243 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6244
6245 for (i = 0; i < 8; i++)
6246 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6247
6248 kvm_get_dr(vcpu, 6, &val);
6249 put_smstate(u32, buf, 0x7fcc, (u32)val);
6250 kvm_get_dr(vcpu, 7, &val);
6251 put_smstate(u32, buf, 0x7fc8, (u32)val);
6252
6253 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6254 put_smstate(u32, buf, 0x7fc4, seg.selector);
6255 put_smstate(u32, buf, 0x7f64, seg.base);
6256 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6257 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6258
6259 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6260 put_smstate(u32, buf, 0x7fc0, seg.selector);
6261 put_smstate(u32, buf, 0x7f80, seg.base);
6262 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6263 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6264
6265 kvm_x86_ops->get_gdt(vcpu, &dt);
6266 put_smstate(u32, buf, 0x7f74, dt.address);
6267 put_smstate(u32, buf, 0x7f70, dt.size);
6268
6269 kvm_x86_ops->get_idt(vcpu, &dt);
6270 put_smstate(u32, buf, 0x7f58, dt.address);
6271 put_smstate(u32, buf, 0x7f54, dt.size);
6272
6273 for (i = 0; i < 6; i++)
ee2cd4b7 6274 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6275
6276 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6277
6278 /* revision id */
6279 put_smstate(u32, buf, 0x7efc, 0x00020000);
6280 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6281}
6282
ee2cd4b7 6283static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6284{
6285#ifdef CONFIG_X86_64
6286 struct desc_ptr dt;
6287 struct kvm_segment seg;
6288 unsigned long val;
6289 int i;
6290
6291 for (i = 0; i < 16; i++)
6292 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6293
6294 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6295 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6296
6297 kvm_get_dr(vcpu, 6, &val);
6298 put_smstate(u64, buf, 0x7f68, val);
6299 kvm_get_dr(vcpu, 7, &val);
6300 put_smstate(u64, buf, 0x7f60, val);
6301
6302 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6303 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6304 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6305
6306 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6307
6308 /* revision id */
6309 put_smstate(u32, buf, 0x7efc, 0x00020064);
6310
6311 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6312
6313 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6314 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6315 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6316 put_smstate(u32, buf, 0x7e94, seg.limit);
6317 put_smstate(u64, buf, 0x7e98, seg.base);
6318
6319 kvm_x86_ops->get_idt(vcpu, &dt);
6320 put_smstate(u32, buf, 0x7e84, dt.size);
6321 put_smstate(u64, buf, 0x7e88, dt.address);
6322
6323 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6324 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6325 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6326 put_smstate(u32, buf, 0x7e74, seg.limit);
6327 put_smstate(u64, buf, 0x7e78, seg.base);
6328
6329 kvm_x86_ops->get_gdt(vcpu, &dt);
6330 put_smstate(u32, buf, 0x7e64, dt.size);
6331 put_smstate(u64, buf, 0x7e68, dt.address);
6332
6333 for (i = 0; i < 6; i++)
ee2cd4b7 6334 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6335#else
6336 WARN_ON_ONCE(1);
6337#endif
6338}
6339
ee2cd4b7 6340static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6341{
660a5d51 6342 struct kvm_segment cs, ds;
18c3626e 6343 struct desc_ptr dt;
660a5d51
PB		 6344 char buf[512];
6345 u32 cr0;
6346
660a5d51
PB		 6347 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6348 vcpu->arch.hflags |= HF_SMM_MASK;
6349 memset(buf, 0, 512);
6350 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6351 enter_smm_save_state_64(vcpu, buf);
660a5d51 6352 else
ee2cd4b7 6353 enter_smm_save_state_32(vcpu, buf);
660a5d51 6354
54bf36aa 6355 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6356
6357 if (kvm_x86_ops->get_nmi_mask(vcpu))
6358 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6359 else
6360 kvm_x86_ops->set_nmi_mask(vcpu, true);
6361
6362 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6363 kvm_rip_write(vcpu, 0x8000);
6364
6365 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6366 kvm_x86_ops->set_cr0(vcpu, cr0);
6367 vcpu->arch.cr0 = cr0;
6368
6369 kvm_x86_ops->set_cr4(vcpu, 0);
6370
18c3626e
PB		 6371 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6372 dt.address = dt.size = 0;
6373 kvm_x86_ops->set_idt(vcpu, &dt);
6374
660a5d51
PB		 6375 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6376
6377 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6378 cs.base = vcpu->arch.smbase;
6379
6380 ds.selector = 0;
6381 ds.base = 0;
6382
6383 cs.limit = ds.limit = 0xffffffff;
6384 cs.type = ds.type = 0x3;
6385 cs.dpl = ds.dpl = 0;
6386 cs.db = ds.db = 0;
6387 cs.s = ds.s = 1;
6388 cs.l = ds.l = 0;
6389 cs.g = ds.g = 1;
6390 cs.avl = ds.avl = 0;
6391 cs.present = ds.present = 1;
6392 cs.unusable = ds.unusable = 0;
6393 cs.padding = ds.padding = 0;
6394
6395 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6396 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6397 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6398 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6399 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6400 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6401
6402 if (guest_cpuid_has_longmode(vcpu))
6403 kvm_x86_ops->set_efer(vcpu, 0);
6404
6405 kvm_update_cpuid(vcpu);
6406 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6407}
6408
ee2cd4b7 6409static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6410{
6411 vcpu->arch.smi_pending = true;
6412 kvm_make_request(KVM_REQ_EVENT, vcpu);
6413}
6414
2860c4b1
PB		 6415void kvm_make_scan_ioapic_request(struct kvm *kvm)
6416{
6417 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6418}
6419
3d81bc7e 6420static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6421{
5c919412
AS		 6422 u64 eoi_exit_bitmap[4];
6423
3d81bc7e
YZ		 6424 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6425 return;
c7c9c56c 6426
6308630b 6427 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6428
b053b2ae 6429 if (irqchip_split(vcpu->kvm))
6308630b 6430 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6431 else {
d62caabb
AS		 6432 if (vcpu->arch.apicv_active)
6433 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6434 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6435 }
5c919412
AS		 6436 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6437 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6438 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6439}
6440
a70656b6
RK		 6441static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6442{
6443 ++vcpu->stat.tlb_flush;
6444 kvm_x86_ops->tlb_flush(vcpu);
6445}
6446
4256f43f
TC		 6447void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6448{
c24ae0dc
TC		 6449 struct page *page = NULL;
6450
35754c98 6451 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6452 return;
6453
4256f43f
TC		 6454 if (!kvm_x86_ops->set_apic_access_page_addr)
6455 return;
6456
c24ae0dc 6457 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6458 if (is_error_page(page))
6459 return;
c24ae0dc
TC		 6460 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6461
6462 /*
6463 * Do not pin apic access page in memory, the MMU notifier
6464 * will call us again if it is migrated or swapped out.
6465 */
6466 put_page(page);
4256f43f
TC		 6467}
6468EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6469
fe71557a
TC		 6470void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6471 unsigned long address)
6472{
c24ae0dc
TC		 6473 /*
6474 * The physical address of apic access page is stored in the VMCS.
6475 * Update it when it becomes invalid.
6476 */
6477 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6478 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6479}
6480
9357d939 6481/*
362c698f 6482 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6483 * exiting to the userspace. Otherwise, the value will be returned to the
6484 * userspace.
6485 */
851ba692 6486static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6487{
6488 int r;
62a193ed
MG		 6489 bool req_int_win =
6490 dm_request_for_irq_injection(vcpu) &&
6491 kvm_cpu_accept_dm_intr(vcpu);
6492
730dca42 6493 bool req_immediate_exit = false;
b6c7a5dc 6494
3e007509 6495 if (vcpu->requests) {
a8eeb04a 6496 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6497 kvm_mmu_unload(vcpu);
a8eeb04a 6498 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6499 __kvm_migrate_timers(vcpu);
d828199e
MT		 6500 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6501 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6502 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6503 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6504 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6505 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6506 if (unlikely(r))
6507 goto out;
6508 }
a8eeb04a 6509 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6510 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6511 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6512 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6513 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6514 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6515 r = 0;
6516 goto out;
6517 }
a8eeb04a 6518 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6519 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6520 r = 0;
6521 goto out;
6522 }
a8eeb04a 6523 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6524 vcpu->fpu_active = 0;
6525 kvm_x86_ops->fpu_deactivate(vcpu);
6526 }
af585b92
GN		 6527 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6528 /* Page is swapped out. Do synthetic halt */
6529 vcpu->arch.apf.halted = true;
6530 r = 1;
6531 goto out;
6532 }
c9aaa895
GC		 6533 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6534 record_steal_time(vcpu);
64d60670 6535 if (kvm_check_request(KVM_REQ_SMI, vcpu))
ee2cd4b7 6536 process_smi(vcpu);
7460fb4a
AK		 6537 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6538 process_nmi(vcpu);
f5132b01 6539 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6540 kvm_pmu_handle_event(vcpu);
f5132b01 6541 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6542 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6543 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6544 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6545 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6546 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6547 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6548 vcpu->run->eoi.vector =
6549 vcpu->arch.pending_ioapic_eoi;
6550 r = 0;
6551 goto out;
6552 }
6553 }
3d81bc7e
YZ		 6554 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6555 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6556 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6557 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6558 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6559 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6560 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6561 r = 0;
6562 goto out;
6563 }
e516cebb
AS		 6564 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6565 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6566 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6567 r = 0;
6568 goto out;
6569 }
db397571
AS		 6570 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6571 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6572 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6573 r = 0;
6574 goto out;
6575 }
f3b138c5
AS		 6576
6577 /*
6578 * KVM_REQ_HV_STIMER has to be processed after
6579 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6580 * depend on the guest clock being up-to-date
6581 */
1f4b34f8
AS		 6582 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6583 kvm_hv_process_stimers(vcpu);
2f52d58c 6584 }
b93463aa 6585
bf9f6ac8
FW		 6586 /*
6587 * KVM_REQ_EVENT is not set when posted interrupts are set by
6588 * VT-d hardware, so we have to update RVI unconditionally.
6589 */
6590 if (kvm_lapic_enabled(vcpu)) {
6591 /*
6592 * Update architecture specific hints for APIC
6593 * virtual interrupt delivery.
6594 */
d62caabb 6595 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6596 kvm_x86_ops->hwapic_irr_update(vcpu,
6597 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6598 }
b93463aa 6599
b463a6f7 6600 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6601 kvm_apic_accept_events(vcpu);
6602 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6603 r = 1;
6604 goto out;
6605 }
6606
b6b8a145
JK		 6607 if (inject_pending_event(vcpu, req_int_win) != 0)
6608 req_immediate_exit = true;
321c5658 6609 else {
c43203ca
PB		 6610 /* Enable NMI/IRQ window open exits if needed.
6611 *
6612 * SMIs have two cases: 1) they can be nested, and
6613 * then there is nothing to do here because RSM will
6614 * cause a vmexit anyway; 2) or the SMI can be pending
6615 * because inject_pending_event has completed the
6616 * injection of an IRQ or NMI from the previous vmexit,
6617 * and then we request an immediate exit to inject the SMI.
6618 */
6619 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6620 req_immediate_exit = true;
321c5658
YS		 6621 if (vcpu->arch.nmi_pending)
6622 kvm_x86_ops->enable_nmi_window(vcpu);
6623 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6624 kvm_x86_ops->enable_irq_window(vcpu);
6625 }
b463a6f7
AK		 6626
6627 if (kvm_lapic_enabled(vcpu)) {
6628 update_cr8_intercept(vcpu);
6629 kvm_lapic_sync_to_vapic(vcpu);
6630 }
6631 }
6632
d8368af8
AK		 6633 r = kvm_mmu_reload(vcpu);
6634 if (unlikely(r)) {
d905c069 6635 goto cancel_injection;
d8368af8
AK		 6636 }
6637
b6c7a5dc
HB		 6638 preempt_disable();
6639
6640 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6641 if (vcpu->fpu_active)
6642 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6643 vcpu->mode = IN_GUEST_MODE;
6644
01b71917
MT		 6645 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6646
0f127d12
LT		 6647 /*
6648 * We should set ->mode before check ->requests,
6649 * Please see the comment in kvm_make_all_cpus_request.
6650 * This also orders the write to mode from any reads
6651 * to the page tables done while the VCPU is running.
6652 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6653 */
01b71917 6654 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6655
d94e1dc9 6656 local_irq_disable();
32f88400 6657
6b7e2d09 6658 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6659 || need_resched() || signal_pending(current)) {
6b7e2d09 6660 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6661 smp_wmb();
6c142801
AK		 6662 local_irq_enable();
6663 preempt_enable();
01b71917 6664 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6665 r = 1;
d905c069 6666 goto cancel_injection;
6c142801
AK		 6667 }
6668
fc5b7f3b
DM		 6669 kvm_load_guest_xcr0(vcpu);
6670
c43203ca
PB		 6671 if (req_immediate_exit) {
6672 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6673 smp_send_reschedule(vcpu->cpu);
c43203ca 6674 }
d6185f20 6675
8b89fe1f
PB		 6676 trace_kvm_entry(vcpu->vcpu_id);
6677 wait_lapic_expire(vcpu);
6edaa530 6678 guest_enter_irqoff();
b6c7a5dc 6679
42dbaa5a 6680 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6681 set_debugreg(0, 7);
6682 set_debugreg(vcpu->arch.eff_db[0], 0);
6683 set_debugreg(vcpu->arch.eff_db[1], 1);
6684 set_debugreg(vcpu->arch.eff_db[2], 2);
6685 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6686 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6687 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6688 }
b6c7a5dc 6689
851ba692 6690 kvm_x86_ops->run(vcpu);
b6c7a5dc 6691
c77fb5fe
PB		 6692 /*
6693 * Do this here before restoring debug registers on the host. And
6694 * since we do this before handling the vmexit, a DR access vmexit
6695 * can (a) read the correct value of the debug registers, (b) set
6696 * KVM_DEBUGREG_WONT_EXIT again.
6697 */
6698 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6699 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6700 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6701 kvm_update_dr0123(vcpu);
6702 kvm_update_dr6(vcpu);
6703 kvm_update_dr7(vcpu);
6704 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6705 }
6706
24f1e32c
FW		 6707 /*
6708 * If the guest has used debug registers, at least dr7
6709 * will be disabled while returning to the host.
6710 * If we don't have active breakpoints in the host, we don't
6711 * care about the messed up debug address registers. But if
6712 * we have some of them active, restore the old state.
6713 */
59d8eb53 6714 if (hw_breakpoint_active())
24f1e32c 6715 hw_breakpoint_restore();
42dbaa5a 6716
4ba76538 6717 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6718
6b7e2d09 6719 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6720 smp_wmb();
a547c6db 6721
fc5b7f3b
DM		 6722 kvm_put_guest_xcr0(vcpu);
6723
a547c6db
YZ		 6724 /* Interrupt is enabled by handle_external_intr() */
6725 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6726
6727 ++vcpu->stat.exits;
6728
f2485b3e 6729 guest_exit_irqoff();
b6c7a5dc 6730
f2485b3e 6731 local_irq_enable();
b6c7a5dc
HB		 6732 preempt_enable();
6733
f656ce01 6734 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6735
b6c7a5dc
HB		 6736 /*
6737 * Profile KVM exit RIPs:
6738 */
6739 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6740 unsigned long rip = kvm_rip_read(vcpu);
6741 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6742 }
6743
cc578287
ZA		 6744 if (unlikely(vcpu->arch.tsc_always_catchup))
6745 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6746
5cfb1d5a
MT		 6747 if (vcpu->arch.apic_attention)
6748 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6749
851ba692 6750 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6751 return r;
6752
6753cancel_injection:
6754 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6755 if (unlikely(vcpu->arch.apic_attention))
6756 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6757out:
6758 return r;
6759}
b6c7a5dc 6760
362c698f
PB		 6761static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6762{
bf9f6ac8
FW		 6763 if (!kvm_arch_vcpu_runnable(vcpu) &&
6764 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6765 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6766 kvm_vcpu_block(vcpu);
6767 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6768
6769 if (kvm_x86_ops->post_block)
6770 kvm_x86_ops->post_block(vcpu);
6771
9c8fd1ba
PB		 6772 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6773 return 1;
6774 }
362c698f
PB		 6775
6776 kvm_apic_accept_events(vcpu);
6777 switch(vcpu->arch.mp_state) {
6778 case KVM_MP_STATE_HALTED:
6779 vcpu->arch.pv.pv_unhalted = false;
6780 vcpu->arch.mp_state =
6781 KVM_MP_STATE_RUNNABLE;
6782 case KVM_MP_STATE_RUNNABLE:
6783 vcpu->arch.apf.halted = false;
6784 break;
6785 case KVM_MP_STATE_INIT_RECEIVED:
6786 break;
6787 default:
6788 return -EINTR;
6789 break;
6790 }
6791 return 1;
6792}
09cec754 6793
5d9bc648
PB		 6794static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6795{
6796 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6797 !vcpu->arch.apf.halted);
6798}
6799
362c698f 6800static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6801{
6802 int r;
f656ce01 6803 struct kvm *kvm = vcpu->kvm;
d7690175 6804
f656ce01 6805 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6806
362c698f 6807 for (;;) {
58f800d5 6808 if (kvm_vcpu_running(vcpu)) {
851ba692 6809 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6810 } else {
362c698f 6811 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6812 }
6813
09cec754
GN		 6814 if (r <= 0)
6815 break;
6816
6817 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6818 if (kvm_cpu_has_pending_timer(vcpu))
6819 kvm_inject_pending_timer_irqs(vcpu);
6820
782d422b
MG		 6821 if (dm_request_for_irq_injection(vcpu) &&
6822 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6823 r = 0;
6824 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6825 ++vcpu->stat.request_irq_exits;
362c698f 6826 break;
09cec754 6827 }
af585b92
GN		 6828
6829 kvm_check_async_pf_completion(vcpu);
6830
09cec754
GN		 6831 if (signal_pending(current)) {
6832 r = -EINTR;
851ba692 6833 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6834 ++vcpu->stat.signal_exits;
362c698f 6835 break;
09cec754
GN		 6836 }
6837 if (need_resched()) {
f656ce01 6838 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6839 cond_resched();
f656ce01 6840 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6841 }
b6c7a5dc
HB		 6842 }
6843
f656ce01 6844 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6845
6846 return r;
6847}
6848
716d51ab
GN		 6849static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6850{
6851 int r;
6852 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6853 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6854 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6855 if (r != EMULATE_DONE)
6856 return 0;
6857 return 1;
6858}
6859
6860static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6861{
6862 BUG_ON(!vcpu->arch.pio.count);
6863
6864 return complete_emulated_io(vcpu);
6865}
6866
f78146b0
AK		 6867/*
6868 * Implements the following, as a state machine:
6869 *
6870 * read:
6871 * for each fragment
87da7e66
XG		 6872 * for each mmio piece in the fragment
6873 * write gpa, len
6874 * exit
6875 * copy data
f78146b0
AK		 6876 * execute insn
6877 *
6878 * write:
6879 * for each fragment
87da7e66
XG		 6880 * for each mmio piece in the fragment
6881 * write gpa, len
6882 * copy data
6883 * exit
f78146b0 6884 */
716d51ab 6885static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6886{
6887 struct kvm_run *run = vcpu->run;
f78146b0 6888 struct kvm_mmio_fragment *frag;
87da7e66 6889 unsigned len;
5287f194 6890
716d51ab 6891 BUG_ON(!vcpu->mmio_needed);
5287f194 6892
716d51ab 6893 /* Complete previous fragment */
87da7e66
XG		 6894 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6895 len = min(8u, frag->len);
716d51ab 6896 if (!vcpu->mmio_is_write)
87da7e66
XG		 6897 memcpy(frag->data, run->mmio.data, len);
6898
6899 if (frag->len <= 8) {
6900 /* Switch to the next fragment. */
6901 frag++;
6902 vcpu->mmio_cur_fragment++;
6903 } else {
6904 /* Go forward to the next mmio piece. */
6905 frag->data += len;
6906 frag->gpa += len;
6907 frag->len -= len;
6908 }
6909
a08d3b3b 6910 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6911 vcpu->mmio_needed = 0;
0912c977
PB		 6912
6913 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6914 if (vcpu->mmio_is_write)
716d51ab
GN		 6915 return 1;
6916 vcpu->mmio_read_completed = 1;
6917 return complete_emulated_io(vcpu);
6918 }
87da7e66 6919
716d51ab
GN		 6920 run->exit_reason = KVM_EXIT_MMIO;
6921 run->mmio.phys_addr = frag->gpa;
6922 if (vcpu->mmio_is_write)
87da7e66
XG		 6923 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6924 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6925 run->mmio.is_write = vcpu->mmio_is_write;
6926 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6927 return 0;
5287f194
AK		 6928}
6929
716d51ab 6930
b6c7a5dc
HB		 6931int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6932{
c5bedc68 6933 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6934 int r;
6935 sigset_t sigsaved;
6936
c4d72e2d 6937 fpu__activate_curr(fpu);
e5c30142 6938
ac9f6dc0
AK		 6939 if (vcpu->sigset_active)
6940 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6941
a4535290 6942 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6943 kvm_vcpu_block(vcpu);
66450a21 6944 kvm_apic_accept_events(vcpu);
d7690175 6945 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6946 r = -EAGAIN;
6947 goto out;
b6c7a5dc
HB		 6948 }
6949
b6c7a5dc 6950 /* re-sync apic's tpr */
35754c98 6951 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6952 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6953 r = -EINVAL;
6954 goto out;
6955 }
6956 }
b6c7a5dc 6957
716d51ab
GN		 6958 if (unlikely(vcpu->arch.complete_userspace_io)) {
6959 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6960 vcpu->arch.complete_userspace_io = NULL;
6961 r = cui(vcpu);
6962 if (r <= 0)
6963 goto out;
6964 } else
6965 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6966
362c698f 6967 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6968
6969out:
f1d86e46 6970 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6971 if (vcpu->sigset_active)
6972 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6973
b6c7a5dc
HB		 6974 return r;
6975}
6976
6977int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6978{
7ae441ea
GN		 6979 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6980 /*
6981 * We are here if userspace calls get_regs() in the middle of
6982 * instruction emulation. Registers state needs to be copied
4a969980 6983 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6984 * that usually, but some bad designed PV devices (vmware
6985 * backdoor interface) need this to work
6986 */
dd856efa 6987 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6988 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6989 }
5fdbf976
MT		 6990 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6991 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6992 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6993 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6994 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6995 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6996 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6997 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6998#ifdef CONFIG_X86_64
5fdbf976
MT		 6999 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7000 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7001 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7002 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7003 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7004 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7005 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7006 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7007#endif
7008
5fdbf976 7009 regs->rip = kvm_rip_read(vcpu);
91586a3b 7010 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7011
b6c7a5dc
HB		 7012 return 0;
7013}
7014
7015int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7016{
7ae441ea
GN		 7017 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7018 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7019
5fdbf976
MT		 7020 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7021 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7022 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7023 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7024 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7025 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7026 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7027 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7028#ifdef CONFIG_X86_64
5fdbf976
MT		 7029 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7030 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7031 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7032 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7033 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7034 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7035 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7036 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7037#endif
7038
5fdbf976 7039 kvm_rip_write(vcpu, regs->rip);
91586a3b 7040 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7041
b4f14abd
JK		 7042 vcpu->arch.exception.pending = false;
7043
3842d135
AK		 7044 kvm_make_request(KVM_REQ_EVENT, vcpu);
7045
b6c7a5dc
HB		 7046 return 0;
7047}
7048
b6c7a5dc
HB		 7049void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7050{
7051 struct kvm_segment cs;
7052
3e6e0aab 7053 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7054 *db = cs.db;
7055 *l = cs.l;
7056}
7057EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7058
7059int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7060 struct kvm_sregs *sregs)
7061{
89a27f4d 7062 struct desc_ptr dt;
b6c7a5dc 7063
3e6e0aab
GT		 7064 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7065 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7066 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7067 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7068 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7069 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7070
3e6e0aab
GT		 7071 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7072 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7073
7074 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7075 sregs->idt.limit = dt.size;
7076 sregs->idt.base = dt.address;
b6c7a5dc 7077 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7078 sregs->gdt.limit = dt.size;
7079 sregs->gdt.base = dt.address;
b6c7a5dc 7080
4d4ec087 7081 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7082 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7083 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7084 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7085 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7086 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7087 sregs->apic_base = kvm_get_apic_base(vcpu);
7088
923c61bb 7089 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7090
36752c9b 7091 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7092 set_bit(vcpu->arch.interrupt.nr,
7093 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7094
b6c7a5dc
HB		 7095 return 0;
7096}
7097
62d9f0db
MT		 7098int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7099 struct kvm_mp_state *mp_state)
7100{
66450a21 7101 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7102 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7103 vcpu->arch.pv.pv_unhalted)
7104 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7105 else
7106 mp_state->mp_state = vcpu->arch.mp_state;
7107
62d9f0db
MT		 7108 return 0;
7109}
7110
7111int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7112 struct kvm_mp_state *mp_state)
7113{
bce87cce 7114 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7115 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7116 return -EINVAL;
7117
7118 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7119 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7120 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7121 } else
7122 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7123 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7124 return 0;
7125}
7126
7f3d35fd
KW		 7127int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7128 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7129{
9d74191a 7130 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7131 int ret;
e01c2426 7132
8ec4722d 7133 init_emulate_ctxt(vcpu);
c697518a 7134
7f3d35fd 7135 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7136 has_error_code, error_code);
c697518a 7137
c697518a 7138 if (ret)
19d04437 7139 return EMULATE_FAIL;
37817f29 7140
9d74191a
TY		 7141 kvm_rip_write(vcpu, ctxt->eip);
7142 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7143 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7144 return EMULATE_DONE;
37817f29
IE		 7145}
7146EXPORT_SYMBOL_GPL(kvm_task_switch);
7147
b6c7a5dc
HB		 7148int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7149 struct kvm_sregs *sregs)
7150{
58cb628d 7151 struct msr_data apic_base_msr;
b6c7a5dc 7152 int mmu_reset_needed = 0;
63f42e02 7153 int pending_vec, max_bits, idx;
89a27f4d 7154 struct desc_ptr dt;
b6c7a5dc 7155
6d1068b3
PM		 7156 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7157 return -EINVAL;
7158
89a27f4d
GN		 7159 dt.size = sregs->idt.limit;
7160 dt.address = sregs->idt.base;
b6c7a5dc 7161 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7162 dt.size = sregs->gdt.limit;
7163 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7164 kvm_x86_ops->set_gdt(vcpu, &dt);
7165
ad312c7c 7166 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7167 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7168 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7169 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7170
2d3ad1f4 7171 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7172
f6801dff 7173 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7174 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7175 apic_base_msr.data = sregs->apic_base;
7176 apic_base_msr.host_initiated = true;
7177 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7178
4d4ec087 7179 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7180 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7181 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7182
fc78f519 7183 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7184 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7185 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7186 kvm_update_cpuid(vcpu);
63f42e02
XG		 7187
7188 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7189 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7190 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7191 mmu_reset_needed = 1;
7192 }
63f42e02 7193 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7194
7195 if (mmu_reset_needed)
7196 kvm_mmu_reset_context(vcpu);
7197
a50abc3b 7198 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7199 pending_vec = find_first_bit(
7200 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7201 if (pending_vec < max_bits) {
66fd3f7f 7202 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7203 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7204 }
7205
3e6e0aab
GT		 7206 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7207 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7208 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7209 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7210 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7211 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7212
3e6e0aab
GT		 7213 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7214 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7215
5f0269f5
ME		 7216 update_cr8_intercept(vcpu);
7217
9c3e4aab 7218 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7219 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7220 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7221 !is_protmode(vcpu))
9c3e4aab
MT		 7222 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7223
3842d135
AK		 7224 kvm_make_request(KVM_REQ_EVENT, vcpu);
7225
b6c7a5dc
HB		 7226 return 0;
7227}
7228
d0bfb940
JK		 7229int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7230 struct kvm_guest_debug *dbg)
b6c7a5dc 7231{
355be0b9 7232 unsigned long rflags;
ae675ef0 7233 int i, r;
b6c7a5dc 7234
4f926bf2
JK		 7235 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7236 r = -EBUSY;
7237 if (vcpu->arch.exception.pending)
2122ff5e 7238 goto out;
4f926bf2
JK		 7239 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7240 kvm_queue_exception(vcpu, DB_VECTOR);
7241 else
7242 kvm_queue_exception(vcpu, BP_VECTOR);
7243 }
7244
91586a3b
JK		 7245 /*
7246 * Read rflags as long as potentially injected trace flags are still
7247 * filtered out.
7248 */
7249 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7250
7251 vcpu->guest_debug = dbg->control;
7252 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7253 vcpu->guest_debug = 0;
7254
7255 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7256 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7257 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7258 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7259 } else {
7260 for (i = 0; i < KVM_NR_DB_REGS; i++)
7261 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7262 }
c8639010 7263 kvm_update_dr7(vcpu);
ae675ef0 7264
f92653ee
JK		 7265 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7266 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7267 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7268
91586a3b
JK		 7269 /*
7270 * Trigger an rflags update that will inject or remove the trace
7271 * flags.
7272 */
7273 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7274
a96036b8 7275 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7276
4f926bf2 7277 r = 0;
d0bfb940 7278
2122ff5e 7279out:
b6c7a5dc
HB		 7280
7281 return r;
7282}
7283
8b006791
ZX		 7284/*
7285 * Translate a guest virtual address to a guest physical address.
7286 */
7287int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7288 struct kvm_translation *tr)
7289{
7290 unsigned long vaddr = tr->linear_address;
7291 gpa_t gpa;
f656ce01 7292 int idx;
8b006791 7293
f656ce01 7294 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7295 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7296 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7297 tr->physical_address = gpa;
7298 tr->valid = gpa != UNMAPPED_GVA;
7299 tr->writeable = 1;
7300 tr->usermode = 0;
8b006791
ZX		 7301
7302 return 0;
7303}
7304
d0752060
HB		 7305int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7306{
c47ada30 7307 struct fxregs_state *fxsave =
7366ed77 7308 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7309
d0752060
HB		 7310 memcpy(fpu->fpr, fxsave->st_space, 128);
7311 fpu->fcw = fxsave->cwd;
7312 fpu->fsw = fxsave->swd;
7313 fpu->ftwx = fxsave->twd;
7314 fpu->last_opcode = fxsave->fop;
7315 fpu->last_ip = fxsave->rip;
7316 fpu->last_dp = fxsave->rdp;
7317 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7318
d0752060
HB		 7319 return 0;
7320}
7321
7322int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7323{
c47ada30 7324 struct fxregs_state *fxsave =
7366ed77 7325 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7326
d0752060
HB		 7327 memcpy(fxsave->st_space, fpu->fpr, 128);
7328 fxsave->cwd = fpu->fcw;
7329 fxsave->swd = fpu->fsw;
7330 fxsave->twd = fpu->ftwx;
7331 fxsave->fop = fpu->last_opcode;
7332 fxsave->rip = fpu->last_ip;
7333 fxsave->rdp = fpu->last_dp;
7334 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7335
d0752060
HB		 7336 return 0;
7337}
7338
0ee6a517 7339static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7340{
bf935b0b 7341 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7342 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7343 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7344 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7345
2acf923e
DC		 7346 /*
7347 * Ensure guest xcr0 is valid for loading
7348 */
d91cab78 7349 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7350
ad312c7c 7351 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7352}
d0752060
HB		 7353
7354void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7355{
2608d7a1 7356 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7357 return;
7358
2acf923e
DC		 7359 /*
7360 * Restore all possible states in the guest,
7361 * and assume host would use all available bits.
7362 * Guest xcr0 would be loaded later.
7363 */
d0752060 7364 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7365 __kernel_fpu_begin();
003e2e8b 7366 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7367 trace_kvm_fpu(1);
d0752060 7368}
d0752060
HB		 7369
7370void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7371{
653f52c3
RR		 7372 if (!vcpu->guest_fpu_loaded) {
7373 vcpu->fpu_counter = 0;
d0752060 7374 return;
653f52c3 7375 }
d0752060
HB		 7376
7377 vcpu->guest_fpu_loaded = 0;
4f836347 7378 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7379 __kernel_fpu_end();
f096ed85 7380 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7381 /*
7382 * If using eager FPU mode, or if the guest is a frequent user
7383 * of the FPU, just leave the FPU active for next time.
7384 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7385 * the FPU in bursts will revert to loading it on demand.
7386 */
5a5fbdc0 7387 if (!use_eager_fpu()) {
653f52c3
RR		 7388 if (++vcpu->fpu_counter < 5)
7389 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7390 }
0c04851c 7391 trace_kvm_fpu(0);
d0752060 7392}
e9b11c17
ZX		 7393
7394void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7395{
12f9a48f 7396 kvmclock_reset(vcpu);
7f1ea208 7397
f5f48ee1 7398 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7399 kvm_x86_ops->vcpu_free(vcpu);
7400}
7401
7402struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7403 unsigned int id)
7404{
c447e76b
LL		 7405 struct kvm_vcpu *vcpu;
7406
6755bae8
ZA		 7407 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7408 printk_once(KERN_WARNING
7409 "kvm: SMP vm created on host with unstable TSC; "
7410 "guest TSC will not be reliable\n");
c447e76b
LL		 7411
7412 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7413
c447e76b 7414 return vcpu;
26e5215f 7415}
e9b11c17 7416
26e5215f
AK		 7417int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7418{
7419 int r;
e9b11c17 7420
19efffa2 7421 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7422 r = vcpu_load(vcpu);
7423 if (r)
7424 return r;
d28bc9dd 7425 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7426 kvm_mmu_setup(vcpu);
e9b11c17 7427 vcpu_put(vcpu);
26e5215f 7428 return r;
e9b11c17
ZX		 7429}
7430
31928aa5 7431void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7432{
8fe8ab46 7433 struct msr_data msr;
332967a3 7434 struct kvm *kvm = vcpu->kvm;
42897d86 7435
31928aa5
DD		 7436 if (vcpu_load(vcpu))
7437 return;
8fe8ab46
WA		 7438 msr.data = 0x0;
7439 msr.index = MSR_IA32_TSC;
7440 msr.host_initiated = true;
7441 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7442 vcpu_put(vcpu);
7443
630994b3
MT		 7444 if (!kvmclock_periodic_sync)
7445 return;
7446
332967a3
AJ		 7447 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7448 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7449}
7450
d40ccc62 7451void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7452{
9fc77441 7453 int r;
344d9588
GN		 7454 vcpu->arch.apf.msr_val = 0;
7455
9fc77441
MT		 7456 r = vcpu_load(vcpu);
7457 BUG_ON(r);
e9b11c17
ZX		 7458 kvm_mmu_unload(vcpu);
7459 vcpu_put(vcpu);
7460
7461 kvm_x86_ops->vcpu_free(vcpu);
7462}
7463
d28bc9dd 7464void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7465{
e69fab5d
PB		 7466 vcpu->arch.hflags = 0;
7467
c43203ca 7468 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7469 atomic_set(&vcpu->arch.nmi_queued, 0);
7470 vcpu->arch.nmi_pending = 0;
448fa4a9 7471 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7472 kvm_clear_interrupt_queue(vcpu);
7473 kvm_clear_exception_queue(vcpu);
448fa4a9 7474
42dbaa5a 7475 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7476 kvm_update_dr0123(vcpu);
6f43ed01 7477 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7478 kvm_update_dr6(vcpu);
42dbaa5a 7479 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7480 kvm_update_dr7(vcpu);
42dbaa5a 7481
1119022c
NA		 7482 vcpu->arch.cr2 = 0;
7483
3842d135 7484 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7485 vcpu->arch.apf.msr_val = 0;
c9aaa895 7486 vcpu->arch.st.msr_val = 0;
3842d135 7487
12f9a48f
GC		 7488 kvmclock_reset(vcpu);
7489
af585b92
GN		 7490 kvm_clear_async_pf_completion_queue(vcpu);
7491 kvm_async_pf_hash_reset(vcpu);
7492 vcpu->arch.apf.halted = false;
3842d135 7493
64d60670 7494 if (!init_event) {
d28bc9dd 7495 kvm_pmu_reset(vcpu);
64d60670
PB		 7496 vcpu->arch.smbase = 0x30000;
7497 }
f5132b01 7498
66f7b72e
JS		 7499 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7500 vcpu->arch.regs_avail = ~0;
7501 vcpu->arch.regs_dirty = ~0;
7502
d28bc9dd 7503 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7504}
7505
2b4a273b 7506void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7507{
7508 struct kvm_segment cs;
7509
7510 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7511 cs.selector = vector << 8;
7512 cs.base = vector << 12;
7513 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7514 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7515}
7516
13a34e06 7517int kvm_arch_hardware_enable(void)
e9b11c17 7518{
ca84d1a2
ZA		 7519 struct kvm *kvm;
7520 struct kvm_vcpu *vcpu;
7521 int i;
0dd6a6ed
ZA		 7522 int ret;
7523 u64 local_tsc;
7524 u64 max_tsc = 0;
7525 bool stable, backwards_tsc = false;
18863bdd
AK		 7526
7527 kvm_shared_msr_cpu_online();
13a34e06 7528 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7529 if (ret != 0)
7530 return ret;
7531
4ea1636b 7532 local_tsc = rdtsc();
0dd6a6ed
ZA		 7533 stable = !check_tsc_unstable();
7534 list_for_each_entry(kvm, &vm_list, vm_list) {
7535 kvm_for_each_vcpu(i, vcpu, kvm) {
7536 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7537 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7538 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7539 backwards_tsc = true;
7540 if (vcpu->arch.last_host_tsc > max_tsc)
7541 max_tsc = vcpu->arch.last_host_tsc;
7542 }
7543 }
7544 }
7545
7546 /*
7547 * Sometimes, even reliable TSCs go backwards. This happens on
7548 * platforms that reset TSC during suspend or hibernate actions, but
7549 * maintain synchronization. We must compensate. Fortunately, we can
7550 * detect that condition here, which happens early in CPU bringup,
7551 * before any KVM threads can be running. Unfortunately, we can't
7552 * bring the TSCs fully up to date with real time, as we aren't yet far
7553 * enough into CPU bringup that we know how much real time has actually
7554 * elapsed; our helper function, get_kernel_ns() will be using boot
7555 * variables that haven't been updated yet.
7556 *
7557 * So we simply find the maximum observed TSC above, then record the
7558 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7559 * the adjustment will be applied. Note that we accumulate
7560 * adjustments, in case multiple suspend cycles happen before some VCPU
7561 * gets a chance to run again. In the event that no KVM threads get a
7562 * chance to run, we will miss the entire elapsed period, as we'll have
7563 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7564 * loose cycle time. This isn't too big a deal, since the loss will be
7565 * uniform across all VCPUs (not to mention the scenario is extremely
7566 * unlikely). It is possible that a second hibernate recovery happens
7567 * much faster than a first, causing the observed TSC here to be
7568 * smaller; this would require additional padding adjustment, which is
7569 * why we set last_host_tsc to the local tsc observed here.
7570 *
7571 * N.B. - this code below runs only on platforms with reliable TSC,
7572 * as that is the only way backwards_tsc is set above. Also note
7573 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7574 * have the same delta_cyc adjustment applied if backwards_tsc
7575 * is detected. Note further, this adjustment is only done once,
7576 * as we reset last_host_tsc on all VCPUs to stop this from being
7577 * called multiple times (one for each physical CPU bringup).
7578 *
4a969980 7579 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7580 * will be compensated by the logic in vcpu_load, which sets the TSC to
7581 * catchup mode. This will catchup all VCPUs to real time, but cannot
7582 * guarantee that they stay in perfect synchronization.
7583 */
7584 if (backwards_tsc) {
7585 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7586 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7587 list_for_each_entry(kvm, &vm_list, vm_list) {
7588 kvm_for_each_vcpu(i, vcpu, kvm) {
7589 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7590 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7591 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7592 }
7593
7594 /*
7595 * We have to disable TSC offset matching.. if you were
7596 * booting a VM while issuing an S4 host suspend....
7597 * you may have some problem. Solving this issue is
7598 * left as an exercise to the reader.
7599 */
7600 kvm->arch.last_tsc_nsec = 0;
7601 kvm->arch.last_tsc_write = 0;
7602 }
7603
7604 }
7605 return 0;
e9b11c17
ZX		 7606}
7607
13a34e06 7608void kvm_arch_hardware_disable(void)
e9b11c17 7609{
13a34e06
RK		 7610 kvm_x86_ops->hardware_disable();
7611 drop_user_return_notifiers();
e9b11c17
ZX		 7612}
7613
7614int kvm_arch_hardware_setup(void)
7615{
9e9c3fe4
NA		 7616 int r;
7617
7618 r = kvm_x86_ops->hardware_setup();
7619 if (r != 0)
7620 return r;
7621
35181e86
HZ		 7622 if (kvm_has_tsc_control) {
7623 /*
7624 * Make sure the user can only configure tsc_khz values that
7625 * fit into a signed integer.
7626 * A min value is not calculated needed because it will always
7627 * be 1 on all machines.
7628 */
7629 u64 max = min(0x7fffffffULL,
7630 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7631 kvm_max_guest_tsc_khz = max;
7632
ad721883 7633 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7634 }
ad721883 7635
9e9c3fe4
NA		 7636 kvm_init_msr_list();
7637 return 0;
e9b11c17
ZX		 7638}
7639
7640void kvm_arch_hardware_unsetup(void)
7641{
7642 kvm_x86_ops->hardware_unsetup();
7643}
7644
7645void kvm_arch_check_processor_compat(void *rtn)
7646{
7647 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7648}
7649
7650bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7651{
7652 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7653}
7654EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7655
7656bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7657{
7658 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7659}
7660
54e9818f 7661struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7662EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7663
e9b11c17
ZX		 7664int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7665{
7666 struct page *page;
7667 struct kvm *kvm;
7668 int r;
7669
7670 BUG_ON(vcpu->kvm == NULL);
7671 kvm = vcpu->kvm;
7672
d62caabb 7673 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7674 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7675 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7676 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7677 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7678 else
a4535290 7679 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7680
7681 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7682 if (!page) {
7683 r = -ENOMEM;
7684 goto fail;
7685 }
ad312c7c 7686 vcpu->arch.pio_data = page_address(page);
e9b11c17 7687
cc578287 7688 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7689
e9b11c17
ZX		 7690 r = kvm_mmu_create(vcpu);
7691 if (r < 0)
7692 goto fail_free_pio_data;
7693
7694 if (irqchip_in_kernel(kvm)) {
7695 r = kvm_create_lapic(vcpu);
7696 if (r < 0)
7697 goto fail_mmu_destroy;
54e9818f
GN		 7698 } else
7699 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7700
890ca9ae
HY		 7701 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7702 GFP_KERNEL);
7703 if (!vcpu->arch.mce_banks) {
7704 r = -ENOMEM;
443c39bc 7705 goto fail_free_lapic;
890ca9ae
HY		 7706 }
7707 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7708
f1797359
WY		 7709 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7710 r = -ENOMEM;
f5f48ee1 7711 goto fail_free_mce_banks;
f1797359 7712 }
f5f48ee1 7713
0ee6a517 7714 fx_init(vcpu);
66f7b72e 7715
ba904635 7716 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7717 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7718
7719 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7720 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7721
5a4f55cd
EK		 7722 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7723
74545705
RK		 7724 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7725
af585b92 7726 kvm_async_pf_hash_reset(vcpu);
f5132b01 7727 kvm_pmu_init(vcpu);
af585b92 7728
1c1a9ce9
SR		 7729 vcpu->arch.pending_external_vector = -1;
7730
5c919412
AS		 7731 kvm_hv_vcpu_init(vcpu);
7732
e9b11c17 7733 return 0;
0ee6a517 7734
f5f48ee1
SY		 7735fail_free_mce_banks:
7736 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7737fail_free_lapic:
7738 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7739fail_mmu_destroy:
7740 kvm_mmu_destroy(vcpu);
7741fail_free_pio_data:
ad312c7c 7742 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7743fail:
7744 return r;
7745}
7746
7747void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7748{
f656ce01
MT		 7749 int idx;
7750
1f4b34f8 7751 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7752 kvm_pmu_destroy(vcpu);
36cb93fd 7753 kfree(vcpu->arch.mce_banks);
e9b11c17 7754 kvm_free_lapic(vcpu);
f656ce01 7755 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7756 kvm_mmu_destroy(vcpu);
f656ce01 7757 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7758 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7759 if (!lapic_in_kernel(vcpu))
54e9818f 7760 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7761}
d19a9cd2 7762
e790d9ef
RK		 7763void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7764{
ae97a3b8 7765 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7766}
7767
e08b9637 7768int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7769{
e08b9637
CO		 7770 if (type)
7771 return -EINVAL;
7772
6ef768fa 7773 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7774 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7775 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7776 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7777 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7778
5550af4d
SY		 7779 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7780 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7781 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7782 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7783 &kvm->arch.irq_sources_bitmap);
5550af4d 7784
038f8c11 7785 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7786 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7787 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7788
7789 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7790
7e44e449 7791 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7792 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7793
0eb05bf2 7794 kvm_page_track_init(kvm);
13d268ca 7795 kvm_mmu_init_vm(kvm);
0eb05bf2 7796
03543133
SS		 7797 if (kvm_x86_ops->vm_init)
7798 return kvm_x86_ops->vm_init(kvm);
7799
d89f5eff 7800 return 0;
d19a9cd2
ZX		 7801}
7802
7803static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7804{
9fc77441
MT		 7805 int r;
7806 r = vcpu_load(vcpu);
7807 BUG_ON(r);
d19a9cd2
ZX		 7808 kvm_mmu_unload(vcpu);
7809 vcpu_put(vcpu);
7810}
7811
7812static void kvm_free_vcpus(struct kvm *kvm)
7813{
7814 unsigned int i;
988a2cae 7815 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7816
7817 /*
7818 * Unpin any mmu pages first.
7819 */
af585b92
GN		 7820 kvm_for_each_vcpu(i, vcpu, kvm) {
7821 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7822 kvm_unload_vcpu_mmu(vcpu);
af585b92 7823 }
988a2cae
GN		 7824 kvm_for_each_vcpu(i, vcpu, kvm)
7825 kvm_arch_vcpu_free(vcpu);
7826
7827 mutex_lock(&kvm->lock);
7828 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7829 kvm->vcpus[i] = NULL;
d19a9cd2 7830
988a2cae
GN		 7831 atomic_set(&kvm->online_vcpus, 0);
7832 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7833}
7834
ad8ba2cd
SY		 7835void kvm_arch_sync_events(struct kvm *kvm)
7836{
332967a3 7837 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7838 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7839 kvm_free_all_assigned_devices(kvm);
aea924f6 7840 kvm_free_pit(kvm);
ad8ba2cd
SY		 7841}
7842
1d8007bd 7843int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7844{
7845 int i, r;
25188b99 7846 unsigned long hva;
f0d648bd
PB		 7847 struct kvm_memslots *slots = kvm_memslots(kvm);
7848 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7849
7850 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7851 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7852 return -EINVAL;
9da0e4d5 7853
f0d648bd
PB		 7854 slot = id_to_memslot(slots, id);
7855 if (size) {
b21629da 7856 if (slot->npages)
f0d648bd
PB		 7857 return -EEXIST;
7858
7859 /*
7860 * MAP_SHARED to prevent internal slot pages from being moved
7861 * by fork()/COW.
7862 */
7863 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7864 MAP_SHARED | MAP_ANONYMOUS, 0);
7865 if (IS_ERR((void *)hva))
7866 return PTR_ERR((void *)hva);
7867 } else {
7868 if (!slot->npages)
7869 return 0;
7870
7871 hva = 0;
7872 }
7873
7874 old = *slot;
9da0e4d5 7875 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7876 struct kvm_userspace_memory_region m;
9da0e4d5 7877
1d8007bd
PB		 7878 m.slot = id | (i << 16);
7879 m.flags = 0;
7880 m.guest_phys_addr = gpa;
f0d648bd 7881 m.userspace_addr = hva;
1d8007bd 7882 m.memory_size = size;
9da0e4d5
PB		 7883 r = __kvm_set_memory_region(kvm, &m);
7884 if (r < 0)
7885 return r;
7886 }
7887
f0d648bd
PB		 7888 if (!size) {
7889 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7890 WARN_ON(r < 0);
7891 }
7892
9da0e4d5
PB		 7893 return 0;
7894}
7895EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7896
1d8007bd 7897int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7898{
7899 int r;
7900
7901 mutex_lock(&kvm->slots_lock);
1d8007bd 7902 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7903 mutex_unlock(&kvm->slots_lock);
7904
7905 return r;
7906}
7907EXPORT_SYMBOL_GPL(x86_set_memory_region);
7908
d19a9cd2
ZX		 7909void kvm_arch_destroy_vm(struct kvm *kvm)
7910{
27469d29
AH		 7911 if (current->mm == kvm->mm) {
7912 /*
7913 * Free memory regions allocated on behalf of userspace,
7914 * unless the the memory map has changed due to process exit
7915 * or fd copying.
7916 */
1d8007bd
PB		 7917 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7918 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7919 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7920 }
03543133
SS		 7921 if (kvm_x86_ops->vm_destroy)
7922 kvm_x86_ops->vm_destroy(kvm);
6eb55818 7923 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7924 kfree(kvm->arch.vpic);
7925 kfree(kvm->arch.vioapic);
d19a9cd2 7926 kvm_free_vcpus(kvm);
1e08ec4a 7927 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7928 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7929}
0de10343 7930
5587027c 7931void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7932 struct kvm_memory_slot *dont)
7933{
7934 int i;
7935
d89cc617
TY		 7936 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7937 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7938 kvfree(free->arch.rmap[i]);
d89cc617 7939 free->arch.rmap[i] = NULL;
77d11309 7940 }
d89cc617
TY		 7941 if (i == 0)
7942 continue;
7943
7944 if (!dont || free->arch.lpage_info[i - 1] !=
7945 dont->arch.lpage_info[i - 1]) {
548ef284 7946 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7947 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7948 }
7949 }
21ebbeda
XG		 7950
7951 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7952}
7953
5587027c
AK		 7954int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7955 unsigned long npages)
db3fe4eb
TY		 7956{
7957 int i;
7958
d89cc617 7959 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7960 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7961 unsigned long ugfn;
7962 int lpages;
d89cc617 7963 int level = i + 1;
db3fe4eb
TY		 7964
7965 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7966 slot->base_gfn, level) + 1;
7967
d89cc617
TY		 7968 slot->arch.rmap[i] =
7969 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7970 if (!slot->arch.rmap[i])
77d11309 7971 goto out_free;
d89cc617
TY		 7972 if (i == 0)
7973 continue;
77d11309 7974
92f94f1e
XG		 7975 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7976 if (!linfo)
db3fe4eb
TY		 7977 goto out_free;
7978
92f94f1e
XG		 7979 slot->arch.lpage_info[i - 1] = linfo;
7980
db3fe4eb 7981 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7982 linfo[0].disallow_lpage = 1;
db3fe4eb 7983 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7984 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7985 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7986 /*
7987 * If the gfn and userspace address are not aligned wrt each
7988 * other, or if explicitly asked to, disable large page
7989 * support for this slot
7990 */
7991 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7992 !kvm_largepages_enabled()) {
7993 unsigned long j;
7994
7995 for (j = 0; j < lpages; ++j)
92f94f1e 7996 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7997 }
7998 }
7999
21ebbeda
XG		 8000 if (kvm_page_track_create_memslot(slot, npages))
8001 goto out_free;
8002
db3fe4eb
TY		 8003 return 0;
8004
8005out_free:
d89cc617 8006 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8007 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8008 slot->arch.rmap[i] = NULL;
8009 if (i == 0)
8010 continue;
8011
548ef284 8012 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8013 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8014 }
8015 return -ENOMEM;
8016}
8017
15f46015 8018void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8019{
e6dff7d1
TY		 8020 /*
8021 * memslots->generation has been incremented.
8022 * mmio generation may have reached its maximum value.
8023 */
54bf36aa 8024 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8025}
8026
f7784b8e
MT		 8027int kvm_arch_prepare_memory_region(struct kvm *kvm,
8028 struct kvm_memory_slot *memslot,
09170a49 8029 const struct kvm_userspace_memory_region *mem,
7b6195a9 8030 enum kvm_mr_change change)
0de10343 8031{
f7784b8e
MT		 8032 return 0;
8033}
8034
88178fd4
KH		 8035static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8036 struct kvm_memory_slot *new)
8037{
8038 /* Still write protect RO slot */
8039 if (new->flags & KVM_MEM_READONLY) {
8040 kvm_mmu_slot_remove_write_access(kvm, new);
8041 return;
8042 }
8043
8044 /*
8045 * Call kvm_x86_ops dirty logging hooks when they are valid.
8046 *
8047 * kvm_x86_ops->slot_disable_log_dirty is called when:
8048 *
8049 * - KVM_MR_CREATE with dirty logging is disabled
8050 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8051 *
8052 * The reason is, in case of PML, we need to set D-bit for any slots
8053 * with dirty logging disabled in order to eliminate unnecessary GPA
8054 * logging in PML buffer (and potential PML buffer full VMEXT). This
8055 * guarantees leaving PML enabled during guest's lifetime won't have
8056 * any additonal overhead from PML when guest is running with dirty
8057 * logging disabled for memory slots.
8058 *
8059 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8060 * to dirty logging mode.
8061 *
8062 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8063 *
8064 * In case of write protect:
8065 *
8066 * Write protect all pages for dirty logging.
8067 *
8068 * All the sptes including the large sptes which point to this
8069 * slot are set to readonly. We can not create any new large
8070 * spte on this slot until the end of the logging.
8071 *
8072 * See the comments in fast_page_fault().
8073 */
8074 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8075 if (kvm_x86_ops->slot_enable_log_dirty)
8076 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8077 else
8078 kvm_mmu_slot_remove_write_access(kvm, new);
8079 } else {
8080 if (kvm_x86_ops->slot_disable_log_dirty)
8081 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8082 }
8083}
8084
f7784b8e 8085void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8086 const struct kvm_userspace_memory_region *mem,
8482644a 8087 const struct kvm_memory_slot *old,
f36f3f28 8088 const struct kvm_memory_slot *new,
8482644a 8089 enum kvm_mr_change change)
f7784b8e 8090{
8482644a 8091 int nr_mmu_pages = 0;
f7784b8e 8092
48c0e4e9
XG		 8093 if (!kvm->arch.n_requested_mmu_pages)
8094 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8095
48c0e4e9 8096 if (nr_mmu_pages)
0de10343 8097 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8098
3ea3b7fa
WL		 8099 /*
8100 * Dirty logging tracks sptes in 4k granularity, meaning that large
8101 * sptes have to be split. If live migration is successful, the guest
8102 * in the source machine will be destroyed and large sptes will be
8103 * created in the destination. However, if the guest continues to run
8104 * in the source machine (for example if live migration fails), small
8105 * sptes will remain around and cause bad performance.
8106 *
8107 * Scan sptes if dirty logging has been stopped, dropping those
8108 * which can be collapsed into a single large-page spte. Later
8109 * page faults will create the large-page sptes.
8110 */
8111 if ((change != KVM_MR_DELETE) &&
8112 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8113 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8114 kvm_mmu_zap_collapsible_sptes(kvm, new);
8115
c972f3b1 8116 /*
88178fd4 8117 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8118 *
88178fd4
KH		 8119 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8120 * been zapped so no dirty logging staff is needed for old slot. For
8121 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8122 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8123 *
8124 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8125 */
88178fd4 8126 if (change != KVM_MR_DELETE)
f36f3f28 8127 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8128}
1d737c8a 8129
2df72e9b 8130void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8131{
6ca18b69 8132 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8133}
8134
2df72e9b
MT		 8135void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8136 struct kvm_memory_slot *slot)
8137{
6ca18b69 8138 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8139}
8140
5d9bc648
PB		 8141static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8142{
8143 if (!list_empty_careful(&vcpu->async_pf.done))
8144 return true;
8145
8146 if (kvm_apic_has_events(vcpu))
8147 return true;
8148
8149 if (vcpu->arch.pv.pv_unhalted)
8150 return true;
8151
8152 if (atomic_read(&vcpu->arch.nmi_queued))
8153 return true;
8154
73917739
PB		 8155 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8156 return true;
8157
5d9bc648
PB		 8158 if (kvm_arch_interrupt_allowed(vcpu) &&
8159 kvm_cpu_has_interrupt(vcpu))
8160 return true;
8161
1f4b34f8
AS		 8162 if (kvm_hv_has_stimer_pending(vcpu))
8163 return true;
8164
5d9bc648
PB		 8165 return false;
8166}
8167
1d737c8a
ZX		 8168int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8169{
b6b8a145
JK		 8170 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8171 kvm_x86_ops->check_nested_events(vcpu, false);
8172
5d9bc648 8173 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8174}
5736199a 8175
b6d33834 8176int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8177{
b6d33834 8178 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8179}
78646121
GN		 8180
8181int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8182{
8183 return kvm_x86_ops->interrupt_allowed(vcpu);
8184}
229456fc 8185
82b32774 8186unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8187{
82b32774
NA		 8188 if (is_64_bit_mode(vcpu))
8189 return kvm_rip_read(vcpu);
8190 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8191 kvm_rip_read(vcpu));
8192}
8193EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8194
82b32774
NA		 8195bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8196{
8197 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8198}
8199EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8200
94fe45da
JK		 8201unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8202{
8203 unsigned long rflags;
8204
8205 rflags = kvm_x86_ops->get_rflags(vcpu);
8206 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8207 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8208 return rflags;
8209}
8210EXPORT_SYMBOL_GPL(kvm_get_rflags);
8211
6addfc42 8212static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8213{
8214 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8215 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8216 rflags |= X86_EFLAGS_TF;
94fe45da 8217 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8218}
8219
8220void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8221{
8222 __kvm_set_rflags(vcpu, rflags);
3842d135 8223 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8224}
8225EXPORT_SYMBOL_GPL(kvm_set_rflags);
8226
56028d08
GN		 8227void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8228{
8229 int r;
8230
fb67e14f 8231 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8232 work->wakeup_all)
56028d08
GN		 8233 return;
8234
8235 r = kvm_mmu_reload(vcpu);
8236 if (unlikely(r))
8237 return;
8238
fb67e14f
XG		 8239 if (!vcpu->arch.mmu.direct_map &&
8240 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8241 return;
8242
56028d08
GN		 8243 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8244}
8245
af585b92
GN		 8246static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8247{
8248 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8249}
8250
8251static inline u32 kvm_async_pf_next_probe(u32 key)
8252{
8253 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8254}
8255
8256static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8257{
8258 u32 key = kvm_async_pf_hash_fn(gfn);
8259
8260 while (vcpu->arch.apf.gfns[key] != ~0)
8261 key = kvm_async_pf_next_probe(key);
8262
8263 vcpu->arch.apf.gfns[key] = gfn;
8264}
8265
8266static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8267{
8268 int i;
8269 u32 key = kvm_async_pf_hash_fn(gfn);
8270
8271 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8272 (vcpu->arch.apf.gfns[key] != gfn &&
8273 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8274 key = kvm_async_pf_next_probe(key);
8275
8276 return key;
8277}
8278
8279bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8280{
8281 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8282}
8283
8284static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8285{
8286 u32 i, j, k;
8287
8288 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8289 while (true) {
8290 vcpu->arch.apf.gfns[i] = ~0;
8291 do {
8292 j = kvm_async_pf_next_probe(j);
8293 if (vcpu->arch.apf.gfns[j] == ~0)
8294 return;
8295 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8296 /*
8297 * k lies cyclically in ]i,j]
8298 * | i.k.j |
8299 * |....j i.k.| or |.k..j i...|
8300 */
8301 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8302 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8303 i = j;
8304 }
8305}
8306
7c90705b
GN		 8307static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8308{
8309
8310 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8311 sizeof(val));
8312}
8313
af585b92
GN		 8314void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8315 struct kvm_async_pf *work)
8316{
6389ee94
AK		 8317 struct x86_exception fault;
8318
7c90705b 8319 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8320 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8321
8322 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8323 (vcpu->arch.apf.send_user_only &&
8324 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8325 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8326 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8327 fault.vector = PF_VECTOR;
8328 fault.error_code_valid = true;
8329 fault.error_code = 0;
8330 fault.nested_page_fault = false;
8331 fault.address = work->arch.token;
8332 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8333 }
af585b92
GN		 8334}
8335
8336void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8337 struct kvm_async_pf *work)
8338{
6389ee94
AK		 8339 struct x86_exception fault;
8340
7c90705b 8341 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8342 if (work->wakeup_all)
7c90705b
GN		 8343 work->arch.token = ~0; /* broadcast wakeup */
8344 else
8345 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8346
8347 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8348 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8349 fault.vector = PF_VECTOR;
8350 fault.error_code_valid = true;
8351 fault.error_code = 0;
8352 fault.nested_page_fault = false;
8353 fault.address = work->arch.token;
8354 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8355 }
e6d53e3b 8356 vcpu->arch.apf.halted = false;
a4fa1635 8357 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8358}
8359
8360bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8361{
8362 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8363 return true;
8364 else
8365 return !kvm_event_needs_reinjection(vcpu) &&
8366 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8367}
8368
5544eb9b
PB		 8369void kvm_arch_start_assignment(struct kvm *kvm)
8370{
8371 atomic_inc(&kvm->arch.assigned_device_count);
8372}
8373EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8374
8375void kvm_arch_end_assignment(struct kvm *kvm)
8376{
8377 atomic_dec(&kvm->arch.assigned_device_count);
8378}
8379EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8380
8381bool kvm_arch_has_assigned_device(struct kvm *kvm)
8382{
8383 return atomic_read(&kvm->arch.assigned_device_count);
8384}
8385EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8386
e0f0bbc5
AW		 8387void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8388{
8389 atomic_inc(&kvm->arch.noncoherent_dma_count);
8390}
8391EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8392
8393void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8394{
8395 atomic_dec(&kvm->arch.noncoherent_dma_count);
8396}
8397EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8398
8399bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8400{
8401 return atomic_read(&kvm->arch.noncoherent_dma_count);
8402}
8403EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8404
14717e20
AW		 8405bool kvm_arch_has_irq_bypass(void)
8406{
8407 return kvm_x86_ops->update_pi_irte != NULL;
8408}
8409
87276880
FW		 8410int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8411 struct irq_bypass_producer *prod)
8412{
8413 struct kvm_kernel_irqfd *irqfd =
8414 container_of(cons, struct kvm_kernel_irqfd, consumer);
8415
14717e20 8416 irqfd->producer = prod;
87276880 8417
14717e20
AW		 8418 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8419 prod->irq, irqfd->gsi, 1);
87276880
FW		 8420}
8421
8422void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8423 struct irq_bypass_producer *prod)
8424{
8425 int ret;
8426 struct kvm_kernel_irqfd *irqfd =
8427 container_of(cons, struct kvm_kernel_irqfd, consumer);
8428
87276880
FW		 8429 WARN_ON(irqfd->producer != prod);
8430 irqfd->producer = NULL;
8431
8432 /*
8433 * When producer of consumer is unregistered, we change back to
8434 * remapped mode, so we can re-use the current implementation
bb3541f1 8435 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8436 * int this case doesn't want to receive the interrupts.
8437 */
8438 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8439 if (ret)
8440 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8441 " fails: %d\n", irqfd->consumer.token, ret);
8442}
8443
8444int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8445 uint32_t guest_irq, bool set)
8446{
8447 if (!kvm_x86_ops->update_pi_irte)
8448 return -EINVAL;
8449
8450 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8451}
8452
52004014
FW		 8453bool kvm_vector_hashing_enabled(void)
8454{
8455 return vector_hashing;
8456}
8457EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8458
229456fc 8459EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8460EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8461EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8462EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8463EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8464EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8465EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8466EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8467EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8468EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8469EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8470EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8471EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8472EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8473EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8474EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8475EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8476EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8477EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)