projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: Do not migrate pending software interrupts.
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
043405e1
CO		 40
41#include <asm/uaccess.h>
d825ed0a 42#include <asm/msr.h>
a5f61300 43#include <asm/desc.h>
0bed3b56 44#include <asm/mtrr.h>
043405e1 45
313a3dc7 46#define MAX_IO_MSRS 256
a03490ed
CO		 47#define CR0_RESERVED_BITS \
48 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
49 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
50 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
51#define CR4_RESERVED_BITS \
52 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
53 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
54 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
55 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
56
57#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 58/* EFER defaults:
59 * - enable syscall per default because its emulated by KVM
60 * - enable LME and LMA per default on 64 bit KVM
61 */
62#ifdef CONFIG_X86_64
63static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
64#else
65static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
66#endif
313a3dc7 67
ba1389b7
AK		 68#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
69#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 70
674eea0f
AK		 71static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
72 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 73struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
74 u32 function, u32 index);
674eea0f 75
97896d04 76struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 77EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 78
417bc304 79struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 80 { "pf_fixed", VCPU_STAT(pf_fixed) },
81 { "pf_guest", VCPU_STAT(pf_guest) },
82 { "tlb_flush", VCPU_STAT(tlb_flush) },
83 { "invlpg", VCPU_STAT(invlpg) },
84 { "exits", VCPU_STAT(exits) },
85 { "io_exits", VCPU_STAT(io_exits) },
86 { "mmio_exits", VCPU_STAT(mmio_exits) },
87 { "signal_exits", VCPU_STAT(signal_exits) },
88 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 89 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 90 { "halt_exits", VCPU_STAT(halt_exits) },
91 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 92 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 93 { "request_irq", VCPU_STAT(request_irq_exits) },
94 { "irq_exits", VCPU_STAT(irq_exits) },
95 { "host_state_reload", VCPU_STAT(host_state_reload) },
96 { "efer_reload", VCPU_STAT(efer_reload) },
97 { "fpu_reload", VCPU_STAT(fpu_reload) },
98 { "insn_emulation", VCPU_STAT(insn_emulation) },
99 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 100 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 101 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 102 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
103 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
104 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
105 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
106 { "mmu_flooded", VM_STAT(mmu_flooded) },
107 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 108 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 109 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 110 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 111 { "largepages", VM_STAT(lpages) },
417bc304
HB		 112 { NULL }
113};
114
5fb76f9b
CO		 115unsigned long segment_base(u16 selector)
116{
117 struct descriptor_table gdt;
a5f61300 118 struct desc_struct *d;
5fb76f9b
CO		 119 unsigned long table_base;
120 unsigned long v;
121
122 if (selector == 0)
123 return 0;
124
125 asm("sgdt %0" : "=m"(gdt));
126 table_base = gdt.base;
127
128 if (selector & 4) { /* from ldt */
129 u16 ldt_selector;
130
131 asm("sldt %0" : "=g"(ldt_selector));
132 table_base = segment_base(ldt_selector);
133 }
a5f61300
AK		 134 d = (struct desc_struct *)(table_base + (selector & ~7));
135 v = d->base0 | ((unsigned long)d->base1 << 16) |
136 ((unsigned long)d->base2 << 24);
5fb76f9b 137#ifdef CONFIG_X86_64
a5f61300
AK		 138 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
139 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 140#endif
141 return v;
142}
143EXPORT_SYMBOL_GPL(segment_base);
144
6866b83e
CO		 145u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
146{
147 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 148 return vcpu->arch.apic_base;
6866b83e 149 else
ad312c7c 150 return vcpu->arch.apic_base;
6866b83e
CO		 151}
152EXPORT_SYMBOL_GPL(kvm_get_apic_base);
153
154void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
155{
156 /* TODO: reserve bits check */
157 if (irqchip_in_kernel(vcpu->kvm))
158 kvm_lapic_set_base(vcpu, data);
159 else
ad312c7c 160 vcpu->arch.apic_base = data;
6866b83e
CO		 161}
162EXPORT_SYMBOL_GPL(kvm_set_apic_base);
163
298101da
AK		 164void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
165{
ad312c7c
ZX		 166 WARN_ON(vcpu->arch.exception.pending);
167 vcpu->arch.exception.pending = true;
168 vcpu->arch.exception.has_error_code = false;
169 vcpu->arch.exception.nr = nr;
298101da
AK		 170}
171EXPORT_SYMBOL_GPL(kvm_queue_exception);
172
c3c91fee
AK		 173void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
174 u32 error_code)
175{
176 ++vcpu->stat.pf_guest;
d8017474 177
71c4dfaf
JR		 178 if (vcpu->arch.exception.pending) {
179 if (vcpu->arch.exception.nr == PF_VECTOR) {
180 printk(KERN_DEBUG "kvm: inject_page_fault:"
181 " double fault 0x%lx\n", addr);
182 vcpu->arch.exception.nr = DF_VECTOR;
183 vcpu->arch.exception.error_code = 0;
184 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
185 /* triple fault -> shutdown */
186 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
187 }
c3c91fee
AK		 188 return;
189 }
ad312c7c 190 vcpu->arch.cr2 = addr;
c3c91fee
AK		 191 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
192}
193
3419ffc8
SY		 194void kvm_inject_nmi(struct kvm_vcpu *vcpu)
195{
196 vcpu->arch.nmi_pending = 1;
197}
198EXPORT_SYMBOL_GPL(kvm_inject_nmi);
199
298101da
AK		 200void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
201{
ad312c7c
ZX		 202 WARN_ON(vcpu->arch.exception.pending);
203 vcpu->arch.exception.pending = true;
204 vcpu->arch.exception.has_error_code = true;
205 vcpu->arch.exception.nr = nr;
206 vcpu->arch.exception.error_code = error_code;
298101da
AK		 207}
208EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
209
210static void __queue_exception(struct kvm_vcpu *vcpu)
211{
ad312c7c
ZX		 212 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
213 vcpu->arch.exception.has_error_code,
214 vcpu->arch.exception.error_code);
298101da
AK		 215}
216
a03490ed
CO		 217/*
218 * Load the pae pdptrs. Return true is they are all valid.
219 */
220int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
221{
222 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
223 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
224 int i;
225 int ret;
ad312c7c 226 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 227
a03490ed
CO		 228 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
229 offset * sizeof(u64), sizeof(pdpte));
230 if (ret < 0) {
231 ret = 0;
232 goto out;
233 }
234 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
20c466b5
DE		 235 if (is_present_pte(pdpte[i]) &&
236 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 237 ret = 0;
238 goto out;
239 }
240 }
241 ret = 1;
242
ad312c7c 243 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 244out:
a03490ed
CO		 245
246 return ret;
247}
cc4b6871 248EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 249
d835dfec
AK		 250static bool pdptrs_changed(struct kvm_vcpu *vcpu)
251{
ad312c7c 252 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 253 bool changed = true;
254 int r;
255
256 if (is_long_mode(vcpu) || !is_pae(vcpu))
257 return false;
258
ad312c7c 259 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 260 if (r < 0)
261 goto out;
ad312c7c 262 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 263out:
d835dfec
AK		 264
265 return changed;
266}
267
2d3ad1f4 268void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 269{
270 if (cr0 & CR0_RESERVED_BITS) {
271 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 272 cr0, vcpu->arch.cr0);
c1a5d4f9 273 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 274 return;
275 }
276
277 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
278 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 279 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 280 return;
281 }
282
283 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
284 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
285 "and a clear PE flag\n");
c1a5d4f9 286 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 287 return;
288 }
289
290 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
291#ifdef CONFIG_X86_64
ad312c7c 292 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 293 int cs_db, cs_l;
294
295 if (!is_pae(vcpu)) {
296 printk(KERN_DEBUG "set_cr0: #GP, start paging "
297 "in long mode while PAE is disabled\n");
c1a5d4f9 298 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 299 return;
300 }
301 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
302 if (cs_l) {
303 printk(KERN_DEBUG "set_cr0: #GP, start paging "
304 "in long mode while CS.L == 1\n");
c1a5d4f9 305 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 306 return;
307
308 }
309 } else
310#endif
ad312c7c 311 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 312 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
313 "reserved bits\n");
c1a5d4f9 314 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 315 return;
316 }
317
318 }
319
320 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 321 vcpu->arch.cr0 = cr0;
a03490ed 322
a03490ed 323 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 324 return;
325}
2d3ad1f4 326EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 327
2d3ad1f4 328void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 329{
2d3ad1f4 330 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 331 KVMTRACE_1D(LMSW, vcpu,
332 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
333 handler);
a03490ed 334}
2d3ad1f4 335EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 336
2d3ad1f4 337void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 338{
a2edf57f
AK		 339 unsigned long old_cr4 = vcpu->arch.cr4;
340 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
341
a03490ed
CO		 342 if (cr4 & CR4_RESERVED_BITS) {
343 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 344 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 345 return;
346 }
347
348 if (is_long_mode(vcpu)) {
349 if (!(cr4 & X86_CR4_PAE)) {
350 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
351 "in long mode\n");
c1a5d4f9 352 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 353 return;
354 }
a2edf57f
AK		 355 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
356 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 357 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 358 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 359 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 360 return;
361 }
362
363 if (cr4 & X86_CR4_VMXE) {
364 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 365 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 366 return;
367 }
368 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 369 vcpu->arch.cr4 = cr4;
5a41accd 370 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 371 kvm_mmu_reset_context(vcpu);
a03490ed 372}
2d3ad1f4 373EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 374
2d3ad1f4 375void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 376{
ad312c7c 377 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 378 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 379 kvm_mmu_flush_tlb(vcpu);
380 return;
381 }
382
a03490ed
CO		 383 if (is_long_mode(vcpu)) {
384 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
385 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 386 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 387 return;
388 }
389 } else {
390 if (is_pae(vcpu)) {
391 if (cr3 & CR3_PAE_RESERVED_BITS) {
392 printk(KERN_DEBUG
393 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 394 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 395 return;
396 }
397 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
398 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
399 "reserved bits\n");
c1a5d4f9 400 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 401 return;
402 }
403 }
404 /*
405 * We don't check reserved bits in nonpae mode, because
406 * this isn't enforced, and VMware depends on this.
407 */
408 }
409
a03490ed
CO		 410 /*
411 * Does the new cr3 value map to physical memory? (Note, we
412 * catch an invalid cr3 even in real-mode, because it would
413 * cause trouble later on when we turn on paging anyway.)
414 *
415 * A real CPU would silently accept an invalid cr3 and would
416 * attempt to use it - with largely undefined (and often hard
417 * to debug) behavior on the guest side.
418 */
419 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 420 kvm_inject_gp(vcpu, 0);
a03490ed 421 else {
ad312c7c
ZX		 422 vcpu->arch.cr3 = cr3;
423 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 424 }
a03490ed 425}
2d3ad1f4 426EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 427
2d3ad1f4 428void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 429{
430 if (cr8 & CR8_RESERVED_BITS) {
431 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 432 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 433 return;
434 }
435 if (irqchip_in_kernel(vcpu->kvm))
436 kvm_lapic_set_tpr(vcpu, cr8);
437 else
ad312c7c 438 vcpu->arch.cr8 = cr8;
a03490ed 439}
2d3ad1f4 440EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 441
2d3ad1f4 442unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 443{
444 if (irqchip_in_kernel(vcpu->kvm))
445 return kvm_lapic_get_cr8(vcpu);
446 else
ad312c7c 447 return vcpu->arch.cr8;
a03490ed 448}
2d3ad1f4 449EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 450
d8017474
AG		 451static inline u32 bit(int bitno)
452{
453 return 1 << (bitno & 31);
454}
455
043405e1
CO		 456/*
457 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
458 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
459 *
460 * This list is modified at module load time to reflect the
461 * capabilities of the host cpu.
462 */
463static u32 msrs_to_save[] = {
464 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
465 MSR_K6_STAR,
466#ifdef CONFIG_X86_64
467 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
468#endif
18068523 469 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 470 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 471};
472
473static unsigned num_msrs_to_save;
474
475static u32 emulated_msrs[] = {
476 MSR_IA32_MISC_ENABLE,
477};
478
15c4a640
CO		 479static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
480{
f2b4b7dd 481 if (efer & efer_reserved_bits) {
15c4a640
CO		 482 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
483 efer);
c1a5d4f9 484 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 485 return;
486 }
487
488 if (is_paging(vcpu)
ad312c7c 489 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 490 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 491 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 492 return;
493 }
494
1b2fd70c
AG		 495 if (efer & EFER_FFXSR) {
496 struct kvm_cpuid_entry2 *feat;
497
498 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
499 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
500 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
501 kvm_inject_gp(vcpu, 0);
502 return;
503 }
504 }
505
d8017474
AG		 506 if (efer & EFER_SVME) {
507 struct kvm_cpuid_entry2 *feat;
508
509 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
510 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
511 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
512 kvm_inject_gp(vcpu, 0);
513 return;
514 }
515 }
516
15c4a640
CO		 517 kvm_x86_ops->set_efer(vcpu, efer);
518
519 efer &= ~EFER_LMA;
ad312c7c 520 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 521
ad312c7c 522 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 523
524 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
525 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 526}
527
f2b4b7dd
JR		 528void kvm_enable_efer_bits(u64 mask)
529{
530 efer_reserved_bits &= ~mask;
531}
532EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
533
534
15c4a640
CO		 535/*
536 * Writes msr value into into the appropriate "register".
537 * Returns 0 on success, non-0 otherwise.
538 * Assumes vcpu_load() was already called.
539 */
540int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
541{
542 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
543}
544
313a3dc7
CO		 545/*
546 * Adapt set_msr() to msr_io()'s calling convention
547 */
548static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
549{
550 return kvm_set_msr(vcpu, index, *data);
551}
552
18068523
GOC		 553static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
554{
555 static int version;
50d0a0f9
GH		 556 struct pvclock_wall_clock wc;
557 struct timespec now, sys, boot;
18068523
GOC		 558
559 if (!wall_clock)
560 return;
561
562 version++;
563
18068523
GOC		 564 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
565
50d0a0f9
GH		 566 /*
567 * The guest calculates current wall clock time by adding
568 * system time (updated by kvm_write_guest_time below) to the
569 * wall clock specified here. guest system time equals host
570 * system time for us, thus we must fill in host boot time here.
571 */
572 now = current_kernel_time();
573 ktime_get_ts(&sys);
574 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
575
576 wc.sec = boot.tv_sec;
577 wc.nsec = boot.tv_nsec;
578 wc.version = version;
18068523
GOC		 579
580 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
581
582 version++;
583 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 584}
585
50d0a0f9
GH		 586static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
587{
588 uint32_t quotient, remainder;
589
590 /* Don't try to replace with do_div(), this one calculates
591 * "(dividend << 32) / divisor" */
592 __asm__ ( "divl %4"
593 : "=a" (quotient), "=d" (remainder)
594 : "0" (0), "1" (dividend), "r" (divisor) );
595 return quotient;
596}
597
598static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
599{
600 uint64_t nsecs = 1000000000LL;
601 int32_t shift = 0;
602 uint64_t tps64;
603 uint32_t tps32;
604
605 tps64 = tsc_khz * 1000LL;
606 while (tps64 > nsecs*2) {
607 tps64 >>= 1;
608 shift--;
609 }
610
611 tps32 = (uint32_t)tps64;
612 while (tps32 <= (uint32_t)nsecs) {
613 tps32 <<= 1;
614 shift++;
615 }
616
617 hv_clock->tsc_shift = shift;
618 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
619
620 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 621 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 622 hv_clock->tsc_to_system_mul);
623}
624
c8076604
GH		 625static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
626
18068523
GOC		 627static void kvm_write_guest_time(struct kvm_vcpu *v)
628{
629 struct timespec ts;
630 unsigned long flags;
631 struct kvm_vcpu_arch *vcpu = &v->arch;
632 void *shared_kaddr;
463656c0 633 unsigned long this_tsc_khz;
18068523
GOC		 634
635 if ((!vcpu->time_page))
636 return;
637
463656c0
AK		 638 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
639 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
640 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
641 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 642 }
463656c0 643 put_cpu_var(cpu_tsc_khz);
50d0a0f9 644
18068523
GOC		 645 /* Keep irq disabled to prevent changes to the clock */
646 local_irq_save(flags);
647 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
648 &vcpu->hv_clock.tsc_timestamp);
649 ktime_get_ts(&ts);
650 local_irq_restore(flags);
651
652 /* With all the info we got, fill in the values */
653
654 vcpu->hv_clock.system_time = ts.tv_nsec +
655 (NSEC_PER_SEC * (u64)ts.tv_sec);
656 /*
657 * The interface expects us to write an even number signaling that the
658 * update is finished. Since the guest won't see the intermediate
50d0a0f9 659 * state, we just increase by 2 at the end.
18068523 660 */
50d0a0f9 661 vcpu->hv_clock.version += 2;
18068523
GOC		 662
663 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
664
665 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 666 sizeof(vcpu->hv_clock));
18068523
GOC		 667
668 kunmap_atomic(shared_kaddr, KM_USER0);
669
670 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
671}
672
c8076604
GH		 673static int kvm_request_guest_time_update(struct kvm_vcpu *v)
674{
675 struct kvm_vcpu_arch *vcpu = &v->arch;
676
677 if (!vcpu->time_page)
678 return 0;
679 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
680 return 1;
681}
682
9ba075a6
AK		 683static bool msr_mtrr_valid(unsigned msr)
684{
685 switch (msr) {
686 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
687 case MSR_MTRRfix64K_00000:
688 case MSR_MTRRfix16K_80000:
689 case MSR_MTRRfix16K_A0000:
690 case MSR_MTRRfix4K_C0000:
691 case MSR_MTRRfix4K_C8000:
692 case MSR_MTRRfix4K_D0000:
693 case MSR_MTRRfix4K_D8000:
694 case MSR_MTRRfix4K_E0000:
695 case MSR_MTRRfix4K_E8000:
696 case MSR_MTRRfix4K_F0000:
697 case MSR_MTRRfix4K_F8000:
698 case MSR_MTRRdefType:
699 case MSR_IA32_CR_PAT:
700 return true;
701 case 0x2f8:
702 return true;
703 }
704 return false;
705}
706
707static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
708{
0bed3b56
SY		 709 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
710
9ba075a6
AK		 711 if (!msr_mtrr_valid(msr))
712 return 1;
713
0bed3b56
SY		 714 if (msr == MSR_MTRRdefType) {
715 vcpu->arch.mtrr_state.def_type = data;
716 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
717 } else if (msr == MSR_MTRRfix64K_00000)
718 p[0] = data;
719 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
720 p[1 + msr - MSR_MTRRfix16K_80000] = data;
721 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
722 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
723 else if (msr == MSR_IA32_CR_PAT)
724 vcpu->arch.pat = data;
725 else { /* Variable MTRRs */
726 int idx, is_mtrr_mask;
727 u64 *pt;
728
729 idx = (msr - 0x200) / 2;
730 is_mtrr_mask = msr - 0x200 - 2 * idx;
731 if (!is_mtrr_mask)
732 pt =
733 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
734 else
735 pt =
736 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
737 *pt = data;
738 }
739
740 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 741 return 0;
742}
15c4a640
CO		 743
744int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
745{
746 switch (msr) {
15c4a640
CO		 747 case MSR_EFER:
748 set_efer(vcpu, data);
749 break;
15c4a640
CO		 750 case MSR_IA32_MC0_STATUS:
751 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 752 __func__, data);
15c4a640
CO		 753 break;
754 case MSR_IA32_MCG_STATUS:
755 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 756 __func__, data);
15c4a640 757 break;
c7ac679c
JR		 758 case MSR_IA32_MCG_CTL:
759 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 760 __func__, data);
c7ac679c 761 break;
b5e2fec0
AG		 762 case MSR_IA32_DEBUGCTLMSR:
763 if (!data) {
764 /* We support the non-activated case already */
765 break;
766 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
767 /* Values other than LBR and BTF are vendor-specific,
768 thus reserved and should throw a #GP */
769 return 1;
770 }
771 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
772 __func__, data);
773 break;
15c4a640
CO		 774 case MSR_IA32_UCODE_REV:
775 case MSR_IA32_UCODE_WRITE:
61a6bd67 776 case MSR_VM_HSAVE_PA:
15c4a640 777 break;
9ba075a6
AK		 778 case 0x200 ... 0x2ff:
779 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 780 case MSR_IA32_APICBASE:
781 kvm_set_apic_base(vcpu, data);
782 break;
783 case MSR_IA32_MISC_ENABLE:
ad312c7c 784 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 785 break;
18068523
GOC		 786 case MSR_KVM_WALL_CLOCK:
787 vcpu->kvm->arch.wall_clock = data;
788 kvm_write_wall_clock(vcpu->kvm, data);
789 break;
790 case MSR_KVM_SYSTEM_TIME: {
791 if (vcpu->arch.time_page) {
792 kvm_release_page_dirty(vcpu->arch.time_page);
793 vcpu->arch.time_page = NULL;
794 }
795
796 vcpu->arch.time = data;
797
798 /* we verify if the enable bit is set... */
799 if (!(data & 1))
800 break;
801
802 /* ...but clean it before doing the actual write */
803 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
804
18068523
GOC		 805 vcpu->arch.time_page =
806 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 807
808 if (is_error_page(vcpu->arch.time_page)) {
809 kvm_release_page_clean(vcpu->arch.time_page);
810 vcpu->arch.time_page = NULL;
811 }
812
c8076604 813 kvm_request_guest_time_update(vcpu);
18068523
GOC		 814 break;
815 }
15c4a640 816 default:
565f1fbd 817 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 818 return 1;
819 }
820 return 0;
821}
822EXPORT_SYMBOL_GPL(kvm_set_msr_common);
823
824
825/*
826 * Reads an msr value (of 'msr_index') into 'pdata'.
827 * Returns 0 on success, non-0 otherwise.
828 * Assumes vcpu_load() was already called.
829 */
830int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
831{
832 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
833}
834
9ba075a6
AK		 835static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
836{
0bed3b56
SY		 837 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
838
9ba075a6
AK		 839 if (!msr_mtrr_valid(msr))
840 return 1;
841
0bed3b56
SY		 842 if (msr == MSR_MTRRdefType)
843 *pdata = vcpu->arch.mtrr_state.def_type +
844 (vcpu->arch.mtrr_state.enabled << 10);
845 else if (msr == MSR_MTRRfix64K_00000)
846 *pdata = p[0];
847 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
848 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
849 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
850 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
851 else if (msr == MSR_IA32_CR_PAT)
852 *pdata = vcpu->arch.pat;
853 else { /* Variable MTRRs */
854 int idx, is_mtrr_mask;
855 u64 *pt;
856
857 idx = (msr - 0x200) / 2;
858 is_mtrr_mask = msr - 0x200 - 2 * idx;
859 if (!is_mtrr_mask)
860 pt =
861 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
862 else
863 pt =
864 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
865 *pdata = *pt;
866 }
867
9ba075a6
AK		 868 return 0;
869}
870
15c4a640
CO		 871int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
872{
873 u64 data;
874
875 switch (msr) {
876 case 0xc0010010: /* SYSCFG */
877 case 0xc0010015: /* HWCR */
878 case MSR_IA32_PLATFORM_ID:
879 case MSR_IA32_P5_MC_ADDR:
880 case MSR_IA32_P5_MC_TYPE:
881 case MSR_IA32_MC0_CTL:
882 case MSR_IA32_MCG_STATUS:
883 case MSR_IA32_MCG_CAP:
c7ac679c 884 case MSR_IA32_MCG_CTL:
15c4a640
CO		 885 case MSR_IA32_MC0_MISC:
886 case MSR_IA32_MC0_MISC+4:
887 case MSR_IA32_MC0_MISC+8:
888 case MSR_IA32_MC0_MISC+12:
889 case MSR_IA32_MC0_MISC+16:
a89c1ad2 890 case MSR_IA32_MC0_MISC+20:
15c4a640 891 case MSR_IA32_UCODE_REV:
15c4a640 892 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 893 case MSR_IA32_DEBUGCTLMSR:
894 case MSR_IA32_LASTBRANCHFROMIP:
895 case MSR_IA32_LASTBRANCHTOIP:
896 case MSR_IA32_LASTINTFROMIP:
897 case MSR_IA32_LASTINTTOIP:
61a6bd67 898 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 899 case MSR_P6_EVNTSEL0:
900 case MSR_P6_EVNTSEL1:
15c4a640
CO		 901 data = 0;
902 break;
9ba075a6
AK		 903 case MSR_MTRRcap:
904 data = 0x500 | KVM_NR_VAR_MTRR;
905 break;
906 case 0x200 ... 0x2ff:
907 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 908 case 0xcd: /* fsb frequency */
909 data = 3;
910 break;
911 case MSR_IA32_APICBASE:
912 data = kvm_get_apic_base(vcpu);
913 break;
914 case MSR_IA32_MISC_ENABLE:
ad312c7c 915 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 916 break;
847f0ad8
AG		 917 case MSR_IA32_PERF_STATUS:
918 /* TSC increment by tick */
919 data = 1000ULL;
920 /* CPU multiplier */
921 data |= (((uint64_t)4ULL) << 40);
922 break;
15c4a640 923 case MSR_EFER:
ad312c7c 924 data = vcpu->arch.shadow_efer;
15c4a640 925 break;
18068523
GOC		 926 case MSR_KVM_WALL_CLOCK:
927 data = vcpu->kvm->arch.wall_clock;
928 break;
929 case MSR_KVM_SYSTEM_TIME:
930 data = vcpu->arch.time;
931 break;
15c4a640
CO		 932 default:
933 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
934 return 1;
935 }
936 *pdata = data;
937 return 0;
938}
939EXPORT_SYMBOL_GPL(kvm_get_msr_common);
940
313a3dc7
CO		 941/*
942 * Read or write a bunch of msrs. All parameters are kernel addresses.
943 *
944 * @return number of msrs set successfully.
945 */
946static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
947 struct kvm_msr_entry *entries,
948 int (*do_msr)(struct kvm_vcpu *vcpu,
949 unsigned index, u64 *data))
950{
951 int i;
952
953 vcpu_load(vcpu);
954
3200f405 955 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 956 for (i = 0; i < msrs->nmsrs; ++i)
957 if (do_msr(vcpu, entries[i].index, &entries[i].data))
958 break;
3200f405 959 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 960
961 vcpu_put(vcpu);
962
963 return i;
964}
965
966/*
967 * Read or write a bunch of msrs. Parameters are user addresses.
968 *
969 * @return number of msrs set successfully.
970 */
971static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
972 int (*do_msr)(struct kvm_vcpu *vcpu,
973 unsigned index, u64 *data),
974 int writeback)
975{
976 struct kvm_msrs msrs;
977 struct kvm_msr_entry *entries;
978 int r, n;
979 unsigned size;
980
981 r = -EFAULT;
982 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
983 goto out;
984
985 r = -E2BIG;
986 if (msrs.nmsrs >= MAX_IO_MSRS)
987 goto out;
988
989 r = -ENOMEM;
990 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
991 entries = vmalloc(size);
992 if (!entries)
993 goto out;
994
995 r = -EFAULT;
996 if (copy_from_user(entries, user_msrs->entries, size))
997 goto out_free;
998
999 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1000 if (r < 0)
1001 goto out_free;
1002
1003 r = -EFAULT;
1004 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1005 goto out_free;
1006
1007 r = n;
1008
1009out_free:
1010 vfree(entries);
1011out:
1012 return r;
1013}
1014
018d00d2
ZX		 1015int kvm_dev_ioctl_check_extension(long ext)
1016{
1017 int r;
1018
1019 switch (ext) {
1020 case KVM_CAP_IRQCHIP:
1021 case KVM_CAP_HLT:
1022 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1023 case KVM_CAP_SET_TSS_ADDR:
07716717 1024 case KVM_CAP_EXT_CPUID:
c8076604 1025 case KVM_CAP_CLOCKSOURCE:
7837699f 1026 case KVM_CAP_PIT:
a28e4f5a 1027 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1028 case KVM_CAP_MP_STATE:
ed848624 1029 case KVM_CAP_SYNC_MMU:
52d939a0 1030 case KVM_CAP_REINJECT_CONTROL:
4925663a 1031 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1032 case KVM_CAP_ASSIGN_DEV_IRQ:
018d00d2
ZX		 1033 r = 1;
1034 break;
542472b5
LV		 1035 case KVM_CAP_COALESCED_MMIO:
1036 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1037 break;
774ead3a
AK		 1038 case KVM_CAP_VAPIC:
1039 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1040 break;
f725230a
AK		 1041 case KVM_CAP_NR_VCPUS:
1042 r = KVM_MAX_VCPUS;
1043 break;
a988b910
AK		 1044 case KVM_CAP_NR_MEMSLOTS:
1045 r = KVM_MEMORY_SLOTS;
1046 break;
2f333bcb
MT		 1047 case KVM_CAP_PV_MMU:
1048 r = !tdp_enabled;
1049 break;
62c476c7 1050 case KVM_CAP_IOMMU:
19de40a8 1051 r = iommu_found();
62c476c7 1052 break;
018d00d2
ZX		 1053 default:
1054 r = 0;
1055 break;
1056 }
1057 return r;
1058
1059}
1060
043405e1
CO		 1061long kvm_arch_dev_ioctl(struct file *filp,
1062 unsigned int ioctl, unsigned long arg)
1063{
1064 void __user *argp = (void __user *)arg;
1065 long r;
1066
1067 switch (ioctl) {
1068 case KVM_GET_MSR_INDEX_LIST: {
1069 struct kvm_msr_list __user *user_msr_list = argp;
1070 struct kvm_msr_list msr_list;
1071 unsigned n;
1072
1073 r = -EFAULT;
1074 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1075 goto out;
1076 n = msr_list.nmsrs;
1077 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1078 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1079 goto out;
1080 r = -E2BIG;
1081 if (n < num_msrs_to_save)
1082 goto out;
1083 r = -EFAULT;
1084 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1085 num_msrs_to_save * sizeof(u32)))
1086 goto out;
1087 if (copy_to_user(user_msr_list->indices
1088 + num_msrs_to_save * sizeof(u32),
1089 &emulated_msrs,
1090 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1091 goto out;
1092 r = 0;
1093 break;
1094 }
674eea0f
AK		 1095 case KVM_GET_SUPPORTED_CPUID: {
1096 struct kvm_cpuid2 __user *cpuid_arg = argp;
1097 struct kvm_cpuid2 cpuid;
1098
1099 r = -EFAULT;
1100 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1101 goto out;
1102 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1103 cpuid_arg->entries);
674eea0f
AK		 1104 if (r)
1105 goto out;
1106
1107 r = -EFAULT;
1108 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1109 goto out;
1110 r = 0;
1111 break;
1112 }
043405e1
CO		 1113 default:
1114 r = -EINVAL;
1115 }
1116out:
1117 return r;
1118}
1119
313a3dc7
CO		 1120void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1121{
1122 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1123 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1124}
1125
1126void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1127{
1128 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1129 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1130}
1131
07716717 1132static int is_efer_nx(void)
313a3dc7 1133{
e286e86e 1134 unsigned long long efer = 0;
313a3dc7 1135
e286e86e 1136 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1137 return efer & EFER_NX;
1138}
1139
1140static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1141{
1142 int i;
1143 struct kvm_cpuid_entry2 *e, *entry;
1144
313a3dc7 1145 entry = NULL;
ad312c7c
ZX		 1146 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1147 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1148 if (e->function == 0x80000001) {
1149 entry = e;
1150 break;
1151 }
1152 }
07716717 1153 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1154 entry->edx &= ~(1 << 20);
1155 printk(KERN_INFO "kvm: guest NX capability removed\n");
1156 }
1157}
1158
07716717 1159/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1160static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1161 struct kvm_cpuid *cpuid,
1162 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1163{
1164 int r, i;
1165 struct kvm_cpuid_entry *cpuid_entries;
1166
1167 r = -E2BIG;
1168 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1169 goto out;
1170 r = -ENOMEM;
1171 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1172 if (!cpuid_entries)
1173 goto out;
1174 r = -EFAULT;
1175 if (copy_from_user(cpuid_entries, entries,
1176 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1177 goto out_free;
1178 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1179 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1180 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1181 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1182 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1183 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1184 vcpu->arch.cpuid_entries[i].index = 0;
1185 vcpu->arch.cpuid_entries[i].flags = 0;
1186 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1187 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1188 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1189 }
1190 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1191 cpuid_fix_nx_cap(vcpu);
1192 r = 0;
1193
1194out_free:
1195 vfree(cpuid_entries);
1196out:
1197 return r;
1198}
1199
1200static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1201 struct kvm_cpuid2 *cpuid,
1202 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1203{
1204 int r;
1205
1206 r = -E2BIG;
1207 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1208 goto out;
1209 r = -EFAULT;
ad312c7c 1210 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1211 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1212 goto out;
ad312c7c 1213 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1214 return 0;
1215
1216out:
1217 return r;
1218}
1219
07716717 1220static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1221 struct kvm_cpuid2 *cpuid,
1222 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1223{
1224 int r;
1225
1226 r = -E2BIG;
ad312c7c 1227 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1228 goto out;
1229 r = -EFAULT;
ad312c7c 1230 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1231 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1232 goto out;
1233 return 0;
1234
1235out:
ad312c7c 1236 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1237 return r;
1238}
1239
07716717 1240static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1241 u32 index)
07716717
DK		 1242{
1243 entry->function = function;
1244 entry->index = index;
1245 cpuid_count(entry->function, entry->index,
19355475 1246 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1247 entry->flags = 0;
1248}
1249
7faa4ee1
AK		 1250#define F(x) bit(X86_FEATURE_##x)
1251
07716717
DK		 1252static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1253 u32 index, int *nent, int maxnent)
1254{
7faa4ee1 1255 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1256#ifdef CONFIG_X86_64
7faa4ee1
AK		 1257 unsigned f_lm = F(LM);
1258#else
1259 unsigned f_lm = 0;
07716717 1260#endif
7faa4ee1
AK		 1261
1262 /* cpuid 1.edx */
1263 const u32 kvm_supported_word0_x86_features =
1264 F(FPU) | F(VME) | F(DE) | F(PSE) |
1265 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1266 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1267 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1268 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1269 0 /* Reserved, DS, ACPI */ | F(MMX) |
1270 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1271 0 /* HTT, TM, Reserved, PBE */;
1272 /* cpuid 0x80000001.edx */
1273 const u32 kvm_supported_word1_x86_features =
1274 F(FPU) | F(VME) | F(DE) | F(PSE) |
1275 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1276 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1277 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1278 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1279 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1280 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1281 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1282 /* cpuid 1.ecx */
1283 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1284 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1285 0 /* DS-CPL, VMX, SMX, EST */ |
1286 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1287 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1288 0 /* Reserved, DCA */ | F(XMM4_1) |
1289 F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
1290 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1291 /* cpuid 0x80000001.ecx */
07716717 1292 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1293 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1294 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1295 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1296 0 /* SKINIT */ | 0 /* WDT */;
07716717 1297
19355475 1298 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1299 get_cpu();
1300 do_cpuid_1_ent(entry, function, index);
1301 ++*nent;
1302
1303 switch (function) {
1304 case 0:
1305 entry->eax = min(entry->eax, (u32)0xb);
1306 break;
1307 case 1:
1308 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1309 entry->ecx &= kvm_supported_word4_x86_features;
07716717
DK		 1310 break;
1311 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1312 * may return different values. This forces us to get_cpu() before
1313 * issuing the first command, and also to emulate this annoying behavior
1314 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1315 case 2: {
1316 int t, times = entry->eax & 0xff;
1317
1318 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1319 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1320 for (t = 1; t < times && *nent < maxnent; ++t) {
1321 do_cpuid_1_ent(&entry[t], function, 0);
1322 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1323 ++*nent;
1324 }
1325 break;
1326 }
1327 /* function 4 and 0xb have additional index. */
1328 case 4: {
14af3f3c 1329 int i, cache_type;
07716717
DK		 1330
1331 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1332 /* read more entries until cache_type is zero */
14af3f3c
HH		 1333 for (i = 1; *nent < maxnent; ++i) {
1334 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1335 if (!cache_type)
1336 break;
14af3f3c
HH		 1337 do_cpuid_1_ent(&entry[i], function, i);
1338 entry[i].flags |=
07716717
DK		 1339 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1340 ++*nent;
1341 }
1342 break;
1343 }
1344 case 0xb: {
14af3f3c 1345 int i, level_type;
07716717
DK		 1346
1347 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1348 /* read more entries until level_type is zero */
14af3f3c 1349 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1350 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1351 if (!level_type)
1352 break;
14af3f3c
HH		 1353 do_cpuid_1_ent(&entry[i], function, i);
1354 entry[i].flags |=
07716717
DK		 1355 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1356 ++*nent;
1357 }
1358 break;
1359 }
1360 case 0x80000000:
1361 entry->eax = min(entry->eax, 0x8000001a);
1362 break;
1363 case 0x80000001:
1364 entry->edx &= kvm_supported_word1_x86_features;
1365 entry->ecx &= kvm_supported_word6_x86_features;
1366 break;
1367 }
1368 put_cpu();
1369}
1370
7faa4ee1
AK		 1371#undef F
1372
674eea0f 1373static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1374 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1375{
1376 struct kvm_cpuid_entry2 *cpuid_entries;
1377 int limit, nent = 0, r = -E2BIG;
1378 u32 func;
1379
1380 if (cpuid->nent < 1)
1381 goto out;
1382 r = -ENOMEM;
1383 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1384 if (!cpuid_entries)
1385 goto out;
1386
1387 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1388 limit = cpuid_entries[0].eax;
1389 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1390 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1391 &nent, cpuid->nent);
07716717
DK		 1392 r = -E2BIG;
1393 if (nent >= cpuid->nent)
1394 goto out_free;
1395
1396 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1397 limit = cpuid_entries[nent - 1].eax;
1398 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1399 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1400 &nent, cpuid->nent);
07716717
DK		 1401 r = -EFAULT;
1402 if (copy_to_user(entries, cpuid_entries,
19355475 1403 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1404 goto out_free;
1405 cpuid->nent = nent;
1406 r = 0;
1407
1408out_free:
1409 vfree(cpuid_entries);
1410out:
1411 return r;
1412}
1413
313a3dc7
CO		 1414static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1415 struct kvm_lapic_state *s)
1416{
1417 vcpu_load(vcpu);
ad312c7c 1418 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1419 vcpu_put(vcpu);
1420
1421 return 0;
1422}
1423
1424static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1425 struct kvm_lapic_state *s)
1426{
1427 vcpu_load(vcpu);
ad312c7c 1428 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1429 kvm_apic_post_state_restore(vcpu);
1430 vcpu_put(vcpu);
1431
1432 return 0;
1433}
1434
f77bc6a4
ZX		 1435static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1436 struct kvm_interrupt *irq)
1437{
1438 if (irq->irq < 0 || irq->irq >= 256)
1439 return -EINVAL;
1440 if (irqchip_in_kernel(vcpu->kvm))
1441 return -ENXIO;
1442 vcpu_load(vcpu);
1443
66fd3f7f 1444 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1445
1446 vcpu_put(vcpu);
1447
1448 return 0;
1449}
1450
c4abb7c9
JK		 1451static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1452{
1453 vcpu_load(vcpu);
1454 kvm_inject_nmi(vcpu);
1455 vcpu_put(vcpu);
1456
1457 return 0;
1458}
1459
b209749f
AK		 1460static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1461 struct kvm_tpr_access_ctl *tac)
1462{
1463 if (tac->flags)
1464 return -EINVAL;
1465 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1466 return 0;
1467}
1468
313a3dc7
CO		 1469long kvm_arch_vcpu_ioctl(struct file *filp,
1470 unsigned int ioctl, unsigned long arg)
1471{
1472 struct kvm_vcpu *vcpu = filp->private_data;
1473 void __user *argp = (void __user *)arg;
1474 int r;
b772ff36 1475 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1476
1477 switch (ioctl) {
1478 case KVM_GET_LAPIC: {
b772ff36 1479 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1480
b772ff36
DH		 1481 r = -ENOMEM;
1482 if (!lapic)
1483 goto out;
1484 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1485 if (r)
1486 goto out;
1487 r = -EFAULT;
b772ff36 1488 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1489 goto out;
1490 r = 0;
1491 break;
1492 }
1493 case KVM_SET_LAPIC: {
b772ff36
DH		 1494 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1495 r = -ENOMEM;
1496 if (!lapic)
1497 goto out;
313a3dc7 1498 r = -EFAULT;
b772ff36 1499 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1500 goto out;
b772ff36 1501 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1502 if (r)
1503 goto out;
1504 r = 0;
1505 break;
1506 }
f77bc6a4
ZX		 1507 case KVM_INTERRUPT: {
1508 struct kvm_interrupt irq;
1509
1510 r = -EFAULT;
1511 if (copy_from_user(&irq, argp, sizeof irq))
1512 goto out;
1513 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1514 if (r)
1515 goto out;
1516 r = 0;
1517 break;
1518 }
c4abb7c9
JK		 1519 case KVM_NMI: {
1520 r = kvm_vcpu_ioctl_nmi(vcpu);
1521 if (r)
1522 goto out;
1523 r = 0;
1524 break;
1525 }
313a3dc7
CO		 1526 case KVM_SET_CPUID: {
1527 struct kvm_cpuid __user *cpuid_arg = argp;
1528 struct kvm_cpuid cpuid;
1529
1530 r = -EFAULT;
1531 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1532 goto out;
1533 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1534 if (r)
1535 goto out;
1536 break;
1537 }
07716717
DK		 1538 case KVM_SET_CPUID2: {
1539 struct kvm_cpuid2 __user *cpuid_arg = argp;
1540 struct kvm_cpuid2 cpuid;
1541
1542 r = -EFAULT;
1543 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1544 goto out;
1545 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1546 cpuid_arg->entries);
07716717
DK		 1547 if (r)
1548 goto out;
1549 break;
1550 }
1551 case KVM_GET_CPUID2: {
1552 struct kvm_cpuid2 __user *cpuid_arg = argp;
1553 struct kvm_cpuid2 cpuid;
1554
1555 r = -EFAULT;
1556 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1557 goto out;
1558 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1559 cpuid_arg->entries);
07716717
DK		 1560 if (r)
1561 goto out;
1562 r = -EFAULT;
1563 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1564 goto out;
1565 r = 0;
1566 break;
1567 }
313a3dc7
CO		 1568 case KVM_GET_MSRS:
1569 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1570 break;
1571 case KVM_SET_MSRS:
1572 r = msr_io(vcpu, argp, do_set_msr, 0);
1573 break;
b209749f
AK		 1574 case KVM_TPR_ACCESS_REPORTING: {
1575 struct kvm_tpr_access_ctl tac;
1576
1577 r = -EFAULT;
1578 if (copy_from_user(&tac, argp, sizeof tac))
1579 goto out;
1580 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1581 if (r)
1582 goto out;
1583 r = -EFAULT;
1584 if (copy_to_user(argp, &tac, sizeof tac))
1585 goto out;
1586 r = 0;
1587 break;
1588 };
b93463aa
AK		 1589 case KVM_SET_VAPIC_ADDR: {
1590 struct kvm_vapic_addr va;
1591
1592 r = -EINVAL;
1593 if (!irqchip_in_kernel(vcpu->kvm))
1594 goto out;
1595 r = -EFAULT;
1596 if (copy_from_user(&va, argp, sizeof va))
1597 goto out;
1598 r = 0;
1599 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1600 break;
1601 }
313a3dc7
CO		 1602 default:
1603 r = -EINVAL;
1604 }
1605out:
7a6ce84c 1606 kfree(lapic);
313a3dc7
CO		 1607 return r;
1608}
1609
1fe779f8
CO		 1610static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1611{
1612 int ret;
1613
1614 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1615 return -1;
1616 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1617 return ret;
1618}
1619
1620static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1621 u32 kvm_nr_mmu_pages)
1622{
1623 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1624 return -EINVAL;
1625
72dc67a6 1626 down_write(&kvm->slots_lock);
7c8a83b7 1627 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1628
1629 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1630 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1631
7c8a83b7 1632 spin_unlock(&kvm->mmu_lock);
72dc67a6 1633 up_write(&kvm->slots_lock);
1fe779f8
CO		 1634 return 0;
1635}
1636
1637static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1638{
f05e70ac 1639 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1640}
1641
e9f85cde
ZX		 1642gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1643{
1644 int i;
1645 struct kvm_mem_alias *alias;
1646
d69fb81f
ZX		 1647 for (i = 0; i < kvm->arch.naliases; ++i) {
1648 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1649 if (gfn >= alias->base_gfn
1650 && gfn < alias->base_gfn + alias->npages)
1651 return alias->target_gfn + gfn - alias->base_gfn;
1652 }
1653 return gfn;
1654}
1655
1fe779f8
CO		 1656/*
1657 * Set a new alias region. Aliases map a portion of physical memory into
1658 * another portion. This is useful for memory windows, for example the PC
1659 * VGA region.
1660 */
1661static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1662 struct kvm_memory_alias *alias)
1663{
1664 int r, n;
1665 struct kvm_mem_alias *p;
1666
1667 r = -EINVAL;
1668 /* General sanity checks */
1669 if (alias->memory_size & (PAGE_SIZE - 1))
1670 goto out;
1671 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1672 goto out;
1673 if (alias->slot >= KVM_ALIAS_SLOTS)
1674 goto out;
1675 if (alias->guest_phys_addr + alias->memory_size
1676 < alias->guest_phys_addr)
1677 goto out;
1678 if (alias->target_phys_addr + alias->memory_size
1679 < alias->target_phys_addr)
1680 goto out;
1681
72dc67a6 1682 down_write(&kvm->slots_lock);
a1708ce8 1683 spin_lock(&kvm->mmu_lock);
1fe779f8 1684
d69fb81f 1685 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1686 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1687 p->npages = alias->memory_size >> PAGE_SHIFT;
1688 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1689
1690 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1691 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1692 break;
d69fb81f 1693 kvm->arch.naliases = n;
1fe779f8 1694
a1708ce8 1695 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1696 kvm_mmu_zap_all(kvm);
1697
72dc67a6 1698 up_write(&kvm->slots_lock);
1fe779f8
CO		 1699
1700 return 0;
1701
1702out:
1703 return r;
1704}
1705
1706static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1707{
1708 int r;
1709
1710 r = 0;
1711 switch (chip->chip_id) {
1712 case KVM_IRQCHIP_PIC_MASTER:
1713 memcpy(&chip->chip.pic,
1714 &pic_irqchip(kvm)->pics[0],
1715 sizeof(struct kvm_pic_state));
1716 break;
1717 case KVM_IRQCHIP_PIC_SLAVE:
1718 memcpy(&chip->chip.pic,
1719 &pic_irqchip(kvm)->pics[1],
1720 sizeof(struct kvm_pic_state));
1721 break;
1722 case KVM_IRQCHIP_IOAPIC:
1723 memcpy(&chip->chip.ioapic,
1724 ioapic_irqchip(kvm),
1725 sizeof(struct kvm_ioapic_state));
1726 break;
1727 default:
1728 r = -EINVAL;
1729 break;
1730 }
1731 return r;
1732}
1733
1734static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1735{
1736 int r;
1737
1738 r = 0;
1739 switch (chip->chip_id) {
1740 case KVM_IRQCHIP_PIC_MASTER:
1741 memcpy(&pic_irqchip(kvm)->pics[0],
1742 &chip->chip.pic,
1743 sizeof(struct kvm_pic_state));
1744 break;
1745 case KVM_IRQCHIP_PIC_SLAVE:
1746 memcpy(&pic_irqchip(kvm)->pics[1],
1747 &chip->chip.pic,
1748 sizeof(struct kvm_pic_state));
1749 break;
1750 case KVM_IRQCHIP_IOAPIC:
1751 memcpy(ioapic_irqchip(kvm),
1752 &chip->chip.ioapic,
1753 sizeof(struct kvm_ioapic_state));
1754 break;
1755 default:
1756 r = -EINVAL;
1757 break;
1758 }
1759 kvm_pic_update_irq(pic_irqchip(kvm));
1760 return r;
1761}
1762
e0f63cb9
SY		 1763static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1764{
1765 int r = 0;
1766
1767 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1768 return r;
1769}
1770
1771static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1772{
1773 int r = 0;
1774
1775 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1776 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1777 return r;
1778}
1779
52d939a0
MT		 1780static int kvm_vm_ioctl_reinject(struct kvm *kvm,
1781 struct kvm_reinject_control *control)
1782{
1783 if (!kvm->arch.vpit)
1784 return -ENXIO;
1785 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
1786 return 0;
1787}
1788
5bb064dc
ZX		 1789/*
1790 * Get (and clear) the dirty memory log for a memory slot.
1791 */
1792int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1793 struct kvm_dirty_log *log)
1794{
1795 int r;
1796 int n;
1797 struct kvm_memory_slot *memslot;
1798 int is_dirty = 0;
1799
72dc67a6 1800 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1801
1802 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1803 if (r)
1804 goto out;
1805
1806 /* If nothing is dirty, don't bother messing with page tables. */
1807 if (is_dirty) {
7c8a83b7 1808 spin_lock(&kvm->mmu_lock);
5bb064dc 1809 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 1810 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 1811 kvm_flush_remote_tlbs(kvm);
1812 memslot = &kvm->memslots[log->slot];
1813 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1814 memset(memslot->dirty_bitmap, 0, n);
1815 }
1816 r = 0;
1817out:
72dc67a6 1818 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1819 return r;
1820}
1821
1fe779f8
CO		 1822long kvm_arch_vm_ioctl(struct file *filp,
1823 unsigned int ioctl, unsigned long arg)
1824{
1825 struct kvm *kvm = filp->private_data;
1826 void __user *argp = (void __user *)arg;
1827 int r = -EINVAL;
f0d66275
DH		 1828 /*
1829 * This union makes it completely explicit to gcc-3.x
1830 * that these two variables' stack usage should be
1831 * combined, not added together.
1832 */
1833 union {
1834 struct kvm_pit_state ps;
1835 struct kvm_memory_alias alias;
1836 } u;
1fe779f8
CO		 1837
1838 switch (ioctl) {
1839 case KVM_SET_TSS_ADDR:
1840 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1841 if (r < 0)
1842 goto out;
1843 break;
1844 case KVM_SET_MEMORY_REGION: {
1845 struct kvm_memory_region kvm_mem;
1846 struct kvm_userspace_memory_region kvm_userspace_mem;
1847
1848 r = -EFAULT;
1849 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1850 goto out;
1851 kvm_userspace_mem.slot = kvm_mem.slot;
1852 kvm_userspace_mem.flags = kvm_mem.flags;
1853 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1854 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1855 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1856 if (r)
1857 goto out;
1858 break;
1859 }
1860 case KVM_SET_NR_MMU_PAGES:
1861 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1862 if (r)
1863 goto out;
1864 break;
1865 case KVM_GET_NR_MMU_PAGES:
1866 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1867 break;
f0d66275 1868 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1869 r = -EFAULT;
f0d66275 1870 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1871 goto out;
f0d66275 1872 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1873 if (r)
1874 goto out;
1875 break;
1fe779f8
CO		 1876 case KVM_CREATE_IRQCHIP:
1877 r = -ENOMEM;
d7deeeb0
ZX		 1878 kvm->arch.vpic = kvm_create_pic(kvm);
1879 if (kvm->arch.vpic) {
1fe779f8
CO		 1880 r = kvm_ioapic_init(kvm);
1881 if (r) {
d7deeeb0
ZX		 1882 kfree(kvm->arch.vpic);
1883 kvm->arch.vpic = NULL;
1fe779f8
CO		 1884 goto out;
1885 }
1886 } else
1887 goto out;
399ec807
AK		 1888 r = kvm_setup_default_irq_routing(kvm);
1889 if (r) {
1890 kfree(kvm->arch.vpic);
1891 kfree(kvm->arch.vioapic);
1892 goto out;
1893 }
1fe779f8 1894 break;
7837699f 1895 case KVM_CREATE_PIT:
269e05e4
AK		 1896 mutex_lock(&kvm->lock);
1897 r = -EEXIST;
1898 if (kvm->arch.vpit)
1899 goto create_pit_unlock;
7837699f
SY		 1900 r = -ENOMEM;
1901 kvm->arch.vpit = kvm_create_pit(kvm);
1902 if (kvm->arch.vpit)
1903 r = 0;
269e05e4
AK		 1904 create_pit_unlock:
1905 mutex_unlock(&kvm->lock);
7837699f 1906 break;
4925663a 1907 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 1908 case KVM_IRQ_LINE: {
1909 struct kvm_irq_level irq_event;
1910
1911 r = -EFAULT;
1912 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1913 goto out;
1914 if (irqchip_in_kernel(kvm)) {
4925663a 1915 __s32 status;
1fe779f8 1916 mutex_lock(&kvm->lock);
4925663a
GN		 1917 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
1918 irq_event.irq, irq_event.level);
1fe779f8 1919 mutex_unlock(&kvm->lock);
4925663a
GN		 1920 if (ioctl == KVM_IRQ_LINE_STATUS) {
1921 irq_event.status = status;
1922 if (copy_to_user(argp, &irq_event,
1923 sizeof irq_event))
1924 goto out;
1925 }
1fe779f8
CO		 1926 r = 0;
1927 }
1928 break;
1929 }
1930 case KVM_GET_IRQCHIP: {
1931 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1932 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1933
f0d66275
DH		 1934 r = -ENOMEM;
1935 if (!chip)
1fe779f8 1936 goto out;
f0d66275
DH		 1937 r = -EFAULT;
1938 if (copy_from_user(chip, argp, sizeof *chip))
1939 goto get_irqchip_out;
1fe779f8
CO		 1940 r = -ENXIO;
1941 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1942 goto get_irqchip_out;
1943 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1944 if (r)
f0d66275 1945 goto get_irqchip_out;
1fe779f8 1946 r = -EFAULT;
f0d66275
DH		 1947 if (copy_to_user(argp, chip, sizeof *chip))
1948 goto get_irqchip_out;
1fe779f8 1949 r = 0;
f0d66275
DH		 1950 get_irqchip_out:
1951 kfree(chip);
1952 if (r)
1953 goto out;
1fe779f8
CO		 1954 break;
1955 }
1956 case KVM_SET_IRQCHIP: {
1957 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1958 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1959
f0d66275
DH		 1960 r = -ENOMEM;
1961 if (!chip)
1fe779f8 1962 goto out;
f0d66275
DH		 1963 r = -EFAULT;
1964 if (copy_from_user(chip, argp, sizeof *chip))
1965 goto set_irqchip_out;
1fe779f8
CO		 1966 r = -ENXIO;
1967 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1968 goto set_irqchip_out;
1969 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 1970 if (r)
f0d66275 1971 goto set_irqchip_out;
1fe779f8 1972 r = 0;
f0d66275
DH		 1973 set_irqchip_out:
1974 kfree(chip);
1975 if (r)
1976 goto out;
1fe779f8
CO		 1977 break;
1978 }
e0f63cb9 1979 case KVM_GET_PIT: {
e0f63cb9 1980 r = -EFAULT;
f0d66275 1981 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1982 goto out;
1983 r = -ENXIO;
1984 if (!kvm->arch.vpit)
1985 goto out;
f0d66275 1986 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 1987 if (r)
1988 goto out;
1989 r = -EFAULT;
f0d66275 1990 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1991 goto out;
1992 r = 0;
1993 break;
1994 }
1995 case KVM_SET_PIT: {
e0f63cb9 1996 r = -EFAULT;
f0d66275 1997 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 1998 goto out;
1999 r = -ENXIO;
2000 if (!kvm->arch.vpit)
2001 goto out;
f0d66275 2002 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2003 if (r)
2004 goto out;
2005 r = 0;
2006 break;
2007 }
52d939a0
MT		 2008 case KVM_REINJECT_CONTROL: {
2009 struct kvm_reinject_control control;
2010 r = -EFAULT;
2011 if (copy_from_user(&control, argp, sizeof(control)))
2012 goto out;
2013 r = kvm_vm_ioctl_reinject(kvm, &control);
2014 if (r)
2015 goto out;
2016 r = 0;
2017 break;
2018 }
1fe779f8
CO		 2019 default:
2020 ;
2021 }
2022out:
2023 return r;
2024}
2025
a16b043c 2026static void kvm_init_msr_list(void)
043405e1
CO		 2027{
2028 u32 dummy[2];
2029 unsigned i, j;
2030
2031 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2032 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2033 continue;
2034 if (j < i)
2035 msrs_to_save[j] = msrs_to_save[i];
2036 j++;
2037 }
2038 num_msrs_to_save = j;
2039}
2040
bbd9b64e
CO		 2041/*
2042 * Only apic need an MMIO device hook, so shortcut now..
2043 */
2044static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2045 gpa_t addr, int len,
2046 int is_write)
bbd9b64e
CO		 2047{
2048 struct kvm_io_device *dev;
2049
ad312c7c
ZX		 2050 if (vcpu->arch.apic) {
2051 dev = &vcpu->arch.apic->dev;
92760499 2052 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 2053 return dev;
2054 }
2055 return NULL;
2056}
2057
2058
2059static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2060 gpa_t addr, int len,
2061 int is_write)
bbd9b64e
CO		 2062{
2063 struct kvm_io_device *dev;
2064
92760499 2065 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 2066 if (dev == NULL)
92760499
LV		 2067 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
2068 is_write);
bbd9b64e
CO		 2069 return dev;
2070}
2071
cded19f3
HE		 2072static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2073 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2074{
2075 void *data = val;
10589a46 2076 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2077
2078 while (bytes) {
ad312c7c 2079 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2080 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2081 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2082 int ret;
2083
10589a46
MT		 2084 if (gpa == UNMAPPED_GVA) {
2085 r = X86EMUL_PROPAGATE_FAULT;
2086 goto out;
2087 }
77c2002e 2088 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2089 if (ret < 0) {
2090 r = X86EMUL_UNHANDLEABLE;
2091 goto out;
2092 }
bbd9b64e 2093
77c2002e
IE		 2094 bytes -= toread;
2095 data += toread;
2096 addr += toread;
bbd9b64e 2097 }
10589a46 2098out:
10589a46 2099 return r;
bbd9b64e 2100}
77c2002e 2101
cded19f3
HE		 2102static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2103 struct kvm_vcpu *vcpu)
77c2002e
IE		 2104{
2105 void *data = val;
2106 int r = X86EMUL_CONTINUE;
2107
2108 while (bytes) {
2109 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2110 unsigned offset = addr & (PAGE_SIZE-1);
2111 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2112 int ret;
2113
2114 if (gpa == UNMAPPED_GVA) {
2115 r = X86EMUL_PROPAGATE_FAULT;
2116 goto out;
2117 }
2118 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2119 if (ret < 0) {
2120 r = X86EMUL_UNHANDLEABLE;
2121 goto out;
2122 }
2123
2124 bytes -= towrite;
2125 data += towrite;
2126 addr += towrite;
2127 }
2128out:
2129 return r;
2130}
2131
bbd9b64e 2132
bbd9b64e
CO		 2133static int emulator_read_emulated(unsigned long addr,
2134 void *val,
2135 unsigned int bytes,
2136 struct kvm_vcpu *vcpu)
2137{
2138 struct kvm_io_device *mmio_dev;
2139 gpa_t gpa;
2140
2141 if (vcpu->mmio_read_completed) {
2142 memcpy(val, vcpu->mmio_data, bytes);
2143 vcpu->mmio_read_completed = 0;
2144 return X86EMUL_CONTINUE;
2145 }
2146
ad312c7c 2147 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2148
2149 /* For APIC access vmexit */
2150 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2151 goto mmio;
2152
77c2002e
IE		 2153 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2154 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2155 return X86EMUL_CONTINUE;
2156 if (gpa == UNMAPPED_GVA)
2157 return X86EMUL_PROPAGATE_FAULT;
2158
2159mmio:
2160 /*
2161 * Is this MMIO handled locally?
2162 */
10589a46 2163 mutex_lock(&vcpu->kvm->lock);
92760499 2164 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2165 if (mmio_dev) {
2166 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2167 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2168 return X86EMUL_CONTINUE;
2169 }
10589a46 2170 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2171
2172 vcpu->mmio_needed = 1;
2173 vcpu->mmio_phys_addr = gpa;
2174 vcpu->mmio_size = bytes;
2175 vcpu->mmio_is_write = 0;
2176
2177 return X86EMUL_UNHANDLEABLE;
2178}
2179
3200f405 2180int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2181 const void *val, int bytes)
bbd9b64e
CO		 2182{
2183 int ret;
2184
2185 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2186 if (ret < 0)
bbd9b64e 2187 return 0;
ad218f85 2188 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2189 return 1;
2190}
2191
2192static int emulator_write_emulated_onepage(unsigned long addr,
2193 const void *val,
2194 unsigned int bytes,
2195 struct kvm_vcpu *vcpu)
2196{
2197 struct kvm_io_device *mmio_dev;
10589a46
MT		 2198 gpa_t gpa;
2199
10589a46 2200 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2201
2202 if (gpa == UNMAPPED_GVA) {
c3c91fee 2203 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2204 return X86EMUL_PROPAGATE_FAULT;
2205 }
2206
2207 /* For APIC access vmexit */
2208 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2209 goto mmio;
2210
2211 if (emulator_write_phys(vcpu, gpa, val, bytes))
2212 return X86EMUL_CONTINUE;
2213
2214mmio:
2215 /*
2216 * Is this MMIO handled locally?
2217 */
10589a46 2218 mutex_lock(&vcpu->kvm->lock);
92760499 2219 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2220 if (mmio_dev) {
2221 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2222 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2223 return X86EMUL_CONTINUE;
2224 }
10589a46 2225 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2226
2227 vcpu->mmio_needed = 1;
2228 vcpu->mmio_phys_addr = gpa;
2229 vcpu->mmio_size = bytes;
2230 vcpu->mmio_is_write = 1;
2231 memcpy(vcpu->mmio_data, val, bytes);
2232
2233 return X86EMUL_CONTINUE;
2234}
2235
2236int emulator_write_emulated(unsigned long addr,
2237 const void *val,
2238 unsigned int bytes,
2239 struct kvm_vcpu *vcpu)
2240{
2241 /* Crossing a page boundary? */
2242 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2243 int rc, now;
2244
2245 now = -addr & ~PAGE_MASK;
2246 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2247 if (rc != X86EMUL_CONTINUE)
2248 return rc;
2249 addr += now;
2250 val += now;
2251 bytes -= now;
2252 }
2253 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2254}
2255EXPORT_SYMBOL_GPL(emulator_write_emulated);
2256
2257static int emulator_cmpxchg_emulated(unsigned long addr,
2258 const void *old,
2259 const void *new,
2260 unsigned int bytes,
2261 struct kvm_vcpu *vcpu)
2262{
2263 static int reported;
2264
2265 if (!reported) {
2266 reported = 1;
2267 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2268 }
2bacc55c
MT		 2269#ifndef CONFIG_X86_64
2270 /* guests cmpxchg8b have to be emulated atomically */
2271 if (bytes == 8) {
10589a46 2272 gpa_t gpa;
2bacc55c 2273 struct page *page;
c0b49b0d 2274 char *kaddr;
2bacc55c
MT		 2275 u64 val;
2276
10589a46
MT		 2277 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2278
2bacc55c
MT		 2279 if (gpa == UNMAPPED_GVA ||
2280 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2281 goto emul_write;
2282
2283 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2284 goto emul_write;
2285
2286 val = *(u64 *)new;
72dc67a6 2287
2bacc55c 2288 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2289
c0b49b0d
AM		 2290 kaddr = kmap_atomic(page, KM_USER0);
2291 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2292 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2293 kvm_release_page_dirty(page);
2294 }
3200f405 2295emul_write:
2bacc55c
MT		 2296#endif
2297
bbd9b64e
CO		 2298 return emulator_write_emulated(addr, new, bytes, vcpu);
2299}
2300
2301static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2302{
2303 return kvm_x86_ops->get_segment_base(vcpu, seg);
2304}
2305
2306int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2307{
a7052897 2308 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2309 return X86EMUL_CONTINUE;
2310}
2311
2312int emulate_clts(struct kvm_vcpu *vcpu)
2313{
54e445ca 2314 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2315 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2316 return X86EMUL_CONTINUE;
2317}
2318
2319int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2320{
2321 struct kvm_vcpu *vcpu = ctxt->vcpu;
2322
2323 switch (dr) {
2324 case 0 ... 3:
2325 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2326 return X86EMUL_CONTINUE;
2327 default:
b8688d51 2328 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2329 return X86EMUL_UNHANDLEABLE;
2330 }
2331}
2332
2333int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2334{
2335 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2336 int exception;
2337
2338 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2339 if (exception) {
2340 /* FIXME: better handling */
2341 return X86EMUL_UNHANDLEABLE;
2342 }
2343 return X86EMUL_CONTINUE;
2344}
2345
2346void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2347{
bbd9b64e 2348 u8 opcodes[4];
5fdbf976 2349 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2350 unsigned long rip_linear;
2351
f76c710d 2352 if (!printk_ratelimit())
bbd9b64e
CO		 2353 return;
2354
25be4608
GC		 2355 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2356
77c2002e 2357 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2358
2359 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2360 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2361}
2362EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2363
14af3f3c 2364static struct x86_emulate_ops emulate_ops = {
77c2002e 2365 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2366 .read_emulated = emulator_read_emulated,
2367 .write_emulated = emulator_write_emulated,
2368 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2369};
2370
5fdbf976
MT		 2371static void cache_all_regs(struct kvm_vcpu *vcpu)
2372{
2373 kvm_register_read(vcpu, VCPU_REGS_RAX);
2374 kvm_register_read(vcpu, VCPU_REGS_RSP);
2375 kvm_register_read(vcpu, VCPU_REGS_RIP);
2376 vcpu->arch.regs_dirty = ~0;
2377}
2378
bbd9b64e
CO		 2379int emulate_instruction(struct kvm_vcpu *vcpu,
2380 struct kvm_run *run,
2381 unsigned long cr2,
2382 u16 error_code,
571008da 2383 int emulation_type)
bbd9b64e 2384{
310b5d30 2385 int r, shadow_mask;
571008da 2386 struct decode_cache *c;
bbd9b64e 2387
26eef70c 2388 kvm_clear_exception_queue(vcpu);
ad312c7c 2389 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2390 /*
2391 * TODO: fix x86_emulate.c to use guest_read/write_register
2392 * instead of direct ->regs accesses, can save hundred cycles
2393 * on Intel for instructions that don't read/change RSP, for
2394 * for example.
2395 */
2396 cache_all_regs(vcpu);
bbd9b64e
CO		 2397
2398 vcpu->mmio_is_write = 0;
ad312c7c 2399 vcpu->arch.pio.string = 0;
bbd9b64e 2400
571008da 2401 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2402 int cs_db, cs_l;
2403 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2404
ad312c7c
ZX		 2405 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2406 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2407 vcpu->arch.emulate_ctxt.mode =
2408 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2409 ? X86EMUL_MODE_REAL : cs_l
2410 ? X86EMUL_MODE_PROT64 : cs_db
2411 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2412
ad312c7c 2413 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2414
2415 /* Reject the instructions other than VMCALL/VMMCALL when
2416 * try to emulate invalid opcode */
2417 c = &vcpu->arch.emulate_ctxt.decode;
2418 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2419 (!(c->twobyte && c->b == 0x01 &&
2420 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2421 c->modrm_mod == 3 && c->modrm_rm == 1)))
2422 return EMULATE_FAIL;
2423
f2b5756b 2424 ++vcpu->stat.insn_emulation;
bbd9b64e 2425 if (r) {
f2b5756b 2426 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2427 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2428 return EMULATE_DONE;
2429 return EMULATE_FAIL;
2430 }
2431 }
2432
ba8afb6b
GN		 2433 if (emulation_type & EMULTYPE_SKIP) {
2434 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2435 return EMULATE_DONE;
2436 }
2437
ad312c7c 2438 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2439 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2440
2441 if (r == 0)
2442 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2443
ad312c7c 2444 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2445 return EMULATE_DO_MMIO;
2446
2447 if ((r || vcpu->mmio_is_write) && run) {
2448 run->exit_reason = KVM_EXIT_MMIO;
2449 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2450 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2451 run->mmio.len = vcpu->mmio_size;
2452 run->mmio.is_write = vcpu->mmio_is_write;
2453 }
2454
2455 if (r) {
2456 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2457 return EMULATE_DONE;
2458 if (!vcpu->mmio_needed) {
2459 kvm_report_emulation_failure(vcpu, "mmio");
2460 return EMULATE_FAIL;
2461 }
2462 return EMULATE_DO_MMIO;
2463 }
2464
ad312c7c 2465 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2466
2467 if (vcpu->mmio_is_write) {
2468 vcpu->mmio_needed = 0;
2469 return EMULATE_DO_MMIO;
2470 }
2471
2472 return EMULATE_DONE;
2473}
2474EXPORT_SYMBOL_GPL(emulate_instruction);
2475
de7d789a
CO		 2476static int pio_copy_data(struct kvm_vcpu *vcpu)
2477{
ad312c7c 2478 void *p = vcpu->arch.pio_data;
0f346074 2479 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2480 unsigned bytes;
0f346074 2481 int ret;
de7d789a 2482
ad312c7c
ZX		 2483 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2484 if (vcpu->arch.pio.in)
0f346074 2485 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2486 else
0f346074
IE		 2487 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2488 return ret;
de7d789a
CO		 2489}
2490
2491int complete_pio(struct kvm_vcpu *vcpu)
2492{
ad312c7c 2493 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2494 long delta;
2495 int r;
5fdbf976 2496 unsigned long val;
de7d789a
CO		 2497
2498 if (!io->string) {
5fdbf976
MT		 2499 if (io->in) {
2500 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2501 memcpy(&val, vcpu->arch.pio_data, io->size);
2502 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2503 }
de7d789a
CO		 2504 } else {
2505 if (io->in) {
2506 r = pio_copy_data(vcpu);
5fdbf976 2507 if (r)
de7d789a 2508 return r;
de7d789a
CO		 2509 }
2510
2511 delta = 1;
2512 if (io->rep) {
2513 delta *= io->cur_count;
2514 /*
2515 * The size of the register should really depend on
2516 * current address size.
2517 */
5fdbf976
MT		 2518 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2519 val -= delta;
2520 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2521 }
2522 if (io->down)
2523 delta = -delta;
2524 delta *= io->size;
5fdbf976
MT		 2525 if (io->in) {
2526 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2527 val += delta;
2528 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2529 } else {
2530 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2531 val += delta;
2532 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2533 }
de7d789a
CO		 2534 }
2535
de7d789a
CO		 2536 io->count -= io->cur_count;
2537 io->cur_count = 0;
2538
2539 return 0;
2540}
2541
2542static void kernel_pio(struct kvm_io_device *pio_dev,
2543 struct kvm_vcpu *vcpu,
2544 void *pd)
2545{
2546 /* TODO: String I/O for in kernel device */
2547
2548 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2549 if (vcpu->arch.pio.in)
2550 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2551 vcpu->arch.pio.size,
de7d789a
CO		 2552 pd);
2553 else
ad312c7c
ZX		 2554 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2555 vcpu->arch.pio.size,
de7d789a
CO		 2556 pd);
2557 mutex_unlock(&vcpu->kvm->lock);
2558}
2559
2560static void pio_string_write(struct kvm_io_device *pio_dev,
2561 struct kvm_vcpu *vcpu)
2562{
ad312c7c
ZX		 2563 struct kvm_pio_request *io = &vcpu->arch.pio;
2564 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2565 int i;
2566
2567 mutex_lock(&vcpu->kvm->lock);
2568 for (i = 0; i < io->cur_count; i++) {
2569 kvm_iodevice_write(pio_dev, io->port,
2570 io->size,
2571 pd);
2572 pd += io->size;
2573 }
2574 mutex_unlock(&vcpu->kvm->lock);
2575}
2576
2577static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2578 gpa_t addr, int len,
2579 int is_write)
de7d789a 2580{
92760499 2581 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2582}
2583
2584int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2585 int size, unsigned port)
2586{
2587 struct kvm_io_device *pio_dev;
5fdbf976 2588 unsigned long val;
de7d789a
CO		 2589
2590 vcpu->run->exit_reason = KVM_EXIT_IO;
2591 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2592 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2593 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2594 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2595 vcpu->run->io.port = vcpu->arch.pio.port = port;
2596 vcpu->arch.pio.in = in;
2597 vcpu->arch.pio.string = 0;
2598 vcpu->arch.pio.down = 0;
ad312c7c 2599 vcpu->arch.pio.rep = 0;
de7d789a 2600
2714d1d3
FEL		 2601 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2602 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2603 handler);
2604 else
2605 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2606 handler);
2607
5fdbf976
MT		 2608 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2609 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2610
92760499 2611 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2612 if (pio_dev) {
ad312c7c 2613 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2614 complete_pio(vcpu);
2615 return 1;
2616 }
2617 return 0;
2618}
2619EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2620
2621int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2622 int size, unsigned long count, int down,
2623 gva_t address, int rep, unsigned port)
2624{
2625 unsigned now, in_page;
0f346074 2626 int ret = 0;
de7d789a
CO		 2627 struct kvm_io_device *pio_dev;
2628
2629 vcpu->run->exit_reason = KVM_EXIT_IO;
2630 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2631 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2632 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2633 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2634 vcpu->run->io.port = vcpu->arch.pio.port = port;
2635 vcpu->arch.pio.in = in;
2636 vcpu->arch.pio.string = 1;
2637 vcpu->arch.pio.down = down;
ad312c7c 2638 vcpu->arch.pio.rep = rep;
de7d789a 2639
2714d1d3
FEL		 2640 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2641 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2642 handler);
2643 else
2644 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2645 handler);
2646
de7d789a
CO		 2647 if (!count) {
2648 kvm_x86_ops->skip_emulated_instruction(vcpu);
2649 return 1;
2650 }
2651
2652 if (!down)
2653 in_page = PAGE_SIZE - offset_in_page(address);
2654 else
2655 in_page = offset_in_page(address) + size;
2656 now = min(count, (unsigned long)in_page / size);
0f346074 2657 if (!now)
de7d789a 2658 now = 1;
de7d789a
CO		 2659 if (down) {
2660 /*
2661 * String I/O in reverse. Yuck. Kill the guest, fix later.
2662 */
2663 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2664 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2665 return 1;
2666 }
2667 vcpu->run->io.count = now;
ad312c7c 2668 vcpu->arch.pio.cur_count = now;
de7d789a 2669
ad312c7c 2670 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2671 kvm_x86_ops->skip_emulated_instruction(vcpu);
2672
0f346074 2673 vcpu->arch.pio.guest_gva = address;
de7d789a 2674
92760499
LV		 2675 pio_dev = vcpu_find_pio_dev(vcpu, port,
2676 vcpu->arch.pio.cur_count,
2677 !vcpu->arch.pio.in);
ad312c7c 2678 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2679 /* string PIO write */
2680 ret = pio_copy_data(vcpu);
0f346074
IE		 2681 if (ret == X86EMUL_PROPAGATE_FAULT) {
2682 kvm_inject_gp(vcpu, 0);
2683 return 1;
2684 }
2685 if (ret == 0 && pio_dev) {
de7d789a
CO		 2686 pio_string_write(pio_dev, vcpu);
2687 complete_pio(vcpu);
ad312c7c 2688 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2689 ret = 1;
2690 }
2691 } else if (pio_dev)
2692 pr_unimpl(vcpu, "no string pio read support yet, "
2693 "port %x size %d count %ld\n",
2694 port, size, count);
2695
2696 return ret;
2697}
2698EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2699
c8076604
GH		 2700static void bounce_off(void *info)
2701{
2702 /* nothing */
2703}
2704
2705static unsigned int ref_freq;
2706static unsigned long tsc_khz_ref;
2707
2708static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2709 void *data)
2710{
2711 struct cpufreq_freqs *freq = data;
2712 struct kvm *kvm;
2713 struct kvm_vcpu *vcpu;
2714 int i, send_ipi = 0;
2715
2716 if (!ref_freq)
2717 ref_freq = freq->old;
2718
2719 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
2720 return 0;
2721 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
2722 return 0;
2723 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
2724
2725 spin_lock(&kvm_lock);
2726 list_for_each_entry(kvm, &vm_list, vm_list) {
2727 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
2728 vcpu = kvm->vcpus[i];
2729 if (!vcpu)
2730 continue;
2731 if (vcpu->cpu != freq->cpu)
2732 continue;
2733 if (!kvm_request_guest_time_update(vcpu))
2734 continue;
2735 if (vcpu->cpu != smp_processor_id())
2736 send_ipi++;
2737 }
2738 }
2739 spin_unlock(&kvm_lock);
2740
2741 if (freq->old < freq->new && send_ipi) {
2742 /*
2743 * We upscale the frequency. Must make the guest
2744 * doesn't see old kvmclock values while running with
2745 * the new frequency, otherwise we risk the guest sees
2746 * time go backwards.
2747 *
2748 * In case we update the frequency for another cpu
2749 * (which might be in guest context) send an interrupt
2750 * to kick the cpu out of guest context. Next time
2751 * guest context is entered kvmclock will be updated,
2752 * so the guest will not see stale values.
2753 */
2754 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
2755 }
2756 return 0;
2757}
2758
2759static struct notifier_block kvmclock_cpufreq_notifier_block = {
2760 .notifier_call = kvmclock_cpufreq_notifier
2761};
2762
f8c16bba 2763int kvm_arch_init(void *opaque)
043405e1 2764{
c8076604 2765 int r, cpu;
f8c16bba
ZX		 2766 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2767
f8c16bba
ZX		 2768 if (kvm_x86_ops) {
2769 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2770 r = -EEXIST;
2771 goto out;
f8c16bba
ZX		 2772 }
2773
2774 if (!ops->cpu_has_kvm_support()) {
2775 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2776 r = -EOPNOTSUPP;
2777 goto out;
f8c16bba
ZX		 2778 }
2779 if (ops->disabled_by_bios()) {
2780 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2781 r = -EOPNOTSUPP;
2782 goto out;
f8c16bba
ZX		 2783 }
2784
97db56ce
AK		 2785 r = kvm_mmu_module_init();
2786 if (r)
2787 goto out;
2788
2789 kvm_init_msr_list();
2790
f8c16bba 2791 kvm_x86_ops = ops;
56c6d28a 2792 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2793 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2794 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 2795 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 2796
2797 for_each_possible_cpu(cpu)
2798 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
2799 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
2800 tsc_khz_ref = tsc_khz;
2801 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
2802 CPUFREQ_TRANSITION_NOTIFIER);
2803 }
2804
f8c16bba 2805 return 0;
56c6d28a
ZX		 2806
2807out:
56c6d28a 2808 return r;
043405e1 2809}
8776e519 2810
f8c16bba
ZX		 2811void kvm_arch_exit(void)
2812{
888d256e
JK		 2813 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
2814 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
2815 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 2816 kvm_x86_ops = NULL;
56c6d28a
ZX		 2817 kvm_mmu_module_exit();
2818}
f8c16bba 2819
8776e519
HB		 2820int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2821{
2822 ++vcpu->stat.halt_exits;
2714d1d3 2823 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2824 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2825 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2826 return 1;
2827 } else {
2828 vcpu->run->exit_reason = KVM_EXIT_HLT;
2829 return 0;
2830 }
2831}
2832EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2833
2f333bcb
MT		 2834static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2835 unsigned long a1)
2836{
2837 if (is_long_mode(vcpu))
2838 return a0;
2839 else
2840 return a0 | ((gpa_t)a1 << 32);
2841}
2842
8776e519
HB		 2843int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2844{
2845 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2846 int r = 1;
8776e519 2847
5fdbf976
MT		 2848 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2849 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2850 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2851 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2852 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2853
2714d1d3
FEL		 2854 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2855
8776e519
HB		 2856 if (!is_long_mode(vcpu)) {
2857 nr &= 0xFFFFFFFF;
2858 a0 &= 0xFFFFFFFF;
2859 a1 &= 0xFFFFFFFF;
2860 a2 &= 0xFFFFFFFF;
2861 a3 &= 0xFFFFFFFF;
2862 }
2863
2864 switch (nr) {
b93463aa
AK		 2865 case KVM_HC_VAPIC_POLL_IRQ:
2866 ret = 0;
2867 break;
2f333bcb
MT		 2868 case KVM_HC_MMU_OP:
2869 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2870 break;
8776e519
HB		 2871 default:
2872 ret = -KVM_ENOSYS;
2873 break;
2874 }
5fdbf976 2875 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2876 ++vcpu->stat.hypercalls;
2f333bcb 2877 return r;
8776e519
HB		 2878}
2879EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2880
2881int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2882{
2883 char instruction[3];
2884 int ret = 0;
5fdbf976 2885 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2886
8776e519
HB		 2887
2888 /*
2889 * Blow out the MMU to ensure that no other VCPU has an active mapping
2890 * to ensure that the updated hypercall appears atomically across all
2891 * VCPUs.
2892 */
2893 kvm_mmu_zap_all(vcpu->kvm);
2894
8776e519 2895 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2896 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2897 != X86EMUL_CONTINUE)
2898 ret = -EFAULT;
2899
8776e519
HB		 2900 return ret;
2901}
2902
2903static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2904{
2905 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2906}
2907
2908void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2909{
2910 struct descriptor_table dt = { limit, base };
2911
2912 kvm_x86_ops->set_gdt(vcpu, &dt);
2913}
2914
2915void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2916{
2917 struct descriptor_table dt = { limit, base };
2918
2919 kvm_x86_ops->set_idt(vcpu, &dt);
2920}
2921
2922void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2923 unsigned long *rflags)
2924{
2d3ad1f4 2925 kvm_lmsw(vcpu, msw);
8776e519
HB		 2926 *rflags = kvm_x86_ops->get_rflags(vcpu);
2927}
2928
2929unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2930{
54e445ca
JR		 2931 unsigned long value;
2932
8776e519
HB		 2933 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2934 switch (cr) {
2935 case 0:
54e445ca
JR		 2936 value = vcpu->arch.cr0;
2937 break;
8776e519 2938 case 2:
54e445ca
JR		 2939 value = vcpu->arch.cr2;
2940 break;
8776e519 2941 case 3:
54e445ca
JR		 2942 value = vcpu->arch.cr3;
2943 break;
8776e519 2944 case 4:
54e445ca
JR		 2945 value = vcpu->arch.cr4;
2946 break;
152ff9be 2947 case 8:
54e445ca
JR		 2948 value = kvm_get_cr8(vcpu);
2949 break;
8776e519 2950 default:
b8688d51 2951 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2952 return 0;
2953 }
54e445ca
JR		 2954 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2955 (u32)((u64)value >> 32), handler);
2956
2957 return value;
8776e519
HB		 2958}
2959
2960void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2961 unsigned long *rflags)
2962{
54e445ca
JR		 2963 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2964 (u32)((u64)val >> 32), handler);
2965
8776e519
HB		 2966 switch (cr) {
2967 case 0:
2d3ad1f4 2968 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2969 *rflags = kvm_x86_ops->get_rflags(vcpu);
2970 break;
2971 case 2:
ad312c7c 2972 vcpu->arch.cr2 = val;
8776e519
HB		 2973 break;
2974 case 3:
2d3ad1f4 2975 kvm_set_cr3(vcpu, val);
8776e519
HB		 2976 break;
2977 case 4:
2d3ad1f4 2978 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2979 break;
152ff9be 2980 case 8:
2d3ad1f4 2981 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2982 break;
8776e519 2983 default:
b8688d51 2984 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2985 }
2986}
2987
07716717
DK		 2988static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2989{
ad312c7c
ZX		 2990 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2991 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2992
2993 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2994 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 2995 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 2996 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2997 if (ej->function == e->function) {
2998 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2999 return j;
3000 }
3001 }
3002 return 0; /* silence gcc, even though control never reaches here */
3003}
3004
3005/* find an entry with matching function, matching index (if needed), and that
3006 * should be read next (if it's stateful) */
3007static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3008 u32 function, u32 index)
3009{
3010 if (e->function != function)
3011 return 0;
3012 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3013 return 0;
3014 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3015 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3016 return 0;
3017 return 1;
3018}
3019
d8017474
AG		 3020struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3021 u32 function, u32 index)
8776e519
HB		 3022{
3023 int i;
d8017474 3024 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3025
ad312c7c 3026 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3027 struct kvm_cpuid_entry2 *e;
3028
ad312c7c 3029 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3030 if (is_matching_cpuid_entry(e, function, index)) {
3031 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3032 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3033 best = e;
3034 break;
3035 }
3036 /*
3037 * Both basic or both extended?
3038 */
3039 if (((e->function ^ function) & 0x80000000) == 0)
3040 if (!best || e->function > best->function)
3041 best = e;
3042 }
d8017474
AG		 3043 return best;
3044}
3045
82725b20
DE		 3046int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3047{
3048 struct kvm_cpuid_entry2 *best;
3049
3050 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3051 if (best)
3052 return best->eax & 0xff;
3053 return 36;
3054}
3055
d8017474
AG		 3056void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3057{
3058 u32 function, index;
3059 struct kvm_cpuid_entry2 *best;
3060
3061 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3062 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3063 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3064 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3065 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3066 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3067 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3068 if (best) {
5fdbf976
MT		 3069 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3070 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3071 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3072 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3073 }
8776e519 3074 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 3075 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 3076 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
3077 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
3078 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
3079 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 3080}
3081EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3082
b6c7a5dc
HB		 3083/*
3084 * Check if userspace requested an interrupt window, and that the
3085 * interrupt window is open.
3086 *
3087 * No need to exit to userspace if we already have an interrupt queued.
3088 */
3089static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3090 struct kvm_run *kvm_run)
3091{
8061823a 3092 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3093 kvm_run->request_interrupt_window &&
5df56646 3094 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3095}
3096
3097static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3098 struct kvm_run *kvm_run)
3099{
3100 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3101 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3102 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3103 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3104 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3105 else
b6c7a5dc 3106 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3107 kvm_arch_interrupt_allowed(vcpu) &&
3108 !kvm_cpu_has_interrupt(vcpu) &&
3109 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3110}
3111
b93463aa
AK		 3112static void vapic_enter(struct kvm_vcpu *vcpu)
3113{
3114 struct kvm_lapic *apic = vcpu->arch.apic;
3115 struct page *page;
3116
3117 if (!apic || !apic->vapic_addr)
3118 return;
3119
3120 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3121
3122 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3123}
3124
3125static void vapic_exit(struct kvm_vcpu *vcpu)
3126{
3127 struct kvm_lapic *apic = vcpu->arch.apic;
3128
3129 if (!apic || !apic->vapic_addr)
3130 return;
3131
f8b78fa3 3132 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3133 kvm_release_page_dirty(apic->vapic_page);
3134 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3135 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3136}
3137
95ba8273
GN		 3138static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3139{
3140 int max_irr, tpr;
3141
3142 if (!kvm_x86_ops->update_cr8_intercept)
3143 return;
3144
3145 max_irr = kvm_lapic_find_highest_irr(vcpu);
3146
3147 if (max_irr != -1)
3148 max_irr >>= 4;
3149
3150 tpr = kvm_lapic_get_cr8(vcpu);
3151
3152 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3153}
3154
6a8b1d13 3155static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273 3156{
6a8b1d13
GN		 3157 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3158 kvm_x86_ops->set_interrupt_shadow(vcpu, 0);
3159
95ba8273
GN		 3160 /* try to reinject previous events if any */
3161 if (vcpu->arch.nmi_injected) {
3162 kvm_x86_ops->set_nmi(vcpu);
3163 return;
3164 }
3165
3166 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3167 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3168 return;
3169 }
3170
3171 /* try to inject new event if pending */
3172 if (vcpu->arch.nmi_pending) {
3173 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3174 vcpu->arch.nmi_pending = false;
3175 vcpu->arch.nmi_injected = true;
3176 kvm_x86_ops->set_nmi(vcpu);
3177 }
3178 } else if (kvm_cpu_has_interrupt(vcpu)) {
3179 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3180 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3181 false);
3182 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3183 }
3184 }
3185}
3186
d7690175 3187static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3188{
3189 int r;
6a8b1d13
GN		 3190 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3191 kvm_run->request_interrupt_window;
b6c7a5dc 3192
2e53d63a
MT		 3193 if (vcpu->requests)
3194 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3195 kvm_mmu_unload(vcpu);
3196
b6c7a5dc
HB		 3197 r = kvm_mmu_reload(vcpu);
3198 if (unlikely(r))
3199 goto out;
3200
2f52d58c
AK		 3201 if (vcpu->requests) {
3202 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3203 __kvm_migrate_timers(vcpu);
c8076604
GH		 3204 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3205 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3206 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3207 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3208 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3209 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3210 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3211 &vcpu->requests)) {
3212 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3213 r = 0;
3214 goto out;
3215 }
71c4dfaf
JR		 3216 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3217 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3218 r = 0;
3219 goto out;
3220 }
2f52d58c 3221 }
b93463aa 3222
b6c7a5dc
HB		 3223 preempt_disable();
3224
3225 kvm_x86_ops->prepare_guest_switch(vcpu);
3226 kvm_load_guest_fpu(vcpu);
3227
3228 local_irq_disable();
3229
32f88400
MT		 3230 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3231 smp_mb__after_clear_bit();
3232
d7690175 3233 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3234 local_irq_enable();
3235 preempt_enable();
3236 r = 1;
3237 goto out;
3238 }
3239
ad312c7c 3240 if (vcpu->arch.exception.pending)
298101da 3241 __queue_exception(vcpu);
eb9774f0 3242 else
95ba8273 3243 inject_pending_irq(vcpu, kvm_run);
b6c7a5dc 3244
6a8b1d13
GN		 3245 /* enable NMI/IRQ window open exits if needed */
3246 if (vcpu->arch.nmi_pending)
3247 kvm_x86_ops->enable_nmi_window(vcpu);
3248 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3249 kvm_x86_ops->enable_irq_window(vcpu);
3250
95ba8273
GN		 3251 if (kvm_lapic_enabled(vcpu)) {
3252 if (!vcpu->arch.apic->vapic_addr)
3253 update_cr8_intercept(vcpu);
3254 else
3255 kvm_lapic_sync_to_vapic(vcpu);
3256 }
b93463aa 3257
3200f405
MT		 3258 up_read(&vcpu->kvm->slots_lock);
3259
b6c7a5dc
HB		 3260 kvm_guest_enter();
3261
42dbaa5a
JK		 3262 get_debugreg(vcpu->arch.host_dr6, 6);
3263 get_debugreg(vcpu->arch.host_dr7, 7);
3264 if (unlikely(vcpu->arch.switch_db_regs)) {
3265 get_debugreg(vcpu->arch.host_db[0], 0);
3266 get_debugreg(vcpu->arch.host_db[1], 1);
3267 get_debugreg(vcpu->arch.host_db[2], 2);
3268 get_debugreg(vcpu->arch.host_db[3], 3);
3269
3270 set_debugreg(0, 7);
3271 set_debugreg(vcpu->arch.eff_db[0], 0);
3272 set_debugreg(vcpu->arch.eff_db[1], 1);
3273 set_debugreg(vcpu->arch.eff_db[2], 2);
3274 set_debugreg(vcpu->arch.eff_db[3], 3);
3275 }
b6c7a5dc 3276
2714d1d3 3277 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3278 kvm_x86_ops->run(vcpu, kvm_run);
3279
42dbaa5a
JK		 3280 if (unlikely(vcpu->arch.switch_db_regs)) {
3281 set_debugreg(0, 7);
3282 set_debugreg(vcpu->arch.host_db[0], 0);
3283 set_debugreg(vcpu->arch.host_db[1], 1);
3284 set_debugreg(vcpu->arch.host_db[2], 2);
3285 set_debugreg(vcpu->arch.host_db[3], 3);
3286 }
3287 set_debugreg(vcpu->arch.host_dr6, 6);
3288 set_debugreg(vcpu->arch.host_dr7, 7);
3289
32f88400 3290 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3291 local_irq_enable();
3292
3293 ++vcpu->stat.exits;
3294
3295 /*
3296 * We must have an instruction between local_irq_enable() and
3297 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3298 * the interrupt shadow. The stat.exits increment will do nicely.
3299 * But we need to prevent reordering, hence this barrier():
3300 */
3301 barrier();
3302
3303 kvm_guest_exit();
3304
3305 preempt_enable();
3306
3200f405
MT		 3307 down_read(&vcpu->kvm->slots_lock);
3308
b6c7a5dc
HB		 3309 /*
3310 * Profile KVM exit RIPs:
3311 */
3312 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3313 unsigned long rip = kvm_rip_read(vcpu);
3314 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3315 }
3316
298101da 3317
b93463aa
AK		 3318 kvm_lapic_sync_from_vapic(vcpu);
3319
b6c7a5dc 3320 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3321out:
3322 return r;
3323}
b6c7a5dc 3324
09cec754 3325
d7690175
MT		 3326static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3327{
3328 int r;
3329
3330 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3331 pr_debug("vcpu %d received sipi with vector # %x\n",
3332 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3333 kvm_lapic_reset(vcpu);
5f179287 3334 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3335 if (r)
3336 return r;
3337 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3338 }
3339
d7690175
MT		 3340 down_read(&vcpu->kvm->slots_lock);
3341 vapic_enter(vcpu);
3342
3343 r = 1;
3344 while (r > 0) {
af2152f5 3345 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3346 r = vcpu_enter_guest(vcpu, kvm_run);
3347 else {
3348 up_read(&vcpu->kvm->slots_lock);
3349 kvm_vcpu_block(vcpu);
3350 down_read(&vcpu->kvm->slots_lock);
3351 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3352 {
3353 switch(vcpu->arch.mp_state) {
3354 case KVM_MP_STATE_HALTED:
d7690175 3355 vcpu->arch.mp_state =
09cec754
GN		 3356 KVM_MP_STATE_RUNNABLE;
3357 case KVM_MP_STATE_RUNNABLE:
3358 break;
3359 case KVM_MP_STATE_SIPI_RECEIVED:
3360 default:
3361 r = -EINTR;
3362 break;
3363 }
3364 }
d7690175
MT		 3365 }
3366
09cec754
GN		 3367 if (r <= 0)
3368 break;
3369
3370 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3371 if (kvm_cpu_has_pending_timer(vcpu))
3372 kvm_inject_pending_timer_irqs(vcpu);
3373
3374 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3375 r = -EINTR;
3376 kvm_run->exit_reason = KVM_EXIT_INTR;
3377 ++vcpu->stat.request_irq_exits;
3378 }
3379 if (signal_pending(current)) {
3380 r = -EINTR;
3381 kvm_run->exit_reason = KVM_EXIT_INTR;
3382 ++vcpu->stat.signal_exits;
3383 }
3384 if (need_resched()) {
3385 up_read(&vcpu->kvm->slots_lock);
3386 kvm_resched(vcpu);
3387 down_read(&vcpu->kvm->slots_lock);
d7690175 3388 }
b6c7a5dc
HB		 3389 }
3390
d7690175 3391 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3392 post_kvm_run_save(vcpu, kvm_run);
3393
b93463aa
AK		 3394 vapic_exit(vcpu);
3395
b6c7a5dc
HB		 3396 return r;
3397}
3398
3399int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3400{
3401 int r;
3402 sigset_t sigsaved;
3403
3404 vcpu_load(vcpu);
3405
ac9f6dc0
AK		 3406 if (vcpu->sigset_active)
3407 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3408
a4535290 3409 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3410 kvm_vcpu_block(vcpu);
d7690175 3411 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3412 r = -EAGAIN;
3413 goto out;
b6c7a5dc
HB		 3414 }
3415
b6c7a5dc
HB		 3416 /* re-sync apic's tpr */
3417 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3418 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3419
ad312c7c 3420 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3421 r = complete_pio(vcpu);
3422 if (r)
3423 goto out;
3424 }
3425#if CONFIG_HAS_IOMEM
3426 if (vcpu->mmio_needed) {
3427 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3428 vcpu->mmio_read_completed = 1;
3429 vcpu->mmio_needed = 0;
3200f405
MT		 3430
3431 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3432 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3433 vcpu->arch.mmio_fault_cr2, 0,
3434 EMULTYPE_NO_DECODE);
3200f405 3435 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3436 if (r == EMULATE_DO_MMIO) {
3437 /*
3438 * Read-modify-write. Back to userspace.
3439 */
3440 r = 0;
3441 goto out;
3442 }
3443 }
3444#endif
5fdbf976
MT		 3445 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3446 kvm_register_write(vcpu, VCPU_REGS_RAX,
3447 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3448
3449 r = __vcpu_run(vcpu, kvm_run);
3450
3451out:
3452 if (vcpu->sigset_active)
3453 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3454
3455 vcpu_put(vcpu);
3456 return r;
3457}
3458
3459int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3460{
3461 vcpu_load(vcpu);
3462
5fdbf976
MT		 3463 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3464 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3465 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3466 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3467 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3468 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3469 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3470 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3471#ifdef CONFIG_X86_64
5fdbf976
MT		 3472 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3473 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3474 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3475 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3476 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3477 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3478 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3479 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3480#endif
3481
5fdbf976 3482 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3483 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3484
3485 /*
3486 * Don't leak debug flags in case they were set for guest debugging
3487 */
d0bfb940 3488 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3489 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3490
3491 vcpu_put(vcpu);
3492
3493 return 0;
3494}
3495
3496int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3497{
3498 vcpu_load(vcpu);
3499
5fdbf976
MT		 3500 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3501 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3502 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3503 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3504 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3505 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3506 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3507 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3508#ifdef CONFIG_X86_64
5fdbf976
MT		 3509 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3510 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3511 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3512 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3513 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3514 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3515 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3516 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3517
b6c7a5dc
HB		 3518#endif
3519
5fdbf976 3520 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3521 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3522
b6c7a5dc 3523
b4f14abd
JK		 3524 vcpu->arch.exception.pending = false;
3525
b6c7a5dc
HB		 3526 vcpu_put(vcpu);
3527
3528 return 0;
3529}
3530
3e6e0aab
GT		 3531void kvm_get_segment(struct kvm_vcpu *vcpu,
3532 struct kvm_segment *var, int seg)
b6c7a5dc 3533{
14af3f3c 3534 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3535}
3536
3537void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3538{
3539 struct kvm_segment cs;
3540
3e6e0aab 3541 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3542 *db = cs.db;
3543 *l = cs.l;
3544}
3545EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3546
3547int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3548 struct kvm_sregs *sregs)
3549{
3550 struct descriptor_table dt;
b6c7a5dc
HB		 3551
3552 vcpu_load(vcpu);
3553
3e6e0aab
GT		 3554 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3555 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3556 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3557 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3558 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3559 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3560
3e6e0aab
GT		 3561 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3562 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3563
3564 kvm_x86_ops->get_idt(vcpu, &dt);
3565 sregs->idt.limit = dt.limit;
3566 sregs->idt.base = dt.base;
3567 kvm_x86_ops->get_gdt(vcpu, &dt);
3568 sregs->gdt.limit = dt.limit;
3569 sregs->gdt.base = dt.base;
3570
3571 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3572 sregs->cr0 = vcpu->arch.cr0;
3573 sregs->cr2 = vcpu->arch.cr2;
3574 sregs->cr3 = vcpu->arch.cr3;
3575 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3576 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3577 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3578 sregs->apic_base = kvm_get_apic_base(vcpu);
3579
923c61bb 3580 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3581
36752c9b 3582 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3583 set_bit(vcpu->arch.interrupt.nr,
3584 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3585
b6c7a5dc
HB		 3586 vcpu_put(vcpu);
3587
3588 return 0;
3589}
3590
62d9f0db
MT		 3591int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3592 struct kvm_mp_state *mp_state)
3593{
3594 vcpu_load(vcpu);
3595 mp_state->mp_state = vcpu->arch.mp_state;
3596 vcpu_put(vcpu);
3597 return 0;
3598}
3599
3600int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3601 struct kvm_mp_state *mp_state)
3602{
3603 vcpu_load(vcpu);
3604 vcpu->arch.mp_state = mp_state->mp_state;
3605 vcpu_put(vcpu);
3606 return 0;
3607}
3608
3e6e0aab 3609static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3610 struct kvm_segment *var, int seg)
3611{
14af3f3c 3612 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3613}
3614
37817f29
IE		 3615static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3616 struct kvm_segment *kvm_desct)
3617{
3618 kvm_desct->base = seg_desc->base0;
3619 kvm_desct->base |= seg_desc->base1 << 16;
3620 kvm_desct->base |= seg_desc->base2 << 24;
3621 kvm_desct->limit = seg_desc->limit0;
3622 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3623 if (seg_desc->g) {
3624 kvm_desct->limit <<= 12;
3625 kvm_desct->limit |= 0xfff;
3626 }
37817f29
IE		 3627 kvm_desct->selector = selector;
3628 kvm_desct->type = seg_desc->type;
3629 kvm_desct->present = seg_desc->p;
3630 kvm_desct->dpl = seg_desc->dpl;
3631 kvm_desct->db = seg_desc->d;
3632 kvm_desct->s = seg_desc->s;
3633 kvm_desct->l = seg_desc->l;
3634 kvm_desct->g = seg_desc->g;
3635 kvm_desct->avl = seg_desc->avl;
3636 if (!selector)
3637 kvm_desct->unusable = 1;
3638 else
3639 kvm_desct->unusable = 0;
3640 kvm_desct->padding = 0;
3641}
3642
b8222ad2
AS		 3643static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3644 u16 selector,
3645 struct descriptor_table *dtable)
37817f29
IE		 3646{
3647 if (selector & 1 << 2) {
3648 struct kvm_segment kvm_seg;
3649
3e6e0aab 3650 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3651
3652 if (kvm_seg.unusable)
3653 dtable->limit = 0;
3654 else
3655 dtable->limit = kvm_seg.limit;
3656 dtable->base = kvm_seg.base;
3657 }
3658 else
3659 kvm_x86_ops->get_gdt(vcpu, dtable);
3660}
3661
3662/* allowed just for 8 bytes segments */
3663static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3664 struct desc_struct *seg_desc)
3665{
98899aa0 3666 gpa_t gpa;
37817f29
IE		 3667 struct descriptor_table dtable;
3668 u16 index = selector >> 3;
3669
b8222ad2 3670 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3671
3672 if (dtable.limit < index * 8 + 7) {
3673 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3674 return 1;
3675 }
98899aa0
MT		 3676 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3677 gpa += index * 8;
3678 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3679}
3680
3681/* allowed just for 8 bytes segments */
3682static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3683 struct desc_struct *seg_desc)
3684{
98899aa0 3685 gpa_t gpa;
37817f29
IE		 3686 struct descriptor_table dtable;
3687 u16 index = selector >> 3;
3688
b8222ad2 3689 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3690
3691 if (dtable.limit < index * 8 + 7)
3692 return 1;
98899aa0
MT		 3693 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3694 gpa += index * 8;
3695 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3696}
3697
3698static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3699 struct desc_struct *seg_desc)
3700{
3701 u32 base_addr;
3702
3703 base_addr = seg_desc->base0;
3704 base_addr |= (seg_desc->base1 << 16);
3705 base_addr |= (seg_desc->base2 << 24);
3706
98899aa0 3707 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3708}
3709
37817f29
IE		 3710static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3711{
3712 struct kvm_segment kvm_seg;
3713
3e6e0aab 3714 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3715 return kvm_seg.selector;
3716}
3717
3718static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3719 u16 selector,
3720 struct kvm_segment *kvm_seg)
3721{
3722 struct desc_struct seg_desc;
3723
3724 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3725 return 1;
3726 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3727 return 0;
3728}
3729
2259e3a7 3730static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3731{
3732 struct kvm_segment segvar = {
3733 .base = selector << 4,
3734 .limit = 0xffff,
3735 .selector = selector,
3736 .type = 3,
3737 .present = 1,
3738 .dpl = 3,
3739 .db = 0,
3740 .s = 1,
3741 .l = 0,
3742 .g = 0,
3743 .avl = 0,
3744 .unusable = 0,
3745 };
3746 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3747 return 0;
3748}
3749
3e6e0aab
GT		 3750int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3751 int type_bits, int seg)
37817f29
IE		 3752{
3753 struct kvm_segment kvm_seg;
3754
f4bbd9aa
AK		 3755 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3756 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3757 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3758 return 1;
3759 kvm_seg.type |= type_bits;
3760
3761 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3762 seg != VCPU_SREG_LDTR)
3763 if (!kvm_seg.s)
3764 kvm_seg.unusable = 1;
3765
3e6e0aab 3766 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3767 return 0;
3768}
3769
3770static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3771 struct tss_segment_32 *tss)
3772{
3773 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3774 tss->eip = kvm_rip_read(vcpu);
37817f29 3775 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3776 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3777 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3778 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3779 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3780 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3781 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3782 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3783 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3784 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3785 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3786 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3787 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3788 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3789 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3790 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 3791}
3792
3793static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3794 struct tss_segment_32 *tss)
3795{
3796 kvm_set_cr3(vcpu, tss->cr3);
3797
5fdbf976 3798 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3799 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3800
5fdbf976
MT		 3801 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3802 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3803 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3804 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3805 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3806 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3807 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3808 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3809
3e6e0aab 3810 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3811 return 1;
3812
3e6e0aab 3813 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3814 return 1;
3815
3e6e0aab 3816 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3817 return 1;
3818
3e6e0aab 3819 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3820 return 1;
3821
3e6e0aab 3822 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3823 return 1;
3824
3e6e0aab 3825 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3826 return 1;
3827
3e6e0aab 3828 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3829 return 1;
3830 return 0;
3831}
3832
3833static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3834 struct tss_segment_16 *tss)
3835{
5fdbf976 3836 tss->ip = kvm_rip_read(vcpu);
37817f29 3837 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3838 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3839 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3840 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3841 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3842 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3843 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3844 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3845 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3846
3847 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3848 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3849 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3850 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3851 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3852 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3853}
3854
3855static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3856 struct tss_segment_16 *tss)
3857{
5fdbf976 3858 kvm_rip_write(vcpu, tss->ip);
37817f29 3859 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3860 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3861 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3862 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3863 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3864 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3865 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3866 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3867 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3868
3e6e0aab 3869 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3870 return 1;
3871
3e6e0aab 3872 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3873 return 1;
3874
3e6e0aab 3875 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3876 return 1;
3877
3e6e0aab 3878 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3879 return 1;
3880
3e6e0aab 3881 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3882 return 1;
3883 return 0;
3884}
3885
8b2cf73c 3886static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 3887 u16 old_tss_sel, u32 old_tss_base,
3888 struct desc_struct *nseg_desc)
37817f29
IE		 3889{
3890 struct tss_segment_16 tss_segment_16;
3891 int ret = 0;
3892
34198bf8
MT		 3893 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3894 sizeof tss_segment_16))
37817f29
IE		 3895 goto out;
3896
3897 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3898
34198bf8
MT		 3899 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3900 sizeof tss_segment_16))
37817f29 3901 goto out;
34198bf8
MT		 3902
3903 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3904 &tss_segment_16, sizeof tss_segment_16))
3905 goto out;
3906
b237ac37
GN		 3907 if (old_tss_sel != 0xffff) {
3908 tss_segment_16.prev_task_link = old_tss_sel;
3909
3910 if (kvm_write_guest(vcpu->kvm,
3911 get_tss_base_addr(vcpu, nseg_desc),
3912 &tss_segment_16.prev_task_link,
3913 sizeof tss_segment_16.prev_task_link))
3914 goto out;
3915 }
3916
37817f29
IE		 3917 if (load_state_from_tss16(vcpu, &tss_segment_16))
3918 goto out;
3919
3920 ret = 1;
3921out:
3922 return ret;
3923}
3924
8b2cf73c 3925static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 3926 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 3927 struct desc_struct *nseg_desc)
3928{
3929 struct tss_segment_32 tss_segment_32;
3930 int ret = 0;
3931
34198bf8
MT		 3932 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3933 sizeof tss_segment_32))
37817f29
IE		 3934 goto out;
3935
3936 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3937
34198bf8
MT		 3938 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3939 sizeof tss_segment_32))
3940 goto out;
3941
3942 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3943 &tss_segment_32, sizeof tss_segment_32))
37817f29 3944 goto out;
34198bf8 3945
b237ac37
GN		 3946 if (old_tss_sel != 0xffff) {
3947 tss_segment_32.prev_task_link = old_tss_sel;
3948
3949 if (kvm_write_guest(vcpu->kvm,
3950 get_tss_base_addr(vcpu, nseg_desc),
3951 &tss_segment_32.prev_task_link,
3952 sizeof tss_segment_32.prev_task_link))
3953 goto out;
3954 }
3955
37817f29
IE		 3956 if (load_state_from_tss32(vcpu, &tss_segment_32))
3957 goto out;
3958
3959 ret = 1;
3960out:
3961 return ret;
3962}
3963
3964int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3965{
3966 struct kvm_segment tr_seg;
3967 struct desc_struct cseg_desc;
3968 struct desc_struct nseg_desc;
3969 int ret = 0;
34198bf8
MT		 3970 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3971 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3972
34198bf8 3973 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3974
34198bf8
MT		 3975 /* FIXME: Handle errors. Failure to read either TSS or their
3976 * descriptors should generate a pagefault.
3977 */
37817f29
IE		 3978 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3979 goto out;
3980
34198bf8 3981 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3982 goto out;
3983
37817f29
IE		 3984 if (reason != TASK_SWITCH_IRET) {
3985 int cpl;
3986
3987 cpl = kvm_x86_ops->get_cpl(vcpu);
3988 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3989 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3990 return 1;
3991 }
3992 }
3993
3994 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3995 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3996 return 1;
3997 }
3998
3999 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4000 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4001 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4002 }
4003
4004 if (reason == TASK_SWITCH_IRET) {
4005 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4006 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4007 }
4008
64a7ec06
GN		 4009 /* set back link to prev task only if NT bit is set in eflags
4010 note that old_tss_sel is not used afetr this point */
4011 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4012 old_tss_sel = 0xffff;
37817f29 4013
b237ac37
GN		 4014 /* set back link to prev task only if NT bit is set in eflags
4015 note that old_tss_sel is not used afetr this point */
4016 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4017 old_tss_sel = 0xffff;
4018
37817f29 4019 if (nseg_desc.type & 8)
b237ac37
GN		 4020 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4021 old_tss_base, &nseg_desc);
37817f29 4022 else
b237ac37
GN		 4023 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4024 old_tss_base, &nseg_desc);
37817f29
IE		 4025
4026 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4027 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4028 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4029 }
4030
4031 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4032 nseg_desc.type |= (1 << 1);
37817f29
IE		 4033 save_guest_segment_descriptor(vcpu, tss_selector,
4034 &nseg_desc);
4035 }
4036
4037 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4038 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4039 tr_seg.type = 11;
3e6e0aab 4040 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4041out:
37817f29
IE		 4042 return ret;
4043}
4044EXPORT_SYMBOL_GPL(kvm_task_switch);
4045
b6c7a5dc
HB		 4046int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4047 struct kvm_sregs *sregs)
4048{
4049 int mmu_reset_needed = 0;
923c61bb 4050 int pending_vec, max_bits;
b6c7a5dc
HB		 4051 struct descriptor_table dt;
4052
4053 vcpu_load(vcpu);
4054
4055 dt.limit = sregs->idt.limit;
4056 dt.base = sregs->idt.base;
4057 kvm_x86_ops->set_idt(vcpu, &dt);
4058 dt.limit = sregs->gdt.limit;
4059 dt.base = sregs->gdt.base;
4060 kvm_x86_ops->set_gdt(vcpu, &dt);
4061
ad312c7c
ZX		 4062 vcpu->arch.cr2 = sregs->cr2;
4063 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
59839dff
MT		 4064
4065 down_read(&vcpu->kvm->slots_lock);
4066 if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT))
4067 vcpu->arch.cr3 = sregs->cr3;
4068 else
4069 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
4070 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc 4071
2d3ad1f4 4072 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4073
ad312c7c 4074 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4075 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4076 kvm_set_apic_base(vcpu, sregs->apic_base);
4077
4078 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4079
ad312c7c 4080 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4081 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4082 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4083
ad312c7c 4084 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4085 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4086 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4087 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4088
4089 if (mmu_reset_needed)
4090 kvm_mmu_reset_context(vcpu);
4091
923c61bb
GN		 4092 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4093 pending_vec = find_first_bit(
4094 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4095 if (pending_vec < max_bits) {
66fd3f7f 4096 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4097 pr_debug("Set back pending irq %d\n", pending_vec);
4098 if (irqchip_in_kernel(vcpu->kvm))
4099 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4100 }
4101
3e6e0aab
GT		 4102 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4103 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4104 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4105 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4106 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4107 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4108
3e6e0aab
GT		 4109 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4110 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4111
9c3e4aab
MT		 4112 /* Older userspace won't unhalt the vcpu on reset. */
4113 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
4114 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4115 !(vcpu->arch.cr0 & X86_CR0_PE))
4116 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4117
b6c7a5dc
HB		 4118 vcpu_put(vcpu);
4119
4120 return 0;
4121}
4122
d0bfb940
JK		 4123int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4124 struct kvm_guest_debug *dbg)
b6c7a5dc 4125{
ae675ef0 4126 int i, r;
b6c7a5dc
HB		 4127
4128 vcpu_load(vcpu);
4129
ae675ef0
JK		 4130 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4131 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4132 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4133 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4134 vcpu->arch.switch_db_regs =
4135 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4136 } else {
4137 for (i = 0; i < KVM_NR_DB_REGS; i++)
4138 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4139 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4140 }
4141
b6c7a5dc
HB		 4142 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4143
d0bfb940
JK		 4144 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4145 kvm_queue_exception(vcpu, DB_VECTOR);
4146 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4147 kvm_queue_exception(vcpu, BP_VECTOR);
4148
b6c7a5dc
HB		 4149 vcpu_put(vcpu);
4150
4151 return r;
4152}
4153
d0752060
HB		 4154/*
4155 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4156 * we have asm/x86/processor.h
4157 */
4158struct fxsave {
4159 u16 cwd;
4160 u16 swd;
4161 u16 twd;
4162 u16 fop;
4163 u64 rip;
4164 u64 rdp;
4165 u32 mxcsr;
4166 u32 mxcsr_mask;
4167 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4168#ifdef CONFIG_X86_64
4169 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4170#else
4171 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4172#endif
4173};
4174
8b006791
ZX		 4175/*
4176 * Translate a guest virtual address to a guest physical address.
4177 */
4178int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4179 struct kvm_translation *tr)
4180{
4181 unsigned long vaddr = tr->linear_address;
4182 gpa_t gpa;
4183
4184 vcpu_load(vcpu);
72dc67a6 4185 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4186 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4187 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4188 tr->physical_address = gpa;
4189 tr->valid = gpa != UNMAPPED_GVA;
4190 tr->writeable = 1;
4191 tr->usermode = 0;
8b006791
ZX		 4192 vcpu_put(vcpu);
4193
4194 return 0;
4195}
4196
d0752060
HB		 4197int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4198{
ad312c7c 4199 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4200
4201 vcpu_load(vcpu);
4202
4203 memcpy(fpu->fpr, fxsave->st_space, 128);
4204 fpu->fcw = fxsave->cwd;
4205 fpu->fsw = fxsave->swd;
4206 fpu->ftwx = fxsave->twd;
4207 fpu->last_opcode = fxsave->fop;
4208 fpu->last_ip = fxsave->rip;
4209 fpu->last_dp = fxsave->rdp;
4210 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4211
4212 vcpu_put(vcpu);
4213
4214 return 0;
4215}
4216
4217int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4218{
ad312c7c 4219 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4220
4221 vcpu_load(vcpu);
4222
4223 memcpy(fxsave->st_space, fpu->fpr, 128);
4224 fxsave->cwd = fpu->fcw;
4225 fxsave->swd = fpu->fsw;
4226 fxsave->twd = fpu->ftwx;
4227 fxsave->fop = fpu->last_opcode;
4228 fxsave->rip = fpu->last_ip;
4229 fxsave->rdp = fpu->last_dp;
4230 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4231
4232 vcpu_put(vcpu);
4233
4234 return 0;
4235}
4236
4237void fx_init(struct kvm_vcpu *vcpu)
4238{
4239 unsigned after_mxcsr_mask;
4240
bc1a34f1
AA		 4241 /*
4242 * Touch the fpu the first time in non atomic context as if
4243 * this is the first fpu instruction the exception handler
4244 * will fire before the instruction returns and it'll have to
4245 * allocate ram with GFP_KERNEL.
4246 */
4247 if (!used_math())
d6e88aec 4248 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4249
d0752060
HB		 4250 /* Initialize guest FPU by resetting ours and saving into guest's */
4251 preempt_disable();
d6e88aec
AK		 4252 kvm_fx_save(&vcpu->arch.host_fx_image);
4253 kvm_fx_finit();
4254 kvm_fx_save(&vcpu->arch.guest_fx_image);
4255 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4256 preempt_enable();
4257
ad312c7c 4258 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4259 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4260 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4261 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4262 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4263}
4264EXPORT_SYMBOL_GPL(fx_init);
4265
4266void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4267{
4268 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4269 return;
4270
4271 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4272 kvm_fx_save(&vcpu->arch.host_fx_image);
4273 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4274}
4275EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4276
4277void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4278{
4279 if (!vcpu->guest_fpu_loaded)
4280 return;
4281
4282 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4283 kvm_fx_save(&vcpu->arch.guest_fx_image);
4284 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4285 ++vcpu->stat.fpu_reload;
d0752060
HB		 4286}
4287EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4288
4289void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4290{
7f1ea208
JR		 4291 if (vcpu->arch.time_page) {
4292 kvm_release_page_dirty(vcpu->arch.time_page);
4293 vcpu->arch.time_page = NULL;
4294 }
4295
e9b11c17
ZX		 4296 kvm_x86_ops->vcpu_free(vcpu);
4297}
4298
4299struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4300 unsigned int id)
4301{
26e5215f
AK		 4302 return kvm_x86_ops->vcpu_create(kvm, id);
4303}
e9b11c17 4304
26e5215f
AK		 4305int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4306{
4307 int r;
e9b11c17
ZX		 4308
4309 /* We do fxsave: this must be aligned. */
ad312c7c 4310 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4311
0bed3b56 4312 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4313 vcpu_load(vcpu);
4314 r = kvm_arch_vcpu_reset(vcpu);
4315 if (r == 0)
4316 r = kvm_mmu_setup(vcpu);
4317 vcpu_put(vcpu);
4318 if (r < 0)
4319 goto free_vcpu;
4320
26e5215f 4321 return 0;
e9b11c17
ZX		 4322free_vcpu:
4323 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4324 return r;
e9b11c17
ZX		 4325}
4326
d40ccc62 4327void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4328{
4329 vcpu_load(vcpu);
4330 kvm_mmu_unload(vcpu);
4331 vcpu_put(vcpu);
4332
4333 kvm_x86_ops->vcpu_free(vcpu);
4334}
4335
4336int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4337{
448fa4a9
JK		 4338 vcpu->arch.nmi_pending = false;
4339 vcpu->arch.nmi_injected = false;
4340
42dbaa5a
JK		 4341 vcpu->arch.switch_db_regs = 0;
4342 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4343 vcpu->arch.dr6 = DR6_FIXED_1;
4344 vcpu->arch.dr7 = DR7_FIXED_1;
4345
e9b11c17
ZX		 4346 return kvm_x86_ops->vcpu_reset(vcpu);
4347}
4348
4349void kvm_arch_hardware_enable(void *garbage)
4350{
4351 kvm_x86_ops->hardware_enable(garbage);
4352}
4353
4354void kvm_arch_hardware_disable(void *garbage)
4355{
4356 kvm_x86_ops->hardware_disable(garbage);
4357}
4358
4359int kvm_arch_hardware_setup(void)
4360{
4361 return kvm_x86_ops->hardware_setup();
4362}
4363
4364void kvm_arch_hardware_unsetup(void)
4365{
4366 kvm_x86_ops->hardware_unsetup();
4367}
4368
4369void kvm_arch_check_processor_compat(void *rtn)
4370{
4371 kvm_x86_ops->check_processor_compatibility(rtn);
4372}
4373
4374int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4375{
4376 struct page *page;
4377 struct kvm *kvm;
4378 int r;
4379
4380 BUG_ON(vcpu->kvm == NULL);
4381 kvm = vcpu->kvm;
4382
ad312c7c 4383 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4384 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4385 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4386 else
a4535290 4387 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4388
4389 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4390 if (!page) {
4391 r = -ENOMEM;
4392 goto fail;
4393 }
ad312c7c 4394 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4395
4396 r = kvm_mmu_create(vcpu);
4397 if (r < 0)
4398 goto fail_free_pio_data;
4399
4400 if (irqchip_in_kernel(kvm)) {
4401 r = kvm_create_lapic(vcpu);
4402 if (r < 0)
4403 goto fail_mmu_destroy;
4404 }
4405
4406 return 0;
4407
4408fail_mmu_destroy:
4409 kvm_mmu_destroy(vcpu);
4410fail_free_pio_data:
ad312c7c 4411 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4412fail:
4413 return r;
4414}
4415
4416void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4417{
4418 kvm_free_lapic(vcpu);
3200f405 4419 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4420 kvm_mmu_destroy(vcpu);
3200f405 4421 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4422 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4423}
d19a9cd2
ZX		 4424
4425struct kvm *kvm_arch_create_vm(void)
4426{
4427 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4428
4429 if (!kvm)
4430 return ERR_PTR(-ENOMEM);
4431
f05e70ac 4432 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4433 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4434
5550af4d
SY		 4435 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4436 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4437
53f658b3
MT		 4438 rdtscll(kvm->arch.vm_init_tsc);
4439
d19a9cd2
ZX		 4440 return kvm;
4441}
4442
4443static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4444{
4445 vcpu_load(vcpu);
4446 kvm_mmu_unload(vcpu);
4447 vcpu_put(vcpu);
4448}
4449
4450static void kvm_free_vcpus(struct kvm *kvm)
4451{
4452 unsigned int i;
4453
4454 /*
4455 * Unpin any mmu pages first.
4456 */
4457 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4458 if (kvm->vcpus[i])
4459 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4460 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4461 if (kvm->vcpus[i]) {
4462 kvm_arch_vcpu_free(kvm->vcpus[i]);
4463 kvm->vcpus[i] = NULL;
4464 }
4465 }
4466
4467}
4468
ad8ba2cd
SY		 4469void kvm_arch_sync_events(struct kvm *kvm)
4470{
ba4cef31 4471 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4472}
4473
d19a9cd2
ZX		 4474void kvm_arch_destroy_vm(struct kvm *kvm)
4475{
6eb55818 4476 kvm_iommu_unmap_guest(kvm);
7837699f 4477 kvm_free_pit(kvm);
d7deeeb0
ZX		 4478 kfree(kvm->arch.vpic);
4479 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4480 kvm_free_vcpus(kvm);
4481 kvm_free_physmem(kvm);
3d45830c
AK		 4482 if (kvm->arch.apic_access_page)
4483 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4484 if (kvm->arch.ept_identity_pagetable)
4485 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4486 kfree(kvm);
4487}
0de10343
ZX		 4488
4489int kvm_arch_set_memory_region(struct kvm *kvm,
4490 struct kvm_userspace_memory_region *mem,
4491 struct kvm_memory_slot old,
4492 int user_alloc)
4493{
4494 int npages = mem->memory_size >> PAGE_SHIFT;
4495 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4496
4497 /*To keep backward compatibility with older userspace,
4498 *x86 needs to hanlde !user_alloc case.
4499 */
4500 if (!user_alloc) {
4501 if (npages && !old.rmap) {
604b38ac
AA		 4502 unsigned long userspace_addr;
4503
72dc67a6 4504 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4505 userspace_addr = do_mmap(NULL, 0,
4506 npages * PAGE_SIZE,
4507 PROT_READ | PROT_WRITE,
acee3c04 4508 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4509 0);
72dc67a6 4510 up_write(&current->mm->mmap_sem);
0de10343 4511
604b38ac
AA		 4512 if (IS_ERR((void *)userspace_addr))
4513 return PTR_ERR((void *)userspace_addr);
4514
4515 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4516 spin_lock(&kvm->mmu_lock);
4517 memslot->userspace_addr = userspace_addr;
4518 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4519 } else {
4520 if (!old.user_alloc && old.rmap) {
4521 int ret;
4522
72dc67a6 4523 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4524 ret = do_munmap(current->mm, old.userspace_addr,
4525 old.npages * PAGE_SIZE);
72dc67a6 4526 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4527 if (ret < 0)
4528 printk(KERN_WARNING
4529 "kvm_vm_ioctl_set_memory_region: "
4530 "failed to munmap memory\n");
4531 }
4532 }
4533 }
4534
7c8a83b7 4535 spin_lock(&kvm->mmu_lock);
f05e70ac 4536 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4537 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4538 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4539 }
4540
4541 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4542 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4543 kvm_flush_remote_tlbs(kvm);
4544
4545 return 0;
4546}
1d737c8a 4547
34d4cb8f
MT		 4548void kvm_arch_flush_shadow(struct kvm *kvm)
4549{
4550 kvm_mmu_zap_all(kvm);
8986ecc0 4551 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4552}
4553
1d737c8a
ZX		 4554int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4555{
a4535290 4556 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4557 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4558 || vcpu->arch.nmi_pending;
1d737c8a 4559}
5736199a 4560
5736199a
ZX		 4561void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4562{
32f88400
MT		 4563 int me;
4564 int cpu = vcpu->cpu;
5736199a
ZX		 4565
4566 if (waitqueue_active(&vcpu->wq)) {
4567 wake_up_interruptible(&vcpu->wq);
4568 ++vcpu->stat.halt_wakeup;
4569 }
32f88400
MT		 4570
4571 me = get_cpu();
4572 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4573 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4574 smp_send_reschedule(cpu);
e9571ed5 4575 put_cpu();
5736199a 4576}
78646121
GN		 4577
4578int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4579{
4580 return kvm_x86_ops->interrupt_allowed(vcpu);
4581}
Linux 6.x block layer and io_uring tree(s)