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KVM: x86 emulator: trap and propagate #DE from DIV and IDIV
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
043405e1 59
313a3dc7 60#define MAX_IO_MSRS 256
a03490ed
CO		 61#define CR0_RESERVED_BITS \
62 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
63 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
64 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
65#define CR4_RESERVED_BITS \
66 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
67 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
68 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 69 | X86_CR4_OSXSAVE \
a03490ed
CO		 70 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
71
72#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 73
74#define KVM_MAX_MCE_BANKS 32
75#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
76
50a37eb4
JR		 77/* EFER defaults:
78 * - enable syscall per default because its emulated by KVM
79 * - enable LME and LMA per default on 64 bit KVM
80 */
81#ifdef CONFIG_X86_64
82static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
83#else
84static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
85#endif
313a3dc7 86
ba1389b7
AK		 87#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
88#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 89
cb142eb7 90static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 91static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
92 struct kvm_cpuid_entry2 __user *entries);
93
97896d04 94struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 95EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 96
ed85c068
AP		 97int ignore_msrs = 0;
98module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
99
18863bdd
AK		 100#define KVM_NR_SHARED_MSRS 16
101
102struct kvm_shared_msrs_global {
103 int nr;
2bf78fa7 104 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 105};
106
107struct kvm_shared_msrs {
108 struct user_return_notifier urn;
109 bool registered;
2bf78fa7
SY		 110 struct kvm_shared_msr_values {
111 u64 host;
112 u64 curr;
113 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
117static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
118
417bc304 119struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 120 { "pf_fixed", VCPU_STAT(pf_fixed) },
121 { "pf_guest", VCPU_STAT(pf_guest) },
122 { "tlb_flush", VCPU_STAT(tlb_flush) },
123 { "invlpg", VCPU_STAT(invlpg) },
124 { "exits", VCPU_STAT(exits) },
125 { "io_exits", VCPU_STAT(io_exits) },
126 { "mmio_exits", VCPU_STAT(mmio_exits) },
127 { "signal_exits", VCPU_STAT(signal_exits) },
128 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 129 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 130 { "halt_exits", VCPU_STAT(halt_exits) },
131 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 132 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 133 { "request_irq", VCPU_STAT(request_irq_exits) },
134 { "irq_exits", VCPU_STAT(irq_exits) },
135 { "host_state_reload", VCPU_STAT(host_state_reload) },
136 { "efer_reload", VCPU_STAT(efer_reload) },
137 { "fpu_reload", VCPU_STAT(fpu_reload) },
138 { "insn_emulation", VCPU_STAT(insn_emulation) },
139 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 140 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 141 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 142 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
143 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
144 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
145 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
146 { "mmu_flooded", VM_STAT(mmu_flooded) },
147 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 148 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 149 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 150 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 151 { "largepages", VM_STAT(lpages) },
417bc304
HB		 152 { NULL }
153};
154
2acf923e
DC		 155u64 __read_mostly host_xcr0;
156
157static inline u32 bit(int bitno)
158{
159 return 1 << (bitno & 31);
160}
161
18863bdd
AK		 162static void kvm_on_user_return(struct user_return_notifier *urn)
163{
164 unsigned slot;
18863bdd
AK		 165 struct kvm_shared_msrs *locals
166 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 167 struct kvm_shared_msr_values *values;
18863bdd
AK		 168
169 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 170 values = &locals->values[slot];
171 if (values->host != values->curr) {
172 wrmsrl(shared_msrs_global.msrs[slot], values->host);
173 values->curr = values->host;
18863bdd
AK		 174 }
175 }
176 locals->registered = false;
177 user_return_notifier_unregister(urn);
178}
179
2bf78fa7 180static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 181{
2bf78fa7 182 struct kvm_shared_msrs *smsr;
18863bdd
AK		 183 u64 value;
184
2bf78fa7
SY		 185 smsr = &__get_cpu_var(shared_msrs);
186 /* only read, and nobody should modify it at this time,
187 * so don't need lock */
188 if (slot >= shared_msrs_global.nr) {
189 printk(KERN_ERR "kvm: invalid MSR slot!");
190 return;
191 }
192 rdmsrl_safe(msr, &value);
193 smsr->values[slot].host = value;
194 smsr->values[slot].curr = value;
195}
196
197void kvm_define_shared_msr(unsigned slot, u32 msr)
198{
18863bdd
AK		 199 if (slot >= shared_msrs_global.nr)
200 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 201 shared_msrs_global.msrs[slot] = msr;
202 /* we need ensured the shared_msr_global have been updated */
203 smp_wmb();
18863bdd
AK		 204}
205EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
206
207static void kvm_shared_msr_cpu_online(void)
208{
209 unsigned i;
18863bdd
AK		 210
211 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 212 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 213}
214
d5696725 215void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 216{
217 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
218
2bf78fa7 219 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 220 return;
2bf78fa7
SY		 221 smsr->values[slot].curr = value;
222 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 223 if (!smsr->registered) {
224 smsr->urn.on_user_return = kvm_on_user_return;
225 user_return_notifier_register(&smsr->urn);
226 smsr->registered = true;
227 }
228}
229EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
230
3548bab5
AK		 231static void drop_user_return_notifiers(void *ignore)
232{
233 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
234
235 if (smsr->registered)
236 kvm_on_user_return(&smsr->urn);
237}
238
6866b83e
CO		 239u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
240{
241 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 242 return vcpu->arch.apic_base;
6866b83e 243 else
ad312c7c 244 return vcpu->arch.apic_base;
6866b83e
CO		 245}
246EXPORT_SYMBOL_GPL(kvm_get_apic_base);
247
248void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
249{
250 /* TODO: reserve bits check */
251 if (irqchip_in_kernel(vcpu->kvm))
252 kvm_lapic_set_base(vcpu, data);
253 else
ad312c7c 254 vcpu->arch.apic_base = data;
6866b83e
CO		 255}
256EXPORT_SYMBOL_GPL(kvm_set_apic_base);
257
3fd28fce
ED		 258#define EXCPT_BENIGN 0
259#define EXCPT_CONTRIBUTORY 1
260#define EXCPT_PF 2
261
262static int exception_class(int vector)
263{
264 switch (vector) {
265 case PF_VECTOR:
266 return EXCPT_PF;
267 case DE_VECTOR:
268 case TS_VECTOR:
269 case NP_VECTOR:
270 case SS_VECTOR:
271 case GP_VECTOR:
272 return EXCPT_CONTRIBUTORY;
273 default:
274 break;
275 }
276 return EXCPT_BENIGN;
277}
278
279static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 280 unsigned nr, bool has_error, u32 error_code,
281 bool reinject)
3fd28fce
ED		 282{
283 u32 prev_nr;
284 int class1, class2;
285
286 if (!vcpu->arch.exception.pending) {
287 queue:
288 vcpu->arch.exception.pending = true;
289 vcpu->arch.exception.has_error_code = has_error;
290 vcpu->arch.exception.nr = nr;
291 vcpu->arch.exception.error_code = error_code;
3f0fd292 292 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 293 return;
294 }
295
296 /* to check exception */
297 prev_nr = vcpu->arch.exception.nr;
298 if (prev_nr == DF_VECTOR) {
299 /* triple fault -> shutdown */
a8eeb04a 300 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 301 return;
302 }
303 class1 = exception_class(prev_nr);
304 class2 = exception_class(nr);
305 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
306 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
307 /* generate double fault per SDM Table 5-5 */
308 vcpu->arch.exception.pending = true;
309 vcpu->arch.exception.has_error_code = true;
310 vcpu->arch.exception.nr = DF_VECTOR;
311 vcpu->arch.exception.error_code = 0;
312 } else
313 /* replace previous exception with a new one in a hope
314 that instruction re-execution will regenerate lost
315 exception */
316 goto queue;
317}
318
298101da
AK		 319void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
320{
ce7ddec4 321 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 322}
323EXPORT_SYMBOL_GPL(kvm_queue_exception);
324
ce7ddec4
JR		 325void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
327 kvm_multiple_exception(vcpu, nr, false, 0, true);
328}
329EXPORT_SYMBOL_GPL(kvm_requeue_exception);
330
c3c91fee
AK		 331void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
332 u32 error_code)
333{
334 ++vcpu->stat.pf_guest;
ad312c7c 335 vcpu->arch.cr2 = addr;
c3c91fee
AK		 336 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
337}
338
3419ffc8
SY		 339void kvm_inject_nmi(struct kvm_vcpu *vcpu)
340{
341 vcpu->arch.nmi_pending = 1;
342}
343EXPORT_SYMBOL_GPL(kvm_inject_nmi);
344
298101da
AK		 345void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
346{
ce7ddec4 347 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 348}
349EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
350
ce7ddec4
JR		 351void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
352{
353 kvm_multiple_exception(vcpu, nr, true, error_code, true);
354}
355EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
356
0a79b009
AK		 357/*
358 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
359 * a #GP and return false.
360 */
361bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 362{
0a79b009
AK		 363 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
364 return true;
365 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
366 return false;
298101da 367}
0a79b009 368EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 369
a03490ed
CO		 370/*
371 * Load the pae pdptrs. Return true is they are all valid.
372 */
373int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
374{
375 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
376 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
377 int i;
378 int ret;
ad312c7c 379 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 380
a03490ed
CO		 381 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
382 offset * sizeof(u64), sizeof(pdpte));
383 if (ret < 0) {
384 ret = 0;
385 goto out;
386 }
387 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 388 if (is_present_gpte(pdpte[i]) &&
20c466b5 389 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 390 ret = 0;
391 goto out;
392 }
393 }
394 ret = 1;
395
ad312c7c 396 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 397 __set_bit(VCPU_EXREG_PDPTR,
398 (unsigned long *)&vcpu->arch.regs_avail);
399 __set_bit(VCPU_EXREG_PDPTR,
400 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 401out:
a03490ed
CO		 402
403 return ret;
404}
cc4b6871 405EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 406
d835dfec
AK		 407static bool pdptrs_changed(struct kvm_vcpu *vcpu)
408{
ad312c7c 409 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 410 bool changed = true;
411 int r;
412
413 if (is_long_mode(vcpu) || !is_pae(vcpu))
414 return false;
415
6de4f3ad
AK		 416 if (!test_bit(VCPU_EXREG_PDPTR,
417 (unsigned long *)&vcpu->arch.regs_avail))
418 return true;
419
ad312c7c 420 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 421 if (r < 0)
422 goto out;
ad312c7c 423 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 424out:
d835dfec
AK		 425
426 return changed;
427}
428
49a9b07e 429int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 430{
aad82703
SY		 431 unsigned long old_cr0 = kvm_read_cr0(vcpu);
432 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
433 X86_CR0_CD | X86_CR0_NW;
434
f9a48e6a
AK		 435 cr0 |= X86_CR0_ET;
436
ab344828 437#ifdef CONFIG_X86_64
0f12244f
GN		 438 if (cr0 & 0xffffffff00000000UL)
439 return 1;
ab344828
GN		 440#endif
441
442 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 443
0f12244f
GN		 444 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
445 return 1;
a03490ed 446
0f12244f
GN		 447 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
448 return 1;
a03490ed
CO		 449
450 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
451#ifdef CONFIG_X86_64
f6801dff 452 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 453 int cs_db, cs_l;
454
0f12244f
GN		 455 if (!is_pae(vcpu))
456 return 1;
a03490ed 457 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 458 if (cs_l)
459 return 1;
a03490ed
CO		 460 } else
461#endif
0f12244f
GN		 462 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
463 return 1;
a03490ed
CO		 464 }
465
466 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 467
aad82703
SY		 468 if ((cr0 ^ old_cr0) & update_bits)
469 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 470 return 0;
471}
2d3ad1f4 472EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 473
2d3ad1f4 474void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 475{
49a9b07e 476 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 477}
2d3ad1f4 478EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 479
2acf923e
DC		 480int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
481{
482 u64 xcr0;
483
484 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
485 if (index != XCR_XFEATURE_ENABLED_MASK)
486 return 1;
487 xcr0 = xcr;
488 if (kvm_x86_ops->get_cpl(vcpu) != 0)
489 return 1;
490 if (!(xcr0 & XSTATE_FP))
491 return 1;
492 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
493 return 1;
494 if (xcr0 & ~host_xcr0)
495 return 1;
496 vcpu->arch.xcr0 = xcr0;
497 vcpu->guest_xcr0_loaded = 0;
498 return 0;
499}
500
501int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
502{
503 if (__kvm_set_xcr(vcpu, index, xcr)) {
504 kvm_inject_gp(vcpu, 0);
505 return 1;
506 }
507 return 0;
508}
509EXPORT_SYMBOL_GPL(kvm_set_xcr);
510
511static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
512{
513 struct kvm_cpuid_entry2 *best;
514
515 best = kvm_find_cpuid_entry(vcpu, 1, 0);
516 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
517}
518
519static void update_cpuid(struct kvm_vcpu *vcpu)
520{
521 struct kvm_cpuid_entry2 *best;
522
523 best = kvm_find_cpuid_entry(vcpu, 1, 0);
524 if (!best)
525 return;
526
527 /* Update OSXSAVE bit */
528 if (cpu_has_xsave && best->function == 0x1) {
529 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
530 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
531 best->ecx |= bit(X86_FEATURE_OSXSAVE);
532 }
533}
534
a83b29c6 535int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 536{
fc78f519 537 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 538 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
539
0f12244f
GN		 540 if (cr4 & CR4_RESERVED_BITS)
541 return 1;
a03490ed 542
2acf923e
DC		 543 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
544 return 1;
545
a03490ed 546 if (is_long_mode(vcpu)) {
0f12244f
GN		 547 if (!(cr4 & X86_CR4_PAE))
548 return 1;
a2edf57f
AK		 549 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
550 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 551 && !load_pdptrs(vcpu, vcpu->arch.cr3))
552 return 1;
553
554 if (cr4 & X86_CR4_VMXE)
555 return 1;
a03490ed 556
a03490ed 557 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 558
aad82703
SY		 559 if ((cr4 ^ old_cr4) & pdptr_bits)
560 kvm_mmu_reset_context(vcpu);
0f12244f 561
2acf923e
DC		 562 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
563 update_cpuid(vcpu);
564
0f12244f
GN		 565 return 0;
566}
2d3ad1f4 567EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 568
2390218b 569int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 570{
ad312c7c 571 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 572 kvm_mmu_sync_roots(vcpu);
d835dfec 573 kvm_mmu_flush_tlb(vcpu);
0f12244f 574 return 0;
d835dfec
AK		 575 }
576
a03490ed 577 if (is_long_mode(vcpu)) {
0f12244f
GN		 578 if (cr3 & CR3_L_MODE_RESERVED_BITS)
579 return 1;
a03490ed
CO		 580 } else {
581 if (is_pae(vcpu)) {
0f12244f
GN		 582 if (cr3 & CR3_PAE_RESERVED_BITS)
583 return 1;
584 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
585 return 1;
a03490ed
CO		 586 }
587 /*
588 * We don't check reserved bits in nonpae mode, because
589 * this isn't enforced, and VMware depends on this.
590 */
591 }
592
a03490ed
CO		 593 /*
594 * Does the new cr3 value map to physical memory? (Note, we
595 * catch an invalid cr3 even in real-mode, because it would
596 * cause trouble later on when we turn on paging anyway.)
597 *
598 * A real CPU would silently accept an invalid cr3 and would
599 * attempt to use it - with largely undefined (and often hard
600 * to debug) behavior on the guest side.
601 */
602 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 603 return 1;
604 vcpu->arch.cr3 = cr3;
605 vcpu->arch.mmu.new_cr3(vcpu);
606 return 0;
607}
2d3ad1f4 608EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 609
0f12244f 610int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 611{
0f12244f
GN		 612 if (cr8 & CR8_RESERVED_BITS)
613 return 1;
a03490ed
CO		 614 if (irqchip_in_kernel(vcpu->kvm))
615 kvm_lapic_set_tpr(vcpu, cr8);
616 else
ad312c7c 617 vcpu->arch.cr8 = cr8;
0f12244f
GN		 618 return 0;
619}
620
621void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
622{
623 if (__kvm_set_cr8(vcpu, cr8))
624 kvm_inject_gp(vcpu, 0);
a03490ed 625}
2d3ad1f4 626EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 627
2d3ad1f4 628unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 629{
630 if (irqchip_in_kernel(vcpu->kvm))
631 return kvm_lapic_get_cr8(vcpu);
632 else
ad312c7c 633 return vcpu->arch.cr8;
a03490ed 634}
2d3ad1f4 635EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 636
338dbc97 637static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 638{
639 switch (dr) {
640 case 0 ... 3:
641 vcpu->arch.db[dr] = val;
642 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
643 vcpu->arch.eff_db[dr] = val;
644 break;
645 case 4:
338dbc97
GN		 646 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
647 return 1; /* #UD */
020df079
GN		 648 /* fall through */
649 case 6:
338dbc97
GN		 650 if (val & 0xffffffff00000000ULL)
651 return -1; /* #GP */
020df079
GN		 652 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
653 break;
654 case 5:
338dbc97
GN		 655 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
656 return 1; /* #UD */
020df079
GN		 657 /* fall through */
658 default: /* 7 */
338dbc97
GN		 659 if (val & 0xffffffff00000000ULL)
660 return -1; /* #GP */
020df079
GN		 661 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
662 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
663 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
664 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
665 }
666 break;
667 }
668
669 return 0;
670}
338dbc97
GN		 671
672int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
673{
674 int res;
675
676 res = __kvm_set_dr(vcpu, dr, val);
677 if (res > 0)
678 kvm_queue_exception(vcpu, UD_VECTOR);
679 else if (res < 0)
680 kvm_inject_gp(vcpu, 0);
681
682 return res;
683}
020df079
GN		 684EXPORT_SYMBOL_GPL(kvm_set_dr);
685
338dbc97 686static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 687{
688 switch (dr) {
689 case 0 ... 3:
690 *val = vcpu->arch.db[dr];
691 break;
692 case 4:
338dbc97 693 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 694 return 1;
020df079
GN		 695 /* fall through */
696 case 6:
697 *val = vcpu->arch.dr6;
698 break;
699 case 5:
338dbc97 700 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 701 return 1;
020df079
GN		 702 /* fall through */
703 default: /* 7 */
704 *val = vcpu->arch.dr7;
705 break;
706 }
707
708 return 0;
709}
338dbc97
GN		 710
711int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
712{
713 if (_kvm_get_dr(vcpu, dr, val)) {
714 kvm_queue_exception(vcpu, UD_VECTOR);
715 return 1;
716 }
717 return 0;
718}
020df079
GN		 719EXPORT_SYMBOL_GPL(kvm_get_dr);
720
043405e1
CO		 721/*
722 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
723 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
724 *
725 * This list is modified at module load time to reflect the
e3267cbb
GC		 726 * capabilities of the host cpu. This capabilities test skips MSRs that are
727 * kvm-specific. Those are put in the beginning of the list.
043405e1 728 */
e3267cbb 729
11c6bffa 730#define KVM_SAVE_MSRS_BEGIN 7
043405e1 731static u32 msrs_to_save[] = {
e3267cbb 732 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 733 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 734 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 735 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 736 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 737 MSR_STAR,
043405e1
CO		 738#ifdef CONFIG_X86_64
739 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
740#endif
e3267cbb 741 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 742};
743
744static unsigned num_msrs_to_save;
745
746static u32 emulated_msrs[] = {
747 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 748 MSR_IA32_MCG_STATUS,
749 MSR_IA32_MCG_CTL,
043405e1
CO		 750};
751
b69e8cae 752static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 753{
aad82703
SY		 754 u64 old_efer = vcpu->arch.efer;
755
b69e8cae
RJ		 756 if (efer & efer_reserved_bits)
757 return 1;
15c4a640
CO		 758
759 if (is_paging(vcpu)
b69e8cae
RJ		 760 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
761 return 1;
15c4a640 762
1b2fd70c
AG		 763 if (efer & EFER_FFXSR) {
764 struct kvm_cpuid_entry2 *feat;
765
766 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 767 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
768 return 1;
1b2fd70c
AG		 769 }
770
d8017474
AG		 771 if (efer & EFER_SVME) {
772 struct kvm_cpuid_entry2 *feat;
773
774 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 775 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
776 return 1;
d8017474
AG		 777 }
778
15c4a640 779 efer &= ~EFER_LMA;
f6801dff 780 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 781
a3d204e2
SY		 782 kvm_x86_ops->set_efer(vcpu, efer);
783
9645bb56
AK		 784 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
785 kvm_mmu_reset_context(vcpu);
b69e8cae 786
aad82703
SY		 787 /* Update reserved bits */
788 if ((efer ^ old_efer) & EFER_NX)
789 kvm_mmu_reset_context(vcpu);
790
b69e8cae 791 return 0;
15c4a640
CO		 792}
793
f2b4b7dd
JR		 794void kvm_enable_efer_bits(u64 mask)
795{
796 efer_reserved_bits &= ~mask;
797}
798EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
799
800
15c4a640
CO		 801/*
802 * Writes msr value into into the appropriate "register".
803 * Returns 0 on success, non-0 otherwise.
804 * Assumes vcpu_load() was already called.
805 */
806int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
807{
808 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
809}
810
313a3dc7
CO		 811/*
812 * Adapt set_msr() to msr_io()'s calling convention
813 */
814static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
815{
816 return kvm_set_msr(vcpu, index, *data);
817}
818
18068523
GOC		 819static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
820{
9ed3c444
AK		 821 int version;
822 int r;
50d0a0f9 823 struct pvclock_wall_clock wc;
923de3cf 824 struct timespec boot;
18068523
GOC		 825
826 if (!wall_clock)
827 return;
828
9ed3c444
AK		 829 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
830 if (r)
831 return;
832
833 if (version & 1)
834 ++version; /* first time write, random junk */
835
836 ++version;
18068523 837
18068523
GOC		 838 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
839
50d0a0f9
GH		 840 /*
841 * The guest calculates current wall clock time by adding
842 * system time (updated by kvm_write_guest_time below) to the
843 * wall clock specified here. guest system time equals host
844 * system time for us, thus we must fill in host boot time here.
845 */
923de3cf 846 getboottime(&boot);
50d0a0f9
GH		 847
848 wc.sec = boot.tv_sec;
849 wc.nsec = boot.tv_nsec;
850 wc.version = version;
18068523
GOC		 851
852 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
853
854 version++;
855 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 856}
857
50d0a0f9
GH		 858static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
859{
860 uint32_t quotient, remainder;
861
862 /* Don't try to replace with do_div(), this one calculates
863 * "(dividend << 32) / divisor" */
864 __asm__ ( "divl %4"
865 : "=a" (quotient), "=d" (remainder)
866 : "0" (0), "1" (dividend), "r" (divisor) );
867 return quotient;
868}
869
870static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
871{
872 uint64_t nsecs = 1000000000LL;
873 int32_t shift = 0;
874 uint64_t tps64;
875 uint32_t tps32;
876
877 tps64 = tsc_khz * 1000LL;
878 while (tps64 > nsecs*2) {
879 tps64 >>= 1;
880 shift--;
881 }
882
883 tps32 = (uint32_t)tps64;
884 while (tps32 <= (uint32_t)nsecs) {
885 tps32 <<= 1;
886 shift++;
887 }
888
889 hv_clock->tsc_shift = shift;
890 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
891
892 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 893 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 894 hv_clock->tsc_to_system_mul);
895}
896
759379dd
ZA		 897static inline u64 get_kernel_ns(void)
898{
899 struct timespec ts;
900
901 WARN_ON(preemptible());
902 ktime_get_ts(&ts);
903 monotonic_to_bootbased(&ts);
904 return timespec_to_ns(&ts);
905}
906
c8076604
GH		 907static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
908
8cfdc000
ZA		 909static inline int kvm_tsc_changes_freq(void)
910{
911 int cpu = get_cpu();
912 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
913 cpufreq_quick_get(cpu) != 0;
914 put_cpu();
915 return ret;
916}
917
759379dd
ZA		 918static inline u64 nsec_to_cycles(u64 nsec)
919{
920 WARN_ON(preemptible());
921 if (kvm_tsc_changes_freq())
922 printk_once(KERN_WARNING
923 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
924 return (nsec * __get_cpu_var(cpu_tsc_khz)) / USEC_PER_SEC;
925}
926
99e3e30a
ZA		 927void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
928{
929 struct kvm *kvm = vcpu->kvm;
f38e098f 930 u64 offset, ns, elapsed;
99e3e30a 931 unsigned long flags;
46543ba4 932 s64 sdiff;
99e3e30a
ZA		 933
934 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
935 offset = data - native_read_tsc();
759379dd 936 ns = get_kernel_ns();
f38e098f 937 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 938 sdiff = data - kvm->arch.last_tsc_write;
939 if (sdiff < 0)
940 sdiff = -sdiff;
f38e098f
ZA		 941
942 /*
46543ba4 943 * Special case: close write to TSC within 5 seconds of
f38e098f 944 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 945 * The 5 seconds is to accomodate host load / swapping as
946 * well as any reset of TSC during the boot process.
f38e098f
ZA		 947 *
948 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 949 * or make a best guest using elapsed value.
f38e098f 950 */
46543ba4
ZA		 951 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
952 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 953 if (!check_tsc_unstable()) {
954 offset = kvm->arch.last_tsc_offset;
955 pr_debug("kvm: matched tsc offset for %llu\n", data);
956 } else {
759379dd
ZA		 957 u64 delta = nsec_to_cycles(elapsed);
958 offset += delta;
959 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 960 }
961 ns = kvm->arch.last_tsc_nsec;
962 }
963 kvm->arch.last_tsc_nsec = ns;
964 kvm->arch.last_tsc_write = data;
965 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 966 kvm_x86_ops->write_tsc_offset(vcpu, offset);
967 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
968
969 /* Reset of TSC must disable overshoot protection below */
970 vcpu->arch.hv_clock.tsc_timestamp = 0;
971}
972EXPORT_SYMBOL_GPL(kvm_write_tsc);
973
8cfdc000 974static int kvm_write_guest_time(struct kvm_vcpu *v)
18068523 975{
18068523
GOC		 976 unsigned long flags;
977 struct kvm_vcpu_arch *vcpu = &v->arch;
978 void *shared_kaddr;
463656c0 979 unsigned long this_tsc_khz;
1d5f066e
ZA		 980 s64 kernel_ns, max_kernel_ns;
981 u64 tsc_timestamp;
18068523
GOC		 982
983 if ((!vcpu->time_page))
8cfdc000 984 return 0;
50d0a0f9 985
18068523
GOC		 986 /* Keep irq disabled to prevent changes to the clock */
987 local_irq_save(flags);
1d5f066e 988 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 989 kernel_ns = get_kernel_ns();
8cfdc000 990 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523
GOC		 991 local_irq_restore(flags);
992
8cfdc000
ZA		 993 if (unlikely(this_tsc_khz == 0)) {
994 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
995 return 1;
996 }
18068523 997
1d5f066e
ZA		 998 /*
999 * Time as measured by the TSC may go backwards when resetting the base
1000 * tsc_timestamp. The reason for this is that the TSC resolution is
1001 * higher than the resolution of the other clock scales. Thus, many
1002 * possible measurments of the TSC correspond to one measurement of any
1003 * other clock, and so a spread of values is possible. This is not a
1004 * problem for the computation of the nanosecond clock; with TSC rates
1005 * around 1GHZ, there can only be a few cycles which correspond to one
1006 * nanosecond value, and any path through this code will inevitably
1007 * take longer than that. However, with the kernel_ns value itself,
1008 * the precision may be much lower, down to HZ granularity. If the
1009 * first sampling of TSC against kernel_ns ends in the low part of the
1010 * range, and the second in the high end of the range, we can get:
1011 *
1012 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1013 *
1014 * As the sampling errors potentially range in the thousands of cycles,
1015 * it is possible such a time value has already been observed by the
1016 * guest. To protect against this, we must compute the system time as
1017 * observed by the guest and ensure the new system time is greater.
1018 */
1019 max_kernel_ns = 0;
1020 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1021 max_kernel_ns = vcpu->last_guest_tsc -
1022 vcpu->hv_clock.tsc_timestamp;
1023 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1024 vcpu->hv_clock.tsc_to_system_mul,
1025 vcpu->hv_clock.tsc_shift);
1026 max_kernel_ns += vcpu->last_kernel_ns;
1027 }
1028
e48672fa 1029 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
8cfdc000 1030 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
e48672fa 1031 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1032 }
1033
1d5f066e
ZA		 1034 if (max_kernel_ns > kernel_ns)
1035 kernel_ns = max_kernel_ns;
1036
8cfdc000 1037 /* With all the info we got, fill in the values */
1d5f066e 1038 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1039 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1040 vcpu->last_kernel_ns = kernel_ns;
371bcf64
GC		 1041 vcpu->hv_clock.flags = 0;
1042
18068523
GOC		 1043 /*
1044 * The interface expects us to write an even number signaling that the
1045 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1046 * state, we just increase by 2 at the end.
18068523 1047 */
50d0a0f9 1048 vcpu->hv_clock.version += 2;
18068523
GOC		 1049
1050 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1051
1052 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1053 sizeof(vcpu->hv_clock));
18068523
GOC		 1054
1055 kunmap_atomic(shared_kaddr, KM_USER0);
1056
1057 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1058 return 0;
18068523
GOC		 1059}
1060
c8076604
GH		 1061static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1062{
1063 struct kvm_vcpu_arch *vcpu = &v->arch;
1064
1065 if (!vcpu->time_page)
1066 return 0;
a8eeb04a 1067 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 1068 return 1;
1069}
1070
9ba075a6
AK		 1071static bool msr_mtrr_valid(unsigned msr)
1072{
1073 switch (msr) {
1074 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1075 case MSR_MTRRfix64K_00000:
1076 case MSR_MTRRfix16K_80000:
1077 case MSR_MTRRfix16K_A0000:
1078 case MSR_MTRRfix4K_C0000:
1079 case MSR_MTRRfix4K_C8000:
1080 case MSR_MTRRfix4K_D0000:
1081 case MSR_MTRRfix4K_D8000:
1082 case MSR_MTRRfix4K_E0000:
1083 case MSR_MTRRfix4K_E8000:
1084 case MSR_MTRRfix4K_F0000:
1085 case MSR_MTRRfix4K_F8000:
1086 case MSR_MTRRdefType:
1087 case MSR_IA32_CR_PAT:
1088 return true;
1089 case 0x2f8:
1090 return true;
1091 }
1092 return false;
1093}
1094
d6289b93
MT		 1095static bool valid_pat_type(unsigned t)
1096{
1097 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1098}
1099
1100static bool valid_mtrr_type(unsigned t)
1101{
1102 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1103}
1104
1105static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1106{
1107 int i;
1108
1109 if (!msr_mtrr_valid(msr))
1110 return false;
1111
1112 if (msr == MSR_IA32_CR_PAT) {
1113 for (i = 0; i < 8; i++)
1114 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1115 return false;
1116 return true;
1117 } else if (msr == MSR_MTRRdefType) {
1118 if (data & ~0xcff)
1119 return false;
1120 return valid_mtrr_type(data & 0xff);
1121 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1122 for (i = 0; i < 8 ; i++)
1123 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1124 return false;
1125 return true;
1126 }
1127
1128 /* variable MTRRs */
1129 return valid_mtrr_type(data & 0xff);
1130}
1131
9ba075a6
AK		 1132static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1133{
0bed3b56
SY		 1134 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1135
d6289b93 1136 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1137 return 1;
1138
0bed3b56
SY		 1139 if (msr == MSR_MTRRdefType) {
1140 vcpu->arch.mtrr_state.def_type = data;
1141 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1142 } else if (msr == MSR_MTRRfix64K_00000)
1143 p[0] = data;
1144 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1145 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1146 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1147 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1148 else if (msr == MSR_IA32_CR_PAT)
1149 vcpu->arch.pat = data;
1150 else { /* Variable MTRRs */
1151 int idx, is_mtrr_mask;
1152 u64 *pt;
1153
1154 idx = (msr - 0x200) / 2;
1155 is_mtrr_mask = msr - 0x200 - 2 * idx;
1156 if (!is_mtrr_mask)
1157 pt =
1158 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1159 else
1160 pt =
1161 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1162 *pt = data;
1163 }
1164
1165 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1166 return 0;
1167}
15c4a640 1168
890ca9ae 1169static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1170{
890ca9ae
HY		 1171 u64 mcg_cap = vcpu->arch.mcg_cap;
1172 unsigned bank_num = mcg_cap & 0xff;
1173
15c4a640 1174 switch (msr) {
15c4a640 1175 case MSR_IA32_MCG_STATUS:
890ca9ae 1176 vcpu->arch.mcg_status = data;
15c4a640 1177 break;
c7ac679c 1178 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1179 if (!(mcg_cap & MCG_CTL_P))
1180 return 1;
1181 if (data != 0 && data != ~(u64)0)
1182 return -1;
1183 vcpu->arch.mcg_ctl = data;
1184 break;
1185 default:
1186 if (msr >= MSR_IA32_MC0_CTL &&
1187 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1188 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1189 /* only 0 or all 1s can be written to IA32_MCi_CTL
1190 * some Linux kernels though clear bit 10 in bank 4 to
1191 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1192 * this to avoid an uncatched #GP in the guest
1193 */
890ca9ae 1194 if ((offset & 0x3) == 0 &&
114be429 1195 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1196 return -1;
1197 vcpu->arch.mce_banks[offset] = data;
1198 break;
1199 }
1200 return 1;
1201 }
1202 return 0;
1203}
1204
ffde22ac
ES		 1205static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1206{
1207 struct kvm *kvm = vcpu->kvm;
1208 int lm = is_long_mode(vcpu);
1209 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1210 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1211 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1212 : kvm->arch.xen_hvm_config.blob_size_32;
1213 u32 page_num = data & ~PAGE_MASK;
1214 u64 page_addr = data & PAGE_MASK;
1215 u8 *page;
1216 int r;
1217
1218 r = -E2BIG;
1219 if (page_num >= blob_size)
1220 goto out;
1221 r = -ENOMEM;
1222 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1223 if (!page)
1224 goto out;
1225 r = -EFAULT;
1226 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1227 goto out_free;
1228 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1229 goto out_free;
1230 r = 0;
1231out_free:
1232 kfree(page);
1233out:
1234 return r;
1235}
1236
55cd8e5a
GN		 1237static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1238{
1239 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1240}
1241
1242static bool kvm_hv_msr_partition_wide(u32 msr)
1243{
1244 bool r = false;
1245 switch (msr) {
1246 case HV_X64_MSR_GUEST_OS_ID:
1247 case HV_X64_MSR_HYPERCALL:
1248 r = true;
1249 break;
1250 }
1251
1252 return r;
1253}
1254
1255static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1256{
1257 struct kvm *kvm = vcpu->kvm;
1258
1259 switch (msr) {
1260 case HV_X64_MSR_GUEST_OS_ID:
1261 kvm->arch.hv_guest_os_id = data;
1262 /* setting guest os id to zero disables hypercall page */
1263 if (!kvm->arch.hv_guest_os_id)
1264 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1265 break;
1266 case HV_X64_MSR_HYPERCALL: {
1267 u64 gfn;
1268 unsigned long addr;
1269 u8 instructions[4];
1270
1271 /* if guest os id is not set hypercall should remain disabled */
1272 if (!kvm->arch.hv_guest_os_id)
1273 break;
1274 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1275 kvm->arch.hv_hypercall = data;
1276 break;
1277 }
1278 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1279 addr = gfn_to_hva(kvm, gfn);
1280 if (kvm_is_error_hva(addr))
1281 return 1;
1282 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1283 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1284 if (copy_to_user((void __user *)addr, instructions, 4))
1285 return 1;
1286 kvm->arch.hv_hypercall = data;
1287 break;
1288 }
1289 default:
1290 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1291 "data 0x%llx\n", msr, data);
1292 return 1;
1293 }
1294 return 0;
1295}
1296
1297static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1298{
10388a07
GN		 1299 switch (msr) {
1300 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1301 unsigned long addr;
55cd8e5a 1302
10388a07
GN		 1303 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1304 vcpu->arch.hv_vapic = data;
1305 break;
1306 }
1307 addr = gfn_to_hva(vcpu->kvm, data >>
1308 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1309 if (kvm_is_error_hva(addr))
1310 return 1;
1311 if (clear_user((void __user *)addr, PAGE_SIZE))
1312 return 1;
1313 vcpu->arch.hv_vapic = data;
1314 break;
1315 }
1316 case HV_X64_MSR_EOI:
1317 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1318 case HV_X64_MSR_ICR:
1319 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1320 case HV_X64_MSR_TPR:
1321 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1322 default:
1323 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1324 "data 0x%llx\n", msr, data);
1325 return 1;
1326 }
1327
1328 return 0;
55cd8e5a
GN		 1329}
1330
15c4a640
CO		 1331int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1332{
1333 switch (msr) {
15c4a640 1334 case MSR_EFER:
b69e8cae 1335 return set_efer(vcpu, data);
8f1589d9
AP		 1336 case MSR_K7_HWCR:
1337 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1338 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1339 if (data != 0) {
1340 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1341 data);
1342 return 1;
1343 }
15c4a640 1344 break;
f7c6d140
AP		 1345 case MSR_FAM10H_MMIO_CONF_BASE:
1346 if (data != 0) {
1347 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1348 "0x%llx\n", data);
1349 return 1;
1350 }
15c4a640 1351 break;
c323c0e5 1352 case MSR_AMD64_NB_CFG:
c7ac679c 1353 break;
b5e2fec0
AG		 1354 case MSR_IA32_DEBUGCTLMSR:
1355 if (!data) {
1356 /* We support the non-activated case already */
1357 break;
1358 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1359 /* Values other than LBR and BTF are vendor-specific,
1360 thus reserved and should throw a #GP */
1361 return 1;
1362 }
1363 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1364 __func__, data);
1365 break;
15c4a640
CO		 1366 case MSR_IA32_UCODE_REV:
1367 case MSR_IA32_UCODE_WRITE:
61a6bd67 1368 case MSR_VM_HSAVE_PA:
6098ca93 1369 case MSR_AMD64_PATCH_LOADER:
15c4a640 1370 break;
9ba075a6
AK		 1371 case 0x200 ... 0x2ff:
1372 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1373 case MSR_IA32_APICBASE:
1374 kvm_set_apic_base(vcpu, data);
1375 break;
0105d1a5
GN		 1376 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1377 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1378 case MSR_IA32_MISC_ENABLE:
ad312c7c 1379 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1380 break;
11c6bffa 1381 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1382 case MSR_KVM_WALL_CLOCK:
1383 vcpu->kvm->arch.wall_clock = data;
1384 kvm_write_wall_clock(vcpu->kvm, data);
1385 break;
11c6bffa 1386 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1387 case MSR_KVM_SYSTEM_TIME: {
1388 if (vcpu->arch.time_page) {
1389 kvm_release_page_dirty(vcpu->arch.time_page);
1390 vcpu->arch.time_page = NULL;
1391 }
1392
1393 vcpu->arch.time = data;
1394
1395 /* we verify if the enable bit is set... */
1396 if (!(data & 1))
1397 break;
1398
1399 /* ...but clean it before doing the actual write */
1400 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1401
18068523
GOC		 1402 vcpu->arch.time_page =
1403 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1404
1405 if (is_error_page(vcpu->arch.time_page)) {
1406 kvm_release_page_clean(vcpu->arch.time_page);
1407 vcpu->arch.time_page = NULL;
1408 }
1409
c8076604 1410 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1411 break;
1412 }
890ca9ae
HY		 1413 case MSR_IA32_MCG_CTL:
1414 case MSR_IA32_MCG_STATUS:
1415 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1416 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1417
1418 /* Performance counters are not protected by a CPUID bit,
1419 * so we should check all of them in the generic path for the sake of
1420 * cross vendor migration.
1421 * Writing a zero into the event select MSRs disables them,
1422 * which we perfectly emulate ;-). Any other value should be at least
1423 * reported, some guests depend on them.
1424 */
1425 case MSR_P6_EVNTSEL0:
1426 case MSR_P6_EVNTSEL1:
1427 case MSR_K7_EVNTSEL0:
1428 case MSR_K7_EVNTSEL1:
1429 case MSR_K7_EVNTSEL2:
1430 case MSR_K7_EVNTSEL3:
1431 if (data != 0)
1432 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1433 "0x%x data 0x%llx\n", msr, data);
1434 break;
1435 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1436 * so we ignore writes to make it happy.
1437 */
1438 case MSR_P6_PERFCTR0:
1439 case MSR_P6_PERFCTR1:
1440 case MSR_K7_PERFCTR0:
1441 case MSR_K7_PERFCTR1:
1442 case MSR_K7_PERFCTR2:
1443 case MSR_K7_PERFCTR3:
1444 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1445 "0x%x data 0x%llx\n", msr, data);
1446 break;
55cd8e5a
GN		 1447 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1448 if (kvm_hv_msr_partition_wide(msr)) {
1449 int r;
1450 mutex_lock(&vcpu->kvm->lock);
1451 r = set_msr_hyperv_pw(vcpu, msr, data);
1452 mutex_unlock(&vcpu->kvm->lock);
1453 return r;
1454 } else
1455 return set_msr_hyperv(vcpu, msr, data);
1456 break;
15c4a640 1457 default:
ffde22ac
ES		 1458 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1459 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1460 if (!ignore_msrs) {
1461 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1462 msr, data);
1463 return 1;
1464 } else {
1465 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1466 msr, data);
1467 break;
1468 }
15c4a640
CO		 1469 }
1470 return 0;
1471}
1472EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1473
1474
1475/*
1476 * Reads an msr value (of 'msr_index') into 'pdata'.
1477 * Returns 0 on success, non-0 otherwise.
1478 * Assumes vcpu_load() was already called.
1479 */
1480int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1481{
1482 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1483}
1484
9ba075a6
AK		 1485static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1486{
0bed3b56
SY		 1487 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1488
9ba075a6
AK		 1489 if (!msr_mtrr_valid(msr))
1490 return 1;
1491
0bed3b56
SY		 1492 if (msr == MSR_MTRRdefType)
1493 *pdata = vcpu->arch.mtrr_state.def_type +
1494 (vcpu->arch.mtrr_state.enabled << 10);
1495 else if (msr == MSR_MTRRfix64K_00000)
1496 *pdata = p[0];
1497 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1498 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1499 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1500 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1501 else if (msr == MSR_IA32_CR_PAT)
1502 *pdata = vcpu->arch.pat;
1503 else { /* Variable MTRRs */
1504 int idx, is_mtrr_mask;
1505 u64 *pt;
1506
1507 idx = (msr - 0x200) / 2;
1508 is_mtrr_mask = msr - 0x200 - 2 * idx;
1509 if (!is_mtrr_mask)
1510 pt =
1511 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1512 else
1513 pt =
1514 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1515 *pdata = *pt;
1516 }
1517
9ba075a6
AK		 1518 return 0;
1519}
1520
890ca9ae 1521static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1522{
1523 u64 data;
890ca9ae
HY		 1524 u64 mcg_cap = vcpu->arch.mcg_cap;
1525 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1526
1527 switch (msr) {
15c4a640
CO		 1528 case MSR_IA32_P5_MC_ADDR:
1529 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1530 data = 0;
1531 break;
15c4a640 1532 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1533 data = vcpu->arch.mcg_cap;
1534 break;
c7ac679c 1535 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1536 if (!(mcg_cap & MCG_CTL_P))
1537 return 1;
1538 data = vcpu->arch.mcg_ctl;
1539 break;
1540 case MSR_IA32_MCG_STATUS:
1541 data = vcpu->arch.mcg_status;
1542 break;
1543 default:
1544 if (msr >= MSR_IA32_MC0_CTL &&
1545 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1546 u32 offset = msr - MSR_IA32_MC0_CTL;
1547 data = vcpu->arch.mce_banks[offset];
1548 break;
1549 }
1550 return 1;
1551 }
1552 *pdata = data;
1553 return 0;
1554}
1555
55cd8e5a
GN		 1556static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1557{
1558 u64 data = 0;
1559 struct kvm *kvm = vcpu->kvm;
1560
1561 switch (msr) {
1562 case HV_X64_MSR_GUEST_OS_ID:
1563 data = kvm->arch.hv_guest_os_id;
1564 break;
1565 case HV_X64_MSR_HYPERCALL:
1566 data = kvm->arch.hv_hypercall;
1567 break;
1568 default:
1569 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1570 return 1;
1571 }
1572
1573 *pdata = data;
1574 return 0;
1575}
1576
1577static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1578{
1579 u64 data = 0;
1580
1581 switch (msr) {
1582 case HV_X64_MSR_VP_INDEX: {
1583 int r;
1584 struct kvm_vcpu *v;
1585 kvm_for_each_vcpu(r, v, vcpu->kvm)
1586 if (v == vcpu)
1587 data = r;
1588 break;
1589 }
10388a07
GN		 1590 case HV_X64_MSR_EOI:
1591 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1592 case HV_X64_MSR_ICR:
1593 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1594 case HV_X64_MSR_TPR:
1595 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1596 default:
1597 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1598 return 1;
1599 }
1600 *pdata = data;
1601 return 0;
1602}
1603
890ca9ae
HY		 1604int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1605{
1606 u64 data;
1607
1608 switch (msr) {
890ca9ae 1609 case MSR_IA32_PLATFORM_ID:
15c4a640 1610 case MSR_IA32_UCODE_REV:
15c4a640 1611 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1612 case MSR_IA32_DEBUGCTLMSR:
1613 case MSR_IA32_LASTBRANCHFROMIP:
1614 case MSR_IA32_LASTBRANCHTOIP:
1615 case MSR_IA32_LASTINTFROMIP:
1616 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1617 case MSR_K8_SYSCFG:
1618 case MSR_K7_HWCR:
61a6bd67 1619 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1620 case MSR_P6_PERFCTR0:
1621 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1622 case MSR_P6_EVNTSEL0:
1623 case MSR_P6_EVNTSEL1:
9e699624 1624 case MSR_K7_EVNTSEL0:
1f3ee616 1625 case MSR_K7_PERFCTR0:
1fdbd48c 1626 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1627 case MSR_AMD64_NB_CFG:
f7c6d140 1628 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1629 data = 0;
1630 break;
9ba075a6
AK		 1631 case MSR_MTRRcap:
1632 data = 0x500 | KVM_NR_VAR_MTRR;
1633 break;
1634 case 0x200 ... 0x2ff:
1635 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1636 case 0xcd: /* fsb frequency */
1637 data = 3;
1638 break;
1639 case MSR_IA32_APICBASE:
1640 data = kvm_get_apic_base(vcpu);
1641 break;
0105d1a5
GN		 1642 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1643 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1644 break;
15c4a640 1645 case MSR_IA32_MISC_ENABLE:
ad312c7c 1646 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1647 break;
847f0ad8
AG		 1648 case MSR_IA32_PERF_STATUS:
1649 /* TSC increment by tick */
1650 data = 1000ULL;
1651 /* CPU multiplier */
1652 data |= (((uint64_t)4ULL) << 40);
1653 break;
15c4a640 1654 case MSR_EFER:
f6801dff 1655 data = vcpu->arch.efer;
15c4a640 1656 break;
18068523 1657 case MSR_KVM_WALL_CLOCK:
11c6bffa 1658 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1659 data = vcpu->kvm->arch.wall_clock;
1660 break;
1661 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1662 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1663 data = vcpu->arch.time;
1664 break;
890ca9ae
HY		 1665 case MSR_IA32_P5_MC_ADDR:
1666 case MSR_IA32_P5_MC_TYPE:
1667 case MSR_IA32_MCG_CAP:
1668 case MSR_IA32_MCG_CTL:
1669 case MSR_IA32_MCG_STATUS:
1670 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1671 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1672 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1673 if (kvm_hv_msr_partition_wide(msr)) {
1674 int r;
1675 mutex_lock(&vcpu->kvm->lock);
1676 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1677 mutex_unlock(&vcpu->kvm->lock);
1678 return r;
1679 } else
1680 return get_msr_hyperv(vcpu, msr, pdata);
1681 break;
15c4a640 1682 default:
ed85c068
AP		 1683 if (!ignore_msrs) {
1684 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1685 return 1;
1686 } else {
1687 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1688 data = 0;
1689 }
1690 break;
15c4a640
CO		 1691 }
1692 *pdata = data;
1693 return 0;
1694}
1695EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1696
313a3dc7
CO		 1697/*
1698 * Read or write a bunch of msrs. All parameters are kernel addresses.
1699 *
1700 * @return number of msrs set successfully.
1701 */
1702static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1703 struct kvm_msr_entry *entries,
1704 int (*do_msr)(struct kvm_vcpu *vcpu,
1705 unsigned index, u64 *data))
1706{
f656ce01 1707 int i, idx;
313a3dc7 1708
f656ce01 1709 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1710 for (i = 0; i < msrs->nmsrs; ++i)
1711 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1712 break;
f656ce01 1713 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1714
313a3dc7
CO		 1715 return i;
1716}
1717
1718/*
1719 * Read or write a bunch of msrs. Parameters are user addresses.
1720 *
1721 * @return number of msrs set successfully.
1722 */
1723static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1724 int (*do_msr)(struct kvm_vcpu *vcpu,
1725 unsigned index, u64 *data),
1726 int writeback)
1727{
1728 struct kvm_msrs msrs;
1729 struct kvm_msr_entry *entries;
1730 int r, n;
1731 unsigned size;
1732
1733 r = -EFAULT;
1734 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1735 goto out;
1736
1737 r = -E2BIG;
1738 if (msrs.nmsrs >= MAX_IO_MSRS)
1739 goto out;
1740
1741 r = -ENOMEM;
1742 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1743 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1744 if (!entries)
1745 goto out;
1746
1747 r = -EFAULT;
1748 if (copy_from_user(entries, user_msrs->entries, size))
1749 goto out_free;
1750
1751 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1752 if (r < 0)
1753 goto out_free;
1754
1755 r = -EFAULT;
1756 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1757 goto out_free;
1758
1759 r = n;
1760
1761out_free:
7a73c028 1762 kfree(entries);
313a3dc7
CO		 1763out:
1764 return r;
1765}
1766
018d00d2
ZX		 1767int kvm_dev_ioctl_check_extension(long ext)
1768{
1769 int r;
1770
1771 switch (ext) {
1772 case KVM_CAP_IRQCHIP:
1773 case KVM_CAP_HLT:
1774 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1775 case KVM_CAP_SET_TSS_ADDR:
07716717 1776 case KVM_CAP_EXT_CPUID:
c8076604 1777 case KVM_CAP_CLOCKSOURCE:
7837699f 1778 case KVM_CAP_PIT:
a28e4f5a 1779 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1780 case KVM_CAP_MP_STATE:
ed848624 1781 case KVM_CAP_SYNC_MMU:
52d939a0 1782 case KVM_CAP_REINJECT_CONTROL:
4925663a 1783 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1784 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1785 case KVM_CAP_IRQFD:
d34e6b17 1786 case KVM_CAP_IOEVENTFD:
c5ff41ce 1787 case KVM_CAP_PIT2:
e9f42757 1788 case KVM_CAP_PIT_STATE2:
b927a3ce 1789 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1790 case KVM_CAP_XEN_HVM:
afbcf7ab 1791 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1792 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1793 case KVM_CAP_HYPERV:
10388a07 1794 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1795 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1796 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1797 case KVM_CAP_DEBUGREGS:
d2be1651 1798 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1799 case KVM_CAP_XSAVE:
018d00d2
ZX		 1800 r = 1;
1801 break;
542472b5
LV		 1802 case KVM_CAP_COALESCED_MMIO:
1803 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1804 break;
774ead3a
AK		 1805 case KVM_CAP_VAPIC:
1806 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1807 break;
f725230a
AK		 1808 case KVM_CAP_NR_VCPUS:
1809 r = KVM_MAX_VCPUS;
1810 break;
a988b910
AK		 1811 case KVM_CAP_NR_MEMSLOTS:
1812 r = KVM_MEMORY_SLOTS;
1813 break;
a68a6a72
MT		 1814 case KVM_CAP_PV_MMU: /* obsolete */
1815 r = 0;
2f333bcb 1816 break;
62c476c7 1817 case KVM_CAP_IOMMU:
19de40a8 1818 r = iommu_found();
62c476c7 1819 break;
890ca9ae
HY		 1820 case KVM_CAP_MCE:
1821 r = KVM_MAX_MCE_BANKS;
1822 break;
2d5b5a66
SY		 1823 case KVM_CAP_XCRS:
1824 r = cpu_has_xsave;
1825 break;
018d00d2
ZX		 1826 default:
1827 r = 0;
1828 break;
1829 }
1830 return r;
1831
1832}
1833
043405e1
CO		 1834long kvm_arch_dev_ioctl(struct file *filp,
1835 unsigned int ioctl, unsigned long arg)
1836{
1837 void __user *argp = (void __user *)arg;
1838 long r;
1839
1840 switch (ioctl) {
1841 case KVM_GET_MSR_INDEX_LIST: {
1842 struct kvm_msr_list __user *user_msr_list = argp;
1843 struct kvm_msr_list msr_list;
1844 unsigned n;
1845
1846 r = -EFAULT;
1847 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1848 goto out;
1849 n = msr_list.nmsrs;
1850 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1851 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1852 goto out;
1853 r = -E2BIG;
e125e7b6 1854 if (n < msr_list.nmsrs)
043405e1
CO		 1855 goto out;
1856 r = -EFAULT;
1857 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1858 num_msrs_to_save * sizeof(u32)))
1859 goto out;
e125e7b6 1860 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1861 &emulated_msrs,
1862 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1863 goto out;
1864 r = 0;
1865 break;
1866 }
674eea0f
AK		 1867 case KVM_GET_SUPPORTED_CPUID: {
1868 struct kvm_cpuid2 __user *cpuid_arg = argp;
1869 struct kvm_cpuid2 cpuid;
1870
1871 r = -EFAULT;
1872 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1873 goto out;
1874 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1875 cpuid_arg->entries);
674eea0f
AK		 1876 if (r)
1877 goto out;
1878
1879 r = -EFAULT;
1880 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1881 goto out;
1882 r = 0;
1883 break;
1884 }
890ca9ae
HY		 1885 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1886 u64 mce_cap;
1887
1888 mce_cap = KVM_MCE_CAP_SUPPORTED;
1889 r = -EFAULT;
1890 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1891 goto out;
1892 r = 0;
1893 break;
1894 }
043405e1
CO		 1895 default:
1896 r = -EINVAL;
1897 }
1898out:
1899 return r;
1900}
1901
f5f48ee1
SY		 1902static void wbinvd_ipi(void *garbage)
1903{
1904 wbinvd();
1905}
1906
1907static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
1908{
1909 return vcpu->kvm->arch.iommu_domain &&
1910 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
1911}
1912
313a3dc7
CO		 1913void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1914{
f5f48ee1
SY		 1915 /* Address WBINVD may be executed by guest */
1916 if (need_emulate_wbinvd(vcpu)) {
1917 if (kvm_x86_ops->has_wbinvd_exit())
1918 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
1919 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
1920 smp_call_function_single(vcpu->cpu,
1921 wbinvd_ipi, NULL, 1);
1922 }
1923
313a3dc7 1924 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 1925 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 1926 /* Make sure TSC doesn't go backwards */
1927 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
1928 native_read_tsc() - vcpu->arch.last_host_tsc;
1929 if (tsc_delta < 0)
1930 mark_tsc_unstable("KVM discovered backwards TSC");
1931 if (check_tsc_unstable())
1932 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
1933 kvm_migrate_timers(vcpu);
1934 vcpu->cpu = cpu;
1935 }
313a3dc7
CO		 1936}
1937
1938void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1939{
02daab21 1940 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1941 kvm_put_guest_fpu(vcpu);
e48672fa 1942 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 1943}
1944
07716717 1945static int is_efer_nx(void)
313a3dc7 1946{
e286e86e 1947 unsigned long long efer = 0;
313a3dc7 1948
e286e86e 1949 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1950 return efer & EFER_NX;
1951}
1952
1953static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1954{
1955 int i;
1956 struct kvm_cpuid_entry2 *e, *entry;
1957
313a3dc7 1958 entry = NULL;
ad312c7c
ZX		 1959 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1960 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1961 if (e->function == 0x80000001) {
1962 entry = e;
1963 break;
1964 }
1965 }
07716717 1966 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1967 entry->edx &= ~(1 << 20);
1968 printk(KERN_INFO "kvm: guest NX capability removed\n");
1969 }
1970}
1971
07716717 1972/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1973static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1974 struct kvm_cpuid *cpuid,
1975 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1976{
1977 int r, i;
1978 struct kvm_cpuid_entry *cpuid_entries;
1979
1980 r = -E2BIG;
1981 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1982 goto out;
1983 r = -ENOMEM;
1984 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1985 if (!cpuid_entries)
1986 goto out;
1987 r = -EFAULT;
1988 if (copy_from_user(cpuid_entries, entries,
1989 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1990 goto out_free;
1991 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1992 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1993 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1994 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1995 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1996 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1997 vcpu->arch.cpuid_entries[i].index = 0;
1998 vcpu->arch.cpuid_entries[i].flags = 0;
1999 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2000 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2001 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2002 }
2003 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2004 cpuid_fix_nx_cap(vcpu);
2005 r = 0;
fc61b800 2006 kvm_apic_set_version(vcpu);
0e851880 2007 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2008 update_cpuid(vcpu);
07716717
DK		 2009
2010out_free:
2011 vfree(cpuid_entries);
2012out:
2013 return r;
2014}
2015
2016static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2017 struct kvm_cpuid2 *cpuid,
2018 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2019{
2020 int r;
2021
2022 r = -E2BIG;
2023 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2024 goto out;
2025 r = -EFAULT;
ad312c7c 2026 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2027 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2028 goto out;
ad312c7c 2029 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2030 kvm_apic_set_version(vcpu);
0e851880 2031 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2032 update_cpuid(vcpu);
313a3dc7
CO		 2033 return 0;
2034
2035out:
2036 return r;
2037}
2038
07716717 2039static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2040 struct kvm_cpuid2 *cpuid,
2041 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2042{
2043 int r;
2044
2045 r = -E2BIG;
ad312c7c 2046 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2047 goto out;
2048 r = -EFAULT;
ad312c7c 2049 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2050 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2051 goto out;
2052 return 0;
2053
2054out:
ad312c7c 2055 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2056 return r;
2057}
2058
07716717 2059static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2060 u32 index)
07716717
DK		 2061{
2062 entry->function = function;
2063 entry->index = index;
2064 cpuid_count(entry->function, entry->index,
19355475 2065 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2066 entry->flags = 0;
2067}
2068
7faa4ee1
AK		 2069#define F(x) bit(X86_FEATURE_##x)
2070
07716717
DK		 2071static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2072 u32 index, int *nent, int maxnent)
2073{
7faa4ee1 2074 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2075#ifdef CONFIG_X86_64
17cc3935
SY		 2076 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2077 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2078 unsigned f_lm = F(LM);
2079#else
17cc3935 2080 unsigned f_gbpages = 0;
7faa4ee1 2081 unsigned f_lm = 0;
07716717 2082#endif
4e47c7a6 2083 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2084
2085 /* cpuid 1.edx */
2086 const u32 kvm_supported_word0_x86_features =
2087 F(FPU) | F(VME) | F(DE) | F(PSE) |
2088 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2089 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2090 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2091 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2092 0 /* Reserved, DS, ACPI */ | F(MMX) |
2093 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2094 0 /* HTT, TM, Reserved, PBE */;
2095 /* cpuid 0x80000001.edx */
2096 const u32 kvm_supported_word1_x86_features =
2097 F(FPU) | F(VME) | F(DE) | F(PSE) |
2098 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2099 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2100 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2101 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2102 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2103 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2104 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2105 /* cpuid 1.ecx */
2106 const u32 kvm_supported_word4_x86_features =
6c3f6041 2107 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2108 0 /* DS-CPL, VMX, SMX, EST */ |
2109 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2110 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2111 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2112 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 2113 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 2114 /* cpuid 0x80000001.ecx */
07716717 2115 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 2116 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
2117 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2118 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2119 0 /* SKINIT */ | 0 /* WDT */;
07716717 2120
19355475 2121 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2122 get_cpu();
2123 do_cpuid_1_ent(entry, function, index);
2124 ++*nent;
2125
2126 switch (function) {
2127 case 0:
2acf923e 2128 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2129 break;
2130 case 1:
2131 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2132 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2133 /* we support x2apic emulation even if host does not support
2134 * it since we emulate x2apic in software */
2135 entry->ecx |= F(X2APIC);
07716717
DK		 2136 break;
2137 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2138 * may return different values. This forces us to get_cpu() before
2139 * issuing the first command, and also to emulate this annoying behavior
2140 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2141 case 2: {
2142 int t, times = entry->eax & 0xff;
2143
2144 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2145 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2146 for (t = 1; t < times && *nent < maxnent; ++t) {
2147 do_cpuid_1_ent(&entry[t], function, 0);
2148 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2149 ++*nent;
2150 }
2151 break;
2152 }
2153 /* function 4 and 0xb have additional index. */
2154 case 4: {
14af3f3c 2155 int i, cache_type;
07716717
DK		 2156
2157 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2158 /* read more entries until cache_type is zero */
14af3f3c
HH		 2159 for (i = 1; *nent < maxnent; ++i) {
2160 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2161 if (!cache_type)
2162 break;
14af3f3c
HH		 2163 do_cpuid_1_ent(&entry[i], function, i);
2164 entry[i].flags |=
07716717
DK		 2165 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2166 ++*nent;
2167 }
2168 break;
2169 }
2170 case 0xb: {
14af3f3c 2171 int i, level_type;
07716717
DK		 2172
2173 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2174 /* read more entries until level_type is zero */
14af3f3c 2175 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2176 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2177 if (!level_type)
2178 break;
14af3f3c
HH		 2179 do_cpuid_1_ent(&entry[i], function, i);
2180 entry[i].flags |=
07716717
DK		 2181 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2182 ++*nent;
2183 }
2184 break;
2185 }
2acf923e
DC		 2186 case 0xd: {
2187 int i;
2188
2189 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2190 for (i = 1; *nent < maxnent; ++i) {
2191 if (entry[i - 1].eax == 0 && i != 2)
2192 break;
2193 do_cpuid_1_ent(&entry[i], function, i);
2194 entry[i].flags |=
2195 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2196 ++*nent;
2197 }
2198 break;
2199 }
84478c82
GC		 2200 case KVM_CPUID_SIGNATURE: {
2201 char signature[12] = "KVMKVMKVM\0\0";
2202 u32 *sigptr = (u32 *)signature;
2203 entry->eax = 0;
2204 entry->ebx = sigptr[0];
2205 entry->ecx = sigptr[1];
2206 entry->edx = sigptr[2];
2207 break;
2208 }
2209 case KVM_CPUID_FEATURES:
2210 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2211 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2212 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2213 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2214 entry->ebx = 0;
2215 entry->ecx = 0;
2216 entry->edx = 0;
2217 break;
07716717
DK		 2218 case 0x80000000:
2219 entry->eax = min(entry->eax, 0x8000001a);
2220 break;
2221 case 0x80000001:
2222 entry->edx &= kvm_supported_word1_x86_features;
2223 entry->ecx &= kvm_supported_word6_x86_features;
2224 break;
2225 }
d4330ef2
JR		 2226
2227 kvm_x86_ops->set_supported_cpuid(function, entry);
2228
07716717
DK		 2229 put_cpu();
2230}
2231
7faa4ee1
AK		 2232#undef F
2233
674eea0f 2234static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2235 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2236{
2237 struct kvm_cpuid_entry2 *cpuid_entries;
2238 int limit, nent = 0, r = -E2BIG;
2239 u32 func;
2240
2241 if (cpuid->nent < 1)
2242 goto out;
6a544355
AK		 2243 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2244 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2245 r = -ENOMEM;
2246 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2247 if (!cpuid_entries)
2248 goto out;
2249
2250 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2251 limit = cpuid_entries[0].eax;
2252 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2253 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2254 &nent, cpuid->nent);
07716717
DK		 2255 r = -E2BIG;
2256 if (nent >= cpuid->nent)
2257 goto out_free;
2258
2259 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2260 limit = cpuid_entries[nent - 1].eax;
2261 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2262 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2263 &nent, cpuid->nent);
84478c82
GC		 2264
2265
2266
2267 r = -E2BIG;
2268 if (nent >= cpuid->nent)
2269 goto out_free;
2270
2271 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2272 cpuid->nent);
2273
2274 r = -E2BIG;
2275 if (nent >= cpuid->nent)
2276 goto out_free;
2277
2278 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2279 cpuid->nent);
2280
cb007648
MM		 2281 r = -E2BIG;
2282 if (nent >= cpuid->nent)
2283 goto out_free;
2284
07716717
DK		 2285 r = -EFAULT;
2286 if (copy_to_user(entries, cpuid_entries,
19355475 2287 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2288 goto out_free;
2289 cpuid->nent = nent;
2290 r = 0;
2291
2292out_free:
2293 vfree(cpuid_entries);
2294out:
2295 return r;
2296}
2297
313a3dc7
CO		 2298static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2299 struct kvm_lapic_state *s)
2300{
ad312c7c 2301 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2302
2303 return 0;
2304}
2305
2306static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2307 struct kvm_lapic_state *s)
2308{
ad312c7c 2309 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2310 kvm_apic_post_state_restore(vcpu);
cb142eb7 2311 update_cr8_intercept(vcpu);
313a3dc7
CO		 2312
2313 return 0;
2314}
2315
f77bc6a4
ZX		 2316static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2317 struct kvm_interrupt *irq)
2318{
2319 if (irq->irq < 0 || irq->irq >= 256)
2320 return -EINVAL;
2321 if (irqchip_in_kernel(vcpu->kvm))
2322 return -ENXIO;
f77bc6a4 2323
66fd3f7f 2324 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2325
f77bc6a4
ZX		 2326 return 0;
2327}
2328
c4abb7c9
JK		 2329static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2330{
c4abb7c9 2331 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2332
2333 return 0;
2334}
2335
b209749f
AK		 2336static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2337 struct kvm_tpr_access_ctl *tac)
2338{
2339 if (tac->flags)
2340 return -EINVAL;
2341 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2342 return 0;
2343}
2344
890ca9ae
HY		 2345static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2346 u64 mcg_cap)
2347{
2348 int r;
2349 unsigned bank_num = mcg_cap & 0xff, bank;
2350
2351 r = -EINVAL;
a9e38c3e 2352 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2353 goto out;
2354 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2355 goto out;
2356 r = 0;
2357 vcpu->arch.mcg_cap = mcg_cap;
2358 /* Init IA32_MCG_CTL to all 1s */
2359 if (mcg_cap & MCG_CTL_P)
2360 vcpu->arch.mcg_ctl = ~(u64)0;
2361 /* Init IA32_MCi_CTL to all 1s */
2362 for (bank = 0; bank < bank_num; bank++)
2363 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2364out:
2365 return r;
2366}
2367
2368static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2369 struct kvm_x86_mce *mce)
2370{
2371 u64 mcg_cap = vcpu->arch.mcg_cap;
2372 unsigned bank_num = mcg_cap & 0xff;
2373 u64 *banks = vcpu->arch.mce_banks;
2374
2375 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2376 return -EINVAL;
2377 /*
2378 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2379 * reporting is disabled
2380 */
2381 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2382 vcpu->arch.mcg_ctl != ~(u64)0)
2383 return 0;
2384 banks += 4 * mce->bank;
2385 /*
2386 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2387 * reporting is disabled for the bank
2388 */
2389 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2390 return 0;
2391 if (mce->status & MCI_STATUS_UC) {
2392 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2393 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2394 printk(KERN_DEBUG "kvm: set_mce: "
2395 "injects mce exception while "
2396 "previous one is in progress!\n");
a8eeb04a 2397 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2398 return 0;
2399 }
2400 if (banks[1] & MCI_STATUS_VAL)
2401 mce->status |= MCI_STATUS_OVER;
2402 banks[2] = mce->addr;
2403 banks[3] = mce->misc;
2404 vcpu->arch.mcg_status = mce->mcg_status;
2405 banks[1] = mce->status;
2406 kvm_queue_exception(vcpu, MC_VECTOR);
2407 } else if (!(banks[1] & MCI_STATUS_VAL)
2408 || !(banks[1] & MCI_STATUS_UC)) {
2409 if (banks[1] & MCI_STATUS_VAL)
2410 mce->status |= MCI_STATUS_OVER;
2411 banks[2] = mce->addr;
2412 banks[3] = mce->misc;
2413 banks[1] = mce->status;
2414 } else
2415 banks[1] |= MCI_STATUS_OVER;
2416 return 0;
2417}
2418
3cfc3092
JK		 2419static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2420 struct kvm_vcpu_events *events)
2421{
03b82a30
JK		 2422 events->exception.injected =
2423 vcpu->arch.exception.pending &&
2424 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2425 events->exception.nr = vcpu->arch.exception.nr;
2426 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2427 events->exception.error_code = vcpu->arch.exception.error_code;
2428
03b82a30
JK		 2429 events->interrupt.injected =
2430 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2431 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2432 events->interrupt.soft = 0;
48005f64
JK		 2433 events->interrupt.shadow =
2434 kvm_x86_ops->get_interrupt_shadow(vcpu,
2435 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2436
2437 events->nmi.injected = vcpu->arch.nmi_injected;
2438 events->nmi.pending = vcpu->arch.nmi_pending;
2439 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2440
2441 events->sipi_vector = vcpu->arch.sipi_vector;
2442
dab4b911 2443 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2444 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2445 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2446}
2447
2448static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2449 struct kvm_vcpu_events *events)
2450{
dab4b911 2451 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2452 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2453 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2454 return -EINVAL;
2455
3cfc3092
JK		 2456 vcpu->arch.exception.pending = events->exception.injected;
2457 vcpu->arch.exception.nr = events->exception.nr;
2458 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2459 vcpu->arch.exception.error_code = events->exception.error_code;
2460
2461 vcpu->arch.interrupt.pending = events->interrupt.injected;
2462 vcpu->arch.interrupt.nr = events->interrupt.nr;
2463 vcpu->arch.interrupt.soft = events->interrupt.soft;
2464 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2465 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2466 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2467 kvm_x86_ops->set_interrupt_shadow(vcpu,
2468 events->interrupt.shadow);
3cfc3092
JK		 2469
2470 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2471 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2472 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2473 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2474
dab4b911
JK		 2475 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2476 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2477
3cfc3092
JK		 2478 return 0;
2479}
2480
a1efbe77
JK		 2481static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2482 struct kvm_debugregs *dbgregs)
2483{
a1efbe77
JK		 2484 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2485 dbgregs->dr6 = vcpu->arch.dr6;
2486 dbgregs->dr7 = vcpu->arch.dr7;
2487 dbgregs->flags = 0;
a1efbe77
JK		 2488}
2489
2490static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2491 struct kvm_debugregs *dbgregs)
2492{
2493 if (dbgregs->flags)
2494 return -EINVAL;
2495
a1efbe77
JK		 2496 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2497 vcpu->arch.dr6 = dbgregs->dr6;
2498 vcpu->arch.dr7 = dbgregs->dr7;
2499
a1efbe77
JK		 2500 return 0;
2501}
2502
2d5b5a66
SY		 2503static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2504 struct kvm_xsave *guest_xsave)
2505{
2506 if (cpu_has_xsave)
2507 memcpy(guest_xsave->region,
2508 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2509 xstate_size);
2d5b5a66
SY		 2510 else {
2511 memcpy(guest_xsave->region,
2512 &vcpu->arch.guest_fpu.state->fxsave,
2513 sizeof(struct i387_fxsave_struct));
2514 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2515 XSTATE_FPSSE;
2516 }
2517}
2518
2519static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2520 struct kvm_xsave *guest_xsave)
2521{
2522 u64 xstate_bv =
2523 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2524
2525 if (cpu_has_xsave)
2526 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2527 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2528 else {
2529 if (xstate_bv & ~XSTATE_FPSSE)
2530 return -EINVAL;
2531 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2532 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2533 }
2534 return 0;
2535}
2536
2537static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2538 struct kvm_xcrs *guest_xcrs)
2539{
2540 if (!cpu_has_xsave) {
2541 guest_xcrs->nr_xcrs = 0;
2542 return;
2543 }
2544
2545 guest_xcrs->nr_xcrs = 1;
2546 guest_xcrs->flags = 0;
2547 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2548 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2549}
2550
2551static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2552 struct kvm_xcrs *guest_xcrs)
2553{
2554 int i, r = 0;
2555
2556 if (!cpu_has_xsave)
2557 return -EINVAL;
2558
2559 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2560 return -EINVAL;
2561
2562 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2563 /* Only support XCR0 currently */
2564 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2565 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2566 guest_xcrs->xcrs[0].value);
2567 break;
2568 }
2569 if (r)
2570 r = -EINVAL;
2571 return r;
2572}
2573
313a3dc7
CO		 2574long kvm_arch_vcpu_ioctl(struct file *filp,
2575 unsigned int ioctl, unsigned long arg)
2576{
2577 struct kvm_vcpu *vcpu = filp->private_data;
2578 void __user *argp = (void __user *)arg;
2579 int r;
d1ac91d8
AK		 2580 union {
2581 struct kvm_lapic_state *lapic;
2582 struct kvm_xsave *xsave;
2583 struct kvm_xcrs *xcrs;
2584 void *buffer;
2585 } u;
2586
2587 u.buffer = NULL;
313a3dc7
CO		 2588 switch (ioctl) {
2589 case KVM_GET_LAPIC: {
2204ae3c
MT		 2590 r = -EINVAL;
2591 if (!vcpu->arch.apic)
2592 goto out;
d1ac91d8 2593 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2594
b772ff36 2595 r = -ENOMEM;
d1ac91d8 2596 if (!u.lapic)
b772ff36 2597 goto out;
d1ac91d8 2598 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2599 if (r)
2600 goto out;
2601 r = -EFAULT;
d1ac91d8 2602 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2603 goto out;
2604 r = 0;
2605 break;
2606 }
2607 case KVM_SET_LAPIC: {
2204ae3c
MT		 2608 r = -EINVAL;
2609 if (!vcpu->arch.apic)
2610 goto out;
d1ac91d8 2611 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2612 r = -ENOMEM;
d1ac91d8 2613 if (!u.lapic)
b772ff36 2614 goto out;
313a3dc7 2615 r = -EFAULT;
d1ac91d8 2616 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2617 goto out;
d1ac91d8 2618 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2619 if (r)
2620 goto out;
2621 r = 0;
2622 break;
2623 }
f77bc6a4
ZX		 2624 case KVM_INTERRUPT: {
2625 struct kvm_interrupt irq;
2626
2627 r = -EFAULT;
2628 if (copy_from_user(&irq, argp, sizeof irq))
2629 goto out;
2630 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2631 if (r)
2632 goto out;
2633 r = 0;
2634 break;
2635 }
c4abb7c9
JK		 2636 case KVM_NMI: {
2637 r = kvm_vcpu_ioctl_nmi(vcpu);
2638 if (r)
2639 goto out;
2640 r = 0;
2641 break;
2642 }
313a3dc7
CO		 2643 case KVM_SET_CPUID: {
2644 struct kvm_cpuid __user *cpuid_arg = argp;
2645 struct kvm_cpuid cpuid;
2646
2647 r = -EFAULT;
2648 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2649 goto out;
2650 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2651 if (r)
2652 goto out;
2653 break;
2654 }
07716717
DK		 2655 case KVM_SET_CPUID2: {
2656 struct kvm_cpuid2 __user *cpuid_arg = argp;
2657 struct kvm_cpuid2 cpuid;
2658
2659 r = -EFAULT;
2660 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2661 goto out;
2662 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2663 cpuid_arg->entries);
07716717
DK		 2664 if (r)
2665 goto out;
2666 break;
2667 }
2668 case KVM_GET_CPUID2: {
2669 struct kvm_cpuid2 __user *cpuid_arg = argp;
2670 struct kvm_cpuid2 cpuid;
2671
2672 r = -EFAULT;
2673 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2674 goto out;
2675 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2676 cpuid_arg->entries);
07716717
DK		 2677 if (r)
2678 goto out;
2679 r = -EFAULT;
2680 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2681 goto out;
2682 r = 0;
2683 break;
2684 }
313a3dc7
CO		 2685 case KVM_GET_MSRS:
2686 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2687 break;
2688 case KVM_SET_MSRS:
2689 r = msr_io(vcpu, argp, do_set_msr, 0);
2690 break;
b209749f
AK		 2691 case KVM_TPR_ACCESS_REPORTING: {
2692 struct kvm_tpr_access_ctl tac;
2693
2694 r = -EFAULT;
2695 if (copy_from_user(&tac, argp, sizeof tac))
2696 goto out;
2697 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2698 if (r)
2699 goto out;
2700 r = -EFAULT;
2701 if (copy_to_user(argp, &tac, sizeof tac))
2702 goto out;
2703 r = 0;
2704 break;
2705 };
b93463aa
AK		 2706 case KVM_SET_VAPIC_ADDR: {
2707 struct kvm_vapic_addr va;
2708
2709 r = -EINVAL;
2710 if (!irqchip_in_kernel(vcpu->kvm))
2711 goto out;
2712 r = -EFAULT;
2713 if (copy_from_user(&va, argp, sizeof va))
2714 goto out;
2715 r = 0;
2716 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2717 break;
2718 }
890ca9ae
HY		 2719 case KVM_X86_SETUP_MCE: {
2720 u64 mcg_cap;
2721
2722 r = -EFAULT;
2723 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2724 goto out;
2725 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2726 break;
2727 }
2728 case KVM_X86_SET_MCE: {
2729 struct kvm_x86_mce mce;
2730
2731 r = -EFAULT;
2732 if (copy_from_user(&mce, argp, sizeof mce))
2733 goto out;
2734 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2735 break;
2736 }
3cfc3092
JK		 2737 case KVM_GET_VCPU_EVENTS: {
2738 struct kvm_vcpu_events events;
2739
2740 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2741
2742 r = -EFAULT;
2743 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2744 break;
2745 r = 0;
2746 break;
2747 }
2748 case KVM_SET_VCPU_EVENTS: {
2749 struct kvm_vcpu_events events;
2750
2751 r = -EFAULT;
2752 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2753 break;
2754
2755 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2756 break;
2757 }
a1efbe77
JK		 2758 case KVM_GET_DEBUGREGS: {
2759 struct kvm_debugregs dbgregs;
2760
2761 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2762
2763 r = -EFAULT;
2764 if (copy_to_user(argp, &dbgregs,
2765 sizeof(struct kvm_debugregs)))
2766 break;
2767 r = 0;
2768 break;
2769 }
2770 case KVM_SET_DEBUGREGS: {
2771 struct kvm_debugregs dbgregs;
2772
2773 r = -EFAULT;
2774 if (copy_from_user(&dbgregs, argp,
2775 sizeof(struct kvm_debugregs)))
2776 break;
2777
2778 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2779 break;
2780 }
2d5b5a66 2781 case KVM_GET_XSAVE: {
d1ac91d8 2782 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2783 r = -ENOMEM;
d1ac91d8 2784 if (!u.xsave)
2d5b5a66
SY		 2785 break;
2786
d1ac91d8 2787 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2788
2789 r = -EFAULT;
d1ac91d8 2790 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2791 break;
2792 r = 0;
2793 break;
2794 }
2795 case KVM_SET_XSAVE: {
d1ac91d8 2796 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2797 r = -ENOMEM;
d1ac91d8 2798 if (!u.xsave)
2d5b5a66
SY		 2799 break;
2800
2801 r = -EFAULT;
d1ac91d8 2802 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2803 break;
2804
d1ac91d8 2805 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2806 break;
2807 }
2808 case KVM_GET_XCRS: {
d1ac91d8 2809 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2810 r = -ENOMEM;
d1ac91d8 2811 if (!u.xcrs)
2d5b5a66
SY		 2812 break;
2813
d1ac91d8 2814 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2815
2816 r = -EFAULT;
d1ac91d8 2817 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2818 sizeof(struct kvm_xcrs)))
2819 break;
2820 r = 0;
2821 break;
2822 }
2823 case KVM_SET_XCRS: {
d1ac91d8 2824 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2825 r = -ENOMEM;
d1ac91d8 2826 if (!u.xcrs)
2d5b5a66
SY		 2827 break;
2828
2829 r = -EFAULT;
d1ac91d8 2830 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2831 sizeof(struct kvm_xcrs)))
2832 break;
2833
d1ac91d8 2834 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2835 break;
2836 }
313a3dc7
CO		 2837 default:
2838 r = -EINVAL;
2839 }
2840out:
d1ac91d8 2841 kfree(u.buffer);
313a3dc7
CO		 2842 return r;
2843}
2844
1fe779f8
CO		 2845static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2846{
2847 int ret;
2848
2849 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2850 return -1;
2851 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2852 return ret;
2853}
2854
b927a3ce
SY		 2855static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2856 u64 ident_addr)
2857{
2858 kvm->arch.ept_identity_map_addr = ident_addr;
2859 return 0;
2860}
2861
1fe779f8
CO		 2862static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2863 u32 kvm_nr_mmu_pages)
2864{
2865 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2866 return -EINVAL;
2867
79fac95e 2868 mutex_lock(&kvm->slots_lock);
7c8a83b7 2869 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2870
2871 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2872 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2873
7c8a83b7 2874 spin_unlock(&kvm->mmu_lock);
79fac95e 2875 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2876 return 0;
2877}
2878
2879static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2880{
39de71ec 2881 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2882}
2883
1fe779f8
CO		 2884static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2885{
2886 int r;
2887
2888 r = 0;
2889 switch (chip->chip_id) {
2890 case KVM_IRQCHIP_PIC_MASTER:
2891 memcpy(&chip->chip.pic,
2892 &pic_irqchip(kvm)->pics[0],
2893 sizeof(struct kvm_pic_state));
2894 break;
2895 case KVM_IRQCHIP_PIC_SLAVE:
2896 memcpy(&chip->chip.pic,
2897 &pic_irqchip(kvm)->pics[1],
2898 sizeof(struct kvm_pic_state));
2899 break;
2900 case KVM_IRQCHIP_IOAPIC:
eba0226b 2901 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2902 break;
2903 default:
2904 r = -EINVAL;
2905 break;
2906 }
2907 return r;
2908}
2909
2910static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2911{
2912 int r;
2913
2914 r = 0;
2915 switch (chip->chip_id) {
2916 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2917 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2918 memcpy(&pic_irqchip(kvm)->pics[0],
2919 &chip->chip.pic,
2920 sizeof(struct kvm_pic_state));
fa8273e9 2921 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2922 break;
2923 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2924 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2925 memcpy(&pic_irqchip(kvm)->pics[1],
2926 &chip->chip.pic,
2927 sizeof(struct kvm_pic_state));
fa8273e9 2928 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2929 break;
2930 case KVM_IRQCHIP_IOAPIC:
eba0226b 2931 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2932 break;
2933 default:
2934 r = -EINVAL;
2935 break;
2936 }
2937 kvm_pic_update_irq(pic_irqchip(kvm));
2938 return r;
2939}
2940
e0f63cb9
SY		 2941static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2942{
2943 int r = 0;
2944
894a9c55 2945 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2946 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2947 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2948 return r;
2949}
2950
2951static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2952{
2953 int r = 0;
2954
894a9c55 2955 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2956 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2957 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2958 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2959 return r;
2960}
2961
2962static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2963{
2964 int r = 0;
2965
2966 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2967 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2968 sizeof(ps->channels));
2969 ps->flags = kvm->arch.vpit->pit_state.flags;
2970 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2971 return r;
2972}
2973
2974static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2975{
2976 int r = 0, start = 0;
2977 u32 prev_legacy, cur_legacy;
2978 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2979 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2980 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2981 if (!prev_legacy && cur_legacy)
2982 start = 1;
2983 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2984 sizeof(kvm->arch.vpit->pit_state.channels));
2985 kvm->arch.vpit->pit_state.flags = ps->flags;
2986 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2987 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2988 return r;
2989}
2990
52d939a0
MT		 2991static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2992 struct kvm_reinject_control *control)
2993{
2994 if (!kvm->arch.vpit)
2995 return -ENXIO;
894a9c55 2996 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2997 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2998 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2999 return 0;
3000}
3001
5bb064dc
ZX		 3002/*
3003 * Get (and clear) the dirty memory log for a memory slot.
3004 */
3005int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3006 struct kvm_dirty_log *log)
3007{
87bf6e7d 3008 int r, i;
5bb064dc 3009 struct kvm_memory_slot *memslot;
87bf6e7d 3010 unsigned long n;
b050b015 3011 unsigned long is_dirty = 0;
5bb064dc 3012
79fac95e 3013 mutex_lock(&kvm->slots_lock);
5bb064dc 3014
b050b015
MT		 3015 r = -EINVAL;
3016 if (log->slot >= KVM_MEMORY_SLOTS)
3017 goto out;
3018
3019 memslot = &kvm->memslots->memslots[log->slot];
3020 r = -ENOENT;
3021 if (!memslot->dirty_bitmap)
3022 goto out;
3023
87bf6e7d 3024 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3025
b050b015
MT		 3026 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3027 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3028
3029 /* If nothing is dirty, don't bother messing with page tables. */
3030 if (is_dirty) {
b050b015 3031 struct kvm_memslots *slots, *old_slots;
914ebccd 3032 unsigned long *dirty_bitmap;
b050b015 3033
7c8a83b7 3034 spin_lock(&kvm->mmu_lock);
5bb064dc 3035 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 3036 spin_unlock(&kvm->mmu_lock);
b050b015 3037
914ebccd
TY		 3038 r = -ENOMEM;
3039 dirty_bitmap = vmalloc(n);
3040 if (!dirty_bitmap)
3041 goto out;
3042 memset(dirty_bitmap, 0, n);
b050b015 3043
914ebccd
TY		 3044 r = -ENOMEM;
3045 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3046 if (!slots) {
3047 vfree(dirty_bitmap);
3048 goto out;
3049 }
b050b015
MT		 3050 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3051 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3052
3053 old_slots = kvm->memslots;
3054 rcu_assign_pointer(kvm->memslots, slots);
3055 synchronize_srcu_expedited(&kvm->srcu);
3056 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3057 kfree(old_slots);
914ebccd
TY		 3058
3059 r = -EFAULT;
3060 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3061 vfree(dirty_bitmap);
3062 goto out;
3063 }
3064 vfree(dirty_bitmap);
3065 } else {
3066 r = -EFAULT;
3067 if (clear_user(log->dirty_bitmap, n))
3068 goto out;
5bb064dc 3069 }
b050b015 3070
5bb064dc
ZX		 3071 r = 0;
3072out:
79fac95e 3073 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3074 return r;
3075}
3076
1fe779f8
CO		 3077long kvm_arch_vm_ioctl(struct file *filp,
3078 unsigned int ioctl, unsigned long arg)
3079{
3080 struct kvm *kvm = filp->private_data;
3081 void __user *argp = (void __user *)arg;
367e1319 3082 int r = -ENOTTY;
f0d66275
DH		 3083 /*
3084 * This union makes it completely explicit to gcc-3.x
3085 * that these two variables' stack usage should be
3086 * combined, not added together.
3087 */
3088 union {
3089 struct kvm_pit_state ps;
e9f42757 3090 struct kvm_pit_state2 ps2;
c5ff41ce 3091 struct kvm_pit_config pit_config;
f0d66275 3092 } u;
1fe779f8
CO		 3093
3094 switch (ioctl) {
3095 case KVM_SET_TSS_ADDR:
3096 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3097 if (r < 0)
3098 goto out;
3099 break;
b927a3ce
SY		 3100 case KVM_SET_IDENTITY_MAP_ADDR: {
3101 u64 ident_addr;
3102
3103 r = -EFAULT;
3104 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3105 goto out;
3106 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3107 if (r < 0)
3108 goto out;
3109 break;
3110 }
1fe779f8
CO		 3111 case KVM_SET_NR_MMU_PAGES:
3112 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3113 if (r)
3114 goto out;
3115 break;
3116 case KVM_GET_NR_MMU_PAGES:
3117 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3118 break;
3ddea128
MT		 3119 case KVM_CREATE_IRQCHIP: {
3120 struct kvm_pic *vpic;
3121
3122 mutex_lock(&kvm->lock);
3123 r = -EEXIST;
3124 if (kvm->arch.vpic)
3125 goto create_irqchip_unlock;
1fe779f8 3126 r = -ENOMEM;
3ddea128
MT		 3127 vpic = kvm_create_pic(kvm);
3128 if (vpic) {
1fe779f8
CO		 3129 r = kvm_ioapic_init(kvm);
3130 if (r) {
72bb2fcd
WY		 3131 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3132 &vpic->dev);
3ddea128
MT		 3133 kfree(vpic);
3134 goto create_irqchip_unlock;
1fe779f8
CO		 3135 }
3136 } else
3ddea128
MT		 3137 goto create_irqchip_unlock;
3138 smp_wmb();
3139 kvm->arch.vpic = vpic;
3140 smp_wmb();
399ec807
AK		 3141 r = kvm_setup_default_irq_routing(kvm);
3142 if (r) {
3ddea128 3143 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3144 kvm_ioapic_destroy(kvm);
3145 kvm_destroy_pic(kvm);
3ddea128 3146 mutex_unlock(&kvm->irq_lock);
399ec807 3147 }
3ddea128
MT		 3148 create_irqchip_unlock:
3149 mutex_unlock(&kvm->lock);
1fe779f8 3150 break;
3ddea128 3151 }
7837699f 3152 case KVM_CREATE_PIT:
c5ff41ce
JK		 3153 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3154 goto create_pit;
3155 case KVM_CREATE_PIT2:
3156 r = -EFAULT;
3157 if (copy_from_user(&u.pit_config, argp,
3158 sizeof(struct kvm_pit_config)))
3159 goto out;
3160 create_pit:
79fac95e 3161 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3162 r = -EEXIST;
3163 if (kvm->arch.vpit)
3164 goto create_pit_unlock;
7837699f 3165 r = -ENOMEM;
c5ff41ce 3166 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3167 if (kvm->arch.vpit)
3168 r = 0;
269e05e4 3169 create_pit_unlock:
79fac95e 3170 mutex_unlock(&kvm->slots_lock);
7837699f 3171 break;
4925663a 3172 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3173 case KVM_IRQ_LINE: {
3174 struct kvm_irq_level irq_event;
3175
3176 r = -EFAULT;
3177 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3178 goto out;
160d2f6c 3179 r = -ENXIO;
1fe779f8 3180 if (irqchip_in_kernel(kvm)) {
4925663a 3181 __s32 status;
4925663a
GN		 3182 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3183 irq_event.irq, irq_event.level);
4925663a 3184 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3185 r = -EFAULT;
4925663a
GN		 3186 irq_event.status = status;
3187 if (copy_to_user(argp, &irq_event,
3188 sizeof irq_event))
3189 goto out;
3190 }
1fe779f8
CO		 3191 r = 0;
3192 }
3193 break;
3194 }
3195 case KVM_GET_IRQCHIP: {
3196 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3197 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3198
f0d66275
DH		 3199 r = -ENOMEM;
3200 if (!chip)
1fe779f8 3201 goto out;
f0d66275
DH		 3202 r = -EFAULT;
3203 if (copy_from_user(chip, argp, sizeof *chip))
3204 goto get_irqchip_out;
1fe779f8
CO		 3205 r = -ENXIO;
3206 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3207 goto get_irqchip_out;
3208 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3209 if (r)
f0d66275 3210 goto get_irqchip_out;
1fe779f8 3211 r = -EFAULT;
f0d66275
DH		 3212 if (copy_to_user(argp, chip, sizeof *chip))
3213 goto get_irqchip_out;
1fe779f8 3214 r = 0;
f0d66275
DH		 3215 get_irqchip_out:
3216 kfree(chip);
3217 if (r)
3218 goto out;
1fe779f8
CO		 3219 break;
3220 }
3221 case KVM_SET_IRQCHIP: {
3222 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3223 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3224
f0d66275
DH		 3225 r = -ENOMEM;
3226 if (!chip)
1fe779f8 3227 goto out;
f0d66275
DH		 3228 r = -EFAULT;
3229 if (copy_from_user(chip, argp, sizeof *chip))
3230 goto set_irqchip_out;
1fe779f8
CO		 3231 r = -ENXIO;
3232 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3233 goto set_irqchip_out;
3234 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3235 if (r)
f0d66275 3236 goto set_irqchip_out;
1fe779f8 3237 r = 0;
f0d66275
DH		 3238 set_irqchip_out:
3239 kfree(chip);
3240 if (r)
3241 goto out;
1fe779f8
CO		 3242 break;
3243 }
e0f63cb9 3244 case KVM_GET_PIT: {
e0f63cb9 3245 r = -EFAULT;
f0d66275 3246 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3247 goto out;
3248 r = -ENXIO;
3249 if (!kvm->arch.vpit)
3250 goto out;
f0d66275 3251 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3252 if (r)
3253 goto out;
3254 r = -EFAULT;
f0d66275 3255 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3256 goto out;
3257 r = 0;
3258 break;
3259 }
3260 case KVM_SET_PIT: {
e0f63cb9 3261 r = -EFAULT;
f0d66275 3262 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3263 goto out;
3264 r = -ENXIO;
3265 if (!kvm->arch.vpit)
3266 goto out;
f0d66275 3267 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3268 if (r)
3269 goto out;
3270 r = 0;
3271 break;
3272 }
e9f42757
BK		 3273 case KVM_GET_PIT2: {
3274 r = -ENXIO;
3275 if (!kvm->arch.vpit)
3276 goto out;
3277 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3278 if (r)
3279 goto out;
3280 r = -EFAULT;
3281 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3282 goto out;
3283 r = 0;
3284 break;
3285 }
3286 case KVM_SET_PIT2: {
3287 r = -EFAULT;
3288 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3289 goto out;
3290 r = -ENXIO;
3291 if (!kvm->arch.vpit)
3292 goto out;
3293 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3294 if (r)
3295 goto out;
3296 r = 0;
3297 break;
3298 }
52d939a0
MT		 3299 case KVM_REINJECT_CONTROL: {
3300 struct kvm_reinject_control control;
3301 r = -EFAULT;
3302 if (copy_from_user(&control, argp, sizeof(control)))
3303 goto out;
3304 r = kvm_vm_ioctl_reinject(kvm, &control);
3305 if (r)
3306 goto out;
3307 r = 0;
3308 break;
3309 }
ffde22ac
ES		 3310 case KVM_XEN_HVM_CONFIG: {
3311 r = -EFAULT;
3312 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3313 sizeof(struct kvm_xen_hvm_config)))
3314 goto out;
3315 r = -EINVAL;
3316 if (kvm->arch.xen_hvm_config.flags)
3317 goto out;
3318 r = 0;
3319 break;
3320 }
afbcf7ab 3321 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3322 struct kvm_clock_data user_ns;
3323 u64 now_ns;
3324 s64 delta;
3325
3326 r = -EFAULT;
3327 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3328 goto out;
3329
3330 r = -EINVAL;
3331 if (user_ns.flags)
3332 goto out;
3333
3334 r = 0;
759379dd 3335 now_ns = get_kernel_ns();
afbcf7ab
GC		 3336 delta = user_ns.clock - now_ns;
3337 kvm->arch.kvmclock_offset = delta;
3338 break;
3339 }
3340 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3341 struct kvm_clock_data user_ns;
3342 u64 now_ns;
3343
759379dd 3344 now_ns = get_kernel_ns();
afbcf7ab
GC		 3345 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3346 user_ns.flags = 0;
3347
3348 r = -EFAULT;
3349 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3350 goto out;
3351 r = 0;
3352 break;
3353 }
3354
1fe779f8
CO		 3355 default:
3356 ;
3357 }
3358out:
3359 return r;
3360}
3361
a16b043c 3362static void kvm_init_msr_list(void)
043405e1
CO		 3363{
3364 u32 dummy[2];
3365 unsigned i, j;
3366
e3267cbb
GC		 3367 /* skip the first msrs in the list. KVM-specific */
3368 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3369 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3370 continue;
3371 if (j < i)
3372 msrs_to_save[j] = msrs_to_save[i];
3373 j++;
3374 }
3375 num_msrs_to_save = j;
3376}
3377
bda9020e
MT		 3378static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3379 const void *v)
bbd9b64e 3380{
bda9020e
MT		 3381 if (vcpu->arch.apic &&
3382 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3383 return 0;
bbd9b64e 3384
e93f8a0f 3385 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3386}
3387
bda9020e 3388static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3389{
bda9020e
MT		 3390 if (vcpu->arch.apic &&
3391 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3392 return 0;
bbd9b64e 3393
e93f8a0f 3394 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3395}
3396
2dafc6c2
GN		 3397static void kvm_set_segment(struct kvm_vcpu *vcpu,
3398 struct kvm_segment *var, int seg)
3399{
3400 kvm_x86_ops->set_segment(vcpu, var, seg);
3401}
3402
3403void kvm_get_segment(struct kvm_vcpu *vcpu,
3404 struct kvm_segment *var, int seg)
3405{
3406 kvm_x86_ops->get_segment(vcpu, var, seg);
3407}
3408
1871c602
GN		 3409gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3410{
3411 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3412 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3413}
3414
3415 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3416{
3417 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3418 access |= PFERR_FETCH_MASK;
3419 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3420}
3421
3422gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3423{
3424 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3425 access |= PFERR_WRITE_MASK;
3426 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3427}
3428
3429/* uses this to access any guest's mapped memory without checking CPL */
3430gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3431{
3432 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3433}
3434
3435static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3436 struct kvm_vcpu *vcpu, u32 access,
3437 u32 *error)
bbd9b64e
CO		 3438{
3439 void *data = val;
10589a46 3440 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3441
3442 while (bytes) {
1871c602 3443 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3444 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3445 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3446 int ret;
3447
10589a46
MT		 3448 if (gpa == UNMAPPED_GVA) {
3449 r = X86EMUL_PROPAGATE_FAULT;
3450 goto out;
3451 }
77c2002e 3452 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3453 if (ret < 0) {
c3cd7ffa 3454 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3455 goto out;
3456 }
bbd9b64e 3457
77c2002e
IE		 3458 bytes -= toread;
3459 data += toread;
3460 addr += toread;
bbd9b64e 3461 }
10589a46 3462out:
10589a46 3463 return r;
bbd9b64e 3464}
77c2002e 3465
1871c602
GN		 3466/* used for instruction fetching */
3467static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3468 struct kvm_vcpu *vcpu, u32 *error)
3469{
3470 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3471 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3472 access | PFERR_FETCH_MASK, error);
3473}
3474
3475static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3476 struct kvm_vcpu *vcpu, u32 *error)
3477{
3478 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3479 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3480 error);
3481}
3482
3483static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3484 struct kvm_vcpu *vcpu, u32 *error)
3485{
3486 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3487}
3488
7972995b 3489static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3490 unsigned int bytes,
7972995b 3491 struct kvm_vcpu *vcpu,
2dafc6c2 3492 u32 *error)
77c2002e
IE		 3493{
3494 void *data = val;
3495 int r = X86EMUL_CONTINUE;
3496
3497 while (bytes) {
7972995b
GN		 3498 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3499 PFERR_WRITE_MASK, error);
77c2002e
IE		 3500 unsigned offset = addr & (PAGE_SIZE-1);
3501 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3502 int ret;
3503
3504 if (gpa == UNMAPPED_GVA) {
3505 r = X86EMUL_PROPAGATE_FAULT;
3506 goto out;
3507 }
3508 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3509 if (ret < 0) {
c3cd7ffa 3510 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3511 goto out;
3512 }
3513
3514 bytes -= towrite;
3515 data += towrite;
3516 addr += towrite;
3517 }
3518out:
3519 return r;
3520}
3521
bbd9b64e
CO		 3522static int emulator_read_emulated(unsigned long addr,
3523 void *val,
3524 unsigned int bytes,
8fe681e9 3525 unsigned int *error_code,
bbd9b64e
CO		 3526 struct kvm_vcpu *vcpu)
3527{
bbd9b64e
CO		 3528 gpa_t gpa;
3529
3530 if (vcpu->mmio_read_completed) {
3531 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3532 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3533 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3534 vcpu->mmio_read_completed = 0;
3535 return X86EMUL_CONTINUE;
3536 }
3537
8fe681e9 3538 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3539
8fe681e9 3540 if (gpa == UNMAPPED_GVA)
1871c602 3541 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3542
3543 /* For APIC access vmexit */
3544 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3545 goto mmio;
3546
1871c602 3547 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3548 == X86EMUL_CONTINUE)
bbd9b64e 3549 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3550
3551mmio:
3552 /*
3553 * Is this MMIO handled locally?
3554 */
aec51dc4
AK		 3555 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3556 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3557 return X86EMUL_CONTINUE;
3558 }
aec51dc4
AK		 3559
3560 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3561
3562 vcpu->mmio_needed = 1;
411c35b7
GN		 3563 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3564 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3565 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3566 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3567
c3cd7ffa 3568 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3569}
3570
3200f405 3571int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3572 const void *val, int bytes)
bbd9b64e
CO		 3573{
3574 int ret;
3575
3576 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3577 if (ret < 0)
bbd9b64e 3578 return 0;
ad218f85 3579 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3580 return 1;
3581}
3582
3583static int emulator_write_emulated_onepage(unsigned long addr,
3584 const void *val,
3585 unsigned int bytes,
8fe681e9 3586 unsigned int *error_code,
bbd9b64e
CO		 3587 struct kvm_vcpu *vcpu)
3588{
10589a46
MT		 3589 gpa_t gpa;
3590
8fe681e9 3591 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3592
8fe681e9 3593 if (gpa == UNMAPPED_GVA)
bbd9b64e 3594 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3595
3596 /* For APIC access vmexit */
3597 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3598 goto mmio;
3599
3600 if (emulator_write_phys(vcpu, gpa, val, bytes))
3601 return X86EMUL_CONTINUE;
3602
3603mmio:
aec51dc4 3604 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3605 /*
3606 * Is this MMIO handled locally?
3607 */
bda9020e 3608 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3609 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3610
3611 vcpu->mmio_needed = 1;
411c35b7
GN		 3612 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3613 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3614 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3615 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3616 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3617
3618 return X86EMUL_CONTINUE;
3619}
3620
3621int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3622 const void *val,
3623 unsigned int bytes,
8fe681e9 3624 unsigned int *error_code,
8f6abd06 3625 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3626{
3627 /* Crossing a page boundary? */
3628 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3629 int rc, now;
3630
3631 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3632 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3633 vcpu);
bbd9b64e
CO		 3634 if (rc != X86EMUL_CONTINUE)
3635 return rc;
3636 addr += now;
3637 val += now;
3638 bytes -= now;
3639 }
8fe681e9
GN		 3640 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3641 vcpu);
bbd9b64e 3642}
bbd9b64e 3643
daea3e73
AK		 3644#define CMPXCHG_TYPE(t, ptr, old, new) \
3645 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3646
3647#ifdef CONFIG_X86_64
3648# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3649#else
3650# define CMPXCHG64(ptr, old, new) \
9749a6c0 3651 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3652#endif
3653
bbd9b64e
CO		 3654static int emulator_cmpxchg_emulated(unsigned long addr,
3655 const void *old,
3656 const void *new,
3657 unsigned int bytes,
8fe681e9 3658 unsigned int *error_code,
bbd9b64e
CO		 3659 struct kvm_vcpu *vcpu)
3660{
daea3e73
AK		 3661 gpa_t gpa;
3662 struct page *page;
3663 char *kaddr;
3664 bool exchanged;
2bacc55c 3665
daea3e73
AK		 3666 /* guests cmpxchg8b have to be emulated atomically */
3667 if (bytes > 8 || (bytes & (bytes - 1)))
3668 goto emul_write;
10589a46 3669
daea3e73 3670 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3671
daea3e73
AK		 3672 if (gpa == UNMAPPED_GVA ||
3673 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3674 goto emul_write;
2bacc55c 3675
daea3e73
AK		 3676 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3677 goto emul_write;
72dc67a6 3678
daea3e73 3679 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3680 if (is_error_page(page)) {
3681 kvm_release_page_clean(page);
3682 goto emul_write;
3683 }
72dc67a6 3684
daea3e73
AK		 3685 kaddr = kmap_atomic(page, KM_USER0);
3686 kaddr += offset_in_page(gpa);
3687 switch (bytes) {
3688 case 1:
3689 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3690 break;
3691 case 2:
3692 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3693 break;
3694 case 4:
3695 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3696 break;
3697 case 8:
3698 exchanged = CMPXCHG64(kaddr, old, new);
3699 break;
3700 default:
3701 BUG();
2bacc55c 3702 }
daea3e73
AK		 3703 kunmap_atomic(kaddr, KM_USER0);
3704 kvm_release_page_dirty(page);
3705
3706 if (!exchanged)
3707 return X86EMUL_CMPXCHG_FAILED;
3708
8f6abd06
GN		 3709 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3710
3711 return X86EMUL_CONTINUE;
4a5f48f6 3712
3200f405 3713emul_write:
daea3e73 3714 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3715
8fe681e9 3716 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3717}
3718
cf8f70bf
GN		 3719static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3720{
3721 /* TODO: String I/O for in kernel device */
3722 int r;
3723
3724 if (vcpu->arch.pio.in)
3725 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3726 vcpu->arch.pio.size, pd);
3727 else
3728 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3729 vcpu->arch.pio.port, vcpu->arch.pio.size,
3730 pd);
3731 return r;
3732}
3733
3734
3735static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3736 unsigned int count, struct kvm_vcpu *vcpu)
3737{
7972995b 3738 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3739 goto data_avail;
3740
3741 trace_kvm_pio(1, port, size, 1);
3742
3743 vcpu->arch.pio.port = port;
3744 vcpu->arch.pio.in = 1;
7972995b 3745 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3746 vcpu->arch.pio.size = size;
3747
3748 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3749 data_avail:
3750 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3751 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3752 return 1;
3753 }
3754
3755 vcpu->run->exit_reason = KVM_EXIT_IO;
3756 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3757 vcpu->run->io.size = size;
3758 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3759 vcpu->run->io.count = count;
3760 vcpu->run->io.port = port;
3761
3762 return 0;
3763}
3764
3765static int emulator_pio_out_emulated(int size, unsigned short port,
3766 const void *val, unsigned int count,
3767 struct kvm_vcpu *vcpu)
3768{
3769 trace_kvm_pio(0, port, size, 1);
3770
3771 vcpu->arch.pio.port = port;
3772 vcpu->arch.pio.in = 0;
7972995b 3773 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3774 vcpu->arch.pio.size = size;
3775
3776 memcpy(vcpu->arch.pio_data, val, size * count);
3777
3778 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3779 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3780 return 1;
3781 }
3782
3783 vcpu->run->exit_reason = KVM_EXIT_IO;
3784 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3785 vcpu->run->io.size = size;
3786 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3787 vcpu->run->io.count = count;
3788 vcpu->run->io.port = port;
3789
3790 return 0;
3791}
3792
bbd9b64e
CO		 3793static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3794{
3795 return kvm_x86_ops->get_segment_base(vcpu, seg);
3796}
3797
3798int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3799{
a7052897 3800 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3801 return X86EMUL_CONTINUE;
3802}
3803
f5f48ee1
SY		 3804int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3805{
3806 if (!need_emulate_wbinvd(vcpu))
3807 return X86EMUL_CONTINUE;
3808
3809 if (kvm_x86_ops->has_wbinvd_exit()) {
3810 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3811 wbinvd_ipi, NULL, 1);
3812 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3813 }
3814 wbinvd();
3815 return X86EMUL_CONTINUE;
3816}
3817EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3818
bbd9b64e
CO		 3819int emulate_clts(struct kvm_vcpu *vcpu)
3820{
4d4ec087 3821 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3822 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3823 return X86EMUL_CONTINUE;
3824}
3825
35aa5375 3826int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3827{
338dbc97 3828 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3829}
3830
35aa5375 3831int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3832{
338dbc97
GN		 3833
3834 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3835}
3836
52a46617 3837static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3838{
52a46617 3839 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3840}
3841
52a46617 3842static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3843{
52a46617
GN		 3844 unsigned long value;
3845
3846 switch (cr) {
3847 case 0:
3848 value = kvm_read_cr0(vcpu);
3849 break;
3850 case 2:
3851 value = vcpu->arch.cr2;
3852 break;
3853 case 3:
3854 value = vcpu->arch.cr3;
3855 break;
3856 case 4:
3857 value = kvm_read_cr4(vcpu);
3858 break;
3859 case 8:
3860 value = kvm_get_cr8(vcpu);
3861 break;
3862 default:
3863 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3864 return 0;
3865 }
3866
3867 return value;
3868}
3869
0f12244f 3870static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3871{
0f12244f
GN		 3872 int res = 0;
3873
52a46617
GN		 3874 switch (cr) {
3875 case 0:
49a9b07e 3876 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3877 break;
3878 case 2:
3879 vcpu->arch.cr2 = val;
3880 break;
3881 case 3:
2390218b 3882 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 3883 break;
3884 case 4:
a83b29c6 3885 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3886 break;
3887 case 8:
0f12244f 3888 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3889 break;
3890 default:
3891 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3892 res = -1;
52a46617 3893 }
0f12244f
GN		 3894
3895 return res;
52a46617
GN		 3896}
3897
9c537244
GN		 3898static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3899{
3900 return kvm_x86_ops->get_cpl(vcpu);
3901}
3902
2dafc6c2
GN		 3903static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3904{
3905 kvm_x86_ops->get_gdt(vcpu, dt);
3906}
3907
160ce1f1
MG		 3908static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3909{
3910 kvm_x86_ops->get_idt(vcpu, dt);
3911}
3912
5951c442
GN		 3913static unsigned long emulator_get_cached_segment_base(int seg,
3914 struct kvm_vcpu *vcpu)
3915{
3916 return get_segment_base(vcpu, seg);
3917}
3918
2dafc6c2
GN		 3919static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3920 struct kvm_vcpu *vcpu)
3921{
3922 struct kvm_segment var;
3923
3924 kvm_get_segment(vcpu, &var, seg);
3925
3926 if (var.unusable)
3927 return false;
3928
3929 if (var.g)
3930 var.limit >>= 12;
3931 set_desc_limit(desc, var.limit);
3932 set_desc_base(desc, (unsigned long)var.base);
3933 desc->type = var.type;
3934 desc->s = var.s;
3935 desc->dpl = var.dpl;
3936 desc->p = var.present;
3937 desc->avl = var.avl;
3938 desc->l = var.l;
3939 desc->d = var.db;
3940 desc->g = var.g;
3941
3942 return true;
3943}
3944
3945static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3946 struct kvm_vcpu *vcpu)
3947{
3948 struct kvm_segment var;
3949
3950 /* needed to preserve selector */
3951 kvm_get_segment(vcpu, &var, seg);
3952
3953 var.base = get_desc_base(desc);
3954 var.limit = get_desc_limit(desc);
3955 if (desc->g)
3956 var.limit = (var.limit << 12) | 0xfff;
3957 var.type = desc->type;
3958 var.present = desc->p;
3959 var.dpl = desc->dpl;
3960 var.db = desc->d;
3961 var.s = desc->s;
3962 var.l = desc->l;
3963 var.g = desc->g;
3964 var.avl = desc->avl;
3965 var.present = desc->p;
3966 var.unusable = !var.present;
3967 var.padding = 0;
3968
3969 kvm_set_segment(vcpu, &var, seg);
3970 return;
3971}
3972
3973static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3974{
3975 struct kvm_segment kvm_seg;
3976
3977 kvm_get_segment(vcpu, &kvm_seg, seg);
3978 return kvm_seg.selector;
3979}
3980
3981static void emulator_set_segment_selector(u16 sel, int seg,
3982 struct kvm_vcpu *vcpu)
3983{
3984 struct kvm_segment kvm_seg;
3985
3986 kvm_get_segment(vcpu, &kvm_seg, seg);
3987 kvm_seg.selector = sel;
3988 kvm_set_segment(vcpu, &kvm_seg, seg);
3989}
3990
14af3f3c 3991static struct x86_emulate_ops emulate_ops = {
1871c602 3992 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3993 .write_std = kvm_write_guest_virt_system,
1871c602 3994 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3995 .read_emulated = emulator_read_emulated,
3996 .write_emulated = emulator_write_emulated,
3997 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3998 .pio_in_emulated = emulator_pio_in_emulated,
3999 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4000 .get_cached_descriptor = emulator_get_cached_descriptor,
4001 .set_cached_descriptor = emulator_set_cached_descriptor,
4002 .get_segment_selector = emulator_get_segment_selector,
4003 .set_segment_selector = emulator_set_segment_selector,
5951c442 4004 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4005 .get_gdt = emulator_get_gdt,
160ce1f1 4006 .get_idt = emulator_get_idt,
52a46617
GN		 4007 .get_cr = emulator_get_cr,
4008 .set_cr = emulator_set_cr,
9c537244 4009 .cpl = emulator_get_cpl,
35aa5375
GN		 4010 .get_dr = emulator_get_dr,
4011 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4012 .set_msr = kvm_set_msr,
4013 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4014};
4015
5fdbf976
MT		 4016static void cache_all_regs(struct kvm_vcpu *vcpu)
4017{
4018 kvm_register_read(vcpu, VCPU_REGS_RAX);
4019 kvm_register_read(vcpu, VCPU_REGS_RSP);
4020 kvm_register_read(vcpu, VCPU_REGS_RIP);
4021 vcpu->arch.regs_dirty = ~0;
4022}
4023
95cb2295
GN		 4024static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4025{
4026 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4027 /*
4028 * an sti; sti; sequence only disable interrupts for the first
4029 * instruction. So, if the last instruction, be it emulated or
4030 * not, left the system with the INT_STI flag enabled, it
4031 * means that the last instruction is an sti. We should not
4032 * leave the flag on in this case. The same goes for mov ss
4033 */
4034 if (!(int_shadow & mask))
4035 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4036}
4037
54b8486f
GN		 4038static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4039{
4040 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4041 if (ctxt->exception == PF_VECTOR)
4042 kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code);
4043 else if (ctxt->error_code_valid)
4044 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4045 else
4046 kvm_queue_exception(vcpu, ctxt->exception);
4047}
4048
8ec4722d
MG		 4049static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4050{
4051 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4052 int cs_db, cs_l;
4053
4054 cache_all_regs(vcpu);
4055
4056 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4057
4058 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4059 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4060 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4061 vcpu->arch.emulate_ctxt.mode =
4062 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4063 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4064 ? X86EMUL_MODE_VM86 : cs_l
4065 ? X86EMUL_MODE_PROT64 : cs_db
4066 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4067 memset(c, 0, sizeof(struct decode_cache));
4068 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4069}
4070
6d77dbfc
GN		 4071static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4072{
6d77dbfc
GN		 4073 ++vcpu->stat.insn_emulation_fail;
4074 trace_kvm_emulate_insn_failed(vcpu);
4075 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4076 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4077 vcpu->run->internal.ndata = 0;
4078 kvm_queue_exception(vcpu, UD_VECTOR);
4079 return EMULATE_FAIL;
4080}
4081
a6f177ef
GN		 4082static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4083{
4084 gpa_t gpa;
4085
68be0803
GN		 4086 if (tdp_enabled)
4087 return false;
4088
a6f177ef
GN		 4089 /*
4090 * if emulation was due to access to shadowed page table
4091 * and it failed try to unshadow page and re-entetr the
4092 * guest to let CPU execute the instruction.
4093 */
4094 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4095 return true;
4096
4097 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4098
4099 if (gpa == UNMAPPED_GVA)
4100 return true; /* let cpu generate fault */
4101
4102 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4103 return true;
4104
4105 return false;
4106}
4107
bbd9b64e 4108int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4109 unsigned long cr2,
4110 u16 error_code,
571008da 4111 int emulation_type)
bbd9b64e 4112{
95cb2295 4113 int r;
4d2179e1 4114 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4115
26eef70c 4116 kvm_clear_exception_queue(vcpu);
ad312c7c 4117 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4118 /*
56e82318 4119 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4120 * instead of direct ->regs accesses, can save hundred cycles
4121 * on Intel for instructions that don't read/change RSP, for
4122 * for example.
4123 */
4124 cache_all_regs(vcpu);
bbd9b64e 4125
571008da 4126 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4127 init_emulate_ctxt(vcpu);
95cb2295 4128 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4129 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4130 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4131
9aabc88f 4132 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
e46479f8 4133 trace_kvm_emulate_insn_start(vcpu);
571008da 4134
0cb5762e
AP		 4135 /* Only allow emulation of specific instructions on #UD
4136 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4137 if (emulation_type & EMULTYPE_TRAP_UD) {
4138 if (!c->twobyte)
4139 return EMULATE_FAIL;
4140 switch (c->b) {
4141 case 0x01: /* VMMCALL */
4142 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4143 return EMULATE_FAIL;
4144 break;
4145 case 0x34: /* sysenter */
4146 case 0x35: /* sysexit */
4147 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4148 return EMULATE_FAIL;
4149 break;
4150 case 0x05: /* syscall */
4151 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4152 return EMULATE_FAIL;
4153 break;
4154 default:
4155 return EMULATE_FAIL;
4156 }
4157
4158 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4159 return EMULATE_FAIL;
4160 }
571008da 4161
f2b5756b 4162 ++vcpu->stat.insn_emulation;
bbd9b64e 4163 if (r) {
a6f177ef 4164 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4165 return EMULATE_DONE;
6d77dbfc
GN		 4166 if (emulation_type & EMULTYPE_SKIP)
4167 return EMULATE_FAIL;
4168 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4169 }
4170 }
4171
ba8afb6b
GN		 4172 if (emulation_type & EMULTYPE_SKIP) {
4173 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4174 return EMULATE_DONE;
4175 }
4176
4d2179e1
GN		 4177 /* this is needed for vmware backdor interface to work since it
4178 changes registers values during IO operation */
4179 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4180
5cd21917 4181restart:
9aabc88f 4182 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4183
d2ddd1c4 4184 if (r == EMULATION_FAILED) {
a6f177ef 4185 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4186 return EMULATE_DONE;
4187
6d77dbfc 4188 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4189 }
4190
d2ddd1c4 4191 if (vcpu->arch.emulate_ctxt.exception >= 0) {
54b8486f 4192 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4193 r = EMULATE_DONE;
4194 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4195 if (!vcpu->arch.pio.in)
4196 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4197 r = EMULATE_DO_MMIO;
4198 } else if (vcpu->mmio_needed) {
3457e419
GN		 4199 if (vcpu->mmio_is_write)
4200 vcpu->mmio_needed = 0;
e85d28f8 4201 r = EMULATE_DO_MMIO;
d2ddd1c4 4202 } else if (r == EMULATION_RESTART)
5cd21917 4203 goto restart;
d2ddd1c4
GN		 4204 else
4205 r = EMULATE_DONE;
f850e2e6 4206
e85d28f8
GN		 4207 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4208 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4209 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4210 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4211
4212 return r;
de7d789a 4213}
bbd9b64e 4214EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4215
cf8f70bf 4216int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4217{
cf8f70bf
GN		 4218 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4219 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4220 /* do not return to emulator after return from userspace */
7972995b 4221 vcpu->arch.pio.count = 0;
de7d789a
CO		 4222 return ret;
4223}
cf8f70bf 4224EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4225
8cfdc000
ZA		 4226static void tsc_bad(void *info)
4227{
4228 __get_cpu_var(cpu_tsc_khz) = 0;
4229}
4230
4231static void tsc_khz_changed(void *data)
c8076604 4232{
8cfdc000
ZA		 4233 struct cpufreq_freqs *freq = data;
4234 unsigned long khz = 0;
4235
4236 if (data)
4237 khz = freq->new;
4238 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4239 khz = cpufreq_quick_get(raw_smp_processor_id());
4240 if (!khz)
4241 khz = tsc_khz;
4242 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4243}
4244
c8076604
GH		 4245static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4246 void *data)
4247{
4248 struct cpufreq_freqs *freq = data;
4249 struct kvm *kvm;
4250 struct kvm_vcpu *vcpu;
4251 int i, send_ipi = 0;
4252
8cfdc000
ZA		 4253 /*
4254 * We allow guests to temporarily run on slowing clocks,
4255 * provided we notify them after, or to run on accelerating
4256 * clocks, provided we notify them before. Thus time never
4257 * goes backwards.
4258 *
4259 * However, we have a problem. We can't atomically update
4260 * the frequency of a given CPU from this function; it is
4261 * merely a notifier, which can be called from any CPU.
4262 * Changing the TSC frequency at arbitrary points in time
4263 * requires a recomputation of local variables related to
4264 * the TSC for each VCPU. We must flag these local variables
4265 * to be updated and be sure the update takes place with the
4266 * new frequency before any guests proceed.
4267 *
4268 * Unfortunately, the combination of hotplug CPU and frequency
4269 * change creates an intractable locking scenario; the order
4270 * of when these callouts happen is undefined with respect to
4271 * CPU hotplug, and they can race with each other. As such,
4272 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4273 * undefined; you can actually have a CPU frequency change take
4274 * place in between the computation of X and the setting of the
4275 * variable. To protect against this problem, all updates of
4276 * the per_cpu tsc_khz variable are done in an interrupt
4277 * protected IPI, and all callers wishing to update the value
4278 * must wait for a synchronous IPI to complete (which is trivial
4279 * if the caller is on the CPU already). This establishes the
4280 * necessary total order on variable updates.
4281 *
4282 * Note that because a guest time update may take place
4283 * anytime after the setting of the VCPU's request bit, the
4284 * correct TSC value must be set before the request. However,
4285 * to ensure the update actually makes it to any guest which
4286 * starts running in hardware virtualization between the set
4287 * and the acquisition of the spinlock, we must also ping the
4288 * CPU after setting the request bit.
4289 *
4290 */
4291
c8076604
GH		 4292 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4293 return 0;
4294 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4295 return 0;
8cfdc000
ZA		 4296
4297 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4298
4299 spin_lock(&kvm_lock);
4300 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4301 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4302 if (vcpu->cpu != freq->cpu)
4303 continue;
4304 if (!kvm_request_guest_time_update(vcpu))
4305 continue;
4306 if (vcpu->cpu != smp_processor_id())
8cfdc000 4307 send_ipi = 1;
c8076604
GH		 4308 }
4309 }
4310 spin_unlock(&kvm_lock);
4311
4312 if (freq->old < freq->new && send_ipi) {
4313 /*
4314 * We upscale the frequency. Must make the guest
4315 * doesn't see old kvmclock values while running with
4316 * the new frequency, otherwise we risk the guest sees
4317 * time go backwards.
4318 *
4319 * In case we update the frequency for another cpu
4320 * (which might be in guest context) send an interrupt
4321 * to kick the cpu out of guest context. Next time
4322 * guest context is entered kvmclock will be updated,
4323 * so the guest will not see stale values.
4324 */
8cfdc000 4325 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4326 }
4327 return 0;
4328}
4329
4330static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4331 .notifier_call = kvmclock_cpufreq_notifier
4332};
4333
4334static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4335 unsigned long action, void *hcpu)
4336{
4337 unsigned int cpu = (unsigned long)hcpu;
4338
4339 switch (action) {
4340 case CPU_ONLINE:
4341 case CPU_DOWN_FAILED:
4342 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4343 break;
4344 case CPU_DOWN_PREPARE:
4345 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4346 break;
4347 }
4348 return NOTIFY_OK;
4349}
4350
4351static struct notifier_block kvmclock_cpu_notifier_block = {
4352 .notifier_call = kvmclock_cpu_notifier,
4353 .priority = -INT_MAX
c8076604
GH		 4354};
4355
b820cc0c
ZA		 4356static void kvm_timer_init(void)
4357{
4358 int cpu;
4359
8cfdc000 4360 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4361 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4362 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4363 CPUFREQ_TRANSITION_NOTIFIER);
4364 }
8cfdc000
ZA		 4365 for_each_online_cpu(cpu)
4366 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4367}
4368
ff9d07a0
ZY		 4369static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4370
4371static int kvm_is_in_guest(void)
4372{
4373 return percpu_read(current_vcpu) != NULL;
4374}
4375
4376static int kvm_is_user_mode(void)
4377{
4378 int user_mode = 3;
dcf46b94 4379
ff9d07a0
ZY		 4380 if (percpu_read(current_vcpu))
4381 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4382
ff9d07a0
ZY		 4383 return user_mode != 0;
4384}
4385
4386static unsigned long kvm_get_guest_ip(void)
4387{
4388 unsigned long ip = 0;
dcf46b94 4389
ff9d07a0
ZY		 4390 if (percpu_read(current_vcpu))
4391 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4392
ff9d07a0
ZY		 4393 return ip;
4394}
4395
4396static struct perf_guest_info_callbacks kvm_guest_cbs = {
4397 .is_in_guest = kvm_is_in_guest,
4398 .is_user_mode = kvm_is_user_mode,
4399 .get_guest_ip = kvm_get_guest_ip,
4400};
4401
4402void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4403{
4404 percpu_write(current_vcpu, vcpu);
4405}
4406EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4407
4408void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4409{
4410 percpu_write(current_vcpu, NULL);
4411}
4412EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4413
f8c16bba 4414int kvm_arch_init(void *opaque)
043405e1 4415{
b820cc0c 4416 int r;
f8c16bba
ZX		 4417 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4418
f8c16bba
ZX		 4419 if (kvm_x86_ops) {
4420 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4421 r = -EEXIST;
4422 goto out;
f8c16bba
ZX		 4423 }
4424
4425 if (!ops->cpu_has_kvm_support()) {
4426 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4427 r = -EOPNOTSUPP;
4428 goto out;
f8c16bba
ZX		 4429 }
4430 if (ops->disabled_by_bios()) {
4431 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4432 r = -EOPNOTSUPP;
4433 goto out;
f8c16bba
ZX		 4434 }
4435
97db56ce
AK		 4436 r = kvm_mmu_module_init();
4437 if (r)
4438 goto out;
4439
4440 kvm_init_msr_list();
4441
f8c16bba 4442 kvm_x86_ops = ops;
56c6d28a 4443 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4444 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4445 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4446 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4447
b820cc0c 4448 kvm_timer_init();
c8076604 4449
ff9d07a0
ZY		 4450 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4451
2acf923e
DC		 4452 if (cpu_has_xsave)
4453 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4454
f8c16bba 4455 return 0;
56c6d28a
ZX		 4456
4457out:
56c6d28a 4458 return r;
043405e1 4459}
8776e519 4460
f8c16bba
ZX		 4461void kvm_arch_exit(void)
4462{
ff9d07a0
ZY		 4463 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4464
888d256e
JK		 4465 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4466 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4467 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4468 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4469 kvm_x86_ops = NULL;
56c6d28a
ZX		 4470 kvm_mmu_module_exit();
4471}
f8c16bba 4472
8776e519
HB		 4473int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4474{
4475 ++vcpu->stat.halt_exits;
4476 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4477 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4478 return 1;
4479 } else {
4480 vcpu->run->exit_reason = KVM_EXIT_HLT;
4481 return 0;
4482 }
4483}
4484EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4485
2f333bcb
MT		 4486static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4487 unsigned long a1)
4488{
4489 if (is_long_mode(vcpu))
4490 return a0;
4491 else
4492 return a0 | ((gpa_t)a1 << 32);
4493}
4494
55cd8e5a
GN		 4495int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4496{
4497 u64 param, ingpa, outgpa, ret;
4498 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4499 bool fast, longmode;
4500 int cs_db, cs_l;
4501
4502 /*
4503 * hypercall generates UD from non zero cpl and real mode
4504 * per HYPER-V spec
4505 */
3eeb3288 4506 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4507 kvm_queue_exception(vcpu, UD_VECTOR);
4508 return 0;
4509 }
4510
4511 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4512 longmode = is_long_mode(vcpu) && cs_l == 1;
4513
4514 if (!longmode) {
ccd46936
GN		 4515 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4516 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4517 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4518 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4519 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4520 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4521 }
4522#ifdef CONFIG_X86_64
4523 else {
4524 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4525 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4526 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4527 }
4528#endif
4529
4530 code = param & 0xffff;
4531 fast = (param >> 16) & 0x1;
4532 rep_cnt = (param >> 32) & 0xfff;
4533 rep_idx = (param >> 48) & 0xfff;
4534
4535 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4536
c25bc163
GN		 4537 switch (code) {
4538 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4539 kvm_vcpu_on_spin(vcpu);
4540 break;
4541 default:
4542 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4543 break;
4544 }
55cd8e5a
GN		 4545
4546 ret = res | (((u64)rep_done & 0xfff) << 32);
4547 if (longmode) {
4548 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4549 } else {
4550 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4551 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4552 }
4553
4554 return 1;
4555}
4556
8776e519
HB		 4557int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4558{
4559 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4560 int r = 1;
8776e519 4561
55cd8e5a
GN		 4562 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4563 return kvm_hv_hypercall(vcpu);
4564
5fdbf976
MT		 4565 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4566 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4567 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4568 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4569 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4570
229456fc 4571 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4572
8776e519
HB		 4573 if (!is_long_mode(vcpu)) {
4574 nr &= 0xFFFFFFFF;
4575 a0 &= 0xFFFFFFFF;
4576 a1 &= 0xFFFFFFFF;
4577 a2 &= 0xFFFFFFFF;
4578 a3 &= 0xFFFFFFFF;
4579 }
4580
07708c4a
JK		 4581 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4582 ret = -KVM_EPERM;
4583 goto out;
4584 }
4585
8776e519 4586 switch (nr) {
b93463aa
AK		 4587 case KVM_HC_VAPIC_POLL_IRQ:
4588 ret = 0;
4589 break;
2f333bcb
MT		 4590 case KVM_HC_MMU_OP:
4591 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4592 break;
8776e519
HB		 4593 default:
4594 ret = -KVM_ENOSYS;
4595 break;
4596 }
07708c4a 4597out:
5fdbf976 4598 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4599 ++vcpu->stat.hypercalls;
2f333bcb 4600 return r;
8776e519
HB		 4601}
4602EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4603
4604int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4605{
4606 char instruction[3];
5fdbf976 4607 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4608
8776e519
HB		 4609 /*
4610 * Blow out the MMU to ensure that no other VCPU has an active mapping
4611 * to ensure that the updated hypercall appears atomically across all
4612 * VCPUs.
4613 */
4614 kvm_mmu_zap_all(vcpu->kvm);
4615
8776e519 4616 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4617
8fe681e9 4618 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4619}
4620
8776e519
HB		 4621void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4622{
89a27f4d 4623 struct desc_ptr dt = { limit, base };
8776e519
HB		 4624
4625 kvm_x86_ops->set_gdt(vcpu, &dt);
4626}
4627
4628void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4629{
89a27f4d 4630 struct desc_ptr dt = { limit, base };
8776e519
HB		 4631
4632 kvm_x86_ops->set_idt(vcpu, &dt);
4633}
4634
07716717
DK		 4635static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4636{
ad312c7c
ZX		 4637 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4638 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4639
4640 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4641 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4642 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4643 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4644 if (ej->function == e->function) {
4645 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4646 return j;
4647 }
4648 }
4649 return 0; /* silence gcc, even though control never reaches here */
4650}
4651
4652/* find an entry with matching function, matching index (if needed), and that
4653 * should be read next (if it's stateful) */
4654static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4655 u32 function, u32 index)
4656{
4657 if (e->function != function)
4658 return 0;
4659 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4660 return 0;
4661 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4662 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4663 return 0;
4664 return 1;
4665}
4666
d8017474
AG		 4667struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4668 u32 function, u32 index)
8776e519
HB		 4669{
4670 int i;
d8017474 4671 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4672
ad312c7c 4673 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4674 struct kvm_cpuid_entry2 *e;
4675
ad312c7c 4676 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4677 if (is_matching_cpuid_entry(e, function, index)) {
4678 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4679 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4680 best = e;
4681 break;
4682 }
4683 /*
4684 * Both basic or both extended?
4685 */
4686 if (((e->function ^ function) & 0x80000000) == 0)
4687 if (!best || e->function > best->function)
4688 best = e;
4689 }
d8017474
AG		 4690 return best;
4691}
0e851880 4692EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4693
82725b20
DE		 4694int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4695{
4696 struct kvm_cpuid_entry2 *best;
4697
f7a71197
AK		 4698 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4699 if (!best || best->eax < 0x80000008)
4700 goto not_found;
82725b20
DE		 4701 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4702 if (best)
4703 return best->eax & 0xff;
f7a71197 4704not_found:
82725b20
DE		 4705 return 36;
4706}
4707
d8017474
AG		 4708void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4709{
4710 u32 function, index;
4711 struct kvm_cpuid_entry2 *best;
4712
4713 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4714 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4715 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4716 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4717 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4718 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4719 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4720 if (best) {
5fdbf976
MT		 4721 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4722 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4723 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4724 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4725 }
8776e519 4726 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4727 trace_kvm_cpuid(function,
4728 kvm_register_read(vcpu, VCPU_REGS_RAX),
4729 kvm_register_read(vcpu, VCPU_REGS_RBX),
4730 kvm_register_read(vcpu, VCPU_REGS_RCX),
4731 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4732}
4733EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4734
b6c7a5dc
HB		 4735/*
4736 * Check if userspace requested an interrupt window, and that the
4737 * interrupt window is open.
4738 *
4739 * No need to exit to userspace if we already have an interrupt queued.
4740 */
851ba692 4741static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4742{
8061823a 4743 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4744 vcpu->run->request_interrupt_window &&
5df56646 4745 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4746}
4747
851ba692 4748static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4749{
851ba692
AK		 4750 struct kvm_run *kvm_run = vcpu->run;
4751
91586a3b 4752 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4753 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4754 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4755 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4756 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4757 else
b6c7a5dc 4758 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4759 kvm_arch_interrupt_allowed(vcpu) &&
4760 !kvm_cpu_has_interrupt(vcpu) &&
4761 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4762}
4763
b93463aa
AK		 4764static void vapic_enter(struct kvm_vcpu *vcpu)
4765{
4766 struct kvm_lapic *apic = vcpu->arch.apic;
4767 struct page *page;
4768
4769 if (!apic || !apic->vapic_addr)
4770 return;
4771
4772 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4773
4774 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4775}
4776
4777static void vapic_exit(struct kvm_vcpu *vcpu)
4778{
4779 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4780 int idx;
b93463aa
AK		 4781
4782 if (!apic || !apic->vapic_addr)
4783 return;
4784
f656ce01 4785 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4786 kvm_release_page_dirty(apic->vapic_page);
4787 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4788 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4789}
4790
95ba8273
GN		 4791static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4792{
4793 int max_irr, tpr;
4794
4795 if (!kvm_x86_ops->update_cr8_intercept)
4796 return;
4797
88c808fd
AK		 4798 if (!vcpu->arch.apic)
4799 return;
4800
8db3baa2
GN		 4801 if (!vcpu->arch.apic->vapic_addr)
4802 max_irr = kvm_lapic_find_highest_irr(vcpu);
4803 else
4804 max_irr = -1;
95ba8273
GN		 4805
4806 if (max_irr != -1)
4807 max_irr >>= 4;
4808
4809 tpr = kvm_lapic_get_cr8(vcpu);
4810
4811 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4812}
4813
851ba692 4814static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4815{
4816 /* try to reinject previous events if any */
b59bb7bd 4817 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4818 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4819 vcpu->arch.exception.has_error_code,
4820 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4821 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4822 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4823 vcpu->arch.exception.error_code,
4824 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4825 return;
4826 }
4827
95ba8273
GN		 4828 if (vcpu->arch.nmi_injected) {
4829 kvm_x86_ops->set_nmi(vcpu);
4830 return;
4831 }
4832
4833 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4834 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4835 return;
4836 }
4837
4838 /* try to inject new event if pending */
4839 if (vcpu->arch.nmi_pending) {
4840 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4841 vcpu->arch.nmi_pending = false;
4842 vcpu->arch.nmi_injected = true;
4843 kvm_x86_ops->set_nmi(vcpu);
4844 }
4845 } else if (kvm_cpu_has_interrupt(vcpu)) {
4846 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4847 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4848 false);
4849 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4850 }
4851 }
4852}
4853
2acf923e
DC		 4854static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4855{
4856 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4857 !vcpu->guest_xcr0_loaded) {
4858 /* kvm_set_xcr() also depends on this */
4859 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4860 vcpu->guest_xcr0_loaded = 1;
4861 }
4862}
4863
4864static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4865{
4866 if (vcpu->guest_xcr0_loaded) {
4867 if (vcpu->arch.xcr0 != host_xcr0)
4868 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4869 vcpu->guest_xcr0_loaded = 0;
4870 }
4871}
4872
851ba692 4873static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4874{
4875 int r;
6a8b1d13 4876 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4877 vcpu->run->request_interrupt_window;
b6c7a5dc 4878
3e007509 4879 if (vcpu->requests) {
a8eeb04a 4880 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 4881 kvm_mmu_unload(vcpu);
a8eeb04a 4882 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 4883 __kvm_migrate_timers(vcpu);
8cfdc000
ZA		 4884 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
4885 r = kvm_write_guest_time(vcpu);
4886 if (unlikely(r))
4887 goto out;
4888 }
a8eeb04a 4889 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 4890 kvm_mmu_sync_roots(vcpu);
a8eeb04a 4891 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 4892 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 4893 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 4894 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4895 r = 0;
4896 goto out;
4897 }
a8eeb04a 4898 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 4899 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4900 r = 0;
4901 goto out;
4902 }
a8eeb04a 4903 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 4904 vcpu->fpu_active = 0;
4905 kvm_x86_ops->fpu_deactivate(vcpu);
4906 }
2f52d58c 4907 }
b93463aa 4908
3e007509
AK		 4909 r = kvm_mmu_reload(vcpu);
4910 if (unlikely(r))
4911 goto out;
4912
b6c7a5dc
HB		 4913 preempt_disable();
4914
4915 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4916 if (vcpu->fpu_active)
4917 kvm_load_guest_fpu(vcpu);
2acf923e 4918 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 4919
d94e1dc9
AK		 4920 atomic_set(&vcpu->guest_mode, 1);
4921 smp_wmb();
b6c7a5dc 4922
d94e1dc9 4923 local_irq_disable();
32f88400 4924
d94e1dc9
AK		 4925 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4926 || need_resched() || signal_pending(current)) {
4927 atomic_set(&vcpu->guest_mode, 0);
4928 smp_wmb();
6c142801
AK		 4929 local_irq_enable();
4930 preempt_enable();
4931 r = 1;
4932 goto out;
4933 }
4934
851ba692 4935 inject_pending_event(vcpu);
b6c7a5dc 4936
6a8b1d13
GN		 4937 /* enable NMI/IRQ window open exits if needed */
4938 if (vcpu->arch.nmi_pending)
4939 kvm_x86_ops->enable_nmi_window(vcpu);
4940 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4941 kvm_x86_ops->enable_irq_window(vcpu);
4942
95ba8273 4943 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4944 update_cr8_intercept(vcpu);
4945 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4946 }
b93463aa 4947
f656ce01 4948 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4949
b6c7a5dc
HB		 4950 kvm_guest_enter();
4951
42dbaa5a 4952 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4953 set_debugreg(0, 7);
4954 set_debugreg(vcpu->arch.eff_db[0], 0);
4955 set_debugreg(vcpu->arch.eff_db[1], 1);
4956 set_debugreg(vcpu->arch.eff_db[2], 2);
4957 set_debugreg(vcpu->arch.eff_db[3], 3);
4958 }
b6c7a5dc 4959
229456fc 4960 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4961 kvm_x86_ops->run(vcpu);
b6c7a5dc 4962
24f1e32c
FW		 4963 /*
4964 * If the guest has used debug registers, at least dr7
4965 * will be disabled while returning to the host.
4966 * If we don't have active breakpoints in the host, we don't
4967 * care about the messed up debug address registers. But if
4968 * we have some of them active, restore the old state.
4969 */
59d8eb53 4970 if (hw_breakpoint_active())
24f1e32c 4971 hw_breakpoint_restore();
42dbaa5a 4972
1d5f066e
ZA		 4973 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
4974
d94e1dc9
AK		 4975 atomic_set(&vcpu->guest_mode, 0);
4976 smp_wmb();
b6c7a5dc
HB		 4977 local_irq_enable();
4978
4979 ++vcpu->stat.exits;
4980
4981 /*
4982 * We must have an instruction between local_irq_enable() and
4983 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4984 * the interrupt shadow. The stat.exits increment will do nicely.
4985 * But we need to prevent reordering, hence this barrier():
4986 */
4987 barrier();
4988
4989 kvm_guest_exit();
4990
4991 preempt_enable();
4992
f656ce01 4993 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4994
b6c7a5dc
HB		 4995 /*
4996 * Profile KVM exit RIPs:
4997 */
4998 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4999 unsigned long rip = kvm_rip_read(vcpu);
5000 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5001 }
5002
298101da 5003
b93463aa
AK		 5004 kvm_lapic_sync_from_vapic(vcpu);
5005
851ba692 5006 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5007out:
5008 return r;
5009}
b6c7a5dc 5010
09cec754 5011
851ba692 5012static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5013{
5014 int r;
f656ce01 5015 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5016
5017 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5018 pr_debug("vcpu %d received sipi with vector # %x\n",
5019 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5020 kvm_lapic_reset(vcpu);
5f179287 5021 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5022 if (r)
5023 return r;
5024 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5025 }
5026
f656ce01 5027 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5028 vapic_enter(vcpu);
5029
5030 r = 1;
5031 while (r > 0) {
af2152f5 5032 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5033 r = vcpu_enter_guest(vcpu);
d7690175 5034 else {
f656ce01 5035 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5036 kvm_vcpu_block(vcpu);
f656ce01 5037 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5038 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5039 {
5040 switch(vcpu->arch.mp_state) {
5041 case KVM_MP_STATE_HALTED:
d7690175 5042 vcpu->arch.mp_state =
09cec754
GN		 5043 KVM_MP_STATE_RUNNABLE;
5044 case KVM_MP_STATE_RUNNABLE:
5045 break;
5046 case KVM_MP_STATE_SIPI_RECEIVED:
5047 default:
5048 r = -EINTR;
5049 break;
5050 }
5051 }
d7690175
MT		 5052 }
5053
09cec754
GN		 5054 if (r <= 0)
5055 break;
5056
5057 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5058 if (kvm_cpu_has_pending_timer(vcpu))
5059 kvm_inject_pending_timer_irqs(vcpu);
5060
851ba692 5061 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5062 r = -EINTR;
851ba692 5063 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5064 ++vcpu->stat.request_irq_exits;
5065 }
5066 if (signal_pending(current)) {
5067 r = -EINTR;
851ba692 5068 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5069 ++vcpu->stat.signal_exits;
5070 }
5071 if (need_resched()) {
f656ce01 5072 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5073 kvm_resched(vcpu);
f656ce01 5074 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5075 }
b6c7a5dc
HB		 5076 }
5077
f656ce01 5078 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5079
b93463aa
AK		 5080 vapic_exit(vcpu);
5081
b6c7a5dc
HB		 5082 return r;
5083}
5084
5085int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5086{
5087 int r;
5088 sigset_t sigsaved;
5089
ac9f6dc0
AK		 5090 if (vcpu->sigset_active)
5091 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5092
a4535290 5093 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5094 kvm_vcpu_block(vcpu);
d7690175 5095 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5096 r = -EAGAIN;
5097 goto out;
b6c7a5dc
HB		 5098 }
5099
b6c7a5dc
HB		 5100 /* re-sync apic's tpr */
5101 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5102 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5103
d2ddd1c4 5104 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5105 if (vcpu->mmio_needed) {
5106 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5107 vcpu->mmio_read_completed = 1;
5108 vcpu->mmio_needed = 0;
b6c7a5dc 5109 }
f656ce01 5110 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5111 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5112 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5113 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5114 r = 0;
5115 goto out;
5116 }
5117 }
5fdbf976
MT		 5118 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5119 kvm_register_write(vcpu, VCPU_REGS_RAX,
5120 kvm_run->hypercall.ret);
b6c7a5dc 5121
851ba692 5122 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5123
5124out:
f1d86e46 5125 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5126 if (vcpu->sigset_active)
5127 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5128
b6c7a5dc
HB		 5129 return r;
5130}
5131
5132int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5133{
5fdbf976
MT		 5134 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5135 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5136 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5137 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5138 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5139 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5140 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5141 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5142#ifdef CONFIG_X86_64
5fdbf976
MT		 5143 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5144 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5145 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5146 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5147 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5148 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5149 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5150 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5151#endif
5152
5fdbf976 5153 regs->rip = kvm_rip_read(vcpu);
91586a3b 5154 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5155
b6c7a5dc
HB		 5156 return 0;
5157}
5158
5159int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5160{
5fdbf976
MT		 5161 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5162 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5163 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5164 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5165 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5166 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5167 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5168 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5169#ifdef CONFIG_X86_64
5fdbf976
MT		 5170 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5171 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5172 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5173 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5174 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5175 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5176 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5177 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5178#endif
5179
5fdbf976 5180 kvm_rip_write(vcpu, regs->rip);
91586a3b 5181 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5182
b4f14abd
JK		 5183 vcpu->arch.exception.pending = false;
5184
b6c7a5dc
HB		 5185 return 0;
5186}
5187
b6c7a5dc
HB		 5188void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5189{
5190 struct kvm_segment cs;
5191
3e6e0aab 5192 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5193 *db = cs.db;
5194 *l = cs.l;
5195}
5196EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5197
5198int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5199 struct kvm_sregs *sregs)
5200{
89a27f4d 5201 struct desc_ptr dt;
b6c7a5dc 5202
3e6e0aab
GT		 5203 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5204 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5205 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5206 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5207 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5208 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5209
3e6e0aab
GT		 5210 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5211 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5212
5213 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5214 sregs->idt.limit = dt.size;
5215 sregs->idt.base = dt.address;
b6c7a5dc 5216 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5217 sregs->gdt.limit = dt.size;
5218 sregs->gdt.base = dt.address;
b6c7a5dc 5219
4d4ec087 5220 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5221 sregs->cr2 = vcpu->arch.cr2;
5222 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5223 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5224 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5225 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5226 sregs->apic_base = kvm_get_apic_base(vcpu);
5227
923c61bb 5228 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5229
36752c9b 5230 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5231 set_bit(vcpu->arch.interrupt.nr,
5232 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5233
b6c7a5dc
HB		 5234 return 0;
5235}
5236
62d9f0db
MT		 5237int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5238 struct kvm_mp_state *mp_state)
5239{
62d9f0db 5240 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5241 return 0;
5242}
5243
5244int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5245 struct kvm_mp_state *mp_state)
5246{
62d9f0db 5247 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 5248 return 0;
5249}
5250
e269fb21
JK		 5251int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5252 bool has_error_code, u32 error_code)
b6c7a5dc 5253{
4d2179e1 5254 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5255 int ret;
e01c2426 5256
8ec4722d 5257 init_emulate_ctxt(vcpu);
c697518a 5258
9aabc88f 5259 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5260 tss_selector, reason, has_error_code,
5261 error_code);
c697518a 5262
c697518a 5263 if (ret)
19d04437 5264 return EMULATE_FAIL;
37817f29 5265
4d2179e1 5266 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5267 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 5268 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5269 return EMULATE_DONE;
37817f29
IE		 5270}
5271EXPORT_SYMBOL_GPL(kvm_task_switch);
5272
b6c7a5dc
HB		 5273int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5274 struct kvm_sregs *sregs)
5275{
5276 int mmu_reset_needed = 0;
923c61bb 5277 int pending_vec, max_bits;
89a27f4d 5278 struct desc_ptr dt;
b6c7a5dc 5279
89a27f4d
GN		 5280 dt.size = sregs->idt.limit;
5281 dt.address = sregs->idt.base;
b6c7a5dc 5282 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5283 dt.size = sregs->gdt.limit;
5284 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5285 kvm_x86_ops->set_gdt(vcpu, &dt);
5286
ad312c7c
ZX		 5287 vcpu->arch.cr2 = sregs->cr2;
5288 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5289 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5290
2d3ad1f4 5291 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5292
f6801dff 5293 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5294 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5295 kvm_set_apic_base(vcpu, sregs->apic_base);
5296
4d4ec087 5297 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5298 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5299 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5300
fc78f519 5301 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5302 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5303 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5304 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5305 mmu_reset_needed = 1;
5306 }
b6c7a5dc
HB		 5307
5308 if (mmu_reset_needed)
5309 kvm_mmu_reset_context(vcpu);
5310
923c61bb
GN		 5311 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5312 pending_vec = find_first_bit(
5313 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5314 if (pending_vec < max_bits) {
66fd3f7f 5315 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5316 pr_debug("Set back pending irq %d\n", pending_vec);
5317 if (irqchip_in_kernel(vcpu->kvm))
5318 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5319 }
5320
3e6e0aab
GT		 5321 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5322 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5323 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5324 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5325 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5326 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5327
3e6e0aab
GT		 5328 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5329 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5330
5f0269f5
ME		 5331 update_cr8_intercept(vcpu);
5332
9c3e4aab 5333 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5334 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5335 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5336 !is_protmode(vcpu))
9c3e4aab
MT		 5337 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5338
b6c7a5dc
HB		 5339 return 0;
5340}
5341
d0bfb940
JK		 5342int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5343 struct kvm_guest_debug *dbg)
b6c7a5dc 5344{
355be0b9 5345 unsigned long rflags;
ae675ef0 5346 int i, r;
b6c7a5dc 5347
4f926bf2
JK		 5348 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5349 r = -EBUSY;
5350 if (vcpu->arch.exception.pending)
2122ff5e 5351 goto out;
4f926bf2
JK		 5352 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5353 kvm_queue_exception(vcpu, DB_VECTOR);
5354 else
5355 kvm_queue_exception(vcpu, BP_VECTOR);
5356 }
5357
91586a3b
JK		 5358 /*
5359 * Read rflags as long as potentially injected trace flags are still
5360 * filtered out.
5361 */
5362 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5363
5364 vcpu->guest_debug = dbg->control;
5365 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5366 vcpu->guest_debug = 0;
5367
5368 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5369 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5370 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5371 vcpu->arch.switch_db_regs =
5372 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5373 } else {
5374 for (i = 0; i < KVM_NR_DB_REGS; i++)
5375 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5376 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5377 }
5378
f92653ee
JK		 5379 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5380 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5381 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5382
91586a3b
JK		 5383 /*
5384 * Trigger an rflags update that will inject or remove the trace
5385 * flags.
5386 */
5387 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5388
355be0b9 5389 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5390
4f926bf2 5391 r = 0;
d0bfb940 5392
2122ff5e 5393out:
b6c7a5dc
HB		 5394
5395 return r;
5396}
5397
8b006791
ZX		 5398/*
5399 * Translate a guest virtual address to a guest physical address.
5400 */
5401int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5402 struct kvm_translation *tr)
5403{
5404 unsigned long vaddr = tr->linear_address;
5405 gpa_t gpa;
f656ce01 5406 int idx;
8b006791 5407
f656ce01 5408 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5409 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5410 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5411 tr->physical_address = gpa;
5412 tr->valid = gpa != UNMAPPED_GVA;
5413 tr->writeable = 1;
5414 tr->usermode = 0;
8b006791
ZX		 5415
5416 return 0;
5417}
5418
d0752060
HB		 5419int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5420{
98918833
SY		 5421 struct i387_fxsave_struct *fxsave =
5422 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5423
d0752060
HB		 5424 memcpy(fpu->fpr, fxsave->st_space, 128);
5425 fpu->fcw = fxsave->cwd;
5426 fpu->fsw = fxsave->swd;
5427 fpu->ftwx = fxsave->twd;
5428 fpu->last_opcode = fxsave->fop;
5429 fpu->last_ip = fxsave->rip;
5430 fpu->last_dp = fxsave->rdp;
5431 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5432
d0752060
HB		 5433 return 0;
5434}
5435
5436int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5437{
98918833
SY		 5438 struct i387_fxsave_struct *fxsave =
5439 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5440
d0752060
HB		 5441 memcpy(fxsave->st_space, fpu->fpr, 128);
5442 fxsave->cwd = fpu->fcw;
5443 fxsave->swd = fpu->fsw;
5444 fxsave->twd = fpu->ftwx;
5445 fxsave->fop = fpu->last_opcode;
5446 fxsave->rip = fpu->last_ip;
5447 fxsave->rdp = fpu->last_dp;
5448 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5449
d0752060
HB		 5450 return 0;
5451}
5452
10ab25cd 5453int fx_init(struct kvm_vcpu *vcpu)
d0752060 5454{
10ab25cd
JK		 5455 int err;
5456
5457 err = fpu_alloc(&vcpu->arch.guest_fpu);
5458 if (err)
5459 return err;
5460
98918833 5461 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5462
2acf923e
DC		 5463 /*
5464 * Ensure guest xcr0 is valid for loading
5465 */
5466 vcpu->arch.xcr0 = XSTATE_FP;
5467
ad312c7c 5468 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5469
5470 return 0;
d0752060
HB		 5471}
5472EXPORT_SYMBOL_GPL(fx_init);
5473
98918833
SY		 5474static void fx_free(struct kvm_vcpu *vcpu)
5475{
5476 fpu_free(&vcpu->arch.guest_fpu);
5477}
5478
d0752060
HB		 5479void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5480{
2608d7a1 5481 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5482 return;
5483
2acf923e
DC		 5484 /*
5485 * Restore all possible states in the guest,
5486 * and assume host would use all available bits.
5487 * Guest xcr0 would be loaded later.
5488 */
5489 kvm_put_guest_xcr0(vcpu);
d0752060 5490 vcpu->guest_fpu_loaded = 1;
7cf30855 5491 unlazy_fpu(current);
98918833 5492 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5493 trace_kvm_fpu(1);
d0752060 5494}
d0752060
HB		 5495
5496void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5497{
2acf923e
DC		 5498 kvm_put_guest_xcr0(vcpu);
5499
d0752060
HB		 5500 if (!vcpu->guest_fpu_loaded)
5501 return;
5502
5503 vcpu->guest_fpu_loaded = 0;
98918833 5504 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5505 ++vcpu->stat.fpu_reload;
a8eeb04a 5506 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5507 trace_kvm_fpu(0);
d0752060 5508}
e9b11c17
ZX		 5509
5510void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5511{
7f1ea208
JR		 5512 if (vcpu->arch.time_page) {
5513 kvm_release_page_dirty(vcpu->arch.time_page);
5514 vcpu->arch.time_page = NULL;
5515 }
5516
f5f48ee1 5517 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5518 fx_free(vcpu);
e9b11c17
ZX		 5519 kvm_x86_ops->vcpu_free(vcpu);
5520}
5521
5522struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5523 unsigned int id)
5524{
6755bae8
ZA		 5525 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5526 printk_once(KERN_WARNING
5527 "kvm: SMP vm created on host with unstable TSC; "
5528 "guest TSC will not be reliable\n");
26e5215f
AK		 5529 return kvm_x86_ops->vcpu_create(kvm, id);
5530}
e9b11c17 5531
26e5215f
AK		 5532int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5533{
5534 int r;
e9b11c17 5535
0bed3b56 5536 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5537 vcpu_load(vcpu);
5538 r = kvm_arch_vcpu_reset(vcpu);
5539 if (r == 0)
5540 r = kvm_mmu_setup(vcpu);
5541 vcpu_put(vcpu);
5542 if (r < 0)
5543 goto free_vcpu;
5544
26e5215f 5545 return 0;
e9b11c17
ZX		 5546free_vcpu:
5547 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5548 return r;
e9b11c17
ZX		 5549}
5550
d40ccc62 5551void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5552{
5553 vcpu_load(vcpu);
5554 kvm_mmu_unload(vcpu);
5555 vcpu_put(vcpu);
5556
98918833 5557 fx_free(vcpu);
e9b11c17
ZX		 5558 kvm_x86_ops->vcpu_free(vcpu);
5559}
5560
5561int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5562{
448fa4a9
JK		 5563 vcpu->arch.nmi_pending = false;
5564 vcpu->arch.nmi_injected = false;
5565
42dbaa5a
JK		 5566 vcpu->arch.switch_db_regs = 0;
5567 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5568 vcpu->arch.dr6 = DR6_FIXED_1;
5569 vcpu->arch.dr7 = DR7_FIXED_1;
5570
e9b11c17
ZX		 5571 return kvm_x86_ops->vcpu_reset(vcpu);
5572}
5573
10474ae8 5574int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5575{
ca84d1a2
ZA		 5576 struct kvm *kvm;
5577 struct kvm_vcpu *vcpu;
5578 int i;
5579
18863bdd 5580 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5581 list_for_each_entry(kvm, &vm_list, vm_list)
5582 kvm_for_each_vcpu(i, vcpu, kvm)
5583 if (vcpu->cpu == smp_processor_id())
5584 kvm_request_guest_time_update(vcpu);
10474ae8 5585 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5586}
5587
5588void kvm_arch_hardware_disable(void *garbage)
5589{
5590 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5591 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5592}
5593
5594int kvm_arch_hardware_setup(void)
5595{
5596 return kvm_x86_ops->hardware_setup();
5597}
5598
5599void kvm_arch_hardware_unsetup(void)
5600{
5601 kvm_x86_ops->hardware_unsetup();
5602}
5603
5604void kvm_arch_check_processor_compat(void *rtn)
5605{
5606 kvm_x86_ops->check_processor_compatibility(rtn);
5607}
5608
5609int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5610{
5611 struct page *page;
5612 struct kvm *kvm;
5613 int r;
5614
5615 BUG_ON(vcpu->kvm == NULL);
5616 kvm = vcpu->kvm;
5617
9aabc88f 5618 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
ad312c7c 5619 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5620 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5621 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5622 else
a4535290 5623 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5624
5625 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5626 if (!page) {
5627 r = -ENOMEM;
5628 goto fail;
5629 }
ad312c7c 5630 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5631
5632 r = kvm_mmu_create(vcpu);
5633 if (r < 0)
5634 goto fail_free_pio_data;
5635
5636 if (irqchip_in_kernel(kvm)) {
5637 r = kvm_create_lapic(vcpu);
5638 if (r < 0)
5639 goto fail_mmu_destroy;
5640 }
5641
890ca9ae
HY		 5642 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5643 GFP_KERNEL);
5644 if (!vcpu->arch.mce_banks) {
5645 r = -ENOMEM;
443c39bc 5646 goto fail_free_lapic;
890ca9ae
HY		 5647 }
5648 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5649
f5f48ee1
SY		 5650 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5651 goto fail_free_mce_banks;
5652
e9b11c17 5653 return 0;
f5f48ee1
SY		 5654fail_free_mce_banks:
5655 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5656fail_free_lapic:
5657 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5658fail_mmu_destroy:
5659 kvm_mmu_destroy(vcpu);
5660fail_free_pio_data:
ad312c7c 5661 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5662fail:
5663 return r;
5664}
5665
5666void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5667{
f656ce01
MT		 5668 int idx;
5669
36cb93fd 5670 kfree(vcpu->arch.mce_banks);
e9b11c17 5671 kvm_free_lapic(vcpu);
f656ce01 5672 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5673 kvm_mmu_destroy(vcpu);
f656ce01 5674 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5675 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5676}
d19a9cd2
ZX		 5677
5678struct kvm *kvm_arch_create_vm(void)
5679{
5680 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5681
5682 if (!kvm)
5683 return ERR_PTR(-ENOMEM);
5684
f05e70ac 5685 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5686 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5687
5550af4d
SY		 5688 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5689 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5690
99e3e30a
ZA		 5691 spin_lock_init(&kvm->arch.tsc_write_lock);
5692
d19a9cd2
ZX		 5693 return kvm;
5694}
5695
5696static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5697{
5698 vcpu_load(vcpu);
5699 kvm_mmu_unload(vcpu);
5700 vcpu_put(vcpu);
5701}
5702
5703static void kvm_free_vcpus(struct kvm *kvm)
5704{
5705 unsigned int i;
988a2cae 5706 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5707
5708 /*
5709 * Unpin any mmu pages first.
5710 */
988a2cae
GN		 5711 kvm_for_each_vcpu(i, vcpu, kvm)
5712 kvm_unload_vcpu_mmu(vcpu);
5713 kvm_for_each_vcpu(i, vcpu, kvm)
5714 kvm_arch_vcpu_free(vcpu);
5715
5716 mutex_lock(&kvm->lock);
5717 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5718 kvm->vcpus[i] = NULL;
d19a9cd2 5719
988a2cae
GN		 5720 atomic_set(&kvm->online_vcpus, 0);
5721 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5722}
5723
ad8ba2cd
SY		 5724void kvm_arch_sync_events(struct kvm *kvm)
5725{
ba4cef31 5726 kvm_free_all_assigned_devices(kvm);
aea924f6 5727 kvm_free_pit(kvm);
ad8ba2cd
SY		 5728}
5729
d19a9cd2
ZX		 5730void kvm_arch_destroy_vm(struct kvm *kvm)
5731{
6eb55818 5732 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5733 kfree(kvm->arch.vpic);
5734 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5735 kvm_free_vcpus(kvm);
5736 kvm_free_physmem(kvm);
3d45830c
AK		 5737 if (kvm->arch.apic_access_page)
5738 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5739 if (kvm->arch.ept_identity_pagetable)
5740 put_page(kvm->arch.ept_identity_pagetable);
64749204 5741 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5742 kfree(kvm);
5743}
0de10343 5744
f7784b8e
MT		 5745int kvm_arch_prepare_memory_region(struct kvm *kvm,
5746 struct kvm_memory_slot *memslot,
0de10343 5747 struct kvm_memory_slot old,
f7784b8e 5748 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5749 int user_alloc)
5750{
f7784b8e 5751 int npages = memslot->npages;
7ac77099
AK		 5752 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5753
5754 /* Prevent internal slot pages from being moved by fork()/COW. */
5755 if (memslot->id >= KVM_MEMORY_SLOTS)
5756 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5757
5758 /*To keep backward compatibility with older userspace,
5759 *x86 needs to hanlde !user_alloc case.
5760 */
5761 if (!user_alloc) {
5762 if (npages && !old.rmap) {
604b38ac
AA		 5763 unsigned long userspace_addr;
5764
72dc67a6 5765 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5766 userspace_addr = do_mmap(NULL, 0,
5767 npages * PAGE_SIZE,
5768 PROT_READ | PROT_WRITE,
7ac77099 5769 map_flags,
604b38ac 5770 0);
72dc67a6 5771 up_write(&current->mm->mmap_sem);
0de10343 5772
604b38ac
AA		 5773 if (IS_ERR((void *)userspace_addr))
5774 return PTR_ERR((void *)userspace_addr);
5775
604b38ac 5776 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5777 }
5778 }
5779
f7784b8e
MT		 5780
5781 return 0;
5782}
5783
5784void kvm_arch_commit_memory_region(struct kvm *kvm,
5785 struct kvm_userspace_memory_region *mem,
5786 struct kvm_memory_slot old,
5787 int user_alloc)
5788{
5789
5790 int npages = mem->memory_size >> PAGE_SHIFT;
5791
5792 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5793 int ret;
5794
5795 down_write(&current->mm->mmap_sem);
5796 ret = do_munmap(current->mm, old.userspace_addr,
5797 old.npages * PAGE_SIZE);
5798 up_write(&current->mm->mmap_sem);
5799 if (ret < 0)
5800 printk(KERN_WARNING
5801 "kvm_vm_ioctl_set_memory_region: "
5802 "failed to munmap memory\n");
5803 }
5804
7c8a83b7 5805 spin_lock(&kvm->mmu_lock);
f05e70ac 5806 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5807 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5808 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5809 }
5810
5811 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5812 spin_unlock(&kvm->mmu_lock);
0de10343 5813}
1d737c8a 5814
34d4cb8f
MT		 5815void kvm_arch_flush_shadow(struct kvm *kvm)
5816{
5817 kvm_mmu_zap_all(kvm);
8986ecc0 5818 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5819}
5820
1d737c8a
ZX		 5821int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5822{
a4535290 5823 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5824 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5825 || vcpu->arch.nmi_pending ||
5826 (kvm_arch_interrupt_allowed(vcpu) &&
5827 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5828}
5736199a 5829
5736199a
ZX		 5830void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5831{
32f88400
MT		 5832 int me;
5833 int cpu = vcpu->cpu;
5736199a
ZX		 5834
5835 if (waitqueue_active(&vcpu->wq)) {
5836 wake_up_interruptible(&vcpu->wq);
5837 ++vcpu->stat.halt_wakeup;
5838 }
32f88400
MT		 5839
5840 me = get_cpu();
5841 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5842 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5843 smp_send_reschedule(cpu);
e9571ed5 5844 put_cpu();
5736199a 5845}
78646121
GN		 5846
5847int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5848{
5849 return kvm_x86_ops->interrupt_allowed(vcpu);
5850}
229456fc 5851
f92653ee
JK		 5852bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5853{
5854 unsigned long current_rip = kvm_rip_read(vcpu) +
5855 get_segment_base(vcpu, VCPU_SREG_CS);
5856
5857 return current_rip == linear_rip;
5858}
5859EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5860
94fe45da
JK		 5861unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5862{
5863 unsigned long rflags;
5864
5865 rflags = kvm_x86_ops->get_rflags(vcpu);
5866 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5867 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5868 return rflags;
5869}
5870EXPORT_SYMBOL_GPL(kvm_get_rflags);
5871
5872void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5873{
5874 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5875 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5876 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5877 kvm_x86_ops->set_rflags(vcpu, rflags);
5878}
5879EXPORT_SYMBOL_GPL(kvm_set_rflags);
5880
229456fc
MT		 5881EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5882EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5883EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5884EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5885EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5886EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5887EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5888EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5889EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5890EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5891EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5892EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 6.x block layer and io_uring tree(s)