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[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
141
52004014
FW		 142static bool __read_mostly vector_hashing = true;
143module_param(vector_hashing, bool, S_IRUGO);
144
c4ae60e4
LA		 145bool __read_mostly enable_vmware_backdoor = false;
146module_param(enable_vmware_backdoor, bool, S_IRUGO);
147EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
148
6c86eedc
WL		 149static bool __read_mostly force_emulation_prefix = false;
150module_param(force_emulation_prefix, bool, S_IRUGO);
151
18863bdd
AK		 152#define KVM_NR_SHARED_MSRS 16
153
154struct kvm_shared_msrs_global {
155 int nr;
2bf78fa7 156 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 157};
158
159struct kvm_shared_msrs {
160 struct user_return_notifier urn;
161 bool registered;
2bf78fa7
SY		 162 struct kvm_shared_msr_values {
163 u64 host;
164 u64 curr;
165 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 166};
167
168static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 169static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 170
417bc304 171struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 172 { "pf_fixed", VCPU_STAT(pf_fixed) },
173 { "pf_guest", VCPU_STAT(pf_guest) },
174 { "tlb_flush", VCPU_STAT(tlb_flush) },
175 { "invlpg", VCPU_STAT(invlpg) },
176 { "exits", VCPU_STAT(exits) },
177 { "io_exits", VCPU_STAT(io_exits) },
178 { "mmio_exits", VCPU_STAT(mmio_exits) },
179 { "signal_exits", VCPU_STAT(signal_exits) },
180 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 181 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 182 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 183 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 184 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 185 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 186 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 187 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 188 { "request_irq", VCPU_STAT(request_irq_exits) },
189 { "irq_exits", VCPU_STAT(irq_exits) },
190 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 191 { "fpu_reload", VCPU_STAT(fpu_reload) },
192 { "insn_emulation", VCPU_STAT(insn_emulation) },
193 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 194 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 195 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 196 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 197 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
198 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
199 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
200 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
201 { "mmu_flooded", VM_STAT(mmu_flooded) },
202 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 203 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 204 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 205 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 206 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 207 { "max_mmu_page_hash_collisions",
208 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 209 { NULL }
210};
211
2acf923e
DC		 212u64 __read_mostly host_xcr0;
213
b6785def 214static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 215
af585b92
GN		 216static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
217{
218 int i;
219 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
220 vcpu->arch.apf.gfns[i] = ~0;
221}
222
18863bdd
AK		 223static void kvm_on_user_return(struct user_return_notifier *urn)
224{
225 unsigned slot;
18863bdd
AK		 226 struct kvm_shared_msrs *locals
227 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 228 struct kvm_shared_msr_values *values;
1650b4eb
IA		 229 unsigned long flags;
230
231 /*
232 * Disabling irqs at this point since the following code could be
233 * interrupted and executed through kvm_arch_hardware_disable()
234 */
235 local_irq_save(flags);
236 if (locals->registered) {
237 locals->registered = false;
238 user_return_notifier_unregister(urn);
239 }
240 local_irq_restore(flags);
18863bdd 241 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 242 values = &locals->values[slot];
243 if (values->host != values->curr) {
244 wrmsrl(shared_msrs_global.msrs[slot], values->host);
245 values->curr = values->host;
18863bdd
AK		 246 }
247 }
18863bdd
AK		 248}
249
2bf78fa7 250static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 251{
18863bdd 252 u64 value;
013f6a5d
MT		 253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 255
2bf78fa7
SY		 256 /* only read, and nobody should modify it at this time,
257 * so don't need lock */
258 if (slot >= shared_msrs_global.nr) {
259 printk(KERN_ERR "kvm: invalid MSR slot!");
260 return;
261 }
262 rdmsrl_safe(msr, &value);
263 smsr->values[slot].host = value;
264 smsr->values[slot].curr = value;
265}
266
267void kvm_define_shared_msr(unsigned slot, u32 msr)
268{
0123be42 269 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 270 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 271 if (slot >= shared_msrs_global.nr)
272 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 273}
274EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
275
276static void kvm_shared_msr_cpu_online(void)
277{
278 unsigned i;
18863bdd
AK		 279
280 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 281 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 282}
283
8b3c3104 284int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 285{
013f6a5d
MT		 286 unsigned int cpu = smp_processor_id();
287 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 288 int err;
18863bdd 289
2bf78fa7 290 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 291 return 0;
2bf78fa7 292 smsr->values[slot].curr = value;
8b3c3104
AH		 293 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
294 if (err)
295 return 1;
296
18863bdd
AK		 297 if (!smsr->registered) {
298 smsr->urn.on_user_return = kvm_on_user_return;
299 user_return_notifier_register(&smsr->urn);
300 smsr->registered = true;
301 }
8b3c3104 302 return 0;
18863bdd
AK		 303}
304EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
305
13a34e06 306static void drop_user_return_notifiers(void)
3548bab5 307{
013f6a5d
MT		 308 unsigned int cpu = smp_processor_id();
309 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 310
311 if (smsr->registered)
312 kvm_on_user_return(&smsr->urn);
313}
314
6866b83e
CO		 315u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
316{
8a5a87d9 317 return vcpu->arch.apic_base;
6866b83e
CO		 318}
319EXPORT_SYMBOL_GPL(kvm_get_apic_base);
320
58cb628d
JK		 321int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
322{
323 u64 old_state = vcpu->arch.apic_base &
324 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
325 u64 new_state = msr_info->data &
326 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 327 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
328 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 329
d3802286
JM		 330 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
331 return 1;
58cb628d 332 if (!msr_info->host_initiated &&
d3802286 333 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 334 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
335 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
336 old_state == 0)))
337 return 1;
338
339 kvm_lapic_set_base(vcpu, msr_info->data);
340 return 0;
6866b83e
CO		 341}
342EXPORT_SYMBOL_GPL(kvm_set_apic_base);
343
2605fc21 344asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 345{
346 /* Fault while not rebooting. We want the trace. */
347 BUG();
348}
349EXPORT_SYMBOL_GPL(kvm_spurious_fault);
350
3fd28fce
ED		 351#define EXCPT_BENIGN 0
352#define EXCPT_CONTRIBUTORY 1
353#define EXCPT_PF 2
354
355static int exception_class(int vector)
356{
357 switch (vector) {
358 case PF_VECTOR:
359 return EXCPT_PF;
360 case DE_VECTOR:
361 case TS_VECTOR:
362 case NP_VECTOR:
363 case SS_VECTOR:
364 case GP_VECTOR:
365 return EXCPT_CONTRIBUTORY;
366 default:
367 break;
368 }
369 return EXCPT_BENIGN;
370}
371
d6e8c854
NA		 372#define EXCPT_FAULT 0
373#define EXCPT_TRAP 1
374#define EXCPT_ABORT 2
375#define EXCPT_INTERRUPT 3
376
377static int exception_type(int vector)
378{
379 unsigned int mask;
380
381 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
382 return EXCPT_INTERRUPT;
383
384 mask = 1 << vector;
385
386 /* #DB is trap, as instruction watchpoints are handled elsewhere */
387 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
388 return EXCPT_TRAP;
389
390 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
391 return EXCPT_ABORT;
392
393 /* Reserved exceptions will result in fault */
394 return EXCPT_FAULT;
395}
396
3fd28fce 397static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 398 unsigned nr, bool has_error, u32 error_code,
399 bool reinject)
3fd28fce
ED		 400{
401 u32 prev_nr;
402 int class1, class2;
403
3842d135
AK		 404 kvm_make_request(KVM_REQ_EVENT, vcpu);
405
664f8e26 406 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 407 queue:
3ffb2468
NA		 408 if (has_error && !is_protmode(vcpu))
409 has_error = false;
664f8e26
WL		 410 if (reinject) {
411 /*
412 * On vmentry, vcpu->arch.exception.pending is only
413 * true if an event injection was blocked by
414 * nested_run_pending. In that case, however,
415 * vcpu_enter_guest requests an immediate exit,
416 * and the guest shouldn't proceed far enough to
417 * need reinjection.
418 */
419 WARN_ON_ONCE(vcpu->arch.exception.pending);
420 vcpu->arch.exception.injected = true;
421 } else {
422 vcpu->arch.exception.pending = true;
423 vcpu->arch.exception.injected = false;
424 }
3fd28fce
ED		 425 vcpu->arch.exception.has_error_code = has_error;
426 vcpu->arch.exception.nr = nr;
427 vcpu->arch.exception.error_code = error_code;
428 return;
429 }
430
431 /* to check exception */
432 prev_nr = vcpu->arch.exception.nr;
433 if (prev_nr == DF_VECTOR) {
434 /* triple fault -> shutdown */
a8eeb04a 435 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 436 return;
437 }
438 class1 = exception_class(prev_nr);
439 class2 = exception_class(nr);
440 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
441 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 442 /*
443 * Generate double fault per SDM Table 5-5. Set
444 * exception.pending = true so that the double fault
445 * can trigger a nested vmexit.
446 */
3fd28fce 447 vcpu->arch.exception.pending = true;
664f8e26 448 vcpu->arch.exception.injected = false;
3fd28fce
ED		 449 vcpu->arch.exception.has_error_code = true;
450 vcpu->arch.exception.nr = DF_VECTOR;
451 vcpu->arch.exception.error_code = 0;
452 } else
453 /* replace previous exception with a new one in a hope
454 that instruction re-execution will regenerate lost
455 exception */
456 goto queue;
457}
458
298101da
AK		 459void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
460{
ce7ddec4 461 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 462}
463EXPORT_SYMBOL_GPL(kvm_queue_exception);
464
ce7ddec4
JR		 465void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
466{
467 kvm_multiple_exception(vcpu, nr, false, 0, true);
468}
469EXPORT_SYMBOL_GPL(kvm_requeue_exception);
470
6affcbed 471int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 472{
db8fcefa
AP		 473 if (err)
474 kvm_inject_gp(vcpu, 0);
475 else
6affcbed
KH		 476 return kvm_skip_emulated_instruction(vcpu);
477
478 return 1;
db8fcefa
AP		 479}
480EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 481
6389ee94 482void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 483{
484 ++vcpu->stat.pf_guest;
adfe20fb
WL		 485 vcpu->arch.exception.nested_apf =
486 is_guest_mode(vcpu) && fault->async_page_fault;
487 if (vcpu->arch.exception.nested_apf)
488 vcpu->arch.apf.nested_apf_token = fault->address;
489 else
490 vcpu->arch.cr2 = fault->address;
6389ee94 491 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 492}
27d6c865 493EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 494
ef54bcfe 495static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 496{
6389ee94
AK		 497 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
498 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 499 else
6389ee94 500 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 501
502 return fault->nested_page_fault;
d4f8cf66
JR		 503}
504
3419ffc8
SY		 505void kvm_inject_nmi(struct kvm_vcpu *vcpu)
506{
7460fb4a
AK		 507 atomic_inc(&vcpu->arch.nmi_queued);
508 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 509}
510EXPORT_SYMBOL_GPL(kvm_inject_nmi);
511
298101da
AK		 512void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
513{
ce7ddec4 514 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 515}
516EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
517
ce7ddec4
JR		 518void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
519{
520 kvm_multiple_exception(vcpu, nr, true, error_code, true);
521}
522EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
523
0a79b009
AK		 524/*
525 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
526 * a #GP and return false.
527 */
528bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 529{
0a79b009
AK		 530 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
531 return true;
532 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
533 return false;
298101da 534}
0a79b009 535EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 536
16f8a6f9
NA		 537bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
538{
539 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
540 return true;
541
542 kvm_queue_exception(vcpu, UD_VECTOR);
543 return false;
544}
545EXPORT_SYMBOL_GPL(kvm_require_dr);
546
ec92fe44
JR		 547/*
548 * This function will be used to read from the physical memory of the currently
54bf36aa 549 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 550 * can read from guest physical or from the guest's guest physical memory.
551 */
552int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
553 gfn_t ngfn, void *data, int offset, int len,
554 u32 access)
555{
54987b7a 556 struct x86_exception exception;
ec92fe44
JR		 557 gfn_t real_gfn;
558 gpa_t ngpa;
559
560 ngpa = gfn_to_gpa(ngfn);
54987b7a 561 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 562 if (real_gfn == UNMAPPED_GVA)
563 return -EFAULT;
564
565 real_gfn = gpa_to_gfn(real_gfn);
566
54bf36aa 567 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 568}
569EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
570
69b0049a 571static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 572 void *data, int offset, int len, u32 access)
573{
574 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
575 data, offset, len, access);
576}
577
a03490ed
CO		 578/*
579 * Load the pae pdptrs. Return true is they are all valid.
580 */
ff03a073 581int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 582{
583 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
584 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
585 int i;
586 int ret;
ff03a073 587 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 588
ff03a073
JR		 589 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
590 offset * sizeof(u64), sizeof(pdpte),
591 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 592 if (ret < 0) {
593 ret = 0;
594 goto out;
595 }
596 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 597 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 598 (pdpte[i] &
599 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 600 ret = 0;
601 goto out;
602 }
603 }
604 ret = 1;
605
ff03a073 606 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 607 __set_bit(VCPU_EXREG_PDPTR,
608 (unsigned long *)&vcpu->arch.regs_avail);
609 __set_bit(VCPU_EXREG_PDPTR,
610 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 611out:
a03490ed
CO		 612
613 return ret;
614}
cc4b6871 615EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 616
9ed38ffa 617bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 618{
ff03a073 619 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 620 bool changed = true;
3d06b8bf
JR		 621 int offset;
622 gfn_t gfn;
d835dfec
AK		 623 int r;
624
625 if (is_long_mode(vcpu) || !is_pae(vcpu))
626 return false;
627
6de4f3ad
AK		 628 if (!test_bit(VCPU_EXREG_PDPTR,
629 (unsigned long *)&vcpu->arch.regs_avail))
630 return true;
631
a512177e
PB		 632 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
633 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 634 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
635 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 636 if (r < 0)
637 goto out;
ff03a073 638 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 639out:
d835dfec
AK		 640
641 return changed;
642}
9ed38ffa 643EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 644
49a9b07e 645int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 646{
aad82703 647 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 648 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 649
f9a48e6a
AK		 650 cr0 |= X86_CR0_ET;
651
ab344828 652#ifdef CONFIG_X86_64
0f12244f
GN		 653 if (cr0 & 0xffffffff00000000UL)
654 return 1;
ab344828
GN		 655#endif
656
657 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 658
0f12244f
GN		 659 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
660 return 1;
a03490ed 661
0f12244f
GN		 662 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
663 return 1;
a03490ed
CO		 664
665 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
666#ifdef CONFIG_X86_64
f6801dff 667 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 668 int cs_db, cs_l;
669
0f12244f
GN		 670 if (!is_pae(vcpu))
671 return 1;
a03490ed 672 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 673 if (cs_l)
674 return 1;
a03490ed
CO		 675 } else
676#endif
ff03a073 677 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 678 kvm_read_cr3(vcpu)))
0f12244f 679 return 1;
a03490ed
CO		 680 }
681
ad756a16
MJ		 682 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
683 return 1;
684
a03490ed 685 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 686
d170c419 687 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 688 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 689 kvm_async_pf_hash_reset(vcpu);
690 }
e5f3f027 691
aad82703
SY		 692 if ((cr0 ^ old_cr0) & update_bits)
693 kvm_mmu_reset_context(vcpu);
b18d5431 694
879ae188
LE		 695 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
696 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
697 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 698 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
699
0f12244f
GN		 700 return 0;
701}
2d3ad1f4 702EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 703
2d3ad1f4 704void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 705{
49a9b07e 706 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 707}
2d3ad1f4 708EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 709
42bdf991
MT		 710static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
711{
712 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
713 !vcpu->guest_xcr0_loaded) {
714 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 715 if (vcpu->arch.xcr0 != host_xcr0)
716 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 717 vcpu->guest_xcr0_loaded = 1;
718 }
719}
720
721static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
722{
723 if (vcpu->guest_xcr0_loaded) {
724 if (vcpu->arch.xcr0 != host_xcr0)
725 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
726 vcpu->guest_xcr0_loaded = 0;
727 }
728}
729
69b0049a 730static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 731{
56c103ec
LJ		 732 u64 xcr0 = xcr;
733 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 734 u64 valid_bits;
2acf923e
DC		 735
736 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
737 if (index != XCR_XFEATURE_ENABLED_MASK)
738 return 1;
d91cab78 739 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 740 return 1;
d91cab78 741 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 742 return 1;
46c34cb0
PB		 743
744 /*
745 * Do not allow the guest to set bits that we do not support
746 * saving. However, xcr0 bit 0 is always set, even if the
747 * emulated CPU does not support XSAVE (see fx_init).
748 */
d91cab78 749 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 750 if (xcr0 & ~valid_bits)
2acf923e 751 return 1;
46c34cb0 752
d91cab78
DH		 753 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
754 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 755 return 1;
756
d91cab78
DH		 757 if (xcr0 & XFEATURE_MASK_AVX512) {
758 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 759 return 1;
d91cab78 760 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 761 return 1;
762 }
2acf923e 763 vcpu->arch.xcr0 = xcr0;
56c103ec 764
d91cab78 765 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 766 kvm_update_cpuid(vcpu);
2acf923e
DC		 767 return 0;
768}
769
770int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
771{
764bcbc5
Z		 772 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
773 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 774 kvm_inject_gp(vcpu, 0);
775 return 1;
776 }
777 return 0;
778}
779EXPORT_SYMBOL_GPL(kvm_set_xcr);
780
a83b29c6 781int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 782{
fc78f519 783 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 784 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 785 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 786
0f12244f
GN		 787 if (cr4 & CR4_RESERVED_BITS)
788 return 1;
a03490ed 789
d6321d49 790 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 791 return 1;
792
d6321d49 793 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 794 return 1;
795
d6321d49 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 797 return 1;
798
d6321d49 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 800 return 1;
801
d6321d49 802 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 803 return 1;
804
fd8cb433 805 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 806 return 1;
807
ae3e61e1
PB		 808 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
809 return 1;
810
a03490ed 811 if (is_long_mode(vcpu)) {
0f12244f
GN		 812 if (!(cr4 & X86_CR4_PAE))
813 return 1;
a2edf57f
AK		 814 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
815 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 816 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
817 kvm_read_cr3(vcpu)))
0f12244f
GN		 818 return 1;
819
ad756a16 820 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 821 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 822 return 1;
823
824 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
825 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
826 return 1;
827 }
828
5e1746d6 829 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 830 return 1;
a03490ed 831
ad756a16
MJ		 832 if (((cr4 ^ old_cr4) & pdptr_bits) ||
833 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 834 kvm_mmu_reset_context(vcpu);
0f12244f 835
b9baba86 836 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 837 kvm_update_cpuid(vcpu);
2acf923e 838
0f12244f
GN		 839 return 0;
840}
2d3ad1f4 841EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 842
2390218b 843int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 844{
ac146235 845#ifdef CONFIG_X86_64
c19986fe
JS		 846 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
847
848 if (pcid_enabled)
849 cr3 &= ~CR3_PCID_INVD;
ac146235 850#endif
9d88fca7 851
9f8fe504 852 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 853 kvm_mmu_sync_roots(vcpu);
77c3913b 854 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 855 return 0;
d835dfec
AK		 856 }
857
d1cd3ce9
YZ		 858 if (is_long_mode(vcpu) &&
859 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
860 return 1;
861 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 862 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 863 return 1;
a03490ed 864
0f12244f 865 vcpu->arch.cr3 = cr3;
aff48baa 866 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 867 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 868 return 0;
869}
2d3ad1f4 870EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 871
eea1cff9 872int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 873{
0f12244f
GN		 874 if (cr8 & CR8_RESERVED_BITS)
875 return 1;
35754c98 876 if (lapic_in_kernel(vcpu))
a03490ed
CO		 877 kvm_lapic_set_tpr(vcpu, cr8);
878 else
ad312c7c 879 vcpu->arch.cr8 = cr8;
0f12244f
GN		 880 return 0;
881}
2d3ad1f4 882EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 883
2d3ad1f4 884unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 885{
35754c98 886 if (lapic_in_kernel(vcpu))
a03490ed
CO		 887 return kvm_lapic_get_cr8(vcpu);
888 else
ad312c7c 889 return vcpu->arch.cr8;
a03490ed 890}
2d3ad1f4 891EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 892
ae561ede
NA		 893static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
894{
895 int i;
896
897 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
898 for (i = 0; i < KVM_NR_DB_REGS; i++)
899 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
900 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
901 }
902}
903
73aaf249
JK		 904static void kvm_update_dr6(struct kvm_vcpu *vcpu)
905{
906 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
907 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
908}
909
c8639010
JK		 910static void kvm_update_dr7(struct kvm_vcpu *vcpu)
911{
912 unsigned long dr7;
913
914 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
915 dr7 = vcpu->arch.guest_debug_dr7;
916 else
917 dr7 = vcpu->arch.dr7;
918 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 919 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
920 if (dr7 & DR7_BP_EN_MASK)
921 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 922}
923
6f43ed01
NA		 924static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
925{
926 u64 fixed = DR6_FIXED_1;
927
d6321d49 928 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 929 fixed |= DR6_RTM;
930 return fixed;
931}
932
338dbc97 933static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 934{
935 switch (dr) {
936 case 0 ... 3:
937 vcpu->arch.db[dr] = val;
938 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
939 vcpu->arch.eff_db[dr] = val;
940 break;
941 case 4:
020df079
GN		 942 /* fall through */
943 case 6:
338dbc97
GN		 944 if (val & 0xffffffff00000000ULL)
945 return -1; /* #GP */
6f43ed01 946 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 947 kvm_update_dr6(vcpu);
020df079
GN		 948 break;
949 case 5:
020df079
GN		 950 /* fall through */
951 default: /* 7 */
338dbc97
GN		 952 if (val & 0xffffffff00000000ULL)
953 return -1; /* #GP */
020df079 954 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 955 kvm_update_dr7(vcpu);
020df079
GN		 956 break;
957 }
958
959 return 0;
960}
338dbc97
GN		 961
962int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
963{
16f8a6f9 964 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 965 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 966 return 1;
967 }
968 return 0;
338dbc97 969}
020df079
GN		 970EXPORT_SYMBOL_GPL(kvm_set_dr);
971
16f8a6f9 972int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 973{
974 switch (dr) {
975 case 0 ... 3:
976 *val = vcpu->arch.db[dr];
977 break;
978 case 4:
020df079
GN		 979 /* fall through */
980 case 6:
73aaf249
JK		 981 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
982 *val = vcpu->arch.dr6;
983 else
984 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 985 break;
986 case 5:
020df079
GN		 987 /* fall through */
988 default: /* 7 */
989 *val = vcpu->arch.dr7;
990 break;
991 }
338dbc97
GN		 992 return 0;
993}
020df079
GN		 994EXPORT_SYMBOL_GPL(kvm_get_dr);
995
022cd0e8
AK		 996bool kvm_rdpmc(struct kvm_vcpu *vcpu)
997{
998 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
999 u64 data;
1000 int err;
1001
c6702c9d 1002 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1003 if (err)
1004 return err;
1005 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1006 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1007 return err;
1008}
1009EXPORT_SYMBOL_GPL(kvm_rdpmc);
1010
043405e1
CO		 1011/*
1012 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1013 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1014 *
1015 * This list is modified at module load time to reflect the
e3267cbb 1016 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1017 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1018 * may depend on host virtualization features rather than host cpu features.
043405e1 1019 */
e3267cbb 1020
043405e1
CO		 1021static u32 msrs_to_save[] = {
1022 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1023 MSR_STAR,
043405e1
CO		 1024#ifdef CONFIG_X86_64
1025 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1026#endif
b3897a49 1027 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1028 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1029 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1030};
1031
1032static unsigned num_msrs_to_save;
1033
62ef68bb
PB		 1034static u32 emulated_msrs[] = {
1035 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1036 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1037 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1038 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1039 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1040 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1041 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1042 HV_X64_MSR_RESET,
11c4b1ca 1043 HV_X64_MSR_VP_INDEX,
9eec50b8 1044 HV_X64_MSR_VP_RUNTIME,
5c919412 1045 HV_X64_MSR_SCONTROL,
1f4b34f8 1046 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1047 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1048 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1049 HV_X64_MSR_TSC_EMULATION_STATUS,
1050
1051 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1052 MSR_KVM_PV_EOI_EN,
1053
ba904635 1054 MSR_IA32_TSC_ADJUST,
a3e06bbe 1055 MSR_IA32_TSCDEADLINE,
043405e1 1056 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1057 MSR_IA32_MCG_STATUS,
1058 MSR_IA32_MCG_CTL,
c45dcc71 1059 MSR_IA32_MCG_EXT_CTL,
64d60670 1060 MSR_IA32_SMBASE,
52797bf9 1061 MSR_SMI_COUNT,
db2336a8
KH		 1062 MSR_PLATFORM_INFO,
1063 MSR_MISC_FEATURES_ENABLES,
bc226f07 1064 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1065};
1066
62ef68bb
PB		 1067static unsigned num_emulated_msrs;
1068
801e459a
TL		 1069/*
1070 * List of msr numbers which are used to expose MSR-based features that
1071 * can be used by a hypervisor to validate requested CPU features.
1072 */
1073static u32 msr_based_features[] = {
1389309c
PB		 1074 MSR_IA32_VMX_BASIC,
1075 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1076 MSR_IA32_VMX_PINBASED_CTLS,
1077 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1078 MSR_IA32_VMX_PROCBASED_CTLS,
1079 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1080 MSR_IA32_VMX_EXIT_CTLS,
1081 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1082 MSR_IA32_VMX_ENTRY_CTLS,
1083 MSR_IA32_VMX_MISC,
1084 MSR_IA32_VMX_CR0_FIXED0,
1085 MSR_IA32_VMX_CR0_FIXED1,
1086 MSR_IA32_VMX_CR4_FIXED0,
1087 MSR_IA32_VMX_CR4_FIXED1,
1088 MSR_IA32_VMX_VMCS_ENUM,
1089 MSR_IA32_VMX_PROCBASED_CTLS2,
1090 MSR_IA32_VMX_EPT_VPID_CAP,
1091 MSR_IA32_VMX_VMFUNC,
1092
d1d93fa9 1093 MSR_F10H_DECFG,
518e7b94 1094 MSR_IA32_UCODE_REV,
801e459a
TL		 1095};
1096
1097static unsigned int num_msr_based_features;
1098
66421c1e
WL		 1099static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1100{
1101 switch (msr->index) {
518e7b94
WL		 1102 case MSR_IA32_UCODE_REV:
1103 rdmsrl(msr->index, msr->data);
1104 break;
66421c1e
WL		 1105 default:
1106 if (kvm_x86_ops->get_msr_feature(msr))
1107 return 1;
1108 }
1109 return 0;
1110}
1111
801e459a
TL		 1112static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1113{
1114 struct kvm_msr_entry msr;
66421c1e 1115 int r;
801e459a
TL		 1116
1117 msr.index = index;
66421c1e
WL		 1118 r = kvm_get_msr_feature(&msr);
1119 if (r)
1120 return r;
801e459a
TL		 1121
1122 *data = msr.data;
1123
1124 return 0;
1125}
1126
384bb783 1127bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1128{
b69e8cae 1129 if (efer & efer_reserved_bits)
384bb783 1130 return false;
15c4a640 1131
1b4d56b8 1132 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1133 return false;
1b2fd70c 1134
1b4d56b8 1135 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1136 return false;
d8017474 1137
384bb783
JK		 1138 return true;
1139}
1140EXPORT_SYMBOL_GPL(kvm_valid_efer);
1141
1142static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1143{
1144 u64 old_efer = vcpu->arch.efer;
1145
1146 if (!kvm_valid_efer(vcpu, efer))
1147 return 1;
1148
1149 if (is_paging(vcpu)
1150 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1151 return 1;
1152
15c4a640 1153 efer &= ~EFER_LMA;
f6801dff 1154 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1155
a3d204e2
SY		 1156 kvm_x86_ops->set_efer(vcpu, efer);
1157
aad82703
SY		 1158 /* Update reserved bits */
1159 if ((efer ^ old_efer) & EFER_NX)
1160 kvm_mmu_reset_context(vcpu);
1161
b69e8cae 1162 return 0;
15c4a640
CO		 1163}
1164
f2b4b7dd
JR		 1165void kvm_enable_efer_bits(u64 mask)
1166{
1167 efer_reserved_bits &= ~mask;
1168}
1169EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1170
15c4a640
CO		 1171/*
1172 * Writes msr value into into the appropriate "register".
1173 * Returns 0 on success, non-0 otherwise.
1174 * Assumes vcpu_load() was already called.
1175 */
8fe8ab46 1176int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1177{
854e8bb1
NA		 1178 switch (msr->index) {
1179 case MSR_FS_BASE:
1180 case MSR_GS_BASE:
1181 case MSR_KERNEL_GS_BASE:
1182 case MSR_CSTAR:
1183 case MSR_LSTAR:
fd8cb433 1184 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1185 return 1;
1186 break;
1187 case MSR_IA32_SYSENTER_EIP:
1188 case MSR_IA32_SYSENTER_ESP:
1189 /*
1190 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1191 * non-canonical address is written on Intel but not on
1192 * AMD (which ignores the top 32-bits, because it does
1193 * not implement 64-bit SYSENTER).
1194 *
1195 * 64-bit code should hence be able to write a non-canonical
1196 * value on AMD. Making the address canonical ensures that
1197 * vmentry does not fail on Intel after writing a non-canonical
1198 * value, and that something deterministic happens if the guest
1199 * invokes 64-bit SYSENTER.
1200 */
fd8cb433 1201 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1202 }
8fe8ab46 1203 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1204}
854e8bb1 1205EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1206
313a3dc7
CO		 1207/*
1208 * Adapt set_msr() to msr_io()'s calling convention
1209 */
609e36d3
PB		 1210static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1211{
1212 struct msr_data msr;
1213 int r;
1214
1215 msr.index = index;
1216 msr.host_initiated = true;
1217 r = kvm_get_msr(vcpu, &msr);
1218 if (r)
1219 return r;
1220
1221 *data = msr.data;
1222 return 0;
1223}
1224
313a3dc7
CO		 1225static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1226{
8fe8ab46
WA		 1227 struct msr_data msr;
1228
1229 msr.data = *data;
1230 msr.index = index;
1231 msr.host_initiated = true;
1232 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1233}
1234
16e8d74d
MT		 1235#ifdef CONFIG_X86_64
1236struct pvclock_gtod_data {
1237 seqcount_t seq;
1238
1239 struct { /* extract of a clocksource struct */
1240 int vclock_mode;
a5a1d1c2
TG		 1241 u64 cycle_last;
1242 u64 mask;
16e8d74d
MT		 1243 u32 mult;
1244 u32 shift;
1245 } clock;
1246
cbcf2dd3
TG		 1247 u64 boot_ns;
1248 u64 nsec_base;
55dd00a7 1249 u64 wall_time_sec;
16e8d74d
MT		 1250};
1251
1252static struct pvclock_gtod_data pvclock_gtod_data;
1253
1254static void update_pvclock_gtod(struct timekeeper *tk)
1255{
1256 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1257 u64 boot_ns;
1258
876e7881 1259 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1260
1261 write_seqcount_begin(&vdata->seq);
1262
1263 /* copy pvclock gtod data */
876e7881
PZ		 1264 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1265 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1266 vdata->clock.mask = tk->tkr_mono.mask;
1267 vdata->clock.mult = tk->tkr_mono.mult;
1268 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1269
cbcf2dd3 1270 vdata->boot_ns = boot_ns;
876e7881 1271 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1272
55dd00a7
MT		 1273 vdata->wall_time_sec = tk->xtime_sec;
1274
16e8d74d
MT		 1275 write_seqcount_end(&vdata->seq);
1276}
1277#endif
1278
bab5bb39
NK		 1279void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1280{
1281 /*
1282 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1283 * vcpu_enter_guest. This function is only called from
1284 * the physical CPU that is running vcpu.
1285 */
1286 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1287}
16e8d74d 1288
18068523
GOC		 1289static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1290{
9ed3c444
AK		 1291 int version;
1292 int r;
50d0a0f9 1293 struct pvclock_wall_clock wc;
87aeb54f 1294 struct timespec64 boot;
18068523
GOC		 1295
1296 if (!wall_clock)
1297 return;
1298
9ed3c444
AK		 1299 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1300 if (r)
1301 return;
1302
1303 if (version & 1)
1304 ++version; /* first time write, random junk */
1305
1306 ++version;
18068523 1307
1dab1345
NK		 1308 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1309 return;
18068523 1310
50d0a0f9
GH		 1311 /*
1312 * The guest calculates current wall clock time by adding
34c238a1 1313 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1314 * wall clock specified here. guest system time equals host
1315 * system time for us, thus we must fill in host boot time here.
1316 */
87aeb54f 1317 getboottime64(&boot);
50d0a0f9 1318
4b648665 1319 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1320 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1321 boot = timespec64_sub(boot, ts);
4b648665 1322 }
87aeb54f 1323 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1324 wc.nsec = boot.tv_nsec;
1325 wc.version = version;
18068523
GOC		 1326
1327 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1328
1329 version++;
1330 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1331}
1332
50d0a0f9
GH		 1333static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1334{
b51012de
PB		 1335 do_shl32_div32(dividend, divisor);
1336 return dividend;
50d0a0f9
GH		 1337}
1338
3ae13faa 1339static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1340 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1341{
5f4e3f88 1342 uint64_t scaled64;
50d0a0f9
GH		 1343 int32_t shift = 0;
1344 uint64_t tps64;
1345 uint32_t tps32;
1346
3ae13faa
PB		 1347 tps64 = base_hz;
1348 scaled64 = scaled_hz;
50933623 1349 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1350 tps64 >>= 1;
1351 shift--;
1352 }
1353
1354 tps32 = (uint32_t)tps64;
50933623
JK		 1355 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1356 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1357 scaled64 >>= 1;
1358 else
1359 tps32 <<= 1;
50d0a0f9
GH		 1360 shift++;
1361 }
1362
5f4e3f88
ZA		 1363 *pshift = shift;
1364 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1365
3ae13faa
PB		 1366 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1367 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1368}
1369
d828199e 1370#ifdef CONFIG_X86_64
16e8d74d 1371static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1372#endif
16e8d74d 1373
c8076604 1374static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1375static unsigned long max_tsc_khz;
c8076604 1376
cc578287 1377static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1378{
cc578287
ZA		 1379 u64 v = (u64)khz * (1000000 + ppm);
1380 do_div(v, 1000000);
1381 return v;
1e993611
JR		 1382}
1383
381d585c
HZ		 1384static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1385{
1386 u64 ratio;
1387
1388 /* Guest TSC same frequency as host TSC? */
1389 if (!scale) {
1390 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1391 return 0;
1392 }
1393
1394 /* TSC scaling supported? */
1395 if (!kvm_has_tsc_control) {
1396 if (user_tsc_khz > tsc_khz) {
1397 vcpu->arch.tsc_catchup = 1;
1398 vcpu->arch.tsc_always_catchup = 1;
1399 return 0;
1400 } else {
1401 WARN(1, "user requested TSC rate below hardware speed\n");
1402 return -1;
1403 }
1404 }
1405
1406 /* TSC scaling required - calculate ratio */
1407 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1408 user_tsc_khz, tsc_khz);
1409
1410 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1411 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1412 user_tsc_khz);
1413 return -1;
1414 }
1415
1416 vcpu->arch.tsc_scaling_ratio = ratio;
1417 return 0;
1418}
1419
4941b8cb 1420static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1421{
cc578287
ZA		 1422 u32 thresh_lo, thresh_hi;
1423 int use_scaling = 0;
217fc9cf 1424
03ba32ca 1425 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1426 if (user_tsc_khz == 0) {
ad721883
HZ		 1427 /* set tsc_scaling_ratio to a safe value */
1428 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1429 return -1;
ad721883 1430 }
03ba32ca 1431
c285545f 1432 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1433 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1434 &vcpu->arch.virtual_tsc_shift,
1435 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1436 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1437
1438 /*
1439 * Compute the variation in TSC rate which is acceptable
1440 * within the range of tolerance and decide if the
1441 * rate being applied is within that bounds of the hardware
1442 * rate. If so, no scaling or compensation need be done.
1443 */
1444 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1445 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1446 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1447 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1448 use_scaling = 1;
1449 }
4941b8cb 1450 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1451}
1452
1453static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1454{
e26101b1 1455 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1456 vcpu->arch.virtual_tsc_mult,
1457 vcpu->arch.virtual_tsc_shift);
e26101b1 1458 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1459 return tsc;
1460}
1461
b0c39dc6
VK		 1462static inline int gtod_is_based_on_tsc(int mode)
1463{
1464 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1465}
1466
69b0049a 1467static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1468{
1469#ifdef CONFIG_X86_64
1470 bool vcpus_matched;
b48aa97e
MT		 1471 struct kvm_arch *ka = &vcpu->kvm->arch;
1472 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1473
1474 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1475 atomic_read(&vcpu->kvm->online_vcpus));
1476
7f187922
MT		 1477 /*
1478 * Once the masterclock is enabled, always perform request in
1479 * order to update it.
1480 *
1481 * In order to enable masterclock, the host clocksource must be TSC
1482 * and the vcpus need to have matched TSCs. When that happens,
1483 * perform request to enable masterclock.
1484 */
1485 if (ka->use_master_clock ||
b0c39dc6 1486 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1487 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1488
1489 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1490 atomic_read(&vcpu->kvm->online_vcpus),
1491 ka->use_master_clock, gtod->clock.vclock_mode);
1492#endif
1493}
1494
ba904635
WA		 1495static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1496{
e79f245d 1497 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1498 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1499}
1500
35181e86
HZ		 1501/*
1502 * Multiply tsc by a fixed point number represented by ratio.
1503 *
1504 * The most significant 64-N bits (mult) of ratio represent the
1505 * integral part of the fixed point number; the remaining N bits
1506 * (frac) represent the fractional part, ie. ratio represents a fixed
1507 * point number (mult + frac * 2^(-N)).
1508 *
1509 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1510 */
1511static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1512{
1513 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1514}
1515
1516u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1517{
1518 u64 _tsc = tsc;
1519 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1520
1521 if (ratio != kvm_default_tsc_scaling_ratio)
1522 _tsc = __scale_tsc(ratio, tsc);
1523
1524 return _tsc;
1525}
1526EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1527
07c1419a
HZ		 1528static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1529{
1530 u64 tsc;
1531
1532 tsc = kvm_scale_tsc(vcpu, rdtsc());
1533
1534 return target_tsc - tsc;
1535}
1536
4ba76538
HZ		 1537u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1538{
e79f245d
KA		 1539 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1540
1541 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1542}
1543EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1544
a545ab6a
LC		 1545static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1546{
1547 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1548 vcpu->arch.tsc_offset = offset;
1549}
1550
b0c39dc6
VK		 1551static inline bool kvm_check_tsc_unstable(void)
1552{
1553#ifdef CONFIG_X86_64
1554 /*
1555 * TSC is marked unstable when we're running on Hyper-V,
1556 * 'TSC page' clocksource is good.
1557 */
1558 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1559 return false;
1560#endif
1561 return check_tsc_unstable();
1562}
1563
8fe8ab46 1564void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1565{
1566 struct kvm *kvm = vcpu->kvm;
f38e098f 1567 u64 offset, ns, elapsed;
99e3e30a 1568 unsigned long flags;
b48aa97e 1569 bool matched;
0d3da0d2 1570 bool already_matched;
8fe8ab46 1571 u64 data = msr->data;
c5e8ec8e 1572 bool synchronizing = false;
99e3e30a 1573
038f8c11 1574 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1575 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1576 ns = ktime_get_boot_ns();
f38e098f 1577 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1578
03ba32ca 1579 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1580 if (data == 0 && msr->host_initiated) {
1581 /*
1582 * detection of vcpu initialization -- need to sync
1583 * with other vCPUs. This particularly helps to keep
1584 * kvm_clock stable after CPU hotplug
1585 */
1586 synchronizing = true;
1587 } else {
1588 u64 tsc_exp = kvm->arch.last_tsc_write +
1589 nsec_to_cycles(vcpu, elapsed);
1590 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1591 /*
1592 * Special case: TSC write with a small delta (1 second)
1593 * of virtual cycle time against real time is
1594 * interpreted as an attempt to synchronize the CPU.
1595 */
1596 synchronizing = data < tsc_exp + tsc_hz &&
1597 data + tsc_hz > tsc_exp;
1598 }
c5e8ec8e 1599 }
f38e098f
ZA		 1600
1601 /*
5d3cb0f6
ZA		 1602 * For a reliable TSC, we can match TSC offsets, and for an unstable
1603 * TSC, we add elapsed time in this computation. We could let the
1604 * compensation code attempt to catch up if we fall behind, but
1605 * it's better to try to match offsets from the beginning.
1606 */
c5e8ec8e 1607 if (synchronizing &&
5d3cb0f6 1608 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1609 if (!kvm_check_tsc_unstable()) {
e26101b1 1610 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1611 pr_debug("kvm: matched tsc offset for %llu\n", data);
1612 } else {
857e4099 1613 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1614 data += delta;
07c1419a 1615 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1616 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1617 }
b48aa97e 1618 matched = true;
0d3da0d2 1619 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1620 } else {
1621 /*
1622 * We split periods of matched TSC writes into generations.
1623 * For each generation, we track the original measured
1624 * nanosecond time, offset, and write, so if TSCs are in
1625 * sync, we can match exact offset, and if not, we can match
4a969980 1626 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1627 *
1628 * These values are tracked in kvm->arch.cur_xxx variables.
1629 */
1630 kvm->arch.cur_tsc_generation++;
1631 kvm->arch.cur_tsc_nsec = ns;
1632 kvm->arch.cur_tsc_write = data;
1633 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1634 matched = false;
0d3da0d2 1635 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1636 kvm->arch.cur_tsc_generation, data);
f38e098f 1637 }
e26101b1
ZA		 1638
1639 /*
1640 * We also track th most recent recorded KHZ, write and time to
1641 * allow the matching interval to be extended at each write.
1642 */
f38e098f
ZA		 1643 kvm->arch.last_tsc_nsec = ns;
1644 kvm->arch.last_tsc_write = data;
5d3cb0f6 1645 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1646
b183aa58 1647 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1648
1649 /* Keep track of which generation this VCPU has synchronized to */
1650 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1651 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1652 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1653
d6321d49 1654 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1655 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1656
a545ab6a 1657 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1658 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1659
1660 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1661 if (!matched) {
b48aa97e 1662 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1663 } else if (!already_matched) {
1664 kvm->arch.nr_vcpus_matched_tsc++;
1665 }
b48aa97e
MT		 1666
1667 kvm_track_tsc_matching(vcpu);
1668 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1669}
e26101b1 1670
99e3e30a
ZA		 1671EXPORT_SYMBOL_GPL(kvm_write_tsc);
1672
58ea6767
HZ		 1673static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1674 s64 adjustment)
1675{
ea26e4ec 1676 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1677}
1678
1679static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1680{
1681 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1682 WARN_ON(adjustment < 0);
1683 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1684 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1685}
1686
d828199e
MT		 1687#ifdef CONFIG_X86_64
1688
a5a1d1c2 1689static u64 read_tsc(void)
d828199e 1690{
a5a1d1c2 1691 u64 ret = (u64)rdtsc_ordered();
03b9730b 1692 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1693
1694 if (likely(ret >= last))
1695 return ret;
1696
1697 /*
1698 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1699 * predictable (it's just a function of time and the likely is
d828199e
MT		 1700 * very likely) and there's a data dependence, so force GCC
1701 * to generate a branch instead. I don't barrier() because
1702 * we don't actually need a barrier, and if this function
1703 * ever gets inlined it will generate worse code.
1704 */
1705 asm volatile ("");
1706 return last;
1707}
1708
b0c39dc6 1709static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1710{
1711 long v;
1712 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1713 u64 tsc_pg_val;
1714
1715 switch (gtod->clock.vclock_mode) {
1716 case VCLOCK_HVCLOCK:
1717 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1718 tsc_timestamp);
1719 if (tsc_pg_val != U64_MAX) {
1720 /* TSC page valid */
1721 *mode = VCLOCK_HVCLOCK;
1722 v = (tsc_pg_val - gtod->clock.cycle_last) &
1723 gtod->clock.mask;
1724 } else {
1725 /* TSC page invalid */
1726 *mode = VCLOCK_NONE;
1727 }
1728 break;
1729 case VCLOCK_TSC:
1730 *mode = VCLOCK_TSC;
1731 *tsc_timestamp = read_tsc();
1732 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1733 gtod->clock.mask;
1734 break;
1735 default:
1736 *mode = VCLOCK_NONE;
1737 }
d828199e 1738
b0c39dc6
VK		 1739 if (*mode == VCLOCK_NONE)
1740 *tsc_timestamp = v = 0;
d828199e 1741
d828199e
MT		 1742 return v * gtod->clock.mult;
1743}
1744
b0c39dc6 1745static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1746{
cbcf2dd3 1747 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1748 unsigned long seq;
d828199e 1749 int mode;
cbcf2dd3 1750 u64 ns;
d828199e 1751
d828199e
MT		 1752 do {
1753 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1754 ns = gtod->nsec_base;
b0c39dc6 1755 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1756 ns >>= gtod->clock.shift;
cbcf2dd3 1757 ns += gtod->boot_ns;
d828199e 1758 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1759 *t = ns;
d828199e
MT		 1760
1761 return mode;
1762}
1763
b0c39dc6 1764static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1765{
1766 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1767 unsigned long seq;
1768 int mode;
1769 u64 ns;
1770
1771 do {
1772 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1773 ts->tv_sec = gtod->wall_time_sec;
1774 ns = gtod->nsec_base;
b0c39dc6 1775 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1776 ns >>= gtod->clock.shift;
1777 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1778
1779 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1780 ts->tv_nsec = ns;
1781
1782 return mode;
1783}
1784
b0c39dc6
VK		 1785/* returns true if host is using TSC based clocksource */
1786static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1787{
d828199e 1788 /* checked again under seqlock below */
b0c39dc6 1789 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1790 return false;
1791
b0c39dc6
VK		 1792 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1793 tsc_timestamp));
d828199e 1794}
55dd00a7 1795
b0c39dc6 1796/* returns true if host is using TSC based clocksource */
55dd00a7 1797static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1798 u64 *tsc_timestamp)
55dd00a7
MT		 1799{
1800 /* checked again under seqlock below */
b0c39dc6 1801 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1802 return false;
1803
b0c39dc6 1804 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1805}
d828199e
MT		 1806#endif
1807
1808/*
1809 *
b48aa97e
MT		 1810 * Assuming a stable TSC across physical CPUS, and a stable TSC
1811 * across virtual CPUs, the following condition is possible.
1812 * Each numbered line represents an event visible to both
d828199e
MT		 1813 * CPUs at the next numbered event.
1814 *
1815 * "timespecX" represents host monotonic time. "tscX" represents
1816 * RDTSC value.
1817 *
1818 * VCPU0 on CPU0 | VCPU1 on CPU1
1819 *
1820 * 1. read timespec0,tsc0
1821 * 2. | timespec1 = timespec0 + N
1822 * | tsc1 = tsc0 + M
1823 * 3. transition to guest | transition to guest
1824 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1825 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1826 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1827 *
1828 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1829 *
1830 * - ret0 < ret1
1831 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1832 * ...
1833 * - 0 < N - M => M < N
1834 *
1835 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1836 * always the case (the difference between two distinct xtime instances
1837 * might be smaller then the difference between corresponding TSC reads,
1838 * when updating guest vcpus pvclock areas).
1839 *
1840 * To avoid that problem, do not allow visibility of distinct
1841 * system_timestamp/tsc_timestamp values simultaneously: use a master
1842 * copy of host monotonic time values. Update that master copy
1843 * in lockstep.
1844 *
b48aa97e 1845 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1846 *
1847 */
1848
1849static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1850{
1851#ifdef CONFIG_X86_64
1852 struct kvm_arch *ka = &kvm->arch;
1853 int vclock_mode;
b48aa97e
MT		 1854 bool host_tsc_clocksource, vcpus_matched;
1855
1856 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1857 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1858
1859 /*
1860 * If the host uses TSC clock, then passthrough TSC as stable
1861 * to the guest.
1862 */
b48aa97e 1863 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1864 &ka->master_kernel_ns,
1865 &ka->master_cycle_now);
1866
16a96021 1867 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1868 && !ka->backwards_tsc_observed
54750f2c 1869 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1870
d828199e
MT		 1871 if (ka->use_master_clock)
1872 atomic_set(&kvm_guest_has_master_clock, 1);
1873
1874 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1875 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1876 vcpus_matched);
d828199e
MT		 1877#endif
1878}
1879
2860c4b1
PB		 1880void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1881{
1882 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1883}
1884
2e762ff7
MT		 1885static void kvm_gen_update_masterclock(struct kvm *kvm)
1886{
1887#ifdef CONFIG_X86_64
1888 int i;
1889 struct kvm_vcpu *vcpu;
1890 struct kvm_arch *ka = &kvm->arch;
1891
1892 spin_lock(&ka->pvclock_gtod_sync_lock);
1893 kvm_make_mclock_inprogress_request(kvm);
1894 /* no guest entries from this point */
1895 pvclock_update_vm_gtod_copy(kvm);
1896
1897 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1898 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1899
1900 /* guest entries allowed */
1901 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1902 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1903
1904 spin_unlock(&ka->pvclock_gtod_sync_lock);
1905#endif
1906}
1907
e891a32e 1908u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1909{
108b249c 1910 struct kvm_arch *ka = &kvm->arch;
8b953440 1911 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1912 u64 ret;
108b249c 1913
8b953440
PB		 1914 spin_lock(&ka->pvclock_gtod_sync_lock);
1915 if (!ka->use_master_clock) {
1916 spin_unlock(&ka->pvclock_gtod_sync_lock);
1917 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1918 }
1919
8b953440
PB		 1920 hv_clock.tsc_timestamp = ka->master_cycle_now;
1921 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1922 spin_unlock(&ka->pvclock_gtod_sync_lock);
1923
e2c2206a
WL		 1924 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1925 get_cpu();
1926
e70b57a6
WL		 1927 if (__this_cpu_read(cpu_tsc_khz)) {
1928 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1929 &hv_clock.tsc_shift,
1930 &hv_clock.tsc_to_system_mul);
1931 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1932 } else
1933 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1934
1935 put_cpu();
1936
1937 return ret;
108b249c
PB		 1938}
1939
0d6dd2ff
PB		 1940static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1941{
1942 struct kvm_vcpu_arch *vcpu = &v->arch;
1943 struct pvclock_vcpu_time_info guest_hv_clock;
1944
4e335d9e 1945 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1946 &guest_hv_clock, sizeof(guest_hv_clock))))
1947 return;
1948
1949 /* This VCPU is paused, but it's legal for a guest to read another
1950 * VCPU's kvmclock, so we really have to follow the specification where
1951 * it says that version is odd if data is being modified, and even after
1952 * it is consistent.
1953 *
1954 * Version field updates must be kept separate. This is because
1955 * kvm_write_guest_cached might use a "rep movs" instruction, and
1956 * writes within a string instruction are weakly ordered. So there
1957 * are three writes overall.
1958 *
1959 * As a small optimization, only write the version field in the first
1960 * and third write. The vcpu->pv_time cache is still valid, because the
1961 * version field is the first in the struct.
1962 */
1963 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1964
51c4b8bb
LA		 1965 if (guest_hv_clock.version & 1)
1966 ++guest_hv_clock.version; /* first time write, random junk */
1967
0d6dd2ff 1968 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1969 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1970 &vcpu->hv_clock,
1971 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1972
1973 smp_wmb();
1974
1975 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1976 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1977
1978 if (vcpu->pvclock_set_guest_stopped_request) {
1979 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1980 vcpu->pvclock_set_guest_stopped_request = false;
1981 }
1982
1983 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1984
4e335d9e
PB		 1985 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1986 &vcpu->hv_clock,
1987 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1988
1989 smp_wmb();
1990
1991 vcpu->hv_clock.version++;
4e335d9e
PB		 1992 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1993 &vcpu->hv_clock,
1994 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1995}
1996
34c238a1 1997static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1998{
78db6a50 1999 unsigned long flags, tgt_tsc_khz;
18068523 2000 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2001 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2002 s64 kernel_ns;
d828199e 2003 u64 tsc_timestamp, host_tsc;
51d59c6b 2004 u8 pvclock_flags;
d828199e
MT		 2005 bool use_master_clock;
2006
2007 kernel_ns = 0;
2008 host_tsc = 0;
18068523 2009
d828199e
MT		 2010 /*
2011 * If the host uses TSC clock, then passthrough TSC as stable
2012 * to the guest.
2013 */
2014 spin_lock(&ka->pvclock_gtod_sync_lock);
2015 use_master_clock = ka->use_master_clock;
2016 if (use_master_clock) {
2017 host_tsc = ka->master_cycle_now;
2018 kernel_ns = ka->master_kernel_ns;
2019 }
2020 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2021
2022 /* Keep irq disabled to prevent changes to the clock */
2023 local_irq_save(flags);
78db6a50
PB		 2024 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2025 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2026 local_irq_restore(flags);
2027 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2028 return 1;
2029 }
d828199e 2030 if (!use_master_clock) {
4ea1636b 2031 host_tsc = rdtsc();
108b249c 2032 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2033 }
2034
4ba76538 2035 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2036
c285545f
ZA		 2037 /*
2038 * We may have to catch up the TSC to match elapsed wall clock
2039 * time for two reasons, even if kvmclock is used.
2040 * 1) CPU could have been running below the maximum TSC rate
2041 * 2) Broken TSC compensation resets the base at each VCPU
2042 * entry to avoid unknown leaps of TSC even when running
2043 * again on the same CPU. This may cause apparent elapsed
2044 * time to disappear, and the guest to stand still or run
2045 * very slowly.
2046 */
2047 if (vcpu->tsc_catchup) {
2048 u64 tsc = compute_guest_tsc(v, kernel_ns);
2049 if (tsc > tsc_timestamp) {
f1e2b260 2050 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2051 tsc_timestamp = tsc;
2052 }
50d0a0f9
GH		 2053 }
2054
18068523
GOC		 2055 local_irq_restore(flags);
2056
0d6dd2ff 2057 /* With all the info we got, fill in the values */
18068523 2058
78db6a50
PB		 2059 if (kvm_has_tsc_control)
2060 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2061
2062 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2063 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2064 &vcpu->hv_clock.tsc_shift,
2065 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2066 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2067 }
2068
1d5f066e 2069 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2070 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2071 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2072
d828199e 2073 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2074 pvclock_flags = 0;
d828199e
MT		 2075 if (use_master_clock)
2076 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2077
78c0337a
MT		 2078 vcpu->hv_clock.flags = pvclock_flags;
2079
095cf55d
PB		 2080 if (vcpu->pv_time_enabled)
2081 kvm_setup_pvclock_page(v);
2082 if (v == kvm_get_vcpu(v->kvm, 0))
2083 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2084 return 0;
c8076604
GH		 2085}
2086
0061d53d
MT		 2087/*
2088 * kvmclock updates which are isolated to a given vcpu, such as
2089 * vcpu->cpu migration, should not allow system_timestamp from
2090 * the rest of the vcpus to remain static. Otherwise ntp frequency
2091 * correction applies to one vcpu's system_timestamp but not
2092 * the others.
2093 *
2094 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2095 * We need to rate-limit these requests though, as they can
2096 * considerably slow guests that have a large number of vcpus.
2097 * The time for a remote vcpu to update its kvmclock is bound
2098 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2099 */
2100
7e44e449
AJ		 2101#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2102
2103static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2104{
2105 int i;
7e44e449
AJ		 2106 struct delayed_work *dwork = to_delayed_work(work);
2107 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2108 kvmclock_update_work);
2109 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2110 struct kvm_vcpu *vcpu;
2111
2112 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2113 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2114 kvm_vcpu_kick(vcpu);
2115 }
2116}
2117
7e44e449
AJ		 2118static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2119{
2120 struct kvm *kvm = v->kvm;
2121
105b21bb 2122 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2123 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2124 KVMCLOCK_UPDATE_DELAY);
2125}
2126
332967a3
AJ		 2127#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2128
2129static void kvmclock_sync_fn(struct work_struct *work)
2130{
2131 struct delayed_work *dwork = to_delayed_work(work);
2132 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2133 kvmclock_sync_work);
2134 struct kvm *kvm = container_of(ka, struct kvm, arch);
2135
630994b3
MT		 2136 if (!kvmclock_periodic_sync)
2137 return;
2138
332967a3
AJ		 2139 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2140 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2141 KVMCLOCK_SYNC_PERIOD);
2142}
2143
9ffd986c 2144static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2145{
890ca9ae
HY		 2146 u64 mcg_cap = vcpu->arch.mcg_cap;
2147 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2148 u32 msr = msr_info->index;
2149 u64 data = msr_info->data;
890ca9ae 2150
15c4a640 2151 switch (msr) {
15c4a640 2152 case MSR_IA32_MCG_STATUS:
890ca9ae 2153 vcpu->arch.mcg_status = data;
15c4a640 2154 break;
c7ac679c 2155 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2156 if (!(mcg_cap & MCG_CTL_P))
2157 return 1;
2158 if (data != 0 && data != ~(u64)0)
2159 return -1;
2160 vcpu->arch.mcg_ctl = data;
2161 break;
2162 default:
2163 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2164 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2165 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2166 /* only 0 or all 1s can be written to IA32_MCi_CTL
2167 * some Linux kernels though clear bit 10 in bank 4 to
2168 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2169 * this to avoid an uncatched #GP in the guest
2170 */
890ca9ae 2171 if ((offset & 0x3) == 0 &&
114be429 2172 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2173 return -1;
9ffd986c
WL		 2174 if (!msr_info->host_initiated &&
2175 (offset & 0x3) == 1 && data != 0)
2176 return -1;
890ca9ae
HY		 2177 vcpu->arch.mce_banks[offset] = data;
2178 break;
2179 }
2180 return 1;
2181 }
2182 return 0;
2183}
2184
ffde22ac
ES		 2185static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2186{
2187 struct kvm *kvm = vcpu->kvm;
2188 int lm = is_long_mode(vcpu);
2189 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2190 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2191 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2192 : kvm->arch.xen_hvm_config.blob_size_32;
2193 u32 page_num = data & ~PAGE_MASK;
2194 u64 page_addr = data & PAGE_MASK;
2195 u8 *page;
2196 int r;
2197
2198 r = -E2BIG;
2199 if (page_num >= blob_size)
2200 goto out;
2201 r = -ENOMEM;
ff5c2c03
SL		 2202 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2203 if (IS_ERR(page)) {
2204 r = PTR_ERR(page);
ffde22ac 2205 goto out;
ff5c2c03 2206 }
54bf36aa 2207 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2208 goto out_free;
2209 r = 0;
2210out_free:
2211 kfree(page);
2212out:
2213 return r;
2214}
2215
344d9588
GN		 2216static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2217{
2218 gpa_t gpa = data & ~0x3f;
2219
52a5c155
WL		 2220 /* Bits 3:5 are reserved, Should be zero */
2221 if (data & 0x38)
344d9588
GN		 2222 return 1;
2223
2224 vcpu->arch.apf.msr_val = data;
2225
2226 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2227 kvm_clear_async_pf_completion_queue(vcpu);
2228 kvm_async_pf_hash_reset(vcpu);
2229 return 0;
2230 }
2231
4e335d9e 2232 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2233 sizeof(u32)))
344d9588
GN		 2234 return 1;
2235
6adba527 2236 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2237 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2238 kvm_async_pf_wakeup_all(vcpu);
2239 return 0;
2240}
2241
12f9a48f
GC		 2242static void kvmclock_reset(struct kvm_vcpu *vcpu)
2243{
0b79459b 2244 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2245}
2246
f38a7b75
WL		 2247static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2248{
2249 ++vcpu->stat.tlb_flush;
2250 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2251}
2252
c9aaa895
GC		 2253static void record_steal_time(struct kvm_vcpu *vcpu)
2254{
2255 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2256 return;
2257
4e335d9e 2258 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2259 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2260 return;
2261
f38a7b75
WL		 2262 /*
2263 * Doing a TLB flush here, on the guest's behalf, can avoid
2264 * expensive IPIs.
2265 */
2266 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2267 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2268
35f3fae1
WL		 2269 if (vcpu->arch.st.steal.version & 1)
2270 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2271
2272 vcpu->arch.st.steal.version += 1;
2273
4e335d9e 2274 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2275 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2276
2277 smp_wmb();
2278
c54cdf14
LC		 2279 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2280 vcpu->arch.st.last_steal;
2281 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2282
4e335d9e 2283 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2284 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2285
2286 smp_wmb();
2287
2288 vcpu->arch.st.steal.version += 1;
c9aaa895 2289
4e335d9e 2290 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2291 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2292}
2293
8fe8ab46 2294int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2295{
5753785f 2296 bool pr = false;
8fe8ab46
WA		 2297 u32 msr = msr_info->index;
2298 u64 data = msr_info->data;
5753785f 2299
15c4a640 2300 switch (msr) {
2e32b719 2301 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2302 case MSR_IA32_UCODE_WRITE:
2303 case MSR_VM_HSAVE_PA:
2304 case MSR_AMD64_PATCH_LOADER:
2305 case MSR_AMD64_BU_CFG2:
405a353a 2306 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2307 break;
2308
518e7b94
WL		 2309 case MSR_IA32_UCODE_REV:
2310 if (msr_info->host_initiated)
2311 vcpu->arch.microcode_version = data;
2312 break;
15c4a640 2313 case MSR_EFER:
b69e8cae 2314 return set_efer(vcpu, data);
8f1589d9
AP		 2315 case MSR_K7_HWCR:
2316 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2317 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2318 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2319 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2320 if (data != 0) {
a737f256
CD		 2321 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2322 data);
8f1589d9
AP		 2323 return 1;
2324 }
15c4a640 2325 break;
f7c6d140
AP		 2326 case MSR_FAM10H_MMIO_CONF_BASE:
2327 if (data != 0) {
a737f256
CD		 2328 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2329 "0x%llx\n", data);
f7c6d140
AP		 2330 return 1;
2331 }
15c4a640 2332 break;
b5e2fec0
AG		 2333 case MSR_IA32_DEBUGCTLMSR:
2334 if (!data) {
2335 /* We support the non-activated case already */
2336 break;
2337 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2338 /* Values other than LBR and BTF are vendor-specific,
2339 thus reserved and should throw a #GP */
2340 return 1;
2341 }
a737f256
CD		 2342 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2343 __func__, data);
b5e2fec0 2344 break;
9ba075a6 2345 case 0x200 ... 0x2ff:
ff53604b 2346 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2347 case MSR_IA32_APICBASE:
58cb628d 2348 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2349 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2350 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2351 case MSR_IA32_TSCDEADLINE:
2352 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2353 break;
ba904635 2354 case MSR_IA32_TSC_ADJUST:
d6321d49 2355 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2356 if (!msr_info->host_initiated) {
d913b904 2357 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2358 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2359 }
2360 vcpu->arch.ia32_tsc_adjust_msr = data;
2361 }
2362 break;
15c4a640 2363 case MSR_IA32_MISC_ENABLE:
ad312c7c 2364 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2365 break;
64d60670
PB		 2366 case MSR_IA32_SMBASE:
2367 if (!msr_info->host_initiated)
2368 return 1;
2369 vcpu->arch.smbase = data;
2370 break;
dd259935
PB		 2371 case MSR_IA32_TSC:
2372 kvm_write_tsc(vcpu, msr_info);
2373 break;
52797bf9
LA		 2374 case MSR_SMI_COUNT:
2375 if (!msr_info->host_initiated)
2376 return 1;
2377 vcpu->arch.smi_count = data;
2378 break;
11c6bffa 2379 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2380 case MSR_KVM_WALL_CLOCK:
2381 vcpu->kvm->arch.wall_clock = data;
2382 kvm_write_wall_clock(vcpu->kvm, data);
2383 break;
11c6bffa 2384 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2385 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2386 struct kvm_arch *ka = &vcpu->kvm->arch;
2387
12f9a48f 2388 kvmclock_reset(vcpu);
18068523 2389
54750f2c
MT		 2390 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2391 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2392
2393 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2394 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2395
2396 ka->boot_vcpu_runs_old_kvmclock = tmp;
2397 }
2398
18068523 2399 vcpu->arch.time = data;
0061d53d 2400 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2401
2402 /* we verify if the enable bit is set... */
2403 if (!(data & 1))
2404 break;
2405
4e335d9e 2406 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2407 &vcpu->arch.pv_time, data & ~1ULL,
2408 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2409 vcpu->arch.pv_time_enabled = false;
2410 else
2411 vcpu->arch.pv_time_enabled = true;
32cad84f 2412
18068523
GOC		 2413 break;
2414 }
344d9588
GN		 2415 case MSR_KVM_ASYNC_PF_EN:
2416 if (kvm_pv_enable_async_pf(vcpu, data))
2417 return 1;
2418 break;
c9aaa895
GC		 2419 case MSR_KVM_STEAL_TIME:
2420
2421 if (unlikely(!sched_info_on()))
2422 return 1;
2423
2424 if (data & KVM_STEAL_RESERVED_MASK)
2425 return 1;
2426
4e335d9e 2427 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2428 data & KVM_STEAL_VALID_BITS,
2429 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2430 return 1;
2431
2432 vcpu->arch.st.msr_val = data;
2433
2434 if (!(data & KVM_MSR_ENABLED))
2435 break;
2436
c9aaa895
GC		 2437 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2438
2439 break;
ae7a2a3f
MT		 2440 case MSR_KVM_PV_EOI_EN:
2441 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2442 return 1;
2443 break;
c9aaa895 2444
890ca9ae
HY		 2445 case MSR_IA32_MCG_CTL:
2446 case MSR_IA32_MCG_STATUS:
81760dcc 2447 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2448 return set_msr_mce(vcpu, msr_info);
71db6023 2449
6912ac32
WH		 2450 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2451 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2452 pr = true; /* fall through */
2453 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2454 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2455 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2456 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2457
2458 if (pr || data != 0)
a737f256
CD		 2459 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2460 "0x%x data 0x%llx\n", msr, data);
5753785f 2461 break;
84e0cefa
JS		 2462 case MSR_K7_CLK_CTL:
2463 /*
2464 * Ignore all writes to this no longer documented MSR.
2465 * Writes are only relevant for old K7 processors,
2466 * all pre-dating SVM, but a recommended workaround from
4a969980 2467 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2468 * affected processor models on the command line, hence
2469 * the need to ignore the workaround.
2470 */
2471 break;
55cd8e5a 2472 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2473 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2474 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2475 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2476 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2477 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2478 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2479 return kvm_hv_set_msr_common(vcpu, msr, data,
2480 msr_info->host_initiated);
91c9c3ed 2481 case MSR_IA32_BBL_CR_CTL3:
2482 /* Drop writes to this legacy MSR -- see rdmsr
2483 * counterpart for further detail.
2484 */
fab0aa3b
EM		 2485 if (report_ignored_msrs)
2486 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2487 msr, data);
91c9c3ed 2488 break;
2b036c6b 2489 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2490 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2491 return 1;
2492 vcpu->arch.osvw.length = data;
2493 break;
2494 case MSR_AMD64_OSVW_STATUS:
d6321d49 2495 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2496 return 1;
2497 vcpu->arch.osvw.status = data;
2498 break;
db2336a8
KH		 2499 case MSR_PLATFORM_INFO:
2500 if (!msr_info->host_initiated ||
2501 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2502 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2503 cpuid_fault_enabled(vcpu)))
2504 return 1;
2505 vcpu->arch.msr_platform_info = data;
2506 break;
2507 case MSR_MISC_FEATURES_ENABLES:
2508 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2509 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2510 !supports_cpuid_fault(vcpu)))
2511 return 1;
2512 vcpu->arch.msr_misc_features_enables = data;
2513 break;
15c4a640 2514 default:
ffde22ac
ES		 2515 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2516 return xen_hvm_config(vcpu, data);
c6702c9d 2517 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2518 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2519 if (!ignore_msrs) {
ae0f5499 2520 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2521 msr, data);
ed85c068
AP		 2522 return 1;
2523 } else {
fab0aa3b
EM		 2524 if (report_ignored_msrs)
2525 vcpu_unimpl(vcpu,
2526 "ignored wrmsr: 0x%x data 0x%llx\n",
2527 msr, data);
ed85c068
AP		 2528 break;
2529 }
15c4a640
CO		 2530 }
2531 return 0;
2532}
2533EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2534
2535
2536/*
2537 * Reads an msr value (of 'msr_index') into 'pdata'.
2538 * Returns 0 on success, non-0 otherwise.
2539 * Assumes vcpu_load() was already called.
2540 */
609e36d3 2541int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2542{
609e36d3 2543 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2544}
ff651cb6 2545EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2546
890ca9ae 2547static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2548{
2549 u64 data;
890ca9ae
HY		 2550 u64 mcg_cap = vcpu->arch.mcg_cap;
2551 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2552
2553 switch (msr) {
15c4a640
CO		 2554 case MSR_IA32_P5_MC_ADDR:
2555 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2556 data = 0;
2557 break;
15c4a640 2558 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2559 data = vcpu->arch.mcg_cap;
2560 break;
c7ac679c 2561 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2562 if (!(mcg_cap & MCG_CTL_P))
2563 return 1;
2564 data = vcpu->arch.mcg_ctl;
2565 break;
2566 case MSR_IA32_MCG_STATUS:
2567 data = vcpu->arch.mcg_status;
2568 break;
2569 default:
2570 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2571 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2572 u32 offset = msr - MSR_IA32_MC0_CTL;
2573 data = vcpu->arch.mce_banks[offset];
2574 break;
2575 }
2576 return 1;
2577 }
2578 *pdata = data;
2579 return 0;
2580}
2581
609e36d3 2582int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2583{
609e36d3 2584 switch (msr_info->index) {
890ca9ae 2585 case MSR_IA32_PLATFORM_ID:
15c4a640 2586 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2587 case MSR_IA32_DEBUGCTLMSR:
2588 case MSR_IA32_LASTBRANCHFROMIP:
2589 case MSR_IA32_LASTBRANCHTOIP:
2590 case MSR_IA32_LASTINTFROMIP:
2591 case MSR_IA32_LASTINTTOIP:
60af2ecd 2592 case MSR_K8_SYSCFG:
3afb1121
PB		 2593 case MSR_K8_TSEG_ADDR:
2594 case MSR_K8_TSEG_MASK:
60af2ecd 2595 case MSR_K7_HWCR:
61a6bd67 2596 case MSR_VM_HSAVE_PA:
1fdbd48c 2597 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2598 case MSR_AMD64_NB_CFG:
f7c6d140 2599 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2600 case MSR_AMD64_BU_CFG2:
0c2df2a1 2601 case MSR_IA32_PERF_CTL:
405a353a 2602 case MSR_AMD64_DC_CFG:
609e36d3 2603 msr_info->data = 0;
15c4a640 2604 break;
c51eb52b 2605 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2606 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2607 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2608 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2609 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2610 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2611 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2612 msr_info->data = 0;
5753785f 2613 break;
742bc670 2614 case MSR_IA32_UCODE_REV:
518e7b94 2615 msr_info->data = vcpu->arch.microcode_version;
742bc670 2616 break;
dd259935
PB		 2617 case MSR_IA32_TSC:
2618 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2619 break;
9ba075a6 2620 case MSR_MTRRcap:
9ba075a6 2621 case 0x200 ... 0x2ff:
ff53604b 2622 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2623 case 0xcd: /* fsb frequency */
609e36d3 2624 msr_info->data = 3;
15c4a640 2625 break;
7b914098
JS		 2626 /*
2627 * MSR_EBC_FREQUENCY_ID
2628 * Conservative value valid for even the basic CPU models.
2629 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2630 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2631 * and 266MHz for model 3, or 4. Set Core Clock
2632 * Frequency to System Bus Frequency Ratio to 1 (bits
2633 * 31:24) even though these are only valid for CPU
2634 * models > 2, however guests may end up dividing or
2635 * multiplying by zero otherwise.
2636 */
2637 case MSR_EBC_FREQUENCY_ID:
609e36d3 2638 msr_info->data = 1 << 24;
7b914098 2639 break;
15c4a640 2640 case MSR_IA32_APICBASE:
609e36d3 2641 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2642 break;
0105d1a5 2643 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2644 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2645 break;
a3e06bbe 2646 case MSR_IA32_TSCDEADLINE:
609e36d3 2647 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2648 break;
ba904635 2649 case MSR_IA32_TSC_ADJUST:
609e36d3 2650 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2651 break;
15c4a640 2652 case MSR_IA32_MISC_ENABLE:
609e36d3 2653 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2654 break;
64d60670
PB		 2655 case MSR_IA32_SMBASE:
2656 if (!msr_info->host_initiated)
2657 return 1;
2658 msr_info->data = vcpu->arch.smbase;
15c4a640 2659 break;
52797bf9
LA		 2660 case MSR_SMI_COUNT:
2661 msr_info->data = vcpu->arch.smi_count;
2662 break;
847f0ad8
AG		 2663 case MSR_IA32_PERF_STATUS:
2664 /* TSC increment by tick */
609e36d3 2665 msr_info->data = 1000ULL;
847f0ad8 2666 /* CPU multiplier */
b0996ae4 2667 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2668 break;
15c4a640 2669 case MSR_EFER:
609e36d3 2670 msr_info->data = vcpu->arch.efer;
15c4a640 2671 break;
18068523 2672 case MSR_KVM_WALL_CLOCK:
11c6bffa 2673 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2674 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2675 break;
2676 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2677 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2678 msr_info->data = vcpu->arch.time;
18068523 2679 break;
344d9588 2680 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2681 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2682 break;
c9aaa895 2683 case MSR_KVM_STEAL_TIME:
609e36d3 2684 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2685 break;
1d92128f 2686 case MSR_KVM_PV_EOI_EN:
609e36d3 2687 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2688 break;
890ca9ae
HY		 2689 case MSR_IA32_P5_MC_ADDR:
2690 case MSR_IA32_P5_MC_TYPE:
2691 case MSR_IA32_MCG_CAP:
2692 case MSR_IA32_MCG_CTL:
2693 case MSR_IA32_MCG_STATUS:
81760dcc 2694 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2695 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2696 case MSR_K7_CLK_CTL:
2697 /*
2698 * Provide expected ramp-up count for K7. All other
2699 * are set to zero, indicating minimum divisors for
2700 * every field.
2701 *
2702 * This prevents guest kernels on AMD host with CPU
2703 * type 6, model 8 and higher from exploding due to
2704 * the rdmsr failing.
2705 */
609e36d3 2706 msr_info->data = 0x20000000;
84e0cefa 2707 break;
55cd8e5a 2708 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2709 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2710 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2711 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2712 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2713 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2714 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887
AS		 2715 return kvm_hv_get_msr_common(vcpu,
2716 msr_info->index, &msr_info->data);
55cd8e5a 2717 break;
91c9c3ed 2718 case MSR_IA32_BBL_CR_CTL3:
2719 /* This legacy MSR exists but isn't fully documented in current
2720 * silicon. It is however accessed by winxp in very narrow
2721 * scenarios where it sets bit #19, itself documented as
2722 * a "reserved" bit. Best effort attempt to source coherent
2723 * read data here should the balance of the register be
2724 * interpreted by the guest:
2725 *
2726 * L2 cache control register 3: 64GB range, 256KB size,
2727 * enabled, latency 0x1, configured
2728 */
609e36d3 2729 msr_info->data = 0xbe702111;
91c9c3ed 2730 break;
2b036c6b 2731 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2732 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2733 return 1;
609e36d3 2734 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2735 break;
2736 case MSR_AMD64_OSVW_STATUS:
d6321d49 2737 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2738 return 1;
609e36d3 2739 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2740 break;
db2336a8
KH		 2741 case MSR_PLATFORM_INFO:
2742 msr_info->data = vcpu->arch.msr_platform_info;
2743 break;
2744 case MSR_MISC_FEATURES_ENABLES:
2745 msr_info->data = vcpu->arch.msr_misc_features_enables;
2746 break;
15c4a640 2747 default:
c6702c9d 2748 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2749 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2750 if (!ignore_msrs) {
ae0f5499
BD		 2751 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2752 msr_info->index);
ed85c068
AP		 2753 return 1;
2754 } else {
fab0aa3b
EM		 2755 if (report_ignored_msrs)
2756 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2757 msr_info->index);
609e36d3 2758 msr_info->data = 0;
ed85c068
AP		 2759 }
2760 break;
15c4a640 2761 }
15c4a640
CO		 2762 return 0;
2763}
2764EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2765
313a3dc7
CO		 2766/*
2767 * Read or write a bunch of msrs. All parameters are kernel addresses.
2768 *
2769 * @return number of msrs set successfully.
2770 */
2771static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2772 struct kvm_msr_entry *entries,
2773 int (*do_msr)(struct kvm_vcpu *vcpu,
2774 unsigned index, u64 *data))
2775{
801e459a 2776 int i;
313a3dc7 2777
313a3dc7
CO		 2778 for (i = 0; i < msrs->nmsrs; ++i)
2779 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2780 break;
2781
313a3dc7
CO		 2782 return i;
2783}
2784
2785/*
2786 * Read or write a bunch of msrs. Parameters are user addresses.
2787 *
2788 * @return number of msrs set successfully.
2789 */
2790static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2791 int (*do_msr)(struct kvm_vcpu *vcpu,
2792 unsigned index, u64 *data),
2793 int writeback)
2794{
2795 struct kvm_msrs msrs;
2796 struct kvm_msr_entry *entries;
2797 int r, n;
2798 unsigned size;
2799
2800 r = -EFAULT;
2801 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2802 goto out;
2803
2804 r = -E2BIG;
2805 if (msrs.nmsrs >= MAX_IO_MSRS)
2806 goto out;
2807
313a3dc7 2808 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2809 entries = memdup_user(user_msrs->entries, size);
2810 if (IS_ERR(entries)) {
2811 r = PTR_ERR(entries);
313a3dc7 2812 goto out;
ff5c2c03 2813 }
313a3dc7
CO		 2814
2815 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2816 if (r < 0)
2817 goto out_free;
2818
2819 r = -EFAULT;
2820 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2821 goto out_free;
2822
2823 r = n;
2824
2825out_free:
7a73c028 2826 kfree(entries);
313a3dc7
CO		 2827out:
2828 return r;
2829}
2830
4d5422ce
WL		 2831static inline bool kvm_can_mwait_in_guest(void)
2832{
2833 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2834 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2835 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2836}
2837
784aa3d7 2838int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2839{
4d5422ce 2840 int r = 0;
018d00d2
ZX		 2841
2842 switch (ext) {
2843 case KVM_CAP_IRQCHIP:
2844 case KVM_CAP_HLT:
2845 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2846 case KVM_CAP_SET_TSS_ADDR:
07716717 2847 case KVM_CAP_EXT_CPUID:
9c15bb1d 2848 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2849 case KVM_CAP_CLOCKSOURCE:
7837699f 2850 case KVM_CAP_PIT:
a28e4f5a 2851 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2852 case KVM_CAP_MP_STATE:
ed848624 2853 case KVM_CAP_SYNC_MMU:
a355c85c 2854 case KVM_CAP_USER_NMI:
52d939a0 2855 case KVM_CAP_REINJECT_CONTROL:
4925663a 2856 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2857 case KVM_CAP_IOEVENTFD:
f848a5a8 2858 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2859 case KVM_CAP_PIT2:
e9f42757 2860 case KVM_CAP_PIT_STATE2:
b927a3ce 2861 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2862 case KVM_CAP_XEN_HVM:
3cfc3092 2863 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2864 case KVM_CAP_HYPERV:
10388a07 2865 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2866 case KVM_CAP_HYPERV_SPIN:
5c919412 2867 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2868 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2869 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2870 case KVM_CAP_HYPERV_EVENTFD:
ab9f4ecb 2871 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2872 case KVM_CAP_DEBUGREGS:
d2be1651 2873 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2874 case KVM_CAP_XSAVE:
344d9588 2875 case KVM_CAP_ASYNC_PF:
92a1f12d 2876 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2877 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2878 case KVM_CAP_READONLY_MEM:
5f66b620 2879 case KVM_CAP_HYPERV_TIME:
100943c5 2880 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2881 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2882 case KVM_CAP_ENABLE_CAP_VM:
2883 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2884 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2885 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2886 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2887 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2888 r = 1;
2889 break;
01643c51
KH		 2890 case KVM_CAP_SYNC_REGS:
2891 r = KVM_SYNC_X86_VALID_FIELDS;
2892 break;
e3fd9a93
PB		 2893 case KVM_CAP_ADJUST_CLOCK:
2894 r = KVM_CLOCK_TSC_STABLE;
2895 break;
4d5422ce 2896 case KVM_CAP_X86_DISABLE_EXITS:
b31c114b 2897 r |= KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2898 if(kvm_can_mwait_in_guest())
2899 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2900 break;
6d396b55
PB		 2901 case KVM_CAP_X86_SMM:
2902 /* SMBASE is usually relocated above 1M on modern chipsets,
2903 * and SMM handlers might indeed rely on 4G segment limits,
2904 * so do not report SMM to be available if real mode is
2905 * emulated via vm86 mode. Still, do not go to great lengths
2906 * to avoid userspace's usage of the feature, because it is a
2907 * fringe case that is not enabled except via specific settings
2908 * of the module parameters.
2909 */
bc226f07 2910 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 2911 break;
774ead3a
AK		 2912 case KVM_CAP_VAPIC:
2913 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2914 break;
f725230a 2915 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2916 r = KVM_SOFT_MAX_VCPUS;
2917 break;
2918 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2919 r = KVM_MAX_VCPUS;
2920 break;
a988b910 2921 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2922 r = KVM_USER_MEM_SLOTS;
a988b910 2923 break;
a68a6a72
MT		 2924 case KVM_CAP_PV_MMU: /* obsolete */
2925 r = 0;
2f333bcb 2926 break;
890ca9ae
HY		 2927 case KVM_CAP_MCE:
2928 r = KVM_MAX_MCE_BANKS;
2929 break;
2d5b5a66 2930 case KVM_CAP_XCRS:
d366bf7e 2931 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2932 break;
92a1f12d
JR		 2933 case KVM_CAP_TSC_CONTROL:
2934 r = kvm_has_tsc_control;
2935 break;
37131313
RK		 2936 case KVM_CAP_X2APIC_API:
2937 r = KVM_X2APIC_API_VALID_FLAGS;
2938 break;
018d00d2 2939 default:
018d00d2
ZX		 2940 break;
2941 }
2942 return r;
2943
2944}
2945
043405e1
CO		 2946long kvm_arch_dev_ioctl(struct file *filp,
2947 unsigned int ioctl, unsigned long arg)
2948{
2949 void __user *argp = (void __user *)arg;
2950 long r;
2951
2952 switch (ioctl) {
2953 case KVM_GET_MSR_INDEX_LIST: {
2954 struct kvm_msr_list __user *user_msr_list = argp;
2955 struct kvm_msr_list msr_list;
2956 unsigned n;
2957
2958 r = -EFAULT;
2959 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2960 goto out;
2961 n = msr_list.nmsrs;
62ef68bb 2962 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2963 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2964 goto out;
2965 r = -E2BIG;
e125e7b6 2966 if (n < msr_list.nmsrs)
043405e1
CO		 2967 goto out;
2968 r = -EFAULT;
2969 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2970 num_msrs_to_save * sizeof(u32)))
2971 goto out;
e125e7b6 2972 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2973 &emulated_msrs,
62ef68bb 2974 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2975 goto out;
2976 r = 0;
2977 break;
2978 }
9c15bb1d
BP		 2979 case KVM_GET_SUPPORTED_CPUID:
2980 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2981 struct kvm_cpuid2 __user *cpuid_arg = argp;
2982 struct kvm_cpuid2 cpuid;
2983
2984 r = -EFAULT;
2985 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2986 goto out;
9c15bb1d
BP		 2987
2988 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2989 ioctl);
674eea0f
AK		 2990 if (r)
2991 goto out;
2992
2993 r = -EFAULT;
2994 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2995 goto out;
2996 r = 0;
2997 break;
2998 }
890ca9ae 2999 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3000 r = -EFAULT;
c45dcc71
AR		 3001 if (copy_to_user(argp, &kvm_mce_cap_supported,
3002 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3003 goto out;
3004 r = 0;
3005 break;
801e459a
TL		 3006 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3007 struct kvm_msr_list __user *user_msr_list = argp;
3008 struct kvm_msr_list msr_list;
3009 unsigned int n;
3010
3011 r = -EFAULT;
3012 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3013 goto out;
3014 n = msr_list.nmsrs;
3015 msr_list.nmsrs = num_msr_based_features;
3016 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3017 goto out;
3018 r = -E2BIG;
3019 if (n < msr_list.nmsrs)
3020 goto out;
3021 r = -EFAULT;
3022 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3023 num_msr_based_features * sizeof(u32)))
3024 goto out;
3025 r = 0;
3026 break;
3027 }
3028 case KVM_GET_MSRS:
3029 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3030 break;
890ca9ae 3031 }
043405e1
CO		 3032 default:
3033 r = -EINVAL;
3034 }
3035out:
3036 return r;
3037}
3038
f5f48ee1
SY		 3039static void wbinvd_ipi(void *garbage)
3040{
3041 wbinvd();
3042}
3043
3044static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3045{
e0f0bbc5 3046 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3047}
3048
313a3dc7
CO		 3049void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3050{
f5f48ee1
SY		 3051 /* Address WBINVD may be executed by guest */
3052 if (need_emulate_wbinvd(vcpu)) {
3053 if (kvm_x86_ops->has_wbinvd_exit())
3054 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3055 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3056 smp_call_function_single(vcpu->cpu,
3057 wbinvd_ipi, NULL, 1);
3058 }
3059
313a3dc7 3060 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3061
0dd6a6ed
ZA		 3062 /* Apply any externally detected TSC adjustments (due to suspend) */
3063 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3064 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3065 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3066 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3067 }
8f6055cb 3068
b0c39dc6 3069 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3070 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3071 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3072 if (tsc_delta < 0)
3073 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3074
b0c39dc6 3075 if (kvm_check_tsc_unstable()) {
07c1419a 3076 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3077 vcpu->arch.last_guest_tsc);
a545ab6a 3078 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3079 vcpu->arch.tsc_catchup = 1;
c285545f 3080 }
a749e247
PB		 3081
3082 if (kvm_lapic_hv_timer_in_use(vcpu))
3083 kvm_lapic_restart_hv_timer(vcpu);
3084
d98d07ca
MT		 3085 /*
3086 * On a host with synchronized TSC, there is no need to update
3087 * kvmclock on vcpu->cpu migration
3088 */
3089 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3090 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3091 if (vcpu->cpu != cpu)
1bd2009e 3092 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3093 vcpu->cpu = cpu;
6b7d7e76 3094 }
c9aaa895 3095
c9aaa895 3096 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3097}
3098
0b9f6c46
PX		 3099static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3100{
3101 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3102 return;
3103
fa55eedd 3104 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3105
4e335d9e 3106 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3107 &vcpu->arch.st.steal.preempted,
3108 offsetof(struct kvm_steal_time, preempted),
3109 sizeof(vcpu->arch.st.steal.preempted));
3110}
3111
313a3dc7
CO		 3112void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3113{
cc0d907c 3114 int idx;
de63ad4c
LM		 3115
3116 if (vcpu->preempted)
3117 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3118
931f261b
AA		 3119 /*
3120 * Disable page faults because we're in atomic context here.
3121 * kvm_write_guest_offset_cached() would call might_fault()
3122 * that relies on pagefault_disable() to tell if there's a
3123 * bug. NOTE: the write to guest memory may not go through if
3124 * during postcopy live migration or if there's heavy guest
3125 * paging.
3126 */
3127 pagefault_disable();
cc0d907c
AA		 3128 /*
3129 * kvm_memslots() will be called by
3130 * kvm_write_guest_offset_cached() so take the srcu lock.
3131 */
3132 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3133 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3134 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3135 pagefault_enable();
02daab21 3136 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3137 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3138 /*
3139 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3140 * on every vmexit, but if not, we might have a stale dr6 from the
3141 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3142 */
3143 set_debugreg(0, 6);
313a3dc7
CO		 3144}
3145
313a3dc7
CO		 3146static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3147 struct kvm_lapic_state *s)
3148{
fa59cc00 3149 if (vcpu->arch.apicv_active)
d62caabb
AS		 3150 kvm_x86_ops->sync_pir_to_irr(vcpu);
3151
a92e2543 3152 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3153}
3154
3155static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3156 struct kvm_lapic_state *s)
3157{
a92e2543
RK		 3158 int r;
3159
3160 r = kvm_apic_set_state(vcpu, s);
3161 if (r)
3162 return r;
cb142eb7 3163 update_cr8_intercept(vcpu);
313a3dc7
CO		 3164
3165 return 0;
3166}
3167
127a457a
MG		 3168static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3169{
3170 return (!lapic_in_kernel(vcpu) ||
3171 kvm_apic_accept_pic_intr(vcpu));
3172}
3173
782d422b
MG		 3174/*
3175 * if userspace requested an interrupt window, check that the
3176 * interrupt window is open.
3177 *
3178 * No need to exit to userspace if we already have an interrupt queued.
3179 */
3180static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3181{
3182 return kvm_arch_interrupt_allowed(vcpu) &&
3183 !kvm_cpu_has_interrupt(vcpu) &&
3184 !kvm_event_needs_reinjection(vcpu) &&
3185 kvm_cpu_accept_dm_intr(vcpu);
3186}
3187
f77bc6a4
ZX		 3188static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3189 struct kvm_interrupt *irq)
3190{
02cdb50f 3191 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3192 return -EINVAL;
1c1a9ce9
SR		 3193
3194 if (!irqchip_in_kernel(vcpu->kvm)) {
3195 kvm_queue_interrupt(vcpu, irq->irq, false);
3196 kvm_make_request(KVM_REQ_EVENT, vcpu);
3197 return 0;
3198 }
3199
3200 /*
3201 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3202 * fail for in-kernel 8259.
3203 */
3204 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3205 return -ENXIO;
f77bc6a4 3206
1c1a9ce9
SR		 3207 if (vcpu->arch.pending_external_vector != -1)
3208 return -EEXIST;
f77bc6a4 3209
1c1a9ce9 3210 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3211 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3212 return 0;
3213}
3214
c4abb7c9
JK		 3215static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3216{
c4abb7c9 3217 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3218
3219 return 0;
3220}
3221
f077825a
PB		 3222static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3223{
64d60670
PB		 3224 kvm_make_request(KVM_REQ_SMI, vcpu);
3225
f077825a
PB		 3226 return 0;
3227}
3228
b209749f
AK		 3229static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3230 struct kvm_tpr_access_ctl *tac)
3231{
3232 if (tac->flags)
3233 return -EINVAL;
3234 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3235 return 0;
3236}
3237
890ca9ae
HY		 3238static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3239 u64 mcg_cap)
3240{
3241 int r;
3242 unsigned bank_num = mcg_cap & 0xff, bank;
3243
3244 r = -EINVAL;
a9e38c3e 3245 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3246 goto out;
c45dcc71 3247 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3248 goto out;
3249 r = 0;
3250 vcpu->arch.mcg_cap = mcg_cap;
3251 /* Init IA32_MCG_CTL to all 1s */
3252 if (mcg_cap & MCG_CTL_P)
3253 vcpu->arch.mcg_ctl = ~(u64)0;
3254 /* Init IA32_MCi_CTL to all 1s */
3255 for (bank = 0; bank < bank_num; bank++)
3256 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3257
3258 if (kvm_x86_ops->setup_mce)
3259 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3260out:
3261 return r;
3262}
3263
3264static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3265 struct kvm_x86_mce *mce)
3266{
3267 u64 mcg_cap = vcpu->arch.mcg_cap;
3268 unsigned bank_num = mcg_cap & 0xff;
3269 u64 *banks = vcpu->arch.mce_banks;
3270
3271 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3272 return -EINVAL;
3273 /*
3274 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3275 * reporting is disabled
3276 */
3277 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3278 vcpu->arch.mcg_ctl != ~(u64)0)
3279 return 0;
3280 banks += 4 * mce->bank;
3281 /*
3282 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3283 * reporting is disabled for the bank
3284 */
3285 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3286 return 0;
3287 if (mce->status & MCI_STATUS_UC) {
3288 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3289 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3290 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3291 return 0;
3292 }
3293 if (banks[1] & MCI_STATUS_VAL)
3294 mce->status |= MCI_STATUS_OVER;
3295 banks[2] = mce->addr;
3296 banks[3] = mce->misc;
3297 vcpu->arch.mcg_status = mce->mcg_status;
3298 banks[1] = mce->status;
3299 kvm_queue_exception(vcpu, MC_VECTOR);
3300 } else if (!(banks[1] & MCI_STATUS_VAL)
3301 || !(banks[1] & MCI_STATUS_UC)) {
3302 if (banks[1] & MCI_STATUS_VAL)
3303 mce->status |= MCI_STATUS_OVER;
3304 banks[2] = mce->addr;
3305 banks[3] = mce->misc;
3306 banks[1] = mce->status;
3307 } else
3308 banks[1] |= MCI_STATUS_OVER;
3309 return 0;
3310}
3311
3cfc3092
JK		 3312static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3313 struct kvm_vcpu_events *events)
3314{
7460fb4a 3315 process_nmi(vcpu);
664f8e26
WL		 3316 /*
3317 * FIXME: pass injected and pending separately. This is only
3318 * needed for nested virtualization, whose state cannot be
3319 * migrated yet. For now we can combine them.
3320 */
03b82a30 3321 events->exception.injected =
664f8e26
WL		 3322 (vcpu->arch.exception.pending ||
3323 vcpu->arch.exception.injected) &&
03b82a30 3324 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3325 events->exception.nr = vcpu->arch.exception.nr;
3326 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3327 events->exception.pad = 0;
3cfc3092
JK		 3328 events->exception.error_code = vcpu->arch.exception.error_code;
3329
03b82a30 3330 events->interrupt.injected =
04140b41 3331 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3332 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3333 events->interrupt.soft = 0;
37ccdcbe 3334 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3335
3336 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3337 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3338 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3339 events->nmi.pad = 0;
3cfc3092 3340
66450a21 3341 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3342
f077825a
PB		 3343 events->smi.smm = is_smm(vcpu);
3344 events->smi.pending = vcpu->arch.smi_pending;
3345 events->smi.smm_inside_nmi =
3346 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3347 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3348
dab4b911 3349 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3350 | KVM_VCPUEVENT_VALID_SHADOW
3351 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3352 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3353}
3354
6ef4e07e
XG		 3355static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3356
3cfc3092
JK		 3357static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3358 struct kvm_vcpu_events *events)
3359{
dab4b911 3360 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3361 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3362 | KVM_VCPUEVENT_VALID_SHADOW
3363 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3364 return -EINVAL;
3365
78e546c8 3366 if (events->exception.injected &&
28d06353
JM		 3367 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3368 is_guest_mode(vcpu)))
78e546c8
PB		 3369 return -EINVAL;
3370
28bf2888
DH		 3371 /* INITs are latched while in SMM */
3372 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3373 (events->smi.smm || events->smi.pending) &&
3374 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3375 return -EINVAL;
3376
7460fb4a 3377 process_nmi(vcpu);
664f8e26 3378 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3379 vcpu->arch.exception.pending = events->exception.injected;
3380 vcpu->arch.exception.nr = events->exception.nr;
3381 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3382 vcpu->arch.exception.error_code = events->exception.error_code;
3383
04140b41 3384 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3385 vcpu->arch.interrupt.nr = events->interrupt.nr;
3386 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3387 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3388 kvm_x86_ops->set_interrupt_shadow(vcpu,
3389 events->interrupt.shadow);
3cfc3092
JK		 3390
3391 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3392 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3393 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3394 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3395
66450a21 3396 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3397 lapic_in_kernel(vcpu))
66450a21 3398 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3399
f077825a 3400 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3401 u32 hflags = vcpu->arch.hflags;
f077825a 3402 if (events->smi.smm)
6ef4e07e 3403 hflags |= HF_SMM_MASK;
f077825a 3404 else
6ef4e07e
XG		 3405 hflags &= ~HF_SMM_MASK;
3406 kvm_set_hflags(vcpu, hflags);
3407
f077825a 3408 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3409
3410 if (events->smi.smm) {
3411 if (events->smi.smm_inside_nmi)
3412 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3413 else
f4ef1910
WL		 3414 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3415 if (lapic_in_kernel(vcpu)) {
3416 if (events->smi.latched_init)
3417 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3418 else
3419 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3420 }
f077825a
PB		 3421 }
3422 }
3423
3842d135
AK		 3424 kvm_make_request(KVM_REQ_EVENT, vcpu);
3425
3cfc3092
JK		 3426 return 0;
3427}
3428
a1efbe77
JK		 3429static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3430 struct kvm_debugregs *dbgregs)
3431{
73aaf249
JK		 3432 unsigned long val;
3433
a1efbe77 3434 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3435 kvm_get_dr(vcpu, 6, &val);
73aaf249 3436 dbgregs->dr6 = val;
a1efbe77
JK		 3437 dbgregs->dr7 = vcpu->arch.dr7;
3438 dbgregs->flags = 0;
97e69aa6 3439 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3440}
3441
3442static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3443 struct kvm_debugregs *dbgregs)
3444{
3445 if (dbgregs->flags)
3446 return -EINVAL;
3447
d14bdb55
PB		 3448 if (dbgregs->dr6 & ~0xffffffffull)
3449 return -EINVAL;
3450 if (dbgregs->dr7 & ~0xffffffffull)
3451 return -EINVAL;
3452
a1efbe77 3453 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3454 kvm_update_dr0123(vcpu);
a1efbe77 3455 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3456 kvm_update_dr6(vcpu);
a1efbe77 3457 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3458 kvm_update_dr7(vcpu);
a1efbe77 3459
a1efbe77
JK		 3460 return 0;
3461}
3462
df1daba7
PB		 3463#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3464
3465static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3466{
c47ada30 3467 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3468 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3469 u64 valid;
3470
3471 /*
3472 * Copy legacy XSAVE area, to avoid complications with CPUID
3473 * leaves 0 and 1 in the loop below.
3474 */
3475 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3476
3477 /* Set XSTATE_BV */
00c87e9a 3478 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3479 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3480
3481 /*
3482 * Copy each region from the possibly compacted offset to the
3483 * non-compacted offset.
3484 */
d91cab78 3485 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3486 while (valid) {
3487 u64 feature = valid & -valid;
3488 int index = fls64(feature) - 1;
3489 void *src = get_xsave_addr(xsave, feature);
3490
3491 if (src) {
3492 u32 size, offset, ecx, edx;
3493 cpuid_count(XSTATE_CPUID, index,
3494 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3495 if (feature == XFEATURE_MASK_PKRU)
3496 memcpy(dest + offset, &vcpu->arch.pkru,
3497 sizeof(vcpu->arch.pkru));
3498 else
3499 memcpy(dest + offset, src, size);
3500
df1daba7
PB		 3501 }
3502
3503 valid -= feature;
3504 }
3505}
3506
3507static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3508{
c47ada30 3509 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3510 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3511 u64 valid;
3512
3513 /*
3514 * Copy legacy XSAVE area, to avoid complications with CPUID
3515 * leaves 0 and 1 in the loop below.
3516 */
3517 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3518
3519 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3520 xsave->header.xfeatures = xstate_bv;
782511b0 3521 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3522 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3523
3524 /*
3525 * Copy each region from the non-compacted offset to the
3526 * possibly compacted offset.
3527 */
d91cab78 3528 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3529 while (valid) {
3530 u64 feature = valid & -valid;
3531 int index = fls64(feature) - 1;
3532 void *dest = get_xsave_addr(xsave, feature);
3533
3534 if (dest) {
3535 u32 size, offset, ecx, edx;
3536 cpuid_count(XSTATE_CPUID, index,
3537 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3538 if (feature == XFEATURE_MASK_PKRU)
3539 memcpy(&vcpu->arch.pkru, src + offset,
3540 sizeof(vcpu->arch.pkru));
3541 else
3542 memcpy(dest, src + offset, size);
ee4100da 3543 }
df1daba7
PB		 3544
3545 valid -= feature;
3546 }
3547}
3548
2d5b5a66
SY		 3549static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3550 struct kvm_xsave *guest_xsave)
3551{
d366bf7e 3552 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3553 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3554 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3555 } else {
2d5b5a66 3556 memcpy(guest_xsave->region,
7366ed77 3557 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3558 sizeof(struct fxregs_state));
2d5b5a66 3559 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3560 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3561 }
3562}
3563
a575813b
WL		 3564#define XSAVE_MXCSR_OFFSET 24
3565
2d5b5a66
SY		 3566static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3567 struct kvm_xsave *guest_xsave)
3568{
3569 u64 xstate_bv =
3570 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3571 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3572
d366bf7e 3573 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3574 /*
3575 * Here we allow setting states that are not present in
3576 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3577 * with old userspace.
3578 */
a575813b
WL		 3579 if (xstate_bv & ~kvm_supported_xcr0() ||
3580 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3581 return -EINVAL;
df1daba7 3582 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3583 } else {
a575813b
WL		 3584 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3585 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3586 return -EINVAL;
7366ed77 3587 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3588 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3589 }
3590 return 0;
3591}
3592
3593static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3594 struct kvm_xcrs *guest_xcrs)
3595{
d366bf7e 3596 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3597 guest_xcrs->nr_xcrs = 0;
3598 return;
3599 }
3600
3601 guest_xcrs->nr_xcrs = 1;
3602 guest_xcrs->flags = 0;
3603 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3604 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3605}
3606
3607static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3608 struct kvm_xcrs *guest_xcrs)
3609{
3610 int i, r = 0;
3611
d366bf7e 3612 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3613 return -EINVAL;
3614
3615 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3616 return -EINVAL;
3617
3618 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3619 /* Only support XCR0 currently */
c67a04cb 3620 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3621 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3622 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3623 break;
3624 }
3625 if (r)
3626 r = -EINVAL;
3627 return r;
3628}
3629
1c0b28c2
EM		 3630/*
3631 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3632 * stopped by the hypervisor. This function will be called from the host only.
3633 * EINVAL is returned when the host attempts to set the flag for a guest that
3634 * does not support pv clocks.
3635 */
3636static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3637{
0b79459b 3638 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3639 return -EINVAL;
51d59c6b 3640 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3641 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3642 return 0;
3643}
3644
5c919412
AS		 3645static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3646 struct kvm_enable_cap *cap)
3647{
3648 if (cap->flags)
3649 return -EINVAL;
3650
3651 switch (cap->cap) {
efc479e6
RK		 3652 case KVM_CAP_HYPERV_SYNIC2:
3653 if (cap->args[0])
3654 return -EINVAL;
5c919412 3655 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3656 if (!irqchip_in_kernel(vcpu->kvm))
3657 return -EINVAL;
efc479e6
RK		 3658 return kvm_hv_activate_synic(vcpu, cap->cap ==
3659 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3660 default:
3661 return -EINVAL;
3662 }
3663}
3664
313a3dc7
CO		 3665long kvm_arch_vcpu_ioctl(struct file *filp,
3666 unsigned int ioctl, unsigned long arg)
3667{
3668 struct kvm_vcpu *vcpu = filp->private_data;
3669 void __user *argp = (void __user *)arg;
3670 int r;
d1ac91d8
AK		 3671 union {
3672 struct kvm_lapic_state *lapic;
3673 struct kvm_xsave *xsave;
3674 struct kvm_xcrs *xcrs;
3675 void *buffer;
3676 } u;
3677
9b062471
CD		 3678 vcpu_load(vcpu);
3679
d1ac91d8 3680 u.buffer = NULL;
313a3dc7
CO		 3681 switch (ioctl) {
3682 case KVM_GET_LAPIC: {
2204ae3c 3683 r = -EINVAL;
bce87cce 3684 if (!lapic_in_kernel(vcpu))
2204ae3c 3685 goto out;
d1ac91d8 3686 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3687
b772ff36 3688 r = -ENOMEM;
d1ac91d8 3689 if (!u.lapic)
b772ff36 3690 goto out;
d1ac91d8 3691 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3692 if (r)
3693 goto out;
3694 r = -EFAULT;
d1ac91d8 3695 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3696 goto out;
3697 r = 0;
3698 break;
3699 }
3700 case KVM_SET_LAPIC: {
2204ae3c 3701 r = -EINVAL;
bce87cce 3702 if (!lapic_in_kernel(vcpu))
2204ae3c 3703 goto out;
ff5c2c03 3704 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3705 if (IS_ERR(u.lapic)) {
3706 r = PTR_ERR(u.lapic);
3707 goto out_nofree;
3708 }
ff5c2c03 3709
d1ac91d8 3710 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3711 break;
3712 }
f77bc6a4
ZX		 3713 case KVM_INTERRUPT: {
3714 struct kvm_interrupt irq;
3715
3716 r = -EFAULT;
3717 if (copy_from_user(&irq, argp, sizeof irq))
3718 goto out;
3719 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3720 break;
3721 }
c4abb7c9
JK		 3722 case KVM_NMI: {
3723 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3724 break;
3725 }
f077825a
PB		 3726 case KVM_SMI: {
3727 r = kvm_vcpu_ioctl_smi(vcpu);
3728 break;
3729 }
313a3dc7
CO		 3730 case KVM_SET_CPUID: {
3731 struct kvm_cpuid __user *cpuid_arg = argp;
3732 struct kvm_cpuid cpuid;
3733
3734 r = -EFAULT;
3735 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3736 goto out;
3737 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3738 break;
3739 }
07716717
DK		 3740 case KVM_SET_CPUID2: {
3741 struct kvm_cpuid2 __user *cpuid_arg = argp;
3742 struct kvm_cpuid2 cpuid;
3743
3744 r = -EFAULT;
3745 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3746 goto out;
3747 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3748 cpuid_arg->entries);
07716717
DK		 3749 break;
3750 }
3751 case KVM_GET_CPUID2: {
3752 struct kvm_cpuid2 __user *cpuid_arg = argp;
3753 struct kvm_cpuid2 cpuid;
3754
3755 r = -EFAULT;
3756 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3757 goto out;
3758 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3759 cpuid_arg->entries);
07716717
DK		 3760 if (r)
3761 goto out;
3762 r = -EFAULT;
3763 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3764 goto out;
3765 r = 0;
3766 break;
3767 }
801e459a
TL		 3768 case KVM_GET_MSRS: {
3769 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3770 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3771 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3772 break;
801e459a
TL		 3773 }
3774 case KVM_SET_MSRS: {
3775 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3776 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3777 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3778 break;
801e459a 3779 }
b209749f
AK		 3780 case KVM_TPR_ACCESS_REPORTING: {
3781 struct kvm_tpr_access_ctl tac;
3782
3783 r = -EFAULT;
3784 if (copy_from_user(&tac, argp, sizeof tac))
3785 goto out;
3786 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3787 if (r)
3788 goto out;
3789 r = -EFAULT;
3790 if (copy_to_user(argp, &tac, sizeof tac))
3791 goto out;
3792 r = 0;
3793 break;
3794 };
b93463aa
AK		 3795 case KVM_SET_VAPIC_ADDR: {
3796 struct kvm_vapic_addr va;
7301d6ab 3797 int idx;
b93463aa
AK		 3798
3799 r = -EINVAL;
35754c98 3800 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3801 goto out;
3802 r = -EFAULT;
3803 if (copy_from_user(&va, argp, sizeof va))
3804 goto out;
7301d6ab 3805 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3806 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3807 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3808 break;
3809 }
890ca9ae
HY		 3810 case KVM_X86_SETUP_MCE: {
3811 u64 mcg_cap;
3812
3813 r = -EFAULT;
3814 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3815 goto out;
3816 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3817 break;
3818 }
3819 case KVM_X86_SET_MCE: {
3820 struct kvm_x86_mce mce;
3821
3822 r = -EFAULT;
3823 if (copy_from_user(&mce, argp, sizeof mce))
3824 goto out;
3825 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3826 break;
3827 }
3cfc3092
JK		 3828 case KVM_GET_VCPU_EVENTS: {
3829 struct kvm_vcpu_events events;
3830
3831 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3832
3833 r = -EFAULT;
3834 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3835 break;
3836 r = 0;
3837 break;
3838 }
3839 case KVM_SET_VCPU_EVENTS: {
3840 struct kvm_vcpu_events events;
3841
3842 r = -EFAULT;
3843 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3844 break;
3845
3846 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3847 break;
3848 }
a1efbe77
JK		 3849 case KVM_GET_DEBUGREGS: {
3850 struct kvm_debugregs dbgregs;
3851
3852 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3853
3854 r = -EFAULT;
3855 if (copy_to_user(argp, &dbgregs,
3856 sizeof(struct kvm_debugregs)))
3857 break;
3858 r = 0;
3859 break;
3860 }
3861 case KVM_SET_DEBUGREGS: {
3862 struct kvm_debugregs dbgregs;
3863
3864 r = -EFAULT;
3865 if (copy_from_user(&dbgregs, argp,
3866 sizeof(struct kvm_debugregs)))
3867 break;
3868
3869 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3870 break;
3871 }
2d5b5a66 3872 case KVM_GET_XSAVE: {
d1ac91d8 3873 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3874 r = -ENOMEM;
d1ac91d8 3875 if (!u.xsave)
2d5b5a66
SY		 3876 break;
3877
d1ac91d8 3878 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3879
3880 r = -EFAULT;
d1ac91d8 3881 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3882 break;
3883 r = 0;
3884 break;
3885 }
3886 case KVM_SET_XSAVE: {
ff5c2c03 3887 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3888 if (IS_ERR(u.xsave)) {
3889 r = PTR_ERR(u.xsave);
3890 goto out_nofree;
3891 }
2d5b5a66 3892
d1ac91d8 3893 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3894 break;
3895 }
3896 case KVM_GET_XCRS: {
d1ac91d8 3897 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3898 r = -ENOMEM;
d1ac91d8 3899 if (!u.xcrs)
2d5b5a66
SY		 3900 break;
3901
d1ac91d8 3902 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3903
3904 r = -EFAULT;
d1ac91d8 3905 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3906 sizeof(struct kvm_xcrs)))
3907 break;
3908 r = 0;
3909 break;
3910 }
3911 case KVM_SET_XCRS: {
ff5c2c03 3912 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3913 if (IS_ERR(u.xcrs)) {
3914 r = PTR_ERR(u.xcrs);
3915 goto out_nofree;
3916 }
2d5b5a66 3917
d1ac91d8 3918 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3919 break;
3920 }
92a1f12d
JR		 3921 case KVM_SET_TSC_KHZ: {
3922 u32 user_tsc_khz;
3923
3924 r = -EINVAL;
92a1f12d
JR		 3925 user_tsc_khz = (u32)arg;
3926
3927 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3928 goto out;
3929
cc578287
ZA		 3930 if (user_tsc_khz == 0)
3931 user_tsc_khz = tsc_khz;
3932
381d585c
HZ		 3933 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3934 r = 0;
92a1f12d 3935
92a1f12d
JR		 3936 goto out;
3937 }
3938 case KVM_GET_TSC_KHZ: {
cc578287 3939 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3940 goto out;
3941 }
1c0b28c2
EM		 3942 case KVM_KVMCLOCK_CTRL: {
3943 r = kvm_set_guest_paused(vcpu);
3944 goto out;
3945 }
5c919412
AS		 3946 case KVM_ENABLE_CAP: {
3947 struct kvm_enable_cap cap;
3948
3949 r = -EFAULT;
3950 if (copy_from_user(&cap, argp, sizeof(cap)))
3951 goto out;
3952 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3953 break;
3954 }
313a3dc7
CO		 3955 default:
3956 r = -EINVAL;
3957 }
3958out:
d1ac91d8 3959 kfree(u.buffer);
9b062471
CD		 3960out_nofree:
3961 vcpu_put(vcpu);
313a3dc7
CO		 3962 return r;
3963}
3964
5b1c1493
CO		 3965int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3966{
3967 return VM_FAULT_SIGBUS;
3968}
3969
1fe779f8
CO		 3970static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3971{
3972 int ret;
3973
3974 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3975 return -EINVAL;
1fe779f8
CO		 3976 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3977 return ret;
3978}
3979
b927a3ce
SY		 3980static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3981 u64 ident_addr)
3982{
2ac52ab8 3983 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3984}
3985
1fe779f8
CO		 3986static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3987 u32 kvm_nr_mmu_pages)
3988{
3989 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3990 return -EINVAL;
3991
79fac95e 3992 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3993
3994 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3995 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3996
79fac95e 3997 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3998 return 0;
3999}
4000
4001static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4002{
39de71ec 4003 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4004}
4005
1fe779f8
CO		 4006static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4007{
90bca052 4008 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4009 int r;
4010
4011 r = 0;
4012 switch (chip->chip_id) {
4013 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4014 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4015 sizeof(struct kvm_pic_state));
4016 break;
4017 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4018 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4019 sizeof(struct kvm_pic_state));
4020 break;
4021 case KVM_IRQCHIP_IOAPIC:
33392b49 4022 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4023 break;
4024 default:
4025 r = -EINVAL;
4026 break;
4027 }
4028 return r;
4029}
4030
4031static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4032{
90bca052 4033 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4034 int r;
4035
4036 r = 0;
4037 switch (chip->chip_id) {
4038 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4039 spin_lock(&pic->lock);
4040 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4041 sizeof(struct kvm_pic_state));
90bca052 4042 spin_unlock(&pic->lock);
1fe779f8
CO		 4043 break;
4044 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4045 spin_lock(&pic->lock);
4046 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4047 sizeof(struct kvm_pic_state));
90bca052 4048 spin_unlock(&pic->lock);
1fe779f8
CO		 4049 break;
4050 case KVM_IRQCHIP_IOAPIC:
33392b49 4051 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4052 break;
4053 default:
4054 r = -EINVAL;
4055 break;
4056 }
90bca052 4057 kvm_pic_update_irq(pic);
1fe779f8
CO		 4058 return r;
4059}
4060
e0f63cb9
SY		 4061static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4062{
34f3941c
RK		 4063 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4064
4065 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4066
4067 mutex_lock(&kps->lock);
4068 memcpy(ps, &kps->channels, sizeof(*ps));
4069 mutex_unlock(&kps->lock);
2da29bcc 4070 return 0;
e0f63cb9
SY		 4071}
4072
4073static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4074{
0185604c 4075 int i;
09edea72
RK		 4076 struct kvm_pit *pit = kvm->arch.vpit;
4077
4078 mutex_lock(&pit->pit_state.lock);
34f3941c 4079 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4080 for (i = 0; i < 3; i++)
09edea72
RK		 4081 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4082 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4083 return 0;
e9f42757
BK		 4084}
4085
4086static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4087{
e9f42757
BK		 4088 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4089 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4090 sizeof(ps->channels));
4091 ps->flags = kvm->arch.vpit->pit_state.flags;
4092 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4093 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4094 return 0;
e9f42757
BK		 4095}
4096
4097static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4098{
2da29bcc 4099 int start = 0;
0185604c 4100 int i;
e9f42757 4101 u32 prev_legacy, cur_legacy;
09edea72
RK		 4102 struct kvm_pit *pit = kvm->arch.vpit;
4103
4104 mutex_lock(&pit->pit_state.lock);
4105 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4106 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4107 if (!prev_legacy && cur_legacy)
4108 start = 1;
09edea72
RK		 4109 memcpy(&pit->pit_state.channels, &ps->channels,
4110 sizeof(pit->pit_state.channels));
4111 pit->pit_state.flags = ps->flags;
0185604c 4112 for (i = 0; i < 3; i++)
09edea72 4113 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4114 start && i == 0);
09edea72 4115 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4116 return 0;
e0f63cb9
SY		 4117}
4118
52d939a0
MT		 4119static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4120 struct kvm_reinject_control *control)
4121{
71474e2f
RK		 4122 struct kvm_pit *pit = kvm->arch.vpit;
4123
4124 if (!pit)
52d939a0 4125 return -ENXIO;
b39c90b6 4126
71474e2f
RK		 4127 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4128 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4129 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4130 */
4131 mutex_lock(&pit->pit_state.lock);
4132 kvm_pit_set_reinject(pit, control->pit_reinject);
4133 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4134
52d939a0
MT		 4135 return 0;
4136}
4137
95d4c16c 4138/**
60c34612
TY		 4139 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4140 * @kvm: kvm instance
4141 * @log: slot id and address to which we copy the log
95d4c16c 4142 *
e108ff2f
PB		 4143 * Steps 1-4 below provide general overview of dirty page logging. See
4144 * kvm_get_dirty_log_protect() function description for additional details.
4145 *
4146 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4147 * always flush the TLB (step 4) even if previous step failed and the dirty
4148 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4149 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4150 * writes will be marked dirty for next log read.
95d4c16c 4151 *
60c34612
TY		 4152 * 1. Take a snapshot of the bit and clear it if needed.
4153 * 2. Write protect the corresponding page.
e108ff2f
PB		 4154 * 3. Copy the snapshot to the userspace.
4155 * 4. Flush TLB's if needed.
5bb064dc 4156 */
60c34612 4157int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4158{
60c34612 4159 bool is_dirty = false;
e108ff2f 4160 int r;
5bb064dc 4161
79fac95e 4162 mutex_lock(&kvm->slots_lock);
5bb064dc 4163
88178fd4
KH		 4164 /*
4165 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4166 */
4167 if (kvm_x86_ops->flush_log_dirty)
4168 kvm_x86_ops->flush_log_dirty(kvm);
4169
e108ff2f 4170 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4171
4172 /*
4173 * All the TLBs can be flushed out of mmu lock, see the comments in
4174 * kvm_mmu_slot_remove_write_access().
4175 */
e108ff2f 4176 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4177 if (is_dirty)
4178 kvm_flush_remote_tlbs(kvm);
4179
79fac95e 4180 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4181 return r;
4182}
4183
aa2fbe6d
YZ		 4184int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4185 bool line_status)
23d43cf9
CD		 4186{
4187 if (!irqchip_in_kernel(kvm))
4188 return -ENXIO;
4189
4190 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4191 irq_event->irq, irq_event->level,
4192 line_status);
23d43cf9
CD		 4193 return 0;
4194}
4195
90de4a18
NA		 4196static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4197 struct kvm_enable_cap *cap)
4198{
4199 int r;
4200
4201 if (cap->flags)
4202 return -EINVAL;
4203
4204 switch (cap->cap) {
4205 case KVM_CAP_DISABLE_QUIRKS:
4206 kvm->arch.disabled_quirks = cap->args[0];
4207 r = 0;
4208 break;
49df6397
SR		 4209 case KVM_CAP_SPLIT_IRQCHIP: {
4210 mutex_lock(&kvm->lock);
b053b2ae
SR		 4211 r = -EINVAL;
4212 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4213 goto split_irqchip_unlock;
49df6397
SR		 4214 r = -EEXIST;
4215 if (irqchip_in_kernel(kvm))
4216 goto split_irqchip_unlock;
557abc40 4217 if (kvm->created_vcpus)
49df6397
SR		 4218 goto split_irqchip_unlock;
4219 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4220 if (r)
49df6397
SR		 4221 goto split_irqchip_unlock;
4222 /* Pairs with irqchip_in_kernel. */
4223 smp_wmb();
49776faf 4224 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4225 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4226 r = 0;
4227split_irqchip_unlock:
4228 mutex_unlock(&kvm->lock);
4229 break;
4230 }
37131313
RK		 4231 case KVM_CAP_X2APIC_API:
4232 r = -EINVAL;
4233 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4234 break;
4235
4236 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4237 kvm->arch.x2apic_format = true;
c519265f
RK		 4238 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4239 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4240
4241 r = 0;
4242 break;
4d5422ce
WL		 4243 case KVM_CAP_X86_DISABLE_EXITS:
4244 r = -EINVAL;
4245 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4246 break;
4247
4248 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4249 kvm_can_mwait_in_guest())
4250 kvm->arch.mwait_in_guest = true;
caa057a2
WL		 4251 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HTL)
4252 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4253 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4254 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4255 r = 0;
4256 break;
90de4a18
NA		 4257 default:
4258 r = -EINVAL;
4259 break;
4260 }
4261 return r;
4262}
4263
1fe779f8
CO		 4264long kvm_arch_vm_ioctl(struct file *filp,
4265 unsigned int ioctl, unsigned long arg)
4266{
4267 struct kvm *kvm = filp->private_data;
4268 void __user *argp = (void __user *)arg;
367e1319 4269 int r = -ENOTTY;
f0d66275
DH		 4270 /*
4271 * This union makes it completely explicit to gcc-3.x
4272 * that these two variables' stack usage should be
4273 * combined, not added together.
4274 */
4275 union {
4276 struct kvm_pit_state ps;
e9f42757 4277 struct kvm_pit_state2 ps2;
c5ff41ce 4278 struct kvm_pit_config pit_config;
f0d66275 4279 } u;
1fe779f8
CO		 4280
4281 switch (ioctl) {
4282 case KVM_SET_TSS_ADDR:
4283 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4284 break;
b927a3ce
SY		 4285 case KVM_SET_IDENTITY_MAP_ADDR: {
4286 u64 ident_addr;
4287
1af1ac91
DH		 4288 mutex_lock(&kvm->lock);
4289 r = -EINVAL;
4290 if (kvm->created_vcpus)
4291 goto set_identity_unlock;
b927a3ce
SY		 4292 r = -EFAULT;
4293 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4294 goto set_identity_unlock;
b927a3ce 4295 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4296set_identity_unlock:
4297 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4298 break;
4299 }
1fe779f8
CO		 4300 case KVM_SET_NR_MMU_PAGES:
4301 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4302 break;
4303 case KVM_GET_NR_MMU_PAGES:
4304 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4305 break;
3ddea128 4306 case KVM_CREATE_IRQCHIP: {
3ddea128 4307 mutex_lock(&kvm->lock);
09941366 4308
3ddea128 4309 r = -EEXIST;
35e6eaa3 4310 if (irqchip_in_kernel(kvm))
3ddea128 4311 goto create_irqchip_unlock;
09941366 4312
3e515705 4313 r = -EINVAL;
557abc40 4314 if (kvm->created_vcpus)
3e515705 4315 goto create_irqchip_unlock;
09941366
RK		 4316
4317 r = kvm_pic_init(kvm);
4318 if (r)
3ddea128 4319 goto create_irqchip_unlock;
09941366
RK		 4320
4321 r = kvm_ioapic_init(kvm);
4322 if (r) {
09941366 4323 kvm_pic_destroy(kvm);
3ddea128 4324 goto create_irqchip_unlock;
09941366
RK		 4325 }
4326
399ec807
AK		 4327 r = kvm_setup_default_irq_routing(kvm);
4328 if (r) {
72bb2fcd 4329 kvm_ioapic_destroy(kvm);
09941366 4330 kvm_pic_destroy(kvm);
71ba994c 4331 goto create_irqchip_unlock;
399ec807 4332 }
49776faf 4333 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4334 smp_wmb();
49776faf 4335 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4336 create_irqchip_unlock:
4337 mutex_unlock(&kvm->lock);
1fe779f8 4338 break;
3ddea128 4339 }
7837699f 4340 case KVM_CREATE_PIT:
c5ff41ce
JK		 4341 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4342 goto create_pit;
4343 case KVM_CREATE_PIT2:
4344 r = -EFAULT;
4345 if (copy_from_user(&u.pit_config, argp,
4346 sizeof(struct kvm_pit_config)))
4347 goto out;
4348 create_pit:
250715a6 4349 mutex_lock(&kvm->lock);
269e05e4
AK		 4350 r = -EEXIST;
4351 if (kvm->arch.vpit)
4352 goto create_pit_unlock;
7837699f 4353 r = -ENOMEM;
c5ff41ce 4354 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4355 if (kvm->arch.vpit)
4356 r = 0;
269e05e4 4357 create_pit_unlock:
250715a6 4358 mutex_unlock(&kvm->lock);
7837699f 4359 break;
1fe779f8
CO		 4360 case KVM_GET_IRQCHIP: {
4361 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4362 struct kvm_irqchip *chip;
1fe779f8 4363
ff5c2c03
SL		 4364 chip = memdup_user(argp, sizeof(*chip));
4365 if (IS_ERR(chip)) {
4366 r = PTR_ERR(chip);
1fe779f8 4367 goto out;
ff5c2c03
SL		 4368 }
4369
1fe779f8 4370 r = -ENXIO;
826da321 4371 if (!irqchip_kernel(kvm))
f0d66275
DH		 4372 goto get_irqchip_out;
4373 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4374 if (r)
f0d66275 4375 goto get_irqchip_out;
1fe779f8 4376 r = -EFAULT;
f0d66275
DH		 4377 if (copy_to_user(argp, chip, sizeof *chip))
4378 goto get_irqchip_out;
1fe779f8 4379 r = 0;
f0d66275
DH		 4380 get_irqchip_out:
4381 kfree(chip);
1fe779f8
CO		 4382 break;
4383 }
4384 case KVM_SET_IRQCHIP: {
4385 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4386 struct kvm_irqchip *chip;
1fe779f8 4387
ff5c2c03
SL		 4388 chip = memdup_user(argp, sizeof(*chip));
4389 if (IS_ERR(chip)) {
4390 r = PTR_ERR(chip);
1fe779f8 4391 goto out;
ff5c2c03
SL		 4392 }
4393
1fe779f8 4394 r = -ENXIO;
826da321 4395 if (!irqchip_kernel(kvm))
f0d66275
DH		 4396 goto set_irqchip_out;
4397 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4398 if (r)
f0d66275 4399 goto set_irqchip_out;
1fe779f8 4400 r = 0;
f0d66275
DH		 4401 set_irqchip_out:
4402 kfree(chip);
1fe779f8
CO		 4403 break;
4404 }
e0f63cb9 4405 case KVM_GET_PIT: {
e0f63cb9 4406 r = -EFAULT;
f0d66275 4407 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4408 goto out;
4409 r = -ENXIO;
4410 if (!kvm->arch.vpit)
4411 goto out;
f0d66275 4412 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4413 if (r)
4414 goto out;
4415 r = -EFAULT;
f0d66275 4416 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4417 goto out;
4418 r = 0;
4419 break;
4420 }
4421 case KVM_SET_PIT: {
e0f63cb9 4422 r = -EFAULT;
f0d66275 4423 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4424 goto out;
4425 r = -ENXIO;
4426 if (!kvm->arch.vpit)
4427 goto out;
f0d66275 4428 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4429 break;
4430 }
e9f42757
BK		 4431 case KVM_GET_PIT2: {
4432 r = -ENXIO;
4433 if (!kvm->arch.vpit)
4434 goto out;
4435 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4436 if (r)
4437 goto out;
4438 r = -EFAULT;
4439 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4440 goto out;
4441 r = 0;
4442 break;
4443 }
4444 case KVM_SET_PIT2: {
4445 r = -EFAULT;
4446 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4447 goto out;
4448 r = -ENXIO;
4449 if (!kvm->arch.vpit)
4450 goto out;
4451 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4452 break;
4453 }
52d939a0
MT		 4454 case KVM_REINJECT_CONTROL: {
4455 struct kvm_reinject_control control;
4456 r = -EFAULT;
4457 if (copy_from_user(&control, argp, sizeof(control)))
4458 goto out;
4459 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4460 break;
4461 }
d71ba788
PB		 4462 case KVM_SET_BOOT_CPU_ID:
4463 r = 0;
4464 mutex_lock(&kvm->lock);
557abc40 4465 if (kvm->created_vcpus)
d71ba788
PB		 4466 r = -EBUSY;
4467 else
4468 kvm->arch.bsp_vcpu_id = arg;
4469 mutex_unlock(&kvm->lock);
4470 break;
ffde22ac 4471 case KVM_XEN_HVM_CONFIG: {
51776043 4472 struct kvm_xen_hvm_config xhc;
ffde22ac 4473 r = -EFAULT;
51776043 4474 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4475 goto out;
4476 r = -EINVAL;
51776043 4477 if (xhc.flags)
ffde22ac 4478 goto out;
51776043 4479 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4480 r = 0;
4481 break;
4482 }
afbcf7ab 4483 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4484 struct kvm_clock_data user_ns;
4485 u64 now_ns;
afbcf7ab
GC		 4486
4487 r = -EFAULT;
4488 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4489 goto out;
4490
4491 r = -EINVAL;
4492 if (user_ns.flags)
4493 goto out;
4494
4495 r = 0;
0bc48bea
RK		 4496 /*
4497 * TODO: userspace has to take care of races with VCPU_RUN, so
4498 * kvm_gen_update_masterclock() can be cut down to locked
4499 * pvclock_update_vm_gtod_copy().
4500 */
4501 kvm_gen_update_masterclock(kvm);
e891a32e 4502 now_ns = get_kvmclock_ns(kvm);
108b249c 4503 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4504 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4505 break;
4506 }
4507 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4508 struct kvm_clock_data user_ns;
4509 u64 now_ns;
4510
e891a32e 4511 now_ns = get_kvmclock_ns(kvm);
108b249c 4512 user_ns.clock = now_ns;
e3fd9a93 4513 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4514 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4515
4516 r = -EFAULT;
4517 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4518 goto out;
4519 r = 0;
4520 break;
4521 }
90de4a18
NA		 4522 case KVM_ENABLE_CAP: {
4523 struct kvm_enable_cap cap;
afbcf7ab 4524
90de4a18
NA		 4525 r = -EFAULT;
4526 if (copy_from_user(&cap, argp, sizeof(cap)))
4527 goto out;
4528 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4529 break;
4530 }
5acc5c06
BS		 4531 case KVM_MEMORY_ENCRYPT_OP: {
4532 r = -ENOTTY;
4533 if (kvm_x86_ops->mem_enc_op)
4534 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4535 break;
4536 }
69eaedee
BS		 4537 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4538 struct kvm_enc_region region;
4539
4540 r = -EFAULT;
4541 if (copy_from_user(&region, argp, sizeof(region)))
4542 goto out;
4543
4544 r = -ENOTTY;
4545 if (kvm_x86_ops->mem_enc_reg_region)
4546 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4547 break;
4548 }
4549 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4550 struct kvm_enc_region region;
4551
4552 r = -EFAULT;
4553 if (copy_from_user(&region, argp, sizeof(region)))
4554 goto out;
4555
4556 r = -ENOTTY;
4557 if (kvm_x86_ops->mem_enc_unreg_region)
4558 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4559 break;
4560 }
faeb7833
RK		 4561 case KVM_HYPERV_EVENTFD: {
4562 struct kvm_hyperv_eventfd hvevfd;
4563
4564 r = -EFAULT;
4565 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4566 goto out;
4567 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4568 break;
4569 }
1fe779f8 4570 default:
ad6260da 4571 r = -ENOTTY;
1fe779f8
CO		 4572 }
4573out:
4574 return r;
4575}
4576
a16b043c 4577static void kvm_init_msr_list(void)
043405e1
CO		 4578{
4579 u32 dummy[2];
4580 unsigned i, j;
4581
62ef68bb 4582 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4583 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4584 continue;
93c4adc7
PB		 4585
4586 /*
4587 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4588 * to the guests in some cases.
93c4adc7
PB		 4589 */
4590 switch (msrs_to_save[i]) {
4591 case MSR_IA32_BNDCFGS:
4592 if (!kvm_x86_ops->mpx_supported())
4593 continue;
4594 break;
9dbe6cf9
PB		 4595 case MSR_TSC_AUX:
4596 if (!kvm_x86_ops->rdtscp_supported())
4597 continue;
4598 break;
93c4adc7
PB		 4599 default:
4600 break;
4601 }
4602
043405e1
CO		 4603 if (j < i)
4604 msrs_to_save[j] = msrs_to_save[i];
4605 j++;
4606 }
4607 num_msrs_to_save = j;
62ef68bb
PB		 4608
4609 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4610 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4611 continue;
62ef68bb
PB		 4612
4613 if (j < i)
4614 emulated_msrs[j] = emulated_msrs[i];
4615 j++;
4616 }
4617 num_emulated_msrs = j;
801e459a
TL		 4618
4619 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4620 struct kvm_msr_entry msr;
4621
4622 msr.index = msr_based_features[i];
66421c1e 4623 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4624 continue;
4625
4626 if (j < i)
4627 msr_based_features[j] = msr_based_features[i];
4628 j++;
4629 }
4630 num_msr_based_features = j;
043405e1
CO		 4631}
4632
bda9020e
MT		 4633static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4634 const void *v)
bbd9b64e 4635{
70252a10
AK		 4636 int handled = 0;
4637 int n;
4638
4639 do {
4640 n = min(len, 8);
bce87cce 4641 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4642 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4643 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4644 break;
4645 handled += n;
4646 addr += n;
4647 len -= n;
4648 v += n;
4649 } while (len);
bbd9b64e 4650
70252a10 4651 return handled;
bbd9b64e
CO		 4652}
4653
bda9020e 4654static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4655{
70252a10
AK		 4656 int handled = 0;
4657 int n;
4658
4659 do {
4660 n = min(len, 8);
bce87cce 4661 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4662 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4663 addr, n, v))
4664 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4665 break;
e39d200f 4666 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4667 handled += n;
4668 addr += n;
4669 len -= n;
4670 v += n;
4671 } while (len);
bbd9b64e 4672
70252a10 4673 return handled;
bbd9b64e
CO		 4674}
4675
2dafc6c2
GN		 4676static void kvm_set_segment(struct kvm_vcpu *vcpu,
4677 struct kvm_segment *var, int seg)
4678{
4679 kvm_x86_ops->set_segment(vcpu, var, seg);
4680}
4681
4682void kvm_get_segment(struct kvm_vcpu *vcpu,
4683 struct kvm_segment *var, int seg)
4684{
4685 kvm_x86_ops->get_segment(vcpu, var, seg);
4686}
4687
54987b7a
PB		 4688gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4689 struct x86_exception *exception)
02f59dc9
JR		 4690{
4691 gpa_t t_gpa;
02f59dc9
JR		 4692
4693 BUG_ON(!mmu_is_nested(vcpu));
4694
4695 /* NPT walks are always user-walks */
4696 access |= PFERR_USER_MASK;
54987b7a 4697 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4698
4699 return t_gpa;
4700}
4701
ab9ae313
AK		 4702gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4703 struct x86_exception *exception)
1871c602
GN		 4704{
4705 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4706 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4707}
4708
ab9ae313
AK		 4709 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4710 struct x86_exception *exception)
1871c602
GN		 4711{
4712 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4713 access |= PFERR_FETCH_MASK;
ab9ae313 4714 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4715}
4716
ab9ae313
AK		 4717gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4718 struct x86_exception *exception)
1871c602
GN		 4719{
4720 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4721 access |= PFERR_WRITE_MASK;
ab9ae313 4722 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4723}
4724
4725/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4726gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4727 struct x86_exception *exception)
1871c602 4728{
ab9ae313 4729 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4730}
4731
4732static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4733 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4734 struct x86_exception *exception)
bbd9b64e
CO		 4735{
4736 void *data = val;
10589a46 4737 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4738
4739 while (bytes) {
14dfe855 4740 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4741 exception);
bbd9b64e 4742 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4743 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4744 int ret;
4745
bcc55cba 4746 if (gpa == UNMAPPED_GVA)
ab9ae313 4747 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4748 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4749 offset, toread);
10589a46 4750 if (ret < 0) {
c3cd7ffa 4751 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4752 goto out;
4753 }
bbd9b64e 4754
77c2002e
IE		 4755 bytes -= toread;
4756 data += toread;
4757 addr += toread;
bbd9b64e 4758 }
10589a46 4759out:
10589a46 4760 return r;
bbd9b64e 4761}
77c2002e 4762
1871c602 4763/* used for instruction fetching */
0f65dd70
AK		 4764static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4765 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4766 struct x86_exception *exception)
1871c602 4767{
0f65dd70 4768 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4769 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4770 unsigned offset;
4771 int ret;
0f65dd70 4772
44583cba
PB		 4773 /* Inline kvm_read_guest_virt_helper for speed. */
4774 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4775 exception);
4776 if (unlikely(gpa == UNMAPPED_GVA))
4777 return X86EMUL_PROPAGATE_FAULT;
4778
4779 offset = addr & (PAGE_SIZE-1);
4780 if (WARN_ON(offset + bytes > PAGE_SIZE))
4781 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4782 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4783 offset, bytes);
44583cba
PB		 4784 if (unlikely(ret < 0))
4785 return X86EMUL_IO_NEEDED;
4786
4787 return X86EMUL_CONTINUE;
1871c602
GN		 4788}
4789
064aea77 4790int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4791 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4792 struct x86_exception *exception)
1871c602 4793{
0f65dd70 4794 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4795 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4796
1871c602 4797 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4798 exception);
1871c602 4799}
064aea77 4800EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4801
0f65dd70
AK		 4802static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4803 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4804 struct x86_exception *exception)
1871c602 4805{
0f65dd70 4806 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4807 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4808}
4809
7a036a6f
RK		 4810static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4811 unsigned long addr, void *val, unsigned int bytes)
4812{
4813 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4814 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4815
4816 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4817}
4818
6a4d7550 4819int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4820 gva_t addr, void *val,
2dafc6c2 4821 unsigned int bytes,
bcc55cba 4822 struct x86_exception *exception)
77c2002e 4823{
0f65dd70 4824 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4825 void *data = val;
4826 int r = X86EMUL_CONTINUE;
4827
4828 while (bytes) {
14dfe855
JR		 4829 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4830 PFERR_WRITE_MASK,
ab9ae313 4831 exception);
77c2002e
IE		 4832 unsigned offset = addr & (PAGE_SIZE-1);
4833 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4834 int ret;
4835
bcc55cba 4836 if (gpa == UNMAPPED_GVA)
ab9ae313 4837 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4838 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4839 if (ret < 0) {
c3cd7ffa 4840 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4841 goto out;
4842 }
4843
4844 bytes -= towrite;
4845 data += towrite;
4846 addr += towrite;
4847 }
4848out:
4849 return r;
4850}
6a4d7550 4851EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4852
082d06ed
WL		 4853int handle_ud(struct kvm_vcpu *vcpu)
4854{
6c86eedc 4855 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 4856 enum emulation_result er;
6c86eedc
WL		 4857 char sig[5]; /* ud2; .ascii "kvm" */
4858 struct x86_exception e;
4859
4860 if (force_emulation_prefix &&
4861 kvm_read_guest_virt(&vcpu->arch.emulate_ctxt,
4862 kvm_get_linear_rip(vcpu), sig, sizeof(sig), &e) == 0 &&
4863 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4864 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4865 emul_type = 0;
4866 }
082d06ed 4867
6c86eedc 4868 er = emulate_instruction(vcpu, emul_type);
082d06ed
WL		 4869 if (er == EMULATE_USER_EXIT)
4870 return 0;
4871 if (er != EMULATE_DONE)
4872 kvm_queue_exception(vcpu, UD_VECTOR);
4873 return 1;
4874}
4875EXPORT_SYMBOL_GPL(handle_ud);
4876
0f89b207
TL		 4877static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4878 gpa_t gpa, bool write)
4879{
4880 /* For APIC access vmexit */
4881 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4882 return 1;
4883
4884 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4885 trace_vcpu_match_mmio(gva, gpa, write, true);
4886 return 1;
4887 }
4888
4889 return 0;
4890}
4891
af7cc7d1
XG		 4892static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4893 gpa_t *gpa, struct x86_exception *exception,
4894 bool write)
4895{
97d64b78
AK		 4896 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4897 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4898
be94f6b7
HH		 4899 /*
4900 * currently PKRU is only applied to ept enabled guest so
4901 * there is no pkey in EPT page table for L1 guest or EPT
4902 * shadow page table for L2 guest.
4903 */
97d64b78 4904 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4905 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4906 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4907 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4908 (gva & (PAGE_SIZE - 1));
4f022648 4909 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4910 return 1;
4911 }
4912
af7cc7d1
XG		 4913 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4914
4915 if (*gpa == UNMAPPED_GVA)
4916 return -1;
4917
0f89b207 4918 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4919}
4920
3200f405 4921int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4922 const void *val, int bytes)
bbd9b64e
CO		 4923{
4924 int ret;
4925
54bf36aa 4926 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4927 if (ret < 0)
bbd9b64e 4928 return 0;
0eb05bf2 4929 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4930 return 1;
4931}
4932
77d197b2
XG		 4933struct read_write_emulator_ops {
4934 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4935 int bytes);
4936 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4937 void *val, int bytes);
4938 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4939 int bytes, void *val);
4940 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4941 void *val, int bytes);
4942 bool write;
4943};
4944
4945static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4946{
4947 if (vcpu->mmio_read_completed) {
77d197b2 4948 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4949 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4950 vcpu->mmio_read_completed = 0;
4951 return 1;
4952 }
4953
4954 return 0;
4955}
4956
4957static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4958 void *val, int bytes)
4959{
54bf36aa 4960 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4961}
4962
4963static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4964 void *val, int bytes)
4965{
4966 return emulator_write_phys(vcpu, gpa, val, bytes);
4967}
4968
4969static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4970{
e39d200f 4971 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4972 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4973}
4974
4975static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4976 void *val, int bytes)
4977{
e39d200f 4978 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4979 return X86EMUL_IO_NEEDED;
4980}
4981
4982static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4983 void *val, int bytes)
4984{
f78146b0
AK		 4985 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4986
87da7e66 4987 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4988 return X86EMUL_CONTINUE;
4989}
4990
0fbe9b0b 4991static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4992 .read_write_prepare = read_prepare,
4993 .read_write_emulate = read_emulate,
4994 .read_write_mmio = vcpu_mmio_read,
4995 .read_write_exit_mmio = read_exit_mmio,
4996};
4997
0fbe9b0b 4998static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4999 .read_write_emulate = write_emulate,
5000 .read_write_mmio = write_mmio,
5001 .read_write_exit_mmio = write_exit_mmio,
5002 .write = true,
5003};
5004
22388a3c
XG		 5005static int emulator_read_write_onepage(unsigned long addr, void *val,
5006 unsigned int bytes,
5007 struct x86_exception *exception,
5008 struct kvm_vcpu *vcpu,
0fbe9b0b 5009 const struct read_write_emulator_ops *ops)
bbd9b64e 5010{
af7cc7d1
XG		 5011 gpa_t gpa;
5012 int handled, ret;
22388a3c 5013 bool write = ops->write;
f78146b0 5014 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5015 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5016
5017 /*
5018 * If the exit was due to a NPF we may already have a GPA.
5019 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5020 * Note, this cannot be used on string operations since string
5021 * operation using rep will only have the initial GPA from the NPF
5022 * occurred.
5023 */
5024 if (vcpu->arch.gpa_available &&
5025 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5026 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5027 gpa = vcpu->arch.gpa_val;
5028 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5029 } else {
5030 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5031 if (ret < 0)
5032 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5033 }
10589a46 5034
618232e2 5035 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5036 return X86EMUL_CONTINUE;
5037
bbd9b64e
CO		 5038 /*
5039 * Is this MMIO handled locally?
5040 */
22388a3c 5041 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5042 if (handled == bytes)
bbd9b64e 5043 return X86EMUL_CONTINUE;
bbd9b64e 5044
70252a10
AK		 5045 gpa += handled;
5046 bytes -= handled;
5047 val += handled;
5048
87da7e66
XG		 5049 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5050 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5051 frag->gpa = gpa;
5052 frag->data = val;
5053 frag->len = bytes;
f78146b0 5054 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5055}
5056
52eb5a6d
XL		 5057static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5058 unsigned long addr,
22388a3c
XG		 5059 void *val, unsigned int bytes,
5060 struct x86_exception *exception,
0fbe9b0b 5061 const struct read_write_emulator_ops *ops)
bbd9b64e 5062{
0f65dd70 5063 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5064 gpa_t gpa;
5065 int rc;
5066
5067 if (ops->read_write_prepare &&
5068 ops->read_write_prepare(vcpu, val, bytes))
5069 return X86EMUL_CONTINUE;
5070
5071 vcpu->mmio_nr_fragments = 0;
0f65dd70 5072
bbd9b64e
CO		 5073 /* Crossing a page boundary? */
5074 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5075 int now;
bbd9b64e
CO		 5076
5077 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5078 rc = emulator_read_write_onepage(addr, val, now, exception,
5079 vcpu, ops);
5080
bbd9b64e
CO		 5081 if (rc != X86EMUL_CONTINUE)
5082 return rc;
5083 addr += now;
bac15531
NA		 5084 if (ctxt->mode != X86EMUL_MODE_PROT64)
5085 addr = (u32)addr;
bbd9b64e
CO		 5086 val += now;
5087 bytes -= now;
5088 }
22388a3c 5089
f78146b0
AK		 5090 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5091 vcpu, ops);
5092 if (rc != X86EMUL_CONTINUE)
5093 return rc;
5094
5095 if (!vcpu->mmio_nr_fragments)
5096 return rc;
5097
5098 gpa = vcpu->mmio_fragments[0].gpa;
5099
5100 vcpu->mmio_needed = 1;
5101 vcpu->mmio_cur_fragment = 0;
5102
87da7e66 5103 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5104 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5105 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5106 vcpu->run->mmio.phys_addr = gpa;
5107
5108 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5109}
5110
5111static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5112 unsigned long addr,
5113 void *val,
5114 unsigned int bytes,
5115 struct x86_exception *exception)
5116{
5117 return emulator_read_write(ctxt, addr, val, bytes,
5118 exception, &read_emultor);
5119}
5120
52eb5a6d 5121static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5122 unsigned long addr,
5123 const void *val,
5124 unsigned int bytes,
5125 struct x86_exception *exception)
5126{
5127 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5128 exception, &write_emultor);
bbd9b64e 5129}
bbd9b64e 5130
daea3e73
AK		 5131#define CMPXCHG_TYPE(t, ptr, old, new) \
5132 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5133
5134#ifdef CONFIG_X86_64
5135# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5136#else
5137# define CMPXCHG64(ptr, old, new) \
9749a6c0 5138 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5139#endif
5140
0f65dd70
AK		 5141static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5142 unsigned long addr,
bbd9b64e
CO		 5143 const void *old,
5144 const void *new,
5145 unsigned int bytes,
0f65dd70 5146 struct x86_exception *exception)
bbd9b64e 5147{
0f65dd70 5148 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5149 gpa_t gpa;
5150 struct page *page;
5151 char *kaddr;
5152 bool exchanged;
2bacc55c 5153
daea3e73
AK		 5154 /* guests cmpxchg8b have to be emulated atomically */
5155 if (bytes > 8 || (bytes & (bytes - 1)))
5156 goto emul_write;
10589a46 5157
daea3e73 5158 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5159
daea3e73
AK		 5160 if (gpa == UNMAPPED_GVA ||
5161 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5162 goto emul_write;
2bacc55c 5163
daea3e73
AK		 5164 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5165 goto emul_write;
72dc67a6 5166
54bf36aa 5167 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5168 if (is_error_page(page))
c19b8bd6 5169 goto emul_write;
72dc67a6 5170
8fd75e12 5171 kaddr = kmap_atomic(page);
daea3e73
AK		 5172 kaddr += offset_in_page(gpa);
5173 switch (bytes) {
5174 case 1:
5175 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5176 break;
5177 case 2:
5178 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5179 break;
5180 case 4:
5181 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5182 break;
5183 case 8:
5184 exchanged = CMPXCHG64(kaddr, old, new);
5185 break;
5186 default:
5187 BUG();
2bacc55c 5188 }
8fd75e12 5189 kunmap_atomic(kaddr);
daea3e73
AK		 5190 kvm_release_page_dirty(page);
5191
5192 if (!exchanged)
5193 return X86EMUL_CMPXCHG_FAILED;
5194
54bf36aa 5195 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5196 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5197
5198 return X86EMUL_CONTINUE;
4a5f48f6 5199
3200f405 5200emul_write:
daea3e73 5201 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5202
0f65dd70 5203 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5204}
5205
cf8f70bf
GN		 5206static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5207{
cbfc6c91 5208 int r = 0, i;
cf8f70bf 5209
cbfc6c91
WL		 5210 for (i = 0; i < vcpu->arch.pio.count; i++) {
5211 if (vcpu->arch.pio.in)
5212 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5213 vcpu->arch.pio.size, pd);
5214 else
5215 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5216 vcpu->arch.pio.port, vcpu->arch.pio.size,
5217 pd);
5218 if (r)
5219 break;
5220 pd += vcpu->arch.pio.size;
5221 }
cf8f70bf
GN		 5222 return r;
5223}
5224
6f6fbe98
XG		 5225static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5226 unsigned short port, void *val,
5227 unsigned int count, bool in)
cf8f70bf 5228{
cf8f70bf 5229 vcpu->arch.pio.port = port;
6f6fbe98 5230 vcpu->arch.pio.in = in;
7972995b 5231 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5232 vcpu->arch.pio.size = size;
5233
5234 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5235 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5236 return 1;
5237 }
5238
5239 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5240 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5241 vcpu->run->io.size = size;
5242 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5243 vcpu->run->io.count = count;
5244 vcpu->run->io.port = port;
5245
5246 return 0;
5247}
5248
6f6fbe98
XG		 5249static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5250 int size, unsigned short port, void *val,
5251 unsigned int count)
cf8f70bf 5252{
ca1d4a9e 5253 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5254 int ret;
ca1d4a9e 5255
6f6fbe98
XG		 5256 if (vcpu->arch.pio.count)
5257 goto data_avail;
cf8f70bf 5258
cbfc6c91
WL		 5259 memset(vcpu->arch.pio_data, 0, size * count);
5260
6f6fbe98
XG		 5261 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5262 if (ret) {
5263data_avail:
5264 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5265 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5266 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5267 return 1;
5268 }
5269
cf8f70bf
GN		 5270 return 0;
5271}
5272
6f6fbe98
XG		 5273static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5274 int size, unsigned short port,
5275 const void *val, unsigned int count)
5276{
5277 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5278
5279 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5280 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5281 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5282}
5283
bbd9b64e
CO		 5284static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5285{
5286 return kvm_x86_ops->get_segment_base(vcpu, seg);
5287}
5288
3cb16fe7 5289static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5290{
3cb16fe7 5291 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5292}
5293
ae6a2375 5294static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5295{
5296 if (!need_emulate_wbinvd(vcpu))
5297 return X86EMUL_CONTINUE;
5298
5299 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5300 int cpu = get_cpu();
5301
5302 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5303 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5304 wbinvd_ipi, NULL, 1);
2eec7343 5305 put_cpu();
f5f48ee1 5306 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5307 } else
5308 wbinvd();
f5f48ee1
SY		 5309 return X86EMUL_CONTINUE;
5310}
5cb56059
JS		 5311
5312int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5313{
6affcbed
KH		 5314 kvm_emulate_wbinvd_noskip(vcpu);
5315 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5316}
f5f48ee1
SY		 5317EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5318
5cb56059
JS		 5319
5320
bcaf5cc5
AK		 5321static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5322{
5cb56059 5323 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5324}
5325
52eb5a6d
XL		 5326static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5327 unsigned long *dest)
bbd9b64e 5328{
16f8a6f9 5329 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5330}
5331
52eb5a6d
XL		 5332static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5333 unsigned long value)
bbd9b64e 5334{
338dbc97 5335
717746e3 5336 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5337}
5338
52a46617 5339static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5340{
52a46617 5341 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5342}
5343
717746e3 5344static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5345{
717746e3 5346 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5347 unsigned long value;
5348
5349 switch (cr) {
5350 case 0:
5351 value = kvm_read_cr0(vcpu);
5352 break;
5353 case 2:
5354 value = vcpu->arch.cr2;
5355 break;
5356 case 3:
9f8fe504 5357 value = kvm_read_cr3(vcpu);
52a46617
GN		 5358 break;
5359 case 4:
5360 value = kvm_read_cr4(vcpu);
5361 break;
5362 case 8:
5363 value = kvm_get_cr8(vcpu);
5364 break;
5365 default:
a737f256 5366 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5367 return 0;
5368 }
5369
5370 return value;
5371}
5372
717746e3 5373static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5374{
717746e3 5375 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5376 int res = 0;
5377
52a46617
GN		 5378 switch (cr) {
5379 case 0:
49a9b07e 5380 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5381 break;
5382 case 2:
5383 vcpu->arch.cr2 = val;
5384 break;
5385 case 3:
2390218b 5386 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5387 break;
5388 case 4:
a83b29c6 5389 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5390 break;
5391 case 8:
eea1cff9 5392 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5393 break;
5394 default:
a737f256 5395 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5396 res = -1;
52a46617 5397 }
0f12244f
GN		 5398
5399 return res;
52a46617
GN		 5400}
5401
717746e3 5402static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5403{
717746e3 5404 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5405}
5406
4bff1e86 5407static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5408{
4bff1e86 5409 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5410}
5411
4bff1e86 5412static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5413{
4bff1e86 5414 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5415}
5416
1ac9d0cf
AK		 5417static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5418{
5419 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5420}
5421
5422static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5423{
5424 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5425}
5426
4bff1e86
AK		 5427static unsigned long emulator_get_cached_segment_base(
5428 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5429{
4bff1e86 5430 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5431}
5432
1aa36616
AK		 5433static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5434 struct desc_struct *desc, u32 *base3,
5435 int seg)
2dafc6c2
GN		 5436{
5437 struct kvm_segment var;
5438
4bff1e86 5439 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5440 *selector = var.selector;
2dafc6c2 5441
378a8b09
GN		 5442 if (var.unusable) {
5443 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5444 if (base3)
5445 *base3 = 0;
2dafc6c2 5446 return false;
378a8b09 5447 }
2dafc6c2
GN		 5448
5449 if (var.g)
5450 var.limit >>= 12;
5451 set_desc_limit(desc, var.limit);
5452 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5453#ifdef CONFIG_X86_64
5454 if (base3)
5455 *base3 = var.base >> 32;
5456#endif
2dafc6c2
GN		 5457 desc->type = var.type;
5458 desc->s = var.s;
5459 desc->dpl = var.dpl;
5460 desc->p = var.present;
5461 desc->avl = var.avl;
5462 desc->l = var.l;
5463 desc->d = var.db;
5464 desc->g = var.g;
5465
5466 return true;
5467}
5468
1aa36616
AK		 5469static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5470 struct desc_struct *desc, u32 base3,
5471 int seg)
2dafc6c2 5472{
4bff1e86 5473 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5474 struct kvm_segment var;
5475
1aa36616 5476 var.selector = selector;
2dafc6c2 5477 var.base = get_desc_base(desc);
5601d05b
GN		 5478#ifdef CONFIG_X86_64
5479 var.base |= ((u64)base3) << 32;
5480#endif
2dafc6c2
GN		 5481 var.limit = get_desc_limit(desc);
5482 if (desc->g)
5483 var.limit = (var.limit << 12) | 0xfff;
5484 var.type = desc->type;
2dafc6c2
GN		 5485 var.dpl = desc->dpl;
5486 var.db = desc->d;
5487 var.s = desc->s;
5488 var.l = desc->l;
5489 var.g = desc->g;
5490 var.avl = desc->avl;
5491 var.present = desc->p;
5492 var.unusable = !var.present;
5493 var.padding = 0;
5494
5495 kvm_set_segment(vcpu, &var, seg);
5496 return;
5497}
5498
717746e3
AK		 5499static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5500 u32 msr_index, u64 *pdata)
5501{
609e36d3
PB		 5502 struct msr_data msr;
5503 int r;
5504
5505 msr.index = msr_index;
5506 msr.host_initiated = false;
5507 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5508 if (r)
5509 return r;
5510
5511 *pdata = msr.data;
5512 return 0;
717746e3
AK		 5513}
5514
5515static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5516 u32 msr_index, u64 data)
5517{
8fe8ab46
WA		 5518 struct msr_data msr;
5519
5520 msr.data = data;
5521 msr.index = msr_index;
5522 msr.host_initiated = false;
5523 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5524}
5525
64d60670
PB		 5526static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5527{
5528 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5529
5530 return vcpu->arch.smbase;
5531}
5532
5533static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5534{
5535 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5536
5537 vcpu->arch.smbase = smbase;
5538}
5539
67f4d428
NA		 5540static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5541 u32 pmc)
5542{
c6702c9d 5543 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5544}
5545
222d21aa
AK		 5546static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5547 u32 pmc, u64 *pdata)
5548{
c6702c9d 5549 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5550}
5551
6c3287f7
AK		 5552static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5553{
5554 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5555}
5556
2953538e 5557static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5558 struct x86_instruction_info *info,
c4f035c6
AK		 5559 enum x86_intercept_stage stage)
5560{
2953538e 5561 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5562}
5563
e911eb3b
YZ		 5564static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5565 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5566{
e911eb3b 5567 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5568}
5569
dd856efa
AK		 5570static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5571{
5572 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5573}
5574
5575static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5576{
5577 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5578}
5579
801806d9
NA		 5580static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5581{
5582 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5583}
5584
6ed071f0
LP		 5585static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5586{
5587 return emul_to_vcpu(ctxt)->arch.hflags;
5588}
5589
5590static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5591{
5592 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5593}
5594
0234bf88
LP		 5595static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5596{
5597 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5598}
5599
0225fb50 5600static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5601 .read_gpr = emulator_read_gpr,
5602 .write_gpr = emulator_write_gpr,
1871c602 5603 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5604 .write_std = kvm_write_guest_virt_system,
7a036a6f 5605 .read_phys = kvm_read_guest_phys_system,
1871c602 5606 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5607 .read_emulated = emulator_read_emulated,
5608 .write_emulated = emulator_write_emulated,
5609 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5610 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5611 .pio_in_emulated = emulator_pio_in_emulated,
5612 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5613 .get_segment = emulator_get_segment,
5614 .set_segment = emulator_set_segment,
5951c442 5615 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5616 .get_gdt = emulator_get_gdt,
160ce1f1 5617 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5618 .set_gdt = emulator_set_gdt,
5619 .set_idt = emulator_set_idt,
52a46617
GN		 5620 .get_cr = emulator_get_cr,
5621 .set_cr = emulator_set_cr,
9c537244 5622 .cpl = emulator_get_cpl,
35aa5375
GN		 5623 .get_dr = emulator_get_dr,
5624 .set_dr = emulator_set_dr,
64d60670
PB		 5625 .get_smbase = emulator_get_smbase,
5626 .set_smbase = emulator_set_smbase,
717746e3
AK		 5627 .set_msr = emulator_set_msr,
5628 .get_msr = emulator_get_msr,
67f4d428 5629 .check_pmc = emulator_check_pmc,
222d21aa 5630 .read_pmc = emulator_read_pmc,
6c3287f7 5631 .halt = emulator_halt,
bcaf5cc5 5632 .wbinvd = emulator_wbinvd,
d6aa1000 5633 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5634 .intercept = emulator_intercept,
bdb42f5a 5635 .get_cpuid = emulator_get_cpuid,
801806d9 5636 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5637 .get_hflags = emulator_get_hflags,
5638 .set_hflags = emulator_set_hflags,
0234bf88 5639 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5640};
5641
95cb2295
GN		 5642static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5643{
37ccdcbe 5644 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5645 /*
5646 * an sti; sti; sequence only disable interrupts for the first
5647 * instruction. So, if the last instruction, be it emulated or
5648 * not, left the system with the INT_STI flag enabled, it
5649 * means that the last instruction is an sti. We should not
5650 * leave the flag on in this case. The same goes for mov ss
5651 */
37ccdcbe
PB		 5652 if (int_shadow & mask)
5653 mask = 0;
6addfc42 5654 if (unlikely(int_shadow || mask)) {
95cb2295 5655 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5656 if (!mask)
5657 kvm_make_request(KVM_REQ_EVENT, vcpu);
5658 }
95cb2295
GN		 5659}
5660
ef54bcfe 5661static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5662{
5663 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5664 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5665 return kvm_propagate_fault(vcpu, &ctxt->exception);
5666
5667 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5668 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5669 ctxt->exception.error_code);
54b8486f 5670 else
da9cb575 5671 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5672 return false;
54b8486f
GN		 5673}
5674
8ec4722d
MG		 5675static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5676{
adf52235 5677 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5678 int cs_db, cs_l;
5679
8ec4722d
MG		 5680 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5681
adf52235 5682 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5683 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5684
adf52235
TY		 5685 ctxt->eip = kvm_rip_read(vcpu);
5686 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5687 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5688 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5689 cs_db ? X86EMUL_MODE_PROT32 :
5690 X86EMUL_MODE_PROT16;
a584539b 5691 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5692 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5693 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5694
dd856efa 5695 init_decode_cache(ctxt);
7ae441ea 5696 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5697}
5698
71f9833b 5699int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5700{
9d74191a 5701 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5702 int ret;
5703
5704 init_emulate_ctxt(vcpu);
5705
9dac77fa
AK		 5706 ctxt->op_bytes = 2;
5707 ctxt->ad_bytes = 2;
5708 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5709 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5710
5711 if (ret != X86EMUL_CONTINUE)
5712 return EMULATE_FAIL;
5713
9dac77fa 5714 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5715 kvm_rip_write(vcpu, ctxt->eip);
5716 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5717
63995653
MG		 5718 return EMULATE_DONE;
5719}
5720EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5721
e2366171 5722static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5723{
fc3a9157
JR		 5724 int r = EMULATE_DONE;
5725
6d77dbfc
GN		 5726 ++vcpu->stat.insn_emulation_fail;
5727 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5728
5729 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5730 return EMULATE_FAIL;
5731
a2b9e6c1 5732 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5733 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5734 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5735 vcpu->run->internal.ndata = 0;
1f4dcb3b 5736 r = EMULATE_USER_EXIT;
fc3a9157 5737 }
e2366171 5738
6d77dbfc 5739 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5740
5741 return r;
6d77dbfc
GN		 5742}
5743
93c05d3e 5744static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5745 bool write_fault_to_shadow_pgtable,
5746 int emulation_type)
a6f177ef 5747{
95b3cf69 5748 gpa_t gpa = cr2;
ba049e93 5749 kvm_pfn_t pfn;
a6f177ef 5750
991eebf9
GN		 5751 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5752 return false;
5753
95b3cf69
XG		 5754 if (!vcpu->arch.mmu.direct_map) {
5755 /*
5756 * Write permission should be allowed since only
5757 * write access need to be emulated.
5758 */
5759 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5760
95b3cf69
XG		 5761 /*
5762 * If the mapping is invalid in guest, let cpu retry
5763 * it to generate fault.
5764 */
5765 if (gpa == UNMAPPED_GVA)
5766 return true;
5767 }
a6f177ef 5768
8e3d9d06
XG		 5769 /*
5770 * Do not retry the unhandleable instruction if it faults on the
5771 * readonly host memory, otherwise it will goto a infinite loop:
5772 * retry instruction -> write #PF -> emulation fail -> retry
5773 * instruction -> ...
5774 */
5775 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5776
5777 /*
5778 * If the instruction failed on the error pfn, it can not be fixed,
5779 * report the error to userspace.
5780 */
5781 if (is_error_noslot_pfn(pfn))
5782 return false;
5783
5784 kvm_release_pfn_clean(pfn);
5785
5786 /* The instructions are well-emulated on direct mmu. */
5787 if (vcpu->arch.mmu.direct_map) {
5788 unsigned int indirect_shadow_pages;
5789
5790 spin_lock(&vcpu->kvm->mmu_lock);
5791 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5792 spin_unlock(&vcpu->kvm->mmu_lock);
5793
5794 if (indirect_shadow_pages)
5795 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5796
a6f177ef 5797 return true;
8e3d9d06 5798 }
a6f177ef 5799
95b3cf69
XG		 5800 /*
5801 * if emulation was due to access to shadowed page table
5802 * and it failed try to unshadow page and re-enter the
5803 * guest to let CPU execute the instruction.
5804 */
5805 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5806
5807 /*
5808 * If the access faults on its page table, it can not
5809 * be fixed by unprotecting shadow page and it should
5810 * be reported to userspace.
5811 */
5812 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5813}
5814
1cb3f3ae
XG		 5815static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5816 unsigned long cr2, int emulation_type)
5817{
5818 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5819 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5820
5821 last_retry_eip = vcpu->arch.last_retry_eip;
5822 last_retry_addr = vcpu->arch.last_retry_addr;
5823
5824 /*
5825 * If the emulation is caused by #PF and it is non-page_table
5826 * writing instruction, it means the VM-EXIT is caused by shadow
5827 * page protected, we can zap the shadow page and retry this
5828 * instruction directly.
5829 *
5830 * Note: if the guest uses a non-page-table modifying instruction
5831 * on the PDE that points to the instruction, then we will unmap
5832 * the instruction and go to an infinite loop. So, we cache the
5833 * last retried eip and the last fault address, if we meet the eip
5834 * and the address again, we can break out of the potential infinite
5835 * loop.
5836 */
5837 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5838
5839 if (!(emulation_type & EMULTYPE_RETRY))
5840 return false;
5841
5842 if (x86_page_table_writing_insn(ctxt))
5843 return false;
5844
5845 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5846 return false;
5847
5848 vcpu->arch.last_retry_eip = ctxt->eip;
5849 vcpu->arch.last_retry_addr = cr2;
5850
5851 if (!vcpu->arch.mmu.direct_map)
5852 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5853
22368028 5854 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5855
5856 return true;
5857}
5858
716d51ab
GN		 5859static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5860static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5861
64d60670 5862static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5863{
64d60670 5864 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5865 /* This is a good place to trace that we are exiting SMM. */
5866 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5867
c43203ca
PB		 5868 /* Process a latched INIT or SMI, if any. */
5869 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5870 }
699023e2
PB		 5871
5872 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5873}
5874
5875static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5876{
5877 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5878
a584539b 5879 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5880
5881 if (changed & HF_SMM_MASK)
5882 kvm_smm_changed(vcpu);
a584539b
PB		 5883}
5884
4a1e10d5
PB		 5885static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5886 unsigned long *db)
5887{
5888 u32 dr6 = 0;
5889 int i;
5890 u32 enable, rwlen;
5891
5892 enable = dr7;
5893 rwlen = dr7 >> 16;
5894 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5895 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5896 dr6 |= (1 << i);
5897 return dr6;
5898}
5899
c8401dda 5900static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5901{
5902 struct kvm_run *kvm_run = vcpu->run;
5903
c8401dda
PB		 5904 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5905 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5906 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5907 kvm_run->debug.arch.exception = DB_VECTOR;
5908 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5909 *r = EMULATE_USER_EXIT;
5910 } else {
5911 /*
5912 * "Certain debug exceptions may clear bit 0-3. The
5913 * remaining contents of the DR6 register are never
5914 * cleared by the processor".
5915 */
5916 vcpu->arch.dr6 &= ~15;
5917 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5918 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5919 }
5920}
5921
6affcbed
KH		 5922int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5923{
5924 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5925 int r = EMULATE_DONE;
5926
5927 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5928
5929 /*
5930 * rflags is the old, "raw" value of the flags. The new value has
5931 * not been saved yet.
5932 *
5933 * This is correct even for TF set by the guest, because "the
5934 * processor will not generate this exception after the instruction
5935 * that sets the TF flag".
5936 */
5937 if (unlikely(rflags & X86_EFLAGS_TF))
5938 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5939 return r == EMULATE_DONE;
5940}
5941EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5942
4a1e10d5
PB		 5943static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5944{
4a1e10d5
PB		 5945 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5946 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5947 struct kvm_run *kvm_run = vcpu->run;
5948 unsigned long eip = kvm_get_linear_rip(vcpu);
5949 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5950 vcpu->arch.guest_debug_dr7,
5951 vcpu->arch.eff_db);
5952
5953 if (dr6 != 0) {
6f43ed01 5954 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5955 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5956 kvm_run->debug.arch.exception = DB_VECTOR;
5957 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5958 *r = EMULATE_USER_EXIT;
5959 return true;
5960 }
5961 }
5962
4161a569
NA		 5963 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5964 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5965 unsigned long eip = kvm_get_linear_rip(vcpu);
5966 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5967 vcpu->arch.dr7,
5968 vcpu->arch.db);
5969
5970 if (dr6 != 0) {
5971 vcpu->arch.dr6 &= ~15;
6f43ed01 5972 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5973 kvm_queue_exception(vcpu, DB_VECTOR);
5974 *r = EMULATE_DONE;
5975 return true;
5976 }
5977 }
5978
5979 return false;
5980}
5981
04789b66
LA		 5982static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
5983{
2d7921c4
AM		 5984 switch (ctxt->opcode_len) {
5985 case 1:
5986 switch (ctxt->b) {
5987 case 0xe4: /* IN */
5988 case 0xe5:
5989 case 0xec:
5990 case 0xed:
5991 case 0xe6: /* OUT */
5992 case 0xe7:
5993 case 0xee:
5994 case 0xef:
5995 case 0x6c: /* INS */
5996 case 0x6d:
5997 case 0x6e: /* OUTS */
5998 case 0x6f:
5999 return true;
6000 }
6001 break;
6002 case 2:
6003 switch (ctxt->b) {
6004 case 0x33: /* RDPMC */
6005 return true;
6006 }
6007 break;
04789b66
LA		 6008 }
6009
6010 return false;
6011}
6012
51d8b661
AP		 6013int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6014 unsigned long cr2,
dc25e89e
AP		 6015 int emulation_type,
6016 void *insn,
6017 int insn_len)
bbd9b64e 6018{
95cb2295 6019 int r;
9d74191a 6020 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6021 bool writeback = true;
93c05d3e 6022 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6023
93c05d3e
XG		 6024 /*
6025 * Clear write_fault_to_shadow_pgtable here to ensure it is
6026 * never reused.
6027 */
6028 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6029 kvm_clear_exception_queue(vcpu);
8d7d8102 6030
571008da 6031 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6032 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6033
6034 /*
6035 * We will reenter on the same instruction since
6036 * we do not set complete_userspace_io. This does not
6037 * handle watchpoints yet, those would be handled in
6038 * the emulate_ops.
6039 */
d391f120
VK		 6040 if (!(emulation_type & EMULTYPE_SKIP) &&
6041 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6042 return r;
6043
9d74191a
TY		 6044 ctxt->interruptibility = 0;
6045 ctxt->have_exception = false;
e0ad0b47 6046 ctxt->exception.vector = -1;
9d74191a 6047 ctxt->perm_ok = false;
bbd9b64e 6048
b51e974f 6049 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6050
9d74191a 6051 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6052
e46479f8 6053 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6054 ++vcpu->stat.insn_emulation;
1d2887e2 6055 if (r != EMULATION_OK) {
4005996e
AK		 6056 if (emulation_type & EMULTYPE_TRAP_UD)
6057 return EMULATE_FAIL;
991eebf9
GN		 6058 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6059 emulation_type))
bbd9b64e 6060 return EMULATE_DONE;
6ea6e843
PB		 6061 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6062 return EMULATE_DONE;
6d77dbfc
GN		 6063 if (emulation_type & EMULTYPE_SKIP)
6064 return EMULATE_FAIL;
e2366171 6065 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6066 }
6067 }
6068
04789b66
LA		 6069 if ((emulation_type & EMULTYPE_VMWARE) &&
6070 !is_vmware_backdoor_opcode(ctxt))
6071 return EMULATE_FAIL;
6072
ba8afb6b 6073 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6074 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6075 if (ctxt->eflags & X86_EFLAGS_RF)
6076 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6077 return EMULATE_DONE;
6078 }
6079
1cb3f3ae
XG		 6080 if (retry_instruction(ctxt, cr2, emulation_type))
6081 return EMULATE_DONE;
6082
7ae441ea 6083 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6084 changes registers values during IO operation */
7ae441ea
GN		 6085 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6086 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6087 emulator_invalidate_register_cache(ctxt);
7ae441ea 6088 }
4d2179e1 6089
5cd21917 6090restart:
0f89b207
TL		 6091 /* Save the faulting GPA (cr2) in the address field */
6092 ctxt->exception.address = cr2;
6093
9d74191a 6094 r = x86_emulate_insn(ctxt);
bbd9b64e 6095
775fde86
JR		 6096 if (r == EMULATION_INTERCEPTED)
6097 return EMULATE_DONE;
6098
d2ddd1c4 6099 if (r == EMULATION_FAILED) {
991eebf9
GN		 6100 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6101 emulation_type))
c3cd7ffa
GN		 6102 return EMULATE_DONE;
6103
e2366171 6104 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6105 }
6106
9d74191a 6107 if (ctxt->have_exception) {
d2ddd1c4 6108 r = EMULATE_DONE;
ef54bcfe
PB		 6109 if (inject_emulated_exception(vcpu))
6110 return r;
d2ddd1c4 6111 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6112 if (!vcpu->arch.pio.in) {
6113 /* FIXME: return into emulator if single-stepping. */
3457e419 6114 vcpu->arch.pio.count = 0;
0912c977 6115 } else {
7ae441ea 6116 writeback = false;
716d51ab
GN		 6117 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6118 }
ac0a48c3 6119 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6120 } else if (vcpu->mmio_needed) {
6121 if (!vcpu->mmio_is_write)
6122 writeback = false;
ac0a48c3 6123 r = EMULATE_USER_EXIT;
716d51ab 6124 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6125 } else if (r == EMULATION_RESTART)
5cd21917 6126 goto restart;
d2ddd1c4
GN		 6127 else
6128 r = EMULATE_DONE;
f850e2e6 6129
7ae441ea 6130 if (writeback) {
6addfc42 6131 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6132 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6133 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6134 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6135 if (r == EMULATE_DONE &&
6136 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6137 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6138 if (!ctxt->have_exception ||
6139 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6140 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6141
6142 /*
6143 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6144 * do nothing, and it will be requested again as soon as
6145 * the shadow expires. But we still need to check here,
6146 * because POPF has no interrupt shadow.
6147 */
6148 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6149 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6150 } else
6151 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6152
6153 return r;
de7d789a 6154}
51d8b661 6155EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6156
dca7f128
SC		 6157static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6158 unsigned short port)
de7d789a 6159{
cf8f70bf 6160 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6161 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6162 size, port, &val, 1);
cf8f70bf 6163 /* do not return to emulator after return from userspace */
7972995b 6164 vcpu->arch.pio.count = 0;
de7d789a
CO		 6165 return ret;
6166}
de7d789a 6167
8370c3d0
TL		 6168static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6169{
6170 unsigned long val;
6171
6172 /* We should only ever be called with arch.pio.count equal to 1 */
6173 BUG_ON(vcpu->arch.pio.count != 1);
6174
6175 /* For size less than 4 we merge, else we zero extend */
6176 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6177 : 0;
6178
6179 /*
6180 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6181 * the copy and tracing
6182 */
6183 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6184 vcpu->arch.pio.port, &val, 1);
6185 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6186
6187 return 1;
6188}
6189
dca7f128
SC		 6190static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6191 unsigned short port)
8370c3d0
TL		 6192{
6193 unsigned long val;
6194 int ret;
6195
6196 /* For size less than 4 we merge, else we zero extend */
6197 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6198
6199 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6200 &val, 1);
6201 if (ret) {
6202 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6203 return ret;
6204 }
6205
6206 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6207
6208 return 0;
6209}
dca7f128
SC		 6210
6211int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6212{
6213 int ret = kvm_skip_emulated_instruction(vcpu);
6214
6215 /*
6216 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6217 * KVM_EXIT_DEBUG here.
6218 */
6219 if (in)
6220 return kvm_fast_pio_in(vcpu, size, port) && ret;
6221 else
6222 return kvm_fast_pio_out(vcpu, size, port) && ret;
6223}
6224EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6225
251a5fd6 6226static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6227{
0a3aee0d 6228 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6229 return 0;
8cfdc000
ZA		 6230}
6231
6232static void tsc_khz_changed(void *data)
c8076604 6233{
8cfdc000
ZA		 6234 struct cpufreq_freqs *freq = data;
6235 unsigned long khz = 0;
6236
6237 if (data)
6238 khz = freq->new;
6239 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6240 khz = cpufreq_quick_get(raw_smp_processor_id());
6241 if (!khz)
6242 khz = tsc_khz;
0a3aee0d 6243 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6244}
6245
5fa4ec9c 6246#ifdef CONFIG_X86_64
0092e434
VK		 6247static void kvm_hyperv_tsc_notifier(void)
6248{
0092e434
VK		 6249 struct kvm *kvm;
6250 struct kvm_vcpu *vcpu;
6251 int cpu;
6252
6253 spin_lock(&kvm_lock);
6254 list_for_each_entry(kvm, &vm_list, vm_list)
6255 kvm_make_mclock_inprogress_request(kvm);
6256
6257 hyperv_stop_tsc_emulation();
6258
6259 /* TSC frequency always matches when on Hyper-V */
6260 for_each_present_cpu(cpu)
6261 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6262 kvm_max_guest_tsc_khz = tsc_khz;
6263
6264 list_for_each_entry(kvm, &vm_list, vm_list) {
6265 struct kvm_arch *ka = &kvm->arch;
6266
6267 spin_lock(&ka->pvclock_gtod_sync_lock);
6268
6269 pvclock_update_vm_gtod_copy(kvm);
6270
6271 kvm_for_each_vcpu(cpu, vcpu, kvm)
6272 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6273
6274 kvm_for_each_vcpu(cpu, vcpu, kvm)
6275 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6276
6277 spin_unlock(&ka->pvclock_gtod_sync_lock);
6278 }
6279 spin_unlock(&kvm_lock);
0092e434 6280}
5fa4ec9c 6281#endif
0092e434 6282
c8076604
GH		 6283static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6284 void *data)
6285{
6286 struct cpufreq_freqs *freq = data;
6287 struct kvm *kvm;
6288 struct kvm_vcpu *vcpu;
6289 int i, send_ipi = 0;
6290
8cfdc000
ZA		 6291 /*
6292 * We allow guests to temporarily run on slowing clocks,
6293 * provided we notify them after, or to run on accelerating
6294 * clocks, provided we notify them before. Thus time never
6295 * goes backwards.
6296 *
6297 * However, we have a problem. We can't atomically update
6298 * the frequency of a given CPU from this function; it is
6299 * merely a notifier, which can be called from any CPU.
6300 * Changing the TSC frequency at arbitrary points in time
6301 * requires a recomputation of local variables related to
6302 * the TSC for each VCPU. We must flag these local variables
6303 * to be updated and be sure the update takes place with the
6304 * new frequency before any guests proceed.
6305 *
6306 * Unfortunately, the combination of hotplug CPU and frequency
6307 * change creates an intractable locking scenario; the order
6308 * of when these callouts happen is undefined with respect to
6309 * CPU hotplug, and they can race with each other. As such,
6310 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6311 * undefined; you can actually have a CPU frequency change take
6312 * place in between the computation of X and the setting of the
6313 * variable. To protect against this problem, all updates of
6314 * the per_cpu tsc_khz variable are done in an interrupt
6315 * protected IPI, and all callers wishing to update the value
6316 * must wait for a synchronous IPI to complete (which is trivial
6317 * if the caller is on the CPU already). This establishes the
6318 * necessary total order on variable updates.
6319 *
6320 * Note that because a guest time update may take place
6321 * anytime after the setting of the VCPU's request bit, the
6322 * correct TSC value must be set before the request. However,
6323 * to ensure the update actually makes it to any guest which
6324 * starts running in hardware virtualization between the set
6325 * and the acquisition of the spinlock, we must also ping the
6326 * CPU after setting the request bit.
6327 *
6328 */
6329
c8076604
GH		 6330 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6331 return 0;
6332 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6333 return 0;
8cfdc000
ZA		 6334
6335 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6336
2f303b74 6337 spin_lock(&kvm_lock);
c8076604 6338 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6339 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6340 if (vcpu->cpu != freq->cpu)
6341 continue;
c285545f 6342 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6343 if (vcpu->cpu != smp_processor_id())
8cfdc000 6344 send_ipi = 1;
c8076604
GH		 6345 }
6346 }
2f303b74 6347 spin_unlock(&kvm_lock);
c8076604
GH		 6348
6349 if (freq->old < freq->new && send_ipi) {
6350 /*
6351 * We upscale the frequency. Must make the guest
6352 * doesn't see old kvmclock values while running with
6353 * the new frequency, otherwise we risk the guest sees
6354 * time go backwards.
6355 *
6356 * In case we update the frequency for another cpu
6357 * (which might be in guest context) send an interrupt
6358 * to kick the cpu out of guest context. Next time
6359 * guest context is entered kvmclock will be updated,
6360 * so the guest will not see stale values.
6361 */
8cfdc000 6362 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6363 }
6364 return 0;
6365}
6366
6367static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6368 .notifier_call = kvmclock_cpufreq_notifier
6369};
6370
251a5fd6 6371static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6372{
251a5fd6
SAS		 6373 tsc_khz_changed(NULL);
6374 return 0;
8cfdc000
ZA		 6375}
6376
b820cc0c
ZA		 6377static void kvm_timer_init(void)
6378{
c285545f 6379 max_tsc_khz = tsc_khz;
460dd42e 6380
b820cc0c 6381 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6382#ifdef CONFIG_CPU_FREQ
6383 struct cpufreq_policy policy;
758f588d
BP		 6384 int cpu;
6385
c285545f 6386 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6387 cpu = get_cpu();
6388 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6389 if (policy.cpuinfo.max_freq)
6390 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6391 put_cpu();
c285545f 6392#endif
b820cc0c
ZA		 6393 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6394 CPUFREQ_TRANSITION_NOTIFIER);
6395 }
c285545f 6396 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6397
73c1b41e 6398 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6399 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6400}
6401
dd60d217
AK		 6402DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6403EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6404
f5132b01 6405int kvm_is_in_guest(void)
ff9d07a0 6406{
086c9855 6407 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6408}
6409
6410static int kvm_is_user_mode(void)
6411{
6412 int user_mode = 3;
dcf46b94 6413
086c9855
AS		 6414 if (__this_cpu_read(current_vcpu))
6415 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6416
ff9d07a0
ZY		 6417 return user_mode != 0;
6418}
6419
6420static unsigned long kvm_get_guest_ip(void)
6421{
6422 unsigned long ip = 0;
dcf46b94 6423
086c9855
AS		 6424 if (__this_cpu_read(current_vcpu))
6425 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6426
ff9d07a0
ZY		 6427 return ip;
6428}
6429
6430static struct perf_guest_info_callbacks kvm_guest_cbs = {
6431 .is_in_guest = kvm_is_in_guest,
6432 .is_user_mode = kvm_is_user_mode,
6433 .get_guest_ip = kvm_get_guest_ip,
6434};
6435
ce88decf
XG		 6436static void kvm_set_mmio_spte_mask(void)
6437{
6438 u64 mask;
6439 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6440
6441 /*
6442 * Set the reserved bits and the present bit of an paging-structure
6443 * entry to generate page fault with PFER.RSV = 1.
6444 */
885032b9 6445 /* Mask the reserved physical address bits. */
d1431483 6446 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6447
885032b9 6448 /* Set the present bit. */
ce88decf
XG		 6449 mask |= 1ull;
6450
6451#ifdef CONFIG_X86_64
6452 /*
6453 * If reserved bit is not supported, clear the present bit to disable
6454 * mmio page fault.
6455 */
6456 if (maxphyaddr == 52)
6457 mask &= ~1ull;
6458#endif
6459
dcdca5fe 6460 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6461}
6462
16e8d74d
MT		 6463#ifdef CONFIG_X86_64
6464static void pvclock_gtod_update_fn(struct work_struct *work)
6465{
d828199e
MT		 6466 struct kvm *kvm;
6467
6468 struct kvm_vcpu *vcpu;
6469 int i;
6470
2f303b74 6471 spin_lock(&kvm_lock);
d828199e
MT		 6472 list_for_each_entry(kvm, &vm_list, vm_list)
6473 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6474 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6475 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6476 spin_unlock(&kvm_lock);
16e8d74d
MT		 6477}
6478
6479static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6480
6481/*
6482 * Notification about pvclock gtod data update.
6483 */
6484static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6485 void *priv)
6486{
6487 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6488 struct timekeeper *tk = priv;
6489
6490 update_pvclock_gtod(tk);
6491
6492 /* disable master clock if host does not trust, or does not
b0c39dc6 6493 * use, TSC based clocksource.
16e8d74d 6494 */
b0c39dc6 6495 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6496 atomic_read(&kvm_guest_has_master_clock) != 0)
6497 queue_work(system_long_wq, &pvclock_gtod_work);
6498
6499 return 0;
6500}
6501
6502static struct notifier_block pvclock_gtod_notifier = {
6503 .notifier_call = pvclock_gtod_notify,
6504};
6505#endif
6506
f8c16bba 6507int kvm_arch_init(void *opaque)
043405e1 6508{
b820cc0c 6509 int r;
6b61edf7 6510 struct kvm_x86_ops *ops = opaque;
f8c16bba 6511
f8c16bba
ZX		 6512 if (kvm_x86_ops) {
6513 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6514 r = -EEXIST;
6515 goto out;
f8c16bba
ZX		 6516 }
6517
6518 if (!ops->cpu_has_kvm_support()) {
6519 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6520 r = -EOPNOTSUPP;
6521 goto out;
f8c16bba
ZX		 6522 }
6523 if (ops->disabled_by_bios()) {
6524 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6525 r = -EOPNOTSUPP;
6526 goto out;
f8c16bba
ZX		 6527 }
6528
013f6a5d
MT		 6529 r = -ENOMEM;
6530 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6531 if (!shared_msrs) {
6532 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6533 goto out;
6534 }
6535
97db56ce
AK		 6536 r = kvm_mmu_module_init();
6537 if (r)
013f6a5d 6538 goto out_free_percpu;
97db56ce 6539
ce88decf 6540 kvm_set_mmio_spte_mask();
97db56ce 6541
f8c16bba 6542 kvm_x86_ops = ops;
920c8377 6543
7b52345e 6544 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6545 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6546 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6547 kvm_timer_init();
c8076604 6548
ff9d07a0
ZY		 6549 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6550
d366bf7e 6551 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6552 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6553
c5cc421b 6554 kvm_lapic_init();
16e8d74d
MT		 6555#ifdef CONFIG_X86_64
6556 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6557
5fa4ec9c 6558 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6559 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6560#endif
6561
f8c16bba 6562 return 0;
56c6d28a 6563
013f6a5d
MT		 6564out_free_percpu:
6565 free_percpu(shared_msrs);
56c6d28a 6566out:
56c6d28a 6567 return r;
043405e1 6568}
8776e519 6569
f8c16bba
ZX		 6570void kvm_arch_exit(void)
6571{
0092e434 6572#ifdef CONFIG_X86_64
5fa4ec9c 6573 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6574 clear_hv_tscchange_cb();
6575#endif
cef84c30 6576 kvm_lapic_exit();
ff9d07a0
ZY		 6577 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6578
888d256e
JK		 6579 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6580 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6581 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6582 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6583#ifdef CONFIG_X86_64
6584 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6585#endif
f8c16bba 6586 kvm_x86_ops = NULL;
56c6d28a 6587 kvm_mmu_module_exit();
013f6a5d 6588 free_percpu(shared_msrs);
56c6d28a 6589}
f8c16bba 6590
5cb56059 6591int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6592{
6593 ++vcpu->stat.halt_exits;
35754c98 6594 if (lapic_in_kernel(vcpu)) {
a4535290 6595 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6596 return 1;
6597 } else {
6598 vcpu->run->exit_reason = KVM_EXIT_HLT;
6599 return 0;
6600 }
6601}
5cb56059
JS		 6602EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6603
6604int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6605{
6affcbed
KH		 6606 int ret = kvm_skip_emulated_instruction(vcpu);
6607 /*
6608 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6609 * KVM_EXIT_DEBUG here.
6610 */
6611 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6612}
8776e519
HB		 6613EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6614
8ef81a9a 6615#ifdef CONFIG_X86_64
55dd00a7
MT		 6616static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6617 unsigned long clock_type)
6618{
6619 struct kvm_clock_pairing clock_pairing;
6620 struct timespec ts;
80fbd89c 6621 u64 cycle;
55dd00a7
MT		 6622 int ret;
6623
6624 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6625 return -KVM_EOPNOTSUPP;
6626
6627 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6628 return -KVM_EOPNOTSUPP;
6629
6630 clock_pairing.sec = ts.tv_sec;
6631 clock_pairing.nsec = ts.tv_nsec;
6632 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6633 clock_pairing.flags = 0;
6634
6635 ret = 0;
6636 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6637 sizeof(struct kvm_clock_pairing)))
6638 ret = -KVM_EFAULT;
6639
6640 return ret;
6641}
8ef81a9a 6642#endif
55dd00a7 6643
6aef266c
SV		 6644/*
6645 * kvm_pv_kick_cpu_op: Kick a vcpu.
6646 *
6647 * @apicid - apicid of vcpu to be kicked.
6648 */
6649static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6650{
24d2166b 6651 struct kvm_lapic_irq lapic_irq;
6aef266c 6652
24d2166b
R		 6653 lapic_irq.shorthand = 0;
6654 lapic_irq.dest_mode = 0;
ebd28fcb 6655 lapic_irq.level = 0;
24d2166b 6656 lapic_irq.dest_id = apicid;
93bbf0b8 6657 lapic_irq.msi_redir_hint = false;
6aef266c 6658
24d2166b 6659 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6660 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6661}
6662
d62caabb
AS		 6663void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6664{
6665 vcpu->arch.apicv_active = false;
6666 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6667}
6668
8776e519
HB		 6669int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6670{
6671 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6672 int op_64_bit;
8776e519 6673
696ca779
RK		 6674 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6675 return kvm_hv_hypercall(vcpu);
55cd8e5a 6676
5fdbf976
MT		 6677 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6678 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6679 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6680 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6681 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6682
229456fc 6683 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6684
a449c7aa
NA		 6685 op_64_bit = is_64_bit_mode(vcpu);
6686 if (!op_64_bit) {
8776e519
HB		 6687 nr &= 0xFFFFFFFF;
6688 a0 &= 0xFFFFFFFF;
6689 a1 &= 0xFFFFFFFF;
6690 a2 &= 0xFFFFFFFF;
6691 a3 &= 0xFFFFFFFF;
6692 }
6693
07708c4a
JK		 6694 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6695 ret = -KVM_EPERM;
696ca779 6696 goto out;
07708c4a
JK		 6697 }
6698
8776e519 6699 switch (nr) {
b93463aa
AK		 6700 case KVM_HC_VAPIC_POLL_IRQ:
6701 ret = 0;
6702 break;
6aef266c
SV		 6703 case KVM_HC_KICK_CPU:
6704 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6705 ret = 0;
6706 break;
8ef81a9a 6707#ifdef CONFIG_X86_64
55dd00a7
MT		 6708 case KVM_HC_CLOCK_PAIRING:
6709 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6710 break;
8ef81a9a 6711#endif
8776e519
HB		 6712 default:
6713 ret = -KVM_ENOSYS;
6714 break;
6715 }
696ca779 6716out:
a449c7aa
NA		 6717 if (!op_64_bit)
6718 ret = (u32)ret;
5fdbf976 6719 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 6720
f11c3a8d 6721 ++vcpu->stat.hypercalls;
6356ee0c 6722 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6723}
6724EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6725
b6785def 6726static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6727{
d6aa1000 6728 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6729 char instruction[3];
5fdbf976 6730 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6731
8776e519 6732 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6733
ce2e852e
DV		 6734 return emulator_write_emulated(ctxt, rip, instruction, 3,
6735 &ctxt->exception);
8776e519
HB		 6736}
6737
851ba692 6738static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6739{
782d422b
MG		 6740 return vcpu->run->request_interrupt_window &&
6741 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6742}
6743
851ba692 6744static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6745{
851ba692
AK		 6746 struct kvm_run *kvm_run = vcpu->run;
6747
91586a3b 6748 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6749 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6750 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6751 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6752 kvm_run->ready_for_interrupt_injection =
6753 pic_in_kernel(vcpu->kvm) ||
782d422b 6754 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6755}
6756
95ba8273
GN		 6757static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6758{
6759 int max_irr, tpr;
6760
6761 if (!kvm_x86_ops->update_cr8_intercept)
6762 return;
6763
bce87cce 6764 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6765 return;
6766
d62caabb
AS		 6767 if (vcpu->arch.apicv_active)
6768 return;
6769
8db3baa2
GN		 6770 if (!vcpu->arch.apic->vapic_addr)
6771 max_irr = kvm_lapic_find_highest_irr(vcpu);
6772 else
6773 max_irr = -1;
95ba8273
GN		 6774
6775 if (max_irr != -1)
6776 max_irr >>= 4;
6777
6778 tpr = kvm_lapic_get_cr8(vcpu);
6779
6780 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6781}
6782
b6b8a145 6783static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6784{
b6b8a145
JK		 6785 int r;
6786
95ba8273 6787 /* try to reinject previous events if any */
664f8e26 6788
1a680e35
LA		 6789 if (vcpu->arch.exception.injected)
6790 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6791 /*
a042c26f
LA		 6792 * Do not inject an NMI or interrupt if there is a pending
6793 * exception. Exceptions and interrupts are recognized at
6794 * instruction boundaries, i.e. the start of an instruction.
6795 * Trap-like exceptions, e.g. #DB, have higher priority than
6796 * NMIs and interrupts, i.e. traps are recognized before an
6797 * NMI/interrupt that's pending on the same instruction.
6798 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6799 * priority, but are only generated (pended) during instruction
6800 * execution, i.e. a pending fault-like exception means the
6801 * fault occurred on the *previous* instruction and must be
6802 * serviced prior to recognizing any new events in order to
6803 * fully complete the previous instruction.
664f8e26 6804 */
1a680e35
LA		 6805 else if (!vcpu->arch.exception.pending) {
6806 if (vcpu->arch.nmi_injected)
664f8e26 6807 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6808 else if (vcpu->arch.interrupt.injected)
664f8e26 6809 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6810 }
6811
1a680e35
LA		 6812 /*
6813 * Call check_nested_events() even if we reinjected a previous event
6814 * in order for caller to determine if it should require immediate-exit
6815 * from L2 to L1 due to pending L1 events which require exit
6816 * from L2 to L1.
6817 */
664f8e26
WL		 6818 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6819 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6820 if (r != 0)
6821 return r;
6822 }
6823
6824 /* try to inject new event if pending */
b59bb7bd 6825 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6826 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6827 vcpu->arch.exception.has_error_code,
6828 vcpu->arch.exception.error_code);
d6e8c854 6829
1a680e35 6830 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 6831 vcpu->arch.exception.pending = false;
6832 vcpu->arch.exception.injected = true;
6833
d6e8c854
NA		 6834 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6835 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6836 X86_EFLAGS_RF);
6837
6bdf0662
NA		 6838 if (vcpu->arch.exception.nr == DB_VECTOR &&
6839 (vcpu->arch.dr7 & DR7_GD)) {
6840 vcpu->arch.dr7 &= ~DR7_GD;
6841 kvm_update_dr7(vcpu);
6842 }
6843
cfcd20e5 6844 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 6845 }
6846
6847 /* Don't consider new event if we re-injected an event */
6848 if (kvm_event_needs_reinjection(vcpu))
6849 return 0;
6850
6851 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6852 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6853 vcpu->arch.smi_pending = false;
52797bf9 6854 ++vcpu->arch.smi_count;
ee2cd4b7 6855 enter_smm(vcpu);
c43203ca 6856 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6857 --vcpu->arch.nmi_pending;
6858 vcpu->arch.nmi_injected = true;
6859 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6860 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6861 /*
6862 * Because interrupts can be injected asynchronously, we are
6863 * calling check_nested_events again here to avoid a race condition.
6864 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6865 * proposal and current concerns. Perhaps we should be setting
6866 * KVM_REQ_EVENT only on certain events and not unconditionally?
6867 */
6868 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6869 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6870 if (r != 0)
6871 return r;
6872 }
95ba8273 6873 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6874 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6875 false);
6876 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6877 }
6878 }
ee2cd4b7 6879
b6b8a145 6880 return 0;
95ba8273
GN		 6881}
6882
7460fb4a
AK		 6883static void process_nmi(struct kvm_vcpu *vcpu)
6884{
6885 unsigned limit = 2;
6886
6887 /*
6888 * x86 is limited to one NMI running, and one NMI pending after it.
6889 * If an NMI is already in progress, limit further NMIs to just one.
6890 * Otherwise, allow two (and we'll inject the first one immediately).
6891 */
6892 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6893 limit = 1;
6894
6895 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6896 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6897 kvm_make_request(KVM_REQ_EVENT, vcpu);
6898}
6899
ee2cd4b7 6900static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6901{
6902 u32 flags = 0;
6903 flags |= seg->g << 23;
6904 flags |= seg->db << 22;
6905 flags |= seg->l << 21;
6906 flags |= seg->avl << 20;
6907 flags |= seg->present << 15;
6908 flags |= seg->dpl << 13;
6909 flags |= seg->s << 12;
6910 flags |= seg->type << 8;
6911 return flags;
6912}
6913
ee2cd4b7 6914static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6915{
6916 struct kvm_segment seg;
6917 int offset;
6918
6919 kvm_get_segment(vcpu, &seg, n);
6920 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6921
6922 if (n < 3)
6923 offset = 0x7f84 + n * 12;
6924 else
6925 offset = 0x7f2c + (n - 3) * 12;
6926
6927 put_smstate(u32, buf, offset + 8, seg.base);
6928 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6929 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6930}
6931
efbb288a 6932#ifdef CONFIG_X86_64
ee2cd4b7 6933static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6934{
6935 struct kvm_segment seg;
6936 int offset;
6937 u16 flags;
6938
6939 kvm_get_segment(vcpu, &seg, n);
6940 offset = 0x7e00 + n * 16;
6941
ee2cd4b7 6942 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6943 put_smstate(u16, buf, offset, seg.selector);
6944 put_smstate(u16, buf, offset + 2, flags);
6945 put_smstate(u32, buf, offset + 4, seg.limit);
6946 put_smstate(u64, buf, offset + 8, seg.base);
6947}
efbb288a 6948#endif
660a5d51 6949
ee2cd4b7 6950static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6951{
6952 struct desc_ptr dt;
6953 struct kvm_segment seg;
6954 unsigned long val;
6955 int i;
6956
6957 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6958 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6959 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6960 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6961
6962 for (i = 0; i < 8; i++)
6963 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6964
6965 kvm_get_dr(vcpu, 6, &val);
6966 put_smstate(u32, buf, 0x7fcc, (u32)val);
6967 kvm_get_dr(vcpu, 7, &val);
6968 put_smstate(u32, buf, 0x7fc8, (u32)val);
6969
6970 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6971 put_smstate(u32, buf, 0x7fc4, seg.selector);
6972 put_smstate(u32, buf, 0x7f64, seg.base);
6973 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6974 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6975
6976 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6977 put_smstate(u32, buf, 0x7fc0, seg.selector);
6978 put_smstate(u32, buf, 0x7f80, seg.base);
6979 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6980 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6981
6982 kvm_x86_ops->get_gdt(vcpu, &dt);
6983 put_smstate(u32, buf, 0x7f74, dt.address);
6984 put_smstate(u32, buf, 0x7f70, dt.size);
6985
6986 kvm_x86_ops->get_idt(vcpu, &dt);
6987 put_smstate(u32, buf, 0x7f58, dt.address);
6988 put_smstate(u32, buf, 0x7f54, dt.size);
6989
6990 for (i = 0; i < 6; i++)
ee2cd4b7 6991 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6992
6993 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6994
6995 /* revision id */
6996 put_smstate(u32, buf, 0x7efc, 0x00020000);
6997 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6998}
6999
ee2cd4b7 7000static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7001{
7002#ifdef CONFIG_X86_64
7003 struct desc_ptr dt;
7004 struct kvm_segment seg;
7005 unsigned long val;
7006 int i;
7007
7008 for (i = 0; i < 16; i++)
7009 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7010
7011 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7012 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7013
7014 kvm_get_dr(vcpu, 6, &val);
7015 put_smstate(u64, buf, 0x7f68, val);
7016 kvm_get_dr(vcpu, 7, &val);
7017 put_smstate(u64, buf, 0x7f60, val);
7018
7019 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7020 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7021 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7022
7023 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7024
7025 /* revision id */
7026 put_smstate(u32, buf, 0x7efc, 0x00020064);
7027
7028 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7029
7030 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7031 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7032 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7033 put_smstate(u32, buf, 0x7e94, seg.limit);
7034 put_smstate(u64, buf, 0x7e98, seg.base);
7035
7036 kvm_x86_ops->get_idt(vcpu, &dt);
7037 put_smstate(u32, buf, 0x7e84, dt.size);
7038 put_smstate(u64, buf, 0x7e88, dt.address);
7039
7040 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7041 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7042 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7043 put_smstate(u32, buf, 0x7e74, seg.limit);
7044 put_smstate(u64, buf, 0x7e78, seg.base);
7045
7046 kvm_x86_ops->get_gdt(vcpu, &dt);
7047 put_smstate(u32, buf, 0x7e64, dt.size);
7048 put_smstate(u64, buf, 0x7e68, dt.address);
7049
7050 for (i = 0; i < 6; i++)
ee2cd4b7 7051 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7052#else
7053 WARN_ON_ONCE(1);
7054#endif
7055}
7056
ee2cd4b7 7057static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7058{
660a5d51 7059 struct kvm_segment cs, ds;
18c3626e 7060 struct desc_ptr dt;
660a5d51
PB		 7061 char buf[512];
7062 u32 cr0;
7063
660a5d51 7064 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7065 memset(buf, 0, 512);
d6321d49 7066 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7067 enter_smm_save_state_64(vcpu, buf);
660a5d51 7068 else
ee2cd4b7 7069 enter_smm_save_state_32(vcpu, buf);
660a5d51 7070
0234bf88
LP		 7071 /*
7072 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7073 * vCPU state (e.g. leave guest mode) after we've saved the state into
7074 * the SMM state-save area.
7075 */
7076 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7077
7078 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7079 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7080
7081 if (kvm_x86_ops->get_nmi_mask(vcpu))
7082 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7083 else
7084 kvm_x86_ops->set_nmi_mask(vcpu, true);
7085
7086 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7087 kvm_rip_write(vcpu, 0x8000);
7088
7089 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7090 kvm_x86_ops->set_cr0(vcpu, cr0);
7091 vcpu->arch.cr0 = cr0;
7092
7093 kvm_x86_ops->set_cr4(vcpu, 0);
7094
18c3626e
PB		 7095 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7096 dt.address = dt.size = 0;
7097 kvm_x86_ops->set_idt(vcpu, &dt);
7098
660a5d51
PB		 7099 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7100
7101 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7102 cs.base = vcpu->arch.smbase;
7103
7104 ds.selector = 0;
7105 ds.base = 0;
7106
7107 cs.limit = ds.limit = 0xffffffff;
7108 cs.type = ds.type = 0x3;
7109 cs.dpl = ds.dpl = 0;
7110 cs.db = ds.db = 0;
7111 cs.s = ds.s = 1;
7112 cs.l = ds.l = 0;
7113 cs.g = ds.g = 1;
7114 cs.avl = ds.avl = 0;
7115 cs.present = ds.present = 1;
7116 cs.unusable = ds.unusable = 0;
7117 cs.padding = ds.padding = 0;
7118
7119 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7120 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7121 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7122 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7123 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7124 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7125
d6321d49 7126 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7127 kvm_x86_ops->set_efer(vcpu, 0);
7128
7129 kvm_update_cpuid(vcpu);
7130 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7131}
7132
ee2cd4b7 7133static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7134{
7135 vcpu->arch.smi_pending = true;
7136 kvm_make_request(KVM_REQ_EVENT, vcpu);
7137}
7138
2860c4b1
PB		 7139void kvm_make_scan_ioapic_request(struct kvm *kvm)
7140{
7141 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7142}
7143
3d81bc7e 7144static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7145{
3d81bc7e
YZ		 7146 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7147 return;
c7c9c56c 7148
6308630b 7149 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7150
b053b2ae 7151 if (irqchip_split(vcpu->kvm))
6308630b 7152 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7153 else {
fa59cc00 7154 if (vcpu->arch.apicv_active)
d62caabb 7155 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7156 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7157 }
e40ff1d6
LA		 7158
7159 if (is_guest_mode(vcpu))
7160 vcpu->arch.load_eoi_exitmap_pending = true;
7161 else
7162 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7163}
7164
7165static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7166{
7167 u64 eoi_exit_bitmap[4];
7168
7169 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7170 return;
7171
5c919412
AS		 7172 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7173 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7174 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7175}
7176
b1394e74
RK		 7177void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7178 unsigned long start, unsigned long end)
7179{
7180 unsigned long apic_address;
7181
7182 /*
7183 * The physical address of apic access page is stored in the VMCS.
7184 * Update it when it becomes invalid.
7185 */
7186 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7187 if (start <= apic_address && apic_address < end)
7188 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7189}
7190
4256f43f
TC		 7191void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7192{
c24ae0dc
TC		 7193 struct page *page = NULL;
7194
35754c98 7195 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7196 return;
7197
4256f43f
TC		 7198 if (!kvm_x86_ops->set_apic_access_page_addr)
7199 return;
7200
c24ae0dc 7201 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7202 if (is_error_page(page))
7203 return;
c24ae0dc
TC		 7204 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7205
7206 /*
7207 * Do not pin apic access page in memory, the MMU notifier
7208 * will call us again if it is migrated or swapped out.
7209 */
7210 put_page(page);
4256f43f
TC		 7211}
7212EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7213
9357d939 7214/*
362c698f 7215 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7216 * exiting to the userspace. Otherwise, the value will be returned to the
7217 * userspace.
7218 */
851ba692 7219static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7220{
7221 int r;
62a193ed
MG		 7222 bool req_int_win =
7223 dm_request_for_irq_injection(vcpu) &&
7224 kvm_cpu_accept_dm_intr(vcpu);
7225
730dca42 7226 bool req_immediate_exit = false;
b6c7a5dc 7227
2fa6e1e1 7228 if (kvm_request_pending(vcpu)) {
a8eeb04a 7229 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7230 kvm_mmu_unload(vcpu);
a8eeb04a 7231 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7232 __kvm_migrate_timers(vcpu);
d828199e
MT		 7233 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7234 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7235 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7236 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7237 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7238 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7239 if (unlikely(r))
7240 goto out;
7241 }
a8eeb04a 7242 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7243 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7244 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7245 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7246 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7247 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7248 r = 0;
7249 goto out;
7250 }
a8eeb04a 7251 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7252 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7253 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7254 r = 0;
7255 goto out;
7256 }
af585b92
GN		 7257 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7258 /* Page is swapped out. Do synthetic halt */
7259 vcpu->arch.apf.halted = true;
7260 r = 1;
7261 goto out;
7262 }
c9aaa895
GC		 7263 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7264 record_steal_time(vcpu);
64d60670
PB		 7265 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7266 process_smi(vcpu);
7460fb4a
AK		 7267 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7268 process_nmi(vcpu);
f5132b01 7269 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7270 kvm_pmu_handle_event(vcpu);
f5132b01 7271 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7272 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7273 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7274 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7275 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7276 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7277 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7278 vcpu->run->eoi.vector =
7279 vcpu->arch.pending_ioapic_eoi;
7280 r = 0;
7281 goto out;
7282 }
7283 }
3d81bc7e
YZ		 7284 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7285 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7286 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7287 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7288 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7289 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7290 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7291 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7292 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7293 r = 0;
7294 goto out;
7295 }
e516cebb
AS		 7296 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7297 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7298 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7299 r = 0;
7300 goto out;
7301 }
db397571
AS		 7302 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7303 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7304 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7305 r = 0;
7306 goto out;
7307 }
f3b138c5
AS		 7308
7309 /*
7310 * KVM_REQ_HV_STIMER has to be processed after
7311 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7312 * depend on the guest clock being up-to-date
7313 */
1f4b34f8
AS		 7314 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7315 kvm_hv_process_stimers(vcpu);
2f52d58c 7316 }
b93463aa 7317
b463a6f7 7318 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7319 ++vcpu->stat.req_event;
66450a21
JK		 7320 kvm_apic_accept_events(vcpu);
7321 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7322 r = 1;
7323 goto out;
7324 }
7325
b6b8a145
JK		 7326 if (inject_pending_event(vcpu, req_int_win) != 0)
7327 req_immediate_exit = true;
321c5658 7328 else {
cc3d967f 7329 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7330 *
cc3d967f
LP		 7331 * SMIs have three cases:
7332 * 1) They can be nested, and then there is nothing to
7333 * do here because RSM will cause a vmexit anyway.
7334 * 2) There is an ISA-specific reason why SMI cannot be
7335 * injected, and the moment when this changes can be
7336 * intercepted.
7337 * 3) Or the SMI can be pending because
7338 * inject_pending_event has completed the injection
7339 * of an IRQ or NMI from the previous vmexit, and
7340 * then we request an immediate exit to inject the
7341 * SMI.
c43203ca
PB		 7342 */
7343 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7344 if (!kvm_x86_ops->enable_smi_window(vcpu))
7345 req_immediate_exit = true;
321c5658
YS		 7346 if (vcpu->arch.nmi_pending)
7347 kvm_x86_ops->enable_nmi_window(vcpu);
7348 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7349 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7350 WARN_ON(vcpu->arch.exception.pending);
321c5658 7351 }
b463a6f7
AK		 7352
7353 if (kvm_lapic_enabled(vcpu)) {
7354 update_cr8_intercept(vcpu);
7355 kvm_lapic_sync_to_vapic(vcpu);
7356 }
7357 }
7358
d8368af8
AK		 7359 r = kvm_mmu_reload(vcpu);
7360 if (unlikely(r)) {
d905c069 7361 goto cancel_injection;
d8368af8
AK		 7362 }
7363
b6c7a5dc
HB		 7364 preempt_disable();
7365
7366 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7367
7368 /*
7369 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7370 * IPI are then delayed after guest entry, which ensures that they
7371 * result in virtual interrupt delivery.
7372 */
7373 local_irq_disable();
6b7e2d09
XG		 7374 vcpu->mode = IN_GUEST_MODE;
7375
01b71917
MT		 7376 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7377
0f127d12 7378 /*
b95234c8 7379 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7380 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7381 *
7382 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7383 * pairs with the memory barrier implicit in pi_test_and_set_on
7384 * (see vmx_deliver_posted_interrupt).
7385 *
7386 * 3) This also orders the write to mode from any reads to the page
7387 * tables done while the VCPU is running. Please see the comment
7388 * in kvm_flush_remote_tlbs.
6b7e2d09 7389 */
01b71917 7390 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7391
b95234c8
PB		 7392 /*
7393 * This handles the case where a posted interrupt was
7394 * notified with kvm_vcpu_kick.
7395 */
fa59cc00
LA		 7396 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7397 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7398
2fa6e1e1 7399 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7400 || need_resched() || signal_pending(current)) {
6b7e2d09 7401 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7402 smp_wmb();
6c142801
AK		 7403 local_irq_enable();
7404 preempt_enable();
01b71917 7405 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7406 r = 1;
d905c069 7407 goto cancel_injection;
6c142801
AK		 7408 }
7409
fc5b7f3b
DM		 7410 kvm_load_guest_xcr0(vcpu);
7411
c43203ca
PB		 7412 if (req_immediate_exit) {
7413 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7414 smp_send_reschedule(vcpu->cpu);
c43203ca 7415 }
d6185f20 7416
8b89fe1f 7417 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7418 if (lapic_timer_advance_ns)
7419 wait_lapic_expire(vcpu);
6edaa530 7420 guest_enter_irqoff();
b6c7a5dc 7421
42dbaa5a 7422 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7423 set_debugreg(0, 7);
7424 set_debugreg(vcpu->arch.eff_db[0], 0);
7425 set_debugreg(vcpu->arch.eff_db[1], 1);
7426 set_debugreg(vcpu->arch.eff_db[2], 2);
7427 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7428 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7429 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7430 }
b6c7a5dc 7431
851ba692 7432 kvm_x86_ops->run(vcpu);
b6c7a5dc 7433
c77fb5fe
PB		 7434 /*
7435 * Do this here before restoring debug registers on the host. And
7436 * since we do this before handling the vmexit, a DR access vmexit
7437 * can (a) read the correct value of the debug registers, (b) set
7438 * KVM_DEBUGREG_WONT_EXIT again.
7439 */
7440 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7441 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7442 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7443 kvm_update_dr0123(vcpu);
7444 kvm_update_dr6(vcpu);
7445 kvm_update_dr7(vcpu);
7446 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7447 }
7448
24f1e32c
FW		 7449 /*
7450 * If the guest has used debug registers, at least dr7
7451 * will be disabled while returning to the host.
7452 * If we don't have active breakpoints in the host, we don't
7453 * care about the messed up debug address registers. But if
7454 * we have some of them active, restore the old state.
7455 */
59d8eb53 7456 if (hw_breakpoint_active())
24f1e32c 7457 hw_breakpoint_restore();
42dbaa5a 7458
4ba76538 7459 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7460
6b7e2d09 7461 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7462 smp_wmb();
a547c6db 7463
fc5b7f3b
DM		 7464 kvm_put_guest_xcr0(vcpu);
7465
dd60d217 7466 kvm_before_interrupt(vcpu);
a547c6db 7467 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7468 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7469
7470 ++vcpu->stat.exits;
7471
f2485b3e 7472 guest_exit_irqoff();
b6c7a5dc 7473
f2485b3e 7474 local_irq_enable();
b6c7a5dc
HB		 7475 preempt_enable();
7476
f656ce01 7477 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7478
b6c7a5dc
HB		 7479 /*
7480 * Profile KVM exit RIPs:
7481 */
7482 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7483 unsigned long rip = kvm_rip_read(vcpu);
7484 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7485 }
7486
cc578287
ZA		 7487 if (unlikely(vcpu->arch.tsc_always_catchup))
7488 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7489
5cfb1d5a
MT		 7490 if (vcpu->arch.apic_attention)
7491 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7492
618232e2 7493 vcpu->arch.gpa_available = false;
851ba692 7494 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7495 return r;
7496
7497cancel_injection:
7498 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7499 if (unlikely(vcpu->arch.apic_attention))
7500 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7501out:
7502 return r;
7503}
b6c7a5dc 7504
362c698f
PB		 7505static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7506{
bf9f6ac8
FW		 7507 if (!kvm_arch_vcpu_runnable(vcpu) &&
7508 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7509 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7510 kvm_vcpu_block(vcpu);
7511 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7512
7513 if (kvm_x86_ops->post_block)
7514 kvm_x86_ops->post_block(vcpu);
7515
9c8fd1ba
PB		 7516 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7517 return 1;
7518 }
362c698f
PB		 7519
7520 kvm_apic_accept_events(vcpu);
7521 switch(vcpu->arch.mp_state) {
7522 case KVM_MP_STATE_HALTED:
7523 vcpu->arch.pv.pv_unhalted = false;
7524 vcpu->arch.mp_state =
7525 KVM_MP_STATE_RUNNABLE;
7526 case KVM_MP_STATE_RUNNABLE:
7527 vcpu->arch.apf.halted = false;
7528 break;
7529 case KVM_MP_STATE_INIT_RECEIVED:
7530 break;
7531 default:
7532 return -EINTR;
7533 break;
7534 }
7535 return 1;
7536}
09cec754 7537
5d9bc648
PB		 7538static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7539{
0ad3bed6
PB		 7540 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7541 kvm_x86_ops->check_nested_events(vcpu, false);
7542
5d9bc648
PB		 7543 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7544 !vcpu->arch.apf.halted);
7545}
7546
362c698f 7547static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7548{
7549 int r;
f656ce01 7550 struct kvm *kvm = vcpu->kvm;
d7690175 7551
f656ce01 7552 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7553
362c698f 7554 for (;;) {
58f800d5 7555 if (kvm_vcpu_running(vcpu)) {
851ba692 7556 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7557 } else {
362c698f 7558 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7559 }
7560
09cec754
GN		 7561 if (r <= 0)
7562 break;
7563
72875d8a 7564 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7565 if (kvm_cpu_has_pending_timer(vcpu))
7566 kvm_inject_pending_timer_irqs(vcpu);
7567
782d422b
MG		 7568 if (dm_request_for_irq_injection(vcpu) &&
7569 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7570 r = 0;
7571 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7572 ++vcpu->stat.request_irq_exits;
362c698f 7573 break;
09cec754 7574 }
af585b92
GN		 7575
7576 kvm_check_async_pf_completion(vcpu);
7577
09cec754
GN		 7578 if (signal_pending(current)) {
7579 r = -EINTR;
851ba692 7580 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7581 ++vcpu->stat.signal_exits;
362c698f 7582 break;
09cec754
GN		 7583 }
7584 if (need_resched()) {
f656ce01 7585 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7586 cond_resched();
f656ce01 7587 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7588 }
b6c7a5dc
HB		 7589 }
7590
f656ce01 7591 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7592
7593 return r;
7594}
7595
716d51ab
GN		 7596static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7597{
7598 int r;
7599 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7600 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7601 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7602 if (r != EMULATE_DONE)
7603 return 0;
7604 return 1;
7605}
7606
7607static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7608{
7609 BUG_ON(!vcpu->arch.pio.count);
7610
7611 return complete_emulated_io(vcpu);
7612}
7613
f78146b0
AK		 7614/*
7615 * Implements the following, as a state machine:
7616 *
7617 * read:
7618 * for each fragment
87da7e66
XG		 7619 * for each mmio piece in the fragment
7620 * write gpa, len
7621 * exit
7622 * copy data
f78146b0
AK		 7623 * execute insn
7624 *
7625 * write:
7626 * for each fragment
87da7e66
XG		 7627 * for each mmio piece in the fragment
7628 * write gpa, len
7629 * copy data
7630 * exit
f78146b0 7631 */
716d51ab 7632static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7633{
7634 struct kvm_run *run = vcpu->run;
f78146b0 7635 struct kvm_mmio_fragment *frag;
87da7e66 7636 unsigned len;
5287f194 7637
716d51ab 7638 BUG_ON(!vcpu->mmio_needed);
5287f194 7639
716d51ab 7640 /* Complete previous fragment */
87da7e66
XG		 7641 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7642 len = min(8u, frag->len);
716d51ab 7643 if (!vcpu->mmio_is_write)
87da7e66
XG		 7644 memcpy(frag->data, run->mmio.data, len);
7645
7646 if (frag->len <= 8) {
7647 /* Switch to the next fragment. */
7648 frag++;
7649 vcpu->mmio_cur_fragment++;
7650 } else {
7651 /* Go forward to the next mmio piece. */
7652 frag->data += len;
7653 frag->gpa += len;
7654 frag->len -= len;
7655 }
7656
a08d3b3b 7657 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7658 vcpu->mmio_needed = 0;
0912c977
PB		 7659
7660 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7661 if (vcpu->mmio_is_write)
716d51ab
GN		 7662 return 1;
7663 vcpu->mmio_read_completed = 1;
7664 return complete_emulated_io(vcpu);
7665 }
87da7e66 7666
716d51ab
GN		 7667 run->exit_reason = KVM_EXIT_MMIO;
7668 run->mmio.phys_addr = frag->gpa;
7669 if (vcpu->mmio_is_write)
87da7e66
XG		 7670 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7671 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7672 run->mmio.is_write = vcpu->mmio_is_write;
7673 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7674 return 0;
5287f194
AK		 7675}
7676
b6c7a5dc
HB		 7677int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7678{
7679 int r;
b6c7a5dc 7680
accb757d 7681 vcpu_load(vcpu);
20b7035c 7682 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7683 kvm_load_guest_fpu(vcpu);
7684
a4535290 7685 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7686 if (kvm_run->immediate_exit) {
7687 r = -EINTR;
7688 goto out;
7689 }
b6c7a5dc 7690 kvm_vcpu_block(vcpu);
66450a21 7691 kvm_apic_accept_events(vcpu);
72875d8a 7692 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7693 r = -EAGAIN;
a0595000
JS		 7694 if (signal_pending(current)) {
7695 r = -EINTR;
7696 vcpu->run->exit_reason = KVM_EXIT_INTR;
7697 ++vcpu->stat.signal_exits;
7698 }
ac9f6dc0 7699 goto out;
b6c7a5dc
HB		 7700 }
7701
01643c51
KH		 7702 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7703 r = -EINVAL;
7704 goto out;
7705 }
7706
7707 if (vcpu->run->kvm_dirty_regs) {
7708 r = sync_regs(vcpu);
7709 if (r != 0)
7710 goto out;
7711 }
7712
b6c7a5dc 7713 /* re-sync apic's tpr */
35754c98 7714 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7715 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7716 r = -EINVAL;
7717 goto out;
7718 }
7719 }
b6c7a5dc 7720
716d51ab
GN		 7721 if (unlikely(vcpu->arch.complete_userspace_io)) {
7722 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7723 vcpu->arch.complete_userspace_io = NULL;
7724 r = cui(vcpu);
7725 if (r <= 0)
5663d8f9 7726 goto out;
716d51ab
GN		 7727 } else
7728 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7729
460df4c1
PB		 7730 if (kvm_run->immediate_exit)
7731 r = -EINTR;
7732 else
7733 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7734
7735out:
5663d8f9 7736 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7737 if (vcpu->run->kvm_valid_regs)
7738 store_regs(vcpu);
f1d86e46 7739 post_kvm_run_save(vcpu);
20b7035c 7740 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7741
accb757d 7742 vcpu_put(vcpu);
b6c7a5dc
HB		 7743 return r;
7744}
7745
01643c51 7746static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7747{
7ae441ea
GN		 7748 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7749 /*
7750 * We are here if userspace calls get_regs() in the middle of
7751 * instruction emulation. Registers state needs to be copied
4a969980 7752 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7753 * that usually, but some bad designed PV devices (vmware
7754 * backdoor interface) need this to work
7755 */
dd856efa 7756 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7757 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7758 }
5fdbf976
MT		 7759 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7760 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7761 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7762 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7763 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7764 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7765 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7766 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7767#ifdef CONFIG_X86_64
5fdbf976
MT		 7768 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7769 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7770 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7771 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7772 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7773 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7774 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7775 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7776#endif
7777
5fdbf976 7778 regs->rip = kvm_rip_read(vcpu);
91586a3b 7779 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7780}
b6c7a5dc 7781
01643c51
KH		 7782int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7783{
7784 vcpu_load(vcpu);
7785 __get_regs(vcpu, regs);
1fc9b76b 7786 vcpu_put(vcpu);
b6c7a5dc
HB		 7787 return 0;
7788}
7789
01643c51 7790static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7791{
7ae441ea
GN		 7792 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7793 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7794
5fdbf976
MT		 7795 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7796 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7797 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7798 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7799 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7800 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7801 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7802 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7803#ifdef CONFIG_X86_64
5fdbf976
MT		 7804 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7805 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7806 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7807 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7808 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7809 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7810 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7811 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7812#endif
7813
5fdbf976 7814 kvm_rip_write(vcpu, regs->rip);
d73235d1 7815 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7816
b4f14abd
JK		 7817 vcpu->arch.exception.pending = false;
7818
3842d135 7819 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7820}
3842d135 7821
01643c51
KH		 7822int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7823{
7824 vcpu_load(vcpu);
7825 __set_regs(vcpu, regs);
875656fe 7826 vcpu_put(vcpu);
b6c7a5dc
HB		 7827 return 0;
7828}
7829
b6c7a5dc
HB		 7830void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7831{
7832 struct kvm_segment cs;
7833
3e6e0aab 7834 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7835 *db = cs.db;
7836 *l = cs.l;
7837}
7838EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7839
01643c51 7840static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7841{
89a27f4d 7842 struct desc_ptr dt;
b6c7a5dc 7843
3e6e0aab
GT		 7844 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7845 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7846 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7847 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7848 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7849 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7850
3e6e0aab
GT		 7851 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7852 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7853
7854 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7855 sregs->idt.limit = dt.size;
7856 sregs->idt.base = dt.address;
b6c7a5dc 7857 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7858 sregs->gdt.limit = dt.size;
7859 sregs->gdt.base = dt.address;
b6c7a5dc 7860
4d4ec087 7861 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7862 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7863 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7864 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7865 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7866 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7867 sregs->apic_base = kvm_get_apic_base(vcpu);
7868
923c61bb 7869 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7870
04140b41 7871 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7872 set_bit(vcpu->arch.interrupt.nr,
7873 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7874}
16d7a191 7875
01643c51
KH		 7876int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7877 struct kvm_sregs *sregs)
7878{
7879 vcpu_load(vcpu);
7880 __get_sregs(vcpu, sregs);
bcdec41c 7881 vcpu_put(vcpu);
b6c7a5dc
HB		 7882 return 0;
7883}
7884
62d9f0db
MT		 7885int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7886 struct kvm_mp_state *mp_state)
7887{
fd232561
CD		 7888 vcpu_load(vcpu);
7889
66450a21 7890 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7891 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7892 vcpu->arch.pv.pv_unhalted)
7893 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7894 else
7895 mp_state->mp_state = vcpu->arch.mp_state;
7896
fd232561 7897 vcpu_put(vcpu);
62d9f0db
MT		 7898 return 0;
7899}
7900
7901int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7902 struct kvm_mp_state *mp_state)
7903{
e83dff5e
CD		 7904 int ret = -EINVAL;
7905
7906 vcpu_load(vcpu);
7907
bce87cce 7908 if (!lapic_in_kernel(vcpu) &&
66450a21 7909 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7910 goto out;
66450a21 7911
28bf2888
DH		 7912 /* INITs are latched while in SMM */
7913 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7914 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7915 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7916 goto out;
28bf2888 7917
66450a21
JK		 7918 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7919 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7920 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7921 } else
7922 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7923 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7924
7925 ret = 0;
7926out:
7927 vcpu_put(vcpu);
7928 return ret;
62d9f0db
MT		 7929}
7930
7f3d35fd
KW		 7931int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7932 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7933{
9d74191a 7934 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7935 int ret;
e01c2426 7936
8ec4722d 7937 init_emulate_ctxt(vcpu);
c697518a 7938
7f3d35fd 7939 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7940 has_error_code, error_code);
c697518a 7941
c697518a 7942 if (ret)
19d04437 7943 return EMULATE_FAIL;
37817f29 7944
9d74191a
TY		 7945 kvm_rip_write(vcpu, ctxt->eip);
7946 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7947 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7948 return EMULATE_DONE;
37817f29
IE		 7949}
7950EXPORT_SYMBOL_GPL(kvm_task_switch);
7951
3140c156 7952static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 7953{
37b95951 7954 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7955 /*
7956 * When EFER.LME and CR0.PG are set, the processor is in
7957 * 64-bit mode (though maybe in a 32-bit code segment).
7958 * CR4.PAE and EFER.LMA must be set.
7959 */
37b95951 7960 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7961 || !(sregs->efer & EFER_LMA))
7962 return -EINVAL;
7963 } else {
7964 /*
7965 * Not in 64-bit mode: EFER.LMA is clear and the code
7966 * segment cannot be 64-bit.
7967 */
7968 if (sregs->efer & EFER_LMA || sregs->cs.l)
7969 return -EINVAL;
7970 }
7971
7972 return 0;
7973}
7974
01643c51 7975static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7976{
58cb628d 7977 struct msr_data apic_base_msr;
b6c7a5dc 7978 int mmu_reset_needed = 0;
c4d21882 7979 int cpuid_update_needed = 0;
63f42e02 7980 int pending_vec, max_bits, idx;
89a27f4d 7981 struct desc_ptr dt;
b4ef9d4e
CD		 7982 int ret = -EINVAL;
7983
d6321d49
RK		 7984 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7985 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7986 goto out;
6d1068b3 7987
f2981033 7988 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 7989 goto out;
f2981033 7990
d3802286
JM		 7991 apic_base_msr.data = sregs->apic_base;
7992 apic_base_msr.host_initiated = true;
7993 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7994 goto out;
6d1068b3 7995
89a27f4d
GN		 7996 dt.size = sregs->idt.limit;
7997 dt.address = sregs->idt.base;
b6c7a5dc 7998 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7999 dt.size = sregs->gdt.limit;
8000 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8001 kvm_x86_ops->set_gdt(vcpu, &dt);
8002
ad312c7c 8003 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8004 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8005 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8006 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8007
2d3ad1f4 8008 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8009
f6801dff 8010 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8011 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8012
4d4ec087 8013 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8014 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8015 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8016
fc78f519 8017 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8018 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8019 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8020 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8021 if (cpuid_update_needed)
00b27a3e 8022 kvm_update_cpuid(vcpu);
63f42e02
XG		 8023
8024 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 8025 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 8026 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8027 mmu_reset_needed = 1;
8028 }
63f42e02 8029 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8030
8031 if (mmu_reset_needed)
8032 kvm_mmu_reset_context(vcpu);
8033
a50abc3b 8034 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8035 pending_vec = find_first_bit(
8036 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8037 if (pending_vec < max_bits) {
66fd3f7f 8038 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8039 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8040 }
8041
3e6e0aab
GT		 8042 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8043 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8044 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8045 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8046 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8047 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8048
3e6e0aab
GT		 8049 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8050 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8051
5f0269f5
ME		 8052 update_cr8_intercept(vcpu);
8053
9c3e4aab 8054 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8055 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8056 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8057 !is_protmode(vcpu))
9c3e4aab
MT		 8058 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8059
3842d135
AK		 8060 kvm_make_request(KVM_REQ_EVENT, vcpu);
8061
b4ef9d4e
CD		 8062 ret = 0;
8063out:
01643c51
KH		 8064 return ret;
8065}
8066
8067int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8068 struct kvm_sregs *sregs)
8069{
8070 int ret;
8071
8072 vcpu_load(vcpu);
8073 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8074 vcpu_put(vcpu);
8075 return ret;
b6c7a5dc
HB		 8076}
8077
d0bfb940
JK		 8078int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8079 struct kvm_guest_debug *dbg)
b6c7a5dc 8080{
355be0b9 8081 unsigned long rflags;
ae675ef0 8082 int i, r;
b6c7a5dc 8083
66b56562
CD		 8084 vcpu_load(vcpu);
8085
4f926bf2
JK		 8086 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8087 r = -EBUSY;
8088 if (vcpu->arch.exception.pending)
2122ff5e 8089 goto out;
4f926bf2
JK		 8090 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8091 kvm_queue_exception(vcpu, DB_VECTOR);
8092 else
8093 kvm_queue_exception(vcpu, BP_VECTOR);
8094 }
8095
91586a3b
JK		 8096 /*
8097 * Read rflags as long as potentially injected trace flags are still
8098 * filtered out.
8099 */
8100 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8101
8102 vcpu->guest_debug = dbg->control;
8103 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8104 vcpu->guest_debug = 0;
8105
8106 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8107 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8108 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8109 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8110 } else {
8111 for (i = 0; i < KVM_NR_DB_REGS; i++)
8112 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8113 }
c8639010 8114 kvm_update_dr7(vcpu);
ae675ef0 8115
f92653ee
JK		 8116 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8117 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8118 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8119
91586a3b
JK		 8120 /*
8121 * Trigger an rflags update that will inject or remove the trace
8122 * flags.
8123 */
8124 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8125
a96036b8 8126 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8127
4f926bf2 8128 r = 0;
d0bfb940 8129
2122ff5e 8130out:
66b56562 8131 vcpu_put(vcpu);
b6c7a5dc
HB		 8132 return r;
8133}
8134
8b006791
ZX		 8135/*
8136 * Translate a guest virtual address to a guest physical address.
8137 */
8138int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8139 struct kvm_translation *tr)
8140{
8141 unsigned long vaddr = tr->linear_address;
8142 gpa_t gpa;
f656ce01 8143 int idx;
8b006791 8144
1da5b61d
CD		 8145 vcpu_load(vcpu);
8146
f656ce01 8147 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8148 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8149 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8150 tr->physical_address = gpa;
8151 tr->valid = gpa != UNMAPPED_GVA;
8152 tr->writeable = 1;
8153 tr->usermode = 0;
8b006791 8154
1da5b61d 8155 vcpu_put(vcpu);
8b006791
ZX		 8156 return 0;
8157}
8158
d0752060
HB		 8159int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8160{
1393123e 8161 struct fxregs_state *fxsave;
d0752060 8162
1393123e 8163 vcpu_load(vcpu);
d0752060 8164
1393123e 8165 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8166 memcpy(fpu->fpr, fxsave->st_space, 128);
8167 fpu->fcw = fxsave->cwd;
8168 fpu->fsw = fxsave->swd;
8169 fpu->ftwx = fxsave->twd;
8170 fpu->last_opcode = fxsave->fop;
8171 fpu->last_ip = fxsave->rip;
8172 fpu->last_dp = fxsave->rdp;
8173 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8174
1393123e 8175 vcpu_put(vcpu);
d0752060
HB		 8176 return 0;
8177}
8178
8179int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8180{
6a96bc7f
CD		 8181 struct fxregs_state *fxsave;
8182
8183 vcpu_load(vcpu);
8184
8185 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8186
d0752060
HB		 8187 memcpy(fxsave->st_space, fpu->fpr, 128);
8188 fxsave->cwd = fpu->fcw;
8189 fxsave->swd = fpu->fsw;
8190 fxsave->twd = fpu->ftwx;
8191 fxsave->fop = fpu->last_opcode;
8192 fxsave->rip = fpu->last_ip;
8193 fxsave->rdp = fpu->last_dp;
8194 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8195
6a96bc7f 8196 vcpu_put(vcpu);
d0752060
HB		 8197 return 0;
8198}
8199
01643c51
KH		 8200static void store_regs(struct kvm_vcpu *vcpu)
8201{
8202 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8203
8204 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8205 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8206
8207 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8208 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8209
8210 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8211 kvm_vcpu_ioctl_x86_get_vcpu_events(
8212 vcpu, &vcpu->run->s.regs.events);
8213}
8214
8215static int sync_regs(struct kvm_vcpu *vcpu)
8216{
8217 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8218 return -EINVAL;
8219
8220 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8221 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8222 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8223 }
8224 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8225 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8226 return -EINVAL;
8227 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8228 }
8229 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8230 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8231 vcpu, &vcpu->run->s.regs.events))
8232 return -EINVAL;
8233 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8234 }
8235
8236 return 0;
8237}
8238
0ee6a517 8239static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8240{
bf935b0b 8241 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8242 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8243 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8244 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8245
2acf923e
DC		 8246 /*
8247 * Ensure guest xcr0 is valid for loading
8248 */
d91cab78 8249 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8250
ad312c7c 8251 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8252}
d0752060 8253
f775b13e 8254/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8255void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8256{
f775b13e
RR		 8257 preempt_disable();
8258 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8259 /* PKRU is separately restored in kvm_x86_ops->run. */
8260 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8261 ~XFEATURE_MASK_PKRU);
f775b13e 8262 preempt_enable();
0c04851c 8263 trace_kvm_fpu(1);
d0752060 8264}
d0752060 8265
f775b13e 8266/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8267void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8268{
f775b13e 8269 preempt_disable();
4f836347 8270 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8271 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8272 preempt_enable();
f096ed85 8273 ++vcpu->stat.fpu_reload;
0c04851c 8274 trace_kvm_fpu(0);
d0752060 8275}
e9b11c17
ZX		 8276
8277void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8278{
bd768e14
IY		 8279 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8280
12f9a48f 8281 kvmclock_reset(vcpu);
7f1ea208 8282
e9b11c17 8283 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8284 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8285}
8286
8287struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8288 unsigned int id)
8289{
c447e76b
LL		 8290 struct kvm_vcpu *vcpu;
8291
b0c39dc6 8292 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8293 printk_once(KERN_WARNING
8294 "kvm: SMP vm created on host with unstable TSC; "
8295 "guest TSC will not be reliable\n");
c447e76b
LL		 8296
8297 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8298
c447e76b 8299 return vcpu;
26e5215f 8300}
e9b11c17 8301
26e5215f
AK		 8302int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8303{
19efffa2 8304 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8305 vcpu_load(vcpu);
d28bc9dd 8306 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8307 kvm_mmu_setup(vcpu);
e9b11c17 8308 vcpu_put(vcpu);
ec7660cc 8309 return 0;
e9b11c17
ZX		 8310}
8311
31928aa5 8312void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8313{
8fe8ab46 8314 struct msr_data msr;
332967a3 8315 struct kvm *kvm = vcpu->kvm;
42897d86 8316
d3457c87
RK		 8317 kvm_hv_vcpu_postcreate(vcpu);
8318
ec7660cc 8319 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8320 return;
ec7660cc 8321 vcpu_load(vcpu);
8fe8ab46
WA		 8322 msr.data = 0x0;
8323 msr.index = MSR_IA32_TSC;
8324 msr.host_initiated = true;
8325 kvm_write_tsc(vcpu, &msr);
42897d86 8326 vcpu_put(vcpu);
ec7660cc 8327 mutex_unlock(&vcpu->mutex);
42897d86 8328
630994b3
MT		 8329 if (!kvmclock_periodic_sync)
8330 return;
8331
332967a3
AJ		 8332 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8333 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8334}
8335
d40ccc62 8336void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8337{
344d9588
GN		 8338 vcpu->arch.apf.msr_val = 0;
8339
ec7660cc 8340 vcpu_load(vcpu);
e9b11c17
ZX		 8341 kvm_mmu_unload(vcpu);
8342 vcpu_put(vcpu);
8343
8344 kvm_x86_ops->vcpu_free(vcpu);
8345}
8346
d28bc9dd 8347void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8348{
b7e31be3
RK		 8349 kvm_lapic_reset(vcpu, init_event);
8350
e69fab5d
PB		 8351 vcpu->arch.hflags = 0;
8352
c43203ca 8353 vcpu->arch.smi_pending = 0;
52797bf9 8354 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8355 atomic_set(&vcpu->arch.nmi_queued, 0);
8356 vcpu->arch.nmi_pending = 0;
448fa4a9 8357 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8358 kvm_clear_interrupt_queue(vcpu);
8359 kvm_clear_exception_queue(vcpu);
664f8e26 8360 vcpu->arch.exception.pending = false;
448fa4a9 8361
42dbaa5a 8362 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8363 kvm_update_dr0123(vcpu);
6f43ed01 8364 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8365 kvm_update_dr6(vcpu);
42dbaa5a 8366 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8367 kvm_update_dr7(vcpu);
42dbaa5a 8368
1119022c
NA		 8369 vcpu->arch.cr2 = 0;
8370
3842d135 8371 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8372 vcpu->arch.apf.msr_val = 0;
c9aaa895 8373 vcpu->arch.st.msr_val = 0;
3842d135 8374
12f9a48f
GC		 8375 kvmclock_reset(vcpu);
8376
af585b92
GN		 8377 kvm_clear_async_pf_completion_queue(vcpu);
8378 kvm_async_pf_hash_reset(vcpu);
8379 vcpu->arch.apf.halted = false;
3842d135 8380
a554d207
WL		 8381 if (kvm_mpx_supported()) {
8382 void *mpx_state_buffer;
8383
8384 /*
8385 * To avoid have the INIT path from kvm_apic_has_events() that be
8386 * called with loaded FPU and does not let userspace fix the state.
8387 */
f775b13e
RR		 8388 if (init_event)
8389 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8390 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8391 XFEATURE_MASK_BNDREGS);
8392 if (mpx_state_buffer)
8393 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8394 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8395 XFEATURE_MASK_BNDCSR);
8396 if (mpx_state_buffer)
8397 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8398 if (init_event)
8399 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8400 }
8401
64d60670 8402 if (!init_event) {
d28bc9dd 8403 kvm_pmu_reset(vcpu);
64d60670 8404 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8405
8406 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8407 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8408
8409 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8410 }
f5132b01 8411
66f7b72e
JS		 8412 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8413 vcpu->arch.regs_avail = ~0;
8414 vcpu->arch.regs_dirty = ~0;
8415
a554d207
WL		 8416 vcpu->arch.ia32_xss = 0;
8417
d28bc9dd 8418 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8419}
8420
2b4a273b 8421void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8422{
8423 struct kvm_segment cs;
8424
8425 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8426 cs.selector = vector << 8;
8427 cs.base = vector << 12;
8428 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8429 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8430}
8431
13a34e06 8432int kvm_arch_hardware_enable(void)
e9b11c17 8433{
ca84d1a2
ZA		 8434 struct kvm *kvm;
8435 struct kvm_vcpu *vcpu;
8436 int i;
0dd6a6ed
ZA		 8437 int ret;
8438 u64 local_tsc;
8439 u64 max_tsc = 0;
8440 bool stable, backwards_tsc = false;
18863bdd
AK		 8441
8442 kvm_shared_msr_cpu_online();
13a34e06 8443 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8444 if (ret != 0)
8445 return ret;
8446
4ea1636b 8447 local_tsc = rdtsc();
b0c39dc6 8448 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8449 list_for_each_entry(kvm, &vm_list, vm_list) {
8450 kvm_for_each_vcpu(i, vcpu, kvm) {
8451 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8452 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8453 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8454 backwards_tsc = true;
8455 if (vcpu->arch.last_host_tsc > max_tsc)
8456 max_tsc = vcpu->arch.last_host_tsc;
8457 }
8458 }
8459 }
8460
8461 /*
8462 * Sometimes, even reliable TSCs go backwards. This happens on
8463 * platforms that reset TSC during suspend or hibernate actions, but
8464 * maintain synchronization. We must compensate. Fortunately, we can
8465 * detect that condition here, which happens early in CPU bringup,
8466 * before any KVM threads can be running. Unfortunately, we can't
8467 * bring the TSCs fully up to date with real time, as we aren't yet far
8468 * enough into CPU bringup that we know how much real time has actually
108b249c 8469 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8470 * variables that haven't been updated yet.
8471 *
8472 * So we simply find the maximum observed TSC above, then record the
8473 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8474 * the adjustment will be applied. Note that we accumulate
8475 * adjustments, in case multiple suspend cycles happen before some VCPU
8476 * gets a chance to run again. In the event that no KVM threads get a
8477 * chance to run, we will miss the entire elapsed period, as we'll have
8478 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8479 * loose cycle time. This isn't too big a deal, since the loss will be
8480 * uniform across all VCPUs (not to mention the scenario is extremely
8481 * unlikely). It is possible that a second hibernate recovery happens
8482 * much faster than a first, causing the observed TSC here to be
8483 * smaller; this would require additional padding adjustment, which is
8484 * why we set last_host_tsc to the local tsc observed here.
8485 *
8486 * N.B. - this code below runs only on platforms with reliable TSC,
8487 * as that is the only way backwards_tsc is set above. Also note
8488 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8489 * have the same delta_cyc adjustment applied if backwards_tsc
8490 * is detected. Note further, this adjustment is only done once,
8491 * as we reset last_host_tsc on all VCPUs to stop this from being
8492 * called multiple times (one for each physical CPU bringup).
8493 *
4a969980 8494 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8495 * will be compensated by the logic in vcpu_load, which sets the TSC to
8496 * catchup mode. This will catchup all VCPUs to real time, but cannot
8497 * guarantee that they stay in perfect synchronization.
8498 */
8499 if (backwards_tsc) {
8500 u64 delta_cyc = max_tsc - local_tsc;
8501 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8502 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8503 kvm_for_each_vcpu(i, vcpu, kvm) {
8504 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8505 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8506 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8507 }
8508
8509 /*
8510 * We have to disable TSC offset matching.. if you were
8511 * booting a VM while issuing an S4 host suspend....
8512 * you may have some problem. Solving this issue is
8513 * left as an exercise to the reader.
8514 */
8515 kvm->arch.last_tsc_nsec = 0;
8516 kvm->arch.last_tsc_write = 0;
8517 }
8518
8519 }
8520 return 0;
e9b11c17
ZX		 8521}
8522
13a34e06 8523void kvm_arch_hardware_disable(void)
e9b11c17 8524{
13a34e06
RK		 8525 kvm_x86_ops->hardware_disable();
8526 drop_user_return_notifiers();
e9b11c17
ZX		 8527}
8528
8529int kvm_arch_hardware_setup(void)
8530{
9e9c3fe4
NA		 8531 int r;
8532
8533 r = kvm_x86_ops->hardware_setup();
8534 if (r != 0)
8535 return r;
8536
35181e86
HZ		 8537 if (kvm_has_tsc_control) {
8538 /*
8539 * Make sure the user can only configure tsc_khz values that
8540 * fit into a signed integer.
8541 * A min value is not calculated needed because it will always
8542 * be 1 on all machines.
8543 */
8544 u64 max = min(0x7fffffffULL,
8545 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8546 kvm_max_guest_tsc_khz = max;
8547
ad721883 8548 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8549 }
ad721883 8550
9e9c3fe4
NA		 8551 kvm_init_msr_list();
8552 return 0;
e9b11c17
ZX		 8553}
8554
8555void kvm_arch_hardware_unsetup(void)
8556{
8557 kvm_x86_ops->hardware_unsetup();
8558}
8559
8560void kvm_arch_check_processor_compat(void *rtn)
8561{
8562 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8563}
8564
8565bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8566{
8567 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8568}
8569EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8570
8571bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8572{
8573 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8574}
8575
54e9818f 8576struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8577EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8578
e9b11c17
ZX		 8579int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8580{
8581 struct page *page;
e9b11c17
ZX		 8582 int r;
8583
b2a05fef 8584 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8585 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8586 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8587 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8588 else
a4535290 8589 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8590
8591 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8592 if (!page) {
8593 r = -ENOMEM;
8594 goto fail;
8595 }
ad312c7c 8596 vcpu->arch.pio_data = page_address(page);
e9b11c17 8597
cc578287 8598 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8599
e9b11c17
ZX		 8600 r = kvm_mmu_create(vcpu);
8601 if (r < 0)
8602 goto fail_free_pio_data;
8603
26de7988 8604 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8605 r = kvm_create_lapic(vcpu);
8606 if (r < 0)
8607 goto fail_mmu_destroy;
54e9818f
GN		 8608 } else
8609 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8610
890ca9ae
HY		 8611 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8612 GFP_KERNEL);
8613 if (!vcpu->arch.mce_banks) {
8614 r = -ENOMEM;
443c39bc 8615 goto fail_free_lapic;
890ca9ae
HY		 8616 }
8617 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8618
f1797359
WY		 8619 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8620 r = -ENOMEM;
f5f48ee1 8621 goto fail_free_mce_banks;
f1797359 8622 }
f5f48ee1 8623
0ee6a517 8624 fx_init(vcpu);
66f7b72e 8625
4344ee98 8626 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8627
5a4f55cd
EK		 8628 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8629
74545705
RK		 8630 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8631
af585b92 8632 kvm_async_pf_hash_reset(vcpu);
f5132b01 8633 kvm_pmu_init(vcpu);
af585b92 8634
1c1a9ce9 8635 vcpu->arch.pending_external_vector = -1;
de63ad4c 8636 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8637
5c919412
AS		 8638 kvm_hv_vcpu_init(vcpu);
8639
e9b11c17 8640 return 0;
0ee6a517 8641
f5f48ee1
SY		 8642fail_free_mce_banks:
8643 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8644fail_free_lapic:
8645 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8646fail_mmu_destroy:
8647 kvm_mmu_destroy(vcpu);
8648fail_free_pio_data:
ad312c7c 8649 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8650fail:
8651 return r;
8652}
8653
8654void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8655{
f656ce01
MT		 8656 int idx;
8657
1f4b34f8 8658 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8659 kvm_pmu_destroy(vcpu);
36cb93fd 8660 kfree(vcpu->arch.mce_banks);
e9b11c17 8661 kvm_free_lapic(vcpu);
f656ce01 8662 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8663 kvm_mmu_destroy(vcpu);
f656ce01 8664 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8665 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8666 if (!lapic_in_kernel(vcpu))
54e9818f 8667 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8668}
d19a9cd2 8669
e790d9ef
RK		 8670void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8671{
ae97a3b8 8672 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8673}
8674
e08b9637 8675int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8676{
e08b9637
CO		 8677 if (type)
8678 return -EINVAL;
8679
6ef768fa 8680 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8681 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8682 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8683 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8684 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8685
5550af4d
SY		 8686 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8687 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8688 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8689 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8690 &kvm->arch.irq_sources_bitmap);
5550af4d 8691
038f8c11 8692 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8693 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8694 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8695
108b249c 8696 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8697 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8698
7e44e449 8699 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8700 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8701
cbc0236a 8702 kvm_hv_init_vm(kvm);
0eb05bf2 8703 kvm_page_track_init(kvm);
13d268ca 8704 kvm_mmu_init_vm(kvm);
0eb05bf2 8705
03543133
SS		 8706 if (kvm_x86_ops->vm_init)
8707 return kvm_x86_ops->vm_init(kvm);
8708
d89f5eff 8709 return 0;
d19a9cd2
ZX		 8710}
8711
8712static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8713{
ec7660cc 8714 vcpu_load(vcpu);
d19a9cd2
ZX		 8715 kvm_mmu_unload(vcpu);
8716 vcpu_put(vcpu);
8717}
8718
8719static void kvm_free_vcpus(struct kvm *kvm)
8720{
8721 unsigned int i;
988a2cae 8722 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8723
8724 /*
8725 * Unpin any mmu pages first.
8726 */
af585b92
GN		 8727 kvm_for_each_vcpu(i, vcpu, kvm) {
8728 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8729 kvm_unload_vcpu_mmu(vcpu);
af585b92 8730 }
988a2cae
GN		 8731 kvm_for_each_vcpu(i, vcpu, kvm)
8732 kvm_arch_vcpu_free(vcpu);
8733
8734 mutex_lock(&kvm->lock);
8735 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8736 kvm->vcpus[i] = NULL;
d19a9cd2 8737
988a2cae
GN		 8738 atomic_set(&kvm->online_vcpus, 0);
8739 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8740}
8741
ad8ba2cd
SY		 8742void kvm_arch_sync_events(struct kvm *kvm)
8743{
332967a3 8744 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8745 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8746 kvm_free_pit(kvm);
ad8ba2cd
SY		 8747}
8748
1d8007bd 8749int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8750{
8751 int i, r;
25188b99 8752 unsigned long hva;
f0d648bd
PB		 8753 struct kvm_memslots *slots = kvm_memslots(kvm);
8754 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8755
8756 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8757 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8758 return -EINVAL;
9da0e4d5 8759
f0d648bd
PB		 8760 slot = id_to_memslot(slots, id);
8761 if (size) {
b21629da 8762 if (slot->npages)
f0d648bd
PB		 8763 return -EEXIST;
8764
8765 /*
8766 * MAP_SHARED to prevent internal slot pages from being moved
8767 * by fork()/COW.
8768 */
8769 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8770 MAP_SHARED | MAP_ANONYMOUS, 0);
8771 if (IS_ERR((void *)hva))
8772 return PTR_ERR((void *)hva);
8773 } else {
8774 if (!slot->npages)
8775 return 0;
8776
8777 hva = 0;
8778 }
8779
8780 old = *slot;
9da0e4d5 8781 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8782 struct kvm_userspace_memory_region m;
9da0e4d5 8783
1d8007bd
PB		 8784 m.slot = id | (i << 16);
8785 m.flags = 0;
8786 m.guest_phys_addr = gpa;
f0d648bd 8787 m.userspace_addr = hva;
1d8007bd 8788 m.memory_size = size;
9da0e4d5
PB		 8789 r = __kvm_set_memory_region(kvm, &m);
8790 if (r < 0)
8791 return r;
8792 }
8793
103c763c
EB		 8794 if (!size)
8795 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8796
9da0e4d5
PB		 8797 return 0;
8798}
8799EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8800
1d8007bd 8801int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8802{
8803 int r;
8804
8805 mutex_lock(&kvm->slots_lock);
1d8007bd 8806 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8807 mutex_unlock(&kvm->slots_lock);
8808
8809 return r;
8810}
8811EXPORT_SYMBOL_GPL(x86_set_memory_region);
8812
d19a9cd2
ZX		 8813void kvm_arch_destroy_vm(struct kvm *kvm)
8814{
27469d29
AH		 8815 if (current->mm == kvm->mm) {
8816 /*
8817 * Free memory regions allocated on behalf of userspace,
8818 * unless the the memory map has changed due to process exit
8819 * or fd copying.
8820 */
1d8007bd
PB		 8821 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8822 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8823 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8824 }
03543133
SS		 8825 if (kvm_x86_ops->vm_destroy)
8826 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8827 kvm_pic_destroy(kvm);
8828 kvm_ioapic_destroy(kvm);
d19a9cd2 8829 kvm_free_vcpus(kvm);
af1bae54 8830 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8831 kvm_mmu_uninit_vm(kvm);
2beb6dad 8832 kvm_page_track_cleanup(kvm);
cbc0236a 8833 kvm_hv_destroy_vm(kvm);
d19a9cd2 8834}
0de10343 8835
5587027c 8836void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8837 struct kvm_memory_slot *dont)
8838{
8839 int i;
8840
d89cc617
TY		 8841 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8842 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8843 kvfree(free->arch.rmap[i]);
d89cc617 8844 free->arch.rmap[i] = NULL;
77d11309 8845 }
d89cc617
TY		 8846 if (i == 0)
8847 continue;
8848
8849 if (!dont || free->arch.lpage_info[i - 1] !=
8850 dont->arch.lpage_info[i - 1]) {
548ef284 8851 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8852 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8853 }
8854 }
21ebbeda
XG		 8855
8856 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8857}
8858
5587027c
AK		 8859int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8860 unsigned long npages)
db3fe4eb
TY		 8861{
8862 int i;
8863
d89cc617 8864 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8865 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8866 unsigned long ugfn;
8867 int lpages;
d89cc617 8868 int level = i + 1;
db3fe4eb
TY		 8869
8870 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8871 slot->base_gfn, level) + 1;
8872
d89cc617 8873 slot->arch.rmap[i] =
a7c3e901 8874 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8875 if (!slot->arch.rmap[i])
77d11309 8876 goto out_free;
d89cc617
TY		 8877 if (i == 0)
8878 continue;
77d11309 8879
a7c3e901 8880 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8881 if (!linfo)
db3fe4eb
TY		 8882 goto out_free;
8883
92f94f1e
XG		 8884 slot->arch.lpage_info[i - 1] = linfo;
8885
db3fe4eb 8886 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8887 linfo[0].disallow_lpage = 1;
db3fe4eb 8888 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8889 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8890 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8891 /*
8892 * If the gfn and userspace address are not aligned wrt each
8893 * other, or if explicitly asked to, disable large page
8894 * support for this slot
8895 */
8896 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8897 !kvm_largepages_enabled()) {
8898 unsigned long j;
8899
8900 for (j = 0; j < lpages; ++j)
92f94f1e 8901 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8902 }
8903 }
8904
21ebbeda
XG		 8905 if (kvm_page_track_create_memslot(slot, npages))
8906 goto out_free;
8907
db3fe4eb
TY		 8908 return 0;
8909
8910out_free:
d89cc617 8911 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8912 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8913 slot->arch.rmap[i] = NULL;
8914 if (i == 0)
8915 continue;
8916
548ef284 8917 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8918 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8919 }
8920 return -ENOMEM;
8921}
8922
15f46015 8923void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8924{
e6dff7d1
TY		 8925 /*
8926 * memslots->generation has been incremented.
8927 * mmio generation may have reached its maximum value.
8928 */
54bf36aa 8929 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8930}
8931
f7784b8e
MT		 8932int kvm_arch_prepare_memory_region(struct kvm *kvm,
8933 struct kvm_memory_slot *memslot,
09170a49 8934 const struct kvm_userspace_memory_region *mem,
7b6195a9 8935 enum kvm_mr_change change)
0de10343 8936{
f7784b8e
MT		 8937 return 0;
8938}
8939
88178fd4
KH		 8940static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8941 struct kvm_memory_slot *new)
8942{
8943 /* Still write protect RO slot */
8944 if (new->flags & KVM_MEM_READONLY) {
8945 kvm_mmu_slot_remove_write_access(kvm, new);
8946 return;
8947 }
8948
8949 /*
8950 * Call kvm_x86_ops dirty logging hooks when they are valid.
8951 *
8952 * kvm_x86_ops->slot_disable_log_dirty is called when:
8953 *
8954 * - KVM_MR_CREATE with dirty logging is disabled
8955 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8956 *
8957 * The reason is, in case of PML, we need to set D-bit for any slots
8958 * with dirty logging disabled in order to eliminate unnecessary GPA
8959 * logging in PML buffer (and potential PML buffer full VMEXT). This
8960 * guarantees leaving PML enabled during guest's lifetime won't have
8961 * any additonal overhead from PML when guest is running with dirty
8962 * logging disabled for memory slots.
8963 *
8964 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8965 * to dirty logging mode.
8966 *
8967 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8968 *
8969 * In case of write protect:
8970 *
8971 * Write protect all pages for dirty logging.
8972 *
8973 * All the sptes including the large sptes which point to this
8974 * slot are set to readonly. We can not create any new large
8975 * spte on this slot until the end of the logging.
8976 *
8977 * See the comments in fast_page_fault().
8978 */
8979 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8980 if (kvm_x86_ops->slot_enable_log_dirty)
8981 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8982 else
8983 kvm_mmu_slot_remove_write_access(kvm, new);
8984 } else {
8985 if (kvm_x86_ops->slot_disable_log_dirty)
8986 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8987 }
8988}
8989
f7784b8e 8990void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8991 const struct kvm_userspace_memory_region *mem,
8482644a 8992 const struct kvm_memory_slot *old,
f36f3f28 8993 const struct kvm_memory_slot *new,
8482644a 8994 enum kvm_mr_change change)
f7784b8e 8995{
8482644a 8996 int nr_mmu_pages = 0;
f7784b8e 8997
48c0e4e9
XG		 8998 if (!kvm->arch.n_requested_mmu_pages)
8999 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9000
48c0e4e9 9001 if (nr_mmu_pages)
0de10343 9002 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9003
3ea3b7fa
WL		 9004 /*
9005 * Dirty logging tracks sptes in 4k granularity, meaning that large
9006 * sptes have to be split. If live migration is successful, the guest
9007 * in the source machine will be destroyed and large sptes will be
9008 * created in the destination. However, if the guest continues to run
9009 * in the source machine (for example if live migration fails), small
9010 * sptes will remain around and cause bad performance.
9011 *
9012 * Scan sptes if dirty logging has been stopped, dropping those
9013 * which can be collapsed into a single large-page spte. Later
9014 * page faults will create the large-page sptes.
9015 */
9016 if ((change != KVM_MR_DELETE) &&
9017 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9018 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9019 kvm_mmu_zap_collapsible_sptes(kvm, new);
9020
c972f3b1 9021 /*
88178fd4 9022 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9023 *
88178fd4
KH		 9024 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9025 * been zapped so no dirty logging staff is needed for old slot. For
9026 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9027 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9028 *
9029 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9030 */
88178fd4 9031 if (change != KVM_MR_DELETE)
f36f3f28 9032 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9033}
1d737c8a 9034
2df72e9b 9035void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9036{
6ca18b69 9037 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9038}
9039
2df72e9b
MT		 9040void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9041 struct kvm_memory_slot *slot)
9042{
ae7cd873 9043 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9044}
9045
5d9bc648
PB		 9046static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9047{
9048 if (!list_empty_careful(&vcpu->async_pf.done))
9049 return true;
9050
9051 if (kvm_apic_has_events(vcpu))
9052 return true;
9053
9054 if (vcpu->arch.pv.pv_unhalted)
9055 return true;
9056
a5f01f8e
WL		 9057 if (vcpu->arch.exception.pending)
9058 return true;
9059
47a66eed
Z		 9060 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9061 (vcpu->arch.nmi_pending &&
9062 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9063 return true;
9064
47a66eed
Z		 9065 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9066 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9067 return true;
9068
5d9bc648
PB		 9069 if (kvm_arch_interrupt_allowed(vcpu) &&
9070 kvm_cpu_has_interrupt(vcpu))
9071 return true;
9072
1f4b34f8
AS		 9073 if (kvm_hv_has_stimer_pending(vcpu))
9074 return true;
9075
5d9bc648
PB		 9076 return false;
9077}
9078
1d737c8a
ZX		 9079int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9080{
5d9bc648 9081 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9082}
5736199a 9083
199b5763
LM		 9084bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9085{
de63ad4c 9086 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9087}
9088
b6d33834 9089int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9090{
b6d33834 9091 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9092}
78646121
GN		 9093
9094int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9095{
9096 return kvm_x86_ops->interrupt_allowed(vcpu);
9097}
229456fc 9098
82b32774 9099unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9100{
82b32774
NA		 9101 if (is_64_bit_mode(vcpu))
9102 return kvm_rip_read(vcpu);
9103 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9104 kvm_rip_read(vcpu));
9105}
9106EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9107
82b32774
NA		 9108bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9109{
9110 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9111}
9112EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9113
94fe45da
JK		 9114unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9115{
9116 unsigned long rflags;
9117
9118 rflags = kvm_x86_ops->get_rflags(vcpu);
9119 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9120 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9121 return rflags;
9122}
9123EXPORT_SYMBOL_GPL(kvm_get_rflags);
9124
6addfc42 9125static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9126{
9127 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9128 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9129 rflags |= X86_EFLAGS_TF;
94fe45da 9130 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9131}
9132
9133void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9134{
9135 __kvm_set_rflags(vcpu, rflags);
3842d135 9136 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9137}
9138EXPORT_SYMBOL_GPL(kvm_set_rflags);
9139
56028d08
GN		 9140void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9141{
9142 int r;
9143
fb67e14f 9144 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9145 work->wakeup_all)
56028d08
GN		 9146 return;
9147
9148 r = kvm_mmu_reload(vcpu);
9149 if (unlikely(r))
9150 return;
9151
fb67e14f
XG		 9152 if (!vcpu->arch.mmu.direct_map &&
9153 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9154 return;
9155
56028d08
GN		 9156 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9157}
9158
af585b92
GN		 9159static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9160{
9161 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9162}
9163
9164static inline u32 kvm_async_pf_next_probe(u32 key)
9165{
9166 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9167}
9168
9169static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9170{
9171 u32 key = kvm_async_pf_hash_fn(gfn);
9172
9173 while (vcpu->arch.apf.gfns[key] != ~0)
9174 key = kvm_async_pf_next_probe(key);
9175
9176 vcpu->arch.apf.gfns[key] = gfn;
9177}
9178
9179static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9180{
9181 int i;
9182 u32 key = kvm_async_pf_hash_fn(gfn);
9183
9184 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9185 (vcpu->arch.apf.gfns[key] != gfn &&
9186 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9187 key = kvm_async_pf_next_probe(key);
9188
9189 return key;
9190}
9191
9192bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9193{
9194 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9195}
9196
9197static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9198{
9199 u32 i, j, k;
9200
9201 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9202 while (true) {
9203 vcpu->arch.apf.gfns[i] = ~0;
9204 do {
9205 j = kvm_async_pf_next_probe(j);
9206 if (vcpu->arch.apf.gfns[j] == ~0)
9207 return;
9208 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9209 /*
9210 * k lies cyclically in ]i,j]
9211 * | i.k.j |
9212 * |....j i.k.| or |.k..j i...|
9213 */
9214 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9215 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9216 i = j;
9217 }
9218}
9219
7c90705b
GN		 9220static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9221{
4e335d9e
PB		 9222
9223 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9224 sizeof(val));
7c90705b
GN		 9225}
9226
9a6e7c39
WL		 9227static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9228{
9229
9230 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9231 sizeof(u32));
9232}
9233
af585b92
GN		 9234void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9235 struct kvm_async_pf *work)
9236{
6389ee94
AK		 9237 struct x86_exception fault;
9238
7c90705b 9239 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9240 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9241
9242 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9243 (vcpu->arch.apf.send_user_only &&
9244 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9245 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9246 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9247 fault.vector = PF_VECTOR;
9248 fault.error_code_valid = true;
9249 fault.error_code = 0;
9250 fault.nested_page_fault = false;
9251 fault.address = work->arch.token;
adfe20fb 9252 fault.async_page_fault = true;
6389ee94 9253 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9254 }
af585b92
GN		 9255}
9256
9257void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9258 struct kvm_async_pf *work)
9259{
6389ee94 9260 struct x86_exception fault;
9a6e7c39 9261 u32 val;
6389ee94 9262
f2e10669 9263 if (work->wakeup_all)
7c90705b
GN		 9264 work->arch.token = ~0; /* broadcast wakeup */
9265 else
9266 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9267 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9268
9a6e7c39
WL		 9269 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9270 !apf_get_user(vcpu, &val)) {
9271 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9272 vcpu->arch.exception.pending &&
9273 vcpu->arch.exception.nr == PF_VECTOR &&
9274 !apf_put_user(vcpu, 0)) {
9275 vcpu->arch.exception.injected = false;
9276 vcpu->arch.exception.pending = false;
9277 vcpu->arch.exception.nr = 0;
9278 vcpu->arch.exception.has_error_code = false;
9279 vcpu->arch.exception.error_code = 0;
9280 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9281 fault.vector = PF_VECTOR;
9282 fault.error_code_valid = true;
9283 fault.error_code = 0;
9284 fault.nested_page_fault = false;
9285 fault.address = work->arch.token;
9286 fault.async_page_fault = true;
9287 kvm_inject_page_fault(vcpu, &fault);
9288 }
7c90705b 9289 }
e6d53e3b 9290 vcpu->arch.apf.halted = false;
a4fa1635 9291 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9292}
9293
9294bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9295{
9296 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9297 return true;
9298 else
9bc1f09f 9299 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9300}
9301
5544eb9b
PB		 9302void kvm_arch_start_assignment(struct kvm *kvm)
9303{
9304 atomic_inc(&kvm->arch.assigned_device_count);
9305}
9306EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9307
9308void kvm_arch_end_assignment(struct kvm *kvm)
9309{
9310 atomic_dec(&kvm->arch.assigned_device_count);
9311}
9312EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9313
9314bool kvm_arch_has_assigned_device(struct kvm *kvm)
9315{
9316 return atomic_read(&kvm->arch.assigned_device_count);
9317}
9318EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9319
e0f0bbc5
AW		 9320void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9321{
9322 atomic_inc(&kvm->arch.noncoherent_dma_count);
9323}
9324EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9325
9326void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9327{
9328 atomic_dec(&kvm->arch.noncoherent_dma_count);
9329}
9330EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9331
9332bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9333{
9334 return atomic_read(&kvm->arch.noncoherent_dma_count);
9335}
9336EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9337
14717e20
AW		 9338bool kvm_arch_has_irq_bypass(void)
9339{
9340 return kvm_x86_ops->update_pi_irte != NULL;
9341}
9342
87276880
FW		 9343int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9344 struct irq_bypass_producer *prod)
9345{
9346 struct kvm_kernel_irqfd *irqfd =
9347 container_of(cons, struct kvm_kernel_irqfd, consumer);
9348
14717e20 9349 irqfd->producer = prod;
87276880 9350
14717e20
AW		 9351 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9352 prod->irq, irqfd->gsi, 1);
87276880
FW		 9353}
9354
9355void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9356 struct irq_bypass_producer *prod)
9357{
9358 int ret;
9359 struct kvm_kernel_irqfd *irqfd =
9360 container_of(cons, struct kvm_kernel_irqfd, consumer);
9361
87276880
FW		 9362 WARN_ON(irqfd->producer != prod);
9363 irqfd->producer = NULL;
9364
9365 /*
9366 * When producer of consumer is unregistered, we change back to
9367 * remapped mode, so we can re-use the current implementation
bb3541f1 9368 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9369 * int this case doesn't want to receive the interrupts.
9370 */
9371 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9372 if (ret)
9373 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9374 " fails: %d\n", irqfd->consumer.token, ret);
9375}
9376
9377int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9378 uint32_t guest_irq, bool set)
9379{
9380 if (!kvm_x86_ops->update_pi_irte)
9381 return -EINVAL;
9382
9383 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9384}
9385
52004014
FW		 9386bool kvm_vector_hashing_enabled(void)
9387{
9388 return vector_hashing;
9389}
9390EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9391
229456fc 9392EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9393EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9394EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9395EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9396EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9397EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9398EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9399EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9400EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9401EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9402EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9403EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9404EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9405EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9406EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9407EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9408EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9409EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9410EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)