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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
88197e6a | 21 | #include "ioapic.h" |
1d737c8a | 22 | #include "mmu.h" |
7837699f | 23 | #include "i8254.h" |
37817f29 | 24 | #include "tss.h" |
5fdbf976 | 25 | #include "kvm_cache_regs.h" |
2f728d66 | 26 | #include "kvm_emulate.h" |
26eef70c | 27 | #include "x86.h" |
00b27a3e | 28 | #include "cpuid.h" |
474a5bb9 | 29 | #include "pmu.h" |
e83d5887 | 30 | #include "hyperv.h" |
8df14af4 | 31 | #include "lapic.h" |
23200b7a | 32 | #include "xen.h" |
313a3dc7 | 33 | |
18068523 | 34 | #include <linux/clocksource.h> |
4d5c5d0f | 35 | #include <linux/interrupt.h> |
313a3dc7 CO |
36 | #include <linux/kvm.h> |
37 | #include <linux/fs.h> | |
38 | #include <linux/vmalloc.h> | |
1767e931 PG |
39 | #include <linux/export.h> |
40 | #include <linux/moduleparam.h> | |
0de10343 | 41 | #include <linux/mman.h> |
2bacc55c | 42 | #include <linux/highmem.h> |
19de40a8 | 43 | #include <linux/iommu.h> |
62c476c7 | 44 | #include <linux/intel-iommu.h> |
c8076604 | 45 | #include <linux/cpufreq.h> |
18863bdd | 46 | #include <linux/user-return-notifier.h> |
a983fb23 | 47 | #include <linux/srcu.h> |
5a0e3ad6 | 48 | #include <linux/slab.h> |
ff9d07a0 | 49 | #include <linux/perf_event.h> |
7bee342a | 50 | #include <linux/uaccess.h> |
af585b92 | 51 | #include <linux/hash.h> |
a1b60c1c | 52 | #include <linux/pci.h> |
16e8d74d MT |
53 | #include <linux/timekeeper_internal.h> |
54 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
55 | #include <linux/kvm_irqfd.h> |
56 | #include <linux/irqbypass.h> | |
3905f9ad | 57 | #include <linux/sched/stat.h> |
0c5f81da | 58 | #include <linux/sched/isolation.h> |
d0ec49d4 | 59 | #include <linux/mem_encrypt.h> |
72c3c0fe | 60 | #include <linux/entry-kvm.h> |
7d62874f | 61 | #include <linux/suspend.h> |
3905f9ad | 62 | |
aec51dc4 | 63 | #include <trace/events/kvm.h> |
2ed152af | 64 | |
24f1e32c | 65 | #include <asm/debugreg.h> |
d825ed0a | 66 | #include <asm/msr.h> |
a5f61300 | 67 | #include <asm/desc.h> |
890ca9ae | 68 | #include <asm/mce.h> |
784a4661 | 69 | #include <asm/pkru.h> |
f89e32e0 | 70 | #include <linux/kernel_stat.h> |
78f7f1e5 | 71 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 72 | #include <asm/pvclock.h> |
217fc9cf | 73 | #include <asm/div64.h> |
efc64404 | 74 | #include <asm/irq_remapping.h> |
b0c39dc6 | 75 | #include <asm/mshyperv.h> |
0092e434 | 76 | #include <asm/hypervisor.h> |
9715092f | 77 | #include <asm/tlbflush.h> |
bf8c55d8 | 78 | #include <asm/intel_pt.h> |
b3dc0695 | 79 | #include <asm/emulate_prefix.h> |
fe7e9488 | 80 | #include <asm/sgx.h> |
dd2cb348 | 81 | #include <clocksource/hyperv_timer.h> |
043405e1 | 82 | |
d1898b73 DH |
83 | #define CREATE_TRACE_POINTS |
84 | #include "trace.h" | |
85 | ||
313a3dc7 | 86 | #define MAX_IO_MSRS 256 |
890ca9ae | 87 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
88 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
89 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 90 | |
0f65dd70 | 91 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 92 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 93 | |
50a37eb4 JR |
94 | /* EFER defaults: |
95 | * - enable syscall per default because its emulated by KVM | |
96 | * - enable LME and LMA per default on 64 bit KVM | |
97 | */ | |
98 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
99 | static |
100 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 101 | #else |
1260edbe | 102 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 103 | #endif |
313a3dc7 | 104 | |
b11306b5 SC |
105 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
106 | ||
0dbb1123 AK |
107 | #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) |
108 | ||
c519265f RK |
109 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
110 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 111 | |
cb142eb7 | 112 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 113 | static void process_nmi(struct kvm_vcpu *vcpu); |
1f7becf1 | 114 | static void process_smi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 115 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 116 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
117 | static void store_regs(struct kvm_vcpu *vcpu); |
118 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 119 | |
6dba9403 ML |
120 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); |
121 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); | |
122 | ||
afaf0b2f | 123 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
5fdbf976 | 124 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 125 | |
9af5471b JB |
126 | #define KVM_X86_OP(func) \ |
127 | DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ | |
128 | *(((struct kvm_x86_ops *)0)->func)); | |
129 | #define KVM_X86_OP_NULL KVM_X86_OP | |
130 | #include <asm/kvm-x86-ops.h> | |
131 | EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); | |
132 | EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); | |
133 | EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); | |
134 | ||
893590c7 | 135 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 136 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 137 | |
d855066f | 138 | bool __read_mostly report_ignored_msrs = true; |
fab0aa3b | 139 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); |
d855066f | 140 | EXPORT_SYMBOL_GPL(report_ignored_msrs); |
fab0aa3b | 141 | |
4c27625b | 142 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
143 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
144 | ||
630994b3 MT |
145 | static bool __read_mostly kvmclock_periodic_sync = true; |
146 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
147 | ||
893590c7 | 148 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 149 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 150 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 151 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
152 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
153 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
154 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
155 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
156 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
157 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
fe6b6bc8 CQ |
158 | bool __read_mostly kvm_has_bus_lock_exit; |
159 | EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); | |
92a1f12d | 160 | |
cc578287 | 161 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 162 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
163 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
164 | ||
c3941d9e SC |
165 | /* |
166 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
d9f6e12f | 167 | * adaptive tuning starting from default advancement of 1000ns. '0' disables |
c3941d9e | 168 | * advancement entirely. Any other value is used as-is and disables adaptive |
d9f6e12f | 169 | * tuning, i.e. allows privileged userspace to set an exact advancement time. |
c3941d9e SC |
170 | */ |
171 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 172 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 173 | |
52004014 FW |
174 | static bool __read_mostly vector_hashing = true; |
175 | module_param(vector_hashing, bool, S_IRUGO); | |
176 | ||
c4ae60e4 LA |
177 | bool __read_mostly enable_vmware_backdoor = false; |
178 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
179 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
180 | ||
6c86eedc WL |
181 | static bool __read_mostly force_emulation_prefix = false; |
182 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
183 | ||
0c5f81da WL |
184 | int __read_mostly pi_inject_timer = -1; |
185 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
186 | ||
7e34fbd0 SC |
187 | /* |
188 | * Restoring the host value for MSRs that are only consumed when running in | |
189 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
190 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
191 | */ | |
192 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 193 | |
7e34fbd0 | 194 | struct kvm_user_return_msrs { |
18863bdd AK |
195 | struct user_return_notifier urn; |
196 | bool registered; | |
7e34fbd0 | 197 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
198 | u64 host; |
199 | u64 curr; | |
7e34fbd0 | 200 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
201 | }; |
202 | ||
9cc39a5a SC |
203 | u32 __read_mostly kvm_nr_uret_msrs; |
204 | EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); | |
205 | static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; | |
7e34fbd0 | 206 | static struct kvm_user_return_msrs __percpu *user_return_msrs; |
18863bdd | 207 | |
cfc48181 SC |
208 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
209 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
210 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
211 | | XFEATURE_MASK_PKRU) | |
212 | ||
91661989 SC |
213 | u64 __read_mostly host_efer; |
214 | EXPORT_SYMBOL_GPL(host_efer); | |
215 | ||
b96e6506 | 216 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
217 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
218 | ||
fdf513e3 VK |
219 | bool __read_mostly enable_apicv = true; |
220 | EXPORT_SYMBOL_GPL(enable_apicv); | |
221 | ||
86137773 TL |
222 | u64 __read_mostly host_xss; |
223 | EXPORT_SYMBOL_GPL(host_xss); | |
408e9a31 PB |
224 | u64 __read_mostly supported_xss; |
225 | EXPORT_SYMBOL_GPL(supported_xss); | |
139a12cf | 226 | |
fcfe1bae JZ |
227 | const struct _kvm_stats_desc kvm_vm_stats_desc[] = { |
228 | KVM_GENERIC_VM_STATS(), | |
229 | STATS_DESC_COUNTER(VM, mmu_shadow_zapped), | |
230 | STATS_DESC_COUNTER(VM, mmu_pte_write), | |
231 | STATS_DESC_COUNTER(VM, mmu_pde_zapped), | |
232 | STATS_DESC_COUNTER(VM, mmu_flooded), | |
233 | STATS_DESC_COUNTER(VM, mmu_recycled), | |
234 | STATS_DESC_COUNTER(VM, mmu_cache_miss), | |
235 | STATS_DESC_ICOUNTER(VM, mmu_unsync), | |
71f51d2c MZ |
236 | STATS_DESC_ICOUNTER(VM, pages_4k), |
237 | STATS_DESC_ICOUNTER(VM, pages_2m), | |
238 | STATS_DESC_ICOUNTER(VM, pages_1g), | |
fcfe1bae | 239 | STATS_DESC_ICOUNTER(VM, nx_lpage_splits), |
ec1cf69c | 240 | STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), |
bc9e9e67 | 241 | STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) |
fcfe1bae | 242 | }; |
fcfe1bae JZ |
243 | |
244 | const struct kvm_stats_header kvm_vm_stats_header = { | |
245 | .name_size = KVM_STATS_NAME_SIZE, | |
246 | .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), | |
247 | .id_offset = sizeof(struct kvm_stats_header), | |
248 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
249 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
250 | sizeof(kvm_vm_stats_desc), | |
251 | }; | |
252 | ||
ce55c049 JZ |
253 | const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { |
254 | KVM_GENERIC_VCPU_STATS(), | |
255 | STATS_DESC_COUNTER(VCPU, pf_fixed), | |
256 | STATS_DESC_COUNTER(VCPU, pf_guest), | |
257 | STATS_DESC_COUNTER(VCPU, tlb_flush), | |
258 | STATS_DESC_COUNTER(VCPU, invlpg), | |
259 | STATS_DESC_COUNTER(VCPU, exits), | |
260 | STATS_DESC_COUNTER(VCPU, io_exits), | |
261 | STATS_DESC_COUNTER(VCPU, mmio_exits), | |
262 | STATS_DESC_COUNTER(VCPU, signal_exits), | |
263 | STATS_DESC_COUNTER(VCPU, irq_window_exits), | |
264 | STATS_DESC_COUNTER(VCPU, nmi_window_exits), | |
265 | STATS_DESC_COUNTER(VCPU, l1d_flush), | |
266 | STATS_DESC_COUNTER(VCPU, halt_exits), | |
267 | STATS_DESC_COUNTER(VCPU, request_irq_exits), | |
268 | STATS_DESC_COUNTER(VCPU, irq_exits), | |
269 | STATS_DESC_COUNTER(VCPU, host_state_reload), | |
270 | STATS_DESC_COUNTER(VCPU, fpu_reload), | |
271 | STATS_DESC_COUNTER(VCPU, insn_emulation), | |
272 | STATS_DESC_COUNTER(VCPU, insn_emulation_fail), | |
273 | STATS_DESC_COUNTER(VCPU, hypercalls), | |
274 | STATS_DESC_COUNTER(VCPU, irq_injections), | |
275 | STATS_DESC_COUNTER(VCPU, nmi_injections), | |
276 | STATS_DESC_COUNTER(VCPU, req_event), | |
277 | STATS_DESC_COUNTER(VCPU, nested_run), | |
278 | STATS_DESC_COUNTER(VCPU, directed_yield_attempted), | |
279 | STATS_DESC_COUNTER(VCPU, directed_yield_successful), | |
280 | STATS_DESC_ICOUNTER(VCPU, guest_mode) | |
281 | }; | |
ce55c049 JZ |
282 | |
283 | const struct kvm_stats_header kvm_vcpu_stats_header = { | |
284 | .name_size = KVM_STATS_NAME_SIZE, | |
285 | .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), | |
286 | .id_offset = sizeof(struct kvm_stats_header), | |
287 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
288 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
289 | sizeof(kvm_vcpu_stats_desc), | |
290 | }; | |
291 | ||
2acf923e | 292 | u64 __read_mostly host_xcr0; |
cfc48181 SC |
293 | u64 __read_mostly supported_xcr0; |
294 | EXPORT_SYMBOL_GPL(supported_xcr0); | |
2acf923e | 295 | |
80fbd280 | 296 | static struct kmem_cache *x86_fpu_cache; |
b666a4b6 | 297 | |
c9b8b07c SC |
298 | static struct kmem_cache *x86_emulator_cache; |
299 | ||
6abe9c13 PX |
300 | /* |
301 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 302 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 303 | */ |
d632826f | 304 | static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) |
6abe9c13 PX |
305 | { |
306 | const char *op = write ? "wrmsr" : "rdmsr"; | |
307 | ||
308 | if (ignore_msrs) { | |
309 | if (report_ignored_msrs) | |
d383b314 TI |
310 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
311 | op, msr, data); | |
6abe9c13 | 312 | /* Mask the error */ |
cc4cb017 | 313 | return true; |
6abe9c13 | 314 | } else { |
d383b314 TI |
315 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
316 | op, msr, data); | |
cc4cb017 | 317 | return false; |
6abe9c13 PX |
318 | } |
319 | } | |
320 | ||
c9b8b07c SC |
321 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
322 | { | |
06add254 SC |
323 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
324 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
325 | ||
326 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 327 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
328 | SLAB_ACCOUNT, useroffset, |
329 | size - useroffset, NULL); | |
c9b8b07c SC |
330 | } |
331 | ||
b6785def | 332 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 333 | |
af585b92 GN |
334 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
335 | { | |
336 | int i; | |
dd03bcaa | 337 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
338 | vcpu->arch.apf.gfns[i] = ~0; |
339 | } | |
340 | ||
18863bdd AK |
341 | static void kvm_on_user_return(struct user_return_notifier *urn) |
342 | { | |
343 | unsigned slot; | |
7e34fbd0 SC |
344 | struct kvm_user_return_msrs *msrs |
345 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
346 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
347 | unsigned long flags; |
348 | ||
349 | /* | |
350 | * Disabling irqs at this point since the following code could be | |
351 | * interrupted and executed through kvm_arch_hardware_disable() | |
352 | */ | |
353 | local_irq_save(flags); | |
7e34fbd0 SC |
354 | if (msrs->registered) { |
355 | msrs->registered = false; | |
1650b4eb IA |
356 | user_return_notifier_unregister(urn); |
357 | } | |
358 | local_irq_restore(flags); | |
9cc39a5a | 359 | for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { |
7e34fbd0 | 360 | values = &msrs->values[slot]; |
2bf78fa7 | 361 | if (values->host != values->curr) { |
9cc39a5a | 362 | wrmsrl(kvm_uret_msrs_list[slot], values->host); |
2bf78fa7 | 363 | values->curr = values->host; |
18863bdd AK |
364 | } |
365 | } | |
18863bdd AK |
366 | } |
367 | ||
e5fda4bb | 368 | static int kvm_probe_user_return_msr(u32 msr) |
5104d7ff SC |
369 | { |
370 | u64 val; | |
371 | int ret; | |
372 | ||
373 | preempt_disable(); | |
374 | ret = rdmsrl_safe(msr, &val); | |
375 | if (ret) | |
376 | goto out; | |
377 | ret = wrmsrl_safe(msr, val); | |
378 | out: | |
379 | preempt_enable(); | |
380 | return ret; | |
381 | } | |
5104d7ff | 382 | |
e5fda4bb | 383 | int kvm_add_user_return_msr(u32 msr) |
2bf78fa7 | 384 | { |
e5fda4bb SC |
385 | BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); |
386 | ||
387 | if (kvm_probe_user_return_msr(msr)) | |
388 | return -1; | |
389 | ||
390 | kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; | |
391 | return kvm_nr_uret_msrs++; | |
18863bdd | 392 | } |
e5fda4bb | 393 | EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); |
18863bdd | 394 | |
8ea8b8d6 SC |
395 | int kvm_find_user_return_msr(u32 msr) |
396 | { | |
397 | int i; | |
398 | ||
9cc39a5a SC |
399 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
400 | if (kvm_uret_msrs_list[i] == msr) | |
8ea8b8d6 SC |
401 | return i; |
402 | } | |
403 | return -1; | |
404 | } | |
405 | EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); | |
406 | ||
7e34fbd0 | 407 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 408 | { |
05c19c2f | 409 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 410 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
411 | u64 value; |
412 | int i; | |
18863bdd | 413 | |
9cc39a5a SC |
414 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
415 | rdmsrl_safe(kvm_uret_msrs_list[i], &value); | |
7e34fbd0 SC |
416 | msrs->values[i].host = value; |
417 | msrs->values[i].curr = value; | |
05c19c2f | 418 | } |
18863bdd AK |
419 | } |
420 | ||
7e34fbd0 | 421 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 422 | { |
013f6a5d | 423 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 424 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 425 | int err; |
18863bdd | 426 | |
7e34fbd0 SC |
427 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
428 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 429 | return 0; |
9cc39a5a | 430 | err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); |
8b3c3104 AH |
431 | if (err) |
432 | return 1; | |
433 | ||
7e34fbd0 SC |
434 | msrs->values[slot].curr = value; |
435 | if (!msrs->registered) { | |
436 | msrs->urn.on_user_return = kvm_on_user_return; | |
437 | user_return_notifier_register(&msrs->urn); | |
438 | msrs->registered = true; | |
18863bdd | 439 | } |
8b3c3104 | 440 | return 0; |
18863bdd | 441 | } |
7e34fbd0 | 442 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 443 | |
13a34e06 | 444 | static void drop_user_return_notifiers(void) |
3548bab5 | 445 | { |
013f6a5d | 446 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 447 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 448 | |
7e34fbd0 SC |
449 | if (msrs->registered) |
450 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
451 | } |
452 | ||
6866b83e CO |
453 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
454 | { | |
8a5a87d9 | 455 | return vcpu->arch.apic_base; |
6866b83e CO |
456 | } |
457 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
458 | ||
58871649 JM |
459 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
460 | { | |
461 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
462 | } | |
463 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
464 | ||
58cb628d JK |
465 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
466 | { | |
58871649 JM |
467 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
468 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
a8ac864a | 469 | u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | |
d6321d49 | 470 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); |
58cb628d | 471 | |
58871649 | 472 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 473 | return 1; |
58871649 JM |
474 | if (!msr_info->host_initiated) { |
475 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
476 | return 1; | |
477 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
478 | return 1; | |
479 | } | |
58cb628d JK |
480 | |
481 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 482 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 483 | return 0; |
6866b83e CO |
484 | } |
485 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
486 | ||
ad0577c3 SC |
487 | /* |
488 | * Handle a fault on a hardware virtualization (VMX or SVM) instruction. | |
489 | * | |
490 | * Hardware virtualization extension instructions may fault if a reboot turns | |
491 | * off virtualization while processes are running. Usually after catching the | |
492 | * fault we just panic; during reboot instead the instruction is ignored. | |
493 | */ | |
494 | noinstr void kvm_spurious_fault(void) | |
e3ba45b8 GL |
495 | { |
496 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 497 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
498 | } |
499 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
500 | ||
3fd28fce ED |
501 | #define EXCPT_BENIGN 0 |
502 | #define EXCPT_CONTRIBUTORY 1 | |
503 | #define EXCPT_PF 2 | |
504 | ||
505 | static int exception_class(int vector) | |
506 | { | |
507 | switch (vector) { | |
508 | case PF_VECTOR: | |
509 | return EXCPT_PF; | |
510 | case DE_VECTOR: | |
511 | case TS_VECTOR: | |
512 | case NP_VECTOR: | |
513 | case SS_VECTOR: | |
514 | case GP_VECTOR: | |
515 | return EXCPT_CONTRIBUTORY; | |
516 | default: | |
517 | break; | |
518 | } | |
519 | return EXCPT_BENIGN; | |
520 | } | |
521 | ||
d6e8c854 NA |
522 | #define EXCPT_FAULT 0 |
523 | #define EXCPT_TRAP 1 | |
524 | #define EXCPT_ABORT 2 | |
525 | #define EXCPT_INTERRUPT 3 | |
526 | ||
527 | static int exception_type(int vector) | |
528 | { | |
529 | unsigned int mask; | |
530 | ||
531 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
532 | return EXCPT_INTERRUPT; | |
533 | ||
534 | mask = 1 << vector; | |
535 | ||
536 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
537 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
538 | return EXCPT_TRAP; | |
539 | ||
540 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
541 | return EXCPT_ABORT; | |
542 | ||
543 | /* Reserved exceptions will result in fault */ | |
544 | return EXCPT_FAULT; | |
545 | } | |
546 | ||
da998b46 JM |
547 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
548 | { | |
549 | unsigned nr = vcpu->arch.exception.nr; | |
550 | bool has_payload = vcpu->arch.exception.has_payload; | |
551 | unsigned long payload = vcpu->arch.exception.payload; | |
552 | ||
553 | if (!has_payload) | |
554 | return; | |
555 | ||
556 | switch (nr) { | |
f10c729f JM |
557 | case DB_VECTOR: |
558 | /* | |
559 | * "Certain debug exceptions may clear bit 0-3. The | |
560 | * remaining contents of the DR6 register are never | |
561 | * cleared by the processor". | |
562 | */ | |
563 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
564 | /* | |
9a3ecd5e CQ |
565 | * In order to reflect the #DB exception payload in guest |
566 | * dr6, three components need to be considered: active low | |
567 | * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, | |
568 | * DR6_BS and DR6_BT) | |
569 | * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. | |
570 | * In the target guest dr6: | |
571 | * FIXED_1 bits should always be set. | |
572 | * Active low bits should be cleared if 1-setting in payload. | |
573 | * Active high bits should be set if 1-setting in payload. | |
574 | * | |
575 | * Note, the payload is compatible with the pending debug | |
576 | * exceptions/exit qualification under VMX, that active_low bits | |
577 | * are active high in payload. | |
578 | * So they need to be flipped for DR6. | |
f10c729f | 579 | */ |
9a3ecd5e | 580 | vcpu->arch.dr6 |= DR6_ACTIVE_LOW; |
f10c729f | 581 | vcpu->arch.dr6 |= payload; |
9a3ecd5e | 582 | vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; |
307f1cfa OU |
583 | |
584 | /* | |
585 | * The #DB payload is defined as compatible with the 'pending | |
586 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
587 | * defined in the 'pending debug exceptions' field (enabled | |
588 | * breakpoint), it is reserved and must be zero in DR6. | |
589 | */ | |
590 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 591 | break; |
da998b46 JM |
592 | case PF_VECTOR: |
593 | vcpu->arch.cr2 = payload; | |
594 | break; | |
595 | } | |
596 | ||
597 | vcpu->arch.exception.has_payload = false; | |
598 | vcpu->arch.exception.payload = 0; | |
599 | } | |
600 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
601 | ||
3fd28fce | 602 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 603 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 604 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
605 | { |
606 | u32 prev_nr; | |
607 | int class1, class2; | |
608 | ||
3842d135 AK |
609 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
610 | ||
664f8e26 | 611 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 612 | queue: |
664f8e26 WL |
613 | if (reinject) { |
614 | /* | |
615 | * On vmentry, vcpu->arch.exception.pending is only | |
616 | * true if an event injection was blocked by | |
617 | * nested_run_pending. In that case, however, | |
618 | * vcpu_enter_guest requests an immediate exit, | |
619 | * and the guest shouldn't proceed far enough to | |
620 | * need reinjection. | |
621 | */ | |
622 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
623 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
624 | if (WARN_ON_ONCE(has_payload)) { |
625 | /* | |
626 | * A reinjected event has already | |
627 | * delivered its payload. | |
628 | */ | |
629 | has_payload = false; | |
630 | payload = 0; | |
631 | } | |
664f8e26 WL |
632 | } else { |
633 | vcpu->arch.exception.pending = true; | |
634 | vcpu->arch.exception.injected = false; | |
635 | } | |
3fd28fce ED |
636 | vcpu->arch.exception.has_error_code = has_error; |
637 | vcpu->arch.exception.nr = nr; | |
638 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
639 | vcpu->arch.exception.has_payload = has_payload; |
640 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 641 | if (!is_guest_mode(vcpu)) |
da998b46 | 642 | kvm_deliver_exception_payload(vcpu); |
3fd28fce ED |
643 | return; |
644 | } | |
645 | ||
646 | /* to check exception */ | |
647 | prev_nr = vcpu->arch.exception.nr; | |
648 | if (prev_nr == DF_VECTOR) { | |
649 | /* triple fault -> shutdown */ | |
a8eeb04a | 650 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
651 | return; |
652 | } | |
653 | class1 = exception_class(prev_nr); | |
654 | class2 = exception_class(nr); | |
655 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
656 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
657 | /* |
658 | * Generate double fault per SDM Table 5-5. Set | |
659 | * exception.pending = true so that the double fault | |
660 | * can trigger a nested vmexit. | |
661 | */ | |
3fd28fce | 662 | vcpu->arch.exception.pending = true; |
664f8e26 | 663 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
664 | vcpu->arch.exception.has_error_code = true; |
665 | vcpu->arch.exception.nr = DF_VECTOR; | |
666 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
667 | vcpu->arch.exception.has_payload = false; |
668 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
669 | } else |
670 | /* replace previous exception with a new one in a hope | |
671 | that instruction re-execution will regenerate lost | |
672 | exception */ | |
673 | goto queue; | |
674 | } | |
675 | ||
298101da AK |
676 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
677 | { | |
91e86d22 | 678 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
679 | } |
680 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
681 | ||
ce7ddec4 JR |
682 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
683 | { | |
91e86d22 | 684 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
685 | } |
686 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
687 | ||
4d5523cf PB |
688 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
689 | unsigned long payload) | |
f10c729f JM |
690 | { |
691 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
692 | } | |
4d5523cf | 693 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 694 | |
da998b46 JM |
695 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
696 | u32 error_code, unsigned long payload) | |
697 | { | |
698 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
699 | true, payload, false); | |
700 | } | |
701 | ||
6affcbed | 702 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 703 | { |
db8fcefa AP |
704 | if (err) |
705 | kvm_inject_gp(vcpu, 0); | |
706 | else | |
6affcbed KH |
707 | return kvm_skip_emulated_instruction(vcpu); |
708 | ||
709 | return 1; | |
db8fcefa AP |
710 | } |
711 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 712 | |
6389ee94 | 713 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
714 | { |
715 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
716 | vcpu->arch.exception.nested_apf = |
717 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 718 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 719 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
720 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
721 | } else { | |
722 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
723 | fault->address); | |
724 | } | |
c3c91fee | 725 | } |
27d6c865 | 726 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 727 | |
53b3d8e9 SC |
728 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
729 | struct x86_exception *fault) | |
d4f8cf66 | 730 | { |
0cd665bd | 731 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
732 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
733 | ||
0cd665bd PB |
734 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
735 | vcpu->arch.walk_mmu; | |
ef54bcfe | 736 | |
ee1fa209 JS |
737 | /* |
738 | * Invalidate the TLB entry for the faulting address, if it exists, | |
739 | * else the access will fault indefinitely (and to emulate hardware). | |
740 | */ | |
741 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
742 | !(fault->error_code & PFERR_RSVD_MASK)) | |
743 | kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, | |
744 | fault_mmu->root_hpa); | |
745 | ||
746 | fault_mmu->inject_page_fault(vcpu, fault); | |
ef54bcfe | 747 | return fault->nested_page_fault; |
d4f8cf66 | 748 | } |
53b3d8e9 | 749 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 750 | |
3419ffc8 SY |
751 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
752 | { | |
7460fb4a AK |
753 | atomic_inc(&vcpu->arch.nmi_queued); |
754 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
755 | } |
756 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
757 | ||
298101da AK |
758 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
759 | { | |
91e86d22 | 760 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
761 | } |
762 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
763 | ||
ce7ddec4 JR |
764 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
765 | { | |
91e86d22 | 766 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
767 | } |
768 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
769 | ||
0a79b009 AK |
770 | /* |
771 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
772 | * a #GP and return false. | |
773 | */ | |
774 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 775 | { |
b3646477 | 776 | if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) |
0a79b009 AK |
777 | return true; |
778 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
779 | return false; | |
298101da | 780 | } |
0a79b009 | 781 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 782 | |
16f8a6f9 NA |
783 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
784 | { | |
785 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
786 | return true; | |
787 | ||
788 | kvm_queue_exception(vcpu, UD_VECTOR); | |
789 | return false; | |
790 | } | |
791 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
792 | ||
16cfacc8 SC |
793 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
794 | { | |
5b7f575c | 795 | return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); |
16cfacc8 SC |
796 | } |
797 | ||
a03490ed | 798 | /* |
16cfacc8 | 799 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 800 | */ |
ff03a073 | 801 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
802 | { |
803 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
15cabbc2 | 804 | gpa_t real_gpa; |
a03490ed CO |
805 | int i; |
806 | int ret; | |
ff03a073 | 807 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 808 | |
15cabbc2 SC |
809 | /* |
810 | * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated | |
811 | * to an L1 GPA. | |
812 | */ | |
813 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(pdpt_gfn), | |
814 | PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); | |
815 | if (real_gpa == UNMAPPED_GVA) | |
816 | return 0; | |
817 | ||
94c641ba | 818 | /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ |
15cabbc2 | 819 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, |
94c641ba | 820 | cr3 & GENMASK(11, 5), sizeof(pdpte)); |
15cabbc2 SC |
821 | if (ret < 0) |
822 | return 0; | |
823 | ||
a03490ed | 824 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { |
812f30b2 | 825 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 826 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
15cabbc2 | 827 | return 0; |
a03490ed CO |
828 | } |
829 | } | |
a03490ed | 830 | |
ff03a073 | 831 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
cb3c1e2f | 832 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
158a48ec ML |
833 | vcpu->arch.pdptrs_from_userspace = false; |
834 | ||
15cabbc2 | 835 | return 1; |
a03490ed | 836 | } |
cc4b6871 | 837 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 838 | |
f27ad38a TL |
839 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) |
840 | { | |
f27ad38a TL |
841 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
842 | kvm_clear_async_pf_completion_queue(vcpu); | |
843 | kvm_async_pf_hash_reset(vcpu); | |
844 | } | |
845 | ||
20f632bd | 846 | if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) |
f27ad38a TL |
847 | kvm_mmu_reset_context(vcpu); |
848 | ||
849 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && | |
850 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
851 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
852 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
853 | } | |
854 | EXPORT_SYMBOL_GPL(kvm_post_set_cr0); | |
855 | ||
49a9b07e | 856 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 857 | { |
aad82703 | 858 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d42e3fae | 859 | unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; |
aad82703 | 860 | |
f9a48e6a AK |
861 | cr0 |= X86_CR0_ET; |
862 | ||
ab344828 | 863 | #ifdef CONFIG_X86_64 |
0f12244f GN |
864 | if (cr0 & 0xffffffff00000000UL) |
865 | return 1; | |
ab344828 GN |
866 | #endif |
867 | ||
868 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 869 | |
0f12244f GN |
870 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
871 | return 1; | |
a03490ed | 872 | |
0f12244f GN |
873 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
874 | return 1; | |
a03490ed | 875 | |
a03490ed | 876 | #ifdef CONFIG_X86_64 |
05487215 SC |
877 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
878 | (cr0 & X86_CR0_PG)) { | |
879 | int cs_db, cs_l; | |
880 | ||
881 | if (!is_pae(vcpu)) | |
882 | return 1; | |
b3646477 | 883 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
05487215 | 884 | if (cs_l) |
0f12244f | 885 | return 1; |
a03490ed | 886 | } |
05487215 SC |
887 | #endif |
888 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
889 | is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && | |
890 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) | |
891 | return 1; | |
a03490ed | 892 | |
ad756a16 MJ |
893 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
894 | return 1; | |
895 | ||
b3646477 | 896 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
a03490ed | 897 | |
f27ad38a | 898 | kvm_post_set_cr0(vcpu, old_cr0, cr0); |
b18d5431 | 899 | |
0f12244f GN |
900 | return 0; |
901 | } | |
2d3ad1f4 | 902 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 903 | |
2d3ad1f4 | 904 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 905 | { |
49a9b07e | 906 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 907 | } |
2d3ad1f4 | 908 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 909 | |
139a12cf | 910 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 911 | { |
16809ecd TL |
912 | if (vcpu->arch.guest_state_protected) |
913 | return; | |
914 | ||
139a12cf AL |
915 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
916 | ||
917 | if (vcpu->arch.xcr0 != host_xcr0) | |
918 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
919 | ||
920 | if (vcpu->arch.xsaves_enabled && | |
921 | vcpu->arch.ia32_xss != host_xss) | |
922 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
923 | } | |
37486135 BM |
924 | |
925 | if (static_cpu_has(X86_FEATURE_PKU) && | |
926 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
927 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && | |
928 | vcpu->arch.pkru != vcpu->arch.host_pkru) | |
72a6c08c | 929 | write_pkru(vcpu->arch.pkru); |
42bdf991 | 930 | } |
139a12cf | 931 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 932 | |
139a12cf | 933 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 934 | { |
16809ecd TL |
935 | if (vcpu->arch.guest_state_protected) |
936 | return; | |
937 | ||
37486135 BM |
938 | if (static_cpu_has(X86_FEATURE_PKU) && |
939 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
940 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { | |
941 | vcpu->arch.pkru = rdpkru(); | |
942 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
72a6c08c | 943 | write_pkru(vcpu->arch.host_pkru); |
37486135 BM |
944 | } |
945 | ||
139a12cf AL |
946 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
947 | ||
948 | if (vcpu->arch.xcr0 != host_xcr0) | |
949 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
950 | ||
951 | if (vcpu->arch.xsaves_enabled && | |
952 | vcpu->arch.ia32_xss != host_xss) | |
953 | wrmsrl(MSR_IA32_XSS, host_xss); | |
954 | } | |
955 | ||
42bdf991 | 956 | } |
139a12cf | 957 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 958 | |
69b0049a | 959 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 960 | { |
56c103ec LJ |
961 | u64 xcr0 = xcr; |
962 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 963 | u64 valid_bits; |
2acf923e DC |
964 | |
965 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
966 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
967 | return 1; | |
d91cab78 | 968 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 969 | return 1; |
d91cab78 | 970 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 971 | return 1; |
46c34cb0 PB |
972 | |
973 | /* | |
974 | * Do not allow the guest to set bits that we do not support | |
975 | * saving. However, xcr0 bit 0 is always set, even if the | |
e8f65b9b | 976 | * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). |
46c34cb0 | 977 | */ |
d91cab78 | 978 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 979 | if (xcr0 & ~valid_bits) |
2acf923e | 980 | return 1; |
46c34cb0 | 981 | |
d91cab78 DH |
982 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
983 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
984 | return 1; |
985 | ||
d91cab78 DH |
986 | if (xcr0 & XFEATURE_MASK_AVX512) { |
987 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 988 | return 1; |
d91cab78 | 989 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
990 | return 1; |
991 | } | |
2acf923e | 992 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 993 | |
d91cab78 | 994 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 995 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
996 | return 0; |
997 | } | |
998 | ||
92f9895c | 999 | int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) |
2acf923e | 1000 | { |
92f9895c SC |
1001 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || |
1002 | __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { | |
1003 | kvm_inject_gp(vcpu, 0); | |
1004 | return 1; | |
1005 | } | |
bbefd4fc | 1006 | |
92f9895c | 1007 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e | 1008 | } |
92f9895c | 1009 | EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); |
2acf923e | 1010 | |
ee69c92b | 1011 | bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 1012 | { |
b11306b5 | 1013 | if (cr4 & cr4_reserved_bits) |
ee69c92b | 1014 | return false; |
b9baba86 | 1015 | |
b899c132 | 1016 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
ee69c92b | 1017 | return false; |
3ca94192 | 1018 | |
b3646477 | 1019 | return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); |
3ca94192 | 1020 | } |
ee69c92b | 1021 | EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); |
3ca94192 | 1022 | |
5b51cb13 TL |
1023 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) |
1024 | { | |
509bfe3d LJ |
1025 | /* |
1026 | * If any role bit is changed, the MMU needs to be reset. | |
1027 | * | |
1028 | * If CR4.PCIDE is changed 1 -> 0, the guest TLB must be flushed. | |
1029 | * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB | |
1030 | * according to the SDM; however, stale prev_roots could be reused | |
1031 | * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we | |
1032 | * free them all. KVM_REQ_MMU_RELOAD is fit for the both cases; it | |
1033 | * is slow, but changing CR4.PCIDE is a rare case. | |
1034 | * | |
1035 | * If CR4.PGE is changed, the guest TLB must be flushed. | |
1036 | * | |
1037 | * Note: resetting MMU is a superset of KVM_REQ_MMU_RELOAD and | |
1038 | * KVM_REQ_MMU_RELOAD is a superset of KVM_REQ_TLB_FLUSH_GUEST, hence | |
1039 | * the usage of "else if". | |
1040 | */ | |
55261738 | 1041 | if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) |
5b51cb13 | 1042 | kvm_mmu_reset_context(vcpu); |
509bfe3d LJ |
1043 | else if ((cr4 ^ old_cr4) & X86_CR4_PCIDE) |
1044 | kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu); | |
1045 | else if ((cr4 ^ old_cr4) & X86_CR4_PGE) | |
55261738 | 1046 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
3ca94192 | 1047 | } |
5b51cb13 | 1048 | EXPORT_SYMBOL_GPL(kvm_post_set_cr4); |
3ca94192 WL |
1049 | |
1050 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1051 | { | |
1052 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
1053 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
cb957adb | 1054 | X86_CR4_SMEP; |
3ca94192 | 1055 | |
ee69c92b | 1056 | if (!kvm_is_valid_cr4(vcpu, cr4)) |
ae3e61e1 PB |
1057 | return 1; |
1058 | ||
a03490ed | 1059 | if (is_long_mode(vcpu)) { |
0f12244f GN |
1060 | if (!(cr4 & X86_CR4_PAE)) |
1061 | return 1; | |
d74fcfc1 SC |
1062 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
1063 | return 1; | |
a2edf57f AK |
1064 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
1065 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
1066 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
1067 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
1068 | return 1; |
1069 | ||
ad756a16 | 1070 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 1071 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
1072 | return 1; |
1073 | ||
1074 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
1075 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1076 | return 1; | |
1077 | } | |
1078 | ||
b3646477 | 1079 | static_call(kvm_x86_set_cr4)(vcpu, cr4); |
a03490ed | 1080 | |
5b51cb13 | 1081 | kvm_post_set_cr4(vcpu, old_cr4, cr4); |
2acf923e | 1082 | |
0f12244f GN |
1083 | return 0; |
1084 | } | |
2d3ad1f4 | 1085 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1086 | |
21823fbd SC |
1087 | static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) |
1088 | { | |
1089 | struct kvm_mmu *mmu = vcpu->arch.mmu; | |
1090 | unsigned long roots_to_free = 0; | |
1091 | int i; | |
1092 | ||
e45e9e39 LJ |
1093 | /* |
1094 | * MOV CR3 and INVPCID are usually not intercepted when using TDP, but | |
1095 | * this is reachable when running EPT=1 and unrestricted_guest=0, and | |
1096 | * also via the emulator. KVM's TDP page tables are not in the scope of | |
1097 | * the invalidation, but the guest's TLB entries need to be flushed as | |
1098 | * the CPU may have cached entries in its TLB for the target PCID. | |
1099 | */ | |
1100 | if (unlikely(tdp_enabled)) { | |
1101 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
1102 | return; | |
1103 | } | |
1104 | ||
21823fbd SC |
1105 | /* |
1106 | * If neither the current CR3 nor any of the prev_roots use the given | |
1107 | * PCID, then nothing needs to be done here because a resync will | |
1108 | * happen anyway before switching to any other CR3. | |
1109 | */ | |
1110 | if (kvm_get_active_pcid(vcpu) == pcid) { | |
e62f1aa8 | 1111 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
21823fbd SC |
1112 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1113 | } | |
1114 | ||
509bfe3d LJ |
1115 | /* |
1116 | * If PCID is disabled, there is no need to free prev_roots even if the | |
1117 | * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB | |
1118 | * with PCIDE=0. | |
1119 | */ | |
1120 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) | |
1121 | return; | |
1122 | ||
21823fbd SC |
1123 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
1124 | if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) | |
1125 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
1126 | ||
1127 | kvm_mmu_free_roots(vcpu, mmu, roots_to_free); | |
1128 | } | |
1129 | ||
2390218b | 1130 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1131 | { |
ade61e28 | 1132 | bool skip_tlb_flush = false; |
21823fbd | 1133 | unsigned long pcid = 0; |
ac146235 | 1134 | #ifdef CONFIG_X86_64 |
c19986fe JS |
1135 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
1136 | ||
ade61e28 | 1137 | if (pcid_enabled) { |
208320ba JS |
1138 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1139 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
21823fbd | 1140 | pcid = cr3 & X86_CR3_PCID_MASK; |
ade61e28 | 1141 | } |
ac146235 | 1142 | #endif |
9d88fca7 | 1143 | |
c7313155 | 1144 | /* PDPTRs are always reloaded for PAE paging. */ |
21823fbd SC |
1145 | if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) |
1146 | goto handle_tlb_flush; | |
d835dfec | 1147 | |
886bbcc7 SC |
1148 | /* |
1149 | * Do not condition the GPA check on long mode, this helper is used to | |
1150 | * stuff CR3, e.g. for RSM emulation, and there is no guarantee that | |
1151 | * the current vCPU mode is accurate. | |
1152 | */ | |
1153 | if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) | |
d1cd3ce9 | 1154 | return 1; |
886bbcc7 SC |
1155 | |
1156 | if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 1157 | return 1; |
a03490ed | 1158 | |
21823fbd | 1159 | if (cr3 != kvm_read_cr3(vcpu)) |
b5129100 | 1160 | kvm_mmu_new_pgd(vcpu, cr3); |
21823fbd | 1161 | |
0f12244f | 1162 | vcpu->arch.cr3 = cr3; |
cb3c1e2f | 1163 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
7c390d35 | 1164 | |
21823fbd SC |
1165 | handle_tlb_flush: |
1166 | /* | |
1167 | * A load of CR3 that flushes the TLB flushes only the current PCID, | |
1168 | * even if PCID is disabled, in which case PCID=0 is flushed. It's a | |
1169 | * moot point in the end because _disabling_ PCID will flush all PCIDs, | |
1170 | * and it's impossible to use a non-zero PCID when PCID is disabled, | |
1171 | * i.e. only PCID=0 can be relevant. | |
1172 | */ | |
1173 | if (!skip_tlb_flush) | |
1174 | kvm_invalidate_pcid(vcpu, pcid); | |
1175 | ||
0f12244f GN |
1176 | return 0; |
1177 | } | |
2d3ad1f4 | 1178 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1179 | |
eea1cff9 | 1180 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1181 | { |
0f12244f GN |
1182 | if (cr8 & CR8_RESERVED_BITS) |
1183 | return 1; | |
35754c98 | 1184 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1185 | kvm_lapic_set_tpr(vcpu, cr8); |
1186 | else | |
ad312c7c | 1187 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1188 | return 0; |
1189 | } | |
2d3ad1f4 | 1190 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1191 | |
2d3ad1f4 | 1192 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1193 | { |
35754c98 | 1194 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1195 | return kvm_lapic_get_cr8(vcpu); |
1196 | else | |
ad312c7c | 1197 | return vcpu->arch.cr8; |
a03490ed | 1198 | } |
2d3ad1f4 | 1199 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1200 | |
ae561ede NA |
1201 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1202 | { | |
1203 | int i; | |
1204 | ||
1205 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1206 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1207 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae561ede NA |
1208 | } |
1209 | } | |
1210 | ||
7c86663b | 1211 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1212 | { |
1213 | unsigned long dr7; | |
1214 | ||
1215 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1216 | dr7 = vcpu->arch.guest_debug_dr7; | |
1217 | else | |
1218 | dr7 = vcpu->arch.dr7; | |
b3646477 | 1219 | static_call(kvm_x86_set_dr7)(vcpu, dr7); |
360b948d PB |
1220 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1221 | if (dr7 & DR7_BP_EN_MASK) | |
1222 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1223 | } |
7c86663b | 1224 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1225 | |
6f43ed01 NA |
1226 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1227 | { | |
1228 | u64 fixed = DR6_FIXED_1; | |
1229 | ||
d6321d49 | 1230 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 | 1231 | fixed |= DR6_RTM; |
e8ea85fb CQ |
1232 | |
1233 | if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) | |
1234 | fixed |= DR6_BUS_LOCK; | |
6f43ed01 NA |
1235 | return fixed; |
1236 | } | |
1237 | ||
996ff542 | 1238 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1239 | { |
ea740059 MP |
1240 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1241 | ||
020df079 GN |
1242 | switch (dr) { |
1243 | case 0 ... 3: | |
ea740059 | 1244 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1245 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1246 | vcpu->arch.eff_db[dr] = val; | |
1247 | break; | |
1248 | case 4: | |
020df079 | 1249 | case 6: |
f5f6145e | 1250 | if (!kvm_dr6_valid(val)) |
996ff542 | 1251 | return 1; /* #GP */ |
6f43ed01 | 1252 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1253 | break; |
1254 | case 5: | |
020df079 | 1255 | default: /* 7 */ |
b91991bf | 1256 | if (!kvm_dr7_valid(val)) |
996ff542 | 1257 | return 1; /* #GP */ |
020df079 | 1258 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1259 | kvm_update_dr7(vcpu); |
020df079 GN |
1260 | break; |
1261 | } | |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | EXPORT_SYMBOL_GPL(kvm_set_dr); | |
1266 | ||
29d6ca41 | 1267 | void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1268 | { |
ea740059 MP |
1269 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1270 | ||
020df079 GN |
1271 | switch (dr) { |
1272 | case 0 ... 3: | |
ea740059 | 1273 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1274 | break; |
1275 | case 4: | |
020df079 | 1276 | case 6: |
5679b803 | 1277 | *val = vcpu->arch.dr6; |
020df079 GN |
1278 | break; |
1279 | case 5: | |
020df079 GN |
1280 | default: /* 7 */ |
1281 | *val = vcpu->arch.dr7; | |
1282 | break; | |
1283 | } | |
338dbc97 | 1284 | } |
020df079 GN |
1285 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1286 | ||
c483c454 | 1287 | int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) |
022cd0e8 | 1288 | { |
de3cd117 | 1289 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 | 1290 | u64 data; |
022cd0e8 | 1291 | |
c483c454 SC |
1292 | if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { |
1293 | kvm_inject_gp(vcpu, 0); | |
1294 | return 1; | |
1295 | } | |
1296 | ||
de3cd117 SC |
1297 | kvm_rax_write(vcpu, (u32)data); |
1298 | kvm_rdx_write(vcpu, data >> 32); | |
c483c454 | 1299 | return kvm_skip_emulated_instruction(vcpu); |
022cd0e8 | 1300 | } |
c483c454 | 1301 | EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); |
022cd0e8 | 1302 | |
043405e1 CO |
1303 | /* |
1304 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1305 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1306 | * | |
7a5ee6ed CQ |
1307 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1308 | * extract the supported MSRs from the related const lists. | |
1309 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1310 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1311 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1312 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1313 | */ |
e3267cbb | 1314 | |
7a5ee6ed | 1315 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1316 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1317 | MSR_STAR, |
043405e1 CO |
1318 | #ifdef CONFIG_X86_64 |
1319 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1320 | #endif | |
b3897a49 | 1321 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1322 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1323 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1324 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1325 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1326 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1327 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1328 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1329 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1330 | MSR_IA32_UMWAIT_CONTROL, |
1331 | ||
e2ada66e JM |
1332 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
1333 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, | |
1334 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, | |
1335 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1336 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1337 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1338 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1339 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1340 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1341 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1342 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1343 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1344 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1345 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1346 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1347 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1348 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1349 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1350 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1351 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1352 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1353 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
e1fc1553 FM |
1354 | |
1355 | MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, | |
1356 | MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, | |
1357 | MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, | |
1358 | MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, | |
1359 | MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, | |
1360 | MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, | |
043405e1 CO |
1361 | }; |
1362 | ||
7a5ee6ed | 1363 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1364 | static unsigned num_msrs_to_save; |
1365 | ||
7a5ee6ed | 1366 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1367 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1368 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1369 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1370 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1371 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1372 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1373 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1374 | HV_X64_MSR_RESET, |
11c4b1ca | 1375 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1376 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1377 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1378 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1379 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1380 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1381 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
f97f5a56 JD |
1382 | HV_X64_MSR_SYNDBG_OPTIONS, |
1383 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1384 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1385 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1386 | |
1387 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1388 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1389 | |
ba904635 | 1390 | MSR_IA32_TSC_ADJUST, |
09141ec0 | 1391 | MSR_IA32_TSC_DEADLINE, |
2bdb76c0 | 1392 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1393 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1394 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1395 | MSR_IA32_MCG_STATUS, |
1396 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1397 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1398 | MSR_IA32_SMBASE, |
52797bf9 | 1399 | MSR_SMI_COUNT, |
db2336a8 KH |
1400 | MSR_PLATFORM_INFO, |
1401 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1402 | MSR_AMD64_VIRT_SPEC_CTRL, |
5228eb96 | 1403 | MSR_AMD64_TSC_RATIO, |
6c6a2ab9 | 1404 | MSR_IA32_POWER_CTL, |
99634e3e | 1405 | MSR_IA32_UCODE_REV, |
191c8137 | 1406 | |
95c5c7c7 PB |
1407 | /* |
1408 | * The following list leaves out MSRs whose values are determined | |
1409 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1410 | * We always support the "true" VMX control MSRs, even if the host | |
1411 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1412 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1413 | */ |
1414 | MSR_IA32_VMX_BASIC, | |
1415 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1416 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1417 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1418 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1419 | MSR_IA32_VMX_MISC, | |
1420 | MSR_IA32_VMX_CR0_FIXED0, | |
1421 | MSR_IA32_VMX_CR4_FIXED0, | |
1422 | MSR_IA32_VMX_VMCS_ENUM, | |
1423 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1424 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1425 | MSR_IA32_VMX_VMFUNC, | |
1426 | ||
191c8137 | 1427 | MSR_K7_HWCR, |
2d5ba19b | 1428 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1429 | }; |
1430 | ||
7a5ee6ed | 1431 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1432 | static unsigned num_emulated_msrs; |
1433 | ||
801e459a TL |
1434 | /* |
1435 | * List of msr numbers which are used to expose MSR-based features that | |
1436 | * can be used by a hypervisor to validate requested CPU features. | |
1437 | */ | |
7a5ee6ed | 1438 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1439 | MSR_IA32_VMX_BASIC, |
1440 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1441 | MSR_IA32_VMX_PINBASED_CTLS, | |
1442 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1443 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1444 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1445 | MSR_IA32_VMX_EXIT_CTLS, | |
1446 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1447 | MSR_IA32_VMX_ENTRY_CTLS, | |
1448 | MSR_IA32_VMX_MISC, | |
1449 | MSR_IA32_VMX_CR0_FIXED0, | |
1450 | MSR_IA32_VMX_CR0_FIXED1, | |
1451 | MSR_IA32_VMX_CR4_FIXED0, | |
1452 | MSR_IA32_VMX_CR4_FIXED1, | |
1453 | MSR_IA32_VMX_VMCS_ENUM, | |
1454 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1455 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1456 | MSR_IA32_VMX_VMFUNC, | |
1457 | ||
d1d93fa9 | 1458 | MSR_F10H_DECFG, |
518e7b94 | 1459 | MSR_IA32_UCODE_REV, |
cd283252 | 1460 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1461 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1462 | }; |
1463 | ||
7a5ee6ed | 1464 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1465 | static unsigned int num_msr_based_features; |
1466 | ||
4d22c17c | 1467 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1468 | { |
4d22c17c | 1469 | u64 data = 0; |
5b76a3cf | 1470 | |
4d22c17c XL |
1471 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1472 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1473 | |
b8e8c830 PB |
1474 | /* |
1475 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1476 | * the nested hypervisor runs with NX huge pages. If it is not, | |
d9f6e12f | 1477 | * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other |
b8e8c830 PB |
1478 | * L1 guests, so it need not worry about its own (L2) guests. |
1479 | */ | |
1480 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1481 | ||
5b76a3cf PB |
1482 | /* |
1483 | * If we're doing cache flushes (either "always" or "cond") | |
1484 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1485 | * If an outer hypervisor is doing the cache flush for us | |
1486 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1487 | * capability to the guest too, and if EPT is disabled we're not | |
1488 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1489 | * require a nested hypervisor to do a flush of its own. | |
1490 | */ | |
1491 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1492 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1493 | ||
0c54914d PB |
1494 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1495 | data |= ARCH_CAP_RDCL_NO; | |
1496 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1497 | data |= ARCH_CAP_SSB_NO; | |
1498 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1499 | data |= ARCH_CAP_MDS_NO; | |
1500 | ||
7131636e PB |
1501 | if (!boot_cpu_has(X86_FEATURE_RTM)) { |
1502 | /* | |
1503 | * If RTM=0 because the kernel has disabled TSX, the host might | |
1504 | * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 | |
1505 | * and therefore knows that there cannot be TAA) but keep | |
1506 | * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, | |
1507 | * and we want to allow migrating those guests to tsx=off hosts. | |
1508 | */ | |
1509 | data &= ~ARCH_CAP_TAA_NO; | |
1510 | } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
cbbaa272 | 1511 | data |= ARCH_CAP_TAA_NO; |
7131636e PB |
1512 | } else { |
1513 | /* | |
1514 | * Nothing to do here; we emulate TSX_CTRL if present on the | |
1515 | * host so the guest can choose between disabling TSX or | |
1516 | * using VERW to clear CPU buffers. | |
1517 | */ | |
1518 | } | |
e1d38b63 | 1519 | |
5b76a3cf PB |
1520 | return data; |
1521 | } | |
5b76a3cf | 1522 | |
66421c1e WL |
1523 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1524 | { | |
1525 | switch (msr->index) { | |
cd283252 | 1526 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1527 | msr->data = kvm_get_arch_capabilities(); |
1528 | break; | |
1529 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1530 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1531 | break; |
66421c1e | 1532 | default: |
b3646477 | 1533 | return static_call(kvm_x86_get_msr_feature)(msr); |
66421c1e WL |
1534 | } |
1535 | return 0; | |
1536 | } | |
1537 | ||
801e459a TL |
1538 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1539 | { | |
1540 | struct kvm_msr_entry msr; | |
66421c1e | 1541 | int r; |
801e459a TL |
1542 | |
1543 | msr.index = index; | |
66421c1e | 1544 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1545 | |
1546 | if (r == KVM_MSR_RET_INVALID) { | |
1547 | /* Unconditionally clear the output for simplicity */ | |
1548 | *data = 0; | |
d632826f | 1549 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1550 | r = 0; |
12bc2132 PX |
1551 | } |
1552 | ||
66421c1e WL |
1553 | if (r) |
1554 | return r; | |
801e459a TL |
1555 | |
1556 | *data = msr.data; | |
1557 | ||
1558 | return 0; | |
1559 | } | |
1560 | ||
11988499 | 1561 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1562 | { |
1b4d56b8 | 1563 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1564 | return false; |
1b2fd70c | 1565 | |
1b4d56b8 | 1566 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1567 | return false; |
d8017474 | 1568 | |
0a629563 SC |
1569 | if (efer & (EFER_LME | EFER_LMA) && |
1570 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1571 | return false; | |
1572 | ||
1573 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1574 | return false; | |
d8017474 | 1575 | |
384bb783 | 1576 | return true; |
11988499 SC |
1577 | |
1578 | } | |
1579 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1580 | { | |
1581 | if (efer & efer_reserved_bits) | |
1582 | return false; | |
1583 | ||
1584 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1585 | } |
1586 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1587 | ||
11988499 | 1588 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1589 | { |
1590 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1591 | u64 efer = msr_info->data; |
72f211ec | 1592 | int r; |
384bb783 | 1593 | |
11988499 | 1594 | if (efer & efer_reserved_bits) |
66f61c92 | 1595 | return 1; |
384bb783 | 1596 | |
11988499 SC |
1597 | if (!msr_info->host_initiated) { |
1598 | if (!__kvm_valid_efer(vcpu, efer)) | |
1599 | return 1; | |
1600 | ||
1601 | if (is_paging(vcpu) && | |
1602 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1603 | return 1; | |
1604 | } | |
384bb783 | 1605 | |
15c4a640 | 1606 | efer &= ~EFER_LMA; |
f6801dff | 1607 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1608 | |
b3646477 | 1609 | r = static_call(kvm_x86_set_efer)(vcpu, efer); |
72f211ec ML |
1610 | if (r) { |
1611 | WARN_ON(r > 0); | |
1612 | return r; | |
1613 | } | |
a3d204e2 | 1614 | |
aad82703 SY |
1615 | /* Update reserved bits */ |
1616 | if ((efer ^ old_efer) & EFER_NX) | |
1617 | kvm_mmu_reset_context(vcpu); | |
1618 | ||
b69e8cae | 1619 | return 0; |
15c4a640 CO |
1620 | } |
1621 | ||
f2b4b7dd JR |
1622 | void kvm_enable_efer_bits(u64 mask) |
1623 | { | |
1624 | efer_reserved_bits &= ~mask; | |
1625 | } | |
1626 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1627 | ||
51de8151 AG |
1628 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1629 | { | |
b318e8de SC |
1630 | struct kvm_x86_msr_filter *msr_filter; |
1631 | struct msr_bitmap_range *ranges; | |
1a155254 | 1632 | struct kvm *kvm = vcpu->kvm; |
b318e8de | 1633 | bool allowed; |
1a155254 | 1634 | int idx; |
b318e8de | 1635 | u32 i; |
1a155254 | 1636 | |
b318e8de SC |
1637 | /* x2APIC MSRs do not support filtering. */ |
1638 | if (index >= 0x800 && index <= 0x8ff) | |
1a155254 AG |
1639 | return true; |
1640 | ||
1a155254 AG |
1641 | idx = srcu_read_lock(&kvm->srcu); |
1642 | ||
b318e8de SC |
1643 | msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); |
1644 | if (!msr_filter) { | |
1645 | allowed = true; | |
1646 | goto out; | |
1647 | } | |
1648 | ||
1649 | allowed = msr_filter->default_allow; | |
1650 | ranges = msr_filter->ranges; | |
1651 | ||
1652 | for (i = 0; i < msr_filter->count; i++) { | |
1a155254 AG |
1653 | u32 start = ranges[i].base; |
1654 | u32 end = start + ranges[i].nmsrs; | |
1655 | u32 flags = ranges[i].flags; | |
1656 | unsigned long *bitmap = ranges[i].bitmap; | |
1657 | ||
1658 | if ((index >= start) && (index < end) && (flags & type)) { | |
b318e8de | 1659 | allowed = !!test_bit(index - start, bitmap); |
1a155254 AG |
1660 | break; |
1661 | } | |
1662 | } | |
1663 | ||
b318e8de | 1664 | out: |
1a155254 AG |
1665 | srcu_read_unlock(&kvm->srcu, idx); |
1666 | ||
b318e8de | 1667 | return allowed; |
51de8151 AG |
1668 | } |
1669 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1670 | ||
15c4a640 | 1671 | /* |
f20935d8 SC |
1672 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1673 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1674 | * Returns 0 on success, non-0 otherwise. |
1675 | * Assumes vcpu_load() was already called. | |
1676 | */ | |
f20935d8 SC |
1677 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1678 | bool host_initiated) | |
15c4a640 | 1679 | { |
f20935d8 SC |
1680 | struct msr_data msr; |
1681 | ||
1a155254 | 1682 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) |
cc4cb017 | 1683 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1684 | |
f20935d8 | 1685 | switch (index) { |
854e8bb1 NA |
1686 | case MSR_FS_BASE: |
1687 | case MSR_GS_BASE: | |
1688 | case MSR_KERNEL_GS_BASE: | |
1689 | case MSR_CSTAR: | |
1690 | case MSR_LSTAR: | |
f20935d8 | 1691 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1692 | return 1; |
1693 | break; | |
1694 | case MSR_IA32_SYSENTER_EIP: | |
1695 | case MSR_IA32_SYSENTER_ESP: | |
1696 | /* | |
1697 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1698 | * non-canonical address is written on Intel but not on | |
1699 | * AMD (which ignores the top 32-bits, because it does | |
1700 | * not implement 64-bit SYSENTER). | |
1701 | * | |
1702 | * 64-bit code should hence be able to write a non-canonical | |
1703 | * value on AMD. Making the address canonical ensures that | |
1704 | * vmentry does not fail on Intel after writing a non-canonical | |
1705 | * value, and that something deterministic happens if the guest | |
1706 | * invokes 64-bit SYSENTER. | |
1707 | */ | |
f20935d8 | 1708 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
61a05d44 SC |
1709 | break; |
1710 | case MSR_TSC_AUX: | |
1711 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1712 | return 1; | |
1713 | ||
1714 | if (!host_initiated && | |
1715 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1716 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1717 | return 1; | |
1718 | ||
1719 | /* | |
1720 | * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has | |
1721 | * incomplete and conflicting architectural behavior. Current | |
1722 | * AMD CPUs completely ignore bits 63:32, i.e. they aren't | |
1723 | * reserved and always read as zeros. Enforce Intel's reserved | |
1724 | * bits check if and only if the guest CPU is Intel, and clear | |
1725 | * the bits in all other cases. This ensures cross-vendor | |
1726 | * migration will provide consistent behavior for the guest. | |
1727 | */ | |
1728 | if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) | |
1729 | return 1; | |
1730 | ||
1731 | data = (u32)data; | |
1732 | break; | |
854e8bb1 | 1733 | } |
f20935d8 SC |
1734 | |
1735 | msr.data = data; | |
1736 | msr.index = index; | |
1737 | msr.host_initiated = host_initiated; | |
1738 | ||
b3646477 | 1739 | return static_call(kvm_x86_set_msr)(vcpu, &msr); |
15c4a640 CO |
1740 | } |
1741 | ||
6abe9c13 PX |
1742 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1743 | u32 index, u64 data, bool host_initiated) | |
1744 | { | |
1745 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1746 | ||
1747 | if (ret == KVM_MSR_RET_INVALID) | |
d632826f | 1748 | if (kvm_msr_ignored_check(index, data, true)) |
cc4cb017 | 1749 | ret = 0; |
6abe9c13 PX |
1750 | |
1751 | return ret; | |
1752 | } | |
1753 | ||
313a3dc7 | 1754 | /* |
f20935d8 SC |
1755 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1756 | * checks are bypassed if @host_initiated is %true. | |
1757 | * Returns 0 on success, non-0 otherwise. | |
1758 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1759 | */ |
edef5c36 PB |
1760 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1761 | bool host_initiated) | |
609e36d3 PB |
1762 | { |
1763 | struct msr_data msr; | |
f20935d8 | 1764 | int ret; |
609e36d3 | 1765 | |
1a155254 | 1766 | if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) |
cc4cb017 | 1767 | return KVM_MSR_RET_FILTERED; |
1a155254 | 1768 | |
61a05d44 SC |
1769 | switch (index) { |
1770 | case MSR_TSC_AUX: | |
1771 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1772 | return 1; | |
1773 | ||
1774 | if (!host_initiated && | |
1775 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1776 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1777 | return 1; | |
1778 | break; | |
1779 | } | |
1780 | ||
609e36d3 | 1781 | msr.index = index; |
f20935d8 | 1782 | msr.host_initiated = host_initiated; |
609e36d3 | 1783 | |
b3646477 | 1784 | ret = static_call(kvm_x86_get_msr)(vcpu, &msr); |
f20935d8 SC |
1785 | if (!ret) |
1786 | *data = msr.data; | |
1787 | return ret; | |
609e36d3 PB |
1788 | } |
1789 | ||
6abe9c13 PX |
1790 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1791 | u32 index, u64 *data, bool host_initiated) | |
1792 | { | |
1793 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1794 | ||
1795 | if (ret == KVM_MSR_RET_INVALID) { | |
1796 | /* Unconditionally clear *data for simplicity */ | |
1797 | *data = 0; | |
d632826f | 1798 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1799 | ret = 0; |
6abe9c13 PX |
1800 | } |
1801 | ||
1802 | return ret; | |
1803 | } | |
1804 | ||
f20935d8 | 1805 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1806 | { |
6abe9c13 | 1807 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1808 | } |
1809 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1810 | |
f20935d8 SC |
1811 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1812 | { | |
6abe9c13 | 1813 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1814 | } |
1815 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1816 | ||
8b474427 | 1817 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) |
1ae09954 | 1818 | { |
8b474427 PB |
1819 | int err = vcpu->run->msr.error; |
1820 | if (!err) { | |
1ae09954 AG |
1821 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); |
1822 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1823 | } | |
1824 | ||
b3646477 | 1825 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); |
1ae09954 AG |
1826 | } |
1827 | ||
1828 | static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) | |
1829 | { | |
b3646477 | 1830 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); |
1ae09954 AG |
1831 | } |
1832 | ||
1833 | static u64 kvm_msr_reason(int r) | |
1834 | { | |
1835 | switch (r) { | |
cc4cb017 | 1836 | case KVM_MSR_RET_INVALID: |
1ae09954 | 1837 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 1838 | case KVM_MSR_RET_FILTERED: |
1a155254 | 1839 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
1840 | default: |
1841 | return KVM_MSR_EXIT_REASON_INVAL; | |
1842 | } | |
1843 | } | |
1844 | ||
1845 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
1846 | u32 exit_reason, u64 data, | |
1847 | int (*completion)(struct kvm_vcpu *vcpu), | |
1848 | int r) | |
1849 | { | |
1850 | u64 msr_reason = kvm_msr_reason(r); | |
1851 | ||
1852 | /* Check if the user wanted to know about this MSR fault */ | |
1853 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
1854 | return 0; | |
1855 | ||
1856 | vcpu->run->exit_reason = exit_reason; | |
1857 | vcpu->run->msr.error = 0; | |
1858 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
1859 | vcpu->run->msr.reason = msr_reason; | |
1860 | vcpu->run->msr.index = index; | |
1861 | vcpu->run->msr.data = data; | |
1862 | vcpu->arch.complete_userspace_io = completion; | |
1863 | ||
1864 | return 1; | |
1865 | } | |
1866 | ||
1867 | static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) | |
1868 | { | |
1869 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, | |
1870 | complete_emulated_rdmsr, r); | |
1871 | } | |
1872 | ||
1873 | static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) | |
1874 | { | |
1875 | return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, | |
1876 | complete_emulated_wrmsr, r); | |
1877 | } | |
1878 | ||
1edce0a9 SC |
1879 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1880 | { | |
1881 | u32 ecx = kvm_rcx_read(vcpu); | |
1882 | u64 data; | |
1ae09954 AG |
1883 | int r; |
1884 | ||
1885 | r = kvm_get_msr(vcpu, ecx, &data); | |
1edce0a9 | 1886 | |
1ae09954 AG |
1887 | /* MSR read failed? See if we should ask user space */ |
1888 | if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { | |
1889 | /* Bounce to user space */ | |
1890 | return 0; | |
1891 | } | |
1892 | ||
8b474427 PB |
1893 | if (!r) { |
1894 | trace_kvm_msr_read(ecx, data); | |
1895 | ||
1896 | kvm_rax_write(vcpu, data & -1u); | |
1897 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1898 | } else { | |
1edce0a9 | 1899 | trace_kvm_msr_read_ex(ecx); |
1edce0a9 SC |
1900 | } |
1901 | ||
b3646477 | 1902 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
1903 | } |
1904 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1905 | ||
1906 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1907 | { | |
1908 | u32 ecx = kvm_rcx_read(vcpu); | |
1909 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 1910 | int r; |
1edce0a9 | 1911 | |
1ae09954 AG |
1912 | r = kvm_set_msr(vcpu, ecx, data); |
1913 | ||
1914 | /* MSR write failed? See if we should ask user space */ | |
7dffecaf | 1915 | if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) |
1ae09954 AG |
1916 | /* Bounce to user space */ |
1917 | return 0; | |
7dffecaf ML |
1918 | |
1919 | /* Signal all other negative errors to userspace */ | |
1920 | if (r < 0) | |
1921 | return r; | |
1ae09954 | 1922 | |
8b474427 PB |
1923 | if (!r) |
1924 | trace_kvm_msr_write(ecx, data); | |
1925 | else | |
1edce0a9 | 1926 | trace_kvm_msr_write_ex(ecx, data); |
1edce0a9 | 1927 | |
b3646477 | 1928 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
1929 | } |
1930 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1931 | ||
5ff3a351 SC |
1932 | int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) |
1933 | { | |
1934 | return kvm_skip_emulated_instruction(vcpu); | |
1935 | } | |
1936 | EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); | |
1937 | ||
1938 | int kvm_emulate_invd(struct kvm_vcpu *vcpu) | |
1939 | { | |
1940 | /* Treat an INVD instruction as a NOP and just skip it. */ | |
1941 | return kvm_emulate_as_nop(vcpu); | |
1942 | } | |
1943 | EXPORT_SYMBOL_GPL(kvm_emulate_invd); | |
1944 | ||
1945 | int kvm_emulate_mwait(struct kvm_vcpu *vcpu) | |
1946 | { | |
1947 | pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); | |
1948 | return kvm_emulate_as_nop(vcpu); | |
1949 | } | |
1950 | EXPORT_SYMBOL_GPL(kvm_emulate_mwait); | |
1951 | ||
1952 | int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) | |
1953 | { | |
1954 | kvm_queue_exception(vcpu, UD_VECTOR); | |
1955 | return 1; | |
1956 | } | |
1957 | EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); | |
1958 | ||
1959 | int kvm_emulate_monitor(struct kvm_vcpu *vcpu) | |
1960 | { | |
1961 | pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); | |
1962 | return kvm_emulate_as_nop(vcpu); | |
1963 | } | |
1964 | EXPORT_SYMBOL_GPL(kvm_emulate_monitor); | |
1965 | ||
d89d04ab | 1966 | static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
5a9f5443 | 1967 | { |
4ae7dc97 | 1968 | xfer_to_guest_mode_prepare(); |
5a9f5443 | 1969 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || |
72c3c0fe | 1970 | xfer_to_guest_mode_work_pending(); |
5a9f5443 | 1971 | } |
5a9f5443 | 1972 | |
1e9e2622 WL |
1973 | /* |
1974 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
1975 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
1976 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
1977 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
1978 | * other cases which must be called after interrupts are enabled on the host. | |
1979 | */ | |
1980 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
1981 | { | |
e1be9ac8 WL |
1982 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
1983 | return 1; | |
1984 | ||
1985 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
1e9e2622 | 1986 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
4064a4c6 WL |
1987 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && |
1988 | ((u32)(data >> 32) != X2APIC_BROADCAST)) { | |
1e9e2622 | 1989 | |
d5361678 WL |
1990 | data &= ~(1 << 12); |
1991 | kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); | |
1e9e2622 | 1992 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); |
d5361678 WL |
1993 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); |
1994 | trace_kvm_apic_write(APIC_ICR, (u32)data); | |
1995 | return 0; | |
1e9e2622 WL |
1996 | } |
1997 | ||
1998 | return 1; | |
1999 | } | |
2000 | ||
ae95f566 WL |
2001 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
2002 | { | |
2003 | if (!kvm_can_use_hv_timer(vcpu)) | |
2004 | return 1; | |
2005 | ||
2006 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2007 | return 0; | |
2008 | } | |
2009 | ||
404d5d7b | 2010 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
2011 | { |
2012 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 2013 | u64 data; |
404d5d7b | 2014 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 WL |
2015 | |
2016 | switch (msr) { | |
2017 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 2018 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
2019 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
2020 | kvm_skip_emulated_instruction(vcpu); | |
2021 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 2022 | } |
1e9e2622 | 2023 | break; |
09141ec0 | 2024 | case MSR_IA32_TSC_DEADLINE: |
ae95f566 WL |
2025 | data = kvm_read_edx_eax(vcpu); |
2026 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
2027 | kvm_skip_emulated_instruction(vcpu); | |
2028 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
2029 | } | |
2030 | break; | |
1e9e2622 | 2031 | default: |
404d5d7b | 2032 | break; |
1e9e2622 WL |
2033 | } |
2034 | ||
404d5d7b | 2035 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 2036 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 2037 | |
404d5d7b | 2038 | return ret; |
1e9e2622 WL |
2039 | } |
2040 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
2041 | ||
f20935d8 SC |
2042 | /* |
2043 | * Adapt set_msr() to msr_io()'s calling convention | |
2044 | */ | |
2045 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2046 | { | |
6abe9c13 | 2047 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
2048 | } |
2049 | ||
2050 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2051 | { | |
6abe9c13 | 2052 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
2053 | } |
2054 | ||
16e8d74d | 2055 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
2056 | struct pvclock_clock { |
2057 | int vclock_mode; | |
2058 | u64 cycle_last; | |
2059 | u64 mask; | |
2060 | u32 mult; | |
2061 | u32 shift; | |
917f9475 PB |
2062 | u64 base_cycles; |
2063 | u64 offset; | |
53fafdbb MT |
2064 | }; |
2065 | ||
16e8d74d MT |
2066 | struct pvclock_gtod_data { |
2067 | seqcount_t seq; | |
2068 | ||
53fafdbb MT |
2069 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
2070 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 2071 | |
917f9475 | 2072 | ktime_t offs_boot; |
55dd00a7 | 2073 | u64 wall_time_sec; |
16e8d74d MT |
2074 | }; |
2075 | ||
2076 | static struct pvclock_gtod_data pvclock_gtod_data; | |
2077 | ||
2078 | static void update_pvclock_gtod(struct timekeeper *tk) | |
2079 | { | |
2080 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
2081 | ||
2082 | write_seqcount_begin(&vdata->seq); | |
2083 | ||
2084 | /* copy pvclock gtod data */ | |
b95a8a27 | 2085 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
2086 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
2087 | vdata->clock.mask = tk->tkr_mono.mask; | |
2088 | vdata->clock.mult = tk->tkr_mono.mult; | |
2089 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
2090 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
2091 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 2092 | |
b95a8a27 | 2093 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
2094 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
2095 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
2096 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
2097 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
2098 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
2099 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 2100 | |
55dd00a7 MT |
2101 | vdata->wall_time_sec = tk->xtime_sec; |
2102 | ||
917f9475 | 2103 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 2104 | |
16e8d74d MT |
2105 | write_seqcount_end(&vdata->seq); |
2106 | } | |
8171cd68 PB |
2107 | |
2108 | static s64 get_kvmclock_base_ns(void) | |
2109 | { | |
2110 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
2111 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
2112 | } | |
2113 | #else | |
2114 | static s64 get_kvmclock_base_ns(void) | |
2115 | { | |
2116 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
2117 | return ktime_get_boottime_ns(); | |
2118 | } | |
16e8d74d MT |
2119 | #endif |
2120 | ||
629b5348 | 2121 | void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) |
18068523 | 2122 | { |
9ed3c444 AK |
2123 | int version; |
2124 | int r; | |
50d0a0f9 | 2125 | struct pvclock_wall_clock wc; |
629b5348 | 2126 | u32 wc_sec_hi; |
8171cd68 | 2127 | u64 wall_nsec; |
18068523 GOC |
2128 | |
2129 | if (!wall_clock) | |
2130 | return; | |
2131 | ||
9ed3c444 AK |
2132 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
2133 | if (r) | |
2134 | return; | |
2135 | ||
2136 | if (version & 1) | |
2137 | ++version; /* first time write, random junk */ | |
2138 | ||
2139 | ++version; | |
18068523 | 2140 | |
1dab1345 NK |
2141 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
2142 | return; | |
18068523 | 2143 | |
50d0a0f9 GH |
2144 | /* |
2145 | * The guest calculates current wall clock time by adding | |
34c238a1 | 2146 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 2147 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 2148 | */ |
8171cd68 | 2149 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 2150 | |
8171cd68 PB |
2151 | wc.nsec = do_div(wall_nsec, 1000000000); |
2152 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 2153 | wc.version = version; |
18068523 GOC |
2154 | |
2155 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
2156 | ||
629b5348 JM |
2157 | if (sec_hi_ofs) { |
2158 | wc_sec_hi = wall_nsec >> 32; | |
2159 | kvm_write_guest(kvm, wall_clock + sec_hi_ofs, | |
2160 | &wc_sec_hi, sizeof(wc_sec_hi)); | |
2161 | } | |
2162 | ||
18068523 GOC |
2163 | version++; |
2164 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
2165 | } |
2166 | ||
5b9bb0eb OU |
2167 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
2168 | bool old_msr, bool host_initiated) | |
2169 | { | |
2170 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
2171 | ||
2172 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 2173 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
2174 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2175 | ||
2176 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
2177 | } | |
2178 | ||
2179 | vcpu->arch.time = system_time; | |
2180 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
2181 | ||
2182 | /* we verify if the enable bit is set... */ | |
2183 | vcpu->arch.pv_time_enabled = false; | |
2184 | if (!(system_time & 1)) | |
2185 | return; | |
2186 | ||
2187 | if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2188 | &vcpu->arch.pv_time, system_time & ~1ULL, | |
2189 | sizeof(struct pvclock_vcpu_time_info))) | |
2190 | vcpu->arch.pv_time_enabled = true; | |
2191 | ||
2192 | return; | |
2193 | } | |
2194 | ||
50d0a0f9 GH |
2195 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
2196 | { | |
b51012de PB |
2197 | do_shl32_div32(dividend, divisor); |
2198 | return dividend; | |
50d0a0f9 GH |
2199 | } |
2200 | ||
3ae13faa | 2201 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2202 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2203 | { |
5f4e3f88 | 2204 | uint64_t scaled64; |
50d0a0f9 GH |
2205 | int32_t shift = 0; |
2206 | uint64_t tps64; | |
2207 | uint32_t tps32; | |
2208 | ||
3ae13faa PB |
2209 | tps64 = base_hz; |
2210 | scaled64 = scaled_hz; | |
50933623 | 2211 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2212 | tps64 >>= 1; |
2213 | shift--; | |
2214 | } | |
2215 | ||
2216 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2217 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2218 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2219 | scaled64 >>= 1; |
2220 | else | |
2221 | tps32 <<= 1; | |
50d0a0f9 GH |
2222 | shift++; |
2223 | } | |
2224 | ||
5f4e3f88 ZA |
2225 | *pshift = shift; |
2226 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2227 | } |
2228 | ||
d828199e | 2229 | #ifdef CONFIG_X86_64 |
16e8d74d | 2230 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2231 | #endif |
16e8d74d | 2232 | |
c8076604 | 2233 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2234 | static unsigned long max_tsc_khz; |
c8076604 | 2235 | |
cc578287 | 2236 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2237 | { |
cc578287 ZA |
2238 | u64 v = (u64)khz * (1000000 + ppm); |
2239 | do_div(v, 1000000); | |
2240 | return v; | |
1e993611 JR |
2241 | } |
2242 | ||
1ab9287a IS |
2243 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); |
2244 | ||
381d585c HZ |
2245 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2246 | { | |
2247 | u64 ratio; | |
2248 | ||
2249 | /* Guest TSC same frequency as host TSC? */ | |
2250 | if (!scale) { | |
1ab9287a | 2251 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); |
381d585c HZ |
2252 | return 0; |
2253 | } | |
2254 | ||
2255 | /* TSC scaling supported? */ | |
2256 | if (!kvm_has_tsc_control) { | |
2257 | if (user_tsc_khz > tsc_khz) { | |
2258 | vcpu->arch.tsc_catchup = 1; | |
2259 | vcpu->arch.tsc_always_catchup = 1; | |
2260 | return 0; | |
2261 | } else { | |
3f16a5c3 | 2262 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2263 | return -1; |
2264 | } | |
2265 | } | |
2266 | ||
2267 | /* TSC scaling required - calculate ratio */ | |
2268 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
2269 | user_tsc_khz, tsc_khz); | |
2270 | ||
2271 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
2272 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2273 | user_tsc_khz); | |
381d585c HZ |
2274 | return -1; |
2275 | } | |
2276 | ||
1ab9287a | 2277 | kvm_vcpu_write_tsc_multiplier(vcpu, ratio); |
381d585c HZ |
2278 | return 0; |
2279 | } | |
2280 | ||
4941b8cb | 2281 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2282 | { |
cc578287 ZA |
2283 | u32 thresh_lo, thresh_hi; |
2284 | int use_scaling = 0; | |
217fc9cf | 2285 | |
03ba32ca | 2286 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2287 | if (user_tsc_khz == 0) { |
ad721883 | 2288 | /* set tsc_scaling_ratio to a safe value */ |
1ab9287a | 2289 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); |
381d585c | 2290 | return -1; |
ad721883 | 2291 | } |
03ba32ca | 2292 | |
c285545f | 2293 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2294 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2295 | &vcpu->arch.virtual_tsc_shift, |
2296 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2297 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2298 | |
2299 | /* | |
2300 | * Compute the variation in TSC rate which is acceptable | |
2301 | * within the range of tolerance and decide if the | |
2302 | * rate being applied is within that bounds of the hardware | |
2303 | * rate. If so, no scaling or compensation need be done. | |
2304 | */ | |
2305 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2306 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
2307 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
2308 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2309 | use_scaling = 1; |
2310 | } | |
4941b8cb | 2311 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2312 | } |
2313 | ||
2314 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2315 | { | |
e26101b1 | 2316 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2317 | vcpu->arch.virtual_tsc_mult, |
2318 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2319 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2320 | return tsc; |
2321 | } | |
2322 | ||
b0c39dc6 VK |
2323 | static inline int gtod_is_based_on_tsc(int mode) |
2324 | { | |
b95a8a27 | 2325 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 VK |
2326 | } |
2327 | ||
69b0049a | 2328 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
2329 | { |
2330 | #ifdef CONFIG_X86_64 | |
2331 | bool vcpus_matched; | |
b48aa97e MT |
2332 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2333 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2334 | ||
2335 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2336 | atomic_read(&vcpu->kvm->online_vcpus)); | |
2337 | ||
7f187922 MT |
2338 | /* |
2339 | * Once the masterclock is enabled, always perform request in | |
2340 | * order to update it. | |
2341 | * | |
2342 | * In order to enable masterclock, the host clocksource must be TSC | |
2343 | * and the vcpus need to have matched TSCs. When that happens, | |
2344 | * perform request to enable masterclock. | |
2345 | */ | |
2346 | if (ka->use_master_clock || | |
b0c39dc6 | 2347 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
2348 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2349 | ||
2350 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2351 | atomic_read(&vcpu->kvm->online_vcpus), | |
2352 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2353 | #endif | |
2354 | } | |
2355 | ||
35181e86 HZ |
2356 | /* |
2357 | * Multiply tsc by a fixed point number represented by ratio. | |
2358 | * | |
2359 | * The most significant 64-N bits (mult) of ratio represent the | |
2360 | * integral part of the fixed point number; the remaining N bits | |
2361 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2362 | * point number (mult + frac * 2^(-N)). | |
2363 | * | |
2364 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
2365 | */ | |
2366 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2367 | { | |
2368 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
2369 | } | |
2370 | ||
fe3eb504 | 2371 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc, u64 ratio) |
35181e86 HZ |
2372 | { |
2373 | u64 _tsc = tsc; | |
35181e86 HZ |
2374 | |
2375 | if (ratio != kvm_default_tsc_scaling_ratio) | |
2376 | _tsc = __scale_tsc(ratio, tsc); | |
2377 | ||
2378 | return _tsc; | |
2379 | } | |
2380 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
2381 | ||
9b399dfd | 2382 | static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
07c1419a HZ |
2383 | { |
2384 | u64 tsc; | |
2385 | ||
fe3eb504 | 2386 | tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); |
07c1419a HZ |
2387 | |
2388 | return target_tsc - tsc; | |
2389 | } | |
2390 | ||
4ba76538 HZ |
2391 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2392 | { | |
fe3eb504 IS |
2393 | return vcpu->arch.l1_tsc_offset + |
2394 | kvm_scale_tsc(vcpu, host_tsc, vcpu->arch.l1_tsc_scaling_ratio); | |
4ba76538 HZ |
2395 | } |
2396 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2397 | ||
83150f29 IS |
2398 | u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) |
2399 | { | |
2400 | u64 nested_offset; | |
2401 | ||
2402 | if (l2_multiplier == kvm_default_tsc_scaling_ratio) | |
2403 | nested_offset = l1_offset; | |
2404 | else | |
2405 | nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, | |
2406 | kvm_tsc_scaling_ratio_frac_bits); | |
2407 | ||
2408 | nested_offset += l2_offset; | |
2409 | return nested_offset; | |
2410 | } | |
2411 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); | |
2412 | ||
2413 | u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) | |
2414 | { | |
2415 | if (l2_multiplier != kvm_default_tsc_scaling_ratio) | |
2416 | return mul_u64_u64_shr(l1_multiplier, l2_multiplier, | |
2417 | kvm_tsc_scaling_ratio_frac_bits); | |
2418 | ||
2419 | return l1_multiplier; | |
2420 | } | |
2421 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); | |
2422 | ||
edcfe540 | 2423 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) |
a545ab6a | 2424 | { |
edcfe540 IS |
2425 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2426 | vcpu->arch.l1_tsc_offset, | |
2427 | l1_offset); | |
2428 | ||
2429 | vcpu->arch.l1_tsc_offset = l1_offset; | |
2430 | ||
2431 | /* | |
2432 | * If we are here because L1 chose not to trap WRMSR to TSC then | |
2433 | * according to the spec this should set L1's TSC (as opposed to | |
2434 | * setting L1's offset for L2). | |
2435 | */ | |
2436 | if (is_guest_mode(vcpu)) | |
2437 | vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( | |
2438 | l1_offset, | |
2439 | static_call(kvm_x86_get_l2_tsc_offset)(vcpu), | |
2440 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2441 | else | |
2442 | vcpu->arch.tsc_offset = l1_offset; | |
2443 | ||
2444 | static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); | |
a545ab6a LC |
2445 | } |
2446 | ||
1ab9287a IS |
2447 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) |
2448 | { | |
2449 | vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; | |
2450 | ||
2451 | /* Userspace is changing the multiplier while L2 is active */ | |
2452 | if (is_guest_mode(vcpu)) | |
2453 | vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( | |
2454 | l1_multiplier, | |
2455 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2456 | else | |
2457 | vcpu->arch.tsc_scaling_ratio = l1_multiplier; | |
2458 | ||
2459 | if (kvm_has_tsc_control) | |
2460 | static_call(kvm_x86_write_tsc_multiplier)( | |
2461 | vcpu, vcpu->arch.tsc_scaling_ratio); | |
2462 | } | |
2463 | ||
b0c39dc6 VK |
2464 | static inline bool kvm_check_tsc_unstable(void) |
2465 | { | |
2466 | #ifdef CONFIG_X86_64 | |
2467 | /* | |
2468 | * TSC is marked unstable when we're running on Hyper-V, | |
2469 | * 'TSC page' clocksource is good. | |
2470 | */ | |
b95a8a27 | 2471 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2472 | return false; |
2473 | #endif | |
2474 | return check_tsc_unstable(); | |
2475 | } | |
2476 | ||
58d4277b OU |
2477 | /* |
2478 | * Infers attempts to synchronize the guest's tsc from host writes. Sets the | |
2479 | * offset for the vcpu and tracks the TSC matching generation that the vcpu | |
2480 | * participates in. | |
2481 | */ | |
2482 | static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, | |
2483 | u64 ns, bool matched) | |
2484 | { | |
2485 | struct kvm *kvm = vcpu->kvm; | |
2486 | ||
2487 | lockdep_assert_held(&kvm->arch.tsc_write_lock); | |
2488 | ||
2489 | /* | |
2490 | * We also track th most recent recorded KHZ, write and time to | |
2491 | * allow the matching interval to be extended at each write. | |
2492 | */ | |
2493 | kvm->arch.last_tsc_nsec = ns; | |
2494 | kvm->arch.last_tsc_write = tsc; | |
2495 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; | |
828ca896 | 2496 | kvm->arch.last_tsc_offset = offset; |
58d4277b OU |
2497 | |
2498 | vcpu->arch.last_guest_tsc = tsc; | |
2499 | ||
2500 | kvm_vcpu_write_tsc_offset(vcpu, offset); | |
2501 | ||
2502 | if (!matched) { | |
2503 | /* | |
2504 | * We split periods of matched TSC writes into generations. | |
2505 | * For each generation, we track the original measured | |
2506 | * nanosecond time, offset, and write, so if TSCs are in | |
2507 | * sync, we can match exact offset, and if not, we can match | |
2508 | * exact software computation in compute_guest_tsc() | |
2509 | * | |
2510 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2511 | */ | |
2512 | kvm->arch.cur_tsc_generation++; | |
2513 | kvm->arch.cur_tsc_nsec = ns; | |
2514 | kvm->arch.cur_tsc_write = tsc; | |
2515 | kvm->arch.cur_tsc_offset = offset; | |
2516 | kvm->arch.nr_vcpus_matched_tsc = 0; | |
2517 | } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { | |
2518 | kvm->arch.nr_vcpus_matched_tsc++; | |
2519 | } | |
2520 | ||
2521 | /* Keep track of which generation this VCPU has synchronized to */ | |
2522 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2523 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2524 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2525 | ||
2526 | kvm_track_tsc_matching(vcpu); | |
2527 | } | |
2528 | ||
0c899c25 | 2529 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) |
99e3e30a ZA |
2530 | { |
2531 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2532 | u64 offset, ns, elapsed; |
99e3e30a | 2533 | unsigned long flags; |
58d4277b | 2534 | bool matched = false; |
c5e8ec8e | 2535 | bool synchronizing = false; |
99e3e30a | 2536 | |
038f8c11 | 2537 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
9b399dfd | 2538 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
8171cd68 | 2539 | ns = get_kvmclock_base_ns(); |
f38e098f | 2540 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2541 | |
03ba32ca | 2542 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2543 | if (data == 0) { |
bd8fab39 DP |
2544 | /* |
2545 | * detection of vcpu initialization -- need to sync | |
2546 | * with other vCPUs. This particularly helps to keep | |
2547 | * kvm_clock stable after CPU hotplug | |
2548 | */ | |
2549 | synchronizing = true; | |
2550 | } else { | |
2551 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2552 | nsec_to_cycles(vcpu, elapsed); | |
2553 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2554 | /* | |
2555 | * Special case: TSC write with a small delta (1 second) | |
2556 | * of virtual cycle time against real time is | |
2557 | * interpreted as an attempt to synchronize the CPU. | |
2558 | */ | |
2559 | synchronizing = data < tsc_exp + tsc_hz && | |
2560 | data + tsc_hz > tsc_exp; | |
2561 | } | |
c5e8ec8e | 2562 | } |
f38e098f ZA |
2563 | |
2564 | /* | |
5d3cb0f6 ZA |
2565 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2566 | * TSC, we add elapsed time in this computation. We could let the | |
2567 | * compensation code attempt to catch up if we fall behind, but | |
2568 | * it's better to try to match offsets from the beginning. | |
2569 | */ | |
c5e8ec8e | 2570 | if (synchronizing && |
5d3cb0f6 | 2571 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2572 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2573 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2574 | } else { |
857e4099 | 2575 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2576 | data += delta; |
9b399dfd | 2577 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
f38e098f | 2578 | } |
b48aa97e | 2579 | matched = true; |
f38e098f | 2580 | } |
e26101b1 | 2581 | |
58d4277b | 2582 | __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); |
869b4421 | 2583 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
99e3e30a | 2584 | } |
e26101b1 | 2585 | |
58ea6767 HZ |
2586 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2587 | s64 adjustment) | |
2588 | { | |
56ba77a4 | 2589 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2590 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2591 | } |
2592 | ||
2593 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2594 | { | |
805d705f | 2595 | if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) |
58ea6767 | 2596 | WARN_ON(adjustment < 0); |
fe3eb504 IS |
2597 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment, |
2598 | vcpu->arch.l1_tsc_scaling_ratio); | |
ea26e4ec | 2599 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2600 | } |
2601 | ||
d828199e MT |
2602 | #ifdef CONFIG_X86_64 |
2603 | ||
a5a1d1c2 | 2604 | static u64 read_tsc(void) |
d828199e | 2605 | { |
a5a1d1c2 | 2606 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2607 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2608 | |
2609 | if (likely(ret >= last)) | |
2610 | return ret; | |
2611 | ||
2612 | /* | |
2613 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2614 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2615 | * very likely) and there's a data dependence, so force GCC |
2616 | * to generate a branch instead. I don't barrier() because | |
2617 | * we don't actually need a barrier, and if this function | |
2618 | * ever gets inlined it will generate worse code. | |
2619 | */ | |
2620 | asm volatile (""); | |
2621 | return last; | |
2622 | } | |
2623 | ||
53fafdbb MT |
2624 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2625 | int *mode) | |
d828199e MT |
2626 | { |
2627 | long v; | |
b0c39dc6 VK |
2628 | u64 tsc_pg_val; |
2629 | ||
53fafdbb | 2630 | switch (clock->vclock_mode) { |
b95a8a27 | 2631 | case VDSO_CLOCKMODE_HVCLOCK: |
b0c39dc6 VK |
2632 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2633 | tsc_timestamp); | |
2634 | if (tsc_pg_val != U64_MAX) { | |
2635 | /* TSC page valid */ | |
b95a8a27 | 2636 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2637 | v = (tsc_pg_val - clock->cycle_last) & |
2638 | clock->mask; | |
b0c39dc6 VK |
2639 | } else { |
2640 | /* TSC page invalid */ | |
b95a8a27 | 2641 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2642 | } |
2643 | break; | |
b95a8a27 TG |
2644 | case VDSO_CLOCKMODE_TSC: |
2645 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2646 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2647 | v = (*tsc_timestamp - clock->cycle_last) & |
2648 | clock->mask; | |
b0c39dc6 VK |
2649 | break; |
2650 | default: | |
b95a8a27 | 2651 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2652 | } |
d828199e | 2653 | |
b95a8a27 | 2654 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2655 | *tsc_timestamp = v = 0; |
d828199e | 2656 | |
53fafdbb | 2657 | return v * clock->mult; |
d828199e MT |
2658 | } |
2659 | ||
53fafdbb | 2660 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2661 | { |
cbcf2dd3 | 2662 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2663 | unsigned long seq; |
d828199e | 2664 | int mode; |
cbcf2dd3 | 2665 | u64 ns; |
d828199e | 2666 | |
d828199e MT |
2667 | do { |
2668 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2669 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2670 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2671 | ns >>= gtod->raw_clock.shift; |
2672 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2673 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2674 | *t = ns; |
d828199e MT |
2675 | |
2676 | return mode; | |
2677 | } | |
2678 | ||
899a31f5 | 2679 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2680 | { |
2681 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2682 | unsigned long seq; | |
2683 | int mode; | |
2684 | u64 ns; | |
2685 | ||
2686 | do { | |
2687 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2688 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2689 | ns = gtod->clock.base_cycles; |
53fafdbb | 2690 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2691 | ns >>= gtod->clock.shift; |
2692 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2693 | ||
2694 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2695 | ts->tv_nsec = ns; | |
2696 | ||
2697 | return mode; | |
2698 | } | |
2699 | ||
b0c39dc6 VK |
2700 | /* returns true if host is using TSC based clocksource */ |
2701 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2702 | { |
d828199e | 2703 | /* checked again under seqlock below */ |
b0c39dc6 | 2704 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2705 | return false; |
2706 | ||
53fafdbb | 2707 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2708 | tsc_timestamp)); |
d828199e | 2709 | } |
55dd00a7 | 2710 | |
b0c39dc6 | 2711 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2712 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2713 | u64 *tsc_timestamp) |
55dd00a7 MT |
2714 | { |
2715 | /* checked again under seqlock below */ | |
b0c39dc6 | 2716 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2717 | return false; |
2718 | ||
b0c39dc6 | 2719 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2720 | } |
d828199e MT |
2721 | #endif |
2722 | ||
2723 | /* | |
2724 | * | |
b48aa97e MT |
2725 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2726 | * across virtual CPUs, the following condition is possible. | |
2727 | * Each numbered line represents an event visible to both | |
d828199e MT |
2728 | * CPUs at the next numbered event. |
2729 | * | |
2730 | * "timespecX" represents host monotonic time. "tscX" represents | |
2731 | * RDTSC value. | |
2732 | * | |
2733 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2734 | * | |
2735 | * 1. read timespec0,tsc0 | |
2736 | * 2. | timespec1 = timespec0 + N | |
2737 | * | tsc1 = tsc0 + M | |
2738 | * 3. transition to guest | transition to guest | |
2739 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2740 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2741 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2742 | * | |
2743 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2744 | * | |
2745 | * - ret0 < ret1 | |
2746 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2747 | * ... | |
2748 | * - 0 < N - M => M < N | |
2749 | * | |
2750 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2751 | * always the case (the difference between two distinct xtime instances | |
2752 | * might be smaller then the difference between corresponding TSC reads, | |
2753 | * when updating guest vcpus pvclock areas). | |
2754 | * | |
2755 | * To avoid that problem, do not allow visibility of distinct | |
2756 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2757 | * copy of host monotonic time values. Update that master copy | |
2758 | * in lockstep. | |
2759 | * | |
b48aa97e | 2760 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2761 | * |
2762 | */ | |
2763 | ||
2764 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2765 | { | |
2766 | #ifdef CONFIG_X86_64 | |
2767 | struct kvm_arch *ka = &kvm->arch; | |
2768 | int vclock_mode; | |
b48aa97e MT |
2769 | bool host_tsc_clocksource, vcpus_matched; |
2770 | ||
869b4421 | 2771 | lockdep_assert_held(&kvm->arch.tsc_write_lock); |
b48aa97e MT |
2772 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == |
2773 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2774 | |
2775 | /* | |
2776 | * If the host uses TSC clock, then passthrough TSC as stable | |
2777 | * to the guest. | |
2778 | */ | |
b48aa97e | 2779 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2780 | &ka->master_kernel_ns, |
2781 | &ka->master_cycle_now); | |
2782 | ||
16a96021 | 2783 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2784 | && !ka->backwards_tsc_observed |
54750f2c | 2785 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2786 | |
d828199e MT |
2787 | if (ka->use_master_clock) |
2788 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2789 | ||
2790 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2791 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2792 | vcpus_matched); | |
d828199e MT |
2793 | #endif |
2794 | } | |
2795 | ||
6b6fcd28 | 2796 | static void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2860c4b1 PB |
2797 | { |
2798 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2799 | } | |
2800 | ||
869b4421 | 2801 | static void __kvm_start_pvclock_update(struct kvm *kvm) |
2e762ff7 | 2802 | { |
869b4421 PB |
2803 | raw_spin_lock_irq(&kvm->arch.tsc_write_lock); |
2804 | write_seqcount_begin(&kvm->arch.pvclock_sc); | |
2805 | } | |
e880c6ea | 2806 | |
869b4421 PB |
2807 | static void kvm_start_pvclock_update(struct kvm *kvm) |
2808 | { | |
2e762ff7 | 2809 | kvm_make_mclock_inprogress_request(kvm); |
c2c647f9 | 2810 | |
2e762ff7 | 2811 | /* no guest entries from this point */ |
869b4421 | 2812 | __kvm_start_pvclock_update(kvm); |
6b6fcd28 | 2813 | } |
2e762ff7 | 2814 | |
6b6fcd28 PB |
2815 | static void kvm_end_pvclock_update(struct kvm *kvm) |
2816 | { | |
2817 | struct kvm_arch *ka = &kvm->arch; | |
2818 | struct kvm_vcpu *vcpu; | |
2819 | int i; | |
2820 | ||
869b4421 PB |
2821 | write_seqcount_end(&ka->pvclock_sc); |
2822 | raw_spin_unlock_irq(&ka->tsc_write_lock); | |
2e762ff7 | 2823 | kvm_for_each_vcpu(i, vcpu, kvm) |
105b21bb | 2824 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2825 | |
2826 | /* guest entries allowed */ | |
2827 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2828 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
6b6fcd28 PB |
2829 | } |
2830 | ||
2831 | static void kvm_update_masterclock(struct kvm *kvm) | |
2832 | { | |
2833 | kvm_hv_invalidate_tsc_page(kvm); | |
2834 | kvm_start_pvclock_update(kvm); | |
2835 | pvclock_update_vm_gtod_copy(kvm); | |
2836 | kvm_end_pvclock_update(kvm); | |
2e762ff7 MT |
2837 | } |
2838 | ||
869b4421 PB |
2839 | /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ |
2840 | static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) | |
108b249c | 2841 | { |
108b249c | 2842 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2843 | struct pvclock_vcpu_time_info hv_clock; |
8b953440 | 2844 | |
e2c2206a WL |
2845 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2846 | get_cpu(); | |
2847 | ||
869b4421 PB |
2848 | data->flags = 0; |
2849 | if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) { | |
c68dc1b5 OU |
2850 | #ifdef CONFIG_X86_64 |
2851 | struct timespec64 ts; | |
2852 | ||
2853 | if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { | |
2854 | data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; | |
2855 | data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; | |
2856 | } else | |
2857 | #endif | |
2858 | data->host_tsc = rdtsc(); | |
2859 | ||
869b4421 PB |
2860 | data->flags |= KVM_CLOCK_TSC_STABLE; |
2861 | hv_clock.tsc_timestamp = ka->master_cycle_now; | |
2862 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
e70b57a6 WL |
2863 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, |
2864 | &hv_clock.tsc_shift, | |
2865 | &hv_clock.tsc_to_system_mul); | |
c68dc1b5 | 2866 | data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); |
55c0cefb OU |
2867 | } else { |
2868 | data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; | |
2869 | } | |
e2c2206a WL |
2870 | |
2871 | put_cpu(); | |
55c0cefb | 2872 | } |
e2c2206a | 2873 | |
869b4421 PB |
2874 | static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) |
2875 | { | |
2876 | struct kvm_arch *ka = &kvm->arch; | |
2877 | unsigned seq; | |
2878 | ||
2879 | do { | |
2880 | seq = read_seqcount_begin(&ka->pvclock_sc); | |
2881 | __get_kvmclock(kvm, data); | |
2882 | } while (read_seqcount_retry(&ka->pvclock_sc, seq)); | |
2883 | } | |
2884 | ||
55c0cefb OU |
2885 | u64 get_kvmclock_ns(struct kvm *kvm) |
2886 | { | |
2887 | struct kvm_clock_data data; | |
2888 | ||
55c0cefb OU |
2889 | get_kvmclock(kvm, &data); |
2890 | return data.clock; | |
108b249c PB |
2891 | } |
2892 | ||
aa096aa0 JM |
2893 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v, |
2894 | struct gfn_to_hva_cache *cache, | |
2895 | unsigned int offset) | |
0d6dd2ff PB |
2896 | { |
2897 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2898 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2899 | ||
aa096aa0 JM |
2900 | if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, |
2901 | &guest_hv_clock, offset, sizeof(guest_hv_clock)))) | |
0d6dd2ff PB |
2902 | return; |
2903 | ||
2904 | /* This VCPU is paused, but it's legal for a guest to read another | |
2905 | * VCPU's kvmclock, so we really have to follow the specification where | |
2906 | * it says that version is odd if data is being modified, and even after | |
2907 | * it is consistent. | |
2908 | * | |
2909 | * Version field updates must be kept separate. This is because | |
2910 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2911 | * writes within a string instruction are weakly ordered. So there | |
2912 | * are three writes overall. | |
2913 | * | |
2914 | * As a small optimization, only write the version field in the first | |
2915 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2916 | * version field is the first in the struct. | |
2917 | */ | |
2918 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2919 | ||
51c4b8bb LA |
2920 | if (guest_hv_clock.version & 1) |
2921 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2922 | ||
0d6dd2ff | 2923 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
aa096aa0 JM |
2924 | kvm_write_guest_offset_cached(v->kvm, cache, |
2925 | &vcpu->hv_clock, offset, | |
2926 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2927 | |
2928 | smp_wmb(); | |
2929 | ||
2930 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2931 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2932 | ||
2933 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2934 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2935 | vcpu->pvclock_set_guest_stopped_request = false; | |
2936 | } | |
2937 | ||
2938 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2939 | ||
aa096aa0 JM |
2940 | kvm_write_guest_offset_cached(v->kvm, cache, |
2941 | &vcpu->hv_clock, offset, | |
2942 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2943 | |
2944 | smp_wmb(); | |
2945 | ||
2946 | vcpu->hv_clock.version++; | |
aa096aa0 JM |
2947 | kvm_write_guest_offset_cached(v->kvm, cache, |
2948 | &vcpu->hv_clock, offset, | |
2949 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2950 | } |
2951 | ||
34c238a1 | 2952 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2953 | { |
78db6a50 | 2954 | unsigned long flags, tgt_tsc_khz; |
869b4421 | 2955 | unsigned seq; |
18068523 | 2956 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2957 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2958 | s64 kernel_ns; |
d828199e | 2959 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2960 | u8 pvclock_flags; |
d828199e MT |
2961 | bool use_master_clock; |
2962 | ||
2963 | kernel_ns = 0; | |
2964 | host_tsc = 0; | |
18068523 | 2965 | |
d828199e MT |
2966 | /* |
2967 | * If the host uses TSC clock, then passthrough TSC as stable | |
2968 | * to the guest. | |
2969 | */ | |
869b4421 PB |
2970 | do { |
2971 | seq = read_seqcount_begin(&ka->pvclock_sc); | |
2972 | use_master_clock = ka->use_master_clock; | |
2973 | if (use_master_clock) { | |
2974 | host_tsc = ka->master_cycle_now; | |
2975 | kernel_ns = ka->master_kernel_ns; | |
2976 | } | |
2977 | } while (read_seqcount_retry(&ka->pvclock_sc, seq)); | |
c09664bb MT |
2978 | |
2979 | /* Keep irq disabled to prevent changes to the clock */ | |
2980 | local_irq_save(flags); | |
78db6a50 PB |
2981 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2982 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2983 | local_irq_restore(flags); |
2984 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2985 | return 1; | |
2986 | } | |
d828199e | 2987 | if (!use_master_clock) { |
4ea1636b | 2988 | host_tsc = rdtsc(); |
8171cd68 | 2989 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
2990 | } |
2991 | ||
4ba76538 | 2992 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2993 | |
c285545f ZA |
2994 | /* |
2995 | * We may have to catch up the TSC to match elapsed wall clock | |
2996 | * time for two reasons, even if kvmclock is used. | |
2997 | * 1) CPU could have been running below the maximum TSC rate | |
2998 | * 2) Broken TSC compensation resets the base at each VCPU | |
2999 | * entry to avoid unknown leaps of TSC even when running | |
3000 | * again on the same CPU. This may cause apparent elapsed | |
3001 | * time to disappear, and the guest to stand still or run | |
3002 | * very slowly. | |
3003 | */ | |
3004 | if (vcpu->tsc_catchup) { | |
3005 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
3006 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 3007 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
3008 | tsc_timestamp = tsc; |
3009 | } | |
50d0a0f9 GH |
3010 | } |
3011 | ||
18068523 GOC |
3012 | local_irq_restore(flags); |
3013 | ||
0d6dd2ff | 3014 | /* With all the info we got, fill in the values */ |
18068523 | 3015 | |
78db6a50 | 3016 | if (kvm_has_tsc_control) |
fe3eb504 IS |
3017 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz, |
3018 | v->arch.l1_tsc_scaling_ratio); | |
78db6a50 PB |
3019 | |
3020 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 3021 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
3022 | &vcpu->hv_clock.tsc_shift, |
3023 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 3024 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
3025 | } |
3026 | ||
1d5f066e | 3027 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 3028 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 3029 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 3030 | |
d828199e | 3031 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 3032 | pvclock_flags = 0; |
d828199e MT |
3033 | if (use_master_clock) |
3034 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
3035 | ||
78c0337a MT |
3036 | vcpu->hv_clock.flags = pvclock_flags; |
3037 | ||
095cf55d | 3038 | if (vcpu->pv_time_enabled) |
aa096aa0 JM |
3039 | kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); |
3040 | if (vcpu->xen.vcpu_info_set) | |
3041 | kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, | |
3042 | offsetof(struct compat_vcpu_info, time)); | |
f2340cd9 JM |
3043 | if (vcpu->xen.vcpu_time_info_set) |
3044 | kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); | |
94c245a2 | 3045 | if (!v->vcpu_idx) |
095cf55d | 3046 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); |
8cfdc000 | 3047 | return 0; |
c8076604 GH |
3048 | } |
3049 | ||
0061d53d MT |
3050 | /* |
3051 | * kvmclock updates which are isolated to a given vcpu, such as | |
3052 | * vcpu->cpu migration, should not allow system_timestamp from | |
3053 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
3054 | * correction applies to one vcpu's system_timestamp but not | |
3055 | * the others. | |
3056 | * | |
3057 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
3058 | * We need to rate-limit these requests though, as they can |
3059 | * considerably slow guests that have a large number of vcpus. | |
3060 | * The time for a remote vcpu to update its kvmclock is bound | |
3061 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
3062 | */ |
3063 | ||
7e44e449 AJ |
3064 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
3065 | ||
3066 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
3067 | { |
3068 | int i; | |
7e44e449 AJ |
3069 | struct delayed_work *dwork = to_delayed_work(work); |
3070 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
3071 | kvmclock_update_work); | |
3072 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
3073 | struct kvm_vcpu *vcpu; |
3074 | ||
3075 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 3076 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
3077 | kvm_vcpu_kick(vcpu); |
3078 | } | |
3079 | } | |
3080 | ||
7e44e449 AJ |
3081 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
3082 | { | |
3083 | struct kvm *kvm = v->kvm; | |
3084 | ||
105b21bb | 3085 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
3086 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
3087 | KVMCLOCK_UPDATE_DELAY); | |
3088 | } | |
3089 | ||
332967a3 AJ |
3090 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
3091 | ||
3092 | static void kvmclock_sync_fn(struct work_struct *work) | |
3093 | { | |
3094 | struct delayed_work *dwork = to_delayed_work(work); | |
3095 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
3096 | kvmclock_sync_work); | |
3097 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
3098 | ||
630994b3 MT |
3099 | if (!kvmclock_periodic_sync) |
3100 | return; | |
3101 | ||
332967a3 AJ |
3102 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
3103 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
3104 | KVMCLOCK_SYNC_PERIOD); | |
3105 | } | |
3106 | ||
191c8137 BP |
3107 | /* |
3108 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
3109 | */ | |
3110 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
3111 | { | |
3112 | /* McStatusWrEn enabled? */ | |
23493d0a | 3113 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
3114 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
3115 | ||
3116 | return false; | |
3117 | } | |
3118 | ||
9ffd986c | 3119 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3120 | { |
890ca9ae HY |
3121 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3122 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
3123 | u32 msr = msr_info->index; |
3124 | u64 data = msr_info->data; | |
890ca9ae | 3125 | |
15c4a640 | 3126 | switch (msr) { |
15c4a640 | 3127 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 3128 | vcpu->arch.mcg_status = data; |
15c4a640 | 3129 | break; |
c7ac679c | 3130 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
3131 | if (!(mcg_cap & MCG_CTL_P) && |
3132 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
3133 | return 1; |
3134 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 3135 | return 1; |
890ca9ae HY |
3136 | vcpu->arch.mcg_ctl = data; |
3137 | break; | |
3138 | default: | |
3139 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3140 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3141 | u32 offset = array_index_nospec( |
3142 | msr - MSR_IA32_MC0_CTL, | |
3143 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3144 | ||
114be429 AP |
3145 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
3146 | * some Linux kernels though clear bit 10 in bank 4 to | |
3147 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
3148 | * this to avoid an uncatched #GP in the guest | |
3149 | */ | |
890ca9ae | 3150 | if ((offset & 0x3) == 0 && |
114be429 | 3151 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 3152 | return -1; |
191c8137 BP |
3153 | |
3154 | /* MCi_STATUS */ | |
9ffd986c | 3155 | if (!msr_info->host_initiated && |
191c8137 BP |
3156 | (offset & 0x3) == 1 && data != 0) { |
3157 | if (!can_set_mci_status(vcpu)) | |
3158 | return -1; | |
3159 | } | |
3160 | ||
890ca9ae HY |
3161 | vcpu->arch.mce_banks[offset] = data; |
3162 | break; | |
3163 | } | |
3164 | return 1; | |
3165 | } | |
3166 | return 0; | |
3167 | } | |
3168 | ||
2635b5c4 VK |
3169 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
3170 | { | |
3171 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
3172 | ||
3173 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
3174 | } | |
3175 | ||
344d9588 GN |
3176 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
3177 | { | |
3178 | gpa_t gpa = data & ~0x3f; | |
3179 | ||
2635b5c4 VK |
3180 | /* Bits 4:5 are reserved, Should be zero */ |
3181 | if (data & 0x30) | |
344d9588 GN |
3182 | return 1; |
3183 | ||
66570e96 OU |
3184 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
3185 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
3186 | return 1; | |
3187 | ||
3188 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
3189 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
3190 | return 1; | |
3191 | ||
9d3c447c | 3192 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 3193 | return data ? 1 : 0; |
9d3c447c | 3194 | |
2635b5c4 | 3195 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 3196 | |
2635b5c4 | 3197 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
3198 | kvm_clear_async_pf_completion_queue(vcpu); |
3199 | kvm_async_pf_hash_reset(vcpu); | |
3200 | return 0; | |
3201 | } | |
3202 | ||
4e335d9e | 3203 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 3204 | sizeof(u64))) |
344d9588 GN |
3205 | return 1; |
3206 | ||
6adba527 | 3207 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 3208 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 3209 | |
344d9588 | 3210 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
3211 | |
3212 | return 0; | |
3213 | } | |
3214 | ||
3215 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
3216 | { | |
3217 | /* Bits 8-63 are reserved */ | |
3218 | if (data >> 8) | |
3219 | return 1; | |
3220 | ||
3221 | if (!lapic_in_kernel(vcpu)) | |
3222 | return 1; | |
3223 | ||
3224 | vcpu->arch.apf.msr_int_val = data; | |
3225 | ||
3226 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
3227 | ||
344d9588 GN |
3228 | return 0; |
3229 | } | |
3230 | ||
12f9a48f GC |
3231 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
3232 | { | |
0b79459b | 3233 | vcpu->arch.pv_time_enabled = false; |
49dedf0d | 3234 | vcpu->arch.time = 0; |
12f9a48f GC |
3235 | } |
3236 | ||
7780938c | 3237 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
3238 | { |
3239 | ++vcpu->stat.tlb_flush; | |
b3646477 | 3240 | static_call(kvm_x86_tlb_flush_all)(vcpu); |
f38a7b75 WL |
3241 | } |
3242 | ||
0baedd79 VK |
3243 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
3244 | { | |
3245 | ++vcpu->stat.tlb_flush; | |
b53e84ee LJ |
3246 | |
3247 | if (!tdp_enabled) { | |
61b05a9f | 3248 | /* |
b53e84ee LJ |
3249 | * A TLB flush on behalf of the guest is equivalent to |
3250 | * INVPCID(all), toggling CR4.PGE, etc., which requires | |
61b05a9f LJ |
3251 | * a forced sync of the shadow page tables. Ensure all the |
3252 | * roots are synced and the guest TLB in hardware is clean. | |
b53e84ee | 3253 | */ |
61b05a9f LJ |
3254 | kvm_mmu_sync_roots(vcpu); |
3255 | kvm_mmu_sync_prev_roots(vcpu); | |
b53e84ee LJ |
3256 | } |
3257 | ||
b3646477 | 3258 | static_call(kvm_x86_tlb_flush_guest)(vcpu); |
0baedd79 VK |
3259 | } |
3260 | ||
c9aaa895 GC |
3261 | static void record_steal_time(struct kvm_vcpu *vcpu) |
3262 | { | |
7e2175eb DW |
3263 | struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; |
3264 | struct kvm_steal_time __user *st; | |
3265 | struct kvm_memslots *slots; | |
3266 | u64 steal; | |
3267 | u32 version; | |
b0431382 | 3268 | |
30b5c851 DW |
3269 | if (kvm_xen_msr_enabled(vcpu->kvm)) { |
3270 | kvm_xen_runstate_set_running(vcpu); | |
3271 | return; | |
3272 | } | |
3273 | ||
c9aaa895 GC |
3274 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
3275 | return; | |
3276 | ||
7e2175eb | 3277 | if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) |
c9aaa895 GC |
3278 | return; |
3279 | ||
7e2175eb DW |
3280 | slots = kvm_memslots(vcpu->kvm); |
3281 | ||
3282 | if (unlikely(slots->generation != ghc->generation || | |
3283 | kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { | |
3284 | gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; | |
3285 | ||
3286 | /* We rely on the fact that it fits in a single page. */ | |
3287 | BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); | |
3288 | ||
3289 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) || | |
3290 | kvm_is_error_hva(ghc->hva) || !ghc->memslot) | |
3291 | return; | |
3292 | } | |
3293 | ||
3294 | st = (struct kvm_steal_time __user *)ghc->hva; | |
3295 | if (!user_access_begin(st, sizeof(*st))) | |
3296 | return; | |
b0431382 | 3297 | |
f38a7b75 WL |
3298 | /* |
3299 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
3300 | * expensive IPIs. | |
3301 | */ | |
66570e96 | 3302 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
7e2175eb DW |
3303 | u8 st_preempted = 0; |
3304 | int err = -EFAULT; | |
3305 | ||
3306 | asm volatile("1: xchgb %0, %2\n" | |
3307 | "xor %1, %1\n" | |
3308 | "2:\n" | |
3309 | _ASM_EXTABLE_UA(1b, 2b) | |
3310 | : "+r" (st_preempted), | |
3311 | "+&r" (err) | |
3312 | : "m" (st->preempted)); | |
3313 | if (err) | |
3314 | goto out; | |
3315 | ||
3316 | user_access_end(); | |
3317 | ||
3318 | vcpu->arch.st.preempted = 0; | |
af3511ff | 3319 | |
66570e96 | 3320 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, |
af3511ff LJ |
3321 | st_preempted & KVM_VCPU_FLUSH_TLB); |
3322 | if (st_preempted & KVM_VCPU_FLUSH_TLB) | |
66570e96 | 3323 | kvm_vcpu_flush_tlb_guest(vcpu); |
7e2175eb DW |
3324 | |
3325 | if (!user_access_begin(st, sizeof(*st))) | |
3326 | goto dirty; | |
1eff0ada | 3327 | } else { |
7e2175eb DW |
3328 | unsafe_put_user(0, &st->preempted, out); |
3329 | vcpu->arch.st.preempted = 0; | |
66570e96 | 3330 | } |
0b9f6c46 | 3331 | |
7e2175eb DW |
3332 | unsafe_get_user(version, &st->version, out); |
3333 | if (version & 1) | |
3334 | version += 1; /* first time write, random junk */ | |
35f3fae1 | 3335 | |
7e2175eb DW |
3336 | version += 1; |
3337 | unsafe_put_user(version, &st->version, out); | |
35f3fae1 WL |
3338 | |
3339 | smp_wmb(); | |
3340 | ||
7e2175eb DW |
3341 | unsafe_get_user(steal, &st->steal, out); |
3342 | steal += current->sched_info.run_delay - | |
c54cdf14 LC |
3343 | vcpu->arch.st.last_steal; |
3344 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
7e2175eb | 3345 | unsafe_put_user(steal, &st->steal, out); |
35f3fae1 | 3346 | |
7e2175eb DW |
3347 | version += 1; |
3348 | unsafe_put_user(version, &st->version, out); | |
c9aaa895 | 3349 | |
7e2175eb DW |
3350 | out: |
3351 | user_access_end(); | |
3352 | dirty: | |
3353 | mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); | |
c9aaa895 GC |
3354 | } |
3355 | ||
8fe8ab46 | 3356 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3357 | { |
5753785f | 3358 | bool pr = false; |
8fe8ab46 WA |
3359 | u32 msr = msr_info->index; |
3360 | u64 data = msr_info->data; | |
5753785f | 3361 | |
1232f8e6 | 3362 | if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) |
23200b7a | 3363 | return kvm_xen_write_hypercall_page(vcpu, data); |
1232f8e6 | 3364 | |
15c4a640 | 3365 | switch (msr) { |
2e32b719 | 3366 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3367 | case MSR_IA32_UCODE_WRITE: |
3368 | case MSR_VM_HSAVE_PA: | |
3369 | case MSR_AMD64_PATCH_LOADER: | |
3370 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3371 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3372 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3373 | break; |
3374 | ||
518e7b94 WL |
3375 | case MSR_IA32_UCODE_REV: |
3376 | if (msr_info->host_initiated) | |
3377 | vcpu->arch.microcode_version = data; | |
3378 | break; | |
0cf9135b SC |
3379 | case MSR_IA32_ARCH_CAPABILITIES: |
3380 | if (!msr_info->host_initiated) | |
3381 | return 1; | |
3382 | vcpu->arch.arch_capabilities = data; | |
3383 | break; | |
d574c539 VK |
3384 | case MSR_IA32_PERF_CAPABILITIES: { |
3385 | struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; | |
3386 | ||
3387 | if (!msr_info->host_initiated) | |
3388 | return 1; | |
3389 | if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) | |
3390 | return 1; | |
3391 | if (data & ~msr_ent.data) | |
3392 | return 1; | |
3393 | ||
3394 | vcpu->arch.perf_capabilities = data; | |
3395 | ||
3396 | return 0; | |
3397 | } | |
15c4a640 | 3398 | case MSR_EFER: |
11988499 | 3399 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3400 | case MSR_K7_HWCR: |
3401 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3402 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3403 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
3404 | |
3405 | /* Handle McStatusWrEn */ | |
3406 | if (data == BIT_ULL(18)) { | |
3407 | vcpu->arch.msr_hwcr = data; | |
3408 | } else if (data != 0) { | |
a737f256 CD |
3409 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
3410 | data); | |
8f1589d9 AP |
3411 | return 1; |
3412 | } | |
15c4a640 | 3413 | break; |
f7c6d140 AP |
3414 | case MSR_FAM10H_MMIO_CONF_BASE: |
3415 | if (data != 0) { | |
a737f256 CD |
3416 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
3417 | "0x%llx\n", data); | |
f7c6d140 AP |
3418 | return 1; |
3419 | } | |
15c4a640 | 3420 | break; |
9ba075a6 | 3421 | case 0x200 ... 0x2ff: |
ff53604b | 3422 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3423 | case MSR_IA32_APICBASE: |
58cb628d | 3424 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3425 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3426 | return kvm_x2apic_msr_write(vcpu, msr, data); |
09141ec0 | 3427 | case MSR_IA32_TSC_DEADLINE: |
a3e06bbe LJ |
3428 | kvm_set_lapic_tscdeadline_msr(vcpu, data); |
3429 | break; | |
ba904635 | 3430 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3431 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3432 | if (!msr_info->host_initiated) { |
d913b904 | 3433 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3434 | adjust_tsc_offset_guest(vcpu, adj); |
d9130a2d ZD |
3435 | /* Before back to guest, tsc_timestamp must be adjusted |
3436 | * as well, otherwise guest's percpu pvclock time could jump. | |
3437 | */ | |
3438 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
ba904635 WA |
3439 | } |
3440 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3441 | } | |
3442 | break; | |
15c4a640 | 3443 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
3444 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
3445 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
3446 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
3447 | return 1; | |
3448 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3449 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3450 | } else { |
3451 | vcpu->arch.ia32_misc_enable_msr = data; | |
3452 | } | |
15c4a640 | 3453 | break; |
64d60670 PB |
3454 | case MSR_IA32_SMBASE: |
3455 | if (!msr_info->host_initiated) | |
3456 | return 1; | |
3457 | vcpu->arch.smbase = data; | |
3458 | break; | |
73f624f4 PB |
3459 | case MSR_IA32_POWER_CTL: |
3460 | vcpu->arch.msr_ia32_power_ctl = data; | |
3461 | break; | |
dd259935 | 3462 | case MSR_IA32_TSC: |
0c899c25 PB |
3463 | if (msr_info->host_initiated) { |
3464 | kvm_synchronize_tsc(vcpu, data); | |
3465 | } else { | |
9b399dfd | 3466 | u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; |
0c899c25 PB |
3467 | adjust_tsc_offset_guest(vcpu, adj); |
3468 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3469 | } | |
dd259935 | 3470 | break; |
864e2ab2 AL |
3471 | case MSR_IA32_XSS: |
3472 | if (!msr_info->host_initiated && | |
3473 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3474 | return 1; | |
3475 | /* | |
a1bead2a SC |
3476 | * KVM supports exposing PT to the guest, but does not support |
3477 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3478 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3479 | */ |
408e9a31 | 3480 | if (data & ~supported_xss) |
864e2ab2 AL |
3481 | return 1; |
3482 | vcpu->arch.ia32_xss = data; | |
3483 | break; | |
52797bf9 LA |
3484 | case MSR_SMI_COUNT: |
3485 | if (!msr_info->host_initiated) | |
3486 | return 1; | |
3487 | vcpu->arch.smi_count = data; | |
3488 | break; | |
11c6bffa | 3489 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3490 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3491 | return 1; | |
3492 | ||
629b5348 JM |
3493 | vcpu->kvm->arch.wall_clock = data; |
3494 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
66570e96 | 3495 | break; |
18068523 | 3496 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3497 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3498 | return 1; | |
3499 | ||
629b5348 JM |
3500 | vcpu->kvm->arch.wall_clock = data; |
3501 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
18068523 | 3502 | break; |
11c6bffa | 3503 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3504 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3505 | return 1; | |
3506 | ||
5b9bb0eb OU |
3507 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3508 | break; | |
3509 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3510 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3511 | return 1; | |
3512 | ||
3513 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3514 | break; |
344d9588 | 3515 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3516 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3517 | return 1; | |
3518 | ||
344d9588 GN |
3519 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3520 | return 1; | |
3521 | break; | |
2635b5c4 | 3522 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3523 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3524 | return 1; | |
3525 | ||
2635b5c4 VK |
3526 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3527 | return 1; | |
3528 | break; | |
557a961a | 3529 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 3530 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
66570e96 | 3531 | return 1; |
557a961a VK |
3532 | if (data & 0x1) { |
3533 | vcpu->arch.apf.pageready_pending = false; | |
3534 | kvm_check_async_pf_completion(vcpu); | |
3535 | } | |
3536 | break; | |
c9aaa895 | 3537 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3538 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3539 | return 1; | |
c9aaa895 GC |
3540 | |
3541 | if (unlikely(!sched_info_on())) | |
3542 | return 1; | |
3543 | ||
3544 | if (data & KVM_STEAL_RESERVED_MASK) | |
3545 | return 1; | |
3546 | ||
c9aaa895 GC |
3547 | vcpu->arch.st.msr_val = data; |
3548 | ||
3549 | if (!(data & KVM_MSR_ENABLED)) | |
3550 | break; | |
3551 | ||
c9aaa895 GC |
3552 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3553 | ||
3554 | break; | |
ae7a2a3f | 3555 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
3556 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3557 | return 1; | |
3558 | ||
77c3323f | 3559 | if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3560 | return 1; |
3561 | break; | |
c9aaa895 | 3562 | |
2d5ba19b | 3563 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
3564 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3565 | return 1; | |
3566 | ||
2d5ba19b MT |
3567 | /* only enable bit supported */ |
3568 | if (data & (-1ULL << 1)) | |
3569 | return 1; | |
3570 | ||
3571 | vcpu->arch.msr_kvm_poll_control = data; | |
3572 | break; | |
3573 | ||
890ca9ae HY |
3574 | case MSR_IA32_MCG_CTL: |
3575 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3576 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3577 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3578 | |
6912ac32 WH |
3579 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3580 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
df561f66 GS |
3581 | pr = true; |
3582 | fallthrough; | |
6912ac32 WH |
3583 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3584 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3585 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3586 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
3587 | |
3588 | if (pr || data != 0) | |
a737f256 CD |
3589 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
3590 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 3591 | break; |
84e0cefa JS |
3592 | case MSR_K7_CLK_CTL: |
3593 | /* | |
3594 | * Ignore all writes to this no longer documented MSR. | |
3595 | * Writes are only relevant for old K7 processors, | |
3596 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3597 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3598 | * affected processor models on the command line, hence |
3599 | * the need to ignore the workaround. | |
3600 | */ | |
3601 | break; | |
55cd8e5a | 3602 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3603 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3604 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3605 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3606 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3607 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3608 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3609 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3610 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
3611 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3612 | msr_info->host_initiated); | |
91c9c3ed | 3613 | case MSR_IA32_BBL_CR_CTL3: |
3614 | /* Drop writes to this legacy MSR -- see rdmsr | |
3615 | * counterpart for further detail. | |
3616 | */ | |
fab0aa3b EM |
3617 | if (report_ignored_msrs) |
3618 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
3619 | msr, data); | |
91c9c3ed | 3620 | break; |
2b036c6b | 3621 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3622 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3623 | return 1; |
3624 | vcpu->arch.osvw.length = data; | |
3625 | break; | |
3626 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3627 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3628 | return 1; |
3629 | vcpu->arch.osvw.status = data; | |
3630 | break; | |
db2336a8 KH |
3631 | case MSR_PLATFORM_INFO: |
3632 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3633 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3634 | cpuid_fault_enabled(vcpu))) | |
3635 | return 1; | |
3636 | vcpu->arch.msr_platform_info = data; | |
3637 | break; | |
3638 | case MSR_MISC_FEATURES_ENABLES: | |
3639 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3640 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3641 | !supports_cpuid_fault(vcpu))) | |
3642 | return 1; | |
3643 | vcpu->arch.msr_misc_features_enables = data; | |
3644 | break; | |
15c4a640 | 3645 | default: |
c6702c9d | 3646 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3647 | return kvm_pmu_set_msr(vcpu, msr_info); |
6abe9c13 | 3648 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3649 | } |
3650 | return 0; | |
3651 | } | |
3652 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
3653 | ||
44883f01 | 3654 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
3655 | { |
3656 | u64 data; | |
890ca9ae HY |
3657 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3658 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
3659 | |
3660 | switch (msr) { | |
15c4a640 CO |
3661 | case MSR_IA32_P5_MC_ADDR: |
3662 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
3663 | data = 0; |
3664 | break; | |
15c4a640 | 3665 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
3666 | data = vcpu->arch.mcg_cap; |
3667 | break; | |
c7ac679c | 3668 | case MSR_IA32_MCG_CTL: |
44883f01 | 3669 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
3670 | return 1; |
3671 | data = vcpu->arch.mcg_ctl; | |
3672 | break; | |
3673 | case MSR_IA32_MCG_STATUS: | |
3674 | data = vcpu->arch.mcg_status; | |
3675 | break; | |
3676 | default: | |
3677 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3678 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3679 | u32 offset = array_index_nospec( |
3680 | msr - MSR_IA32_MC0_CTL, | |
3681 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3682 | ||
890ca9ae HY |
3683 | data = vcpu->arch.mce_banks[offset]; |
3684 | break; | |
3685 | } | |
3686 | return 1; | |
3687 | } | |
3688 | *pdata = data; | |
3689 | return 0; | |
3690 | } | |
3691 | ||
609e36d3 | 3692 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3693 | { |
609e36d3 | 3694 | switch (msr_info->index) { |
890ca9ae | 3695 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3696 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3697 | case MSR_IA32_LASTBRANCHFROMIP: |
3698 | case MSR_IA32_LASTBRANCHTOIP: | |
3699 | case MSR_IA32_LASTINTFROMIP: | |
3700 | case MSR_IA32_LASTINTTOIP: | |
059e5c32 | 3701 | case MSR_AMD64_SYSCFG: |
3afb1121 PB |
3702 | case MSR_K8_TSEG_ADDR: |
3703 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3704 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3705 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3706 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3707 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3708 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3709 | case MSR_IA32_PERF_CTL: |
405a353a | 3710 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3711 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
3712 | /* |
3713 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
3714 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
3715 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
3716 | * so for existing CPU-specific MSRs. | |
3717 | */ | |
3718 | case MSR_RAPL_POWER_UNIT: | |
3719 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
3720 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
3721 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
3722 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 3723 | msr_info->data = 0; |
15c4a640 | 3724 | break; |
c51eb52b | 3725 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
c28fa560 VK |
3726 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
3727 | return kvm_pmu_get_msr(vcpu, msr_info); | |
3728 | if (!msr_info->host_initiated) | |
3729 | return 1; | |
3730 | msr_info->data = 0; | |
3731 | break; | |
6912ac32 WH |
3732 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3733 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3734 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3735 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3736 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3737 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 3738 | msr_info->data = 0; |
5753785f | 3739 | break; |
742bc670 | 3740 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3741 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3742 | break; |
0cf9135b SC |
3743 | case MSR_IA32_ARCH_CAPABILITIES: |
3744 | if (!msr_info->host_initiated && | |
3745 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3746 | return 1; | |
3747 | msr_info->data = vcpu->arch.arch_capabilities; | |
3748 | break; | |
d574c539 VK |
3749 | case MSR_IA32_PERF_CAPABILITIES: |
3750 | if (!msr_info->host_initiated && | |
3751 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
3752 | return 1; | |
3753 | msr_info->data = vcpu->arch.perf_capabilities; | |
3754 | break; | |
73f624f4 PB |
3755 | case MSR_IA32_POWER_CTL: |
3756 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3757 | break; | |
cc5b54dd ML |
3758 | case MSR_IA32_TSC: { |
3759 | /* | |
3760 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
3761 | * even when not intercepted. AMD manual doesn't explicitly | |
3762 | * state this but appears to behave the same. | |
3763 | * | |
ee6fa053 | 3764 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 3765 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 3766 | * behavior for migration. |
cc5b54dd | 3767 | */ |
fe3eb504 | 3768 | u64 offset, ratio; |
cc5b54dd | 3769 | |
fe3eb504 IS |
3770 | if (msr_info->host_initiated) { |
3771 | offset = vcpu->arch.l1_tsc_offset; | |
3772 | ratio = vcpu->arch.l1_tsc_scaling_ratio; | |
3773 | } else { | |
3774 | offset = vcpu->arch.tsc_offset; | |
3775 | ratio = vcpu->arch.tsc_scaling_ratio; | |
3776 | } | |
3777 | ||
3778 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc(), ratio) + offset; | |
dd259935 | 3779 | break; |
cc5b54dd | 3780 | } |
9ba075a6 | 3781 | case MSR_MTRRcap: |
9ba075a6 | 3782 | case 0x200 ... 0x2ff: |
ff53604b | 3783 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 3784 | case 0xcd: /* fsb frequency */ |
609e36d3 | 3785 | msr_info->data = 3; |
15c4a640 | 3786 | break; |
7b914098 JS |
3787 | /* |
3788 | * MSR_EBC_FREQUENCY_ID | |
3789 | * Conservative value valid for even the basic CPU models. | |
3790 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
3791 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
3792 | * and 266MHz for model 3, or 4. Set Core Clock | |
3793 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
3794 | * 31:24) even though these are only valid for CPU | |
3795 | * models > 2, however guests may end up dividing or | |
3796 | * multiplying by zero otherwise. | |
3797 | */ | |
3798 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 3799 | msr_info->data = 1 << 24; |
7b914098 | 3800 | break; |
15c4a640 | 3801 | case MSR_IA32_APICBASE: |
609e36d3 | 3802 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 3803 | break; |
bf10bd0b | 3804 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 3805 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
09141ec0 | 3806 | case MSR_IA32_TSC_DEADLINE: |
609e36d3 | 3807 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 3808 | break; |
ba904635 | 3809 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 3810 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 3811 | break; |
15c4a640 | 3812 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 3813 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 3814 | break; |
64d60670 PB |
3815 | case MSR_IA32_SMBASE: |
3816 | if (!msr_info->host_initiated) | |
3817 | return 1; | |
3818 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 3819 | break; |
52797bf9 LA |
3820 | case MSR_SMI_COUNT: |
3821 | msr_info->data = vcpu->arch.smi_count; | |
3822 | break; | |
847f0ad8 AG |
3823 | case MSR_IA32_PERF_STATUS: |
3824 | /* TSC increment by tick */ | |
609e36d3 | 3825 | msr_info->data = 1000ULL; |
847f0ad8 | 3826 | /* CPU multiplier */ |
b0996ae4 | 3827 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 3828 | break; |
15c4a640 | 3829 | case MSR_EFER: |
609e36d3 | 3830 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 3831 | break; |
18068523 | 3832 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
3833 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3834 | return 1; | |
3835 | ||
3836 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
3837 | break; | |
11c6bffa | 3838 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
3839 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3840 | return 1; | |
3841 | ||
609e36d3 | 3842 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
3843 | break; |
3844 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
3845 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3846 | return 1; | |
3847 | ||
3848 | msr_info->data = vcpu->arch.time; | |
3849 | break; | |
11c6bffa | 3850 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
3851 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3852 | return 1; | |
3853 | ||
609e36d3 | 3854 | msr_info->data = vcpu->arch.time; |
18068523 | 3855 | break; |
344d9588 | 3856 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
3857 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3858 | return 1; | |
3859 | ||
2635b5c4 VK |
3860 | msr_info->data = vcpu->arch.apf.msr_en_val; |
3861 | break; | |
3862 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
3863 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3864 | return 1; | |
3865 | ||
2635b5c4 | 3866 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 3867 | break; |
557a961a | 3868 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 3869 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
1930e5dd OU |
3870 | return 1; |
3871 | ||
557a961a VK |
3872 | msr_info->data = 0; |
3873 | break; | |
c9aaa895 | 3874 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
3875 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3876 | return 1; | |
3877 | ||
609e36d3 | 3878 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3879 | break; |
1d92128f | 3880 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
3881 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3882 | return 1; | |
3883 | ||
609e36d3 | 3884 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3885 | break; |
2d5ba19b | 3886 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
3887 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3888 | return 1; | |
3889 | ||
2d5ba19b MT |
3890 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
3891 | break; | |
890ca9ae HY |
3892 | case MSR_IA32_P5_MC_ADDR: |
3893 | case MSR_IA32_P5_MC_TYPE: | |
3894 | case MSR_IA32_MCG_CAP: | |
3895 | case MSR_IA32_MCG_CTL: | |
3896 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3897 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3898 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3899 | msr_info->host_initiated); | |
864e2ab2 AL |
3900 | case MSR_IA32_XSS: |
3901 | if (!msr_info->host_initiated && | |
3902 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3903 | return 1; | |
3904 | msr_info->data = vcpu->arch.ia32_xss; | |
3905 | break; | |
84e0cefa JS |
3906 | case MSR_K7_CLK_CTL: |
3907 | /* | |
3908 | * Provide expected ramp-up count for K7. All other | |
3909 | * are set to zero, indicating minimum divisors for | |
3910 | * every field. | |
3911 | * | |
3912 | * This prevents guest kernels on AMD host with CPU | |
3913 | * type 6, model 8 and higher from exploding due to | |
3914 | * the rdmsr failing. | |
3915 | */ | |
609e36d3 | 3916 | msr_info->data = 0x20000000; |
84e0cefa | 3917 | break; |
55cd8e5a | 3918 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3919 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3920 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3921 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3922 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3923 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3924 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3925 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3926 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3927 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3928 | msr_info->index, &msr_info->data, |
3929 | msr_info->host_initiated); | |
91c9c3ed | 3930 | case MSR_IA32_BBL_CR_CTL3: |
3931 | /* This legacy MSR exists but isn't fully documented in current | |
3932 | * silicon. It is however accessed by winxp in very narrow | |
3933 | * scenarios where it sets bit #19, itself documented as | |
3934 | * a "reserved" bit. Best effort attempt to source coherent | |
3935 | * read data here should the balance of the register be | |
3936 | * interpreted by the guest: | |
3937 | * | |
3938 | * L2 cache control register 3: 64GB range, 256KB size, | |
3939 | * enabled, latency 0x1, configured | |
3940 | */ | |
609e36d3 | 3941 | msr_info->data = 0xbe702111; |
91c9c3ed | 3942 | break; |
2b036c6b | 3943 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3944 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3945 | return 1; |
609e36d3 | 3946 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3947 | break; |
3948 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3949 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3950 | return 1; |
609e36d3 | 3951 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3952 | break; |
db2336a8 | 3953 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3954 | if (!msr_info->host_initiated && |
3955 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3956 | return 1; | |
db2336a8 KH |
3957 | msr_info->data = vcpu->arch.msr_platform_info; |
3958 | break; | |
3959 | case MSR_MISC_FEATURES_ENABLES: | |
3960 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3961 | break; | |
191c8137 BP |
3962 | case MSR_K7_HWCR: |
3963 | msr_info->data = vcpu->arch.msr_hwcr; | |
3964 | break; | |
15c4a640 | 3965 | default: |
c6702c9d | 3966 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3967 | return kvm_pmu_get_msr(vcpu, msr_info); |
6abe9c13 | 3968 | return KVM_MSR_RET_INVALID; |
15c4a640 | 3969 | } |
15c4a640 CO |
3970 | return 0; |
3971 | } | |
3972 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3973 | ||
313a3dc7 CO |
3974 | /* |
3975 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3976 | * | |
3977 | * @return number of msrs set successfully. | |
3978 | */ | |
3979 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3980 | struct kvm_msr_entry *entries, | |
3981 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3982 | unsigned index, u64 *data)) | |
3983 | { | |
801e459a | 3984 | int i; |
313a3dc7 | 3985 | |
313a3dc7 CO |
3986 | for (i = 0; i < msrs->nmsrs; ++i) |
3987 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3988 | break; | |
3989 | ||
313a3dc7 CO |
3990 | return i; |
3991 | } | |
3992 | ||
3993 | /* | |
3994 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3995 | * | |
3996 | * @return number of msrs set successfully. | |
3997 | */ | |
3998 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3999 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
4000 | unsigned index, u64 *data), | |
4001 | int writeback) | |
4002 | { | |
4003 | struct kvm_msrs msrs; | |
4004 | struct kvm_msr_entry *entries; | |
4005 | int r, n; | |
4006 | unsigned size; | |
4007 | ||
4008 | r = -EFAULT; | |
0e96f31e | 4009 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
4010 | goto out; |
4011 | ||
4012 | r = -E2BIG; | |
4013 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
4014 | goto out; | |
4015 | ||
313a3dc7 | 4016 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
4017 | entries = memdup_user(user_msrs->entries, size); |
4018 | if (IS_ERR(entries)) { | |
4019 | r = PTR_ERR(entries); | |
313a3dc7 | 4020 | goto out; |
ff5c2c03 | 4021 | } |
313a3dc7 CO |
4022 | |
4023 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
4024 | if (r < 0) | |
4025 | goto out_free; | |
4026 | ||
4027 | r = -EFAULT; | |
4028 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
4029 | goto out_free; | |
4030 | ||
4031 | r = n; | |
4032 | ||
4033 | out_free: | |
7a73c028 | 4034 | kfree(entries); |
313a3dc7 CO |
4035 | out: |
4036 | return r; | |
4037 | } | |
4038 | ||
4d5422ce WL |
4039 | static inline bool kvm_can_mwait_in_guest(void) |
4040 | { | |
4041 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
4042 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
4043 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
4044 | } |
4045 | ||
c21d54f0 VK |
4046 | static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, |
4047 | struct kvm_cpuid2 __user *cpuid_arg) | |
4048 | { | |
4049 | struct kvm_cpuid2 cpuid; | |
4050 | int r; | |
4051 | ||
4052 | r = -EFAULT; | |
4053 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
4054 | return r; | |
4055 | ||
4056 | r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
4057 | if (r) | |
4058 | return r; | |
4059 | ||
4060 | r = -EFAULT; | |
4061 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
4062 | return r; | |
4063 | ||
4064 | return 0; | |
4065 | } | |
4066 | ||
784aa3d7 | 4067 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 4068 | { |
4d5422ce | 4069 | int r = 0; |
018d00d2 ZX |
4070 | |
4071 | switch (ext) { | |
4072 | case KVM_CAP_IRQCHIP: | |
4073 | case KVM_CAP_HLT: | |
4074 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 4075 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 4076 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 4077 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 4078 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 4079 | case KVM_CAP_PIT: |
a28e4f5a | 4080 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 4081 | case KVM_CAP_MP_STATE: |
ed848624 | 4082 | case KVM_CAP_SYNC_MMU: |
a355c85c | 4083 | case KVM_CAP_USER_NMI: |
52d939a0 | 4084 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 4085 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 4086 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 4087 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 4088 | case KVM_CAP_PIT2: |
e9f42757 | 4089 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 4090 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
3cfc3092 | 4091 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 4092 | case KVM_CAP_HYPERV: |
10388a07 | 4093 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 4094 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 4095 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 4096 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 4097 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 4098 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 4099 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 4100 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 4101 | case KVM_CAP_HYPERV_CPUID: |
644f7067 | 4102 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
c21d54f0 | 4103 | case KVM_CAP_SYS_HYPERV_CPUID: |
ab9f4ecb | 4104 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 4105 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 4106 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 4107 | case KVM_CAP_XSAVE: |
344d9588 | 4108 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 4109 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 4110 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 4111 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 4112 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 4113 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 4114 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 4115 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 4116 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 4117 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 4118 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 4119 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 4120 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 4121 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 4122 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 4123 | case KVM_CAP_EXCEPTION_PAYLOAD: |
b9b2782c | 4124 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 4125 | case KVM_CAP_LAST_CPU: |
1ae09954 | 4126 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 4127 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 4128 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
fe7e9488 SC |
4129 | #ifdef CONFIG_X86_SGX_KVM |
4130 | case KVM_CAP_SGX_ATTRIBUTE: | |
4131 | #endif | |
54526d1f | 4132 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
6dba9403 | 4133 | case KVM_CAP_SREGS2: |
19238e75 | 4134 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
828ca896 | 4135 | case KVM_CAP_VCPU_ATTRIBUTES: |
018d00d2 ZX |
4136 | r = 1; |
4137 | break; | |
0dbb1123 AK |
4138 | case KVM_CAP_EXIT_HYPERCALL: |
4139 | r = KVM_EXIT_HYPERCALL_VALID_MASK; | |
4140 | break; | |
7e582ccb ML |
4141 | case KVM_CAP_SET_GUEST_DEBUG2: |
4142 | return KVM_GUESTDBG_VALID_MASK; | |
b59b153d | 4143 | #ifdef CONFIG_KVM_XEN |
23200b7a JM |
4144 | case KVM_CAP_XEN_HVM: |
4145 | r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | | |
8d4e7e80 DW |
4146 | KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | |
4147 | KVM_XEN_HVM_CONFIG_SHARED_INFO; | |
30b5c851 DW |
4148 | if (sched_info_on()) |
4149 | r |= KVM_XEN_HVM_CONFIG_RUNSTATE; | |
23200b7a | 4150 | break; |
b59b153d | 4151 | #endif |
01643c51 KH |
4152 | case KVM_CAP_SYNC_REGS: |
4153 | r = KVM_SYNC_X86_VALID_FIELDS; | |
4154 | break; | |
e3fd9a93 | 4155 | case KVM_CAP_ADJUST_CLOCK: |
c68dc1b5 | 4156 | r = KVM_CLOCK_VALID_FLAGS; |
e3fd9a93 | 4157 | break; |
4d5422ce | 4158 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
4159 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
4160 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
4161 | if(kvm_can_mwait_in_guest()) |
4162 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 4163 | break; |
6d396b55 PB |
4164 | case KVM_CAP_X86_SMM: |
4165 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
4166 | * and SMM handlers might indeed rely on 4G segment limits, | |
4167 | * so do not report SMM to be available if real mode is | |
4168 | * emulated via vm86 mode. Still, do not go to great lengths | |
4169 | * to avoid userspace's usage of the feature, because it is a | |
4170 | * fringe case that is not enabled except via specific settings | |
4171 | * of the module parameters. | |
4172 | */ | |
b3646477 | 4173 | r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); |
6d396b55 | 4174 | break; |
774ead3a | 4175 | case KVM_CAP_VAPIC: |
b3646477 | 4176 | r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); |
774ead3a | 4177 | break; |
f725230a | 4178 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
4179 | r = KVM_SOFT_MAX_VCPUS; |
4180 | break; | |
4181 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
4182 | r = KVM_MAX_VCPUS; |
4183 | break; | |
a86cb413 | 4184 | case KVM_CAP_MAX_VCPU_ID: |
a1c42dde | 4185 | r = KVM_MAX_VCPU_IDS; |
a86cb413 | 4186 | break; |
a68a6a72 MT |
4187 | case KVM_CAP_PV_MMU: /* obsolete */ |
4188 | r = 0; | |
2f333bcb | 4189 | break; |
890ca9ae HY |
4190 | case KVM_CAP_MCE: |
4191 | r = KVM_MAX_MCE_BANKS; | |
4192 | break; | |
2d5b5a66 | 4193 | case KVM_CAP_XCRS: |
d366bf7e | 4194 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 4195 | break; |
92a1f12d JR |
4196 | case KVM_CAP_TSC_CONTROL: |
4197 | r = kvm_has_tsc_control; | |
4198 | break; | |
37131313 RK |
4199 | case KVM_CAP_X2APIC_API: |
4200 | r = KVM_X2APIC_API_VALID_FLAGS; | |
4201 | break; | |
8fcc4b59 | 4202 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
4203 | r = kvm_x86_ops.nested_ops->get_state ? |
4204 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 4205 | break; |
344c6c80 | 4206 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4207 | r = kvm_x86_ops.enable_direct_tlbflush != NULL; |
5a0165f6 VK |
4208 | break; |
4209 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 4210 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 4211 | break; |
3edd6839 MG |
4212 | case KVM_CAP_SMALLER_MAXPHYADDR: |
4213 | r = (int) allow_smaller_maxphyaddr; | |
4214 | break; | |
004a0124 AJ |
4215 | case KVM_CAP_STEAL_TIME: |
4216 | r = sched_info_on(); | |
4217 | break; | |
fe6b6bc8 CQ |
4218 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
4219 | if (kvm_has_bus_lock_exit) | |
4220 | r = KVM_BUS_LOCK_DETECTION_OFF | | |
4221 | KVM_BUS_LOCK_DETECTION_EXIT; | |
4222 | else | |
4223 | r = 0; | |
4224 | break; | |
018d00d2 | 4225 | default: |
018d00d2 ZX |
4226 | break; |
4227 | } | |
4228 | return r; | |
4229 | ||
4230 | } | |
4231 | ||
043405e1 CO |
4232 | long kvm_arch_dev_ioctl(struct file *filp, |
4233 | unsigned int ioctl, unsigned long arg) | |
4234 | { | |
4235 | void __user *argp = (void __user *)arg; | |
4236 | long r; | |
4237 | ||
4238 | switch (ioctl) { | |
4239 | case KVM_GET_MSR_INDEX_LIST: { | |
4240 | struct kvm_msr_list __user *user_msr_list = argp; | |
4241 | struct kvm_msr_list msr_list; | |
4242 | unsigned n; | |
4243 | ||
4244 | r = -EFAULT; | |
0e96f31e | 4245 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
4246 | goto out; |
4247 | n = msr_list.nmsrs; | |
62ef68bb | 4248 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 4249 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
4250 | goto out; |
4251 | r = -E2BIG; | |
e125e7b6 | 4252 | if (n < msr_list.nmsrs) |
043405e1 CO |
4253 | goto out; |
4254 | r = -EFAULT; | |
4255 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
4256 | num_msrs_to_save * sizeof(u32))) | |
4257 | goto out; | |
e125e7b6 | 4258 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 4259 | &emulated_msrs, |
62ef68bb | 4260 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
4261 | goto out; |
4262 | r = 0; | |
4263 | break; | |
4264 | } | |
9c15bb1d BP |
4265 | case KVM_GET_SUPPORTED_CPUID: |
4266 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
4267 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
4268 | struct kvm_cpuid2 cpuid; | |
4269 | ||
4270 | r = -EFAULT; | |
0e96f31e | 4271 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 4272 | goto out; |
9c15bb1d BP |
4273 | |
4274 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
4275 | ioctl); | |
674eea0f AK |
4276 | if (r) |
4277 | goto out; | |
4278 | ||
4279 | r = -EFAULT; | |
0e96f31e | 4280 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
4281 | goto out; |
4282 | r = 0; | |
4283 | break; | |
4284 | } | |
cf6c26ec | 4285 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 4286 | r = -EFAULT; |
c45dcc71 AR |
4287 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
4288 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
4289 | goto out; |
4290 | r = 0; | |
4291 | break; | |
801e459a TL |
4292 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
4293 | struct kvm_msr_list __user *user_msr_list = argp; | |
4294 | struct kvm_msr_list msr_list; | |
4295 | unsigned int n; | |
4296 | ||
4297 | r = -EFAULT; | |
4298 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
4299 | goto out; | |
4300 | n = msr_list.nmsrs; | |
4301 | msr_list.nmsrs = num_msr_based_features; | |
4302 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
4303 | goto out; | |
4304 | r = -E2BIG; | |
4305 | if (n < msr_list.nmsrs) | |
4306 | goto out; | |
4307 | r = -EFAULT; | |
4308 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
4309 | num_msr_based_features * sizeof(u32))) | |
4310 | goto out; | |
4311 | r = 0; | |
4312 | break; | |
4313 | } | |
4314 | case KVM_GET_MSRS: | |
4315 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
4316 | break; | |
c21d54f0 VK |
4317 | case KVM_GET_SUPPORTED_HV_CPUID: |
4318 | r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); | |
4319 | break; | |
043405e1 CO |
4320 | default: |
4321 | r = -EINVAL; | |
cf6c26ec | 4322 | break; |
043405e1 CO |
4323 | } |
4324 | out: | |
4325 | return r; | |
4326 | } | |
4327 | ||
f5f48ee1 SY |
4328 | static void wbinvd_ipi(void *garbage) |
4329 | { | |
4330 | wbinvd(); | |
4331 | } | |
4332 | ||
4333 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4334 | { | |
e0f0bbc5 | 4335 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
4336 | } |
4337 | ||
313a3dc7 CO |
4338 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
4339 | { | |
f5f48ee1 SY |
4340 | /* Address WBINVD may be executed by guest */ |
4341 | if (need_emulate_wbinvd(vcpu)) { | |
b3646477 | 4342 | if (static_call(kvm_x86_has_wbinvd_exit)()) |
f5f48ee1 SY |
4343 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
4344 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
4345 | smp_call_function_single(vcpu->cpu, | |
4346 | wbinvd_ipi, NULL, 1); | |
4347 | } | |
4348 | ||
b3646477 | 4349 | static_call(kvm_x86_vcpu_load)(vcpu, cpu); |
8f6055cb | 4350 | |
37486135 BM |
4351 | /* Save host pkru register if supported */ |
4352 | vcpu->arch.host_pkru = read_pkru(); | |
4353 | ||
0dd6a6ed ZA |
4354 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
4355 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
4356 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
4357 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 4358 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 4359 | } |
8f6055cb | 4360 | |
b0c39dc6 | 4361 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 4362 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 4363 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
4364 | if (tsc_delta < 0) |
4365 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 4366 | |
b0c39dc6 | 4367 | if (kvm_check_tsc_unstable()) { |
9b399dfd | 4368 | u64 offset = kvm_compute_l1_tsc_offset(vcpu, |
b183aa58 | 4369 | vcpu->arch.last_guest_tsc); |
a545ab6a | 4370 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 4371 | vcpu->arch.tsc_catchup = 1; |
c285545f | 4372 | } |
a749e247 PB |
4373 | |
4374 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
4375 | kvm_lapic_restart_hv_timer(vcpu); | |
4376 | ||
d98d07ca MT |
4377 | /* |
4378 | * On a host with synchronized TSC, there is no need to update | |
4379 | * kvmclock on vcpu->cpu migration | |
4380 | */ | |
4381 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 4382 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 4383 | if (vcpu->cpu != cpu) |
1bd2009e | 4384 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 4385 | vcpu->cpu = cpu; |
6b7d7e76 | 4386 | } |
c9aaa895 | 4387 | |
c9aaa895 | 4388 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
4389 | } |
4390 | ||
0b9f6c46 PX |
4391 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
4392 | { | |
7e2175eb DW |
4393 | struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; |
4394 | struct kvm_steal_time __user *st; | |
4395 | struct kvm_memslots *slots; | |
4396 | static const u8 preempted = KVM_VCPU_PREEMPTED; | |
b0431382 | 4397 | |
0b9f6c46 PX |
4398 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
4399 | return; | |
4400 | ||
a6bd811f | 4401 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
4402 | return; |
4403 | ||
7e2175eb DW |
4404 | /* This happens on process exit */ |
4405 | if (unlikely(current->mm != vcpu->kvm->mm)) | |
9c1a0744 | 4406 | return; |
b0431382 | 4407 | |
7e2175eb DW |
4408 | slots = kvm_memslots(vcpu->kvm); |
4409 | ||
4410 | if (unlikely(slots->generation != ghc->generation || | |
4411 | kvm_is_error_hva(ghc->hva) || !ghc->memslot)) | |
4412 | return; | |
0b9f6c46 | 4413 | |
7e2175eb DW |
4414 | st = (struct kvm_steal_time __user *)ghc->hva; |
4415 | BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); | |
0b9f6c46 | 4416 | |
7e2175eb DW |
4417 | if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) |
4418 | vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; | |
4419 | ||
4420 | mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); | |
0b9f6c46 PX |
4421 | } |
4422 | ||
313a3dc7 CO |
4423 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
4424 | { | |
9c1a0744 WL |
4425 | int idx; |
4426 | ||
f1c6366e | 4427 | if (vcpu->preempted && !vcpu->arch.guest_state_protected) |
b3646477 | 4428 | vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); |
de63ad4c | 4429 | |
9c1a0744 WL |
4430 | /* |
4431 | * Take the srcu lock as memslots will be accessed to check the gfn | |
4432 | * cache generation against the memslots generation. | |
4433 | */ | |
4434 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
30b5c851 DW |
4435 | if (kvm_xen_msr_enabled(vcpu->kvm)) |
4436 | kvm_xen_runstate_set_preempted(vcpu); | |
4437 | else | |
4438 | kvm_steal_time_set_preempted(vcpu); | |
9c1a0744 | 4439 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
30b5c851 | 4440 | |
b3646477 | 4441 | static_call(kvm_x86_vcpu_put)(vcpu); |
4ea1636b | 4442 | vcpu->arch.last_host_tsc = rdtsc(); |
313a3dc7 CO |
4443 | } |
4444 | ||
313a3dc7 CO |
4445 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
4446 | struct kvm_lapic_state *s) | |
4447 | { | |
fa59cc00 | 4448 | if (vcpu->arch.apicv_active) |
b3646477 | 4449 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
d62caabb | 4450 | |
a92e2543 | 4451 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
4452 | } |
4453 | ||
4454 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
4455 | struct kvm_lapic_state *s) | |
4456 | { | |
a92e2543 RK |
4457 | int r; |
4458 | ||
4459 | r = kvm_apic_set_state(vcpu, s); | |
4460 | if (r) | |
4461 | return r; | |
cb142eb7 | 4462 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
4463 | |
4464 | return 0; | |
4465 | } | |
4466 | ||
127a457a MG |
4467 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
4468 | { | |
71cc849b PB |
4469 | /* |
4470 | * We can accept userspace's request for interrupt injection | |
4471 | * as long as we have a place to store the interrupt number. | |
4472 | * The actual injection will happen when the CPU is able to | |
4473 | * deliver the interrupt. | |
4474 | */ | |
4475 | if (kvm_cpu_has_extint(vcpu)) | |
4476 | return false; | |
4477 | ||
4478 | /* Acknowledging ExtINT does not happen if LINT0 is masked. */ | |
127a457a MG |
4479 | return (!lapic_in_kernel(vcpu) || |
4480 | kvm_apic_accept_pic_intr(vcpu)); | |
4481 | } | |
4482 | ||
782d422b MG |
4483 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
4484 | { | |
fa7a549d PB |
4485 | /* |
4486 | * Do not cause an interrupt window exit if an exception | |
4487 | * is pending or an event needs reinjection; userspace | |
4488 | * might want to inject the interrupt manually using KVM_SET_REGS | |
4489 | * or KVM_SET_SREGS. For that to work, we must be at an | |
4490 | * instruction boundary and with no events half-injected. | |
4491 | */ | |
4492 | return (kvm_arch_interrupt_allowed(vcpu) && | |
4493 | kvm_cpu_accept_dm_intr(vcpu) && | |
4494 | !kvm_event_needs_reinjection(vcpu) && | |
4495 | !vcpu->arch.exception.pending); | |
782d422b MG |
4496 | } |
4497 | ||
f77bc6a4 ZX |
4498 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
4499 | struct kvm_interrupt *irq) | |
4500 | { | |
02cdb50f | 4501 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 4502 | return -EINVAL; |
1c1a9ce9 SR |
4503 | |
4504 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
4505 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
4506 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4507 | return 0; | |
4508 | } | |
4509 | ||
4510 | /* | |
4511 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
4512 | * fail for in-kernel 8259. | |
4513 | */ | |
4514 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 4515 | return -ENXIO; |
f77bc6a4 | 4516 | |
1c1a9ce9 SR |
4517 | if (vcpu->arch.pending_external_vector != -1) |
4518 | return -EEXIST; | |
f77bc6a4 | 4519 | |
1c1a9ce9 | 4520 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 4521 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
4522 | return 0; |
4523 | } | |
4524 | ||
c4abb7c9 JK |
4525 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
4526 | { | |
c4abb7c9 | 4527 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
4528 | |
4529 | return 0; | |
4530 | } | |
4531 | ||
f077825a PB |
4532 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
4533 | { | |
64d60670 PB |
4534 | kvm_make_request(KVM_REQ_SMI, vcpu); |
4535 | ||
f077825a PB |
4536 | return 0; |
4537 | } | |
4538 | ||
b209749f AK |
4539 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
4540 | struct kvm_tpr_access_ctl *tac) | |
4541 | { | |
4542 | if (tac->flags) | |
4543 | return -EINVAL; | |
4544 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
4545 | return 0; | |
4546 | } | |
4547 | ||
890ca9ae HY |
4548 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
4549 | u64 mcg_cap) | |
4550 | { | |
4551 | int r; | |
4552 | unsigned bank_num = mcg_cap & 0xff, bank; | |
4553 | ||
4554 | r = -EINVAL; | |
c4e0e4ab | 4555 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 4556 | goto out; |
c45dcc71 | 4557 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
4558 | goto out; |
4559 | r = 0; | |
4560 | vcpu->arch.mcg_cap = mcg_cap; | |
4561 | /* Init IA32_MCG_CTL to all 1s */ | |
4562 | if (mcg_cap & MCG_CTL_P) | |
4563 | vcpu->arch.mcg_ctl = ~(u64)0; | |
4564 | /* Init IA32_MCi_CTL to all 1s */ | |
4565 | for (bank = 0; bank < bank_num; bank++) | |
4566 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 4567 | |
b3646477 | 4568 | static_call(kvm_x86_setup_mce)(vcpu); |
890ca9ae HY |
4569 | out: |
4570 | return r; | |
4571 | } | |
4572 | ||
4573 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
4574 | struct kvm_x86_mce *mce) | |
4575 | { | |
4576 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
4577 | unsigned bank_num = mcg_cap & 0xff; | |
4578 | u64 *banks = vcpu->arch.mce_banks; | |
4579 | ||
4580 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
4581 | return -EINVAL; | |
4582 | /* | |
4583 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
4584 | * reporting is disabled | |
4585 | */ | |
4586 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
4587 | vcpu->arch.mcg_ctl != ~(u64)0) | |
4588 | return 0; | |
4589 | banks += 4 * mce->bank; | |
4590 | /* | |
4591 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
4592 | * reporting is disabled for the bank | |
4593 | */ | |
4594 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
4595 | return 0; | |
4596 | if (mce->status & MCI_STATUS_UC) { | |
4597 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 4598 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 4599 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
4600 | return 0; |
4601 | } | |
4602 | if (banks[1] & MCI_STATUS_VAL) | |
4603 | mce->status |= MCI_STATUS_OVER; | |
4604 | banks[2] = mce->addr; | |
4605 | banks[3] = mce->misc; | |
4606 | vcpu->arch.mcg_status = mce->mcg_status; | |
4607 | banks[1] = mce->status; | |
4608 | kvm_queue_exception(vcpu, MC_VECTOR); | |
4609 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
4610 | || !(banks[1] & MCI_STATUS_UC)) { | |
4611 | if (banks[1] & MCI_STATUS_VAL) | |
4612 | mce->status |= MCI_STATUS_OVER; | |
4613 | banks[2] = mce->addr; | |
4614 | banks[3] = mce->misc; | |
4615 | banks[1] = mce->status; | |
4616 | } else | |
4617 | banks[1] |= MCI_STATUS_OVER; | |
4618 | return 0; | |
4619 | } | |
4620 | ||
3cfc3092 JK |
4621 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
4622 | struct kvm_vcpu_events *events) | |
4623 | { | |
7460fb4a | 4624 | process_nmi(vcpu); |
59073aaf | 4625 | |
1f7becf1 JZ |
4626 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
4627 | process_smi(vcpu); | |
4628 | ||
a06230b6 OU |
4629 | /* |
4630 | * In guest mode, payload delivery should be deferred, | |
4631 | * so that the L1 hypervisor can intercept #PF before | |
4632 | * CR2 is modified (or intercept #DB before DR6 is | |
4633 | * modified under nVMX). Unless the per-VM capability, | |
4634 | * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of | |
4635 | * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we | |
4636 | * opportunistically defer the exception payload, deliver it if the | |
4637 | * capability hasn't been requested before processing a | |
4638 | * KVM_GET_VCPU_EVENTS. | |
4639 | */ | |
4640 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
4641 | vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) | |
4642 | kvm_deliver_exception_payload(vcpu); | |
4643 | ||
664f8e26 | 4644 | /* |
59073aaf JM |
4645 | * The API doesn't provide the instruction length for software |
4646 | * exceptions, so don't report them. As long as the guest RIP | |
4647 | * isn't advanced, we should expect to encounter the exception | |
4648 | * again. | |
664f8e26 | 4649 | */ |
59073aaf JM |
4650 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
4651 | events->exception.injected = 0; | |
4652 | events->exception.pending = 0; | |
4653 | } else { | |
4654 | events->exception.injected = vcpu->arch.exception.injected; | |
4655 | events->exception.pending = vcpu->arch.exception.pending; | |
4656 | /* | |
4657 | * For ABI compatibility, deliberately conflate | |
4658 | * pending and injected exceptions when | |
4659 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
4660 | */ | |
4661 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4662 | events->exception.injected |= | |
4663 | vcpu->arch.exception.pending; | |
4664 | } | |
3cfc3092 JK |
4665 | events->exception.nr = vcpu->arch.exception.nr; |
4666 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
4667 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
4668 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
4669 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 4670 | |
03b82a30 | 4671 | events->interrupt.injected = |
04140b41 | 4672 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 4673 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 4674 | events->interrupt.soft = 0; |
b3646477 | 4675 | events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
3cfc3092 JK |
4676 | |
4677 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 4678 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
b3646477 | 4679 | events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); |
97e69aa6 | 4680 | events->nmi.pad = 0; |
3cfc3092 | 4681 | |
66450a21 | 4682 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 4683 | |
f077825a PB |
4684 | events->smi.smm = is_smm(vcpu); |
4685 | events->smi.pending = vcpu->arch.smi_pending; | |
4686 | events->smi.smm_inside_nmi = | |
4687 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
4688 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
4689 | ||
dab4b911 | 4690 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
4691 | | KVM_VCPUEVENT_VALID_SHADOW |
4692 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
4693 | if (vcpu->kvm->arch.exception_payload_enabled) |
4694 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
4695 | ||
97e69aa6 | 4696 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
4697 | } |
4698 | ||
dc87275f | 4699 | static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); |
6ef4e07e | 4700 | |
3cfc3092 JK |
4701 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
4702 | struct kvm_vcpu_events *events) | |
4703 | { | |
dab4b911 | 4704 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 4705 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 4706 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
4707 | | KVM_VCPUEVENT_VALID_SMM |
4708 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
4709 | return -EINVAL; |
4710 | ||
59073aaf JM |
4711 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
4712 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4713 | return -EINVAL; | |
4714 | if (events->exception.pending) | |
4715 | events->exception.injected = 0; | |
4716 | else | |
4717 | events->exception_has_payload = 0; | |
4718 | } else { | |
4719 | events->exception.pending = 0; | |
4720 | events->exception_has_payload = 0; | |
4721 | } | |
4722 | ||
4723 | if ((events->exception.injected || events->exception.pending) && | |
4724 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
4725 | return -EINVAL; |
4726 | ||
28bf2888 DH |
4727 | /* INITs are latched while in SMM */ |
4728 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
4729 | (events->smi.smm || events->smi.pending) && | |
4730 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
4731 | return -EINVAL; | |
4732 | ||
7460fb4a | 4733 | process_nmi(vcpu); |
59073aaf JM |
4734 | vcpu->arch.exception.injected = events->exception.injected; |
4735 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
4736 | vcpu->arch.exception.nr = events->exception.nr; |
4737 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
4738 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
4739 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
4740 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 4741 | |
04140b41 | 4742 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
4743 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
4744 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 4745 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
b3646477 JB |
4746 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, |
4747 | events->interrupt.shadow); | |
3cfc3092 JK |
4748 | |
4749 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
4750 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
4751 | vcpu->arch.nmi_pending = events->nmi.pending; | |
b3646477 | 4752 | static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); |
3cfc3092 | 4753 | |
66450a21 | 4754 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 4755 | lapic_in_kernel(vcpu)) |
66450a21 | 4756 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 4757 | |
f077825a | 4758 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
dc87275f SC |
4759 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) |
4760 | kvm_smm_changed(vcpu, events->smi.smm); | |
6ef4e07e | 4761 | |
f077825a | 4762 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
4763 | |
4764 | if (events->smi.smm) { | |
4765 | if (events->smi.smm_inside_nmi) | |
4766 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 4767 | else |
f4ef1910 | 4768 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
4769 | } |
4770 | ||
4771 | if (lapic_in_kernel(vcpu)) { | |
4772 | if (events->smi.latched_init) | |
4773 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
4774 | else | |
4775 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
4776 | } |
4777 | } | |
4778 | ||
3842d135 AK |
4779 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
4780 | ||
3cfc3092 JK |
4781 | return 0; |
4782 | } | |
4783 | ||
a1efbe77 JK |
4784 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
4785 | struct kvm_debugregs *dbgregs) | |
4786 | { | |
73aaf249 JK |
4787 | unsigned long val; |
4788 | ||
a1efbe77 | 4789 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 4790 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 4791 | dbgregs->dr6 = val; |
a1efbe77 JK |
4792 | dbgregs->dr7 = vcpu->arch.dr7; |
4793 | dbgregs->flags = 0; | |
97e69aa6 | 4794 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
4795 | } |
4796 | ||
4797 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
4798 | struct kvm_debugregs *dbgregs) | |
4799 | { | |
4800 | if (dbgregs->flags) | |
4801 | return -EINVAL; | |
4802 | ||
fd238002 | 4803 | if (!kvm_dr6_valid(dbgregs->dr6)) |
d14bdb55 | 4804 | return -EINVAL; |
fd238002 | 4805 | if (!kvm_dr7_valid(dbgregs->dr7)) |
d14bdb55 PB |
4806 | return -EINVAL; |
4807 | ||
a1efbe77 | 4808 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 4809 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
4810 | vcpu->arch.dr6 = dbgregs->dr6; |
4811 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 4812 | kvm_update_dr7(vcpu); |
a1efbe77 | 4813 | |
a1efbe77 JK |
4814 | return 0; |
4815 | } | |
4816 | ||
df1daba7 PB |
4817 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
4818 | ||
4819 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
4820 | { | |
b666a4b6 | 4821 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 4822 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
4823 | u64 valid; |
4824 | ||
4825 | /* | |
4826 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4827 | * leaves 0 and 1 in the loop below. | |
4828 | */ | |
4829 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
4830 | ||
4831 | /* Set XSTATE_BV */ | |
00c87e9a | 4832 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
4833 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
4834 | ||
4835 | /* | |
4836 | * Copy each region from the possibly compacted offset to the | |
4837 | * non-compacted offset. | |
4838 | */ | |
d91cab78 | 4839 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4840 | while (valid) { |
71ef4533 | 4841 | u32 size, offset, ecx, edx; |
abd16d68 SAS |
4842 | u64 xfeature_mask = valid & -valid; |
4843 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
71ef4533 DH |
4844 | void *src; |
4845 | ||
4846 | cpuid_count(XSTATE_CPUID, xfeature_nr, | |
4847 | &size, &offset, &ecx, &edx); | |
38cfd5e3 | 4848 | |
71ef4533 DH |
4849 | if (xfeature_nr == XFEATURE_PKRU) { |
4850 | memcpy(dest + offset, &vcpu->arch.pkru, | |
4851 | sizeof(vcpu->arch.pkru)); | |
4852 | } else { | |
4853 | src = get_xsave_addr(xsave, xfeature_nr); | |
4854 | if (src) | |
4855 | memcpy(dest + offset, src, size); | |
df1daba7 PB |
4856 | } |
4857 | ||
abd16d68 | 4858 | valid -= xfeature_mask; |
df1daba7 PB |
4859 | } |
4860 | } | |
4861 | ||
4862 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
4863 | { | |
b666a4b6 | 4864 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
4865 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
4866 | u64 valid; | |
4867 | ||
4868 | /* | |
4869 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4870 | * leaves 0 and 1 in the loop below. | |
4871 | */ | |
4872 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
4873 | ||
4874 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 4875 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 4876 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 4877 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
4878 | |
4879 | /* | |
4880 | * Copy each region from the non-compacted offset to the | |
4881 | * possibly compacted offset. | |
4882 | */ | |
d91cab78 | 4883 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4884 | while (valid) { |
71ef4533 | 4885 | u32 size, offset, ecx, edx; |
abd16d68 SAS |
4886 | u64 xfeature_mask = valid & -valid; |
4887 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
71ef4533 DH |
4888 | |
4889 | cpuid_count(XSTATE_CPUID, xfeature_nr, | |
4890 | &size, &offset, &ecx, &edx); | |
4891 | ||
4892 | if (xfeature_nr == XFEATURE_PKRU) { | |
4893 | memcpy(&vcpu->arch.pkru, src + offset, | |
4894 | sizeof(vcpu->arch.pkru)); | |
4895 | } else { | |
4896 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
4897 | ||
4898 | if (dest) | |
38cfd5e3 | 4899 | memcpy(dest, src + offset, size); |
ee4100da | 4900 | } |
df1daba7 | 4901 | |
abd16d68 | 4902 | valid -= xfeature_mask; |
df1daba7 PB |
4903 | } |
4904 | } | |
4905 | ||
2d5b5a66 SY |
4906 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
4907 | struct kvm_xsave *guest_xsave) | |
4908 | { | |
ed02b213 TL |
4909 | if (!vcpu->arch.guest_fpu) |
4910 | return; | |
4911 | ||
d366bf7e | 4912 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
4913 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
4914 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 4915 | } else { |
2d5b5a66 | 4916 | memcpy(guest_xsave->region, |
b666a4b6 | 4917 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4918 | sizeof(struct fxregs_state)); |
2d5b5a66 | 4919 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 4920 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
4921 | } |
4922 | } | |
4923 | ||
a575813b WL |
4924 | #define XSAVE_MXCSR_OFFSET 24 |
4925 | ||
2d5b5a66 SY |
4926 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
4927 | struct kvm_xsave *guest_xsave) | |
4928 | { | |
ed02b213 TL |
4929 | u64 xstate_bv; |
4930 | u32 mxcsr; | |
4931 | ||
4932 | if (!vcpu->arch.guest_fpu) | |
4933 | return 0; | |
4934 | ||
4935 | xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
4936 | mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; | |
2d5b5a66 | 4937 | |
d366bf7e | 4938 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
4939 | /* |
4940 | * Here we allow setting states that are not present in | |
4941 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
4942 | * with old userspace. | |
4943 | */ | |
cfc48181 | 4944 | if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) |
d7876f1b | 4945 | return -EINVAL; |
df1daba7 | 4946 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 4947 | } else { |
a575813b WL |
4948 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
4949 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 4950 | return -EINVAL; |
b666a4b6 | 4951 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4952 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
4953 | } |
4954 | return 0; | |
4955 | } | |
4956 | ||
4957 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
4958 | struct kvm_xcrs *guest_xcrs) | |
4959 | { | |
d366bf7e | 4960 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
4961 | guest_xcrs->nr_xcrs = 0; |
4962 | return; | |
4963 | } | |
4964 | ||
4965 | guest_xcrs->nr_xcrs = 1; | |
4966 | guest_xcrs->flags = 0; | |
4967 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
4968 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
4969 | } | |
4970 | ||
4971 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
4972 | struct kvm_xcrs *guest_xcrs) | |
4973 | { | |
4974 | int i, r = 0; | |
4975 | ||
d366bf7e | 4976 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
4977 | return -EINVAL; |
4978 | ||
4979 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
4980 | return -EINVAL; | |
4981 | ||
4982 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4983 | /* Only support XCR0 currently */ | |
c67a04cb | 4984 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4985 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4986 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4987 | break; |
4988 | } | |
4989 | if (r) | |
4990 | r = -EINVAL; | |
4991 | return r; | |
4992 | } | |
4993 | ||
1c0b28c2 EM |
4994 | /* |
4995 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4996 | * stopped by the hypervisor. This function will be called from the host only. | |
4997 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4998 | * does not support pv clocks. | |
4999 | */ | |
5000 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
5001 | { | |
0b79459b | 5002 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 5003 | return -EINVAL; |
51d59c6b | 5004 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
5005 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
5006 | return 0; | |
5007 | } | |
5008 | ||
828ca896 OU |
5009 | static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, |
5010 | struct kvm_device_attr *attr) | |
5011 | { | |
5012 | int r; | |
5013 | ||
5014 | switch (attr->attr) { | |
5015 | case KVM_VCPU_TSC_OFFSET: | |
5016 | r = 0; | |
5017 | break; | |
5018 | default: | |
5019 | r = -ENXIO; | |
5020 | } | |
5021 | ||
5022 | return r; | |
5023 | } | |
5024 | ||
5025 | static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, | |
5026 | struct kvm_device_attr *attr) | |
5027 | { | |
5028 | u64 __user *uaddr = (u64 __user *)(unsigned long)attr->addr; | |
5029 | int r; | |
5030 | ||
5031 | if ((u64)(unsigned long)uaddr != attr->addr) | |
5032 | return -EFAULT; | |
5033 | ||
5034 | switch (attr->attr) { | |
5035 | case KVM_VCPU_TSC_OFFSET: | |
5036 | r = -EFAULT; | |
5037 | if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) | |
5038 | break; | |
5039 | r = 0; | |
5040 | break; | |
5041 | default: | |
5042 | r = -ENXIO; | |
5043 | } | |
5044 | ||
5045 | return r; | |
5046 | } | |
5047 | ||
5048 | static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, | |
5049 | struct kvm_device_attr *attr) | |
5050 | { | |
5051 | u64 __user *uaddr = (u64 __user *)(unsigned long)attr->addr; | |
5052 | struct kvm *kvm = vcpu->kvm; | |
5053 | int r; | |
5054 | ||
5055 | if ((u64)(unsigned long)uaddr != attr->addr) | |
5056 | return -EFAULT; | |
5057 | ||
5058 | switch (attr->attr) { | |
5059 | case KVM_VCPU_TSC_OFFSET: { | |
5060 | u64 offset, tsc, ns; | |
5061 | unsigned long flags; | |
5062 | bool matched; | |
5063 | ||
5064 | r = -EFAULT; | |
5065 | if (get_user(offset, uaddr)) | |
5066 | break; | |
5067 | ||
5068 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); | |
5069 | ||
5070 | matched = (vcpu->arch.virtual_tsc_khz && | |
5071 | kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && | |
5072 | kvm->arch.last_tsc_offset == offset); | |
5073 | ||
5074 | tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; | |
5075 | ns = get_kvmclock_base_ns(); | |
5076 | ||
5077 | __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); | |
5078 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
5079 | ||
5080 | r = 0; | |
5081 | break; | |
5082 | } | |
5083 | default: | |
5084 | r = -ENXIO; | |
5085 | } | |
5086 | ||
5087 | return r; | |
5088 | } | |
5089 | ||
5090 | static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, | |
5091 | unsigned int ioctl, | |
5092 | void __user *argp) | |
5093 | { | |
5094 | struct kvm_device_attr attr; | |
5095 | int r; | |
5096 | ||
5097 | if (copy_from_user(&attr, argp, sizeof(attr))) | |
5098 | return -EFAULT; | |
5099 | ||
5100 | if (attr.group != KVM_VCPU_TSC_CTRL) | |
5101 | return -ENXIO; | |
5102 | ||
5103 | switch (ioctl) { | |
5104 | case KVM_HAS_DEVICE_ATTR: | |
5105 | r = kvm_arch_tsc_has_attr(vcpu, &attr); | |
5106 | break; | |
5107 | case KVM_GET_DEVICE_ATTR: | |
5108 | r = kvm_arch_tsc_get_attr(vcpu, &attr); | |
5109 | break; | |
5110 | case KVM_SET_DEVICE_ATTR: | |
5111 | r = kvm_arch_tsc_set_attr(vcpu, &attr); | |
5112 | break; | |
5113 | } | |
5114 | ||
5115 | return r; | |
5116 | } | |
5117 | ||
5c919412 AS |
5118 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
5119 | struct kvm_enable_cap *cap) | |
5120 | { | |
57b119da VK |
5121 | int r; |
5122 | uint16_t vmcs_version; | |
5123 | void __user *user_ptr; | |
5124 | ||
5c919412 AS |
5125 | if (cap->flags) |
5126 | return -EINVAL; | |
5127 | ||
5128 | switch (cap->cap) { | |
efc479e6 RK |
5129 | case KVM_CAP_HYPERV_SYNIC2: |
5130 | if (cap->args[0]) | |
5131 | return -EINVAL; | |
df561f66 | 5132 | fallthrough; |
b2869f28 | 5133 | |
5c919412 | 5134 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
5135 | if (!irqchip_in_kernel(vcpu->kvm)) |
5136 | return -EINVAL; | |
efc479e6 RK |
5137 | return kvm_hv_activate_synic(vcpu, cap->cap == |
5138 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 5139 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 5140 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 5141 | return -ENOTTY; |
33b22172 | 5142 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
5143 | if (!r) { |
5144 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
5145 | if (copy_to_user(user_ptr, &vmcs_version, | |
5146 | sizeof(vmcs_version))) | |
5147 | r = -EFAULT; | |
5148 | } | |
5149 | return r; | |
344c6c80 | 5150 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 5151 | if (!kvm_x86_ops.enable_direct_tlbflush) |
344c6c80 TL |
5152 | return -ENOTTY; |
5153 | ||
b3646477 | 5154 | return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); |
57b119da | 5155 | |
644f7067 VK |
5156 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
5157 | return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); | |
5158 | ||
66570e96 OU |
5159 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
5160 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
5161 | if (vcpu->arch.pv_cpuid.enforce) |
5162 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
5163 | |
5164 | return 0; | |
5c919412 AS |
5165 | default: |
5166 | return -EINVAL; | |
5167 | } | |
5168 | } | |
5169 | ||
313a3dc7 CO |
5170 | long kvm_arch_vcpu_ioctl(struct file *filp, |
5171 | unsigned int ioctl, unsigned long arg) | |
5172 | { | |
5173 | struct kvm_vcpu *vcpu = filp->private_data; | |
5174 | void __user *argp = (void __user *)arg; | |
5175 | int r; | |
d1ac91d8 | 5176 | union { |
6dba9403 | 5177 | struct kvm_sregs2 *sregs2; |
d1ac91d8 AK |
5178 | struct kvm_lapic_state *lapic; |
5179 | struct kvm_xsave *xsave; | |
5180 | struct kvm_xcrs *xcrs; | |
5181 | void *buffer; | |
5182 | } u; | |
5183 | ||
9b062471 CD |
5184 | vcpu_load(vcpu); |
5185 | ||
d1ac91d8 | 5186 | u.buffer = NULL; |
313a3dc7 CO |
5187 | switch (ioctl) { |
5188 | case KVM_GET_LAPIC: { | |
2204ae3c | 5189 | r = -EINVAL; |
bce87cce | 5190 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 5191 | goto out; |
254272ce BG |
5192 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
5193 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 5194 | |
b772ff36 | 5195 | r = -ENOMEM; |
d1ac91d8 | 5196 | if (!u.lapic) |
b772ff36 | 5197 | goto out; |
d1ac91d8 | 5198 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
5199 | if (r) |
5200 | goto out; | |
5201 | r = -EFAULT; | |
d1ac91d8 | 5202 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
5203 | goto out; |
5204 | r = 0; | |
5205 | break; | |
5206 | } | |
5207 | case KVM_SET_LAPIC: { | |
2204ae3c | 5208 | r = -EINVAL; |
bce87cce | 5209 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 5210 | goto out; |
ff5c2c03 | 5211 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
5212 | if (IS_ERR(u.lapic)) { |
5213 | r = PTR_ERR(u.lapic); | |
5214 | goto out_nofree; | |
5215 | } | |
ff5c2c03 | 5216 | |
d1ac91d8 | 5217 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
5218 | break; |
5219 | } | |
f77bc6a4 ZX |
5220 | case KVM_INTERRUPT: { |
5221 | struct kvm_interrupt irq; | |
5222 | ||
5223 | r = -EFAULT; | |
0e96f31e | 5224 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
5225 | goto out; |
5226 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
5227 | break; |
5228 | } | |
c4abb7c9 JK |
5229 | case KVM_NMI: { |
5230 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
5231 | break; |
5232 | } | |
f077825a PB |
5233 | case KVM_SMI: { |
5234 | r = kvm_vcpu_ioctl_smi(vcpu); | |
5235 | break; | |
5236 | } | |
313a3dc7 CO |
5237 | case KVM_SET_CPUID: { |
5238 | struct kvm_cpuid __user *cpuid_arg = argp; | |
5239 | struct kvm_cpuid cpuid; | |
5240 | ||
5241 | r = -EFAULT; | |
0e96f31e | 5242 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
5243 | goto out; |
5244 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
5245 | break; |
5246 | } | |
07716717 DK |
5247 | case KVM_SET_CPUID2: { |
5248 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5249 | struct kvm_cpuid2 cpuid; | |
5250 | ||
5251 | r = -EFAULT; | |
0e96f31e | 5252 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5253 | goto out; |
5254 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 5255 | cpuid_arg->entries); |
07716717 DK |
5256 | break; |
5257 | } | |
5258 | case KVM_GET_CPUID2: { | |
5259 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5260 | struct kvm_cpuid2 cpuid; | |
5261 | ||
5262 | r = -EFAULT; | |
0e96f31e | 5263 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5264 | goto out; |
5265 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 5266 | cpuid_arg->entries); |
07716717 DK |
5267 | if (r) |
5268 | goto out; | |
5269 | r = -EFAULT; | |
0e96f31e | 5270 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
5271 | goto out; |
5272 | r = 0; | |
5273 | break; | |
5274 | } | |
801e459a TL |
5275 | case KVM_GET_MSRS: { |
5276 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 5277 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 5278 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5279 | break; |
801e459a TL |
5280 | } |
5281 | case KVM_SET_MSRS: { | |
5282 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 5283 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 5284 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5285 | break; |
801e459a | 5286 | } |
b209749f AK |
5287 | case KVM_TPR_ACCESS_REPORTING: { |
5288 | struct kvm_tpr_access_ctl tac; | |
5289 | ||
5290 | r = -EFAULT; | |
0e96f31e | 5291 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
5292 | goto out; |
5293 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
5294 | if (r) | |
5295 | goto out; | |
5296 | r = -EFAULT; | |
0e96f31e | 5297 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
5298 | goto out; |
5299 | r = 0; | |
5300 | break; | |
5301 | }; | |
b93463aa AK |
5302 | case KVM_SET_VAPIC_ADDR: { |
5303 | struct kvm_vapic_addr va; | |
7301d6ab | 5304 | int idx; |
b93463aa AK |
5305 | |
5306 | r = -EINVAL; | |
35754c98 | 5307 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
5308 | goto out; |
5309 | r = -EFAULT; | |
0e96f31e | 5310 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 5311 | goto out; |
7301d6ab | 5312 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 5313 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 5314 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5315 | break; |
5316 | } | |
890ca9ae HY |
5317 | case KVM_X86_SETUP_MCE: { |
5318 | u64 mcg_cap; | |
5319 | ||
5320 | r = -EFAULT; | |
0e96f31e | 5321 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
5322 | goto out; |
5323 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
5324 | break; | |
5325 | } | |
5326 | case KVM_X86_SET_MCE: { | |
5327 | struct kvm_x86_mce mce; | |
5328 | ||
5329 | r = -EFAULT; | |
0e96f31e | 5330 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
5331 | goto out; |
5332 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
5333 | break; | |
5334 | } | |
3cfc3092 JK |
5335 | case KVM_GET_VCPU_EVENTS: { |
5336 | struct kvm_vcpu_events events; | |
5337 | ||
5338 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
5339 | ||
5340 | r = -EFAULT; | |
5341 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
5342 | break; | |
5343 | r = 0; | |
5344 | break; | |
5345 | } | |
5346 | case KVM_SET_VCPU_EVENTS: { | |
5347 | struct kvm_vcpu_events events; | |
5348 | ||
5349 | r = -EFAULT; | |
5350 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
5351 | break; | |
5352 | ||
5353 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
5354 | break; | |
5355 | } | |
a1efbe77 JK |
5356 | case KVM_GET_DEBUGREGS: { |
5357 | struct kvm_debugregs dbgregs; | |
5358 | ||
5359 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
5360 | ||
5361 | r = -EFAULT; | |
5362 | if (copy_to_user(argp, &dbgregs, | |
5363 | sizeof(struct kvm_debugregs))) | |
5364 | break; | |
5365 | r = 0; | |
5366 | break; | |
5367 | } | |
5368 | case KVM_SET_DEBUGREGS: { | |
5369 | struct kvm_debugregs dbgregs; | |
5370 | ||
5371 | r = -EFAULT; | |
5372 | if (copy_from_user(&dbgregs, argp, | |
5373 | sizeof(struct kvm_debugregs))) | |
5374 | break; | |
5375 | ||
5376 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
5377 | break; | |
5378 | } | |
2d5b5a66 | 5379 | case KVM_GET_XSAVE: { |
254272ce | 5380 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5381 | r = -ENOMEM; |
d1ac91d8 | 5382 | if (!u.xsave) |
2d5b5a66 SY |
5383 | break; |
5384 | ||
d1ac91d8 | 5385 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5386 | |
5387 | r = -EFAULT; | |
d1ac91d8 | 5388 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
5389 | break; |
5390 | r = 0; | |
5391 | break; | |
5392 | } | |
5393 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 5394 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
5395 | if (IS_ERR(u.xsave)) { |
5396 | r = PTR_ERR(u.xsave); | |
5397 | goto out_nofree; | |
5398 | } | |
2d5b5a66 | 5399 | |
d1ac91d8 | 5400 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5401 | break; |
5402 | } | |
5403 | case KVM_GET_XCRS: { | |
254272ce | 5404 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5405 | r = -ENOMEM; |
d1ac91d8 | 5406 | if (!u.xcrs) |
2d5b5a66 SY |
5407 | break; |
5408 | ||
d1ac91d8 | 5409 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5410 | |
5411 | r = -EFAULT; | |
d1ac91d8 | 5412 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
5413 | sizeof(struct kvm_xcrs))) |
5414 | break; | |
5415 | r = 0; | |
5416 | break; | |
5417 | } | |
5418 | case KVM_SET_XCRS: { | |
ff5c2c03 | 5419 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
5420 | if (IS_ERR(u.xcrs)) { |
5421 | r = PTR_ERR(u.xcrs); | |
5422 | goto out_nofree; | |
5423 | } | |
2d5b5a66 | 5424 | |
d1ac91d8 | 5425 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5426 | break; |
5427 | } | |
92a1f12d JR |
5428 | case KVM_SET_TSC_KHZ: { |
5429 | u32 user_tsc_khz; | |
5430 | ||
5431 | r = -EINVAL; | |
92a1f12d JR |
5432 | user_tsc_khz = (u32)arg; |
5433 | ||
26769f96 MT |
5434 | if (kvm_has_tsc_control && |
5435 | user_tsc_khz >= kvm_max_guest_tsc_khz) | |
92a1f12d JR |
5436 | goto out; |
5437 | ||
cc578287 ZA |
5438 | if (user_tsc_khz == 0) |
5439 | user_tsc_khz = tsc_khz; | |
5440 | ||
381d585c HZ |
5441 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
5442 | r = 0; | |
92a1f12d | 5443 | |
92a1f12d JR |
5444 | goto out; |
5445 | } | |
5446 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 5447 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
5448 | goto out; |
5449 | } | |
1c0b28c2 EM |
5450 | case KVM_KVMCLOCK_CTRL: { |
5451 | r = kvm_set_guest_paused(vcpu); | |
5452 | goto out; | |
5453 | } | |
5c919412 AS |
5454 | case KVM_ENABLE_CAP: { |
5455 | struct kvm_enable_cap cap; | |
5456 | ||
5457 | r = -EFAULT; | |
5458 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
5459 | goto out; | |
5460 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
5461 | break; | |
5462 | } | |
8fcc4b59 JM |
5463 | case KVM_GET_NESTED_STATE: { |
5464 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5465 | u32 user_data_size; | |
5466 | ||
5467 | r = -EINVAL; | |
33b22172 | 5468 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
5469 | break; |
5470 | ||
5471 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 5472 | r = -EFAULT; |
8fcc4b59 | 5473 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 5474 | break; |
8fcc4b59 | 5475 | |
33b22172 PB |
5476 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
5477 | user_data_size); | |
8fcc4b59 | 5478 | if (r < 0) |
26b471c7 | 5479 | break; |
8fcc4b59 JM |
5480 | |
5481 | if (r > user_data_size) { | |
5482 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
5483 | r = -EFAULT; |
5484 | else | |
5485 | r = -E2BIG; | |
5486 | break; | |
8fcc4b59 | 5487 | } |
26b471c7 | 5488 | |
8fcc4b59 JM |
5489 | r = 0; |
5490 | break; | |
5491 | } | |
5492 | case KVM_SET_NESTED_STATE: { | |
5493 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5494 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 5495 | int idx; |
8fcc4b59 JM |
5496 | |
5497 | r = -EINVAL; | |
33b22172 | 5498 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
5499 | break; |
5500 | ||
26b471c7 | 5501 | r = -EFAULT; |
8fcc4b59 | 5502 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 5503 | break; |
8fcc4b59 | 5504 | |
26b471c7 | 5505 | r = -EINVAL; |
8fcc4b59 | 5506 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 5507 | break; |
8fcc4b59 JM |
5508 | |
5509 | if (kvm_state.flags & | |
8cab6507 | 5510 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
5511 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
5512 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 5513 | break; |
8fcc4b59 JM |
5514 | |
5515 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
5516 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
5517 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 5518 | break; |
8fcc4b59 | 5519 | |
ad5996d9 | 5520 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 5521 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 5522 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
5523 | break; |
5524 | } | |
c21d54f0 VK |
5525 | case KVM_GET_SUPPORTED_HV_CPUID: |
5526 | r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); | |
2bc39970 | 5527 | break; |
b59b153d | 5528 | #ifdef CONFIG_KVM_XEN |
3e324615 DW |
5529 | case KVM_XEN_VCPU_GET_ATTR: { |
5530 | struct kvm_xen_vcpu_attr xva; | |
5531 | ||
5532 | r = -EFAULT; | |
5533 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5534 | goto out; | |
5535 | r = kvm_xen_vcpu_get_attr(vcpu, &xva); | |
5536 | if (!r && copy_to_user(argp, &xva, sizeof(xva))) | |
5537 | r = -EFAULT; | |
5538 | break; | |
5539 | } | |
5540 | case KVM_XEN_VCPU_SET_ATTR: { | |
5541 | struct kvm_xen_vcpu_attr xva; | |
5542 | ||
5543 | r = -EFAULT; | |
5544 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5545 | goto out; | |
5546 | r = kvm_xen_vcpu_set_attr(vcpu, &xva); | |
5547 | break; | |
5548 | } | |
b59b153d | 5549 | #endif |
6dba9403 ML |
5550 | case KVM_GET_SREGS2: { |
5551 | u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); | |
5552 | r = -ENOMEM; | |
5553 | if (!u.sregs2) | |
5554 | goto out; | |
5555 | __get_sregs2(vcpu, u.sregs2); | |
5556 | r = -EFAULT; | |
5557 | if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) | |
5558 | goto out; | |
5559 | r = 0; | |
5560 | break; | |
5561 | } | |
5562 | case KVM_SET_SREGS2: { | |
5563 | u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); | |
5564 | if (IS_ERR(u.sregs2)) { | |
5565 | r = PTR_ERR(u.sregs2); | |
5566 | u.sregs2 = NULL; | |
5567 | goto out; | |
5568 | } | |
5569 | r = __set_sregs2(vcpu, u.sregs2); | |
5570 | break; | |
5571 | } | |
828ca896 OU |
5572 | case KVM_HAS_DEVICE_ATTR: |
5573 | case KVM_GET_DEVICE_ATTR: | |
5574 | case KVM_SET_DEVICE_ATTR: | |
5575 | r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); | |
5576 | break; | |
313a3dc7 CO |
5577 | default: |
5578 | r = -EINVAL; | |
5579 | } | |
5580 | out: | |
d1ac91d8 | 5581 | kfree(u.buffer); |
9b062471 CD |
5582 | out_nofree: |
5583 | vcpu_put(vcpu); | |
313a3dc7 CO |
5584 | return r; |
5585 | } | |
5586 | ||
1499fa80 | 5587 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
5588 | { |
5589 | return VM_FAULT_SIGBUS; | |
5590 | } | |
5591 | ||
1fe779f8 CO |
5592 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
5593 | { | |
5594 | int ret; | |
5595 | ||
5596 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 5597 | return -EINVAL; |
b3646477 | 5598 | ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); |
1fe779f8 CO |
5599 | return ret; |
5600 | } | |
5601 | ||
b927a3ce SY |
5602 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
5603 | u64 ident_addr) | |
5604 | { | |
b3646477 | 5605 | return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); |
b927a3ce SY |
5606 | } |
5607 | ||
1fe779f8 | 5608 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 5609 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
5610 | { |
5611 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
5612 | return -EINVAL; | |
5613 | ||
79fac95e | 5614 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
5615 | |
5616 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 5617 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 5618 | |
79fac95e | 5619 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
5620 | return 0; |
5621 | } | |
5622 | ||
bc8a3d89 | 5623 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 5624 | { |
39de71ec | 5625 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
5626 | } |
5627 | ||
1fe779f8 CO |
5628 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
5629 | { | |
90bca052 | 5630 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5631 | int r; |
5632 | ||
5633 | r = 0; | |
5634 | switch (chip->chip_id) { | |
5635 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 5636 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
5637 | sizeof(struct kvm_pic_state)); |
5638 | break; | |
5639 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 5640 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
5641 | sizeof(struct kvm_pic_state)); |
5642 | break; | |
5643 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5644 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5645 | break; |
5646 | default: | |
5647 | r = -EINVAL; | |
5648 | break; | |
5649 | } | |
5650 | return r; | |
5651 | } | |
5652 | ||
5653 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
5654 | { | |
90bca052 | 5655 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5656 | int r; |
5657 | ||
5658 | r = 0; | |
5659 | switch (chip->chip_id) { | |
5660 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
5661 | spin_lock(&pic->lock); |
5662 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 5663 | sizeof(struct kvm_pic_state)); |
90bca052 | 5664 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5665 | break; |
5666 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
5667 | spin_lock(&pic->lock); |
5668 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 5669 | sizeof(struct kvm_pic_state)); |
90bca052 | 5670 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5671 | break; |
5672 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5673 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5674 | break; |
5675 | default: | |
5676 | r = -EINVAL; | |
5677 | break; | |
5678 | } | |
90bca052 | 5679 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
5680 | return r; |
5681 | } | |
5682 | ||
e0f63cb9 SY |
5683 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
5684 | { | |
34f3941c RK |
5685 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
5686 | ||
5687 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
5688 | ||
5689 | mutex_lock(&kps->lock); | |
5690 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
5691 | mutex_unlock(&kps->lock); | |
2da29bcc | 5692 | return 0; |
e0f63cb9 SY |
5693 | } |
5694 | ||
5695 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
5696 | { | |
0185604c | 5697 | int i; |
09edea72 RK |
5698 | struct kvm_pit *pit = kvm->arch.vpit; |
5699 | ||
5700 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 5701 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 5702 | for (i = 0; i < 3; i++) |
09edea72 RK |
5703 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
5704 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 5705 | return 0; |
e9f42757 BK |
5706 | } |
5707 | ||
5708 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5709 | { | |
e9f42757 BK |
5710 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
5711 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
5712 | sizeof(ps->channels)); | |
5713 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
5714 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 5715 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 5716 | return 0; |
e9f42757 BK |
5717 | } |
5718 | ||
5719 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
5720 | { | |
2da29bcc | 5721 | int start = 0; |
0185604c | 5722 | int i; |
e9f42757 | 5723 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
5724 | struct kvm_pit *pit = kvm->arch.vpit; |
5725 | ||
5726 | mutex_lock(&pit->pit_state.lock); | |
5727 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
5728 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
5729 | if (!prev_legacy && cur_legacy) | |
5730 | start = 1; | |
09edea72 RK |
5731 | memcpy(&pit->pit_state.channels, &ps->channels, |
5732 | sizeof(pit->pit_state.channels)); | |
5733 | pit->pit_state.flags = ps->flags; | |
0185604c | 5734 | for (i = 0; i < 3; i++) |
09edea72 | 5735 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 5736 | start && i == 0); |
09edea72 | 5737 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 5738 | return 0; |
e0f63cb9 SY |
5739 | } |
5740 | ||
52d939a0 MT |
5741 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
5742 | struct kvm_reinject_control *control) | |
5743 | { | |
71474e2f RK |
5744 | struct kvm_pit *pit = kvm->arch.vpit; |
5745 | ||
71474e2f RK |
5746 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
5747 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
5748 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
5749 | */ | |
5750 | mutex_lock(&pit->pit_state.lock); | |
5751 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
5752 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 5753 | |
52d939a0 MT |
5754 | return 0; |
5755 | } | |
5756 | ||
0dff0846 | 5757 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 5758 | { |
a018eba5 | 5759 | |
88178fd4 | 5760 | /* |
a018eba5 SC |
5761 | * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called |
5762 | * before reporting dirty_bitmap to userspace. KVM flushes the buffers | |
5763 | * on all VM-Exits, thus we only need to kick running vCPUs to force a | |
5764 | * VM-Exit. | |
88178fd4 | 5765 | */ |
a018eba5 SC |
5766 | struct kvm_vcpu *vcpu; |
5767 | int i; | |
5768 | ||
5769 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5770 | kvm_vcpu_kick(vcpu); | |
5bb064dc ZX |
5771 | } |
5772 | ||
aa2fbe6d YZ |
5773 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
5774 | bool line_status) | |
23d43cf9 CD |
5775 | { |
5776 | if (!irqchip_in_kernel(kvm)) | |
5777 | return -ENXIO; | |
5778 | ||
5779 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
5780 | irq_event->irq, irq_event->level, |
5781 | line_status); | |
23d43cf9 CD |
5782 | return 0; |
5783 | } | |
5784 | ||
e5d83c74 PB |
5785 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
5786 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
5787 | { |
5788 | int r; | |
5789 | ||
5790 | if (cap->flags) | |
5791 | return -EINVAL; | |
5792 | ||
5793 | switch (cap->cap) { | |
5794 | case KVM_CAP_DISABLE_QUIRKS: | |
5795 | kvm->arch.disabled_quirks = cap->args[0]; | |
5796 | r = 0; | |
5797 | break; | |
49df6397 SR |
5798 | case KVM_CAP_SPLIT_IRQCHIP: { |
5799 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
5800 | r = -EINVAL; |
5801 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
5802 | goto split_irqchip_unlock; | |
49df6397 SR |
5803 | r = -EEXIST; |
5804 | if (irqchip_in_kernel(kvm)) | |
5805 | goto split_irqchip_unlock; | |
557abc40 | 5806 | if (kvm->created_vcpus) |
49df6397 SR |
5807 | goto split_irqchip_unlock; |
5808 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 5809 | if (r) |
49df6397 SR |
5810 | goto split_irqchip_unlock; |
5811 | /* Pairs with irqchip_in_kernel. */ | |
5812 | smp_wmb(); | |
49776faf | 5813 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 5814 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
5815 | r = 0; |
5816 | split_irqchip_unlock: | |
5817 | mutex_unlock(&kvm->lock); | |
5818 | break; | |
5819 | } | |
37131313 RK |
5820 | case KVM_CAP_X2APIC_API: |
5821 | r = -EINVAL; | |
5822 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
5823 | break; | |
5824 | ||
5825 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
5826 | kvm->arch.x2apic_format = true; | |
c519265f RK |
5827 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
5828 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
5829 | |
5830 | r = 0; | |
5831 | break; | |
4d5422ce WL |
5832 | case KVM_CAP_X86_DISABLE_EXITS: |
5833 | r = -EINVAL; | |
5834 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
5835 | break; | |
5836 | ||
5837 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
5838 | kvm_can_mwait_in_guest()) | |
5839 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 5840 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 5841 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
5842 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
5843 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
5844 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
5845 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
5846 | r = 0; |
5847 | break; | |
6fbbde9a DS |
5848 | case KVM_CAP_MSR_PLATFORM_INFO: |
5849 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
5850 | r = 0; | |
c4f55198 JM |
5851 | break; |
5852 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
5853 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
5854 | r = 0; | |
6fbbde9a | 5855 | break; |
1ae09954 AG |
5856 | case KVM_CAP_X86_USER_SPACE_MSR: |
5857 | kvm->arch.user_space_msr_mask = cap->args[0]; | |
5858 | r = 0; | |
5859 | break; | |
fe6b6bc8 CQ |
5860 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
5861 | r = -EINVAL; | |
5862 | if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) | |
5863 | break; | |
5864 | ||
5865 | if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && | |
5866 | (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) | |
5867 | break; | |
5868 | ||
5869 | if (kvm_has_bus_lock_exit && | |
5870 | cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) | |
5871 | kvm->arch.bus_lock_detection_enabled = true; | |
5872 | r = 0; | |
5873 | break; | |
fe7e9488 SC |
5874 | #ifdef CONFIG_X86_SGX_KVM |
5875 | case KVM_CAP_SGX_ATTRIBUTE: { | |
5876 | unsigned long allowed_attributes = 0; | |
5877 | ||
5878 | r = sgx_set_attribute(&allowed_attributes, cap->args[0]); | |
5879 | if (r) | |
5880 | break; | |
5881 | ||
5882 | /* KVM only supports the PROVISIONKEY privileged attribute. */ | |
5883 | if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && | |
5884 | !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) | |
5885 | kvm->arch.sgx_provisioning_allowed = true; | |
5886 | else | |
5887 | r = -EINVAL; | |
5888 | break; | |
5889 | } | |
5890 | #endif | |
54526d1f NT |
5891 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
5892 | r = -EINVAL; | |
5893 | if (kvm_x86_ops.vm_copy_enc_context_from) | |
5894 | r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); | |
5895 | return r; | |
0dbb1123 AK |
5896 | case KVM_CAP_EXIT_HYPERCALL: |
5897 | if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { | |
5898 | r = -EINVAL; | |
5899 | break; | |
5900 | } | |
5901 | kvm->arch.hypercall_exit_enabled = cap->args[0]; | |
5902 | r = 0; | |
5903 | break; | |
19238e75 AL |
5904 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
5905 | r = -EINVAL; | |
5906 | if (cap->args[0] & ~1) | |
5907 | break; | |
5908 | kvm->arch.exit_on_emulation_error = cap->args[0]; | |
5909 | r = 0; | |
5910 | break; | |
90de4a18 NA |
5911 | default: |
5912 | r = -EINVAL; | |
5913 | break; | |
5914 | } | |
5915 | return r; | |
5916 | } | |
5917 | ||
b318e8de SC |
5918 | static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) |
5919 | { | |
5920 | struct kvm_x86_msr_filter *msr_filter; | |
5921 | ||
5922 | msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); | |
5923 | if (!msr_filter) | |
5924 | return NULL; | |
5925 | ||
5926 | msr_filter->default_allow = default_allow; | |
5927 | return msr_filter; | |
5928 | } | |
5929 | ||
5930 | static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) | |
1a155254 AG |
5931 | { |
5932 | u32 i; | |
1a155254 | 5933 | |
b318e8de SC |
5934 | if (!msr_filter) |
5935 | return; | |
5936 | ||
5937 | for (i = 0; i < msr_filter->count; i++) | |
5938 | kfree(msr_filter->ranges[i].bitmap); | |
1a155254 | 5939 | |
b318e8de | 5940 | kfree(msr_filter); |
1a155254 AG |
5941 | } |
5942 | ||
b318e8de SC |
5943 | static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, |
5944 | struct kvm_msr_filter_range *user_range) | |
1a155254 | 5945 | { |
1a155254 AG |
5946 | unsigned long *bitmap = NULL; |
5947 | size_t bitmap_size; | |
1a155254 AG |
5948 | |
5949 | if (!user_range->nmsrs) | |
5950 | return 0; | |
5951 | ||
aca35288 SC |
5952 | if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) |
5953 | return -EINVAL; | |
5954 | ||
5955 | if (!user_range->flags) | |
5956 | return -EINVAL; | |
5957 | ||
1a155254 AG |
5958 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); |
5959 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
5960 | return -EINVAL; | |
5961 | ||
5962 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
5963 | if (IS_ERR(bitmap)) | |
5964 | return PTR_ERR(bitmap); | |
5965 | ||
aca35288 | 5966 | msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { |
1a155254 AG |
5967 | .flags = user_range->flags, |
5968 | .base = user_range->base, | |
5969 | .nmsrs = user_range->nmsrs, | |
5970 | .bitmap = bitmap, | |
5971 | }; | |
5972 | ||
b318e8de | 5973 | msr_filter->count++; |
1a155254 | 5974 | return 0; |
1a155254 AG |
5975 | } |
5976 | ||
5977 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) | |
5978 | { | |
5979 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
b318e8de | 5980 | struct kvm_x86_msr_filter *new_filter, *old_filter; |
1a155254 AG |
5981 | struct kvm_msr_filter filter; |
5982 | bool default_allow; | |
043248b3 | 5983 | bool empty = true; |
b318e8de | 5984 | int r = 0; |
1a155254 AG |
5985 | u32 i; |
5986 | ||
5987 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
5988 | return -EFAULT; | |
5989 | ||
043248b3 PB |
5990 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) |
5991 | empty &= !filter.ranges[i].nmsrs; | |
1a155254 AG |
5992 | |
5993 | default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); | |
043248b3 PB |
5994 | if (empty && !default_allow) |
5995 | return -EINVAL; | |
5996 | ||
b318e8de SC |
5997 | new_filter = kvm_alloc_msr_filter(default_allow); |
5998 | if (!new_filter) | |
5999 | return -ENOMEM; | |
1a155254 | 6000 | |
1a155254 | 6001 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { |
b318e8de SC |
6002 | r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); |
6003 | if (r) { | |
6004 | kvm_free_msr_filter(new_filter); | |
6005 | return r; | |
6006 | } | |
1a155254 AG |
6007 | } |
6008 | ||
b318e8de SC |
6009 | mutex_lock(&kvm->lock); |
6010 | ||
6011 | /* The per-VM filter is protected by kvm->lock... */ | |
6012 | old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); | |
6013 | ||
6014 | rcu_assign_pointer(kvm->arch.msr_filter, new_filter); | |
6015 | synchronize_srcu(&kvm->srcu); | |
6016 | ||
6017 | kvm_free_msr_filter(old_filter); | |
6018 | ||
1a155254 AG |
6019 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); |
6020 | mutex_unlock(&kvm->lock); | |
6021 | ||
b318e8de | 6022 | return 0; |
1a155254 AG |
6023 | } |
6024 | ||
7d62874f SS |
6025 | #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER |
6026 | static int kvm_arch_suspend_notifier(struct kvm *kvm) | |
6027 | { | |
6028 | struct kvm_vcpu *vcpu; | |
6029 | int i, ret = 0; | |
6030 | ||
6031 | mutex_lock(&kvm->lock); | |
6032 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6033 | if (!vcpu->arch.pv_time_enabled) | |
6034 | continue; | |
6035 | ||
6036 | ret = kvm_set_guest_paused(vcpu); | |
6037 | if (ret) { | |
6038 | kvm_err("Failed to pause guest VCPU%d: %d\n", | |
6039 | vcpu->vcpu_id, ret); | |
6040 | break; | |
6041 | } | |
6042 | } | |
6043 | mutex_unlock(&kvm->lock); | |
6044 | ||
6045 | return ret ? NOTIFY_BAD : NOTIFY_DONE; | |
6046 | } | |
6047 | ||
6048 | int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) | |
6049 | { | |
6050 | switch (state) { | |
6051 | case PM_HIBERNATION_PREPARE: | |
6052 | case PM_SUSPEND_PREPARE: | |
6053 | return kvm_arch_suspend_notifier(kvm); | |
6054 | } | |
6055 | ||
6056 | return NOTIFY_DONE; | |
6057 | } | |
6058 | #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ | |
6059 | ||
45e6c2fa PB |
6060 | static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) |
6061 | { | |
869b4421 | 6062 | struct kvm_clock_data data = { 0 }; |
45e6c2fa | 6063 | |
55c0cefb | 6064 | get_kvmclock(kvm, &data); |
45e6c2fa PB |
6065 | if (copy_to_user(argp, &data, sizeof(data))) |
6066 | return -EFAULT; | |
6067 | ||
6068 | return 0; | |
6069 | } | |
6070 | ||
6071 | static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) | |
6072 | { | |
6073 | struct kvm_arch *ka = &kvm->arch; | |
6074 | struct kvm_clock_data data; | |
c68dc1b5 | 6075 | u64 now_raw_ns; |
45e6c2fa PB |
6076 | |
6077 | if (copy_from_user(&data, argp, sizeof(data))) | |
6078 | return -EFAULT; | |
6079 | ||
c68dc1b5 OU |
6080 | /* |
6081 | * Only KVM_CLOCK_REALTIME is used, but allow passing the | |
6082 | * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. | |
6083 | */ | |
6084 | if (data.flags & ~KVM_CLOCK_VALID_FLAGS) | |
45e6c2fa PB |
6085 | return -EINVAL; |
6086 | ||
6087 | kvm_hv_invalidate_tsc_page(kvm); | |
6088 | kvm_start_pvclock_update(kvm); | |
6089 | pvclock_update_vm_gtod_copy(kvm); | |
6090 | ||
6091 | /* | |
6092 | * This pairs with kvm_guest_time_update(): when masterclock is | |
6093 | * in use, we use master_kernel_ns + kvmclock_offset to set | |
6094 | * unsigned 'system_time' so if we use get_kvmclock_ns() (which | |
6095 | * is slightly ahead) here we risk going negative on unsigned | |
6096 | * 'system_time' when 'data.clock' is very small. | |
6097 | */ | |
c68dc1b5 OU |
6098 | if (data.flags & KVM_CLOCK_REALTIME) { |
6099 | u64 now_real_ns = ktime_get_real_ns(); | |
6100 | ||
6101 | /* | |
6102 | * Avoid stepping the kvmclock backwards. | |
6103 | */ | |
6104 | if (now_real_ns > data.realtime) | |
6105 | data.clock += now_real_ns - data.realtime; | |
6106 | } | |
6107 | ||
6108 | if (ka->use_master_clock) | |
6109 | now_raw_ns = ka->master_kernel_ns; | |
45e6c2fa | 6110 | else |
c68dc1b5 OU |
6111 | now_raw_ns = get_kvmclock_base_ns(); |
6112 | ka->kvmclock_offset = data.clock - now_raw_ns; | |
45e6c2fa PB |
6113 | kvm_end_pvclock_update(kvm); |
6114 | return 0; | |
6115 | } | |
6116 | ||
1fe779f8 CO |
6117 | long kvm_arch_vm_ioctl(struct file *filp, |
6118 | unsigned int ioctl, unsigned long arg) | |
6119 | { | |
6120 | struct kvm *kvm = filp->private_data; | |
6121 | void __user *argp = (void __user *)arg; | |
367e1319 | 6122 | int r = -ENOTTY; |
f0d66275 DH |
6123 | /* |
6124 | * This union makes it completely explicit to gcc-3.x | |
6125 | * that these two variables' stack usage should be | |
6126 | * combined, not added together. | |
6127 | */ | |
6128 | union { | |
6129 | struct kvm_pit_state ps; | |
e9f42757 | 6130 | struct kvm_pit_state2 ps2; |
c5ff41ce | 6131 | struct kvm_pit_config pit_config; |
f0d66275 | 6132 | } u; |
1fe779f8 CO |
6133 | |
6134 | switch (ioctl) { | |
6135 | case KVM_SET_TSS_ADDR: | |
6136 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 6137 | break; |
b927a3ce SY |
6138 | case KVM_SET_IDENTITY_MAP_ADDR: { |
6139 | u64 ident_addr; | |
6140 | ||
1af1ac91 DH |
6141 | mutex_lock(&kvm->lock); |
6142 | r = -EINVAL; | |
6143 | if (kvm->created_vcpus) | |
6144 | goto set_identity_unlock; | |
b927a3ce | 6145 | r = -EFAULT; |
0e96f31e | 6146 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 6147 | goto set_identity_unlock; |
b927a3ce | 6148 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
6149 | set_identity_unlock: |
6150 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
6151 | break; |
6152 | } | |
1fe779f8 CO |
6153 | case KVM_SET_NR_MMU_PAGES: |
6154 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
6155 | break; |
6156 | case KVM_GET_NR_MMU_PAGES: | |
6157 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
6158 | break; | |
3ddea128 | 6159 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 6160 | mutex_lock(&kvm->lock); |
09941366 | 6161 | |
3ddea128 | 6162 | r = -EEXIST; |
35e6eaa3 | 6163 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 6164 | goto create_irqchip_unlock; |
09941366 | 6165 | |
3e515705 | 6166 | r = -EINVAL; |
557abc40 | 6167 | if (kvm->created_vcpus) |
3e515705 | 6168 | goto create_irqchip_unlock; |
09941366 RK |
6169 | |
6170 | r = kvm_pic_init(kvm); | |
6171 | if (r) | |
3ddea128 | 6172 | goto create_irqchip_unlock; |
09941366 RK |
6173 | |
6174 | r = kvm_ioapic_init(kvm); | |
6175 | if (r) { | |
09941366 | 6176 | kvm_pic_destroy(kvm); |
3ddea128 | 6177 | goto create_irqchip_unlock; |
09941366 RK |
6178 | } |
6179 | ||
399ec807 AK |
6180 | r = kvm_setup_default_irq_routing(kvm); |
6181 | if (r) { | |
72bb2fcd | 6182 | kvm_ioapic_destroy(kvm); |
09941366 | 6183 | kvm_pic_destroy(kvm); |
71ba994c | 6184 | goto create_irqchip_unlock; |
399ec807 | 6185 | } |
49776faf | 6186 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 6187 | smp_wmb(); |
49776faf | 6188 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
6189 | create_irqchip_unlock: |
6190 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 6191 | break; |
3ddea128 | 6192 | } |
7837699f | 6193 | case KVM_CREATE_PIT: |
c5ff41ce JK |
6194 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
6195 | goto create_pit; | |
6196 | case KVM_CREATE_PIT2: | |
6197 | r = -EFAULT; | |
6198 | if (copy_from_user(&u.pit_config, argp, | |
6199 | sizeof(struct kvm_pit_config))) | |
6200 | goto out; | |
6201 | create_pit: | |
250715a6 | 6202 | mutex_lock(&kvm->lock); |
269e05e4 AK |
6203 | r = -EEXIST; |
6204 | if (kvm->arch.vpit) | |
6205 | goto create_pit_unlock; | |
7837699f | 6206 | r = -ENOMEM; |
c5ff41ce | 6207 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
6208 | if (kvm->arch.vpit) |
6209 | r = 0; | |
269e05e4 | 6210 | create_pit_unlock: |
250715a6 | 6211 | mutex_unlock(&kvm->lock); |
7837699f | 6212 | break; |
1fe779f8 CO |
6213 | case KVM_GET_IRQCHIP: { |
6214 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 6215 | struct kvm_irqchip *chip; |
1fe779f8 | 6216 | |
ff5c2c03 SL |
6217 | chip = memdup_user(argp, sizeof(*chip)); |
6218 | if (IS_ERR(chip)) { | |
6219 | r = PTR_ERR(chip); | |
1fe779f8 | 6220 | goto out; |
ff5c2c03 SL |
6221 | } |
6222 | ||
1fe779f8 | 6223 | r = -ENXIO; |
826da321 | 6224 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
6225 | goto get_irqchip_out; |
6226 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 6227 | if (r) |
f0d66275 | 6228 | goto get_irqchip_out; |
1fe779f8 | 6229 | r = -EFAULT; |
0e96f31e | 6230 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 6231 | goto get_irqchip_out; |
1fe779f8 | 6232 | r = 0; |
f0d66275 DH |
6233 | get_irqchip_out: |
6234 | kfree(chip); | |
1fe779f8 CO |
6235 | break; |
6236 | } | |
6237 | case KVM_SET_IRQCHIP: { | |
6238 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 6239 | struct kvm_irqchip *chip; |
1fe779f8 | 6240 | |
ff5c2c03 SL |
6241 | chip = memdup_user(argp, sizeof(*chip)); |
6242 | if (IS_ERR(chip)) { | |
6243 | r = PTR_ERR(chip); | |
1fe779f8 | 6244 | goto out; |
ff5c2c03 SL |
6245 | } |
6246 | ||
1fe779f8 | 6247 | r = -ENXIO; |
826da321 | 6248 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
6249 | goto set_irqchip_out; |
6250 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
6251 | set_irqchip_out: |
6252 | kfree(chip); | |
1fe779f8 CO |
6253 | break; |
6254 | } | |
e0f63cb9 | 6255 | case KVM_GET_PIT: { |
e0f63cb9 | 6256 | r = -EFAULT; |
f0d66275 | 6257 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
6258 | goto out; |
6259 | r = -ENXIO; | |
6260 | if (!kvm->arch.vpit) | |
6261 | goto out; | |
f0d66275 | 6262 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
6263 | if (r) |
6264 | goto out; | |
6265 | r = -EFAULT; | |
f0d66275 | 6266 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
6267 | goto out; |
6268 | r = 0; | |
6269 | break; | |
6270 | } | |
6271 | case KVM_SET_PIT: { | |
e0f63cb9 | 6272 | r = -EFAULT; |
0e96f31e | 6273 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 6274 | goto out; |
7289fdb5 | 6275 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
6276 | r = -ENXIO; |
6277 | if (!kvm->arch.vpit) | |
7289fdb5 | 6278 | goto set_pit_out; |
f0d66275 | 6279 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
6280 | set_pit_out: |
6281 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
6282 | break; |
6283 | } | |
e9f42757 BK |
6284 | case KVM_GET_PIT2: { |
6285 | r = -ENXIO; | |
6286 | if (!kvm->arch.vpit) | |
6287 | goto out; | |
6288 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
6289 | if (r) | |
6290 | goto out; | |
6291 | r = -EFAULT; | |
6292 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
6293 | goto out; | |
6294 | r = 0; | |
6295 | break; | |
6296 | } | |
6297 | case KVM_SET_PIT2: { | |
6298 | r = -EFAULT; | |
6299 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
6300 | goto out; | |
7289fdb5 | 6301 | mutex_lock(&kvm->lock); |
e9f42757 BK |
6302 | r = -ENXIO; |
6303 | if (!kvm->arch.vpit) | |
7289fdb5 | 6304 | goto set_pit2_out; |
e9f42757 | 6305 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
6306 | set_pit2_out: |
6307 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
6308 | break; |
6309 | } | |
52d939a0 MT |
6310 | case KVM_REINJECT_CONTROL: { |
6311 | struct kvm_reinject_control control; | |
6312 | r = -EFAULT; | |
6313 | if (copy_from_user(&control, argp, sizeof(control))) | |
6314 | goto out; | |
cad23e72 ML |
6315 | r = -ENXIO; |
6316 | if (!kvm->arch.vpit) | |
6317 | goto out; | |
52d939a0 | 6318 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
6319 | break; |
6320 | } | |
d71ba788 PB |
6321 | case KVM_SET_BOOT_CPU_ID: |
6322 | r = 0; | |
6323 | mutex_lock(&kvm->lock); | |
557abc40 | 6324 | if (kvm->created_vcpus) |
d71ba788 PB |
6325 | r = -EBUSY; |
6326 | else | |
6327 | kvm->arch.bsp_vcpu_id = arg; | |
6328 | mutex_unlock(&kvm->lock); | |
6329 | break; | |
b59b153d | 6330 | #ifdef CONFIG_KVM_XEN |
ffde22ac | 6331 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 6332 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 6333 | r = -EFAULT; |
51776043 | 6334 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac | 6335 | goto out; |
78e9878c | 6336 | r = kvm_xen_hvm_config(kvm, &xhc); |
ffde22ac ES |
6337 | break; |
6338 | } | |
a76b9641 JM |
6339 | case KVM_XEN_HVM_GET_ATTR: { |
6340 | struct kvm_xen_hvm_attr xha; | |
6341 | ||
6342 | r = -EFAULT; | |
6343 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
ffde22ac | 6344 | goto out; |
a76b9641 JM |
6345 | r = kvm_xen_hvm_get_attr(kvm, &xha); |
6346 | if (!r && copy_to_user(argp, &xha, sizeof(xha))) | |
6347 | r = -EFAULT; | |
6348 | break; | |
6349 | } | |
6350 | case KVM_XEN_HVM_SET_ATTR: { | |
6351 | struct kvm_xen_hvm_attr xha; | |
6352 | ||
6353 | r = -EFAULT; | |
6354 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
6355 | goto out; | |
6356 | r = kvm_xen_hvm_set_attr(kvm, &xha); | |
ffde22ac ES |
6357 | break; |
6358 | } | |
b59b153d | 6359 | #endif |
45e6c2fa PB |
6360 | case KVM_SET_CLOCK: |
6361 | r = kvm_vm_ioctl_set_clock(kvm, argp); | |
afbcf7ab | 6362 | break; |
45e6c2fa PB |
6363 | case KVM_GET_CLOCK: |
6364 | r = kvm_vm_ioctl_get_clock(kvm, argp); | |
afbcf7ab | 6365 | break; |
5acc5c06 BS |
6366 | case KVM_MEMORY_ENCRYPT_OP: { |
6367 | r = -ENOTTY; | |
afaf0b2f | 6368 | if (kvm_x86_ops.mem_enc_op) |
b3646477 | 6369 | r = static_call(kvm_x86_mem_enc_op)(kvm, argp); |
5acc5c06 BS |
6370 | break; |
6371 | } | |
69eaedee BS |
6372 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
6373 | struct kvm_enc_region region; | |
6374 | ||
6375 | r = -EFAULT; | |
6376 | if (copy_from_user(®ion, argp, sizeof(region))) | |
6377 | goto out; | |
6378 | ||
6379 | r = -ENOTTY; | |
afaf0b2f | 6380 | if (kvm_x86_ops.mem_enc_reg_region) |
b3646477 | 6381 | r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); |
69eaedee BS |
6382 | break; |
6383 | } | |
6384 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
6385 | struct kvm_enc_region region; | |
6386 | ||
6387 | r = -EFAULT; | |
6388 | if (copy_from_user(®ion, argp, sizeof(region))) | |
6389 | goto out; | |
6390 | ||
6391 | r = -ENOTTY; | |
afaf0b2f | 6392 | if (kvm_x86_ops.mem_enc_unreg_region) |
b3646477 | 6393 | r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); |
69eaedee BS |
6394 | break; |
6395 | } | |
faeb7833 RK |
6396 | case KVM_HYPERV_EVENTFD: { |
6397 | struct kvm_hyperv_eventfd hvevfd; | |
6398 | ||
6399 | r = -EFAULT; | |
6400 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
6401 | goto out; | |
6402 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
6403 | break; | |
6404 | } | |
66bb8a06 EH |
6405 | case KVM_SET_PMU_EVENT_FILTER: |
6406 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
6407 | break; | |
1a155254 AG |
6408 | case KVM_X86_SET_MSR_FILTER: |
6409 | r = kvm_vm_ioctl_set_msr_filter(kvm, argp); | |
6410 | break; | |
1fe779f8 | 6411 | default: |
ad6260da | 6412 | r = -ENOTTY; |
1fe779f8 CO |
6413 | } |
6414 | out: | |
6415 | return r; | |
6416 | } | |
6417 | ||
a16b043c | 6418 | static void kvm_init_msr_list(void) |
043405e1 | 6419 | { |
24c29b7a | 6420 | struct x86_pmu_capability x86_pmu; |
043405e1 | 6421 | u32 dummy[2]; |
7a5ee6ed | 6422 | unsigned i; |
043405e1 | 6423 | |
e2ada66e | 6424 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
7a5ee6ed | 6425 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a PB |
6426 | |
6427 | perf_get_x86_pmu_capability(&x86_pmu); | |
e2ada66e | 6428 | |
6cbee2b9 XL |
6429 | num_msrs_to_save = 0; |
6430 | num_emulated_msrs = 0; | |
6431 | num_msr_based_features = 0; | |
6432 | ||
7a5ee6ed CQ |
6433 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
6434 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 6435 | continue; |
93c4adc7 PB |
6436 | |
6437 | /* | |
6438 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 6439 | * to the guests in some cases. |
93c4adc7 | 6440 | */ |
7a5ee6ed | 6441 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 6442 | case MSR_IA32_BNDCFGS: |
503234b3 | 6443 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
6444 | continue; |
6445 | break; | |
9dbe6cf9 | 6446 | case MSR_TSC_AUX: |
36fa06f9 SC |
6447 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && |
6448 | !kvm_cpu_cap_has(X86_FEATURE_RDPID)) | |
9dbe6cf9 PB |
6449 | continue; |
6450 | break; | |
f4cfcd2d ML |
6451 | case MSR_IA32_UMWAIT_CONTROL: |
6452 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
6453 | continue; | |
6454 | break; | |
bf8c55d8 CP |
6455 | case MSR_IA32_RTIT_CTL: |
6456 | case MSR_IA32_RTIT_STATUS: | |
7b874c26 | 6457 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) |
bf8c55d8 CP |
6458 | continue; |
6459 | break; | |
6460 | case MSR_IA32_RTIT_CR3_MATCH: | |
7b874c26 | 6461 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6462 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) |
6463 | continue; | |
6464 | break; | |
6465 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
6466 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7b874c26 | 6467 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6468 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && |
6469 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
6470 | continue; | |
6471 | break; | |
7cb85fc4 | 6472 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: |
7b874c26 | 6473 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
7a5ee6ed | 6474 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
6475 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
6476 | continue; | |
6477 | break; | |
cf05a67b | 6478 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 6479 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
24c29b7a PB |
6480 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
6481 | continue; | |
6482 | break; | |
cf05a67b | 6483 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 6484 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
24c29b7a PB |
6485 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
6486 | continue; | |
7cb85fc4 | 6487 | break; |
93c4adc7 PB |
6488 | default: |
6489 | break; | |
6490 | } | |
6491 | ||
7a5ee6ed | 6492 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 6493 | } |
62ef68bb | 6494 | |
7a5ee6ed | 6495 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
b3646477 | 6496 | if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) |
bc226f07 | 6497 | continue; |
62ef68bb | 6498 | |
7a5ee6ed | 6499 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 6500 | } |
801e459a | 6501 | |
7a5ee6ed | 6502 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
6503 | struct kvm_msr_entry msr; |
6504 | ||
7a5ee6ed | 6505 | msr.index = msr_based_features_all[i]; |
66421c1e | 6506 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
6507 | continue; |
6508 | ||
7a5ee6ed | 6509 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 6510 | } |
043405e1 CO |
6511 | } |
6512 | ||
bda9020e MT |
6513 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
6514 | const void *v) | |
bbd9b64e | 6515 | { |
70252a10 AK |
6516 | int handled = 0; |
6517 | int n; | |
6518 | ||
6519 | do { | |
6520 | n = min(len, 8); | |
bce87cce | 6521 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6522 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
6523 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
6524 | break; |
6525 | handled += n; | |
6526 | addr += n; | |
6527 | len -= n; | |
6528 | v += n; | |
6529 | } while (len); | |
bbd9b64e | 6530 | |
70252a10 | 6531 | return handled; |
bbd9b64e CO |
6532 | } |
6533 | ||
bda9020e | 6534 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 6535 | { |
70252a10 AK |
6536 | int handled = 0; |
6537 | int n; | |
6538 | ||
6539 | do { | |
6540 | n = min(len, 8); | |
bce87cce | 6541 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6542 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
6543 | addr, n, v)) | |
6544 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 6545 | break; |
e39d200f | 6546 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
6547 | handled += n; |
6548 | addr += n; | |
6549 | len -= n; | |
6550 | v += n; | |
6551 | } while (len); | |
bbd9b64e | 6552 | |
70252a10 | 6553 | return handled; |
bbd9b64e CO |
6554 | } |
6555 | ||
2dafc6c2 GN |
6556 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
6557 | struct kvm_segment *var, int seg) | |
6558 | { | |
b3646477 | 6559 | static_call(kvm_x86_set_segment)(vcpu, var, seg); |
2dafc6c2 GN |
6560 | } |
6561 | ||
6562 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
6563 | struct kvm_segment *var, int seg) | |
6564 | { | |
b3646477 | 6565 | static_call(kvm_x86_get_segment)(vcpu, var, seg); |
2dafc6c2 GN |
6566 | } |
6567 | ||
54987b7a PB |
6568 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
6569 | struct x86_exception *exception) | |
02f59dc9 JR |
6570 | { |
6571 | gpa_t t_gpa; | |
02f59dc9 JR |
6572 | |
6573 | BUG_ON(!mmu_is_nested(vcpu)); | |
6574 | ||
6575 | /* NPT walks are always user-walks */ | |
6576 | access |= PFERR_USER_MASK; | |
44dd3ffa | 6577 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
6578 | |
6579 | return t_gpa; | |
6580 | } | |
6581 | ||
ab9ae313 AK |
6582 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
6583 | struct x86_exception *exception) | |
1871c602 | 6584 | { |
b3646477 | 6585 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
ab9ae313 | 6586 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 | 6587 | } |
54f958cd | 6588 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); |
1871c602 | 6589 | |
ab9ae313 AK |
6590 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
6591 | struct x86_exception *exception) | |
1871c602 | 6592 | { |
b3646477 | 6593 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 6594 | access |= PFERR_FETCH_MASK; |
ab9ae313 | 6595 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
6596 | } |
6597 | ||
ab9ae313 AK |
6598 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
6599 | struct x86_exception *exception) | |
1871c602 | 6600 | { |
b3646477 | 6601 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 6602 | access |= PFERR_WRITE_MASK; |
ab9ae313 | 6603 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 | 6604 | } |
54f958cd | 6605 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); |
1871c602 GN |
6606 | |
6607 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
6608 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
6609 | struct x86_exception *exception) | |
1871c602 | 6610 | { |
ab9ae313 | 6611 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
6612 | } |
6613 | ||
6614 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
6615 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 6616 | struct x86_exception *exception) |
bbd9b64e CO |
6617 | { |
6618 | void *data = val; | |
10589a46 | 6619 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
6620 | |
6621 | while (bytes) { | |
14dfe855 | 6622 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 6623 | exception); |
bbd9b64e | 6624 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 6625 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
6626 | int ret; |
6627 | ||
bcc55cba | 6628 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6629 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
6630 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
6631 | offset, toread); | |
10589a46 | 6632 | if (ret < 0) { |
c3cd7ffa | 6633 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
6634 | goto out; |
6635 | } | |
bbd9b64e | 6636 | |
77c2002e IE |
6637 | bytes -= toread; |
6638 | data += toread; | |
6639 | addr += toread; | |
bbd9b64e | 6640 | } |
10589a46 | 6641 | out: |
10589a46 | 6642 | return r; |
bbd9b64e | 6643 | } |
77c2002e | 6644 | |
1871c602 | 6645 | /* used for instruction fetching */ |
0f65dd70 AK |
6646 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
6647 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 6648 | struct x86_exception *exception) |
1871c602 | 6649 | { |
0f65dd70 | 6650 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
b3646477 | 6651 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
6652 | unsigned offset; |
6653 | int ret; | |
0f65dd70 | 6654 | |
44583cba PB |
6655 | /* Inline kvm_read_guest_virt_helper for speed. */ |
6656 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
6657 | exception); | |
6658 | if (unlikely(gpa == UNMAPPED_GVA)) | |
6659 | return X86EMUL_PROPAGATE_FAULT; | |
6660 | ||
6661 | offset = addr & (PAGE_SIZE-1); | |
6662 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
6663 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
6664 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
6665 | offset, bytes); | |
44583cba PB |
6666 | if (unlikely(ret < 0)) |
6667 | return X86EMUL_IO_NEEDED; | |
6668 | ||
6669 | return X86EMUL_CONTINUE; | |
1871c602 GN |
6670 | } |
6671 | ||
ce14e868 | 6672 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 6673 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 6674 | struct x86_exception *exception) |
1871c602 | 6675 | { |
b3646477 | 6676 | u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 6677 | |
353c0956 PB |
6678 | /* |
6679 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
6680 | * is returned, but our callers are not ready for that and they blindly | |
6681 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
6682 | * uninitialized kernel stack memory into cr2 and error code. | |
6683 | */ | |
6684 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 6685 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 6686 | exception); |
1871c602 | 6687 | } |
064aea77 | 6688 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 6689 | |
ce14e868 PB |
6690 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
6691 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 6692 | struct x86_exception *exception, bool system) |
1871c602 | 6693 | { |
0f65dd70 | 6694 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
6695 | u32 access = 0; |
6696 | ||
b3646477 | 6697 | if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) |
3c9fa24c PB |
6698 | access |= PFERR_USER_MASK; |
6699 | ||
6700 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
6701 | } |
6702 | ||
7a036a6f RK |
6703 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
6704 | unsigned long addr, void *val, unsigned int bytes) | |
6705 | { | |
6706 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6707 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
6708 | ||
6709 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
6710 | } | |
6711 | ||
ce14e868 PB |
6712 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
6713 | struct kvm_vcpu *vcpu, u32 access, | |
6714 | struct x86_exception *exception) | |
77c2002e IE |
6715 | { |
6716 | void *data = val; | |
6717 | int r = X86EMUL_CONTINUE; | |
6718 | ||
6719 | while (bytes) { | |
14dfe855 | 6720 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 6721 | access, |
ab9ae313 | 6722 | exception); |
77c2002e IE |
6723 | unsigned offset = addr & (PAGE_SIZE-1); |
6724 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
6725 | int ret; | |
6726 | ||
bcc55cba | 6727 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 6728 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 6729 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 6730 | if (ret < 0) { |
c3cd7ffa | 6731 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
6732 | goto out; |
6733 | } | |
6734 | ||
6735 | bytes -= towrite; | |
6736 | data += towrite; | |
6737 | addr += towrite; | |
6738 | } | |
6739 | out: | |
6740 | return r; | |
6741 | } | |
ce14e868 PB |
6742 | |
6743 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
6744 | unsigned int bytes, struct x86_exception *exception, |
6745 | bool system) | |
ce14e868 PB |
6746 | { |
6747 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
6748 | u32 access = PFERR_WRITE_MASK; |
6749 | ||
b3646477 | 6750 | if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) |
3c9fa24c | 6751 | access |= PFERR_USER_MASK; |
ce14e868 PB |
6752 | |
6753 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 6754 | access, exception); |
ce14e868 PB |
6755 | } |
6756 | ||
6757 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
6758 | unsigned int bytes, struct x86_exception *exception) | |
6759 | { | |
c595ceee PB |
6760 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
6761 | vcpu->arch.l1tf_flush_l1d = true; | |
6762 | ||
ce14e868 PB |
6763 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
6764 | PFERR_WRITE_MASK, exception); | |
6765 | } | |
6a4d7550 | 6766 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 6767 | |
082d06ed WL |
6768 | int handle_ud(struct kvm_vcpu *vcpu) |
6769 | { | |
b3dc0695 | 6770 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 6771 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
6772 | char sig[5]; /* ud2; .ascii "kvm" */ |
6773 | struct x86_exception e; | |
6774 | ||
b3646477 | 6775 | if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) |
09e3e2a1 SC |
6776 | return 1; |
6777 | ||
6c86eedc | 6778 | if (force_emulation_prefix && |
3c9fa24c PB |
6779 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
6780 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 6781 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
6c86eedc | 6782 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 6783 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 6784 | } |
082d06ed | 6785 | |
60fc3d02 | 6786 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
6787 | } |
6788 | EXPORT_SYMBOL_GPL(handle_ud); | |
6789 | ||
0f89b207 TL |
6790 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6791 | gpa_t gpa, bool write) | |
6792 | { | |
6793 | /* For APIC access vmexit */ | |
6794 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6795 | return 1; | |
6796 | ||
6797 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
6798 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
6799 | return 1; | |
6800 | } | |
6801 | ||
6802 | return 0; | |
6803 | } | |
6804 | ||
af7cc7d1 XG |
6805 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
6806 | gpa_t *gpa, struct x86_exception *exception, | |
6807 | bool write) | |
6808 | { | |
b3646477 | 6809 | u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 6810 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 6811 | |
be94f6b7 HH |
6812 | /* |
6813 | * currently PKRU is only applied to ept enabled guest so | |
6814 | * there is no pkey in EPT page table for L1 guest or EPT | |
6815 | * shadow page table for L2 guest. | |
6816 | */ | |
908b7d43 SC |
6817 | if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || |
6818 | !permission_fault(vcpu, vcpu->arch.walk_mmu, | |
6819 | vcpu->arch.mmio_access, 0, access))) { | |
bebb106a XG |
6820 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
6821 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 6822 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
6823 | return 1; |
6824 | } | |
6825 | ||
af7cc7d1 XG |
6826 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
6827 | ||
6828 | if (*gpa == UNMAPPED_GVA) | |
6829 | return -1; | |
6830 | ||
0f89b207 | 6831 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
6832 | } |
6833 | ||
3200f405 | 6834 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 6835 | const void *val, int bytes) |
bbd9b64e CO |
6836 | { |
6837 | int ret; | |
6838 | ||
54bf36aa | 6839 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 6840 | if (ret < 0) |
bbd9b64e | 6841 | return 0; |
0eb05bf2 | 6842 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
6843 | return 1; |
6844 | } | |
6845 | ||
77d197b2 XG |
6846 | struct read_write_emulator_ops { |
6847 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
6848 | int bytes); | |
6849 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6850 | void *val, int bytes); | |
6851 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6852 | int bytes, void *val); | |
6853 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6854 | void *val, int bytes); | |
6855 | bool write; | |
6856 | }; | |
6857 | ||
6858 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
6859 | { | |
6860 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 6861 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 6862 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
6863 | vcpu->mmio_read_completed = 0; |
6864 | return 1; | |
6865 | } | |
6866 | ||
6867 | return 0; | |
6868 | } | |
6869 | ||
6870 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6871 | void *val, int bytes) | |
6872 | { | |
54bf36aa | 6873 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
6874 | } |
6875 | ||
6876 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6877 | void *val, int bytes) | |
6878 | { | |
6879 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
6880 | } | |
6881 | ||
6882 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
6883 | { | |
e39d200f | 6884 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
6885 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
6886 | } | |
6887 | ||
6888 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6889 | void *val, int bytes) | |
6890 | { | |
e39d200f | 6891 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
6892 | return X86EMUL_IO_NEEDED; |
6893 | } | |
6894 | ||
6895 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
6896 | void *val, int bytes) | |
6897 | { | |
f78146b0 AK |
6898 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
6899 | ||
87da7e66 | 6900 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
6901 | return X86EMUL_CONTINUE; |
6902 | } | |
6903 | ||
0fbe9b0b | 6904 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
6905 | .read_write_prepare = read_prepare, |
6906 | .read_write_emulate = read_emulate, | |
6907 | .read_write_mmio = vcpu_mmio_read, | |
6908 | .read_write_exit_mmio = read_exit_mmio, | |
6909 | }; | |
6910 | ||
0fbe9b0b | 6911 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
6912 | .read_write_emulate = write_emulate, |
6913 | .read_write_mmio = write_mmio, | |
6914 | .read_write_exit_mmio = write_exit_mmio, | |
6915 | .write = true, | |
6916 | }; | |
6917 | ||
22388a3c XG |
6918 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
6919 | unsigned int bytes, | |
6920 | struct x86_exception *exception, | |
6921 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 6922 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6923 | { |
af7cc7d1 XG |
6924 | gpa_t gpa; |
6925 | int handled, ret; | |
22388a3c | 6926 | bool write = ops->write; |
f78146b0 | 6927 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 6928 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
6929 | |
6930 | /* | |
6931 | * If the exit was due to a NPF we may already have a GPA. | |
6932 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
6933 | * Note, this cannot be used on string operations since string | |
6934 | * operation using rep will only have the initial GPA from the NPF | |
6935 | * occurred. | |
6936 | */ | |
744e699c SC |
6937 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
6938 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
6939 | gpa = ctxt->gpa_val; | |
618232e2 BS |
6940 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
6941 | } else { | |
6942 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
6943 | if (ret < 0) | |
6944 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 6945 | } |
10589a46 | 6946 | |
618232e2 | 6947 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
6948 | return X86EMUL_CONTINUE; |
6949 | ||
bbd9b64e CO |
6950 | /* |
6951 | * Is this MMIO handled locally? | |
6952 | */ | |
22388a3c | 6953 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 6954 | if (handled == bytes) |
bbd9b64e | 6955 | return X86EMUL_CONTINUE; |
bbd9b64e | 6956 | |
70252a10 AK |
6957 | gpa += handled; |
6958 | bytes -= handled; | |
6959 | val += handled; | |
6960 | ||
87da7e66 XG |
6961 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
6962 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
6963 | frag->gpa = gpa; | |
6964 | frag->data = val; | |
6965 | frag->len = bytes; | |
f78146b0 | 6966 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
6967 | } |
6968 | ||
52eb5a6d XL |
6969 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
6970 | unsigned long addr, | |
22388a3c XG |
6971 | void *val, unsigned int bytes, |
6972 | struct x86_exception *exception, | |
0fbe9b0b | 6973 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 6974 | { |
0f65dd70 | 6975 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
6976 | gpa_t gpa; |
6977 | int rc; | |
6978 | ||
6979 | if (ops->read_write_prepare && | |
6980 | ops->read_write_prepare(vcpu, val, bytes)) | |
6981 | return X86EMUL_CONTINUE; | |
6982 | ||
6983 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 6984 | |
bbd9b64e CO |
6985 | /* Crossing a page boundary? */ |
6986 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 6987 | int now; |
bbd9b64e CO |
6988 | |
6989 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
6990 | rc = emulator_read_write_onepage(addr, val, now, exception, |
6991 | vcpu, ops); | |
6992 | ||
bbd9b64e CO |
6993 | if (rc != X86EMUL_CONTINUE) |
6994 | return rc; | |
6995 | addr += now; | |
bac15531 NA |
6996 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6997 | addr = (u32)addr; | |
bbd9b64e CO |
6998 | val += now; |
6999 | bytes -= now; | |
7000 | } | |
22388a3c | 7001 | |
f78146b0 AK |
7002 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
7003 | vcpu, ops); | |
7004 | if (rc != X86EMUL_CONTINUE) | |
7005 | return rc; | |
7006 | ||
7007 | if (!vcpu->mmio_nr_fragments) | |
7008 | return rc; | |
7009 | ||
7010 | gpa = vcpu->mmio_fragments[0].gpa; | |
7011 | ||
7012 | vcpu->mmio_needed = 1; | |
7013 | vcpu->mmio_cur_fragment = 0; | |
7014 | ||
87da7e66 | 7015 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
7016 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
7017 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
7018 | vcpu->run->mmio.phys_addr = gpa; | |
7019 | ||
7020 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
7021 | } |
7022 | ||
7023 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
7024 | unsigned long addr, | |
7025 | void *val, | |
7026 | unsigned int bytes, | |
7027 | struct x86_exception *exception) | |
7028 | { | |
7029 | return emulator_read_write(ctxt, addr, val, bytes, | |
7030 | exception, &read_emultor); | |
7031 | } | |
7032 | ||
52eb5a6d | 7033 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
7034 | unsigned long addr, |
7035 | const void *val, | |
7036 | unsigned int bytes, | |
7037 | struct x86_exception *exception) | |
7038 | { | |
7039 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
7040 | exception, &write_emultor); | |
bbd9b64e | 7041 | } |
bbd9b64e | 7042 | |
daea3e73 AK |
7043 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
7044 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
7045 | ||
7046 | #ifdef CONFIG_X86_64 | |
7047 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
7048 | #else | |
7049 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 7050 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
7051 | #endif |
7052 | ||
0f65dd70 AK |
7053 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
7054 | unsigned long addr, | |
bbd9b64e CO |
7055 | const void *old, |
7056 | const void *new, | |
7057 | unsigned int bytes, | |
0f65dd70 | 7058 | struct x86_exception *exception) |
bbd9b64e | 7059 | { |
42e35f80 | 7060 | struct kvm_host_map map; |
0f65dd70 | 7061 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 7062 | u64 page_line_mask; |
daea3e73 | 7063 | gpa_t gpa; |
daea3e73 AK |
7064 | char *kaddr; |
7065 | bool exchanged; | |
2bacc55c | 7066 | |
daea3e73 AK |
7067 | /* guests cmpxchg8b have to be emulated atomically */ |
7068 | if (bytes > 8 || (bytes & (bytes - 1))) | |
7069 | goto emul_write; | |
10589a46 | 7070 | |
daea3e73 | 7071 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 7072 | |
daea3e73 AK |
7073 | if (gpa == UNMAPPED_GVA || |
7074 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
7075 | goto emul_write; | |
2bacc55c | 7076 | |
9de6fe3c XL |
7077 | /* |
7078 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
7079 | * enabled in the host and the access splits a cache line. | |
7080 | */ | |
7081 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
7082 | page_line_mask = ~(cache_line_size() - 1); | |
7083 | else | |
7084 | page_line_mask = PAGE_MASK; | |
7085 | ||
7086 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 7087 | goto emul_write; |
72dc67a6 | 7088 | |
42e35f80 | 7089 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 7090 | goto emul_write; |
72dc67a6 | 7091 | |
42e35f80 KA |
7092 | kaddr = map.hva + offset_in_page(gpa); |
7093 | ||
daea3e73 AK |
7094 | switch (bytes) { |
7095 | case 1: | |
7096 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
7097 | break; | |
7098 | case 2: | |
7099 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
7100 | break; | |
7101 | case 4: | |
7102 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
7103 | break; | |
7104 | case 8: | |
7105 | exchanged = CMPXCHG64(kaddr, old, new); | |
7106 | break; | |
7107 | default: | |
7108 | BUG(); | |
2bacc55c | 7109 | } |
42e35f80 KA |
7110 | |
7111 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
7112 | |
7113 | if (!exchanged) | |
7114 | return X86EMUL_CMPXCHG_FAILED; | |
7115 | ||
0eb05bf2 | 7116 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
7117 | |
7118 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 7119 | |
3200f405 | 7120 | emul_write: |
daea3e73 | 7121 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 7122 | |
0f65dd70 | 7123 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
7124 | } |
7125 | ||
cf8f70bf GN |
7126 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
7127 | { | |
cbfc6c91 | 7128 | int r = 0, i; |
cf8f70bf | 7129 | |
cbfc6c91 WL |
7130 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
7131 | if (vcpu->arch.pio.in) | |
7132 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
7133 | vcpu->arch.pio.size, pd); | |
7134 | else | |
7135 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
7136 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
7137 | pd); | |
7138 | if (r) | |
7139 | break; | |
7140 | pd += vcpu->arch.pio.size; | |
7141 | } | |
cf8f70bf GN |
7142 | return r; |
7143 | } | |
7144 | ||
6f6fbe98 XG |
7145 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
7146 | unsigned short port, void *val, | |
7147 | unsigned int count, bool in) | |
cf8f70bf | 7148 | { |
cf8f70bf | 7149 | vcpu->arch.pio.port = port; |
6f6fbe98 | 7150 | vcpu->arch.pio.in = in; |
7972995b | 7151 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
7152 | vcpu->arch.pio.size = size; |
7153 | ||
7154 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 7155 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
7156 | return 1; |
7157 | } | |
7158 | ||
7159 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 7160 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
7161 | vcpu->run->io.size = size; |
7162 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
7163 | vcpu->run->io.count = count; | |
7164 | vcpu->run->io.port = port; | |
7165 | ||
7166 | return 0; | |
7167 | } | |
7168 | ||
2e3bb4d8 SC |
7169 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
7170 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 7171 | { |
6f6fbe98 | 7172 | int ret; |
ca1d4a9e | 7173 | |
6f6fbe98 XG |
7174 | if (vcpu->arch.pio.count) |
7175 | goto data_avail; | |
cf8f70bf | 7176 | |
cbfc6c91 WL |
7177 | memset(vcpu->arch.pio_data, 0, size * count); |
7178 | ||
6f6fbe98 XG |
7179 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
7180 | if (ret) { | |
7181 | data_avail: | |
7182 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 7183 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 7184 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
7185 | return 1; |
7186 | } | |
7187 | ||
cf8f70bf GN |
7188 | return 0; |
7189 | } | |
7190 | ||
2e3bb4d8 SC |
7191 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
7192 | int size, unsigned short port, void *val, | |
7193 | unsigned int count) | |
6f6fbe98 | 7194 | { |
2e3bb4d8 | 7195 | return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); |
6f6fbe98 | 7196 | |
2e3bb4d8 | 7197 | } |
6f6fbe98 | 7198 | |
2e3bb4d8 SC |
7199 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
7200 | unsigned short port, const void *val, | |
7201 | unsigned int count) | |
7202 | { | |
6f6fbe98 | 7203 | memcpy(vcpu->arch.pio_data, val, size * count); |
1171903d | 7204 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
7205 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
7206 | } | |
7207 | ||
2e3bb4d8 SC |
7208 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
7209 | int size, unsigned short port, | |
7210 | const void *val, unsigned int count) | |
7211 | { | |
7212 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
7213 | } | |
7214 | ||
bbd9b64e CO |
7215 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
7216 | { | |
b3646477 | 7217 | return static_call(kvm_x86_get_segment_base)(vcpu, seg); |
bbd9b64e CO |
7218 | } |
7219 | ||
3cb16fe7 | 7220 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 7221 | { |
3cb16fe7 | 7222 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
7223 | } |
7224 | ||
ae6a2375 | 7225 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
7226 | { |
7227 | if (!need_emulate_wbinvd(vcpu)) | |
7228 | return X86EMUL_CONTINUE; | |
7229 | ||
b3646477 | 7230 | if (static_call(kvm_x86_has_wbinvd_exit)()) { |
2eec7343 JK |
7231 | int cpu = get_cpu(); |
7232 | ||
7233 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
c2162e13 | 7234 | on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, |
f5f48ee1 | 7235 | wbinvd_ipi, NULL, 1); |
2eec7343 | 7236 | put_cpu(); |
f5f48ee1 | 7237 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
7238 | } else |
7239 | wbinvd(); | |
f5f48ee1 SY |
7240 | return X86EMUL_CONTINUE; |
7241 | } | |
5cb56059 JS |
7242 | |
7243 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
7244 | { | |
6affcbed KH |
7245 | kvm_emulate_wbinvd_noskip(vcpu); |
7246 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 7247 | } |
f5f48ee1 SY |
7248 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
7249 | ||
5cb56059 JS |
7250 | |
7251 | ||
bcaf5cc5 AK |
7252 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
7253 | { | |
5cb56059 | 7254 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
7255 | } |
7256 | ||
29d6ca41 PB |
7257 | static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
7258 | unsigned long *dest) | |
bbd9b64e | 7259 | { |
29d6ca41 | 7260 | kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
7261 | } |
7262 | ||
52eb5a6d XL |
7263 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
7264 | unsigned long value) | |
bbd9b64e | 7265 | { |
338dbc97 | 7266 | |
996ff542 | 7267 | return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
7268 | } |
7269 | ||
52a46617 | 7270 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 7271 | { |
52a46617 | 7272 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
7273 | } |
7274 | ||
717746e3 | 7275 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 7276 | { |
717746e3 | 7277 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
7278 | unsigned long value; |
7279 | ||
7280 | switch (cr) { | |
7281 | case 0: | |
7282 | value = kvm_read_cr0(vcpu); | |
7283 | break; | |
7284 | case 2: | |
7285 | value = vcpu->arch.cr2; | |
7286 | break; | |
7287 | case 3: | |
9f8fe504 | 7288 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
7289 | break; |
7290 | case 4: | |
7291 | value = kvm_read_cr4(vcpu); | |
7292 | break; | |
7293 | case 8: | |
7294 | value = kvm_get_cr8(vcpu); | |
7295 | break; | |
7296 | default: | |
a737f256 | 7297 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
7298 | return 0; |
7299 | } | |
7300 | ||
7301 | return value; | |
7302 | } | |
7303 | ||
717746e3 | 7304 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 7305 | { |
717746e3 | 7306 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
7307 | int res = 0; |
7308 | ||
52a46617 GN |
7309 | switch (cr) { |
7310 | case 0: | |
49a9b07e | 7311 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
7312 | break; |
7313 | case 2: | |
7314 | vcpu->arch.cr2 = val; | |
7315 | break; | |
7316 | case 3: | |
2390218b | 7317 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
7318 | break; |
7319 | case 4: | |
a83b29c6 | 7320 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
7321 | break; |
7322 | case 8: | |
eea1cff9 | 7323 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
7324 | break; |
7325 | default: | |
a737f256 | 7326 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 7327 | res = -1; |
52a46617 | 7328 | } |
0f12244f GN |
7329 | |
7330 | return res; | |
52a46617 GN |
7331 | } |
7332 | ||
717746e3 | 7333 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 7334 | { |
b3646477 | 7335 | return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); |
9c537244 GN |
7336 | } |
7337 | ||
4bff1e86 | 7338 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 7339 | { |
b3646477 | 7340 | static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
7341 | } |
7342 | ||
4bff1e86 | 7343 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 7344 | { |
b3646477 | 7345 | static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
7346 | } |
7347 | ||
1ac9d0cf AK |
7348 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
7349 | { | |
b3646477 | 7350 | static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
7351 | } |
7352 | ||
7353 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
7354 | { | |
b3646477 | 7355 | static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
7356 | } |
7357 | ||
4bff1e86 AK |
7358 | static unsigned long emulator_get_cached_segment_base( |
7359 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 7360 | { |
4bff1e86 | 7361 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
7362 | } |
7363 | ||
1aa36616 AK |
7364 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
7365 | struct desc_struct *desc, u32 *base3, | |
7366 | int seg) | |
2dafc6c2 GN |
7367 | { |
7368 | struct kvm_segment var; | |
7369 | ||
4bff1e86 | 7370 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 7371 | *selector = var.selector; |
2dafc6c2 | 7372 | |
378a8b09 GN |
7373 | if (var.unusable) { |
7374 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
7375 | if (base3) |
7376 | *base3 = 0; | |
2dafc6c2 | 7377 | return false; |
378a8b09 | 7378 | } |
2dafc6c2 GN |
7379 | |
7380 | if (var.g) | |
7381 | var.limit >>= 12; | |
7382 | set_desc_limit(desc, var.limit); | |
7383 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
7384 | #ifdef CONFIG_X86_64 |
7385 | if (base3) | |
7386 | *base3 = var.base >> 32; | |
7387 | #endif | |
2dafc6c2 GN |
7388 | desc->type = var.type; |
7389 | desc->s = var.s; | |
7390 | desc->dpl = var.dpl; | |
7391 | desc->p = var.present; | |
7392 | desc->avl = var.avl; | |
7393 | desc->l = var.l; | |
7394 | desc->d = var.db; | |
7395 | desc->g = var.g; | |
7396 | ||
7397 | return true; | |
7398 | } | |
7399 | ||
1aa36616 AK |
7400 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
7401 | struct desc_struct *desc, u32 base3, | |
7402 | int seg) | |
2dafc6c2 | 7403 | { |
4bff1e86 | 7404 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
7405 | struct kvm_segment var; |
7406 | ||
1aa36616 | 7407 | var.selector = selector; |
2dafc6c2 | 7408 | var.base = get_desc_base(desc); |
5601d05b GN |
7409 | #ifdef CONFIG_X86_64 |
7410 | var.base |= ((u64)base3) << 32; | |
7411 | #endif | |
2dafc6c2 GN |
7412 | var.limit = get_desc_limit(desc); |
7413 | if (desc->g) | |
7414 | var.limit = (var.limit << 12) | 0xfff; | |
7415 | var.type = desc->type; | |
2dafc6c2 GN |
7416 | var.dpl = desc->dpl; |
7417 | var.db = desc->d; | |
7418 | var.s = desc->s; | |
7419 | var.l = desc->l; | |
7420 | var.g = desc->g; | |
7421 | var.avl = desc->avl; | |
7422 | var.present = desc->p; | |
7423 | var.unusable = !var.present; | |
7424 | var.padding = 0; | |
7425 | ||
7426 | kvm_set_segment(vcpu, &var, seg); | |
7427 | return; | |
7428 | } | |
7429 | ||
717746e3 AK |
7430 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
7431 | u32 msr_index, u64 *pdata) | |
7432 | { | |
1ae09954 AG |
7433 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7434 | int r; | |
7435 | ||
7436 | r = kvm_get_msr(vcpu, msr_index, pdata); | |
7437 | ||
7438 | if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { | |
7439 | /* Bounce to user space */ | |
7440 | return X86EMUL_IO_NEEDED; | |
7441 | } | |
7442 | ||
7443 | return r; | |
717746e3 AK |
7444 | } |
7445 | ||
7446 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
7447 | u32 msr_index, u64 data) | |
7448 | { | |
1ae09954 AG |
7449 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7450 | int r; | |
7451 | ||
7452 | r = kvm_set_msr(vcpu, msr_index, data); | |
7453 | ||
7454 | if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { | |
7455 | /* Bounce to user space */ | |
7456 | return X86EMUL_IO_NEEDED; | |
7457 | } | |
7458 | ||
7459 | return r; | |
717746e3 AK |
7460 | } |
7461 | ||
64d60670 PB |
7462 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
7463 | { | |
7464 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7465 | ||
7466 | return vcpu->arch.smbase; | |
7467 | } | |
7468 | ||
7469 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
7470 | { | |
7471 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7472 | ||
7473 | vcpu->arch.smbase = smbase; | |
7474 | } | |
7475 | ||
67f4d428 NA |
7476 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
7477 | u32 pmc) | |
7478 | { | |
e6cd31f1 JM |
7479 | if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc)) |
7480 | return 0; | |
7481 | return -EINVAL; | |
67f4d428 NA |
7482 | } |
7483 | ||
222d21aa AK |
7484 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
7485 | u32 pmc, u64 *pdata) | |
7486 | { | |
c6702c9d | 7487 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
7488 | } |
7489 | ||
6c3287f7 AK |
7490 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
7491 | { | |
7492 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
7493 | } | |
7494 | ||
2953538e | 7495 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 7496 | struct x86_instruction_info *info, |
c4f035c6 AK |
7497 | enum x86_intercept_stage stage) |
7498 | { | |
b3646477 | 7499 | return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 7500 | &ctxt->exception); |
c4f035c6 AK |
7501 | } |
7502 | ||
e911eb3b | 7503 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
7504 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
7505 | bool exact_only) | |
bdb42f5a | 7506 | { |
f91af517 | 7507 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
7508 | } |
7509 | ||
5ae78e95 SC |
7510 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
7511 | { | |
7512 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
7513 | } | |
7514 | ||
7515 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
7516 | { | |
7517 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
7518 | } | |
7519 | ||
7520 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
7521 | { | |
7522 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
7523 | } | |
7524 | ||
dd856efa AK |
7525 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
7526 | { | |
27b4a9c4 | 7527 | return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); |
dd856efa AK |
7528 | } |
7529 | ||
7530 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
7531 | { | |
27b4a9c4 | 7532 | kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); |
dd856efa AK |
7533 | } |
7534 | ||
801806d9 NA |
7535 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
7536 | { | |
b3646477 | 7537 | static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
7538 | } |
7539 | ||
6ed071f0 LP |
7540 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
7541 | { | |
7542 | return emul_to_vcpu(ctxt)->arch.hflags; | |
7543 | } | |
7544 | ||
edce4654 | 7545 | static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) |
6ed071f0 | 7546 | { |
78fcb2c9 SC |
7547 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7548 | ||
dc87275f | 7549 | kvm_smm_changed(vcpu, false); |
6ed071f0 LP |
7550 | } |
7551 | ||
ecc513e5 | 7552 | static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, |
ed19321f | 7553 | const char *smstate) |
0234bf88 | 7554 | { |
ecc513e5 | 7555 | return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
7556 | } |
7557 | ||
25b17226 SC |
7558 | static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) |
7559 | { | |
7560 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); | |
7561 | } | |
7562 | ||
02d4160f VK |
7563 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
7564 | { | |
7565 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
7566 | } | |
7567 | ||
0225fb50 | 7568 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
7569 | .read_gpr = emulator_read_gpr, |
7570 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
7571 | .read_std = emulator_read_std, |
7572 | .write_std = emulator_write_std, | |
7a036a6f | 7573 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 7574 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
7575 | .read_emulated = emulator_read_emulated, |
7576 | .write_emulated = emulator_write_emulated, | |
7577 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 7578 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
7579 | .pio_in_emulated = emulator_pio_in_emulated, |
7580 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
7581 | .get_segment = emulator_get_segment, |
7582 | .set_segment = emulator_set_segment, | |
5951c442 | 7583 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 7584 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 7585 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
7586 | .set_gdt = emulator_set_gdt, |
7587 | .set_idt = emulator_set_idt, | |
52a46617 GN |
7588 | .get_cr = emulator_get_cr, |
7589 | .set_cr = emulator_set_cr, | |
9c537244 | 7590 | .cpl = emulator_get_cpl, |
35aa5375 GN |
7591 | .get_dr = emulator_get_dr, |
7592 | .set_dr = emulator_set_dr, | |
64d60670 PB |
7593 | .get_smbase = emulator_get_smbase, |
7594 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
7595 | .set_msr = emulator_set_msr, |
7596 | .get_msr = emulator_get_msr, | |
67f4d428 | 7597 | .check_pmc = emulator_check_pmc, |
222d21aa | 7598 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 7599 | .halt = emulator_halt, |
bcaf5cc5 | 7600 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 7601 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 7602 | .intercept = emulator_intercept, |
bdb42f5a | 7603 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
7604 | .guest_has_long_mode = emulator_guest_has_long_mode, |
7605 | .guest_has_movbe = emulator_guest_has_movbe, | |
7606 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
801806d9 | 7607 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 | 7608 | .get_hflags = emulator_get_hflags, |
edce4654 | 7609 | .exiting_smm = emulator_exiting_smm, |
ecc513e5 | 7610 | .leave_smm = emulator_leave_smm, |
25b17226 | 7611 | .triple_fault = emulator_triple_fault, |
02d4160f | 7612 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
7613 | }; |
7614 | ||
95cb2295 GN |
7615 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
7616 | { | |
b3646477 | 7617 | u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
95cb2295 GN |
7618 | /* |
7619 | * an sti; sti; sequence only disable interrupts for the first | |
7620 | * instruction. So, if the last instruction, be it emulated or | |
7621 | * not, left the system with the INT_STI flag enabled, it | |
7622 | * means that the last instruction is an sti. We should not | |
7623 | * leave the flag on in this case. The same goes for mov ss | |
7624 | */ | |
37ccdcbe PB |
7625 | if (int_shadow & mask) |
7626 | mask = 0; | |
6addfc42 | 7627 | if (unlikely(int_shadow || mask)) { |
b3646477 | 7628 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); |
6addfc42 PB |
7629 | if (!mask) |
7630 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7631 | } | |
95cb2295 GN |
7632 | } |
7633 | ||
ef54bcfe | 7634 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 7635 | { |
c9b8b07c | 7636 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
da9cb575 | 7637 | if (ctxt->exception.vector == PF_VECTOR) |
53b3d8e9 | 7638 | return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); |
ef54bcfe PB |
7639 | |
7640 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
7641 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
7642 | ctxt->exception.error_code); | |
54b8486f | 7643 | else |
da9cb575 | 7644 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 7645 | return false; |
54b8486f GN |
7646 | } |
7647 | ||
c9b8b07c SC |
7648 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
7649 | { | |
7650 | struct x86_emulate_ctxt *ctxt; | |
7651 | ||
7652 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
7653 | if (!ctxt) { | |
7654 | pr_err("kvm: failed to allocate vcpu's emulator\n"); | |
7655 | return NULL; | |
7656 | } | |
7657 | ||
7658 | ctxt->vcpu = vcpu; | |
7659 | ctxt->ops = &emulate_ops; | |
7660 | vcpu->arch.emulate_ctxt = ctxt; | |
7661 | ||
7662 | return ctxt; | |
7663 | } | |
7664 | ||
8ec4722d MG |
7665 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
7666 | { | |
c9b8b07c | 7667 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
7668 | int cs_db, cs_l; |
7669 | ||
b3646477 | 7670 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
8ec4722d | 7671 | |
744e699c | 7672 | ctxt->gpa_available = false; |
adf52235 | 7673 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
7674 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
7675 | ||
adf52235 TY |
7676 | ctxt->eip = kvm_rip_read(vcpu); |
7677 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
7678 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 7679 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
7680 | cs_db ? X86EMUL_MODE_PROT32 : |
7681 | X86EMUL_MODE_PROT16; | |
a584539b | 7682 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
7683 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
7684 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 7685 | |
da6393cd WL |
7686 | ctxt->interruptibility = 0; |
7687 | ctxt->have_exception = false; | |
7688 | ctxt->exception.vector = -1; | |
7689 | ctxt->perm_ok = false; | |
7690 | ||
dd856efa | 7691 | init_decode_cache(ctxt); |
7ae441ea | 7692 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
7693 | } |
7694 | ||
9497e1f2 | 7695 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 7696 | { |
c9b8b07c | 7697 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
7698 | int ret; |
7699 | ||
7700 | init_emulate_ctxt(vcpu); | |
7701 | ||
9dac77fa AK |
7702 | ctxt->op_bytes = 2; |
7703 | ctxt->ad_bytes = 2; | |
7704 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 7705 | ret = emulate_int_real(ctxt, irq); |
63995653 | 7706 | |
9497e1f2 SC |
7707 | if (ret != X86EMUL_CONTINUE) { |
7708 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
7709 | } else { | |
7710 | ctxt->eip = ctxt->_eip; | |
7711 | kvm_rip_write(vcpu, ctxt->eip); | |
7712 | kvm_set_rflags(vcpu, ctxt->eflags); | |
7713 | } | |
63995653 MG |
7714 | } |
7715 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
7716 | ||
e615e355 DE |
7717 | static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, |
7718 | u8 ndata, u8 *insn_bytes, u8 insn_size) | |
19238e75 | 7719 | { |
19238e75 | 7720 | struct kvm_run *run = vcpu->run; |
e615e355 DE |
7721 | u64 info[5]; |
7722 | u8 info_start; | |
7723 | ||
7724 | /* | |
7725 | * Zero the whole array used to retrieve the exit info, as casting to | |
7726 | * u32 for select entries will leave some chunks uninitialized. | |
7727 | */ | |
7728 | memset(&info, 0, sizeof(info)); | |
7729 | ||
7730 | static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1], | |
7731 | &info[2], (u32 *)&info[3], | |
7732 | (u32 *)&info[4]); | |
19238e75 AL |
7733 | |
7734 | run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7735 | run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
e615e355 DE |
7736 | |
7737 | /* | |
7738 | * There's currently space for 13 entries, but 5 are used for the exit | |
7739 | * reason and info. Restrict to 4 to reduce the maintenance burden | |
7740 | * when expanding kvm_run.emulation_failure in the future. | |
7741 | */ | |
7742 | if (WARN_ON_ONCE(ndata > 4)) | |
7743 | ndata = 4; | |
7744 | ||
7745 | /* Always include the flags as a 'data' entry. */ | |
7746 | info_start = 1; | |
19238e75 AL |
7747 | run->emulation_failure.flags = 0; |
7748 | ||
7749 | if (insn_size) { | |
e615e355 DE |
7750 | BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + |
7751 | sizeof(run->emulation_failure.insn_bytes) != 16)); | |
7752 | info_start += 2; | |
19238e75 AL |
7753 | run->emulation_failure.flags |= |
7754 | KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; | |
7755 | run->emulation_failure.insn_size = insn_size; | |
7756 | memset(run->emulation_failure.insn_bytes, 0x90, | |
7757 | sizeof(run->emulation_failure.insn_bytes)); | |
e615e355 | 7758 | memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); |
19238e75 | 7759 | } |
e615e355 DE |
7760 | |
7761 | memcpy(&run->internal.data[info_start], info, sizeof(info)); | |
7762 | memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, | |
7763 | ndata * sizeof(data[0])); | |
7764 | ||
7765 | run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; | |
19238e75 AL |
7766 | } |
7767 | ||
e615e355 DE |
7768 | static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) |
7769 | { | |
7770 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
7771 | ||
7772 | prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, | |
7773 | ctxt->fetch.end - ctxt->fetch.data); | |
7774 | } | |
7775 | ||
7776 | void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, | |
7777 | u8 ndata) | |
7778 | { | |
7779 | prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); | |
7780 | } | |
7781 | EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); | |
7782 | ||
7783 | void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) | |
7784 | { | |
7785 | __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); | |
7786 | } | |
7787 | EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); | |
7788 | ||
e2366171 | 7789 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 7790 | { |
19238e75 AL |
7791 | struct kvm *kvm = vcpu->kvm; |
7792 | ||
6d77dbfc GN |
7793 | ++vcpu->stat.insn_emulation_fail; |
7794 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 7795 | |
42cbf068 SC |
7796 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
7797 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 7798 | return 1; |
42cbf068 | 7799 | } |
e2366171 | 7800 | |
19238e75 AL |
7801 | if (kvm->arch.exit_on_emulation_error || |
7802 | (emulation_type & EMULTYPE_SKIP)) { | |
e615e355 | 7803 | prepare_emulation_ctxt_failure_exit(vcpu); |
60fc3d02 | 7804 | return 0; |
738fece4 SC |
7805 | } |
7806 | ||
22da61c9 SC |
7807 | kvm_queue_exception(vcpu, UD_VECTOR); |
7808 | ||
b3646477 | 7809 | if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { |
e615e355 | 7810 | prepare_emulation_ctxt_failure_exit(vcpu); |
60fc3d02 | 7811 | return 0; |
fc3a9157 | 7812 | } |
e2366171 | 7813 | |
60fc3d02 | 7814 | return 1; |
6d77dbfc GN |
7815 | } |
7816 | ||
736c291c | 7817 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
7818 | bool write_fault_to_shadow_pgtable, |
7819 | int emulation_type) | |
a6f177ef | 7820 | { |
736c291c | 7821 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 7822 | kvm_pfn_t pfn; |
a6f177ef | 7823 | |
92daa48b | 7824 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
7825 | return false; |
7826 | ||
92daa48b SC |
7827 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7828 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7829 | return false; |
7830 | ||
44dd3ffa | 7831 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7832 | /* |
7833 | * Write permission should be allowed since only | |
7834 | * write access need to be emulated. | |
7835 | */ | |
736c291c | 7836 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 7837 | |
95b3cf69 XG |
7838 | /* |
7839 | * If the mapping is invalid in guest, let cpu retry | |
7840 | * it to generate fault. | |
7841 | */ | |
7842 | if (gpa == UNMAPPED_GVA) | |
7843 | return true; | |
7844 | } | |
a6f177ef | 7845 | |
8e3d9d06 XG |
7846 | /* |
7847 | * Do not retry the unhandleable instruction if it faults on the | |
7848 | * readonly host memory, otherwise it will goto a infinite loop: | |
7849 | * retry instruction -> write #PF -> emulation fail -> retry | |
7850 | * instruction -> ... | |
7851 | */ | |
7852 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
7853 | |
7854 | /* | |
7855 | * If the instruction failed on the error pfn, it can not be fixed, | |
7856 | * report the error to userspace. | |
7857 | */ | |
7858 | if (is_error_noslot_pfn(pfn)) | |
7859 | return false; | |
7860 | ||
7861 | kvm_release_pfn_clean(pfn); | |
7862 | ||
7863 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 7864 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
7865 | unsigned int indirect_shadow_pages; |
7866 | ||
531810ca | 7867 | write_lock(&vcpu->kvm->mmu_lock); |
95b3cf69 | 7868 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; |
531810ca | 7869 | write_unlock(&vcpu->kvm->mmu_lock); |
95b3cf69 XG |
7870 | |
7871 | if (indirect_shadow_pages) | |
7872 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
7873 | ||
a6f177ef | 7874 | return true; |
8e3d9d06 | 7875 | } |
a6f177ef | 7876 | |
95b3cf69 XG |
7877 | /* |
7878 | * if emulation was due to access to shadowed page table | |
7879 | * and it failed try to unshadow page and re-enter the | |
7880 | * guest to let CPU execute the instruction. | |
7881 | */ | |
7882 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
7883 | |
7884 | /* | |
7885 | * If the access faults on its page table, it can not | |
7886 | * be fixed by unprotecting shadow page and it should | |
7887 | * be reported to userspace. | |
7888 | */ | |
7889 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
7890 | } |
7891 | ||
1cb3f3ae | 7892 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 7893 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
7894 | { |
7895 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 7896 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
7897 | |
7898 | last_retry_eip = vcpu->arch.last_retry_eip; | |
7899 | last_retry_addr = vcpu->arch.last_retry_addr; | |
7900 | ||
7901 | /* | |
7902 | * If the emulation is caused by #PF and it is non-page_table | |
7903 | * writing instruction, it means the VM-EXIT is caused by shadow | |
7904 | * page protected, we can zap the shadow page and retry this | |
7905 | * instruction directly. | |
7906 | * | |
7907 | * Note: if the guest uses a non-page-table modifying instruction | |
7908 | * on the PDE that points to the instruction, then we will unmap | |
7909 | * the instruction and go to an infinite loop. So, we cache the | |
7910 | * last retried eip and the last fault address, if we meet the eip | |
7911 | * and the address again, we can break out of the potential infinite | |
7912 | * loop. | |
7913 | */ | |
7914 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
7915 | ||
92daa48b | 7916 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
7917 | return false; |
7918 | ||
92daa48b SC |
7919 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
7920 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
7921 | return false; |
7922 | ||
1cb3f3ae XG |
7923 | if (x86_page_table_writing_insn(ctxt)) |
7924 | return false; | |
7925 | ||
736c291c | 7926 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
7927 | return false; |
7928 | ||
7929 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 7930 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 7931 | |
44dd3ffa | 7932 | if (!vcpu->arch.mmu->direct_map) |
736c291c | 7933 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 7934 | |
22368028 | 7935 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
7936 | |
7937 | return true; | |
7938 | } | |
7939 | ||
716d51ab GN |
7940 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
7941 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
7942 | ||
dc87275f | 7943 | static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) |
a584539b | 7944 | { |
1270e647 | 7945 | trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); |
0d7ee6f4 | 7946 | |
dc87275f SC |
7947 | if (entering_smm) { |
7948 | vcpu->arch.hflags |= HF_SMM_MASK; | |
7949 | } else { | |
7950 | vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); | |
7951 | ||
c43203ca PB |
7952 | /* Process a latched INIT or SMI, if any. */ |
7953 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
37687c40 ML |
7954 | |
7955 | /* | |
7956 | * Even if KVM_SET_SREGS2 loaded PDPTRs out of band, | |
7957 | * on SMM exit we still need to reload them from | |
7958 | * guest memory | |
7959 | */ | |
7960 | vcpu->arch.pdptrs_from_userspace = false; | |
64d60670 | 7961 | } |
699023e2 PB |
7962 | |
7963 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7964 | } |
7965 | ||
4a1e10d5 PB |
7966 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
7967 | unsigned long *db) | |
7968 | { | |
7969 | u32 dr6 = 0; | |
7970 | int i; | |
7971 | u32 enable, rwlen; | |
7972 | ||
7973 | enable = dr7; | |
7974 | rwlen = dr7 >> 16; | |
7975 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
7976 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
7977 | dr6 |= (1 << i); | |
7978 | return dr6; | |
7979 | } | |
7980 | ||
120c2c4f | 7981 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
7982 | { |
7983 | struct kvm_run *kvm_run = vcpu->run; | |
7984 | ||
c8401dda | 7985 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
9a3ecd5e | 7986 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; |
d5d260c5 | 7987 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
7988 | kvm_run->debug.arch.exception = DB_VECTOR; |
7989 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 7990 | return 0; |
663f4c61 | 7991 | } |
120c2c4f | 7992 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 7993 | return 1; |
663f4c61 PB |
7994 | } |
7995 | ||
6affcbed KH |
7996 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
7997 | { | |
b3646477 | 7998 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
f8ea7c60 | 7999 | int r; |
6affcbed | 8000 | |
b3646477 | 8001 | r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); |
60fc3d02 | 8002 | if (unlikely(!r)) |
f8ea7c60 | 8003 | return 0; |
c8401dda PB |
8004 | |
8005 | /* | |
8006 | * rflags is the old, "raw" value of the flags. The new value has | |
8007 | * not been saved yet. | |
8008 | * | |
8009 | * This is correct even for TF set by the guest, because "the | |
8010 | * processor will not generate this exception after the instruction | |
8011 | * that sets the TF flag". | |
8012 | */ | |
8013 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 8014 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 8015 | return r; |
6affcbed KH |
8016 | } |
8017 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
8018 | ||
4a1e10d5 PB |
8019 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
8020 | { | |
4a1e10d5 PB |
8021 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
8022 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
8023 | struct kvm_run *kvm_run = vcpu->run; |
8024 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
8025 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
8026 | vcpu->arch.guest_debug_dr7, |
8027 | vcpu->arch.eff_db); | |
8028 | ||
8029 | if (dr6 != 0) { | |
9a3ecd5e | 8030 | kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; |
82b32774 | 8031 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
8032 | kvm_run->debug.arch.exception = DB_VECTOR; |
8033 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 8034 | *r = 0; |
4a1e10d5 PB |
8035 | return true; |
8036 | } | |
8037 | } | |
8038 | ||
4161a569 NA |
8039 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
8040 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
8041 | unsigned long eip = kvm_get_linear_rip(vcpu); |
8042 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
8043 | vcpu->arch.dr7, |
8044 | vcpu->arch.db); | |
8045 | ||
8046 | if (dr6 != 0) { | |
4d5523cf | 8047 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 8048 | *r = 1; |
4a1e10d5 PB |
8049 | return true; |
8050 | } | |
8051 | } | |
8052 | ||
8053 | return false; | |
8054 | } | |
8055 | ||
04789b66 LA |
8056 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
8057 | { | |
2d7921c4 AM |
8058 | switch (ctxt->opcode_len) { |
8059 | case 1: | |
8060 | switch (ctxt->b) { | |
8061 | case 0xe4: /* IN */ | |
8062 | case 0xe5: | |
8063 | case 0xec: | |
8064 | case 0xed: | |
8065 | case 0xe6: /* OUT */ | |
8066 | case 0xe7: | |
8067 | case 0xee: | |
8068 | case 0xef: | |
8069 | case 0x6c: /* INS */ | |
8070 | case 0x6d: | |
8071 | case 0x6e: /* OUTS */ | |
8072 | case 0x6f: | |
8073 | return true; | |
8074 | } | |
8075 | break; | |
8076 | case 2: | |
8077 | switch (ctxt->b) { | |
8078 | case 0x33: /* RDPMC */ | |
8079 | return true; | |
8080 | } | |
8081 | break; | |
04789b66 LA |
8082 | } |
8083 | ||
8084 | return false; | |
8085 | } | |
8086 | ||
4aa2691d WH |
8087 | /* |
8088 | * Decode to be emulated instruction. Return EMULATION_OK if success. | |
8089 | */ | |
8090 | int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, | |
8091 | void *insn, int insn_len) | |
8092 | { | |
8093 | int r = EMULATION_OK; | |
8094 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
8095 | ||
8096 | init_emulate_ctxt(vcpu); | |
8097 | ||
8098 | /* | |
8099 | * We will reenter on the same instruction since we do not set | |
8100 | * complete_userspace_io. This does not handle watchpoints yet, | |
8101 | * those would be handled in the emulate_ops. | |
8102 | */ | |
8103 | if (!(emulation_type & EMULTYPE_SKIP) && | |
8104 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
8105 | return r; | |
8106 | ||
b35491e6 | 8107 | r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); |
4aa2691d WH |
8108 | |
8109 | trace_kvm_emulate_insn_start(vcpu); | |
8110 | ++vcpu->stat.insn_emulation; | |
8111 | ||
8112 | return r; | |
8113 | } | |
8114 | EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); | |
8115 | ||
736c291c SC |
8116 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
8117 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 8118 | { |
95cb2295 | 8119 | int r; |
c9b8b07c | 8120 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 8121 | bool writeback = true; |
09e3e2a1 SC |
8122 | bool write_fault_to_spt; |
8123 | ||
b3646477 | 8124 | if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) |
09e3e2a1 | 8125 | return 1; |
bbd9b64e | 8126 | |
c595ceee PB |
8127 | vcpu->arch.l1tf_flush_l1d = true; |
8128 | ||
93c05d3e XG |
8129 | /* |
8130 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
8131 | * never reused. | |
8132 | */ | |
09e3e2a1 | 8133 | write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
93c05d3e | 8134 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
8d7d8102 | 8135 | |
571008da | 8136 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
4aa2691d | 8137 | kvm_clear_exception_queue(vcpu); |
4a1e10d5 | 8138 | |
4aa2691d WH |
8139 | r = x86_decode_emulated_instruction(vcpu, emulation_type, |
8140 | insn, insn_len); | |
1d2887e2 | 8141 | if (r != EMULATION_OK) { |
b4000606 | 8142 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
8143 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
8144 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 8145 | return 1; |
c83fad65 | 8146 | } |
736c291c SC |
8147 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
8148 | write_fault_to_spt, | |
8149 | emulation_type)) | |
60fc3d02 | 8150 | return 1; |
8530a79c | 8151 | if (ctxt->have_exception) { |
c8848cee JD |
8152 | /* |
8153 | * #UD should result in just EMULATION_FAILED, and trap-like | |
8154 | * exception should not be encountered during decode. | |
8155 | */ | |
8156 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
8157 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 8158 | inject_emulated_exception(vcpu); |
60fc3d02 | 8159 | return 1; |
8530a79c | 8160 | } |
e2366171 | 8161 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
8162 | } |
8163 | } | |
8164 | ||
42cbf068 SC |
8165 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
8166 | !is_vmware_backdoor_opcode(ctxt)) { | |
8167 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 8168 | return 1; |
42cbf068 | 8169 | } |
04789b66 | 8170 | |
1957aa63 SC |
8171 | /* |
8172 | * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks | |
8173 | * for kvm_skip_emulated_instruction(). The caller is responsible for | |
8174 | * updating interruptibility state and injecting single-step #DBs. | |
8175 | */ | |
ba8afb6b | 8176 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 8177 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
8178 | if (ctxt->eflags & X86_EFLAGS_RF) |
8179 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 8180 | return 1; |
ba8afb6b GN |
8181 | } |
8182 | ||
736c291c | 8183 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 8184 | return 1; |
1cb3f3ae | 8185 | |
7ae441ea | 8186 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 8187 | changes registers values during IO operation */ |
7ae441ea GN |
8188 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
8189 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 8190 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 8191 | } |
4d2179e1 | 8192 | |
5cd21917 | 8193 | restart: |
92daa48b SC |
8194 | if (emulation_type & EMULTYPE_PF) { |
8195 | /* Save the faulting GPA (cr2) in the address field */ | |
8196 | ctxt->exception.address = cr2_or_gpa; | |
8197 | ||
8198 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
8199 | if (vcpu->arch.mmu->direct_map) { | |
744e699c SC |
8200 | ctxt->gpa_available = true; |
8201 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
8202 | } |
8203 | } else { | |
8204 | /* Sanitize the address out of an abundance of paranoia. */ | |
8205 | ctxt->exception.address = 0; | |
8206 | } | |
0f89b207 | 8207 | |
9d74191a | 8208 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 8209 | |
775fde86 | 8210 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 8211 | return 1; |
775fde86 | 8212 | |
d2ddd1c4 | 8213 | if (r == EMULATION_FAILED) { |
736c291c | 8214 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 8215 | emulation_type)) |
60fc3d02 | 8216 | return 1; |
c3cd7ffa | 8217 | |
e2366171 | 8218 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
8219 | } |
8220 | ||
9d74191a | 8221 | if (ctxt->have_exception) { |
60fc3d02 | 8222 | r = 1; |
ef54bcfe PB |
8223 | if (inject_emulated_exception(vcpu)) |
8224 | return r; | |
d2ddd1c4 | 8225 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
8226 | if (!vcpu->arch.pio.in) { |
8227 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 8228 | vcpu->arch.pio.count = 0; |
0912c977 | 8229 | } else { |
7ae441ea | 8230 | writeback = false; |
716d51ab GN |
8231 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
8232 | } | |
60fc3d02 | 8233 | r = 0; |
7ae441ea | 8234 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
8235 | ++vcpu->stat.mmio_exits; |
8236 | ||
7ae441ea GN |
8237 | if (!vcpu->mmio_is_write) |
8238 | writeback = false; | |
60fc3d02 | 8239 | r = 0; |
716d51ab | 8240 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 8241 | } else if (r == EMULATION_RESTART) |
5cd21917 | 8242 | goto restart; |
d2ddd1c4 | 8243 | else |
60fc3d02 | 8244 | r = 1; |
f850e2e6 | 8245 | |
7ae441ea | 8246 | if (writeback) { |
b3646477 | 8247 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
9d74191a | 8248 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 8249 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 8250 | if (!ctxt->have_exception || |
75ee23b3 SC |
8251 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
8252 | kvm_rip_write(vcpu, ctxt->eip); | |
384dea1c | 8253 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 8254 | r = kvm_vcpu_do_singlestep(vcpu); |
afaf0b2f | 8255 | if (kvm_x86_ops.update_emulated_instruction) |
b3646477 | 8256 | static_call(kvm_x86_update_emulated_instruction)(vcpu); |
38827dbd | 8257 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 8258 | } |
6addfc42 PB |
8259 | |
8260 | /* | |
8261 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
8262 | * do nothing, and it will be requested again as soon as | |
8263 | * the shadow expires. But we still need to check here, | |
8264 | * because POPF has no interrupt shadow. | |
8265 | */ | |
8266 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
8267 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
8268 | } else |
8269 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
8270 | |
8271 | return r; | |
de7d789a | 8272 | } |
c60658d1 SC |
8273 | |
8274 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
8275 | { | |
8276 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
8277 | } | |
8278 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
8279 | ||
8280 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
8281 | void *insn, int insn_len) | |
8282 | { | |
8283 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
8284 | } | |
8285 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 8286 | |
8764ed55 SC |
8287 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
8288 | { | |
8289 | vcpu->arch.pio.count = 0; | |
8290 | return 1; | |
8291 | } | |
8292 | ||
45def77e SC |
8293 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
8294 | { | |
8295 | vcpu->arch.pio.count = 0; | |
8296 | ||
8297 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
8298 | return 1; | |
8299 | ||
8300 | return kvm_skip_emulated_instruction(vcpu); | |
8301 | } | |
8302 | ||
dca7f128 SC |
8303 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
8304 | unsigned short port) | |
de7d789a | 8305 | { |
de3cd117 | 8306 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
8307 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
8308 | ||
8764ed55 SC |
8309 | if (ret) |
8310 | return ret; | |
45def77e | 8311 | |
8764ed55 SC |
8312 | /* |
8313 | * Workaround userspace that relies on old KVM behavior of %rip being | |
8314 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
8315 | */ | |
8316 | if (port == 0x7e && | |
8317 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
8318 | vcpu->arch.complete_userspace_io = | |
8319 | complete_fast_pio_out_port_0x7e; | |
8320 | kvm_skip_emulated_instruction(vcpu); | |
8321 | } else { | |
45def77e SC |
8322 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8323 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
8324 | } | |
8764ed55 | 8325 | return 0; |
de7d789a | 8326 | } |
de7d789a | 8327 | |
8370c3d0 TL |
8328 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
8329 | { | |
8330 | unsigned long val; | |
8331 | ||
8332 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
8333 | BUG_ON(vcpu->arch.pio.count != 1); | |
8334 | ||
45def77e SC |
8335 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
8336 | vcpu->arch.pio.count = 0; | |
8337 | return 1; | |
8338 | } | |
8339 | ||
8370c3d0 | 8340 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 8341 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
8342 | |
8343 | /* | |
2e3bb4d8 | 8344 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform |
8370c3d0 TL |
8345 | * the copy and tracing |
8346 | */ | |
2e3bb4d8 | 8347 | emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); |
de3cd117 | 8348 | kvm_rax_write(vcpu, val); |
8370c3d0 | 8349 | |
45def77e | 8350 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
8351 | } |
8352 | ||
dca7f128 SC |
8353 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
8354 | unsigned short port) | |
8370c3d0 TL |
8355 | { |
8356 | unsigned long val; | |
8357 | int ret; | |
8358 | ||
8359 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 8360 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 8361 | |
2e3bb4d8 | 8362 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 8363 | if (ret) { |
de3cd117 | 8364 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
8365 | return ret; |
8366 | } | |
8367 | ||
45def77e | 8368 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
8369 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
8370 | ||
8371 | return 0; | |
8372 | } | |
dca7f128 SC |
8373 | |
8374 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
8375 | { | |
45def77e | 8376 | int ret; |
dca7f128 | 8377 | |
dca7f128 | 8378 | if (in) |
45def77e | 8379 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 8380 | else |
45def77e SC |
8381 | ret = kvm_fast_pio_out(vcpu, size, port); |
8382 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
8383 | } |
8384 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 8385 | |
251a5fd6 | 8386 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 8387 | { |
0a3aee0d | 8388 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 8389 | return 0; |
8cfdc000 ZA |
8390 | } |
8391 | ||
8392 | static void tsc_khz_changed(void *data) | |
c8076604 | 8393 | { |
8cfdc000 ZA |
8394 | struct cpufreq_freqs *freq = data; |
8395 | unsigned long khz = 0; | |
8396 | ||
8397 | if (data) | |
8398 | khz = freq->new; | |
8399 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
8400 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
8401 | if (!khz) | |
8402 | khz = tsc_khz; | |
0a3aee0d | 8403 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
8404 | } |
8405 | ||
5fa4ec9c | 8406 | #ifdef CONFIG_X86_64 |
0092e434 VK |
8407 | static void kvm_hyperv_tsc_notifier(void) |
8408 | { | |
0092e434 | 8409 | struct kvm *kvm; |
0092e434 VK |
8410 | int cpu; |
8411 | ||
0d9ce162 | 8412 | mutex_lock(&kvm_lock); |
0092e434 VK |
8413 | list_for_each_entry(kvm, &vm_list, vm_list) |
8414 | kvm_make_mclock_inprogress_request(kvm); | |
8415 | ||
6b6fcd28 | 8416 | /* no guest entries from this point */ |
0092e434 VK |
8417 | hyperv_stop_tsc_emulation(); |
8418 | ||
8419 | /* TSC frequency always matches when on Hyper-V */ | |
8420 | for_each_present_cpu(cpu) | |
8421 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
8422 | kvm_max_guest_tsc_khz = tsc_khz; | |
8423 | ||
8424 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
869b4421 | 8425 | __kvm_start_pvclock_update(kvm); |
0092e434 | 8426 | pvclock_update_vm_gtod_copy(kvm); |
6b6fcd28 | 8427 | kvm_end_pvclock_update(kvm); |
0092e434 | 8428 | } |
6b6fcd28 | 8429 | |
0d9ce162 | 8430 | mutex_unlock(&kvm_lock); |
0092e434 | 8431 | } |
5fa4ec9c | 8432 | #endif |
0092e434 | 8433 | |
df24014a | 8434 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 8435 | { |
c8076604 GH |
8436 | struct kvm *kvm; |
8437 | struct kvm_vcpu *vcpu; | |
8438 | int i, send_ipi = 0; | |
8439 | ||
8cfdc000 ZA |
8440 | /* |
8441 | * We allow guests to temporarily run on slowing clocks, | |
8442 | * provided we notify them after, or to run on accelerating | |
8443 | * clocks, provided we notify them before. Thus time never | |
8444 | * goes backwards. | |
8445 | * | |
8446 | * However, we have a problem. We can't atomically update | |
8447 | * the frequency of a given CPU from this function; it is | |
8448 | * merely a notifier, which can be called from any CPU. | |
8449 | * Changing the TSC frequency at arbitrary points in time | |
8450 | * requires a recomputation of local variables related to | |
8451 | * the TSC for each VCPU. We must flag these local variables | |
8452 | * to be updated and be sure the update takes place with the | |
8453 | * new frequency before any guests proceed. | |
8454 | * | |
8455 | * Unfortunately, the combination of hotplug CPU and frequency | |
8456 | * change creates an intractable locking scenario; the order | |
8457 | * of when these callouts happen is undefined with respect to | |
8458 | * CPU hotplug, and they can race with each other. As such, | |
8459 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
8460 | * undefined; you can actually have a CPU frequency change take | |
8461 | * place in between the computation of X and the setting of the | |
8462 | * variable. To protect against this problem, all updates of | |
8463 | * the per_cpu tsc_khz variable are done in an interrupt | |
8464 | * protected IPI, and all callers wishing to update the value | |
8465 | * must wait for a synchronous IPI to complete (which is trivial | |
8466 | * if the caller is on the CPU already). This establishes the | |
8467 | * necessary total order on variable updates. | |
8468 | * | |
8469 | * Note that because a guest time update may take place | |
8470 | * anytime after the setting of the VCPU's request bit, the | |
8471 | * correct TSC value must be set before the request. However, | |
8472 | * to ensure the update actually makes it to any guest which | |
8473 | * starts running in hardware virtualization between the set | |
8474 | * and the acquisition of the spinlock, we must also ping the | |
8475 | * CPU after setting the request bit. | |
8476 | * | |
8477 | */ | |
8478 | ||
df24014a | 8479 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 8480 | |
0d9ce162 | 8481 | mutex_lock(&kvm_lock); |
c8076604 | 8482 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 8483 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 8484 | if (vcpu->cpu != cpu) |
c8076604 | 8485 | continue; |
c285545f | 8486 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 8487 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 8488 | send_ipi = 1; |
c8076604 GH |
8489 | } |
8490 | } | |
0d9ce162 | 8491 | mutex_unlock(&kvm_lock); |
c8076604 GH |
8492 | |
8493 | if (freq->old < freq->new && send_ipi) { | |
8494 | /* | |
8495 | * We upscale the frequency. Must make the guest | |
8496 | * doesn't see old kvmclock values while running with | |
8497 | * the new frequency, otherwise we risk the guest sees | |
8498 | * time go backwards. | |
8499 | * | |
8500 | * In case we update the frequency for another cpu | |
8501 | * (which might be in guest context) send an interrupt | |
8502 | * to kick the cpu out of guest context. Next time | |
8503 | * guest context is entered kvmclock will be updated, | |
8504 | * so the guest will not see stale values. | |
8505 | */ | |
df24014a | 8506 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 8507 | } |
df24014a VK |
8508 | } |
8509 | ||
8510 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
8511 | void *data) | |
8512 | { | |
8513 | struct cpufreq_freqs *freq = data; | |
8514 | int cpu; | |
8515 | ||
8516 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
8517 | return 0; | |
8518 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
8519 | return 0; | |
8520 | ||
8521 | for_each_cpu(cpu, freq->policy->cpus) | |
8522 | __kvmclock_cpufreq_notifier(freq, cpu); | |
8523 | ||
c8076604 GH |
8524 | return 0; |
8525 | } | |
8526 | ||
8527 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
8528 | .notifier_call = kvmclock_cpufreq_notifier |
8529 | }; | |
8530 | ||
251a5fd6 | 8531 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 8532 | { |
251a5fd6 SAS |
8533 | tsc_khz_changed(NULL); |
8534 | return 0; | |
8cfdc000 ZA |
8535 | } |
8536 | ||
b820cc0c ZA |
8537 | static void kvm_timer_init(void) |
8538 | { | |
c285545f | 8539 | max_tsc_khz = tsc_khz; |
460dd42e | 8540 | |
b820cc0c | 8541 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f | 8542 | #ifdef CONFIG_CPU_FREQ |
aaec7c03 | 8543 | struct cpufreq_policy *policy; |
758f588d BP |
8544 | int cpu; |
8545 | ||
3e26f230 | 8546 | cpu = get_cpu(); |
aaec7c03 | 8547 | policy = cpufreq_cpu_get(cpu); |
9a11997e WL |
8548 | if (policy) { |
8549 | if (policy->cpuinfo.max_freq) | |
8550 | max_tsc_khz = policy->cpuinfo.max_freq; | |
8551 | cpufreq_cpu_put(policy); | |
8552 | } | |
3e26f230 | 8553 | put_cpu(); |
c285545f | 8554 | #endif |
b820cc0c ZA |
8555 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
8556 | CPUFREQ_TRANSITION_NOTIFIER); | |
8557 | } | |
460dd42e | 8558 | |
73c1b41e | 8559 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 8560 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
8561 | } |
8562 | ||
dd60d217 AK |
8563 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
8564 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 8565 | |
f5132b01 | 8566 | int kvm_is_in_guest(void) |
ff9d07a0 | 8567 | { |
086c9855 | 8568 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
8569 | } |
8570 | ||
8571 | static int kvm_is_user_mode(void) | |
8572 | { | |
8573 | int user_mode = 3; | |
dcf46b94 | 8574 | |
086c9855 | 8575 | if (__this_cpu_read(current_vcpu)) |
b3646477 | 8576 | user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); |
dcf46b94 | 8577 | |
ff9d07a0 ZY |
8578 | return user_mode != 0; |
8579 | } | |
8580 | ||
8581 | static unsigned long kvm_get_guest_ip(void) | |
8582 | { | |
8583 | unsigned long ip = 0; | |
dcf46b94 | 8584 | |
086c9855 AS |
8585 | if (__this_cpu_read(current_vcpu)) |
8586 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 8587 | |
ff9d07a0 ZY |
8588 | return ip; |
8589 | } | |
8590 | ||
8479e04e LK |
8591 | static void kvm_handle_intel_pt_intr(void) |
8592 | { | |
8593 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
8594 | ||
8595 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
8596 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
8597 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
8598 | } | |
8599 | ||
ff9d07a0 ZY |
8600 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
8601 | .is_in_guest = kvm_is_in_guest, | |
8602 | .is_user_mode = kvm_is_user_mode, | |
8603 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 8604 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
8605 | }; |
8606 | ||
16e8d74d MT |
8607 | #ifdef CONFIG_X86_64 |
8608 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
8609 | { | |
d828199e MT |
8610 | struct kvm *kvm; |
8611 | ||
8612 | struct kvm_vcpu *vcpu; | |
8613 | int i; | |
8614 | ||
0d9ce162 | 8615 | mutex_lock(&kvm_lock); |
d828199e MT |
8616 | list_for_each_entry(kvm, &vm_list, vm_list) |
8617 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 8618 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 8619 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 8620 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
8621 | } |
8622 | ||
8623 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
8624 | ||
3f804f6d TG |
8625 | /* |
8626 | * Indirection to move queue_work() out of the tk_core.seq write held | |
8627 | * region to prevent possible deadlocks against time accessors which | |
8628 | * are invoked with work related locks held. | |
8629 | */ | |
8630 | static void pvclock_irq_work_fn(struct irq_work *w) | |
8631 | { | |
8632 | queue_work(system_long_wq, &pvclock_gtod_work); | |
8633 | } | |
8634 | ||
8635 | static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); | |
8636 | ||
16e8d74d MT |
8637 | /* |
8638 | * Notification about pvclock gtod data update. | |
8639 | */ | |
8640 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
8641 | void *priv) | |
8642 | { | |
8643 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
8644 | struct timekeeper *tk = priv; | |
8645 | ||
8646 | update_pvclock_gtod(tk); | |
8647 | ||
3f804f6d TG |
8648 | /* |
8649 | * Disable master clock if host does not trust, or does not use, | |
8650 | * TSC based clocksource. Delegate queue_work() to irq_work as | |
8651 | * this is invoked with tk_core.seq write held. | |
16e8d74d | 8652 | */ |
b0c39dc6 | 8653 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d | 8654 | atomic_read(&kvm_guest_has_master_clock) != 0) |
3f804f6d | 8655 | irq_work_queue(&pvclock_irq_work); |
16e8d74d MT |
8656 | return 0; |
8657 | } | |
8658 | ||
8659 | static struct notifier_block pvclock_gtod_notifier = { | |
8660 | .notifier_call = pvclock_gtod_notify, | |
8661 | }; | |
8662 | #endif | |
8663 | ||
f8c16bba | 8664 | int kvm_arch_init(void *opaque) |
043405e1 | 8665 | { |
d008dfdb | 8666 | struct kvm_x86_init_ops *ops = opaque; |
b820cc0c | 8667 | int r; |
f8c16bba | 8668 | |
afaf0b2f | 8669 | if (kvm_x86_ops.hardware_enable) { |
9dadfc4a | 8670 | pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name); |
56c6d28a ZX |
8671 | r = -EEXIST; |
8672 | goto out; | |
f8c16bba ZX |
8673 | } |
8674 | ||
8675 | if (!ops->cpu_has_kvm_support()) { | |
9dadfc4a SC |
8676 | pr_err_ratelimited("kvm: no hardware support for '%s'\n", |
8677 | ops->runtime_ops->name); | |
56c6d28a ZX |
8678 | r = -EOPNOTSUPP; |
8679 | goto out; | |
f8c16bba ZX |
8680 | } |
8681 | if (ops->disabled_by_bios()) { | |
9dadfc4a SC |
8682 | pr_err_ratelimited("kvm: support for '%s' disabled by bios\n", |
8683 | ops->runtime_ops->name); | |
56c6d28a ZX |
8684 | r = -EOPNOTSUPP; |
8685 | goto out; | |
f8c16bba ZX |
8686 | } |
8687 | ||
b666a4b6 MO |
8688 | /* |
8689 | * KVM explicitly assumes that the guest has an FPU and | |
8690 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
8691 | * vCPU's FPU state as a fxregs_state struct. | |
8692 | */ | |
8693 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
8694 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
8695 | r = -EOPNOTSUPP; | |
8696 | goto out; | |
8697 | } | |
8698 | ||
013f6a5d | 8699 | r = -ENOMEM; |
ed8e4812 | 8700 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
8701 | __alignof__(struct fpu), SLAB_ACCOUNT, |
8702 | NULL); | |
8703 | if (!x86_fpu_cache) { | |
8704 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
8705 | goto out; | |
8706 | } | |
8707 | ||
c9b8b07c SC |
8708 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
8709 | if (!x86_emulator_cache) { | |
8710 | pr_err("kvm: failed to allocate cache for x86 emulator\n"); | |
8711 | goto out_free_x86_fpu_cache; | |
8712 | } | |
8713 | ||
7e34fbd0 SC |
8714 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
8715 | if (!user_return_msrs) { | |
8716 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); | |
c9b8b07c | 8717 | goto out_free_x86_emulator_cache; |
013f6a5d | 8718 | } |
e5fda4bb | 8719 | kvm_nr_uret_msrs = 0; |
013f6a5d | 8720 | |
97db56ce AK |
8721 | r = kvm_mmu_module_init(); |
8722 | if (r) | |
013f6a5d | 8723 | goto out_free_percpu; |
97db56ce | 8724 | |
b820cc0c | 8725 | kvm_timer_init(); |
c8076604 | 8726 | |
ff9d07a0 ZY |
8727 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
8728 | ||
cfc48181 | 8729 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 8730 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
cfc48181 SC |
8731 | supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
8732 | } | |
2acf923e | 8733 | |
0c5f81da WL |
8734 | if (pi_inject_timer == -1) |
8735 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
8736 | #ifdef CONFIG_X86_64 |
8737 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 8738 | |
5fa4ec9c | 8739 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 8740 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
8741 | #endif |
8742 | ||
f8c16bba | 8743 | return 0; |
56c6d28a | 8744 | |
013f6a5d | 8745 | out_free_percpu: |
7e34fbd0 | 8746 | free_percpu(user_return_msrs); |
c9b8b07c SC |
8747 | out_free_x86_emulator_cache: |
8748 | kmem_cache_destroy(x86_emulator_cache); | |
b666a4b6 MO |
8749 | out_free_x86_fpu_cache: |
8750 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 8751 | out: |
56c6d28a | 8752 | return r; |
043405e1 | 8753 | } |
8776e519 | 8754 | |
f8c16bba ZX |
8755 | void kvm_arch_exit(void) |
8756 | { | |
0092e434 | 8757 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 8758 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
8759 | clear_hv_tscchange_cb(); |
8760 | #endif | |
cef84c30 | 8761 | kvm_lapic_exit(); |
ff9d07a0 ZY |
8762 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
8763 | ||
888d256e JK |
8764 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
8765 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
8766 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 8767 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
8768 | #ifdef CONFIG_X86_64 |
8769 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
3f804f6d | 8770 | irq_work_sync(&pvclock_irq_work); |
594b27e6 | 8771 | cancel_work_sync(&pvclock_gtod_work); |
16e8d74d | 8772 | #endif |
afaf0b2f | 8773 | kvm_x86_ops.hardware_enable = NULL; |
56c6d28a | 8774 | kvm_mmu_module_exit(); |
7e34fbd0 | 8775 | free_percpu(user_return_msrs); |
dfdc0a71 | 8776 | kmem_cache_destroy(x86_emulator_cache); |
b666a4b6 | 8777 | kmem_cache_destroy(x86_fpu_cache); |
b59b153d | 8778 | #ifdef CONFIG_KVM_XEN |
c462f859 | 8779 | static_key_deferred_flush(&kvm_xen_enabled); |
7d6bbebb | 8780 | WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); |
b59b153d | 8781 | #endif |
56c6d28a | 8782 | } |
f8c16bba | 8783 | |
872f36eb | 8784 | static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) |
8776e519 HB |
8785 | { |
8786 | ++vcpu->stat.halt_exits; | |
35754c98 | 8787 | if (lapic_in_kernel(vcpu)) { |
647daca2 | 8788 | vcpu->arch.mp_state = state; |
8776e519 HB |
8789 | return 1; |
8790 | } else { | |
647daca2 | 8791 | vcpu->run->exit_reason = reason; |
8776e519 HB |
8792 | return 0; |
8793 | } | |
8794 | } | |
647daca2 TL |
8795 | |
8796 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) | |
8797 | { | |
8798 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); | |
8799 | } | |
5cb56059 JS |
8800 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
8801 | ||
8802 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
8803 | { | |
6affcbed KH |
8804 | int ret = kvm_skip_emulated_instruction(vcpu); |
8805 | /* | |
8806 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
8807 | * KVM_EXIT_DEBUG here. | |
8808 | */ | |
8809 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 8810 | } |
8776e519 HB |
8811 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
8812 | ||
647daca2 TL |
8813 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) |
8814 | { | |
8815 | int ret = kvm_skip_emulated_instruction(vcpu); | |
8816 | ||
8817 | return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; | |
8818 | } | |
8819 | EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); | |
8820 | ||
8ef81a9a | 8821 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8822 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
8823 | unsigned long clock_type) | |
8824 | { | |
8825 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 8826 | struct timespec64 ts; |
80fbd89c | 8827 | u64 cycle; |
55dd00a7 MT |
8828 | int ret; |
8829 | ||
8830 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
8831 | return -KVM_EOPNOTSUPP; | |
8832 | ||
7ca7f3b9 | 8833 | if (!kvm_get_walltime_and_clockread(&ts, &cycle)) |
55dd00a7 MT |
8834 | return -KVM_EOPNOTSUPP; |
8835 | ||
8836 | clock_pairing.sec = ts.tv_sec; | |
8837 | clock_pairing.nsec = ts.tv_nsec; | |
8838 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
8839 | clock_pairing.flags = 0; | |
bcbfbd8e | 8840 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
8841 | |
8842 | ret = 0; | |
8843 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
8844 | sizeof(struct kvm_clock_pairing))) | |
8845 | ret = -KVM_EFAULT; | |
8846 | ||
8847 | return ret; | |
8848 | } | |
8ef81a9a | 8849 | #endif |
55dd00a7 | 8850 | |
6aef266c SV |
8851 | /* |
8852 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
8853 | * | |
8854 | * @apicid - apicid of vcpu to be kicked. | |
8855 | */ | |
8856 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
8857 | { | |
24d2166b | 8858 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 8859 | |
150a84fe | 8860 | lapic_irq.shorthand = APIC_DEST_NOSHORT; |
c96001c5 | 8861 | lapic_irq.dest_mode = APIC_DEST_PHYSICAL; |
ebd28fcb | 8862 | lapic_irq.level = 0; |
24d2166b | 8863 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 8864 | lapic_irq.msi_redir_hint = false; |
6aef266c | 8865 | |
24d2166b | 8866 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 8867 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
8868 | } |
8869 | ||
4e19c36f SS |
8870 | bool kvm_apicv_activated(struct kvm *kvm) |
8871 | { | |
8872 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
8873 | } | |
8874 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
8875 | ||
4651fc56 | 8876 | static void kvm_apicv_init(struct kvm *kvm) |
4e19c36f | 8877 | { |
187c8833 | 8878 | init_rwsem(&kvm->arch.apicv_update_lock); |
b0a1637f | 8879 | |
4651fc56 | 8880 | if (enable_apicv) |
4e19c36f SS |
8881 | clear_bit(APICV_INHIBIT_REASON_DISABLE, |
8882 | &kvm->arch.apicv_inhibit_reasons); | |
8883 | else | |
8884 | set_bit(APICV_INHIBIT_REASON_DISABLE, | |
8885 | &kvm->arch.apicv_inhibit_reasons); | |
8886 | } | |
4e19c36f | 8887 | |
4a7132ef | 8888 | static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) |
71506297 WL |
8889 | { |
8890 | struct kvm_vcpu *target = NULL; | |
8891 | struct kvm_apic_map *map; | |
8892 | ||
4a7132ef WL |
8893 | vcpu->stat.directed_yield_attempted++; |
8894 | ||
72b268a8 WL |
8895 | if (single_task_running()) |
8896 | goto no_yield; | |
8897 | ||
71506297 | 8898 | rcu_read_lock(); |
4a7132ef | 8899 | map = rcu_dereference(vcpu->kvm->arch.apic_map); |
71506297 WL |
8900 | |
8901 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
8902 | target = map->phys_map[dest_id]->vcpu; | |
8903 | ||
8904 | rcu_read_unlock(); | |
8905 | ||
4a7132ef WL |
8906 | if (!target || !READ_ONCE(target->ready)) |
8907 | goto no_yield; | |
8908 | ||
a1fa4cbd WL |
8909 | /* Ignore requests to yield to self */ |
8910 | if (vcpu == target) | |
8911 | goto no_yield; | |
8912 | ||
4a7132ef WL |
8913 | if (kvm_vcpu_yield_to(target) <= 0) |
8914 | goto no_yield; | |
8915 | ||
8916 | vcpu->stat.directed_yield_successful++; | |
8917 | ||
8918 | no_yield: | |
8919 | return; | |
71506297 WL |
8920 | } |
8921 | ||
0dbb1123 AK |
8922 | static int complete_hypercall_exit(struct kvm_vcpu *vcpu) |
8923 | { | |
8924 | u64 ret = vcpu->run->hypercall.ret; | |
8925 | ||
8926 | if (!is_64_bit_mode(vcpu)) | |
8927 | ret = (u32)ret; | |
8928 | kvm_rax_write(vcpu, ret); | |
8929 | ++vcpu->stat.hypercalls; | |
8930 | return kvm_skip_emulated_instruction(vcpu); | |
8931 | } | |
8932 | ||
8776e519 HB |
8933 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
8934 | { | |
8935 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 8936 | int op_64_bit; |
8776e519 | 8937 | |
23200b7a JM |
8938 | if (kvm_xen_hypercall_enabled(vcpu->kvm)) |
8939 | return kvm_xen_hypercall(vcpu); | |
8940 | ||
8f014550 | 8941 | if (kvm_hv_hypercall_enabled(vcpu)) |
696ca779 | 8942 | return kvm_hv_hypercall(vcpu); |
55cd8e5a | 8943 | |
de3cd117 SC |
8944 | nr = kvm_rax_read(vcpu); |
8945 | a0 = kvm_rbx_read(vcpu); | |
8946 | a1 = kvm_rcx_read(vcpu); | |
8947 | a2 = kvm_rdx_read(vcpu); | |
8948 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 8949 | |
229456fc | 8950 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 8951 | |
a449c7aa NA |
8952 | op_64_bit = is_64_bit_mode(vcpu); |
8953 | if (!op_64_bit) { | |
8776e519 HB |
8954 | nr &= 0xFFFFFFFF; |
8955 | a0 &= 0xFFFFFFFF; | |
8956 | a1 &= 0xFFFFFFFF; | |
8957 | a2 &= 0xFFFFFFFF; | |
8958 | a3 &= 0xFFFFFFFF; | |
8959 | } | |
8960 | ||
b3646477 | 8961 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { |
07708c4a | 8962 | ret = -KVM_EPERM; |
696ca779 | 8963 | goto out; |
07708c4a JK |
8964 | } |
8965 | ||
66570e96 OU |
8966 | ret = -KVM_ENOSYS; |
8967 | ||
8776e519 | 8968 | switch (nr) { |
b93463aa AK |
8969 | case KVM_HC_VAPIC_POLL_IRQ: |
8970 | ret = 0; | |
8971 | break; | |
6aef266c | 8972 | case KVM_HC_KICK_CPU: |
66570e96 OU |
8973 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
8974 | break; | |
8975 | ||
6aef266c | 8976 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); |
4a7132ef | 8977 | kvm_sched_yield(vcpu, a1); |
6aef266c SV |
8978 | ret = 0; |
8979 | break; | |
8ef81a9a | 8980 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
8981 | case KVM_HC_CLOCK_PAIRING: |
8982 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
8983 | break; | |
1ed199a4 | 8984 | #endif |
4180bf1b | 8985 | case KVM_HC_SEND_IPI: |
66570e96 OU |
8986 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
8987 | break; | |
8988 | ||
4180bf1b WL |
8989 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
8990 | break; | |
71506297 | 8991 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
8992 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
8993 | break; | |
8994 | ||
4a7132ef | 8995 | kvm_sched_yield(vcpu, a0); |
71506297 WL |
8996 | ret = 0; |
8997 | break; | |
0dbb1123 AK |
8998 | case KVM_HC_MAP_GPA_RANGE: { |
8999 | u64 gpa = a0, npages = a1, attrs = a2; | |
9000 | ||
9001 | ret = -KVM_ENOSYS; | |
9002 | if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) | |
9003 | break; | |
9004 | ||
9005 | if (!PAGE_ALIGNED(gpa) || !npages || | |
9006 | gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { | |
9007 | ret = -KVM_EINVAL; | |
9008 | break; | |
9009 | } | |
9010 | ||
9011 | vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; | |
9012 | vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; | |
9013 | vcpu->run->hypercall.args[0] = gpa; | |
9014 | vcpu->run->hypercall.args[1] = npages; | |
9015 | vcpu->run->hypercall.args[2] = attrs; | |
9016 | vcpu->run->hypercall.longmode = op_64_bit; | |
9017 | vcpu->arch.complete_userspace_io = complete_hypercall_exit; | |
9018 | return 0; | |
9019 | } | |
8776e519 HB |
9020 | default: |
9021 | ret = -KVM_ENOSYS; | |
9022 | break; | |
9023 | } | |
696ca779 | 9024 | out: |
a449c7aa NA |
9025 | if (!op_64_bit) |
9026 | ret = (u32)ret; | |
de3cd117 | 9027 | kvm_rax_write(vcpu, ret); |
6356ee0c | 9028 | |
f11c3a8d | 9029 | ++vcpu->stat.hypercalls; |
6356ee0c | 9030 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
9031 | } |
9032 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
9033 | ||
b6785def | 9034 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 9035 | { |
d6aa1000 | 9036 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 9037 | char instruction[3]; |
5fdbf976 | 9038 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 9039 | |
b3646477 | 9040 | static_call(kvm_x86_patch_hypercall)(vcpu, instruction); |
8776e519 | 9041 | |
ce2e852e DV |
9042 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
9043 | &ctxt->exception); | |
8776e519 HB |
9044 | } |
9045 | ||
851ba692 | 9046 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9047 | { |
782d422b MG |
9048 | return vcpu->run->request_interrupt_window && |
9049 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
9050 | } |
9051 | ||
851ba692 | 9052 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9053 | { |
851ba692 AK |
9054 | struct kvm_run *kvm_run = vcpu->run; |
9055 | ||
f1c6366e TL |
9056 | /* |
9057 | * if_flag is obsolete and useless, so do not bother | |
9058 | * setting it for SEV-ES guests. Userspace can just | |
9059 | * use kvm_run->ready_for_interrupt_injection. | |
9060 | */ | |
9061 | kvm_run->if_flag = !vcpu->arch.guest_state_protected | |
9062 | && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; | |
9063 | ||
2d3ad1f4 | 9064 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 9065 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
9066 | kvm_run->ready_for_interrupt_injection = |
9067 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 9068 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
15aad3be CQ |
9069 | |
9070 | if (is_smm(vcpu)) | |
9071 | kvm_run->flags |= KVM_RUN_X86_SMM; | |
b6c7a5dc HB |
9072 | } |
9073 | ||
95ba8273 GN |
9074 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
9075 | { | |
9076 | int max_irr, tpr; | |
9077 | ||
afaf0b2f | 9078 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
9079 | return; |
9080 | ||
bce87cce | 9081 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
9082 | return; |
9083 | ||
d62caabb AS |
9084 | if (vcpu->arch.apicv_active) |
9085 | return; | |
9086 | ||
8db3baa2 GN |
9087 | if (!vcpu->arch.apic->vapic_addr) |
9088 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
9089 | else | |
9090 | max_irr = -1; | |
95ba8273 GN |
9091 | |
9092 | if (max_irr != -1) | |
9093 | max_irr >>= 4; | |
9094 | ||
9095 | tpr = kvm_lapic_get_cr8(vcpu); | |
9096 | ||
b3646477 | 9097 | static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); |
95ba8273 GN |
9098 | } |
9099 | ||
b97f0745 | 9100 | |
cb6a32c2 SC |
9101 | int kvm_check_nested_events(struct kvm_vcpu *vcpu) |
9102 | { | |
cb6a32c2 SC |
9103 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
9104 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
9105 | return 1; | |
9106 | } | |
9107 | ||
9108 | return kvm_x86_ops.nested_ops->check_events(vcpu); | |
9109 | } | |
9110 | ||
b97f0745 ML |
9111 | static void kvm_inject_exception(struct kvm_vcpu *vcpu) |
9112 | { | |
9113 | if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) | |
9114 | vcpu->arch.exception.error_code = false; | |
9115 | static_call(kvm_x86_queue_exception)(vcpu); | |
9116 | } | |
9117 | ||
a5f6909a | 9118 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) |
95ba8273 | 9119 | { |
b6b8a145 | 9120 | int r; |
c6b22f59 | 9121 | bool can_inject = true; |
b6b8a145 | 9122 | |
95ba8273 | 9123 | /* try to reinject previous events if any */ |
664f8e26 | 9124 | |
c6b22f59 | 9125 | if (vcpu->arch.exception.injected) { |
b97f0745 | 9126 | kvm_inject_exception(vcpu); |
c6b22f59 PB |
9127 | can_inject = false; |
9128 | } | |
664f8e26 | 9129 | /* |
a042c26f LA |
9130 | * Do not inject an NMI or interrupt if there is a pending |
9131 | * exception. Exceptions and interrupts are recognized at | |
9132 | * instruction boundaries, i.e. the start of an instruction. | |
9133 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
9134 | * NMIs and interrupts, i.e. traps are recognized before an | |
9135 | * NMI/interrupt that's pending on the same instruction. | |
9136 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
9137 | * priority, but are only generated (pended) during instruction | |
9138 | * execution, i.e. a pending fault-like exception means the | |
9139 | * fault occurred on the *previous* instruction and must be | |
9140 | * serviced prior to recognizing any new events in order to | |
9141 | * fully complete the previous instruction. | |
664f8e26 | 9142 | */ |
1a680e35 | 9143 | else if (!vcpu->arch.exception.pending) { |
c6b22f59 | 9144 | if (vcpu->arch.nmi_injected) { |
b3646477 | 9145 | static_call(kvm_x86_set_nmi)(vcpu); |
c6b22f59 PB |
9146 | can_inject = false; |
9147 | } else if (vcpu->arch.interrupt.injected) { | |
b3646477 | 9148 | static_call(kvm_x86_set_irq)(vcpu); |
c6b22f59 PB |
9149 | can_inject = false; |
9150 | } | |
664f8e26 WL |
9151 | } |
9152 | ||
3b82b8d7 SC |
9153 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
9154 | vcpu->arch.exception.pending); | |
9155 | ||
1a680e35 LA |
9156 | /* |
9157 | * Call check_nested_events() even if we reinjected a previous event | |
9158 | * in order for caller to determine if it should require immediate-exit | |
9159 | * from L2 to L1 due to pending L1 events which require exit | |
9160 | * from L2 to L1. | |
9161 | */ | |
56083bdf | 9162 | if (is_guest_mode(vcpu)) { |
cb6a32c2 | 9163 | r = kvm_check_nested_events(vcpu); |
c9d40913 | 9164 | if (r < 0) |
a5f6909a | 9165 | goto out; |
664f8e26 WL |
9166 | } |
9167 | ||
9168 | /* try to inject new event if pending */ | |
b59bb7bd | 9169 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
9170 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
9171 | vcpu->arch.exception.has_error_code, | |
9172 | vcpu->arch.exception.error_code); | |
d6e8c854 | 9173 | |
664f8e26 WL |
9174 | vcpu->arch.exception.pending = false; |
9175 | vcpu->arch.exception.injected = true; | |
9176 | ||
d6e8c854 NA |
9177 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
9178 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
9179 | X86_EFLAGS_RF); | |
9180 | ||
f10c729f | 9181 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
f10c729f JM |
9182 | kvm_deliver_exception_payload(vcpu); |
9183 | if (vcpu->arch.dr7 & DR7_GD) { | |
9184 | vcpu->arch.dr7 &= ~DR7_GD; | |
9185 | kvm_update_dr7(vcpu); | |
9186 | } | |
6bdf0662 NA |
9187 | } |
9188 | ||
b97f0745 | 9189 | kvm_inject_exception(vcpu); |
c6b22f59 | 9190 | can_inject = false; |
1a680e35 LA |
9191 | } |
9192 | ||
61e5f69e ML |
9193 | /* Don't inject interrupts if the user asked to avoid doing so */ |
9194 | if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) | |
9195 | return 0; | |
9196 | ||
c9d40913 PB |
9197 | /* |
9198 | * Finally, inject interrupt events. If an event cannot be injected | |
9199 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
9200 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
9201 | * and can architecturally be injected, but we cannot do it right now: | |
9202 | * an interrupt could have arrived just now and we have to inject it | |
9203 | * as a vmexit, or there could already an event in the queue, which is | |
9204 | * indicated by can_inject. In that case we request an immediate exit | |
9205 | * in order to make progress and get back here for another iteration. | |
9206 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
9207 | */ | |
9208 | if (vcpu->arch.smi_pending) { | |
b3646477 | 9209 | r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 9210 | if (r < 0) |
a5f6909a | 9211 | goto out; |
c9d40913 PB |
9212 | if (r) { |
9213 | vcpu->arch.smi_pending = false; | |
9214 | ++vcpu->arch.smi_count; | |
9215 | enter_smm(vcpu); | |
9216 | can_inject = false; | |
9217 | } else | |
b3646477 | 9218 | static_call(kvm_x86_enable_smi_window)(vcpu); |
c9d40913 PB |
9219 | } |
9220 | ||
9221 | if (vcpu->arch.nmi_pending) { | |
b3646477 | 9222 | r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 9223 | if (r < 0) |
a5f6909a | 9224 | goto out; |
c9d40913 PB |
9225 | if (r) { |
9226 | --vcpu->arch.nmi_pending; | |
9227 | vcpu->arch.nmi_injected = true; | |
b3646477 | 9228 | static_call(kvm_x86_set_nmi)(vcpu); |
c9d40913 | 9229 | can_inject = false; |
b3646477 | 9230 | WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); |
c9d40913 PB |
9231 | } |
9232 | if (vcpu->arch.nmi_pending) | |
b3646477 | 9233 | static_call(kvm_x86_enable_nmi_window)(vcpu); |
c9d40913 | 9234 | } |
1a680e35 | 9235 | |
c9d40913 | 9236 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
b3646477 | 9237 | r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 9238 | if (r < 0) |
a5f6909a | 9239 | goto out; |
c9d40913 PB |
9240 | if (r) { |
9241 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); | |
b3646477 JB |
9242 | static_call(kvm_x86_set_irq)(vcpu); |
9243 | WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); | |
c9d40913 PB |
9244 | } |
9245 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
b3646477 | 9246 | static_call(kvm_x86_enable_irq_window)(vcpu); |
95ba8273 | 9247 | } |
ee2cd4b7 | 9248 | |
c9d40913 PB |
9249 | if (is_guest_mode(vcpu) && |
9250 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
9251 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
9252 | *req_immediate_exit = true; | |
9253 | ||
9254 | WARN_ON(vcpu->arch.exception.pending); | |
a5f6909a | 9255 | return 0; |
c9d40913 | 9256 | |
a5f6909a JM |
9257 | out: |
9258 | if (r == -EBUSY) { | |
9259 | *req_immediate_exit = true; | |
9260 | r = 0; | |
9261 | } | |
9262 | return r; | |
95ba8273 GN |
9263 | } |
9264 | ||
7460fb4a AK |
9265 | static void process_nmi(struct kvm_vcpu *vcpu) |
9266 | { | |
9267 | unsigned limit = 2; | |
9268 | ||
9269 | /* | |
9270 | * x86 is limited to one NMI running, and one NMI pending after it. | |
9271 | * If an NMI is already in progress, limit further NMIs to just one. | |
9272 | * Otherwise, allow two (and we'll inject the first one immediately). | |
9273 | */ | |
b3646477 | 9274 | if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a AK |
9275 | limit = 1; |
9276 | ||
9277 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
9278 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
9279 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9280 | } | |
9281 | ||
ee2cd4b7 | 9282 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
9283 | { |
9284 | u32 flags = 0; | |
9285 | flags |= seg->g << 23; | |
9286 | flags |= seg->db << 22; | |
9287 | flags |= seg->l << 21; | |
9288 | flags |= seg->avl << 20; | |
9289 | flags |= seg->present << 15; | |
9290 | flags |= seg->dpl << 13; | |
9291 | flags |= seg->s << 12; | |
9292 | flags |= seg->type << 8; | |
9293 | return flags; | |
9294 | } | |
9295 | ||
ee2cd4b7 | 9296 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
9297 | { |
9298 | struct kvm_segment seg; | |
9299 | int offset; | |
9300 | ||
9301 | kvm_get_segment(vcpu, &seg, n); | |
9302 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
9303 | ||
9304 | if (n < 3) | |
9305 | offset = 0x7f84 + n * 12; | |
9306 | else | |
9307 | offset = 0x7f2c + (n - 3) * 12; | |
9308 | ||
9309 | put_smstate(u32, buf, offset + 8, seg.base); | |
9310 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 9311 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
9312 | } |
9313 | ||
efbb288a | 9314 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 9315 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
9316 | { |
9317 | struct kvm_segment seg; | |
9318 | int offset; | |
9319 | u16 flags; | |
9320 | ||
9321 | kvm_get_segment(vcpu, &seg, n); | |
9322 | offset = 0x7e00 + n * 16; | |
9323 | ||
ee2cd4b7 | 9324 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
9325 | put_smstate(u16, buf, offset, seg.selector); |
9326 | put_smstate(u16, buf, offset + 2, flags); | |
9327 | put_smstate(u32, buf, offset + 4, seg.limit); | |
9328 | put_smstate(u64, buf, offset + 8, seg.base); | |
9329 | } | |
efbb288a | 9330 | #endif |
660a5d51 | 9331 | |
ee2cd4b7 | 9332 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
9333 | { |
9334 | struct desc_ptr dt; | |
9335 | struct kvm_segment seg; | |
9336 | unsigned long val; | |
9337 | int i; | |
9338 | ||
9339 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
9340 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
9341 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
9342 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
9343 | ||
9344 | for (i = 0; i < 8; i++) | |
27b4a9c4 | 9345 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
9346 | |
9347 | kvm_get_dr(vcpu, 6, &val); | |
9348 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
9349 | kvm_get_dr(vcpu, 7, &val); | |
9350 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
9351 | ||
9352 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
9353 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
9354 | put_smstate(u32, buf, 0x7f64, seg.base); | |
9355 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 9356 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
9357 | |
9358 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
9359 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
9360 | put_smstate(u32, buf, 0x7f80, seg.base); | |
9361 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 9362 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 | 9363 | |
b3646477 | 9364 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
9365 | put_smstate(u32, buf, 0x7f74, dt.address); |
9366 | put_smstate(u32, buf, 0x7f70, dt.size); | |
9367 | ||
b3646477 | 9368 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
9369 | put_smstate(u32, buf, 0x7f58, dt.address); |
9370 | put_smstate(u32, buf, 0x7f54, dt.size); | |
9371 | ||
9372 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 9373 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
9374 | |
9375 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
9376 | ||
9377 | /* revision id */ | |
9378 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
9379 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
9380 | } | |
9381 | ||
b68f3cc7 | 9382 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 9383 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 9384 | { |
660a5d51 PB |
9385 | struct desc_ptr dt; |
9386 | struct kvm_segment seg; | |
9387 | unsigned long val; | |
9388 | int i; | |
9389 | ||
9390 | for (i = 0; i < 16; i++) | |
27b4a9c4 | 9391 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
9392 | |
9393 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
9394 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
9395 | ||
9396 | kvm_get_dr(vcpu, 6, &val); | |
9397 | put_smstate(u64, buf, 0x7f68, val); | |
9398 | kvm_get_dr(vcpu, 7, &val); | |
9399 | put_smstate(u64, buf, 0x7f60, val); | |
9400 | ||
9401 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
9402 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
9403 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
9404 | ||
9405 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
9406 | ||
9407 | /* revision id */ | |
9408 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
9409 | ||
9410 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
9411 | ||
9412 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
9413 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 9414 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
9415 | put_smstate(u32, buf, 0x7e94, seg.limit); |
9416 | put_smstate(u64, buf, 0x7e98, seg.base); | |
9417 | ||
b3646477 | 9418 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
9419 | put_smstate(u32, buf, 0x7e84, dt.size); |
9420 | put_smstate(u64, buf, 0x7e88, dt.address); | |
9421 | ||
9422 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
9423 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 9424 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
9425 | put_smstate(u32, buf, 0x7e74, seg.limit); |
9426 | put_smstate(u64, buf, 0x7e78, seg.base); | |
9427 | ||
b3646477 | 9428 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
9429 | put_smstate(u32, buf, 0x7e64, dt.size); |
9430 | put_smstate(u64, buf, 0x7e68, dt.address); | |
9431 | ||
9432 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 9433 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 9434 | } |
b68f3cc7 | 9435 | #endif |
660a5d51 | 9436 | |
ee2cd4b7 | 9437 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 9438 | { |
660a5d51 | 9439 | struct kvm_segment cs, ds; |
18c3626e | 9440 | struct desc_ptr dt; |
dbc4739b | 9441 | unsigned long cr0; |
660a5d51 | 9442 | char buf[512]; |
660a5d51 | 9443 | |
660a5d51 | 9444 | memset(buf, 0, 512); |
b68f3cc7 | 9445 | #ifdef CONFIG_X86_64 |
d6321d49 | 9446 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 9447 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 9448 | else |
b68f3cc7 | 9449 | #endif |
ee2cd4b7 | 9450 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 9451 | |
0234bf88 | 9452 | /* |
ecc513e5 SC |
9453 | * Give enter_smm() a chance to make ISA-specific changes to the vCPU |
9454 | * state (e.g. leave guest mode) after we've saved the state into the | |
9455 | * SMM state-save area. | |
0234bf88 | 9456 | */ |
ecc513e5 | 9457 | static_call(kvm_x86_enter_smm)(vcpu, buf); |
0234bf88 | 9458 | |
dc87275f | 9459 | kvm_smm_changed(vcpu, true); |
54bf36aa | 9460 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 | 9461 | |
b3646477 | 9462 | if (static_call(kvm_x86_get_nmi_mask)(vcpu)) |
660a5d51 PB |
9463 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; |
9464 | else | |
b3646477 | 9465 | static_call(kvm_x86_set_nmi_mask)(vcpu, true); |
660a5d51 PB |
9466 | |
9467 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
9468 | kvm_rip_write(vcpu, 0x8000); | |
9469 | ||
9470 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
b3646477 | 9471 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
660a5d51 PB |
9472 | vcpu->arch.cr0 = cr0; |
9473 | ||
b3646477 | 9474 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
660a5d51 | 9475 | |
18c3626e PB |
9476 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
9477 | dt.address = dt.size = 0; | |
b3646477 | 9478 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
18c3626e | 9479 | |
996ff542 | 9480 | kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
660a5d51 PB |
9481 | |
9482 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
9483 | cs.base = vcpu->arch.smbase; | |
9484 | ||
9485 | ds.selector = 0; | |
9486 | ds.base = 0; | |
9487 | ||
9488 | cs.limit = ds.limit = 0xffffffff; | |
9489 | cs.type = ds.type = 0x3; | |
9490 | cs.dpl = ds.dpl = 0; | |
9491 | cs.db = ds.db = 0; | |
9492 | cs.s = ds.s = 1; | |
9493 | cs.l = ds.l = 0; | |
9494 | cs.g = ds.g = 1; | |
9495 | cs.avl = ds.avl = 0; | |
9496 | cs.present = ds.present = 1; | |
9497 | cs.unusable = ds.unusable = 0; | |
9498 | cs.padding = ds.padding = 0; | |
9499 | ||
9500 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
9501 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
9502 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
9503 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
9504 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
9505 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
9506 | ||
b68f3cc7 | 9507 | #ifdef CONFIG_X86_64 |
d6321d49 | 9508 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
b3646477 | 9509 | static_call(kvm_x86_set_efer)(vcpu, 0); |
b68f3cc7 | 9510 | #endif |
660a5d51 | 9511 | |
aedbaf4f | 9512 | kvm_update_cpuid_runtime(vcpu); |
660a5d51 | 9513 | kvm_mmu_reset_context(vcpu); |
64d60670 PB |
9514 | } |
9515 | ||
ee2cd4b7 | 9516 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
9517 | { |
9518 | vcpu->arch.smi_pending = true; | |
9519 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9520 | } | |
9521 | ||
7ee30bc1 NNL |
9522 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
9523 | unsigned long *vcpu_bitmap) | |
9524 | { | |
620b2438 | 9525 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); |
7ee30bc1 NNL |
9526 | } |
9527 | ||
2860c4b1 PB |
9528 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
9529 | { | |
9530 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
9531 | } | |
9532 | ||
8df14af4 SS |
9533 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
9534 | { | |
06ef8134 ML |
9535 | bool activate; |
9536 | ||
8df14af4 SS |
9537 | if (!lapic_in_kernel(vcpu)) |
9538 | return; | |
9539 | ||
187c8833 | 9540 | down_read(&vcpu->kvm->arch.apicv_update_lock); |
b0a1637f | 9541 | |
06ef8134 ML |
9542 | activate = kvm_apicv_activated(vcpu->kvm); |
9543 | if (vcpu->arch.apicv_active == activate) | |
9544 | goto out; | |
9545 | ||
9546 | vcpu->arch.apicv_active = activate; | |
8df14af4 | 9547 | kvm_apic_update_apicv(vcpu); |
b3646477 | 9548 | static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); |
bca66dbc VK |
9549 | |
9550 | /* | |
9551 | * When APICv gets disabled, we may still have injected interrupts | |
9552 | * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was | |
9553 | * still active when the interrupt got accepted. Make sure | |
9554 | * inject_pending_event() is called to check for that. | |
9555 | */ | |
9556 | if (!vcpu->arch.apicv_active) | |
9557 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b0a1637f | 9558 | |
06ef8134 | 9559 | out: |
187c8833 | 9560 | up_read(&vcpu->kvm->arch.apicv_update_lock); |
8df14af4 SS |
9561 | } |
9562 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
9563 | ||
b0a1637f | 9564 | void __kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) |
8df14af4 | 9565 | { |
b0a1637f | 9566 | unsigned long old, new; |
8e205a6b | 9567 | |
187c8833 SC |
9568 | lockdep_assert_held_write(&kvm->arch.apicv_update_lock); |
9569 | ||
afaf0b2f | 9570 | if (!kvm_x86_ops.check_apicv_inhibit_reasons || |
b3646477 | 9571 | !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) |
ef8efd7a SS |
9572 | return; |
9573 | ||
b0a1637f ML |
9574 | old = new = kvm->arch.apicv_inhibit_reasons; |
9575 | ||
9576 | if (activate) | |
9577 | __clear_bit(bit, &new); | |
9578 | else | |
9579 | __set_bit(bit, &new); | |
8e205a6b | 9580 | |
36222b11 ML |
9581 | if (!!old != !!new) { |
9582 | trace_kvm_apicv_update_request(activate, bit); | |
ee49a893 SC |
9583 | /* |
9584 | * Kick all vCPUs before setting apicv_inhibit_reasons to avoid | |
9585 | * false positives in the sanity check WARN in svm_vcpu_run(). | |
9586 | * This task will wait for all vCPUs to ack the kick IRQ before | |
9587 | * updating apicv_inhibit_reasons, and all other vCPUs will | |
9588 | * block on acquiring apicv_update_lock so that vCPUs can't | |
9589 | * redo svm_vcpu_run() without seeing the new inhibit state. | |
9590 | * | |
9591 | * Note, holding apicv_update_lock and taking it in the read | |
9592 | * side (handling the request) also prevents other vCPUs from | |
9593 | * servicing the request with a stale apicv_inhibit_reasons. | |
9594 | */ | |
36222b11 | 9595 | kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); |
b0a1637f | 9596 | kvm->arch.apicv_inhibit_reasons = new; |
36222b11 ML |
9597 | if (new) { |
9598 | unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); | |
36222b11 ML |
9599 | kvm_zap_gfn_range(kvm, gfn, gfn+1); |
9600 | } | |
b0a1637f ML |
9601 | } else |
9602 | kvm->arch.apicv_inhibit_reasons = new; | |
9603 | } | |
9604 | EXPORT_SYMBOL_GPL(__kvm_request_apicv_update); | |
7d611233 | 9605 | |
b0a1637f ML |
9606 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) |
9607 | { | |
187c8833 | 9608 | down_write(&kvm->arch.apicv_update_lock); |
b0a1637f | 9609 | __kvm_request_apicv_update(kvm, activate, bit); |
187c8833 | 9610 | up_write(&kvm->arch.apicv_update_lock); |
8df14af4 SS |
9611 | } |
9612 | EXPORT_SYMBOL_GPL(kvm_request_apicv_update); | |
9613 | ||
3d81bc7e | 9614 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 9615 | { |
dcbd3e49 | 9616 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 9617 | return; |
c7c9c56c | 9618 | |
6308630b | 9619 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 9620 | |
b053b2ae | 9621 | if (irqchip_split(vcpu->kvm)) |
6308630b | 9622 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 9623 | else { |
fa59cc00 | 9624 | if (vcpu->arch.apicv_active) |
b3646477 | 9625 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
e97f852f WL |
9626 | if (ioapic_in_kernel(vcpu->kvm)) |
9627 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 9628 | } |
e40ff1d6 LA |
9629 | |
9630 | if (is_guest_mode(vcpu)) | |
9631 | vcpu->arch.load_eoi_exitmap_pending = true; | |
9632 | else | |
9633 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
9634 | } | |
9635 | ||
9636 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
9637 | { | |
9638 | u64 eoi_exit_bitmap[4]; | |
9639 | ||
9640 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
9641 | return; | |
9642 | ||
f2bc14b6 VK |
9643 | if (to_hv_vcpu(vcpu)) |
9644 | bitmap_or((ulong *)eoi_exit_bitmap, | |
9645 | vcpu->arch.ioapic_handled_vectors, | |
9646 | to_hv_synic(vcpu)->vec_bitmap, 256); | |
9647 | ||
b3646477 | 9648 | static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); |
c7c9c56c YZ |
9649 | } |
9650 | ||
e649b3f0 ET |
9651 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
9652 | unsigned long start, unsigned long end) | |
b1394e74 RK |
9653 | { |
9654 | unsigned long apic_address; | |
9655 | ||
9656 | /* | |
9657 | * The physical address of apic access page is stored in the VMCS. | |
9658 | * Update it when it becomes invalid. | |
9659 | */ | |
9660 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
9661 | if (start <= apic_address && apic_address < end) | |
9662 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
9663 | } | |
9664 | ||
4256f43f TC |
9665 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
9666 | { | |
35754c98 | 9667 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
9668 | return; |
9669 | ||
afaf0b2f | 9670 | if (!kvm_x86_ops.set_apic_access_page_addr) |
4256f43f TC |
9671 | return; |
9672 | ||
b3646477 | 9673 | static_call(kvm_x86_set_apic_access_page_addr)(vcpu); |
4256f43f | 9674 | } |
4256f43f | 9675 | |
d264ee0c SC |
9676 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
9677 | { | |
9678 | smp_send_reschedule(vcpu->cpu); | |
9679 | } | |
9680 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
9681 | ||
9357d939 | 9682 | /* |
362c698f | 9683 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
9684 | * exiting to the userspace. Otherwise, the value will be returned to the |
9685 | * userspace. | |
9686 | */ | |
851ba692 | 9687 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
9688 | { |
9689 | int r; | |
62a193ed MG |
9690 | bool req_int_win = |
9691 | dm_request_for_irq_injection(vcpu) && | |
9692 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 9693 | fastpath_t exit_fastpath; |
62a193ed | 9694 | |
730dca42 | 9695 | bool req_immediate_exit = false; |
b6c7a5dc | 9696 | |
fb04a1ed PX |
9697 | /* Forbid vmenter if vcpu dirty ring is soft-full */ |
9698 | if (unlikely(vcpu->kvm->dirty_ring_size && | |
9699 | kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { | |
9700 | vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; | |
9701 | trace_kvm_dirty_ring_exit(vcpu); | |
9702 | r = 0; | |
9703 | goto out; | |
9704 | } | |
9705 | ||
2fa6e1e1 | 9706 | if (kvm_request_pending(vcpu)) { |
67369273 SC |
9707 | if (kvm_check_request(KVM_REQ_VM_BUGGED, vcpu)) { |
9708 | r = -EIO; | |
9709 | goto out; | |
9710 | } | |
729c15c2 | 9711 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
9a78e158 | 9712 | if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { |
671ddc70 JM |
9713 | r = 0; |
9714 | goto out; | |
9715 | } | |
9716 | } | |
a8eeb04a | 9717 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 9718 | kvm_mmu_unload(vcpu); |
a8eeb04a | 9719 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 9720 | __kvm_migrate_timers(vcpu); |
d828199e | 9721 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
6b6fcd28 | 9722 | kvm_update_masterclock(vcpu->kvm); |
0061d53d MT |
9723 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
9724 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
9725 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
9726 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
9727 | if (unlikely(r)) |
9728 | goto out; | |
9729 | } | |
a8eeb04a | 9730 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 9731 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
9732 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
9733 | kvm_mmu_load_pgd(vcpu); | |
eeeb4f67 | 9734 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { |
7780938c | 9735 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 SC |
9736 | |
9737 | /* Flushing all ASIDs flushes the current ASID... */ | |
9738 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
9739 | } | |
9740 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
9741 | kvm_vcpu_flush_tlb_current(vcpu); | |
07ffaf34 | 9742 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) |
0baedd79 | 9743 | kvm_vcpu_flush_tlb_guest(vcpu); |
eeeb4f67 | 9744 | |
a8eeb04a | 9745 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 9746 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
9747 | r = 0; |
9748 | goto out; | |
9749 | } | |
a8eeb04a | 9750 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
cb6a32c2 SC |
9751 | if (is_guest_mode(vcpu)) { |
9752 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
9753 | } else { | |
9754 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; | |
9755 | vcpu->mmio_needed = 0; | |
9756 | r = 0; | |
9757 | goto out; | |
9758 | } | |
71c4dfaf | 9759 | } |
af585b92 GN |
9760 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
9761 | /* Page is swapped out. Do synthetic halt */ | |
9762 | vcpu->arch.apf.halted = true; | |
9763 | r = 1; | |
9764 | goto out; | |
9765 | } | |
c9aaa895 GC |
9766 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
9767 | record_steal_time(vcpu); | |
64d60670 PB |
9768 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
9769 | process_smi(vcpu); | |
7460fb4a AK |
9770 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
9771 | process_nmi(vcpu); | |
f5132b01 | 9772 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 9773 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 9774 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 9775 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
9776 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
9777 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
9778 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 9779 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
9780 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
9781 | vcpu->run->eoi.vector = | |
9782 | vcpu->arch.pending_ioapic_eoi; | |
9783 | r = 0; | |
9784 | goto out; | |
9785 | } | |
9786 | } | |
3d81bc7e YZ |
9787 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
9788 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
9789 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
9790 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
9791 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
9792 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
9793 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
9794 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
9795 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
9796 | r = 0; | |
9797 | goto out; | |
9798 | } | |
e516cebb AS |
9799 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
9800 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
9801 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
9802 | r = 0; | |
9803 | goto out; | |
9804 | } | |
db397571 | 9805 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
9ff5e030 VK |
9806 | struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); |
9807 | ||
db397571 | 9808 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; |
9ff5e030 | 9809 | vcpu->run->hyperv = hv_vcpu->exit; |
db397571 AS |
9810 | r = 0; |
9811 | goto out; | |
9812 | } | |
f3b138c5 AS |
9813 | |
9814 | /* | |
9815 | * KVM_REQ_HV_STIMER has to be processed after | |
9816 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
9817 | * depend on the guest clock being up-to-date | |
9818 | */ | |
1f4b34f8 AS |
9819 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
9820 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
9821 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
9822 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
9823 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
9824 | kvm_check_async_pf_completion(vcpu); | |
1a155254 | 9825 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
b3646477 | 9826 | static_call(kvm_x86_msr_filter_changed)(vcpu); |
a85863c2 MS |
9827 | |
9828 | if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) | |
9829 | static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); | |
2f52d58c | 9830 | } |
b93463aa | 9831 | |
40da8ccd DW |
9832 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || |
9833 | kvm_xen_has_interrupt(vcpu)) { | |
0f1e261e | 9834 | ++vcpu->stat.req_event; |
4fe09bcf JM |
9835 | r = kvm_apic_accept_events(vcpu); |
9836 | if (r < 0) { | |
9837 | r = 0; | |
9838 | goto out; | |
9839 | } | |
66450a21 JK |
9840 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
9841 | r = 1; | |
9842 | goto out; | |
9843 | } | |
9844 | ||
a5f6909a JM |
9845 | r = inject_pending_event(vcpu, &req_immediate_exit); |
9846 | if (r < 0) { | |
9847 | r = 0; | |
9848 | goto out; | |
9849 | } | |
c9d40913 | 9850 | if (req_int_win) |
b3646477 | 9851 | static_call(kvm_x86_enable_irq_window)(vcpu); |
b463a6f7 AK |
9852 | |
9853 | if (kvm_lapic_enabled(vcpu)) { | |
9854 | update_cr8_intercept(vcpu); | |
9855 | kvm_lapic_sync_to_vapic(vcpu); | |
9856 | } | |
9857 | } | |
9858 | ||
d8368af8 AK |
9859 | r = kvm_mmu_reload(vcpu); |
9860 | if (unlikely(r)) { | |
d905c069 | 9861 | goto cancel_injection; |
d8368af8 AK |
9862 | } |
9863 | ||
b6c7a5dc HB |
9864 | preempt_disable(); |
9865 | ||
b3646477 | 9866 | static_call(kvm_x86_prepare_guest_switch)(vcpu); |
b95234c8 PB |
9867 | |
9868 | /* | |
9869 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
9870 | * IPI are then delayed after guest entry, which ensures that they | |
9871 | * result in virtual interrupt delivery. | |
9872 | */ | |
9873 | local_irq_disable(); | |
6b7e2d09 XG |
9874 | vcpu->mode = IN_GUEST_MODE; |
9875 | ||
01b71917 MT |
9876 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
9877 | ||
0f127d12 | 9878 | /* |
b95234c8 | 9879 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 9880 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 9881 | * |
81b01667 | 9882 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
9883 | * pairs with the memory barrier implicit in pi_test_and_set_on |
9884 | * (see vmx_deliver_posted_interrupt). | |
9885 | * | |
9886 | * 3) This also orders the write to mode from any reads to the page | |
9887 | * tables done while the VCPU is running. Please see the comment | |
9888 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 9889 | */ |
01b71917 | 9890 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 9891 | |
b95234c8 PB |
9892 | /* |
9893 | * This handles the case where a posted interrupt was | |
9894 | * notified with kvm_vcpu_kick. | |
9895 | */ | |
fa59cc00 | 9896 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
b3646477 | 9897 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); |
32f88400 | 9898 | |
5a9f5443 | 9899 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 9900 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9901 | smp_wmb(); |
6c142801 AK |
9902 | local_irq_enable(); |
9903 | preempt_enable(); | |
01b71917 | 9904 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 9905 | r = 1; |
d905c069 | 9906 | goto cancel_injection; |
6c142801 AK |
9907 | } |
9908 | ||
c43203ca PB |
9909 | if (req_immediate_exit) { |
9910 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 9911 | static_call(kvm_x86_request_immediate_exit)(vcpu); |
c43203ca | 9912 | } |
d6185f20 | 9913 | |
2620fe26 SC |
9914 | fpregs_assert_state_consistent(); |
9915 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
9916 | switch_fpu_return(); | |
5f409e20 | 9917 | |
42dbaa5a | 9918 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
9919 | set_debugreg(0, 7); |
9920 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
9921 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
9922 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
9923 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
f85d4016 LJ |
9924 | } else if (unlikely(hw_breakpoint_active())) { |
9925 | set_debugreg(0, 7); | |
42dbaa5a | 9926 | } |
b6c7a5dc | 9927 | |
d89d04ab | 9928 | for (;;) { |
ee49a893 SC |
9929 | /* |
9930 | * Assert that vCPU vs. VM APICv state is consistent. An APICv | |
9931 | * update must kick and wait for all vCPUs before toggling the | |
9932 | * per-VM state, and responsing vCPUs must wait for the update | |
9933 | * to complete before servicing KVM_REQ_APICV_UPDATE. | |
9934 | */ | |
9935 | WARN_ON_ONCE(kvm_apicv_activated(vcpu->kvm) != kvm_vcpu_apicv_active(vcpu)); | |
9936 | ||
d89d04ab PB |
9937 | exit_fastpath = static_call(kvm_x86_run)(vcpu); |
9938 | if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) | |
9939 | break; | |
9940 | ||
9941 | if (unlikely(kvm_vcpu_exit_request(vcpu))) { | |
9942 | exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; | |
9943 | break; | |
9944 | } | |
9945 | ||
9946 | if (vcpu->arch.apicv_active) | |
9947 | static_call(kvm_x86_sync_pir_to_irr)(vcpu); | |
9948 | } | |
b6c7a5dc | 9949 | |
c77fb5fe PB |
9950 | /* |
9951 | * Do this here before restoring debug registers on the host. And | |
9952 | * since we do this before handling the vmexit, a DR access vmexit | |
9953 | * can (a) read the correct value of the debug registers, (b) set | |
9954 | * KVM_DEBUGREG_WONT_EXIT again. | |
9955 | */ | |
9956 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 9957 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
b3646477 | 9958 | static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); |
70e4da7a | 9959 | kvm_update_dr0123(vcpu); |
70e4da7a | 9960 | kvm_update_dr7(vcpu); |
c77fb5fe PB |
9961 | } |
9962 | ||
24f1e32c FW |
9963 | /* |
9964 | * If the guest has used debug registers, at least dr7 | |
9965 | * will be disabled while returning to the host. | |
9966 | * If we don't have active breakpoints in the host, we don't | |
9967 | * care about the messed up debug address registers. But if | |
9968 | * we have some of them active, restore the old state. | |
9969 | */ | |
59d8eb53 | 9970 | if (hw_breakpoint_active()) |
24f1e32c | 9971 | hw_breakpoint_restore(); |
42dbaa5a | 9972 | |
c967118d | 9973 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 9974 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 9975 | |
6b7e2d09 | 9976 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 9977 | smp_wmb(); |
a547c6db | 9978 | |
b3646477 | 9979 | static_call(kvm_x86_handle_exit_irqoff)(vcpu); |
b6c7a5dc | 9980 | |
d7a08882 SC |
9981 | /* |
9982 | * Consume any pending interrupts, including the possible source of | |
9983 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
9984 | * An instruction is required after local_irq_enable() to fully unblock | |
9985 | * interrupts on processors that implement an interrupt shadow, the | |
9986 | * stat.exits increment will do nicely. | |
9987 | */ | |
9988 | kvm_before_interrupt(vcpu); | |
9989 | local_irq_enable(); | |
b6c7a5dc | 9990 | ++vcpu->stat.exits; |
d7a08882 SC |
9991 | local_irq_disable(); |
9992 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 9993 | |
16045714 WL |
9994 | /* |
9995 | * Wait until after servicing IRQs to account guest time so that any | |
9996 | * ticks that occurred while running the guest are properly accounted | |
9997 | * to the guest. Waiting until IRQs are enabled degrades the accuracy | |
9998 | * of accounting via context tracking, but the loss of accuracy is | |
9999 | * acceptable for all known use cases. | |
10000 | */ | |
10001 | vtime_account_guest_exit(); | |
10002 | ||
ec0671d5 WL |
10003 | if (lapic_in_kernel(vcpu)) { |
10004 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
10005 | if (delta != S64_MIN) { | |
10006 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
10007 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
10008 | } | |
10009 | } | |
b6c7a5dc | 10010 | |
f2485b3e | 10011 | local_irq_enable(); |
b6c7a5dc HB |
10012 | preempt_enable(); |
10013 | ||
f656ce01 | 10014 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 10015 | |
b6c7a5dc HB |
10016 | /* |
10017 | * Profile KVM exit RIPs: | |
10018 | */ | |
10019 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
10020 | unsigned long rip = kvm_rip_read(vcpu); |
10021 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
10022 | } |
10023 | ||
cc578287 ZA |
10024 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
10025 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 10026 | |
5cfb1d5a MT |
10027 | if (vcpu->arch.apic_attention) |
10028 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 10029 | |
b3646477 | 10030 | r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); |
d905c069 MT |
10031 | return r; |
10032 | ||
10033 | cancel_injection: | |
8081ad06 SC |
10034 | if (req_immediate_exit) |
10035 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 10036 | static_call(kvm_x86_cancel_injection)(vcpu); |
ae7a2a3f MT |
10037 | if (unlikely(vcpu->arch.apic_attention)) |
10038 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
10039 | out: |
10040 | return r; | |
10041 | } | |
b6c7a5dc | 10042 | |
362c698f PB |
10043 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
10044 | { | |
bf9f6ac8 | 10045 | if (!kvm_arch_vcpu_runnable(vcpu) && |
b3646477 | 10046 | (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { |
9c8fd1ba PB |
10047 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
10048 | kvm_vcpu_block(vcpu); | |
10049 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 | 10050 | |
afaf0b2f | 10051 | if (kvm_x86_ops.post_block) |
b3646477 | 10052 | static_call(kvm_x86_post_block)(vcpu); |
bf9f6ac8 | 10053 | |
9c8fd1ba PB |
10054 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
10055 | return 1; | |
10056 | } | |
362c698f | 10057 | |
4fe09bcf JM |
10058 | if (kvm_apic_accept_events(vcpu) < 0) |
10059 | return 0; | |
362c698f PB |
10060 | switch(vcpu->arch.mp_state) { |
10061 | case KVM_MP_STATE_HALTED: | |
647daca2 | 10062 | case KVM_MP_STATE_AP_RESET_HOLD: |
362c698f PB |
10063 | vcpu->arch.pv.pv_unhalted = false; |
10064 | vcpu->arch.mp_state = | |
10065 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 10066 | fallthrough; |
362c698f PB |
10067 | case KVM_MP_STATE_RUNNABLE: |
10068 | vcpu->arch.apf.halted = false; | |
10069 | break; | |
10070 | case KVM_MP_STATE_INIT_RECEIVED: | |
10071 | break; | |
10072 | default: | |
10073 | return -EINTR; | |
362c698f PB |
10074 | } |
10075 | return 1; | |
10076 | } | |
09cec754 | 10077 | |
5d9bc648 PB |
10078 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
10079 | { | |
56083bdf | 10080 | if (is_guest_mode(vcpu)) |
cb6a32c2 | 10081 | kvm_check_nested_events(vcpu); |
0ad3bed6 | 10082 | |
5d9bc648 PB |
10083 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
10084 | !vcpu->arch.apf.halted); | |
10085 | } | |
10086 | ||
362c698f | 10087 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
10088 | { |
10089 | int r; | |
f656ce01 | 10090 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 10091 | |
f656ce01 | 10092 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 10093 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 10094 | |
362c698f | 10095 | for (;;) { |
58f800d5 | 10096 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 10097 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 10098 | } else { |
362c698f | 10099 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
10100 | } |
10101 | ||
09cec754 GN |
10102 | if (r <= 0) |
10103 | break; | |
10104 | ||
084071d5 | 10105 | kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); |
09cec754 GN |
10106 | if (kvm_cpu_has_pending_timer(vcpu)) |
10107 | kvm_inject_pending_timer_irqs(vcpu); | |
10108 | ||
782d422b MG |
10109 | if (dm_request_for_irq_injection(vcpu) && |
10110 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
10111 | r = 0; |
10112 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 10113 | ++vcpu->stat.request_irq_exits; |
362c698f | 10114 | break; |
09cec754 | 10115 | } |
af585b92 | 10116 | |
f3020b88 | 10117 | if (__xfer_to_guest_mode_work_pending()) { |
f656ce01 | 10118 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
72c3c0fe TG |
10119 | r = xfer_to_guest_mode_handle_work(vcpu); |
10120 | if (r) | |
10121 | return r; | |
f656ce01 | 10122 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 10123 | } |
b6c7a5dc HB |
10124 | } |
10125 | ||
f656ce01 | 10126 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
10127 | |
10128 | return r; | |
10129 | } | |
10130 | ||
716d51ab GN |
10131 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
10132 | { | |
10133 | int r; | |
60fc3d02 | 10134 | |
716d51ab | 10135 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
0ce97a2b | 10136 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab | 10137 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
60fc3d02 | 10138 | return r; |
716d51ab GN |
10139 | } |
10140 | ||
10141 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
10142 | { | |
10143 | BUG_ON(!vcpu->arch.pio.count); | |
10144 | ||
10145 | return complete_emulated_io(vcpu); | |
10146 | } | |
10147 | ||
f78146b0 AK |
10148 | /* |
10149 | * Implements the following, as a state machine: | |
10150 | * | |
10151 | * read: | |
10152 | * for each fragment | |
87da7e66 XG |
10153 | * for each mmio piece in the fragment |
10154 | * write gpa, len | |
10155 | * exit | |
10156 | * copy data | |
f78146b0 AK |
10157 | * execute insn |
10158 | * | |
10159 | * write: | |
10160 | * for each fragment | |
87da7e66 XG |
10161 | * for each mmio piece in the fragment |
10162 | * write gpa, len | |
10163 | * copy data | |
10164 | * exit | |
f78146b0 | 10165 | */ |
716d51ab | 10166 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
10167 | { |
10168 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 10169 | struct kvm_mmio_fragment *frag; |
87da7e66 | 10170 | unsigned len; |
5287f194 | 10171 | |
716d51ab | 10172 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 10173 | |
716d51ab | 10174 | /* Complete previous fragment */ |
87da7e66 XG |
10175 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
10176 | len = min(8u, frag->len); | |
716d51ab | 10177 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
10178 | memcpy(frag->data, run->mmio.data, len); |
10179 | ||
10180 | if (frag->len <= 8) { | |
10181 | /* Switch to the next fragment. */ | |
10182 | frag++; | |
10183 | vcpu->mmio_cur_fragment++; | |
10184 | } else { | |
10185 | /* Go forward to the next mmio piece. */ | |
10186 | frag->data += len; | |
10187 | frag->gpa += len; | |
10188 | frag->len -= len; | |
10189 | } | |
10190 | ||
a08d3b3b | 10191 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 10192 | vcpu->mmio_needed = 0; |
0912c977 PB |
10193 | |
10194 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 10195 | if (vcpu->mmio_is_write) |
716d51ab GN |
10196 | return 1; |
10197 | vcpu->mmio_read_completed = 1; | |
10198 | return complete_emulated_io(vcpu); | |
10199 | } | |
87da7e66 | 10200 | |
716d51ab GN |
10201 | run->exit_reason = KVM_EXIT_MMIO; |
10202 | run->mmio.phys_addr = frag->gpa; | |
10203 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
10204 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
10205 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
10206 | run->mmio.is_write = vcpu->mmio_is_write; |
10207 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
10208 | return 0; | |
5287f194 AK |
10209 | } |
10210 | ||
c9aef3b8 SC |
10211 | static void kvm_save_current_fpu(struct fpu *fpu) |
10212 | { | |
10213 | /* | |
10214 | * If the target FPU state is not resident in the CPU registers, just | |
10215 | * memcpy() from current, else save CPU state directly to the target. | |
10216 | */ | |
10217 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
10218 | memcpy(&fpu->state, ¤t->thread.fpu.state, | |
10219 | fpu_kernel_xstate_size); | |
10220 | else | |
ebe7234b | 10221 | save_fpregs_to_fpstate(fpu); |
c9aef3b8 SC |
10222 | } |
10223 | ||
822f312d SAS |
10224 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
10225 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
10226 | { | |
5f409e20 RR |
10227 | fpregs_lock(); |
10228 | ||
c9aef3b8 SC |
10229 | kvm_save_current_fpu(vcpu->arch.user_fpu); |
10230 | ||
ed02b213 TL |
10231 | /* |
10232 | * Guests with protected state can't have it set by the hypervisor, | |
10233 | * so skip trying to set it. | |
10234 | */ | |
10235 | if (vcpu->arch.guest_fpu) | |
10236 | /* PKRU is separately restored in kvm_x86_ops.run. */ | |
1c61fada | 10237 | __restore_fpregs_from_fpstate(&vcpu->arch.guest_fpu->state, |
ed02b213 | 10238 | ~XFEATURE_MASK_PKRU); |
5f409e20 RR |
10239 | |
10240 | fpregs_mark_activate(); | |
10241 | fpregs_unlock(); | |
10242 | ||
822f312d SAS |
10243 | trace_kvm_fpu(1); |
10244 | } | |
10245 | ||
10246 | /* When vcpu_run ends, restore user space FPU context. */ | |
10247 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
10248 | { | |
5f409e20 RR |
10249 | fpregs_lock(); |
10250 | ||
ed02b213 TL |
10251 | /* |
10252 | * Guests with protected state can't have it read by the hypervisor, | |
10253 | * so skip trying to save it. | |
10254 | */ | |
10255 | if (vcpu->arch.guest_fpu) | |
10256 | kvm_save_current_fpu(vcpu->arch.guest_fpu); | |
c9aef3b8 | 10257 | |
1c61fada | 10258 | restore_fpregs_from_fpstate(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
10259 | |
10260 | fpregs_mark_activate(); | |
10261 | fpregs_unlock(); | |
10262 | ||
822f312d SAS |
10263 | ++vcpu->stat.fpu_reload; |
10264 | trace_kvm_fpu(0); | |
10265 | } | |
10266 | ||
1b94f6f8 | 10267 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 10268 | { |
1b94f6f8 | 10269 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 10270 | int r; |
b6c7a5dc | 10271 | |
accb757d | 10272 | vcpu_load(vcpu); |
20b7035c | 10273 | kvm_sigset_activate(vcpu); |
15aad3be | 10274 | kvm_run->flags = 0; |
5663d8f9 PX |
10275 | kvm_load_guest_fpu(vcpu); |
10276 | ||
a4535290 | 10277 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
10278 | if (kvm_run->immediate_exit) { |
10279 | r = -EINTR; | |
10280 | goto out; | |
10281 | } | |
b6c7a5dc | 10282 | kvm_vcpu_block(vcpu); |
4fe09bcf JM |
10283 | if (kvm_apic_accept_events(vcpu) < 0) { |
10284 | r = 0; | |
10285 | goto out; | |
10286 | } | |
72875d8a | 10287 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 10288 | r = -EAGAIN; |
a0595000 JS |
10289 | if (signal_pending(current)) { |
10290 | r = -EINTR; | |
1b94f6f8 | 10291 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
10292 | ++vcpu->stat.signal_exits; |
10293 | } | |
ac9f6dc0 | 10294 | goto out; |
b6c7a5dc HB |
10295 | } |
10296 | ||
e489a4a6 SC |
10297 | if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || |
10298 | (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { | |
01643c51 KH |
10299 | r = -EINVAL; |
10300 | goto out; | |
10301 | } | |
10302 | ||
1b94f6f8 | 10303 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
10304 | r = sync_regs(vcpu); |
10305 | if (r != 0) | |
10306 | goto out; | |
10307 | } | |
10308 | ||
b6c7a5dc | 10309 | /* re-sync apic's tpr */ |
35754c98 | 10310 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
10311 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
10312 | r = -EINVAL; | |
10313 | goto out; | |
10314 | } | |
10315 | } | |
b6c7a5dc | 10316 | |
716d51ab GN |
10317 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
10318 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
10319 | vcpu->arch.complete_userspace_io = NULL; | |
10320 | r = cui(vcpu); | |
10321 | if (r <= 0) | |
5663d8f9 | 10322 | goto out; |
716d51ab GN |
10323 | } else |
10324 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 10325 | |
460df4c1 PB |
10326 | if (kvm_run->immediate_exit) |
10327 | r = -EINTR; | |
10328 | else | |
10329 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
10330 | |
10331 | out: | |
5663d8f9 | 10332 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 10333 | if (kvm_run->kvm_valid_regs) |
01643c51 | 10334 | store_regs(vcpu); |
f1d86e46 | 10335 | post_kvm_run_save(vcpu); |
20b7035c | 10336 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 10337 | |
accb757d | 10338 | vcpu_put(vcpu); |
b6c7a5dc HB |
10339 | return r; |
10340 | } | |
10341 | ||
01643c51 | 10342 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 10343 | { |
7ae441ea GN |
10344 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
10345 | /* | |
10346 | * We are here if userspace calls get_regs() in the middle of | |
10347 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 10348 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
10349 | * that usually, but some bad designed PV devices (vmware |
10350 | * backdoor interface) need this to work | |
10351 | */ | |
c9b8b07c | 10352 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
10353 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
10354 | } | |
de3cd117 SC |
10355 | regs->rax = kvm_rax_read(vcpu); |
10356 | regs->rbx = kvm_rbx_read(vcpu); | |
10357 | regs->rcx = kvm_rcx_read(vcpu); | |
10358 | regs->rdx = kvm_rdx_read(vcpu); | |
10359 | regs->rsi = kvm_rsi_read(vcpu); | |
10360 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 10361 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 10362 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 10363 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
10364 | regs->r8 = kvm_r8_read(vcpu); |
10365 | regs->r9 = kvm_r9_read(vcpu); | |
10366 | regs->r10 = kvm_r10_read(vcpu); | |
10367 | regs->r11 = kvm_r11_read(vcpu); | |
10368 | regs->r12 = kvm_r12_read(vcpu); | |
10369 | regs->r13 = kvm_r13_read(vcpu); | |
10370 | regs->r14 = kvm_r14_read(vcpu); | |
10371 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
10372 | #endif |
10373 | ||
5fdbf976 | 10374 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 10375 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 10376 | } |
b6c7a5dc | 10377 | |
01643c51 KH |
10378 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
10379 | { | |
10380 | vcpu_load(vcpu); | |
10381 | __get_regs(vcpu, regs); | |
1fc9b76b | 10382 | vcpu_put(vcpu); |
b6c7a5dc HB |
10383 | return 0; |
10384 | } | |
10385 | ||
01643c51 | 10386 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 10387 | { |
7ae441ea GN |
10388 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
10389 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
10390 | ||
de3cd117 SC |
10391 | kvm_rax_write(vcpu, regs->rax); |
10392 | kvm_rbx_write(vcpu, regs->rbx); | |
10393 | kvm_rcx_write(vcpu, regs->rcx); | |
10394 | kvm_rdx_write(vcpu, regs->rdx); | |
10395 | kvm_rsi_write(vcpu, regs->rsi); | |
10396 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 10397 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 10398 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 10399 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
10400 | kvm_r8_write(vcpu, regs->r8); |
10401 | kvm_r9_write(vcpu, regs->r9); | |
10402 | kvm_r10_write(vcpu, regs->r10); | |
10403 | kvm_r11_write(vcpu, regs->r11); | |
10404 | kvm_r12_write(vcpu, regs->r12); | |
10405 | kvm_r13_write(vcpu, regs->r13); | |
10406 | kvm_r14_write(vcpu, regs->r14); | |
10407 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
10408 | #endif |
10409 | ||
5fdbf976 | 10410 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 10411 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 10412 | |
b4f14abd JK |
10413 | vcpu->arch.exception.pending = false; |
10414 | ||
3842d135 | 10415 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 10416 | } |
3842d135 | 10417 | |
01643c51 KH |
10418 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
10419 | { | |
10420 | vcpu_load(vcpu); | |
10421 | __set_regs(vcpu, regs); | |
875656fe | 10422 | vcpu_put(vcpu); |
b6c7a5dc HB |
10423 | return 0; |
10424 | } | |
10425 | ||
b6c7a5dc HB |
10426 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
10427 | { | |
10428 | struct kvm_segment cs; | |
10429 | ||
3e6e0aab | 10430 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
10431 | *db = cs.db; |
10432 | *l = cs.l; | |
10433 | } | |
10434 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
10435 | ||
6dba9403 | 10436 | static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 10437 | { |
89a27f4d | 10438 | struct desc_ptr dt; |
b6c7a5dc | 10439 | |
5265713a TL |
10440 | if (vcpu->arch.guest_state_protected) |
10441 | goto skip_protected_regs; | |
10442 | ||
3e6e0aab GT |
10443 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
10444 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
10445 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
10446 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
10447 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
10448 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 10449 | |
3e6e0aab GT |
10450 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
10451 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 10452 | |
b3646477 | 10453 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
89a27f4d GN |
10454 | sregs->idt.limit = dt.size; |
10455 | sregs->idt.base = dt.address; | |
b3646477 | 10456 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
89a27f4d GN |
10457 | sregs->gdt.limit = dt.size; |
10458 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 10459 | |
ad312c7c | 10460 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 10461 | sregs->cr3 = kvm_read_cr3(vcpu); |
5265713a TL |
10462 | |
10463 | skip_protected_regs: | |
10464 | sregs->cr0 = kvm_read_cr0(vcpu); | |
fc78f519 | 10465 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 10466 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 10467 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc | 10468 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6dba9403 | 10469 | } |
b6c7a5dc | 10470 | |
6dba9403 ML |
10471 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
10472 | { | |
10473 | __get_sregs_common(vcpu, sregs); | |
10474 | ||
10475 | if (vcpu->arch.guest_state_protected) | |
10476 | return; | |
b6c7a5dc | 10477 | |
04140b41 | 10478 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
10479 | set_bit(vcpu->arch.interrupt.nr, |
10480 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 10481 | } |
16d7a191 | 10482 | |
6dba9403 ML |
10483 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
10484 | { | |
10485 | int i; | |
10486 | ||
10487 | __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); | |
10488 | ||
10489 | if (vcpu->arch.guest_state_protected) | |
10490 | return; | |
10491 | ||
10492 | if (is_pae_paging(vcpu)) { | |
10493 | for (i = 0 ; i < 4 ; i++) | |
10494 | sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); | |
10495 | sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
10496 | } | |
10497 | } | |
10498 | ||
01643c51 KH |
10499 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
10500 | struct kvm_sregs *sregs) | |
10501 | { | |
10502 | vcpu_load(vcpu); | |
10503 | __get_sregs(vcpu, sregs); | |
bcdec41c | 10504 | vcpu_put(vcpu); |
b6c7a5dc HB |
10505 | return 0; |
10506 | } | |
10507 | ||
62d9f0db MT |
10508 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
10509 | struct kvm_mp_state *mp_state) | |
10510 | { | |
4fe09bcf JM |
10511 | int r; |
10512 | ||
fd232561 | 10513 | vcpu_load(vcpu); |
f958bd23 SC |
10514 | if (kvm_mpx_supported()) |
10515 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 10516 | |
4fe09bcf JM |
10517 | r = kvm_apic_accept_events(vcpu); |
10518 | if (r < 0) | |
10519 | goto out; | |
10520 | r = 0; | |
10521 | ||
647daca2 TL |
10522 | if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || |
10523 | vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && | |
10524 | vcpu->arch.pv.pv_unhalted) | |
6aef266c SV |
10525 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; |
10526 | else | |
10527 | mp_state->mp_state = vcpu->arch.mp_state; | |
10528 | ||
4fe09bcf | 10529 | out: |
f958bd23 SC |
10530 | if (kvm_mpx_supported()) |
10531 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 10532 | vcpu_put(vcpu); |
4fe09bcf | 10533 | return r; |
62d9f0db MT |
10534 | } |
10535 | ||
10536 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
10537 | struct kvm_mp_state *mp_state) | |
10538 | { | |
e83dff5e CD |
10539 | int ret = -EINVAL; |
10540 | ||
10541 | vcpu_load(vcpu); | |
10542 | ||
bce87cce | 10543 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 10544 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 10545 | goto out; |
66450a21 | 10546 | |
27cbe7d6 LA |
10547 | /* |
10548 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
10549 | * INIT state; latched init should be reported using | |
10550 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
10551 | */ | |
10552 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
10553 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
10554 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 10555 | goto out; |
28bf2888 | 10556 | |
66450a21 JK |
10557 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
10558 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
10559 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
10560 | } else | |
10561 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 10562 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
10563 | |
10564 | ret = 0; | |
10565 | out: | |
10566 | vcpu_put(vcpu); | |
10567 | return ret; | |
62d9f0db MT |
10568 | } |
10569 | ||
7f3d35fd KW |
10570 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
10571 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 10572 | { |
c9b8b07c | 10573 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 10574 | int ret; |
e01c2426 | 10575 | |
8ec4722d | 10576 | init_emulate_ctxt(vcpu); |
c697518a | 10577 | |
7f3d35fd | 10578 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 10579 | has_error_code, error_code); |
1051778f SC |
10580 | if (ret) { |
10581 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
10582 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
10583 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 10584 | return 0; |
1051778f | 10585 | } |
37817f29 | 10586 | |
9d74191a TY |
10587 | kvm_rip_write(vcpu, ctxt->eip); |
10588 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 10589 | return 1; |
37817f29 IE |
10590 | } |
10591 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
10592 | ||
ee69c92b | 10593 | static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 10594 | { |
37b95951 | 10595 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
10596 | /* |
10597 | * When EFER.LME and CR0.PG are set, the processor is in | |
10598 | * 64-bit mode (though maybe in a 32-bit code segment). | |
10599 | * CR4.PAE and EFER.LMA must be set. | |
10600 | */ | |
ee69c92b SC |
10601 | if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) |
10602 | return false; | |
ca29e145 | 10603 | if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) |
c1c35cf7 | 10604 | return false; |
f2981033 LT |
10605 | } else { |
10606 | /* | |
10607 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
10608 | * segment cannot be 64-bit. | |
10609 | */ | |
10610 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
ee69c92b | 10611 | return false; |
f2981033 LT |
10612 | } |
10613 | ||
ee69c92b | 10614 | return kvm_is_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
10615 | } |
10616 | ||
6dba9403 ML |
10617 | static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, |
10618 | int *mmu_reset_needed, bool update_pdptrs) | |
b6c7a5dc | 10619 | { |
58cb628d | 10620 | struct msr_data apic_base_msr; |
6dba9403 | 10621 | int idx; |
89a27f4d | 10622 | struct desc_ptr dt; |
b4ef9d4e | 10623 | |
ee69c92b | 10624 | if (!kvm_is_valid_sregs(vcpu, sregs)) |
6dba9403 | 10625 | return -EINVAL; |
f2981033 | 10626 | |
d3802286 JM |
10627 | apic_base_msr.data = sregs->apic_base; |
10628 | apic_base_msr.host_initiated = true; | |
10629 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
6dba9403 | 10630 | return -EINVAL; |
6d1068b3 | 10631 | |
5265713a | 10632 | if (vcpu->arch.guest_state_protected) |
6dba9403 | 10633 | return 0; |
5265713a | 10634 | |
89a27f4d GN |
10635 | dt.size = sregs->idt.limit; |
10636 | dt.address = sregs->idt.base; | |
b3646477 | 10637 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
89a27f4d GN |
10638 | dt.size = sregs->gdt.limit; |
10639 | dt.address = sregs->gdt.base; | |
b3646477 | 10640 | static_call(kvm_x86_set_gdt)(vcpu, &dt); |
b6c7a5dc | 10641 | |
ad312c7c | 10642 | vcpu->arch.cr2 = sregs->cr2; |
6dba9403 | 10643 | *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 10644 | vcpu->arch.cr3 = sregs->cr3; |
cb3c1e2f | 10645 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
b6c7a5dc | 10646 | |
2d3ad1f4 | 10647 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 10648 | |
6dba9403 | 10649 | *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b3646477 | 10650 | static_call(kvm_x86_set_efer)(vcpu, sregs->efer); |
b6c7a5dc | 10651 | |
6dba9403 | 10652 | *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b3646477 | 10653 | static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); |
d7306163 | 10654 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 10655 | |
6dba9403 | 10656 | *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b3646477 | 10657 | static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); |
63f42e02 | 10658 | |
6dba9403 ML |
10659 | if (update_pdptrs) { |
10660 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
10661 | if (is_pae_paging(vcpu)) { | |
10662 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); | |
10663 | *mmu_reset_needed = 1; | |
10664 | } | |
10665 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
7c93be44 | 10666 | } |
b6c7a5dc | 10667 | |
3e6e0aab GT |
10668 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
10669 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
10670 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
10671 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
10672 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
10673 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 10674 | |
3e6e0aab GT |
10675 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
10676 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 10677 | |
5f0269f5 ME |
10678 | update_cr8_intercept(vcpu); |
10679 | ||
9c3e4aab | 10680 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 10681 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 10682 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 10683 | !is_protmode(vcpu)) |
9c3e4aab MT |
10684 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
10685 | ||
6dba9403 ML |
10686 | return 0; |
10687 | } | |
10688 | ||
10689 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
10690 | { | |
10691 | int pending_vec, max_bits; | |
10692 | int mmu_reset_needed = 0; | |
10693 | int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); | |
10694 | ||
10695 | if (ret) | |
10696 | return ret; | |
10697 | ||
10698 | if (mmu_reset_needed) | |
10699 | kvm_mmu_reset_context(vcpu); | |
10700 | ||
5265713a TL |
10701 | max_bits = KVM_NR_INTERRUPTS; |
10702 | pending_vec = find_first_bit( | |
10703 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6dba9403 | 10704 | |
5265713a TL |
10705 | if (pending_vec < max_bits) { |
10706 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
10707 | pr_debug("Set back pending irq %d\n", pending_vec); | |
6dba9403 | 10708 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5265713a | 10709 | } |
6dba9403 ML |
10710 | return 0; |
10711 | } | |
5265713a | 10712 | |
6dba9403 ML |
10713 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
10714 | { | |
10715 | int mmu_reset_needed = 0; | |
10716 | bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
10717 | bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && | |
10718 | !(sregs2->efer & EFER_LMA); | |
10719 | int i, ret; | |
3842d135 | 10720 | |
6dba9403 ML |
10721 | if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) |
10722 | return -EINVAL; | |
10723 | ||
10724 | if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) | |
10725 | return -EINVAL; | |
10726 | ||
10727 | ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, | |
10728 | &mmu_reset_needed, !valid_pdptrs); | |
10729 | if (ret) | |
10730 | return ret; | |
10731 | ||
10732 | if (valid_pdptrs) { | |
10733 | for (i = 0; i < 4 ; i++) | |
10734 | kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); | |
10735 | ||
10736 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); | |
10737 | mmu_reset_needed = 1; | |
158a48ec | 10738 | vcpu->arch.pdptrs_from_userspace = true; |
6dba9403 ML |
10739 | } |
10740 | if (mmu_reset_needed) | |
10741 | kvm_mmu_reset_context(vcpu); | |
10742 | return 0; | |
01643c51 KH |
10743 | } |
10744 | ||
10745 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
10746 | struct kvm_sregs *sregs) | |
10747 | { | |
10748 | int ret; | |
10749 | ||
10750 | vcpu_load(vcpu); | |
10751 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
10752 | vcpu_put(vcpu); |
10753 | return ret; | |
b6c7a5dc HB |
10754 | } |
10755 | ||
cae72dcc ML |
10756 | static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) |
10757 | { | |
10758 | bool inhibit = false; | |
10759 | struct kvm_vcpu *vcpu; | |
10760 | int i; | |
10761 | ||
10762 | down_write(&kvm->arch.apicv_update_lock); | |
10763 | ||
10764 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
10765 | if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { | |
10766 | inhibit = true; | |
10767 | break; | |
10768 | } | |
10769 | } | |
10770 | __kvm_request_apicv_update(kvm, !inhibit, APICV_INHIBIT_REASON_BLOCKIRQ); | |
10771 | up_write(&kvm->arch.apicv_update_lock); | |
10772 | } | |
10773 | ||
d0bfb940 JK |
10774 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
10775 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 10776 | { |
355be0b9 | 10777 | unsigned long rflags; |
ae675ef0 | 10778 | int i, r; |
b6c7a5dc | 10779 | |
8d4846b9 TL |
10780 | if (vcpu->arch.guest_state_protected) |
10781 | return -EINVAL; | |
10782 | ||
66b56562 CD |
10783 | vcpu_load(vcpu); |
10784 | ||
4f926bf2 JK |
10785 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
10786 | r = -EBUSY; | |
10787 | if (vcpu->arch.exception.pending) | |
2122ff5e | 10788 | goto out; |
4f926bf2 JK |
10789 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
10790 | kvm_queue_exception(vcpu, DB_VECTOR); | |
10791 | else | |
10792 | kvm_queue_exception(vcpu, BP_VECTOR); | |
10793 | } | |
10794 | ||
91586a3b JK |
10795 | /* |
10796 | * Read rflags as long as potentially injected trace flags are still | |
10797 | * filtered out. | |
10798 | */ | |
10799 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
10800 | |
10801 | vcpu->guest_debug = dbg->control; | |
10802 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
10803 | vcpu->guest_debug = 0; | |
10804 | ||
10805 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
10806 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
10807 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 10808 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
10809 | } else { |
10810 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
10811 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 10812 | } |
c8639010 | 10813 | kvm_update_dr7(vcpu); |
ae675ef0 | 10814 | |
f92653ee | 10815 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
e87e46d5 | 10816 | vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); |
94fe45da | 10817 | |
91586a3b JK |
10818 | /* |
10819 | * Trigger an rflags update that will inject or remove the trace | |
10820 | * flags. | |
10821 | */ | |
10822 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 10823 | |
b3646477 | 10824 | static_call(kvm_x86_update_exception_bitmap)(vcpu); |
b6c7a5dc | 10825 | |
cae72dcc ML |
10826 | kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); |
10827 | ||
4f926bf2 | 10828 | r = 0; |
d0bfb940 | 10829 | |
2122ff5e | 10830 | out: |
66b56562 | 10831 | vcpu_put(vcpu); |
b6c7a5dc HB |
10832 | return r; |
10833 | } | |
10834 | ||
8b006791 ZX |
10835 | /* |
10836 | * Translate a guest virtual address to a guest physical address. | |
10837 | */ | |
10838 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
10839 | struct kvm_translation *tr) | |
10840 | { | |
10841 | unsigned long vaddr = tr->linear_address; | |
10842 | gpa_t gpa; | |
f656ce01 | 10843 | int idx; |
8b006791 | 10844 | |
1da5b61d CD |
10845 | vcpu_load(vcpu); |
10846 | ||
f656ce01 | 10847 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 10848 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 10849 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
10850 | tr->physical_address = gpa; |
10851 | tr->valid = gpa != UNMAPPED_GVA; | |
10852 | tr->writeable = 1; | |
10853 | tr->usermode = 0; | |
8b006791 | 10854 | |
1da5b61d | 10855 | vcpu_put(vcpu); |
8b006791 ZX |
10856 | return 0; |
10857 | } | |
10858 | ||
d0752060 HB |
10859 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
10860 | { | |
1393123e | 10861 | struct fxregs_state *fxsave; |
d0752060 | 10862 | |
ed02b213 TL |
10863 | if (!vcpu->arch.guest_fpu) |
10864 | return 0; | |
10865 | ||
1393123e | 10866 | vcpu_load(vcpu); |
d0752060 | 10867 | |
b666a4b6 | 10868 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
10869 | memcpy(fpu->fpr, fxsave->st_space, 128); |
10870 | fpu->fcw = fxsave->cwd; | |
10871 | fpu->fsw = fxsave->swd; | |
10872 | fpu->ftwx = fxsave->twd; | |
10873 | fpu->last_opcode = fxsave->fop; | |
10874 | fpu->last_ip = fxsave->rip; | |
10875 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 10876 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 10877 | |
1393123e | 10878 | vcpu_put(vcpu); |
d0752060 HB |
10879 | return 0; |
10880 | } | |
10881 | ||
10882 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
10883 | { | |
6a96bc7f CD |
10884 | struct fxregs_state *fxsave; |
10885 | ||
ed02b213 TL |
10886 | if (!vcpu->arch.guest_fpu) |
10887 | return 0; | |
10888 | ||
6a96bc7f CD |
10889 | vcpu_load(vcpu); |
10890 | ||
b666a4b6 | 10891 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 10892 | |
d0752060 HB |
10893 | memcpy(fxsave->st_space, fpu->fpr, 128); |
10894 | fxsave->cwd = fpu->fcw; | |
10895 | fxsave->swd = fpu->fsw; | |
10896 | fxsave->twd = fpu->ftwx; | |
10897 | fxsave->fop = fpu->last_opcode; | |
10898 | fxsave->rip = fpu->last_ip; | |
10899 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 10900 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 10901 | |
6a96bc7f | 10902 | vcpu_put(vcpu); |
d0752060 HB |
10903 | return 0; |
10904 | } | |
10905 | ||
01643c51 KH |
10906 | static void store_regs(struct kvm_vcpu *vcpu) |
10907 | { | |
10908 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
10909 | ||
10910 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
10911 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
10912 | ||
10913 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
10914 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
10915 | ||
10916 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
10917 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
10918 | vcpu, &vcpu->run->s.regs.events); | |
10919 | } | |
10920 | ||
10921 | static int sync_regs(struct kvm_vcpu *vcpu) | |
10922 | { | |
01643c51 KH |
10923 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { |
10924 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
10925 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
10926 | } | |
10927 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
10928 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
10929 | return -EINVAL; | |
10930 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
10931 | } | |
10932 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
10933 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
10934 | vcpu, &vcpu->run->s.regs.events)) | |
10935 | return -EINVAL; | |
10936 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
10937 | } | |
10938 | ||
10939 | return 0; | |
10940 | } | |
10941 | ||
ed02b213 TL |
10942 | void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) |
10943 | { | |
10944 | if (vcpu->arch.guest_fpu) { | |
10945 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
10946 | vcpu->arch.guest_fpu = NULL; | |
10947 | } | |
10948 | } | |
10949 | EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); | |
10950 | ||
897cc38e | 10951 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 10952 | { |
897cc38e SC |
10953 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
10954 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " | |
10955 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 10956 | |
897cc38e | 10957 | return 0; |
e9b11c17 ZX |
10958 | } |
10959 | ||
e529ef66 | 10960 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 10961 | { |
95a0d01e SC |
10962 | struct page *page; |
10963 | int r; | |
c447e76b | 10964 | |
63f5a190 | 10965 | vcpu->arch.last_vmentry_cpu = -1; |
7117003f SC |
10966 | vcpu->arch.regs_avail = ~0; |
10967 | vcpu->arch.regs_dirty = ~0; | |
63f5a190 | 10968 | |
95a0d01e SC |
10969 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
10970 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
10971 | else | |
10972 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 10973 | |
95a0d01e SC |
10974 | r = kvm_mmu_create(vcpu); |
10975 | if (r < 0) | |
10976 | return r; | |
10977 | ||
10978 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
10979 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
10980 | if (r < 0) | |
10981 | goto fail_mmu_destroy; | |
4e19c36f SS |
10982 | if (kvm_apicv_activated(vcpu->kvm)) |
10983 | vcpu->arch.apicv_active = true; | |
95a0d01e | 10984 | } else |
6e4e3b4d | 10985 | static_branch_inc(&kvm_has_noapic_vcpu); |
95a0d01e SC |
10986 | |
10987 | r = -ENOMEM; | |
10988 | ||
93bb59ca | 10989 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
95a0d01e SC |
10990 | if (!page) |
10991 | goto fail_free_lapic; | |
10992 | vcpu->arch.pio_data = page_address(page); | |
10993 | ||
10994 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
10995 | GFP_KERNEL_ACCOUNT); | |
10996 | if (!vcpu->arch.mce_banks) | |
10997 | goto fail_free_pio_data; | |
10998 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
10999 | ||
11000 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
11001 | GFP_KERNEL_ACCOUNT)) | |
11002 | goto fail_free_mce_banks; | |
11003 | ||
c9b8b07c SC |
11004 | if (!alloc_emulate_ctxt(vcpu)) |
11005 | goto free_wbinvd_dirty_mask; | |
11006 | ||
95a0d01e SC |
11007 | vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, |
11008 | GFP_KERNEL_ACCOUNT); | |
11009 | if (!vcpu->arch.user_fpu) { | |
11010 | pr_err("kvm: failed to allocate userspace's fpu\n"); | |
c9b8b07c | 11011 | goto free_emulate_ctxt; |
95a0d01e SC |
11012 | } |
11013 | ||
11014 | vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
11015 | GFP_KERNEL_ACCOUNT); | |
11016 | if (!vcpu->arch.guest_fpu) { | |
11017 | pr_err("kvm: failed to allocate vcpu's fpu\n"); | |
11018 | goto free_user_fpu; | |
11019 | } | |
583d369b SC |
11020 | fpstate_init(&vcpu->arch.guest_fpu->state); |
11021 | if (boot_cpu_has(X86_FEATURE_XSAVES)) | |
11022 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = | |
11023 | host_xcr0 | XSTATE_COMPACTION_ENABLED; | |
95a0d01e | 11024 | |
95a0d01e | 11025 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
a8ac864a | 11026 | vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); |
95a0d01e SC |
11027 | |
11028 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
11029 | ||
11030 | kvm_async_pf_hash_reset(vcpu); | |
11031 | kvm_pmu_init(vcpu); | |
11032 | ||
11033 | vcpu->arch.pending_external_vector = -1; | |
11034 | vcpu->arch.preempted_in_kernel = false; | |
11035 | ||
3c86c0d3 VP |
11036 | #if IS_ENABLED(CONFIG_HYPERV) |
11037 | vcpu->arch.hv_root_tdp = INVALID_PAGE; | |
11038 | #endif | |
11039 | ||
b3646477 | 11040 | r = static_call(kvm_x86_vcpu_create)(vcpu); |
95a0d01e SC |
11041 | if (r) |
11042 | goto free_guest_fpu; | |
e9b11c17 | 11043 | |
0cf9135b | 11044 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 11045 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 11046 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 11047 | vcpu_load(vcpu); |
1ab9287a | 11048 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
d28bc9dd | 11049 | kvm_vcpu_reset(vcpu, false); |
c9060662 | 11050 | kvm_init_mmu(vcpu); |
e9b11c17 | 11051 | vcpu_put(vcpu); |
ec7660cc | 11052 | return 0; |
95a0d01e SC |
11053 | |
11054 | free_guest_fpu: | |
ed02b213 | 11055 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
11056 | free_user_fpu: |
11057 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
c9b8b07c SC |
11058 | free_emulate_ctxt: |
11059 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
11060 | free_wbinvd_dirty_mask: |
11061 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
11062 | fail_free_mce_banks: | |
11063 | kfree(vcpu->arch.mce_banks); | |
11064 | fail_free_pio_data: | |
11065 | free_page((unsigned long)vcpu->arch.pio_data); | |
11066 | fail_free_lapic: | |
11067 | kvm_free_lapic(vcpu); | |
11068 | fail_mmu_destroy: | |
11069 | kvm_mmu_destroy(vcpu); | |
11070 | return r; | |
e9b11c17 ZX |
11071 | } |
11072 | ||
31928aa5 | 11073 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 11074 | { |
332967a3 | 11075 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 11076 | |
ec7660cc | 11077 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 11078 | return; |
ec7660cc | 11079 | vcpu_load(vcpu); |
0c899c25 | 11080 | kvm_synchronize_tsc(vcpu, 0); |
42897d86 | 11081 | vcpu_put(vcpu); |
2d5ba19b MT |
11082 | |
11083 | /* poll control enabled by default */ | |
11084 | vcpu->arch.msr_kvm_poll_control = 1; | |
11085 | ||
ec7660cc | 11086 | mutex_unlock(&vcpu->mutex); |
42897d86 | 11087 | |
b34de572 WL |
11088 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
11089 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
11090 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
11091 | } |
11092 | ||
d40ccc62 | 11093 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 11094 | { |
95a0d01e | 11095 | int idx; |
344d9588 | 11096 | |
50b143e1 | 11097 | kvmclock_reset(vcpu); |
e9b11c17 | 11098 | |
b3646477 | 11099 | static_call(kvm_x86_vcpu_free)(vcpu); |
50b143e1 | 11100 | |
c9b8b07c | 11101 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 SC |
11102 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
11103 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
ed02b213 | 11104 | kvm_free_guest_fpu(vcpu); |
95a0d01e SC |
11105 | |
11106 | kvm_hv_vcpu_uninit(vcpu); | |
11107 | kvm_pmu_destroy(vcpu); | |
11108 | kfree(vcpu->arch.mce_banks); | |
11109 | kvm_free_lapic(vcpu); | |
11110 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
11111 | kvm_mmu_destroy(vcpu); | |
11112 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
11113 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 11114 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e | 11115 | if (!lapic_in_kernel(vcpu)) |
6e4e3b4d | 11116 | static_branch_dec(&kvm_has_noapic_vcpu); |
e9b11c17 ZX |
11117 | } |
11118 | ||
d28bc9dd | 11119 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 11120 | { |
25b97845 | 11121 | struct kvm_cpuid_entry2 *cpuid_0x1; |
0aa18375 | 11122 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
4c72ab5a | 11123 | unsigned long new_cr0; |
0aa18375 | 11124 | |
62dd57dd SC |
11125 | /* |
11126 | * Several of the "set" flows, e.g. ->set_cr0(), read other registers | |
11127 | * to handle side effects. RESET emulation hits those flows and relies | |
11128 | * on emulated/virtualized registers, including those that are loaded | |
11129 | * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel | |
11130 | * to detect improper or missing initialization. | |
11131 | */ | |
11132 | WARN_ON_ONCE(!init_event && | |
11133 | (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); | |
11134 | ||
b7e31be3 RK |
11135 | kvm_lapic_reset(vcpu, init_event); |
11136 | ||
e69fab5d PB |
11137 | vcpu->arch.hflags = 0; |
11138 | ||
c43203ca | 11139 | vcpu->arch.smi_pending = 0; |
52797bf9 | 11140 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
11141 | atomic_set(&vcpu->arch.nmi_queued, 0); |
11142 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 11143 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
11144 | kvm_clear_interrupt_queue(vcpu); |
11145 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 11146 | |
42dbaa5a | 11147 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 11148 | kvm_update_dr0123(vcpu); |
9a3ecd5e | 11149 | vcpu->arch.dr6 = DR6_ACTIVE_LOW; |
42dbaa5a | 11150 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 11151 | kvm_update_dr7(vcpu); |
42dbaa5a | 11152 | |
1119022c NA |
11153 | vcpu->arch.cr2 = 0; |
11154 | ||
3842d135 | 11155 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
11156 | vcpu->arch.apf.msr_en_val = 0; |
11157 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 11158 | vcpu->arch.st.msr_val = 0; |
3842d135 | 11159 | |
12f9a48f GC |
11160 | kvmclock_reset(vcpu); |
11161 | ||
af585b92 GN |
11162 | kvm_clear_async_pf_completion_queue(vcpu); |
11163 | kvm_async_pf_hash_reset(vcpu); | |
11164 | vcpu->arch.apf.halted = false; | |
3842d135 | 11165 | |
ed02b213 | 11166 | if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { |
a554d207 WL |
11167 | void *mpx_state_buffer; |
11168 | ||
11169 | /* | |
11170 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
11171 | * called with loaded FPU and does not let userspace fix the state. | |
11172 | */ | |
f775b13e RR |
11173 | if (init_event) |
11174 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 11175 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 11176 | XFEATURE_BNDREGS); |
a554d207 WL |
11177 | if (mpx_state_buffer) |
11178 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 11179 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 11180 | XFEATURE_BNDCSR); |
a554d207 WL |
11181 | if (mpx_state_buffer) |
11182 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
11183 | if (init_event) |
11184 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
11185 | } |
11186 | ||
64d60670 | 11187 | if (!init_event) { |
d28bc9dd | 11188 | kvm_pmu_reset(vcpu); |
64d60670 | 11189 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 11190 | |
db2336a8 | 11191 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
11192 | |
11193 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 11194 | } |
f5132b01 | 11195 | |
ff8828c8 | 11196 | /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ |
66f7b72e | 11197 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
ff8828c8 | 11198 | kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); |
66f7b72e | 11199 | |
49d8665c SC |
11200 | /* |
11201 | * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) | |
11202 | * if no CPUID match is found. Note, it's impossible to get a match at | |
11203 | * RESET since KVM emulates RESET before exposing the vCPU to userspace, | |
25b97845 SC |
11204 | * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry |
11205 | * on RESET. But, go through the motions in case that's ever remedied. | |
49d8665c | 11206 | */ |
25b97845 SC |
11207 | cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1, 0); |
11208 | kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); | |
49d8665c | 11209 | |
a554d207 WL |
11210 | vcpu->arch.ia32_xss = 0; |
11211 | ||
b3646477 | 11212 | static_call(kvm_x86_vcpu_reset)(vcpu, init_event); |
0aa18375 | 11213 | |
f39e805e SC |
11214 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); |
11215 | kvm_rip_write(vcpu, 0xfff0); | |
11216 | ||
03a6e840 SC |
11217 | vcpu->arch.cr3 = 0; |
11218 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); | |
11219 | ||
4c72ab5a SC |
11220 | /* |
11221 | * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions | |
11222 | * of Intel's SDM list CD/NW as being set on INIT, but they contradict | |
11223 | * (or qualify) that with a footnote stating that CD/NW are preserved. | |
11224 | */ | |
11225 | new_cr0 = X86_CR0_ET; | |
11226 | if (init_event) | |
11227 | new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); | |
11228 | else | |
11229 | new_cr0 |= X86_CR0_NW | X86_CR0_CD; | |
11230 | ||
11231 | static_call(kvm_x86_set_cr0)(vcpu, new_cr0); | |
f39e805e SC |
11232 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
11233 | static_call(kvm_x86_set_efer)(vcpu, 0); | |
11234 | static_call(kvm_x86_update_exception_bitmap)(vcpu); | |
11235 | ||
0aa18375 SC |
11236 | /* |
11237 | * Reset the MMU context if paging was enabled prior to INIT (which is | |
11238 | * implied if CR0.PG=1 as CR0 will be '0' prior to RESET). Unlike the | |
11239 | * standard CR0/CR4/EFER modification paths, only CR0.PG needs to be | |
11240 | * checked because it is unconditionally cleared on INIT and all other | |
11241 | * paging related bits are ignored if paging is disabled, i.e. CR0.WP, | |
11242 | * CR4, and EFER changes are all irrelevant if CR0.PG was '0'. | |
11243 | */ | |
11244 | if (old_cr0 & X86_CR0_PG) | |
11245 | kvm_mmu_reset_context(vcpu); | |
df37ed38 SC |
11246 | |
11247 | /* | |
11248 | * Intel's SDM states that all TLB entries are flushed on INIT. AMD's | |
11249 | * APM states the TLBs are untouched by INIT, but it also states that | |
11250 | * the TLBs are flushed on "External initialization of the processor." | |
11251 | * Flush the guest TLB regardless of vendor, there is no meaningful | |
11252 | * benefit in relying on the guest to flush the TLB immediately after | |
11253 | * INIT. A spurious TLB flush is benign and likely negligible from a | |
11254 | * performance perspective. | |
11255 | */ | |
11256 | if (init_event) | |
11257 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
e9b11c17 | 11258 | } |
265e4353 | 11259 | EXPORT_SYMBOL_GPL(kvm_vcpu_reset); |
e9b11c17 | 11260 | |
2b4a273b | 11261 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
11262 | { |
11263 | struct kvm_segment cs; | |
11264 | ||
11265 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
11266 | cs.selector = vector << 8; | |
11267 | cs.base = vector << 12; | |
11268 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
11269 | kvm_rip_write(vcpu, 0); | |
e9b11c17 | 11270 | } |
647daca2 | 11271 | EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); |
e9b11c17 | 11272 | |
13a34e06 | 11273 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 11274 | { |
ca84d1a2 ZA |
11275 | struct kvm *kvm; |
11276 | struct kvm_vcpu *vcpu; | |
11277 | int i; | |
0dd6a6ed ZA |
11278 | int ret; |
11279 | u64 local_tsc; | |
11280 | u64 max_tsc = 0; | |
11281 | bool stable, backwards_tsc = false; | |
18863bdd | 11282 | |
7e34fbd0 | 11283 | kvm_user_return_msr_cpu_online(); |
b3646477 | 11284 | ret = static_call(kvm_x86_hardware_enable)(); |
0dd6a6ed ZA |
11285 | if (ret != 0) |
11286 | return ret; | |
11287 | ||
4ea1636b | 11288 | local_tsc = rdtsc(); |
b0c39dc6 | 11289 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
11290 | list_for_each_entry(kvm, &vm_list, vm_list) { |
11291 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
11292 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 11293 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
11294 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
11295 | backwards_tsc = true; | |
11296 | if (vcpu->arch.last_host_tsc > max_tsc) | |
11297 | max_tsc = vcpu->arch.last_host_tsc; | |
11298 | } | |
11299 | } | |
11300 | } | |
11301 | ||
11302 | /* | |
11303 | * Sometimes, even reliable TSCs go backwards. This happens on | |
11304 | * platforms that reset TSC during suspend or hibernate actions, but | |
11305 | * maintain synchronization. We must compensate. Fortunately, we can | |
11306 | * detect that condition here, which happens early in CPU bringup, | |
11307 | * before any KVM threads can be running. Unfortunately, we can't | |
11308 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
11309 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 11310 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
11311 | * variables that haven't been updated yet. |
11312 | * | |
11313 | * So we simply find the maximum observed TSC above, then record the | |
11314 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
11315 | * the adjustment will be applied. Note that we accumulate | |
11316 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
11317 | * gets a chance to run again. In the event that no KVM threads get a | |
11318 | * chance to run, we will miss the entire elapsed period, as we'll have | |
11319 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
11320 | * loose cycle time. This isn't too big a deal, since the loss will be | |
11321 | * uniform across all VCPUs (not to mention the scenario is extremely | |
11322 | * unlikely). It is possible that a second hibernate recovery happens | |
11323 | * much faster than a first, causing the observed TSC here to be | |
11324 | * smaller; this would require additional padding adjustment, which is | |
11325 | * why we set last_host_tsc to the local tsc observed here. | |
11326 | * | |
11327 | * N.B. - this code below runs only on platforms with reliable TSC, | |
11328 | * as that is the only way backwards_tsc is set above. Also note | |
11329 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
11330 | * have the same delta_cyc adjustment applied if backwards_tsc | |
11331 | * is detected. Note further, this adjustment is only done once, | |
11332 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
11333 | * called multiple times (one for each physical CPU bringup). | |
11334 | * | |
4a969980 | 11335 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
11336 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
11337 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
11338 | * guarantee that they stay in perfect synchronization. | |
11339 | */ | |
11340 | if (backwards_tsc) { | |
11341 | u64 delta_cyc = max_tsc - local_tsc; | |
11342 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 11343 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
11344 | kvm_for_each_vcpu(i, vcpu, kvm) { |
11345 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
11346 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 11347 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
11348 | } |
11349 | ||
11350 | /* | |
11351 | * We have to disable TSC offset matching.. if you were | |
11352 | * booting a VM while issuing an S4 host suspend.... | |
11353 | * you may have some problem. Solving this issue is | |
11354 | * left as an exercise to the reader. | |
11355 | */ | |
11356 | kvm->arch.last_tsc_nsec = 0; | |
11357 | kvm->arch.last_tsc_write = 0; | |
11358 | } | |
11359 | ||
11360 | } | |
11361 | return 0; | |
e9b11c17 ZX |
11362 | } |
11363 | ||
13a34e06 | 11364 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 11365 | { |
b3646477 | 11366 | static_call(kvm_x86_hardware_disable)(); |
13a34e06 | 11367 | drop_user_return_notifiers(); |
e9b11c17 ZX |
11368 | } |
11369 | ||
b9904085 | 11370 | int kvm_arch_hardware_setup(void *opaque) |
e9b11c17 | 11371 | { |
d008dfdb | 11372 | struct kvm_x86_init_ops *ops = opaque; |
9e9c3fe4 NA |
11373 | int r; |
11374 | ||
91661989 SC |
11375 | rdmsrl_safe(MSR_EFER, &host_efer); |
11376 | ||
408e9a31 PB |
11377 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
11378 | rdmsrl(MSR_IA32_XSS, host_xss); | |
11379 | ||
d008dfdb | 11380 | r = ops->hardware_setup(); |
9e9c3fe4 NA |
11381 | if (r != 0) |
11382 | return r; | |
11383 | ||
afaf0b2f | 11384 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); |
b3646477 | 11385 | kvm_ops_static_call_update(); |
69c6f69a | 11386 | |
408e9a31 PB |
11387 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) |
11388 | supported_xss = 0; | |
11389 | ||
139f7425 PB |
11390 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) |
11391 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
11392 | #undef __kvm_cpu_cap_has | |
b11306b5 | 11393 | |
35181e86 HZ |
11394 | if (kvm_has_tsc_control) { |
11395 | /* | |
11396 | * Make sure the user can only configure tsc_khz values that | |
11397 | * fit into a signed integer. | |
273ba457 | 11398 | * A min value is not calculated because it will always |
35181e86 HZ |
11399 | * be 1 on all machines. |
11400 | */ | |
11401 | u64 max = min(0x7fffffffULL, | |
11402 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
11403 | kvm_max_guest_tsc_khz = max; | |
11404 | ||
ad721883 | 11405 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 11406 | } |
ad721883 | 11407 | |
9e9c3fe4 NA |
11408 | kvm_init_msr_list(); |
11409 | return 0; | |
e9b11c17 ZX |
11410 | } |
11411 | ||
11412 | void kvm_arch_hardware_unsetup(void) | |
11413 | { | |
b3646477 | 11414 | static_call(kvm_x86_hardware_unsetup)(); |
e9b11c17 ZX |
11415 | } |
11416 | ||
b9904085 | 11417 | int kvm_arch_check_processor_compat(void *opaque) |
e9b11c17 | 11418 | { |
f1cdecf5 | 11419 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
d008dfdb | 11420 | struct kvm_x86_init_ops *ops = opaque; |
f1cdecf5 SC |
11421 | |
11422 | WARN_ON(!irqs_disabled()); | |
11423 | ||
139f7425 PB |
11424 | if (__cr4_reserved_bits(cpu_has, c) != |
11425 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
f1cdecf5 SC |
11426 | return -EIO; |
11427 | ||
d008dfdb | 11428 | return ops->check_processor_compatibility(); |
d71ba788 PB |
11429 | } |
11430 | ||
11431 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
11432 | { | |
11433 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
11434 | } | |
11435 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
11436 | ||
11437 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
11438 | { | |
11439 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
11440 | } |
11441 | ||
6e4e3b4d CL |
11442 | __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); |
11443 | EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); | |
54e9818f | 11444 | |
e790d9ef RK |
11445 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
11446 | { | |
b35e5548 LX |
11447 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
11448 | ||
c595ceee | 11449 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
11450 | if (pmu->version && unlikely(pmu->event_count)) { |
11451 | pmu->need_cleanup = true; | |
11452 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
11453 | } | |
b3646477 | 11454 | static_call(kvm_x86_sched_in)(vcpu, cpu); |
e790d9ef RK |
11455 | } |
11456 | ||
562b6b08 SC |
11457 | void kvm_arch_free_vm(struct kvm *kvm) |
11458 | { | |
05f04ae4 | 11459 | kfree(to_kvm_hv(kvm)->hv_pa_pg); |
78b497f2 | 11460 | __kvm_arch_free_vm(kvm); |
e790d9ef RK |
11461 | } |
11462 | ||
562b6b08 | 11463 | |
e08b9637 | 11464 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 11465 | { |
eb7511bf | 11466 | int ret; |
869b4421 | 11467 | unsigned long flags; |
eb7511bf | 11468 | |
e08b9637 CO |
11469 | if (type) |
11470 | return -EINVAL; | |
11471 | ||
eb7511bf HZ |
11472 | ret = kvm_page_track_init(kvm); |
11473 | if (ret) | |
11474 | return ret; | |
11475 | ||
6ef768fa | 11476 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 11477 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
10605204 | 11478 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
1aa9b957 | 11479 | INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); |
4d5c5d0f | 11480 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 11481 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 11482 | |
5550af4d SY |
11483 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
11484 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
11485 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
11486 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
11487 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 11488 | |
038f8c11 | 11489 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 11490 | mutex_init(&kvm->arch.apic_map_lock); |
869b4421 | 11491 | seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); |
8171cd68 | 11492 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
869b4421 PB |
11493 | |
11494 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); | |
d828199e | 11495 | pvclock_update_vm_gtod_copy(kvm); |
869b4421 | 11496 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
53f658b3 | 11497 | |
6fbbde9a DS |
11498 | kvm->arch.guest_can_read_msr_platform_info = true; |
11499 | ||
3c86c0d3 VP |
11500 | #if IS_ENABLED(CONFIG_HYPERV) |
11501 | spin_lock_init(&kvm->arch.hv_root_tdp_lock); | |
11502 | kvm->arch.hv_root_tdp = INVALID_PAGE; | |
11503 | #endif | |
11504 | ||
7e44e449 | 11505 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 11506 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 11507 | |
4651fc56 | 11508 | kvm_apicv_init(kvm); |
cbc0236a | 11509 | kvm_hv_init_vm(kvm); |
13d268ca | 11510 | kvm_mmu_init_vm(kvm); |
319afe68 | 11511 | kvm_xen_init_vm(kvm); |
0eb05bf2 | 11512 | |
b3646477 | 11513 | return static_call(kvm_x86_vm_init)(kvm); |
d19a9cd2 ZX |
11514 | } |
11515 | ||
1aa9b957 JS |
11516 | int kvm_arch_post_init_vm(struct kvm *kvm) |
11517 | { | |
11518 | return kvm_mmu_post_init_vm(kvm); | |
11519 | } | |
11520 | ||
d19a9cd2 ZX |
11521 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
11522 | { | |
ec7660cc | 11523 | vcpu_load(vcpu); |
d19a9cd2 ZX |
11524 | kvm_mmu_unload(vcpu); |
11525 | vcpu_put(vcpu); | |
11526 | } | |
11527 | ||
11528 | static void kvm_free_vcpus(struct kvm *kvm) | |
11529 | { | |
11530 | unsigned int i; | |
988a2cae | 11531 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
11532 | |
11533 | /* | |
11534 | * Unpin any mmu pages first. | |
11535 | */ | |
af585b92 GN |
11536 | kvm_for_each_vcpu(i, vcpu, kvm) { |
11537 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 11538 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 11539 | } |
988a2cae | 11540 | kvm_for_each_vcpu(i, vcpu, kvm) |
4543bdc0 | 11541 | kvm_vcpu_destroy(vcpu); |
988a2cae GN |
11542 | |
11543 | mutex_lock(&kvm->lock); | |
11544 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
11545 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 11546 | |
988a2cae GN |
11547 | atomic_set(&kvm->online_vcpus, 0); |
11548 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
11549 | } |
11550 | ||
ad8ba2cd SY |
11551 | void kvm_arch_sync_events(struct kvm *kvm) |
11552 | { | |
332967a3 | 11553 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 11554 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 11555 | kvm_free_pit(kvm); |
ad8ba2cd SY |
11556 | } |
11557 | ||
ff5a983c PX |
11558 | #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) |
11559 | ||
11560 | /** | |
11561 | * __x86_set_memory_region: Setup KVM internal memory slot | |
11562 | * | |
11563 | * @kvm: the kvm pointer to the VM. | |
11564 | * @id: the slot ID to setup. | |
11565 | * @gpa: the GPA to install the slot (unused when @size == 0). | |
11566 | * @size: the size of the slot. Set to zero to uninstall a slot. | |
11567 | * | |
11568 | * This function helps to setup a KVM internal memory slot. Specify | |
11569 | * @size > 0 to install a new slot, while @size == 0 to uninstall a | |
11570 | * slot. The return code can be one of the following: | |
11571 | * | |
11572 | * HVA: on success (uninstall will return a bogus HVA) | |
11573 | * -errno: on error | |
11574 | * | |
11575 | * The caller should always use IS_ERR() to check the return value | |
11576 | * before use. Note, the KVM internal memory slots are guaranteed to | |
11577 | * remain valid and unchanged until the VM is destroyed, i.e., the | |
11578 | * GPA->HVA translation will not change. However, the HVA is a user | |
11579 | * address, i.e. its accessibility is not guaranteed, and must be | |
11580 | * accessed via __copy_{to,from}_user(). | |
11581 | */ | |
11582 | void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, | |
11583 | u32 size) | |
9da0e4d5 PB |
11584 | { |
11585 | int i, r; | |
3f649ab7 | 11586 | unsigned long hva, old_npages; |
f0d648bd | 11587 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 11588 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
11589 | |
11590 | /* Called with kvm->slots_lock held. */ | |
1d8007bd | 11591 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
ff5a983c | 11592 | return ERR_PTR_USR(-EINVAL); |
9da0e4d5 | 11593 | |
f0d648bd PB |
11594 | slot = id_to_memslot(slots, id); |
11595 | if (size) { | |
0577d1ab | 11596 | if (slot && slot->npages) |
ff5a983c | 11597 | return ERR_PTR_USR(-EEXIST); |
f0d648bd PB |
11598 | |
11599 | /* | |
11600 | * MAP_SHARED to prevent internal slot pages from being moved | |
11601 | * by fork()/COW. | |
11602 | */ | |
11603 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
11604 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
11605 | if (IS_ERR((void *)hva)) | |
ff5a983c | 11606 | return (void __user *)hva; |
f0d648bd | 11607 | } else { |
0577d1ab | 11608 | if (!slot || !slot->npages) |
46914534 | 11609 | return NULL; |
f0d648bd | 11610 | |
0577d1ab | 11611 | old_npages = slot->npages; |
b66f9bab | 11612 | hva = slot->userspace_addr; |
f0d648bd PB |
11613 | } |
11614 | ||
9da0e4d5 | 11615 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 11616 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 11617 | |
1d8007bd PB |
11618 | m.slot = id | (i << 16); |
11619 | m.flags = 0; | |
11620 | m.guest_phys_addr = gpa; | |
f0d648bd | 11621 | m.userspace_addr = hva; |
1d8007bd | 11622 | m.memory_size = size; |
9da0e4d5 PB |
11623 | r = __kvm_set_memory_region(kvm, &m); |
11624 | if (r < 0) | |
ff5a983c | 11625 | return ERR_PTR_USR(r); |
9da0e4d5 PB |
11626 | } |
11627 | ||
103c763c | 11628 | if (!size) |
0577d1ab | 11629 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 11630 | |
ff5a983c | 11631 | return (void __user *)hva; |
9da0e4d5 PB |
11632 | } |
11633 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
11634 | ||
1aa9b957 JS |
11635 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
11636 | { | |
11637 | kvm_mmu_pre_destroy_vm(kvm); | |
11638 | } | |
11639 | ||
d19a9cd2 ZX |
11640 | void kvm_arch_destroy_vm(struct kvm *kvm) |
11641 | { | |
27469d29 AH |
11642 | if (current->mm == kvm->mm) { |
11643 | /* | |
11644 | * Free memory regions allocated on behalf of userspace, | |
11645 | * unless the the memory map has changed due to process exit | |
11646 | * or fd copying. | |
11647 | */ | |
6a3c623b PX |
11648 | mutex_lock(&kvm->slots_lock); |
11649 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
11650 | 0, 0); | |
11651 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
11652 | 0, 0); | |
11653 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
11654 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 11655 | } |
b3646477 | 11656 | static_call_cond(kvm_x86_vm_destroy)(kvm); |
b318e8de | 11657 | kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); |
c761159c PX |
11658 | kvm_pic_destroy(kvm); |
11659 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 11660 | kvm_free_vcpus(kvm); |
af1bae54 | 11661 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 11662 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 11663 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 11664 | kvm_page_track_cleanup(kvm); |
7d6bbebb | 11665 | kvm_xen_destroy_vm(kvm); |
cbc0236a | 11666 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 11667 | } |
0de10343 | 11668 | |
c9b929b3 | 11669 | static void memslot_rmap_free(struct kvm_memory_slot *slot) |
db3fe4eb TY |
11670 | { |
11671 | int i; | |
11672 | ||
d89cc617 | 11673 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
11674 | kvfree(slot->arch.rmap[i]); |
11675 | slot->arch.rmap[i] = NULL; | |
c9b929b3 BG |
11676 | } |
11677 | } | |
e96c81ee | 11678 | |
c9b929b3 BG |
11679 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
11680 | { | |
11681 | int i; | |
11682 | ||
11683 | memslot_rmap_free(slot); | |
d89cc617 | 11684 | |
c9b929b3 | 11685 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
11686 | kvfree(slot->arch.lpage_info[i - 1]); |
11687 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 11688 | } |
21ebbeda | 11689 | |
e96c81ee | 11690 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
11691 | } |
11692 | ||
1e76a3ce | 11693 | int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) |
56dd1019 BG |
11694 | { |
11695 | const int sz = sizeof(*slot->arch.rmap[0]); | |
11696 | int i; | |
11697 | ||
11698 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { | |
11699 | int level = i + 1; | |
4139b197 | 11700 | int lpages = __kvm_mmu_slot_lpages(slot, npages, level); |
56dd1019 | 11701 | |
fa13843d PB |
11702 | if (slot->arch.rmap[i]) |
11703 | continue; | |
d501f747 | 11704 | |
56dd1019 BG |
11705 | slot->arch.rmap[i] = kvcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); |
11706 | if (!slot->arch.rmap[i]) { | |
11707 | memslot_rmap_free(slot); | |
11708 | return -ENOMEM; | |
11709 | } | |
11710 | } | |
11711 | ||
11712 | return 0; | |
11713 | } | |
11714 | ||
a2557408 BG |
11715 | static int kvm_alloc_memslot_metadata(struct kvm *kvm, |
11716 | struct kvm_memory_slot *slot, | |
0dab98b7 | 11717 | unsigned long npages) |
db3fe4eb | 11718 | { |
56dd1019 | 11719 | int i, r; |
db3fe4eb | 11720 | |
edd4fa37 SC |
11721 | /* |
11722 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
11723 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
11724 | * the new memslot is successful. | |
11725 | */ | |
11726 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
11727 | ||
e2209710 | 11728 | if (kvm_memslots_have_rmaps(kvm)) { |
a2557408 BG |
11729 | r = memslot_rmap_alloc(slot, npages); |
11730 | if (r) | |
11731 | return r; | |
11732 | } | |
56dd1019 BG |
11733 | |
11734 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { | |
92f94f1e | 11735 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
11736 | unsigned long ugfn; |
11737 | int lpages; | |
d89cc617 | 11738 | int level = i + 1; |
db3fe4eb | 11739 | |
4139b197 | 11740 | lpages = __kvm_mmu_slot_lpages(slot, npages, level); |
db3fe4eb | 11741 | |
254272ce | 11742 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 11743 | if (!linfo) |
db3fe4eb TY |
11744 | goto out_free; |
11745 | ||
92f94f1e XG |
11746 | slot->arch.lpage_info[i - 1] = linfo; |
11747 | ||
db3fe4eb | 11748 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 11749 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 11750 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 11751 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
11752 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
11753 | /* | |
11754 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 11755 | * other, disable large page support for this slot. |
db3fe4eb | 11756 | */ |
600087b6 | 11757 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
11758 | unsigned long j; |
11759 | ||
11760 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 11761 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
11762 | } |
11763 | } | |
11764 | ||
deae4a10 | 11765 | if (kvm_page_track_create_memslot(kvm, slot, npages)) |
21ebbeda XG |
11766 | goto out_free; |
11767 | ||
db3fe4eb TY |
11768 | return 0; |
11769 | ||
11770 | out_free: | |
c9b929b3 | 11771 | memslot_rmap_free(slot); |
d89cc617 | 11772 | |
c9b929b3 | 11773 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 11774 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 11775 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
11776 | } |
11777 | return -ENOMEM; | |
11778 | } | |
11779 | ||
15248258 | 11780 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 11781 | { |
91724814 BO |
11782 | struct kvm_vcpu *vcpu; |
11783 | int i; | |
11784 | ||
e6dff7d1 TY |
11785 | /* |
11786 | * memslots->generation has been incremented. | |
11787 | * mmio generation may have reached its maximum value. | |
11788 | */ | |
15248258 | 11789 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
11790 | |
11791 | /* Force re-initialization of steal_time cache */ | |
11792 | kvm_for_each_vcpu(i, vcpu, kvm) | |
11793 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
11794 | } |
11795 | ||
f7784b8e MT |
11796 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
11797 | struct kvm_memory_slot *memslot, | |
09170a49 | 11798 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 11799 | enum kvm_mr_change change) |
0de10343 | 11800 | { |
0dab98b7 | 11801 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) |
a2557408 | 11802 | return kvm_alloc_memslot_metadata(kvm, memslot, |
0dab98b7 | 11803 | mem->memory_size >> PAGE_SHIFT); |
f7784b8e MT |
11804 | return 0; |
11805 | } | |
11806 | ||
a85863c2 MS |
11807 | |
11808 | static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) | |
11809 | { | |
11810 | struct kvm_arch *ka = &kvm->arch; | |
11811 | ||
11812 | if (!kvm_x86_ops.cpu_dirty_log_size) | |
11813 | return; | |
11814 | ||
11815 | if ((enable && ++ka->cpu_dirty_logging_count == 1) || | |
11816 | (!enable && --ka->cpu_dirty_logging_count == 0)) | |
11817 | kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); | |
11818 | ||
11819 | WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); | |
11820 | } | |
11821 | ||
88178fd4 | 11822 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b | 11823 | struct kvm_memory_slot *old, |
269e9552 | 11824 | const struct kvm_memory_slot *new, |
3741679b | 11825 | enum kvm_mr_change change) |
88178fd4 | 11826 | { |
a85863c2 MS |
11827 | bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; |
11828 | ||
3741679b | 11829 | /* |
a85863c2 MS |
11830 | * Update CPU dirty logging if dirty logging is being toggled. This |
11831 | * applies to all operations. | |
3741679b | 11832 | */ |
a85863c2 MS |
11833 | if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) |
11834 | kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); | |
88178fd4 KH |
11835 | |
11836 | /* | |
a85863c2 | 11837 | * Nothing more to do for RO slots (which can't be dirtied and can't be |
b6e16ae5 | 11838 | * made writable) or CREATE/MOVE/DELETE of a slot. |
88178fd4 | 11839 | * |
b6e16ae5 | 11840 | * For a memslot with dirty logging disabled: |
3741679b AY |
11841 | * CREATE: No dirty mappings will already exist. |
11842 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
11843 | * kvm_arch_flush_shadow_memslot() | |
b6e16ae5 SC |
11844 | * |
11845 | * For a memslot with dirty logging enabled: | |
11846 | * CREATE: No shadow pages exist, thus nothing to write-protect | |
11847 | * and no dirty bits to clear. | |
11848 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
11849 | * kvm_arch_flush_shadow_memslot(). | |
3741679b | 11850 | */ |
3741679b | 11851 | if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) |
88178fd4 | 11852 | return; |
3741679b AY |
11853 | |
11854 | /* | |
52f46079 SC |
11855 | * READONLY and non-flags changes were filtered out above, and the only |
11856 | * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty | |
11857 | * logging isn't being toggled on or off. | |
88178fd4 | 11858 | */ |
52f46079 SC |
11859 | if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) |
11860 | return; | |
11861 | ||
b6e16ae5 SC |
11862 | if (!log_dirty_pages) { |
11863 | /* | |
11864 | * Dirty logging tracks sptes in 4k granularity, meaning that | |
11865 | * large sptes have to be split. If live migration succeeds, | |
11866 | * the guest in the source machine will be destroyed and large | |
11867 | * sptes will be created in the destination. However, if the | |
11868 | * guest continues to run in the source machine (for example if | |
11869 | * live migration fails), small sptes will remain around and | |
11870 | * cause bad performance. | |
11871 | * | |
11872 | * Scan sptes if dirty logging has been stopped, dropping those | |
11873 | * which can be collapsed into a single large-page spte. Later | |
11874 | * page faults will create the large-page sptes. | |
11875 | */ | |
3741679b | 11876 | kvm_mmu_zap_collapsible_sptes(kvm, new); |
b6e16ae5 | 11877 | } else { |
89212919 KZ |
11878 | /* |
11879 | * Initially-all-set does not require write protecting any page, | |
11880 | * because they're all assumed to be dirty. | |
11881 | */ | |
11882 | if (kvm_dirty_log_manual_protect_and_init_set(kvm)) | |
11883 | return; | |
a1419f8b | 11884 | |
a018eba5 | 11885 | if (kvm_x86_ops.cpu_dirty_log_size) { |
89212919 KZ |
11886 | kvm_mmu_slot_leaf_clear_dirty(kvm, new); |
11887 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); | |
11888 | } else { | |
11889 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); | |
3c9bd400 | 11890 | } |
88178fd4 KH |
11891 | } |
11892 | } | |
11893 | ||
f7784b8e | 11894 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 11895 | const struct kvm_userspace_memory_region *mem, |
9d4c197c | 11896 | struct kvm_memory_slot *old, |
f36f3f28 | 11897 | const struct kvm_memory_slot *new, |
8482644a | 11898 | enum kvm_mr_change change) |
f7784b8e | 11899 | { |
48c0e4e9 | 11900 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
11901 | kvm_mmu_change_mmu_pages(kvm, |
11902 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 11903 | |
269e9552 | 11904 | kvm_mmu_slot_apply_flags(kvm, old, new, change); |
21198846 SC |
11905 | |
11906 | /* Free the arrays associated with the old memslot. */ | |
11907 | if (change == KVM_MR_MOVE) | |
e96c81ee | 11908 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 11909 | } |
1d737c8a | 11910 | |
2df72e9b | 11911 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 11912 | { |
7390de1e | 11913 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
11914 | } |
11915 | ||
2df72e9b MT |
11916 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
11917 | struct kvm_memory_slot *slot) | |
11918 | { | |
ae7cd873 | 11919 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
11920 | } |
11921 | ||
e6c67d8c LA |
11922 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
11923 | { | |
11924 | return (is_guest_mode(vcpu) && | |
afaf0b2f | 11925 | kvm_x86_ops.guest_apic_has_interrupt && |
b3646477 | 11926 | static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); |
e6c67d8c LA |
11927 | } |
11928 | ||
5d9bc648 PB |
11929 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
11930 | { | |
11931 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
11932 | return true; | |
11933 | ||
11934 | if (kvm_apic_has_events(vcpu)) | |
11935 | return true; | |
11936 | ||
11937 | if (vcpu->arch.pv.pv_unhalted) | |
11938 | return true; | |
11939 | ||
a5f01f8e WL |
11940 | if (vcpu->arch.exception.pending) |
11941 | return true; | |
11942 | ||
47a66eed Z |
11943 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
11944 | (vcpu->arch.nmi_pending && | |
b3646477 | 11945 | static_call(kvm_x86_nmi_allowed)(vcpu, false))) |
5d9bc648 PB |
11946 | return true; |
11947 | ||
47a66eed | 11948 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 11949 | (vcpu->arch.smi_pending && |
b3646477 | 11950 | static_call(kvm_x86_smi_allowed)(vcpu, false))) |
73917739 PB |
11951 | return true; |
11952 | ||
5d9bc648 | 11953 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
11954 | (kvm_cpu_has_interrupt(vcpu) || |
11955 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
11956 | return true; |
11957 | ||
1f4b34f8 AS |
11958 | if (kvm_hv_has_stimer_pending(vcpu)) |
11959 | return true; | |
11960 | ||
d2060bd4 SC |
11961 | if (is_guest_mode(vcpu) && |
11962 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
11963 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
11964 | return true; | |
11965 | ||
5d9bc648 PB |
11966 | return false; |
11967 | } | |
11968 | ||
1d737c8a ZX |
11969 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
11970 | { | |
5d9bc648 | 11971 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 11972 | } |
5736199a | 11973 | |
10dbdf98 | 11974 | bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) |
17e433b5 | 11975 | { |
b3646477 | 11976 | if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) |
52acd22f WL |
11977 | return true; |
11978 | ||
11979 | return false; | |
11980 | } | |
11981 | ||
17e433b5 WL |
11982 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
11983 | { | |
11984 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
11985 | return true; | |
11986 | ||
11987 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
11988 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
11989 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
11990 | return true; | |
11991 | ||
10dbdf98 | 11992 | return kvm_arch_dy_has_pending_interrupt(vcpu); |
17e433b5 WL |
11993 | } |
11994 | ||
199b5763 LM |
11995 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
11996 | { | |
b86bb11e WL |
11997 | if (vcpu->arch.guest_state_protected) |
11998 | return true; | |
11999 | ||
de63ad4c | 12000 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
12001 | } |
12002 | ||
b6d33834 | 12003 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 12004 | { |
b6d33834 | 12005 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 12006 | } |
78646121 GN |
12007 | |
12008 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
12009 | { | |
b3646477 | 12010 | return static_call(kvm_x86_interrupt_allowed)(vcpu, false); |
78646121 | 12011 | } |
229456fc | 12012 | |
82b32774 | 12013 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 12014 | { |
7ed9abfe TL |
12015 | /* Can't read the RIP when guest state is protected, just return 0 */ |
12016 | if (vcpu->arch.guest_state_protected) | |
12017 | return 0; | |
12018 | ||
82b32774 NA |
12019 | if (is_64_bit_mode(vcpu)) |
12020 | return kvm_rip_read(vcpu); | |
12021 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
12022 | kvm_rip_read(vcpu)); | |
12023 | } | |
12024 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 12025 | |
82b32774 NA |
12026 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
12027 | { | |
12028 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
12029 | } |
12030 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
12031 | ||
94fe45da JK |
12032 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
12033 | { | |
12034 | unsigned long rflags; | |
12035 | ||
b3646477 | 12036 | rflags = static_call(kvm_x86_get_rflags)(vcpu); |
94fe45da | 12037 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 12038 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
12039 | return rflags; |
12040 | } | |
12041 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
12042 | ||
6addfc42 | 12043 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
12044 | { |
12045 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 12046 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 12047 | rflags |= X86_EFLAGS_TF; |
b3646477 | 12048 | static_call(kvm_x86_set_rflags)(vcpu, rflags); |
6addfc42 PB |
12049 | } |
12050 | ||
12051 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
12052 | { | |
12053 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 12054 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
12055 | } |
12056 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
12057 | ||
56028d08 GN |
12058 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
12059 | { | |
12060 | int r; | |
12061 | ||
44dd3ffa | 12062 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 12063 | work->wakeup_all) |
56028d08 GN |
12064 | return; |
12065 | ||
12066 | r = kvm_mmu_reload(vcpu); | |
12067 | if (unlikely(r)) | |
12068 | return; | |
12069 | ||
44dd3ffa | 12070 | if (!vcpu->arch.mmu->direct_map && |
d8dd54e0 | 12071 | work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) |
fb67e14f XG |
12072 | return; |
12073 | ||
7a02674d | 12074 | kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); |
56028d08 GN |
12075 | } |
12076 | ||
af585b92 GN |
12077 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
12078 | { | |
dd03bcaa PX |
12079 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
12080 | ||
af585b92 GN |
12081 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
12082 | } | |
12083 | ||
12084 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
12085 | { | |
dd03bcaa | 12086 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
12087 | } |
12088 | ||
12089 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
12090 | { | |
12091 | u32 key = kvm_async_pf_hash_fn(gfn); | |
12092 | ||
12093 | while (vcpu->arch.apf.gfns[key] != ~0) | |
12094 | key = kvm_async_pf_next_probe(key); | |
12095 | ||
12096 | vcpu->arch.apf.gfns[key] = gfn; | |
12097 | } | |
12098 | ||
12099 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
12100 | { | |
12101 | int i; | |
12102 | u32 key = kvm_async_pf_hash_fn(gfn); | |
12103 | ||
dd03bcaa | 12104 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
12105 | (vcpu->arch.apf.gfns[key] != gfn && |
12106 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
12107 | key = kvm_async_pf_next_probe(key); |
12108 | ||
12109 | return key; | |
12110 | } | |
12111 | ||
12112 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
12113 | { | |
12114 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
12115 | } | |
12116 | ||
12117 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
12118 | { | |
12119 | u32 i, j, k; | |
12120 | ||
12121 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
12122 | |
12123 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
12124 | return; | |
12125 | ||
af585b92 GN |
12126 | while (true) { |
12127 | vcpu->arch.apf.gfns[i] = ~0; | |
12128 | do { | |
12129 | j = kvm_async_pf_next_probe(j); | |
12130 | if (vcpu->arch.apf.gfns[j] == ~0) | |
12131 | return; | |
12132 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
12133 | /* | |
12134 | * k lies cyclically in ]i,j] | |
12135 | * | i.k.j | | |
12136 | * |....j i.k.| or |.k..j i...| | |
12137 | */ | |
12138 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
12139 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
12140 | i = j; | |
12141 | } | |
12142 | } | |
12143 | ||
68fd66f1 | 12144 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 12145 | { |
68fd66f1 VK |
12146 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
12147 | ||
12148 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
12149 | sizeof(reason)); | |
12150 | } | |
12151 | ||
12152 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
12153 | { | |
2635b5c4 | 12154 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 12155 | |
2635b5c4 VK |
12156 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
12157 | &token, offset, sizeof(token)); | |
12158 | } | |
12159 | ||
12160 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
12161 | { | |
12162 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
12163 | u32 val; | |
12164 | ||
12165 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
12166 | &val, offset, sizeof(val))) | |
12167 | return false; | |
12168 | ||
12169 | return !val; | |
7c90705b GN |
12170 | } |
12171 | ||
1dfdb45e PB |
12172 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
12173 | { | |
12174 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
12175 | return false; | |
12176 | ||
2635b5c4 | 12177 | if (!kvm_pv_async_pf_enabled(vcpu) || |
b3646477 | 12178 | (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) |
1dfdb45e PB |
12179 | return false; |
12180 | ||
12181 | return true; | |
12182 | } | |
12183 | ||
12184 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
12185 | { | |
12186 | if (unlikely(!lapic_in_kernel(vcpu) || | |
12187 | kvm_event_needs_reinjection(vcpu) || | |
12188 | vcpu->arch.exception.pending)) | |
12189 | return false; | |
12190 | ||
12191 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
12192 | return false; | |
12193 | ||
12194 | /* | |
12195 | * If interrupts are off we cannot even use an artificial | |
12196 | * halt state. | |
12197 | */ | |
c300ab9f | 12198 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
12199 | } |
12200 | ||
2a18b7e7 | 12201 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
12202 | struct kvm_async_pf *work) |
12203 | { | |
6389ee94 AK |
12204 | struct x86_exception fault; |
12205 | ||
736c291c | 12206 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 12207 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 12208 | |
1dfdb45e | 12209 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 12210 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
12211 | fault.vector = PF_VECTOR; |
12212 | fault.error_code_valid = true; | |
12213 | fault.error_code = 0; | |
12214 | fault.nested_page_fault = false; | |
12215 | fault.address = work->arch.token; | |
adfe20fb | 12216 | fault.async_page_fault = true; |
6389ee94 | 12217 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 12218 | return true; |
1dfdb45e PB |
12219 | } else { |
12220 | /* | |
12221 | * It is not possible to deliver a paravirtualized asynchronous | |
12222 | * page fault, but putting the guest in an artificial halt state | |
12223 | * can be beneficial nevertheless: if an interrupt arrives, we | |
12224 | * can deliver it timely and perhaps the guest will schedule | |
12225 | * another process. When the instruction that triggered a page | |
12226 | * fault is retried, hopefully the page will be ready in the host. | |
12227 | */ | |
12228 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 12229 | return false; |
7c90705b | 12230 | } |
af585b92 GN |
12231 | } |
12232 | ||
12233 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
12234 | struct kvm_async_pf *work) | |
12235 | { | |
2635b5c4 VK |
12236 | struct kvm_lapic_irq irq = { |
12237 | .delivery_mode = APIC_DM_FIXED, | |
12238 | .vector = vcpu->arch.apf.vec | |
12239 | }; | |
6389ee94 | 12240 | |
f2e10669 | 12241 | if (work->wakeup_all) |
7c90705b GN |
12242 | work->arch.token = ~0; /* broadcast wakeup */ |
12243 | else | |
12244 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 12245 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 12246 | |
2a18b7e7 VK |
12247 | if ((work->wakeup_all || work->notpresent_injected) && |
12248 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
12249 | !apf_put_user_ready(vcpu, work->arch.token)) { |
12250 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 12251 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 12252 | } |
2635b5c4 | 12253 | |
e6d53e3b | 12254 | vcpu->arch.apf.halted = false; |
a4fa1635 | 12255 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
12256 | } |
12257 | ||
557a961a VK |
12258 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
12259 | { | |
12260 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
12261 | if (!vcpu->arch.apf.pageready_pending) | |
12262 | kvm_vcpu_kick(vcpu); | |
12263 | } | |
12264 | ||
7c0ade6c | 12265 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 12266 | { |
2635b5c4 | 12267 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
12268 | return true; |
12269 | else | |
2f15d027 | 12270 | return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); |
af585b92 GN |
12271 | } |
12272 | ||
5544eb9b PB |
12273 | void kvm_arch_start_assignment(struct kvm *kvm) |
12274 | { | |
57ab8794 MT |
12275 | if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) |
12276 | static_call_cond(kvm_x86_start_assignment)(kvm); | |
5544eb9b PB |
12277 | } |
12278 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
12279 | ||
12280 | void kvm_arch_end_assignment(struct kvm *kvm) | |
12281 | { | |
12282 | atomic_dec(&kvm->arch.assigned_device_count); | |
12283 | } | |
12284 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
12285 | ||
12286 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
12287 | { | |
12288 | return atomic_read(&kvm->arch.assigned_device_count); | |
12289 | } | |
12290 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
12291 | ||
e0f0bbc5 AW |
12292 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
12293 | { | |
12294 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
12295 | } | |
12296 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
12297 | ||
12298 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
12299 | { | |
12300 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
12301 | } | |
12302 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
12303 | ||
12304 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
12305 | { | |
12306 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
12307 | } | |
12308 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
12309 | ||
14717e20 AW |
12310 | bool kvm_arch_has_irq_bypass(void) |
12311 | { | |
92735b1b | 12312 | return true; |
14717e20 AW |
12313 | } |
12314 | ||
87276880 FW |
12315 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
12316 | struct irq_bypass_producer *prod) | |
12317 | { | |
12318 | struct kvm_kernel_irqfd *irqfd = | |
12319 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 12320 | int ret; |
87276880 | 12321 | |
14717e20 | 12322 | irqfd->producer = prod; |
2edd9cb7 | 12323 | kvm_arch_start_assignment(irqfd->kvm); |
b3646477 | 12324 | ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, |
2edd9cb7 ZL |
12325 | prod->irq, irqfd->gsi, 1); |
12326 | ||
12327 | if (ret) | |
12328 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 12329 | |
2edd9cb7 | 12330 | return ret; |
87276880 FW |
12331 | } |
12332 | ||
12333 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
12334 | struct irq_bypass_producer *prod) | |
12335 | { | |
12336 | int ret; | |
12337 | struct kvm_kernel_irqfd *irqfd = | |
12338 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
12339 | ||
87276880 FW |
12340 | WARN_ON(irqfd->producer != prod); |
12341 | irqfd->producer = NULL; | |
12342 | ||
12343 | /* | |
12344 | * When producer of consumer is unregistered, we change back to | |
12345 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 12346 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
12347 | * int this case doesn't want to receive the interrupts. |
12348 | */ | |
b3646477 | 12349 | ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
12350 | if (ret) |
12351 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
12352 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
12353 | |
12354 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
12355 | } |
12356 | ||
12357 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
12358 | uint32_t guest_irq, bool set) | |
12359 | { | |
b3646477 | 12360 | return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); |
87276880 FW |
12361 | } |
12362 | ||
515a0c79 LM |
12363 | bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, |
12364 | struct kvm_kernel_irq_routing_entry *new) | |
12365 | { | |
12366 | if (new->type != KVM_IRQ_ROUTING_MSI) | |
12367 | return true; | |
12368 | ||
12369 | return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); | |
12370 | } | |
12371 | ||
52004014 FW |
12372 | bool kvm_vector_hashing_enabled(void) |
12373 | { | |
12374 | return vector_hashing; | |
12375 | } | |
52004014 | 12376 | |
2d5ba19b MT |
12377 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
12378 | { | |
12379 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
12380 | } | |
12381 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
12382 | ||
841c2be0 ML |
12383 | |
12384 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 12385 | { |
841c2be0 ML |
12386 | /* |
12387 | * test that setting IA32_SPEC_CTRL to given value | |
12388 | * is allowed by the host processor | |
12389 | */ | |
6441fa61 | 12390 | |
841c2be0 ML |
12391 | u64 saved_value; |
12392 | unsigned long flags; | |
12393 | int ret = 0; | |
6441fa61 | 12394 | |
841c2be0 | 12395 | local_irq_save(flags); |
6441fa61 | 12396 | |
841c2be0 ML |
12397 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
12398 | ret = 1; | |
12399 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
12400 | ret = 1; | |
12401 | else | |
12402 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 12403 | |
841c2be0 | 12404 | local_irq_restore(flags); |
6441fa61 | 12405 | |
841c2be0 | 12406 | return ret; |
6441fa61 | 12407 | } |
841c2be0 | 12408 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 12409 | |
89786147 MG |
12410 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
12411 | { | |
12412 | struct x86_exception fault; | |
19cf4b7e PB |
12413 | u32 access = error_code & |
12414 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); | |
89786147 MG |
12415 | |
12416 | if (!(error_code & PFERR_PRESENT_MASK) || | |
19cf4b7e | 12417 | vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { |
89786147 MG |
12418 | /* |
12419 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
12420 | * tables probably do not match the TLB. Just proceed | |
12421 | * with the error code that the processor gave. | |
12422 | */ | |
12423 | fault.vector = PF_VECTOR; | |
12424 | fault.error_code_valid = true; | |
12425 | fault.error_code = error_code; | |
12426 | fault.nested_page_fault = false; | |
12427 | fault.address = gva; | |
12428 | } | |
12429 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 12430 | } |
89786147 | 12431 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 12432 | |
3f3393b3 BM |
12433 | /* |
12434 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
12435 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
12436 | * indicates whether exit to userspace is needed. | |
12437 | */ | |
12438 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
12439 | struct x86_exception *e) | |
12440 | { | |
12441 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
12442 | kvm_inject_emulated_page_fault(vcpu, e); | |
12443 | return 1; | |
12444 | } | |
12445 | ||
12446 | /* | |
12447 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
12448 | * while handling a VMX instruction KVM could've handled the request | |
12449 | * correctly by exiting to userspace and performing I/O but there | |
12450 | * doesn't seem to be a real use-case behind such requests, just return | |
12451 | * KVM_EXIT_INTERNAL_ERROR for now. | |
12452 | */ | |
e615e355 | 12453 | kvm_prepare_emulation_failure_exit(vcpu); |
3f3393b3 BM |
12454 | |
12455 | return 0; | |
12456 | } | |
12457 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
12458 | ||
9715092f BM |
12459 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
12460 | { | |
12461 | bool pcid_enabled; | |
12462 | struct x86_exception e; | |
9715092f BM |
12463 | struct { |
12464 | u64 pcid; | |
12465 | u64 gla; | |
12466 | } operand; | |
12467 | int r; | |
12468 | ||
12469 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
12470 | if (r != X86EMUL_CONTINUE) | |
12471 | return kvm_handle_memory_failure(vcpu, r, &e); | |
12472 | ||
12473 | if (operand.pcid >> 12 != 0) { | |
12474 | kvm_inject_gp(vcpu, 0); | |
12475 | return 1; | |
12476 | } | |
12477 | ||
12478 | pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); | |
12479 | ||
12480 | switch (type) { | |
12481 | case INVPCID_TYPE_INDIV_ADDR: | |
12482 | if ((!pcid_enabled && (operand.pcid != 0)) || | |
12483 | is_noncanonical_address(operand.gla, vcpu)) { | |
12484 | kvm_inject_gp(vcpu, 0); | |
12485 | return 1; | |
12486 | } | |
12487 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
12488 | return kvm_skip_emulated_instruction(vcpu); | |
12489 | ||
12490 | case INVPCID_TYPE_SINGLE_CTXT: | |
12491 | if (!pcid_enabled && (operand.pcid != 0)) { | |
12492 | kvm_inject_gp(vcpu, 0); | |
12493 | return 1; | |
12494 | } | |
12495 | ||
21823fbd | 12496 | kvm_invalidate_pcid(vcpu, operand.pcid); |
9715092f BM |
12497 | return kvm_skip_emulated_instruction(vcpu); |
12498 | ||
12499 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
12500 | /* | |
12501 | * Currently, KVM doesn't mark global entries in the shadow | |
12502 | * page tables, so a non-global flush just degenerates to a | |
12503 | * global flush. If needed, we could optimize this later by | |
12504 | * keeping track of global entries in shadow page tables. | |
12505 | */ | |
12506 | ||
12507 | fallthrough; | |
12508 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
28f28d45 | 12509 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
9715092f BM |
12510 | return kvm_skip_emulated_instruction(vcpu); |
12511 | ||
12512 | default: | |
12513 | BUG(); /* We have already checked above that type <= 3 */ | |
12514 | } | |
12515 | } | |
12516 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
12517 | ||
8f423a80 TL |
12518 | static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) |
12519 | { | |
12520 | struct kvm_run *run = vcpu->run; | |
12521 | struct kvm_mmio_fragment *frag; | |
12522 | unsigned int len; | |
12523 | ||
12524 | BUG_ON(!vcpu->mmio_needed); | |
12525 | ||
12526 | /* Complete previous fragment */ | |
12527 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
12528 | len = min(8u, frag->len); | |
12529 | if (!vcpu->mmio_is_write) | |
12530 | memcpy(frag->data, run->mmio.data, len); | |
12531 | ||
12532 | if (frag->len <= 8) { | |
12533 | /* Switch to the next fragment. */ | |
12534 | frag++; | |
12535 | vcpu->mmio_cur_fragment++; | |
12536 | } else { | |
12537 | /* Go forward to the next mmio piece. */ | |
12538 | frag->data += len; | |
12539 | frag->gpa += len; | |
12540 | frag->len -= len; | |
12541 | } | |
12542 | ||
12543 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { | |
12544 | vcpu->mmio_needed = 0; | |
12545 | ||
12546 | // VMG change, at this point, we're always done | |
12547 | // RIP has already been advanced | |
12548 | return 1; | |
12549 | } | |
12550 | ||
12551 | // More MMIO is needed | |
12552 | run->mmio.phys_addr = frag->gpa; | |
12553 | run->mmio.len = min(8u, frag->len); | |
12554 | run->mmio.is_write = vcpu->mmio_is_write; | |
12555 | if (run->mmio.is_write) | |
12556 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
12557 | run->exit_reason = KVM_EXIT_MMIO; | |
12558 | ||
12559 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12560 | ||
12561 | return 0; | |
12562 | } | |
12563 | ||
12564 | int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
12565 | void *data) | |
12566 | { | |
12567 | int handled; | |
12568 | struct kvm_mmio_fragment *frag; | |
12569 | ||
12570 | if (!data) | |
12571 | return -EINVAL; | |
12572 | ||
12573 | handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
12574 | if (handled == bytes) | |
12575 | return 1; | |
12576 | ||
12577 | bytes -= handled; | |
12578 | gpa += handled; | |
12579 | data += handled; | |
12580 | ||
12581 | /*TODO: Check if need to increment number of frags */ | |
12582 | frag = vcpu->mmio_fragments; | |
12583 | vcpu->mmio_nr_fragments = 1; | |
12584 | frag->len = bytes; | |
12585 | frag->gpa = gpa; | |
12586 | frag->data = data; | |
12587 | ||
12588 | vcpu->mmio_needed = 1; | |
12589 | vcpu->mmio_cur_fragment = 0; | |
12590 | ||
12591 | vcpu->run->mmio.phys_addr = gpa; | |
12592 | vcpu->run->mmio.len = min(8u, frag->len); | |
12593 | vcpu->run->mmio.is_write = 1; | |
12594 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
12595 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
12596 | ||
12597 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12598 | ||
12599 | return 0; | |
12600 | } | |
12601 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); | |
12602 | ||
12603 | int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
12604 | void *data) | |
12605 | { | |
12606 | int handled; | |
12607 | struct kvm_mmio_fragment *frag; | |
12608 | ||
12609 | if (!data) | |
12610 | return -EINVAL; | |
12611 | ||
12612 | handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
12613 | if (handled == bytes) | |
12614 | return 1; | |
12615 | ||
12616 | bytes -= handled; | |
12617 | gpa += handled; | |
12618 | data += handled; | |
12619 | ||
12620 | /*TODO: Check if need to increment number of frags */ | |
12621 | frag = vcpu->mmio_fragments; | |
12622 | vcpu->mmio_nr_fragments = 1; | |
12623 | frag->len = bytes; | |
12624 | frag->gpa = gpa; | |
12625 | frag->data = data; | |
12626 | ||
12627 | vcpu->mmio_needed = 1; | |
12628 | vcpu->mmio_cur_fragment = 0; | |
12629 | ||
12630 | vcpu->run->mmio.phys_addr = gpa; | |
12631 | vcpu->run->mmio.len = min(8u, frag->len); | |
12632 | vcpu->run->mmio.is_write = 0; | |
12633 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
12634 | ||
12635 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
12636 | ||
12637 | return 0; | |
12638 | } | |
12639 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); | |
12640 | ||
7ed9abfe TL |
12641 | static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) |
12642 | { | |
12643 | memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, | |
12644 | vcpu->arch.pio.count * vcpu->arch.pio.size); | |
12645 | vcpu->arch.pio.count = 0; | |
12646 | ||
12647 | return 1; | |
12648 | } | |
12649 | ||
12650 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, | |
12651 | unsigned int port, void *data, unsigned int count) | |
12652 | { | |
12653 | int ret; | |
12654 | ||
12655 | ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, | |
12656 | data, count); | |
12657 | if (ret) | |
12658 | return ret; | |
12659 | ||
12660 | vcpu->arch.pio.count = 0; | |
12661 | ||
12662 | return 0; | |
12663 | } | |
12664 | ||
12665 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, | |
12666 | unsigned int port, void *data, unsigned int count) | |
12667 | { | |
12668 | int ret; | |
12669 | ||
12670 | ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, | |
12671 | data, count); | |
12672 | if (ret) { | |
12673 | vcpu->arch.pio.count = 0; | |
12674 | } else { | |
12675 | vcpu->arch.guest_ins_data = data; | |
12676 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; | |
12677 | } | |
12678 | ||
12679 | return 0; | |
12680 | } | |
12681 | ||
12682 | int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, | |
12683 | unsigned int port, void *data, unsigned int count, | |
12684 | int in) | |
12685 | { | |
12686 | return in ? kvm_sev_es_ins(vcpu, size, port, data, count) | |
12687 | : kvm_sev_es_outs(vcpu, size, port, data, count); | |
12688 | } | |
12689 | EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); | |
12690 | ||
d95df951 | 12691 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); |
229456fc | 12692 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 12693 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
12694 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
12695 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
12696 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
12697 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 12698 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 12699 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 12700 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 12701 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 12702 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 12703 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 12704 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 12705 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 12706 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 12707 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 12708 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 12709 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
12710 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
12711 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 12712 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
24bbf74c | 12713 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); |
d523ab6b TL |
12714 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); |
12715 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); | |
59e38b58 TL |
12716 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); |
12717 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); |