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KVM/nVMX: Use kvm_vcpu_map when mapping the posted interrupt descriptor table
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
bf8c55d8 72#include <asm/intel_pt.h>
043405e1 73
d1898b73
DH		 74#define CREATE_TRACE_POINTS
75#include "trace.h"
76
313a3dc7 77#define MAX_IO_MSRS 256
890ca9ae 78#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 79u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 81
0f65dd70
AK		 82#define emul_to_vcpu(ctxt) \
83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
84
50a37eb4
JR		 85/* EFER defaults:
86 * - enable syscall per default because its emulated by KVM
87 * - enable LME and LMA per default on 64 bit KVM
88 */
89#ifdef CONFIG_X86_64
1260edbe
LJ		 90static
91u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 92#else
1260edbe 93static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 94#endif
313a3dc7 95
ba1389b7
AK		 96#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
97#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 98
c519265f
RK		 99#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
100 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 101
cb142eb7 102static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 103static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 104static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 105static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 106static void store_regs(struct kvm_vcpu *vcpu);
107static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 108
893590c7 109struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 110EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 111
893590c7 112static bool __read_mostly ignore_msrs = 0;
476bc001 113module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 114
fab0aa3b
EM		 115static bool __read_mostly report_ignored_msrs = true;
116module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117
4c27625b 118unsigned int min_timer_period_us = 200;
9ed96e87
MT		 119module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120
630994b3
MT		 121static bool __read_mostly kvmclock_periodic_sync = true;
122module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123
893590c7 124bool __read_mostly kvm_has_tsc_control;
92a1f12d 125EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 126u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 127EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 128u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
129EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
130u64 __read_mostly kvm_max_tsc_scaling_ratio;
131EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 132u64 __read_mostly kvm_default_tsc_scaling_ratio;
133EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 134
cc578287 135/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 136static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 137module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
138
d0659d94 139/* lapic timer advance (tscdeadline mode only) in nanoseconds */
3b8a5df6 140unsigned int __read_mostly lapic_timer_advance_ns = 1000;
d0659d94 141module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 142EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 143
52004014
FW		 144static bool __read_mostly vector_hashing = true;
145module_param(vector_hashing, bool, S_IRUGO);
146
c4ae60e4
LA		 147bool __read_mostly enable_vmware_backdoor = false;
148module_param(enable_vmware_backdoor, bool, S_IRUGO);
149EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
150
6c86eedc
WL		 151static bool __read_mostly force_emulation_prefix = false;
152module_param(force_emulation_prefix, bool, S_IRUGO);
153
18863bdd
AK		 154#define KVM_NR_SHARED_MSRS 16
155
156struct kvm_shared_msrs_global {
157 int nr;
2bf78fa7 158 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 159};
160
161struct kvm_shared_msrs {
162 struct user_return_notifier urn;
163 bool registered;
2bf78fa7
SY		 164 struct kvm_shared_msr_values {
165 u64 host;
166 u64 curr;
167 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 168};
169
170static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 171static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 172
417bc304 173struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 174 { "pf_fixed", VCPU_STAT(pf_fixed) },
175 { "pf_guest", VCPU_STAT(pf_guest) },
176 { "tlb_flush", VCPU_STAT(tlb_flush) },
177 { "invlpg", VCPU_STAT(invlpg) },
178 { "exits", VCPU_STAT(exits) },
179 { "io_exits", VCPU_STAT(io_exits) },
180 { "mmio_exits", VCPU_STAT(mmio_exits) },
181 { "signal_exits", VCPU_STAT(signal_exits) },
182 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 183 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 184 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 185 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 186 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 187 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 188 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 189 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 190 { "request_irq", VCPU_STAT(request_irq_exits) },
191 { "irq_exits", VCPU_STAT(irq_exits) },
192 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 193 { "fpu_reload", VCPU_STAT(fpu_reload) },
194 { "insn_emulation", VCPU_STAT(insn_emulation) },
195 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 196 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 197 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 198 { "req_event", VCPU_STAT(req_event) },
c595ceee 199 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 200 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
201 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
202 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
203 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
204 { "mmu_flooded", VM_STAT(mmu_flooded) },
205 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 206 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 207 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 208 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 209 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 210 { "max_mmu_page_hash_collisions",
211 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 212 { NULL }
213};
214
2acf923e
DC		 215u64 __read_mostly host_xcr0;
216
b666a4b6
MO		 217struct kmem_cache *x86_fpu_cache;
218EXPORT_SYMBOL_GPL(x86_fpu_cache);
219
b6785def 220static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 221
af585b92
GN		 222static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
223{
224 int i;
225 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
226 vcpu->arch.apf.gfns[i] = ~0;
227}
228
18863bdd
AK		 229static void kvm_on_user_return(struct user_return_notifier *urn)
230{
231 unsigned slot;
18863bdd
AK		 232 struct kvm_shared_msrs *locals
233 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 234 struct kvm_shared_msr_values *values;
1650b4eb
IA		 235 unsigned long flags;
236
237 /*
238 * Disabling irqs at this point since the following code could be
239 * interrupted and executed through kvm_arch_hardware_disable()
240 */
241 local_irq_save(flags);
242 if (locals->registered) {
243 locals->registered = false;
244 user_return_notifier_unregister(urn);
245 }
246 local_irq_restore(flags);
18863bdd 247 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 248 values = &locals->values[slot];
249 if (values->host != values->curr) {
250 wrmsrl(shared_msrs_global.msrs[slot], values->host);
251 values->curr = values->host;
18863bdd
AK		 252 }
253 }
18863bdd
AK		 254}
255
2bf78fa7 256static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 257{
18863bdd 258 u64 value;
013f6a5d
MT		 259 unsigned int cpu = smp_processor_id();
260 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 261
2bf78fa7
SY		 262 /* only read, and nobody should modify it at this time,
263 * so don't need lock */
264 if (slot >= shared_msrs_global.nr) {
265 printk(KERN_ERR "kvm: invalid MSR slot!");
266 return;
267 }
268 rdmsrl_safe(msr, &value);
269 smsr->values[slot].host = value;
270 smsr->values[slot].curr = value;
271}
272
273void kvm_define_shared_msr(unsigned slot, u32 msr)
274{
0123be42 275 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 276 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 277 if (slot >= shared_msrs_global.nr)
278 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 279}
280EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
281
282static void kvm_shared_msr_cpu_online(void)
283{
284 unsigned i;
18863bdd
AK		 285
286 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 287 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 288}
289
8b3c3104 290int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 291{
013f6a5d
MT		 292 unsigned int cpu = smp_processor_id();
293 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 294 int err;
18863bdd 295
2bf78fa7 296 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 297 return 0;
2bf78fa7 298 smsr->values[slot].curr = value;
8b3c3104
AH		 299 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
300 if (err)
301 return 1;
302
18863bdd
AK		 303 if (!smsr->registered) {
304 smsr->urn.on_user_return = kvm_on_user_return;
305 user_return_notifier_register(&smsr->urn);
306 smsr->registered = true;
307 }
8b3c3104 308 return 0;
18863bdd
AK		 309}
310EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
311
13a34e06 312static void drop_user_return_notifiers(void)
3548bab5 313{
013f6a5d
MT		 314 unsigned int cpu = smp_processor_id();
315 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 316
317 if (smsr->registered)
318 kvm_on_user_return(&smsr->urn);
319}
320
6866b83e
CO		 321u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
322{
8a5a87d9 323 return vcpu->arch.apic_base;
6866b83e
CO		 324}
325EXPORT_SYMBOL_GPL(kvm_get_apic_base);
326
58871649
JM		 327enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
328{
329 return kvm_apic_mode(kvm_get_apic_base(vcpu));
330}
331EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
332
58cb628d
JK		 333int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
334{
58871649
JM		 335 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
336 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 337 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
338 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 339
58871649 340 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 341 return 1;
58871649
JM		 342 if (!msr_info->host_initiated) {
343 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
344 return 1;
345 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
346 return 1;
347 }
58cb628d
JK		 348
349 kvm_lapic_set_base(vcpu, msr_info->data);
350 return 0;
6866b83e
CO		 351}
352EXPORT_SYMBOL_GPL(kvm_set_apic_base);
353
2605fc21 354asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 355{
356 /* Fault while not rebooting. We want the trace. */
357 BUG();
358}
359EXPORT_SYMBOL_GPL(kvm_spurious_fault);
360
3fd28fce
ED		 361#define EXCPT_BENIGN 0
362#define EXCPT_CONTRIBUTORY 1
363#define EXCPT_PF 2
364
365static int exception_class(int vector)
366{
367 switch (vector) {
368 case PF_VECTOR:
369 return EXCPT_PF;
370 case DE_VECTOR:
371 case TS_VECTOR:
372 case NP_VECTOR:
373 case SS_VECTOR:
374 case GP_VECTOR:
375 return EXCPT_CONTRIBUTORY;
376 default:
377 break;
378 }
379 return EXCPT_BENIGN;
380}
381
d6e8c854
NA		 382#define EXCPT_FAULT 0
383#define EXCPT_TRAP 1
384#define EXCPT_ABORT 2
385#define EXCPT_INTERRUPT 3
386
387static int exception_type(int vector)
388{
389 unsigned int mask;
390
391 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
392 return EXCPT_INTERRUPT;
393
394 mask = 1 << vector;
395
396 /* #DB is trap, as instruction watchpoints are handled elsewhere */
397 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
398 return EXCPT_TRAP;
399
400 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
401 return EXCPT_ABORT;
402
403 /* Reserved exceptions will result in fault */
404 return EXCPT_FAULT;
405}
406
da998b46
JM		 407void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
408{
409 unsigned nr = vcpu->arch.exception.nr;
410 bool has_payload = vcpu->arch.exception.has_payload;
411 unsigned long payload = vcpu->arch.exception.payload;
412
413 if (!has_payload)
414 return;
415
416 switch (nr) {
f10c729f
JM		 417 case DB_VECTOR:
418 /*
419 * "Certain debug exceptions may clear bit 0-3. The
420 * remaining contents of the DR6 register are never
421 * cleared by the processor".
422 */
423 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
424 /*
425 * DR6.RTM is set by all #DB exceptions that don't clear it.
426 */
427 vcpu->arch.dr6 |= DR6_RTM;
428 vcpu->arch.dr6 |= payload;
429 /*
430 * Bit 16 should be set in the payload whenever the #DB
431 * exception should clear DR6.RTM. This makes the payload
432 * compatible with the pending debug exceptions under VMX.
433 * Though not currently documented in the SDM, this also
434 * makes the payload compatible with the exit qualification
435 * for #DB exceptions under VMX.
436 */
437 vcpu->arch.dr6 ^= payload & DR6_RTM;
438 break;
da998b46
JM		 439 case PF_VECTOR:
440 vcpu->arch.cr2 = payload;
441 break;
442 }
443
444 vcpu->arch.exception.has_payload = false;
445 vcpu->arch.exception.payload = 0;
446}
447EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
448
3fd28fce 449static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 450 unsigned nr, bool has_error, u32 error_code,
91e86d22 451 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 452{
453 u32 prev_nr;
454 int class1, class2;
455
3842d135
AK		 456 kvm_make_request(KVM_REQ_EVENT, vcpu);
457
664f8e26 458 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 459 queue:
3ffb2468
NA		 460 if (has_error && !is_protmode(vcpu))
461 has_error = false;
664f8e26
WL		 462 if (reinject) {
463 /*
464 * On vmentry, vcpu->arch.exception.pending is only
465 * true if an event injection was blocked by
466 * nested_run_pending. In that case, however,
467 * vcpu_enter_guest requests an immediate exit,
468 * and the guest shouldn't proceed far enough to
469 * need reinjection.
470 */
471 WARN_ON_ONCE(vcpu->arch.exception.pending);
472 vcpu->arch.exception.injected = true;
91e86d22
JM		 473 if (WARN_ON_ONCE(has_payload)) {
474 /*
475 * A reinjected event has already
476 * delivered its payload.
477 */
478 has_payload = false;
479 payload = 0;
480 }
664f8e26
WL		 481 } else {
482 vcpu->arch.exception.pending = true;
483 vcpu->arch.exception.injected = false;
484 }
3fd28fce
ED		 485 vcpu->arch.exception.has_error_code = has_error;
486 vcpu->arch.exception.nr = nr;
487 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 488 vcpu->arch.exception.has_payload = has_payload;
489 vcpu->arch.exception.payload = payload;
da998b46
JM		 490 /*
491 * In guest mode, payload delivery should be deferred,
492 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 493 * CR2 is modified (or intercept #DB before DR6 is
494 * modified under nVMX). However, for ABI
495 * compatibility with KVM_GET_VCPU_EVENTS and
496 * KVM_SET_VCPU_EVENTS, we can't delay payload
497 * delivery unless userspace has enabled this
498 * functionality via the per-VM capability,
499 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 500 */
501 if (!vcpu->kvm->arch.exception_payload_enabled ||
502 !is_guest_mode(vcpu))
503 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 504 return;
505 }
506
507 /* to check exception */
508 prev_nr = vcpu->arch.exception.nr;
509 if (prev_nr == DF_VECTOR) {
510 /* triple fault -> shutdown */
a8eeb04a 511 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 512 return;
513 }
514 class1 = exception_class(prev_nr);
515 class2 = exception_class(nr);
516 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
517 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 518 /*
519 * Generate double fault per SDM Table 5-5. Set
520 * exception.pending = true so that the double fault
521 * can trigger a nested vmexit.
522 */
3fd28fce 523 vcpu->arch.exception.pending = true;
664f8e26 524 vcpu->arch.exception.injected = false;
3fd28fce
ED		 525 vcpu->arch.exception.has_error_code = true;
526 vcpu->arch.exception.nr = DF_VECTOR;
527 vcpu->arch.exception.error_code = 0;
c851436a
JM		 528 vcpu->arch.exception.has_payload = false;
529 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 530 } else
531 /* replace previous exception with a new one in a hope
532 that instruction re-execution will regenerate lost
533 exception */
534 goto queue;
535}
536
298101da
AK		 537void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
538{
91e86d22 539 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 540}
541EXPORT_SYMBOL_GPL(kvm_queue_exception);
542
ce7ddec4
JR		 543void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544{
91e86d22 545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 546}
547EXPORT_SYMBOL_GPL(kvm_requeue_exception);
548
f10c729f
JM		 549static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
550 unsigned long payload)
551{
552 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
553}
554
da998b46
JM		 555static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
556 u32 error_code, unsigned long payload)
557{
558 kvm_multiple_exception(vcpu, nr, true, error_code,
559 true, payload, false);
560}
561
6affcbed 562int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 563{
db8fcefa
AP		 564 if (err)
565 kvm_inject_gp(vcpu, 0);
566 else
6affcbed
KH		 567 return kvm_skip_emulated_instruction(vcpu);
568
569 return 1;
db8fcefa
AP		 570}
571EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 572
6389ee94 573void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 574{
575 ++vcpu->stat.pf_guest;
adfe20fb
WL		 576 vcpu->arch.exception.nested_apf =
577 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 578 if (vcpu->arch.exception.nested_apf) {
adfe20fb 579 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 580 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
581 } else {
582 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
583 fault->address);
584 }
c3c91fee 585}
27d6c865 586EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 587
ef54bcfe 588static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 589{
6389ee94
AK		 590 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
591 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 592 else
44dd3ffa 593 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 594
595 return fault->nested_page_fault;
d4f8cf66
JR		 596}
597
3419ffc8
SY		 598void kvm_inject_nmi(struct kvm_vcpu *vcpu)
599{
7460fb4a
AK		 600 atomic_inc(&vcpu->arch.nmi_queued);
601 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 602}
603EXPORT_SYMBOL_GPL(kvm_inject_nmi);
604
298101da
AK		 605void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
606{
91e86d22 607 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 608}
609EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
610
ce7ddec4
JR		 611void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612{
91e86d22 613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 614}
615EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
616
0a79b009
AK		 617/*
618 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
619 * a #GP and return false.
620 */
621bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 622{
0a79b009
AK		 623 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
624 return true;
625 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
626 return false;
298101da 627}
0a79b009 628EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 629
16f8a6f9
NA		 630bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
631{
632 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
633 return true;
634
635 kvm_queue_exception(vcpu, UD_VECTOR);
636 return false;
637}
638EXPORT_SYMBOL_GPL(kvm_require_dr);
639
ec92fe44
JR		 640/*
641 * This function will be used to read from the physical memory of the currently
54bf36aa 642 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 643 * can read from guest physical or from the guest's guest physical memory.
644 */
645int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
646 gfn_t ngfn, void *data, int offset, int len,
647 u32 access)
648{
54987b7a 649 struct x86_exception exception;
ec92fe44
JR		 650 gfn_t real_gfn;
651 gpa_t ngpa;
652
653 ngpa = gfn_to_gpa(ngfn);
54987b7a 654 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 655 if (real_gfn == UNMAPPED_GVA)
656 return -EFAULT;
657
658 real_gfn = gpa_to_gfn(real_gfn);
659
54bf36aa 660 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 661}
662EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
663
69b0049a 664static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 665 void *data, int offset, int len, u32 access)
666{
667 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
668 data, offset, len, access);
669}
670
a03490ed
CO		 671/*
672 * Load the pae pdptrs. Return true is they are all valid.
673 */
ff03a073 674int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 675{
676 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
677 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
678 int i;
679 int ret;
ff03a073 680 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 681
ff03a073
JR		 682 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
683 offset * sizeof(u64), sizeof(pdpte),
684 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 685 if (ret < 0) {
686 ret = 0;
687 goto out;
688 }
689 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 690 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 691 (pdpte[i] &
44dd3ffa 692 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 693 ret = 0;
694 goto out;
695 }
696 }
697 ret = 1;
698
ff03a073 699 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 700 __set_bit(VCPU_EXREG_PDPTR,
701 (unsigned long *)&vcpu->arch.regs_avail);
702 __set_bit(VCPU_EXREG_PDPTR,
703 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 704out:
a03490ed
CO		 705
706 return ret;
707}
cc4b6871 708EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 709
9ed38ffa 710bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 711{
ff03a073 712 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 713 bool changed = true;
3d06b8bf
JR		 714 int offset;
715 gfn_t gfn;
d835dfec
AK		 716 int r;
717
d35b34a9 718 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
d835dfec
AK		 719 return false;
720
6de4f3ad
AK		 721 if (!test_bit(VCPU_EXREG_PDPTR,
722 (unsigned long *)&vcpu->arch.regs_avail))
723 return true;
724
a512177e
PB		 725 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
726 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 727 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
728 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 729 if (r < 0)
730 goto out;
ff03a073 731 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 732out:
d835dfec
AK		 733
734 return changed;
735}
9ed38ffa 736EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 737
49a9b07e 738int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 739{
aad82703 740 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 741 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 742
f9a48e6a
AK		 743 cr0 |= X86_CR0_ET;
744
ab344828 745#ifdef CONFIG_X86_64
0f12244f
GN		 746 if (cr0 & 0xffffffff00000000UL)
747 return 1;
ab344828
GN		 748#endif
749
750 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 751
0f12244f
GN		 752 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
753 return 1;
a03490ed 754
0f12244f
GN		 755 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
756 return 1;
a03490ed
CO		 757
758 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
759#ifdef CONFIG_X86_64
f6801dff 760 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 761 int cs_db, cs_l;
762
0f12244f
GN		 763 if (!is_pae(vcpu))
764 return 1;
a03490ed 765 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 766 if (cs_l)
767 return 1;
a03490ed
CO		 768 } else
769#endif
ff03a073 770 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 771 kvm_read_cr3(vcpu)))
0f12244f 772 return 1;
a03490ed
CO		 773 }
774
ad756a16
MJ		 775 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
776 return 1;
777
a03490ed 778 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 779
d170c419 780 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 781 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 782 kvm_async_pf_hash_reset(vcpu);
783 }
e5f3f027 784
aad82703
SY		 785 if ((cr0 ^ old_cr0) & update_bits)
786 kvm_mmu_reset_context(vcpu);
b18d5431 787
879ae188
LE		 788 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
789 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
790 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 791 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
792
0f12244f
GN		 793 return 0;
794}
2d3ad1f4 795EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 796
2d3ad1f4 797void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 798{
49a9b07e 799 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 802
1811d979 803void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 804{
805 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
806 !vcpu->guest_xcr0_loaded) {
807 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 808 if (vcpu->arch.xcr0 != host_xcr0)
809 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 810 vcpu->guest_xcr0_loaded = 1;
811 }
812}
1811d979 813EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
42bdf991 814
1811d979 815void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 816{
817 if (vcpu->guest_xcr0_loaded) {
818 if (vcpu->arch.xcr0 != host_xcr0)
819 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
820 vcpu->guest_xcr0_loaded = 0;
821 }
822}
1811d979 823EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
42bdf991 824
69b0049a 825static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 826{
56c103ec
LJ		 827 u64 xcr0 = xcr;
828 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 829 u64 valid_bits;
2acf923e
DC		 830
831 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
832 if (index != XCR_XFEATURE_ENABLED_MASK)
833 return 1;
d91cab78 834 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 835 return 1;
d91cab78 836 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 837 return 1;
46c34cb0
PB		 838
839 /*
840 * Do not allow the guest to set bits that we do not support
841 * saving. However, xcr0 bit 0 is always set, even if the
842 * emulated CPU does not support XSAVE (see fx_init).
843 */
d91cab78 844 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 845 if (xcr0 & ~valid_bits)
2acf923e 846 return 1;
46c34cb0 847
d91cab78
DH		 848 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
849 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 850 return 1;
851
d91cab78
DH		 852 if (xcr0 & XFEATURE_MASK_AVX512) {
853 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 854 return 1;
d91cab78 855 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 856 return 1;
857 }
2acf923e 858 vcpu->arch.xcr0 = xcr0;
56c103ec 859
d91cab78 860 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 861 kvm_update_cpuid(vcpu);
2acf923e
DC		 862 return 0;
863}
864
865int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
866{
764bcbc5
Z		 867 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
868 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 869 kvm_inject_gp(vcpu, 0);
870 return 1;
871 }
872 return 0;
873}
874EXPORT_SYMBOL_GPL(kvm_set_xcr);
875
a83b29c6 876int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 877{
fc78f519 878 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 879 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 880 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 881
0f12244f
GN		 882 if (cr4 & CR4_RESERVED_BITS)
883 return 1;
a03490ed 884
d6321d49 885 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 886 return 1;
887
d6321d49 888 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 889 return 1;
890
d6321d49 891 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 892 return 1;
893
d6321d49 894 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 895 return 1;
896
d6321d49 897 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 898 return 1;
899
fd8cb433 900 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 901 return 1;
902
ae3e61e1
PB		 903 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
904 return 1;
905
a03490ed 906 if (is_long_mode(vcpu)) {
0f12244f
GN		 907 if (!(cr4 & X86_CR4_PAE))
908 return 1;
a2edf57f
AK		 909 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
910 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 911 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
912 kvm_read_cr3(vcpu)))
0f12244f
GN		 913 return 1;
914
ad756a16 915 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 916 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 917 return 1;
918
919 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
920 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
921 return 1;
922 }
923
5e1746d6 924 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 925 return 1;
a03490ed 926
ad756a16
MJ		 927 if (((cr4 ^ old_cr4) & pdptr_bits) ||
928 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 929 kvm_mmu_reset_context(vcpu);
0f12244f 930
b9baba86 931 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 932 kvm_update_cpuid(vcpu);
2acf923e 933
0f12244f
GN		 934 return 0;
935}
2d3ad1f4 936EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 937
2390218b 938int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 939{
ade61e28 940 bool skip_tlb_flush = false;
ac146235 941#ifdef CONFIG_X86_64
c19986fe
JS		 942 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
943
ade61e28 944 if (pcid_enabled) {
208320ba
JS		 945 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
946 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 947 }
ac146235 948#endif
9d88fca7 949
9f8fe504 950 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 951 if (!skip_tlb_flush) {
952 kvm_mmu_sync_roots(vcpu);
ade61e28 953 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 954 }
0f12244f 955 return 0;
d835dfec
AK		 956 }
957
d1cd3ce9 958 if (is_long_mode(vcpu) &&
a780a3ea 959 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 960 return 1;
961 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 962 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 963 return 1;
a03490ed 964
ade61e28 965 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 966 vcpu->arch.cr3 = cr3;
aff48baa 967 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 968
0f12244f
GN		 969 return 0;
970}
2d3ad1f4 971EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 972
eea1cff9 973int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 974{
0f12244f
GN		 975 if (cr8 & CR8_RESERVED_BITS)
976 return 1;
35754c98 977 if (lapic_in_kernel(vcpu))
a03490ed
CO		 978 kvm_lapic_set_tpr(vcpu, cr8);
979 else
ad312c7c 980 vcpu->arch.cr8 = cr8;
0f12244f
GN		 981 return 0;
982}
2d3ad1f4 983EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 984
2d3ad1f4 985unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 986{
35754c98 987 if (lapic_in_kernel(vcpu))
a03490ed
CO		 988 return kvm_lapic_get_cr8(vcpu);
989 else
ad312c7c 990 return vcpu->arch.cr8;
a03490ed 991}
2d3ad1f4 992EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 993
ae561ede
NA		 994static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
995{
996 int i;
997
998 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
999 for (i = 0; i < KVM_NR_DB_REGS; i++)
1000 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1001 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1002 }
1003}
1004
73aaf249
JK		 1005static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1006{
1007 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1008 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1009}
1010
c8639010
JK		 1011static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1012{
1013 unsigned long dr7;
1014
1015 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1016 dr7 = vcpu->arch.guest_debug_dr7;
1017 else
1018 dr7 = vcpu->arch.dr7;
1019 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1020 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1021 if (dr7 & DR7_BP_EN_MASK)
1022 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1023}
1024
6f43ed01
NA		 1025static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1026{
1027 u64 fixed = DR6_FIXED_1;
1028
d6321d49 1029 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1030 fixed |= DR6_RTM;
1031 return fixed;
1032}
1033
338dbc97 1034static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1035{
1036 switch (dr) {
1037 case 0 ... 3:
1038 vcpu->arch.db[dr] = val;
1039 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1040 vcpu->arch.eff_db[dr] = val;
1041 break;
1042 case 4:
020df079
GN		 1043 /* fall through */
1044 case 6:
338dbc97
GN		 1045 if (val & 0xffffffff00000000ULL)
1046 return -1; /* #GP */
6f43ed01 1047 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1048 kvm_update_dr6(vcpu);
020df079
GN		 1049 break;
1050 case 5:
020df079
GN		 1051 /* fall through */
1052 default: /* 7 */
338dbc97
GN		 1053 if (val & 0xffffffff00000000ULL)
1054 return -1; /* #GP */
020df079 1055 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1056 kvm_update_dr7(vcpu);
020df079
GN		 1057 break;
1058 }
1059
1060 return 0;
1061}
338dbc97
GN		 1062
1063int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1064{
16f8a6f9 1065 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1066 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1067 return 1;
1068 }
1069 return 0;
338dbc97 1070}
020df079
GN		 1071EXPORT_SYMBOL_GPL(kvm_set_dr);
1072
16f8a6f9 1073int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1074{
1075 switch (dr) {
1076 case 0 ... 3:
1077 *val = vcpu->arch.db[dr];
1078 break;
1079 case 4:
020df079
GN		 1080 /* fall through */
1081 case 6:
73aaf249
JK		 1082 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1083 *val = vcpu->arch.dr6;
1084 else
1085 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1086 break;
1087 case 5:
020df079
GN		 1088 /* fall through */
1089 default: /* 7 */
1090 *val = vcpu->arch.dr7;
1091 break;
1092 }
338dbc97
GN		 1093 return 0;
1094}
020df079
GN		 1095EXPORT_SYMBOL_GPL(kvm_get_dr);
1096
022cd0e8
AK		 1097bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1098{
1099 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1100 u64 data;
1101 int err;
1102
c6702c9d 1103 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1104 if (err)
1105 return err;
1106 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1107 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1108 return err;
1109}
1110EXPORT_SYMBOL_GPL(kvm_rdpmc);
1111
043405e1
CO		 1112/*
1113 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1114 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1115 *
1116 * This list is modified at module load time to reflect the
e3267cbb 1117 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1118 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1119 * may depend on host virtualization features rather than host cpu features.
043405e1 1120 */
e3267cbb 1121
043405e1
CO		 1122static u32 msrs_to_save[] = {
1123 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1124 MSR_STAR,
043405e1
CO		 1125#ifdef CONFIG_X86_64
1126 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1127#endif
b3897a49 1128 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1129 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1130 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1131 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1132 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1133 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1134 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1135 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1136 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
043405e1
CO		 1137};
1138
1139static unsigned num_msrs_to_save;
1140
62ef68bb
PB		 1141static u32 emulated_msrs[] = {
1142 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1143 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1144 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1145 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1146 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1147 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1148 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1149 HV_X64_MSR_RESET,
11c4b1ca 1150 HV_X64_MSR_VP_INDEX,
9eec50b8 1151 HV_X64_MSR_VP_RUNTIME,
5c919412 1152 HV_X64_MSR_SCONTROL,
1f4b34f8 1153 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1154 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1155 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1156 HV_X64_MSR_TSC_EMULATION_STATUS,
1157
1158 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1159 MSR_KVM_PV_EOI_EN,
1160
ba904635 1161 MSR_IA32_TSC_ADJUST,
a3e06bbe 1162 MSR_IA32_TSCDEADLINE,
2bdb76c0 1163 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1164 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1165 MSR_IA32_MCG_STATUS,
1166 MSR_IA32_MCG_CTL,
c45dcc71 1167 MSR_IA32_MCG_EXT_CTL,
64d60670 1168 MSR_IA32_SMBASE,
52797bf9 1169 MSR_SMI_COUNT,
db2336a8
KH		 1170 MSR_PLATFORM_INFO,
1171 MSR_MISC_FEATURES_ENABLES,
bc226f07 1172 MSR_AMD64_VIRT_SPEC_CTRL,
6c6a2ab9 1173 MSR_IA32_POWER_CTL,
191c8137
BP		 1174
1175 MSR_K7_HWCR,
043405e1
CO		 1176};
1177
62ef68bb
PB		 1178static unsigned num_emulated_msrs;
1179
801e459a
TL		 1180/*
1181 * List of msr numbers which are used to expose MSR-based features that
1182 * can be used by a hypervisor to validate requested CPU features.
1183 */
1184static u32 msr_based_features[] = {
1389309c
PB		 1185 MSR_IA32_VMX_BASIC,
1186 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1187 MSR_IA32_VMX_PINBASED_CTLS,
1188 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1189 MSR_IA32_VMX_PROCBASED_CTLS,
1190 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1191 MSR_IA32_VMX_EXIT_CTLS,
1192 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1193 MSR_IA32_VMX_ENTRY_CTLS,
1194 MSR_IA32_VMX_MISC,
1195 MSR_IA32_VMX_CR0_FIXED0,
1196 MSR_IA32_VMX_CR0_FIXED1,
1197 MSR_IA32_VMX_CR4_FIXED0,
1198 MSR_IA32_VMX_CR4_FIXED1,
1199 MSR_IA32_VMX_VMCS_ENUM,
1200 MSR_IA32_VMX_PROCBASED_CTLS2,
1201 MSR_IA32_VMX_EPT_VPID_CAP,
1202 MSR_IA32_VMX_VMFUNC,
1203
d1d93fa9 1204 MSR_F10H_DECFG,
518e7b94 1205 MSR_IA32_UCODE_REV,
cd283252 1206 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1207};
1208
1209static unsigned int num_msr_based_features;
1210
5b76a3cf
PB		 1211u64 kvm_get_arch_capabilities(void)
1212{
1213 u64 data;
1214
1215 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1216
1217 /*
1218 * If we're doing cache flushes (either "always" or "cond")
1219 * we will do one whenever the guest does a vmlaunch/vmresume.
1220 * If an outer hypervisor is doing the cache flush for us
1221 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1222 * capability to the guest too, and if EPT is disabled we're not
1223 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1224 * require a nested hypervisor to do a flush of its own.
1225 */
1226 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1227 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1228
1229 return data;
1230}
1231EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1232
66421c1e
WL		 1233static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1234{
1235 switch (msr->index) {
cd283252 1236 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1237 msr->data = kvm_get_arch_capabilities();
1238 break;
1239 case MSR_IA32_UCODE_REV:
cd283252 1240 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1241 break;
66421c1e
WL		 1242 default:
1243 if (kvm_x86_ops->get_msr_feature(msr))
1244 return 1;
1245 }
1246 return 0;
1247}
1248
801e459a
TL		 1249static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1250{
1251 struct kvm_msr_entry msr;
66421c1e 1252 int r;
801e459a
TL		 1253
1254 msr.index = index;
66421c1e
WL		 1255 r = kvm_get_msr_feature(&msr);
1256 if (r)
1257 return r;
801e459a
TL		 1258
1259 *data = msr.data;
1260
1261 return 0;
1262}
1263
11988499 1264static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1265{
1b4d56b8 1266 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
11988499 1267 return false;
1b2fd70c 1268
1b4d56b8 1269 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
11988499 1270 return false;
d8017474 1271
0a629563
SC		 1272 if (efer & (EFER_LME | EFER_LMA) &&
1273 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1274 return false;
1275
1276 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1277 return false;
1278
384bb783 1279 return true;
11988499
SC		 1280
1281}
1282bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1283{
1284 if (efer & efer_reserved_bits)
1285 return false;
1286
1287 return __kvm_valid_efer(vcpu, efer);
384bb783
JK		 1288}
1289EXPORT_SYMBOL_GPL(kvm_valid_efer);
1290
11988499 1291static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
384bb783
JK		 1292{
1293 u64 old_efer = vcpu->arch.efer;
11988499 1294 u64 efer = msr_info->data;
384bb783 1295
11988499
SC		 1296 if (efer & efer_reserved_bits)
1297 return false;
384bb783 1298
11988499
SC		 1299 if (!msr_info->host_initiated) {
1300 if (!__kvm_valid_efer(vcpu, efer))
1301 return 1;
1302
1303 if (is_paging(vcpu) &&
1304 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1305 return 1;
1306 }
384bb783 1307
15c4a640 1308 efer &= ~EFER_LMA;
f6801dff 1309 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1310
a3d204e2
SY		 1311 kvm_x86_ops->set_efer(vcpu, efer);
1312
aad82703
SY		 1313 /* Update reserved bits */
1314 if ((efer ^ old_efer) & EFER_NX)
1315 kvm_mmu_reset_context(vcpu);
1316
b69e8cae 1317 return 0;
15c4a640
CO		 1318}
1319
f2b4b7dd
JR		 1320void kvm_enable_efer_bits(u64 mask)
1321{
1322 efer_reserved_bits &= ~mask;
1323}
1324EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1325
15c4a640
CO		 1326/*
1327 * Writes msr value into into the appropriate "register".
1328 * Returns 0 on success, non-0 otherwise.
1329 * Assumes vcpu_load() was already called.
1330 */
8fe8ab46 1331int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1332{
854e8bb1
NA		 1333 switch (msr->index) {
1334 case MSR_FS_BASE:
1335 case MSR_GS_BASE:
1336 case MSR_KERNEL_GS_BASE:
1337 case MSR_CSTAR:
1338 case MSR_LSTAR:
fd8cb433 1339 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1340 return 1;
1341 break;
1342 case MSR_IA32_SYSENTER_EIP:
1343 case MSR_IA32_SYSENTER_ESP:
1344 /*
1345 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1346 * non-canonical address is written on Intel but not on
1347 * AMD (which ignores the top 32-bits, because it does
1348 * not implement 64-bit SYSENTER).
1349 *
1350 * 64-bit code should hence be able to write a non-canonical
1351 * value on AMD. Making the address canonical ensures that
1352 * vmentry does not fail on Intel after writing a non-canonical
1353 * value, and that something deterministic happens if the guest
1354 * invokes 64-bit SYSENTER.
1355 */
fd8cb433 1356 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1357 }
8fe8ab46 1358 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1359}
854e8bb1 1360EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1361
313a3dc7
CO		 1362/*
1363 * Adapt set_msr() to msr_io()'s calling convention
1364 */
609e36d3
PB		 1365static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1366{
1367 struct msr_data msr;
1368 int r;
1369
1370 msr.index = index;
1371 msr.host_initiated = true;
1372 r = kvm_get_msr(vcpu, &msr);
1373 if (r)
1374 return r;
1375
1376 *data = msr.data;
1377 return 0;
1378}
1379
313a3dc7
CO		 1380static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1381{
8fe8ab46
WA		 1382 struct msr_data msr;
1383
1384 msr.data = *data;
1385 msr.index = index;
1386 msr.host_initiated = true;
1387 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1388}
1389
16e8d74d
MT		 1390#ifdef CONFIG_X86_64
1391struct pvclock_gtod_data {
1392 seqcount_t seq;
1393
1394 struct { /* extract of a clocksource struct */
1395 int vclock_mode;
a5a1d1c2
TG		 1396 u64 cycle_last;
1397 u64 mask;
16e8d74d
MT		 1398 u32 mult;
1399 u32 shift;
1400 } clock;
1401
cbcf2dd3
TG		 1402 u64 boot_ns;
1403 u64 nsec_base;
55dd00a7 1404 u64 wall_time_sec;
16e8d74d
MT		 1405};
1406
1407static struct pvclock_gtod_data pvclock_gtod_data;
1408
1409static void update_pvclock_gtod(struct timekeeper *tk)
1410{
1411 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1412 u64 boot_ns;
1413
876e7881 1414 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1415
1416 write_seqcount_begin(&vdata->seq);
1417
1418 /* copy pvclock gtod data */
876e7881
PZ		 1419 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1420 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1421 vdata->clock.mask = tk->tkr_mono.mask;
1422 vdata->clock.mult = tk->tkr_mono.mult;
1423 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1424
cbcf2dd3 1425 vdata->boot_ns = boot_ns;
876e7881 1426 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1427
55dd00a7
MT		 1428 vdata->wall_time_sec = tk->xtime_sec;
1429
16e8d74d
MT		 1430 write_seqcount_end(&vdata->seq);
1431}
1432#endif
1433
bab5bb39
NK		 1434void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1435{
1436 /*
1437 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1438 * vcpu_enter_guest. This function is only called from
1439 * the physical CPU that is running vcpu.
1440 */
1441 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1442}
16e8d74d 1443
18068523
GOC		 1444static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1445{
9ed3c444
AK		 1446 int version;
1447 int r;
50d0a0f9 1448 struct pvclock_wall_clock wc;
87aeb54f 1449 struct timespec64 boot;
18068523
GOC		 1450
1451 if (!wall_clock)
1452 return;
1453
9ed3c444
AK		 1454 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1455 if (r)
1456 return;
1457
1458 if (version & 1)
1459 ++version; /* first time write, random junk */
1460
1461 ++version;
18068523 1462
1dab1345
NK		 1463 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1464 return;
18068523 1465
50d0a0f9
GH		 1466 /*
1467 * The guest calculates current wall clock time by adding
34c238a1 1468 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1469 * wall clock specified here. guest system time equals host
1470 * system time for us, thus we must fill in host boot time here.
1471 */
87aeb54f 1472 getboottime64(&boot);
50d0a0f9 1473
4b648665 1474 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1475 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1476 boot = timespec64_sub(boot, ts);
4b648665 1477 }
87aeb54f 1478 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1479 wc.nsec = boot.tv_nsec;
1480 wc.version = version;
18068523
GOC		 1481
1482 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1483
1484 version++;
1485 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1486}
1487
50d0a0f9
GH		 1488static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1489{
b51012de
PB		 1490 do_shl32_div32(dividend, divisor);
1491 return dividend;
50d0a0f9
GH		 1492}
1493
3ae13faa 1494static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1495 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1496{
5f4e3f88 1497 uint64_t scaled64;
50d0a0f9
GH		 1498 int32_t shift = 0;
1499 uint64_t tps64;
1500 uint32_t tps32;
1501
3ae13faa
PB		 1502 tps64 = base_hz;
1503 scaled64 = scaled_hz;
50933623 1504 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1505 tps64 >>= 1;
1506 shift--;
1507 }
1508
1509 tps32 = (uint32_t)tps64;
50933623
JK		 1510 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1511 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1512 scaled64 >>= 1;
1513 else
1514 tps32 <<= 1;
50d0a0f9
GH		 1515 shift++;
1516 }
1517
5f4e3f88
ZA		 1518 *pshift = shift;
1519 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1520
3ae13faa
PB		 1521 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1522 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1523}
1524
d828199e 1525#ifdef CONFIG_X86_64
16e8d74d 1526static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1527#endif
16e8d74d 1528
c8076604 1529static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1530static unsigned long max_tsc_khz;
c8076604 1531
cc578287 1532static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1533{
cc578287
ZA		 1534 u64 v = (u64)khz * (1000000 + ppm);
1535 do_div(v, 1000000);
1536 return v;
1e993611
JR		 1537}
1538
381d585c
HZ		 1539static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1540{
1541 u64 ratio;
1542
1543 /* Guest TSC same frequency as host TSC? */
1544 if (!scale) {
1545 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1546 return 0;
1547 }
1548
1549 /* TSC scaling supported? */
1550 if (!kvm_has_tsc_control) {
1551 if (user_tsc_khz > tsc_khz) {
1552 vcpu->arch.tsc_catchup = 1;
1553 vcpu->arch.tsc_always_catchup = 1;
1554 return 0;
1555 } else {
1556 WARN(1, "user requested TSC rate below hardware speed\n");
1557 return -1;
1558 }
1559 }
1560
1561 /* TSC scaling required - calculate ratio */
1562 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1563 user_tsc_khz, tsc_khz);
1564
1565 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1566 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1567 user_tsc_khz);
1568 return -1;
1569 }
1570
1571 vcpu->arch.tsc_scaling_ratio = ratio;
1572 return 0;
1573}
1574
4941b8cb 1575static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1576{
cc578287
ZA		 1577 u32 thresh_lo, thresh_hi;
1578 int use_scaling = 0;
217fc9cf 1579
03ba32ca 1580 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1581 if (user_tsc_khz == 0) {
ad721883
HZ		 1582 /* set tsc_scaling_ratio to a safe value */
1583 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1584 return -1;
ad721883 1585 }
03ba32ca 1586
c285545f 1587 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1588 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1589 &vcpu->arch.virtual_tsc_shift,
1590 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1591 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1592
1593 /*
1594 * Compute the variation in TSC rate which is acceptable
1595 * within the range of tolerance and decide if the
1596 * rate being applied is within that bounds of the hardware
1597 * rate. If so, no scaling or compensation need be done.
1598 */
1599 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1600 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1601 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1602 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1603 use_scaling = 1;
1604 }
4941b8cb 1605 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1606}
1607
1608static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1609{
e26101b1 1610 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1611 vcpu->arch.virtual_tsc_mult,
1612 vcpu->arch.virtual_tsc_shift);
e26101b1 1613 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1614 return tsc;
1615}
1616
b0c39dc6
VK		 1617static inline int gtod_is_based_on_tsc(int mode)
1618{
1619 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1620}
1621
69b0049a 1622static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1623{
1624#ifdef CONFIG_X86_64
1625 bool vcpus_matched;
b48aa97e
MT		 1626 struct kvm_arch *ka = &vcpu->kvm->arch;
1627 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1628
1629 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1630 atomic_read(&vcpu->kvm->online_vcpus));
1631
7f187922
MT		 1632 /*
1633 * Once the masterclock is enabled, always perform request in
1634 * order to update it.
1635 *
1636 * In order to enable masterclock, the host clocksource must be TSC
1637 * and the vcpus need to have matched TSCs. When that happens,
1638 * perform request to enable masterclock.
1639 */
1640 if (ka->use_master_clock ||
b0c39dc6 1641 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1642 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1643
1644 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1645 atomic_read(&vcpu->kvm->online_vcpus),
1646 ka->use_master_clock, gtod->clock.vclock_mode);
1647#endif
1648}
1649
ba904635
WA		 1650static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1651{
e79f245d 1652 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1653 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1654}
1655
35181e86
HZ		 1656/*
1657 * Multiply tsc by a fixed point number represented by ratio.
1658 *
1659 * The most significant 64-N bits (mult) of ratio represent the
1660 * integral part of the fixed point number; the remaining N bits
1661 * (frac) represent the fractional part, ie. ratio represents a fixed
1662 * point number (mult + frac * 2^(-N)).
1663 *
1664 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1665 */
1666static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1667{
1668 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1669}
1670
1671u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1672{
1673 u64 _tsc = tsc;
1674 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1675
1676 if (ratio != kvm_default_tsc_scaling_ratio)
1677 _tsc = __scale_tsc(ratio, tsc);
1678
1679 return _tsc;
1680}
1681EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1682
07c1419a
HZ		 1683static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1684{
1685 u64 tsc;
1686
1687 tsc = kvm_scale_tsc(vcpu, rdtsc());
1688
1689 return target_tsc - tsc;
1690}
1691
4ba76538
HZ		 1692u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1693{
e79f245d
KA		 1694 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1695
1696 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1697}
1698EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1699
a545ab6a
LC		 1700static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1701{
326e7425 1702 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1703}
1704
b0c39dc6
VK		 1705static inline bool kvm_check_tsc_unstable(void)
1706{
1707#ifdef CONFIG_X86_64
1708 /*
1709 * TSC is marked unstable when we're running on Hyper-V,
1710 * 'TSC page' clocksource is good.
1711 */
1712 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1713 return false;
1714#endif
1715 return check_tsc_unstable();
1716}
1717
8fe8ab46 1718void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1719{
1720 struct kvm *kvm = vcpu->kvm;
f38e098f 1721 u64 offset, ns, elapsed;
99e3e30a 1722 unsigned long flags;
b48aa97e 1723 bool matched;
0d3da0d2 1724 bool already_matched;
8fe8ab46 1725 u64 data = msr->data;
c5e8ec8e 1726 bool synchronizing = false;
99e3e30a 1727
038f8c11 1728 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1729 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1730 ns = ktime_get_boot_ns();
f38e098f 1731 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1732
03ba32ca 1733 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1734 if (data == 0 && msr->host_initiated) {
1735 /*
1736 * detection of vcpu initialization -- need to sync
1737 * with other vCPUs. This particularly helps to keep
1738 * kvm_clock stable after CPU hotplug
1739 */
1740 synchronizing = true;
1741 } else {
1742 u64 tsc_exp = kvm->arch.last_tsc_write +
1743 nsec_to_cycles(vcpu, elapsed);
1744 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1745 /*
1746 * Special case: TSC write with a small delta (1 second)
1747 * of virtual cycle time against real time is
1748 * interpreted as an attempt to synchronize the CPU.
1749 */
1750 synchronizing = data < tsc_exp + tsc_hz &&
1751 data + tsc_hz > tsc_exp;
1752 }
c5e8ec8e 1753 }
f38e098f
ZA		 1754
1755 /*
5d3cb0f6
ZA		 1756 * For a reliable TSC, we can match TSC offsets, and for an unstable
1757 * TSC, we add elapsed time in this computation. We could let the
1758 * compensation code attempt to catch up if we fall behind, but
1759 * it's better to try to match offsets from the beginning.
1760 */
c5e8ec8e 1761 if (synchronizing &&
5d3cb0f6 1762 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1763 if (!kvm_check_tsc_unstable()) {
e26101b1 1764 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1765 pr_debug("kvm: matched tsc offset for %llu\n", data);
1766 } else {
857e4099 1767 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1768 data += delta;
07c1419a 1769 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1770 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1771 }
b48aa97e 1772 matched = true;
0d3da0d2 1773 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1774 } else {
1775 /*
1776 * We split periods of matched TSC writes into generations.
1777 * For each generation, we track the original measured
1778 * nanosecond time, offset, and write, so if TSCs are in
1779 * sync, we can match exact offset, and if not, we can match
4a969980 1780 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1781 *
1782 * These values are tracked in kvm->arch.cur_xxx variables.
1783 */
1784 kvm->arch.cur_tsc_generation++;
1785 kvm->arch.cur_tsc_nsec = ns;
1786 kvm->arch.cur_tsc_write = data;
1787 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1788 matched = false;
0d3da0d2 1789 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1790 kvm->arch.cur_tsc_generation, data);
f38e098f 1791 }
e26101b1
ZA		 1792
1793 /*
1794 * We also track th most recent recorded KHZ, write and time to
1795 * allow the matching interval to be extended at each write.
1796 */
f38e098f
ZA		 1797 kvm->arch.last_tsc_nsec = ns;
1798 kvm->arch.last_tsc_write = data;
5d3cb0f6 1799 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1800
b183aa58 1801 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1802
1803 /* Keep track of which generation this VCPU has synchronized to */
1804 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1805 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1806 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1807
d6321d49 1808 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1809 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1810
a545ab6a 1811 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1812 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1813
1814 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1815 if (!matched) {
b48aa97e 1816 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1817 } else if (!already_matched) {
1818 kvm->arch.nr_vcpus_matched_tsc++;
1819 }
b48aa97e
MT		 1820
1821 kvm_track_tsc_matching(vcpu);
1822 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1823}
e26101b1 1824
99e3e30a
ZA		 1825EXPORT_SYMBOL_GPL(kvm_write_tsc);
1826
58ea6767
HZ		 1827static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1828 s64 adjustment)
1829{
326e7425
LS		 1830 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1831 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1832}
1833
1834static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1835{
1836 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1837 WARN_ON(adjustment < 0);
1838 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1839 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1840}
1841
d828199e
MT		 1842#ifdef CONFIG_X86_64
1843
a5a1d1c2 1844static u64 read_tsc(void)
d828199e 1845{
a5a1d1c2 1846 u64 ret = (u64)rdtsc_ordered();
03b9730b 1847 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1848
1849 if (likely(ret >= last))
1850 return ret;
1851
1852 /*
1853 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1854 * predictable (it's just a function of time and the likely is
d828199e
MT		 1855 * very likely) and there's a data dependence, so force GCC
1856 * to generate a branch instead. I don't barrier() because
1857 * we don't actually need a barrier, and if this function
1858 * ever gets inlined it will generate worse code.
1859 */
1860 asm volatile ("");
1861 return last;
1862}
1863
b0c39dc6 1864static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1865{
1866 long v;
1867 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1868 u64 tsc_pg_val;
1869
1870 switch (gtod->clock.vclock_mode) {
1871 case VCLOCK_HVCLOCK:
1872 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1873 tsc_timestamp);
1874 if (tsc_pg_val != U64_MAX) {
1875 /* TSC page valid */
1876 *mode = VCLOCK_HVCLOCK;
1877 v = (tsc_pg_val - gtod->clock.cycle_last) &
1878 gtod->clock.mask;
1879 } else {
1880 /* TSC page invalid */
1881 *mode = VCLOCK_NONE;
1882 }
1883 break;
1884 case VCLOCK_TSC:
1885 *mode = VCLOCK_TSC;
1886 *tsc_timestamp = read_tsc();
1887 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1888 gtod->clock.mask;
1889 break;
1890 default:
1891 *mode = VCLOCK_NONE;
1892 }
d828199e 1893
b0c39dc6
VK		 1894 if (*mode == VCLOCK_NONE)
1895 *tsc_timestamp = v = 0;
d828199e 1896
d828199e
MT		 1897 return v * gtod->clock.mult;
1898}
1899
b0c39dc6 1900static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1901{
cbcf2dd3 1902 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1903 unsigned long seq;
d828199e 1904 int mode;
cbcf2dd3 1905 u64 ns;
d828199e 1906
d828199e
MT		 1907 do {
1908 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1909 ns = gtod->nsec_base;
b0c39dc6 1910 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1911 ns >>= gtod->clock.shift;
cbcf2dd3 1912 ns += gtod->boot_ns;
d828199e 1913 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1914 *t = ns;
d828199e
MT		 1915
1916 return mode;
1917}
1918
899a31f5 1919static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1920{
1921 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1922 unsigned long seq;
1923 int mode;
1924 u64 ns;
1925
1926 do {
1927 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1928 ts->tv_sec = gtod->wall_time_sec;
1929 ns = gtod->nsec_base;
b0c39dc6 1930 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1931 ns >>= gtod->clock.shift;
1932 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1933
1934 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1935 ts->tv_nsec = ns;
1936
1937 return mode;
1938}
1939
b0c39dc6
VK		 1940/* returns true if host is using TSC based clocksource */
1941static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1942{
d828199e 1943 /* checked again under seqlock below */
b0c39dc6 1944 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1945 return false;
1946
b0c39dc6
VK		 1947 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1948 tsc_timestamp));
d828199e 1949}
55dd00a7 1950
b0c39dc6 1951/* returns true if host is using TSC based clocksource */
899a31f5 1952static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1953 u64 *tsc_timestamp)
55dd00a7
MT		 1954{
1955 /* checked again under seqlock below */
b0c39dc6 1956 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1957 return false;
1958
b0c39dc6 1959 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1960}
d828199e
MT		 1961#endif
1962
1963/*
1964 *
b48aa97e
MT		 1965 * Assuming a stable TSC across physical CPUS, and a stable TSC
1966 * across virtual CPUs, the following condition is possible.
1967 * Each numbered line represents an event visible to both
d828199e
MT		 1968 * CPUs at the next numbered event.
1969 *
1970 * "timespecX" represents host monotonic time. "tscX" represents
1971 * RDTSC value.
1972 *
1973 * VCPU0 on CPU0 | VCPU1 on CPU1
1974 *
1975 * 1. read timespec0,tsc0
1976 * 2. | timespec1 = timespec0 + N
1977 * | tsc1 = tsc0 + M
1978 * 3. transition to guest | transition to guest
1979 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1980 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1981 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1982 *
1983 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1984 *
1985 * - ret0 < ret1
1986 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1987 * ...
1988 * - 0 < N - M => M < N
1989 *
1990 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1991 * always the case (the difference between two distinct xtime instances
1992 * might be smaller then the difference between corresponding TSC reads,
1993 * when updating guest vcpus pvclock areas).
1994 *
1995 * To avoid that problem, do not allow visibility of distinct
1996 * system_timestamp/tsc_timestamp values simultaneously: use a master
1997 * copy of host monotonic time values. Update that master copy
1998 * in lockstep.
1999 *
b48aa97e 2000 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 2001 *
2002 */
2003
2004static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2005{
2006#ifdef CONFIG_X86_64
2007 struct kvm_arch *ka = &kvm->arch;
2008 int vclock_mode;
b48aa97e
MT		 2009 bool host_tsc_clocksource, vcpus_matched;
2010
2011 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2012 atomic_read(&kvm->online_vcpus));
d828199e
MT		 2013
2014 /*
2015 * If the host uses TSC clock, then passthrough TSC as stable
2016 * to the guest.
2017 */
b48aa97e 2018 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 2019 &ka->master_kernel_ns,
2020 &ka->master_cycle_now);
2021
16a96021 2022 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2023 && !ka->backwards_tsc_observed
54750f2c 2024 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2025
d828199e
MT		 2026 if (ka->use_master_clock)
2027 atomic_set(&kvm_guest_has_master_clock, 1);
2028
2029 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2030 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2031 vcpus_matched);
d828199e
MT		 2032#endif
2033}
2034
2860c4b1
PB		 2035void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2036{
2037 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2038}
2039
2e762ff7
MT		 2040static void kvm_gen_update_masterclock(struct kvm *kvm)
2041{
2042#ifdef CONFIG_X86_64
2043 int i;
2044 struct kvm_vcpu *vcpu;
2045 struct kvm_arch *ka = &kvm->arch;
2046
2047 spin_lock(&ka->pvclock_gtod_sync_lock);
2048 kvm_make_mclock_inprogress_request(kvm);
2049 /* no guest entries from this point */
2050 pvclock_update_vm_gtod_copy(kvm);
2051
2052 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2053 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2054
2055 /* guest entries allowed */
2056 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2057 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2058
2059 spin_unlock(&ka->pvclock_gtod_sync_lock);
2060#endif
2061}
2062
e891a32e 2063u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2064{
108b249c 2065 struct kvm_arch *ka = &kvm->arch;
8b953440 2066 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2067 u64 ret;
108b249c 2068
8b953440
PB		 2069 spin_lock(&ka->pvclock_gtod_sync_lock);
2070 if (!ka->use_master_clock) {
2071 spin_unlock(&ka->pvclock_gtod_sync_lock);
2072 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 2073 }
2074
8b953440
PB		 2075 hv_clock.tsc_timestamp = ka->master_cycle_now;
2076 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2077 spin_unlock(&ka->pvclock_gtod_sync_lock);
2078
e2c2206a
WL		 2079 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2080 get_cpu();
2081
e70b57a6
WL		 2082 if (__this_cpu_read(cpu_tsc_khz)) {
2083 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2084 &hv_clock.tsc_shift,
2085 &hv_clock.tsc_to_system_mul);
2086 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2087 } else
2088 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2089
2090 put_cpu();
2091
2092 return ret;
108b249c
PB		 2093}
2094
0d6dd2ff
PB		 2095static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2096{
2097 struct kvm_vcpu_arch *vcpu = &v->arch;
2098 struct pvclock_vcpu_time_info guest_hv_clock;
2099
4e335d9e 2100 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2101 &guest_hv_clock, sizeof(guest_hv_clock))))
2102 return;
2103
2104 /* This VCPU is paused, but it's legal for a guest to read another
2105 * VCPU's kvmclock, so we really have to follow the specification where
2106 * it says that version is odd if data is being modified, and even after
2107 * it is consistent.
2108 *
2109 * Version field updates must be kept separate. This is because
2110 * kvm_write_guest_cached might use a "rep movs" instruction, and
2111 * writes within a string instruction are weakly ordered. So there
2112 * are three writes overall.
2113 *
2114 * As a small optimization, only write the version field in the first
2115 * and third write. The vcpu->pv_time cache is still valid, because the
2116 * version field is the first in the struct.
2117 */
2118 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2119
51c4b8bb
LA		 2120 if (guest_hv_clock.version & 1)
2121 ++guest_hv_clock.version; /* first time write, random junk */
2122
0d6dd2ff 2123 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2124 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2125 &vcpu->hv_clock,
2126 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2127
2128 smp_wmb();
2129
2130 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2131 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2132
2133 if (vcpu->pvclock_set_guest_stopped_request) {
2134 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2135 vcpu->pvclock_set_guest_stopped_request = false;
2136 }
2137
2138 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2139
4e335d9e
PB		 2140 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2141 &vcpu->hv_clock,
2142 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2143
2144 smp_wmb();
2145
2146 vcpu->hv_clock.version++;
4e335d9e
PB		 2147 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2148 &vcpu->hv_clock,
2149 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2150}
2151
34c238a1 2152static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2153{
78db6a50 2154 unsigned long flags, tgt_tsc_khz;
18068523 2155 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2156 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2157 s64 kernel_ns;
d828199e 2158 u64 tsc_timestamp, host_tsc;
51d59c6b 2159 u8 pvclock_flags;
d828199e
MT		 2160 bool use_master_clock;
2161
2162 kernel_ns = 0;
2163 host_tsc = 0;
18068523 2164
d828199e
MT		 2165 /*
2166 * If the host uses TSC clock, then passthrough TSC as stable
2167 * to the guest.
2168 */
2169 spin_lock(&ka->pvclock_gtod_sync_lock);
2170 use_master_clock = ka->use_master_clock;
2171 if (use_master_clock) {
2172 host_tsc = ka->master_cycle_now;
2173 kernel_ns = ka->master_kernel_ns;
2174 }
2175 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2176
2177 /* Keep irq disabled to prevent changes to the clock */
2178 local_irq_save(flags);
78db6a50
PB		 2179 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2180 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2181 local_irq_restore(flags);
2182 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2183 return 1;
2184 }
d828199e 2185 if (!use_master_clock) {
4ea1636b 2186 host_tsc = rdtsc();
108b249c 2187 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2188 }
2189
4ba76538 2190 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2191
c285545f
ZA		 2192 /*
2193 * We may have to catch up the TSC to match elapsed wall clock
2194 * time for two reasons, even if kvmclock is used.
2195 * 1) CPU could have been running below the maximum TSC rate
2196 * 2) Broken TSC compensation resets the base at each VCPU
2197 * entry to avoid unknown leaps of TSC even when running
2198 * again on the same CPU. This may cause apparent elapsed
2199 * time to disappear, and the guest to stand still or run
2200 * very slowly.
2201 */
2202 if (vcpu->tsc_catchup) {
2203 u64 tsc = compute_guest_tsc(v, kernel_ns);
2204 if (tsc > tsc_timestamp) {
f1e2b260 2205 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2206 tsc_timestamp = tsc;
2207 }
50d0a0f9
GH		 2208 }
2209
18068523
GOC		 2210 local_irq_restore(flags);
2211
0d6dd2ff 2212 /* With all the info we got, fill in the values */
18068523 2213
78db6a50
PB		 2214 if (kvm_has_tsc_control)
2215 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2216
2217 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2218 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2219 &vcpu->hv_clock.tsc_shift,
2220 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2221 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2222 }
2223
1d5f066e 2224 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2225 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2226 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2227
d828199e 2228 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2229 pvclock_flags = 0;
d828199e
MT		 2230 if (use_master_clock)
2231 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2232
78c0337a
MT		 2233 vcpu->hv_clock.flags = pvclock_flags;
2234
095cf55d
PB		 2235 if (vcpu->pv_time_enabled)
2236 kvm_setup_pvclock_page(v);
2237 if (v == kvm_get_vcpu(v->kvm, 0))
2238 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2239 return 0;
c8076604
GH		 2240}
2241
0061d53d
MT		 2242/*
2243 * kvmclock updates which are isolated to a given vcpu, such as
2244 * vcpu->cpu migration, should not allow system_timestamp from
2245 * the rest of the vcpus to remain static. Otherwise ntp frequency
2246 * correction applies to one vcpu's system_timestamp but not
2247 * the others.
2248 *
2249 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2250 * We need to rate-limit these requests though, as they can
2251 * considerably slow guests that have a large number of vcpus.
2252 * The time for a remote vcpu to update its kvmclock is bound
2253 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2254 */
2255
7e44e449
AJ		 2256#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2257
2258static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2259{
2260 int i;
7e44e449
AJ		 2261 struct delayed_work *dwork = to_delayed_work(work);
2262 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2263 kvmclock_update_work);
2264 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2265 struct kvm_vcpu *vcpu;
2266
2267 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2268 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2269 kvm_vcpu_kick(vcpu);
2270 }
2271}
2272
7e44e449
AJ		 2273static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2274{
2275 struct kvm *kvm = v->kvm;
2276
105b21bb 2277 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2278 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2279 KVMCLOCK_UPDATE_DELAY);
2280}
2281
332967a3
AJ		 2282#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2283
2284static void kvmclock_sync_fn(struct work_struct *work)
2285{
2286 struct delayed_work *dwork = to_delayed_work(work);
2287 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2288 kvmclock_sync_work);
2289 struct kvm *kvm = container_of(ka, struct kvm, arch);
2290
630994b3
MT		 2291 if (!kvmclock_periodic_sync)
2292 return;
2293
332967a3
AJ		 2294 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2295 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2296 KVMCLOCK_SYNC_PERIOD);
2297}
2298
191c8137
BP		 2299/*
2300 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2301 */
2302static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2303{
2304 /* McStatusWrEn enabled? */
2305 if (guest_cpuid_is_amd(vcpu))
2306 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2307
2308 return false;
2309}
2310
9ffd986c 2311static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2312{
890ca9ae
HY		 2313 u64 mcg_cap = vcpu->arch.mcg_cap;
2314 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2315 u32 msr = msr_info->index;
2316 u64 data = msr_info->data;
890ca9ae 2317
15c4a640 2318 switch (msr) {
15c4a640 2319 case MSR_IA32_MCG_STATUS:
890ca9ae 2320 vcpu->arch.mcg_status = data;
15c4a640 2321 break;
c7ac679c 2322 case MSR_IA32_MCG_CTL:
44883f01
PB		 2323 if (!(mcg_cap & MCG_CTL_P) &&
2324 (data || !msr_info->host_initiated))
890ca9ae
HY		 2325 return 1;
2326 if (data != 0 && data != ~(u64)0)
44883f01 2327 return 1;
890ca9ae
HY		 2328 vcpu->arch.mcg_ctl = data;
2329 break;
2330 default:
2331 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2332 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2333 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2334 /* only 0 or all 1s can be written to IA32_MCi_CTL
2335 * some Linux kernels though clear bit 10 in bank 4 to
2336 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2337 * this to avoid an uncatched #GP in the guest
2338 */
890ca9ae 2339 if ((offset & 0x3) == 0 &&
114be429 2340 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2341 return -1;
191c8137
BP		 2342
2343 /* MCi_STATUS */
9ffd986c 2344 if (!msr_info->host_initiated &&
191c8137
BP		 2345 (offset & 0x3) == 1 && data != 0) {
2346 if (!can_set_mci_status(vcpu))
2347 return -1;
2348 }
2349
890ca9ae
HY		 2350 vcpu->arch.mce_banks[offset] = data;
2351 break;
2352 }
2353 return 1;
2354 }
2355 return 0;
2356}
2357
ffde22ac
ES		 2358static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2359{
2360 struct kvm *kvm = vcpu->kvm;
2361 int lm = is_long_mode(vcpu);
2362 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2363 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2364 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2365 : kvm->arch.xen_hvm_config.blob_size_32;
2366 u32 page_num = data & ~PAGE_MASK;
2367 u64 page_addr = data & PAGE_MASK;
2368 u8 *page;
2369 int r;
2370
2371 r = -E2BIG;
2372 if (page_num >= blob_size)
2373 goto out;
2374 r = -ENOMEM;
ff5c2c03
SL		 2375 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2376 if (IS_ERR(page)) {
2377 r = PTR_ERR(page);
ffde22ac 2378 goto out;
ff5c2c03 2379 }
54bf36aa 2380 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2381 goto out_free;
2382 r = 0;
2383out_free:
2384 kfree(page);
2385out:
2386 return r;
2387}
2388
344d9588
GN		 2389static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2390{
2391 gpa_t gpa = data & ~0x3f;
2392
52a5c155
WL		 2393 /* Bits 3:5 are reserved, Should be zero */
2394 if (data & 0x38)
344d9588
GN		 2395 return 1;
2396
2397 vcpu->arch.apf.msr_val = data;
2398
2399 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2400 kvm_clear_async_pf_completion_queue(vcpu);
2401 kvm_async_pf_hash_reset(vcpu);
2402 return 0;
2403 }
2404
4e335d9e 2405 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2406 sizeof(u32)))
344d9588
GN		 2407 return 1;
2408
6adba527 2409 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2410 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2411 kvm_async_pf_wakeup_all(vcpu);
2412 return 0;
2413}
2414
12f9a48f
GC		 2415static void kvmclock_reset(struct kvm_vcpu *vcpu)
2416{
0b79459b 2417 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2418}
2419
f38a7b75
WL		 2420static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2421{
2422 ++vcpu->stat.tlb_flush;
2423 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2424}
2425
c9aaa895
GC		 2426static void record_steal_time(struct kvm_vcpu *vcpu)
2427{
2428 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2429 return;
2430
4e335d9e 2431 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2432 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2433 return;
2434
f38a7b75
WL		 2435 /*
2436 * Doing a TLB flush here, on the guest's behalf, can avoid
2437 * expensive IPIs.
2438 */
2439 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2440 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2441
35f3fae1
WL		 2442 if (vcpu->arch.st.steal.version & 1)
2443 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2444
2445 vcpu->arch.st.steal.version += 1;
2446
4e335d9e 2447 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2448 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2449
2450 smp_wmb();
2451
c54cdf14
LC		 2452 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2453 vcpu->arch.st.last_steal;
2454 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2455
4e335d9e 2456 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2457 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2458
2459 smp_wmb();
2460
2461 vcpu->arch.st.steal.version += 1;
c9aaa895 2462
4e335d9e 2463 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2464 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2465}
2466
8fe8ab46 2467int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2468{
5753785f 2469 bool pr = false;
8fe8ab46
WA		 2470 u32 msr = msr_info->index;
2471 u64 data = msr_info->data;
5753785f 2472
15c4a640 2473 switch (msr) {
2e32b719 2474 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2475 case MSR_IA32_UCODE_WRITE:
2476 case MSR_VM_HSAVE_PA:
2477 case MSR_AMD64_PATCH_LOADER:
2478 case MSR_AMD64_BU_CFG2:
405a353a 2479 case MSR_AMD64_DC_CFG:
0e1b869f 2480 case MSR_F15H_EX_CFG:
2e32b719
BP		 2481 break;
2482
518e7b94
WL		 2483 case MSR_IA32_UCODE_REV:
2484 if (msr_info->host_initiated)
2485 vcpu->arch.microcode_version = data;
2486 break;
0cf9135b
SC		 2487 case MSR_IA32_ARCH_CAPABILITIES:
2488 if (!msr_info->host_initiated)
2489 return 1;
2490 vcpu->arch.arch_capabilities = data;
2491 break;
15c4a640 2492 case MSR_EFER:
11988499 2493 return set_efer(vcpu, msr_info);
8f1589d9
AP		 2494 case MSR_K7_HWCR:
2495 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2496 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2497 data &= ~(u64)0x8; /* ignore TLB cache disable */
191c8137
BP		 2498
2499 /* Handle McStatusWrEn */
2500 if (data == BIT_ULL(18)) {
2501 vcpu->arch.msr_hwcr = data;
2502 } else if (data != 0) {
a737f256
CD		 2503 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2504 data);
8f1589d9
AP		 2505 return 1;
2506 }
15c4a640 2507 break;
f7c6d140
AP		 2508 case MSR_FAM10H_MMIO_CONF_BASE:
2509 if (data != 0) {
a737f256
CD		 2510 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2511 "0x%llx\n", data);
f7c6d140
AP		 2512 return 1;
2513 }
15c4a640 2514 break;
b5e2fec0
AG		 2515 case MSR_IA32_DEBUGCTLMSR:
2516 if (!data) {
2517 /* We support the non-activated case already */
2518 break;
2519 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2520 /* Values other than LBR and BTF are vendor-specific,
2521 thus reserved and should throw a #GP */
2522 return 1;
2523 }
a737f256
CD		 2524 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2525 __func__, data);
b5e2fec0 2526 break;
9ba075a6 2527 case 0x200 ... 0x2ff:
ff53604b 2528 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2529 case MSR_IA32_APICBASE:
58cb628d 2530 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2531 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2532 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2533 case MSR_IA32_TSCDEADLINE:
2534 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2535 break;
ba904635 2536 case MSR_IA32_TSC_ADJUST:
d6321d49 2537 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2538 if (!msr_info->host_initiated) {
d913b904 2539 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2540 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2541 }
2542 vcpu->arch.ia32_tsc_adjust_msr = data;
2543 }
2544 break;
15c4a640 2545 case MSR_IA32_MISC_ENABLE:
ad312c7c 2546 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2547 break;
64d60670
PB		 2548 case MSR_IA32_SMBASE:
2549 if (!msr_info->host_initiated)
2550 return 1;
2551 vcpu->arch.smbase = data;
2552 break;
dd259935
PB		 2553 case MSR_IA32_TSC:
2554 kvm_write_tsc(vcpu, msr_info);
2555 break;
52797bf9
LA		 2556 case MSR_SMI_COUNT:
2557 if (!msr_info->host_initiated)
2558 return 1;
2559 vcpu->arch.smi_count = data;
2560 break;
11c6bffa 2561 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2562 case MSR_KVM_WALL_CLOCK:
2563 vcpu->kvm->arch.wall_clock = data;
2564 kvm_write_wall_clock(vcpu->kvm, data);
2565 break;
11c6bffa 2566 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2567 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2568 struct kvm_arch *ka = &vcpu->kvm->arch;
2569
12f9a48f 2570 kvmclock_reset(vcpu);
18068523 2571
54750f2c
MT		 2572 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2573 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2574
2575 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2576 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2577
2578 ka->boot_vcpu_runs_old_kvmclock = tmp;
2579 }
2580
18068523 2581 vcpu->arch.time = data;
0061d53d 2582 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2583
2584 /* we verify if the enable bit is set... */
2585 if (!(data & 1))
2586 break;
2587
4e335d9e 2588 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2589 &vcpu->arch.pv_time, data & ~1ULL,
2590 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2591 vcpu->arch.pv_time_enabled = false;
2592 else
2593 vcpu->arch.pv_time_enabled = true;
32cad84f 2594
18068523
GOC		 2595 break;
2596 }
344d9588
GN		 2597 case MSR_KVM_ASYNC_PF_EN:
2598 if (kvm_pv_enable_async_pf(vcpu, data))
2599 return 1;
2600 break;
c9aaa895
GC		 2601 case MSR_KVM_STEAL_TIME:
2602
2603 if (unlikely(!sched_info_on()))
2604 return 1;
2605
2606 if (data & KVM_STEAL_RESERVED_MASK)
2607 return 1;
2608
4e335d9e 2609 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2610 data & KVM_STEAL_VALID_BITS,
2611 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2612 return 1;
2613
2614 vcpu->arch.st.msr_val = data;
2615
2616 if (!(data & KVM_MSR_ENABLED))
2617 break;
2618
c9aaa895
GC		 2619 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2620
2621 break;
ae7a2a3f 2622 case MSR_KVM_PV_EOI_EN:
72bbf935 2623 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2624 return 1;
2625 break;
c9aaa895 2626
890ca9ae
HY		 2627 case MSR_IA32_MCG_CTL:
2628 case MSR_IA32_MCG_STATUS:
81760dcc 2629 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2630 return set_msr_mce(vcpu, msr_info);
71db6023 2631
6912ac32
WH		 2632 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2633 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2634 pr = true; /* fall through */
2635 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2636 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2637 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2638 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2639
2640 if (pr || data != 0)
a737f256
CD		 2641 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2642 "0x%x data 0x%llx\n", msr, data);
5753785f 2643 break;
84e0cefa
JS		 2644 case MSR_K7_CLK_CTL:
2645 /*
2646 * Ignore all writes to this no longer documented MSR.
2647 * Writes are only relevant for old K7 processors,
2648 * all pre-dating SVM, but a recommended workaround from
4a969980 2649 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2650 * affected processor models on the command line, hence
2651 * the need to ignore the workaround.
2652 */
2653 break;
55cd8e5a 2654 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2655 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2656 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2657 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2658 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2659 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2660 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2661 return kvm_hv_set_msr_common(vcpu, msr, data,
2662 msr_info->host_initiated);
91c9c3ed 2663 case MSR_IA32_BBL_CR_CTL3:
2664 /* Drop writes to this legacy MSR -- see rdmsr
2665 * counterpart for further detail.
2666 */
fab0aa3b
EM		 2667 if (report_ignored_msrs)
2668 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2669 msr, data);
91c9c3ed 2670 break;
2b036c6b 2671 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2672 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2673 return 1;
2674 vcpu->arch.osvw.length = data;
2675 break;
2676 case MSR_AMD64_OSVW_STATUS:
d6321d49 2677 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2678 return 1;
2679 vcpu->arch.osvw.status = data;
2680 break;
db2336a8
KH		 2681 case MSR_PLATFORM_INFO:
2682 if (!msr_info->host_initiated ||
db2336a8
KH		 2683 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2684 cpuid_fault_enabled(vcpu)))
2685 return 1;
2686 vcpu->arch.msr_platform_info = data;
2687 break;
2688 case MSR_MISC_FEATURES_ENABLES:
2689 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2690 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2691 !supports_cpuid_fault(vcpu)))
2692 return 1;
2693 vcpu->arch.msr_misc_features_enables = data;
2694 break;
15c4a640 2695 default:
ffde22ac
ES		 2696 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2697 return xen_hvm_config(vcpu, data);
c6702c9d 2698 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2699 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2700 if (!ignore_msrs) {
ae0f5499 2701 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2702 msr, data);
ed85c068
AP		 2703 return 1;
2704 } else {
fab0aa3b
EM		 2705 if (report_ignored_msrs)
2706 vcpu_unimpl(vcpu,
2707 "ignored wrmsr: 0x%x data 0x%llx\n",
2708 msr, data);
ed85c068
AP		 2709 break;
2710 }
15c4a640
CO		 2711 }
2712 return 0;
2713}
2714EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2715
2716
2717/*
2718 * Reads an msr value (of 'msr_index') into 'pdata'.
2719 * Returns 0 on success, non-0 otherwise.
2720 * Assumes vcpu_load() was already called.
2721 */
609e36d3 2722int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2723{
609e36d3 2724 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2725}
ff651cb6 2726EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2727
44883f01 2728static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2729{
2730 u64 data;
890ca9ae
HY		 2731 u64 mcg_cap = vcpu->arch.mcg_cap;
2732 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2733
2734 switch (msr) {
15c4a640
CO		 2735 case MSR_IA32_P5_MC_ADDR:
2736 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2737 data = 0;
2738 break;
15c4a640 2739 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2740 data = vcpu->arch.mcg_cap;
2741 break;
c7ac679c 2742 case MSR_IA32_MCG_CTL:
44883f01 2743 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2744 return 1;
2745 data = vcpu->arch.mcg_ctl;
2746 break;
2747 case MSR_IA32_MCG_STATUS:
2748 data = vcpu->arch.mcg_status;
2749 break;
2750 default:
2751 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2752 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2753 u32 offset = msr - MSR_IA32_MC0_CTL;
2754 data = vcpu->arch.mce_banks[offset];
2755 break;
2756 }
2757 return 1;
2758 }
2759 *pdata = data;
2760 return 0;
2761}
2762
609e36d3 2763int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2764{
609e36d3 2765 switch (msr_info->index) {
890ca9ae 2766 case MSR_IA32_PLATFORM_ID:
15c4a640 2767 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2768 case MSR_IA32_DEBUGCTLMSR:
2769 case MSR_IA32_LASTBRANCHFROMIP:
2770 case MSR_IA32_LASTBRANCHTOIP:
2771 case MSR_IA32_LASTINTFROMIP:
2772 case MSR_IA32_LASTINTTOIP:
60af2ecd 2773 case MSR_K8_SYSCFG:
3afb1121
PB		 2774 case MSR_K8_TSEG_ADDR:
2775 case MSR_K8_TSEG_MASK:
61a6bd67 2776 case MSR_VM_HSAVE_PA:
1fdbd48c 2777 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2778 case MSR_AMD64_NB_CFG:
f7c6d140 2779 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2780 case MSR_AMD64_BU_CFG2:
0c2df2a1 2781 case MSR_IA32_PERF_CTL:
405a353a 2782 case MSR_AMD64_DC_CFG:
0e1b869f 2783 case MSR_F15H_EX_CFG:
609e36d3 2784 msr_info->data = 0;
15c4a640 2785 break;
c51eb52b 2786 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2787 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2788 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2789 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2790 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2791 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2792 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2793 msr_info->data = 0;
5753785f 2794 break;
742bc670 2795 case MSR_IA32_UCODE_REV:
518e7b94 2796 msr_info->data = vcpu->arch.microcode_version;
742bc670 2797 break;
0cf9135b
SC		 2798 case MSR_IA32_ARCH_CAPABILITIES:
2799 if (!msr_info->host_initiated &&
2800 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2801 return 1;
2802 msr_info->data = vcpu->arch.arch_capabilities;
2803 break;
dd259935
PB		 2804 case MSR_IA32_TSC:
2805 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2806 break;
9ba075a6 2807 case MSR_MTRRcap:
9ba075a6 2808 case 0x200 ... 0x2ff:
ff53604b 2809 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2810 case 0xcd: /* fsb frequency */
609e36d3 2811 msr_info->data = 3;
15c4a640 2812 break;
7b914098
JS		 2813 /*
2814 * MSR_EBC_FREQUENCY_ID
2815 * Conservative value valid for even the basic CPU models.
2816 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2817 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2818 * and 266MHz for model 3, or 4. Set Core Clock
2819 * Frequency to System Bus Frequency Ratio to 1 (bits
2820 * 31:24) even though these are only valid for CPU
2821 * models > 2, however guests may end up dividing or
2822 * multiplying by zero otherwise.
2823 */
2824 case MSR_EBC_FREQUENCY_ID:
609e36d3 2825 msr_info->data = 1 << 24;
7b914098 2826 break;
15c4a640 2827 case MSR_IA32_APICBASE:
609e36d3 2828 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2829 break;
0105d1a5 2830 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2831 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2832 break;
a3e06bbe 2833 case MSR_IA32_TSCDEADLINE:
609e36d3 2834 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2835 break;
ba904635 2836 case MSR_IA32_TSC_ADJUST:
609e36d3 2837 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2838 break;
15c4a640 2839 case MSR_IA32_MISC_ENABLE:
609e36d3 2840 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2841 break;
64d60670
PB		 2842 case MSR_IA32_SMBASE:
2843 if (!msr_info->host_initiated)
2844 return 1;
2845 msr_info->data = vcpu->arch.smbase;
15c4a640 2846 break;
52797bf9
LA		 2847 case MSR_SMI_COUNT:
2848 msr_info->data = vcpu->arch.smi_count;
2849 break;
847f0ad8
AG		 2850 case MSR_IA32_PERF_STATUS:
2851 /* TSC increment by tick */
609e36d3 2852 msr_info->data = 1000ULL;
847f0ad8 2853 /* CPU multiplier */
b0996ae4 2854 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2855 break;
15c4a640 2856 case MSR_EFER:
609e36d3 2857 msr_info->data = vcpu->arch.efer;
15c4a640 2858 break;
18068523 2859 case MSR_KVM_WALL_CLOCK:
11c6bffa 2860 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2861 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2862 break;
2863 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2864 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2865 msr_info->data = vcpu->arch.time;
18068523 2866 break;
344d9588 2867 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2868 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2869 break;
c9aaa895 2870 case MSR_KVM_STEAL_TIME:
609e36d3 2871 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2872 break;
1d92128f 2873 case MSR_KVM_PV_EOI_EN:
609e36d3 2874 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2875 break;
890ca9ae
HY		 2876 case MSR_IA32_P5_MC_ADDR:
2877 case MSR_IA32_P5_MC_TYPE:
2878 case MSR_IA32_MCG_CAP:
2879 case MSR_IA32_MCG_CTL:
2880 case MSR_IA32_MCG_STATUS:
81760dcc 2881 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2882 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2883 msr_info->host_initiated);
84e0cefa
JS		 2884 case MSR_K7_CLK_CTL:
2885 /*
2886 * Provide expected ramp-up count for K7. All other
2887 * are set to zero, indicating minimum divisors for
2888 * every field.
2889 *
2890 * This prevents guest kernels on AMD host with CPU
2891 * type 6, model 8 and higher from exploding due to
2892 * the rdmsr failing.
2893 */
609e36d3 2894 msr_info->data = 0x20000000;
84e0cefa 2895 break;
55cd8e5a 2896 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2897 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2898 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2899 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2900 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2901 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2902 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2903 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2904 msr_info->index, &msr_info->data,
2905 msr_info->host_initiated);
55cd8e5a 2906 break;
91c9c3ed 2907 case MSR_IA32_BBL_CR_CTL3:
2908 /* This legacy MSR exists but isn't fully documented in current
2909 * silicon. It is however accessed by winxp in very narrow
2910 * scenarios where it sets bit #19, itself documented as
2911 * a "reserved" bit. Best effort attempt to source coherent
2912 * read data here should the balance of the register be
2913 * interpreted by the guest:
2914 *
2915 * L2 cache control register 3: 64GB range, 256KB size,
2916 * enabled, latency 0x1, configured
2917 */
609e36d3 2918 msr_info->data = 0xbe702111;
91c9c3ed 2919 break;
2b036c6b 2920 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2921 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2922 return 1;
609e36d3 2923 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2924 break;
2925 case MSR_AMD64_OSVW_STATUS:
d6321d49 2926 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2927 return 1;
609e36d3 2928 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2929 break;
db2336a8 2930 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2931 if (!msr_info->host_initiated &&
2932 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2933 return 1;
db2336a8
KH		 2934 msr_info->data = vcpu->arch.msr_platform_info;
2935 break;
2936 case MSR_MISC_FEATURES_ENABLES:
2937 msr_info->data = vcpu->arch.msr_misc_features_enables;
2938 break;
191c8137
BP		 2939 case MSR_K7_HWCR:
2940 msr_info->data = vcpu->arch.msr_hwcr;
2941 break;
15c4a640 2942 default:
c6702c9d 2943 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2944 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2945 if (!ignore_msrs) {
ae0f5499
BD		 2946 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2947 msr_info->index);
ed85c068
AP		 2948 return 1;
2949 } else {
fab0aa3b
EM		 2950 if (report_ignored_msrs)
2951 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2952 msr_info->index);
609e36d3 2953 msr_info->data = 0;
ed85c068
AP		 2954 }
2955 break;
15c4a640 2956 }
15c4a640
CO		 2957 return 0;
2958}
2959EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2960
313a3dc7
CO		 2961/*
2962 * Read or write a bunch of msrs. All parameters are kernel addresses.
2963 *
2964 * @return number of msrs set successfully.
2965 */
2966static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2967 struct kvm_msr_entry *entries,
2968 int (*do_msr)(struct kvm_vcpu *vcpu,
2969 unsigned index, u64 *data))
2970{
801e459a 2971 int i;
313a3dc7 2972
313a3dc7
CO		 2973 for (i = 0; i < msrs->nmsrs; ++i)
2974 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2975 break;
2976
313a3dc7
CO		 2977 return i;
2978}
2979
2980/*
2981 * Read or write a bunch of msrs. Parameters are user addresses.
2982 *
2983 * @return number of msrs set successfully.
2984 */
2985static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2986 int (*do_msr)(struct kvm_vcpu *vcpu,
2987 unsigned index, u64 *data),
2988 int writeback)
2989{
2990 struct kvm_msrs msrs;
2991 struct kvm_msr_entry *entries;
2992 int r, n;
2993 unsigned size;
2994
2995 r = -EFAULT;
0e96f31e 2996 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 2997 goto out;
2998
2999 r = -E2BIG;
3000 if (msrs.nmsrs >= MAX_IO_MSRS)
3001 goto out;
3002
313a3dc7 3003 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 3004 entries = memdup_user(user_msrs->entries, size);
3005 if (IS_ERR(entries)) {
3006 r = PTR_ERR(entries);
313a3dc7 3007 goto out;
ff5c2c03 3008 }
313a3dc7
CO		 3009
3010 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3011 if (r < 0)
3012 goto out_free;
3013
3014 r = -EFAULT;
3015 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3016 goto out_free;
3017
3018 r = n;
3019
3020out_free:
7a73c028 3021 kfree(entries);
313a3dc7
CO		 3022out:
3023 return r;
3024}
3025
4d5422ce
WL		 3026static inline bool kvm_can_mwait_in_guest(void)
3027{
3028 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 3029 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3030 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 3031}
3032
784aa3d7 3033int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 3034{
4d5422ce 3035 int r = 0;
018d00d2
ZX		 3036
3037 switch (ext) {
3038 case KVM_CAP_IRQCHIP:
3039 case KVM_CAP_HLT:
3040 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 3041 case KVM_CAP_SET_TSS_ADDR:
07716717 3042 case KVM_CAP_EXT_CPUID:
9c15bb1d 3043 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3044 case KVM_CAP_CLOCKSOURCE:
7837699f 3045 case KVM_CAP_PIT:
a28e4f5a 3046 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3047 case KVM_CAP_MP_STATE:
ed848624 3048 case KVM_CAP_SYNC_MMU:
a355c85c 3049 case KVM_CAP_USER_NMI:
52d939a0 3050 case KVM_CAP_REINJECT_CONTROL:
4925663a 3051 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3052 case KVM_CAP_IOEVENTFD:
f848a5a8 3053 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3054 case KVM_CAP_PIT2:
e9f42757 3055 case KVM_CAP_PIT_STATE2:
b927a3ce 3056 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3057 case KVM_CAP_XEN_HVM:
3cfc3092 3058 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3059 case KVM_CAP_HYPERV:
10388a07 3060 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3061 case KVM_CAP_HYPERV_SPIN:
5c919412 3062 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3063 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3064 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3065 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3066 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3067 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 3068 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
2bc39970 3069 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3070 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3071 case KVM_CAP_DEBUGREGS:
d2be1651 3072 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3073 case KVM_CAP_XSAVE:
344d9588 3074 case KVM_CAP_ASYNC_PF:
92a1f12d 3075 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3076 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3077 case KVM_CAP_READONLY_MEM:
5f66b620 3078 case KVM_CAP_HYPERV_TIME:
100943c5 3079 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3080 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3081 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3082 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3083 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3084 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 3085 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3086 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3087 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3088 r = 1;
3089 break;
01643c51
KH		 3090 case KVM_CAP_SYNC_REGS:
3091 r = KVM_SYNC_X86_VALID_FIELDS;
3092 break;
e3fd9a93
PB		 3093 case KVM_CAP_ADJUST_CLOCK:
3094 r = KVM_CLOCK_TSC_STABLE;
3095 break;
4d5422ce 3096 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 3097 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 3098 if(kvm_can_mwait_in_guest())
3099 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3100 break;
6d396b55
PB		 3101 case KVM_CAP_X86_SMM:
3102 /* SMBASE is usually relocated above 1M on modern chipsets,
3103 * and SMM handlers might indeed rely on 4G segment limits,
3104 * so do not report SMM to be available if real mode is
3105 * emulated via vm86 mode. Still, do not go to great lengths
3106 * to avoid userspace's usage of the feature, because it is a
3107 * fringe case that is not enabled except via specific settings
3108 * of the module parameters.
3109 */
bc226f07 3110 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3111 break;
774ead3a
AK		 3112 case KVM_CAP_VAPIC:
3113 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3114 break;
f725230a 3115 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3116 r = KVM_SOFT_MAX_VCPUS;
3117 break;
3118 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3119 r = KVM_MAX_VCPUS;
3120 break;
a68a6a72
MT		 3121 case KVM_CAP_PV_MMU: /* obsolete */
3122 r = 0;
2f333bcb 3123 break;
890ca9ae
HY		 3124 case KVM_CAP_MCE:
3125 r = KVM_MAX_MCE_BANKS;
3126 break;
2d5b5a66 3127 case KVM_CAP_XCRS:
d366bf7e 3128 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3129 break;
92a1f12d
JR		 3130 case KVM_CAP_TSC_CONTROL:
3131 r = kvm_has_tsc_control;
3132 break;
37131313
RK		 3133 case KVM_CAP_X2APIC_API:
3134 r = KVM_X2APIC_API_VALID_FLAGS;
3135 break;
8fcc4b59
JM		 3136 case KVM_CAP_NESTED_STATE:
3137 r = kvm_x86_ops->get_nested_state ?
be43c440 3138 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3139 break;
018d00d2 3140 default:
018d00d2
ZX		 3141 break;
3142 }
3143 return r;
3144
3145}
3146
043405e1
CO		 3147long kvm_arch_dev_ioctl(struct file *filp,
3148 unsigned int ioctl, unsigned long arg)
3149{
3150 void __user *argp = (void __user *)arg;
3151 long r;
3152
3153 switch (ioctl) {
3154 case KVM_GET_MSR_INDEX_LIST: {
3155 struct kvm_msr_list __user *user_msr_list = argp;
3156 struct kvm_msr_list msr_list;
3157 unsigned n;
3158
3159 r = -EFAULT;
0e96f31e 3160 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3161 goto out;
3162 n = msr_list.nmsrs;
62ef68bb 3163 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3164 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3165 goto out;
3166 r = -E2BIG;
e125e7b6 3167 if (n < msr_list.nmsrs)
043405e1
CO		 3168 goto out;
3169 r = -EFAULT;
3170 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3171 num_msrs_to_save * sizeof(u32)))
3172 goto out;
e125e7b6 3173 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3174 &emulated_msrs,
62ef68bb 3175 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3176 goto out;
3177 r = 0;
3178 break;
3179 }
9c15bb1d
BP		 3180 case KVM_GET_SUPPORTED_CPUID:
3181 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3182 struct kvm_cpuid2 __user *cpuid_arg = argp;
3183 struct kvm_cpuid2 cpuid;
3184
3185 r = -EFAULT;
0e96f31e 3186 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3187 goto out;
9c15bb1d
BP		 3188
3189 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3190 ioctl);
674eea0f
AK		 3191 if (r)
3192 goto out;
3193
3194 r = -EFAULT;
0e96f31e 3195 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3196 goto out;
3197 r = 0;
3198 break;
3199 }
890ca9ae 3200 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3201 r = -EFAULT;
c45dcc71
AR		 3202 if (copy_to_user(argp, &kvm_mce_cap_supported,
3203 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3204 goto out;
3205 r = 0;
3206 break;
801e459a
TL		 3207 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3208 struct kvm_msr_list __user *user_msr_list = argp;
3209 struct kvm_msr_list msr_list;
3210 unsigned int n;
3211
3212 r = -EFAULT;
3213 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3214 goto out;
3215 n = msr_list.nmsrs;
3216 msr_list.nmsrs = num_msr_based_features;
3217 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3218 goto out;
3219 r = -E2BIG;
3220 if (n < msr_list.nmsrs)
3221 goto out;
3222 r = -EFAULT;
3223 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3224 num_msr_based_features * sizeof(u32)))
3225 goto out;
3226 r = 0;
3227 break;
3228 }
3229 case KVM_GET_MSRS:
3230 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3231 break;
890ca9ae 3232 }
043405e1
CO		 3233 default:
3234 r = -EINVAL;
3235 }
3236out:
3237 return r;
3238}
3239
f5f48ee1
SY		 3240static void wbinvd_ipi(void *garbage)
3241{
3242 wbinvd();
3243}
3244
3245static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3246{
e0f0bbc5 3247 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3248}
3249
313a3dc7
CO		 3250void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3251{
f5f48ee1
SY		 3252 /* Address WBINVD may be executed by guest */
3253 if (need_emulate_wbinvd(vcpu)) {
3254 if (kvm_x86_ops->has_wbinvd_exit())
3255 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3256 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3257 smp_call_function_single(vcpu->cpu,
3258 wbinvd_ipi, NULL, 1);
3259 }
3260
313a3dc7 3261 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3262
0dd6a6ed
ZA		 3263 /* Apply any externally detected TSC adjustments (due to suspend) */
3264 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3265 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3266 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3267 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3268 }
8f6055cb 3269
b0c39dc6 3270 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3271 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3272 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3273 if (tsc_delta < 0)
3274 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3275
b0c39dc6 3276 if (kvm_check_tsc_unstable()) {
07c1419a 3277 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3278 vcpu->arch.last_guest_tsc);
a545ab6a 3279 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3280 vcpu->arch.tsc_catchup = 1;
c285545f 3281 }
a749e247
PB		 3282
3283 if (kvm_lapic_hv_timer_in_use(vcpu))
3284 kvm_lapic_restart_hv_timer(vcpu);
3285
d98d07ca
MT		 3286 /*
3287 * On a host with synchronized TSC, there is no need to update
3288 * kvmclock on vcpu->cpu migration
3289 */
3290 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3291 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3292 if (vcpu->cpu != cpu)
1bd2009e 3293 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3294 vcpu->cpu = cpu;
6b7d7e76 3295 }
c9aaa895 3296
c9aaa895 3297 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3298}
3299
0b9f6c46
PX		 3300static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3301{
3302 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3303 return;
3304
fa55eedd 3305 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3306
4e335d9e 3307 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3308 &vcpu->arch.st.steal.preempted,
3309 offsetof(struct kvm_steal_time, preempted),
3310 sizeof(vcpu->arch.st.steal.preempted));
3311}
3312
313a3dc7
CO		 3313void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3314{
cc0d907c 3315 int idx;
de63ad4c
LM		 3316
3317 if (vcpu->preempted)
3318 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3319
931f261b
AA		 3320 /*
3321 * Disable page faults because we're in atomic context here.
3322 * kvm_write_guest_offset_cached() would call might_fault()
3323 * that relies on pagefault_disable() to tell if there's a
3324 * bug. NOTE: the write to guest memory may not go through if
3325 * during postcopy live migration or if there's heavy guest
3326 * paging.
3327 */
3328 pagefault_disable();
cc0d907c
AA		 3329 /*
3330 * kvm_memslots() will be called by
3331 * kvm_write_guest_offset_cached() so take the srcu lock.
3332 */
3333 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3334 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3335 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3336 pagefault_enable();
02daab21 3337 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3338 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3339 /*
f9dcf08e
RK		 3340 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3341 * on every vmexit, but if not, we might have a stale dr6 from the
3342 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3343 */
f9dcf08e 3344 set_debugreg(0, 6);
313a3dc7
CO		 3345}
3346
313a3dc7
CO		 3347static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3348 struct kvm_lapic_state *s)
3349{
fa59cc00 3350 if (vcpu->arch.apicv_active)
d62caabb
AS		 3351 kvm_x86_ops->sync_pir_to_irr(vcpu);
3352
a92e2543 3353 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3354}
3355
3356static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3357 struct kvm_lapic_state *s)
3358{
a92e2543
RK		 3359 int r;
3360
3361 r = kvm_apic_set_state(vcpu, s);
3362 if (r)
3363 return r;
cb142eb7 3364 update_cr8_intercept(vcpu);
313a3dc7
CO		 3365
3366 return 0;
3367}
3368
127a457a
MG		 3369static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3370{
3371 return (!lapic_in_kernel(vcpu) ||
3372 kvm_apic_accept_pic_intr(vcpu));
3373}
3374
782d422b
MG		 3375/*
3376 * if userspace requested an interrupt window, check that the
3377 * interrupt window is open.
3378 *
3379 * No need to exit to userspace if we already have an interrupt queued.
3380 */
3381static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3382{
3383 return kvm_arch_interrupt_allowed(vcpu) &&
3384 !kvm_cpu_has_interrupt(vcpu) &&
3385 !kvm_event_needs_reinjection(vcpu) &&
3386 kvm_cpu_accept_dm_intr(vcpu);
3387}
3388
f77bc6a4
ZX		 3389static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3390 struct kvm_interrupt *irq)
3391{
02cdb50f 3392 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3393 return -EINVAL;
1c1a9ce9
SR		 3394
3395 if (!irqchip_in_kernel(vcpu->kvm)) {
3396 kvm_queue_interrupt(vcpu, irq->irq, false);
3397 kvm_make_request(KVM_REQ_EVENT, vcpu);
3398 return 0;
3399 }
3400
3401 /*
3402 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3403 * fail for in-kernel 8259.
3404 */
3405 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3406 return -ENXIO;
f77bc6a4 3407
1c1a9ce9
SR		 3408 if (vcpu->arch.pending_external_vector != -1)
3409 return -EEXIST;
f77bc6a4 3410
1c1a9ce9 3411 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3412 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3413 return 0;
3414}
3415
c4abb7c9
JK		 3416static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3417{
c4abb7c9 3418 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3419
3420 return 0;
3421}
3422
f077825a
PB		 3423static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3424{
64d60670
PB		 3425 kvm_make_request(KVM_REQ_SMI, vcpu);
3426
f077825a
PB		 3427 return 0;
3428}
3429
b209749f
AK		 3430static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3431 struct kvm_tpr_access_ctl *tac)
3432{
3433 if (tac->flags)
3434 return -EINVAL;
3435 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3436 return 0;
3437}
3438
890ca9ae
HY		 3439static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3440 u64 mcg_cap)
3441{
3442 int r;
3443 unsigned bank_num = mcg_cap & 0xff, bank;
3444
3445 r = -EINVAL;
a9e38c3e 3446 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3447 goto out;
c45dcc71 3448 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3449 goto out;
3450 r = 0;
3451 vcpu->arch.mcg_cap = mcg_cap;
3452 /* Init IA32_MCG_CTL to all 1s */
3453 if (mcg_cap & MCG_CTL_P)
3454 vcpu->arch.mcg_ctl = ~(u64)0;
3455 /* Init IA32_MCi_CTL to all 1s */
3456 for (bank = 0; bank < bank_num; bank++)
3457 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3458
3459 if (kvm_x86_ops->setup_mce)
3460 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3461out:
3462 return r;
3463}
3464
3465static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3466 struct kvm_x86_mce *mce)
3467{
3468 u64 mcg_cap = vcpu->arch.mcg_cap;
3469 unsigned bank_num = mcg_cap & 0xff;
3470 u64 *banks = vcpu->arch.mce_banks;
3471
3472 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3473 return -EINVAL;
3474 /*
3475 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3476 * reporting is disabled
3477 */
3478 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3479 vcpu->arch.mcg_ctl != ~(u64)0)
3480 return 0;
3481 banks += 4 * mce->bank;
3482 /*
3483 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3484 * reporting is disabled for the bank
3485 */
3486 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3487 return 0;
3488 if (mce->status & MCI_STATUS_UC) {
3489 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3490 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3491 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3492 return 0;
3493 }
3494 if (banks[1] & MCI_STATUS_VAL)
3495 mce->status |= MCI_STATUS_OVER;
3496 banks[2] = mce->addr;
3497 banks[3] = mce->misc;
3498 vcpu->arch.mcg_status = mce->mcg_status;
3499 banks[1] = mce->status;
3500 kvm_queue_exception(vcpu, MC_VECTOR);
3501 } else if (!(banks[1] & MCI_STATUS_VAL)
3502 || !(banks[1] & MCI_STATUS_UC)) {
3503 if (banks[1] & MCI_STATUS_VAL)
3504 mce->status |= MCI_STATUS_OVER;
3505 banks[2] = mce->addr;
3506 banks[3] = mce->misc;
3507 banks[1] = mce->status;
3508 } else
3509 banks[1] |= MCI_STATUS_OVER;
3510 return 0;
3511}
3512
3cfc3092
JK		 3513static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3514 struct kvm_vcpu_events *events)
3515{
7460fb4a 3516 process_nmi(vcpu);
59073aaf 3517
664f8e26 3518 /*
59073aaf
JM		 3519 * The API doesn't provide the instruction length for software
3520 * exceptions, so don't report them. As long as the guest RIP
3521 * isn't advanced, we should expect to encounter the exception
3522 * again.
664f8e26 3523 */
59073aaf
JM		 3524 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3525 events->exception.injected = 0;
3526 events->exception.pending = 0;
3527 } else {
3528 events->exception.injected = vcpu->arch.exception.injected;
3529 events->exception.pending = vcpu->arch.exception.pending;
3530 /*
3531 * For ABI compatibility, deliberately conflate
3532 * pending and injected exceptions when
3533 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3534 */
3535 if (!vcpu->kvm->arch.exception_payload_enabled)
3536 events->exception.injected |=
3537 vcpu->arch.exception.pending;
3538 }
3cfc3092
JK		 3539 events->exception.nr = vcpu->arch.exception.nr;
3540 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3541 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3542 events->exception_has_payload = vcpu->arch.exception.has_payload;
3543 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3544
03b82a30 3545 events->interrupt.injected =
04140b41 3546 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3547 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3548 events->interrupt.soft = 0;
37ccdcbe 3549 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3550
3551 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3552 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3553 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3554 events->nmi.pad = 0;
3cfc3092 3555
66450a21 3556 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3557
f077825a
PB		 3558 events->smi.smm = is_smm(vcpu);
3559 events->smi.pending = vcpu->arch.smi_pending;
3560 events->smi.smm_inside_nmi =
3561 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3562 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3563
dab4b911 3564 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3565 | KVM_VCPUEVENT_VALID_SHADOW
3566 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3567 if (vcpu->kvm->arch.exception_payload_enabled)
3568 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3569
97e69aa6 3570 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3571}
3572
c5833c7a 3573static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3574
3cfc3092
JK		 3575static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3576 struct kvm_vcpu_events *events)
3577{
dab4b911 3578 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3579 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3580 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3581 | KVM_VCPUEVENT_VALID_SMM
3582 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3583 return -EINVAL;
3584
59073aaf
JM		 3585 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3586 if (!vcpu->kvm->arch.exception_payload_enabled)
3587 return -EINVAL;
3588 if (events->exception.pending)
3589 events->exception.injected = 0;
3590 else
3591 events->exception_has_payload = 0;
3592 } else {
3593 events->exception.pending = 0;
3594 events->exception_has_payload = 0;
3595 }
3596
3597 if ((events->exception.injected || events->exception.pending) &&
3598 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3599 return -EINVAL;
3600
28bf2888
DH		 3601 /* INITs are latched while in SMM */
3602 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3603 (events->smi.smm || events->smi.pending) &&
3604 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3605 return -EINVAL;
3606
7460fb4a 3607 process_nmi(vcpu);
59073aaf
JM		 3608 vcpu->arch.exception.injected = events->exception.injected;
3609 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3610 vcpu->arch.exception.nr = events->exception.nr;
3611 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3612 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3613 vcpu->arch.exception.has_payload = events->exception_has_payload;
3614 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3615
04140b41 3616 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3617 vcpu->arch.interrupt.nr = events->interrupt.nr;
3618 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3619 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3620 kvm_x86_ops->set_interrupt_shadow(vcpu,
3621 events->interrupt.shadow);
3cfc3092
JK		 3622
3623 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3624 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3625 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3626 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3627
66450a21 3628 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3629 lapic_in_kernel(vcpu))
66450a21 3630 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3631
f077825a 3632 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3633 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3634 if (events->smi.smm)
3635 vcpu->arch.hflags |= HF_SMM_MASK;
3636 else
3637 vcpu->arch.hflags &= ~HF_SMM_MASK;
3638 kvm_smm_changed(vcpu);
3639 }
6ef4e07e 3640
f077825a 3641 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3642
3643 if (events->smi.smm) {
3644 if (events->smi.smm_inside_nmi)
3645 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3646 else
f4ef1910
WL		 3647 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3648 if (lapic_in_kernel(vcpu)) {
3649 if (events->smi.latched_init)
3650 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3651 else
3652 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3653 }
f077825a
PB		 3654 }
3655 }
3656
3842d135
AK		 3657 kvm_make_request(KVM_REQ_EVENT, vcpu);
3658
3cfc3092
JK		 3659 return 0;
3660}
3661
a1efbe77
JK		 3662static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3663 struct kvm_debugregs *dbgregs)
3664{
73aaf249
JK		 3665 unsigned long val;
3666
a1efbe77 3667 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3668 kvm_get_dr(vcpu, 6, &val);
73aaf249 3669 dbgregs->dr6 = val;
a1efbe77
JK		 3670 dbgregs->dr7 = vcpu->arch.dr7;
3671 dbgregs->flags = 0;
97e69aa6 3672 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3673}
3674
3675static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3676 struct kvm_debugregs *dbgregs)
3677{
3678 if (dbgregs->flags)
3679 return -EINVAL;
3680
d14bdb55
PB		 3681 if (dbgregs->dr6 & ~0xffffffffull)
3682 return -EINVAL;
3683 if (dbgregs->dr7 & ~0xffffffffull)
3684 return -EINVAL;
3685
a1efbe77 3686 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3687 kvm_update_dr0123(vcpu);
a1efbe77 3688 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3689 kvm_update_dr6(vcpu);
a1efbe77 3690 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3691 kvm_update_dr7(vcpu);
a1efbe77 3692
a1efbe77
JK		 3693 return 0;
3694}
3695
df1daba7
PB		 3696#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3697
3698static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3699{
b666a4b6 3700 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3701 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3702 u64 valid;
3703
3704 /*
3705 * Copy legacy XSAVE area, to avoid complications with CPUID
3706 * leaves 0 and 1 in the loop below.
3707 */
3708 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3709
3710 /* Set XSTATE_BV */
00c87e9a 3711 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3712 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3713
3714 /*
3715 * Copy each region from the possibly compacted offset to the
3716 * non-compacted offset.
3717 */
d91cab78 3718 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3719 while (valid) {
3720 u64 feature = valid & -valid;
3721 int index = fls64(feature) - 1;
3722 void *src = get_xsave_addr(xsave, feature);
3723
3724 if (src) {
3725 u32 size, offset, ecx, edx;
3726 cpuid_count(XSTATE_CPUID, index,
3727 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3728 if (feature == XFEATURE_MASK_PKRU)
3729 memcpy(dest + offset, &vcpu->arch.pkru,
3730 sizeof(vcpu->arch.pkru));
3731 else
3732 memcpy(dest + offset, src, size);
3733
df1daba7
PB		 3734 }
3735
3736 valid -= feature;
3737 }
3738}
3739
3740static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3741{
b666a4b6 3742 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3743 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3744 u64 valid;
3745
3746 /*
3747 * Copy legacy XSAVE area, to avoid complications with CPUID
3748 * leaves 0 and 1 in the loop below.
3749 */
3750 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3751
3752 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3753 xsave->header.xfeatures = xstate_bv;
782511b0 3754 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3755 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3756
3757 /*
3758 * Copy each region from the non-compacted offset to the
3759 * possibly compacted offset.
3760 */
d91cab78 3761 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3762 while (valid) {
3763 u64 feature = valid & -valid;
3764 int index = fls64(feature) - 1;
3765 void *dest = get_xsave_addr(xsave, feature);
3766
3767 if (dest) {
3768 u32 size, offset, ecx, edx;
3769 cpuid_count(XSTATE_CPUID, index,
3770 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3771 if (feature == XFEATURE_MASK_PKRU)
3772 memcpy(&vcpu->arch.pkru, src + offset,
3773 sizeof(vcpu->arch.pkru));
3774 else
3775 memcpy(dest, src + offset, size);
ee4100da 3776 }
df1daba7
PB		 3777
3778 valid -= feature;
3779 }
3780}
3781
2d5b5a66
SY		 3782static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3783 struct kvm_xsave *guest_xsave)
3784{
d366bf7e 3785 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3786 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3787 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3788 } else {
2d5b5a66 3789 memcpy(guest_xsave->region,
b666a4b6 3790 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3791 sizeof(struct fxregs_state));
2d5b5a66 3792 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3793 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3794 }
3795}
3796
a575813b
WL		 3797#define XSAVE_MXCSR_OFFSET 24
3798
2d5b5a66
SY		 3799static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3800 struct kvm_xsave *guest_xsave)
3801{
3802 u64 xstate_bv =
3803 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3804 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3805
d366bf7e 3806 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3807 /*
3808 * Here we allow setting states that are not present in
3809 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3810 * with old userspace.
3811 */
a575813b
WL		 3812 if (xstate_bv & ~kvm_supported_xcr0() ||
3813 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3814 return -EINVAL;
df1daba7 3815 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3816 } else {
a575813b
WL		 3817 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3818 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3819 return -EINVAL;
b666a4b6 3820 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3821 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3822 }
3823 return 0;
3824}
3825
3826static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3827 struct kvm_xcrs *guest_xcrs)
3828{
d366bf7e 3829 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3830 guest_xcrs->nr_xcrs = 0;
3831 return;
3832 }
3833
3834 guest_xcrs->nr_xcrs = 1;
3835 guest_xcrs->flags = 0;
3836 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3837 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3838}
3839
3840static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3841 struct kvm_xcrs *guest_xcrs)
3842{
3843 int i, r = 0;
3844
d366bf7e 3845 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3846 return -EINVAL;
3847
3848 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3849 return -EINVAL;
3850
3851 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3852 /* Only support XCR0 currently */
c67a04cb 3853 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3854 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3855 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3856 break;
3857 }
3858 if (r)
3859 r = -EINVAL;
3860 return r;
3861}
3862
1c0b28c2
EM		 3863/*
3864 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3865 * stopped by the hypervisor. This function will be called from the host only.
3866 * EINVAL is returned when the host attempts to set the flag for a guest that
3867 * does not support pv clocks.
3868 */
3869static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3870{
0b79459b 3871 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3872 return -EINVAL;
51d59c6b 3873 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3874 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3875 return 0;
3876}
3877
5c919412
AS		 3878static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3879 struct kvm_enable_cap *cap)
3880{
57b119da
VK		 3881 int r;
3882 uint16_t vmcs_version;
3883 void __user *user_ptr;
3884
5c919412
AS		 3885 if (cap->flags)
3886 return -EINVAL;
3887
3888 switch (cap->cap) {
efc479e6
RK		 3889 case KVM_CAP_HYPERV_SYNIC2:
3890 if (cap->args[0])
3891 return -EINVAL;
b2869f28
GS		 3892 /* fall through */
3893
5c919412 3894 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3895 if (!irqchip_in_kernel(vcpu->kvm))
3896 return -EINVAL;
efc479e6
RK		 3897 return kvm_hv_activate_synic(vcpu, cap->cap ==
3898 KVM_CAP_HYPERV_SYNIC2);
57b119da 3899 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 3900 if (!kvm_x86_ops->nested_enable_evmcs)
3901 return -ENOTTY;
57b119da
VK		 3902 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3903 if (!r) {
3904 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3905 if (copy_to_user(user_ptr, &vmcs_version,
3906 sizeof(vmcs_version)))
3907 r = -EFAULT;
3908 }
3909 return r;
3910
5c919412
AS		 3911 default:
3912 return -EINVAL;
3913 }
3914}
3915
313a3dc7
CO		 3916long kvm_arch_vcpu_ioctl(struct file *filp,
3917 unsigned int ioctl, unsigned long arg)
3918{
3919 struct kvm_vcpu *vcpu = filp->private_data;
3920 void __user *argp = (void __user *)arg;
3921 int r;
d1ac91d8
AK		 3922 union {
3923 struct kvm_lapic_state *lapic;
3924 struct kvm_xsave *xsave;
3925 struct kvm_xcrs *xcrs;
3926 void *buffer;
3927 } u;
3928
9b062471
CD		 3929 vcpu_load(vcpu);
3930
d1ac91d8 3931 u.buffer = NULL;
313a3dc7
CO		 3932 switch (ioctl) {
3933 case KVM_GET_LAPIC: {
2204ae3c 3934 r = -EINVAL;
bce87cce 3935 if (!lapic_in_kernel(vcpu))
2204ae3c 3936 goto out;
254272ce
BG		 3937 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3938 GFP_KERNEL_ACCOUNT);
313a3dc7 3939
b772ff36 3940 r = -ENOMEM;
d1ac91d8 3941 if (!u.lapic)
b772ff36 3942 goto out;
d1ac91d8 3943 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3944 if (r)
3945 goto out;
3946 r = -EFAULT;
d1ac91d8 3947 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3948 goto out;
3949 r = 0;
3950 break;
3951 }
3952 case KVM_SET_LAPIC: {
2204ae3c 3953 r = -EINVAL;
bce87cce 3954 if (!lapic_in_kernel(vcpu))
2204ae3c 3955 goto out;
ff5c2c03 3956 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3957 if (IS_ERR(u.lapic)) {
3958 r = PTR_ERR(u.lapic);
3959 goto out_nofree;
3960 }
ff5c2c03 3961
d1ac91d8 3962 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3963 break;
3964 }
f77bc6a4
ZX		 3965 case KVM_INTERRUPT: {
3966 struct kvm_interrupt irq;
3967
3968 r = -EFAULT;
0e96f31e 3969 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 3970 goto out;
3971 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3972 break;
3973 }
c4abb7c9
JK		 3974 case KVM_NMI: {
3975 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3976 break;
3977 }
f077825a
PB		 3978 case KVM_SMI: {
3979 r = kvm_vcpu_ioctl_smi(vcpu);
3980 break;
3981 }
313a3dc7
CO		 3982 case KVM_SET_CPUID: {
3983 struct kvm_cpuid __user *cpuid_arg = argp;
3984 struct kvm_cpuid cpuid;
3985
3986 r = -EFAULT;
0e96f31e 3987 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 3988 goto out;
3989 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3990 break;
3991 }
07716717
DK		 3992 case KVM_SET_CPUID2: {
3993 struct kvm_cpuid2 __user *cpuid_arg = argp;
3994 struct kvm_cpuid2 cpuid;
3995
3996 r = -EFAULT;
0e96f31e 3997 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 3998 goto out;
3999 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 4000 cpuid_arg->entries);
07716717
DK		 4001 break;
4002 }
4003 case KVM_GET_CPUID2: {
4004 struct kvm_cpuid2 __user *cpuid_arg = argp;
4005 struct kvm_cpuid2 cpuid;
4006
4007 r = -EFAULT;
0e96f31e 4008 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4009 goto out;
4010 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 4011 cpuid_arg->entries);
07716717
DK		 4012 if (r)
4013 goto out;
4014 r = -EFAULT;
0e96f31e 4015 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 4016 goto out;
4017 r = 0;
4018 break;
4019 }
801e459a
TL		 4020 case KVM_GET_MSRS: {
4021 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 4022 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 4023 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4024 break;
801e459a
TL		 4025 }
4026 case KVM_SET_MSRS: {
4027 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 4028 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 4029 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4030 break;
801e459a 4031 }
b209749f
AK		 4032 case KVM_TPR_ACCESS_REPORTING: {
4033 struct kvm_tpr_access_ctl tac;
4034
4035 r = -EFAULT;
0e96f31e 4036 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 4037 goto out;
4038 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4039 if (r)
4040 goto out;
4041 r = -EFAULT;
0e96f31e 4042 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4043 goto out;
4044 r = 0;
4045 break;
4046 };
b93463aa
AK		 4047 case KVM_SET_VAPIC_ADDR: {
4048 struct kvm_vapic_addr va;
7301d6ab 4049 int idx;
b93463aa
AK		 4050
4051 r = -EINVAL;
35754c98 4052 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4053 goto out;
4054 r = -EFAULT;
0e96f31e 4055 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4056 goto out;
7301d6ab 4057 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4058 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4059 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4060 break;
4061 }
890ca9ae
HY		 4062 case KVM_X86_SETUP_MCE: {
4063 u64 mcg_cap;
4064
4065 r = -EFAULT;
0e96f31e 4066 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4067 goto out;
4068 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4069 break;
4070 }
4071 case KVM_X86_SET_MCE: {
4072 struct kvm_x86_mce mce;
4073
4074 r = -EFAULT;
0e96f31e 4075 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4076 goto out;
4077 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4078 break;
4079 }
3cfc3092
JK		 4080 case KVM_GET_VCPU_EVENTS: {
4081 struct kvm_vcpu_events events;
4082
4083 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4084
4085 r = -EFAULT;
4086 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4087 break;
4088 r = 0;
4089 break;
4090 }
4091 case KVM_SET_VCPU_EVENTS: {
4092 struct kvm_vcpu_events events;
4093
4094 r = -EFAULT;
4095 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4096 break;
4097
4098 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4099 break;
4100 }
a1efbe77
JK		 4101 case KVM_GET_DEBUGREGS: {
4102 struct kvm_debugregs dbgregs;
4103
4104 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4105
4106 r = -EFAULT;
4107 if (copy_to_user(argp, &dbgregs,
4108 sizeof(struct kvm_debugregs)))
4109 break;
4110 r = 0;
4111 break;
4112 }
4113 case KVM_SET_DEBUGREGS: {
4114 struct kvm_debugregs dbgregs;
4115
4116 r = -EFAULT;
4117 if (copy_from_user(&dbgregs, argp,
4118 sizeof(struct kvm_debugregs)))
4119 break;
4120
4121 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4122 break;
4123 }
2d5b5a66 4124 case KVM_GET_XSAVE: {
254272ce 4125 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4126 r = -ENOMEM;
d1ac91d8 4127 if (!u.xsave)
2d5b5a66
SY		 4128 break;
4129
d1ac91d8 4130 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4131
4132 r = -EFAULT;
d1ac91d8 4133 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4134 break;
4135 r = 0;
4136 break;
4137 }
4138 case KVM_SET_XSAVE: {
ff5c2c03 4139 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4140 if (IS_ERR(u.xsave)) {
4141 r = PTR_ERR(u.xsave);
4142 goto out_nofree;
4143 }
2d5b5a66 4144
d1ac91d8 4145 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4146 break;
4147 }
4148 case KVM_GET_XCRS: {
254272ce 4149 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4150 r = -ENOMEM;
d1ac91d8 4151 if (!u.xcrs)
2d5b5a66
SY		 4152 break;
4153
d1ac91d8 4154 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4155
4156 r = -EFAULT;
d1ac91d8 4157 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4158 sizeof(struct kvm_xcrs)))
4159 break;
4160 r = 0;
4161 break;
4162 }
4163 case KVM_SET_XCRS: {
ff5c2c03 4164 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4165 if (IS_ERR(u.xcrs)) {
4166 r = PTR_ERR(u.xcrs);
4167 goto out_nofree;
4168 }
2d5b5a66 4169
d1ac91d8 4170 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4171 break;
4172 }
92a1f12d
JR		 4173 case KVM_SET_TSC_KHZ: {
4174 u32 user_tsc_khz;
4175
4176 r = -EINVAL;
92a1f12d
JR		 4177 user_tsc_khz = (u32)arg;
4178
4179 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4180 goto out;
4181
cc578287
ZA		 4182 if (user_tsc_khz == 0)
4183 user_tsc_khz = tsc_khz;
4184
381d585c
HZ		 4185 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4186 r = 0;
92a1f12d 4187
92a1f12d
JR		 4188 goto out;
4189 }
4190 case KVM_GET_TSC_KHZ: {
cc578287 4191 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4192 goto out;
4193 }
1c0b28c2
EM		 4194 case KVM_KVMCLOCK_CTRL: {
4195 r = kvm_set_guest_paused(vcpu);
4196 goto out;
4197 }
5c919412
AS		 4198 case KVM_ENABLE_CAP: {
4199 struct kvm_enable_cap cap;
4200
4201 r = -EFAULT;
4202 if (copy_from_user(&cap, argp, sizeof(cap)))
4203 goto out;
4204 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4205 break;
4206 }
8fcc4b59
JM		 4207 case KVM_GET_NESTED_STATE: {
4208 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4209 u32 user_data_size;
4210
4211 r = -EINVAL;
4212 if (!kvm_x86_ops->get_nested_state)
4213 break;
4214
4215 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4216 r = -EFAULT;
8fcc4b59 4217 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4218 break;
8fcc4b59
JM		 4219
4220 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4221 user_data_size);
4222 if (r < 0)
26b471c7 4223 break;
8fcc4b59
JM		 4224
4225 if (r > user_data_size) {
4226 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4227 r = -EFAULT;
4228 else
4229 r = -E2BIG;
4230 break;
8fcc4b59 4231 }
26b471c7 4232
8fcc4b59
JM		 4233 r = 0;
4234 break;
4235 }
4236 case KVM_SET_NESTED_STATE: {
4237 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4238 struct kvm_nested_state kvm_state;
4239
4240 r = -EINVAL;
4241 if (!kvm_x86_ops->set_nested_state)
4242 break;
4243
26b471c7 4244 r = -EFAULT;
8fcc4b59 4245 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4246 break;
8fcc4b59 4247
26b471c7 4248 r = -EINVAL;
8fcc4b59 4249 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4250 break;
8fcc4b59
JM		 4251
4252 if (kvm_state.flags &
8cab6507
VK		 4253 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4254 | KVM_STATE_NESTED_EVMCS))
26b471c7 4255 break;
8fcc4b59
JM		 4256
4257 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4258 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4259 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4260 break;
8fcc4b59
JM		 4261
4262 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4263 break;
4264 }
2bc39970
VK		 4265 case KVM_GET_SUPPORTED_HV_CPUID: {
4266 struct kvm_cpuid2 __user *cpuid_arg = argp;
4267 struct kvm_cpuid2 cpuid;
4268
4269 r = -EFAULT;
4270 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4271 goto out;
4272
4273 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4274 cpuid_arg->entries);
4275 if (r)
4276 goto out;
4277
4278 r = -EFAULT;
4279 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4280 goto out;
4281 r = 0;
4282 break;
4283 }
313a3dc7
CO		 4284 default:
4285 r = -EINVAL;
4286 }
4287out:
d1ac91d8 4288 kfree(u.buffer);
9b062471
CD		 4289out_nofree:
4290 vcpu_put(vcpu);
313a3dc7
CO		 4291 return r;
4292}
4293
1499fa80 4294vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4295{
4296 return VM_FAULT_SIGBUS;
4297}
4298
1fe779f8
CO		 4299static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4300{
4301 int ret;
4302
4303 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4304 return -EINVAL;
1fe779f8
CO		 4305 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4306 return ret;
4307}
4308
b927a3ce
SY		 4309static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4310 u64 ident_addr)
4311{
2ac52ab8 4312 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4313}
4314
1fe779f8 4315static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4316 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4317{
4318 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4319 return -EINVAL;
4320
79fac95e 4321 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4322
4323 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4324 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4325
79fac95e 4326 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4327 return 0;
4328}
4329
bc8a3d89 4330static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4331{
39de71ec 4332 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4333}
4334
1fe779f8
CO		 4335static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4336{
90bca052 4337 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4338 int r;
4339
4340 r = 0;
4341 switch (chip->chip_id) {
4342 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4343 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4344 sizeof(struct kvm_pic_state));
4345 break;
4346 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4347 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4348 sizeof(struct kvm_pic_state));
4349 break;
4350 case KVM_IRQCHIP_IOAPIC:
33392b49 4351 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4352 break;
4353 default:
4354 r = -EINVAL;
4355 break;
4356 }
4357 return r;
4358}
4359
4360static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4361{
90bca052 4362 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4363 int r;
4364
4365 r = 0;
4366 switch (chip->chip_id) {
4367 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4368 spin_lock(&pic->lock);
4369 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4370 sizeof(struct kvm_pic_state));
90bca052 4371 spin_unlock(&pic->lock);
1fe779f8
CO		 4372 break;
4373 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4374 spin_lock(&pic->lock);
4375 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4376 sizeof(struct kvm_pic_state));
90bca052 4377 spin_unlock(&pic->lock);
1fe779f8
CO		 4378 break;
4379 case KVM_IRQCHIP_IOAPIC:
33392b49 4380 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4381 break;
4382 default:
4383 r = -EINVAL;
4384 break;
4385 }
90bca052 4386 kvm_pic_update_irq(pic);
1fe779f8
CO		 4387 return r;
4388}
4389
e0f63cb9
SY		 4390static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4391{
34f3941c
RK		 4392 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4393
4394 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4395
4396 mutex_lock(&kps->lock);
4397 memcpy(ps, &kps->channels, sizeof(*ps));
4398 mutex_unlock(&kps->lock);
2da29bcc 4399 return 0;
e0f63cb9
SY		 4400}
4401
4402static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4403{
0185604c 4404 int i;
09edea72
RK		 4405 struct kvm_pit *pit = kvm->arch.vpit;
4406
4407 mutex_lock(&pit->pit_state.lock);
34f3941c 4408 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4409 for (i = 0; i < 3; i++)
09edea72
RK		 4410 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4411 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4412 return 0;
e9f42757
BK		 4413}
4414
4415static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4416{
e9f42757
BK		 4417 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4418 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4419 sizeof(ps->channels));
4420 ps->flags = kvm->arch.vpit->pit_state.flags;
4421 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4422 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4423 return 0;
e9f42757
BK		 4424}
4425
4426static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4427{
2da29bcc 4428 int start = 0;
0185604c 4429 int i;
e9f42757 4430 u32 prev_legacy, cur_legacy;
09edea72
RK		 4431 struct kvm_pit *pit = kvm->arch.vpit;
4432
4433 mutex_lock(&pit->pit_state.lock);
4434 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4435 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4436 if (!prev_legacy && cur_legacy)
4437 start = 1;
09edea72
RK		 4438 memcpy(&pit->pit_state.channels, &ps->channels,
4439 sizeof(pit->pit_state.channels));
4440 pit->pit_state.flags = ps->flags;
0185604c 4441 for (i = 0; i < 3; i++)
09edea72 4442 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4443 start && i == 0);
09edea72 4444 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4445 return 0;
e0f63cb9
SY		 4446}
4447
52d939a0
MT		 4448static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4449 struct kvm_reinject_control *control)
4450{
71474e2f
RK		 4451 struct kvm_pit *pit = kvm->arch.vpit;
4452
4453 if (!pit)
52d939a0 4454 return -ENXIO;
b39c90b6 4455
71474e2f
RK		 4456 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4457 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4458 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4459 */
4460 mutex_lock(&pit->pit_state.lock);
4461 kvm_pit_set_reinject(pit, control->pit_reinject);
4462 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4463
52d939a0
MT		 4464 return 0;
4465}
4466
95d4c16c 4467/**
60c34612
TY		 4468 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4469 * @kvm: kvm instance
4470 * @log: slot id and address to which we copy the log
95d4c16c 4471 *
e108ff2f
PB		 4472 * Steps 1-4 below provide general overview of dirty page logging. See
4473 * kvm_get_dirty_log_protect() function description for additional details.
4474 *
4475 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4476 * always flush the TLB (step 4) even if previous step failed and the dirty
4477 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4478 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4479 * writes will be marked dirty for next log read.
95d4c16c 4480 *
60c34612
TY		 4481 * 1. Take a snapshot of the bit and clear it if needed.
4482 * 2. Write protect the corresponding page.
e108ff2f
PB		 4483 * 3. Copy the snapshot to the userspace.
4484 * 4. Flush TLB's if needed.
5bb064dc 4485 */
60c34612 4486int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4487{
8fe65a82 4488 bool flush = false;
e108ff2f 4489 int r;
5bb064dc 4490
79fac95e 4491 mutex_lock(&kvm->slots_lock);
5bb064dc 4492
88178fd4
KH		 4493 /*
4494 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4495 */
4496 if (kvm_x86_ops->flush_log_dirty)
4497 kvm_x86_ops->flush_log_dirty(kvm);
4498
8fe65a82 4499 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4500
4501 /*
4502 * All the TLBs can be flushed out of mmu lock, see the comments in
4503 * kvm_mmu_slot_remove_write_access().
4504 */
e108ff2f 4505 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4506 if (flush)
2a31b9db
PB		 4507 kvm_flush_remote_tlbs(kvm);
4508
4509 mutex_unlock(&kvm->slots_lock);
4510 return r;
4511}
4512
4513int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4514{
4515 bool flush = false;
4516 int r;
4517
4518 mutex_lock(&kvm->slots_lock);
4519
4520 /*
4521 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4522 */
4523 if (kvm_x86_ops->flush_log_dirty)
4524 kvm_x86_ops->flush_log_dirty(kvm);
4525
4526 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4527
4528 /*
4529 * All the TLBs can be flushed out of mmu lock, see the comments in
4530 * kvm_mmu_slot_remove_write_access().
4531 */
4532 lockdep_assert_held(&kvm->slots_lock);
4533 if (flush)
198c74f4
XG		 4534 kvm_flush_remote_tlbs(kvm);
4535
79fac95e 4536 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4537 return r;
4538}
4539
aa2fbe6d
YZ		 4540int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4541 bool line_status)
23d43cf9
CD		 4542{
4543 if (!irqchip_in_kernel(kvm))
4544 return -ENXIO;
4545
4546 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4547 irq_event->irq, irq_event->level,
4548 line_status);
23d43cf9
CD		 4549 return 0;
4550}
4551
e5d83c74
PB		 4552int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4553 struct kvm_enable_cap *cap)
90de4a18
NA		 4554{
4555 int r;
4556
4557 if (cap->flags)
4558 return -EINVAL;
4559
4560 switch (cap->cap) {
4561 case KVM_CAP_DISABLE_QUIRKS:
4562 kvm->arch.disabled_quirks = cap->args[0];
4563 r = 0;
4564 break;
49df6397
SR		 4565 case KVM_CAP_SPLIT_IRQCHIP: {
4566 mutex_lock(&kvm->lock);
b053b2ae
SR		 4567 r = -EINVAL;
4568 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4569 goto split_irqchip_unlock;
49df6397
SR		 4570 r = -EEXIST;
4571 if (irqchip_in_kernel(kvm))
4572 goto split_irqchip_unlock;
557abc40 4573 if (kvm->created_vcpus)
49df6397
SR		 4574 goto split_irqchip_unlock;
4575 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4576 if (r)
49df6397
SR		 4577 goto split_irqchip_unlock;
4578 /* Pairs with irqchip_in_kernel. */
4579 smp_wmb();
49776faf 4580 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4581 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4582 r = 0;
4583split_irqchip_unlock:
4584 mutex_unlock(&kvm->lock);
4585 break;
4586 }
37131313
RK		 4587 case KVM_CAP_X2APIC_API:
4588 r = -EINVAL;
4589 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4590 break;
4591
4592 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4593 kvm->arch.x2apic_format = true;
c519265f
RK		 4594 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4595 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4596
4597 r = 0;
4598 break;
4d5422ce
WL		 4599 case KVM_CAP_X86_DISABLE_EXITS:
4600 r = -EINVAL;
4601 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4602 break;
4603
4604 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4605 kvm_can_mwait_in_guest())
4606 kvm->arch.mwait_in_guest = true;
766d3571 4607 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4608 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4609 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4610 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4611 r = 0;
4612 break;
6fbbde9a
DS		 4613 case KVM_CAP_MSR_PLATFORM_INFO:
4614 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4615 r = 0;
c4f55198
JM		 4616 break;
4617 case KVM_CAP_EXCEPTION_PAYLOAD:
4618 kvm->arch.exception_payload_enabled = cap->args[0];
4619 r = 0;
6fbbde9a 4620 break;
90de4a18
NA		 4621 default:
4622 r = -EINVAL;
4623 break;
4624 }
4625 return r;
4626}
4627
1fe779f8
CO		 4628long kvm_arch_vm_ioctl(struct file *filp,
4629 unsigned int ioctl, unsigned long arg)
4630{
4631 struct kvm *kvm = filp->private_data;
4632 void __user *argp = (void __user *)arg;
367e1319 4633 int r = -ENOTTY;
f0d66275
DH		 4634 /*
4635 * This union makes it completely explicit to gcc-3.x
4636 * that these two variables' stack usage should be
4637 * combined, not added together.
4638 */
4639 union {
4640 struct kvm_pit_state ps;
e9f42757 4641 struct kvm_pit_state2 ps2;
c5ff41ce 4642 struct kvm_pit_config pit_config;
f0d66275 4643 } u;
1fe779f8
CO		 4644
4645 switch (ioctl) {
4646 case KVM_SET_TSS_ADDR:
4647 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4648 break;
b927a3ce
SY		 4649 case KVM_SET_IDENTITY_MAP_ADDR: {
4650 u64 ident_addr;
4651
1af1ac91
DH		 4652 mutex_lock(&kvm->lock);
4653 r = -EINVAL;
4654 if (kvm->created_vcpus)
4655 goto set_identity_unlock;
b927a3ce 4656 r = -EFAULT;
0e96f31e 4657 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4658 goto set_identity_unlock;
b927a3ce 4659 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4660set_identity_unlock:
4661 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4662 break;
4663 }
1fe779f8
CO		 4664 case KVM_SET_NR_MMU_PAGES:
4665 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4666 break;
4667 case KVM_GET_NR_MMU_PAGES:
4668 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4669 break;
3ddea128 4670 case KVM_CREATE_IRQCHIP: {
3ddea128 4671 mutex_lock(&kvm->lock);
09941366 4672
3ddea128 4673 r = -EEXIST;
35e6eaa3 4674 if (irqchip_in_kernel(kvm))
3ddea128 4675 goto create_irqchip_unlock;
09941366 4676
3e515705 4677 r = -EINVAL;
557abc40 4678 if (kvm->created_vcpus)
3e515705 4679 goto create_irqchip_unlock;
09941366
RK		 4680
4681 r = kvm_pic_init(kvm);
4682 if (r)
3ddea128 4683 goto create_irqchip_unlock;
09941366
RK		 4684
4685 r = kvm_ioapic_init(kvm);
4686 if (r) {
09941366 4687 kvm_pic_destroy(kvm);
3ddea128 4688 goto create_irqchip_unlock;
09941366
RK		 4689 }
4690
399ec807
AK		 4691 r = kvm_setup_default_irq_routing(kvm);
4692 if (r) {
72bb2fcd 4693 kvm_ioapic_destroy(kvm);
09941366 4694 kvm_pic_destroy(kvm);
71ba994c 4695 goto create_irqchip_unlock;
399ec807 4696 }
49776faf 4697 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4698 smp_wmb();
49776faf 4699 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4700 create_irqchip_unlock:
4701 mutex_unlock(&kvm->lock);
1fe779f8 4702 break;
3ddea128 4703 }
7837699f 4704 case KVM_CREATE_PIT:
c5ff41ce
JK		 4705 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4706 goto create_pit;
4707 case KVM_CREATE_PIT2:
4708 r = -EFAULT;
4709 if (copy_from_user(&u.pit_config, argp,
4710 sizeof(struct kvm_pit_config)))
4711 goto out;
4712 create_pit:
250715a6 4713 mutex_lock(&kvm->lock);
269e05e4
AK		 4714 r = -EEXIST;
4715 if (kvm->arch.vpit)
4716 goto create_pit_unlock;
7837699f 4717 r = -ENOMEM;
c5ff41ce 4718 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4719 if (kvm->arch.vpit)
4720 r = 0;
269e05e4 4721 create_pit_unlock:
250715a6 4722 mutex_unlock(&kvm->lock);
7837699f 4723 break;
1fe779f8
CO		 4724 case KVM_GET_IRQCHIP: {
4725 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4726 struct kvm_irqchip *chip;
1fe779f8 4727
ff5c2c03
SL		 4728 chip = memdup_user(argp, sizeof(*chip));
4729 if (IS_ERR(chip)) {
4730 r = PTR_ERR(chip);
1fe779f8 4731 goto out;
ff5c2c03
SL		 4732 }
4733
1fe779f8 4734 r = -ENXIO;
826da321 4735 if (!irqchip_kernel(kvm))
f0d66275
DH		 4736 goto get_irqchip_out;
4737 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4738 if (r)
f0d66275 4739 goto get_irqchip_out;
1fe779f8 4740 r = -EFAULT;
0e96f31e 4741 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4742 goto get_irqchip_out;
1fe779f8 4743 r = 0;
f0d66275
DH		 4744 get_irqchip_out:
4745 kfree(chip);
1fe779f8
CO		 4746 break;
4747 }
4748 case KVM_SET_IRQCHIP: {
4749 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4750 struct kvm_irqchip *chip;
1fe779f8 4751
ff5c2c03
SL		 4752 chip = memdup_user(argp, sizeof(*chip));
4753 if (IS_ERR(chip)) {
4754 r = PTR_ERR(chip);
1fe779f8 4755 goto out;
ff5c2c03
SL		 4756 }
4757
1fe779f8 4758 r = -ENXIO;
826da321 4759 if (!irqchip_kernel(kvm))
f0d66275
DH		 4760 goto set_irqchip_out;
4761 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4762 if (r)
f0d66275 4763 goto set_irqchip_out;
1fe779f8 4764 r = 0;
f0d66275
DH		 4765 set_irqchip_out:
4766 kfree(chip);
1fe779f8
CO		 4767 break;
4768 }
e0f63cb9 4769 case KVM_GET_PIT: {
e0f63cb9 4770 r = -EFAULT;
f0d66275 4771 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4772 goto out;
4773 r = -ENXIO;
4774 if (!kvm->arch.vpit)
4775 goto out;
f0d66275 4776 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4777 if (r)
4778 goto out;
4779 r = -EFAULT;
f0d66275 4780 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4781 goto out;
4782 r = 0;
4783 break;
4784 }
4785 case KVM_SET_PIT: {
e0f63cb9 4786 r = -EFAULT;
0e96f31e 4787 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4788 goto out;
4789 r = -ENXIO;
4790 if (!kvm->arch.vpit)
4791 goto out;
f0d66275 4792 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4793 break;
4794 }
e9f42757
BK		 4795 case KVM_GET_PIT2: {
4796 r = -ENXIO;
4797 if (!kvm->arch.vpit)
4798 goto out;
4799 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4800 if (r)
4801 goto out;
4802 r = -EFAULT;
4803 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4804 goto out;
4805 r = 0;
4806 break;
4807 }
4808 case KVM_SET_PIT2: {
4809 r = -EFAULT;
4810 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4811 goto out;
4812 r = -ENXIO;
4813 if (!kvm->arch.vpit)
4814 goto out;
4815 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4816 break;
4817 }
52d939a0
MT		 4818 case KVM_REINJECT_CONTROL: {
4819 struct kvm_reinject_control control;
4820 r = -EFAULT;
4821 if (copy_from_user(&control, argp, sizeof(control)))
4822 goto out;
4823 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4824 break;
4825 }
d71ba788
PB		 4826 case KVM_SET_BOOT_CPU_ID:
4827 r = 0;
4828 mutex_lock(&kvm->lock);
557abc40 4829 if (kvm->created_vcpus)
d71ba788
PB		 4830 r = -EBUSY;
4831 else
4832 kvm->arch.bsp_vcpu_id = arg;
4833 mutex_unlock(&kvm->lock);
4834 break;
ffde22ac 4835 case KVM_XEN_HVM_CONFIG: {
51776043 4836 struct kvm_xen_hvm_config xhc;
ffde22ac 4837 r = -EFAULT;
51776043 4838 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4839 goto out;
4840 r = -EINVAL;
51776043 4841 if (xhc.flags)
ffde22ac 4842 goto out;
51776043 4843 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4844 r = 0;
4845 break;
4846 }
afbcf7ab 4847 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4848 struct kvm_clock_data user_ns;
4849 u64 now_ns;
afbcf7ab
GC		 4850
4851 r = -EFAULT;
4852 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4853 goto out;
4854
4855 r = -EINVAL;
4856 if (user_ns.flags)
4857 goto out;
4858
4859 r = 0;
0bc48bea
RK		 4860 /*
4861 * TODO: userspace has to take care of races with VCPU_RUN, so
4862 * kvm_gen_update_masterclock() can be cut down to locked
4863 * pvclock_update_vm_gtod_copy().
4864 */
4865 kvm_gen_update_masterclock(kvm);
e891a32e 4866 now_ns = get_kvmclock_ns(kvm);
108b249c 4867 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4868 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4869 break;
4870 }
4871 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4872 struct kvm_clock_data user_ns;
4873 u64 now_ns;
4874
e891a32e 4875 now_ns = get_kvmclock_ns(kvm);
108b249c 4876 user_ns.clock = now_ns;
e3fd9a93 4877 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4878 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4879
4880 r = -EFAULT;
4881 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4882 goto out;
4883 r = 0;
4884 break;
4885 }
5acc5c06
BS		 4886 case KVM_MEMORY_ENCRYPT_OP: {
4887 r = -ENOTTY;
4888 if (kvm_x86_ops->mem_enc_op)
4889 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4890 break;
4891 }
69eaedee
BS		 4892 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4893 struct kvm_enc_region region;
4894
4895 r = -EFAULT;
4896 if (copy_from_user(&region, argp, sizeof(region)))
4897 goto out;
4898
4899 r = -ENOTTY;
4900 if (kvm_x86_ops->mem_enc_reg_region)
4901 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4902 break;
4903 }
4904 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4905 struct kvm_enc_region region;
4906
4907 r = -EFAULT;
4908 if (copy_from_user(&region, argp, sizeof(region)))
4909 goto out;
4910
4911 r = -ENOTTY;
4912 if (kvm_x86_ops->mem_enc_unreg_region)
4913 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4914 break;
4915 }
faeb7833
RK		 4916 case KVM_HYPERV_EVENTFD: {
4917 struct kvm_hyperv_eventfd hvevfd;
4918
4919 r = -EFAULT;
4920 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4921 goto out;
4922 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4923 break;
4924 }
1fe779f8 4925 default:
ad6260da 4926 r = -ENOTTY;
1fe779f8
CO		 4927 }
4928out:
4929 return r;
4930}
4931
a16b043c 4932static void kvm_init_msr_list(void)
043405e1
CO		 4933{
4934 u32 dummy[2];
4935 unsigned i, j;
4936
62ef68bb 4937 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4938 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4939 continue;
93c4adc7
PB		 4940
4941 /*
4942 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4943 * to the guests in some cases.
93c4adc7
PB		 4944 */
4945 switch (msrs_to_save[i]) {
4946 case MSR_IA32_BNDCFGS:
503234b3 4947 if (!kvm_mpx_supported())
93c4adc7
PB		 4948 continue;
4949 break;
9dbe6cf9
PB		 4950 case MSR_TSC_AUX:
4951 if (!kvm_x86_ops->rdtscp_supported())
4952 continue;
4953 break;
bf8c55d8
CP		 4954 case MSR_IA32_RTIT_CTL:
4955 case MSR_IA32_RTIT_STATUS:
4956 if (!kvm_x86_ops->pt_supported())
4957 continue;
4958 break;
4959 case MSR_IA32_RTIT_CR3_MATCH:
4960 if (!kvm_x86_ops->pt_supported() ||
4961 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
4962 continue;
4963 break;
4964 case MSR_IA32_RTIT_OUTPUT_BASE:
4965 case MSR_IA32_RTIT_OUTPUT_MASK:
4966 if (!kvm_x86_ops->pt_supported() ||
4967 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
4968 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
4969 continue;
4970 break;
4971 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
4972 if (!kvm_x86_ops->pt_supported() ||
4973 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
4974 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
4975 continue;
4976 break;
4977 }
93c4adc7
PB		 4978 default:
4979 break;
4980 }
4981
043405e1
CO		 4982 if (j < i)
4983 msrs_to_save[j] = msrs_to_save[i];
4984 j++;
4985 }
4986 num_msrs_to_save = j;
62ef68bb
PB		 4987
4988 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4989 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4990 continue;
62ef68bb
PB		 4991
4992 if (j < i)
4993 emulated_msrs[j] = emulated_msrs[i];
4994 j++;
4995 }
4996 num_emulated_msrs = j;
801e459a
TL		 4997
4998 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4999 struct kvm_msr_entry msr;
5000
5001 msr.index = msr_based_features[i];
66421c1e 5002 if (kvm_get_msr_feature(&msr))
801e459a
TL		 5003 continue;
5004
5005 if (j < i)
5006 msr_based_features[j] = msr_based_features[i];
5007 j++;
5008 }
5009 num_msr_based_features = j;
043405e1
CO		 5010}
5011
bda9020e
MT		 5012static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5013 const void *v)
bbd9b64e 5014{
70252a10
AK		 5015 int handled = 0;
5016 int n;
5017
5018 do {
5019 n = min(len, 8);
bce87cce 5020 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5021 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5022 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 5023 break;
5024 handled += n;
5025 addr += n;
5026 len -= n;
5027 v += n;
5028 } while (len);
bbd9b64e 5029
70252a10 5030 return handled;
bbd9b64e
CO		 5031}
5032
bda9020e 5033static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 5034{
70252a10
AK		 5035 int handled = 0;
5036 int n;
5037
5038 do {
5039 n = min(len, 8);
bce87cce 5040 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5041 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5042 addr, n, v))
5043 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5044 break;
e39d200f 5045 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5046 handled += n;
5047 addr += n;
5048 len -= n;
5049 v += n;
5050 } while (len);
bbd9b64e 5051
70252a10 5052 return handled;
bbd9b64e
CO		 5053}
5054
2dafc6c2
GN		 5055static void kvm_set_segment(struct kvm_vcpu *vcpu,
5056 struct kvm_segment *var, int seg)
5057{
5058 kvm_x86_ops->set_segment(vcpu, var, seg);
5059}
5060
5061void kvm_get_segment(struct kvm_vcpu *vcpu,
5062 struct kvm_segment *var, int seg)
5063{
5064 kvm_x86_ops->get_segment(vcpu, var, seg);
5065}
5066
54987b7a
PB		 5067gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5068 struct x86_exception *exception)
02f59dc9
JR		 5069{
5070 gpa_t t_gpa;
02f59dc9
JR		 5071
5072 BUG_ON(!mmu_is_nested(vcpu));
5073
5074 /* NPT walks are always user-walks */
5075 access |= PFERR_USER_MASK;
44dd3ffa 5076 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5077
5078 return t_gpa;
5079}
5080
ab9ae313
AK		 5081gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5082 struct x86_exception *exception)
1871c602
GN		 5083{
5084 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5085 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5086}
5087
ab9ae313
AK		 5088 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5089 struct x86_exception *exception)
1871c602
GN		 5090{
5091 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5092 access |= PFERR_FETCH_MASK;
ab9ae313 5093 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5094}
5095
ab9ae313
AK		 5096gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5097 struct x86_exception *exception)
1871c602
GN		 5098{
5099 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5100 access |= PFERR_WRITE_MASK;
ab9ae313 5101 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5102}
5103
5104/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5105gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5106 struct x86_exception *exception)
1871c602 5107{
ab9ae313 5108 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5109}
5110
5111static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5112 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5113 struct x86_exception *exception)
bbd9b64e
CO		 5114{
5115 void *data = val;
10589a46 5116 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5117
5118 while (bytes) {
14dfe855 5119 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5120 exception);
bbd9b64e 5121 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5122 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5123 int ret;
5124
bcc55cba 5125 if (gpa == UNMAPPED_GVA)
ab9ae313 5126 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5127 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5128 offset, toread);
10589a46 5129 if (ret < 0) {
c3cd7ffa 5130 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5131 goto out;
5132 }
bbd9b64e 5133
77c2002e
IE		 5134 bytes -= toread;
5135 data += toread;
5136 addr += toread;
bbd9b64e 5137 }
10589a46 5138out:
10589a46 5139 return r;
bbd9b64e 5140}
77c2002e 5141
1871c602 5142/* used for instruction fetching */
0f65dd70
AK		 5143static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5144 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5145 struct x86_exception *exception)
1871c602 5146{
0f65dd70 5147 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5148 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5149 unsigned offset;
5150 int ret;
0f65dd70 5151
44583cba
PB		 5152 /* Inline kvm_read_guest_virt_helper for speed. */
5153 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5154 exception);
5155 if (unlikely(gpa == UNMAPPED_GVA))
5156 return X86EMUL_PROPAGATE_FAULT;
5157
5158 offset = addr & (PAGE_SIZE-1);
5159 if (WARN_ON(offset + bytes > PAGE_SIZE))
5160 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5161 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5162 offset, bytes);
44583cba
PB		 5163 if (unlikely(ret < 0))
5164 return X86EMUL_IO_NEEDED;
5165
5166 return X86EMUL_CONTINUE;
1871c602
GN		 5167}
5168
ce14e868 5169int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5170 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5171 struct x86_exception *exception)
1871c602
GN		 5172{
5173 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5174
353c0956
PB		 5175 /*
5176 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5177 * is returned, but our callers are not ready for that and they blindly
5178 * call kvm_inject_page_fault. Ensure that they at least do not leak
5179 * uninitialized kernel stack memory into cr2 and error code.
5180 */
5181 memset(exception, 0, sizeof(*exception));
1871c602 5182 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5183 exception);
1871c602 5184}
064aea77 5185EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5186
ce14e868
PB		 5187static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5188 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5189 struct x86_exception *exception, bool system)
1871c602 5190{
0f65dd70 5191 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5192 u32 access = 0;
5193
5194 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5195 access |= PFERR_USER_MASK;
5196
5197 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5198}
5199
7a036a6f
RK		 5200static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5201 unsigned long addr, void *val, unsigned int bytes)
5202{
5203 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5204 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5205
5206 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5207}
5208
ce14e868
PB		 5209static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5210 struct kvm_vcpu *vcpu, u32 access,
5211 struct x86_exception *exception)
77c2002e
IE		 5212{
5213 void *data = val;
5214 int r = X86EMUL_CONTINUE;
5215
5216 while (bytes) {
14dfe855 5217 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5218 access,
ab9ae313 5219 exception);
77c2002e
IE		 5220 unsigned offset = addr & (PAGE_SIZE-1);
5221 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5222 int ret;
5223
bcc55cba 5224 if (gpa == UNMAPPED_GVA)
ab9ae313 5225 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5226 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5227 if (ret < 0) {
c3cd7ffa 5228 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5229 goto out;
5230 }
5231
5232 bytes -= towrite;
5233 data += towrite;
5234 addr += towrite;
5235 }
5236out:
5237 return r;
5238}
ce14e868
PB		 5239
5240static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5241 unsigned int bytes, struct x86_exception *exception,
5242 bool system)
ce14e868
PB		 5243{
5244 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5245 u32 access = PFERR_WRITE_MASK;
5246
5247 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5248 access |= PFERR_USER_MASK;
ce14e868
PB		 5249
5250 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5251 access, exception);
ce14e868
PB		 5252}
5253
5254int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5255 unsigned int bytes, struct x86_exception *exception)
5256{
c595ceee
PB		 5257 /* kvm_write_guest_virt_system can pull in tons of pages. */
5258 vcpu->arch.l1tf_flush_l1d = true;
5259
ce14e868
PB		 5260 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5261 PFERR_WRITE_MASK, exception);
5262}
6a4d7550 5263EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5264
082d06ed
WL		 5265int handle_ud(struct kvm_vcpu *vcpu)
5266{
6c86eedc 5267 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5268 enum emulation_result er;
6c86eedc
WL		 5269 char sig[5]; /* ud2; .ascii "kvm" */
5270 struct x86_exception e;
5271
5272 if (force_emulation_prefix &&
3c9fa24c
PB		 5273 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5274 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5275 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5276 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5277 emul_type = 0;
5278 }
082d06ed 5279
0ce97a2b 5280 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5281 if (er == EMULATE_USER_EXIT)
5282 return 0;
5283 if (er != EMULATE_DONE)
5284 kvm_queue_exception(vcpu, UD_VECTOR);
5285 return 1;
5286}
5287EXPORT_SYMBOL_GPL(handle_ud);
5288
0f89b207
TL		 5289static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5290 gpa_t gpa, bool write)
5291{
5292 /* For APIC access vmexit */
5293 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5294 return 1;
5295
5296 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5297 trace_vcpu_match_mmio(gva, gpa, write, true);
5298 return 1;
5299 }
5300
5301 return 0;
5302}
5303
af7cc7d1
XG		 5304static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5305 gpa_t *gpa, struct x86_exception *exception,
5306 bool write)
5307{
97d64b78
AK		 5308 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5309 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5310
be94f6b7
HH		 5311 /*
5312 * currently PKRU is only applied to ept enabled guest so
5313 * there is no pkey in EPT page table for L1 guest or EPT
5314 * shadow page table for L2 guest.
5315 */
97d64b78 5316 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5317 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5318 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5319 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5320 (gva & (PAGE_SIZE - 1));
4f022648 5321 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5322 return 1;
5323 }
5324
af7cc7d1
XG		 5325 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5326
5327 if (*gpa == UNMAPPED_GVA)
5328 return -1;
5329
0f89b207 5330 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5331}
5332
3200f405 5333int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5334 const void *val, int bytes)
bbd9b64e
CO		 5335{
5336 int ret;
5337
54bf36aa 5338 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5339 if (ret < 0)
bbd9b64e 5340 return 0;
0eb05bf2 5341 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5342 return 1;
5343}
5344
77d197b2
XG		 5345struct read_write_emulator_ops {
5346 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5347 int bytes);
5348 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5349 void *val, int bytes);
5350 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5351 int bytes, void *val);
5352 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5353 void *val, int bytes);
5354 bool write;
5355};
5356
5357static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5358{
5359 if (vcpu->mmio_read_completed) {
77d197b2 5360 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5361 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5362 vcpu->mmio_read_completed = 0;
5363 return 1;
5364 }
5365
5366 return 0;
5367}
5368
5369static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5370 void *val, int bytes)
5371{
54bf36aa 5372 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5373}
5374
5375static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5376 void *val, int bytes)
5377{
5378 return emulator_write_phys(vcpu, gpa, val, bytes);
5379}
5380
5381static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5382{
e39d200f 5383 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5384 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5385}
5386
5387static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5388 void *val, int bytes)
5389{
e39d200f 5390 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5391 return X86EMUL_IO_NEEDED;
5392}
5393
5394static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5395 void *val, int bytes)
5396{
f78146b0
AK		 5397 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5398
87da7e66 5399 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5400 return X86EMUL_CONTINUE;
5401}
5402
0fbe9b0b 5403static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5404 .read_write_prepare = read_prepare,
5405 .read_write_emulate = read_emulate,
5406 .read_write_mmio = vcpu_mmio_read,
5407 .read_write_exit_mmio = read_exit_mmio,
5408};
5409
0fbe9b0b 5410static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5411 .read_write_emulate = write_emulate,
5412 .read_write_mmio = write_mmio,
5413 .read_write_exit_mmio = write_exit_mmio,
5414 .write = true,
5415};
5416
22388a3c
XG		 5417static int emulator_read_write_onepage(unsigned long addr, void *val,
5418 unsigned int bytes,
5419 struct x86_exception *exception,
5420 struct kvm_vcpu *vcpu,
0fbe9b0b 5421 const struct read_write_emulator_ops *ops)
bbd9b64e 5422{
af7cc7d1
XG		 5423 gpa_t gpa;
5424 int handled, ret;
22388a3c 5425 bool write = ops->write;
f78146b0 5426 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5427 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5428
5429 /*
5430 * If the exit was due to a NPF we may already have a GPA.
5431 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5432 * Note, this cannot be used on string operations since string
5433 * operation using rep will only have the initial GPA from the NPF
5434 * occurred.
5435 */
5436 if (vcpu->arch.gpa_available &&
5437 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5438 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5439 gpa = vcpu->arch.gpa_val;
5440 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5441 } else {
5442 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5443 if (ret < 0)
5444 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5445 }
10589a46 5446
618232e2 5447 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5448 return X86EMUL_CONTINUE;
5449
bbd9b64e
CO		 5450 /*
5451 * Is this MMIO handled locally?
5452 */
22388a3c 5453 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5454 if (handled == bytes)
bbd9b64e 5455 return X86EMUL_CONTINUE;
bbd9b64e 5456
70252a10
AK		 5457 gpa += handled;
5458 bytes -= handled;
5459 val += handled;
5460
87da7e66
XG		 5461 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5462 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5463 frag->gpa = gpa;
5464 frag->data = val;
5465 frag->len = bytes;
f78146b0 5466 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5467}
5468
52eb5a6d
XL		 5469static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5470 unsigned long addr,
22388a3c
XG		 5471 void *val, unsigned int bytes,
5472 struct x86_exception *exception,
0fbe9b0b 5473 const struct read_write_emulator_ops *ops)
bbd9b64e 5474{
0f65dd70 5475 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5476 gpa_t gpa;
5477 int rc;
5478
5479 if (ops->read_write_prepare &&
5480 ops->read_write_prepare(vcpu, val, bytes))
5481 return X86EMUL_CONTINUE;
5482
5483 vcpu->mmio_nr_fragments = 0;
0f65dd70 5484
bbd9b64e
CO		 5485 /* Crossing a page boundary? */
5486 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5487 int now;
bbd9b64e
CO		 5488
5489 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5490 rc = emulator_read_write_onepage(addr, val, now, exception,
5491 vcpu, ops);
5492
bbd9b64e
CO		 5493 if (rc != X86EMUL_CONTINUE)
5494 return rc;
5495 addr += now;
bac15531
NA		 5496 if (ctxt->mode != X86EMUL_MODE_PROT64)
5497 addr = (u32)addr;
bbd9b64e
CO		 5498 val += now;
5499 bytes -= now;
5500 }
22388a3c 5501
f78146b0
AK		 5502 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5503 vcpu, ops);
5504 if (rc != X86EMUL_CONTINUE)
5505 return rc;
5506
5507 if (!vcpu->mmio_nr_fragments)
5508 return rc;
5509
5510 gpa = vcpu->mmio_fragments[0].gpa;
5511
5512 vcpu->mmio_needed = 1;
5513 vcpu->mmio_cur_fragment = 0;
5514
87da7e66 5515 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5516 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5517 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5518 vcpu->run->mmio.phys_addr = gpa;
5519
5520 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5521}
5522
5523static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5524 unsigned long addr,
5525 void *val,
5526 unsigned int bytes,
5527 struct x86_exception *exception)
5528{
5529 return emulator_read_write(ctxt, addr, val, bytes,
5530 exception, &read_emultor);
5531}
5532
52eb5a6d 5533static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5534 unsigned long addr,
5535 const void *val,
5536 unsigned int bytes,
5537 struct x86_exception *exception)
5538{
5539 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5540 exception, &write_emultor);
bbd9b64e 5541}
bbd9b64e 5542
daea3e73
AK		 5543#define CMPXCHG_TYPE(t, ptr, old, new) \
5544 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5545
5546#ifdef CONFIG_X86_64
5547# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5548#else
5549# define CMPXCHG64(ptr, old, new) \
9749a6c0 5550 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5551#endif
5552
0f65dd70
AK		 5553static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5554 unsigned long addr,
bbd9b64e
CO		 5555 const void *old,
5556 const void *new,
5557 unsigned int bytes,
0f65dd70 5558 struct x86_exception *exception)
bbd9b64e 5559{
0f65dd70 5560 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5561 gpa_t gpa;
5562 struct page *page;
5563 char *kaddr;
5564 bool exchanged;
2bacc55c 5565
daea3e73
AK		 5566 /* guests cmpxchg8b have to be emulated atomically */
5567 if (bytes > 8 || (bytes & (bytes - 1)))
5568 goto emul_write;
10589a46 5569
daea3e73 5570 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5571
daea3e73
AK		 5572 if (gpa == UNMAPPED_GVA ||
5573 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5574 goto emul_write;
2bacc55c 5575
daea3e73
AK		 5576 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5577 goto emul_write;
72dc67a6 5578
54bf36aa 5579 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5580 if (is_error_page(page))
c19b8bd6 5581 goto emul_write;
72dc67a6 5582
8fd75e12 5583 kaddr = kmap_atomic(page);
daea3e73
AK		 5584 kaddr += offset_in_page(gpa);
5585 switch (bytes) {
5586 case 1:
5587 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5588 break;
5589 case 2:
5590 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5591 break;
5592 case 4:
5593 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5594 break;
5595 case 8:
5596 exchanged = CMPXCHG64(kaddr, old, new);
5597 break;
5598 default:
5599 BUG();
2bacc55c 5600 }
8fd75e12 5601 kunmap_atomic(kaddr);
daea3e73
AK		 5602 kvm_release_page_dirty(page);
5603
5604 if (!exchanged)
5605 return X86EMUL_CMPXCHG_FAILED;
5606
54bf36aa 5607 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5608 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5609
5610 return X86EMUL_CONTINUE;
4a5f48f6 5611
3200f405 5612emul_write:
daea3e73 5613 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5614
0f65dd70 5615 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5616}
5617
cf8f70bf
GN		 5618static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5619{
cbfc6c91 5620 int r = 0, i;
cf8f70bf 5621
cbfc6c91
WL		 5622 for (i = 0; i < vcpu->arch.pio.count; i++) {
5623 if (vcpu->arch.pio.in)
5624 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5625 vcpu->arch.pio.size, pd);
5626 else
5627 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5628 vcpu->arch.pio.port, vcpu->arch.pio.size,
5629 pd);
5630 if (r)
5631 break;
5632 pd += vcpu->arch.pio.size;
5633 }
cf8f70bf
GN		 5634 return r;
5635}
5636
6f6fbe98
XG		 5637static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5638 unsigned short port, void *val,
5639 unsigned int count, bool in)
cf8f70bf 5640{
cf8f70bf 5641 vcpu->arch.pio.port = port;
6f6fbe98 5642 vcpu->arch.pio.in = in;
7972995b 5643 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5644 vcpu->arch.pio.size = size;
5645
5646 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5647 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5648 return 1;
5649 }
5650
5651 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5652 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5653 vcpu->run->io.size = size;
5654 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5655 vcpu->run->io.count = count;
5656 vcpu->run->io.port = port;
5657
5658 return 0;
5659}
5660
6f6fbe98
XG		 5661static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5662 int size, unsigned short port, void *val,
5663 unsigned int count)
cf8f70bf 5664{
ca1d4a9e 5665 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5666 int ret;
ca1d4a9e 5667
6f6fbe98
XG		 5668 if (vcpu->arch.pio.count)
5669 goto data_avail;
cf8f70bf 5670
cbfc6c91
WL		 5671 memset(vcpu->arch.pio_data, 0, size * count);
5672
6f6fbe98
XG		 5673 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5674 if (ret) {
5675data_avail:
5676 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5677 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5678 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5679 return 1;
5680 }
5681
cf8f70bf
GN		 5682 return 0;
5683}
5684
6f6fbe98
XG		 5685static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5686 int size, unsigned short port,
5687 const void *val, unsigned int count)
5688{
5689 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5690
5691 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5692 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5693 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5694}
5695
bbd9b64e
CO		 5696static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5697{
5698 return kvm_x86_ops->get_segment_base(vcpu, seg);
5699}
5700
3cb16fe7 5701static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5702{
3cb16fe7 5703 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5704}
5705
ae6a2375 5706static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5707{
5708 if (!need_emulate_wbinvd(vcpu))
5709 return X86EMUL_CONTINUE;
5710
5711 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5712 int cpu = get_cpu();
5713
5714 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5715 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5716 wbinvd_ipi, NULL, 1);
2eec7343 5717 put_cpu();
f5f48ee1 5718 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5719 } else
5720 wbinvd();
f5f48ee1
SY		 5721 return X86EMUL_CONTINUE;
5722}
5cb56059
JS		 5723
5724int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5725{
6affcbed
KH		 5726 kvm_emulate_wbinvd_noskip(vcpu);
5727 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5728}
f5f48ee1
SY		 5729EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5730
5cb56059
JS		 5731
5732
bcaf5cc5
AK		 5733static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5734{
5cb56059 5735 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5736}
5737
52eb5a6d
XL		 5738static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5739 unsigned long *dest)
bbd9b64e 5740{
16f8a6f9 5741 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5742}
5743
52eb5a6d
XL		 5744static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5745 unsigned long value)
bbd9b64e 5746{
338dbc97 5747
717746e3 5748 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5749}
5750
52a46617 5751static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5752{
52a46617 5753 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5754}
5755
717746e3 5756static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5757{
717746e3 5758 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5759 unsigned long value;
5760
5761 switch (cr) {
5762 case 0:
5763 value = kvm_read_cr0(vcpu);
5764 break;
5765 case 2:
5766 value = vcpu->arch.cr2;
5767 break;
5768 case 3:
9f8fe504 5769 value = kvm_read_cr3(vcpu);
52a46617
GN		 5770 break;
5771 case 4:
5772 value = kvm_read_cr4(vcpu);
5773 break;
5774 case 8:
5775 value = kvm_get_cr8(vcpu);
5776 break;
5777 default:
a737f256 5778 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5779 return 0;
5780 }
5781
5782 return value;
5783}
5784
717746e3 5785static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5786{
717746e3 5787 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5788 int res = 0;
5789
52a46617
GN		 5790 switch (cr) {
5791 case 0:
49a9b07e 5792 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5793 break;
5794 case 2:
5795 vcpu->arch.cr2 = val;
5796 break;
5797 case 3:
2390218b 5798 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5799 break;
5800 case 4:
a83b29c6 5801 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5802 break;
5803 case 8:
eea1cff9 5804 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5805 break;
5806 default:
a737f256 5807 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5808 res = -1;
52a46617 5809 }
0f12244f
GN		 5810
5811 return res;
52a46617
GN		 5812}
5813
717746e3 5814static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5815{
717746e3 5816 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5817}
5818
4bff1e86 5819static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5820{
4bff1e86 5821 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5822}
5823
4bff1e86 5824static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5825{
4bff1e86 5826 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5827}
5828
1ac9d0cf
AK		 5829static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5830{
5831 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5832}
5833
5834static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5835{
5836 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5837}
5838
4bff1e86
AK		 5839static unsigned long emulator_get_cached_segment_base(
5840 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5841{
4bff1e86 5842 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5843}
5844
1aa36616
AK		 5845static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5846 struct desc_struct *desc, u32 *base3,
5847 int seg)
2dafc6c2
GN		 5848{
5849 struct kvm_segment var;
5850
4bff1e86 5851 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5852 *selector = var.selector;
2dafc6c2 5853
378a8b09
GN		 5854 if (var.unusable) {
5855 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5856 if (base3)
5857 *base3 = 0;
2dafc6c2 5858 return false;
378a8b09 5859 }
2dafc6c2
GN		 5860
5861 if (var.g)
5862 var.limit >>= 12;
5863 set_desc_limit(desc, var.limit);
5864 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5865#ifdef CONFIG_X86_64
5866 if (base3)
5867 *base3 = var.base >> 32;
5868#endif
2dafc6c2
GN		 5869 desc->type = var.type;
5870 desc->s = var.s;
5871 desc->dpl = var.dpl;
5872 desc->p = var.present;
5873 desc->avl = var.avl;
5874 desc->l = var.l;
5875 desc->d = var.db;
5876 desc->g = var.g;
5877
5878 return true;
5879}
5880
1aa36616
AK		 5881static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5882 struct desc_struct *desc, u32 base3,
5883 int seg)
2dafc6c2 5884{
4bff1e86 5885 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5886 struct kvm_segment var;
5887
1aa36616 5888 var.selector = selector;
2dafc6c2 5889 var.base = get_desc_base(desc);
5601d05b
GN		 5890#ifdef CONFIG_X86_64
5891 var.base |= ((u64)base3) << 32;
5892#endif
2dafc6c2
GN		 5893 var.limit = get_desc_limit(desc);
5894 if (desc->g)
5895 var.limit = (var.limit << 12) | 0xfff;
5896 var.type = desc->type;
2dafc6c2
GN		 5897 var.dpl = desc->dpl;
5898 var.db = desc->d;
5899 var.s = desc->s;
5900 var.l = desc->l;
5901 var.g = desc->g;
5902 var.avl = desc->avl;
5903 var.present = desc->p;
5904 var.unusable = !var.present;
5905 var.padding = 0;
5906
5907 kvm_set_segment(vcpu, &var, seg);
5908 return;
5909}
5910
717746e3
AK		 5911static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5912 u32 msr_index, u64 *pdata)
5913{
609e36d3
PB		 5914 struct msr_data msr;
5915 int r;
5916
5917 msr.index = msr_index;
5918 msr.host_initiated = false;
5919 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5920 if (r)
5921 return r;
5922
5923 *pdata = msr.data;
5924 return 0;
717746e3
AK		 5925}
5926
5927static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5928 u32 msr_index, u64 data)
5929{
8fe8ab46
WA		 5930 struct msr_data msr;
5931
5932 msr.data = data;
5933 msr.index = msr_index;
5934 msr.host_initiated = false;
5935 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5936}
5937
64d60670
PB		 5938static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5939{
5940 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5941
5942 return vcpu->arch.smbase;
5943}
5944
5945static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5946{
5947 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5948
5949 vcpu->arch.smbase = smbase;
5950}
5951
67f4d428
NA		 5952static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5953 u32 pmc)
5954{
c6702c9d 5955 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5956}
5957
222d21aa
AK		 5958static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5959 u32 pmc, u64 *pdata)
5960{
c6702c9d 5961 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5962}
5963
6c3287f7
AK		 5964static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5965{
5966 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5967}
5968
2953538e 5969static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5970 struct x86_instruction_info *info,
c4f035c6
AK		 5971 enum x86_intercept_stage stage)
5972{
2953538e 5973 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5974}
5975
e911eb3b
YZ		 5976static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5977 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5978{
e911eb3b 5979 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5980}
5981
dd856efa
AK		 5982static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5983{
5984 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5985}
5986
5987static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5988{
5989 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5990}
5991
801806d9
NA		 5992static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5993{
5994 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5995}
5996
6ed071f0
LP		 5997static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5998{
5999 return emul_to_vcpu(ctxt)->arch.hflags;
6000}
6001
6002static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6003{
c5833c7a 6004 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 6005}
6006
ed19321f
SC		 6007static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6008 const char *smstate)
0234bf88 6009{
ed19321f 6010 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 6011}
6012
c5833c7a
SC		 6013static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6014{
6015 kvm_smm_changed(emul_to_vcpu(ctxt));
6016}
6017
0225fb50 6018static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 6019 .read_gpr = emulator_read_gpr,
6020 .write_gpr = emulator_write_gpr,
ce14e868
PB		 6021 .read_std = emulator_read_std,
6022 .write_std = emulator_write_std,
7a036a6f 6023 .read_phys = kvm_read_guest_phys_system,
1871c602 6024 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 6025 .read_emulated = emulator_read_emulated,
6026 .write_emulated = emulator_write_emulated,
6027 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 6028 .invlpg = emulator_invlpg,
cf8f70bf
GN		 6029 .pio_in_emulated = emulator_pio_in_emulated,
6030 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 6031 .get_segment = emulator_get_segment,
6032 .set_segment = emulator_set_segment,
5951c442 6033 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 6034 .get_gdt = emulator_get_gdt,
160ce1f1 6035 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 6036 .set_gdt = emulator_set_gdt,
6037 .set_idt = emulator_set_idt,
52a46617
GN		 6038 .get_cr = emulator_get_cr,
6039 .set_cr = emulator_set_cr,
9c537244 6040 .cpl = emulator_get_cpl,
35aa5375
GN		 6041 .get_dr = emulator_get_dr,
6042 .set_dr = emulator_set_dr,
64d60670
PB		 6043 .get_smbase = emulator_get_smbase,
6044 .set_smbase = emulator_set_smbase,
717746e3
AK		 6045 .set_msr = emulator_set_msr,
6046 .get_msr = emulator_get_msr,
67f4d428 6047 .check_pmc = emulator_check_pmc,
222d21aa 6048 .read_pmc = emulator_read_pmc,
6c3287f7 6049 .halt = emulator_halt,
bcaf5cc5 6050 .wbinvd = emulator_wbinvd,
d6aa1000 6051 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6052 .intercept = emulator_intercept,
bdb42f5a 6053 .get_cpuid = emulator_get_cpuid,
801806d9 6054 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6055 .get_hflags = emulator_get_hflags,
6056 .set_hflags = emulator_set_hflags,
0234bf88 6057 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6058 .post_leave_smm = emulator_post_leave_smm,
bbd9b64e
CO		 6059};
6060
95cb2295
GN		 6061static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6062{
37ccdcbe 6063 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6064 /*
6065 * an sti; sti; sequence only disable interrupts for the first
6066 * instruction. So, if the last instruction, be it emulated or
6067 * not, left the system with the INT_STI flag enabled, it
6068 * means that the last instruction is an sti. We should not
6069 * leave the flag on in this case. The same goes for mov ss
6070 */
37ccdcbe
PB		 6071 if (int_shadow & mask)
6072 mask = 0;
6addfc42 6073 if (unlikely(int_shadow || mask)) {
95cb2295 6074 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6075 if (!mask)
6076 kvm_make_request(KVM_REQ_EVENT, vcpu);
6077 }
95cb2295
GN		 6078}
6079
ef54bcfe 6080static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6081{
6082 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6083 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6084 return kvm_propagate_fault(vcpu, &ctxt->exception);
6085
6086 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6087 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6088 ctxt->exception.error_code);
54b8486f 6089 else
da9cb575 6090 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6091 return false;
54b8486f
GN		 6092}
6093
8ec4722d
MG		 6094static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6095{
adf52235 6096 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6097 int cs_db, cs_l;
6098
8ec4722d
MG		 6099 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6100
adf52235 6101 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6102 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6103
adf52235
TY		 6104 ctxt->eip = kvm_rip_read(vcpu);
6105 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6106 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6107 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6108 cs_db ? X86EMUL_MODE_PROT32 :
6109 X86EMUL_MODE_PROT16;
a584539b 6110 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6111 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6112 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6113
dd856efa 6114 init_decode_cache(ctxt);
7ae441ea 6115 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6116}
6117
71f9833b 6118int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6119{
9d74191a 6120 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6121 int ret;
6122
6123 init_emulate_ctxt(vcpu);
6124
9dac77fa
AK		 6125 ctxt->op_bytes = 2;
6126 ctxt->ad_bytes = 2;
6127 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6128 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6129
6130 if (ret != X86EMUL_CONTINUE)
6131 return EMULATE_FAIL;
6132
9dac77fa 6133 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6134 kvm_rip_write(vcpu, ctxt->eip);
6135 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6136
63995653
MG		 6137 return EMULATE_DONE;
6138}
6139EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6140
e2366171 6141static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6142{
fc3a9157
JR		 6143 int r = EMULATE_DONE;
6144
6d77dbfc
GN		 6145 ++vcpu->stat.insn_emulation_fail;
6146 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6147
6148 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6149 return EMULATE_FAIL;
6150
a2b9e6c1 6151 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6152 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6153 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6154 vcpu->run->internal.ndata = 0;
1f4dcb3b 6155 r = EMULATE_USER_EXIT;
fc3a9157 6156 }
e2366171 6157
6d77dbfc 6158 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6159
6160 return r;
6d77dbfc
GN		 6161}
6162
93c05d3e 6163static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6164 bool write_fault_to_shadow_pgtable,
6165 int emulation_type)
a6f177ef 6166{
95b3cf69 6167 gpa_t gpa = cr2;
ba049e93 6168 kvm_pfn_t pfn;
a6f177ef 6169
384bf221 6170 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6171 return false;
6172
6c3dfeb6
SC		 6173 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6174 return false;
6175
44dd3ffa 6176 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6177 /*
6178 * Write permission should be allowed since only
6179 * write access need to be emulated.
6180 */
6181 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6182
95b3cf69
XG		 6183 /*
6184 * If the mapping is invalid in guest, let cpu retry
6185 * it to generate fault.
6186 */
6187 if (gpa == UNMAPPED_GVA)
6188 return true;
6189 }
a6f177ef 6190
8e3d9d06
XG		 6191 /*
6192 * Do not retry the unhandleable instruction if it faults on the
6193 * readonly host memory, otherwise it will goto a infinite loop:
6194 * retry instruction -> write #PF -> emulation fail -> retry
6195 * instruction -> ...
6196 */
6197 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6198
6199 /*
6200 * If the instruction failed on the error pfn, it can not be fixed,
6201 * report the error to userspace.
6202 */
6203 if (is_error_noslot_pfn(pfn))
6204 return false;
6205
6206 kvm_release_pfn_clean(pfn);
6207
6208 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6209 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6210 unsigned int indirect_shadow_pages;
6211
6212 spin_lock(&vcpu->kvm->mmu_lock);
6213 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6214 spin_unlock(&vcpu->kvm->mmu_lock);
6215
6216 if (indirect_shadow_pages)
6217 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6218
a6f177ef 6219 return true;
8e3d9d06 6220 }
a6f177ef 6221
95b3cf69
XG		 6222 /*
6223 * if emulation was due to access to shadowed page table
6224 * and it failed try to unshadow page and re-enter the
6225 * guest to let CPU execute the instruction.
6226 */
6227 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6228
6229 /*
6230 * If the access faults on its page table, it can not
6231 * be fixed by unprotecting shadow page and it should
6232 * be reported to userspace.
6233 */
6234 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6235}
6236
1cb3f3ae
XG		 6237static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6238 unsigned long cr2, int emulation_type)
6239{
6240 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6241 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6242
6243 last_retry_eip = vcpu->arch.last_retry_eip;
6244 last_retry_addr = vcpu->arch.last_retry_addr;
6245
6246 /*
6247 * If the emulation is caused by #PF and it is non-page_table
6248 * writing instruction, it means the VM-EXIT is caused by shadow
6249 * page protected, we can zap the shadow page and retry this
6250 * instruction directly.
6251 *
6252 * Note: if the guest uses a non-page-table modifying instruction
6253 * on the PDE that points to the instruction, then we will unmap
6254 * the instruction and go to an infinite loop. So, we cache the
6255 * last retried eip and the last fault address, if we meet the eip
6256 * and the address again, we can break out of the potential infinite
6257 * loop.
6258 */
6259 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6260
384bf221 6261 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6262 return false;
6263
6c3dfeb6
SC		 6264 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6265 return false;
6266
1cb3f3ae
XG		 6267 if (x86_page_table_writing_insn(ctxt))
6268 return false;
6269
6270 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6271 return false;
6272
6273 vcpu->arch.last_retry_eip = ctxt->eip;
6274 vcpu->arch.last_retry_addr = cr2;
6275
44dd3ffa 6276 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6277 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6278
22368028 6279 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6280
6281 return true;
6282}
6283
716d51ab
GN		 6284static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6285static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6286
64d60670 6287static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6288{
64d60670 6289 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6290 /* This is a good place to trace that we are exiting SMM. */
6291 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6292
c43203ca
PB		 6293 /* Process a latched INIT or SMI, if any. */
6294 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6295 }
699023e2
PB		 6296
6297 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6298}
6299
4a1e10d5
PB		 6300static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6301 unsigned long *db)
6302{
6303 u32 dr6 = 0;
6304 int i;
6305 u32 enable, rwlen;
6306
6307 enable = dr7;
6308 rwlen = dr7 >> 16;
6309 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6310 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6311 dr6 |= (1 << i);
6312 return dr6;
6313}
6314
c8401dda 6315static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6316{
6317 struct kvm_run *kvm_run = vcpu->run;
6318
c8401dda
PB		 6319 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6320 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6321 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6322 kvm_run->debug.arch.exception = DB_VECTOR;
6323 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6324 *r = EMULATE_USER_EXIT;
6325 } else {
f10c729f 6326 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6327 }
6328}
6329
6affcbed
KH		 6330int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6331{
6332 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6333 int r = EMULATE_DONE;
6334
6335 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6336
6337 /*
6338 * rflags is the old, "raw" value of the flags. The new value has
6339 * not been saved yet.
6340 *
6341 * This is correct even for TF set by the guest, because "the
6342 * processor will not generate this exception after the instruction
6343 * that sets the TF flag".
6344 */
6345 if (unlikely(rflags & X86_EFLAGS_TF))
6346 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6347 return r == EMULATE_DONE;
6348}
6349EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6350
4a1e10d5
PB		 6351static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6352{
4a1e10d5
PB		 6353 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6354 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6355 struct kvm_run *kvm_run = vcpu->run;
6356 unsigned long eip = kvm_get_linear_rip(vcpu);
6357 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6358 vcpu->arch.guest_debug_dr7,
6359 vcpu->arch.eff_db);
6360
6361 if (dr6 != 0) {
6f43ed01 6362 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6363 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6364 kvm_run->debug.arch.exception = DB_VECTOR;
6365 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6366 *r = EMULATE_USER_EXIT;
6367 return true;
6368 }
6369 }
6370
4161a569
NA		 6371 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6372 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6373 unsigned long eip = kvm_get_linear_rip(vcpu);
6374 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6375 vcpu->arch.dr7,
6376 vcpu->arch.db);
6377
6378 if (dr6 != 0) {
6379 vcpu->arch.dr6 &= ~15;
6f43ed01 6380 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6381 kvm_queue_exception(vcpu, DB_VECTOR);
6382 *r = EMULATE_DONE;
6383 return true;
6384 }
6385 }
6386
6387 return false;
6388}
6389
04789b66
LA		 6390static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6391{
2d7921c4
AM		 6392 switch (ctxt->opcode_len) {
6393 case 1:
6394 switch (ctxt->b) {
6395 case 0xe4: /* IN */
6396 case 0xe5:
6397 case 0xec:
6398 case 0xed:
6399 case 0xe6: /* OUT */
6400 case 0xe7:
6401 case 0xee:
6402 case 0xef:
6403 case 0x6c: /* INS */
6404 case 0x6d:
6405 case 0x6e: /* OUTS */
6406 case 0x6f:
6407 return true;
6408 }
6409 break;
6410 case 2:
6411 switch (ctxt->b) {
6412 case 0x33: /* RDPMC */
6413 return true;
6414 }
6415 break;
04789b66
LA		 6416 }
6417
6418 return false;
6419}
6420
51d8b661
AP		 6421int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6422 unsigned long cr2,
dc25e89e
AP		 6423 int emulation_type,
6424 void *insn,
6425 int insn_len)
bbd9b64e 6426{
95cb2295 6427 int r;
9d74191a 6428 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6429 bool writeback = true;
93c05d3e 6430 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6431
c595ceee
PB		 6432 vcpu->arch.l1tf_flush_l1d = true;
6433
93c05d3e
XG		 6434 /*
6435 * Clear write_fault_to_shadow_pgtable here to ensure it is
6436 * never reused.
6437 */
6438 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6439 kvm_clear_exception_queue(vcpu);
8d7d8102 6440
571008da 6441 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6442 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6443
6444 /*
6445 * We will reenter on the same instruction since
6446 * we do not set complete_userspace_io. This does not
6447 * handle watchpoints yet, those would be handled in
6448 * the emulate_ops.
6449 */
d391f120
VK		 6450 if (!(emulation_type & EMULTYPE_SKIP) &&
6451 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6452 return r;
6453
9d74191a
TY		 6454 ctxt->interruptibility = 0;
6455 ctxt->have_exception = false;
e0ad0b47 6456 ctxt->exception.vector = -1;
9d74191a 6457 ctxt->perm_ok = false;
bbd9b64e 6458
b51e974f 6459 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6460
9d74191a 6461 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6462
e46479f8 6463 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6464 ++vcpu->stat.insn_emulation;
1d2887e2 6465 if (r != EMULATION_OK) {
4005996e
AK		 6466 if (emulation_type & EMULTYPE_TRAP_UD)
6467 return EMULATE_FAIL;
991eebf9
GN		 6468 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6469 emulation_type))
bbd9b64e 6470 return EMULATE_DONE;
6ea6e843
PB		 6471 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6472 return EMULATE_DONE;
6d77dbfc
GN		 6473 if (emulation_type & EMULTYPE_SKIP)
6474 return EMULATE_FAIL;
e2366171 6475 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6476 }
6477 }
6478
04789b66
LA		 6479 if ((emulation_type & EMULTYPE_VMWARE) &&
6480 !is_vmware_backdoor_opcode(ctxt))
6481 return EMULATE_FAIL;
6482
ba8afb6b 6483 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6484 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6485 if (ctxt->eflags & X86_EFLAGS_RF)
6486 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6487 return EMULATE_DONE;
6488 }
6489
1cb3f3ae
XG		 6490 if (retry_instruction(ctxt, cr2, emulation_type))
6491 return EMULATE_DONE;
6492
7ae441ea 6493 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6494 changes registers values during IO operation */
7ae441ea
GN		 6495 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6496 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6497 emulator_invalidate_register_cache(ctxt);
7ae441ea 6498 }
4d2179e1 6499
5cd21917 6500restart:
0f89b207
TL		 6501 /* Save the faulting GPA (cr2) in the address field */
6502 ctxt->exception.address = cr2;
6503
9d74191a 6504 r = x86_emulate_insn(ctxt);
bbd9b64e 6505
775fde86
JR		 6506 if (r == EMULATION_INTERCEPTED)
6507 return EMULATE_DONE;
6508
d2ddd1c4 6509 if (r == EMULATION_FAILED) {
991eebf9
GN		 6510 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6511 emulation_type))
c3cd7ffa
GN		 6512 return EMULATE_DONE;
6513
e2366171 6514 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6515 }
6516
9d74191a 6517 if (ctxt->have_exception) {
d2ddd1c4 6518 r = EMULATE_DONE;
ef54bcfe
PB		 6519 if (inject_emulated_exception(vcpu))
6520 return r;
d2ddd1c4 6521 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6522 if (!vcpu->arch.pio.in) {
6523 /* FIXME: return into emulator if single-stepping. */
3457e419 6524 vcpu->arch.pio.count = 0;
0912c977 6525 } else {
7ae441ea 6526 writeback = false;
716d51ab
GN		 6527 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6528 }
ac0a48c3 6529 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6530 } else if (vcpu->mmio_needed) {
6531 if (!vcpu->mmio_is_write)
6532 writeback = false;
ac0a48c3 6533 r = EMULATE_USER_EXIT;
716d51ab 6534 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6535 } else if (r == EMULATION_RESTART)
5cd21917 6536 goto restart;
d2ddd1c4
GN		 6537 else
6538 r = EMULATE_DONE;
f850e2e6 6539
7ae441ea 6540 if (writeback) {
6addfc42 6541 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6542 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6543 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6544 kvm_rip_write(vcpu, ctxt->eip);
5cc244a2 6545 if (r == EMULATE_DONE && ctxt->tf)
c8401dda 6546 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6547 if (!ctxt->have_exception ||
6548 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6549 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6550
6551 /*
6552 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6553 * do nothing, and it will be requested again as soon as
6554 * the shadow expires. But we still need to check here,
6555 * because POPF has no interrupt shadow.
6556 */
6557 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6558 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6559 } else
6560 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6561
6562 return r;
de7d789a 6563}
c60658d1
SC		 6564
6565int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6566{
6567 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6568}
6569EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6570
6571int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6572 void *insn, int insn_len)
6573{
6574 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6575}
6576EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6577
45def77e
SC		 6578static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6579{
6580 vcpu->arch.pio.count = 0;
6581
6582 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6583 return 1;
6584
6585 return kvm_skip_emulated_instruction(vcpu);
6586}
6587
dca7f128
SC		 6588static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6589 unsigned short port)
de7d789a 6590{
cf8f70bf 6591 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6592 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6593 size, port, &val, 1);
45def77e
SC		 6594
6595 if (!ret) {
6596 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6597 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6598 }
de7d789a
CO		 6599 return ret;
6600}
de7d789a 6601
8370c3d0
TL		 6602static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6603{
6604 unsigned long val;
6605
6606 /* We should only ever be called with arch.pio.count equal to 1 */
6607 BUG_ON(vcpu->arch.pio.count != 1);
6608
45def77e
SC		 6609 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6610 vcpu->arch.pio.count = 0;
6611 return 1;
6612 }
6613
8370c3d0
TL		 6614 /* For size less than 4 we merge, else we zero extend */
6615 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6616 : 0;
6617
6618 /*
6619 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6620 * the copy and tracing
6621 */
6622 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6623 vcpu->arch.pio.port, &val, 1);
6624 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6625
45def77e 6626 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6627}
6628
dca7f128
SC		 6629static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6630 unsigned short port)
8370c3d0
TL		 6631{
6632 unsigned long val;
6633 int ret;
6634
6635 /* For size less than 4 we merge, else we zero extend */
6636 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6637
6638 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6639 &val, 1);
6640 if (ret) {
6641 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6642 return ret;
6643 }
6644
45def77e 6645 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6646 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6647
6648 return 0;
6649}
dca7f128
SC		 6650
6651int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6652{
45def77e 6653 int ret;
dca7f128 6654
dca7f128 6655 if (in)
45def77e 6656 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6657 else
45def77e
SC		 6658 ret = kvm_fast_pio_out(vcpu, size, port);
6659 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 6660}
6661EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6662
251a5fd6 6663static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6664{
0a3aee0d 6665 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6666 return 0;
8cfdc000
ZA		 6667}
6668
6669static void tsc_khz_changed(void *data)
c8076604 6670{
8cfdc000
ZA		 6671 struct cpufreq_freqs *freq = data;
6672 unsigned long khz = 0;
6673
6674 if (data)
6675 khz = freq->new;
6676 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6677 khz = cpufreq_quick_get(raw_smp_processor_id());
6678 if (!khz)
6679 khz = tsc_khz;
0a3aee0d 6680 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6681}
6682
5fa4ec9c 6683#ifdef CONFIG_X86_64
0092e434
VK		 6684static void kvm_hyperv_tsc_notifier(void)
6685{
0092e434
VK		 6686 struct kvm *kvm;
6687 struct kvm_vcpu *vcpu;
6688 int cpu;
6689
6690 spin_lock(&kvm_lock);
6691 list_for_each_entry(kvm, &vm_list, vm_list)
6692 kvm_make_mclock_inprogress_request(kvm);
6693
6694 hyperv_stop_tsc_emulation();
6695
6696 /* TSC frequency always matches when on Hyper-V */
6697 for_each_present_cpu(cpu)
6698 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6699 kvm_max_guest_tsc_khz = tsc_khz;
6700
6701 list_for_each_entry(kvm, &vm_list, vm_list) {
6702 struct kvm_arch *ka = &kvm->arch;
6703
6704 spin_lock(&ka->pvclock_gtod_sync_lock);
6705
6706 pvclock_update_vm_gtod_copy(kvm);
6707
6708 kvm_for_each_vcpu(cpu, vcpu, kvm)
6709 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6710
6711 kvm_for_each_vcpu(cpu, vcpu, kvm)
6712 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6713
6714 spin_unlock(&ka->pvclock_gtod_sync_lock);
6715 }
6716 spin_unlock(&kvm_lock);
0092e434 6717}
5fa4ec9c 6718#endif
0092e434 6719
c8076604
GH		 6720static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6721 void *data)
6722{
6723 struct cpufreq_freqs *freq = data;
6724 struct kvm *kvm;
6725 struct kvm_vcpu *vcpu;
6726 int i, send_ipi = 0;
6727
8cfdc000
ZA		 6728 /*
6729 * We allow guests to temporarily run on slowing clocks,
6730 * provided we notify them after, or to run on accelerating
6731 * clocks, provided we notify them before. Thus time never
6732 * goes backwards.
6733 *
6734 * However, we have a problem. We can't atomically update
6735 * the frequency of a given CPU from this function; it is
6736 * merely a notifier, which can be called from any CPU.
6737 * Changing the TSC frequency at arbitrary points in time
6738 * requires a recomputation of local variables related to
6739 * the TSC for each VCPU. We must flag these local variables
6740 * to be updated and be sure the update takes place with the
6741 * new frequency before any guests proceed.
6742 *
6743 * Unfortunately, the combination of hotplug CPU and frequency
6744 * change creates an intractable locking scenario; the order
6745 * of when these callouts happen is undefined with respect to
6746 * CPU hotplug, and they can race with each other. As such,
6747 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6748 * undefined; you can actually have a CPU frequency change take
6749 * place in between the computation of X and the setting of the
6750 * variable. To protect against this problem, all updates of
6751 * the per_cpu tsc_khz variable are done in an interrupt
6752 * protected IPI, and all callers wishing to update the value
6753 * must wait for a synchronous IPI to complete (which is trivial
6754 * if the caller is on the CPU already). This establishes the
6755 * necessary total order on variable updates.
6756 *
6757 * Note that because a guest time update may take place
6758 * anytime after the setting of the VCPU's request bit, the
6759 * correct TSC value must be set before the request. However,
6760 * to ensure the update actually makes it to any guest which
6761 * starts running in hardware virtualization between the set
6762 * and the acquisition of the spinlock, we must also ping the
6763 * CPU after setting the request bit.
6764 *
6765 */
6766
c8076604
GH		 6767 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6768 return 0;
6769 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6770 return 0;
8cfdc000
ZA		 6771
6772 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6773
2f303b74 6774 spin_lock(&kvm_lock);
c8076604 6775 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6776 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6777 if (vcpu->cpu != freq->cpu)
6778 continue;
c285545f 6779 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6780 if (vcpu->cpu != smp_processor_id())
8cfdc000 6781 send_ipi = 1;
c8076604
GH		 6782 }
6783 }
2f303b74 6784 spin_unlock(&kvm_lock);
c8076604
GH		 6785
6786 if (freq->old < freq->new && send_ipi) {
6787 /*
6788 * We upscale the frequency. Must make the guest
6789 * doesn't see old kvmclock values while running with
6790 * the new frequency, otherwise we risk the guest sees
6791 * time go backwards.
6792 *
6793 * In case we update the frequency for another cpu
6794 * (which might be in guest context) send an interrupt
6795 * to kick the cpu out of guest context. Next time
6796 * guest context is entered kvmclock will be updated,
6797 * so the guest will not see stale values.
6798 */
8cfdc000 6799 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6800 }
6801 return 0;
6802}
6803
6804static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6805 .notifier_call = kvmclock_cpufreq_notifier
6806};
6807
251a5fd6 6808static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6809{
251a5fd6
SAS		 6810 tsc_khz_changed(NULL);
6811 return 0;
8cfdc000
ZA		 6812}
6813
b820cc0c
ZA		 6814static void kvm_timer_init(void)
6815{
c285545f 6816 max_tsc_khz = tsc_khz;
460dd42e 6817
b820cc0c 6818 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6819#ifdef CONFIG_CPU_FREQ
6820 struct cpufreq_policy policy;
758f588d
BP		 6821 int cpu;
6822
c285545f 6823 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6824 cpu = get_cpu();
6825 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6826 if (policy.cpuinfo.max_freq)
6827 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6828 put_cpu();
c285545f 6829#endif
b820cc0c
ZA		 6830 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6831 CPUFREQ_TRANSITION_NOTIFIER);
6832 }
c285545f 6833 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6834
73c1b41e 6835 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6836 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6837}
6838
dd60d217
AK		 6839DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6840EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6841
f5132b01 6842int kvm_is_in_guest(void)
ff9d07a0 6843{
086c9855 6844 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6845}
6846
6847static int kvm_is_user_mode(void)
6848{
6849 int user_mode = 3;
dcf46b94 6850
086c9855
AS		 6851 if (__this_cpu_read(current_vcpu))
6852 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6853
ff9d07a0
ZY		 6854 return user_mode != 0;
6855}
6856
6857static unsigned long kvm_get_guest_ip(void)
6858{
6859 unsigned long ip = 0;
dcf46b94 6860
086c9855
AS		 6861 if (__this_cpu_read(current_vcpu))
6862 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6863
ff9d07a0
ZY		 6864 return ip;
6865}
6866
8479e04e
LK		 6867static void kvm_handle_intel_pt_intr(void)
6868{
6869 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6870
6871 kvm_make_request(KVM_REQ_PMI, vcpu);
6872 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6873 (unsigned long *)&vcpu->arch.pmu.global_status);
6874}
6875
ff9d07a0
ZY		 6876static struct perf_guest_info_callbacks kvm_guest_cbs = {
6877 .is_in_guest = kvm_is_in_guest,
6878 .is_user_mode = kvm_is_user_mode,
6879 .get_guest_ip = kvm_get_guest_ip,
8479e04e 6880 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
ff9d07a0
ZY		 6881};
6882
ce88decf
XG		 6883static void kvm_set_mmio_spte_mask(void)
6884{
6885 u64 mask;
6886 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6887
6888 /*
6889 * Set the reserved bits and the present bit of an paging-structure
6890 * entry to generate page fault with PFER.RSV = 1.
6891 */
28a1f3ac
JS		 6892
6893 /*
6894 * Mask the uppermost physical address bit, which would be reserved as
6895 * long as the supported physical address width is less than 52.
6896 */
6897 mask = 1ull << 51;
885032b9 6898
885032b9 6899 /* Set the present bit. */
ce88decf
XG		 6900 mask |= 1ull;
6901
ce88decf
XG		 6902 /*
6903 * If reserved bit is not supported, clear the present bit to disable
6904 * mmio page fault.
6905 */
7288bde1 6906 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
ce88decf 6907 mask &= ~1ull;
ce88decf 6908
dcdca5fe 6909 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6910}
6911
16e8d74d
MT		 6912#ifdef CONFIG_X86_64
6913static void pvclock_gtod_update_fn(struct work_struct *work)
6914{
d828199e
MT		 6915 struct kvm *kvm;
6916
6917 struct kvm_vcpu *vcpu;
6918 int i;
6919
2f303b74 6920 spin_lock(&kvm_lock);
d828199e
MT		 6921 list_for_each_entry(kvm, &vm_list, vm_list)
6922 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6923 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6924 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6925 spin_unlock(&kvm_lock);
16e8d74d
MT		 6926}
6927
6928static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6929
6930/*
6931 * Notification about pvclock gtod data update.
6932 */
6933static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6934 void *priv)
6935{
6936 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6937 struct timekeeper *tk = priv;
6938
6939 update_pvclock_gtod(tk);
6940
6941 /* disable master clock if host does not trust, or does not
b0c39dc6 6942 * use, TSC based clocksource.
16e8d74d 6943 */
b0c39dc6 6944 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6945 atomic_read(&kvm_guest_has_master_clock) != 0)
6946 queue_work(system_long_wq, &pvclock_gtod_work);
6947
6948 return 0;
6949}
6950
6951static struct notifier_block pvclock_gtod_notifier = {
6952 .notifier_call = pvclock_gtod_notify,
6953};
6954#endif
6955
f8c16bba 6956int kvm_arch_init(void *opaque)
043405e1 6957{
b820cc0c 6958 int r;
6b61edf7 6959 struct kvm_x86_ops *ops = opaque;
f8c16bba 6960
f8c16bba
ZX		 6961 if (kvm_x86_ops) {
6962 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6963 r = -EEXIST;
6964 goto out;
f8c16bba
ZX		 6965 }
6966
6967 if (!ops->cpu_has_kvm_support()) {
6968 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6969 r = -EOPNOTSUPP;
6970 goto out;
f8c16bba
ZX		 6971 }
6972 if (ops->disabled_by_bios()) {
6973 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6974 r = -EOPNOTSUPP;
6975 goto out;
f8c16bba
ZX		 6976 }
6977
b666a4b6
MO		 6978 /*
6979 * KVM explicitly assumes that the guest has an FPU and
6980 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
6981 * vCPU's FPU state as a fxregs_state struct.
6982 */
6983 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
6984 printk(KERN_ERR "kvm: inadequate fpu\n");
6985 r = -EOPNOTSUPP;
6986 goto out;
6987 }
6988
013f6a5d 6989 r = -ENOMEM;
ed8e4812 6990 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 6991 __alignof__(struct fpu), SLAB_ACCOUNT,
6992 NULL);
6993 if (!x86_fpu_cache) {
6994 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
6995 goto out;
6996 }
6997
013f6a5d
MT		 6998 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6999 if (!shared_msrs) {
7000 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 7001 goto out_free_x86_fpu_cache;
013f6a5d
MT		 7002 }
7003
97db56ce
AK		 7004 r = kvm_mmu_module_init();
7005 if (r)
013f6a5d 7006 goto out_free_percpu;
97db56ce 7007
ce88decf 7008 kvm_set_mmio_spte_mask();
97db56ce 7009
f8c16bba 7010 kvm_x86_ops = ops;
920c8377 7011
7b52345e 7012 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 7013 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 7014 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 7015 kvm_timer_init();
c8076604 7016
ff9d07a0
ZY		 7017 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7018
d366bf7e 7019 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 7020 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7021
c5cc421b 7022 kvm_lapic_init();
16e8d74d
MT		 7023#ifdef CONFIG_X86_64
7024 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 7025
5fa4ec9c 7026 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 7027 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 7028#endif
7029
f8c16bba 7030 return 0;
56c6d28a 7031
013f6a5d
MT		 7032out_free_percpu:
7033 free_percpu(shared_msrs);
b666a4b6
MO		 7034out_free_x86_fpu_cache:
7035 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7036out:
56c6d28a 7037 return r;
043405e1 7038}
8776e519 7039
f8c16bba
ZX		 7040void kvm_arch_exit(void)
7041{
0092e434 7042#ifdef CONFIG_X86_64
5fa4ec9c 7043 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 7044 clear_hv_tscchange_cb();
7045#endif
cef84c30 7046 kvm_lapic_exit();
ff9d07a0
ZY		 7047 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7048
888d256e
JK		 7049 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7050 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7051 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7052 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7053#ifdef CONFIG_X86_64
7054 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7055#endif
f8c16bba 7056 kvm_x86_ops = NULL;
56c6d28a 7057 kvm_mmu_module_exit();
013f6a5d 7058 free_percpu(shared_msrs);
b666a4b6 7059 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7060}
f8c16bba 7061
5cb56059 7062int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7063{
7064 ++vcpu->stat.halt_exits;
35754c98 7065 if (lapic_in_kernel(vcpu)) {
a4535290 7066 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7067 return 1;
7068 } else {
7069 vcpu->run->exit_reason = KVM_EXIT_HLT;
7070 return 0;
7071 }
7072}
5cb56059
JS		 7073EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7074
7075int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7076{
6affcbed
KH		 7077 int ret = kvm_skip_emulated_instruction(vcpu);
7078 /*
7079 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7080 * KVM_EXIT_DEBUG here.
7081 */
7082 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7083}
8776e519
HB		 7084EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7085
8ef81a9a 7086#ifdef CONFIG_X86_64
55dd00a7
MT		 7087static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7088 unsigned long clock_type)
7089{
7090 struct kvm_clock_pairing clock_pairing;
899a31f5 7091 struct timespec64 ts;
80fbd89c 7092 u64 cycle;
55dd00a7
MT		 7093 int ret;
7094
7095 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7096 return -KVM_EOPNOTSUPP;
7097
7098 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7099 return -KVM_EOPNOTSUPP;
7100
7101 clock_pairing.sec = ts.tv_sec;
7102 clock_pairing.nsec = ts.tv_nsec;
7103 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7104 clock_pairing.flags = 0;
bcbfbd8e 7105 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7106
7107 ret = 0;
7108 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7109 sizeof(struct kvm_clock_pairing)))
7110 ret = -KVM_EFAULT;
7111
7112 return ret;
7113}
8ef81a9a 7114#endif
55dd00a7 7115
6aef266c
SV		 7116/*
7117 * kvm_pv_kick_cpu_op: Kick a vcpu.
7118 *
7119 * @apicid - apicid of vcpu to be kicked.
7120 */
7121static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7122{
24d2166b 7123 struct kvm_lapic_irq lapic_irq;
6aef266c 7124
24d2166b
R		 7125 lapic_irq.shorthand = 0;
7126 lapic_irq.dest_mode = 0;
ebd28fcb 7127 lapic_irq.level = 0;
24d2166b 7128 lapic_irq.dest_id = apicid;
93bbf0b8 7129 lapic_irq.msi_redir_hint = false;
6aef266c 7130
24d2166b 7131 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7132 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7133}
7134
d62caabb
AS		 7135void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7136{
f7589cca
PB		 7137 if (!lapic_in_kernel(vcpu)) {
7138 WARN_ON_ONCE(vcpu->arch.apicv_active);
7139 return;
7140 }
7141 if (!vcpu->arch.apicv_active)
7142 return;
7143
d62caabb
AS		 7144 vcpu->arch.apicv_active = false;
7145 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7146}
7147
8776e519
HB		 7148int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7149{
7150 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7151 int op_64_bit;
8776e519 7152
696ca779
RK		 7153 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7154 return kvm_hv_hypercall(vcpu);
55cd8e5a 7155
5fdbf976
MT		 7156 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
7157 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
7158 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
7159 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
7160 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 7161
229456fc 7162 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7163
a449c7aa
NA		 7164 op_64_bit = is_64_bit_mode(vcpu);
7165 if (!op_64_bit) {
8776e519
HB		 7166 nr &= 0xFFFFFFFF;
7167 a0 &= 0xFFFFFFFF;
7168 a1 &= 0xFFFFFFFF;
7169 a2 &= 0xFFFFFFFF;
7170 a3 &= 0xFFFFFFFF;
7171 }
7172
07708c4a
JK		 7173 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7174 ret = -KVM_EPERM;
696ca779 7175 goto out;
07708c4a
JK		 7176 }
7177
8776e519 7178 switch (nr) {
b93463aa
AK		 7179 case KVM_HC_VAPIC_POLL_IRQ:
7180 ret = 0;
7181 break;
6aef266c
SV		 7182 case KVM_HC_KICK_CPU:
7183 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7184 ret = 0;
7185 break;
8ef81a9a 7186#ifdef CONFIG_X86_64
55dd00a7
MT		 7187 case KVM_HC_CLOCK_PAIRING:
7188 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7189 break;
1ed199a4 7190#endif
4180bf1b
WL		 7191 case KVM_HC_SEND_IPI:
7192 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7193 break;
8776e519
HB		 7194 default:
7195 ret = -KVM_ENOSYS;
7196 break;
7197 }
696ca779 7198out:
a449c7aa
NA		 7199 if (!op_64_bit)
7200 ret = (u32)ret;
5fdbf976 7201 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 7202
f11c3a8d 7203 ++vcpu->stat.hypercalls;
6356ee0c 7204 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7205}
7206EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7207
b6785def 7208static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7209{
d6aa1000 7210 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7211 char instruction[3];
5fdbf976 7212 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7213
8776e519 7214 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7215
ce2e852e
DV		 7216 return emulator_write_emulated(ctxt, rip, instruction, 3,
7217 &ctxt->exception);
8776e519
HB		 7218}
7219
851ba692 7220static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7221{
782d422b
MG		 7222 return vcpu->run->request_interrupt_window &&
7223 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7224}
7225
851ba692 7226static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7227{
851ba692
AK		 7228 struct kvm_run *kvm_run = vcpu->run;
7229
91586a3b 7230 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7231 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7232 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7233 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7234 kvm_run->ready_for_interrupt_injection =
7235 pic_in_kernel(vcpu->kvm) ||
782d422b 7236 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7237}
7238
95ba8273
GN		 7239static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7240{
7241 int max_irr, tpr;
7242
7243 if (!kvm_x86_ops->update_cr8_intercept)
7244 return;
7245
bce87cce 7246 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7247 return;
7248
d62caabb
AS		 7249 if (vcpu->arch.apicv_active)
7250 return;
7251
8db3baa2
GN		 7252 if (!vcpu->arch.apic->vapic_addr)
7253 max_irr = kvm_lapic_find_highest_irr(vcpu);
7254 else
7255 max_irr = -1;
95ba8273
GN		 7256
7257 if (max_irr != -1)
7258 max_irr >>= 4;
7259
7260 tpr = kvm_lapic_get_cr8(vcpu);
7261
7262 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7263}
7264
b6b8a145 7265static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7266{
b6b8a145
JK		 7267 int r;
7268
95ba8273 7269 /* try to reinject previous events if any */
664f8e26 7270
1a680e35
LA		 7271 if (vcpu->arch.exception.injected)
7272 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7273 /*
a042c26f
LA		 7274 * Do not inject an NMI or interrupt if there is a pending
7275 * exception. Exceptions and interrupts are recognized at
7276 * instruction boundaries, i.e. the start of an instruction.
7277 * Trap-like exceptions, e.g. #DB, have higher priority than
7278 * NMIs and interrupts, i.e. traps are recognized before an
7279 * NMI/interrupt that's pending on the same instruction.
7280 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7281 * priority, but are only generated (pended) during instruction
7282 * execution, i.e. a pending fault-like exception means the
7283 * fault occurred on the *previous* instruction and must be
7284 * serviced prior to recognizing any new events in order to
7285 * fully complete the previous instruction.
664f8e26 7286 */
1a680e35
LA		 7287 else if (!vcpu->arch.exception.pending) {
7288 if (vcpu->arch.nmi_injected)
664f8e26 7289 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7290 else if (vcpu->arch.interrupt.injected)
664f8e26 7291 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7292 }
7293
1a680e35
LA		 7294 /*
7295 * Call check_nested_events() even if we reinjected a previous event
7296 * in order for caller to determine if it should require immediate-exit
7297 * from L2 to L1 due to pending L1 events which require exit
7298 * from L2 to L1.
7299 */
664f8e26
WL		 7300 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7301 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7302 if (r != 0)
7303 return r;
7304 }
7305
7306 /* try to inject new event if pending */
b59bb7bd 7307 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7308 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7309 vcpu->arch.exception.has_error_code,
7310 vcpu->arch.exception.error_code);
d6e8c854 7311
1a680e35 7312 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7313 vcpu->arch.exception.pending = false;
7314 vcpu->arch.exception.injected = true;
7315
d6e8c854
NA		 7316 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7317 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7318 X86_EFLAGS_RF);
7319
f10c729f
JM		 7320 if (vcpu->arch.exception.nr == DB_VECTOR) {
7321 /*
7322 * This code assumes that nSVM doesn't use
7323 * check_nested_events(). If it does, the
7324 * DR6/DR7 changes should happen before L1
7325 * gets a #VMEXIT for an intercepted #DB in
7326 * L2. (Under VMX, on the other hand, the
7327 * DR6/DR7 changes should not happen in the
7328 * event of a VM-exit to L1 for an intercepted
7329 * #DB in L2.)
7330 */
7331 kvm_deliver_exception_payload(vcpu);
7332 if (vcpu->arch.dr7 & DR7_GD) {
7333 vcpu->arch.dr7 &= ~DR7_GD;
7334 kvm_update_dr7(vcpu);
7335 }
6bdf0662
NA		 7336 }
7337
cfcd20e5 7338 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7339 }
7340
7341 /* Don't consider new event if we re-injected an event */
7342 if (kvm_event_needs_reinjection(vcpu))
7343 return 0;
7344
7345 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7346 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7347 vcpu->arch.smi_pending = false;
52797bf9 7348 ++vcpu->arch.smi_count;
ee2cd4b7 7349 enter_smm(vcpu);
c43203ca 7350 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7351 --vcpu->arch.nmi_pending;
7352 vcpu->arch.nmi_injected = true;
7353 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7354 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7355 /*
7356 * Because interrupts can be injected asynchronously, we are
7357 * calling check_nested_events again here to avoid a race condition.
7358 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7359 * proposal and current concerns. Perhaps we should be setting
7360 * KVM_REQ_EVENT only on certain events and not unconditionally?
7361 */
7362 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7363 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7364 if (r != 0)
7365 return r;
7366 }
95ba8273 7367 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7368 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7369 false);
7370 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7371 }
7372 }
ee2cd4b7 7373
b6b8a145 7374 return 0;
95ba8273
GN		 7375}
7376
7460fb4a
AK		 7377static void process_nmi(struct kvm_vcpu *vcpu)
7378{
7379 unsigned limit = 2;
7380
7381 /*
7382 * x86 is limited to one NMI running, and one NMI pending after it.
7383 * If an NMI is already in progress, limit further NMIs to just one.
7384 * Otherwise, allow two (and we'll inject the first one immediately).
7385 */
7386 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7387 limit = 1;
7388
7389 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7390 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7391 kvm_make_request(KVM_REQ_EVENT, vcpu);
7392}
7393
ee2cd4b7 7394static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7395{
7396 u32 flags = 0;
7397 flags |= seg->g << 23;
7398 flags |= seg->db << 22;
7399 flags |= seg->l << 21;
7400 flags |= seg->avl << 20;
7401 flags |= seg->present << 15;
7402 flags |= seg->dpl << 13;
7403 flags |= seg->s << 12;
7404 flags |= seg->type << 8;
7405 return flags;
7406}
7407
ee2cd4b7 7408static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7409{
7410 struct kvm_segment seg;
7411 int offset;
7412
7413 kvm_get_segment(vcpu, &seg, n);
7414 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7415
7416 if (n < 3)
7417 offset = 0x7f84 + n * 12;
7418 else
7419 offset = 0x7f2c + (n - 3) * 12;
7420
7421 put_smstate(u32, buf, offset + 8, seg.base);
7422 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7423 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7424}
7425
efbb288a 7426#ifdef CONFIG_X86_64
ee2cd4b7 7427static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7428{
7429 struct kvm_segment seg;
7430 int offset;
7431 u16 flags;
7432
7433 kvm_get_segment(vcpu, &seg, n);
7434 offset = 0x7e00 + n * 16;
7435
ee2cd4b7 7436 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7437 put_smstate(u16, buf, offset, seg.selector);
7438 put_smstate(u16, buf, offset + 2, flags);
7439 put_smstate(u32, buf, offset + 4, seg.limit);
7440 put_smstate(u64, buf, offset + 8, seg.base);
7441}
efbb288a 7442#endif
660a5d51 7443
ee2cd4b7 7444static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7445{
7446 struct desc_ptr dt;
7447 struct kvm_segment seg;
7448 unsigned long val;
7449 int i;
7450
7451 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7452 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7453 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7454 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7455
7456 for (i = 0; i < 8; i++)
7457 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7458
7459 kvm_get_dr(vcpu, 6, &val);
7460 put_smstate(u32, buf, 0x7fcc, (u32)val);
7461 kvm_get_dr(vcpu, 7, &val);
7462 put_smstate(u32, buf, 0x7fc8, (u32)val);
7463
7464 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7465 put_smstate(u32, buf, 0x7fc4, seg.selector);
7466 put_smstate(u32, buf, 0x7f64, seg.base);
7467 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7468 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7469
7470 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7471 put_smstate(u32, buf, 0x7fc0, seg.selector);
7472 put_smstate(u32, buf, 0x7f80, seg.base);
7473 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7474 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7475
7476 kvm_x86_ops->get_gdt(vcpu, &dt);
7477 put_smstate(u32, buf, 0x7f74, dt.address);
7478 put_smstate(u32, buf, 0x7f70, dt.size);
7479
7480 kvm_x86_ops->get_idt(vcpu, &dt);
7481 put_smstate(u32, buf, 0x7f58, dt.address);
7482 put_smstate(u32, buf, 0x7f54, dt.size);
7483
7484 for (i = 0; i < 6; i++)
ee2cd4b7 7485 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7486
7487 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7488
7489 /* revision id */
7490 put_smstate(u32, buf, 0x7efc, 0x00020000);
7491 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7492}
7493
b68f3cc7 7494#ifdef CONFIG_X86_64
ee2cd4b7 7495static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7496{
660a5d51
PB		 7497 struct desc_ptr dt;
7498 struct kvm_segment seg;
7499 unsigned long val;
7500 int i;
7501
7502 for (i = 0; i < 16; i++)
7503 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7504
7505 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7506 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7507
7508 kvm_get_dr(vcpu, 6, &val);
7509 put_smstate(u64, buf, 0x7f68, val);
7510 kvm_get_dr(vcpu, 7, &val);
7511 put_smstate(u64, buf, 0x7f60, val);
7512
7513 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7514 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7515 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7516
7517 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7518
7519 /* revision id */
7520 put_smstate(u32, buf, 0x7efc, 0x00020064);
7521
7522 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7523
7524 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7525 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7526 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7527 put_smstate(u32, buf, 0x7e94, seg.limit);
7528 put_smstate(u64, buf, 0x7e98, seg.base);
7529
7530 kvm_x86_ops->get_idt(vcpu, &dt);
7531 put_smstate(u32, buf, 0x7e84, dt.size);
7532 put_smstate(u64, buf, 0x7e88, dt.address);
7533
7534 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7535 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7536 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7537 put_smstate(u32, buf, 0x7e74, seg.limit);
7538 put_smstate(u64, buf, 0x7e78, seg.base);
7539
7540 kvm_x86_ops->get_gdt(vcpu, &dt);
7541 put_smstate(u32, buf, 0x7e64, dt.size);
7542 put_smstate(u64, buf, 0x7e68, dt.address);
7543
7544 for (i = 0; i < 6; i++)
ee2cd4b7 7545 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7546}
b68f3cc7 7547#endif
660a5d51 7548
ee2cd4b7 7549static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7550{
660a5d51 7551 struct kvm_segment cs, ds;
18c3626e 7552 struct desc_ptr dt;
660a5d51
PB		 7553 char buf[512];
7554 u32 cr0;
7555
660a5d51 7556 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7557 memset(buf, 0, 512);
b68f3cc7 7558#ifdef CONFIG_X86_64
d6321d49 7559 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7560 enter_smm_save_state_64(vcpu, buf);
660a5d51 7561 else
b68f3cc7 7562#endif
ee2cd4b7 7563 enter_smm_save_state_32(vcpu, buf);
660a5d51 7564
0234bf88
LP		 7565 /*
7566 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7567 * vCPU state (e.g. leave guest mode) after we've saved the state into
7568 * the SMM state-save area.
7569 */
7570 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7571
7572 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7573 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7574
7575 if (kvm_x86_ops->get_nmi_mask(vcpu))
7576 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7577 else
7578 kvm_x86_ops->set_nmi_mask(vcpu, true);
7579
7580 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7581 kvm_rip_write(vcpu, 0x8000);
7582
7583 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7584 kvm_x86_ops->set_cr0(vcpu, cr0);
7585 vcpu->arch.cr0 = cr0;
7586
7587 kvm_x86_ops->set_cr4(vcpu, 0);
7588
18c3626e
PB		 7589 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7590 dt.address = dt.size = 0;
7591 kvm_x86_ops->set_idt(vcpu, &dt);
7592
660a5d51
PB		 7593 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7594
7595 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7596 cs.base = vcpu->arch.smbase;
7597
7598 ds.selector = 0;
7599 ds.base = 0;
7600
7601 cs.limit = ds.limit = 0xffffffff;
7602 cs.type = ds.type = 0x3;
7603 cs.dpl = ds.dpl = 0;
7604 cs.db = ds.db = 0;
7605 cs.s = ds.s = 1;
7606 cs.l = ds.l = 0;
7607 cs.g = ds.g = 1;
7608 cs.avl = ds.avl = 0;
7609 cs.present = ds.present = 1;
7610 cs.unusable = ds.unusable = 0;
7611 cs.padding = ds.padding = 0;
7612
7613 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7614 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7615 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7616 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7617 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7618 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7619
b68f3cc7 7620#ifdef CONFIG_X86_64
d6321d49 7621 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7622 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7623#endif
660a5d51
PB		 7624
7625 kvm_update_cpuid(vcpu);
7626 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7627}
7628
ee2cd4b7 7629static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7630{
7631 vcpu->arch.smi_pending = true;
7632 kvm_make_request(KVM_REQ_EVENT, vcpu);
7633}
7634
2860c4b1
PB		 7635void kvm_make_scan_ioapic_request(struct kvm *kvm)
7636{
7637 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7638}
7639
3d81bc7e 7640static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7641{
dcbd3e49 7642 if (!kvm_apic_present(vcpu))
3d81bc7e 7643 return;
c7c9c56c 7644
6308630b 7645 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7646
b053b2ae 7647 if (irqchip_split(vcpu->kvm))
6308630b 7648 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7649 else {
fa59cc00 7650 if (vcpu->arch.apicv_active)
d62caabb 7651 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7652 if (ioapic_in_kernel(vcpu->kvm))
7653 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7654 }
e40ff1d6
LA		 7655
7656 if (is_guest_mode(vcpu))
7657 vcpu->arch.load_eoi_exitmap_pending = true;
7658 else
7659 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7660}
7661
7662static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7663{
7664 u64 eoi_exit_bitmap[4];
7665
7666 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7667 return;
7668
5c919412
AS		 7669 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7670 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7671 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7672}
7673
93065ac7
MH		 7674int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7675 unsigned long start, unsigned long end,
7676 bool blockable)
b1394e74
RK		 7677{
7678 unsigned long apic_address;
7679
7680 /*
7681 * The physical address of apic access page is stored in the VMCS.
7682 * Update it when it becomes invalid.
7683 */
7684 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7685 if (start <= apic_address && apic_address < end)
7686 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7687
7688 return 0;
b1394e74
RK		 7689}
7690
4256f43f
TC		 7691void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7692{
c24ae0dc
TC		 7693 struct page *page = NULL;
7694
35754c98 7695 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7696 return;
7697
4256f43f
TC		 7698 if (!kvm_x86_ops->set_apic_access_page_addr)
7699 return;
7700
c24ae0dc 7701 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7702 if (is_error_page(page))
7703 return;
c24ae0dc
TC		 7704 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7705
7706 /*
7707 * Do not pin apic access page in memory, the MMU notifier
7708 * will call us again if it is migrated or swapped out.
7709 */
7710 put_page(page);
4256f43f
TC		 7711}
7712EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7713
d264ee0c
SC		 7714void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7715{
7716 smp_send_reschedule(vcpu->cpu);
7717}
7718EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7719
9357d939 7720/*
362c698f 7721 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7722 * exiting to the userspace. Otherwise, the value will be returned to the
7723 * userspace.
7724 */
851ba692 7725static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7726{
7727 int r;
62a193ed
MG		 7728 bool req_int_win =
7729 dm_request_for_irq_injection(vcpu) &&
7730 kvm_cpu_accept_dm_intr(vcpu);
7731
730dca42 7732 bool req_immediate_exit = false;
b6c7a5dc 7733
2fa6e1e1 7734 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7735 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7736 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7737 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7738 kvm_mmu_unload(vcpu);
a8eeb04a 7739 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7740 __kvm_migrate_timers(vcpu);
d828199e
MT		 7741 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7742 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7743 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7744 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7745 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7746 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7747 if (unlikely(r))
7748 goto out;
7749 }
a8eeb04a 7750 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7751 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7752 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7753 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7754 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7755 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7756 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7757 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7758 r = 0;
7759 goto out;
7760 }
a8eeb04a 7761 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7762 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7763 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7764 r = 0;
7765 goto out;
7766 }
af585b92
GN		 7767 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7768 /* Page is swapped out. Do synthetic halt */
7769 vcpu->arch.apf.halted = true;
7770 r = 1;
7771 goto out;
7772 }
c9aaa895
GC		 7773 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7774 record_steal_time(vcpu);
64d60670
PB		 7775 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7776 process_smi(vcpu);
7460fb4a
AK		 7777 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7778 process_nmi(vcpu);
f5132b01 7779 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7780 kvm_pmu_handle_event(vcpu);
f5132b01 7781 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7782 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7783 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7784 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7785 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7786 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7787 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7788 vcpu->run->eoi.vector =
7789 vcpu->arch.pending_ioapic_eoi;
7790 r = 0;
7791 goto out;
7792 }
7793 }
3d81bc7e
YZ		 7794 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7795 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7796 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7797 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7798 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7799 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7800 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7801 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7802 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7803 r = 0;
7804 goto out;
7805 }
e516cebb
AS		 7806 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7807 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7808 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7809 r = 0;
7810 goto out;
7811 }
db397571
AS		 7812 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7813 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7814 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7815 r = 0;
7816 goto out;
7817 }
f3b138c5
AS		 7818
7819 /*
7820 * KVM_REQ_HV_STIMER has to be processed after
7821 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7822 * depend on the guest clock being up-to-date
7823 */
1f4b34f8
AS		 7824 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7825 kvm_hv_process_stimers(vcpu);
2f52d58c 7826 }
b93463aa 7827
b463a6f7 7828 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7829 ++vcpu->stat.req_event;
66450a21
JK		 7830 kvm_apic_accept_events(vcpu);
7831 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7832 r = 1;
7833 goto out;
7834 }
7835
b6b8a145
JK		 7836 if (inject_pending_event(vcpu, req_int_win) != 0)
7837 req_immediate_exit = true;
321c5658 7838 else {
cc3d967f 7839 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7840 *
cc3d967f
LP		 7841 * SMIs have three cases:
7842 * 1) They can be nested, and then there is nothing to
7843 * do here because RSM will cause a vmexit anyway.
7844 * 2) There is an ISA-specific reason why SMI cannot be
7845 * injected, and the moment when this changes can be
7846 * intercepted.
7847 * 3) Or the SMI can be pending because
7848 * inject_pending_event has completed the injection
7849 * of an IRQ or NMI from the previous vmexit, and
7850 * then we request an immediate exit to inject the
7851 * SMI.
c43203ca
PB		 7852 */
7853 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7854 if (!kvm_x86_ops->enable_smi_window(vcpu))
7855 req_immediate_exit = true;
321c5658
YS		 7856 if (vcpu->arch.nmi_pending)
7857 kvm_x86_ops->enable_nmi_window(vcpu);
7858 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7859 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7860 WARN_ON(vcpu->arch.exception.pending);
321c5658 7861 }
b463a6f7
AK		 7862
7863 if (kvm_lapic_enabled(vcpu)) {
7864 update_cr8_intercept(vcpu);
7865 kvm_lapic_sync_to_vapic(vcpu);
7866 }
7867 }
7868
d8368af8
AK		 7869 r = kvm_mmu_reload(vcpu);
7870 if (unlikely(r)) {
d905c069 7871 goto cancel_injection;
d8368af8
AK		 7872 }
7873
b6c7a5dc
HB		 7874 preempt_disable();
7875
7876 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7877
7878 /*
7879 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7880 * IPI are then delayed after guest entry, which ensures that they
7881 * result in virtual interrupt delivery.
7882 */
7883 local_irq_disable();
6b7e2d09
XG		 7884 vcpu->mode = IN_GUEST_MODE;
7885
01b71917
MT		 7886 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7887
0f127d12 7888 /*
b95234c8 7889 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7890 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 7891 *
81b01667 7892 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 7893 * pairs with the memory barrier implicit in pi_test_and_set_on
7894 * (see vmx_deliver_posted_interrupt).
7895 *
7896 * 3) This also orders the write to mode from any reads to the page
7897 * tables done while the VCPU is running. Please see the comment
7898 * in kvm_flush_remote_tlbs.
6b7e2d09 7899 */
01b71917 7900 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7901
b95234c8
PB		 7902 /*
7903 * This handles the case where a posted interrupt was
7904 * notified with kvm_vcpu_kick.
7905 */
fa59cc00
LA		 7906 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7907 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7908
2fa6e1e1 7909 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7910 || need_resched() || signal_pending(current)) {
6b7e2d09 7911 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7912 smp_wmb();
6c142801
AK		 7913 local_irq_enable();
7914 preempt_enable();
01b71917 7915 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7916 r = 1;
d905c069 7917 goto cancel_injection;
6c142801
AK		 7918 }
7919
c43203ca
PB		 7920 if (req_immediate_exit) {
7921 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7922 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7923 }
d6185f20 7924
8b89fe1f 7925 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7926 if (lapic_timer_advance_ns)
7927 wait_lapic_expire(vcpu);
6edaa530 7928 guest_enter_irqoff();
b6c7a5dc 7929
42dbaa5a 7930 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7931 set_debugreg(0, 7);
7932 set_debugreg(vcpu->arch.eff_db[0], 0);
7933 set_debugreg(vcpu->arch.eff_db[1], 1);
7934 set_debugreg(vcpu->arch.eff_db[2], 2);
7935 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7936 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7937 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7938 }
b6c7a5dc 7939
851ba692 7940 kvm_x86_ops->run(vcpu);
b6c7a5dc 7941
c77fb5fe
PB		 7942 /*
7943 * Do this here before restoring debug registers on the host. And
7944 * since we do this before handling the vmexit, a DR access vmexit
7945 * can (a) read the correct value of the debug registers, (b) set
7946 * KVM_DEBUGREG_WONT_EXIT again.
7947 */
7948 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7949 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7950 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7951 kvm_update_dr0123(vcpu);
7952 kvm_update_dr6(vcpu);
7953 kvm_update_dr7(vcpu);
7954 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7955 }
7956
24f1e32c
FW		 7957 /*
7958 * If the guest has used debug registers, at least dr7
7959 * will be disabled while returning to the host.
7960 * If we don't have active breakpoints in the host, we don't
7961 * care about the messed up debug address registers. But if
7962 * we have some of them active, restore the old state.
7963 */
59d8eb53 7964 if (hw_breakpoint_active())
24f1e32c 7965 hw_breakpoint_restore();
42dbaa5a 7966
4ba76538 7967 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7968
6b7e2d09 7969 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7970 smp_wmb();
a547c6db 7971
dd60d217 7972 kvm_before_interrupt(vcpu);
a547c6db 7973 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7974 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7975
7976 ++vcpu->stat.exits;
7977
f2485b3e 7978 guest_exit_irqoff();
b6c7a5dc 7979
f2485b3e 7980 local_irq_enable();
b6c7a5dc
HB		 7981 preempt_enable();
7982
f656ce01 7983 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7984
b6c7a5dc
HB		 7985 /*
7986 * Profile KVM exit RIPs:
7987 */
7988 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7989 unsigned long rip = kvm_rip_read(vcpu);
7990 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7991 }
7992
cc578287
ZA		 7993 if (unlikely(vcpu->arch.tsc_always_catchup))
7994 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7995
5cfb1d5a
MT		 7996 if (vcpu->arch.apic_attention)
7997 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7998
618232e2 7999 vcpu->arch.gpa_available = false;
851ba692 8000 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 8001 return r;
8002
8003cancel_injection:
8004 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 8005 if (unlikely(vcpu->arch.apic_attention))
8006 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 8007out:
8008 return r;
8009}
b6c7a5dc 8010
362c698f
PB		 8011static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8012{
bf9f6ac8
FW		 8013 if (!kvm_arch_vcpu_runnable(vcpu) &&
8014 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 8015 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8016 kvm_vcpu_block(vcpu);
8017 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 8018
8019 if (kvm_x86_ops->post_block)
8020 kvm_x86_ops->post_block(vcpu);
8021
9c8fd1ba
PB		 8022 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8023 return 1;
8024 }
362c698f
PB		 8025
8026 kvm_apic_accept_events(vcpu);
8027 switch(vcpu->arch.mp_state) {
8028 case KVM_MP_STATE_HALTED:
8029 vcpu->arch.pv.pv_unhalted = false;
8030 vcpu->arch.mp_state =
8031 KVM_MP_STATE_RUNNABLE;
b2869f28 8032 /* fall through */
362c698f
PB		 8033 case KVM_MP_STATE_RUNNABLE:
8034 vcpu->arch.apf.halted = false;
8035 break;
8036 case KVM_MP_STATE_INIT_RECEIVED:
8037 break;
8038 default:
8039 return -EINTR;
8040 break;
8041 }
8042 return 1;
8043}
09cec754 8044
5d9bc648
PB		 8045static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8046{
0ad3bed6
PB		 8047 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8048 kvm_x86_ops->check_nested_events(vcpu, false);
8049
5d9bc648
PB		 8050 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8051 !vcpu->arch.apf.halted);
8052}
8053
362c698f 8054static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8055{
8056 int r;
f656ce01 8057 struct kvm *kvm = vcpu->kvm;
d7690175 8058
f656ce01 8059 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8060 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8061
362c698f 8062 for (;;) {
58f800d5 8063 if (kvm_vcpu_running(vcpu)) {
851ba692 8064 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8065 } else {
362c698f 8066 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8067 }
8068
09cec754
GN		 8069 if (r <= 0)
8070 break;
8071
72875d8a 8072 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8073 if (kvm_cpu_has_pending_timer(vcpu))
8074 kvm_inject_pending_timer_irqs(vcpu);
8075
782d422b
MG		 8076 if (dm_request_for_irq_injection(vcpu) &&
8077 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8078 r = 0;
8079 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8080 ++vcpu->stat.request_irq_exits;
362c698f 8081 break;
09cec754 8082 }
af585b92
GN		 8083
8084 kvm_check_async_pf_completion(vcpu);
8085
09cec754
GN		 8086 if (signal_pending(current)) {
8087 r = -EINTR;
851ba692 8088 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8089 ++vcpu->stat.signal_exits;
362c698f 8090 break;
09cec754
GN		 8091 }
8092 if (need_resched()) {
f656ce01 8093 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8094 cond_resched();
f656ce01 8095 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8096 }
b6c7a5dc
HB		 8097 }
8098
f656ce01 8099 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8100
8101 return r;
8102}
8103
716d51ab
GN		 8104static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8105{
8106 int r;
8107 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8108 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 8109 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8110 if (r != EMULATE_DONE)
8111 return 0;
8112 return 1;
8113}
8114
8115static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8116{
8117 BUG_ON(!vcpu->arch.pio.count);
8118
8119 return complete_emulated_io(vcpu);
8120}
8121
f78146b0
AK		 8122/*
8123 * Implements the following, as a state machine:
8124 *
8125 * read:
8126 * for each fragment
87da7e66
XG		 8127 * for each mmio piece in the fragment
8128 * write gpa, len
8129 * exit
8130 * copy data
f78146b0
AK		 8131 * execute insn
8132 *
8133 * write:
8134 * for each fragment
87da7e66
XG		 8135 * for each mmio piece in the fragment
8136 * write gpa, len
8137 * copy data
8138 * exit
f78146b0 8139 */
716d51ab 8140static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8141{
8142 struct kvm_run *run = vcpu->run;
f78146b0 8143 struct kvm_mmio_fragment *frag;
87da7e66 8144 unsigned len;
5287f194 8145
716d51ab 8146 BUG_ON(!vcpu->mmio_needed);
5287f194 8147
716d51ab 8148 /* Complete previous fragment */
87da7e66
XG		 8149 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8150 len = min(8u, frag->len);
716d51ab 8151 if (!vcpu->mmio_is_write)
87da7e66
XG		 8152 memcpy(frag->data, run->mmio.data, len);
8153
8154 if (frag->len <= 8) {
8155 /* Switch to the next fragment. */
8156 frag++;
8157 vcpu->mmio_cur_fragment++;
8158 } else {
8159 /* Go forward to the next mmio piece. */
8160 frag->data += len;
8161 frag->gpa += len;
8162 frag->len -= len;
8163 }
8164
a08d3b3b 8165 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8166 vcpu->mmio_needed = 0;
0912c977
PB		 8167
8168 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8169 if (vcpu->mmio_is_write)
716d51ab
GN		 8170 return 1;
8171 vcpu->mmio_read_completed = 1;
8172 return complete_emulated_io(vcpu);
8173 }
87da7e66 8174
716d51ab
GN		 8175 run->exit_reason = KVM_EXIT_MMIO;
8176 run->mmio.phys_addr = frag->gpa;
8177 if (vcpu->mmio_is_write)
87da7e66
XG		 8178 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8179 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8180 run->mmio.is_write = vcpu->mmio_is_write;
8181 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8182 return 0;
5287f194
AK		 8183}
8184
822f312d
SAS		 8185/* Swap (qemu) user FPU context for the guest FPU context. */
8186static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8187{
8188 preempt_disable();
240c35a3 8189 copy_fpregs_to_fpstate(&current->thread.fpu);
822f312d 8190 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8191 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d
SAS		 8192 ~XFEATURE_MASK_PKRU);
8193 preempt_enable();
8194 trace_kvm_fpu(1);
8195}
8196
8197/* When vcpu_run ends, restore user space FPU context. */
8198static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8199{
8200 preempt_disable();
b666a4b6 8201 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
240c35a3 8202 copy_kernel_to_fpregs(&current->thread.fpu.state);
822f312d
SAS		 8203 preempt_enable();
8204 ++vcpu->stat.fpu_reload;
8205 trace_kvm_fpu(0);
8206}
8207
b6c7a5dc
HB		 8208int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8209{
8210 int r;
b6c7a5dc 8211
accb757d 8212 vcpu_load(vcpu);
20b7035c 8213 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8214 kvm_load_guest_fpu(vcpu);
8215
a4535290 8216 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8217 if (kvm_run->immediate_exit) {
8218 r = -EINTR;
8219 goto out;
8220 }
b6c7a5dc 8221 kvm_vcpu_block(vcpu);
66450a21 8222 kvm_apic_accept_events(vcpu);
72875d8a 8223 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8224 r = -EAGAIN;
a0595000
JS		 8225 if (signal_pending(current)) {
8226 r = -EINTR;
8227 vcpu->run->exit_reason = KVM_EXIT_INTR;
8228 ++vcpu->stat.signal_exits;
8229 }
ac9f6dc0 8230 goto out;
b6c7a5dc
HB		 8231 }
8232
01643c51
KH		 8233 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8234 r = -EINVAL;
8235 goto out;
8236 }
8237
8238 if (vcpu->run->kvm_dirty_regs) {
8239 r = sync_regs(vcpu);
8240 if (r != 0)
8241 goto out;
8242 }
8243
b6c7a5dc 8244 /* re-sync apic's tpr */
35754c98 8245 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8246 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8247 r = -EINVAL;
8248 goto out;
8249 }
8250 }
b6c7a5dc 8251
716d51ab
GN		 8252 if (unlikely(vcpu->arch.complete_userspace_io)) {
8253 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8254 vcpu->arch.complete_userspace_io = NULL;
8255 r = cui(vcpu);
8256 if (r <= 0)
5663d8f9 8257 goto out;
716d51ab
GN		 8258 } else
8259 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8260
460df4c1
PB		 8261 if (kvm_run->immediate_exit)
8262 r = -EINTR;
8263 else
8264 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8265
8266out:
5663d8f9 8267 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8268 if (vcpu->run->kvm_valid_regs)
8269 store_regs(vcpu);
f1d86e46 8270 post_kvm_run_save(vcpu);
20b7035c 8271 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8272
accb757d 8273 vcpu_put(vcpu);
b6c7a5dc
HB		 8274 return r;
8275}
8276
01643c51 8277static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8278{
7ae441ea
GN		 8279 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8280 /*
8281 * We are here if userspace calls get_regs() in the middle of
8282 * instruction emulation. Registers state needs to be copied
4a969980 8283 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8284 * that usually, but some bad designed PV devices (vmware
8285 * backdoor interface) need this to work
8286 */
dd856efa 8287 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8288 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8289 }
5fdbf976
MT		 8290 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
8291 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
8292 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
8293 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
8294 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
8295 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
8296 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8297 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 8298#ifdef CONFIG_X86_64
5fdbf976
MT		 8299 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
8300 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
8301 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
8302 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
8303 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
8304 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
8305 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
8306 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 8307#endif
8308
5fdbf976 8309 regs->rip = kvm_rip_read(vcpu);
91586a3b 8310 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8311}
b6c7a5dc 8312
01643c51
KH		 8313int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8314{
8315 vcpu_load(vcpu);
8316 __get_regs(vcpu, regs);
1fc9b76b 8317 vcpu_put(vcpu);
b6c7a5dc
HB		 8318 return 0;
8319}
8320
01643c51 8321static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8322{
7ae441ea
GN		 8323 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8324 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8325
5fdbf976
MT		 8326 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
8327 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8328 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8329 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8330 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8331 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8332 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8333 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 8334#ifdef CONFIG_X86_64
5fdbf976
MT		 8335 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8336 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8337 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8338 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8339 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8340 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8341 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8342 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 8343#endif
8344
5fdbf976 8345 kvm_rip_write(vcpu, regs->rip);
d73235d1 8346 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8347
b4f14abd
JK		 8348 vcpu->arch.exception.pending = false;
8349
3842d135 8350 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8351}
3842d135 8352
01643c51
KH		 8353int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8354{
8355 vcpu_load(vcpu);
8356 __set_regs(vcpu, regs);
875656fe 8357 vcpu_put(vcpu);
b6c7a5dc
HB		 8358 return 0;
8359}
8360
b6c7a5dc
HB		 8361void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8362{
8363 struct kvm_segment cs;
8364
3e6e0aab 8365 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8366 *db = cs.db;
8367 *l = cs.l;
8368}
8369EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8370
01643c51 8371static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8372{
89a27f4d 8373 struct desc_ptr dt;
b6c7a5dc 8374
3e6e0aab
GT		 8375 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8376 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8377 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8378 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8379 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8380 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8381
3e6e0aab
GT		 8382 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8383 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8384
8385 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8386 sregs->idt.limit = dt.size;
8387 sregs->idt.base = dt.address;
b6c7a5dc 8388 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8389 sregs->gdt.limit = dt.size;
8390 sregs->gdt.base = dt.address;
b6c7a5dc 8391
4d4ec087 8392 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8393 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8394 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8395 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8396 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8397 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8398 sregs->apic_base = kvm_get_apic_base(vcpu);
8399
0e96f31e 8400 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8401
04140b41 8402 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8403 set_bit(vcpu->arch.interrupt.nr,
8404 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8405}
16d7a191 8406
01643c51
KH		 8407int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8408 struct kvm_sregs *sregs)
8409{
8410 vcpu_load(vcpu);
8411 __get_sregs(vcpu, sregs);
bcdec41c 8412 vcpu_put(vcpu);
b6c7a5dc
HB		 8413 return 0;
8414}
8415
62d9f0db
MT		 8416int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8417 struct kvm_mp_state *mp_state)
8418{
fd232561
CD		 8419 vcpu_load(vcpu);
8420
66450a21 8421 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8422 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8423 vcpu->arch.pv.pv_unhalted)
8424 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8425 else
8426 mp_state->mp_state = vcpu->arch.mp_state;
8427
fd232561 8428 vcpu_put(vcpu);
62d9f0db
MT		 8429 return 0;
8430}
8431
8432int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8433 struct kvm_mp_state *mp_state)
8434{
e83dff5e
CD		 8435 int ret = -EINVAL;
8436
8437 vcpu_load(vcpu);
8438
bce87cce 8439 if (!lapic_in_kernel(vcpu) &&
66450a21 8440 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8441 goto out;
66450a21 8442
28bf2888
DH		 8443 /* INITs are latched while in SMM */
8444 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8445 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8446 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8447 goto out;
28bf2888 8448
66450a21
JK		 8449 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8450 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8451 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8452 } else
8453 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8454 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8455
8456 ret = 0;
8457out:
8458 vcpu_put(vcpu);
8459 return ret;
62d9f0db
MT		 8460}
8461
7f3d35fd
KW		 8462int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8463 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8464{
9d74191a 8465 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8466 int ret;
e01c2426 8467
8ec4722d 8468 init_emulate_ctxt(vcpu);
c697518a 8469
7f3d35fd 8470 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8471 has_error_code, error_code);
c697518a 8472
c697518a 8473 if (ret)
19d04437 8474 return EMULATE_FAIL;
37817f29 8475
9d74191a
TY		 8476 kvm_rip_write(vcpu, ctxt->eip);
8477 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8478 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8479 return EMULATE_DONE;
37817f29
IE		 8480}
8481EXPORT_SYMBOL_GPL(kvm_task_switch);
8482
3140c156 8483static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8484{
74fec5b9
TL		 8485 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8486 (sregs->cr4 & X86_CR4_OSXSAVE))
8487 return -EINVAL;
8488
37b95951 8489 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8490 /*
8491 * When EFER.LME and CR0.PG are set, the processor is in
8492 * 64-bit mode (though maybe in a 32-bit code segment).
8493 * CR4.PAE and EFER.LMA must be set.
8494 */
37b95951 8495 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8496 || !(sregs->efer & EFER_LMA))
8497 return -EINVAL;
8498 } else {
8499 /*
8500 * Not in 64-bit mode: EFER.LMA is clear and the code
8501 * segment cannot be 64-bit.
8502 */
8503 if (sregs->efer & EFER_LMA || sregs->cs.l)
8504 return -EINVAL;
8505 }
8506
8507 return 0;
8508}
8509
01643c51 8510static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8511{
58cb628d 8512 struct msr_data apic_base_msr;
b6c7a5dc 8513 int mmu_reset_needed = 0;
c4d21882 8514 int cpuid_update_needed = 0;
63f42e02 8515 int pending_vec, max_bits, idx;
89a27f4d 8516 struct desc_ptr dt;
b4ef9d4e
CD		 8517 int ret = -EINVAL;
8518
f2981033 8519 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8520 goto out;
f2981033 8521
d3802286
JM		 8522 apic_base_msr.data = sregs->apic_base;
8523 apic_base_msr.host_initiated = true;
8524 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8525 goto out;
6d1068b3 8526
89a27f4d
GN		 8527 dt.size = sregs->idt.limit;
8528 dt.address = sregs->idt.base;
b6c7a5dc 8529 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8530 dt.size = sregs->gdt.limit;
8531 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8532 kvm_x86_ops->set_gdt(vcpu, &dt);
8533
ad312c7c 8534 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8535 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8536 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8537 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8538
2d3ad1f4 8539 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8540
f6801dff 8541 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8542 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8543
4d4ec087 8544 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8545 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8546 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8547
fc78f519 8548 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8549 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8550 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8551 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8552 if (cpuid_update_needed)
00b27a3e 8553 kvm_update_cpuid(vcpu);
63f42e02
XG		 8554
8555 idx = srcu_read_lock(&vcpu->kvm->srcu);
d35b34a9 8556 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
9f8fe504 8557 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8558 mmu_reset_needed = 1;
8559 }
63f42e02 8560 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8561
8562 if (mmu_reset_needed)
8563 kvm_mmu_reset_context(vcpu);
8564
a50abc3b 8565 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8566 pending_vec = find_first_bit(
8567 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8568 if (pending_vec < max_bits) {
66fd3f7f 8569 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8570 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8571 }
8572
3e6e0aab
GT		 8573 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8574 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8575 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8576 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8577 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8578 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8579
3e6e0aab
GT		 8580 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8581 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8582
5f0269f5
ME		 8583 update_cr8_intercept(vcpu);
8584
9c3e4aab 8585 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8586 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8587 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8588 !is_protmode(vcpu))
9c3e4aab
MT		 8589 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8590
3842d135
AK		 8591 kvm_make_request(KVM_REQ_EVENT, vcpu);
8592
b4ef9d4e
CD		 8593 ret = 0;
8594out:
01643c51
KH		 8595 return ret;
8596}
8597
8598int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8599 struct kvm_sregs *sregs)
8600{
8601 int ret;
8602
8603 vcpu_load(vcpu);
8604 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8605 vcpu_put(vcpu);
8606 return ret;
b6c7a5dc
HB		 8607}
8608
d0bfb940
JK		 8609int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8610 struct kvm_guest_debug *dbg)
b6c7a5dc 8611{
355be0b9 8612 unsigned long rflags;
ae675ef0 8613 int i, r;
b6c7a5dc 8614
66b56562
CD		 8615 vcpu_load(vcpu);
8616
4f926bf2
JK		 8617 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8618 r = -EBUSY;
8619 if (vcpu->arch.exception.pending)
2122ff5e 8620 goto out;
4f926bf2
JK		 8621 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8622 kvm_queue_exception(vcpu, DB_VECTOR);
8623 else
8624 kvm_queue_exception(vcpu, BP_VECTOR);
8625 }
8626
91586a3b
JK		 8627 /*
8628 * Read rflags as long as potentially injected trace flags are still
8629 * filtered out.
8630 */
8631 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8632
8633 vcpu->guest_debug = dbg->control;
8634 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8635 vcpu->guest_debug = 0;
8636
8637 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8638 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8639 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8640 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8641 } else {
8642 for (i = 0; i < KVM_NR_DB_REGS; i++)
8643 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8644 }
c8639010 8645 kvm_update_dr7(vcpu);
ae675ef0 8646
f92653ee
JK		 8647 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8648 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8649 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8650
91586a3b
JK		 8651 /*
8652 * Trigger an rflags update that will inject or remove the trace
8653 * flags.
8654 */
8655 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8656
a96036b8 8657 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8658
4f926bf2 8659 r = 0;
d0bfb940 8660
2122ff5e 8661out:
66b56562 8662 vcpu_put(vcpu);
b6c7a5dc
HB		 8663 return r;
8664}
8665
8b006791
ZX		 8666/*
8667 * Translate a guest virtual address to a guest physical address.
8668 */
8669int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8670 struct kvm_translation *tr)
8671{
8672 unsigned long vaddr = tr->linear_address;
8673 gpa_t gpa;
f656ce01 8674 int idx;
8b006791 8675
1da5b61d
CD		 8676 vcpu_load(vcpu);
8677
f656ce01 8678 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8679 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8680 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8681 tr->physical_address = gpa;
8682 tr->valid = gpa != UNMAPPED_GVA;
8683 tr->writeable = 1;
8684 tr->usermode = 0;
8b006791 8685
1da5b61d 8686 vcpu_put(vcpu);
8b006791
ZX		 8687 return 0;
8688}
8689
d0752060
HB		 8690int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8691{
1393123e 8692 struct fxregs_state *fxsave;
d0752060 8693
1393123e 8694 vcpu_load(vcpu);
d0752060 8695
b666a4b6 8696 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8697 memcpy(fpu->fpr, fxsave->st_space, 128);
8698 fpu->fcw = fxsave->cwd;
8699 fpu->fsw = fxsave->swd;
8700 fpu->ftwx = fxsave->twd;
8701 fpu->last_opcode = fxsave->fop;
8702 fpu->last_ip = fxsave->rip;
8703 fpu->last_dp = fxsave->rdp;
0e96f31e 8704 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8705
1393123e 8706 vcpu_put(vcpu);
d0752060
HB		 8707 return 0;
8708}
8709
8710int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8711{
6a96bc7f
CD		 8712 struct fxregs_state *fxsave;
8713
8714 vcpu_load(vcpu);
8715
b666a4b6 8716 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8717
d0752060
HB		 8718 memcpy(fxsave->st_space, fpu->fpr, 128);
8719 fxsave->cwd = fpu->fcw;
8720 fxsave->swd = fpu->fsw;
8721 fxsave->twd = fpu->ftwx;
8722 fxsave->fop = fpu->last_opcode;
8723 fxsave->rip = fpu->last_ip;
8724 fxsave->rdp = fpu->last_dp;
0e96f31e 8725 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8726
6a96bc7f 8727 vcpu_put(vcpu);
d0752060
HB		 8728 return 0;
8729}
8730
01643c51
KH		 8731static void store_regs(struct kvm_vcpu *vcpu)
8732{
8733 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8734
8735 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8736 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8737
8738 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8739 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8740
8741 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8742 kvm_vcpu_ioctl_x86_get_vcpu_events(
8743 vcpu, &vcpu->run->s.regs.events);
8744}
8745
8746static int sync_regs(struct kvm_vcpu *vcpu)
8747{
8748 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8749 return -EINVAL;
8750
8751 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8752 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8753 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8754 }
8755 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8756 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8757 return -EINVAL;
8758 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8759 }
8760 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8761 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8762 vcpu, &vcpu->run->s.regs.events))
8763 return -EINVAL;
8764 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8765 }
8766
8767 return 0;
8768}
8769
0ee6a517 8770static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8771{
b666a4b6 8772 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 8773 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 8774 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 8775 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8776
2acf923e
DC		 8777 /*
8778 * Ensure guest xcr0 is valid for loading
8779 */
d91cab78 8780 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8781
ad312c7c 8782 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8783}
d0752060 8784
e9b11c17
ZX		 8785void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8786{
bd768e14
IY		 8787 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8788
12f9a48f 8789 kvmclock_reset(vcpu);
7f1ea208 8790
e9b11c17 8791 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8792 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8793}
8794
8795struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8796 unsigned int id)
8797{
c447e76b
LL		 8798 struct kvm_vcpu *vcpu;
8799
b0c39dc6 8800 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8801 printk_once(KERN_WARNING
8802 "kvm: SMP vm created on host with unstable TSC; "
8803 "guest TSC will not be reliable\n");
c447e76b
LL		 8804
8805 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8806
c447e76b 8807 return vcpu;
26e5215f 8808}
e9b11c17 8809
26e5215f
AK		 8810int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8811{
0cf9135b 8812 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 8813 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 8814 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8815 vcpu_load(vcpu);
d28bc9dd 8816 kvm_vcpu_reset(vcpu, false);
e1732991 8817 kvm_init_mmu(vcpu, false);
e9b11c17 8818 vcpu_put(vcpu);
ec7660cc 8819 return 0;
e9b11c17
ZX		 8820}
8821
31928aa5 8822void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8823{
8fe8ab46 8824 struct msr_data msr;
332967a3 8825 struct kvm *kvm = vcpu->kvm;
42897d86 8826
d3457c87
RK		 8827 kvm_hv_vcpu_postcreate(vcpu);
8828
ec7660cc 8829 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8830 return;
ec7660cc 8831 vcpu_load(vcpu);
8fe8ab46
WA		 8832 msr.data = 0x0;
8833 msr.index = MSR_IA32_TSC;
8834 msr.host_initiated = true;
8835 kvm_write_tsc(vcpu, &msr);
42897d86 8836 vcpu_put(vcpu);
ec7660cc 8837 mutex_unlock(&vcpu->mutex);
42897d86 8838
630994b3
MT		 8839 if (!kvmclock_periodic_sync)
8840 return;
8841
332967a3
AJ		 8842 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8843 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8844}
8845
d40ccc62 8846void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8847{
344d9588
GN		 8848 vcpu->arch.apf.msr_val = 0;
8849
ec7660cc 8850 vcpu_load(vcpu);
e9b11c17
ZX		 8851 kvm_mmu_unload(vcpu);
8852 vcpu_put(vcpu);
8853
8854 kvm_x86_ops->vcpu_free(vcpu);
8855}
8856
d28bc9dd 8857void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8858{
b7e31be3
RK		 8859 kvm_lapic_reset(vcpu, init_event);
8860
e69fab5d
PB		 8861 vcpu->arch.hflags = 0;
8862
c43203ca 8863 vcpu->arch.smi_pending = 0;
52797bf9 8864 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8865 atomic_set(&vcpu->arch.nmi_queued, 0);
8866 vcpu->arch.nmi_pending = 0;
448fa4a9 8867 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8868 kvm_clear_interrupt_queue(vcpu);
8869 kvm_clear_exception_queue(vcpu);
664f8e26 8870 vcpu->arch.exception.pending = false;
448fa4a9 8871
42dbaa5a 8872 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8873 kvm_update_dr0123(vcpu);
6f43ed01 8874 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8875 kvm_update_dr6(vcpu);
42dbaa5a 8876 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8877 kvm_update_dr7(vcpu);
42dbaa5a 8878
1119022c
NA		 8879 vcpu->arch.cr2 = 0;
8880
3842d135 8881 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8882 vcpu->arch.apf.msr_val = 0;
c9aaa895 8883 vcpu->arch.st.msr_val = 0;
3842d135 8884
12f9a48f
GC		 8885 kvmclock_reset(vcpu);
8886
af585b92
GN		 8887 kvm_clear_async_pf_completion_queue(vcpu);
8888 kvm_async_pf_hash_reset(vcpu);
8889 vcpu->arch.apf.halted = false;
3842d135 8890
a554d207
WL		 8891 if (kvm_mpx_supported()) {
8892 void *mpx_state_buffer;
8893
8894 /*
8895 * To avoid have the INIT path from kvm_apic_has_events() that be
8896 * called with loaded FPU and does not let userspace fix the state.
8897 */
f775b13e
RR		 8898 if (init_event)
8899 kvm_put_guest_fpu(vcpu);
b666a4b6 8900 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
a554d207
WL		 8901 XFEATURE_MASK_BNDREGS);
8902 if (mpx_state_buffer)
8903 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 8904 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
a554d207
WL		 8905 XFEATURE_MASK_BNDCSR);
8906 if (mpx_state_buffer)
8907 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8908 if (init_event)
8909 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8910 }
8911
64d60670 8912 if (!init_event) {
d28bc9dd 8913 kvm_pmu_reset(vcpu);
64d60670 8914 vcpu->arch.smbase = 0x30000;
db2336a8 8915
db2336a8 8916 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8917
8918 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8919 }
f5132b01 8920
66f7b72e
JS		 8921 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8922 vcpu->arch.regs_avail = ~0;
8923 vcpu->arch.regs_dirty = ~0;
8924
a554d207
WL		 8925 vcpu->arch.ia32_xss = 0;
8926
d28bc9dd 8927 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8928}
8929
2b4a273b 8930void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8931{
8932 struct kvm_segment cs;
8933
8934 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8935 cs.selector = vector << 8;
8936 cs.base = vector << 12;
8937 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8938 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8939}
8940
13a34e06 8941int kvm_arch_hardware_enable(void)
e9b11c17 8942{
ca84d1a2
ZA		 8943 struct kvm *kvm;
8944 struct kvm_vcpu *vcpu;
8945 int i;
0dd6a6ed
ZA		 8946 int ret;
8947 u64 local_tsc;
8948 u64 max_tsc = 0;
8949 bool stable, backwards_tsc = false;
18863bdd
AK		 8950
8951 kvm_shared_msr_cpu_online();
13a34e06 8952 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8953 if (ret != 0)
8954 return ret;
8955
4ea1636b 8956 local_tsc = rdtsc();
b0c39dc6 8957 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8958 list_for_each_entry(kvm, &vm_list, vm_list) {
8959 kvm_for_each_vcpu(i, vcpu, kvm) {
8960 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8961 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8962 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8963 backwards_tsc = true;
8964 if (vcpu->arch.last_host_tsc > max_tsc)
8965 max_tsc = vcpu->arch.last_host_tsc;
8966 }
8967 }
8968 }
8969
8970 /*
8971 * Sometimes, even reliable TSCs go backwards. This happens on
8972 * platforms that reset TSC during suspend or hibernate actions, but
8973 * maintain synchronization. We must compensate. Fortunately, we can
8974 * detect that condition here, which happens early in CPU bringup,
8975 * before any KVM threads can be running. Unfortunately, we can't
8976 * bring the TSCs fully up to date with real time, as we aren't yet far
8977 * enough into CPU bringup that we know how much real time has actually
108b249c 8978 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8979 * variables that haven't been updated yet.
8980 *
8981 * So we simply find the maximum observed TSC above, then record the
8982 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8983 * the adjustment will be applied. Note that we accumulate
8984 * adjustments, in case multiple suspend cycles happen before some VCPU
8985 * gets a chance to run again. In the event that no KVM threads get a
8986 * chance to run, we will miss the entire elapsed period, as we'll have
8987 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8988 * loose cycle time. This isn't too big a deal, since the loss will be
8989 * uniform across all VCPUs (not to mention the scenario is extremely
8990 * unlikely). It is possible that a second hibernate recovery happens
8991 * much faster than a first, causing the observed TSC here to be
8992 * smaller; this would require additional padding adjustment, which is
8993 * why we set last_host_tsc to the local tsc observed here.
8994 *
8995 * N.B. - this code below runs only on platforms with reliable TSC,
8996 * as that is the only way backwards_tsc is set above. Also note
8997 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8998 * have the same delta_cyc adjustment applied if backwards_tsc
8999 * is detected. Note further, this adjustment is only done once,
9000 * as we reset last_host_tsc on all VCPUs to stop this from being
9001 * called multiple times (one for each physical CPU bringup).
9002 *
4a969980 9003 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 9004 * will be compensated by the logic in vcpu_load, which sets the TSC to
9005 * catchup mode. This will catchup all VCPUs to real time, but cannot
9006 * guarantee that they stay in perfect synchronization.
9007 */
9008 if (backwards_tsc) {
9009 u64 delta_cyc = max_tsc - local_tsc;
9010 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 9011 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 9012 kvm_for_each_vcpu(i, vcpu, kvm) {
9013 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9014 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 9015 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9016 }
9017
9018 /*
9019 * We have to disable TSC offset matching.. if you were
9020 * booting a VM while issuing an S4 host suspend....
9021 * you may have some problem. Solving this issue is
9022 * left as an exercise to the reader.
9023 */
9024 kvm->arch.last_tsc_nsec = 0;
9025 kvm->arch.last_tsc_write = 0;
9026 }
9027
9028 }
9029 return 0;
e9b11c17
ZX		 9030}
9031
13a34e06 9032void kvm_arch_hardware_disable(void)
e9b11c17 9033{
13a34e06
RK		 9034 kvm_x86_ops->hardware_disable();
9035 drop_user_return_notifiers();
e9b11c17
ZX		 9036}
9037
9038int kvm_arch_hardware_setup(void)
9039{
9e9c3fe4
NA		 9040 int r;
9041
9042 r = kvm_x86_ops->hardware_setup();
9043 if (r != 0)
9044 return r;
9045
35181e86
HZ		 9046 if (kvm_has_tsc_control) {
9047 /*
9048 * Make sure the user can only configure tsc_khz values that
9049 * fit into a signed integer.
273ba457 9050 * A min value is not calculated because it will always
35181e86
HZ		 9051 * be 1 on all machines.
9052 */
9053 u64 max = min(0x7fffffffULL,
9054 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9055 kvm_max_guest_tsc_khz = max;
9056
ad721883 9057 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9058 }
ad721883 9059
9e9c3fe4
NA		 9060 kvm_init_msr_list();
9061 return 0;
e9b11c17
ZX		 9062}
9063
9064void kvm_arch_hardware_unsetup(void)
9065{
9066 kvm_x86_ops->hardware_unsetup();
9067}
9068
9069void kvm_arch_check_processor_compat(void *rtn)
9070{
9071 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 9072}
9073
9074bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9075{
9076 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9077}
9078EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9079
9080bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9081{
9082 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9083}
9084
54e9818f 9085struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9086EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9087
e9b11c17
ZX		 9088int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9089{
9090 struct page *page;
e9b11c17
ZX		 9091 int r;
9092
9aabc88f 9093 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9094 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9095 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9096 else
a4535290 9097 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9098
9099 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9100 if (!page) {
9101 r = -ENOMEM;
9102 goto fail;
9103 }
ad312c7c 9104 vcpu->arch.pio_data = page_address(page);
e9b11c17 9105
cc578287 9106 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9107
e9b11c17
ZX		 9108 r = kvm_mmu_create(vcpu);
9109 if (r < 0)
9110 goto fail_free_pio_data;
9111
26de7988 9112 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9113 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
e9b11c17
ZX		 9114 r = kvm_create_lapic(vcpu);
9115 if (r < 0)
9116 goto fail_mmu_destroy;
54e9818f
GN		 9117 } else
9118 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9119
890ca9ae 9120 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
254272ce 9121 GFP_KERNEL_ACCOUNT);
890ca9ae
HY		 9122 if (!vcpu->arch.mce_banks) {
9123 r = -ENOMEM;
443c39bc 9124 goto fail_free_lapic;
890ca9ae
HY		 9125 }
9126 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9127
254272ce
BG		 9128 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9129 GFP_KERNEL_ACCOUNT)) {
f1797359 9130 r = -ENOMEM;
f5f48ee1 9131 goto fail_free_mce_banks;
f1797359 9132 }
f5f48ee1 9133
0ee6a517 9134 fx_init(vcpu);
66f7b72e 9135
4344ee98 9136 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9137
5a4f55cd
EK		 9138 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9139
74545705
RK		 9140 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9141
af585b92 9142 kvm_async_pf_hash_reset(vcpu);
f5132b01 9143 kvm_pmu_init(vcpu);
af585b92 9144
1c1a9ce9 9145 vcpu->arch.pending_external_vector = -1;
de63ad4c 9146 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9147
5c919412
AS		 9148 kvm_hv_vcpu_init(vcpu);
9149
e9b11c17 9150 return 0;
0ee6a517 9151
f5f48ee1
SY		 9152fail_free_mce_banks:
9153 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9154fail_free_lapic:
9155 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9156fail_mmu_destroy:
9157 kvm_mmu_destroy(vcpu);
9158fail_free_pio_data:
ad312c7c 9159 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9160fail:
9161 return r;
9162}
9163
9164void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9165{
f656ce01
MT		 9166 int idx;
9167
1f4b34f8 9168 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9169 kvm_pmu_destroy(vcpu);
36cb93fd 9170 kfree(vcpu->arch.mce_banks);
e9b11c17 9171 kvm_free_lapic(vcpu);
f656ce01 9172 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9173 kvm_mmu_destroy(vcpu);
f656ce01 9174 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9175 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9176 if (!lapic_in_kernel(vcpu))
54e9818f 9177 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9178}
d19a9cd2 9179
e790d9ef
RK		 9180void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9181{
c595ceee 9182 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9183 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9184}
9185
e08b9637 9186int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9187{
e08b9637
CO		 9188 if (type)
9189 return -EINVAL;
9190
6ef768fa 9191 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9192 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 9193 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9194 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9195
5550af4d
SY		 9196 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9197 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9198 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9199 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9200 &kvm->arch.irq_sources_bitmap);
5550af4d 9201
038f8c11 9202 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9203 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9204 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9205
108b249c 9206 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 9207 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9208
6fbbde9a
DS		 9209 kvm->arch.guest_can_read_msr_platform_info = true;
9210
7e44e449 9211 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9212 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9213
cbc0236a 9214 kvm_hv_init_vm(kvm);
0eb05bf2 9215 kvm_page_track_init(kvm);
13d268ca 9216 kvm_mmu_init_vm(kvm);
0eb05bf2 9217
03543133
SS		 9218 if (kvm_x86_ops->vm_init)
9219 return kvm_x86_ops->vm_init(kvm);
9220
d89f5eff 9221 return 0;
d19a9cd2
ZX		 9222}
9223
9224static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9225{
ec7660cc 9226 vcpu_load(vcpu);
d19a9cd2
ZX		 9227 kvm_mmu_unload(vcpu);
9228 vcpu_put(vcpu);
9229}
9230
9231static void kvm_free_vcpus(struct kvm *kvm)
9232{
9233 unsigned int i;
988a2cae 9234 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9235
9236 /*
9237 * Unpin any mmu pages first.
9238 */
af585b92
GN		 9239 kvm_for_each_vcpu(i, vcpu, kvm) {
9240 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9241 kvm_unload_vcpu_mmu(vcpu);
af585b92 9242 }
988a2cae
GN		 9243 kvm_for_each_vcpu(i, vcpu, kvm)
9244 kvm_arch_vcpu_free(vcpu);
9245
9246 mutex_lock(&kvm->lock);
9247 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9248 kvm->vcpus[i] = NULL;
d19a9cd2 9249
988a2cae
GN		 9250 atomic_set(&kvm->online_vcpus, 0);
9251 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9252}
9253
ad8ba2cd
SY		 9254void kvm_arch_sync_events(struct kvm *kvm)
9255{
332967a3 9256 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9257 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9258 kvm_free_pit(kvm);
ad8ba2cd
SY		 9259}
9260
1d8007bd 9261int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9262{
9263 int i, r;
25188b99 9264 unsigned long hva;
f0d648bd
PB		 9265 struct kvm_memslots *slots = kvm_memslots(kvm);
9266 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9267
9268 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9269 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9270 return -EINVAL;
9da0e4d5 9271
f0d648bd
PB		 9272 slot = id_to_memslot(slots, id);
9273 if (size) {
b21629da 9274 if (slot->npages)
f0d648bd
PB		 9275 return -EEXIST;
9276
9277 /*
9278 * MAP_SHARED to prevent internal slot pages from being moved
9279 * by fork()/COW.
9280 */
9281 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9282 MAP_SHARED | MAP_ANONYMOUS, 0);
9283 if (IS_ERR((void *)hva))
9284 return PTR_ERR((void *)hva);
9285 } else {
9286 if (!slot->npages)
9287 return 0;
9288
9289 hva = 0;
9290 }
9291
9292 old = *slot;
9da0e4d5 9293 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9294 struct kvm_userspace_memory_region m;
9da0e4d5 9295
1d8007bd
PB		 9296 m.slot = id | (i << 16);
9297 m.flags = 0;
9298 m.guest_phys_addr = gpa;
f0d648bd 9299 m.userspace_addr = hva;
1d8007bd 9300 m.memory_size = size;
9da0e4d5
PB		 9301 r = __kvm_set_memory_region(kvm, &m);
9302 if (r < 0)
9303 return r;
9304 }
9305
103c763c
EB		 9306 if (!size)
9307 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9308
9da0e4d5
PB		 9309 return 0;
9310}
9311EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9312
1d8007bd 9313int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9314{
9315 int r;
9316
9317 mutex_lock(&kvm->slots_lock);
1d8007bd 9318 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9319 mutex_unlock(&kvm->slots_lock);
9320
9321 return r;
9322}
9323EXPORT_SYMBOL_GPL(x86_set_memory_region);
9324
d19a9cd2
ZX		 9325void kvm_arch_destroy_vm(struct kvm *kvm)
9326{
27469d29
AH		 9327 if (current->mm == kvm->mm) {
9328 /*
9329 * Free memory regions allocated on behalf of userspace,
9330 * unless the the memory map has changed due to process exit
9331 * or fd copying.
9332 */
1d8007bd
PB		 9333 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9334 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9335 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9336 }
03543133
SS		 9337 if (kvm_x86_ops->vm_destroy)
9338 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9339 kvm_pic_destroy(kvm);
9340 kvm_ioapic_destroy(kvm);
d19a9cd2 9341 kvm_free_vcpus(kvm);
af1bae54 9342 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 9343 kvm_mmu_uninit_vm(kvm);
2beb6dad 9344 kvm_page_track_cleanup(kvm);
cbc0236a 9345 kvm_hv_destroy_vm(kvm);
d19a9cd2 9346}
0de10343 9347
5587027c 9348void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9349 struct kvm_memory_slot *dont)
9350{
9351 int i;
9352
d89cc617
TY		 9353 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9354 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9355 kvfree(free->arch.rmap[i]);
d89cc617 9356 free->arch.rmap[i] = NULL;
77d11309 9357 }
d89cc617
TY		 9358 if (i == 0)
9359 continue;
9360
9361 if (!dont || free->arch.lpage_info[i - 1] !=
9362 dont->arch.lpage_info[i - 1]) {
548ef284 9363 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9364 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9365 }
9366 }
21ebbeda
XG		 9367
9368 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9369}
9370
5587027c
AK		 9371int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9372 unsigned long npages)
db3fe4eb
TY		 9373{
9374 int i;
9375
d89cc617 9376 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9377 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9378 unsigned long ugfn;
9379 int lpages;
d89cc617 9380 int level = i + 1;
db3fe4eb
TY		 9381
9382 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9383 slot->base_gfn, level) + 1;
9384
d89cc617 9385 slot->arch.rmap[i] =
778e1cdd 9386 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9387 GFP_KERNEL_ACCOUNT);
d89cc617 9388 if (!slot->arch.rmap[i])
77d11309 9389 goto out_free;
d89cc617
TY		 9390 if (i == 0)
9391 continue;
77d11309 9392
254272ce 9393 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9394 if (!linfo)
db3fe4eb
TY		 9395 goto out_free;
9396
92f94f1e
XG		 9397 slot->arch.lpage_info[i - 1] = linfo;
9398
db3fe4eb 9399 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9400 linfo[0].disallow_lpage = 1;
db3fe4eb 9401 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9402 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9403 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9404 /*
9405 * If the gfn and userspace address are not aligned wrt each
9406 * other, or if explicitly asked to, disable large page
9407 * support for this slot
9408 */
9409 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9410 !kvm_largepages_enabled()) {
9411 unsigned long j;
9412
9413 for (j = 0; j < lpages; ++j)
92f94f1e 9414 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9415 }
9416 }
9417
21ebbeda
XG		 9418 if (kvm_page_track_create_memslot(slot, npages))
9419 goto out_free;
9420
db3fe4eb
TY		 9421 return 0;
9422
9423out_free:
d89cc617 9424 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9425 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9426 slot->arch.rmap[i] = NULL;
9427 if (i == 0)
9428 continue;
9429
548ef284 9430 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9431 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9432 }
9433 return -ENOMEM;
9434}
9435
15248258 9436void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9437{
e6dff7d1
TY		 9438 /*
9439 * memslots->generation has been incremented.
9440 * mmio generation may have reached its maximum value.
9441 */
15248258 9442 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9443}
9444
f7784b8e
MT		 9445int kvm_arch_prepare_memory_region(struct kvm *kvm,
9446 struct kvm_memory_slot *memslot,
09170a49 9447 const struct kvm_userspace_memory_region *mem,
7b6195a9 9448 enum kvm_mr_change change)
0de10343 9449{
f7784b8e
MT		 9450 return 0;
9451}
9452
88178fd4
KH		 9453static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9454 struct kvm_memory_slot *new)
9455{
9456 /* Still write protect RO slot */
9457 if (new->flags & KVM_MEM_READONLY) {
9458 kvm_mmu_slot_remove_write_access(kvm, new);
9459 return;
9460 }
9461
9462 /*
9463 * Call kvm_x86_ops dirty logging hooks when they are valid.
9464 *
9465 * kvm_x86_ops->slot_disable_log_dirty is called when:
9466 *
9467 * - KVM_MR_CREATE with dirty logging is disabled
9468 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9469 *
9470 * The reason is, in case of PML, we need to set D-bit for any slots
9471 * with dirty logging disabled in order to eliminate unnecessary GPA
9472 * logging in PML buffer (and potential PML buffer full VMEXT). This
9473 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9474 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9475 * logging disabled for memory slots.
9476 *
9477 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9478 * to dirty logging mode.
9479 *
9480 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9481 *
9482 * In case of write protect:
9483 *
9484 * Write protect all pages for dirty logging.
9485 *
9486 * All the sptes including the large sptes which point to this
9487 * slot are set to readonly. We can not create any new large
9488 * spte on this slot until the end of the logging.
9489 *
9490 * See the comments in fast_page_fault().
9491 */
9492 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9493 if (kvm_x86_ops->slot_enable_log_dirty)
9494 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9495 else
9496 kvm_mmu_slot_remove_write_access(kvm, new);
9497 } else {
9498 if (kvm_x86_ops->slot_disable_log_dirty)
9499 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9500 }
9501}
9502
f7784b8e 9503void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9504 const struct kvm_userspace_memory_region *mem,
8482644a 9505 const struct kvm_memory_slot *old,
f36f3f28 9506 const struct kvm_memory_slot *new,
8482644a 9507 enum kvm_mr_change change)
f7784b8e 9508{
48c0e4e9 9509 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9510 kvm_mmu_change_mmu_pages(kvm,
9511 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9512
3ea3b7fa
WL		 9513 /*
9514 * Dirty logging tracks sptes in 4k granularity, meaning that large
9515 * sptes have to be split. If live migration is successful, the guest
9516 * in the source machine will be destroyed and large sptes will be
9517 * created in the destination. However, if the guest continues to run
9518 * in the source machine (for example if live migration fails), small
9519 * sptes will remain around and cause bad performance.
9520 *
9521 * Scan sptes if dirty logging has been stopped, dropping those
9522 * which can be collapsed into a single large-page spte. Later
9523 * page faults will create the large-page sptes.
9524 */
9525 if ((change != KVM_MR_DELETE) &&
9526 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9527 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9528 kvm_mmu_zap_collapsible_sptes(kvm, new);
9529
c972f3b1 9530 /*
88178fd4 9531 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9532 *
88178fd4
KH		 9533 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9534 * been zapped so no dirty logging staff is needed for old slot. For
9535 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9536 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9537 *
9538 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9539 */
88178fd4 9540 if (change != KVM_MR_DELETE)
f36f3f28 9541 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9542}
1d737c8a 9543
2df72e9b 9544void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9545{
7390de1e 9546 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9547}
9548
2df72e9b
MT		 9549void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9550 struct kvm_memory_slot *slot)
9551{
ae7cd873 9552 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9553}
9554
e6c67d8c
LA		 9555static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9556{
9557 return (is_guest_mode(vcpu) &&
9558 kvm_x86_ops->guest_apic_has_interrupt &&
9559 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9560}
9561
5d9bc648
PB		 9562static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9563{
9564 if (!list_empty_careful(&vcpu->async_pf.done))
9565 return true;
9566
9567 if (kvm_apic_has_events(vcpu))
9568 return true;
9569
9570 if (vcpu->arch.pv.pv_unhalted)
9571 return true;
9572
a5f01f8e
WL		 9573 if (vcpu->arch.exception.pending)
9574 return true;
9575
47a66eed
Z		 9576 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9577 (vcpu->arch.nmi_pending &&
9578 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9579 return true;
9580
47a66eed
Z		 9581 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9582 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9583 return true;
9584
5d9bc648 9585 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9586 (kvm_cpu_has_interrupt(vcpu) ||
9587 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9588 return true;
9589
1f4b34f8
AS		 9590 if (kvm_hv_has_stimer_pending(vcpu))
9591 return true;
9592
5d9bc648
PB		 9593 return false;
9594}
9595
1d737c8a
ZX		 9596int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9597{
5d9bc648 9598 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9599}
5736199a 9600
199b5763
LM		 9601bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9602{
de63ad4c 9603 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9604}
9605
b6d33834 9606int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9607{
b6d33834 9608 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9609}
78646121
GN		 9610
9611int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9612{
9613 return kvm_x86_ops->interrupt_allowed(vcpu);
9614}
229456fc 9615
82b32774 9616unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9617{
82b32774
NA		 9618 if (is_64_bit_mode(vcpu))
9619 return kvm_rip_read(vcpu);
9620 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9621 kvm_rip_read(vcpu));
9622}
9623EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9624
82b32774
NA		 9625bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9626{
9627 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9628}
9629EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9630
94fe45da
JK		 9631unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9632{
9633 unsigned long rflags;
9634
9635 rflags = kvm_x86_ops->get_rflags(vcpu);
9636 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9637 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9638 return rflags;
9639}
9640EXPORT_SYMBOL_GPL(kvm_get_rflags);
9641
6addfc42 9642static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9643{
9644 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9645 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9646 rflags |= X86_EFLAGS_TF;
94fe45da 9647 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9648}
9649
9650void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9651{
9652 __kvm_set_rflags(vcpu, rflags);
3842d135 9653 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9654}
9655EXPORT_SYMBOL_GPL(kvm_set_rflags);
9656
56028d08
GN		 9657void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9658{
9659 int r;
9660
44dd3ffa 9661 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9662 work->wakeup_all)
56028d08
GN		 9663 return;
9664
9665 r = kvm_mmu_reload(vcpu);
9666 if (unlikely(r))
9667 return;
9668
44dd3ffa
VK		 9669 if (!vcpu->arch.mmu->direct_map &&
9670 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9671 return;
9672
44dd3ffa 9673 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9674}
9675
af585b92
GN		 9676static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9677{
9678 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9679}
9680
9681static inline u32 kvm_async_pf_next_probe(u32 key)
9682{
9683 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9684}
9685
9686static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9687{
9688 u32 key = kvm_async_pf_hash_fn(gfn);
9689
9690 while (vcpu->arch.apf.gfns[key] != ~0)
9691 key = kvm_async_pf_next_probe(key);
9692
9693 vcpu->arch.apf.gfns[key] = gfn;
9694}
9695
9696static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9697{
9698 int i;
9699 u32 key = kvm_async_pf_hash_fn(gfn);
9700
9701 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9702 (vcpu->arch.apf.gfns[key] != gfn &&
9703 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9704 key = kvm_async_pf_next_probe(key);
9705
9706 return key;
9707}
9708
9709bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9710{
9711 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9712}
9713
9714static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9715{
9716 u32 i, j, k;
9717
9718 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9719 while (true) {
9720 vcpu->arch.apf.gfns[i] = ~0;
9721 do {
9722 j = kvm_async_pf_next_probe(j);
9723 if (vcpu->arch.apf.gfns[j] == ~0)
9724 return;
9725 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9726 /*
9727 * k lies cyclically in ]i,j]
9728 * | i.k.j |
9729 * |....j i.k.| or |.k..j i...|
9730 */
9731 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9732 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9733 i = j;
9734 }
9735}
9736
7c90705b
GN		 9737static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9738{
4e335d9e
PB		 9739
9740 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9741 sizeof(val));
7c90705b
GN		 9742}
9743
9a6e7c39
WL		 9744static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9745{
9746
9747 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9748 sizeof(u32));
9749}
9750
af585b92
GN		 9751void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9752 struct kvm_async_pf *work)
9753{
6389ee94
AK		 9754 struct x86_exception fault;
9755
7c90705b 9756 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9757 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9758
9759 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9760 (vcpu->arch.apf.send_user_only &&
9761 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9762 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9763 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9764 fault.vector = PF_VECTOR;
9765 fault.error_code_valid = true;
9766 fault.error_code = 0;
9767 fault.nested_page_fault = false;
9768 fault.address = work->arch.token;
adfe20fb 9769 fault.async_page_fault = true;
6389ee94 9770 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9771 }
af585b92
GN		 9772}
9773
9774void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9775 struct kvm_async_pf *work)
9776{
6389ee94 9777 struct x86_exception fault;
9a6e7c39 9778 u32 val;
6389ee94 9779
f2e10669 9780 if (work->wakeup_all)
7c90705b
GN		 9781 work->arch.token = ~0; /* broadcast wakeup */
9782 else
9783 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9784 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9785
9a6e7c39
WL		 9786 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9787 !apf_get_user(vcpu, &val)) {
9788 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9789 vcpu->arch.exception.pending &&
9790 vcpu->arch.exception.nr == PF_VECTOR &&
9791 !apf_put_user(vcpu, 0)) {
9792 vcpu->arch.exception.injected = false;
9793 vcpu->arch.exception.pending = false;
9794 vcpu->arch.exception.nr = 0;
9795 vcpu->arch.exception.has_error_code = false;
9796 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9797 vcpu->arch.exception.has_payload = false;
9798 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9799 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9800 fault.vector = PF_VECTOR;
9801 fault.error_code_valid = true;
9802 fault.error_code = 0;
9803 fault.nested_page_fault = false;
9804 fault.address = work->arch.token;
9805 fault.async_page_fault = true;
9806 kvm_inject_page_fault(vcpu, &fault);
9807 }
7c90705b 9808 }
e6d53e3b 9809 vcpu->arch.apf.halted = false;
a4fa1635 9810 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9811}
9812
9813bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9814{
9815 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9816 return true;
9817 else
9bc1f09f 9818 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9819}
9820
5544eb9b
PB		 9821void kvm_arch_start_assignment(struct kvm *kvm)
9822{
9823 atomic_inc(&kvm->arch.assigned_device_count);
9824}
9825EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9826
9827void kvm_arch_end_assignment(struct kvm *kvm)
9828{
9829 atomic_dec(&kvm->arch.assigned_device_count);
9830}
9831EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9832
9833bool kvm_arch_has_assigned_device(struct kvm *kvm)
9834{
9835 return atomic_read(&kvm->arch.assigned_device_count);
9836}
9837EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9838
e0f0bbc5
AW		 9839void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9840{
9841 atomic_inc(&kvm->arch.noncoherent_dma_count);
9842}
9843EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9844
9845void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9846{
9847 atomic_dec(&kvm->arch.noncoherent_dma_count);
9848}
9849EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9850
9851bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9852{
9853 return atomic_read(&kvm->arch.noncoherent_dma_count);
9854}
9855EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9856
14717e20
AW		 9857bool kvm_arch_has_irq_bypass(void)
9858{
9859 return kvm_x86_ops->update_pi_irte != NULL;
9860}
9861
87276880
FW		 9862int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9863 struct irq_bypass_producer *prod)
9864{
9865 struct kvm_kernel_irqfd *irqfd =
9866 container_of(cons, struct kvm_kernel_irqfd, consumer);
9867
14717e20 9868 irqfd->producer = prod;
87276880 9869
14717e20
AW		 9870 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9871 prod->irq, irqfd->gsi, 1);
87276880
FW		 9872}
9873
9874void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9875 struct irq_bypass_producer *prod)
9876{
9877 int ret;
9878 struct kvm_kernel_irqfd *irqfd =
9879 container_of(cons, struct kvm_kernel_irqfd, consumer);
9880
87276880
FW		 9881 WARN_ON(irqfd->producer != prod);
9882 irqfd->producer = NULL;
9883
9884 /*
9885 * When producer of consumer is unregistered, we change back to
9886 * remapped mode, so we can re-use the current implementation
bb3541f1 9887 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9888 * int this case doesn't want to receive the interrupts.
9889 */
9890 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9891 if (ret)
9892 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9893 " fails: %d\n", irqfd->consumer.token, ret);
9894}
9895
9896int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9897 uint32_t guest_irq, bool set)
9898{
9899 if (!kvm_x86_ops->update_pi_irte)
9900 return -EINVAL;
9901
9902 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9903}
9904
52004014
FW		 9905bool kvm_vector_hashing_enabled(void)
9906{
9907 return vector_hashing;
9908}
9909EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9910
229456fc 9911EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9912EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9913EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9914EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9915EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9916EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9917EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9918EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9919EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9920EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9921EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9922EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9923EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9924EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9925EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9926EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9927EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9928EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9929EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)