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Documentation: move Documentation/virtual to Documentation/virt
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
043405e1
CO		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 17 */
18
edf88417 19#include <linux/kvm_host.h>
313a3dc7 20#include "irq.h"
1d737c8a 21#include "mmu.h"
7837699f 22#include "i8254.h"
37817f29 23#include "tss.h"
5fdbf976 24#include "kvm_cache_regs.h"
26eef70c 25#include "x86.h"
00b27a3e 26#include "cpuid.h"
474a5bb9 27#include "pmu.h"
e83d5887 28#include "hyperv.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
1767e931
PG		 35#include <linux/export.h>
36#include <linux/moduleparam.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
87276880
FW		 51#include <linux/kvm_irqfd.h>
52#include <linux/irqbypass.h>
3905f9ad 53#include <linux/sched/stat.h>
0c5f81da 54#include <linux/sched/isolation.h>
d0ec49d4 55#include <linux/mem_encrypt.h>
3905f9ad 56
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
b0c39dc6 68#include <asm/mshyperv.h>
0092e434 69#include <asm/hypervisor.h>
bf8c55d8 70#include <asm/intel_pt.h>
dd2cb348 71#include <clocksource/hyperv_timer.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
c3941d9e
SC		 138/*
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
143 */
144static int __read_mostly lapic_timer_advance_ns = -1;
0e6edceb 145module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
d0659d94 146
52004014
FW		 147static bool __read_mostly vector_hashing = true;
148module_param(vector_hashing, bool, S_IRUGO);
149
c4ae60e4
LA		 150bool __read_mostly enable_vmware_backdoor = false;
151module_param(enable_vmware_backdoor, bool, S_IRUGO);
152EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
153
6c86eedc
WL		 154static bool __read_mostly force_emulation_prefix = false;
155module_param(force_emulation_prefix, bool, S_IRUGO);
156
0c5f81da
WL		 157int __read_mostly pi_inject_timer = -1;
158module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
159
18863bdd
AK		 160#define KVM_NR_SHARED_MSRS 16
161
162struct kvm_shared_msrs_global {
163 int nr;
2bf78fa7 164 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 165};
166
167struct kvm_shared_msrs {
168 struct user_return_notifier urn;
169 bool registered;
2bf78fa7
SY		 170 struct kvm_shared_msr_values {
171 u64 host;
172 u64 curr;
173 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 174};
175
176static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 177static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 178
417bc304 179struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 190 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 195 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 202 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 203 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 204 { "req_event", VCPU_STAT(req_event) },
c595ceee 205 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 213 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 215 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 218 { NULL }
219};
220
2acf923e
DC		 221u64 __read_mostly host_xcr0;
222
b666a4b6
MO		 223struct kmem_cache *x86_fpu_cache;
224EXPORT_SYMBOL_GPL(x86_fpu_cache);
225
b6785def 226static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 227
af585b92
GN		 228static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
229{
230 int i;
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
233}
234
18863bdd
AK		 235static void kvm_on_user_return(struct user_return_notifier *urn)
236{
237 unsigned slot;
18863bdd
AK		 238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 240 struct kvm_shared_msr_values *values;
1650b4eb
IA		 241 unsigned long flags;
242
243 /*
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
246 */
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
251 }
252 local_irq_restore(flags);
18863bdd 253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
18863bdd
AK		 258 }
259 }
18863bdd
AK		 260}
261
2bf78fa7 262static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 263{
18863bdd 264 u64 value;
013f6a5d
MT		 265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 267
2bf78fa7
SY		 268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
272 return;
273 }
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
277}
278
279void kvm_define_shared_msr(unsigned slot, u32 msr)
280{
0123be42 281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 282 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 285}
286EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
287
288static void kvm_shared_msr_cpu_online(void)
289{
290 unsigned i;
18863bdd
AK		 291
292 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 293 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 294}
295
8b3c3104 296int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 300 int err;
18863bdd 301
2bf78fa7 302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 303 return 0;
2bf78fa7 304 smsr->values[slot].curr = value;
8b3c3104
AH		 305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
306 if (err)
307 return 1;
308
18863bdd
AK		 309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
313 }
8b3c3104 314 return 0;
18863bdd
AK		 315}
316EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
317
13a34e06 318static void drop_user_return_notifiers(void)
3548bab5 319{
013f6a5d
MT		 320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 322
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
325}
326
6866b83e
CO		 327u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
328{
8a5a87d9 329 return vcpu->arch.apic_base;
6866b83e
CO		 330}
331EXPORT_SYMBOL_GPL(kvm_get_apic_base);
332
58871649
JM		 333enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
334{
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
336}
337EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
338
58cb628d
JK		 339int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
340{
58871649
JM		 341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 345
58871649 346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 347 return 1;
58871649
JM		 348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
350 return 1;
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
352 return 1;
353 }
58cb628d
JK		 354
355 kvm_lapic_set_base(vcpu, msr_info->data);
356 return 0;
6866b83e
CO		 357}
358EXPORT_SYMBOL_GPL(kvm_set_apic_base);
359
2605fc21 360asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 361{
362 /* Fault while not rebooting. We want the trace. */
363 BUG();
364}
365EXPORT_SYMBOL_GPL(kvm_spurious_fault);
366
3fd28fce
ED		 367#define EXCPT_BENIGN 0
368#define EXCPT_CONTRIBUTORY 1
369#define EXCPT_PF 2
370
371static int exception_class(int vector)
372{
373 switch (vector) {
374 case PF_VECTOR:
375 return EXCPT_PF;
376 case DE_VECTOR:
377 case TS_VECTOR:
378 case NP_VECTOR:
379 case SS_VECTOR:
380 case GP_VECTOR:
381 return EXCPT_CONTRIBUTORY;
382 default:
383 break;
384 }
385 return EXCPT_BENIGN;
386}
387
d6e8c854
NA		 388#define EXCPT_FAULT 0
389#define EXCPT_TRAP 1
390#define EXCPT_ABORT 2
391#define EXCPT_INTERRUPT 3
392
393static int exception_type(int vector)
394{
395 unsigned int mask;
396
397 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
398 return EXCPT_INTERRUPT;
399
400 mask = 1 << vector;
401
402 /* #DB is trap, as instruction watchpoints are handled elsewhere */
403 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
404 return EXCPT_TRAP;
405
406 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
407 return EXCPT_ABORT;
408
409 /* Reserved exceptions will result in fault */
410 return EXCPT_FAULT;
411}
412
da998b46
JM		 413void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
414{
415 unsigned nr = vcpu->arch.exception.nr;
416 bool has_payload = vcpu->arch.exception.has_payload;
417 unsigned long payload = vcpu->arch.exception.payload;
418
419 if (!has_payload)
420 return;
421
422 switch (nr) {
f10c729f
JM		 423 case DB_VECTOR:
424 /*
425 * "Certain debug exceptions may clear bit 0-3. The
426 * remaining contents of the DR6 register are never
427 * cleared by the processor".
428 */
429 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
430 /*
431 * DR6.RTM is set by all #DB exceptions that don't clear it.
432 */
433 vcpu->arch.dr6 |= DR6_RTM;
434 vcpu->arch.dr6 |= payload;
435 /*
436 * Bit 16 should be set in the payload whenever the #DB
437 * exception should clear DR6.RTM. This makes the payload
438 * compatible with the pending debug exceptions under VMX.
439 * Though not currently documented in the SDM, this also
440 * makes the payload compatible with the exit qualification
441 * for #DB exceptions under VMX.
442 */
443 vcpu->arch.dr6 ^= payload & DR6_RTM;
444 break;
da998b46
JM		 445 case PF_VECTOR:
446 vcpu->arch.cr2 = payload;
447 break;
448 }
449
450 vcpu->arch.exception.has_payload = false;
451 vcpu->arch.exception.payload = 0;
452}
453EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
454
3fd28fce 455static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 456 unsigned nr, bool has_error, u32 error_code,
91e86d22 457 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 458{
459 u32 prev_nr;
460 int class1, class2;
461
3842d135
AK		 462 kvm_make_request(KVM_REQ_EVENT, vcpu);
463
664f8e26 464 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 465 queue:
3ffb2468
NA		 466 if (has_error && !is_protmode(vcpu))
467 has_error = false;
664f8e26
WL		 468 if (reinject) {
469 /*
470 * On vmentry, vcpu->arch.exception.pending is only
471 * true if an event injection was blocked by
472 * nested_run_pending. In that case, however,
473 * vcpu_enter_guest requests an immediate exit,
474 * and the guest shouldn't proceed far enough to
475 * need reinjection.
476 */
477 WARN_ON_ONCE(vcpu->arch.exception.pending);
478 vcpu->arch.exception.injected = true;
91e86d22
JM		 479 if (WARN_ON_ONCE(has_payload)) {
480 /*
481 * A reinjected event has already
482 * delivered its payload.
483 */
484 has_payload = false;
485 payload = 0;
486 }
664f8e26
WL		 487 } else {
488 vcpu->arch.exception.pending = true;
489 vcpu->arch.exception.injected = false;
490 }
3fd28fce
ED		 491 vcpu->arch.exception.has_error_code = has_error;
492 vcpu->arch.exception.nr = nr;
493 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 494 vcpu->arch.exception.has_payload = has_payload;
495 vcpu->arch.exception.payload = payload;
da998b46
JM		 496 /*
497 * In guest mode, payload delivery should be deferred,
498 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 499 * CR2 is modified (or intercept #DB before DR6 is
500 * modified under nVMX). However, for ABI
501 * compatibility with KVM_GET_VCPU_EVENTS and
502 * KVM_SET_VCPU_EVENTS, we can't delay payload
503 * delivery unless userspace has enabled this
504 * functionality via the per-VM capability,
505 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 506 */
507 if (!vcpu->kvm->arch.exception_payload_enabled ||
508 !is_guest_mode(vcpu))
509 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 510 return;
511 }
512
513 /* to check exception */
514 prev_nr = vcpu->arch.exception.nr;
515 if (prev_nr == DF_VECTOR) {
516 /* triple fault -> shutdown */
a8eeb04a 517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 518 return;
519 }
520 class1 = exception_class(prev_nr);
521 class2 = exception_class(nr);
522 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
523 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 524 /*
525 * Generate double fault per SDM Table 5-5. Set
526 * exception.pending = true so that the double fault
527 * can trigger a nested vmexit.
528 */
3fd28fce 529 vcpu->arch.exception.pending = true;
664f8e26 530 vcpu->arch.exception.injected = false;
3fd28fce
ED		 531 vcpu->arch.exception.has_error_code = true;
532 vcpu->arch.exception.nr = DF_VECTOR;
533 vcpu->arch.exception.error_code = 0;
c851436a
JM		 534 vcpu->arch.exception.has_payload = false;
535 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 536 } else
537 /* replace previous exception with a new one in a hope
538 that instruction re-execution will regenerate lost
539 exception */
540 goto queue;
541}
542
298101da
AK		 543void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544{
91e86d22 545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 546}
547EXPORT_SYMBOL_GPL(kvm_queue_exception);
548
ce7ddec4
JR		 549void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
550{
91e86d22 551 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 552}
553EXPORT_SYMBOL_GPL(kvm_requeue_exception);
554
f10c729f
JM		 555static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
556 unsigned long payload)
557{
558 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
559}
560
da998b46
JM		 561static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
562 u32 error_code, unsigned long payload)
563{
564 kvm_multiple_exception(vcpu, nr, true, error_code,
565 true, payload, false);
566}
567
6affcbed 568int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 569{
db8fcefa
AP		 570 if (err)
571 kvm_inject_gp(vcpu, 0);
572 else
6affcbed
KH		 573 return kvm_skip_emulated_instruction(vcpu);
574
575 return 1;
db8fcefa
AP		 576}
577EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 578
6389ee94 579void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 580{
581 ++vcpu->stat.pf_guest;
adfe20fb
WL		 582 vcpu->arch.exception.nested_apf =
583 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 584 if (vcpu->arch.exception.nested_apf) {
adfe20fb 585 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 586 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
587 } else {
588 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
589 fault->address);
590 }
c3c91fee 591}
27d6c865 592EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 593
ef54bcfe 594static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 595{
6389ee94
AK		 596 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
597 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 598 else
44dd3ffa 599 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 600
601 return fault->nested_page_fault;
d4f8cf66
JR		 602}
603
3419ffc8
SY		 604void kvm_inject_nmi(struct kvm_vcpu *vcpu)
605{
7460fb4a
AK		 606 atomic_inc(&vcpu->arch.nmi_queued);
607 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 608}
609EXPORT_SYMBOL_GPL(kvm_inject_nmi);
610
298101da
AK		 611void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612{
91e86d22 613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 614}
615EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
616
ce7ddec4
JR		 617void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
618{
91e86d22 619 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 620}
621EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
622
0a79b009
AK		 623/*
624 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
625 * a #GP and return false.
626 */
627bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 628{
0a79b009
AK		 629 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
630 return true;
631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
632 return false;
298101da 633}
0a79b009 634EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 635
16f8a6f9
NA		 636bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
637{
638 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
639 return true;
640
641 kvm_queue_exception(vcpu, UD_VECTOR);
642 return false;
643}
644EXPORT_SYMBOL_GPL(kvm_require_dr);
645
ec92fe44
JR		 646/*
647 * This function will be used to read from the physical memory of the currently
54bf36aa 648 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 649 * can read from guest physical or from the guest's guest physical memory.
650 */
651int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
652 gfn_t ngfn, void *data, int offset, int len,
653 u32 access)
654{
54987b7a 655 struct x86_exception exception;
ec92fe44
JR		 656 gfn_t real_gfn;
657 gpa_t ngpa;
658
659 ngpa = gfn_to_gpa(ngfn);
54987b7a 660 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 661 if (real_gfn == UNMAPPED_GVA)
662 return -EFAULT;
663
664 real_gfn = gpa_to_gfn(real_gfn);
665
54bf36aa 666 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 667}
668EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
669
69b0049a 670static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 671 void *data, int offset, int len, u32 access)
672{
673 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
674 data, offset, len, access);
675}
676
a03490ed
CO		 677/*
678 * Load the pae pdptrs. Return true is they are all valid.
679 */
ff03a073 680int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 681{
682 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
683 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
684 int i;
685 int ret;
ff03a073 686 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 687
ff03a073
JR		 688 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
689 offset * sizeof(u64), sizeof(pdpte),
690 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 691 if (ret < 0) {
692 ret = 0;
693 goto out;
694 }
695 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 696 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 697 (pdpte[i] &
44dd3ffa 698 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 699 ret = 0;
700 goto out;
701 }
702 }
703 ret = 1;
704
ff03a073 705 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 706 __set_bit(VCPU_EXREG_PDPTR,
707 (unsigned long *)&vcpu->arch.regs_avail);
708 __set_bit(VCPU_EXREG_PDPTR,
709 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 710out:
a03490ed
CO		 711
712 return ret;
713}
cc4b6871 714EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 715
9ed38ffa 716bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 717{
ff03a073 718 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 719 bool changed = true;
3d06b8bf
JR		 720 int offset;
721 gfn_t gfn;
d835dfec
AK		 722 int r;
723
bf03d4f9 724 if (!is_pae_paging(vcpu))
d835dfec
AK		 725 return false;
726
6de4f3ad
AK		 727 if (!test_bit(VCPU_EXREG_PDPTR,
728 (unsigned long *)&vcpu->arch.regs_avail))
729 return true;
730
a512177e
PB		 731 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
732 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 733 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
734 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 735 if (r < 0)
736 goto out;
ff03a073 737 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 738out:
d835dfec
AK		 739
740 return changed;
741}
9ed38ffa 742EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 743
49a9b07e 744int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 745{
aad82703 746 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 747 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 748
f9a48e6a
AK		 749 cr0 |= X86_CR0_ET;
750
ab344828 751#ifdef CONFIG_X86_64
0f12244f
GN		 752 if (cr0 & 0xffffffff00000000UL)
753 return 1;
ab344828
GN		 754#endif
755
756 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 757
0f12244f
GN		 758 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
759 return 1;
a03490ed 760
0f12244f
GN		 761 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
762 return 1;
a03490ed
CO		 763
764 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
765#ifdef CONFIG_X86_64
f6801dff 766 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 767 int cs_db, cs_l;
768
0f12244f
GN		 769 if (!is_pae(vcpu))
770 return 1;
a03490ed 771 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 772 if (cs_l)
773 return 1;
a03490ed
CO		 774 } else
775#endif
ff03a073 776 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 777 kvm_read_cr3(vcpu)))
0f12244f 778 return 1;
a03490ed
CO		 779 }
780
ad756a16
MJ		 781 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
782 return 1;
783
a03490ed 784 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 785
d170c419 786 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 787 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 788 kvm_async_pf_hash_reset(vcpu);
789 }
e5f3f027 790
aad82703
SY		 791 if ((cr0 ^ old_cr0) & update_bits)
792 kvm_mmu_reset_context(vcpu);
b18d5431 793
879ae188
LE		 794 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
795 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
796 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 797 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
798
0f12244f
GN		 799 return 0;
800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 802
2d3ad1f4 803void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 804{
49a9b07e 805 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 806}
2d3ad1f4 807EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 808
1811d979 809void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 810{
811 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
812 !vcpu->guest_xcr0_loaded) {
813 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 814 if (vcpu->arch.xcr0 != host_xcr0)
815 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 816 vcpu->guest_xcr0_loaded = 1;
817 }
818}
1811d979 819EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
42bdf991 820
1811d979 821void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 822{
823 if (vcpu->guest_xcr0_loaded) {
824 if (vcpu->arch.xcr0 != host_xcr0)
825 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
826 vcpu->guest_xcr0_loaded = 0;
827 }
828}
1811d979 829EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
42bdf991 830
69b0049a 831static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 832{
56c103ec
LJ		 833 u64 xcr0 = xcr;
834 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 835 u64 valid_bits;
2acf923e
DC		 836
837 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
838 if (index != XCR_XFEATURE_ENABLED_MASK)
839 return 1;
d91cab78 840 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 841 return 1;
d91cab78 842 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 843 return 1;
46c34cb0
PB		 844
845 /*
846 * Do not allow the guest to set bits that we do not support
847 * saving. However, xcr0 bit 0 is always set, even if the
848 * emulated CPU does not support XSAVE (see fx_init).
849 */
d91cab78 850 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 851 if (xcr0 & ~valid_bits)
2acf923e 852 return 1;
46c34cb0 853
d91cab78
DH		 854 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
855 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 856 return 1;
857
d91cab78
DH		 858 if (xcr0 & XFEATURE_MASK_AVX512) {
859 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 860 return 1;
d91cab78 861 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 862 return 1;
863 }
2acf923e 864 vcpu->arch.xcr0 = xcr0;
56c103ec 865
d91cab78 866 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 867 kvm_update_cpuid(vcpu);
2acf923e
DC		 868 return 0;
869}
870
871int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
872{
764bcbc5
Z		 873 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
874 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 875 kvm_inject_gp(vcpu, 0);
876 return 1;
877 }
878 return 0;
879}
880EXPORT_SYMBOL_GPL(kvm_set_xcr);
881
a83b29c6 882int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 883{
fc78f519 884 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 885 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 886 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 887
0f12244f
GN		 888 if (cr4 & CR4_RESERVED_BITS)
889 return 1;
a03490ed 890
d6321d49 891 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 892 return 1;
893
d6321d49 894 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 895 return 1;
896
d6321d49 897 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 898 return 1;
899
d6321d49 900 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 901 return 1;
902
d6321d49 903 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 904 return 1;
905
fd8cb433 906 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 907 return 1;
908
ae3e61e1
PB		 909 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
910 return 1;
911
a03490ed 912 if (is_long_mode(vcpu)) {
0f12244f
GN		 913 if (!(cr4 & X86_CR4_PAE))
914 return 1;
a2edf57f
AK		 915 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
916 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 917 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
918 kvm_read_cr3(vcpu)))
0f12244f
GN		 919 return 1;
920
ad756a16 921 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 922 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 923 return 1;
924
925 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
926 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
927 return 1;
928 }
929
5e1746d6 930 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 931 return 1;
a03490ed 932
ad756a16
MJ		 933 if (((cr4 ^ old_cr4) & pdptr_bits) ||
934 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 935 kvm_mmu_reset_context(vcpu);
0f12244f 936
b9baba86 937 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 938 kvm_update_cpuid(vcpu);
2acf923e 939
0f12244f
GN		 940 return 0;
941}
2d3ad1f4 942EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 943
2390218b 944int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 945{
ade61e28 946 bool skip_tlb_flush = false;
ac146235 947#ifdef CONFIG_X86_64
c19986fe
JS		 948 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
949
ade61e28 950 if (pcid_enabled) {
208320ba
JS		 951 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
952 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 953 }
ac146235 954#endif
9d88fca7 955
9f8fe504 956 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 957 if (!skip_tlb_flush) {
958 kvm_mmu_sync_roots(vcpu);
ade61e28 959 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 960 }
0f12244f 961 return 0;
d835dfec
AK		 962 }
963
d1cd3ce9 964 if (is_long_mode(vcpu) &&
a780a3ea 965 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9 966 return 1;
bf03d4f9
PB		 967 else if (is_pae_paging(vcpu) &&
968 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 969 return 1;
a03490ed 970
ade61e28 971 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 972 vcpu->arch.cr3 = cr3;
aff48baa 973 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 974
0f12244f
GN		 975 return 0;
976}
2d3ad1f4 977EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 978
eea1cff9 979int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 980{
0f12244f
GN		 981 if (cr8 & CR8_RESERVED_BITS)
982 return 1;
35754c98 983 if (lapic_in_kernel(vcpu))
a03490ed
CO		 984 kvm_lapic_set_tpr(vcpu, cr8);
985 else
ad312c7c 986 vcpu->arch.cr8 = cr8;
0f12244f
GN		 987 return 0;
988}
2d3ad1f4 989EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 990
2d3ad1f4 991unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 992{
35754c98 993 if (lapic_in_kernel(vcpu))
a03490ed
CO		 994 return kvm_lapic_get_cr8(vcpu);
995 else
ad312c7c 996 return vcpu->arch.cr8;
a03490ed 997}
2d3ad1f4 998EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 999
ae561ede
NA		 1000static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1001{
1002 int i;
1003
1004 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1005 for (i = 0; i < KVM_NR_DB_REGS; i++)
1006 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1007 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1008 }
1009}
1010
73aaf249
JK		 1011static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1012{
1013 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1014 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1015}
1016
c8639010
JK		 1017static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1018{
1019 unsigned long dr7;
1020
1021 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1022 dr7 = vcpu->arch.guest_debug_dr7;
1023 else
1024 dr7 = vcpu->arch.dr7;
1025 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1026 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1027 if (dr7 & DR7_BP_EN_MASK)
1028 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1029}
1030
6f43ed01
NA		 1031static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1032{
1033 u64 fixed = DR6_FIXED_1;
1034
d6321d49 1035 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1036 fixed |= DR6_RTM;
1037 return fixed;
1038}
1039
338dbc97 1040static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1041{
1042 switch (dr) {
1043 case 0 ... 3:
1044 vcpu->arch.db[dr] = val;
1045 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1046 vcpu->arch.eff_db[dr] = val;
1047 break;
1048 case 4:
020df079
GN		 1049 /* fall through */
1050 case 6:
338dbc97
GN		 1051 if (val & 0xffffffff00000000ULL)
1052 return -1; /* #GP */
6f43ed01 1053 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1054 kvm_update_dr6(vcpu);
020df079
GN		 1055 break;
1056 case 5:
020df079
GN		 1057 /* fall through */
1058 default: /* 7 */
338dbc97
GN		 1059 if (val & 0xffffffff00000000ULL)
1060 return -1; /* #GP */
020df079 1061 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1062 kvm_update_dr7(vcpu);
020df079
GN		 1063 break;
1064 }
1065
1066 return 0;
1067}
338dbc97
GN		 1068
1069int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1070{
16f8a6f9 1071 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1072 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1073 return 1;
1074 }
1075 return 0;
338dbc97 1076}
020df079
GN		 1077EXPORT_SYMBOL_GPL(kvm_set_dr);
1078
16f8a6f9 1079int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1080{
1081 switch (dr) {
1082 case 0 ... 3:
1083 *val = vcpu->arch.db[dr];
1084 break;
1085 case 4:
020df079
GN		 1086 /* fall through */
1087 case 6:
73aaf249
JK		 1088 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1089 *val = vcpu->arch.dr6;
1090 else
1091 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1092 break;
1093 case 5:
020df079
GN		 1094 /* fall through */
1095 default: /* 7 */
1096 *val = vcpu->arch.dr7;
1097 break;
1098 }
338dbc97
GN		 1099 return 0;
1100}
020df079
GN		 1101EXPORT_SYMBOL_GPL(kvm_get_dr);
1102
022cd0e8
AK		 1103bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1104{
de3cd117 1105 u32 ecx = kvm_rcx_read(vcpu);
022cd0e8
AK		 1106 u64 data;
1107 int err;
1108
c6702c9d 1109 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1110 if (err)
1111 return err;
de3cd117
SC		 1112 kvm_rax_write(vcpu, (u32)data);
1113 kvm_rdx_write(vcpu, data >> 32);
022cd0e8
AK		 1114 return err;
1115}
1116EXPORT_SYMBOL_GPL(kvm_rdpmc);
1117
043405e1
CO		 1118/*
1119 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1120 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1121 *
1122 * This list is modified at module load time to reflect the
e3267cbb 1123 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1124 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1125 * may depend on host virtualization features rather than host cpu features.
043405e1 1126 */
e3267cbb 1127
043405e1
CO		 1128static u32 msrs_to_save[] = {
1129 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1130 MSR_STAR,
043405e1
CO		 1131#ifdef CONFIG_X86_64
1132 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1133#endif
b3897a49 1134 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1135 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1136 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1137 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1138 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1139 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1140 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1141 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1142 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
043405e1
CO		 1143};
1144
1145static unsigned num_msrs_to_save;
1146
62ef68bb
PB		 1147static u32 emulated_msrs[] = {
1148 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1149 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1150 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1151 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1152 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1153 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1154 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1155 HV_X64_MSR_RESET,
11c4b1ca 1156 HV_X64_MSR_VP_INDEX,
9eec50b8 1157 HV_X64_MSR_VP_RUNTIME,
5c919412 1158 HV_X64_MSR_SCONTROL,
1f4b34f8 1159 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1160 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1161 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1162 HV_X64_MSR_TSC_EMULATION_STATUS,
1163
1164 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1165 MSR_KVM_PV_EOI_EN,
1166
ba904635 1167 MSR_IA32_TSC_ADJUST,
a3e06bbe 1168 MSR_IA32_TSCDEADLINE,
2bdb76c0 1169 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1170 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1171 MSR_IA32_MCG_STATUS,
1172 MSR_IA32_MCG_CTL,
c45dcc71 1173 MSR_IA32_MCG_EXT_CTL,
64d60670 1174 MSR_IA32_SMBASE,
52797bf9 1175 MSR_SMI_COUNT,
db2336a8
KH		 1176 MSR_PLATFORM_INFO,
1177 MSR_MISC_FEATURES_ENABLES,
bc226f07 1178 MSR_AMD64_VIRT_SPEC_CTRL,
6c6a2ab9 1179 MSR_IA32_POWER_CTL,
191c8137 1180
95c5c7c7
PB		 1181 /*
1182 * The following list leaves out MSRs whose values are determined
1183 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1184 * We always support the "true" VMX control MSRs, even if the host
1185 * processor does not, so I am putting these registers here rather
1186 * than in msrs_to_save.
1187 */
1188 MSR_IA32_VMX_BASIC,
1189 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1190 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1191 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1192 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1193 MSR_IA32_VMX_MISC,
1194 MSR_IA32_VMX_CR0_FIXED0,
1195 MSR_IA32_VMX_CR4_FIXED0,
1196 MSR_IA32_VMX_VMCS_ENUM,
1197 MSR_IA32_VMX_PROCBASED_CTLS2,
1198 MSR_IA32_VMX_EPT_VPID_CAP,
1199 MSR_IA32_VMX_VMFUNC,
1200
191c8137 1201 MSR_K7_HWCR,
2d5ba19b 1202 MSR_KVM_POLL_CONTROL,
043405e1
CO		 1203};
1204
62ef68bb
PB		 1205static unsigned num_emulated_msrs;
1206
801e459a
TL		 1207/*
1208 * List of msr numbers which are used to expose MSR-based features that
1209 * can be used by a hypervisor to validate requested CPU features.
1210 */
1211static u32 msr_based_features[] = {
1389309c
PB		 1212 MSR_IA32_VMX_BASIC,
1213 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1214 MSR_IA32_VMX_PINBASED_CTLS,
1215 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1216 MSR_IA32_VMX_PROCBASED_CTLS,
1217 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1218 MSR_IA32_VMX_EXIT_CTLS,
1219 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1220 MSR_IA32_VMX_ENTRY_CTLS,
1221 MSR_IA32_VMX_MISC,
1222 MSR_IA32_VMX_CR0_FIXED0,
1223 MSR_IA32_VMX_CR0_FIXED1,
1224 MSR_IA32_VMX_CR4_FIXED0,
1225 MSR_IA32_VMX_CR4_FIXED1,
1226 MSR_IA32_VMX_VMCS_ENUM,
1227 MSR_IA32_VMX_PROCBASED_CTLS2,
1228 MSR_IA32_VMX_EPT_VPID_CAP,
1229 MSR_IA32_VMX_VMFUNC,
1230
d1d93fa9 1231 MSR_F10H_DECFG,
518e7b94 1232 MSR_IA32_UCODE_REV,
cd283252 1233 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1234};
1235
1236static unsigned int num_msr_based_features;
1237
4d22c17c 1238static u64 kvm_get_arch_capabilities(void)
5b76a3cf 1239{
4d22c17c 1240 u64 data = 0;
5b76a3cf 1241
4d22c17c
XL		 1242 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1243 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
5b76a3cf
PB		 1244
1245 /*
1246 * If we're doing cache flushes (either "always" or "cond")
1247 * we will do one whenever the guest does a vmlaunch/vmresume.
1248 * If an outer hypervisor is doing the cache flush for us
1249 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1250 * capability to the guest too, and if EPT is disabled we're not
1251 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1252 * require a nested hypervisor to do a flush of its own.
1253 */
1254 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1255 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1256
1257 return data;
1258}
5b76a3cf 1259
66421c1e
WL		 1260static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1261{
1262 switch (msr->index) {
cd283252 1263 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1264 msr->data = kvm_get_arch_capabilities();
1265 break;
1266 case MSR_IA32_UCODE_REV:
cd283252 1267 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1268 break;
66421c1e
WL		 1269 default:
1270 if (kvm_x86_ops->get_msr_feature(msr))
1271 return 1;
1272 }
1273 return 0;
1274}
1275
801e459a
TL		 1276static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1277{
1278 struct kvm_msr_entry msr;
66421c1e 1279 int r;
801e459a
TL		 1280
1281 msr.index = index;
66421c1e
WL		 1282 r = kvm_get_msr_feature(&msr);
1283 if (r)
1284 return r;
801e459a
TL		 1285
1286 *data = msr.data;
1287
1288 return 0;
1289}
1290
11988499 1291static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1292{
1b4d56b8 1293 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
11988499 1294 return false;
1b2fd70c 1295
1b4d56b8 1296 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
11988499 1297 return false;
d8017474 1298
0a629563
SC		 1299 if (efer & (EFER_LME | EFER_LMA) &&
1300 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1301 return false;
1302
1303 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1304 return false;
d8017474 1305
384bb783 1306 return true;
11988499
SC		 1307
1308}
1309bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1310{
1311 if (efer & efer_reserved_bits)
1312 return false;
1313
1314 return __kvm_valid_efer(vcpu, efer);
384bb783
JK		 1315}
1316EXPORT_SYMBOL_GPL(kvm_valid_efer);
1317
11988499 1318static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
384bb783
JK		 1319{
1320 u64 old_efer = vcpu->arch.efer;
11988499 1321 u64 efer = msr_info->data;
384bb783 1322
11988499 1323 if (efer & efer_reserved_bits)
66f61c92 1324 return 1;
384bb783 1325
11988499
SC		 1326 if (!msr_info->host_initiated) {
1327 if (!__kvm_valid_efer(vcpu, efer))
1328 return 1;
1329
1330 if (is_paging(vcpu) &&
1331 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1332 return 1;
1333 }
384bb783 1334
15c4a640 1335 efer &= ~EFER_LMA;
f6801dff 1336 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1337
a3d204e2
SY		 1338 kvm_x86_ops->set_efer(vcpu, efer);
1339
aad82703
SY		 1340 /* Update reserved bits */
1341 if ((efer ^ old_efer) & EFER_NX)
1342 kvm_mmu_reset_context(vcpu);
1343
b69e8cae 1344 return 0;
15c4a640
CO		 1345}
1346
f2b4b7dd
JR		 1347void kvm_enable_efer_bits(u64 mask)
1348{
1349 efer_reserved_bits &= ~mask;
1350}
1351EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1352
15c4a640
CO		 1353/*
1354 * Writes msr value into into the appropriate "register".
1355 * Returns 0 on success, non-0 otherwise.
1356 * Assumes vcpu_load() was already called.
1357 */
8fe8ab46 1358int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1359{
854e8bb1
NA		 1360 switch (msr->index) {
1361 case MSR_FS_BASE:
1362 case MSR_GS_BASE:
1363 case MSR_KERNEL_GS_BASE:
1364 case MSR_CSTAR:
1365 case MSR_LSTAR:
fd8cb433 1366 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1367 return 1;
1368 break;
1369 case MSR_IA32_SYSENTER_EIP:
1370 case MSR_IA32_SYSENTER_ESP:
1371 /*
1372 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1373 * non-canonical address is written on Intel but not on
1374 * AMD (which ignores the top 32-bits, because it does
1375 * not implement 64-bit SYSENTER).
1376 *
1377 * 64-bit code should hence be able to write a non-canonical
1378 * value on AMD. Making the address canonical ensures that
1379 * vmentry does not fail on Intel after writing a non-canonical
1380 * value, and that something deterministic happens if the guest
1381 * invokes 64-bit SYSENTER.
1382 */
fd8cb433 1383 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1384 }
8fe8ab46 1385 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1386}
854e8bb1 1387EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1388
313a3dc7
CO		 1389/*
1390 * Adapt set_msr() to msr_io()'s calling convention
1391 */
609e36d3
PB		 1392static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1393{
1394 struct msr_data msr;
1395 int r;
1396
1397 msr.index = index;
1398 msr.host_initiated = true;
1399 r = kvm_get_msr(vcpu, &msr);
1400 if (r)
1401 return r;
1402
1403 *data = msr.data;
1404 return 0;
1405}
1406
313a3dc7
CO		 1407static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1408{
8fe8ab46
WA		 1409 struct msr_data msr;
1410
1411 msr.data = *data;
1412 msr.index = index;
1413 msr.host_initiated = true;
1414 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1415}
1416
16e8d74d
MT		 1417#ifdef CONFIG_X86_64
1418struct pvclock_gtod_data {
1419 seqcount_t seq;
1420
1421 struct { /* extract of a clocksource struct */
1422 int vclock_mode;
a5a1d1c2
TG		 1423 u64 cycle_last;
1424 u64 mask;
16e8d74d
MT		 1425 u32 mult;
1426 u32 shift;
1427 } clock;
1428
cbcf2dd3
TG		 1429 u64 boot_ns;
1430 u64 nsec_base;
55dd00a7 1431 u64 wall_time_sec;
16e8d74d
MT		 1432};
1433
1434static struct pvclock_gtod_data pvclock_gtod_data;
1435
1436static void update_pvclock_gtod(struct timekeeper *tk)
1437{
1438 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1439 u64 boot_ns;
1440
876e7881 1441 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1442
1443 write_seqcount_begin(&vdata->seq);
1444
1445 /* copy pvclock gtod data */
876e7881
PZ		 1446 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1447 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1448 vdata->clock.mask = tk->tkr_mono.mask;
1449 vdata->clock.mult = tk->tkr_mono.mult;
1450 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1451
cbcf2dd3 1452 vdata->boot_ns = boot_ns;
876e7881 1453 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1454
55dd00a7
MT		 1455 vdata->wall_time_sec = tk->xtime_sec;
1456
16e8d74d
MT		 1457 write_seqcount_end(&vdata->seq);
1458}
1459#endif
1460
bab5bb39
NK		 1461void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1462{
bab5bb39 1463 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
4d151bf3 1464 kvm_vcpu_kick(vcpu);
bab5bb39 1465}
16e8d74d 1466
18068523
GOC		 1467static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1468{
9ed3c444
AK		 1469 int version;
1470 int r;
50d0a0f9 1471 struct pvclock_wall_clock wc;
87aeb54f 1472 struct timespec64 boot;
18068523
GOC		 1473
1474 if (!wall_clock)
1475 return;
1476
9ed3c444
AK		 1477 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1478 if (r)
1479 return;
1480
1481 if (version & 1)
1482 ++version; /* first time write, random junk */
1483
1484 ++version;
18068523 1485
1dab1345
NK		 1486 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1487 return;
18068523 1488
50d0a0f9
GH		 1489 /*
1490 * The guest calculates current wall clock time by adding
34c238a1 1491 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1492 * wall clock specified here. guest system time equals host
1493 * system time for us, thus we must fill in host boot time here.
1494 */
87aeb54f 1495 getboottime64(&boot);
50d0a0f9 1496
4b648665 1497 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1498 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1499 boot = timespec64_sub(boot, ts);
4b648665 1500 }
87aeb54f 1501 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1502 wc.nsec = boot.tv_nsec;
1503 wc.version = version;
18068523
GOC		 1504
1505 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1506
1507 version++;
1508 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1509}
1510
50d0a0f9
GH		 1511static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1512{
b51012de
PB		 1513 do_shl32_div32(dividend, divisor);
1514 return dividend;
50d0a0f9
GH		 1515}
1516
3ae13faa 1517static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1518 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1519{
5f4e3f88 1520 uint64_t scaled64;
50d0a0f9
GH		 1521 int32_t shift = 0;
1522 uint64_t tps64;
1523 uint32_t tps32;
1524
3ae13faa
PB		 1525 tps64 = base_hz;
1526 scaled64 = scaled_hz;
50933623 1527 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1528 tps64 >>= 1;
1529 shift--;
1530 }
1531
1532 tps32 = (uint32_t)tps64;
50933623
JK		 1533 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1534 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1535 scaled64 >>= 1;
1536 else
1537 tps32 <<= 1;
50d0a0f9
GH		 1538 shift++;
1539 }
1540
5f4e3f88
ZA		 1541 *pshift = shift;
1542 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9
GH		 1543}
1544
d828199e 1545#ifdef CONFIG_X86_64
16e8d74d 1546static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1547#endif
16e8d74d 1548
c8076604 1549static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1550static unsigned long max_tsc_khz;
c8076604 1551
cc578287 1552static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1553{
cc578287
ZA		 1554 u64 v = (u64)khz * (1000000 + ppm);
1555 do_div(v, 1000000);
1556 return v;
1e993611
JR		 1557}
1558
381d585c
HZ		 1559static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1560{
1561 u64 ratio;
1562
1563 /* Guest TSC same frequency as host TSC? */
1564 if (!scale) {
1565 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1566 return 0;
1567 }
1568
1569 /* TSC scaling supported? */
1570 if (!kvm_has_tsc_control) {
1571 if (user_tsc_khz > tsc_khz) {
1572 vcpu->arch.tsc_catchup = 1;
1573 vcpu->arch.tsc_always_catchup = 1;
1574 return 0;
1575 } else {
3f16a5c3 1576 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
381d585c
HZ		 1577 return -1;
1578 }
1579 }
1580
1581 /* TSC scaling required - calculate ratio */
1582 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1583 user_tsc_khz, tsc_khz);
1584
1585 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
3f16a5c3
PB		 1586 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1587 user_tsc_khz);
381d585c
HZ		 1588 return -1;
1589 }
1590
1591 vcpu->arch.tsc_scaling_ratio = ratio;
1592 return 0;
1593}
1594
4941b8cb 1595static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1596{
cc578287
ZA		 1597 u32 thresh_lo, thresh_hi;
1598 int use_scaling = 0;
217fc9cf 1599
03ba32ca 1600 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1601 if (user_tsc_khz == 0) {
ad721883
HZ		 1602 /* set tsc_scaling_ratio to a safe value */
1603 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1604 return -1;
ad721883 1605 }
03ba32ca 1606
c285545f 1607 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1608 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1609 &vcpu->arch.virtual_tsc_shift,
1610 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1611 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1612
1613 /*
1614 * Compute the variation in TSC rate which is acceptable
1615 * within the range of tolerance and decide if the
1616 * rate being applied is within that bounds of the hardware
1617 * rate. If so, no scaling or compensation need be done.
1618 */
1619 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1620 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1621 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1622 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1623 use_scaling = 1;
1624 }
4941b8cb 1625 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1626}
1627
1628static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1629{
e26101b1 1630 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1631 vcpu->arch.virtual_tsc_mult,
1632 vcpu->arch.virtual_tsc_shift);
e26101b1 1633 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1634 return tsc;
1635}
1636
b0c39dc6
VK		 1637static inline int gtod_is_based_on_tsc(int mode)
1638{
1639 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1640}
1641
69b0049a 1642static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1643{
1644#ifdef CONFIG_X86_64
1645 bool vcpus_matched;
b48aa97e
MT		 1646 struct kvm_arch *ka = &vcpu->kvm->arch;
1647 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1648
1649 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1650 atomic_read(&vcpu->kvm->online_vcpus));
1651
7f187922
MT		 1652 /*
1653 * Once the masterclock is enabled, always perform request in
1654 * order to update it.
1655 *
1656 * In order to enable masterclock, the host clocksource must be TSC
1657 * and the vcpus need to have matched TSCs. When that happens,
1658 * perform request to enable masterclock.
1659 */
1660 if (ka->use_master_clock ||
b0c39dc6 1661 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1662 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1663
1664 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1665 atomic_read(&vcpu->kvm->online_vcpus),
1666 ka->use_master_clock, gtod->clock.vclock_mode);
1667#endif
1668}
1669
ba904635
WA		 1670static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1671{
e79f245d 1672 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1673 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1674}
1675
35181e86
HZ		 1676/*
1677 * Multiply tsc by a fixed point number represented by ratio.
1678 *
1679 * The most significant 64-N bits (mult) of ratio represent the
1680 * integral part of the fixed point number; the remaining N bits
1681 * (frac) represent the fractional part, ie. ratio represents a fixed
1682 * point number (mult + frac * 2^(-N)).
1683 *
1684 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1685 */
1686static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1687{
1688 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1689}
1690
1691u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1692{
1693 u64 _tsc = tsc;
1694 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1695
1696 if (ratio != kvm_default_tsc_scaling_ratio)
1697 _tsc = __scale_tsc(ratio, tsc);
1698
1699 return _tsc;
1700}
1701EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1702
07c1419a
HZ		 1703static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1704{
1705 u64 tsc;
1706
1707 tsc = kvm_scale_tsc(vcpu, rdtsc());
1708
1709 return target_tsc - tsc;
1710}
1711
4ba76538
HZ		 1712u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1713{
e79f245d
KA		 1714 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1715
1716 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1717}
1718EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1719
a545ab6a
LC		 1720static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1721{
326e7425 1722 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1723}
1724
b0c39dc6
VK		 1725static inline bool kvm_check_tsc_unstable(void)
1726{
1727#ifdef CONFIG_X86_64
1728 /*
1729 * TSC is marked unstable when we're running on Hyper-V,
1730 * 'TSC page' clocksource is good.
1731 */
1732 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1733 return false;
1734#endif
1735 return check_tsc_unstable();
1736}
1737
8fe8ab46 1738void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1739{
1740 struct kvm *kvm = vcpu->kvm;
f38e098f 1741 u64 offset, ns, elapsed;
99e3e30a 1742 unsigned long flags;
b48aa97e 1743 bool matched;
0d3da0d2 1744 bool already_matched;
8fe8ab46 1745 u64 data = msr->data;
c5e8ec8e 1746 bool synchronizing = false;
99e3e30a 1747
038f8c11 1748 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1749 offset = kvm_compute_tsc_offset(vcpu, data);
9285ec4c 1750 ns = ktime_get_boottime_ns();
f38e098f 1751 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1752
03ba32ca 1753 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1754 if (data == 0 && msr->host_initiated) {
1755 /*
1756 * detection of vcpu initialization -- need to sync
1757 * with other vCPUs. This particularly helps to keep
1758 * kvm_clock stable after CPU hotplug
1759 */
1760 synchronizing = true;
1761 } else {
1762 u64 tsc_exp = kvm->arch.last_tsc_write +
1763 nsec_to_cycles(vcpu, elapsed);
1764 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1765 /*
1766 * Special case: TSC write with a small delta (1 second)
1767 * of virtual cycle time against real time is
1768 * interpreted as an attempt to synchronize the CPU.
1769 */
1770 synchronizing = data < tsc_exp + tsc_hz &&
1771 data + tsc_hz > tsc_exp;
1772 }
c5e8ec8e 1773 }
f38e098f
ZA		 1774
1775 /*
5d3cb0f6
ZA		 1776 * For a reliable TSC, we can match TSC offsets, and for an unstable
1777 * TSC, we add elapsed time in this computation. We could let the
1778 * compensation code attempt to catch up if we fall behind, but
1779 * it's better to try to match offsets from the beginning.
1780 */
c5e8ec8e 1781 if (synchronizing &&
5d3cb0f6 1782 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1783 if (!kvm_check_tsc_unstable()) {
e26101b1 1784 offset = kvm->arch.cur_tsc_offset;
f38e098f 1785 } else {
857e4099 1786 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1787 data += delta;
07c1419a 1788 offset = kvm_compute_tsc_offset(vcpu, data);
f38e098f 1789 }
b48aa97e 1790 matched = true;
0d3da0d2 1791 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1792 } else {
1793 /*
1794 * We split periods of matched TSC writes into generations.
1795 * For each generation, we track the original measured
1796 * nanosecond time, offset, and write, so if TSCs are in
1797 * sync, we can match exact offset, and if not, we can match
4a969980 1798 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1799 *
1800 * These values are tracked in kvm->arch.cur_xxx variables.
1801 */
1802 kvm->arch.cur_tsc_generation++;
1803 kvm->arch.cur_tsc_nsec = ns;
1804 kvm->arch.cur_tsc_write = data;
1805 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1806 matched = false;
f38e098f 1807 }
e26101b1
ZA		 1808
1809 /*
1810 * We also track th most recent recorded KHZ, write and time to
1811 * allow the matching interval to be extended at each write.
1812 */
f38e098f
ZA		 1813 kvm->arch.last_tsc_nsec = ns;
1814 kvm->arch.last_tsc_write = data;
5d3cb0f6 1815 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1816
b183aa58 1817 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1818
1819 /* Keep track of which generation this VCPU has synchronized to */
1820 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1821 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1822 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1823
d6321d49 1824 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1825 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1826
a545ab6a 1827 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1828 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1829
1830 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1831 if (!matched) {
b48aa97e 1832 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1833 } else if (!already_matched) {
1834 kvm->arch.nr_vcpus_matched_tsc++;
1835 }
b48aa97e
MT		 1836
1837 kvm_track_tsc_matching(vcpu);
1838 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1839}
e26101b1 1840
99e3e30a
ZA		 1841EXPORT_SYMBOL_GPL(kvm_write_tsc);
1842
58ea6767
HZ		 1843static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1844 s64 adjustment)
1845{
326e7425
LS		 1846 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1847 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1848}
1849
1850static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1851{
1852 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1853 WARN_ON(adjustment < 0);
1854 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1855 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1856}
1857
d828199e
MT		 1858#ifdef CONFIG_X86_64
1859
a5a1d1c2 1860static u64 read_tsc(void)
d828199e 1861{
a5a1d1c2 1862 u64 ret = (u64)rdtsc_ordered();
03b9730b 1863 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1864
1865 if (likely(ret >= last))
1866 return ret;
1867
1868 /*
1869 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1870 * predictable (it's just a function of time and the likely is
d828199e
MT		 1871 * very likely) and there's a data dependence, so force GCC
1872 * to generate a branch instead. I don't barrier() because
1873 * we don't actually need a barrier, and if this function
1874 * ever gets inlined it will generate worse code.
1875 */
1876 asm volatile ("");
1877 return last;
1878}
1879
b0c39dc6 1880static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1881{
1882 long v;
1883 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1884 u64 tsc_pg_val;
1885
1886 switch (gtod->clock.vclock_mode) {
1887 case VCLOCK_HVCLOCK:
1888 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1889 tsc_timestamp);
1890 if (tsc_pg_val != U64_MAX) {
1891 /* TSC page valid */
1892 *mode = VCLOCK_HVCLOCK;
1893 v = (tsc_pg_val - gtod->clock.cycle_last) &
1894 gtod->clock.mask;
1895 } else {
1896 /* TSC page invalid */
1897 *mode = VCLOCK_NONE;
1898 }
1899 break;
1900 case VCLOCK_TSC:
1901 *mode = VCLOCK_TSC;
1902 *tsc_timestamp = read_tsc();
1903 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1904 gtod->clock.mask;
1905 break;
1906 default:
1907 *mode = VCLOCK_NONE;
1908 }
d828199e 1909
b0c39dc6
VK		 1910 if (*mode == VCLOCK_NONE)
1911 *tsc_timestamp = v = 0;
d828199e 1912
d828199e
MT		 1913 return v * gtod->clock.mult;
1914}
1915
b0c39dc6 1916static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1917{
cbcf2dd3 1918 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1919 unsigned long seq;
d828199e 1920 int mode;
cbcf2dd3 1921 u64 ns;
d828199e 1922
d828199e
MT		 1923 do {
1924 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1925 ns = gtod->nsec_base;
b0c39dc6 1926 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1927 ns >>= gtod->clock.shift;
cbcf2dd3 1928 ns += gtod->boot_ns;
d828199e 1929 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1930 *t = ns;
d828199e
MT		 1931
1932 return mode;
1933}
1934
899a31f5 1935static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1936{
1937 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1938 unsigned long seq;
1939 int mode;
1940 u64 ns;
1941
1942 do {
1943 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1944 ts->tv_sec = gtod->wall_time_sec;
1945 ns = gtod->nsec_base;
b0c39dc6 1946 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1947 ns >>= gtod->clock.shift;
1948 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1949
1950 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1951 ts->tv_nsec = ns;
1952
1953 return mode;
1954}
1955
b0c39dc6
VK		 1956/* returns true if host is using TSC based clocksource */
1957static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1958{
d828199e 1959 /* checked again under seqlock below */
b0c39dc6 1960 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1961 return false;
1962
b0c39dc6
VK		 1963 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1964 tsc_timestamp));
d828199e 1965}
55dd00a7 1966
b0c39dc6 1967/* returns true if host is using TSC based clocksource */
899a31f5 1968static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1969 u64 *tsc_timestamp)
55dd00a7
MT		 1970{
1971 /* checked again under seqlock below */
b0c39dc6 1972 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1973 return false;
1974
b0c39dc6 1975 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1976}
d828199e
MT		 1977#endif
1978
1979/*
1980 *
b48aa97e
MT		 1981 * Assuming a stable TSC across physical CPUS, and a stable TSC
1982 * across virtual CPUs, the following condition is possible.
1983 * Each numbered line represents an event visible to both
d828199e
MT		 1984 * CPUs at the next numbered event.
1985 *
1986 * "timespecX" represents host monotonic time. "tscX" represents
1987 * RDTSC value.
1988 *
1989 * VCPU0 on CPU0 | VCPU1 on CPU1
1990 *
1991 * 1. read timespec0,tsc0
1992 * 2. | timespec1 = timespec0 + N
1993 * | tsc1 = tsc0 + M
1994 * 3. transition to guest | transition to guest
1995 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1996 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1997 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1998 *
1999 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2000 *
2001 * - ret0 < ret1
2002 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2003 * ...
2004 * - 0 < N - M => M < N
2005 *
2006 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2007 * always the case (the difference between two distinct xtime instances
2008 * might be smaller then the difference between corresponding TSC reads,
2009 * when updating guest vcpus pvclock areas).
2010 *
2011 * To avoid that problem, do not allow visibility of distinct
2012 * system_timestamp/tsc_timestamp values simultaneously: use a master
2013 * copy of host monotonic time values. Update that master copy
2014 * in lockstep.
2015 *
b48aa97e 2016 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 2017 *
2018 */
2019
2020static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2021{
2022#ifdef CONFIG_X86_64
2023 struct kvm_arch *ka = &kvm->arch;
2024 int vclock_mode;
b48aa97e
MT		 2025 bool host_tsc_clocksource, vcpus_matched;
2026
2027 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2028 atomic_read(&kvm->online_vcpus));
d828199e
MT		 2029
2030 /*
2031 * If the host uses TSC clock, then passthrough TSC as stable
2032 * to the guest.
2033 */
b48aa97e 2034 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 2035 &ka->master_kernel_ns,
2036 &ka->master_cycle_now);
2037
16a96021 2038 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2039 && !ka->backwards_tsc_observed
54750f2c 2040 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2041
d828199e
MT		 2042 if (ka->use_master_clock)
2043 atomic_set(&kvm_guest_has_master_clock, 1);
2044
2045 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2046 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2047 vcpus_matched);
d828199e
MT		 2048#endif
2049}
2050
2860c4b1
PB		 2051void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2052{
2053 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2054}
2055
2e762ff7
MT		 2056static void kvm_gen_update_masterclock(struct kvm *kvm)
2057{
2058#ifdef CONFIG_X86_64
2059 int i;
2060 struct kvm_vcpu *vcpu;
2061 struct kvm_arch *ka = &kvm->arch;
2062
2063 spin_lock(&ka->pvclock_gtod_sync_lock);
2064 kvm_make_mclock_inprogress_request(kvm);
2065 /* no guest entries from this point */
2066 pvclock_update_vm_gtod_copy(kvm);
2067
2068 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2069 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2070
2071 /* guest entries allowed */
2072 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2073 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2074
2075 spin_unlock(&ka->pvclock_gtod_sync_lock);
2076#endif
2077}
2078
e891a32e 2079u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2080{
108b249c 2081 struct kvm_arch *ka = &kvm->arch;
8b953440 2082 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2083 u64 ret;
108b249c 2084
8b953440
PB		 2085 spin_lock(&ka->pvclock_gtod_sync_lock);
2086 if (!ka->use_master_clock) {
2087 spin_unlock(&ka->pvclock_gtod_sync_lock);
9285ec4c 2088 return ktime_get_boottime_ns() + ka->kvmclock_offset;
108b249c
PB		 2089 }
2090
8b953440
PB		 2091 hv_clock.tsc_timestamp = ka->master_cycle_now;
2092 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2093 spin_unlock(&ka->pvclock_gtod_sync_lock);
2094
e2c2206a
WL		 2095 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2096 get_cpu();
2097
e70b57a6
WL		 2098 if (__this_cpu_read(cpu_tsc_khz)) {
2099 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2100 &hv_clock.tsc_shift,
2101 &hv_clock.tsc_to_system_mul);
2102 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2103 } else
9285ec4c 2104 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2105
2106 put_cpu();
2107
2108 return ret;
108b249c
PB		 2109}
2110
0d6dd2ff
PB		 2111static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2112{
2113 struct kvm_vcpu_arch *vcpu = &v->arch;
2114 struct pvclock_vcpu_time_info guest_hv_clock;
2115
4e335d9e 2116 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2117 &guest_hv_clock, sizeof(guest_hv_clock))))
2118 return;
2119
2120 /* This VCPU is paused, but it's legal for a guest to read another
2121 * VCPU's kvmclock, so we really have to follow the specification where
2122 * it says that version is odd if data is being modified, and even after
2123 * it is consistent.
2124 *
2125 * Version field updates must be kept separate. This is because
2126 * kvm_write_guest_cached might use a "rep movs" instruction, and
2127 * writes within a string instruction are weakly ordered. So there
2128 * are three writes overall.
2129 *
2130 * As a small optimization, only write the version field in the first
2131 * and third write. The vcpu->pv_time cache is still valid, because the
2132 * version field is the first in the struct.
2133 */
2134 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2135
51c4b8bb
LA		 2136 if (guest_hv_clock.version & 1)
2137 ++guest_hv_clock.version; /* first time write, random junk */
2138
0d6dd2ff 2139 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2140 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2141 &vcpu->hv_clock,
2142 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2143
2144 smp_wmb();
2145
2146 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2147 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2148
2149 if (vcpu->pvclock_set_guest_stopped_request) {
2150 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2151 vcpu->pvclock_set_guest_stopped_request = false;
2152 }
2153
2154 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2155
4e335d9e
PB		 2156 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2157 &vcpu->hv_clock,
2158 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2159
2160 smp_wmb();
2161
2162 vcpu->hv_clock.version++;
4e335d9e
PB		 2163 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2164 &vcpu->hv_clock,
2165 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2166}
2167
34c238a1 2168static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2169{
78db6a50 2170 unsigned long flags, tgt_tsc_khz;
18068523 2171 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2172 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2173 s64 kernel_ns;
d828199e 2174 u64 tsc_timestamp, host_tsc;
51d59c6b 2175 u8 pvclock_flags;
d828199e
MT		 2176 bool use_master_clock;
2177
2178 kernel_ns = 0;
2179 host_tsc = 0;
18068523 2180
d828199e
MT		 2181 /*
2182 * If the host uses TSC clock, then passthrough TSC as stable
2183 * to the guest.
2184 */
2185 spin_lock(&ka->pvclock_gtod_sync_lock);
2186 use_master_clock = ka->use_master_clock;
2187 if (use_master_clock) {
2188 host_tsc = ka->master_cycle_now;
2189 kernel_ns = ka->master_kernel_ns;
2190 }
2191 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2192
2193 /* Keep irq disabled to prevent changes to the clock */
2194 local_irq_save(flags);
78db6a50
PB		 2195 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2196 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2197 local_irq_restore(flags);
2198 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2199 return 1;
2200 }
d828199e 2201 if (!use_master_clock) {
4ea1636b 2202 host_tsc = rdtsc();
9285ec4c 2203 kernel_ns = ktime_get_boottime_ns();
d828199e
MT		 2204 }
2205
4ba76538 2206 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2207
c285545f
ZA		 2208 /*
2209 * We may have to catch up the TSC to match elapsed wall clock
2210 * time for two reasons, even if kvmclock is used.
2211 * 1) CPU could have been running below the maximum TSC rate
2212 * 2) Broken TSC compensation resets the base at each VCPU
2213 * entry to avoid unknown leaps of TSC even when running
2214 * again on the same CPU. This may cause apparent elapsed
2215 * time to disappear, and the guest to stand still or run
2216 * very slowly.
2217 */
2218 if (vcpu->tsc_catchup) {
2219 u64 tsc = compute_guest_tsc(v, kernel_ns);
2220 if (tsc > tsc_timestamp) {
f1e2b260 2221 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2222 tsc_timestamp = tsc;
2223 }
50d0a0f9
GH		 2224 }
2225
18068523
GOC		 2226 local_irq_restore(flags);
2227
0d6dd2ff 2228 /* With all the info we got, fill in the values */
18068523 2229
78db6a50
PB		 2230 if (kvm_has_tsc_control)
2231 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2232
2233 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2234 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2235 &vcpu->hv_clock.tsc_shift,
2236 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2237 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2238 }
2239
1d5f066e 2240 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2241 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2242 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2243
d828199e 2244 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2245 pvclock_flags = 0;
d828199e
MT		 2246 if (use_master_clock)
2247 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2248
78c0337a
MT		 2249 vcpu->hv_clock.flags = pvclock_flags;
2250
095cf55d
PB		 2251 if (vcpu->pv_time_enabled)
2252 kvm_setup_pvclock_page(v);
2253 if (v == kvm_get_vcpu(v->kvm, 0))
2254 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2255 return 0;
c8076604
GH		 2256}
2257
0061d53d
MT		 2258/*
2259 * kvmclock updates which are isolated to a given vcpu, such as
2260 * vcpu->cpu migration, should not allow system_timestamp from
2261 * the rest of the vcpus to remain static. Otherwise ntp frequency
2262 * correction applies to one vcpu's system_timestamp but not
2263 * the others.
2264 *
2265 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2266 * We need to rate-limit these requests though, as they can
2267 * considerably slow guests that have a large number of vcpus.
2268 * The time for a remote vcpu to update its kvmclock is bound
2269 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2270 */
2271
7e44e449
AJ		 2272#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2273
2274static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2275{
2276 int i;
7e44e449
AJ		 2277 struct delayed_work *dwork = to_delayed_work(work);
2278 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2279 kvmclock_update_work);
2280 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2281 struct kvm_vcpu *vcpu;
2282
2283 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2284 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2285 kvm_vcpu_kick(vcpu);
2286 }
2287}
2288
7e44e449
AJ		 2289static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2290{
2291 struct kvm *kvm = v->kvm;
2292
105b21bb 2293 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2294 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2295 KVMCLOCK_UPDATE_DELAY);
2296}
2297
332967a3
AJ		 2298#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2299
2300static void kvmclock_sync_fn(struct work_struct *work)
2301{
2302 struct delayed_work *dwork = to_delayed_work(work);
2303 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2304 kvmclock_sync_work);
2305 struct kvm *kvm = container_of(ka, struct kvm, arch);
2306
630994b3
MT		 2307 if (!kvmclock_periodic_sync)
2308 return;
2309
332967a3
AJ		 2310 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2311 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2312 KVMCLOCK_SYNC_PERIOD);
2313}
2314
191c8137
BP		 2315/*
2316 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2317 */
2318static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2319{
2320 /* McStatusWrEn enabled? */
2321 if (guest_cpuid_is_amd(vcpu))
2322 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2323
2324 return false;
2325}
2326
9ffd986c 2327static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2328{
890ca9ae
HY		 2329 u64 mcg_cap = vcpu->arch.mcg_cap;
2330 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2331 u32 msr = msr_info->index;
2332 u64 data = msr_info->data;
890ca9ae 2333
15c4a640 2334 switch (msr) {
15c4a640 2335 case MSR_IA32_MCG_STATUS:
890ca9ae 2336 vcpu->arch.mcg_status = data;
15c4a640 2337 break;
c7ac679c 2338 case MSR_IA32_MCG_CTL:
44883f01
PB		 2339 if (!(mcg_cap & MCG_CTL_P) &&
2340 (data || !msr_info->host_initiated))
890ca9ae
HY		 2341 return 1;
2342 if (data != 0 && data != ~(u64)0)
44883f01 2343 return 1;
890ca9ae
HY		 2344 vcpu->arch.mcg_ctl = data;
2345 break;
2346 default:
2347 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2348 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2349 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2350 /* only 0 or all 1s can be written to IA32_MCi_CTL
2351 * some Linux kernels though clear bit 10 in bank 4 to
2352 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2353 * this to avoid an uncatched #GP in the guest
2354 */
890ca9ae 2355 if ((offset & 0x3) == 0 &&
114be429 2356 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2357 return -1;
191c8137
BP		 2358
2359 /* MCi_STATUS */
9ffd986c 2360 if (!msr_info->host_initiated &&
191c8137
BP		 2361 (offset & 0x3) == 1 && data != 0) {
2362 if (!can_set_mci_status(vcpu))
2363 return -1;
2364 }
2365
890ca9ae
HY		 2366 vcpu->arch.mce_banks[offset] = data;
2367 break;
2368 }
2369 return 1;
2370 }
2371 return 0;
2372}
2373
ffde22ac
ES		 2374static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2375{
2376 struct kvm *kvm = vcpu->kvm;
2377 int lm = is_long_mode(vcpu);
2378 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2379 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2380 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2381 : kvm->arch.xen_hvm_config.blob_size_32;
2382 u32 page_num = data & ~PAGE_MASK;
2383 u64 page_addr = data & PAGE_MASK;
2384 u8 *page;
2385 int r;
2386
2387 r = -E2BIG;
2388 if (page_num >= blob_size)
2389 goto out;
2390 r = -ENOMEM;
ff5c2c03
SL		 2391 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2392 if (IS_ERR(page)) {
2393 r = PTR_ERR(page);
ffde22ac 2394 goto out;
ff5c2c03 2395 }
54bf36aa 2396 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2397 goto out_free;
2398 r = 0;
2399out_free:
2400 kfree(page);
2401out:
2402 return r;
2403}
2404
344d9588
GN		 2405static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2406{
2407 gpa_t gpa = data & ~0x3f;
2408
52a5c155
WL		 2409 /* Bits 3:5 are reserved, Should be zero */
2410 if (data & 0x38)
344d9588
GN		 2411 return 1;
2412
2413 vcpu->arch.apf.msr_val = data;
2414
2415 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2416 kvm_clear_async_pf_completion_queue(vcpu);
2417 kvm_async_pf_hash_reset(vcpu);
2418 return 0;
2419 }
2420
4e335d9e 2421 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2422 sizeof(u32)))
344d9588
GN		 2423 return 1;
2424
6adba527 2425 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2426 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2427 kvm_async_pf_wakeup_all(vcpu);
2428 return 0;
2429}
2430
12f9a48f
GC		 2431static void kvmclock_reset(struct kvm_vcpu *vcpu)
2432{
0b79459b 2433 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2434}
2435
f38a7b75
WL		 2436static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2437{
2438 ++vcpu->stat.tlb_flush;
2439 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2440}
2441
c9aaa895
GC		 2442static void record_steal_time(struct kvm_vcpu *vcpu)
2443{
2444 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2445 return;
2446
4e335d9e 2447 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2448 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2449 return;
2450
f38a7b75
WL		 2451 /*
2452 * Doing a TLB flush here, on the guest's behalf, can avoid
2453 * expensive IPIs.
2454 */
2455 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2456 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2457
35f3fae1
WL		 2458 if (vcpu->arch.st.steal.version & 1)
2459 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2460
2461 vcpu->arch.st.steal.version += 1;
2462
4e335d9e 2463 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2464 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2465
2466 smp_wmb();
2467
c54cdf14
LC		 2468 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2469 vcpu->arch.st.last_steal;
2470 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2471
4e335d9e 2472 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2473 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2474
2475 smp_wmb();
2476
2477 vcpu->arch.st.steal.version += 1;
c9aaa895 2478
4e335d9e 2479 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2480 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2481}
2482
8fe8ab46 2483int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2484{
5753785f 2485 bool pr = false;
8fe8ab46
WA		 2486 u32 msr = msr_info->index;
2487 u64 data = msr_info->data;
5753785f 2488
15c4a640 2489 switch (msr) {
2e32b719 2490 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2491 case MSR_IA32_UCODE_WRITE:
2492 case MSR_VM_HSAVE_PA:
2493 case MSR_AMD64_PATCH_LOADER:
2494 case MSR_AMD64_BU_CFG2:
405a353a 2495 case MSR_AMD64_DC_CFG:
0e1b869f 2496 case MSR_F15H_EX_CFG:
2e32b719
BP		 2497 break;
2498
518e7b94
WL		 2499 case MSR_IA32_UCODE_REV:
2500 if (msr_info->host_initiated)
2501 vcpu->arch.microcode_version = data;
2502 break;
0cf9135b
SC		 2503 case MSR_IA32_ARCH_CAPABILITIES:
2504 if (!msr_info->host_initiated)
2505 return 1;
2506 vcpu->arch.arch_capabilities = data;
2507 break;
15c4a640 2508 case MSR_EFER:
11988499 2509 return set_efer(vcpu, msr_info);
8f1589d9
AP		 2510 case MSR_K7_HWCR:
2511 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2512 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2513 data &= ~(u64)0x8; /* ignore TLB cache disable */
191c8137
BP		 2514
2515 /* Handle McStatusWrEn */
2516 if (data == BIT_ULL(18)) {
2517 vcpu->arch.msr_hwcr = data;
2518 } else if (data != 0) {
a737f256
CD		 2519 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2520 data);
8f1589d9
AP		 2521 return 1;
2522 }
15c4a640 2523 break;
f7c6d140
AP		 2524 case MSR_FAM10H_MMIO_CONF_BASE:
2525 if (data != 0) {
a737f256
CD		 2526 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2527 "0x%llx\n", data);
f7c6d140
AP		 2528 return 1;
2529 }
15c4a640 2530 break;
b5e2fec0
AG		 2531 case MSR_IA32_DEBUGCTLMSR:
2532 if (!data) {
2533 /* We support the non-activated case already */
2534 break;
2535 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2536 /* Values other than LBR and BTF are vendor-specific,
2537 thus reserved and should throw a #GP */
2538 return 1;
2539 }
a737f256
CD		 2540 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2541 __func__, data);
b5e2fec0 2542 break;
9ba075a6 2543 case 0x200 ... 0x2ff:
ff53604b 2544 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2545 case MSR_IA32_APICBASE:
58cb628d 2546 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2547 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2548 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2549 case MSR_IA32_TSCDEADLINE:
2550 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2551 break;
ba904635 2552 case MSR_IA32_TSC_ADJUST:
d6321d49 2553 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2554 if (!msr_info->host_initiated) {
d913b904 2555 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2556 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2557 }
2558 vcpu->arch.ia32_tsc_adjust_msr = data;
2559 }
2560 break;
15c4a640 2561 case MSR_IA32_MISC_ENABLE:
511a8556
WL		 2562 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2563 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2564 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2565 return 1;
2566 vcpu->arch.ia32_misc_enable_msr = data;
2567 kvm_update_cpuid(vcpu);
2568 } else {
2569 vcpu->arch.ia32_misc_enable_msr = data;
2570 }
15c4a640 2571 break;
64d60670
PB		 2572 case MSR_IA32_SMBASE:
2573 if (!msr_info->host_initiated)
2574 return 1;
2575 vcpu->arch.smbase = data;
2576 break;
73f624f4
PB		 2577 case MSR_IA32_POWER_CTL:
2578 vcpu->arch.msr_ia32_power_ctl = data;
2579 break;
dd259935
PB		 2580 case MSR_IA32_TSC:
2581 kvm_write_tsc(vcpu, msr_info);
2582 break;
52797bf9
LA		 2583 case MSR_SMI_COUNT:
2584 if (!msr_info->host_initiated)
2585 return 1;
2586 vcpu->arch.smi_count = data;
2587 break;
11c6bffa 2588 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2589 case MSR_KVM_WALL_CLOCK:
2590 vcpu->kvm->arch.wall_clock = data;
2591 kvm_write_wall_clock(vcpu->kvm, data);
2592 break;
11c6bffa 2593 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2594 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2595 struct kvm_arch *ka = &vcpu->kvm->arch;
2596
12f9a48f 2597 kvmclock_reset(vcpu);
18068523 2598
54750f2c
MT		 2599 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2600 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2601
2602 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2603 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2604
2605 ka->boot_vcpu_runs_old_kvmclock = tmp;
2606 }
2607
18068523 2608 vcpu->arch.time = data;
0061d53d 2609 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2610
2611 /* we verify if the enable bit is set... */
2612 if (!(data & 1))
2613 break;
2614
4e335d9e 2615 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2616 &vcpu->arch.pv_time, data & ~1ULL,
2617 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2618 vcpu->arch.pv_time_enabled = false;
2619 else
2620 vcpu->arch.pv_time_enabled = true;
32cad84f 2621
18068523
GOC		 2622 break;
2623 }
344d9588
GN		 2624 case MSR_KVM_ASYNC_PF_EN:
2625 if (kvm_pv_enable_async_pf(vcpu, data))
2626 return 1;
2627 break;
c9aaa895
GC		 2628 case MSR_KVM_STEAL_TIME:
2629
2630 if (unlikely(!sched_info_on()))
2631 return 1;
2632
2633 if (data & KVM_STEAL_RESERVED_MASK)
2634 return 1;
2635
4e335d9e 2636 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2637 data & KVM_STEAL_VALID_BITS,
2638 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2639 return 1;
2640
2641 vcpu->arch.st.msr_val = data;
2642
2643 if (!(data & KVM_MSR_ENABLED))
2644 break;
2645
c9aaa895
GC		 2646 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2647
2648 break;
ae7a2a3f 2649 case MSR_KVM_PV_EOI_EN:
72bbf935 2650 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2651 return 1;
2652 break;
c9aaa895 2653
2d5ba19b
MT		 2654 case MSR_KVM_POLL_CONTROL:
2655 /* only enable bit supported */
2656 if (data & (-1ULL << 1))
2657 return 1;
2658
2659 vcpu->arch.msr_kvm_poll_control = data;
2660 break;
2661
890ca9ae
HY		 2662 case MSR_IA32_MCG_CTL:
2663 case MSR_IA32_MCG_STATUS:
81760dcc 2664 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2665 return set_msr_mce(vcpu, msr_info);
71db6023 2666
6912ac32
WH		 2667 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2668 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2669 pr = true; /* fall through */
2670 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2671 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2672 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2673 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2674
2675 if (pr || data != 0)
a737f256
CD		 2676 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2677 "0x%x data 0x%llx\n", msr, data);
5753785f 2678 break;
84e0cefa
JS		 2679 case MSR_K7_CLK_CTL:
2680 /*
2681 * Ignore all writes to this no longer documented MSR.
2682 * Writes are only relevant for old K7 processors,
2683 * all pre-dating SVM, but a recommended workaround from
4a969980 2684 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2685 * affected processor models on the command line, hence
2686 * the need to ignore the workaround.
2687 */
2688 break;
55cd8e5a 2689 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2690 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2691 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2692 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2693 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2694 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2695 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2696 return kvm_hv_set_msr_common(vcpu, msr, data,
2697 msr_info->host_initiated);
91c9c3ed 2698 case MSR_IA32_BBL_CR_CTL3:
2699 /* Drop writes to this legacy MSR -- see rdmsr
2700 * counterpart for further detail.
2701 */
fab0aa3b
EM		 2702 if (report_ignored_msrs)
2703 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2704 msr, data);
91c9c3ed 2705 break;
2b036c6b 2706 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2707 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2708 return 1;
2709 vcpu->arch.osvw.length = data;
2710 break;
2711 case MSR_AMD64_OSVW_STATUS:
d6321d49 2712 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2713 return 1;
2714 vcpu->arch.osvw.status = data;
2715 break;
db2336a8
KH		 2716 case MSR_PLATFORM_INFO:
2717 if (!msr_info->host_initiated ||
db2336a8
KH		 2718 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2719 cpuid_fault_enabled(vcpu)))
2720 return 1;
2721 vcpu->arch.msr_platform_info = data;
2722 break;
2723 case MSR_MISC_FEATURES_ENABLES:
2724 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2725 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2726 !supports_cpuid_fault(vcpu)))
2727 return 1;
2728 vcpu->arch.msr_misc_features_enables = data;
2729 break;
15c4a640 2730 default:
ffde22ac
ES		 2731 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2732 return xen_hvm_config(vcpu, data);
c6702c9d 2733 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2734 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2735 if (!ignore_msrs) {
ae0f5499 2736 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2737 msr, data);
ed85c068
AP		 2738 return 1;
2739 } else {
fab0aa3b
EM		 2740 if (report_ignored_msrs)
2741 vcpu_unimpl(vcpu,
2742 "ignored wrmsr: 0x%x data 0x%llx\n",
2743 msr, data);
ed85c068
AP		 2744 break;
2745 }
15c4a640
CO		 2746 }
2747 return 0;
2748}
2749EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2750
2751
2752/*
2753 * Reads an msr value (of 'msr_index') into 'pdata'.
2754 * Returns 0 on success, non-0 otherwise.
2755 * Assumes vcpu_load() was already called.
2756 */
609e36d3 2757int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2758{
609e36d3 2759 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2760}
ff651cb6 2761EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2762
44883f01 2763static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2764{
2765 u64 data;
890ca9ae
HY		 2766 u64 mcg_cap = vcpu->arch.mcg_cap;
2767 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2768
2769 switch (msr) {
15c4a640
CO		 2770 case MSR_IA32_P5_MC_ADDR:
2771 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2772 data = 0;
2773 break;
15c4a640 2774 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2775 data = vcpu->arch.mcg_cap;
2776 break;
c7ac679c 2777 case MSR_IA32_MCG_CTL:
44883f01 2778 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2779 return 1;
2780 data = vcpu->arch.mcg_ctl;
2781 break;
2782 case MSR_IA32_MCG_STATUS:
2783 data = vcpu->arch.mcg_status;
2784 break;
2785 default:
2786 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2787 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2788 u32 offset = msr - MSR_IA32_MC0_CTL;
2789 data = vcpu->arch.mce_banks[offset];
2790 break;
2791 }
2792 return 1;
2793 }
2794 *pdata = data;
2795 return 0;
2796}
2797
609e36d3 2798int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2799{
609e36d3 2800 switch (msr_info->index) {
890ca9ae 2801 case MSR_IA32_PLATFORM_ID:
15c4a640 2802 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2803 case MSR_IA32_DEBUGCTLMSR:
2804 case MSR_IA32_LASTBRANCHFROMIP:
2805 case MSR_IA32_LASTBRANCHTOIP:
2806 case MSR_IA32_LASTINTFROMIP:
2807 case MSR_IA32_LASTINTTOIP:
60af2ecd 2808 case MSR_K8_SYSCFG:
3afb1121
PB		 2809 case MSR_K8_TSEG_ADDR:
2810 case MSR_K8_TSEG_MASK:
61a6bd67 2811 case MSR_VM_HSAVE_PA:
1fdbd48c 2812 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2813 case MSR_AMD64_NB_CFG:
f7c6d140 2814 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2815 case MSR_AMD64_BU_CFG2:
0c2df2a1 2816 case MSR_IA32_PERF_CTL:
405a353a 2817 case MSR_AMD64_DC_CFG:
0e1b869f 2818 case MSR_F15H_EX_CFG:
609e36d3 2819 msr_info->data = 0;
15c4a640 2820 break;
c51eb52b 2821 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2822 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2823 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2824 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2825 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2826 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2827 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2828 msr_info->data = 0;
5753785f 2829 break;
742bc670 2830 case MSR_IA32_UCODE_REV:
518e7b94 2831 msr_info->data = vcpu->arch.microcode_version;
742bc670 2832 break;
0cf9135b
SC		 2833 case MSR_IA32_ARCH_CAPABILITIES:
2834 if (!msr_info->host_initiated &&
2835 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2836 return 1;
2837 msr_info->data = vcpu->arch.arch_capabilities;
2838 break;
73f624f4
PB		 2839 case MSR_IA32_POWER_CTL:
2840 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2841 break;
dd259935
PB		 2842 case MSR_IA32_TSC:
2843 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2844 break;
9ba075a6 2845 case MSR_MTRRcap:
9ba075a6 2846 case 0x200 ... 0x2ff:
ff53604b 2847 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2848 case 0xcd: /* fsb frequency */
609e36d3 2849 msr_info->data = 3;
15c4a640 2850 break;
7b914098
JS		 2851 /*
2852 * MSR_EBC_FREQUENCY_ID
2853 * Conservative value valid for even the basic CPU models.
2854 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2855 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2856 * and 266MHz for model 3, or 4. Set Core Clock
2857 * Frequency to System Bus Frequency Ratio to 1 (bits
2858 * 31:24) even though these are only valid for CPU
2859 * models > 2, however guests may end up dividing or
2860 * multiplying by zero otherwise.
2861 */
2862 case MSR_EBC_FREQUENCY_ID:
609e36d3 2863 msr_info->data = 1 << 24;
7b914098 2864 break;
15c4a640 2865 case MSR_IA32_APICBASE:
609e36d3 2866 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2867 break;
0105d1a5 2868 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2869 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2870 break;
a3e06bbe 2871 case MSR_IA32_TSCDEADLINE:
609e36d3 2872 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2873 break;
ba904635 2874 case MSR_IA32_TSC_ADJUST:
609e36d3 2875 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2876 break;
15c4a640 2877 case MSR_IA32_MISC_ENABLE:
609e36d3 2878 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2879 break;
64d60670
PB		 2880 case MSR_IA32_SMBASE:
2881 if (!msr_info->host_initiated)
2882 return 1;
2883 msr_info->data = vcpu->arch.smbase;
15c4a640 2884 break;
52797bf9
LA		 2885 case MSR_SMI_COUNT:
2886 msr_info->data = vcpu->arch.smi_count;
2887 break;
847f0ad8
AG		 2888 case MSR_IA32_PERF_STATUS:
2889 /* TSC increment by tick */
609e36d3 2890 msr_info->data = 1000ULL;
847f0ad8 2891 /* CPU multiplier */
b0996ae4 2892 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2893 break;
15c4a640 2894 case MSR_EFER:
609e36d3 2895 msr_info->data = vcpu->arch.efer;
15c4a640 2896 break;
18068523 2897 case MSR_KVM_WALL_CLOCK:
11c6bffa 2898 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2899 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2900 break;
2901 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2902 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2903 msr_info->data = vcpu->arch.time;
18068523 2904 break;
344d9588 2905 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2906 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2907 break;
c9aaa895 2908 case MSR_KVM_STEAL_TIME:
609e36d3 2909 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2910 break;
1d92128f 2911 case MSR_KVM_PV_EOI_EN:
609e36d3 2912 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2913 break;
2d5ba19b
MT		 2914 case MSR_KVM_POLL_CONTROL:
2915 msr_info->data = vcpu->arch.msr_kvm_poll_control;
2916 break;
890ca9ae
HY		 2917 case MSR_IA32_P5_MC_ADDR:
2918 case MSR_IA32_P5_MC_TYPE:
2919 case MSR_IA32_MCG_CAP:
2920 case MSR_IA32_MCG_CTL:
2921 case MSR_IA32_MCG_STATUS:
81760dcc 2922 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2923 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2924 msr_info->host_initiated);
84e0cefa
JS		 2925 case MSR_K7_CLK_CTL:
2926 /*
2927 * Provide expected ramp-up count for K7. All other
2928 * are set to zero, indicating minimum divisors for
2929 * every field.
2930 *
2931 * This prevents guest kernels on AMD host with CPU
2932 * type 6, model 8 and higher from exploding due to
2933 * the rdmsr failing.
2934 */
609e36d3 2935 msr_info->data = 0x20000000;
84e0cefa 2936 break;
55cd8e5a 2937 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2938 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2939 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2940 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2941 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2942 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2943 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2944 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2945 msr_info->index, &msr_info->data,
2946 msr_info->host_initiated);
55cd8e5a 2947 break;
91c9c3ed 2948 case MSR_IA32_BBL_CR_CTL3:
2949 /* This legacy MSR exists but isn't fully documented in current
2950 * silicon. It is however accessed by winxp in very narrow
2951 * scenarios where it sets bit #19, itself documented as
2952 * a "reserved" bit. Best effort attempt to source coherent
2953 * read data here should the balance of the register be
2954 * interpreted by the guest:
2955 *
2956 * L2 cache control register 3: 64GB range, 256KB size,
2957 * enabled, latency 0x1, configured
2958 */
609e36d3 2959 msr_info->data = 0xbe702111;
91c9c3ed 2960 break;
2b036c6b 2961 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2962 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2963 return 1;
609e36d3 2964 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2965 break;
2966 case MSR_AMD64_OSVW_STATUS:
d6321d49 2967 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2968 return 1;
609e36d3 2969 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2970 break;
db2336a8 2971 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2972 if (!msr_info->host_initiated &&
2973 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2974 return 1;
db2336a8
KH		 2975 msr_info->data = vcpu->arch.msr_platform_info;
2976 break;
2977 case MSR_MISC_FEATURES_ENABLES:
2978 msr_info->data = vcpu->arch.msr_misc_features_enables;
2979 break;
191c8137
BP		 2980 case MSR_K7_HWCR:
2981 msr_info->data = vcpu->arch.msr_hwcr;
2982 break;
15c4a640 2983 default:
c6702c9d 2984 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2985 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2986 if (!ignore_msrs) {
ae0f5499
BD		 2987 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2988 msr_info->index);
ed85c068
AP		 2989 return 1;
2990 } else {
fab0aa3b
EM		 2991 if (report_ignored_msrs)
2992 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2993 msr_info->index);
609e36d3 2994 msr_info->data = 0;
ed85c068
AP		 2995 }
2996 break;
15c4a640 2997 }
15c4a640
CO		 2998 return 0;
2999}
3000EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3001
313a3dc7
CO		 3002/*
3003 * Read or write a bunch of msrs. All parameters are kernel addresses.
3004 *
3005 * @return number of msrs set successfully.
3006 */
3007static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3008 struct kvm_msr_entry *entries,
3009 int (*do_msr)(struct kvm_vcpu *vcpu,
3010 unsigned index, u64 *data))
3011{
801e459a 3012 int i;
313a3dc7 3013
313a3dc7
CO		 3014 for (i = 0; i < msrs->nmsrs; ++i)
3015 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3016 break;
3017
313a3dc7
CO		 3018 return i;
3019}
3020
3021/*
3022 * Read or write a bunch of msrs. Parameters are user addresses.
3023 *
3024 * @return number of msrs set successfully.
3025 */
3026static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3027 int (*do_msr)(struct kvm_vcpu *vcpu,
3028 unsigned index, u64 *data),
3029 int writeback)
3030{
3031 struct kvm_msrs msrs;
3032 struct kvm_msr_entry *entries;
3033 int r, n;
3034 unsigned size;
3035
3036 r = -EFAULT;
0e96f31e 3037 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 3038 goto out;
3039
3040 r = -E2BIG;
3041 if (msrs.nmsrs >= MAX_IO_MSRS)
3042 goto out;
3043
313a3dc7 3044 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 3045 entries = memdup_user(user_msrs->entries, size);
3046 if (IS_ERR(entries)) {
3047 r = PTR_ERR(entries);
313a3dc7 3048 goto out;
ff5c2c03 3049 }
313a3dc7
CO		 3050
3051 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3052 if (r < 0)
3053 goto out_free;
3054
3055 r = -EFAULT;
3056 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3057 goto out_free;
3058
3059 r = n;
3060
3061out_free:
7a73c028 3062 kfree(entries);
313a3dc7
CO		 3063out:
3064 return r;
3065}
3066
4d5422ce
WL		 3067static inline bool kvm_can_mwait_in_guest(void)
3068{
3069 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 3070 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3071 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 3072}
3073
784aa3d7 3074int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 3075{
4d5422ce 3076 int r = 0;
018d00d2
ZX		 3077
3078 switch (ext) {
3079 case KVM_CAP_IRQCHIP:
3080 case KVM_CAP_HLT:
3081 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 3082 case KVM_CAP_SET_TSS_ADDR:
07716717 3083 case KVM_CAP_EXT_CPUID:
9c15bb1d 3084 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3085 case KVM_CAP_CLOCKSOURCE:
7837699f 3086 case KVM_CAP_PIT:
a28e4f5a 3087 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3088 case KVM_CAP_MP_STATE:
ed848624 3089 case KVM_CAP_SYNC_MMU:
a355c85c 3090 case KVM_CAP_USER_NMI:
52d939a0 3091 case KVM_CAP_REINJECT_CONTROL:
4925663a 3092 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3093 case KVM_CAP_IOEVENTFD:
f848a5a8 3094 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3095 case KVM_CAP_PIT2:
e9f42757 3096 case KVM_CAP_PIT_STATE2:
b927a3ce 3097 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3098 case KVM_CAP_XEN_HVM:
3cfc3092 3099 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3100 case KVM_CAP_HYPERV:
10388a07 3101 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3102 case KVM_CAP_HYPERV_SPIN:
5c919412 3103 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3104 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3105 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3106 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3107 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3108 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 3109 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
2bc39970 3110 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3111 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3112 case KVM_CAP_DEBUGREGS:
d2be1651 3113 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3114 case KVM_CAP_XSAVE:
344d9588 3115 case KVM_CAP_ASYNC_PF:
92a1f12d 3116 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3117 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3118 case KVM_CAP_READONLY_MEM:
5f66b620 3119 case KVM_CAP_HYPERV_TIME:
100943c5 3120 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3121 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3122 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3123 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3124 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3125 case KVM_CAP_IMMEDIATE_EXIT:
66bb8a06 3126 case KVM_CAP_PMU_EVENT_FILTER:
801e459a 3127 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3128 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3129 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3130 r = 1;
3131 break;
01643c51
KH		 3132 case KVM_CAP_SYNC_REGS:
3133 r = KVM_SYNC_X86_VALID_FIELDS;
3134 break;
e3fd9a93
PB		 3135 case KVM_CAP_ADJUST_CLOCK:
3136 r = KVM_CLOCK_TSC_STABLE;
3137 break;
4d5422ce 3138 case KVM_CAP_X86_DISABLE_EXITS:
b5170063
WL		 3139 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3140 KVM_X86_DISABLE_EXITS_CSTATE;
4d5422ce
WL		 3141 if(kvm_can_mwait_in_guest())
3142 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3143 break;
6d396b55
PB		 3144 case KVM_CAP_X86_SMM:
3145 /* SMBASE is usually relocated above 1M on modern chipsets,
3146 * and SMM handlers might indeed rely on 4G segment limits,
3147 * so do not report SMM to be available if real mode is
3148 * emulated via vm86 mode. Still, do not go to great lengths
3149 * to avoid userspace's usage of the feature, because it is a
3150 * fringe case that is not enabled except via specific settings
3151 * of the module parameters.
3152 */
bc226f07 3153 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3154 break;
774ead3a
AK		 3155 case KVM_CAP_VAPIC:
3156 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3157 break;
f725230a 3158 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3159 r = KVM_SOFT_MAX_VCPUS;
3160 break;
3161 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3162 r = KVM_MAX_VCPUS;
3163 break;
a86cb413
TH		 3164 case KVM_CAP_MAX_VCPU_ID:
3165 r = KVM_MAX_VCPU_ID;
3166 break;
a68a6a72
MT		 3167 case KVM_CAP_PV_MMU: /* obsolete */
3168 r = 0;
2f333bcb 3169 break;
890ca9ae
HY		 3170 case KVM_CAP_MCE:
3171 r = KVM_MAX_MCE_BANKS;
3172 break;
2d5b5a66 3173 case KVM_CAP_XCRS:
d366bf7e 3174 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3175 break;
92a1f12d
JR		 3176 case KVM_CAP_TSC_CONTROL:
3177 r = kvm_has_tsc_control;
3178 break;
37131313
RK		 3179 case KVM_CAP_X2APIC_API:
3180 r = KVM_X2APIC_API_VALID_FLAGS;
3181 break;
8fcc4b59
JM		 3182 case KVM_CAP_NESTED_STATE:
3183 r = kvm_x86_ops->get_nested_state ?
be43c440 3184 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3185 break;
018d00d2 3186 default:
018d00d2
ZX		 3187 break;
3188 }
3189 return r;
3190
3191}
3192
043405e1
CO		 3193long kvm_arch_dev_ioctl(struct file *filp,
3194 unsigned int ioctl, unsigned long arg)
3195{
3196 void __user *argp = (void __user *)arg;
3197 long r;
3198
3199 switch (ioctl) {
3200 case KVM_GET_MSR_INDEX_LIST: {
3201 struct kvm_msr_list __user *user_msr_list = argp;
3202 struct kvm_msr_list msr_list;
3203 unsigned n;
3204
3205 r = -EFAULT;
0e96f31e 3206 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3207 goto out;
3208 n = msr_list.nmsrs;
62ef68bb 3209 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3210 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3211 goto out;
3212 r = -E2BIG;
e125e7b6 3213 if (n < msr_list.nmsrs)
043405e1
CO		 3214 goto out;
3215 r = -EFAULT;
3216 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3217 num_msrs_to_save * sizeof(u32)))
3218 goto out;
e125e7b6 3219 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3220 &emulated_msrs,
62ef68bb 3221 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3222 goto out;
3223 r = 0;
3224 break;
3225 }
9c15bb1d
BP		 3226 case KVM_GET_SUPPORTED_CPUID:
3227 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3228 struct kvm_cpuid2 __user *cpuid_arg = argp;
3229 struct kvm_cpuid2 cpuid;
3230
3231 r = -EFAULT;
0e96f31e 3232 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3233 goto out;
9c15bb1d
BP		 3234
3235 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3236 ioctl);
674eea0f
AK		 3237 if (r)
3238 goto out;
3239
3240 r = -EFAULT;
0e96f31e 3241 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3242 goto out;
3243 r = 0;
3244 break;
3245 }
890ca9ae 3246 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3247 r = -EFAULT;
c45dcc71
AR		 3248 if (copy_to_user(argp, &kvm_mce_cap_supported,
3249 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3250 goto out;
3251 r = 0;
3252 break;
801e459a
TL		 3253 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3254 struct kvm_msr_list __user *user_msr_list = argp;
3255 struct kvm_msr_list msr_list;
3256 unsigned int n;
3257
3258 r = -EFAULT;
3259 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3260 goto out;
3261 n = msr_list.nmsrs;
3262 msr_list.nmsrs = num_msr_based_features;
3263 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3264 goto out;
3265 r = -E2BIG;
3266 if (n < msr_list.nmsrs)
3267 goto out;
3268 r = -EFAULT;
3269 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3270 num_msr_based_features * sizeof(u32)))
3271 goto out;
3272 r = 0;
3273 break;
3274 }
3275 case KVM_GET_MSRS:
3276 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3277 break;
890ca9ae 3278 }
043405e1
CO		 3279 default:
3280 r = -EINVAL;
3281 }
3282out:
3283 return r;
3284}
3285
f5f48ee1
SY		 3286static void wbinvd_ipi(void *garbage)
3287{
3288 wbinvd();
3289}
3290
3291static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3292{
e0f0bbc5 3293 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3294}
3295
313a3dc7
CO		 3296void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3297{
f5f48ee1
SY		 3298 /* Address WBINVD may be executed by guest */
3299 if (need_emulate_wbinvd(vcpu)) {
3300 if (kvm_x86_ops->has_wbinvd_exit())
3301 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3302 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3303 smp_call_function_single(vcpu->cpu,
3304 wbinvd_ipi, NULL, 1);
3305 }
3306
313a3dc7 3307 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3308
e7517324
WL		 3309 fpregs_assert_state_consistent();
3310 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3311 switch_fpu_return();
3312
0dd6a6ed
ZA		 3313 /* Apply any externally detected TSC adjustments (due to suspend) */
3314 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3315 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3316 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3317 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3318 }
8f6055cb 3319
b0c39dc6 3320 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3321 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3322 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3323 if (tsc_delta < 0)
3324 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3325
b0c39dc6 3326 if (kvm_check_tsc_unstable()) {
07c1419a 3327 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3328 vcpu->arch.last_guest_tsc);
a545ab6a 3329 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3330 vcpu->arch.tsc_catchup = 1;
c285545f 3331 }
a749e247
PB		 3332
3333 if (kvm_lapic_hv_timer_in_use(vcpu))
3334 kvm_lapic_restart_hv_timer(vcpu);
3335
d98d07ca
MT		 3336 /*
3337 * On a host with synchronized TSC, there is no need to update
3338 * kvmclock on vcpu->cpu migration
3339 */
3340 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3341 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3342 if (vcpu->cpu != cpu)
1bd2009e 3343 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3344 vcpu->cpu = cpu;
6b7d7e76 3345 }
c9aaa895 3346
c9aaa895 3347 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3348}
3349
0b9f6c46
PX		 3350static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3351{
3352 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3353 return;
3354
fa55eedd 3355 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3356
4e335d9e 3357 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3358 &vcpu->arch.st.steal.preempted,
3359 offsetof(struct kvm_steal_time, preempted),
3360 sizeof(vcpu->arch.st.steal.preempted));
3361}
3362
313a3dc7
CO		 3363void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3364{
cc0d907c 3365 int idx;
de63ad4c
LM		 3366
3367 if (vcpu->preempted)
3368 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3369
931f261b
AA		 3370 /*
3371 * Disable page faults because we're in atomic context here.
3372 * kvm_write_guest_offset_cached() would call might_fault()
3373 * that relies on pagefault_disable() to tell if there's a
3374 * bug. NOTE: the write to guest memory may not go through if
3375 * during postcopy live migration or if there's heavy guest
3376 * paging.
3377 */
3378 pagefault_disable();
cc0d907c
AA		 3379 /*
3380 * kvm_memslots() will be called by
3381 * kvm_write_guest_offset_cached() so take the srcu lock.
3382 */
3383 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3384 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3385 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3386 pagefault_enable();
02daab21 3387 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3388 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3389 /*
f9dcf08e
RK		 3390 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3391 * on every vmexit, but if not, we might have a stale dr6 from the
3392 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3393 */
f9dcf08e 3394 set_debugreg(0, 6);
313a3dc7
CO		 3395}
3396
313a3dc7
CO		 3397static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3398 struct kvm_lapic_state *s)
3399{
fa59cc00 3400 if (vcpu->arch.apicv_active)
d62caabb
AS		 3401 kvm_x86_ops->sync_pir_to_irr(vcpu);
3402
a92e2543 3403 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3404}
3405
3406static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3407 struct kvm_lapic_state *s)
3408{
a92e2543
RK		 3409 int r;
3410
3411 r = kvm_apic_set_state(vcpu, s);
3412 if (r)
3413 return r;
cb142eb7 3414 update_cr8_intercept(vcpu);
313a3dc7
CO		 3415
3416 return 0;
3417}
3418
127a457a
MG		 3419static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3420{
3421 return (!lapic_in_kernel(vcpu) ||
3422 kvm_apic_accept_pic_intr(vcpu));
3423}
3424
782d422b
MG		 3425/*
3426 * if userspace requested an interrupt window, check that the
3427 * interrupt window is open.
3428 *
3429 * No need to exit to userspace if we already have an interrupt queued.
3430 */
3431static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3432{
3433 return kvm_arch_interrupt_allowed(vcpu) &&
3434 !kvm_cpu_has_interrupt(vcpu) &&
3435 !kvm_event_needs_reinjection(vcpu) &&
3436 kvm_cpu_accept_dm_intr(vcpu);
3437}
3438
f77bc6a4
ZX		 3439static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3440 struct kvm_interrupt *irq)
3441{
02cdb50f 3442 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3443 return -EINVAL;
1c1a9ce9
SR		 3444
3445 if (!irqchip_in_kernel(vcpu->kvm)) {
3446 kvm_queue_interrupt(vcpu, irq->irq, false);
3447 kvm_make_request(KVM_REQ_EVENT, vcpu);
3448 return 0;
3449 }
3450
3451 /*
3452 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3453 * fail for in-kernel 8259.
3454 */
3455 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3456 return -ENXIO;
f77bc6a4 3457
1c1a9ce9
SR		 3458 if (vcpu->arch.pending_external_vector != -1)
3459 return -EEXIST;
f77bc6a4 3460
1c1a9ce9 3461 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3462 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3463 return 0;
3464}
3465
c4abb7c9
JK		 3466static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3467{
c4abb7c9 3468 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3469
3470 return 0;
3471}
3472
f077825a
PB		 3473static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3474{
64d60670
PB		 3475 kvm_make_request(KVM_REQ_SMI, vcpu);
3476
f077825a
PB		 3477 return 0;
3478}
3479
b209749f
AK		 3480static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3481 struct kvm_tpr_access_ctl *tac)
3482{
3483 if (tac->flags)
3484 return -EINVAL;
3485 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3486 return 0;
3487}
3488
890ca9ae
HY		 3489static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3490 u64 mcg_cap)
3491{
3492 int r;
3493 unsigned bank_num = mcg_cap & 0xff, bank;
3494
3495 r = -EINVAL;
a9e38c3e 3496 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3497 goto out;
c45dcc71 3498 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3499 goto out;
3500 r = 0;
3501 vcpu->arch.mcg_cap = mcg_cap;
3502 /* Init IA32_MCG_CTL to all 1s */
3503 if (mcg_cap & MCG_CTL_P)
3504 vcpu->arch.mcg_ctl = ~(u64)0;
3505 /* Init IA32_MCi_CTL to all 1s */
3506 for (bank = 0; bank < bank_num; bank++)
3507 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3508
3509 if (kvm_x86_ops->setup_mce)
3510 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3511out:
3512 return r;
3513}
3514
3515static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3516 struct kvm_x86_mce *mce)
3517{
3518 u64 mcg_cap = vcpu->arch.mcg_cap;
3519 unsigned bank_num = mcg_cap & 0xff;
3520 u64 *banks = vcpu->arch.mce_banks;
3521
3522 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3523 return -EINVAL;
3524 /*
3525 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3526 * reporting is disabled
3527 */
3528 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3529 vcpu->arch.mcg_ctl != ~(u64)0)
3530 return 0;
3531 banks += 4 * mce->bank;
3532 /*
3533 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3534 * reporting is disabled for the bank
3535 */
3536 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3537 return 0;
3538 if (mce->status & MCI_STATUS_UC) {
3539 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3540 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3541 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3542 return 0;
3543 }
3544 if (banks[1] & MCI_STATUS_VAL)
3545 mce->status |= MCI_STATUS_OVER;
3546 banks[2] = mce->addr;
3547 banks[3] = mce->misc;
3548 vcpu->arch.mcg_status = mce->mcg_status;
3549 banks[1] = mce->status;
3550 kvm_queue_exception(vcpu, MC_VECTOR);
3551 } else if (!(banks[1] & MCI_STATUS_VAL)
3552 || !(banks[1] & MCI_STATUS_UC)) {
3553 if (banks[1] & MCI_STATUS_VAL)
3554 mce->status |= MCI_STATUS_OVER;
3555 banks[2] = mce->addr;
3556 banks[3] = mce->misc;
3557 banks[1] = mce->status;
3558 } else
3559 banks[1] |= MCI_STATUS_OVER;
3560 return 0;
3561}
3562
3cfc3092
JK		 3563static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3564 struct kvm_vcpu_events *events)
3565{
7460fb4a 3566 process_nmi(vcpu);
59073aaf 3567
664f8e26 3568 /*
59073aaf
JM		 3569 * The API doesn't provide the instruction length for software
3570 * exceptions, so don't report them. As long as the guest RIP
3571 * isn't advanced, we should expect to encounter the exception
3572 * again.
664f8e26 3573 */
59073aaf
JM		 3574 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3575 events->exception.injected = 0;
3576 events->exception.pending = 0;
3577 } else {
3578 events->exception.injected = vcpu->arch.exception.injected;
3579 events->exception.pending = vcpu->arch.exception.pending;
3580 /*
3581 * For ABI compatibility, deliberately conflate
3582 * pending and injected exceptions when
3583 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3584 */
3585 if (!vcpu->kvm->arch.exception_payload_enabled)
3586 events->exception.injected |=
3587 vcpu->arch.exception.pending;
3588 }
3cfc3092
JK		 3589 events->exception.nr = vcpu->arch.exception.nr;
3590 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3591 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3592 events->exception_has_payload = vcpu->arch.exception.has_payload;
3593 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3594
03b82a30 3595 events->interrupt.injected =
04140b41 3596 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3597 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3598 events->interrupt.soft = 0;
37ccdcbe 3599 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3600
3601 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3602 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3603 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3604 events->nmi.pad = 0;
3cfc3092 3605
66450a21 3606 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3607
f077825a
PB		 3608 events->smi.smm = is_smm(vcpu);
3609 events->smi.pending = vcpu->arch.smi_pending;
3610 events->smi.smm_inside_nmi =
3611 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3612 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3613
dab4b911 3614 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3615 | KVM_VCPUEVENT_VALID_SHADOW
3616 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3617 if (vcpu->kvm->arch.exception_payload_enabled)
3618 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3619
97e69aa6 3620 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3621}
3622
c5833c7a 3623static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3624
3cfc3092
JK		 3625static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3626 struct kvm_vcpu_events *events)
3627{
dab4b911 3628 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3629 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3630 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3631 | KVM_VCPUEVENT_VALID_SMM
3632 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3633 return -EINVAL;
3634
59073aaf
JM		 3635 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3636 if (!vcpu->kvm->arch.exception_payload_enabled)
3637 return -EINVAL;
3638 if (events->exception.pending)
3639 events->exception.injected = 0;
3640 else
3641 events->exception_has_payload = 0;
3642 } else {
3643 events->exception.pending = 0;
3644 events->exception_has_payload = 0;
3645 }
3646
3647 if ((events->exception.injected || events->exception.pending) &&
3648 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3649 return -EINVAL;
3650
28bf2888
DH		 3651 /* INITs are latched while in SMM */
3652 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3653 (events->smi.smm || events->smi.pending) &&
3654 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3655 return -EINVAL;
3656
7460fb4a 3657 process_nmi(vcpu);
59073aaf
JM		 3658 vcpu->arch.exception.injected = events->exception.injected;
3659 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3660 vcpu->arch.exception.nr = events->exception.nr;
3661 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3662 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3663 vcpu->arch.exception.has_payload = events->exception_has_payload;
3664 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3665
04140b41 3666 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3667 vcpu->arch.interrupt.nr = events->interrupt.nr;
3668 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3669 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3670 kvm_x86_ops->set_interrupt_shadow(vcpu,
3671 events->interrupt.shadow);
3cfc3092
JK		 3672
3673 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3674 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3675 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3676 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3677
66450a21 3678 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3679 lapic_in_kernel(vcpu))
66450a21 3680 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3681
f077825a 3682 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3683 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3684 if (events->smi.smm)
3685 vcpu->arch.hflags |= HF_SMM_MASK;
3686 else
3687 vcpu->arch.hflags &= ~HF_SMM_MASK;
3688 kvm_smm_changed(vcpu);
3689 }
6ef4e07e 3690
f077825a 3691 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3692
3693 if (events->smi.smm) {
3694 if (events->smi.smm_inside_nmi)
3695 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3696 else
f4ef1910
WL		 3697 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3698 if (lapic_in_kernel(vcpu)) {
3699 if (events->smi.latched_init)
3700 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3701 else
3702 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3703 }
f077825a
PB		 3704 }
3705 }
3706
3842d135
AK		 3707 kvm_make_request(KVM_REQ_EVENT, vcpu);
3708
3cfc3092
JK		 3709 return 0;
3710}
3711
a1efbe77
JK		 3712static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3713 struct kvm_debugregs *dbgregs)
3714{
73aaf249
JK		 3715 unsigned long val;
3716
a1efbe77 3717 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3718 kvm_get_dr(vcpu, 6, &val);
73aaf249 3719 dbgregs->dr6 = val;
a1efbe77
JK		 3720 dbgregs->dr7 = vcpu->arch.dr7;
3721 dbgregs->flags = 0;
97e69aa6 3722 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3723}
3724
3725static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3726 struct kvm_debugregs *dbgregs)
3727{
3728 if (dbgregs->flags)
3729 return -EINVAL;
3730
d14bdb55
PB		 3731 if (dbgregs->dr6 & ~0xffffffffull)
3732 return -EINVAL;
3733 if (dbgregs->dr7 & ~0xffffffffull)
3734 return -EINVAL;
3735
a1efbe77 3736 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3737 kvm_update_dr0123(vcpu);
a1efbe77 3738 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3739 kvm_update_dr6(vcpu);
a1efbe77 3740 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3741 kvm_update_dr7(vcpu);
a1efbe77 3742
a1efbe77
JK		 3743 return 0;
3744}
3745
df1daba7
PB		 3746#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3747
3748static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3749{
b666a4b6 3750 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3751 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3752 u64 valid;
3753
3754 /*
3755 * Copy legacy XSAVE area, to avoid complications with CPUID
3756 * leaves 0 and 1 in the loop below.
3757 */
3758 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3759
3760 /* Set XSTATE_BV */
00c87e9a 3761 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3762 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3763
3764 /*
3765 * Copy each region from the possibly compacted offset to the
3766 * non-compacted offset.
3767 */
d91cab78 3768 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3769 while (valid) {
abd16d68
SAS		 3770 u64 xfeature_mask = valid & -valid;
3771 int xfeature_nr = fls64(xfeature_mask) - 1;
3772 void *src = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3773
3774 if (src) {
3775 u32 size, offset, ecx, edx;
abd16d68 3776 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3777 &size, &offset, &ecx, &edx);
abd16d68 3778 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3779 memcpy(dest + offset, &vcpu->arch.pkru,
3780 sizeof(vcpu->arch.pkru));
3781 else
3782 memcpy(dest + offset, src, size);
3783
df1daba7
PB		 3784 }
3785
abd16d68 3786 valid -= xfeature_mask;
df1daba7
PB		 3787 }
3788}
3789
3790static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3791{
b666a4b6 3792 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3793 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3794 u64 valid;
3795
3796 /*
3797 * Copy legacy XSAVE area, to avoid complications with CPUID
3798 * leaves 0 and 1 in the loop below.
3799 */
3800 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3801
3802 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3803 xsave->header.xfeatures = xstate_bv;
782511b0 3804 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3805 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3806
3807 /*
3808 * Copy each region from the non-compacted offset to the
3809 * possibly compacted offset.
3810 */
d91cab78 3811 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3812 while (valid) {
abd16d68
SAS		 3813 u64 xfeature_mask = valid & -valid;
3814 int xfeature_nr = fls64(xfeature_mask) - 1;
3815 void *dest = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3816
3817 if (dest) {
3818 u32 size, offset, ecx, edx;
abd16d68 3819 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3820 &size, &offset, &ecx, &edx);
abd16d68 3821 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3822 memcpy(&vcpu->arch.pkru, src + offset,
3823 sizeof(vcpu->arch.pkru));
3824 else
3825 memcpy(dest, src + offset, size);
ee4100da 3826 }
df1daba7 3827
abd16d68 3828 valid -= xfeature_mask;
df1daba7
PB		 3829 }
3830}
3831
2d5b5a66
SY		 3832static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3833 struct kvm_xsave *guest_xsave)
3834{
d366bf7e 3835 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3836 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3837 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3838 } else {
2d5b5a66 3839 memcpy(guest_xsave->region,
b666a4b6 3840 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3841 sizeof(struct fxregs_state));
2d5b5a66 3842 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3843 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3844 }
3845}
3846
a575813b
WL		 3847#define XSAVE_MXCSR_OFFSET 24
3848
2d5b5a66
SY		 3849static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3850 struct kvm_xsave *guest_xsave)
3851{
3852 u64 xstate_bv =
3853 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3854 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3855
d366bf7e 3856 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3857 /*
3858 * Here we allow setting states that are not present in
3859 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3860 * with old userspace.
3861 */
a575813b
WL		 3862 if (xstate_bv & ~kvm_supported_xcr0() ||
3863 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3864 return -EINVAL;
df1daba7 3865 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3866 } else {
a575813b
WL		 3867 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3868 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3869 return -EINVAL;
b666a4b6 3870 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3871 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3872 }
3873 return 0;
3874}
3875
3876static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3877 struct kvm_xcrs *guest_xcrs)
3878{
d366bf7e 3879 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3880 guest_xcrs->nr_xcrs = 0;
3881 return;
3882 }
3883
3884 guest_xcrs->nr_xcrs = 1;
3885 guest_xcrs->flags = 0;
3886 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3887 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3888}
3889
3890static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3891 struct kvm_xcrs *guest_xcrs)
3892{
3893 int i, r = 0;
3894
d366bf7e 3895 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3896 return -EINVAL;
3897
3898 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3899 return -EINVAL;
3900
3901 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3902 /* Only support XCR0 currently */
c67a04cb 3903 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3904 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3905 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3906 break;
3907 }
3908 if (r)
3909 r = -EINVAL;
3910 return r;
3911}
3912
1c0b28c2
EM		 3913/*
3914 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3915 * stopped by the hypervisor. This function will be called from the host only.
3916 * EINVAL is returned when the host attempts to set the flag for a guest that
3917 * does not support pv clocks.
3918 */
3919static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3920{
0b79459b 3921 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3922 return -EINVAL;
51d59c6b 3923 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3924 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3925 return 0;
3926}
3927
5c919412
AS		 3928static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3929 struct kvm_enable_cap *cap)
3930{
57b119da
VK		 3931 int r;
3932 uint16_t vmcs_version;
3933 void __user *user_ptr;
3934
5c919412
AS		 3935 if (cap->flags)
3936 return -EINVAL;
3937
3938 switch (cap->cap) {
efc479e6
RK		 3939 case KVM_CAP_HYPERV_SYNIC2:
3940 if (cap->args[0])
3941 return -EINVAL;
b2869f28
GS		 3942 /* fall through */
3943
5c919412 3944 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3945 if (!irqchip_in_kernel(vcpu->kvm))
3946 return -EINVAL;
efc479e6
RK		 3947 return kvm_hv_activate_synic(vcpu, cap->cap ==
3948 KVM_CAP_HYPERV_SYNIC2);
57b119da 3949 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 3950 if (!kvm_x86_ops->nested_enable_evmcs)
3951 return -ENOTTY;
57b119da
VK		 3952 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3953 if (!r) {
3954 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3955 if (copy_to_user(user_ptr, &vmcs_version,
3956 sizeof(vmcs_version)))
3957 r = -EFAULT;
3958 }
3959 return r;
3960
5c919412
AS		 3961 default:
3962 return -EINVAL;
3963 }
3964}
3965
313a3dc7
CO		 3966long kvm_arch_vcpu_ioctl(struct file *filp,
3967 unsigned int ioctl, unsigned long arg)
3968{
3969 struct kvm_vcpu *vcpu = filp->private_data;
3970 void __user *argp = (void __user *)arg;
3971 int r;
d1ac91d8
AK		 3972 union {
3973 struct kvm_lapic_state *lapic;
3974 struct kvm_xsave *xsave;
3975 struct kvm_xcrs *xcrs;
3976 void *buffer;
3977 } u;
3978
9b062471
CD		 3979 vcpu_load(vcpu);
3980
d1ac91d8 3981 u.buffer = NULL;
313a3dc7
CO		 3982 switch (ioctl) {
3983 case KVM_GET_LAPIC: {
2204ae3c 3984 r = -EINVAL;
bce87cce 3985 if (!lapic_in_kernel(vcpu))
2204ae3c 3986 goto out;
254272ce
BG		 3987 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3988 GFP_KERNEL_ACCOUNT);
313a3dc7 3989
b772ff36 3990 r = -ENOMEM;
d1ac91d8 3991 if (!u.lapic)
b772ff36 3992 goto out;
d1ac91d8 3993 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3994 if (r)
3995 goto out;
3996 r = -EFAULT;
d1ac91d8 3997 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3998 goto out;
3999 r = 0;
4000 break;
4001 }
4002 case KVM_SET_LAPIC: {
2204ae3c 4003 r = -EINVAL;
bce87cce 4004 if (!lapic_in_kernel(vcpu))
2204ae3c 4005 goto out;
ff5c2c03 4006 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 4007 if (IS_ERR(u.lapic)) {
4008 r = PTR_ERR(u.lapic);
4009 goto out_nofree;
4010 }
ff5c2c03 4011
d1ac91d8 4012 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 4013 break;
4014 }
f77bc6a4
ZX		 4015 case KVM_INTERRUPT: {
4016 struct kvm_interrupt irq;
4017
4018 r = -EFAULT;
0e96f31e 4019 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 4020 goto out;
4021 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 4022 break;
4023 }
c4abb7c9
JK		 4024 case KVM_NMI: {
4025 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 4026 break;
4027 }
f077825a
PB		 4028 case KVM_SMI: {
4029 r = kvm_vcpu_ioctl_smi(vcpu);
4030 break;
4031 }
313a3dc7
CO		 4032 case KVM_SET_CPUID: {
4033 struct kvm_cpuid __user *cpuid_arg = argp;
4034 struct kvm_cpuid cpuid;
4035
4036 r = -EFAULT;
0e96f31e 4037 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 4038 goto out;
4039 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 4040 break;
4041 }
07716717
DK		 4042 case KVM_SET_CPUID2: {
4043 struct kvm_cpuid2 __user *cpuid_arg = argp;
4044 struct kvm_cpuid2 cpuid;
4045
4046 r = -EFAULT;
0e96f31e 4047 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4048 goto out;
4049 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 4050 cpuid_arg->entries);
07716717
DK		 4051 break;
4052 }
4053 case KVM_GET_CPUID2: {
4054 struct kvm_cpuid2 __user *cpuid_arg = argp;
4055 struct kvm_cpuid2 cpuid;
4056
4057 r = -EFAULT;
0e96f31e 4058 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4059 goto out;
4060 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 4061 cpuid_arg->entries);
07716717
DK		 4062 if (r)
4063 goto out;
4064 r = -EFAULT;
0e96f31e 4065 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 4066 goto out;
4067 r = 0;
4068 break;
4069 }
801e459a
TL		 4070 case KVM_GET_MSRS: {
4071 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 4072 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 4073 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4074 break;
801e459a
TL		 4075 }
4076 case KVM_SET_MSRS: {
4077 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 4078 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 4079 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4080 break;
801e459a 4081 }
b209749f
AK		 4082 case KVM_TPR_ACCESS_REPORTING: {
4083 struct kvm_tpr_access_ctl tac;
4084
4085 r = -EFAULT;
0e96f31e 4086 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 4087 goto out;
4088 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4089 if (r)
4090 goto out;
4091 r = -EFAULT;
0e96f31e 4092 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4093 goto out;
4094 r = 0;
4095 break;
4096 };
b93463aa
AK		 4097 case KVM_SET_VAPIC_ADDR: {
4098 struct kvm_vapic_addr va;
7301d6ab 4099 int idx;
b93463aa
AK		 4100
4101 r = -EINVAL;
35754c98 4102 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4103 goto out;
4104 r = -EFAULT;
0e96f31e 4105 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4106 goto out;
7301d6ab 4107 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4108 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4109 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4110 break;
4111 }
890ca9ae
HY		 4112 case KVM_X86_SETUP_MCE: {
4113 u64 mcg_cap;
4114
4115 r = -EFAULT;
0e96f31e 4116 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4117 goto out;
4118 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4119 break;
4120 }
4121 case KVM_X86_SET_MCE: {
4122 struct kvm_x86_mce mce;
4123
4124 r = -EFAULT;
0e96f31e 4125 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4126 goto out;
4127 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4128 break;
4129 }
3cfc3092
JK		 4130 case KVM_GET_VCPU_EVENTS: {
4131 struct kvm_vcpu_events events;
4132
4133 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4134
4135 r = -EFAULT;
4136 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4137 break;
4138 r = 0;
4139 break;
4140 }
4141 case KVM_SET_VCPU_EVENTS: {
4142 struct kvm_vcpu_events events;
4143
4144 r = -EFAULT;
4145 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4146 break;
4147
4148 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4149 break;
4150 }
a1efbe77
JK		 4151 case KVM_GET_DEBUGREGS: {
4152 struct kvm_debugregs dbgregs;
4153
4154 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4155
4156 r = -EFAULT;
4157 if (copy_to_user(argp, &dbgregs,
4158 sizeof(struct kvm_debugregs)))
4159 break;
4160 r = 0;
4161 break;
4162 }
4163 case KVM_SET_DEBUGREGS: {
4164 struct kvm_debugregs dbgregs;
4165
4166 r = -EFAULT;
4167 if (copy_from_user(&dbgregs, argp,
4168 sizeof(struct kvm_debugregs)))
4169 break;
4170
4171 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4172 break;
4173 }
2d5b5a66 4174 case KVM_GET_XSAVE: {
254272ce 4175 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4176 r = -ENOMEM;
d1ac91d8 4177 if (!u.xsave)
2d5b5a66
SY		 4178 break;
4179
d1ac91d8 4180 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4181
4182 r = -EFAULT;
d1ac91d8 4183 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4184 break;
4185 r = 0;
4186 break;
4187 }
4188 case KVM_SET_XSAVE: {
ff5c2c03 4189 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4190 if (IS_ERR(u.xsave)) {
4191 r = PTR_ERR(u.xsave);
4192 goto out_nofree;
4193 }
2d5b5a66 4194
d1ac91d8 4195 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4196 break;
4197 }
4198 case KVM_GET_XCRS: {
254272ce 4199 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4200 r = -ENOMEM;
d1ac91d8 4201 if (!u.xcrs)
2d5b5a66
SY		 4202 break;
4203
d1ac91d8 4204 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4205
4206 r = -EFAULT;
d1ac91d8 4207 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4208 sizeof(struct kvm_xcrs)))
4209 break;
4210 r = 0;
4211 break;
4212 }
4213 case KVM_SET_XCRS: {
ff5c2c03 4214 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4215 if (IS_ERR(u.xcrs)) {
4216 r = PTR_ERR(u.xcrs);
4217 goto out_nofree;
4218 }
2d5b5a66 4219
d1ac91d8 4220 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4221 break;
4222 }
92a1f12d
JR		 4223 case KVM_SET_TSC_KHZ: {
4224 u32 user_tsc_khz;
4225
4226 r = -EINVAL;
92a1f12d
JR		 4227 user_tsc_khz = (u32)arg;
4228
4229 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4230 goto out;
4231
cc578287
ZA		 4232 if (user_tsc_khz == 0)
4233 user_tsc_khz = tsc_khz;
4234
381d585c
HZ		 4235 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4236 r = 0;
92a1f12d 4237
92a1f12d
JR		 4238 goto out;
4239 }
4240 case KVM_GET_TSC_KHZ: {
cc578287 4241 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4242 goto out;
4243 }
1c0b28c2
EM		 4244 case KVM_KVMCLOCK_CTRL: {
4245 r = kvm_set_guest_paused(vcpu);
4246 goto out;
4247 }
5c919412
AS		 4248 case KVM_ENABLE_CAP: {
4249 struct kvm_enable_cap cap;
4250
4251 r = -EFAULT;
4252 if (copy_from_user(&cap, argp, sizeof(cap)))
4253 goto out;
4254 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4255 break;
4256 }
8fcc4b59
JM		 4257 case KVM_GET_NESTED_STATE: {
4258 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4259 u32 user_data_size;
4260
4261 r = -EINVAL;
4262 if (!kvm_x86_ops->get_nested_state)
4263 break;
4264
4265 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4266 r = -EFAULT;
8fcc4b59 4267 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4268 break;
8fcc4b59
JM		 4269
4270 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4271 user_data_size);
4272 if (r < 0)
26b471c7 4273 break;
8fcc4b59
JM		 4274
4275 if (r > user_data_size) {
4276 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4277 r = -EFAULT;
4278 else
4279 r = -E2BIG;
4280 break;
8fcc4b59 4281 }
26b471c7 4282
8fcc4b59
JM		 4283 r = 0;
4284 break;
4285 }
4286 case KVM_SET_NESTED_STATE: {
4287 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4288 struct kvm_nested_state kvm_state;
4289
4290 r = -EINVAL;
4291 if (!kvm_x86_ops->set_nested_state)
4292 break;
4293
26b471c7 4294 r = -EFAULT;
8fcc4b59 4295 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4296 break;
8fcc4b59 4297
26b471c7 4298 r = -EINVAL;
8fcc4b59 4299 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4300 break;
8fcc4b59
JM		 4301
4302 if (kvm_state.flags &
8cab6507
VK		 4303 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4304 | KVM_STATE_NESTED_EVMCS))
26b471c7 4305 break;
8fcc4b59
JM		 4306
4307 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4308 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4309 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4310 break;
8fcc4b59
JM		 4311
4312 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4313 break;
4314 }
2bc39970
VK		 4315 case KVM_GET_SUPPORTED_HV_CPUID: {
4316 struct kvm_cpuid2 __user *cpuid_arg = argp;
4317 struct kvm_cpuid2 cpuid;
4318
4319 r = -EFAULT;
4320 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4321 goto out;
4322
4323 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4324 cpuid_arg->entries);
4325 if (r)
4326 goto out;
4327
4328 r = -EFAULT;
4329 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4330 goto out;
4331 r = 0;
4332 break;
4333 }
313a3dc7
CO		 4334 default:
4335 r = -EINVAL;
4336 }
4337out:
d1ac91d8 4338 kfree(u.buffer);
9b062471
CD		 4339out_nofree:
4340 vcpu_put(vcpu);
313a3dc7
CO		 4341 return r;
4342}
4343
1499fa80 4344vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4345{
4346 return VM_FAULT_SIGBUS;
4347}
4348
1fe779f8
CO		 4349static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4350{
4351 int ret;
4352
4353 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4354 return -EINVAL;
1fe779f8
CO		 4355 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4356 return ret;
4357}
4358
b927a3ce
SY		 4359static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4360 u64 ident_addr)
4361{
2ac52ab8 4362 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4363}
4364
1fe779f8 4365static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4366 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4367{
4368 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4369 return -EINVAL;
4370
79fac95e 4371 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4372
4373 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4374 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4375
79fac95e 4376 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4377 return 0;
4378}
4379
bc8a3d89 4380static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4381{
39de71ec 4382 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4383}
4384
1fe779f8
CO		 4385static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4386{
90bca052 4387 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4388 int r;
4389
4390 r = 0;
4391 switch (chip->chip_id) {
4392 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4393 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4394 sizeof(struct kvm_pic_state));
4395 break;
4396 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4397 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4398 sizeof(struct kvm_pic_state));
4399 break;
4400 case KVM_IRQCHIP_IOAPIC:
33392b49 4401 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4402 break;
4403 default:
4404 r = -EINVAL;
4405 break;
4406 }
4407 return r;
4408}
4409
4410static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4411{
90bca052 4412 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4413 int r;
4414
4415 r = 0;
4416 switch (chip->chip_id) {
4417 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4418 spin_lock(&pic->lock);
4419 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4420 sizeof(struct kvm_pic_state));
90bca052 4421 spin_unlock(&pic->lock);
1fe779f8
CO		 4422 break;
4423 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4424 spin_lock(&pic->lock);
4425 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4426 sizeof(struct kvm_pic_state));
90bca052 4427 spin_unlock(&pic->lock);
1fe779f8
CO		 4428 break;
4429 case KVM_IRQCHIP_IOAPIC:
33392b49 4430 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4431 break;
4432 default:
4433 r = -EINVAL;
4434 break;
4435 }
90bca052 4436 kvm_pic_update_irq(pic);
1fe779f8
CO		 4437 return r;
4438}
4439
e0f63cb9
SY		 4440static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4441{
34f3941c
RK		 4442 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4443
4444 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4445
4446 mutex_lock(&kps->lock);
4447 memcpy(ps, &kps->channels, sizeof(*ps));
4448 mutex_unlock(&kps->lock);
2da29bcc 4449 return 0;
e0f63cb9
SY		 4450}
4451
4452static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4453{
0185604c 4454 int i;
09edea72
RK		 4455 struct kvm_pit *pit = kvm->arch.vpit;
4456
4457 mutex_lock(&pit->pit_state.lock);
34f3941c 4458 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4459 for (i = 0; i < 3; i++)
09edea72
RK		 4460 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4461 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4462 return 0;
e9f42757
BK		 4463}
4464
4465static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4466{
e9f42757
BK		 4467 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4468 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4469 sizeof(ps->channels));
4470 ps->flags = kvm->arch.vpit->pit_state.flags;
4471 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4472 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4473 return 0;
e9f42757
BK		 4474}
4475
4476static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4477{
2da29bcc 4478 int start = 0;
0185604c 4479 int i;
e9f42757 4480 u32 prev_legacy, cur_legacy;
09edea72
RK		 4481 struct kvm_pit *pit = kvm->arch.vpit;
4482
4483 mutex_lock(&pit->pit_state.lock);
4484 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4485 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4486 if (!prev_legacy && cur_legacy)
4487 start = 1;
09edea72
RK		 4488 memcpy(&pit->pit_state.channels, &ps->channels,
4489 sizeof(pit->pit_state.channels));
4490 pit->pit_state.flags = ps->flags;
0185604c 4491 for (i = 0; i < 3; i++)
09edea72 4492 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4493 start && i == 0);
09edea72 4494 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4495 return 0;
e0f63cb9
SY		 4496}
4497
52d939a0
MT		 4498static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4499 struct kvm_reinject_control *control)
4500{
71474e2f
RK		 4501 struct kvm_pit *pit = kvm->arch.vpit;
4502
4503 if (!pit)
52d939a0 4504 return -ENXIO;
b39c90b6 4505
71474e2f
RK		 4506 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4507 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4508 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4509 */
4510 mutex_lock(&pit->pit_state.lock);
4511 kvm_pit_set_reinject(pit, control->pit_reinject);
4512 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4513
52d939a0
MT		 4514 return 0;
4515}
4516
95d4c16c 4517/**
60c34612
TY		 4518 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4519 * @kvm: kvm instance
4520 * @log: slot id and address to which we copy the log
95d4c16c 4521 *
e108ff2f
PB		 4522 * Steps 1-4 below provide general overview of dirty page logging. See
4523 * kvm_get_dirty_log_protect() function description for additional details.
4524 *
4525 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4526 * always flush the TLB (step 4) even if previous step failed and the dirty
4527 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4528 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4529 * writes will be marked dirty for next log read.
95d4c16c 4530 *
60c34612
TY		 4531 * 1. Take a snapshot of the bit and clear it if needed.
4532 * 2. Write protect the corresponding page.
e108ff2f
PB		 4533 * 3. Copy the snapshot to the userspace.
4534 * 4. Flush TLB's if needed.
5bb064dc 4535 */
60c34612 4536int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4537{
8fe65a82 4538 bool flush = false;
e108ff2f 4539 int r;
5bb064dc 4540
79fac95e 4541 mutex_lock(&kvm->slots_lock);
5bb064dc 4542
88178fd4
KH		 4543 /*
4544 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4545 */
4546 if (kvm_x86_ops->flush_log_dirty)
4547 kvm_x86_ops->flush_log_dirty(kvm);
4548
8fe65a82 4549 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4550
4551 /*
4552 * All the TLBs can be flushed out of mmu lock, see the comments in
4553 * kvm_mmu_slot_remove_write_access().
4554 */
e108ff2f 4555 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4556 if (flush)
2a31b9db
PB		 4557 kvm_flush_remote_tlbs(kvm);
4558
4559 mutex_unlock(&kvm->slots_lock);
4560 return r;
4561}
4562
4563int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4564{
4565 bool flush = false;
4566 int r;
4567
4568 mutex_lock(&kvm->slots_lock);
4569
4570 /*
4571 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4572 */
4573 if (kvm_x86_ops->flush_log_dirty)
4574 kvm_x86_ops->flush_log_dirty(kvm);
4575
4576 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4577
4578 /*
4579 * All the TLBs can be flushed out of mmu lock, see the comments in
4580 * kvm_mmu_slot_remove_write_access().
4581 */
4582 lockdep_assert_held(&kvm->slots_lock);
4583 if (flush)
198c74f4
XG		 4584 kvm_flush_remote_tlbs(kvm);
4585
79fac95e 4586 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4587 return r;
4588}
4589
aa2fbe6d
YZ		 4590int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4591 bool line_status)
23d43cf9
CD		 4592{
4593 if (!irqchip_in_kernel(kvm))
4594 return -ENXIO;
4595
4596 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4597 irq_event->irq, irq_event->level,
4598 line_status);
23d43cf9
CD		 4599 return 0;
4600}
4601
e5d83c74
PB		 4602int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4603 struct kvm_enable_cap *cap)
90de4a18
NA		 4604{
4605 int r;
4606
4607 if (cap->flags)
4608 return -EINVAL;
4609
4610 switch (cap->cap) {
4611 case KVM_CAP_DISABLE_QUIRKS:
4612 kvm->arch.disabled_quirks = cap->args[0];
4613 r = 0;
4614 break;
49df6397
SR		 4615 case KVM_CAP_SPLIT_IRQCHIP: {
4616 mutex_lock(&kvm->lock);
b053b2ae
SR		 4617 r = -EINVAL;
4618 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4619 goto split_irqchip_unlock;
49df6397
SR		 4620 r = -EEXIST;
4621 if (irqchip_in_kernel(kvm))
4622 goto split_irqchip_unlock;
557abc40 4623 if (kvm->created_vcpus)
49df6397
SR		 4624 goto split_irqchip_unlock;
4625 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4626 if (r)
49df6397
SR		 4627 goto split_irqchip_unlock;
4628 /* Pairs with irqchip_in_kernel. */
4629 smp_wmb();
49776faf 4630 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4631 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4632 r = 0;
4633split_irqchip_unlock:
4634 mutex_unlock(&kvm->lock);
4635 break;
4636 }
37131313
RK		 4637 case KVM_CAP_X2APIC_API:
4638 r = -EINVAL;
4639 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4640 break;
4641
4642 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4643 kvm->arch.x2apic_format = true;
c519265f
RK		 4644 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4645 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4646
4647 r = 0;
4648 break;
4d5422ce
WL		 4649 case KVM_CAP_X86_DISABLE_EXITS:
4650 r = -EINVAL;
4651 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4652 break;
4653
4654 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4655 kvm_can_mwait_in_guest())
4656 kvm->arch.mwait_in_guest = true;
766d3571 4657 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4658 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4659 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4660 kvm->arch.pause_in_guest = true;
b5170063
WL		 4661 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4662 kvm->arch.cstate_in_guest = true;
4d5422ce
WL		 4663 r = 0;
4664 break;
6fbbde9a
DS		 4665 case KVM_CAP_MSR_PLATFORM_INFO:
4666 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4667 r = 0;
c4f55198
JM		 4668 break;
4669 case KVM_CAP_EXCEPTION_PAYLOAD:
4670 kvm->arch.exception_payload_enabled = cap->args[0];
4671 r = 0;
6fbbde9a 4672 break;
90de4a18
NA		 4673 default:
4674 r = -EINVAL;
4675 break;
4676 }
4677 return r;
4678}
4679
1fe779f8
CO		 4680long kvm_arch_vm_ioctl(struct file *filp,
4681 unsigned int ioctl, unsigned long arg)
4682{
4683 struct kvm *kvm = filp->private_data;
4684 void __user *argp = (void __user *)arg;
367e1319 4685 int r = -ENOTTY;
f0d66275
DH		 4686 /*
4687 * This union makes it completely explicit to gcc-3.x
4688 * that these two variables' stack usage should be
4689 * combined, not added together.
4690 */
4691 union {
4692 struct kvm_pit_state ps;
e9f42757 4693 struct kvm_pit_state2 ps2;
c5ff41ce 4694 struct kvm_pit_config pit_config;
f0d66275 4695 } u;
1fe779f8
CO		 4696
4697 switch (ioctl) {
4698 case KVM_SET_TSS_ADDR:
4699 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4700 break;
b927a3ce
SY		 4701 case KVM_SET_IDENTITY_MAP_ADDR: {
4702 u64 ident_addr;
4703
1af1ac91
DH		 4704 mutex_lock(&kvm->lock);
4705 r = -EINVAL;
4706 if (kvm->created_vcpus)
4707 goto set_identity_unlock;
b927a3ce 4708 r = -EFAULT;
0e96f31e 4709 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4710 goto set_identity_unlock;
b927a3ce 4711 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4712set_identity_unlock:
4713 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4714 break;
4715 }
1fe779f8
CO		 4716 case KVM_SET_NR_MMU_PAGES:
4717 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4718 break;
4719 case KVM_GET_NR_MMU_PAGES:
4720 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4721 break;
3ddea128 4722 case KVM_CREATE_IRQCHIP: {
3ddea128 4723 mutex_lock(&kvm->lock);
09941366 4724
3ddea128 4725 r = -EEXIST;
35e6eaa3 4726 if (irqchip_in_kernel(kvm))
3ddea128 4727 goto create_irqchip_unlock;
09941366 4728
3e515705 4729 r = -EINVAL;
557abc40 4730 if (kvm->created_vcpus)
3e515705 4731 goto create_irqchip_unlock;
09941366
RK		 4732
4733 r = kvm_pic_init(kvm);
4734 if (r)
3ddea128 4735 goto create_irqchip_unlock;
09941366
RK		 4736
4737 r = kvm_ioapic_init(kvm);
4738 if (r) {
09941366 4739 kvm_pic_destroy(kvm);
3ddea128 4740 goto create_irqchip_unlock;
09941366
RK		 4741 }
4742
399ec807
AK		 4743 r = kvm_setup_default_irq_routing(kvm);
4744 if (r) {
72bb2fcd 4745 kvm_ioapic_destroy(kvm);
09941366 4746 kvm_pic_destroy(kvm);
71ba994c 4747 goto create_irqchip_unlock;
399ec807 4748 }
49776faf 4749 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4750 smp_wmb();
49776faf 4751 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4752 create_irqchip_unlock:
4753 mutex_unlock(&kvm->lock);
1fe779f8 4754 break;
3ddea128 4755 }
7837699f 4756 case KVM_CREATE_PIT:
c5ff41ce
JK		 4757 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4758 goto create_pit;
4759 case KVM_CREATE_PIT2:
4760 r = -EFAULT;
4761 if (copy_from_user(&u.pit_config, argp,
4762 sizeof(struct kvm_pit_config)))
4763 goto out;
4764 create_pit:
250715a6 4765 mutex_lock(&kvm->lock);
269e05e4
AK		 4766 r = -EEXIST;
4767 if (kvm->arch.vpit)
4768 goto create_pit_unlock;
7837699f 4769 r = -ENOMEM;
c5ff41ce 4770 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4771 if (kvm->arch.vpit)
4772 r = 0;
269e05e4 4773 create_pit_unlock:
250715a6 4774 mutex_unlock(&kvm->lock);
7837699f 4775 break;
1fe779f8
CO		 4776 case KVM_GET_IRQCHIP: {
4777 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4778 struct kvm_irqchip *chip;
1fe779f8 4779
ff5c2c03
SL		 4780 chip = memdup_user(argp, sizeof(*chip));
4781 if (IS_ERR(chip)) {
4782 r = PTR_ERR(chip);
1fe779f8 4783 goto out;
ff5c2c03
SL		 4784 }
4785
1fe779f8 4786 r = -ENXIO;
826da321 4787 if (!irqchip_kernel(kvm))
f0d66275
DH		 4788 goto get_irqchip_out;
4789 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4790 if (r)
f0d66275 4791 goto get_irqchip_out;
1fe779f8 4792 r = -EFAULT;
0e96f31e 4793 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4794 goto get_irqchip_out;
1fe779f8 4795 r = 0;
f0d66275
DH		 4796 get_irqchip_out:
4797 kfree(chip);
1fe779f8
CO		 4798 break;
4799 }
4800 case KVM_SET_IRQCHIP: {
4801 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4802 struct kvm_irqchip *chip;
1fe779f8 4803
ff5c2c03
SL		 4804 chip = memdup_user(argp, sizeof(*chip));
4805 if (IS_ERR(chip)) {
4806 r = PTR_ERR(chip);
1fe779f8 4807 goto out;
ff5c2c03
SL		 4808 }
4809
1fe779f8 4810 r = -ENXIO;
826da321 4811 if (!irqchip_kernel(kvm))
f0d66275
DH		 4812 goto set_irqchip_out;
4813 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4814 if (r)
f0d66275 4815 goto set_irqchip_out;
1fe779f8 4816 r = 0;
f0d66275
DH		 4817 set_irqchip_out:
4818 kfree(chip);
1fe779f8
CO		 4819 break;
4820 }
e0f63cb9 4821 case KVM_GET_PIT: {
e0f63cb9 4822 r = -EFAULT;
f0d66275 4823 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4824 goto out;
4825 r = -ENXIO;
4826 if (!kvm->arch.vpit)
4827 goto out;
f0d66275 4828 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4829 if (r)
4830 goto out;
4831 r = -EFAULT;
f0d66275 4832 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4833 goto out;
4834 r = 0;
4835 break;
4836 }
4837 case KVM_SET_PIT: {
e0f63cb9 4838 r = -EFAULT;
0e96f31e 4839 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4840 goto out;
4841 r = -ENXIO;
4842 if (!kvm->arch.vpit)
4843 goto out;
f0d66275 4844 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4845 break;
4846 }
e9f42757
BK		 4847 case KVM_GET_PIT2: {
4848 r = -ENXIO;
4849 if (!kvm->arch.vpit)
4850 goto out;
4851 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4852 if (r)
4853 goto out;
4854 r = -EFAULT;
4855 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4856 goto out;
4857 r = 0;
4858 break;
4859 }
4860 case KVM_SET_PIT2: {
4861 r = -EFAULT;
4862 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4863 goto out;
4864 r = -ENXIO;
4865 if (!kvm->arch.vpit)
4866 goto out;
4867 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4868 break;
4869 }
52d939a0
MT		 4870 case KVM_REINJECT_CONTROL: {
4871 struct kvm_reinject_control control;
4872 r = -EFAULT;
4873 if (copy_from_user(&control, argp, sizeof(control)))
4874 goto out;
4875 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4876 break;
4877 }
d71ba788
PB		 4878 case KVM_SET_BOOT_CPU_ID:
4879 r = 0;
4880 mutex_lock(&kvm->lock);
557abc40 4881 if (kvm->created_vcpus)
d71ba788
PB		 4882 r = -EBUSY;
4883 else
4884 kvm->arch.bsp_vcpu_id = arg;
4885 mutex_unlock(&kvm->lock);
4886 break;
ffde22ac 4887 case KVM_XEN_HVM_CONFIG: {
51776043 4888 struct kvm_xen_hvm_config xhc;
ffde22ac 4889 r = -EFAULT;
51776043 4890 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4891 goto out;
4892 r = -EINVAL;
51776043 4893 if (xhc.flags)
ffde22ac 4894 goto out;
51776043 4895 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4896 r = 0;
4897 break;
4898 }
afbcf7ab 4899 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4900 struct kvm_clock_data user_ns;
4901 u64 now_ns;
afbcf7ab
GC		 4902
4903 r = -EFAULT;
4904 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4905 goto out;
4906
4907 r = -EINVAL;
4908 if (user_ns.flags)
4909 goto out;
4910
4911 r = 0;
0bc48bea
RK		 4912 /*
4913 * TODO: userspace has to take care of races with VCPU_RUN, so
4914 * kvm_gen_update_masterclock() can be cut down to locked
4915 * pvclock_update_vm_gtod_copy().
4916 */
4917 kvm_gen_update_masterclock(kvm);
e891a32e 4918 now_ns = get_kvmclock_ns(kvm);
108b249c 4919 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4920 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4921 break;
4922 }
4923 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4924 struct kvm_clock_data user_ns;
4925 u64 now_ns;
4926
e891a32e 4927 now_ns = get_kvmclock_ns(kvm);
108b249c 4928 user_ns.clock = now_ns;
e3fd9a93 4929 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4930 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4931
4932 r = -EFAULT;
4933 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4934 goto out;
4935 r = 0;
4936 break;
4937 }
5acc5c06
BS		 4938 case KVM_MEMORY_ENCRYPT_OP: {
4939 r = -ENOTTY;
4940 if (kvm_x86_ops->mem_enc_op)
4941 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4942 break;
4943 }
69eaedee
BS		 4944 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4945 struct kvm_enc_region region;
4946
4947 r = -EFAULT;
4948 if (copy_from_user(&region, argp, sizeof(region)))
4949 goto out;
4950
4951 r = -ENOTTY;
4952 if (kvm_x86_ops->mem_enc_reg_region)
4953 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4954 break;
4955 }
4956 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4957 struct kvm_enc_region region;
4958
4959 r = -EFAULT;
4960 if (copy_from_user(&region, argp, sizeof(region)))
4961 goto out;
4962
4963 r = -ENOTTY;
4964 if (kvm_x86_ops->mem_enc_unreg_region)
4965 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4966 break;
4967 }
faeb7833
RK		 4968 case KVM_HYPERV_EVENTFD: {
4969 struct kvm_hyperv_eventfd hvevfd;
4970
4971 r = -EFAULT;
4972 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4973 goto out;
4974 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4975 break;
4976 }
66bb8a06
EH		 4977 case KVM_SET_PMU_EVENT_FILTER:
4978 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
4979 break;
1fe779f8 4980 default:
ad6260da 4981 r = -ENOTTY;
1fe779f8
CO		 4982 }
4983out:
4984 return r;
4985}
4986
a16b043c 4987static void kvm_init_msr_list(void)
043405e1
CO		 4988{
4989 u32 dummy[2];
4990 unsigned i, j;
4991
62ef68bb 4992 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4993 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4994 continue;
93c4adc7
PB		 4995
4996 /*
4997 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4998 * to the guests in some cases.
93c4adc7
PB		 4999 */
5000 switch (msrs_to_save[i]) {
5001 case MSR_IA32_BNDCFGS:
503234b3 5002 if (!kvm_mpx_supported())
93c4adc7
PB		 5003 continue;
5004 break;
9dbe6cf9
PB		 5005 case MSR_TSC_AUX:
5006 if (!kvm_x86_ops->rdtscp_supported())
5007 continue;
5008 break;
bf8c55d8
CP		 5009 case MSR_IA32_RTIT_CTL:
5010 case MSR_IA32_RTIT_STATUS:
5011 if (!kvm_x86_ops->pt_supported())
5012 continue;
5013 break;
5014 case MSR_IA32_RTIT_CR3_MATCH:
5015 if (!kvm_x86_ops->pt_supported() ||
5016 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5017 continue;
5018 break;
5019 case MSR_IA32_RTIT_OUTPUT_BASE:
5020 case MSR_IA32_RTIT_OUTPUT_MASK:
5021 if (!kvm_x86_ops->pt_supported() ||
5022 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5023 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5024 continue;
5025 break;
5026 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5027 if (!kvm_x86_ops->pt_supported() ||
5028 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5029 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5030 continue;
5031 break;
5032 }
93c4adc7
PB		 5033 default:
5034 break;
5035 }
5036
043405e1
CO		 5037 if (j < i)
5038 msrs_to_save[j] = msrs_to_save[i];
5039 j++;
5040 }
5041 num_msrs_to_save = j;
62ef68bb
PB		 5042
5043 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 5044 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5045 continue;
62ef68bb
PB		 5046
5047 if (j < i)
5048 emulated_msrs[j] = emulated_msrs[i];
5049 j++;
5050 }
5051 num_emulated_msrs = j;
801e459a
TL		 5052
5053 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5054 struct kvm_msr_entry msr;
5055
5056 msr.index = msr_based_features[i];
66421c1e 5057 if (kvm_get_msr_feature(&msr))
801e459a
TL		 5058 continue;
5059
5060 if (j < i)
5061 msr_based_features[j] = msr_based_features[i];
5062 j++;
5063 }
5064 num_msr_based_features = j;
043405e1
CO		 5065}
5066
bda9020e
MT		 5067static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5068 const void *v)
bbd9b64e 5069{
70252a10
AK		 5070 int handled = 0;
5071 int n;
5072
5073 do {
5074 n = min(len, 8);
bce87cce 5075 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5076 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5077 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 5078 break;
5079 handled += n;
5080 addr += n;
5081 len -= n;
5082 v += n;
5083 } while (len);
bbd9b64e 5084
70252a10 5085 return handled;
bbd9b64e
CO		 5086}
5087
bda9020e 5088static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 5089{
70252a10
AK		 5090 int handled = 0;
5091 int n;
5092
5093 do {
5094 n = min(len, 8);
bce87cce 5095 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5096 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5097 addr, n, v))
5098 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5099 break;
e39d200f 5100 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5101 handled += n;
5102 addr += n;
5103 len -= n;
5104 v += n;
5105 } while (len);
bbd9b64e 5106
70252a10 5107 return handled;
bbd9b64e
CO		 5108}
5109
2dafc6c2
GN		 5110static void kvm_set_segment(struct kvm_vcpu *vcpu,
5111 struct kvm_segment *var, int seg)
5112{
5113 kvm_x86_ops->set_segment(vcpu, var, seg);
5114}
5115
5116void kvm_get_segment(struct kvm_vcpu *vcpu,
5117 struct kvm_segment *var, int seg)
5118{
5119 kvm_x86_ops->get_segment(vcpu, var, seg);
5120}
5121
54987b7a
PB		 5122gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5123 struct x86_exception *exception)
02f59dc9
JR		 5124{
5125 gpa_t t_gpa;
02f59dc9
JR		 5126
5127 BUG_ON(!mmu_is_nested(vcpu));
5128
5129 /* NPT walks are always user-walks */
5130 access |= PFERR_USER_MASK;
44dd3ffa 5131 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5132
5133 return t_gpa;
5134}
5135
ab9ae313
AK		 5136gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5137 struct x86_exception *exception)
1871c602
GN		 5138{
5139 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5140 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5141}
5142
ab9ae313
AK		 5143 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5144 struct x86_exception *exception)
1871c602
GN		 5145{
5146 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5147 access |= PFERR_FETCH_MASK;
ab9ae313 5148 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5149}
5150
ab9ae313
AK		 5151gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5152 struct x86_exception *exception)
1871c602
GN		 5153{
5154 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5155 access |= PFERR_WRITE_MASK;
ab9ae313 5156 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5157}
5158
5159/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5160gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5161 struct x86_exception *exception)
1871c602 5162{
ab9ae313 5163 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5164}
5165
5166static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5167 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5168 struct x86_exception *exception)
bbd9b64e
CO		 5169{
5170 void *data = val;
10589a46 5171 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5172
5173 while (bytes) {
14dfe855 5174 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5175 exception);
bbd9b64e 5176 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5177 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5178 int ret;
5179
bcc55cba 5180 if (gpa == UNMAPPED_GVA)
ab9ae313 5181 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5182 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5183 offset, toread);
10589a46 5184 if (ret < 0) {
c3cd7ffa 5185 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5186 goto out;
5187 }
bbd9b64e 5188
77c2002e
IE		 5189 bytes -= toread;
5190 data += toread;
5191 addr += toread;
bbd9b64e 5192 }
10589a46 5193out:
10589a46 5194 return r;
bbd9b64e 5195}
77c2002e 5196
1871c602 5197/* used for instruction fetching */
0f65dd70
AK		 5198static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5199 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5200 struct x86_exception *exception)
1871c602 5201{
0f65dd70 5202 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5203 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5204 unsigned offset;
5205 int ret;
0f65dd70 5206
44583cba
PB		 5207 /* Inline kvm_read_guest_virt_helper for speed. */
5208 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5209 exception);
5210 if (unlikely(gpa == UNMAPPED_GVA))
5211 return X86EMUL_PROPAGATE_FAULT;
5212
5213 offset = addr & (PAGE_SIZE-1);
5214 if (WARN_ON(offset + bytes > PAGE_SIZE))
5215 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5216 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5217 offset, bytes);
44583cba
PB		 5218 if (unlikely(ret < 0))
5219 return X86EMUL_IO_NEEDED;
5220
5221 return X86EMUL_CONTINUE;
1871c602
GN		 5222}
5223
ce14e868 5224int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5225 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5226 struct x86_exception *exception)
1871c602
GN		 5227{
5228 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5229
353c0956
PB		 5230 /*
5231 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5232 * is returned, but our callers are not ready for that and they blindly
5233 * call kvm_inject_page_fault. Ensure that they at least do not leak
5234 * uninitialized kernel stack memory into cr2 and error code.
5235 */
5236 memset(exception, 0, sizeof(*exception));
1871c602 5237 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5238 exception);
1871c602 5239}
064aea77 5240EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5241
ce14e868
PB		 5242static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5243 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5244 struct x86_exception *exception, bool system)
1871c602 5245{
0f65dd70 5246 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5247 u32 access = 0;
5248
5249 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5250 access |= PFERR_USER_MASK;
5251
5252 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5253}
5254
7a036a6f
RK		 5255static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5256 unsigned long addr, void *val, unsigned int bytes)
5257{
5258 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5259 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5260
5261 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5262}
5263
ce14e868
PB		 5264static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5265 struct kvm_vcpu *vcpu, u32 access,
5266 struct x86_exception *exception)
77c2002e
IE		 5267{
5268 void *data = val;
5269 int r = X86EMUL_CONTINUE;
5270
5271 while (bytes) {
14dfe855 5272 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5273 access,
ab9ae313 5274 exception);
77c2002e
IE		 5275 unsigned offset = addr & (PAGE_SIZE-1);
5276 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5277 int ret;
5278
bcc55cba 5279 if (gpa == UNMAPPED_GVA)
ab9ae313 5280 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5281 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5282 if (ret < 0) {
c3cd7ffa 5283 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5284 goto out;
5285 }
5286
5287 bytes -= towrite;
5288 data += towrite;
5289 addr += towrite;
5290 }
5291out:
5292 return r;
5293}
ce14e868
PB		 5294
5295static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5296 unsigned int bytes, struct x86_exception *exception,
5297 bool system)
ce14e868
PB		 5298{
5299 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5300 u32 access = PFERR_WRITE_MASK;
5301
5302 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5303 access |= PFERR_USER_MASK;
ce14e868
PB		 5304
5305 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5306 access, exception);
ce14e868
PB		 5307}
5308
5309int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5310 unsigned int bytes, struct x86_exception *exception)
5311{
c595ceee
PB		 5312 /* kvm_write_guest_virt_system can pull in tons of pages. */
5313 vcpu->arch.l1tf_flush_l1d = true;
5314
ce14e868
PB		 5315 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5316 PFERR_WRITE_MASK, exception);
5317}
6a4d7550 5318EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5319
082d06ed
WL		 5320int handle_ud(struct kvm_vcpu *vcpu)
5321{
6c86eedc 5322 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5323 enum emulation_result er;
6c86eedc
WL		 5324 char sig[5]; /* ud2; .ascii "kvm" */
5325 struct x86_exception e;
5326
5327 if (force_emulation_prefix &&
3c9fa24c
PB		 5328 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5329 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5330 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5331 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5332 emul_type = 0;
5333 }
082d06ed 5334
0ce97a2b 5335 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5336 if (er == EMULATE_USER_EXIT)
5337 return 0;
5338 if (er != EMULATE_DONE)
5339 kvm_queue_exception(vcpu, UD_VECTOR);
5340 return 1;
5341}
5342EXPORT_SYMBOL_GPL(handle_ud);
5343
0f89b207
TL		 5344static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5345 gpa_t gpa, bool write)
5346{
5347 /* For APIC access vmexit */
5348 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5349 return 1;
5350
5351 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5352 trace_vcpu_match_mmio(gva, gpa, write, true);
5353 return 1;
5354 }
5355
5356 return 0;
5357}
5358
af7cc7d1
XG		 5359static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5360 gpa_t *gpa, struct x86_exception *exception,
5361 bool write)
5362{
97d64b78
AK		 5363 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5364 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5365
be94f6b7
HH		 5366 /*
5367 * currently PKRU is only applied to ept enabled guest so
5368 * there is no pkey in EPT page table for L1 guest or EPT
5369 * shadow page table for L2 guest.
5370 */
97d64b78 5371 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5372 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5373 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5374 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5375 (gva & (PAGE_SIZE - 1));
4f022648 5376 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5377 return 1;
5378 }
5379
af7cc7d1
XG		 5380 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5381
5382 if (*gpa == UNMAPPED_GVA)
5383 return -1;
5384
0f89b207 5385 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5386}
5387
3200f405 5388int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5389 const void *val, int bytes)
bbd9b64e
CO		 5390{
5391 int ret;
5392
54bf36aa 5393 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5394 if (ret < 0)
bbd9b64e 5395 return 0;
0eb05bf2 5396 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5397 return 1;
5398}
5399
77d197b2
XG		 5400struct read_write_emulator_ops {
5401 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5402 int bytes);
5403 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5404 void *val, int bytes);
5405 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5406 int bytes, void *val);
5407 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5408 void *val, int bytes);
5409 bool write;
5410};
5411
5412static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5413{
5414 if (vcpu->mmio_read_completed) {
77d197b2 5415 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5416 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5417 vcpu->mmio_read_completed = 0;
5418 return 1;
5419 }
5420
5421 return 0;
5422}
5423
5424static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5425 void *val, int bytes)
5426{
54bf36aa 5427 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5428}
5429
5430static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5431 void *val, int bytes)
5432{
5433 return emulator_write_phys(vcpu, gpa, val, bytes);
5434}
5435
5436static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5437{
e39d200f 5438 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5439 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5440}
5441
5442static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5443 void *val, int bytes)
5444{
e39d200f 5445 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5446 return X86EMUL_IO_NEEDED;
5447}
5448
5449static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5450 void *val, int bytes)
5451{
f78146b0
AK		 5452 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5453
87da7e66 5454 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5455 return X86EMUL_CONTINUE;
5456}
5457
0fbe9b0b 5458static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5459 .read_write_prepare = read_prepare,
5460 .read_write_emulate = read_emulate,
5461 .read_write_mmio = vcpu_mmio_read,
5462 .read_write_exit_mmio = read_exit_mmio,
5463};
5464
0fbe9b0b 5465static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5466 .read_write_emulate = write_emulate,
5467 .read_write_mmio = write_mmio,
5468 .read_write_exit_mmio = write_exit_mmio,
5469 .write = true,
5470};
5471
22388a3c
XG		 5472static int emulator_read_write_onepage(unsigned long addr, void *val,
5473 unsigned int bytes,
5474 struct x86_exception *exception,
5475 struct kvm_vcpu *vcpu,
0fbe9b0b 5476 const struct read_write_emulator_ops *ops)
bbd9b64e 5477{
af7cc7d1
XG		 5478 gpa_t gpa;
5479 int handled, ret;
22388a3c 5480 bool write = ops->write;
f78146b0 5481 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5482 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5483
5484 /*
5485 * If the exit was due to a NPF we may already have a GPA.
5486 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5487 * Note, this cannot be used on string operations since string
5488 * operation using rep will only have the initial GPA from the NPF
5489 * occurred.
5490 */
5491 if (vcpu->arch.gpa_available &&
5492 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5493 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5494 gpa = vcpu->arch.gpa_val;
5495 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5496 } else {
5497 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5498 if (ret < 0)
5499 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5500 }
10589a46 5501
618232e2 5502 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5503 return X86EMUL_CONTINUE;
5504
bbd9b64e
CO		 5505 /*
5506 * Is this MMIO handled locally?
5507 */
22388a3c 5508 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5509 if (handled == bytes)
bbd9b64e 5510 return X86EMUL_CONTINUE;
bbd9b64e 5511
70252a10
AK		 5512 gpa += handled;
5513 bytes -= handled;
5514 val += handled;
5515
87da7e66
XG		 5516 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5517 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5518 frag->gpa = gpa;
5519 frag->data = val;
5520 frag->len = bytes;
f78146b0 5521 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5522}
5523
52eb5a6d
XL		 5524static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5525 unsigned long addr,
22388a3c
XG		 5526 void *val, unsigned int bytes,
5527 struct x86_exception *exception,
0fbe9b0b 5528 const struct read_write_emulator_ops *ops)
bbd9b64e 5529{
0f65dd70 5530 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5531 gpa_t gpa;
5532 int rc;
5533
5534 if (ops->read_write_prepare &&
5535 ops->read_write_prepare(vcpu, val, bytes))
5536 return X86EMUL_CONTINUE;
5537
5538 vcpu->mmio_nr_fragments = 0;
0f65dd70 5539
bbd9b64e
CO		 5540 /* Crossing a page boundary? */
5541 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5542 int now;
bbd9b64e
CO		 5543
5544 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5545 rc = emulator_read_write_onepage(addr, val, now, exception,
5546 vcpu, ops);
5547
bbd9b64e
CO		 5548 if (rc != X86EMUL_CONTINUE)
5549 return rc;
5550 addr += now;
bac15531
NA		 5551 if (ctxt->mode != X86EMUL_MODE_PROT64)
5552 addr = (u32)addr;
bbd9b64e
CO		 5553 val += now;
5554 bytes -= now;
5555 }
22388a3c 5556
f78146b0
AK		 5557 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5558 vcpu, ops);
5559 if (rc != X86EMUL_CONTINUE)
5560 return rc;
5561
5562 if (!vcpu->mmio_nr_fragments)
5563 return rc;
5564
5565 gpa = vcpu->mmio_fragments[0].gpa;
5566
5567 vcpu->mmio_needed = 1;
5568 vcpu->mmio_cur_fragment = 0;
5569
87da7e66 5570 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5571 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5572 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5573 vcpu->run->mmio.phys_addr = gpa;
5574
5575 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5576}
5577
5578static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5579 unsigned long addr,
5580 void *val,
5581 unsigned int bytes,
5582 struct x86_exception *exception)
5583{
5584 return emulator_read_write(ctxt, addr, val, bytes,
5585 exception, &read_emultor);
5586}
5587
52eb5a6d 5588static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5589 unsigned long addr,
5590 const void *val,
5591 unsigned int bytes,
5592 struct x86_exception *exception)
5593{
5594 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5595 exception, &write_emultor);
bbd9b64e 5596}
bbd9b64e 5597
daea3e73
AK		 5598#define CMPXCHG_TYPE(t, ptr, old, new) \
5599 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5600
5601#ifdef CONFIG_X86_64
5602# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5603#else
5604# define CMPXCHG64(ptr, old, new) \
9749a6c0 5605 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5606#endif
5607
0f65dd70
AK		 5608static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5609 unsigned long addr,
bbd9b64e
CO		 5610 const void *old,
5611 const void *new,
5612 unsigned int bytes,
0f65dd70 5613 struct x86_exception *exception)
bbd9b64e 5614{
42e35f80 5615 struct kvm_host_map map;
0f65dd70 5616 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73 5617 gpa_t gpa;
daea3e73
AK		 5618 char *kaddr;
5619 bool exchanged;
2bacc55c 5620
daea3e73
AK		 5621 /* guests cmpxchg8b have to be emulated atomically */
5622 if (bytes > 8 || (bytes & (bytes - 1)))
5623 goto emul_write;
10589a46 5624
daea3e73 5625 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5626
daea3e73
AK		 5627 if (gpa == UNMAPPED_GVA ||
5628 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5629 goto emul_write;
2bacc55c 5630
daea3e73
AK		 5631 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5632 goto emul_write;
72dc67a6 5633
42e35f80 5634 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
c19b8bd6 5635 goto emul_write;
72dc67a6 5636
42e35f80
KA		 5637 kaddr = map.hva + offset_in_page(gpa);
5638
daea3e73
AK		 5639 switch (bytes) {
5640 case 1:
5641 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5642 break;
5643 case 2:
5644 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5645 break;
5646 case 4:
5647 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5648 break;
5649 case 8:
5650 exchanged = CMPXCHG64(kaddr, old, new);
5651 break;
5652 default:
5653 BUG();
2bacc55c 5654 }
42e35f80
KA		 5655
5656 kvm_vcpu_unmap(vcpu, &map, true);
daea3e73
AK		 5657
5658 if (!exchanged)
5659 return X86EMUL_CMPXCHG_FAILED;
5660
0eb05bf2 5661 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5662
5663 return X86EMUL_CONTINUE;
4a5f48f6 5664
3200f405 5665emul_write:
daea3e73 5666 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5667
0f65dd70 5668 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5669}
5670
cf8f70bf
GN		 5671static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5672{
cbfc6c91 5673 int r = 0, i;
cf8f70bf 5674
cbfc6c91
WL		 5675 for (i = 0; i < vcpu->arch.pio.count; i++) {
5676 if (vcpu->arch.pio.in)
5677 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5678 vcpu->arch.pio.size, pd);
5679 else
5680 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5681 vcpu->arch.pio.port, vcpu->arch.pio.size,
5682 pd);
5683 if (r)
5684 break;
5685 pd += vcpu->arch.pio.size;
5686 }
cf8f70bf
GN		 5687 return r;
5688}
5689
6f6fbe98
XG		 5690static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5691 unsigned short port, void *val,
5692 unsigned int count, bool in)
cf8f70bf 5693{
cf8f70bf 5694 vcpu->arch.pio.port = port;
6f6fbe98 5695 vcpu->arch.pio.in = in;
7972995b 5696 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5697 vcpu->arch.pio.size = size;
5698
5699 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5700 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5701 return 1;
5702 }
5703
5704 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5705 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5706 vcpu->run->io.size = size;
5707 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5708 vcpu->run->io.count = count;
5709 vcpu->run->io.port = port;
5710
5711 return 0;
5712}
5713
6f6fbe98
XG		 5714static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5715 int size, unsigned short port, void *val,
5716 unsigned int count)
cf8f70bf 5717{
ca1d4a9e 5718 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5719 int ret;
ca1d4a9e 5720
6f6fbe98
XG		 5721 if (vcpu->arch.pio.count)
5722 goto data_avail;
cf8f70bf 5723
cbfc6c91
WL		 5724 memset(vcpu->arch.pio_data, 0, size * count);
5725
6f6fbe98
XG		 5726 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5727 if (ret) {
5728data_avail:
5729 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5730 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5731 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5732 return 1;
5733 }
5734
cf8f70bf
GN		 5735 return 0;
5736}
5737
6f6fbe98
XG		 5738static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5739 int size, unsigned short port,
5740 const void *val, unsigned int count)
5741{
5742 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5743
5744 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5745 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5746 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5747}
5748
bbd9b64e
CO		 5749static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5750{
5751 return kvm_x86_ops->get_segment_base(vcpu, seg);
5752}
5753
3cb16fe7 5754static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5755{
3cb16fe7 5756 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5757}
5758
ae6a2375 5759static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5760{
5761 if (!need_emulate_wbinvd(vcpu))
5762 return X86EMUL_CONTINUE;
5763
5764 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5765 int cpu = get_cpu();
5766
5767 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5768 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5769 wbinvd_ipi, NULL, 1);
2eec7343 5770 put_cpu();
f5f48ee1 5771 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5772 } else
5773 wbinvd();
f5f48ee1
SY		 5774 return X86EMUL_CONTINUE;
5775}
5cb56059
JS		 5776
5777int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5778{
6affcbed
KH		 5779 kvm_emulate_wbinvd_noskip(vcpu);
5780 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5781}
f5f48ee1
SY		 5782EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5783
5cb56059
JS		 5784
5785
bcaf5cc5
AK		 5786static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5787{
5cb56059 5788 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5789}
5790
52eb5a6d
XL		 5791static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5792 unsigned long *dest)
bbd9b64e 5793{
16f8a6f9 5794 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5795}
5796
52eb5a6d
XL		 5797static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5798 unsigned long value)
bbd9b64e 5799{
338dbc97 5800
717746e3 5801 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5802}
5803
52a46617 5804static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5805{
52a46617 5806 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5807}
5808
717746e3 5809static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5810{
717746e3 5811 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5812 unsigned long value;
5813
5814 switch (cr) {
5815 case 0:
5816 value = kvm_read_cr0(vcpu);
5817 break;
5818 case 2:
5819 value = vcpu->arch.cr2;
5820 break;
5821 case 3:
9f8fe504 5822 value = kvm_read_cr3(vcpu);
52a46617
GN		 5823 break;
5824 case 4:
5825 value = kvm_read_cr4(vcpu);
5826 break;
5827 case 8:
5828 value = kvm_get_cr8(vcpu);
5829 break;
5830 default:
a737f256 5831 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5832 return 0;
5833 }
5834
5835 return value;
5836}
5837
717746e3 5838static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5839{
717746e3 5840 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5841 int res = 0;
5842
52a46617
GN		 5843 switch (cr) {
5844 case 0:
49a9b07e 5845 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5846 break;
5847 case 2:
5848 vcpu->arch.cr2 = val;
5849 break;
5850 case 3:
2390218b 5851 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5852 break;
5853 case 4:
a83b29c6 5854 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5855 break;
5856 case 8:
eea1cff9 5857 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5858 break;
5859 default:
a737f256 5860 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5861 res = -1;
52a46617 5862 }
0f12244f
GN		 5863
5864 return res;
52a46617
GN		 5865}
5866
717746e3 5867static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5868{
717746e3 5869 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5870}
5871
4bff1e86 5872static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5873{
4bff1e86 5874 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5875}
5876
4bff1e86 5877static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5878{
4bff1e86 5879 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5880}
5881
1ac9d0cf
AK		 5882static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5883{
5884 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5885}
5886
5887static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5888{
5889 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5890}
5891
4bff1e86
AK		 5892static unsigned long emulator_get_cached_segment_base(
5893 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5894{
4bff1e86 5895 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5896}
5897
1aa36616
AK		 5898static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5899 struct desc_struct *desc, u32 *base3,
5900 int seg)
2dafc6c2
GN		 5901{
5902 struct kvm_segment var;
5903
4bff1e86 5904 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5905 *selector = var.selector;
2dafc6c2 5906
378a8b09
GN		 5907 if (var.unusable) {
5908 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5909 if (base3)
5910 *base3 = 0;
2dafc6c2 5911 return false;
378a8b09 5912 }
2dafc6c2
GN		 5913
5914 if (var.g)
5915 var.limit >>= 12;
5916 set_desc_limit(desc, var.limit);
5917 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5918#ifdef CONFIG_X86_64
5919 if (base3)
5920 *base3 = var.base >> 32;
5921#endif
2dafc6c2
GN		 5922 desc->type = var.type;
5923 desc->s = var.s;
5924 desc->dpl = var.dpl;
5925 desc->p = var.present;
5926 desc->avl = var.avl;
5927 desc->l = var.l;
5928 desc->d = var.db;
5929 desc->g = var.g;
5930
5931 return true;
5932}
5933
1aa36616
AK		 5934static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5935 struct desc_struct *desc, u32 base3,
5936 int seg)
2dafc6c2 5937{
4bff1e86 5938 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5939 struct kvm_segment var;
5940
1aa36616 5941 var.selector = selector;
2dafc6c2 5942 var.base = get_desc_base(desc);
5601d05b
GN		 5943#ifdef CONFIG_X86_64
5944 var.base |= ((u64)base3) << 32;
5945#endif
2dafc6c2
GN		 5946 var.limit = get_desc_limit(desc);
5947 if (desc->g)
5948 var.limit = (var.limit << 12) | 0xfff;
5949 var.type = desc->type;
2dafc6c2
GN		 5950 var.dpl = desc->dpl;
5951 var.db = desc->d;
5952 var.s = desc->s;
5953 var.l = desc->l;
5954 var.g = desc->g;
5955 var.avl = desc->avl;
5956 var.present = desc->p;
5957 var.unusable = !var.present;
5958 var.padding = 0;
5959
5960 kvm_set_segment(vcpu, &var, seg);
5961 return;
5962}
5963
717746e3
AK		 5964static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5965 u32 msr_index, u64 *pdata)
5966{
609e36d3
PB		 5967 struct msr_data msr;
5968 int r;
5969
5970 msr.index = msr_index;
5971 msr.host_initiated = false;
5972 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5973 if (r)
5974 return r;
5975
5976 *pdata = msr.data;
5977 return 0;
717746e3
AK		 5978}
5979
5980static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5981 u32 msr_index, u64 data)
5982{
8fe8ab46
WA		 5983 struct msr_data msr;
5984
5985 msr.data = data;
5986 msr.index = msr_index;
5987 msr.host_initiated = false;
5988 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5989}
5990
64d60670
PB		 5991static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5992{
5993 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5994
5995 return vcpu->arch.smbase;
5996}
5997
5998static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5999{
6000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6001
6002 vcpu->arch.smbase = smbase;
6003}
6004
67f4d428
NA		 6005static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6006 u32 pmc)
6007{
c6702c9d 6008 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 6009}
6010
222d21aa
AK		 6011static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6012 u32 pmc, u64 *pdata)
6013{
c6702c9d 6014 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 6015}
6016
6c3287f7
AK		 6017static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6018{
6019 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6020}
6021
2953538e 6022static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 6023 struct x86_instruction_info *info,
c4f035c6
AK		 6024 enum x86_intercept_stage stage)
6025{
2953538e 6026 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 6027}
6028
e911eb3b
YZ		 6029static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6030 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 6031{
e911eb3b 6032 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 6033}
6034
dd856efa
AK		 6035static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6036{
6037 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6038}
6039
6040static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6041{
6042 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6043}
6044
801806d9
NA		 6045static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6046{
6047 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6048}
6049
6ed071f0
LP		 6050static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6051{
6052 return emul_to_vcpu(ctxt)->arch.hflags;
6053}
6054
6055static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6056{
c5833c7a 6057 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 6058}
6059
ed19321f
SC		 6060static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6061 const char *smstate)
0234bf88 6062{
ed19321f 6063 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 6064}
6065
c5833c7a
SC		 6066static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6067{
6068 kvm_smm_changed(emul_to_vcpu(ctxt));
6069}
6070
0225fb50 6071static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 6072 .read_gpr = emulator_read_gpr,
6073 .write_gpr = emulator_write_gpr,
ce14e868
PB		 6074 .read_std = emulator_read_std,
6075 .write_std = emulator_write_std,
7a036a6f 6076 .read_phys = kvm_read_guest_phys_system,
1871c602 6077 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 6078 .read_emulated = emulator_read_emulated,
6079 .write_emulated = emulator_write_emulated,
6080 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 6081 .invlpg = emulator_invlpg,
cf8f70bf
GN		 6082 .pio_in_emulated = emulator_pio_in_emulated,
6083 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 6084 .get_segment = emulator_get_segment,
6085 .set_segment = emulator_set_segment,
5951c442 6086 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 6087 .get_gdt = emulator_get_gdt,
160ce1f1 6088 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 6089 .set_gdt = emulator_set_gdt,
6090 .set_idt = emulator_set_idt,
52a46617
GN		 6091 .get_cr = emulator_get_cr,
6092 .set_cr = emulator_set_cr,
9c537244 6093 .cpl = emulator_get_cpl,
35aa5375
GN		 6094 .get_dr = emulator_get_dr,
6095 .set_dr = emulator_set_dr,
64d60670
PB		 6096 .get_smbase = emulator_get_smbase,
6097 .set_smbase = emulator_set_smbase,
717746e3
AK		 6098 .set_msr = emulator_set_msr,
6099 .get_msr = emulator_get_msr,
67f4d428 6100 .check_pmc = emulator_check_pmc,
222d21aa 6101 .read_pmc = emulator_read_pmc,
6c3287f7 6102 .halt = emulator_halt,
bcaf5cc5 6103 .wbinvd = emulator_wbinvd,
d6aa1000 6104 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6105 .intercept = emulator_intercept,
bdb42f5a 6106 .get_cpuid = emulator_get_cpuid,
801806d9 6107 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6108 .get_hflags = emulator_get_hflags,
6109 .set_hflags = emulator_set_hflags,
0234bf88 6110 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6111 .post_leave_smm = emulator_post_leave_smm,
bbd9b64e
CO		 6112};
6113
95cb2295
GN		 6114static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6115{
37ccdcbe 6116 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6117 /*
6118 * an sti; sti; sequence only disable interrupts for the first
6119 * instruction. So, if the last instruction, be it emulated or
6120 * not, left the system with the INT_STI flag enabled, it
6121 * means that the last instruction is an sti. We should not
6122 * leave the flag on in this case. The same goes for mov ss
6123 */
37ccdcbe
PB		 6124 if (int_shadow & mask)
6125 mask = 0;
6addfc42 6126 if (unlikely(int_shadow || mask)) {
95cb2295 6127 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6128 if (!mask)
6129 kvm_make_request(KVM_REQ_EVENT, vcpu);
6130 }
95cb2295
GN		 6131}
6132
ef54bcfe 6133static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6134{
6135 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6136 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6137 return kvm_propagate_fault(vcpu, &ctxt->exception);
6138
6139 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6140 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6141 ctxt->exception.error_code);
54b8486f 6142 else
da9cb575 6143 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6144 return false;
54b8486f
GN		 6145}
6146
8ec4722d
MG		 6147static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6148{
adf52235 6149 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6150 int cs_db, cs_l;
6151
8ec4722d
MG		 6152 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6153
adf52235 6154 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6155 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6156
adf52235
TY		 6157 ctxt->eip = kvm_rip_read(vcpu);
6158 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6159 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6160 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6161 cs_db ? X86EMUL_MODE_PROT32 :
6162 X86EMUL_MODE_PROT16;
a584539b 6163 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6164 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6165 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6166
dd856efa 6167 init_decode_cache(ctxt);
7ae441ea 6168 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6169}
6170
71f9833b 6171int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6172{
9d74191a 6173 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6174 int ret;
6175
6176 init_emulate_ctxt(vcpu);
6177
9dac77fa
AK		 6178 ctxt->op_bytes = 2;
6179 ctxt->ad_bytes = 2;
6180 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6181 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6182
6183 if (ret != X86EMUL_CONTINUE)
6184 return EMULATE_FAIL;
6185
9dac77fa 6186 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6187 kvm_rip_write(vcpu, ctxt->eip);
6188 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6189
63995653
MG		 6190 return EMULATE_DONE;
6191}
6192EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6193
e2366171 6194static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6195{
fc3a9157
JR		 6196 int r = EMULATE_DONE;
6197
6d77dbfc
GN		 6198 ++vcpu->stat.insn_emulation_fail;
6199 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6200
6201 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6202 return EMULATE_FAIL;
6203
a2b9e6c1 6204 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6205 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6206 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6207 vcpu->run->internal.ndata = 0;
1f4dcb3b 6208 r = EMULATE_USER_EXIT;
fc3a9157 6209 }
e2366171 6210
6d77dbfc 6211 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6212
6213 return r;
6d77dbfc
GN		 6214}
6215
93c05d3e 6216static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6217 bool write_fault_to_shadow_pgtable,
6218 int emulation_type)
a6f177ef 6219{
95b3cf69 6220 gpa_t gpa = cr2;
ba049e93 6221 kvm_pfn_t pfn;
a6f177ef 6222
384bf221 6223 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6224 return false;
6225
6c3dfeb6
SC		 6226 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6227 return false;
6228
44dd3ffa 6229 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6230 /*
6231 * Write permission should be allowed since only
6232 * write access need to be emulated.
6233 */
6234 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6235
95b3cf69
XG		 6236 /*
6237 * If the mapping is invalid in guest, let cpu retry
6238 * it to generate fault.
6239 */
6240 if (gpa == UNMAPPED_GVA)
6241 return true;
6242 }
a6f177ef 6243
8e3d9d06
XG		 6244 /*
6245 * Do not retry the unhandleable instruction if it faults on the
6246 * readonly host memory, otherwise it will goto a infinite loop:
6247 * retry instruction -> write #PF -> emulation fail -> retry
6248 * instruction -> ...
6249 */
6250 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6251
6252 /*
6253 * If the instruction failed on the error pfn, it can not be fixed,
6254 * report the error to userspace.
6255 */
6256 if (is_error_noslot_pfn(pfn))
6257 return false;
6258
6259 kvm_release_pfn_clean(pfn);
6260
6261 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6262 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6263 unsigned int indirect_shadow_pages;
6264
6265 spin_lock(&vcpu->kvm->mmu_lock);
6266 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6267 spin_unlock(&vcpu->kvm->mmu_lock);
6268
6269 if (indirect_shadow_pages)
6270 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6271
a6f177ef 6272 return true;
8e3d9d06 6273 }
a6f177ef 6274
95b3cf69
XG		 6275 /*
6276 * if emulation was due to access to shadowed page table
6277 * and it failed try to unshadow page and re-enter the
6278 * guest to let CPU execute the instruction.
6279 */
6280 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6281
6282 /*
6283 * If the access faults on its page table, it can not
6284 * be fixed by unprotecting shadow page and it should
6285 * be reported to userspace.
6286 */
6287 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6288}
6289
1cb3f3ae
XG		 6290static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6291 unsigned long cr2, int emulation_type)
6292{
6293 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6294 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6295
6296 last_retry_eip = vcpu->arch.last_retry_eip;
6297 last_retry_addr = vcpu->arch.last_retry_addr;
6298
6299 /*
6300 * If the emulation is caused by #PF and it is non-page_table
6301 * writing instruction, it means the VM-EXIT is caused by shadow
6302 * page protected, we can zap the shadow page and retry this
6303 * instruction directly.
6304 *
6305 * Note: if the guest uses a non-page-table modifying instruction
6306 * on the PDE that points to the instruction, then we will unmap
6307 * the instruction and go to an infinite loop. So, we cache the
6308 * last retried eip and the last fault address, if we meet the eip
6309 * and the address again, we can break out of the potential infinite
6310 * loop.
6311 */
6312 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6313
384bf221 6314 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6315 return false;
6316
6c3dfeb6
SC		 6317 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6318 return false;
6319
1cb3f3ae
XG		 6320 if (x86_page_table_writing_insn(ctxt))
6321 return false;
6322
6323 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6324 return false;
6325
6326 vcpu->arch.last_retry_eip = ctxt->eip;
6327 vcpu->arch.last_retry_addr = cr2;
6328
44dd3ffa 6329 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6330 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6331
22368028 6332 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6333
6334 return true;
6335}
6336
716d51ab
GN		 6337static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6338static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6339
64d60670 6340static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6341{
64d60670 6342 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6343 /* This is a good place to trace that we are exiting SMM. */
6344 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6345
c43203ca
PB		 6346 /* Process a latched INIT or SMI, if any. */
6347 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6348 }
699023e2
PB		 6349
6350 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6351}
6352
4a1e10d5
PB		 6353static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6354 unsigned long *db)
6355{
6356 u32 dr6 = 0;
6357 int i;
6358 u32 enable, rwlen;
6359
6360 enable = dr7;
6361 rwlen = dr7 >> 16;
6362 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6363 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6364 dr6 |= (1 << i);
6365 return dr6;
6366}
6367
c8401dda 6368static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6369{
6370 struct kvm_run *kvm_run = vcpu->run;
6371
c8401dda
PB		 6372 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6373 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6374 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6375 kvm_run->debug.arch.exception = DB_VECTOR;
6376 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6377 *r = EMULATE_USER_EXIT;
6378 } else {
f10c729f 6379 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6380 }
6381}
6382
6affcbed
KH		 6383int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6384{
6385 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6386 int r = EMULATE_DONE;
6387
6388 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6389
6390 /*
6391 * rflags is the old, "raw" value of the flags. The new value has
6392 * not been saved yet.
6393 *
6394 * This is correct even for TF set by the guest, because "the
6395 * processor will not generate this exception after the instruction
6396 * that sets the TF flag".
6397 */
6398 if (unlikely(rflags & X86_EFLAGS_TF))
6399 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6400 return r == EMULATE_DONE;
6401}
6402EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6403
4a1e10d5
PB		 6404static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6405{
4a1e10d5
PB		 6406 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6407 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6408 struct kvm_run *kvm_run = vcpu->run;
6409 unsigned long eip = kvm_get_linear_rip(vcpu);
6410 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6411 vcpu->arch.guest_debug_dr7,
6412 vcpu->arch.eff_db);
6413
6414 if (dr6 != 0) {
6f43ed01 6415 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6416 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6417 kvm_run->debug.arch.exception = DB_VECTOR;
6418 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6419 *r = EMULATE_USER_EXIT;
6420 return true;
6421 }
6422 }
6423
4161a569
NA		 6424 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6425 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6426 unsigned long eip = kvm_get_linear_rip(vcpu);
6427 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6428 vcpu->arch.dr7,
6429 vcpu->arch.db);
6430
6431 if (dr6 != 0) {
1fc5d194 6432 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 6433 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6434 kvm_queue_exception(vcpu, DB_VECTOR);
6435 *r = EMULATE_DONE;
6436 return true;
6437 }
6438 }
6439
6440 return false;
6441}
6442
04789b66
LA		 6443static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6444{
2d7921c4
AM		 6445 switch (ctxt->opcode_len) {
6446 case 1:
6447 switch (ctxt->b) {
6448 case 0xe4: /* IN */
6449 case 0xe5:
6450 case 0xec:
6451 case 0xed:
6452 case 0xe6: /* OUT */
6453 case 0xe7:
6454 case 0xee:
6455 case 0xef:
6456 case 0x6c: /* INS */
6457 case 0x6d:
6458 case 0x6e: /* OUTS */
6459 case 0x6f:
6460 return true;
6461 }
6462 break;
6463 case 2:
6464 switch (ctxt->b) {
6465 case 0x33: /* RDPMC */
6466 return true;
6467 }
6468 break;
04789b66
LA		 6469 }
6470
6471 return false;
6472}
6473
51d8b661
AP		 6474int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6475 unsigned long cr2,
dc25e89e
AP		 6476 int emulation_type,
6477 void *insn,
6478 int insn_len)
bbd9b64e 6479{
95cb2295 6480 int r;
9d74191a 6481 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6482 bool writeback = true;
93c05d3e 6483 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6484
c595ceee
PB		 6485 vcpu->arch.l1tf_flush_l1d = true;
6486
93c05d3e
XG		 6487 /*
6488 * Clear write_fault_to_shadow_pgtable here to ensure it is
6489 * never reused.
6490 */
6491 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6492 kvm_clear_exception_queue(vcpu);
8d7d8102 6493
571008da 6494 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6495 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6496
6497 /*
6498 * We will reenter on the same instruction since
6499 * we do not set complete_userspace_io. This does not
6500 * handle watchpoints yet, those would be handled in
6501 * the emulate_ops.
6502 */
d391f120
VK		 6503 if (!(emulation_type & EMULTYPE_SKIP) &&
6504 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6505 return r;
6506
9d74191a
TY		 6507 ctxt->interruptibility = 0;
6508 ctxt->have_exception = false;
e0ad0b47 6509 ctxt->exception.vector = -1;
9d74191a 6510 ctxt->perm_ok = false;
bbd9b64e 6511
b51e974f 6512 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6513
9d74191a 6514 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6515
e46479f8 6516 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6517 ++vcpu->stat.insn_emulation;
1d2887e2 6518 if (r != EMULATION_OK) {
4005996e
AK		 6519 if (emulation_type & EMULTYPE_TRAP_UD)
6520 return EMULATE_FAIL;
991eebf9
GN		 6521 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6522 emulation_type))
bbd9b64e 6523 return EMULATE_DONE;
6ea6e843
PB		 6524 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6525 return EMULATE_DONE;
6d77dbfc
GN		 6526 if (emulation_type & EMULTYPE_SKIP)
6527 return EMULATE_FAIL;
e2366171 6528 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6529 }
6530 }
6531
04789b66
LA		 6532 if ((emulation_type & EMULTYPE_VMWARE) &&
6533 !is_vmware_backdoor_opcode(ctxt))
6534 return EMULATE_FAIL;
6535
ba8afb6b 6536 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6537 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6538 if (ctxt->eflags & X86_EFLAGS_RF)
6539 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6540 return EMULATE_DONE;
6541 }
6542
1cb3f3ae
XG		 6543 if (retry_instruction(ctxt, cr2, emulation_type))
6544 return EMULATE_DONE;
6545
7ae441ea 6546 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6547 changes registers values during IO operation */
7ae441ea
GN		 6548 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6549 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6550 emulator_invalidate_register_cache(ctxt);
7ae441ea 6551 }
4d2179e1 6552
5cd21917 6553restart:
0f89b207
TL		 6554 /* Save the faulting GPA (cr2) in the address field */
6555 ctxt->exception.address = cr2;
6556
9d74191a 6557 r = x86_emulate_insn(ctxt);
bbd9b64e 6558
775fde86
JR		 6559 if (r == EMULATION_INTERCEPTED)
6560 return EMULATE_DONE;
6561
d2ddd1c4 6562 if (r == EMULATION_FAILED) {
991eebf9
GN		 6563 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6564 emulation_type))
c3cd7ffa
GN		 6565 return EMULATE_DONE;
6566
e2366171 6567 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6568 }
6569
9d74191a 6570 if (ctxt->have_exception) {
d2ddd1c4 6571 r = EMULATE_DONE;
ef54bcfe
PB		 6572 if (inject_emulated_exception(vcpu))
6573 return r;
d2ddd1c4 6574 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6575 if (!vcpu->arch.pio.in) {
6576 /* FIXME: return into emulator if single-stepping. */
3457e419 6577 vcpu->arch.pio.count = 0;
0912c977 6578 } else {
7ae441ea 6579 writeback = false;
716d51ab
GN		 6580 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6581 }
ac0a48c3 6582 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6583 } else if (vcpu->mmio_needed) {
6584 if (!vcpu->mmio_is_write)
6585 writeback = false;
ac0a48c3 6586 r = EMULATE_USER_EXIT;
716d51ab 6587 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6588 } else if (r == EMULATION_RESTART)
5cd21917 6589 goto restart;
d2ddd1c4
GN		 6590 else
6591 r = EMULATE_DONE;
f850e2e6 6592
7ae441ea 6593 if (writeback) {
6addfc42 6594 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6595 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6596 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6597 kvm_rip_write(vcpu, ctxt->eip);
5cc244a2 6598 if (r == EMULATE_DONE && ctxt->tf)
c8401dda 6599 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6600 if (!ctxt->have_exception ||
6601 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6602 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6603
6604 /*
6605 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6606 * do nothing, and it will be requested again as soon as
6607 * the shadow expires. But we still need to check here,
6608 * because POPF has no interrupt shadow.
6609 */
6610 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6611 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6612 } else
6613 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6614
6615 return r;
de7d789a 6616}
c60658d1
SC		 6617
6618int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6619{
6620 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6621}
6622EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6623
6624int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6625 void *insn, int insn_len)
6626{
6627 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6628}
6629EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6630
8764ed55
SC		 6631static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6632{
6633 vcpu->arch.pio.count = 0;
6634 return 1;
6635}
6636
45def77e
SC		 6637static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6638{
6639 vcpu->arch.pio.count = 0;
6640
6641 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6642 return 1;
6643
6644 return kvm_skip_emulated_instruction(vcpu);
6645}
6646
dca7f128
SC		 6647static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6648 unsigned short port)
de7d789a 6649{
de3cd117 6650 unsigned long val = kvm_rax_read(vcpu);
ca1d4a9e
AK		 6651 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6652 size, port, &val, 1);
8764ed55
SC		 6653 if (ret)
6654 return ret;
45def77e 6655
8764ed55
SC		 6656 /*
6657 * Workaround userspace that relies on old KVM behavior of %rip being
6658 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6659 */
6660 if (port == 0x7e &&
6661 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6662 vcpu->arch.complete_userspace_io =
6663 complete_fast_pio_out_port_0x7e;
6664 kvm_skip_emulated_instruction(vcpu);
6665 } else {
45def77e
SC		 6666 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6667 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6668 }
8764ed55 6669 return 0;
de7d789a 6670}
de7d789a 6671
8370c3d0
TL		 6672static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6673{
6674 unsigned long val;
6675
6676 /* We should only ever be called with arch.pio.count equal to 1 */
6677 BUG_ON(vcpu->arch.pio.count != 1);
6678
45def77e
SC		 6679 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6680 vcpu->arch.pio.count = 0;
6681 return 1;
6682 }
6683
8370c3d0 6684 /* For size less than 4 we merge, else we zero extend */
de3cd117 6685 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6686
6687 /*
6688 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6689 * the copy and tracing
6690 */
6691 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6692 vcpu->arch.pio.port, &val, 1);
de3cd117 6693 kvm_rax_write(vcpu, val);
8370c3d0 6694
45def77e 6695 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6696}
6697
dca7f128
SC		 6698static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6699 unsigned short port)
8370c3d0
TL		 6700{
6701 unsigned long val;
6702 int ret;
6703
6704 /* For size less than 4 we merge, else we zero extend */
de3cd117 6705 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6706
6707 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6708 &val, 1);
6709 if (ret) {
de3cd117 6710 kvm_rax_write(vcpu, val);
8370c3d0
TL		 6711 return ret;
6712 }
6713
45def77e 6714 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6715 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6716
6717 return 0;
6718}
dca7f128
SC		 6719
6720int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6721{
45def77e 6722 int ret;
dca7f128 6723
dca7f128 6724 if (in)
45def77e 6725 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6726 else
45def77e
SC		 6727 ret = kvm_fast_pio_out(vcpu, size, port);
6728 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 6729}
6730EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6731
251a5fd6 6732static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6733{
0a3aee0d 6734 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6735 return 0;
8cfdc000
ZA		 6736}
6737
6738static void tsc_khz_changed(void *data)
c8076604 6739{
8cfdc000
ZA		 6740 struct cpufreq_freqs *freq = data;
6741 unsigned long khz = 0;
6742
6743 if (data)
6744 khz = freq->new;
6745 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6746 khz = cpufreq_quick_get(raw_smp_processor_id());
6747 if (!khz)
6748 khz = tsc_khz;
0a3aee0d 6749 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6750}
6751
5fa4ec9c 6752#ifdef CONFIG_X86_64
0092e434
VK		 6753static void kvm_hyperv_tsc_notifier(void)
6754{
0092e434
VK		 6755 struct kvm *kvm;
6756 struct kvm_vcpu *vcpu;
6757 int cpu;
6758
0d9ce162 6759 mutex_lock(&kvm_lock);
0092e434
VK		 6760 list_for_each_entry(kvm, &vm_list, vm_list)
6761 kvm_make_mclock_inprogress_request(kvm);
6762
6763 hyperv_stop_tsc_emulation();
6764
6765 /* TSC frequency always matches when on Hyper-V */
6766 for_each_present_cpu(cpu)
6767 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6768 kvm_max_guest_tsc_khz = tsc_khz;
6769
6770 list_for_each_entry(kvm, &vm_list, vm_list) {
6771 struct kvm_arch *ka = &kvm->arch;
6772
6773 spin_lock(&ka->pvclock_gtod_sync_lock);
6774
6775 pvclock_update_vm_gtod_copy(kvm);
6776
6777 kvm_for_each_vcpu(cpu, vcpu, kvm)
6778 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6779
6780 kvm_for_each_vcpu(cpu, vcpu, kvm)
6781 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6782
6783 spin_unlock(&ka->pvclock_gtod_sync_lock);
6784 }
0d9ce162 6785 mutex_unlock(&kvm_lock);
0092e434 6786}
5fa4ec9c 6787#endif
0092e434 6788
df24014a 6789static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
c8076604 6790{
c8076604
GH		 6791 struct kvm *kvm;
6792 struct kvm_vcpu *vcpu;
6793 int i, send_ipi = 0;
6794
8cfdc000
ZA		 6795 /*
6796 * We allow guests to temporarily run on slowing clocks,
6797 * provided we notify them after, or to run on accelerating
6798 * clocks, provided we notify them before. Thus time never
6799 * goes backwards.
6800 *
6801 * However, we have a problem. We can't atomically update
6802 * the frequency of a given CPU from this function; it is
6803 * merely a notifier, which can be called from any CPU.
6804 * Changing the TSC frequency at arbitrary points in time
6805 * requires a recomputation of local variables related to
6806 * the TSC for each VCPU. We must flag these local variables
6807 * to be updated and be sure the update takes place with the
6808 * new frequency before any guests proceed.
6809 *
6810 * Unfortunately, the combination of hotplug CPU and frequency
6811 * change creates an intractable locking scenario; the order
6812 * of when these callouts happen is undefined with respect to
6813 * CPU hotplug, and they can race with each other. As such,
6814 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6815 * undefined; you can actually have a CPU frequency change take
6816 * place in between the computation of X and the setting of the
6817 * variable. To protect against this problem, all updates of
6818 * the per_cpu tsc_khz variable are done in an interrupt
6819 * protected IPI, and all callers wishing to update the value
6820 * must wait for a synchronous IPI to complete (which is trivial
6821 * if the caller is on the CPU already). This establishes the
6822 * necessary total order on variable updates.
6823 *
6824 * Note that because a guest time update may take place
6825 * anytime after the setting of the VCPU's request bit, the
6826 * correct TSC value must be set before the request. However,
6827 * to ensure the update actually makes it to any guest which
6828 * starts running in hardware virtualization between the set
6829 * and the acquisition of the spinlock, we must also ping the
6830 * CPU after setting the request bit.
6831 *
6832 */
6833
df24014a 6834 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6835
0d9ce162 6836 mutex_lock(&kvm_lock);
c8076604 6837 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6838 kvm_for_each_vcpu(i, vcpu, kvm) {
df24014a 6839 if (vcpu->cpu != cpu)
c8076604 6840 continue;
c285545f 6841 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0d9ce162 6842 if (vcpu->cpu != raw_smp_processor_id())
8cfdc000 6843 send_ipi = 1;
c8076604
GH		 6844 }
6845 }
0d9ce162 6846 mutex_unlock(&kvm_lock);
c8076604
GH		 6847
6848 if (freq->old < freq->new && send_ipi) {
6849 /*
6850 * We upscale the frequency. Must make the guest
6851 * doesn't see old kvmclock values while running with
6852 * the new frequency, otherwise we risk the guest sees
6853 * time go backwards.
6854 *
6855 * In case we update the frequency for another cpu
6856 * (which might be in guest context) send an interrupt
6857 * to kick the cpu out of guest context. Next time
6858 * guest context is entered kvmclock will be updated,
6859 * so the guest will not see stale values.
6860 */
df24014a 6861 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6862 }
df24014a
VK		 6863}
6864
6865static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6866 void *data)
6867{
6868 struct cpufreq_freqs *freq = data;
6869 int cpu;
6870
6871 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6872 return 0;
6873 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6874 return 0;
6875
6876 for_each_cpu(cpu, freq->policy->cpus)
6877 __kvmclock_cpufreq_notifier(freq, cpu);
6878
c8076604
GH		 6879 return 0;
6880}
6881
6882static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6883 .notifier_call = kvmclock_cpufreq_notifier
6884};
6885
251a5fd6 6886static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6887{
251a5fd6
SAS		 6888 tsc_khz_changed(NULL);
6889 return 0;
8cfdc000
ZA		 6890}
6891
b820cc0c
ZA		 6892static void kvm_timer_init(void)
6893{
c285545f 6894 max_tsc_khz = tsc_khz;
460dd42e 6895
b820cc0c 6896 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6897#ifdef CONFIG_CPU_FREQ
6898 struct cpufreq_policy policy;
758f588d
BP		 6899 int cpu;
6900
c285545f 6901 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6902 cpu = get_cpu();
6903 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6904 if (policy.cpuinfo.max_freq)
6905 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6906 put_cpu();
c285545f 6907#endif
b820cc0c
ZA		 6908 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6909 CPUFREQ_TRANSITION_NOTIFIER);
6910 }
460dd42e 6911
73c1b41e 6912 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6913 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6914}
6915
dd60d217
AK		 6916DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6917EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6918
f5132b01 6919int kvm_is_in_guest(void)
ff9d07a0 6920{
086c9855 6921 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6922}
6923
6924static int kvm_is_user_mode(void)
6925{
6926 int user_mode = 3;
dcf46b94 6927
086c9855
AS		 6928 if (__this_cpu_read(current_vcpu))
6929 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6930
ff9d07a0
ZY		 6931 return user_mode != 0;
6932}
6933
6934static unsigned long kvm_get_guest_ip(void)
6935{
6936 unsigned long ip = 0;
dcf46b94 6937
086c9855
AS		 6938 if (__this_cpu_read(current_vcpu))
6939 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6940
ff9d07a0
ZY		 6941 return ip;
6942}
6943
8479e04e
LK		 6944static void kvm_handle_intel_pt_intr(void)
6945{
6946 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6947
6948 kvm_make_request(KVM_REQ_PMI, vcpu);
6949 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6950 (unsigned long *)&vcpu->arch.pmu.global_status);
6951}
6952
ff9d07a0
ZY		 6953static struct perf_guest_info_callbacks kvm_guest_cbs = {
6954 .is_in_guest = kvm_is_in_guest,
6955 .is_user_mode = kvm_is_user_mode,
6956 .get_guest_ip = kvm_get_guest_ip,
8479e04e 6957 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
ff9d07a0
ZY		 6958};
6959
16e8d74d
MT		 6960#ifdef CONFIG_X86_64
6961static void pvclock_gtod_update_fn(struct work_struct *work)
6962{
d828199e
MT		 6963 struct kvm *kvm;
6964
6965 struct kvm_vcpu *vcpu;
6966 int i;
6967
0d9ce162 6968 mutex_lock(&kvm_lock);
d828199e
MT		 6969 list_for_each_entry(kvm, &vm_list, vm_list)
6970 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6971 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6972 atomic_set(&kvm_guest_has_master_clock, 0);
0d9ce162 6973 mutex_unlock(&kvm_lock);
16e8d74d
MT		 6974}
6975
6976static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6977
6978/*
6979 * Notification about pvclock gtod data update.
6980 */
6981static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6982 void *priv)
6983{
6984 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6985 struct timekeeper *tk = priv;
6986
6987 update_pvclock_gtod(tk);
6988
6989 /* disable master clock if host does not trust, or does not
b0c39dc6 6990 * use, TSC based clocksource.
16e8d74d 6991 */
b0c39dc6 6992 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6993 atomic_read(&kvm_guest_has_master_clock) != 0)
6994 queue_work(system_long_wq, &pvclock_gtod_work);
6995
6996 return 0;
6997}
6998
6999static struct notifier_block pvclock_gtod_notifier = {
7000 .notifier_call = pvclock_gtod_notify,
7001};
7002#endif
7003
f8c16bba 7004int kvm_arch_init(void *opaque)
043405e1 7005{
b820cc0c 7006 int r;
6b61edf7 7007 struct kvm_x86_ops *ops = opaque;
f8c16bba 7008
f8c16bba
ZX		 7009 if (kvm_x86_ops) {
7010 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 7011 r = -EEXIST;
7012 goto out;
f8c16bba
ZX		 7013 }
7014
7015 if (!ops->cpu_has_kvm_support()) {
7016 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 7017 r = -EOPNOTSUPP;
7018 goto out;
f8c16bba
ZX		 7019 }
7020 if (ops->disabled_by_bios()) {
7021 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 7022 r = -EOPNOTSUPP;
7023 goto out;
f8c16bba
ZX		 7024 }
7025
b666a4b6
MO		 7026 /*
7027 * KVM explicitly assumes that the guest has an FPU and
7028 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7029 * vCPU's FPU state as a fxregs_state struct.
7030 */
7031 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7032 printk(KERN_ERR "kvm: inadequate fpu\n");
7033 r = -EOPNOTSUPP;
7034 goto out;
7035 }
7036
013f6a5d 7037 r = -ENOMEM;
ed8e4812 7038 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 7039 __alignof__(struct fpu), SLAB_ACCOUNT,
7040 NULL);
7041 if (!x86_fpu_cache) {
7042 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7043 goto out;
7044 }
7045
013f6a5d
MT		 7046 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7047 if (!shared_msrs) {
7048 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 7049 goto out_free_x86_fpu_cache;
013f6a5d
MT		 7050 }
7051
97db56ce
AK		 7052 r = kvm_mmu_module_init();
7053 if (r)
013f6a5d 7054 goto out_free_percpu;
97db56ce 7055
f8c16bba 7056 kvm_x86_ops = ops;
920c8377 7057
7b52345e 7058 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 7059 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 7060 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 7061 kvm_timer_init();
c8076604 7062
ff9d07a0
ZY		 7063 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7064
d366bf7e 7065 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 7066 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7067
c5cc421b 7068 kvm_lapic_init();
0c5f81da
WL		 7069 if (pi_inject_timer == -1)
7070 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
16e8d74d
MT		 7071#ifdef CONFIG_X86_64
7072 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 7073
5fa4ec9c 7074 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 7075 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 7076#endif
7077
f8c16bba 7078 return 0;
56c6d28a 7079
013f6a5d
MT		 7080out_free_percpu:
7081 free_percpu(shared_msrs);
b666a4b6
MO		 7082out_free_x86_fpu_cache:
7083 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7084out:
56c6d28a 7085 return r;
043405e1 7086}
8776e519 7087
f8c16bba
ZX		 7088void kvm_arch_exit(void)
7089{
0092e434 7090#ifdef CONFIG_X86_64
5fa4ec9c 7091 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 7092 clear_hv_tscchange_cb();
7093#endif
cef84c30 7094 kvm_lapic_exit();
ff9d07a0
ZY		 7095 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7096
888d256e
JK		 7097 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7098 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7099 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7100 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7101#ifdef CONFIG_X86_64
7102 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7103#endif
f8c16bba 7104 kvm_x86_ops = NULL;
56c6d28a 7105 kvm_mmu_module_exit();
013f6a5d 7106 free_percpu(shared_msrs);
b666a4b6 7107 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7108}
f8c16bba 7109
5cb56059 7110int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7111{
7112 ++vcpu->stat.halt_exits;
35754c98 7113 if (lapic_in_kernel(vcpu)) {
a4535290 7114 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7115 return 1;
7116 } else {
7117 vcpu->run->exit_reason = KVM_EXIT_HLT;
7118 return 0;
7119 }
7120}
5cb56059
JS		 7121EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7122
7123int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7124{
6affcbed
KH		 7125 int ret = kvm_skip_emulated_instruction(vcpu);
7126 /*
7127 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7128 * KVM_EXIT_DEBUG here.
7129 */
7130 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7131}
8776e519
HB		 7132EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7133
8ef81a9a 7134#ifdef CONFIG_X86_64
55dd00a7
MT		 7135static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7136 unsigned long clock_type)
7137{
7138 struct kvm_clock_pairing clock_pairing;
899a31f5 7139 struct timespec64 ts;
80fbd89c 7140 u64 cycle;
55dd00a7
MT		 7141 int ret;
7142
7143 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7144 return -KVM_EOPNOTSUPP;
7145
7146 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7147 return -KVM_EOPNOTSUPP;
7148
7149 clock_pairing.sec = ts.tv_sec;
7150 clock_pairing.nsec = ts.tv_nsec;
7151 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7152 clock_pairing.flags = 0;
bcbfbd8e 7153 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7154
7155 ret = 0;
7156 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7157 sizeof(struct kvm_clock_pairing)))
7158 ret = -KVM_EFAULT;
7159
7160 return ret;
7161}
8ef81a9a 7162#endif
55dd00a7 7163
6aef266c
SV		 7164/*
7165 * kvm_pv_kick_cpu_op: Kick a vcpu.
7166 *
7167 * @apicid - apicid of vcpu to be kicked.
7168 */
7169static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7170{
24d2166b 7171 struct kvm_lapic_irq lapic_irq;
6aef266c 7172
24d2166b
R		 7173 lapic_irq.shorthand = 0;
7174 lapic_irq.dest_mode = 0;
ebd28fcb 7175 lapic_irq.level = 0;
24d2166b 7176 lapic_irq.dest_id = apicid;
93bbf0b8 7177 lapic_irq.msi_redir_hint = false;
6aef266c 7178
24d2166b 7179 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7180 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7181}
7182
d62caabb
AS		 7183void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7184{
f7589cca
PB		 7185 if (!lapic_in_kernel(vcpu)) {
7186 WARN_ON_ONCE(vcpu->arch.apicv_active);
7187 return;
7188 }
7189 if (!vcpu->arch.apicv_active)
7190 return;
7191
d62caabb
AS		 7192 vcpu->arch.apicv_active = false;
7193 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7194}
7195
71506297
WL		 7196static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7197{
7198 struct kvm_vcpu *target = NULL;
7199 struct kvm_apic_map *map;
7200
7201 rcu_read_lock();
7202 map = rcu_dereference(kvm->arch.apic_map);
7203
7204 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7205 target = map->phys_map[dest_id]->vcpu;
7206
7207 rcu_read_unlock();
7208
7209 if (target)
7210 kvm_vcpu_yield_to(target);
7211}
7212
8776e519
HB		 7213int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7214{
7215 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7216 int op_64_bit;
8776e519 7217
696ca779
RK		 7218 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7219 return kvm_hv_hypercall(vcpu);
55cd8e5a 7220
de3cd117
SC		 7221 nr = kvm_rax_read(vcpu);
7222 a0 = kvm_rbx_read(vcpu);
7223 a1 = kvm_rcx_read(vcpu);
7224 a2 = kvm_rdx_read(vcpu);
7225 a3 = kvm_rsi_read(vcpu);
8776e519 7226
229456fc 7227 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7228
a449c7aa
NA		 7229 op_64_bit = is_64_bit_mode(vcpu);
7230 if (!op_64_bit) {
8776e519
HB		 7231 nr &= 0xFFFFFFFF;
7232 a0 &= 0xFFFFFFFF;
7233 a1 &= 0xFFFFFFFF;
7234 a2 &= 0xFFFFFFFF;
7235 a3 &= 0xFFFFFFFF;
7236 }
7237
07708c4a
JK		 7238 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7239 ret = -KVM_EPERM;
696ca779 7240 goto out;
07708c4a
JK		 7241 }
7242
8776e519 7243 switch (nr) {
b93463aa
AK		 7244 case KVM_HC_VAPIC_POLL_IRQ:
7245 ret = 0;
7246 break;
6aef266c
SV		 7247 case KVM_HC_KICK_CPU:
7248 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7249 ret = 0;
7250 break;
8ef81a9a 7251#ifdef CONFIG_X86_64
55dd00a7
MT		 7252 case KVM_HC_CLOCK_PAIRING:
7253 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7254 break;
1ed199a4 7255#endif
4180bf1b
WL		 7256 case KVM_HC_SEND_IPI:
7257 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7258 break;
71506297
WL		 7259 case KVM_HC_SCHED_YIELD:
7260 kvm_sched_yield(vcpu->kvm, a0);
7261 ret = 0;
7262 break;
8776e519
HB		 7263 default:
7264 ret = -KVM_ENOSYS;
7265 break;
7266 }
696ca779 7267out:
a449c7aa
NA		 7268 if (!op_64_bit)
7269 ret = (u32)ret;
de3cd117 7270 kvm_rax_write(vcpu, ret);
6356ee0c 7271
f11c3a8d 7272 ++vcpu->stat.hypercalls;
6356ee0c 7273 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7274}
7275EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7276
b6785def 7277static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7278{
d6aa1000 7279 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7280 char instruction[3];
5fdbf976 7281 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7282
8776e519 7283 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7284
ce2e852e
DV		 7285 return emulator_write_emulated(ctxt, rip, instruction, 3,
7286 &ctxt->exception);
8776e519
HB		 7287}
7288
851ba692 7289static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7290{
782d422b
MG		 7291 return vcpu->run->request_interrupt_window &&
7292 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7293}
7294
851ba692 7295static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7296{
851ba692
AK		 7297 struct kvm_run *kvm_run = vcpu->run;
7298
91586a3b 7299 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7300 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7301 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7302 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7303 kvm_run->ready_for_interrupt_injection =
7304 pic_in_kernel(vcpu->kvm) ||
782d422b 7305 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7306}
7307
95ba8273
GN		 7308static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7309{
7310 int max_irr, tpr;
7311
7312 if (!kvm_x86_ops->update_cr8_intercept)
7313 return;
7314
bce87cce 7315 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7316 return;
7317
d62caabb
AS		 7318 if (vcpu->arch.apicv_active)
7319 return;
7320
8db3baa2
GN		 7321 if (!vcpu->arch.apic->vapic_addr)
7322 max_irr = kvm_lapic_find_highest_irr(vcpu);
7323 else
7324 max_irr = -1;
95ba8273
GN		 7325
7326 if (max_irr != -1)
7327 max_irr >>= 4;
7328
7329 tpr = kvm_lapic_get_cr8(vcpu);
7330
7331 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7332}
7333
b6b8a145 7334static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7335{
b6b8a145
JK		 7336 int r;
7337
95ba8273 7338 /* try to reinject previous events if any */
664f8e26 7339
1a680e35
LA		 7340 if (vcpu->arch.exception.injected)
7341 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7342 /*
a042c26f
LA		 7343 * Do not inject an NMI or interrupt if there is a pending
7344 * exception. Exceptions and interrupts are recognized at
7345 * instruction boundaries, i.e. the start of an instruction.
7346 * Trap-like exceptions, e.g. #DB, have higher priority than
7347 * NMIs and interrupts, i.e. traps are recognized before an
7348 * NMI/interrupt that's pending on the same instruction.
7349 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7350 * priority, but are only generated (pended) during instruction
7351 * execution, i.e. a pending fault-like exception means the
7352 * fault occurred on the *previous* instruction and must be
7353 * serviced prior to recognizing any new events in order to
7354 * fully complete the previous instruction.
664f8e26 7355 */
1a680e35
LA		 7356 else if (!vcpu->arch.exception.pending) {
7357 if (vcpu->arch.nmi_injected)
664f8e26 7358 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7359 else if (vcpu->arch.interrupt.injected)
664f8e26 7360 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7361 }
7362
1a680e35
LA		 7363 /*
7364 * Call check_nested_events() even if we reinjected a previous event
7365 * in order for caller to determine if it should require immediate-exit
7366 * from L2 to L1 due to pending L1 events which require exit
7367 * from L2 to L1.
7368 */
664f8e26
WL		 7369 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7370 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7371 if (r != 0)
7372 return r;
7373 }
7374
7375 /* try to inject new event if pending */
b59bb7bd 7376 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7377 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7378 vcpu->arch.exception.has_error_code,
7379 vcpu->arch.exception.error_code);
d6e8c854 7380
1a680e35 7381 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7382 vcpu->arch.exception.pending = false;
7383 vcpu->arch.exception.injected = true;
7384
d6e8c854
NA		 7385 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7386 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7387 X86_EFLAGS_RF);
7388
f10c729f
JM		 7389 if (vcpu->arch.exception.nr == DB_VECTOR) {
7390 /*
7391 * This code assumes that nSVM doesn't use
7392 * check_nested_events(). If it does, the
7393 * DR6/DR7 changes should happen before L1
7394 * gets a #VMEXIT for an intercepted #DB in
7395 * L2. (Under VMX, on the other hand, the
7396 * DR6/DR7 changes should not happen in the
7397 * event of a VM-exit to L1 for an intercepted
7398 * #DB in L2.)
7399 */
7400 kvm_deliver_exception_payload(vcpu);
7401 if (vcpu->arch.dr7 & DR7_GD) {
7402 vcpu->arch.dr7 &= ~DR7_GD;
7403 kvm_update_dr7(vcpu);
7404 }
6bdf0662
NA		 7405 }
7406
cfcd20e5 7407 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7408 }
7409
7410 /* Don't consider new event if we re-injected an event */
7411 if (kvm_event_needs_reinjection(vcpu))
7412 return 0;
7413
7414 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7415 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7416 vcpu->arch.smi_pending = false;
52797bf9 7417 ++vcpu->arch.smi_count;
ee2cd4b7 7418 enter_smm(vcpu);
c43203ca 7419 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7420 --vcpu->arch.nmi_pending;
7421 vcpu->arch.nmi_injected = true;
7422 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7423 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7424 /*
7425 * Because interrupts can be injected asynchronously, we are
7426 * calling check_nested_events again here to avoid a race condition.
7427 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7428 * proposal and current concerns. Perhaps we should be setting
7429 * KVM_REQ_EVENT only on certain events and not unconditionally?
7430 */
7431 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7432 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7433 if (r != 0)
7434 return r;
7435 }
95ba8273 7436 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7437 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7438 false);
7439 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7440 }
7441 }
ee2cd4b7 7442
b6b8a145 7443 return 0;
95ba8273
GN		 7444}
7445
7460fb4a
AK		 7446static void process_nmi(struct kvm_vcpu *vcpu)
7447{
7448 unsigned limit = 2;
7449
7450 /*
7451 * x86 is limited to one NMI running, and one NMI pending after it.
7452 * If an NMI is already in progress, limit further NMIs to just one.
7453 * Otherwise, allow two (and we'll inject the first one immediately).
7454 */
7455 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7456 limit = 1;
7457
7458 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7459 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7460 kvm_make_request(KVM_REQ_EVENT, vcpu);
7461}
7462
ee2cd4b7 7463static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7464{
7465 u32 flags = 0;
7466 flags |= seg->g << 23;
7467 flags |= seg->db << 22;
7468 flags |= seg->l << 21;
7469 flags |= seg->avl << 20;
7470 flags |= seg->present << 15;
7471 flags |= seg->dpl << 13;
7472 flags |= seg->s << 12;
7473 flags |= seg->type << 8;
7474 return flags;
7475}
7476
ee2cd4b7 7477static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7478{
7479 struct kvm_segment seg;
7480 int offset;
7481
7482 kvm_get_segment(vcpu, &seg, n);
7483 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7484
7485 if (n < 3)
7486 offset = 0x7f84 + n * 12;
7487 else
7488 offset = 0x7f2c + (n - 3) * 12;
7489
7490 put_smstate(u32, buf, offset + 8, seg.base);
7491 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7492 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7493}
7494
efbb288a 7495#ifdef CONFIG_X86_64
ee2cd4b7 7496static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7497{
7498 struct kvm_segment seg;
7499 int offset;
7500 u16 flags;
7501
7502 kvm_get_segment(vcpu, &seg, n);
7503 offset = 0x7e00 + n * 16;
7504
ee2cd4b7 7505 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7506 put_smstate(u16, buf, offset, seg.selector);
7507 put_smstate(u16, buf, offset + 2, flags);
7508 put_smstate(u32, buf, offset + 4, seg.limit);
7509 put_smstate(u64, buf, offset + 8, seg.base);
7510}
efbb288a 7511#endif
660a5d51 7512
ee2cd4b7 7513static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7514{
7515 struct desc_ptr dt;
7516 struct kvm_segment seg;
7517 unsigned long val;
7518 int i;
7519
7520 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7521 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7522 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7523 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7524
7525 for (i = 0; i < 8; i++)
7526 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7527
7528 kvm_get_dr(vcpu, 6, &val);
7529 put_smstate(u32, buf, 0x7fcc, (u32)val);
7530 kvm_get_dr(vcpu, 7, &val);
7531 put_smstate(u32, buf, 0x7fc8, (u32)val);
7532
7533 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7534 put_smstate(u32, buf, 0x7fc4, seg.selector);
7535 put_smstate(u32, buf, 0x7f64, seg.base);
7536 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7537 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7538
7539 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7540 put_smstate(u32, buf, 0x7fc0, seg.selector);
7541 put_smstate(u32, buf, 0x7f80, seg.base);
7542 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7543 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7544
7545 kvm_x86_ops->get_gdt(vcpu, &dt);
7546 put_smstate(u32, buf, 0x7f74, dt.address);
7547 put_smstate(u32, buf, 0x7f70, dt.size);
7548
7549 kvm_x86_ops->get_idt(vcpu, &dt);
7550 put_smstate(u32, buf, 0x7f58, dt.address);
7551 put_smstate(u32, buf, 0x7f54, dt.size);
7552
7553 for (i = 0; i < 6; i++)
ee2cd4b7 7554 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7555
7556 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7557
7558 /* revision id */
7559 put_smstate(u32, buf, 0x7efc, 0x00020000);
7560 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7561}
7562
b68f3cc7 7563#ifdef CONFIG_X86_64
ee2cd4b7 7564static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7565{
660a5d51
PB		 7566 struct desc_ptr dt;
7567 struct kvm_segment seg;
7568 unsigned long val;
7569 int i;
7570
7571 for (i = 0; i < 16; i++)
7572 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7573
7574 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7575 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7576
7577 kvm_get_dr(vcpu, 6, &val);
7578 put_smstate(u64, buf, 0x7f68, val);
7579 kvm_get_dr(vcpu, 7, &val);
7580 put_smstate(u64, buf, 0x7f60, val);
7581
7582 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7583 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7584 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7585
7586 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7587
7588 /* revision id */
7589 put_smstate(u32, buf, 0x7efc, 0x00020064);
7590
7591 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7592
7593 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7594 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7595 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7596 put_smstate(u32, buf, 0x7e94, seg.limit);
7597 put_smstate(u64, buf, 0x7e98, seg.base);
7598
7599 kvm_x86_ops->get_idt(vcpu, &dt);
7600 put_smstate(u32, buf, 0x7e84, dt.size);
7601 put_smstate(u64, buf, 0x7e88, dt.address);
7602
7603 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7604 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7605 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7606 put_smstate(u32, buf, 0x7e74, seg.limit);
7607 put_smstate(u64, buf, 0x7e78, seg.base);
7608
7609 kvm_x86_ops->get_gdt(vcpu, &dt);
7610 put_smstate(u32, buf, 0x7e64, dt.size);
7611 put_smstate(u64, buf, 0x7e68, dt.address);
7612
7613 for (i = 0; i < 6; i++)
ee2cd4b7 7614 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7615}
b68f3cc7 7616#endif
660a5d51 7617
ee2cd4b7 7618static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7619{
660a5d51 7620 struct kvm_segment cs, ds;
18c3626e 7621 struct desc_ptr dt;
660a5d51
PB		 7622 char buf[512];
7623 u32 cr0;
7624
660a5d51 7625 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7626 memset(buf, 0, 512);
b68f3cc7 7627#ifdef CONFIG_X86_64
d6321d49 7628 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7629 enter_smm_save_state_64(vcpu, buf);
660a5d51 7630 else
b68f3cc7 7631#endif
ee2cd4b7 7632 enter_smm_save_state_32(vcpu, buf);
660a5d51 7633
0234bf88
LP		 7634 /*
7635 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7636 * vCPU state (e.g. leave guest mode) after we've saved the state into
7637 * the SMM state-save area.
7638 */
7639 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7640
7641 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7642 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7643
7644 if (kvm_x86_ops->get_nmi_mask(vcpu))
7645 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7646 else
7647 kvm_x86_ops->set_nmi_mask(vcpu, true);
7648
7649 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7650 kvm_rip_write(vcpu, 0x8000);
7651
7652 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7653 kvm_x86_ops->set_cr0(vcpu, cr0);
7654 vcpu->arch.cr0 = cr0;
7655
7656 kvm_x86_ops->set_cr4(vcpu, 0);
7657
18c3626e
PB		 7658 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7659 dt.address = dt.size = 0;
7660 kvm_x86_ops->set_idt(vcpu, &dt);
7661
660a5d51
PB		 7662 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7663
7664 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7665 cs.base = vcpu->arch.smbase;
7666
7667 ds.selector = 0;
7668 ds.base = 0;
7669
7670 cs.limit = ds.limit = 0xffffffff;
7671 cs.type = ds.type = 0x3;
7672 cs.dpl = ds.dpl = 0;
7673 cs.db = ds.db = 0;
7674 cs.s = ds.s = 1;
7675 cs.l = ds.l = 0;
7676 cs.g = ds.g = 1;
7677 cs.avl = ds.avl = 0;
7678 cs.present = ds.present = 1;
7679 cs.unusable = ds.unusable = 0;
7680 cs.padding = ds.padding = 0;
7681
7682 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7683 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7684 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7685 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7686 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7687 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7688
b68f3cc7 7689#ifdef CONFIG_X86_64
d6321d49 7690 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7691 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7692#endif
660a5d51
PB		 7693
7694 kvm_update_cpuid(vcpu);
7695 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7696}
7697
ee2cd4b7 7698static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7699{
7700 vcpu->arch.smi_pending = true;
7701 kvm_make_request(KVM_REQ_EVENT, vcpu);
7702}
7703
2860c4b1
PB		 7704void kvm_make_scan_ioapic_request(struct kvm *kvm)
7705{
7706 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7707}
7708
3d81bc7e 7709static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7710{
dcbd3e49 7711 if (!kvm_apic_present(vcpu))
3d81bc7e 7712 return;
c7c9c56c 7713
6308630b 7714 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7715
b053b2ae 7716 if (irqchip_split(vcpu->kvm))
6308630b 7717 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7718 else {
fa59cc00 7719 if (vcpu->arch.apicv_active)
d62caabb 7720 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7721 if (ioapic_in_kernel(vcpu->kvm))
7722 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7723 }
e40ff1d6
LA		 7724
7725 if (is_guest_mode(vcpu))
7726 vcpu->arch.load_eoi_exitmap_pending = true;
7727 else
7728 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7729}
7730
7731static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7732{
7733 u64 eoi_exit_bitmap[4];
7734
7735 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7736 return;
7737
5c919412
AS		 7738 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7739 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7740 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7741}
7742
93065ac7
MH		 7743int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7744 unsigned long start, unsigned long end,
7745 bool blockable)
b1394e74
RK		 7746{
7747 unsigned long apic_address;
7748
7749 /*
7750 * The physical address of apic access page is stored in the VMCS.
7751 * Update it when it becomes invalid.
7752 */
7753 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7754 if (start <= apic_address && apic_address < end)
7755 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7756
7757 return 0;
b1394e74
RK		 7758}
7759
4256f43f
TC		 7760void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7761{
c24ae0dc
TC		 7762 struct page *page = NULL;
7763
35754c98 7764 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7765 return;
7766
4256f43f
TC		 7767 if (!kvm_x86_ops->set_apic_access_page_addr)
7768 return;
7769
c24ae0dc 7770 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7771 if (is_error_page(page))
7772 return;
c24ae0dc
TC		 7773 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7774
7775 /*
7776 * Do not pin apic access page in memory, the MMU notifier
7777 * will call us again if it is migrated or swapped out.
7778 */
7779 put_page(page);
4256f43f
TC		 7780}
7781EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7782
d264ee0c
SC		 7783void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7784{
7785 smp_send_reschedule(vcpu->cpu);
7786}
7787EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7788
9357d939 7789/*
362c698f 7790 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7791 * exiting to the userspace. Otherwise, the value will be returned to the
7792 * userspace.
7793 */
851ba692 7794static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7795{
7796 int r;
62a193ed
MG		 7797 bool req_int_win =
7798 dm_request_for_irq_injection(vcpu) &&
7799 kvm_cpu_accept_dm_intr(vcpu);
7800
730dca42 7801 bool req_immediate_exit = false;
b6c7a5dc 7802
2fa6e1e1 7803 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7804 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7805 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7806 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7807 kvm_mmu_unload(vcpu);
a8eeb04a 7808 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7809 __kvm_migrate_timers(vcpu);
d828199e
MT		 7810 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7811 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7812 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7813 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7814 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7815 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7816 if (unlikely(r))
7817 goto out;
7818 }
a8eeb04a 7819 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7820 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7821 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7822 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7823 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7824 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7825 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7826 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7827 r = 0;
7828 goto out;
7829 }
a8eeb04a 7830 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7831 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7832 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7833 r = 0;
7834 goto out;
7835 }
af585b92
GN		 7836 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7837 /* Page is swapped out. Do synthetic halt */
7838 vcpu->arch.apf.halted = true;
7839 r = 1;
7840 goto out;
7841 }
c9aaa895
GC		 7842 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7843 record_steal_time(vcpu);
64d60670
PB		 7844 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7845 process_smi(vcpu);
7460fb4a
AK		 7846 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7847 process_nmi(vcpu);
f5132b01 7848 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7849 kvm_pmu_handle_event(vcpu);
f5132b01 7850 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7851 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7852 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7853 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7854 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7855 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7856 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7857 vcpu->run->eoi.vector =
7858 vcpu->arch.pending_ioapic_eoi;
7859 r = 0;
7860 goto out;
7861 }
7862 }
3d81bc7e
YZ		 7863 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7864 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7865 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7866 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7867 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7868 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7869 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7870 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7871 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7872 r = 0;
7873 goto out;
7874 }
e516cebb
AS		 7875 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7876 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7877 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7878 r = 0;
7879 goto out;
7880 }
db397571
AS		 7881 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7882 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7883 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7884 r = 0;
7885 goto out;
7886 }
f3b138c5
AS		 7887
7888 /*
7889 * KVM_REQ_HV_STIMER has to be processed after
7890 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7891 * depend on the guest clock being up-to-date
7892 */
1f4b34f8
AS		 7893 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7894 kvm_hv_process_stimers(vcpu);
2f52d58c 7895 }
b93463aa 7896
b463a6f7 7897 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7898 ++vcpu->stat.req_event;
66450a21
JK		 7899 kvm_apic_accept_events(vcpu);
7900 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7901 r = 1;
7902 goto out;
7903 }
7904
b6b8a145
JK		 7905 if (inject_pending_event(vcpu, req_int_win) != 0)
7906 req_immediate_exit = true;
321c5658 7907 else {
cc3d967f 7908 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7909 *
cc3d967f
LP		 7910 * SMIs have three cases:
7911 * 1) They can be nested, and then there is nothing to
7912 * do here because RSM will cause a vmexit anyway.
7913 * 2) There is an ISA-specific reason why SMI cannot be
7914 * injected, and the moment when this changes can be
7915 * intercepted.
7916 * 3) Or the SMI can be pending because
7917 * inject_pending_event has completed the injection
7918 * of an IRQ or NMI from the previous vmexit, and
7919 * then we request an immediate exit to inject the
7920 * SMI.
c43203ca
PB		 7921 */
7922 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7923 if (!kvm_x86_ops->enable_smi_window(vcpu))
7924 req_immediate_exit = true;
321c5658
YS		 7925 if (vcpu->arch.nmi_pending)
7926 kvm_x86_ops->enable_nmi_window(vcpu);
7927 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7928 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7929 WARN_ON(vcpu->arch.exception.pending);
321c5658 7930 }
b463a6f7
AK		 7931
7932 if (kvm_lapic_enabled(vcpu)) {
7933 update_cr8_intercept(vcpu);
7934 kvm_lapic_sync_to_vapic(vcpu);
7935 }
7936 }
7937
d8368af8
AK		 7938 r = kvm_mmu_reload(vcpu);
7939 if (unlikely(r)) {
d905c069 7940 goto cancel_injection;
d8368af8
AK		 7941 }
7942
b6c7a5dc
HB		 7943 preempt_disable();
7944
7945 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7946
7947 /*
7948 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7949 * IPI are then delayed after guest entry, which ensures that they
7950 * result in virtual interrupt delivery.
7951 */
7952 local_irq_disable();
6b7e2d09
XG		 7953 vcpu->mode = IN_GUEST_MODE;
7954
01b71917
MT		 7955 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7956
0f127d12 7957 /*
b95234c8 7958 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7959 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 7960 *
81b01667 7961 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 7962 * pairs with the memory barrier implicit in pi_test_and_set_on
7963 * (see vmx_deliver_posted_interrupt).
7964 *
7965 * 3) This also orders the write to mode from any reads to the page
7966 * tables done while the VCPU is running. Please see the comment
7967 * in kvm_flush_remote_tlbs.
6b7e2d09 7968 */
01b71917 7969 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7970
b95234c8
PB		 7971 /*
7972 * This handles the case where a posted interrupt was
7973 * notified with kvm_vcpu_kick.
7974 */
fa59cc00
LA		 7975 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7976 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7977
2fa6e1e1 7978 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7979 || need_resched() || signal_pending(current)) {
6b7e2d09 7980 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7981 smp_wmb();
6c142801
AK		 7982 local_irq_enable();
7983 preempt_enable();
01b71917 7984 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7985 r = 1;
d905c069 7986 goto cancel_injection;
6c142801
AK		 7987 }
7988
c43203ca
PB		 7989 if (req_immediate_exit) {
7990 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7991 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7992 }
d6185f20 7993
8b89fe1f 7994 trace_kvm_entry(vcpu->vcpu_id);
6edaa530 7995 guest_enter_irqoff();
b6c7a5dc 7996
e7517324
WL		 7997 /* The preempt notifier should have taken care of the FPU already. */
7998 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
5f409e20 7999
42dbaa5a 8000 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 8001 set_debugreg(0, 7);
8002 set_debugreg(vcpu->arch.eff_db[0], 0);
8003 set_debugreg(vcpu->arch.eff_db[1], 1);
8004 set_debugreg(vcpu->arch.eff_db[2], 2);
8005 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 8006 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 8007 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 8008 }
b6c7a5dc 8009
851ba692 8010 kvm_x86_ops->run(vcpu);
b6c7a5dc 8011
c77fb5fe
PB		 8012 /*
8013 * Do this here before restoring debug registers on the host. And
8014 * since we do this before handling the vmexit, a DR access vmexit
8015 * can (a) read the correct value of the debug registers, (b) set
8016 * KVM_DEBUGREG_WONT_EXIT again.
8017 */
8018 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 8019 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8020 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 8021 kvm_update_dr0123(vcpu);
8022 kvm_update_dr6(vcpu);
8023 kvm_update_dr7(vcpu);
8024 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 8025 }
8026
24f1e32c
FW		 8027 /*
8028 * If the guest has used debug registers, at least dr7
8029 * will be disabled while returning to the host.
8030 * If we don't have active breakpoints in the host, we don't
8031 * care about the messed up debug address registers. But if
8032 * we have some of them active, restore the old state.
8033 */
59d8eb53 8034 if (hw_breakpoint_active())
24f1e32c 8035 hw_breakpoint_restore();
42dbaa5a 8036
4ba76538 8037 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 8038
6b7e2d09 8039 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8040 smp_wmb();
a547c6db 8041
95b5a48c 8042 kvm_x86_ops->handle_exit_irqoff(vcpu);
b6c7a5dc 8043
d7a08882
SC		 8044 /*
8045 * Consume any pending interrupts, including the possible source of
8046 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8047 * An instruction is required after local_irq_enable() to fully unblock
8048 * interrupts on processors that implement an interrupt shadow, the
8049 * stat.exits increment will do nicely.
8050 */
8051 kvm_before_interrupt(vcpu);
8052 local_irq_enable();
b6c7a5dc 8053 ++vcpu->stat.exits;
d7a08882
SC		 8054 local_irq_disable();
8055 kvm_after_interrupt(vcpu);
b6c7a5dc 8056
f2485b3e 8057 guest_exit_irqoff();
ec0671d5
WL		 8058 if (lapic_in_kernel(vcpu)) {
8059 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8060 if (delta != S64_MIN) {
8061 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8062 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8063 }
8064 }
b6c7a5dc 8065
f2485b3e 8066 local_irq_enable();
b6c7a5dc
HB		 8067 preempt_enable();
8068
f656ce01 8069 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 8070
b6c7a5dc
HB		 8071 /*
8072 * Profile KVM exit RIPs:
8073 */
8074 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 8075 unsigned long rip = kvm_rip_read(vcpu);
8076 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 8077 }
8078
cc578287
ZA		 8079 if (unlikely(vcpu->arch.tsc_always_catchup))
8080 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 8081
5cfb1d5a
MT		 8082 if (vcpu->arch.apic_attention)
8083 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 8084
618232e2 8085 vcpu->arch.gpa_available = false;
851ba692 8086 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 8087 return r;
8088
8089cancel_injection:
8090 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 8091 if (unlikely(vcpu->arch.apic_attention))
8092 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 8093out:
8094 return r;
8095}
b6c7a5dc 8096
362c698f
PB		 8097static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8098{
bf9f6ac8
FW		 8099 if (!kvm_arch_vcpu_runnable(vcpu) &&
8100 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 8101 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8102 kvm_vcpu_block(vcpu);
8103 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 8104
8105 if (kvm_x86_ops->post_block)
8106 kvm_x86_ops->post_block(vcpu);
8107
9c8fd1ba
PB		 8108 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8109 return 1;
8110 }
362c698f
PB		 8111
8112 kvm_apic_accept_events(vcpu);
8113 switch(vcpu->arch.mp_state) {
8114 case KVM_MP_STATE_HALTED:
8115 vcpu->arch.pv.pv_unhalted = false;
8116 vcpu->arch.mp_state =
8117 KVM_MP_STATE_RUNNABLE;
b2869f28 8118 /* fall through */
362c698f
PB		 8119 case KVM_MP_STATE_RUNNABLE:
8120 vcpu->arch.apf.halted = false;
8121 break;
8122 case KVM_MP_STATE_INIT_RECEIVED:
8123 break;
8124 default:
8125 return -EINTR;
8126 break;
8127 }
8128 return 1;
8129}
09cec754 8130
5d9bc648
PB		 8131static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8132{
0ad3bed6
PB		 8133 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8134 kvm_x86_ops->check_nested_events(vcpu, false);
8135
5d9bc648
PB		 8136 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8137 !vcpu->arch.apf.halted);
8138}
8139
362c698f 8140static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8141{
8142 int r;
f656ce01 8143 struct kvm *kvm = vcpu->kvm;
d7690175 8144
f656ce01 8145 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8146 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8147
362c698f 8148 for (;;) {
58f800d5 8149 if (kvm_vcpu_running(vcpu)) {
851ba692 8150 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8151 } else {
362c698f 8152 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8153 }
8154
09cec754
GN		 8155 if (r <= 0)
8156 break;
8157
72875d8a 8158 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8159 if (kvm_cpu_has_pending_timer(vcpu))
8160 kvm_inject_pending_timer_irqs(vcpu);
8161
782d422b
MG		 8162 if (dm_request_for_irq_injection(vcpu) &&
8163 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8164 r = 0;
8165 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8166 ++vcpu->stat.request_irq_exits;
362c698f 8167 break;
09cec754 8168 }
af585b92
GN		 8169
8170 kvm_check_async_pf_completion(vcpu);
8171
09cec754
GN		 8172 if (signal_pending(current)) {
8173 r = -EINTR;
851ba692 8174 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8175 ++vcpu->stat.signal_exits;
362c698f 8176 break;
09cec754
GN		 8177 }
8178 if (need_resched()) {
f656ce01 8179 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8180 cond_resched();
f656ce01 8181 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8182 }
b6c7a5dc
HB		 8183 }
8184
f656ce01 8185 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8186
8187 return r;
8188}
8189
716d51ab
GN		 8190static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8191{
8192 int r;
8193 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8194 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 8195 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8196 if (r != EMULATE_DONE)
8197 return 0;
8198 return 1;
8199}
8200
8201static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8202{
8203 BUG_ON(!vcpu->arch.pio.count);
8204
8205 return complete_emulated_io(vcpu);
8206}
8207
f78146b0
AK		 8208/*
8209 * Implements the following, as a state machine:
8210 *
8211 * read:
8212 * for each fragment
87da7e66
XG		 8213 * for each mmio piece in the fragment
8214 * write gpa, len
8215 * exit
8216 * copy data
f78146b0
AK		 8217 * execute insn
8218 *
8219 * write:
8220 * for each fragment
87da7e66
XG		 8221 * for each mmio piece in the fragment
8222 * write gpa, len
8223 * copy data
8224 * exit
f78146b0 8225 */
716d51ab 8226static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8227{
8228 struct kvm_run *run = vcpu->run;
f78146b0 8229 struct kvm_mmio_fragment *frag;
87da7e66 8230 unsigned len;
5287f194 8231
716d51ab 8232 BUG_ON(!vcpu->mmio_needed);
5287f194 8233
716d51ab 8234 /* Complete previous fragment */
87da7e66
XG		 8235 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8236 len = min(8u, frag->len);
716d51ab 8237 if (!vcpu->mmio_is_write)
87da7e66
XG		 8238 memcpy(frag->data, run->mmio.data, len);
8239
8240 if (frag->len <= 8) {
8241 /* Switch to the next fragment. */
8242 frag++;
8243 vcpu->mmio_cur_fragment++;
8244 } else {
8245 /* Go forward to the next mmio piece. */
8246 frag->data += len;
8247 frag->gpa += len;
8248 frag->len -= len;
8249 }
8250
a08d3b3b 8251 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8252 vcpu->mmio_needed = 0;
0912c977
PB		 8253
8254 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8255 if (vcpu->mmio_is_write)
716d51ab
GN		 8256 return 1;
8257 vcpu->mmio_read_completed = 1;
8258 return complete_emulated_io(vcpu);
8259 }
87da7e66 8260
716d51ab
GN		 8261 run->exit_reason = KVM_EXIT_MMIO;
8262 run->mmio.phys_addr = frag->gpa;
8263 if (vcpu->mmio_is_write)
87da7e66
XG		 8264 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8265 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8266 run->mmio.is_write = vcpu->mmio_is_write;
8267 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8268 return 0;
5287f194
AK		 8269}
8270
822f312d
SAS		 8271/* Swap (qemu) user FPU context for the guest FPU context. */
8272static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8273{
5f409e20
RR		 8274 fpregs_lock();
8275
d9a710e5 8276 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
822f312d 8277 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8278 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d 8279 ~XFEATURE_MASK_PKRU);
5f409e20
RR		 8280
8281 fpregs_mark_activate();
8282 fpregs_unlock();
8283
822f312d
SAS		 8284 trace_kvm_fpu(1);
8285}
8286
8287/* When vcpu_run ends, restore user space FPU context. */
8288static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8289{
5f409e20
RR		 8290 fpregs_lock();
8291
b666a4b6 8292 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
d9a710e5 8293 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
5f409e20
RR		 8294
8295 fpregs_mark_activate();
8296 fpregs_unlock();
8297
822f312d
SAS		 8298 ++vcpu->stat.fpu_reload;
8299 trace_kvm_fpu(0);
8300}
8301
b6c7a5dc
HB		 8302int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8303{
8304 int r;
b6c7a5dc 8305
accb757d 8306 vcpu_load(vcpu);
20b7035c 8307 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8308 kvm_load_guest_fpu(vcpu);
8309
a4535290 8310 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8311 if (kvm_run->immediate_exit) {
8312 r = -EINTR;
8313 goto out;
8314 }
b6c7a5dc 8315 kvm_vcpu_block(vcpu);
66450a21 8316 kvm_apic_accept_events(vcpu);
72875d8a 8317 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8318 r = -EAGAIN;
a0595000
JS		 8319 if (signal_pending(current)) {
8320 r = -EINTR;
8321 vcpu->run->exit_reason = KVM_EXIT_INTR;
8322 ++vcpu->stat.signal_exits;
8323 }
ac9f6dc0 8324 goto out;
b6c7a5dc
HB		 8325 }
8326
01643c51
KH		 8327 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8328 r = -EINVAL;
8329 goto out;
8330 }
8331
8332 if (vcpu->run->kvm_dirty_regs) {
8333 r = sync_regs(vcpu);
8334 if (r != 0)
8335 goto out;
8336 }
8337
b6c7a5dc 8338 /* re-sync apic's tpr */
35754c98 8339 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8340 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8341 r = -EINVAL;
8342 goto out;
8343 }
8344 }
b6c7a5dc 8345
716d51ab
GN		 8346 if (unlikely(vcpu->arch.complete_userspace_io)) {
8347 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8348 vcpu->arch.complete_userspace_io = NULL;
8349 r = cui(vcpu);
8350 if (r <= 0)
5663d8f9 8351 goto out;
716d51ab
GN		 8352 } else
8353 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8354
460df4c1
PB		 8355 if (kvm_run->immediate_exit)
8356 r = -EINTR;
8357 else
8358 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8359
8360out:
5663d8f9 8361 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8362 if (vcpu->run->kvm_valid_regs)
8363 store_regs(vcpu);
f1d86e46 8364 post_kvm_run_save(vcpu);
20b7035c 8365 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8366
accb757d 8367 vcpu_put(vcpu);
b6c7a5dc
HB		 8368 return r;
8369}
8370
01643c51 8371static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8372{
7ae441ea
GN		 8373 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8374 /*
8375 * We are here if userspace calls get_regs() in the middle of
8376 * instruction emulation. Registers state needs to be copied
4a969980 8377 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8378 * that usually, but some bad designed PV devices (vmware
8379 * backdoor interface) need this to work
8380 */
dd856efa 8381 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8382 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8383 }
de3cd117
SC		 8384 regs->rax = kvm_rax_read(vcpu);
8385 regs->rbx = kvm_rbx_read(vcpu);
8386 regs->rcx = kvm_rcx_read(vcpu);
8387 regs->rdx = kvm_rdx_read(vcpu);
8388 regs->rsi = kvm_rsi_read(vcpu);
8389 regs->rdi = kvm_rdi_read(vcpu);
e9c16c78 8390 regs->rsp = kvm_rsp_read(vcpu);
de3cd117 8391 regs->rbp = kvm_rbp_read(vcpu);
b6c7a5dc 8392#ifdef CONFIG_X86_64
de3cd117
SC		 8393 regs->r8 = kvm_r8_read(vcpu);
8394 regs->r9 = kvm_r9_read(vcpu);
8395 regs->r10 = kvm_r10_read(vcpu);
8396 regs->r11 = kvm_r11_read(vcpu);
8397 regs->r12 = kvm_r12_read(vcpu);
8398 regs->r13 = kvm_r13_read(vcpu);
8399 regs->r14 = kvm_r14_read(vcpu);
8400 regs->r15 = kvm_r15_read(vcpu);
b6c7a5dc
HB		 8401#endif
8402
5fdbf976 8403 regs->rip = kvm_rip_read(vcpu);
91586a3b 8404 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8405}
b6c7a5dc 8406
01643c51
KH		 8407int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8408{
8409 vcpu_load(vcpu);
8410 __get_regs(vcpu, regs);
1fc9b76b 8411 vcpu_put(vcpu);
b6c7a5dc
HB		 8412 return 0;
8413}
8414
01643c51 8415static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8416{
7ae441ea
GN		 8417 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8418 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8419
de3cd117
SC		 8420 kvm_rax_write(vcpu, regs->rax);
8421 kvm_rbx_write(vcpu, regs->rbx);
8422 kvm_rcx_write(vcpu, regs->rcx);
8423 kvm_rdx_write(vcpu, regs->rdx);
8424 kvm_rsi_write(vcpu, regs->rsi);
8425 kvm_rdi_write(vcpu, regs->rdi);
e9c16c78 8426 kvm_rsp_write(vcpu, regs->rsp);
de3cd117 8427 kvm_rbp_write(vcpu, regs->rbp);
b6c7a5dc 8428#ifdef CONFIG_X86_64
de3cd117
SC		 8429 kvm_r8_write(vcpu, regs->r8);
8430 kvm_r9_write(vcpu, regs->r9);
8431 kvm_r10_write(vcpu, regs->r10);
8432 kvm_r11_write(vcpu, regs->r11);
8433 kvm_r12_write(vcpu, regs->r12);
8434 kvm_r13_write(vcpu, regs->r13);
8435 kvm_r14_write(vcpu, regs->r14);
8436 kvm_r15_write(vcpu, regs->r15);
b6c7a5dc
HB		 8437#endif
8438
5fdbf976 8439 kvm_rip_write(vcpu, regs->rip);
d73235d1 8440 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8441
b4f14abd
JK		 8442 vcpu->arch.exception.pending = false;
8443
3842d135 8444 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8445}
3842d135 8446
01643c51
KH		 8447int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8448{
8449 vcpu_load(vcpu);
8450 __set_regs(vcpu, regs);
875656fe 8451 vcpu_put(vcpu);
b6c7a5dc
HB		 8452 return 0;
8453}
8454
b6c7a5dc
HB		 8455void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8456{
8457 struct kvm_segment cs;
8458
3e6e0aab 8459 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8460 *db = cs.db;
8461 *l = cs.l;
8462}
8463EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8464
01643c51 8465static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8466{
89a27f4d 8467 struct desc_ptr dt;
b6c7a5dc 8468
3e6e0aab
GT		 8469 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8470 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8471 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8472 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8473 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8474 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8475
3e6e0aab
GT		 8476 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8477 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8478
8479 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8480 sregs->idt.limit = dt.size;
8481 sregs->idt.base = dt.address;
b6c7a5dc 8482 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8483 sregs->gdt.limit = dt.size;
8484 sregs->gdt.base = dt.address;
b6c7a5dc 8485
4d4ec087 8486 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8487 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8488 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8489 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8490 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8491 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8492 sregs->apic_base = kvm_get_apic_base(vcpu);
8493
0e96f31e 8494 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8495
04140b41 8496 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8497 set_bit(vcpu->arch.interrupt.nr,
8498 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8499}
16d7a191 8500
01643c51
KH		 8501int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8502 struct kvm_sregs *sregs)
8503{
8504 vcpu_load(vcpu);
8505 __get_sregs(vcpu, sregs);
bcdec41c 8506 vcpu_put(vcpu);
b6c7a5dc
HB		 8507 return 0;
8508}
8509
62d9f0db
MT		 8510int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8511 struct kvm_mp_state *mp_state)
8512{
fd232561
CD		 8513 vcpu_load(vcpu);
8514
66450a21 8515 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8516 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8517 vcpu->arch.pv.pv_unhalted)
8518 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8519 else
8520 mp_state->mp_state = vcpu->arch.mp_state;
8521
fd232561 8522 vcpu_put(vcpu);
62d9f0db
MT		 8523 return 0;
8524}
8525
8526int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8527 struct kvm_mp_state *mp_state)
8528{
e83dff5e
CD		 8529 int ret = -EINVAL;
8530
8531 vcpu_load(vcpu);
8532
bce87cce 8533 if (!lapic_in_kernel(vcpu) &&
66450a21 8534 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8535 goto out;
66450a21 8536
28bf2888
DH		 8537 /* INITs are latched while in SMM */
8538 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8539 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8540 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8541 goto out;
28bf2888 8542
66450a21
JK		 8543 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8544 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8545 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8546 } else
8547 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8548 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8549
8550 ret = 0;
8551out:
8552 vcpu_put(vcpu);
8553 return ret;
62d9f0db
MT		 8554}
8555
7f3d35fd
KW		 8556int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8557 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8558{
9d74191a 8559 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8560 int ret;
e01c2426 8561
8ec4722d 8562 init_emulate_ctxt(vcpu);
c697518a 8563
7f3d35fd 8564 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8565 has_error_code, error_code);
c697518a 8566
c697518a 8567 if (ret)
19d04437 8568 return EMULATE_FAIL;
37817f29 8569
9d74191a
TY		 8570 kvm_rip_write(vcpu, ctxt->eip);
8571 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8572 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8573 return EMULATE_DONE;
37817f29
IE		 8574}
8575EXPORT_SYMBOL_GPL(kvm_task_switch);
8576
3140c156 8577static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8578{
74fec5b9
TL		 8579 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8580 (sregs->cr4 & X86_CR4_OSXSAVE))
8581 return -EINVAL;
8582
37b95951 8583 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8584 /*
8585 * When EFER.LME and CR0.PG are set, the processor is in
8586 * 64-bit mode (though maybe in a 32-bit code segment).
8587 * CR4.PAE and EFER.LMA must be set.
8588 */
37b95951 8589 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8590 || !(sregs->efer & EFER_LMA))
8591 return -EINVAL;
8592 } else {
8593 /*
8594 * Not in 64-bit mode: EFER.LMA is clear and the code
8595 * segment cannot be 64-bit.
8596 */
8597 if (sregs->efer & EFER_LMA || sregs->cs.l)
8598 return -EINVAL;
8599 }
8600
8601 return 0;
8602}
8603
01643c51 8604static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8605{
58cb628d 8606 struct msr_data apic_base_msr;
b6c7a5dc 8607 int mmu_reset_needed = 0;
c4d21882 8608 int cpuid_update_needed = 0;
63f42e02 8609 int pending_vec, max_bits, idx;
89a27f4d 8610 struct desc_ptr dt;
b4ef9d4e
CD		 8611 int ret = -EINVAL;
8612
f2981033 8613 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8614 goto out;
f2981033 8615
d3802286
JM		 8616 apic_base_msr.data = sregs->apic_base;
8617 apic_base_msr.host_initiated = true;
8618 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8619 goto out;
6d1068b3 8620
89a27f4d
GN		 8621 dt.size = sregs->idt.limit;
8622 dt.address = sregs->idt.base;
b6c7a5dc 8623 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8624 dt.size = sregs->gdt.limit;
8625 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8626 kvm_x86_ops->set_gdt(vcpu, &dt);
8627
ad312c7c 8628 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8629 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8630 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8631 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8632
2d3ad1f4 8633 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8634
f6801dff 8635 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8636 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8637
4d4ec087 8638 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8639 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8640 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8641
fc78f519 8642 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8643 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8644 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8645 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8646 if (cpuid_update_needed)
00b27a3e 8647 kvm_update_cpuid(vcpu);
63f42e02
XG		 8648
8649 idx = srcu_read_lock(&vcpu->kvm->srcu);
bf03d4f9 8650 if (is_pae_paging(vcpu)) {
9f8fe504 8651 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8652 mmu_reset_needed = 1;
8653 }
63f42e02 8654 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8655
8656 if (mmu_reset_needed)
8657 kvm_mmu_reset_context(vcpu);
8658
a50abc3b 8659 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8660 pending_vec = find_first_bit(
8661 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8662 if (pending_vec < max_bits) {
66fd3f7f 8663 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8664 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8665 }
8666
3e6e0aab
GT		 8667 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8668 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8669 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8670 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8671 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8672 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8673
3e6e0aab
GT		 8674 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8675 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8676
5f0269f5
ME		 8677 update_cr8_intercept(vcpu);
8678
9c3e4aab 8679 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8680 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8681 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8682 !is_protmode(vcpu))
9c3e4aab
MT		 8683 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8684
3842d135
AK		 8685 kvm_make_request(KVM_REQ_EVENT, vcpu);
8686
b4ef9d4e
CD		 8687 ret = 0;
8688out:
01643c51
KH		 8689 return ret;
8690}
8691
8692int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8693 struct kvm_sregs *sregs)
8694{
8695 int ret;
8696
8697 vcpu_load(vcpu);
8698 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8699 vcpu_put(vcpu);
8700 return ret;
b6c7a5dc
HB		 8701}
8702
d0bfb940
JK		 8703int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8704 struct kvm_guest_debug *dbg)
b6c7a5dc 8705{
355be0b9 8706 unsigned long rflags;
ae675ef0 8707 int i, r;
b6c7a5dc 8708
66b56562
CD		 8709 vcpu_load(vcpu);
8710
4f926bf2
JK		 8711 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8712 r = -EBUSY;
8713 if (vcpu->arch.exception.pending)
2122ff5e 8714 goto out;
4f926bf2
JK		 8715 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8716 kvm_queue_exception(vcpu, DB_VECTOR);
8717 else
8718 kvm_queue_exception(vcpu, BP_VECTOR);
8719 }
8720
91586a3b
JK		 8721 /*
8722 * Read rflags as long as potentially injected trace flags are still
8723 * filtered out.
8724 */
8725 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8726
8727 vcpu->guest_debug = dbg->control;
8728 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8729 vcpu->guest_debug = 0;
8730
8731 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8732 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8733 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8734 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8735 } else {
8736 for (i = 0; i < KVM_NR_DB_REGS; i++)
8737 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8738 }
c8639010 8739 kvm_update_dr7(vcpu);
ae675ef0 8740
f92653ee
JK		 8741 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8742 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8743 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8744
91586a3b
JK		 8745 /*
8746 * Trigger an rflags update that will inject or remove the trace
8747 * flags.
8748 */
8749 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8750
a96036b8 8751 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8752
4f926bf2 8753 r = 0;
d0bfb940 8754
2122ff5e 8755out:
66b56562 8756 vcpu_put(vcpu);
b6c7a5dc
HB		 8757 return r;
8758}
8759
8b006791
ZX		 8760/*
8761 * Translate a guest virtual address to a guest physical address.
8762 */
8763int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8764 struct kvm_translation *tr)
8765{
8766 unsigned long vaddr = tr->linear_address;
8767 gpa_t gpa;
f656ce01 8768 int idx;
8b006791 8769
1da5b61d
CD		 8770 vcpu_load(vcpu);
8771
f656ce01 8772 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8773 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8774 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8775 tr->physical_address = gpa;
8776 tr->valid = gpa != UNMAPPED_GVA;
8777 tr->writeable = 1;
8778 tr->usermode = 0;
8b006791 8779
1da5b61d 8780 vcpu_put(vcpu);
8b006791
ZX		 8781 return 0;
8782}
8783
d0752060
HB		 8784int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8785{
1393123e 8786 struct fxregs_state *fxsave;
d0752060 8787
1393123e 8788 vcpu_load(vcpu);
d0752060 8789
b666a4b6 8790 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8791 memcpy(fpu->fpr, fxsave->st_space, 128);
8792 fpu->fcw = fxsave->cwd;
8793 fpu->fsw = fxsave->swd;
8794 fpu->ftwx = fxsave->twd;
8795 fpu->last_opcode = fxsave->fop;
8796 fpu->last_ip = fxsave->rip;
8797 fpu->last_dp = fxsave->rdp;
0e96f31e 8798 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8799
1393123e 8800 vcpu_put(vcpu);
d0752060
HB		 8801 return 0;
8802}
8803
8804int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8805{
6a96bc7f
CD		 8806 struct fxregs_state *fxsave;
8807
8808 vcpu_load(vcpu);
8809
b666a4b6 8810 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8811
d0752060
HB		 8812 memcpy(fxsave->st_space, fpu->fpr, 128);
8813 fxsave->cwd = fpu->fcw;
8814 fxsave->swd = fpu->fsw;
8815 fxsave->twd = fpu->ftwx;
8816 fxsave->fop = fpu->last_opcode;
8817 fxsave->rip = fpu->last_ip;
8818 fxsave->rdp = fpu->last_dp;
0e96f31e 8819 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8820
6a96bc7f 8821 vcpu_put(vcpu);
d0752060
HB		 8822 return 0;
8823}
8824
01643c51
KH		 8825static void store_regs(struct kvm_vcpu *vcpu)
8826{
8827 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8828
8829 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8830 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8831
8832 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8833 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8834
8835 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8836 kvm_vcpu_ioctl_x86_get_vcpu_events(
8837 vcpu, &vcpu->run->s.regs.events);
8838}
8839
8840static int sync_regs(struct kvm_vcpu *vcpu)
8841{
8842 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8843 return -EINVAL;
8844
8845 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8846 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8847 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8848 }
8849 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8850 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8851 return -EINVAL;
8852 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8853 }
8854 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8855 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8856 vcpu, &vcpu->run->s.regs.events))
8857 return -EINVAL;
8858 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8859 }
8860
8861 return 0;
8862}
8863
0ee6a517 8864static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8865{
b666a4b6 8866 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 8867 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 8868 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 8869 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8870
2acf923e
DC		 8871 /*
8872 * Ensure guest xcr0 is valid for loading
8873 */
d91cab78 8874 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8875
ad312c7c 8876 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8877}
d0752060 8878
e9b11c17
ZX		 8879void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8880{
bd768e14
IY		 8881 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8882
12f9a48f 8883 kvmclock_reset(vcpu);
7f1ea208 8884
e9b11c17 8885 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8886 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8887}
8888
8889struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8890 unsigned int id)
8891{
c447e76b
LL		 8892 struct kvm_vcpu *vcpu;
8893
b0c39dc6 8894 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8895 printk_once(KERN_WARNING
8896 "kvm: SMP vm created on host with unstable TSC; "
8897 "guest TSC will not be reliable\n");
c447e76b
LL		 8898
8899 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8900
c447e76b 8901 return vcpu;
26e5215f 8902}
e9b11c17 8903
26e5215f
AK		 8904int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8905{
0cf9135b 8906 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 8907 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 8908 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8909 vcpu_load(vcpu);
d28bc9dd 8910 kvm_vcpu_reset(vcpu, false);
e1732991 8911 kvm_init_mmu(vcpu, false);
e9b11c17 8912 vcpu_put(vcpu);
ec7660cc 8913 return 0;
e9b11c17
ZX		 8914}
8915
31928aa5 8916void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8917{
8fe8ab46 8918 struct msr_data msr;
332967a3 8919 struct kvm *kvm = vcpu->kvm;
42897d86 8920
d3457c87
RK		 8921 kvm_hv_vcpu_postcreate(vcpu);
8922
ec7660cc 8923 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8924 return;
ec7660cc 8925 vcpu_load(vcpu);
8fe8ab46
WA		 8926 msr.data = 0x0;
8927 msr.index = MSR_IA32_TSC;
8928 msr.host_initiated = true;
8929 kvm_write_tsc(vcpu, &msr);
42897d86 8930 vcpu_put(vcpu);
2d5ba19b
MT		 8931
8932 /* poll control enabled by default */
8933 vcpu->arch.msr_kvm_poll_control = 1;
8934
ec7660cc 8935 mutex_unlock(&vcpu->mutex);
42897d86 8936
630994b3
MT		 8937 if (!kvmclock_periodic_sync)
8938 return;
8939
332967a3
AJ		 8940 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8941 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8942}
8943
d40ccc62 8944void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8945{
344d9588
GN		 8946 vcpu->arch.apf.msr_val = 0;
8947
ec7660cc 8948 vcpu_load(vcpu);
e9b11c17
ZX		 8949 kvm_mmu_unload(vcpu);
8950 vcpu_put(vcpu);
8951
8952 kvm_x86_ops->vcpu_free(vcpu);
8953}
8954
d28bc9dd 8955void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8956{
b7e31be3
RK		 8957 kvm_lapic_reset(vcpu, init_event);
8958
e69fab5d
PB		 8959 vcpu->arch.hflags = 0;
8960
c43203ca 8961 vcpu->arch.smi_pending = 0;
52797bf9 8962 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8963 atomic_set(&vcpu->arch.nmi_queued, 0);
8964 vcpu->arch.nmi_pending = 0;
448fa4a9 8965 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8966 kvm_clear_interrupt_queue(vcpu);
8967 kvm_clear_exception_queue(vcpu);
664f8e26 8968 vcpu->arch.exception.pending = false;
448fa4a9 8969
42dbaa5a 8970 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8971 kvm_update_dr0123(vcpu);
6f43ed01 8972 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8973 kvm_update_dr6(vcpu);
42dbaa5a 8974 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8975 kvm_update_dr7(vcpu);
42dbaa5a 8976
1119022c
NA		 8977 vcpu->arch.cr2 = 0;
8978
3842d135 8979 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8980 vcpu->arch.apf.msr_val = 0;
c9aaa895 8981 vcpu->arch.st.msr_val = 0;
3842d135 8982
12f9a48f
GC		 8983 kvmclock_reset(vcpu);
8984
af585b92
GN		 8985 kvm_clear_async_pf_completion_queue(vcpu);
8986 kvm_async_pf_hash_reset(vcpu);
8987 vcpu->arch.apf.halted = false;
3842d135 8988
a554d207
WL		 8989 if (kvm_mpx_supported()) {
8990 void *mpx_state_buffer;
8991
8992 /*
8993 * To avoid have the INIT path from kvm_apic_has_events() that be
8994 * called with loaded FPU and does not let userspace fix the state.
8995 */
f775b13e
RR		 8996 if (init_event)
8997 kvm_put_guest_fpu(vcpu);
b666a4b6 8998 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 8999 XFEATURE_BNDREGS);
a554d207
WL		 9000 if (mpx_state_buffer)
9001 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 9002 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9003 XFEATURE_BNDCSR);
a554d207
WL		 9004 if (mpx_state_buffer)
9005 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 9006 if (init_event)
9007 kvm_load_guest_fpu(vcpu);
a554d207
WL		 9008 }
9009
64d60670 9010 if (!init_event) {
d28bc9dd 9011 kvm_pmu_reset(vcpu);
64d60670 9012 vcpu->arch.smbase = 0x30000;
db2336a8 9013
db2336a8 9014 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 9015
9016 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 9017 }
f5132b01 9018
66f7b72e
JS		 9019 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9020 vcpu->arch.regs_avail = ~0;
9021 vcpu->arch.regs_dirty = ~0;
9022
a554d207
WL		 9023 vcpu->arch.ia32_xss = 0;
9024
d28bc9dd 9025 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 9026}
9027
2b4a273b 9028void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 9029{
9030 struct kvm_segment cs;
9031
9032 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9033 cs.selector = vector << 8;
9034 cs.base = vector << 12;
9035 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9036 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 9037}
9038
13a34e06 9039int kvm_arch_hardware_enable(void)
e9b11c17 9040{
ca84d1a2
ZA		 9041 struct kvm *kvm;
9042 struct kvm_vcpu *vcpu;
9043 int i;
0dd6a6ed
ZA		 9044 int ret;
9045 u64 local_tsc;
9046 u64 max_tsc = 0;
9047 bool stable, backwards_tsc = false;
18863bdd
AK		 9048
9049 kvm_shared_msr_cpu_online();
13a34e06 9050 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 9051 if (ret != 0)
9052 return ret;
9053
4ea1636b 9054 local_tsc = rdtsc();
b0c39dc6 9055 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 9056 list_for_each_entry(kvm, &vm_list, vm_list) {
9057 kvm_for_each_vcpu(i, vcpu, kvm) {
9058 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 9059 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9060 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9061 backwards_tsc = true;
9062 if (vcpu->arch.last_host_tsc > max_tsc)
9063 max_tsc = vcpu->arch.last_host_tsc;
9064 }
9065 }
9066 }
9067
9068 /*
9069 * Sometimes, even reliable TSCs go backwards. This happens on
9070 * platforms that reset TSC during suspend or hibernate actions, but
9071 * maintain synchronization. We must compensate. Fortunately, we can
9072 * detect that condition here, which happens early in CPU bringup,
9073 * before any KVM threads can be running. Unfortunately, we can't
9074 * bring the TSCs fully up to date with real time, as we aren't yet far
9075 * enough into CPU bringup that we know how much real time has actually
9285ec4c 9076 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
0dd6a6ed
ZA		 9077 * variables that haven't been updated yet.
9078 *
9079 * So we simply find the maximum observed TSC above, then record the
9080 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9081 * the adjustment will be applied. Note that we accumulate
9082 * adjustments, in case multiple suspend cycles happen before some VCPU
9083 * gets a chance to run again. In the event that no KVM threads get a
9084 * chance to run, we will miss the entire elapsed period, as we'll have
9085 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9086 * loose cycle time. This isn't too big a deal, since the loss will be
9087 * uniform across all VCPUs (not to mention the scenario is extremely
9088 * unlikely). It is possible that a second hibernate recovery happens
9089 * much faster than a first, causing the observed TSC here to be
9090 * smaller; this would require additional padding adjustment, which is
9091 * why we set last_host_tsc to the local tsc observed here.
9092 *
9093 * N.B. - this code below runs only on platforms with reliable TSC,
9094 * as that is the only way backwards_tsc is set above. Also note
9095 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9096 * have the same delta_cyc adjustment applied if backwards_tsc
9097 * is detected. Note further, this adjustment is only done once,
9098 * as we reset last_host_tsc on all VCPUs to stop this from being
9099 * called multiple times (one for each physical CPU bringup).
9100 *
4a969980 9101 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 9102 * will be compensated by the logic in vcpu_load, which sets the TSC to
9103 * catchup mode. This will catchup all VCPUs to real time, but cannot
9104 * guarantee that they stay in perfect synchronization.
9105 */
9106 if (backwards_tsc) {
9107 u64 delta_cyc = max_tsc - local_tsc;
9108 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 9109 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 9110 kvm_for_each_vcpu(i, vcpu, kvm) {
9111 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9112 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 9113 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9114 }
9115
9116 /*
9117 * We have to disable TSC offset matching.. if you were
9118 * booting a VM while issuing an S4 host suspend....
9119 * you may have some problem. Solving this issue is
9120 * left as an exercise to the reader.
9121 */
9122 kvm->arch.last_tsc_nsec = 0;
9123 kvm->arch.last_tsc_write = 0;
9124 }
9125
9126 }
9127 return 0;
e9b11c17
ZX		 9128}
9129
13a34e06 9130void kvm_arch_hardware_disable(void)
e9b11c17 9131{
13a34e06
RK		 9132 kvm_x86_ops->hardware_disable();
9133 drop_user_return_notifiers();
e9b11c17
ZX		 9134}
9135
9136int kvm_arch_hardware_setup(void)
9137{
9e9c3fe4
NA		 9138 int r;
9139
9140 r = kvm_x86_ops->hardware_setup();
9141 if (r != 0)
9142 return r;
9143
35181e86
HZ		 9144 if (kvm_has_tsc_control) {
9145 /*
9146 * Make sure the user can only configure tsc_khz values that
9147 * fit into a signed integer.
273ba457 9148 * A min value is not calculated because it will always
35181e86
HZ		 9149 * be 1 on all machines.
9150 */
9151 u64 max = min(0x7fffffffULL,
9152 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9153 kvm_max_guest_tsc_khz = max;
9154
ad721883 9155 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9156 }
ad721883 9157
9e9c3fe4
NA		 9158 kvm_init_msr_list();
9159 return 0;
e9b11c17
ZX		 9160}
9161
9162void kvm_arch_hardware_unsetup(void)
9163{
9164 kvm_x86_ops->hardware_unsetup();
9165}
9166
f257d6dc 9167int kvm_arch_check_processor_compat(void)
e9b11c17 9168{
f257d6dc 9169 return kvm_x86_ops->check_processor_compatibility();
d71ba788
PB		 9170}
9171
9172bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9173{
9174 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9175}
9176EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9177
9178bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9179{
9180 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9181}
9182
54e9818f 9183struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9184EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9185
e9b11c17
ZX		 9186int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9187{
9188 struct page *page;
e9b11c17
ZX		 9189 int r;
9190
9aabc88f 9191 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9192 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9193 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9194 else
a4535290 9195 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9196
9197 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9198 if (!page) {
9199 r = -ENOMEM;
9200 goto fail;
9201 }
ad312c7c 9202 vcpu->arch.pio_data = page_address(page);
e9b11c17 9203
cc578287 9204 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9205
e9b11c17
ZX		 9206 r = kvm_mmu_create(vcpu);
9207 if (r < 0)
9208 goto fail_free_pio_data;
9209
26de7988 9210 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9211 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
39497d76 9212 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
e9b11c17
ZX		 9213 if (r < 0)
9214 goto fail_mmu_destroy;
54e9818f
GN		 9215 } else
9216 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9217
890ca9ae 9218 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
254272ce 9219 GFP_KERNEL_ACCOUNT);
890ca9ae
HY		 9220 if (!vcpu->arch.mce_banks) {
9221 r = -ENOMEM;
443c39bc 9222 goto fail_free_lapic;
890ca9ae
HY		 9223 }
9224 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9225
254272ce
BG		 9226 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9227 GFP_KERNEL_ACCOUNT)) {
f1797359 9228 r = -ENOMEM;
f5f48ee1 9229 goto fail_free_mce_banks;
f1797359 9230 }
f5f48ee1 9231
0ee6a517 9232 fx_init(vcpu);
66f7b72e 9233
4344ee98 9234 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9235
5a4f55cd
EK		 9236 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9237
74545705
RK		 9238 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9239
af585b92 9240 kvm_async_pf_hash_reset(vcpu);
f5132b01 9241 kvm_pmu_init(vcpu);
af585b92 9242
1c1a9ce9 9243 vcpu->arch.pending_external_vector = -1;
de63ad4c 9244 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9245
5c919412
AS		 9246 kvm_hv_vcpu_init(vcpu);
9247
e9b11c17 9248 return 0;
0ee6a517 9249
f5f48ee1
SY		 9250fail_free_mce_banks:
9251 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9252fail_free_lapic:
9253 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9254fail_mmu_destroy:
9255 kvm_mmu_destroy(vcpu);
9256fail_free_pio_data:
ad312c7c 9257 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9258fail:
9259 return r;
9260}
9261
9262void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9263{
f656ce01
MT		 9264 int idx;
9265
1f4b34f8 9266 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9267 kvm_pmu_destroy(vcpu);
36cb93fd 9268 kfree(vcpu->arch.mce_banks);
e9b11c17 9269 kvm_free_lapic(vcpu);
f656ce01 9270 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9271 kvm_mmu_destroy(vcpu);
f656ce01 9272 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9273 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9274 if (!lapic_in_kernel(vcpu))
54e9818f 9275 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9276}
d19a9cd2 9277
e790d9ef
RK		 9278void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9279{
c595ceee 9280 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9281 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9282}
9283
e08b9637 9284int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9285{
e08b9637
CO		 9286 if (type)
9287 return -EINVAL;
9288
6ef768fa 9289 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9290 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 9291 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9292 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9293
5550af4d
SY		 9294 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9295 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9296 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9297 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9298 &kvm->arch.irq_sources_bitmap);
5550af4d 9299
038f8c11 9300 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9301 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9302 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9303
9285ec4c 9304 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
d828199e 9305 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9306
6fbbde9a
DS		 9307 kvm->arch.guest_can_read_msr_platform_info = true;
9308
7e44e449 9309 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9310 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9311
cbc0236a 9312 kvm_hv_init_vm(kvm);
0eb05bf2 9313 kvm_page_track_init(kvm);
13d268ca 9314 kvm_mmu_init_vm(kvm);
0eb05bf2 9315
03543133
SS		 9316 if (kvm_x86_ops->vm_init)
9317 return kvm_x86_ops->vm_init(kvm);
9318
d89f5eff 9319 return 0;
d19a9cd2
ZX		 9320}
9321
9322static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9323{
ec7660cc 9324 vcpu_load(vcpu);
d19a9cd2
ZX		 9325 kvm_mmu_unload(vcpu);
9326 vcpu_put(vcpu);
9327}
9328
9329static void kvm_free_vcpus(struct kvm *kvm)
9330{
9331 unsigned int i;
988a2cae 9332 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9333
9334 /*
9335 * Unpin any mmu pages first.
9336 */
af585b92
GN		 9337 kvm_for_each_vcpu(i, vcpu, kvm) {
9338 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9339 kvm_unload_vcpu_mmu(vcpu);
af585b92 9340 }
988a2cae
GN		 9341 kvm_for_each_vcpu(i, vcpu, kvm)
9342 kvm_arch_vcpu_free(vcpu);
9343
9344 mutex_lock(&kvm->lock);
9345 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9346 kvm->vcpus[i] = NULL;
d19a9cd2 9347
988a2cae
GN		 9348 atomic_set(&kvm->online_vcpus, 0);
9349 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9350}
9351
ad8ba2cd
SY		 9352void kvm_arch_sync_events(struct kvm *kvm)
9353{
332967a3 9354 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9355 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9356 kvm_free_pit(kvm);
ad8ba2cd
SY		 9357}
9358
1d8007bd 9359int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9360{
9361 int i, r;
25188b99 9362 unsigned long hva;
f0d648bd
PB		 9363 struct kvm_memslots *slots = kvm_memslots(kvm);
9364 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9365
9366 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9367 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9368 return -EINVAL;
9da0e4d5 9369
f0d648bd
PB		 9370 slot = id_to_memslot(slots, id);
9371 if (size) {
b21629da 9372 if (slot->npages)
f0d648bd
PB		 9373 return -EEXIST;
9374
9375 /*
9376 * MAP_SHARED to prevent internal slot pages from being moved
9377 * by fork()/COW.
9378 */
9379 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9380 MAP_SHARED | MAP_ANONYMOUS, 0);
9381 if (IS_ERR((void *)hva))
9382 return PTR_ERR((void *)hva);
9383 } else {
9384 if (!slot->npages)
9385 return 0;
9386
9387 hva = 0;
9388 }
9389
9390 old = *slot;
9da0e4d5 9391 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9392 struct kvm_userspace_memory_region m;
9da0e4d5 9393
1d8007bd
PB		 9394 m.slot = id | (i << 16);
9395 m.flags = 0;
9396 m.guest_phys_addr = gpa;
f0d648bd 9397 m.userspace_addr = hva;
1d8007bd 9398 m.memory_size = size;
9da0e4d5
PB		 9399 r = __kvm_set_memory_region(kvm, &m);
9400 if (r < 0)
9401 return r;
9402 }
9403
103c763c
EB		 9404 if (!size)
9405 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9406
9da0e4d5
PB		 9407 return 0;
9408}
9409EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9410
1d8007bd 9411int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9412{
9413 int r;
9414
9415 mutex_lock(&kvm->slots_lock);
1d8007bd 9416 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9417 mutex_unlock(&kvm->slots_lock);
9418
9419 return r;
9420}
9421EXPORT_SYMBOL_GPL(x86_set_memory_region);
9422
d19a9cd2
ZX		 9423void kvm_arch_destroy_vm(struct kvm *kvm)
9424{
27469d29
AH		 9425 if (current->mm == kvm->mm) {
9426 /*
9427 * Free memory regions allocated on behalf of userspace,
9428 * unless the the memory map has changed due to process exit
9429 * or fd copying.
9430 */
1d8007bd
PB		 9431 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9432 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9433 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9434 }
03543133
SS		 9435 if (kvm_x86_ops->vm_destroy)
9436 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9437 kvm_pic_destroy(kvm);
9438 kvm_ioapic_destroy(kvm);
d19a9cd2 9439 kvm_free_vcpus(kvm);
af1bae54 9440 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
66bb8a06 9441 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
13d268ca 9442 kvm_mmu_uninit_vm(kvm);
2beb6dad 9443 kvm_page_track_cleanup(kvm);
cbc0236a 9444 kvm_hv_destroy_vm(kvm);
d19a9cd2 9445}
0de10343 9446
5587027c 9447void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9448 struct kvm_memory_slot *dont)
9449{
9450 int i;
9451
d89cc617
TY		 9452 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9453 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9454 kvfree(free->arch.rmap[i]);
d89cc617 9455 free->arch.rmap[i] = NULL;
77d11309 9456 }
d89cc617
TY		 9457 if (i == 0)
9458 continue;
9459
9460 if (!dont || free->arch.lpage_info[i - 1] !=
9461 dont->arch.lpage_info[i - 1]) {
548ef284 9462 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9463 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9464 }
9465 }
21ebbeda
XG		 9466
9467 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9468}
9469
5587027c
AK		 9470int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9471 unsigned long npages)
db3fe4eb
TY		 9472{
9473 int i;
9474
d89cc617 9475 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9476 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9477 unsigned long ugfn;
9478 int lpages;
d89cc617 9479 int level = i + 1;
db3fe4eb
TY		 9480
9481 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9482 slot->base_gfn, level) + 1;
9483
d89cc617 9484 slot->arch.rmap[i] =
778e1cdd 9485 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9486 GFP_KERNEL_ACCOUNT);
d89cc617 9487 if (!slot->arch.rmap[i])
77d11309 9488 goto out_free;
d89cc617
TY		 9489 if (i == 0)
9490 continue;
77d11309 9491
254272ce 9492 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9493 if (!linfo)
db3fe4eb
TY		 9494 goto out_free;
9495
92f94f1e
XG		 9496 slot->arch.lpage_info[i - 1] = linfo;
9497
db3fe4eb 9498 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9499 linfo[0].disallow_lpage = 1;
db3fe4eb 9500 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9501 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9502 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9503 /*
9504 * If the gfn and userspace address are not aligned wrt each
9505 * other, or if explicitly asked to, disable large page
9506 * support for this slot
9507 */
9508 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9509 !kvm_largepages_enabled()) {
9510 unsigned long j;
9511
9512 for (j = 0; j < lpages; ++j)
92f94f1e 9513 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9514 }
9515 }
9516
21ebbeda
XG		 9517 if (kvm_page_track_create_memslot(slot, npages))
9518 goto out_free;
9519
db3fe4eb
TY		 9520 return 0;
9521
9522out_free:
d89cc617 9523 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9524 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9525 slot->arch.rmap[i] = NULL;
9526 if (i == 0)
9527 continue;
9528
548ef284 9529 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9530 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9531 }
9532 return -ENOMEM;
9533}
9534
15248258 9535void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9536{
e6dff7d1
TY		 9537 /*
9538 * memslots->generation has been incremented.
9539 * mmio generation may have reached its maximum value.
9540 */
15248258 9541 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9542}
9543
f7784b8e
MT		 9544int kvm_arch_prepare_memory_region(struct kvm *kvm,
9545 struct kvm_memory_slot *memslot,
09170a49 9546 const struct kvm_userspace_memory_region *mem,
7b6195a9 9547 enum kvm_mr_change change)
0de10343 9548{
f7784b8e
MT		 9549 return 0;
9550}
9551
88178fd4
KH		 9552static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9553 struct kvm_memory_slot *new)
9554{
9555 /* Still write protect RO slot */
9556 if (new->flags & KVM_MEM_READONLY) {
9557 kvm_mmu_slot_remove_write_access(kvm, new);
9558 return;
9559 }
9560
9561 /*
9562 * Call kvm_x86_ops dirty logging hooks when they are valid.
9563 *
9564 * kvm_x86_ops->slot_disable_log_dirty is called when:
9565 *
9566 * - KVM_MR_CREATE with dirty logging is disabled
9567 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9568 *
9569 * The reason is, in case of PML, we need to set D-bit for any slots
9570 * with dirty logging disabled in order to eliminate unnecessary GPA
9571 * logging in PML buffer (and potential PML buffer full VMEXT). This
9572 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9573 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9574 * logging disabled for memory slots.
9575 *
9576 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9577 * to dirty logging mode.
9578 *
9579 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9580 *
9581 * In case of write protect:
9582 *
9583 * Write protect all pages for dirty logging.
9584 *
9585 * All the sptes including the large sptes which point to this
9586 * slot are set to readonly. We can not create any new large
9587 * spte on this slot until the end of the logging.
9588 *
9589 * See the comments in fast_page_fault().
9590 */
9591 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9592 if (kvm_x86_ops->slot_enable_log_dirty)
9593 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9594 else
9595 kvm_mmu_slot_remove_write_access(kvm, new);
9596 } else {
9597 if (kvm_x86_ops->slot_disable_log_dirty)
9598 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9599 }
9600}
9601
f7784b8e 9602void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9603 const struct kvm_userspace_memory_region *mem,
8482644a 9604 const struct kvm_memory_slot *old,
f36f3f28 9605 const struct kvm_memory_slot *new,
8482644a 9606 enum kvm_mr_change change)
f7784b8e 9607{
48c0e4e9 9608 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9609 kvm_mmu_change_mmu_pages(kvm,
9610 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9611
3ea3b7fa
WL		 9612 /*
9613 * Dirty logging tracks sptes in 4k granularity, meaning that large
9614 * sptes have to be split. If live migration is successful, the guest
9615 * in the source machine will be destroyed and large sptes will be
9616 * created in the destination. However, if the guest continues to run
9617 * in the source machine (for example if live migration fails), small
9618 * sptes will remain around and cause bad performance.
9619 *
9620 * Scan sptes if dirty logging has been stopped, dropping those
9621 * which can be collapsed into a single large-page spte. Later
9622 * page faults will create the large-page sptes.
9623 */
9624 if ((change != KVM_MR_DELETE) &&
9625 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9626 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9627 kvm_mmu_zap_collapsible_sptes(kvm, new);
9628
c972f3b1 9629 /*
88178fd4 9630 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9631 *
88178fd4
KH		 9632 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9633 * been zapped so no dirty logging staff is needed for old slot. For
9634 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9635 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9636 *
9637 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9638 */
88178fd4 9639 if (change != KVM_MR_DELETE)
f36f3f28 9640 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9641}
1d737c8a 9642
2df72e9b 9643void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9644{
7390de1e 9645 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9646}
9647
2df72e9b
MT		 9648void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9649 struct kvm_memory_slot *slot)
9650{
ae7cd873 9651 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9652}
9653
e6c67d8c
LA		 9654static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9655{
9656 return (is_guest_mode(vcpu) &&
9657 kvm_x86_ops->guest_apic_has_interrupt &&
9658 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9659}
9660
5d9bc648
PB		 9661static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9662{
9663 if (!list_empty_careful(&vcpu->async_pf.done))
9664 return true;
9665
9666 if (kvm_apic_has_events(vcpu))
9667 return true;
9668
9669 if (vcpu->arch.pv.pv_unhalted)
9670 return true;
9671
a5f01f8e
WL		 9672 if (vcpu->arch.exception.pending)
9673 return true;
9674
47a66eed
Z		 9675 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9676 (vcpu->arch.nmi_pending &&
9677 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9678 return true;
9679
47a66eed
Z		 9680 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9681 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9682 return true;
9683
5d9bc648 9684 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9685 (kvm_cpu_has_interrupt(vcpu) ||
9686 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9687 return true;
9688
1f4b34f8
AS		 9689 if (kvm_hv_has_stimer_pending(vcpu))
9690 return true;
9691
5d9bc648
PB		 9692 return false;
9693}
9694
1d737c8a
ZX		 9695int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9696{
5d9bc648 9697 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9698}
5736199a 9699
199b5763
LM		 9700bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9701{
de63ad4c 9702 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9703}
9704
b6d33834 9705int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9706{
b6d33834 9707 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9708}
78646121
GN		 9709
9710int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9711{
9712 return kvm_x86_ops->interrupt_allowed(vcpu);
9713}
229456fc 9714
82b32774 9715unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9716{
82b32774
NA		 9717 if (is_64_bit_mode(vcpu))
9718 return kvm_rip_read(vcpu);
9719 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9720 kvm_rip_read(vcpu));
9721}
9722EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9723
82b32774
NA		 9724bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9725{
9726 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9727}
9728EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9729
94fe45da
JK		 9730unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9731{
9732 unsigned long rflags;
9733
9734 rflags = kvm_x86_ops->get_rflags(vcpu);
9735 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9736 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9737 return rflags;
9738}
9739EXPORT_SYMBOL_GPL(kvm_get_rflags);
9740
6addfc42 9741static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9742{
9743 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9744 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9745 rflags |= X86_EFLAGS_TF;
94fe45da 9746 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9747}
9748
9749void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9750{
9751 __kvm_set_rflags(vcpu, rflags);
3842d135 9752 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9753}
9754EXPORT_SYMBOL_GPL(kvm_set_rflags);
9755
56028d08
GN		 9756void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9757{
9758 int r;
9759
44dd3ffa 9760 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9761 work->wakeup_all)
56028d08
GN		 9762 return;
9763
9764 r = kvm_mmu_reload(vcpu);
9765 if (unlikely(r))
9766 return;
9767
44dd3ffa
VK		 9768 if (!vcpu->arch.mmu->direct_map &&
9769 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9770 return;
9771
44dd3ffa 9772 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9773}
9774
af585b92
GN		 9775static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9776{
9777 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9778}
9779
9780static inline u32 kvm_async_pf_next_probe(u32 key)
9781{
9782 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9783}
9784
9785static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9786{
9787 u32 key = kvm_async_pf_hash_fn(gfn);
9788
9789 while (vcpu->arch.apf.gfns[key] != ~0)
9790 key = kvm_async_pf_next_probe(key);
9791
9792 vcpu->arch.apf.gfns[key] = gfn;
9793}
9794
9795static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9796{
9797 int i;
9798 u32 key = kvm_async_pf_hash_fn(gfn);
9799
9800 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9801 (vcpu->arch.apf.gfns[key] != gfn &&
9802 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9803 key = kvm_async_pf_next_probe(key);
9804
9805 return key;
9806}
9807
9808bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9809{
9810 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9811}
9812
9813static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9814{
9815 u32 i, j, k;
9816
9817 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9818 while (true) {
9819 vcpu->arch.apf.gfns[i] = ~0;
9820 do {
9821 j = kvm_async_pf_next_probe(j);
9822 if (vcpu->arch.apf.gfns[j] == ~0)
9823 return;
9824 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9825 /*
9826 * k lies cyclically in ]i,j]
9827 * | i.k.j |
9828 * |....j i.k.| or |.k..j i...|
9829 */
9830 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9831 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9832 i = j;
9833 }
9834}
9835
7c90705b
GN		 9836static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9837{
4e335d9e
PB		 9838
9839 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9840 sizeof(val));
7c90705b
GN		 9841}
9842
9a6e7c39
WL		 9843static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9844{
9845
9846 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9847 sizeof(u32));
9848}
9849
1dfdb45e
PB		 9850static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
9851{
9852 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
9853 return false;
9854
9855 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9856 (vcpu->arch.apf.send_user_only &&
9857 kvm_x86_ops->get_cpl(vcpu) == 0))
9858 return false;
9859
9860 return true;
9861}
9862
9863bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
9864{
9865 if (unlikely(!lapic_in_kernel(vcpu) ||
9866 kvm_event_needs_reinjection(vcpu) ||
9867 vcpu->arch.exception.pending))
9868 return false;
9869
9870 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
9871 return false;
9872
9873 /*
9874 * If interrupts are off we cannot even use an artificial
9875 * halt state.
9876 */
9877 return kvm_x86_ops->interrupt_allowed(vcpu);
9878}
9879
af585b92
GN		 9880void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9881 struct kvm_async_pf *work)
9882{
6389ee94
AK		 9883 struct x86_exception fault;
9884
7c90705b 9885 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9886 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b 9887
1dfdb45e
PB		 9888 if (kvm_can_deliver_async_pf(vcpu) &&
9889 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9890 fault.vector = PF_VECTOR;
9891 fault.error_code_valid = true;
9892 fault.error_code = 0;
9893 fault.nested_page_fault = false;
9894 fault.address = work->arch.token;
adfe20fb 9895 fault.async_page_fault = true;
6389ee94 9896 kvm_inject_page_fault(vcpu, &fault);
1dfdb45e
PB		 9897 } else {
9898 /*
9899 * It is not possible to deliver a paravirtualized asynchronous
9900 * page fault, but putting the guest in an artificial halt state
9901 * can be beneficial nevertheless: if an interrupt arrives, we
9902 * can deliver it timely and perhaps the guest will schedule
9903 * another process. When the instruction that triggered a page
9904 * fault is retried, hopefully the page will be ready in the host.
9905 */
9906 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7c90705b 9907 }
af585b92
GN		 9908}
9909
9910void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9911 struct kvm_async_pf *work)
9912{
6389ee94 9913 struct x86_exception fault;
9a6e7c39 9914 u32 val;
6389ee94 9915
f2e10669 9916 if (work->wakeup_all)
7c90705b
GN		 9917 work->arch.token = ~0; /* broadcast wakeup */
9918 else
9919 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9920 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9921
9a6e7c39
WL		 9922 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9923 !apf_get_user(vcpu, &val)) {
9924 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9925 vcpu->arch.exception.pending &&
9926 vcpu->arch.exception.nr == PF_VECTOR &&
9927 !apf_put_user(vcpu, 0)) {
9928 vcpu->arch.exception.injected = false;
9929 vcpu->arch.exception.pending = false;
9930 vcpu->arch.exception.nr = 0;
9931 vcpu->arch.exception.has_error_code = false;
9932 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9933 vcpu->arch.exception.has_payload = false;
9934 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9935 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9936 fault.vector = PF_VECTOR;
9937 fault.error_code_valid = true;
9938 fault.error_code = 0;
9939 fault.nested_page_fault = false;
9940 fault.address = work->arch.token;
9941 fault.async_page_fault = true;
9942 kvm_inject_page_fault(vcpu, &fault);
9943 }
7c90705b 9944 }
e6d53e3b 9945 vcpu->arch.apf.halted = false;
a4fa1635 9946 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9947}
9948
9949bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9950{
9951 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9952 return true;
9953 else
9bc1f09f 9954 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9955}
9956
5544eb9b
PB		 9957void kvm_arch_start_assignment(struct kvm *kvm)
9958{
9959 atomic_inc(&kvm->arch.assigned_device_count);
9960}
9961EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9962
9963void kvm_arch_end_assignment(struct kvm *kvm)
9964{
9965 atomic_dec(&kvm->arch.assigned_device_count);
9966}
9967EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9968
9969bool kvm_arch_has_assigned_device(struct kvm *kvm)
9970{
9971 return atomic_read(&kvm->arch.assigned_device_count);
9972}
9973EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9974
e0f0bbc5
AW		 9975void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9976{
9977 atomic_inc(&kvm->arch.noncoherent_dma_count);
9978}
9979EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9980
9981void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9982{
9983 atomic_dec(&kvm->arch.noncoherent_dma_count);
9984}
9985EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9986
9987bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9988{
9989 return atomic_read(&kvm->arch.noncoherent_dma_count);
9990}
9991EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9992
14717e20
AW		 9993bool kvm_arch_has_irq_bypass(void)
9994{
9995 return kvm_x86_ops->update_pi_irte != NULL;
9996}
9997
87276880
FW		 9998int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9999 struct irq_bypass_producer *prod)
10000{
10001 struct kvm_kernel_irqfd *irqfd =
10002 container_of(cons, struct kvm_kernel_irqfd, consumer);
10003
14717e20 10004 irqfd->producer = prod;
87276880 10005
14717e20
AW		 10006 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10007 prod->irq, irqfd->gsi, 1);
87276880
FW		 10008}
10009
10010void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10011 struct irq_bypass_producer *prod)
10012{
10013 int ret;
10014 struct kvm_kernel_irqfd *irqfd =
10015 container_of(cons, struct kvm_kernel_irqfd, consumer);
10016
87276880
FW		 10017 WARN_ON(irqfd->producer != prod);
10018 irqfd->producer = NULL;
10019
10020 /*
10021 * When producer of consumer is unregistered, we change back to
10022 * remapped mode, so we can re-use the current implementation
bb3541f1 10023 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 10024 * int this case doesn't want to receive the interrupts.
10025 */
10026 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10027 if (ret)
10028 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10029 " fails: %d\n", irqfd->consumer.token, ret);
10030}
10031
10032int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10033 uint32_t guest_irq, bool set)
10034{
10035 if (!kvm_x86_ops->update_pi_irte)
10036 return -EINVAL;
10037
10038 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10039}
10040
52004014
FW		 10041bool kvm_vector_hashing_enabled(void)
10042{
10043 return vector_hashing;
10044}
10045EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10046
2d5ba19b
MT		 10047bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10048{
10049 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10050}
10051EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10052
10053
229456fc 10054EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 10055EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 10056EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10057EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10058EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10059EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 10060EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 10061EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 10062EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 10063EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 10064EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 10065EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 10066EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 10067EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 10068EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 10069EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 10070EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 10071EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10072EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)