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KVM: x86: notifier for clocksource changes
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
123static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
8b6e4547
JK		 165static int kvm_vcpu_reset(struct kvm_vcpu *vcpu);
166
af585b92
GN		 167static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
168{
169 int i;
170 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
171 vcpu->arch.apf.gfns[i] = ~0;
172}
173
18863bdd
AK		 174static void kvm_on_user_return(struct user_return_notifier *urn)
175{
176 unsigned slot;
18863bdd
AK		 177 struct kvm_shared_msrs *locals
178 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 179 struct kvm_shared_msr_values *values;
18863bdd
AK		 180
181 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 182 values = &locals->values[slot];
183 if (values->host != values->curr) {
184 wrmsrl(shared_msrs_global.msrs[slot], values->host);
185 values->curr = values->host;
18863bdd
AK		 186 }
187 }
188 locals->registered = false;
189 user_return_notifier_unregister(urn);
190}
191
2bf78fa7 192static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 193{
2bf78fa7 194 struct kvm_shared_msrs *smsr;
18863bdd
AK		 195 u64 value;
196
2bf78fa7
SY		 197 smsr = &__get_cpu_var(shared_msrs);
198 /* only read, and nobody should modify it at this time,
199 * so don't need lock */
200 if (slot >= shared_msrs_global.nr) {
201 printk(KERN_ERR "kvm: invalid MSR slot!");
202 return;
203 }
204 rdmsrl_safe(msr, &value);
205 smsr->values[slot].host = value;
206 smsr->values[slot].curr = value;
207}
208
209void kvm_define_shared_msr(unsigned slot, u32 msr)
210{
18863bdd
AK		 211 if (slot >= shared_msrs_global.nr)
212 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 213 shared_msrs_global.msrs[slot] = msr;
214 /* we need ensured the shared_msr_global have been updated */
215 smp_wmb();
18863bdd
AK		 216}
217EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
218
219static void kvm_shared_msr_cpu_online(void)
220{
221 unsigned i;
18863bdd
AK		 222
223 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 224 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 225}
226
d5696725 227void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 228{
229 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
230
2bf78fa7 231 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 232 return;
2bf78fa7
SY		 233 smsr->values[slot].curr = value;
234 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 235 if (!smsr->registered) {
236 smsr->urn.on_user_return = kvm_on_user_return;
237 user_return_notifier_register(&smsr->urn);
238 smsr->registered = true;
239 }
240}
241EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
242
3548bab5
AK		 243static void drop_user_return_notifiers(void *ignore)
244{
245 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249}
250
6866b83e
CO		 251u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252{
8a5a87d9 253 return vcpu->arch.apic_base;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258{
259 /* TODO: reserve bits check */
8a5a87d9 260 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
3fd28fce
ED		 264#define EXCPT_BENIGN 0
265#define EXCPT_CONTRIBUTORY 1
266#define EXCPT_PF 2
267
268static int exception_class(int vector)
269{
270 switch (vector) {
271 case PF_VECTOR:
272 return EXCPT_PF;
273 case DE_VECTOR:
274 case TS_VECTOR:
275 case NP_VECTOR:
276 case SS_VECTOR:
277 case GP_VECTOR:
278 return EXCPT_CONTRIBUTORY;
279 default:
280 break;
281 }
282 return EXCPT_BENIGN;
283}
284
285static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 286 unsigned nr, bool has_error, u32 error_code,
287 bool reinject)
3fd28fce
ED		 288{
289 u32 prev_nr;
290 int class1, class2;
291
3842d135
AK		 292 kvm_make_request(KVM_REQ_EVENT, vcpu);
293
3fd28fce
ED		 294 if (!vcpu->arch.exception.pending) {
295 queue:
296 vcpu->arch.exception.pending = true;
297 vcpu->arch.exception.has_error_code = has_error;
298 vcpu->arch.exception.nr = nr;
299 vcpu->arch.exception.error_code = error_code;
3f0fd292 300 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 301 return;
302 }
303
304 /* to check exception */
305 prev_nr = vcpu->arch.exception.nr;
306 if (prev_nr == DF_VECTOR) {
307 /* triple fault -> shutdown */
a8eeb04a 308 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 309 return;
310 }
311 class1 = exception_class(prev_nr);
312 class2 = exception_class(nr);
313 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
314 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
315 /* generate double fault per SDM Table 5-5 */
316 vcpu->arch.exception.pending = true;
317 vcpu->arch.exception.has_error_code = true;
318 vcpu->arch.exception.nr = DF_VECTOR;
319 vcpu->arch.exception.error_code = 0;
320 } else
321 /* replace previous exception with a new one in a hope
322 that instruction re-execution will regenerate lost
323 exception */
324 goto queue;
325}
326
298101da
AK		 327void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
328{
ce7ddec4 329 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 330}
331EXPORT_SYMBOL_GPL(kvm_queue_exception);
332
ce7ddec4
JR		 333void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
334{
335 kvm_multiple_exception(vcpu, nr, false, 0, true);
336}
337EXPORT_SYMBOL_GPL(kvm_requeue_exception);
338
db8fcefa 339void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 340{
db8fcefa
AP		 341 if (err)
342 kvm_inject_gp(vcpu, 0);
343 else
344 kvm_x86_ops->skip_emulated_instruction(vcpu);
345}
346EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 347
6389ee94 348void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 349{
350 ++vcpu->stat.pf_guest;
6389ee94
AK		 351 vcpu->arch.cr2 = fault->address;
352 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 353}
27d6c865 354EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 355
6389ee94 356void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 357{
6389ee94
AK		 358 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
359 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 360 else
6389ee94 361 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 362}
363
3419ffc8
SY		 364void kvm_inject_nmi(struct kvm_vcpu *vcpu)
365{
7460fb4a
AK		 366 atomic_inc(&vcpu->arch.nmi_queued);
367 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 368}
369EXPORT_SYMBOL_GPL(kvm_inject_nmi);
370
298101da
AK		 371void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
372{
ce7ddec4 373 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 374}
375EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
376
ce7ddec4
JR		 377void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
378{
379 kvm_multiple_exception(vcpu, nr, true, error_code, true);
380}
381EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
382
0a79b009
AK		 383/*
384 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
385 * a #GP and return false.
386 */
387bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 388{
0a79b009
AK		 389 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
390 return true;
391 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
392 return false;
298101da 393}
0a79b009 394EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 395
ec92fe44
JR		 396/*
397 * This function will be used to read from the physical memory of the currently
398 * running guest. The difference to kvm_read_guest_page is that this function
399 * can read from guest physical or from the guest's guest physical memory.
400 */
401int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
402 gfn_t ngfn, void *data, int offset, int len,
403 u32 access)
404{
405 gfn_t real_gfn;
406 gpa_t ngpa;
407
408 ngpa = gfn_to_gpa(ngfn);
409 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
410 if (real_gfn == UNMAPPED_GVA)
411 return -EFAULT;
412
413 real_gfn = gpa_to_gfn(real_gfn);
414
415 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
416}
417EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
418
3d06b8bf
JR		 419int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
420 void *data, int offset, int len, u32 access)
421{
422 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
423 data, offset, len, access);
424}
425
a03490ed
CO		 426/*
427 * Load the pae pdptrs. Return true is they are all valid.
428 */
ff03a073 429int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 430{
431 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
432 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
433 int i;
434 int ret;
ff03a073 435 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 436
ff03a073
JR		 437 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
438 offset * sizeof(u64), sizeof(pdpte),
439 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 440 if (ret < 0) {
441 ret = 0;
442 goto out;
443 }
444 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 445 if (is_present_gpte(pdpte[i]) &&
20c466b5 446 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 447 ret = 0;
448 goto out;
449 }
450 }
451 ret = 1;
452
ff03a073 453 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 454 __set_bit(VCPU_EXREG_PDPTR,
455 (unsigned long *)&vcpu->arch.regs_avail);
456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 458out:
a03490ed
CO		 459
460 return ret;
461}
cc4b6871 462EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 463
d835dfec
AK		 464static bool pdptrs_changed(struct kvm_vcpu *vcpu)
465{
ff03a073 466 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 467 bool changed = true;
3d06b8bf
JR		 468 int offset;
469 gfn_t gfn;
d835dfec
AK		 470 int r;
471
472 if (is_long_mode(vcpu) || !is_pae(vcpu))
473 return false;
474
6de4f3ad
AK		 475 if (!test_bit(VCPU_EXREG_PDPTR,
476 (unsigned long *)&vcpu->arch.regs_avail))
477 return true;
478
9f8fe504
AK		 479 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
480 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 481 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
482 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 483 if (r < 0)
484 goto out;
ff03a073 485 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 486out:
d835dfec
AK		 487
488 return changed;
489}
490
49a9b07e 491int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 492{
aad82703
SY		 493 unsigned long old_cr0 = kvm_read_cr0(vcpu);
494 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
495 X86_CR0_CD | X86_CR0_NW;
496
f9a48e6a
AK		 497 cr0 |= X86_CR0_ET;
498
ab344828 499#ifdef CONFIG_X86_64
0f12244f
GN		 500 if (cr0 & 0xffffffff00000000UL)
501 return 1;
ab344828
GN		 502#endif
503
504 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 505
0f12244f
GN		 506 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
507 return 1;
a03490ed 508
0f12244f
GN		 509 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
510 return 1;
a03490ed
CO		 511
512 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
513#ifdef CONFIG_X86_64
f6801dff 514 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 515 int cs_db, cs_l;
516
0f12244f
GN		 517 if (!is_pae(vcpu))
518 return 1;
a03490ed 519 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 520 if (cs_l)
521 return 1;
a03490ed
CO		 522 } else
523#endif
ff03a073 524 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 525 kvm_read_cr3(vcpu)))
0f12244f 526 return 1;
a03490ed
CO		 527 }
528
ad756a16
MJ		 529 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
530 return 1;
531
a03490ed 532 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 533
d170c419 534 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 535 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 536 kvm_async_pf_hash_reset(vcpu);
537 }
e5f3f027 538
aad82703
SY		 539 if ((cr0 ^ old_cr0) & update_bits)
540 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 541 return 0;
542}
2d3ad1f4 543EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 544
2d3ad1f4 545void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 546{
49a9b07e 547 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 548}
2d3ad1f4 549EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 550
2acf923e
DC		 551int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
552{
553 u64 xcr0;
554
555 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
556 if (index != XCR_XFEATURE_ENABLED_MASK)
557 return 1;
558 xcr0 = xcr;
559 if (kvm_x86_ops->get_cpl(vcpu) != 0)
560 return 1;
561 if (!(xcr0 & XSTATE_FP))
562 return 1;
563 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
564 return 1;
565 if (xcr0 & ~host_xcr0)
566 return 1;
567 vcpu->arch.xcr0 = xcr0;
568 vcpu->guest_xcr0_loaded = 0;
569 return 0;
570}
571
572int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
573{
574 if (__kvm_set_xcr(vcpu, index, xcr)) {
575 kvm_inject_gp(vcpu, 0);
576 return 1;
577 }
578 return 0;
579}
580EXPORT_SYMBOL_GPL(kvm_set_xcr);
581
a83b29c6 582int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 583{
fc78f519 584 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 585 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
586 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 587 if (cr4 & CR4_RESERVED_BITS)
588 return 1;
a03490ed 589
2acf923e
DC		 590 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
591 return 1;
592
c68b734f
YW		 593 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
594 return 1;
595
74dc2b4f
YW		 596 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
597 return 1;
598
a03490ed 599 if (is_long_mode(vcpu)) {
0f12244f
GN		 600 if (!(cr4 & X86_CR4_PAE))
601 return 1;
a2edf57f
AK		 602 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
603 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 604 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
605 kvm_read_cr3(vcpu)))
0f12244f
GN		 606 return 1;
607
ad756a16
MJ		 608 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
609 if (!guest_cpuid_has_pcid(vcpu))
610 return 1;
611
612 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
613 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
614 return 1;
615 }
616
5e1746d6 617 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 618 return 1;
a03490ed 619
ad756a16
MJ		 620 if (((cr4 ^ old_cr4) & pdptr_bits) ||
621 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 622 kvm_mmu_reset_context(vcpu);
0f12244f 623
2acf923e 624 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 625 kvm_update_cpuid(vcpu);
2acf923e 626
0f12244f
GN		 627 return 0;
628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 630
2390218b 631int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 632{
9f8fe504 633 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 634 kvm_mmu_sync_roots(vcpu);
d835dfec 635 kvm_mmu_flush_tlb(vcpu);
0f12244f 636 return 0;
d835dfec
AK		 637 }
638
a03490ed 639 if (is_long_mode(vcpu)) {
471842ec 640 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 641 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
642 return 1;
643 } else
644 if (cr3 & CR3_L_MODE_RESERVED_BITS)
645 return 1;
a03490ed
CO		 646 } else {
647 if (is_pae(vcpu)) {
0f12244f
GN		 648 if (cr3 & CR3_PAE_RESERVED_BITS)
649 return 1;
ff03a073
JR		 650 if (is_paging(vcpu) &&
651 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 652 return 1;
a03490ed
CO		 653 }
654 /*
655 * We don't check reserved bits in nonpae mode, because
656 * this isn't enforced, and VMware depends on this.
657 */
658 }
659
a03490ed
CO		 660 /*
661 * Does the new cr3 value map to physical memory? (Note, we
662 * catch an invalid cr3 even in real-mode, because it would
663 * cause trouble later on when we turn on paging anyway.)
664 *
665 * A real CPU would silently accept an invalid cr3 and would
666 * attempt to use it - with largely undefined (and often hard
667 * to debug) behavior on the guest side.
668 */
669 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 670 return 1;
671 vcpu->arch.cr3 = cr3;
aff48baa 672 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 673 vcpu->arch.mmu.new_cr3(vcpu);
674 return 0;
675}
2d3ad1f4 676EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 677
eea1cff9 678int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 679{
0f12244f
GN		 680 if (cr8 & CR8_RESERVED_BITS)
681 return 1;
a03490ed
CO		 682 if (irqchip_in_kernel(vcpu->kvm))
683 kvm_lapic_set_tpr(vcpu, cr8);
684 else
ad312c7c 685 vcpu->arch.cr8 = cr8;
0f12244f
GN		 686 return 0;
687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 689
2d3ad1f4 690unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 691{
692 if (irqchip_in_kernel(vcpu->kvm))
693 return kvm_lapic_get_cr8(vcpu);
694 else
ad312c7c 695 return vcpu->arch.cr8;
a03490ed 696}
2d3ad1f4 697EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 698
c8639010
JK		 699static void kvm_update_dr7(struct kvm_vcpu *vcpu)
700{
701 unsigned long dr7;
702
703 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
704 dr7 = vcpu->arch.guest_debug_dr7;
705 else
706 dr7 = vcpu->arch.dr7;
707 kvm_x86_ops->set_dr7(vcpu, dr7);
708 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
709}
710
338dbc97 711static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 712{
713 switch (dr) {
714 case 0 ... 3:
715 vcpu->arch.db[dr] = val;
716 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
717 vcpu->arch.eff_db[dr] = val;
718 break;
719 case 4:
338dbc97
GN		 720 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
721 return 1; /* #UD */
020df079
GN		 722 /* fall through */
723 case 6:
338dbc97
GN		 724 if (val & 0xffffffff00000000ULL)
725 return -1; /* #GP */
020df079
GN		 726 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
727 break;
728 case 5:
338dbc97
GN		 729 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
730 return 1; /* #UD */
020df079
GN		 731 /* fall through */
732 default: /* 7 */
338dbc97
GN		 733 if (val & 0xffffffff00000000ULL)
734 return -1; /* #GP */
020df079 735 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 736 kvm_update_dr7(vcpu);
020df079
GN		 737 break;
738 }
739
740 return 0;
741}
338dbc97
GN		 742
743int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
744{
745 int res;
746
747 res = __kvm_set_dr(vcpu, dr, val);
748 if (res > 0)
749 kvm_queue_exception(vcpu, UD_VECTOR);
750 else if (res < 0)
751 kvm_inject_gp(vcpu, 0);
752
753 return res;
754}
020df079
GN		 755EXPORT_SYMBOL_GPL(kvm_set_dr);
756
338dbc97 757static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 758{
759 switch (dr) {
760 case 0 ... 3:
761 *val = vcpu->arch.db[dr];
762 break;
763 case 4:
338dbc97 764 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 765 return 1;
020df079
GN		 766 /* fall through */
767 case 6:
768 *val = vcpu->arch.dr6;
769 break;
770 case 5:
338dbc97 771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 772 return 1;
020df079
GN		 773 /* fall through */
774 default: /* 7 */
775 *val = vcpu->arch.dr7;
776 break;
777 }
778
779 return 0;
780}
338dbc97
GN		 781
782int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
783{
784 if (_kvm_get_dr(vcpu, dr, val)) {
785 kvm_queue_exception(vcpu, UD_VECTOR);
786 return 1;
787 }
788 return 0;
789}
020df079
GN		 790EXPORT_SYMBOL_GPL(kvm_get_dr);
791
022cd0e8
AK		 792bool kvm_rdpmc(struct kvm_vcpu *vcpu)
793{
794 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
795 u64 data;
796 int err;
797
798 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
799 if (err)
800 return err;
801 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
802 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
803 return err;
804}
805EXPORT_SYMBOL_GPL(kvm_rdpmc);
806
043405e1
CO		 807/*
808 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
809 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
810 *
811 * This list is modified at module load time to reflect the
e3267cbb
GC		 812 * capabilities of the host cpu. This capabilities test skips MSRs that are
813 * kvm-specific. Those are put in the beginning of the list.
043405e1 814 */
e3267cbb 815
439793d4 816#define KVM_SAVE_MSRS_BEGIN 10
043405e1 817static u32 msrs_to_save[] = {
e3267cbb 818 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 819 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 820 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 821 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 822 MSR_KVM_PV_EOI_EN,
043405e1 823 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 824 MSR_STAR,
043405e1
CO		 825#ifdef CONFIG_X86_64
826 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
827#endif
e90aa41e 828 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 829};
830
831static unsigned num_msrs_to_save;
832
f1d24831 833static const u32 emulated_msrs[] = {
a3e06bbe 834 MSR_IA32_TSCDEADLINE,
043405e1 835 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 836 MSR_IA32_MCG_STATUS,
837 MSR_IA32_MCG_CTL,
043405e1
CO		 838};
839
b69e8cae 840static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 841{
aad82703
SY		 842 u64 old_efer = vcpu->arch.efer;
843
b69e8cae
RJ		 844 if (efer & efer_reserved_bits)
845 return 1;
15c4a640
CO		 846
847 if (is_paging(vcpu)
b69e8cae
RJ		 848 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
849 return 1;
15c4a640 850
1b2fd70c
AG		 851 if (efer & EFER_FFXSR) {
852 struct kvm_cpuid_entry2 *feat;
853
854 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 855 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
856 return 1;
1b2fd70c
AG		 857 }
858
d8017474
AG		 859 if (efer & EFER_SVME) {
860 struct kvm_cpuid_entry2 *feat;
861
862 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 863 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
864 return 1;
d8017474
AG		 865 }
866
15c4a640 867 efer &= ~EFER_LMA;
f6801dff 868 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 869
a3d204e2
SY		 870 kvm_x86_ops->set_efer(vcpu, efer);
871
9645bb56 872 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 873
aad82703
SY		 874 /* Update reserved bits */
875 if ((efer ^ old_efer) & EFER_NX)
876 kvm_mmu_reset_context(vcpu);
877
b69e8cae 878 return 0;
15c4a640
CO		 879}
880
f2b4b7dd
JR		 881void kvm_enable_efer_bits(u64 mask)
882{
883 efer_reserved_bits &= ~mask;
884}
885EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
886
887
15c4a640
CO		 888/*
889 * Writes msr value into into the appropriate "register".
890 * Returns 0 on success, non-0 otherwise.
891 * Assumes vcpu_load() was already called.
892 */
893int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
894{
895 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
896}
897
313a3dc7
CO		 898/*
899 * Adapt set_msr() to msr_io()'s calling convention
900 */
901static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
902{
903 return kvm_set_msr(vcpu, index, *data);
904}
905
16e8d74d
MT		 906#ifdef CONFIG_X86_64
907struct pvclock_gtod_data {
908 seqcount_t seq;
909
910 struct { /* extract of a clocksource struct */
911 int vclock_mode;
912 cycle_t cycle_last;
913 cycle_t mask;
914 u32 mult;
915 u32 shift;
916 } clock;
917
918 /* open coded 'struct timespec' */
919 u64 monotonic_time_snsec;
920 time_t monotonic_time_sec;
921};
922
923static struct pvclock_gtod_data pvclock_gtod_data;
924
925static void update_pvclock_gtod(struct timekeeper *tk)
926{
927 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
928
929 write_seqcount_begin(&vdata->seq);
930
931 /* copy pvclock gtod data */
932 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
933 vdata->clock.cycle_last = tk->clock->cycle_last;
934 vdata->clock.mask = tk->clock->mask;
935 vdata->clock.mult = tk->mult;
936 vdata->clock.shift = tk->shift;
937
938 vdata->monotonic_time_sec = tk->xtime_sec
939 + tk->wall_to_monotonic.tv_sec;
940 vdata->monotonic_time_snsec = tk->xtime_nsec
941 + (tk->wall_to_monotonic.tv_nsec
942 << tk->shift);
943 while (vdata->monotonic_time_snsec >=
944 (((u64)NSEC_PER_SEC) << tk->shift)) {
945 vdata->monotonic_time_snsec -=
946 ((u64)NSEC_PER_SEC) << tk->shift;
947 vdata->monotonic_time_sec++;
948 }
949
950 write_seqcount_end(&vdata->seq);
951}
952#endif
953
954
18068523
GOC		 955static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
956{
9ed3c444
AK		 957 int version;
958 int r;
50d0a0f9 959 struct pvclock_wall_clock wc;
923de3cf 960 struct timespec boot;
18068523
GOC		 961
962 if (!wall_clock)
963 return;
964
9ed3c444
AK		 965 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
966 if (r)
967 return;
968
969 if (version & 1)
970 ++version; /* first time write, random junk */
971
972 ++version;
18068523 973
18068523
GOC		 974 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
975
50d0a0f9
GH		 976 /*
977 * The guest calculates current wall clock time by adding
34c238a1 978 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 979 * wall clock specified here. guest system time equals host
980 * system time for us, thus we must fill in host boot time here.
981 */
923de3cf 982 getboottime(&boot);
50d0a0f9 983
4b648665
BR		 984 if (kvm->arch.kvmclock_offset) {
985 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
986 boot = timespec_sub(boot, ts);
987 }
50d0a0f9
GH		 988 wc.sec = boot.tv_sec;
989 wc.nsec = boot.tv_nsec;
990 wc.version = version;
18068523
GOC		 991
992 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
993
994 version++;
995 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 996}
997
50d0a0f9
GH		 998static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
999{
1000 uint32_t quotient, remainder;
1001
1002 /* Don't try to replace with do_div(), this one calculates
1003 * "(dividend << 32) / divisor" */
1004 __asm__ ( "divl %4"
1005 : "=a" (quotient), "=d" (remainder)
1006 : "0" (0), "1" (dividend), "r" (divisor) );
1007 return quotient;
1008}
1009
5f4e3f88
ZA		 1010static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1011 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1012{
5f4e3f88 1013 uint64_t scaled64;
50d0a0f9
GH		 1014 int32_t shift = 0;
1015 uint64_t tps64;
1016 uint32_t tps32;
1017
5f4e3f88
ZA		 1018 tps64 = base_khz * 1000LL;
1019 scaled64 = scaled_khz * 1000LL;
50933623 1020 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1021 tps64 >>= 1;
1022 shift--;
1023 }
1024
1025 tps32 = (uint32_t)tps64;
50933623
JK		 1026 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1027 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1028 scaled64 >>= 1;
1029 else
1030 tps32 <<= 1;
50d0a0f9
GH		 1031 shift++;
1032 }
1033
5f4e3f88
ZA		 1034 *pshift = shift;
1035 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1036
5f4e3f88
ZA		 1037 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1038 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1039}
1040
759379dd
ZA		 1041static inline u64 get_kernel_ns(void)
1042{
1043 struct timespec ts;
1044
1045 WARN_ON(preemptible());
1046 ktime_get_ts(&ts);
1047 monotonic_to_bootbased(&ts);
1048 return timespec_to_ns(&ts);
50d0a0f9
GH		 1049}
1050
16e8d74d
MT		 1051static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1052
c8076604 1053static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1054unsigned long max_tsc_khz;
c8076604 1055
cc578287 1056static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1057{
cc578287
ZA		 1058 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1059 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1060}
1061
cc578287 1062static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1063{
cc578287
ZA		 1064 u64 v = (u64)khz * (1000000 + ppm);
1065 do_div(v, 1000000);
1066 return v;
1e993611
JR		 1067}
1068
cc578287 1069static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1070{
cc578287
ZA		 1071 u32 thresh_lo, thresh_hi;
1072 int use_scaling = 0;
217fc9cf 1073
c285545f
ZA		 1074 /* Compute a scale to convert nanoseconds in TSC cycles */
1075 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1076 &vcpu->arch.virtual_tsc_shift,
1077 &vcpu->arch.virtual_tsc_mult);
1078 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1079
1080 /*
1081 * Compute the variation in TSC rate which is acceptable
1082 * within the range of tolerance and decide if the
1083 * rate being applied is within that bounds of the hardware
1084 * rate. If so, no scaling or compensation need be done.
1085 */
1086 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1087 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1088 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1089 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1090 use_scaling = 1;
1091 }
1092 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1093}
1094
1095static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1096{
e26101b1 1097 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1098 vcpu->arch.virtual_tsc_mult,
1099 vcpu->arch.virtual_tsc_shift);
e26101b1 1100 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1101 return tsc;
1102}
1103
99e3e30a
ZA		 1104void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1105{
1106 struct kvm *kvm = vcpu->kvm;
f38e098f 1107 u64 offset, ns, elapsed;
99e3e30a 1108 unsigned long flags;
02626b6a 1109 s64 usdiff;
99e3e30a 1110
038f8c11 1111 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1112 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1113 ns = get_kernel_ns();
f38e098f 1114 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1115
1116 /* n.b - signed multiplication and division required */
02626b6a 1117 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1118#ifdef CONFIG_X86_64
02626b6a 1119 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1120#else
1121 /* do_div() only does unsigned */
1122 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1123 : "=A"(usdiff)
1124 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1125#endif
02626b6a
MT		 1126 do_div(elapsed, 1000);
1127 usdiff -= elapsed;
1128 if (usdiff < 0)
1129 usdiff = -usdiff;
f38e098f
ZA		 1130
1131 /*
5d3cb0f6
ZA		 1132 * Special case: TSC write with a small delta (1 second) of virtual
1133 * cycle time against real time is interpreted as an attempt to
1134 * synchronize the CPU.
1135 *
1136 * For a reliable TSC, we can match TSC offsets, and for an unstable
1137 * TSC, we add elapsed time in this computation. We could let the
1138 * compensation code attempt to catch up if we fall behind, but
1139 * it's better to try to match offsets from the beginning.
1140 */
02626b6a 1141 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1142 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1143 if (!check_tsc_unstable()) {
e26101b1 1144 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1145 pr_debug("kvm: matched tsc offset for %llu\n", data);
1146 } else {
857e4099 1147 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1148 data += delta;
1149 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1150 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1151 }
e26101b1
ZA		 1152 } else {
1153 /*
1154 * We split periods of matched TSC writes into generations.
1155 * For each generation, we track the original measured
1156 * nanosecond time, offset, and write, so if TSCs are in
1157 * sync, we can match exact offset, and if not, we can match
4a969980 1158 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1159 *
1160 * These values are tracked in kvm->arch.cur_xxx variables.
1161 */
1162 kvm->arch.cur_tsc_generation++;
1163 kvm->arch.cur_tsc_nsec = ns;
1164 kvm->arch.cur_tsc_write = data;
1165 kvm->arch.cur_tsc_offset = offset;
1166 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1167 kvm->arch.cur_tsc_generation, data);
f38e098f 1168 }
e26101b1
ZA		 1169
1170 /*
1171 * We also track th most recent recorded KHZ, write and time to
1172 * allow the matching interval to be extended at each write.
1173 */
f38e098f
ZA		 1174 kvm->arch.last_tsc_nsec = ns;
1175 kvm->arch.last_tsc_write = data;
5d3cb0f6 1176 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1177
1178 /* Reset of TSC must disable overshoot protection below */
1179 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1180 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1181
1182 /* Keep track of which generation this VCPU has synchronized to */
1183 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1184 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1185 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1186
1187 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1188 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1189}
e26101b1 1190
99e3e30a
ZA		 1191EXPORT_SYMBOL_GPL(kvm_write_tsc);
1192
34c238a1 1193static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1194{
18068523
GOC		 1195 unsigned long flags;
1196 struct kvm_vcpu_arch *vcpu = &v->arch;
1197 void *shared_kaddr;
463656c0 1198 unsigned long this_tsc_khz;
1d5f066e
ZA		 1199 s64 kernel_ns, max_kernel_ns;
1200 u64 tsc_timestamp;
78c0337a 1201 struct pvclock_vcpu_time_info *guest_hv_clock;
51d59c6b 1202 u8 pvclock_flags;
18068523 1203
18068523
GOC		 1204 /* Keep irq disabled to prevent changes to the clock */
1205 local_irq_save(flags);
886b470c 1206 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, native_read_tsc());
759379dd 1207 kernel_ns = get_kernel_ns();
cc578287 1208 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1209 if (unlikely(this_tsc_khz == 0)) {
c285545f 1210 local_irq_restore(flags);
34c238a1 1211 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1212 return 1;
1213 }
18068523 1214
c285545f
ZA		 1215 /*
1216 * We may have to catch up the TSC to match elapsed wall clock
1217 * time for two reasons, even if kvmclock is used.
1218 * 1) CPU could have been running below the maximum TSC rate
1219 * 2) Broken TSC compensation resets the base at each VCPU
1220 * entry to avoid unknown leaps of TSC even when running
1221 * again on the same CPU. This may cause apparent elapsed
1222 * time to disappear, and the guest to stand still or run
1223 * very slowly.
1224 */
1225 if (vcpu->tsc_catchup) {
1226 u64 tsc = compute_guest_tsc(v, kernel_ns);
1227 if (tsc > tsc_timestamp) {
f1e2b260 1228 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1229 tsc_timestamp = tsc;
1230 }
50d0a0f9
GH		 1231 }
1232
18068523
GOC		 1233 local_irq_restore(flags);
1234
c285545f
ZA		 1235 if (!vcpu->time_page)
1236 return 0;
18068523 1237
1d5f066e
ZA		 1238 /*
1239 * Time as measured by the TSC may go backwards when resetting the base
1240 * tsc_timestamp. The reason for this is that the TSC resolution is
1241 * higher than the resolution of the other clock scales. Thus, many
1242 * possible measurments of the TSC correspond to one measurement of any
1243 * other clock, and so a spread of values is possible. This is not a
1244 * problem for the computation of the nanosecond clock; with TSC rates
1245 * around 1GHZ, there can only be a few cycles which correspond to one
1246 * nanosecond value, and any path through this code will inevitably
1247 * take longer than that. However, with the kernel_ns value itself,
1248 * the precision may be much lower, down to HZ granularity. If the
1249 * first sampling of TSC against kernel_ns ends in the low part of the
1250 * range, and the second in the high end of the range, we can get:
1251 *
1252 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1253 *
1254 * As the sampling errors potentially range in the thousands of cycles,
1255 * it is possible such a time value has already been observed by the
1256 * guest. To protect against this, we must compute the system time as
1257 * observed by the guest and ensure the new system time is greater.
1258 */
1259 max_kernel_ns = 0;
b183aa58 1260 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1261 max_kernel_ns = vcpu->last_guest_tsc -
1262 vcpu->hv_clock.tsc_timestamp;
1263 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1264 vcpu->hv_clock.tsc_to_system_mul,
1265 vcpu->hv_clock.tsc_shift);
1266 max_kernel_ns += vcpu->last_kernel_ns;
1267 }
afbcf7ab 1268
e48672fa 1269 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1270 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1271 &vcpu->hv_clock.tsc_shift,
1272 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1273 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1274 }
1275
1d5f066e
ZA		 1276 if (max_kernel_ns > kernel_ns)
1277 kernel_ns = max_kernel_ns;
1278
8cfdc000 1279 /* With all the info we got, fill in the values */
1d5f066e 1280 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1281 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1282 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1283 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1284
18068523
GOC		 1285 /*
1286 * The interface expects us to write an even number signaling that the
1287 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1288 * state, we just increase by 2 at the end.
18068523 1289 */
50d0a0f9 1290 vcpu->hv_clock.version += 2;
18068523 1291
8fd75e12 1292 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523 1293
78c0337a
MT		 1294 guest_hv_clock = shared_kaddr + vcpu->time_offset;
1295
1296 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1297 pvclock_flags = (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
1298
1299 if (vcpu->pvclock_set_guest_stopped_request) {
1300 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1301 vcpu->pvclock_set_guest_stopped_request = false;
1302 }
1303
1304 vcpu->hv_clock.flags = pvclock_flags;
1305
18068523 1306 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1307 sizeof(vcpu->hv_clock));
18068523 1308
8fd75e12 1309 kunmap_atomic(shared_kaddr);
18068523
GOC		 1310
1311 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1312 return 0;
c8076604
GH		 1313}
1314
9ba075a6
AK		 1315static bool msr_mtrr_valid(unsigned msr)
1316{
1317 switch (msr) {
1318 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1319 case MSR_MTRRfix64K_00000:
1320 case MSR_MTRRfix16K_80000:
1321 case MSR_MTRRfix16K_A0000:
1322 case MSR_MTRRfix4K_C0000:
1323 case MSR_MTRRfix4K_C8000:
1324 case MSR_MTRRfix4K_D0000:
1325 case MSR_MTRRfix4K_D8000:
1326 case MSR_MTRRfix4K_E0000:
1327 case MSR_MTRRfix4K_E8000:
1328 case MSR_MTRRfix4K_F0000:
1329 case MSR_MTRRfix4K_F8000:
1330 case MSR_MTRRdefType:
1331 case MSR_IA32_CR_PAT:
1332 return true;
1333 case 0x2f8:
1334 return true;
1335 }
1336 return false;
1337}
1338
d6289b93
MT		 1339static bool valid_pat_type(unsigned t)
1340{
1341 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1342}
1343
1344static bool valid_mtrr_type(unsigned t)
1345{
1346 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1347}
1348
1349static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1350{
1351 int i;
1352
1353 if (!msr_mtrr_valid(msr))
1354 return false;
1355
1356 if (msr == MSR_IA32_CR_PAT) {
1357 for (i = 0; i < 8; i++)
1358 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1359 return false;
1360 return true;
1361 } else if (msr == MSR_MTRRdefType) {
1362 if (data & ~0xcff)
1363 return false;
1364 return valid_mtrr_type(data & 0xff);
1365 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1366 for (i = 0; i < 8 ; i++)
1367 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1368 return false;
1369 return true;
1370 }
1371
1372 /* variable MTRRs */
1373 return valid_mtrr_type(data & 0xff);
1374}
1375
9ba075a6
AK		 1376static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1377{
0bed3b56
SY		 1378 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1379
d6289b93 1380 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1381 return 1;
1382
0bed3b56
SY		 1383 if (msr == MSR_MTRRdefType) {
1384 vcpu->arch.mtrr_state.def_type = data;
1385 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1386 } else if (msr == MSR_MTRRfix64K_00000)
1387 p[0] = data;
1388 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1389 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1390 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1391 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1392 else if (msr == MSR_IA32_CR_PAT)
1393 vcpu->arch.pat = data;
1394 else { /* Variable MTRRs */
1395 int idx, is_mtrr_mask;
1396 u64 *pt;
1397
1398 idx = (msr - 0x200) / 2;
1399 is_mtrr_mask = msr - 0x200 - 2 * idx;
1400 if (!is_mtrr_mask)
1401 pt =
1402 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1403 else
1404 pt =
1405 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1406 *pt = data;
1407 }
1408
1409 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1410 return 0;
1411}
15c4a640 1412
890ca9ae 1413static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1414{
890ca9ae
HY		 1415 u64 mcg_cap = vcpu->arch.mcg_cap;
1416 unsigned bank_num = mcg_cap & 0xff;
1417
15c4a640 1418 switch (msr) {
15c4a640 1419 case MSR_IA32_MCG_STATUS:
890ca9ae 1420 vcpu->arch.mcg_status = data;
15c4a640 1421 break;
c7ac679c 1422 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1423 if (!(mcg_cap & MCG_CTL_P))
1424 return 1;
1425 if (data != 0 && data != ~(u64)0)
1426 return -1;
1427 vcpu->arch.mcg_ctl = data;
1428 break;
1429 default:
1430 if (msr >= MSR_IA32_MC0_CTL &&
1431 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1432 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1433 /* only 0 or all 1s can be written to IA32_MCi_CTL
1434 * some Linux kernels though clear bit 10 in bank 4 to
1435 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1436 * this to avoid an uncatched #GP in the guest
1437 */
890ca9ae 1438 if ((offset & 0x3) == 0 &&
114be429 1439 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1440 return -1;
1441 vcpu->arch.mce_banks[offset] = data;
1442 break;
1443 }
1444 return 1;
1445 }
1446 return 0;
1447}
1448
ffde22ac
ES		 1449static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1450{
1451 struct kvm *kvm = vcpu->kvm;
1452 int lm = is_long_mode(vcpu);
1453 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1454 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1455 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1456 : kvm->arch.xen_hvm_config.blob_size_32;
1457 u32 page_num = data & ~PAGE_MASK;
1458 u64 page_addr = data & PAGE_MASK;
1459 u8 *page;
1460 int r;
1461
1462 r = -E2BIG;
1463 if (page_num >= blob_size)
1464 goto out;
1465 r = -ENOMEM;
ff5c2c03
SL		 1466 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1467 if (IS_ERR(page)) {
1468 r = PTR_ERR(page);
ffde22ac 1469 goto out;
ff5c2c03 1470 }
ffde22ac
ES		 1471 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1472 goto out_free;
1473 r = 0;
1474out_free:
1475 kfree(page);
1476out:
1477 return r;
1478}
1479
55cd8e5a
GN		 1480static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1481{
1482 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1483}
1484
1485static bool kvm_hv_msr_partition_wide(u32 msr)
1486{
1487 bool r = false;
1488 switch (msr) {
1489 case HV_X64_MSR_GUEST_OS_ID:
1490 case HV_X64_MSR_HYPERCALL:
1491 r = true;
1492 break;
1493 }
1494
1495 return r;
1496}
1497
1498static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1499{
1500 struct kvm *kvm = vcpu->kvm;
1501
1502 switch (msr) {
1503 case HV_X64_MSR_GUEST_OS_ID:
1504 kvm->arch.hv_guest_os_id = data;
1505 /* setting guest os id to zero disables hypercall page */
1506 if (!kvm->arch.hv_guest_os_id)
1507 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1508 break;
1509 case HV_X64_MSR_HYPERCALL: {
1510 u64 gfn;
1511 unsigned long addr;
1512 u8 instructions[4];
1513
1514 /* if guest os id is not set hypercall should remain disabled */
1515 if (!kvm->arch.hv_guest_os_id)
1516 break;
1517 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1518 kvm->arch.hv_hypercall = data;
1519 break;
1520 }
1521 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1522 addr = gfn_to_hva(kvm, gfn);
1523 if (kvm_is_error_hva(addr))
1524 return 1;
1525 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1526 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1527 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1528 return 1;
1529 kvm->arch.hv_hypercall = data;
1530 break;
1531 }
1532 default:
a737f256
CD		 1533 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1534 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1535 return 1;
1536 }
1537 return 0;
1538}
1539
1540static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1541{
10388a07
GN		 1542 switch (msr) {
1543 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1544 unsigned long addr;
55cd8e5a 1545
10388a07
GN		 1546 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1547 vcpu->arch.hv_vapic = data;
1548 break;
1549 }
1550 addr = gfn_to_hva(vcpu->kvm, data >>
1551 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1552 if (kvm_is_error_hva(addr))
1553 return 1;
8b0cedff 1554 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1555 return 1;
1556 vcpu->arch.hv_vapic = data;
1557 break;
1558 }
1559 case HV_X64_MSR_EOI:
1560 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1561 case HV_X64_MSR_ICR:
1562 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1563 case HV_X64_MSR_TPR:
1564 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1565 default:
a737f256
CD		 1566 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1567 "data 0x%llx\n", msr, data);
10388a07
GN		 1568 return 1;
1569 }
1570
1571 return 0;
55cd8e5a
GN		 1572}
1573
344d9588
GN		 1574static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1575{
1576 gpa_t gpa = data & ~0x3f;
1577
4a969980 1578 /* Bits 2:5 are reserved, Should be zero */
6adba527 1579 if (data & 0x3c)
344d9588
GN		 1580 return 1;
1581
1582 vcpu->arch.apf.msr_val = data;
1583
1584 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1585 kvm_clear_async_pf_completion_queue(vcpu);
1586 kvm_async_pf_hash_reset(vcpu);
1587 return 0;
1588 }
1589
1590 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1591 return 1;
1592
6adba527 1593 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1594 kvm_async_pf_wakeup_all(vcpu);
1595 return 0;
1596}
1597
12f9a48f
GC		 1598static void kvmclock_reset(struct kvm_vcpu *vcpu)
1599{
1600 if (vcpu->arch.time_page) {
1601 kvm_release_page_dirty(vcpu->arch.time_page);
1602 vcpu->arch.time_page = NULL;
1603 }
1604}
1605
c9aaa895
GC		 1606static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1607{
1608 u64 delta;
1609
1610 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1611 return;
1612
1613 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1614 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1615 vcpu->arch.st.accum_steal = delta;
1616}
1617
1618static void record_steal_time(struct kvm_vcpu *vcpu)
1619{
1620 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1621 return;
1622
1623 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1624 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1625 return;
1626
1627 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1628 vcpu->arch.st.steal.version += 2;
1629 vcpu->arch.st.accum_steal = 0;
1630
1631 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1632 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1633}
1634
15c4a640
CO		 1635int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1636{
5753785f
GN		 1637 bool pr = false;
1638
15c4a640 1639 switch (msr) {
15c4a640 1640 case MSR_EFER:
b69e8cae 1641 return set_efer(vcpu, data);
8f1589d9
AP		 1642 case MSR_K7_HWCR:
1643 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1644 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1645 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1646 if (data != 0) {
a737f256
CD		 1647 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1648 data);
8f1589d9
AP		 1649 return 1;
1650 }
15c4a640 1651 break;
f7c6d140
AP		 1652 case MSR_FAM10H_MMIO_CONF_BASE:
1653 if (data != 0) {
a737f256
CD		 1654 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1655 "0x%llx\n", data);
f7c6d140
AP		 1656 return 1;
1657 }
15c4a640 1658 break;
c323c0e5 1659 case MSR_AMD64_NB_CFG:
c7ac679c 1660 break;
b5e2fec0
AG		 1661 case MSR_IA32_DEBUGCTLMSR:
1662 if (!data) {
1663 /* We support the non-activated case already */
1664 break;
1665 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1666 /* Values other than LBR and BTF are vendor-specific,
1667 thus reserved and should throw a #GP */
1668 return 1;
1669 }
a737f256
CD		 1670 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1671 __func__, data);
b5e2fec0 1672 break;
15c4a640
CO		 1673 case MSR_IA32_UCODE_REV:
1674 case MSR_IA32_UCODE_WRITE:
61a6bd67 1675 case MSR_VM_HSAVE_PA:
6098ca93 1676 case MSR_AMD64_PATCH_LOADER:
15c4a640 1677 break;
9ba075a6
AK		 1678 case 0x200 ... 0x2ff:
1679 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1680 case MSR_IA32_APICBASE:
1681 kvm_set_apic_base(vcpu, data);
1682 break;
0105d1a5
GN		 1683 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1684 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1685 case MSR_IA32_TSCDEADLINE:
1686 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1687 break;
15c4a640 1688 case MSR_IA32_MISC_ENABLE:
ad312c7c 1689 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1690 break;
11c6bffa 1691 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1692 case MSR_KVM_WALL_CLOCK:
1693 vcpu->kvm->arch.wall_clock = data;
1694 kvm_write_wall_clock(vcpu->kvm, data);
1695 break;
11c6bffa 1696 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1697 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1698 kvmclock_reset(vcpu);
18068523
GOC		 1699
1700 vcpu->arch.time = data;
c285545f 1701 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1702
1703 /* we verify if the enable bit is set... */
1704 if (!(data & 1))
1705 break;
1706
1707 /* ...but clean it before doing the actual write */
1708 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1709
18068523
GOC		 1710 vcpu->arch.time_page =
1711 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523 1712
32cad84f 1713 if (is_error_page(vcpu->arch.time_page))
18068523 1714 vcpu->arch.time_page = NULL;
32cad84f 1715
18068523
GOC		 1716 break;
1717 }
344d9588
GN		 1718 case MSR_KVM_ASYNC_PF_EN:
1719 if (kvm_pv_enable_async_pf(vcpu, data))
1720 return 1;
1721 break;
c9aaa895
GC		 1722 case MSR_KVM_STEAL_TIME:
1723
1724 if (unlikely(!sched_info_on()))
1725 return 1;
1726
1727 if (data & KVM_STEAL_RESERVED_MASK)
1728 return 1;
1729
1730 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1731 data & KVM_STEAL_VALID_BITS))
1732 return 1;
1733
1734 vcpu->arch.st.msr_val = data;
1735
1736 if (!(data & KVM_MSR_ENABLED))
1737 break;
1738
1739 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1740
1741 preempt_disable();
1742 accumulate_steal_time(vcpu);
1743 preempt_enable();
1744
1745 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1746
1747 break;
ae7a2a3f
MT		 1748 case MSR_KVM_PV_EOI_EN:
1749 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1750 return 1;
1751 break;
c9aaa895 1752
890ca9ae
HY		 1753 case MSR_IA32_MCG_CTL:
1754 case MSR_IA32_MCG_STATUS:
1755 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1756 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1757
1758 /* Performance counters are not protected by a CPUID bit,
1759 * so we should check all of them in the generic path for the sake of
1760 * cross vendor migration.
1761 * Writing a zero into the event select MSRs disables them,
1762 * which we perfectly emulate ;-). Any other value should be at least
1763 * reported, some guests depend on them.
1764 */
71db6023
AP		 1765 case MSR_K7_EVNTSEL0:
1766 case MSR_K7_EVNTSEL1:
1767 case MSR_K7_EVNTSEL2:
1768 case MSR_K7_EVNTSEL3:
1769 if (data != 0)
a737f256
CD		 1770 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1771 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 1772 break;
1773 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1774 * so we ignore writes to make it happy.
1775 */
71db6023
AP		 1776 case MSR_K7_PERFCTR0:
1777 case MSR_K7_PERFCTR1:
1778 case MSR_K7_PERFCTR2:
1779 case MSR_K7_PERFCTR3:
a737f256
CD		 1780 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1781 "0x%x data 0x%llx\n", msr, data);
71db6023 1782 break;
5753785f
GN		 1783 case MSR_P6_PERFCTR0:
1784 case MSR_P6_PERFCTR1:
1785 pr = true;
1786 case MSR_P6_EVNTSEL0:
1787 case MSR_P6_EVNTSEL1:
1788 if (kvm_pmu_msr(vcpu, msr))
1789 return kvm_pmu_set_msr(vcpu, msr, data);
1790
1791 if (pr || data != 0)
a737f256
CD		 1792 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1793 "0x%x data 0x%llx\n", msr, data);
5753785f 1794 break;
84e0cefa
JS		 1795 case MSR_K7_CLK_CTL:
1796 /*
1797 * Ignore all writes to this no longer documented MSR.
1798 * Writes are only relevant for old K7 processors,
1799 * all pre-dating SVM, but a recommended workaround from
4a969980 1800 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 1801 * affected processor models on the command line, hence
1802 * the need to ignore the workaround.
1803 */
1804 break;
55cd8e5a
GN		 1805 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1806 if (kvm_hv_msr_partition_wide(msr)) {
1807 int r;
1808 mutex_lock(&vcpu->kvm->lock);
1809 r = set_msr_hyperv_pw(vcpu, msr, data);
1810 mutex_unlock(&vcpu->kvm->lock);
1811 return r;
1812 } else
1813 return set_msr_hyperv(vcpu, msr, data);
1814 break;
91c9c3ed 1815 case MSR_IA32_BBL_CR_CTL3:
1816 /* Drop writes to this legacy MSR -- see rdmsr
1817 * counterpart for further detail.
1818 */
a737f256 1819 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 1820 break;
2b036c6b
BO		 1821 case MSR_AMD64_OSVW_ID_LENGTH:
1822 if (!guest_cpuid_has_osvw(vcpu))
1823 return 1;
1824 vcpu->arch.osvw.length = data;
1825 break;
1826 case MSR_AMD64_OSVW_STATUS:
1827 if (!guest_cpuid_has_osvw(vcpu))
1828 return 1;
1829 vcpu->arch.osvw.status = data;
1830 break;
15c4a640 1831 default:
ffde22ac
ES		 1832 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1833 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1834 if (kvm_pmu_msr(vcpu, msr))
1835 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 1836 if (!ignore_msrs) {
a737f256
CD		 1837 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1838 msr, data);
ed85c068
AP		 1839 return 1;
1840 } else {
a737f256
CD		 1841 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1842 msr, data);
ed85c068
AP		 1843 break;
1844 }
15c4a640
CO		 1845 }
1846 return 0;
1847}
1848EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1849
1850
1851/*
1852 * Reads an msr value (of 'msr_index') into 'pdata'.
1853 * Returns 0 on success, non-0 otherwise.
1854 * Assumes vcpu_load() was already called.
1855 */
1856int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1857{
1858 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1859}
1860
9ba075a6
AK		 1861static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1862{
0bed3b56
SY		 1863 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1864
9ba075a6
AK		 1865 if (!msr_mtrr_valid(msr))
1866 return 1;
1867
0bed3b56
SY		 1868 if (msr == MSR_MTRRdefType)
1869 *pdata = vcpu->arch.mtrr_state.def_type +
1870 (vcpu->arch.mtrr_state.enabled << 10);
1871 else if (msr == MSR_MTRRfix64K_00000)
1872 *pdata = p[0];
1873 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1874 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1875 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1876 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1877 else if (msr == MSR_IA32_CR_PAT)
1878 *pdata = vcpu->arch.pat;
1879 else { /* Variable MTRRs */
1880 int idx, is_mtrr_mask;
1881 u64 *pt;
1882
1883 idx = (msr - 0x200) / 2;
1884 is_mtrr_mask = msr - 0x200 - 2 * idx;
1885 if (!is_mtrr_mask)
1886 pt =
1887 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1888 else
1889 pt =
1890 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1891 *pdata = *pt;
1892 }
1893
9ba075a6
AK		 1894 return 0;
1895}
1896
890ca9ae 1897static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1898{
1899 u64 data;
890ca9ae
HY		 1900 u64 mcg_cap = vcpu->arch.mcg_cap;
1901 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1902
1903 switch (msr) {
15c4a640
CO		 1904 case MSR_IA32_P5_MC_ADDR:
1905 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1906 data = 0;
1907 break;
15c4a640 1908 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1909 data = vcpu->arch.mcg_cap;
1910 break;
c7ac679c 1911 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1912 if (!(mcg_cap & MCG_CTL_P))
1913 return 1;
1914 data = vcpu->arch.mcg_ctl;
1915 break;
1916 case MSR_IA32_MCG_STATUS:
1917 data = vcpu->arch.mcg_status;
1918 break;
1919 default:
1920 if (msr >= MSR_IA32_MC0_CTL &&
1921 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1922 u32 offset = msr - MSR_IA32_MC0_CTL;
1923 data = vcpu->arch.mce_banks[offset];
1924 break;
1925 }
1926 return 1;
1927 }
1928 *pdata = data;
1929 return 0;
1930}
1931
55cd8e5a
GN		 1932static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1933{
1934 u64 data = 0;
1935 struct kvm *kvm = vcpu->kvm;
1936
1937 switch (msr) {
1938 case HV_X64_MSR_GUEST_OS_ID:
1939 data = kvm->arch.hv_guest_os_id;
1940 break;
1941 case HV_X64_MSR_HYPERCALL:
1942 data = kvm->arch.hv_hypercall;
1943 break;
1944 default:
a737f256 1945 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1946 return 1;
1947 }
1948
1949 *pdata = data;
1950 return 0;
1951}
1952
1953static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1954{
1955 u64 data = 0;
1956
1957 switch (msr) {
1958 case HV_X64_MSR_VP_INDEX: {
1959 int r;
1960 struct kvm_vcpu *v;
1961 kvm_for_each_vcpu(r, v, vcpu->kvm)
1962 if (v == vcpu)
1963 data = r;
1964 break;
1965 }
10388a07
GN		 1966 case HV_X64_MSR_EOI:
1967 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1968 case HV_X64_MSR_ICR:
1969 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1970 case HV_X64_MSR_TPR:
1971 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1972 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1973 data = vcpu->arch.hv_vapic;
1974 break;
55cd8e5a 1975 default:
a737f256 1976 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1977 return 1;
1978 }
1979 *pdata = data;
1980 return 0;
1981}
1982
890ca9ae
HY		 1983int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1984{
1985 u64 data;
1986
1987 switch (msr) {
890ca9ae 1988 case MSR_IA32_PLATFORM_ID:
15c4a640 1989 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1990 case MSR_IA32_DEBUGCTLMSR:
1991 case MSR_IA32_LASTBRANCHFROMIP:
1992 case MSR_IA32_LASTBRANCHTOIP:
1993 case MSR_IA32_LASTINTFROMIP:
1994 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1995 case MSR_K8_SYSCFG:
1996 case MSR_K7_HWCR:
61a6bd67 1997 case MSR_VM_HSAVE_PA:
9e699624 1998 case MSR_K7_EVNTSEL0:
1f3ee616 1999 case MSR_K7_PERFCTR0:
1fdbd48c 2000 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2001 case MSR_AMD64_NB_CFG:
f7c6d140 2002 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 2003 data = 0;
2004 break;
5753785f
GN		 2005 case MSR_P6_PERFCTR0:
2006 case MSR_P6_PERFCTR1:
2007 case MSR_P6_EVNTSEL0:
2008 case MSR_P6_EVNTSEL1:
2009 if (kvm_pmu_msr(vcpu, msr))
2010 return kvm_pmu_get_msr(vcpu, msr, pdata);
2011 data = 0;
2012 break;
742bc670
MT		 2013 case MSR_IA32_UCODE_REV:
2014 data = 0x100000000ULL;
2015 break;
9ba075a6
AK		 2016 case MSR_MTRRcap:
2017 data = 0x500 | KVM_NR_VAR_MTRR;
2018 break;
2019 case 0x200 ... 0x2ff:
2020 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2021 case 0xcd: /* fsb frequency */
2022 data = 3;
2023 break;
7b914098
JS		 2024 /*
2025 * MSR_EBC_FREQUENCY_ID
2026 * Conservative value valid for even the basic CPU models.
2027 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2028 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2029 * and 266MHz for model 3, or 4. Set Core Clock
2030 * Frequency to System Bus Frequency Ratio to 1 (bits
2031 * 31:24) even though these are only valid for CPU
2032 * models > 2, however guests may end up dividing or
2033 * multiplying by zero otherwise.
2034 */
2035 case MSR_EBC_FREQUENCY_ID:
2036 data = 1 << 24;
2037 break;
15c4a640
CO		 2038 case MSR_IA32_APICBASE:
2039 data = kvm_get_apic_base(vcpu);
2040 break;
0105d1a5
GN		 2041 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2042 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2043 break;
a3e06bbe
LJ		 2044 case MSR_IA32_TSCDEADLINE:
2045 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2046 break;
15c4a640 2047 case MSR_IA32_MISC_ENABLE:
ad312c7c 2048 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2049 break;
847f0ad8
AG		 2050 case MSR_IA32_PERF_STATUS:
2051 /* TSC increment by tick */
2052 data = 1000ULL;
2053 /* CPU multiplier */
2054 data |= (((uint64_t)4ULL) << 40);
2055 break;
15c4a640 2056 case MSR_EFER:
f6801dff 2057 data = vcpu->arch.efer;
15c4a640 2058 break;
18068523 2059 case MSR_KVM_WALL_CLOCK:
11c6bffa 2060 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2061 data = vcpu->kvm->arch.wall_clock;
2062 break;
2063 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2064 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2065 data = vcpu->arch.time;
2066 break;
344d9588
GN		 2067 case MSR_KVM_ASYNC_PF_EN:
2068 data = vcpu->arch.apf.msr_val;
2069 break;
c9aaa895
GC		 2070 case MSR_KVM_STEAL_TIME:
2071 data = vcpu->arch.st.msr_val;
2072 break;
1d92128f
MT		 2073 case MSR_KVM_PV_EOI_EN:
2074 data = vcpu->arch.pv_eoi.msr_val;
2075 break;
890ca9ae
HY		 2076 case MSR_IA32_P5_MC_ADDR:
2077 case MSR_IA32_P5_MC_TYPE:
2078 case MSR_IA32_MCG_CAP:
2079 case MSR_IA32_MCG_CTL:
2080 case MSR_IA32_MCG_STATUS:
2081 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2082 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2083 case MSR_K7_CLK_CTL:
2084 /*
2085 * Provide expected ramp-up count for K7. All other
2086 * are set to zero, indicating minimum divisors for
2087 * every field.
2088 *
2089 * This prevents guest kernels on AMD host with CPU
2090 * type 6, model 8 and higher from exploding due to
2091 * the rdmsr failing.
2092 */
2093 data = 0x20000000;
2094 break;
55cd8e5a
GN		 2095 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2096 if (kvm_hv_msr_partition_wide(msr)) {
2097 int r;
2098 mutex_lock(&vcpu->kvm->lock);
2099 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2100 mutex_unlock(&vcpu->kvm->lock);
2101 return r;
2102 } else
2103 return get_msr_hyperv(vcpu, msr, pdata);
2104 break;
91c9c3ed 2105 case MSR_IA32_BBL_CR_CTL3:
2106 /* This legacy MSR exists but isn't fully documented in current
2107 * silicon. It is however accessed by winxp in very narrow
2108 * scenarios where it sets bit #19, itself documented as
2109 * a "reserved" bit. Best effort attempt to source coherent
2110 * read data here should the balance of the register be
2111 * interpreted by the guest:
2112 *
2113 * L2 cache control register 3: 64GB range, 256KB size,
2114 * enabled, latency 0x1, configured
2115 */
2116 data = 0xbe702111;
2117 break;
2b036c6b
BO		 2118 case MSR_AMD64_OSVW_ID_LENGTH:
2119 if (!guest_cpuid_has_osvw(vcpu))
2120 return 1;
2121 data = vcpu->arch.osvw.length;
2122 break;
2123 case MSR_AMD64_OSVW_STATUS:
2124 if (!guest_cpuid_has_osvw(vcpu))
2125 return 1;
2126 data = vcpu->arch.osvw.status;
2127 break;
15c4a640 2128 default:
f5132b01
GN		 2129 if (kvm_pmu_msr(vcpu, msr))
2130 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2131 if (!ignore_msrs) {
a737f256 2132 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2133 return 1;
2134 } else {
a737f256 2135 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2136 data = 0;
2137 }
2138 break;
15c4a640
CO		 2139 }
2140 *pdata = data;
2141 return 0;
2142}
2143EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2144
313a3dc7
CO		 2145/*
2146 * Read or write a bunch of msrs. All parameters are kernel addresses.
2147 *
2148 * @return number of msrs set successfully.
2149 */
2150static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2151 struct kvm_msr_entry *entries,
2152 int (*do_msr)(struct kvm_vcpu *vcpu,
2153 unsigned index, u64 *data))
2154{
f656ce01 2155 int i, idx;
313a3dc7 2156
f656ce01 2157 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2158 for (i = 0; i < msrs->nmsrs; ++i)
2159 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2160 break;
f656ce01 2161 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2162
313a3dc7
CO		 2163 return i;
2164}
2165
2166/*
2167 * Read or write a bunch of msrs. Parameters are user addresses.
2168 *
2169 * @return number of msrs set successfully.
2170 */
2171static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2172 int (*do_msr)(struct kvm_vcpu *vcpu,
2173 unsigned index, u64 *data),
2174 int writeback)
2175{
2176 struct kvm_msrs msrs;
2177 struct kvm_msr_entry *entries;
2178 int r, n;
2179 unsigned size;
2180
2181 r = -EFAULT;
2182 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2183 goto out;
2184
2185 r = -E2BIG;
2186 if (msrs.nmsrs >= MAX_IO_MSRS)
2187 goto out;
2188
313a3dc7 2189 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2190 entries = memdup_user(user_msrs->entries, size);
2191 if (IS_ERR(entries)) {
2192 r = PTR_ERR(entries);
313a3dc7 2193 goto out;
ff5c2c03 2194 }
313a3dc7
CO		 2195
2196 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2197 if (r < 0)
2198 goto out_free;
2199
2200 r = -EFAULT;
2201 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2202 goto out_free;
2203
2204 r = n;
2205
2206out_free:
7a73c028 2207 kfree(entries);
313a3dc7
CO		 2208out:
2209 return r;
2210}
2211
018d00d2
ZX		 2212int kvm_dev_ioctl_check_extension(long ext)
2213{
2214 int r;
2215
2216 switch (ext) {
2217 case KVM_CAP_IRQCHIP:
2218 case KVM_CAP_HLT:
2219 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2220 case KVM_CAP_SET_TSS_ADDR:
07716717 2221 case KVM_CAP_EXT_CPUID:
c8076604 2222 case KVM_CAP_CLOCKSOURCE:
7837699f 2223 case KVM_CAP_PIT:
a28e4f5a 2224 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2225 case KVM_CAP_MP_STATE:
ed848624 2226 case KVM_CAP_SYNC_MMU:
a355c85c 2227 case KVM_CAP_USER_NMI:
52d939a0 2228 case KVM_CAP_REINJECT_CONTROL:
4925663a 2229 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2230 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2231 case KVM_CAP_IRQFD:
d34e6b17 2232 case KVM_CAP_IOEVENTFD:
c5ff41ce 2233 case KVM_CAP_PIT2:
e9f42757 2234 case KVM_CAP_PIT_STATE2:
b927a3ce 2235 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2236 case KVM_CAP_XEN_HVM:
afbcf7ab 2237 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2238 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2239 case KVM_CAP_HYPERV:
10388a07 2240 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2241 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2242 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2243 case KVM_CAP_DEBUGREGS:
d2be1651 2244 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2245 case KVM_CAP_XSAVE:
344d9588 2246 case KVM_CAP_ASYNC_PF:
92a1f12d 2247 case KVM_CAP_GET_TSC_KHZ:
07700a94 2248 case KVM_CAP_PCI_2_3:
1c0b28c2 2249 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2250 case KVM_CAP_READONLY_MEM:
7a84428a 2251 case KVM_CAP_IRQFD_RESAMPLE:
018d00d2
ZX		 2252 r = 1;
2253 break;
542472b5
LV		 2254 case KVM_CAP_COALESCED_MMIO:
2255 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2256 break;
774ead3a
AK		 2257 case KVM_CAP_VAPIC:
2258 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2259 break;
f725230a 2260 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2261 r = KVM_SOFT_MAX_VCPUS;
2262 break;
2263 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2264 r = KVM_MAX_VCPUS;
2265 break;
a988b910
AK		 2266 case KVM_CAP_NR_MEMSLOTS:
2267 r = KVM_MEMORY_SLOTS;
2268 break;
a68a6a72
MT		 2269 case KVM_CAP_PV_MMU: /* obsolete */
2270 r = 0;
2f333bcb 2271 break;
62c476c7 2272 case KVM_CAP_IOMMU:
a1b60c1c 2273 r = iommu_present(&pci_bus_type);
62c476c7 2274 break;
890ca9ae
HY		 2275 case KVM_CAP_MCE:
2276 r = KVM_MAX_MCE_BANKS;
2277 break;
2d5b5a66
SY		 2278 case KVM_CAP_XCRS:
2279 r = cpu_has_xsave;
2280 break;
92a1f12d
JR		 2281 case KVM_CAP_TSC_CONTROL:
2282 r = kvm_has_tsc_control;
2283 break;
4d25a066
JK		 2284 case KVM_CAP_TSC_DEADLINE_TIMER:
2285 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2286 break;
018d00d2
ZX		 2287 default:
2288 r = 0;
2289 break;
2290 }
2291 return r;
2292
2293}
2294
043405e1
CO		 2295long kvm_arch_dev_ioctl(struct file *filp,
2296 unsigned int ioctl, unsigned long arg)
2297{
2298 void __user *argp = (void __user *)arg;
2299 long r;
2300
2301 switch (ioctl) {
2302 case KVM_GET_MSR_INDEX_LIST: {
2303 struct kvm_msr_list __user *user_msr_list = argp;
2304 struct kvm_msr_list msr_list;
2305 unsigned n;
2306
2307 r = -EFAULT;
2308 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2309 goto out;
2310 n = msr_list.nmsrs;
2311 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2312 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2313 goto out;
2314 r = -E2BIG;
e125e7b6 2315 if (n < msr_list.nmsrs)
043405e1
CO		 2316 goto out;
2317 r = -EFAULT;
2318 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2319 num_msrs_to_save * sizeof(u32)))
2320 goto out;
e125e7b6 2321 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2322 &emulated_msrs,
2323 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2324 goto out;
2325 r = 0;
2326 break;
2327 }
674eea0f
AK		 2328 case KVM_GET_SUPPORTED_CPUID: {
2329 struct kvm_cpuid2 __user *cpuid_arg = argp;
2330 struct kvm_cpuid2 cpuid;
2331
2332 r = -EFAULT;
2333 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2334 goto out;
2335 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2336 cpuid_arg->entries);
674eea0f
AK		 2337 if (r)
2338 goto out;
2339
2340 r = -EFAULT;
2341 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2342 goto out;
2343 r = 0;
2344 break;
2345 }
890ca9ae
HY		 2346 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2347 u64 mce_cap;
2348
2349 mce_cap = KVM_MCE_CAP_SUPPORTED;
2350 r = -EFAULT;
2351 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2352 goto out;
2353 r = 0;
2354 break;
2355 }
043405e1
CO		 2356 default:
2357 r = -EINVAL;
2358 }
2359out:
2360 return r;
2361}
2362
f5f48ee1
SY		 2363static void wbinvd_ipi(void *garbage)
2364{
2365 wbinvd();
2366}
2367
2368static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2369{
2370 return vcpu->kvm->arch.iommu_domain &&
2371 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2372}
2373
313a3dc7
CO		 2374void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2375{
f5f48ee1
SY		 2376 /* Address WBINVD may be executed by guest */
2377 if (need_emulate_wbinvd(vcpu)) {
2378 if (kvm_x86_ops->has_wbinvd_exit())
2379 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2380 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2381 smp_call_function_single(vcpu->cpu,
2382 wbinvd_ipi, NULL, 1);
2383 }
2384
313a3dc7 2385 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2386
0dd6a6ed
ZA		 2387 /* Apply any externally detected TSC adjustments (due to suspend) */
2388 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2389 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2390 vcpu->arch.tsc_offset_adjustment = 0;
2391 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2392 }
8f6055cb 2393
48434c20 2394 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2395 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2396 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2397 if (tsc_delta < 0)
2398 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2399 if (check_tsc_unstable()) {
b183aa58
ZA		 2400 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2401 vcpu->arch.last_guest_tsc);
2402 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2403 vcpu->arch.tsc_catchup = 1;
c285545f 2404 }
1aa8ceef 2405 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2406 if (vcpu->cpu != cpu)
2407 kvm_migrate_timers(vcpu);
e48672fa 2408 vcpu->cpu = cpu;
6b7d7e76 2409 }
c9aaa895
GC		 2410
2411 accumulate_steal_time(vcpu);
2412 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2413}
2414
2415void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2416{
02daab21 2417 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2418 kvm_put_guest_fpu(vcpu);
6f526ec5 2419 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2420}
2421
313a3dc7
CO		 2422static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2423 struct kvm_lapic_state *s)
2424{
ad312c7c 2425 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2426
2427 return 0;
2428}
2429
2430static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2431 struct kvm_lapic_state *s)
2432{
64eb0620 2433 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2434 update_cr8_intercept(vcpu);
313a3dc7
CO		 2435
2436 return 0;
2437}
2438
f77bc6a4
ZX		 2439static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2440 struct kvm_interrupt *irq)
2441{
a50abc3b 2442 if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2443 return -EINVAL;
2444 if (irqchip_in_kernel(vcpu->kvm))
2445 return -ENXIO;
f77bc6a4 2446
66fd3f7f 2447 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2448 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2449
f77bc6a4
ZX		 2450 return 0;
2451}
2452
c4abb7c9
JK		 2453static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2454{
c4abb7c9 2455 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2456
2457 return 0;
2458}
2459
b209749f
AK		 2460static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2461 struct kvm_tpr_access_ctl *tac)
2462{
2463 if (tac->flags)
2464 return -EINVAL;
2465 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2466 return 0;
2467}
2468
890ca9ae
HY		 2469static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2470 u64 mcg_cap)
2471{
2472 int r;
2473 unsigned bank_num = mcg_cap & 0xff, bank;
2474
2475 r = -EINVAL;
a9e38c3e 2476 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2477 goto out;
2478 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2479 goto out;
2480 r = 0;
2481 vcpu->arch.mcg_cap = mcg_cap;
2482 /* Init IA32_MCG_CTL to all 1s */
2483 if (mcg_cap & MCG_CTL_P)
2484 vcpu->arch.mcg_ctl = ~(u64)0;
2485 /* Init IA32_MCi_CTL to all 1s */
2486 for (bank = 0; bank < bank_num; bank++)
2487 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2488out:
2489 return r;
2490}
2491
2492static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2493 struct kvm_x86_mce *mce)
2494{
2495 u64 mcg_cap = vcpu->arch.mcg_cap;
2496 unsigned bank_num = mcg_cap & 0xff;
2497 u64 *banks = vcpu->arch.mce_banks;
2498
2499 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2500 return -EINVAL;
2501 /*
2502 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2503 * reporting is disabled
2504 */
2505 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2506 vcpu->arch.mcg_ctl != ~(u64)0)
2507 return 0;
2508 banks += 4 * mce->bank;
2509 /*
2510 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2511 * reporting is disabled for the bank
2512 */
2513 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2514 return 0;
2515 if (mce->status & MCI_STATUS_UC) {
2516 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2517 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2518 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2519 return 0;
2520 }
2521 if (banks[1] & MCI_STATUS_VAL)
2522 mce->status |= MCI_STATUS_OVER;
2523 banks[2] = mce->addr;
2524 banks[3] = mce->misc;
2525 vcpu->arch.mcg_status = mce->mcg_status;
2526 banks[1] = mce->status;
2527 kvm_queue_exception(vcpu, MC_VECTOR);
2528 } else if (!(banks[1] & MCI_STATUS_VAL)
2529 || !(banks[1] & MCI_STATUS_UC)) {
2530 if (banks[1] & MCI_STATUS_VAL)
2531 mce->status |= MCI_STATUS_OVER;
2532 banks[2] = mce->addr;
2533 banks[3] = mce->misc;
2534 banks[1] = mce->status;
2535 } else
2536 banks[1] |= MCI_STATUS_OVER;
2537 return 0;
2538}
2539
3cfc3092
JK		 2540static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2541 struct kvm_vcpu_events *events)
2542{
7460fb4a 2543 process_nmi(vcpu);
03b82a30
JK		 2544 events->exception.injected =
2545 vcpu->arch.exception.pending &&
2546 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2547 events->exception.nr = vcpu->arch.exception.nr;
2548 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2549 events->exception.pad = 0;
3cfc3092
JK		 2550 events->exception.error_code = vcpu->arch.exception.error_code;
2551
03b82a30
JK		 2552 events->interrupt.injected =
2553 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2554 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2555 events->interrupt.soft = 0;
48005f64
JK		 2556 events->interrupt.shadow =
2557 kvm_x86_ops->get_interrupt_shadow(vcpu,
2558 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2559
2560 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2561 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2562 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2563 events->nmi.pad = 0;
3cfc3092
JK		 2564
2565 events->sipi_vector = vcpu->arch.sipi_vector;
2566
dab4b911 2567 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2568 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2569 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2570 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2571}
2572
2573static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2574 struct kvm_vcpu_events *events)
2575{
dab4b911 2576 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2577 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2578 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2579 return -EINVAL;
2580
7460fb4a 2581 process_nmi(vcpu);
3cfc3092
JK		 2582 vcpu->arch.exception.pending = events->exception.injected;
2583 vcpu->arch.exception.nr = events->exception.nr;
2584 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2585 vcpu->arch.exception.error_code = events->exception.error_code;
2586
2587 vcpu->arch.interrupt.pending = events->interrupt.injected;
2588 vcpu->arch.interrupt.nr = events->interrupt.nr;
2589 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2590 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2591 kvm_x86_ops->set_interrupt_shadow(vcpu,
2592 events->interrupt.shadow);
3cfc3092
JK		 2593
2594 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2595 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2596 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2597 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2598
dab4b911
JK		 2599 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2600 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2601
3842d135
AK		 2602 kvm_make_request(KVM_REQ_EVENT, vcpu);
2603
3cfc3092
JK		 2604 return 0;
2605}
2606
a1efbe77
JK		 2607static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2608 struct kvm_debugregs *dbgregs)
2609{
a1efbe77
JK		 2610 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2611 dbgregs->dr6 = vcpu->arch.dr6;
2612 dbgregs->dr7 = vcpu->arch.dr7;
2613 dbgregs->flags = 0;
97e69aa6 2614 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2615}
2616
2617static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2618 struct kvm_debugregs *dbgregs)
2619{
2620 if (dbgregs->flags)
2621 return -EINVAL;
2622
a1efbe77
JK		 2623 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2624 vcpu->arch.dr6 = dbgregs->dr6;
2625 vcpu->arch.dr7 = dbgregs->dr7;
2626
a1efbe77
JK		 2627 return 0;
2628}
2629
2d5b5a66
SY		 2630static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2631 struct kvm_xsave *guest_xsave)
2632{
2633 if (cpu_has_xsave)
2634 memcpy(guest_xsave->region,
2635 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2636 xstate_size);
2d5b5a66
SY		 2637 else {
2638 memcpy(guest_xsave->region,
2639 &vcpu->arch.guest_fpu.state->fxsave,
2640 sizeof(struct i387_fxsave_struct));
2641 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2642 XSTATE_FPSSE;
2643 }
2644}
2645
2646static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2647 struct kvm_xsave *guest_xsave)
2648{
2649 u64 xstate_bv =
2650 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2651
2652 if (cpu_has_xsave)
2653 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2654 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2655 else {
2656 if (xstate_bv & ~XSTATE_FPSSE)
2657 return -EINVAL;
2658 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2659 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2660 }
2661 return 0;
2662}
2663
2664static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2665 struct kvm_xcrs *guest_xcrs)
2666{
2667 if (!cpu_has_xsave) {
2668 guest_xcrs->nr_xcrs = 0;
2669 return;
2670 }
2671
2672 guest_xcrs->nr_xcrs = 1;
2673 guest_xcrs->flags = 0;
2674 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2675 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2676}
2677
2678static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2679 struct kvm_xcrs *guest_xcrs)
2680{
2681 int i, r = 0;
2682
2683 if (!cpu_has_xsave)
2684 return -EINVAL;
2685
2686 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2687 return -EINVAL;
2688
2689 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2690 /* Only support XCR0 currently */
2691 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2692 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2693 guest_xcrs->xcrs[0].value);
2694 break;
2695 }
2696 if (r)
2697 r = -EINVAL;
2698 return r;
2699}
2700
1c0b28c2
EM		 2701/*
2702 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2703 * stopped by the hypervisor. This function will be called from the host only.
2704 * EINVAL is returned when the host attempts to set the flag for a guest that
2705 * does not support pv clocks.
2706 */
2707static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2708{
1c0b28c2
EM		 2709 if (!vcpu->arch.time_page)
2710 return -EINVAL;
51d59c6b 2711 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2712 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2713 return 0;
2714}
2715
313a3dc7
CO		 2716long kvm_arch_vcpu_ioctl(struct file *filp,
2717 unsigned int ioctl, unsigned long arg)
2718{
2719 struct kvm_vcpu *vcpu = filp->private_data;
2720 void __user *argp = (void __user *)arg;
2721 int r;
d1ac91d8
AK		 2722 union {
2723 struct kvm_lapic_state *lapic;
2724 struct kvm_xsave *xsave;
2725 struct kvm_xcrs *xcrs;
2726 void *buffer;
2727 } u;
2728
2729 u.buffer = NULL;
313a3dc7
CO		 2730 switch (ioctl) {
2731 case KVM_GET_LAPIC: {
2204ae3c
MT		 2732 r = -EINVAL;
2733 if (!vcpu->arch.apic)
2734 goto out;
d1ac91d8 2735 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2736
b772ff36 2737 r = -ENOMEM;
d1ac91d8 2738 if (!u.lapic)
b772ff36 2739 goto out;
d1ac91d8 2740 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2741 if (r)
2742 goto out;
2743 r = -EFAULT;
d1ac91d8 2744 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2745 goto out;
2746 r = 0;
2747 break;
2748 }
2749 case KVM_SET_LAPIC: {
2204ae3c
MT		 2750 if (!vcpu->arch.apic)
2751 goto out;
ff5c2c03 2752 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 2753 if (IS_ERR(u.lapic))
2754 return PTR_ERR(u.lapic);
ff5c2c03 2755
d1ac91d8 2756 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2757 break;
2758 }
f77bc6a4
ZX		 2759 case KVM_INTERRUPT: {
2760 struct kvm_interrupt irq;
2761
2762 r = -EFAULT;
2763 if (copy_from_user(&irq, argp, sizeof irq))
2764 goto out;
2765 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 2766 break;
2767 }
c4abb7c9
JK		 2768 case KVM_NMI: {
2769 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 2770 break;
2771 }
313a3dc7
CO		 2772 case KVM_SET_CPUID: {
2773 struct kvm_cpuid __user *cpuid_arg = argp;
2774 struct kvm_cpuid cpuid;
2775
2776 r = -EFAULT;
2777 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2778 goto out;
2779 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 2780 break;
2781 }
07716717
DK		 2782 case KVM_SET_CPUID2: {
2783 struct kvm_cpuid2 __user *cpuid_arg = argp;
2784 struct kvm_cpuid2 cpuid;
2785
2786 r = -EFAULT;
2787 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2788 goto out;
2789 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2790 cpuid_arg->entries);
07716717
DK		 2791 break;
2792 }
2793 case KVM_GET_CPUID2: {
2794 struct kvm_cpuid2 __user *cpuid_arg = argp;
2795 struct kvm_cpuid2 cpuid;
2796
2797 r = -EFAULT;
2798 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2799 goto out;
2800 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2801 cpuid_arg->entries);
07716717
DK		 2802 if (r)
2803 goto out;
2804 r = -EFAULT;
2805 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2806 goto out;
2807 r = 0;
2808 break;
2809 }
313a3dc7
CO		 2810 case KVM_GET_MSRS:
2811 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2812 break;
2813 case KVM_SET_MSRS:
2814 r = msr_io(vcpu, argp, do_set_msr, 0);
2815 break;
b209749f
AK		 2816 case KVM_TPR_ACCESS_REPORTING: {
2817 struct kvm_tpr_access_ctl tac;
2818
2819 r = -EFAULT;
2820 if (copy_from_user(&tac, argp, sizeof tac))
2821 goto out;
2822 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2823 if (r)
2824 goto out;
2825 r = -EFAULT;
2826 if (copy_to_user(argp, &tac, sizeof tac))
2827 goto out;
2828 r = 0;
2829 break;
2830 };
b93463aa
AK		 2831 case KVM_SET_VAPIC_ADDR: {
2832 struct kvm_vapic_addr va;
2833
2834 r = -EINVAL;
2835 if (!irqchip_in_kernel(vcpu->kvm))
2836 goto out;
2837 r = -EFAULT;
2838 if (copy_from_user(&va, argp, sizeof va))
2839 goto out;
2840 r = 0;
2841 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2842 break;
2843 }
890ca9ae
HY		 2844 case KVM_X86_SETUP_MCE: {
2845 u64 mcg_cap;
2846
2847 r = -EFAULT;
2848 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2849 goto out;
2850 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2851 break;
2852 }
2853 case KVM_X86_SET_MCE: {
2854 struct kvm_x86_mce mce;
2855
2856 r = -EFAULT;
2857 if (copy_from_user(&mce, argp, sizeof mce))
2858 goto out;
2859 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2860 break;
2861 }
3cfc3092
JK		 2862 case KVM_GET_VCPU_EVENTS: {
2863 struct kvm_vcpu_events events;
2864
2865 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2866
2867 r = -EFAULT;
2868 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2869 break;
2870 r = 0;
2871 break;
2872 }
2873 case KVM_SET_VCPU_EVENTS: {
2874 struct kvm_vcpu_events events;
2875
2876 r = -EFAULT;
2877 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2878 break;
2879
2880 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2881 break;
2882 }
a1efbe77
JK		 2883 case KVM_GET_DEBUGREGS: {
2884 struct kvm_debugregs dbgregs;
2885
2886 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2887
2888 r = -EFAULT;
2889 if (copy_to_user(argp, &dbgregs,
2890 sizeof(struct kvm_debugregs)))
2891 break;
2892 r = 0;
2893 break;
2894 }
2895 case KVM_SET_DEBUGREGS: {
2896 struct kvm_debugregs dbgregs;
2897
2898 r = -EFAULT;
2899 if (copy_from_user(&dbgregs, argp,
2900 sizeof(struct kvm_debugregs)))
2901 break;
2902
2903 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2904 break;
2905 }
2d5b5a66 2906 case KVM_GET_XSAVE: {
d1ac91d8 2907 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2908 r = -ENOMEM;
d1ac91d8 2909 if (!u.xsave)
2d5b5a66
SY		 2910 break;
2911
d1ac91d8 2912 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2913
2914 r = -EFAULT;
d1ac91d8 2915 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2916 break;
2917 r = 0;
2918 break;
2919 }
2920 case KVM_SET_XSAVE: {
ff5c2c03 2921 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 2922 if (IS_ERR(u.xsave))
2923 return PTR_ERR(u.xsave);
2d5b5a66 2924
d1ac91d8 2925 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2926 break;
2927 }
2928 case KVM_GET_XCRS: {
d1ac91d8 2929 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2930 r = -ENOMEM;
d1ac91d8 2931 if (!u.xcrs)
2d5b5a66
SY		 2932 break;
2933
d1ac91d8 2934 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2935
2936 r = -EFAULT;
d1ac91d8 2937 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2938 sizeof(struct kvm_xcrs)))
2939 break;
2940 r = 0;
2941 break;
2942 }
2943 case KVM_SET_XCRS: {
ff5c2c03 2944 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 2945 if (IS_ERR(u.xcrs))
2946 return PTR_ERR(u.xcrs);
2d5b5a66 2947
d1ac91d8 2948 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2949 break;
2950 }
92a1f12d
JR		 2951 case KVM_SET_TSC_KHZ: {
2952 u32 user_tsc_khz;
2953
2954 r = -EINVAL;
92a1f12d
JR		 2955 user_tsc_khz = (u32)arg;
2956
2957 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2958 goto out;
2959
cc578287
ZA		 2960 if (user_tsc_khz == 0)
2961 user_tsc_khz = tsc_khz;
2962
2963 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 2964
2965 r = 0;
2966 goto out;
2967 }
2968 case KVM_GET_TSC_KHZ: {
cc578287 2969 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 2970 goto out;
2971 }
1c0b28c2
EM		 2972 case KVM_KVMCLOCK_CTRL: {
2973 r = kvm_set_guest_paused(vcpu);
2974 goto out;
2975 }
313a3dc7
CO		 2976 default:
2977 r = -EINVAL;
2978 }
2979out:
d1ac91d8 2980 kfree(u.buffer);
313a3dc7
CO		 2981 return r;
2982}
2983
5b1c1493
CO		 2984int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2985{
2986 return VM_FAULT_SIGBUS;
2987}
2988
1fe779f8
CO		 2989static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2990{
2991 int ret;
2992
2993 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 2994 return -EINVAL;
1fe779f8
CO		 2995 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2996 return ret;
2997}
2998
b927a3ce
SY		 2999static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3000 u64 ident_addr)
3001{
3002 kvm->arch.ept_identity_map_addr = ident_addr;
3003 return 0;
3004}
3005
1fe779f8
CO		 3006static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3007 u32 kvm_nr_mmu_pages)
3008{
3009 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3010 return -EINVAL;
3011
79fac95e 3012 mutex_lock(&kvm->slots_lock);
7c8a83b7 3013 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3014
3015 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3016 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3017
7c8a83b7 3018 spin_unlock(&kvm->mmu_lock);
79fac95e 3019 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3020 return 0;
3021}
3022
3023static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3024{
39de71ec 3025 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3026}
3027
1fe779f8
CO		 3028static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3029{
3030 int r;
3031
3032 r = 0;
3033 switch (chip->chip_id) {
3034 case KVM_IRQCHIP_PIC_MASTER:
3035 memcpy(&chip->chip.pic,
3036 &pic_irqchip(kvm)->pics[0],
3037 sizeof(struct kvm_pic_state));
3038 break;
3039 case KVM_IRQCHIP_PIC_SLAVE:
3040 memcpy(&chip->chip.pic,
3041 &pic_irqchip(kvm)->pics[1],
3042 sizeof(struct kvm_pic_state));
3043 break;
3044 case KVM_IRQCHIP_IOAPIC:
eba0226b 3045 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3046 break;
3047 default:
3048 r = -EINVAL;
3049 break;
3050 }
3051 return r;
3052}
3053
3054static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3055{
3056 int r;
3057
3058 r = 0;
3059 switch (chip->chip_id) {
3060 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3061 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3062 memcpy(&pic_irqchip(kvm)->pics[0],
3063 &chip->chip.pic,
3064 sizeof(struct kvm_pic_state));
f4f51050 3065 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3066 break;
3067 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3068 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3069 memcpy(&pic_irqchip(kvm)->pics[1],
3070 &chip->chip.pic,
3071 sizeof(struct kvm_pic_state));
f4f51050 3072 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3073 break;
3074 case KVM_IRQCHIP_IOAPIC:
eba0226b 3075 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3076 break;
3077 default:
3078 r = -EINVAL;
3079 break;
3080 }
3081 kvm_pic_update_irq(pic_irqchip(kvm));
3082 return r;
3083}
3084
e0f63cb9
SY		 3085static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3086{
3087 int r = 0;
3088
894a9c55 3089 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3090 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3091 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3092 return r;
3093}
3094
3095static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3096{
3097 int r = 0;
3098
894a9c55 3099 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3100 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3101 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3102 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3103 return r;
3104}
3105
3106static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3107{
3108 int r = 0;
3109
3110 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3111 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3112 sizeof(ps->channels));
3113 ps->flags = kvm->arch.vpit->pit_state.flags;
3114 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3115 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3116 return r;
3117}
3118
3119static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3120{
3121 int r = 0, start = 0;
3122 u32 prev_legacy, cur_legacy;
3123 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3124 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3125 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3126 if (!prev_legacy && cur_legacy)
3127 start = 1;
3128 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3129 sizeof(kvm->arch.vpit->pit_state.channels));
3130 kvm->arch.vpit->pit_state.flags = ps->flags;
3131 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3132 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3133 return r;
3134}
3135
52d939a0
MT		 3136static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3137 struct kvm_reinject_control *control)
3138{
3139 if (!kvm->arch.vpit)
3140 return -ENXIO;
894a9c55 3141 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3142 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3143 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3144 return 0;
3145}
3146
95d4c16c 3147/**
60c34612
TY		 3148 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3149 * @kvm: kvm instance
3150 * @log: slot id and address to which we copy the log
95d4c16c 3151 *
60c34612
TY		 3152 * We need to keep it in mind that VCPU threads can write to the bitmap
3153 * concurrently. So, to avoid losing data, we keep the following order for
3154 * each bit:
95d4c16c 3155 *
60c34612
TY		 3156 * 1. Take a snapshot of the bit and clear it if needed.
3157 * 2. Write protect the corresponding page.
3158 * 3. Flush TLB's if needed.
3159 * 4. Copy the snapshot to the userspace.
95d4c16c 3160 *
60c34612
TY		 3161 * Between 2 and 3, the guest may write to the page using the remaining TLB
3162 * entry. This is not a problem because the page will be reported dirty at
3163 * step 4 using the snapshot taken before and step 3 ensures that successive
3164 * writes will be logged for the next call.
5bb064dc 3165 */
60c34612 3166int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3167{
7850ac54 3168 int r;
5bb064dc 3169 struct kvm_memory_slot *memslot;
60c34612
TY		 3170 unsigned long n, i;
3171 unsigned long *dirty_bitmap;
3172 unsigned long *dirty_bitmap_buffer;
3173 bool is_dirty = false;
5bb064dc 3174
79fac95e 3175 mutex_lock(&kvm->slots_lock);
5bb064dc 3176
b050b015
MT		 3177 r = -EINVAL;
3178 if (log->slot >= KVM_MEMORY_SLOTS)
3179 goto out;
3180
28a37544 3181 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3182
3183 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3184 r = -ENOENT;
60c34612 3185 if (!dirty_bitmap)
b050b015
MT		 3186 goto out;
3187
87bf6e7d 3188 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3189
60c34612
TY		 3190 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3191 memset(dirty_bitmap_buffer, 0, n);
b050b015 3192
60c34612 3193 spin_lock(&kvm->mmu_lock);
b050b015 3194
60c34612
TY		 3195 for (i = 0; i < n / sizeof(long); i++) {
3196 unsigned long mask;
3197 gfn_t offset;
cdfca7b3 3198
60c34612
TY		 3199 if (!dirty_bitmap[i])
3200 continue;
b050b015 3201
60c34612 3202 is_dirty = true;
914ebccd 3203
60c34612
TY		 3204 mask = xchg(&dirty_bitmap[i], 0);
3205 dirty_bitmap_buffer[i] = mask;
edde99ce 3206
60c34612
TY		 3207 offset = i * BITS_PER_LONG;
3208 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3209 }
60c34612
TY		 3210 if (is_dirty)
3211 kvm_flush_remote_tlbs(kvm);
3212
3213 spin_unlock(&kvm->mmu_lock);
3214
3215 r = -EFAULT;
3216 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3217 goto out;
b050b015 3218
5bb064dc
ZX		 3219 r = 0;
3220out:
79fac95e 3221 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3222 return r;
3223}
3224
23d43cf9
CD		 3225int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3226{
3227 if (!irqchip_in_kernel(kvm))
3228 return -ENXIO;
3229
3230 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3231 irq_event->irq, irq_event->level);
3232 return 0;
3233}
3234
1fe779f8
CO		 3235long kvm_arch_vm_ioctl(struct file *filp,
3236 unsigned int ioctl, unsigned long arg)
3237{
3238 struct kvm *kvm = filp->private_data;
3239 void __user *argp = (void __user *)arg;
367e1319 3240 int r = -ENOTTY;
f0d66275
DH		 3241 /*
3242 * This union makes it completely explicit to gcc-3.x
3243 * that these two variables' stack usage should be
3244 * combined, not added together.
3245 */
3246 union {
3247 struct kvm_pit_state ps;
e9f42757 3248 struct kvm_pit_state2 ps2;
c5ff41ce 3249 struct kvm_pit_config pit_config;
f0d66275 3250 } u;
1fe779f8
CO		 3251
3252 switch (ioctl) {
3253 case KVM_SET_TSS_ADDR:
3254 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3255 break;
b927a3ce
SY		 3256 case KVM_SET_IDENTITY_MAP_ADDR: {
3257 u64 ident_addr;
3258
3259 r = -EFAULT;
3260 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3261 goto out;
3262 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3263 break;
3264 }
1fe779f8
CO		 3265 case KVM_SET_NR_MMU_PAGES:
3266 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3267 break;
3268 case KVM_GET_NR_MMU_PAGES:
3269 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3270 break;
3ddea128
MT		 3271 case KVM_CREATE_IRQCHIP: {
3272 struct kvm_pic *vpic;
3273
3274 mutex_lock(&kvm->lock);
3275 r = -EEXIST;
3276 if (kvm->arch.vpic)
3277 goto create_irqchip_unlock;
3e515705
AK		 3278 r = -EINVAL;
3279 if (atomic_read(&kvm->online_vcpus))
3280 goto create_irqchip_unlock;
1fe779f8 3281 r = -ENOMEM;
3ddea128
MT		 3282 vpic = kvm_create_pic(kvm);
3283 if (vpic) {
1fe779f8
CO		 3284 r = kvm_ioapic_init(kvm);
3285 if (r) {
175504cd 3286 mutex_lock(&kvm->slots_lock);
72bb2fcd 3287 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3288 &vpic->dev_master);
3289 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3290 &vpic->dev_slave);
3291 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3292 &vpic->dev_eclr);
175504cd 3293 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3294 kfree(vpic);
3295 goto create_irqchip_unlock;
1fe779f8
CO		 3296 }
3297 } else
3ddea128
MT		 3298 goto create_irqchip_unlock;
3299 smp_wmb();
3300 kvm->arch.vpic = vpic;
3301 smp_wmb();
399ec807
AK		 3302 r = kvm_setup_default_irq_routing(kvm);
3303 if (r) {
175504cd 3304 mutex_lock(&kvm->slots_lock);
3ddea128 3305 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3306 kvm_ioapic_destroy(kvm);
3307 kvm_destroy_pic(kvm);
3ddea128 3308 mutex_unlock(&kvm->irq_lock);
175504cd 3309 mutex_unlock(&kvm->slots_lock);
399ec807 3310 }
3ddea128
MT		 3311 create_irqchip_unlock:
3312 mutex_unlock(&kvm->lock);
1fe779f8 3313 break;
3ddea128 3314 }
7837699f 3315 case KVM_CREATE_PIT:
c5ff41ce
JK		 3316 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3317 goto create_pit;
3318 case KVM_CREATE_PIT2:
3319 r = -EFAULT;
3320 if (copy_from_user(&u.pit_config, argp,
3321 sizeof(struct kvm_pit_config)))
3322 goto out;
3323 create_pit:
79fac95e 3324 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3325 r = -EEXIST;
3326 if (kvm->arch.vpit)
3327 goto create_pit_unlock;
7837699f 3328 r = -ENOMEM;
c5ff41ce 3329 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3330 if (kvm->arch.vpit)
3331 r = 0;
269e05e4 3332 create_pit_unlock:
79fac95e 3333 mutex_unlock(&kvm->slots_lock);
7837699f 3334 break;
1fe779f8
CO		 3335 case KVM_GET_IRQCHIP: {
3336 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3337 struct kvm_irqchip *chip;
1fe779f8 3338
ff5c2c03
SL		 3339 chip = memdup_user(argp, sizeof(*chip));
3340 if (IS_ERR(chip)) {
3341 r = PTR_ERR(chip);
1fe779f8 3342 goto out;
ff5c2c03
SL		 3343 }
3344
1fe779f8
CO		 3345 r = -ENXIO;
3346 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3347 goto get_irqchip_out;
3348 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3349 if (r)
f0d66275 3350 goto get_irqchip_out;
1fe779f8 3351 r = -EFAULT;
f0d66275
DH		 3352 if (copy_to_user(argp, chip, sizeof *chip))
3353 goto get_irqchip_out;
1fe779f8 3354 r = 0;
f0d66275
DH		 3355 get_irqchip_out:
3356 kfree(chip);
1fe779f8
CO		 3357 break;
3358 }
3359 case KVM_SET_IRQCHIP: {
3360 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3361 struct kvm_irqchip *chip;
1fe779f8 3362
ff5c2c03
SL		 3363 chip = memdup_user(argp, sizeof(*chip));
3364 if (IS_ERR(chip)) {
3365 r = PTR_ERR(chip);
1fe779f8 3366 goto out;
ff5c2c03
SL		 3367 }
3368
1fe779f8
CO		 3369 r = -ENXIO;
3370 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3371 goto set_irqchip_out;
3372 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3373 if (r)
f0d66275 3374 goto set_irqchip_out;
1fe779f8 3375 r = 0;
f0d66275
DH		 3376 set_irqchip_out:
3377 kfree(chip);
1fe779f8
CO		 3378 break;
3379 }
e0f63cb9 3380 case KVM_GET_PIT: {
e0f63cb9 3381 r = -EFAULT;
f0d66275 3382 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3383 goto out;
3384 r = -ENXIO;
3385 if (!kvm->arch.vpit)
3386 goto out;
f0d66275 3387 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3388 if (r)
3389 goto out;
3390 r = -EFAULT;
f0d66275 3391 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3392 goto out;
3393 r = 0;
3394 break;
3395 }
3396 case KVM_SET_PIT: {
e0f63cb9 3397 r = -EFAULT;
f0d66275 3398 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3399 goto out;
3400 r = -ENXIO;
3401 if (!kvm->arch.vpit)
3402 goto out;
f0d66275 3403 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3404 break;
3405 }
e9f42757
BK		 3406 case KVM_GET_PIT2: {
3407 r = -ENXIO;
3408 if (!kvm->arch.vpit)
3409 goto out;
3410 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3411 if (r)
3412 goto out;
3413 r = -EFAULT;
3414 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3415 goto out;
3416 r = 0;
3417 break;
3418 }
3419 case KVM_SET_PIT2: {
3420 r = -EFAULT;
3421 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3422 goto out;
3423 r = -ENXIO;
3424 if (!kvm->arch.vpit)
3425 goto out;
3426 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3427 break;
3428 }
52d939a0
MT		 3429 case KVM_REINJECT_CONTROL: {
3430 struct kvm_reinject_control control;
3431 r = -EFAULT;
3432 if (copy_from_user(&control, argp, sizeof(control)))
3433 goto out;
3434 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3435 break;
3436 }
ffde22ac
ES		 3437 case KVM_XEN_HVM_CONFIG: {
3438 r = -EFAULT;
3439 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3440 sizeof(struct kvm_xen_hvm_config)))
3441 goto out;
3442 r = -EINVAL;
3443 if (kvm->arch.xen_hvm_config.flags)
3444 goto out;
3445 r = 0;
3446 break;
3447 }
afbcf7ab 3448 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3449 struct kvm_clock_data user_ns;
3450 u64 now_ns;
3451 s64 delta;
3452
3453 r = -EFAULT;
3454 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3455 goto out;
3456
3457 r = -EINVAL;
3458 if (user_ns.flags)
3459 goto out;
3460
3461 r = 0;
395c6b0a 3462 local_irq_disable();
759379dd 3463 now_ns = get_kernel_ns();
afbcf7ab 3464 delta = user_ns.clock - now_ns;
395c6b0a 3465 local_irq_enable();
afbcf7ab
GC		 3466 kvm->arch.kvmclock_offset = delta;
3467 break;
3468 }
3469 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3470 struct kvm_clock_data user_ns;
3471 u64 now_ns;
3472
395c6b0a 3473 local_irq_disable();
759379dd 3474 now_ns = get_kernel_ns();
afbcf7ab 3475 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3476 local_irq_enable();
afbcf7ab 3477 user_ns.flags = 0;
97e69aa6 3478 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3479
3480 r = -EFAULT;
3481 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3482 goto out;
3483 r = 0;
3484 break;
3485 }
3486
1fe779f8
CO		 3487 default:
3488 ;
3489 }
3490out:
3491 return r;
3492}
3493
a16b043c 3494static void kvm_init_msr_list(void)
043405e1
CO		 3495{
3496 u32 dummy[2];
3497 unsigned i, j;
3498
e3267cbb
GC		 3499 /* skip the first msrs in the list. KVM-specific */
3500 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3501 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3502 continue;
3503 if (j < i)
3504 msrs_to_save[j] = msrs_to_save[i];
3505 j++;
3506 }
3507 num_msrs_to_save = j;
3508}
3509
bda9020e
MT		 3510static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3511 const void *v)
bbd9b64e 3512{
70252a10
AK		 3513 int handled = 0;
3514 int n;
3515
3516 do {
3517 n = min(len, 8);
3518 if (!(vcpu->arch.apic &&
3519 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3520 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3521 break;
3522 handled += n;
3523 addr += n;
3524 len -= n;
3525 v += n;
3526 } while (len);
bbd9b64e 3527
70252a10 3528 return handled;
bbd9b64e
CO		 3529}
3530
bda9020e 3531static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3532{
70252a10
AK		 3533 int handled = 0;
3534 int n;
3535
3536 do {
3537 n = min(len, 8);
3538 if (!(vcpu->arch.apic &&
3539 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3540 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3541 break;
3542 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3543 handled += n;
3544 addr += n;
3545 len -= n;
3546 v += n;
3547 } while (len);
bbd9b64e 3548
70252a10 3549 return handled;
bbd9b64e
CO		 3550}
3551
2dafc6c2
GN		 3552static void kvm_set_segment(struct kvm_vcpu *vcpu,
3553 struct kvm_segment *var, int seg)
3554{
3555 kvm_x86_ops->set_segment(vcpu, var, seg);
3556}
3557
3558void kvm_get_segment(struct kvm_vcpu *vcpu,
3559 struct kvm_segment *var, int seg)
3560{
3561 kvm_x86_ops->get_segment(vcpu, var, seg);
3562}
3563
e459e322 3564gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3565{
3566 gpa_t t_gpa;
ab9ae313 3567 struct x86_exception exception;
02f59dc9
JR		 3568
3569 BUG_ON(!mmu_is_nested(vcpu));
3570
3571 /* NPT walks are always user-walks */
3572 access |= PFERR_USER_MASK;
ab9ae313 3573 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3574
3575 return t_gpa;
3576}
3577
ab9ae313
AK		 3578gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3579 struct x86_exception *exception)
1871c602
GN		 3580{
3581 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3582 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3583}
3584
ab9ae313
AK		 3585 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3586 struct x86_exception *exception)
1871c602
GN		 3587{
3588 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3589 access |= PFERR_FETCH_MASK;
ab9ae313 3590 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3591}
3592
ab9ae313
AK		 3593gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3594 struct x86_exception *exception)
1871c602
GN		 3595{
3596 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3597 access |= PFERR_WRITE_MASK;
ab9ae313 3598 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3599}
3600
3601/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3602gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3603 struct x86_exception *exception)
1871c602 3604{
ab9ae313 3605 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3606}
3607
3608static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3609 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3610 struct x86_exception *exception)
bbd9b64e
CO		 3611{
3612 void *data = val;
10589a46 3613 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3614
3615 while (bytes) {
14dfe855 3616 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3617 exception);
bbd9b64e 3618 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3619 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3620 int ret;
3621
bcc55cba 3622 if (gpa == UNMAPPED_GVA)
ab9ae313 3623 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3624 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3625 if (ret < 0) {
c3cd7ffa 3626 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3627 goto out;
3628 }
bbd9b64e 3629
77c2002e
IE		 3630 bytes -= toread;
3631 data += toread;
3632 addr += toread;
bbd9b64e 3633 }
10589a46 3634out:
10589a46 3635 return r;
bbd9b64e 3636}
77c2002e 3637
1871c602 3638/* used for instruction fetching */
0f65dd70
AK		 3639static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3640 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3641 struct x86_exception *exception)
1871c602 3642{
0f65dd70 3643 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3644 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3645
1871c602 3646 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3647 access | PFERR_FETCH_MASK,
3648 exception);
1871c602
GN		 3649}
3650
064aea77 3651int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3652 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3653 struct x86_exception *exception)
1871c602 3654{
0f65dd70 3655 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3656 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3657
1871c602 3658 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3659 exception);
1871c602 3660}
064aea77 3661EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3662
0f65dd70
AK		 3663static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3664 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3665 struct x86_exception *exception)
1871c602 3666{
0f65dd70 3667 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3668 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3669}
3670
6a4d7550 3671int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3672 gva_t addr, void *val,
2dafc6c2 3673 unsigned int bytes,
bcc55cba 3674 struct x86_exception *exception)
77c2002e 3675{
0f65dd70 3676 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3677 void *data = val;
3678 int r = X86EMUL_CONTINUE;
3679
3680 while (bytes) {
14dfe855
JR		 3681 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3682 PFERR_WRITE_MASK,
ab9ae313 3683 exception);
77c2002e
IE		 3684 unsigned offset = addr & (PAGE_SIZE-1);
3685 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3686 int ret;
3687
bcc55cba 3688 if (gpa == UNMAPPED_GVA)
ab9ae313 3689 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3690 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3691 if (ret < 0) {
c3cd7ffa 3692 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3693 goto out;
3694 }
3695
3696 bytes -= towrite;
3697 data += towrite;
3698 addr += towrite;
3699 }
3700out:
3701 return r;
3702}
6a4d7550 3703EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3704
af7cc7d1
XG		 3705static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3706 gpa_t *gpa, struct x86_exception *exception,
3707 bool write)
3708{
97d64b78
AK		 3709 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3710 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 3711
97d64b78
AK		 3712 if (vcpu_match_mmio_gva(vcpu, gva)
3713 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 3714 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3715 (gva & (PAGE_SIZE - 1));
4f022648 3716 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3717 return 1;
3718 }
3719
af7cc7d1
XG		 3720 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3721
3722 if (*gpa == UNMAPPED_GVA)
3723 return -1;
3724
3725 /* For APIC access vmexit */
3726 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3727 return 1;
3728
4f022648
XG		 3729 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3730 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3731 return 1;
4f022648 3732 }
bebb106a 3733
af7cc7d1
XG		 3734 return 0;
3735}
3736
3200f405 3737int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3738 const void *val, int bytes)
bbd9b64e
CO		 3739{
3740 int ret;
3741
3742 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3743 if (ret < 0)
bbd9b64e 3744 return 0;
f57f2ef5 3745 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3746 return 1;
3747}
3748
77d197b2
XG		 3749struct read_write_emulator_ops {
3750 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3751 int bytes);
3752 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3753 void *val, int bytes);
3754 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3755 int bytes, void *val);
3756 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3757 void *val, int bytes);
3758 bool write;
3759};
3760
3761static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3762{
3763 if (vcpu->mmio_read_completed) {
77d197b2 3764 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 3765 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 3766 vcpu->mmio_read_completed = 0;
3767 return 1;
3768 }
3769
3770 return 0;
3771}
3772
3773static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3774 void *val, int bytes)
3775{
3776 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3777}
3778
3779static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3780 void *val, int bytes)
3781{
3782 return emulator_write_phys(vcpu, gpa, val, bytes);
3783}
3784
3785static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3786{
3787 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3788 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3789}
3790
3791static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3792 void *val, int bytes)
3793{
3794 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3795 return X86EMUL_IO_NEEDED;
3796}
3797
3798static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3799 void *val, int bytes)
3800{
f78146b0
AK		 3801 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3802
3803 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
77d197b2
XG		 3804 return X86EMUL_CONTINUE;
3805}
3806
0fbe9b0b 3807static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 3808 .read_write_prepare = read_prepare,
3809 .read_write_emulate = read_emulate,
3810 .read_write_mmio = vcpu_mmio_read,
3811 .read_write_exit_mmio = read_exit_mmio,
3812};
3813
0fbe9b0b 3814static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 3815 .read_write_emulate = write_emulate,
3816 .read_write_mmio = write_mmio,
3817 .read_write_exit_mmio = write_exit_mmio,
3818 .write = true,
3819};
3820
22388a3c
XG		 3821static int emulator_read_write_onepage(unsigned long addr, void *val,
3822 unsigned int bytes,
3823 struct x86_exception *exception,
3824 struct kvm_vcpu *vcpu,
0fbe9b0b 3825 const struct read_write_emulator_ops *ops)
bbd9b64e 3826{
af7cc7d1
XG		 3827 gpa_t gpa;
3828 int handled, ret;
22388a3c 3829 bool write = ops->write;
f78146b0 3830 struct kvm_mmio_fragment *frag;
10589a46 3831
22388a3c 3832 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3833
af7cc7d1 3834 if (ret < 0)
bbd9b64e 3835 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3836
3837 /* For APIC access vmexit */
af7cc7d1 3838 if (ret)
bbd9b64e
CO		 3839 goto mmio;
3840
22388a3c 3841 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3842 return X86EMUL_CONTINUE;
3843
3844mmio:
3845 /*
3846 * Is this MMIO handled locally?
3847 */
22388a3c 3848 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3849 if (handled == bytes)
bbd9b64e 3850 return X86EMUL_CONTINUE;
bbd9b64e 3851
70252a10
AK		 3852 gpa += handled;
3853 bytes -= handled;
3854 val += handled;
3855
f78146b0
AK		 3856 while (bytes) {
3857 unsigned now = min(bytes, 8U);
bbd9b64e 3858
f78146b0
AK		 3859 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3860 frag->gpa = gpa;
3861 frag->data = val;
3862 frag->len = now;
3863
3864 gpa += now;
3865 val += now;
3866 bytes -= now;
3867 }
3868 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3869}
3870
22388a3c
XG		 3871int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3872 void *val, unsigned int bytes,
3873 struct x86_exception *exception,
0fbe9b0b 3874 const struct read_write_emulator_ops *ops)
bbd9b64e 3875{
0f65dd70 3876 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 3877 gpa_t gpa;
3878 int rc;
3879
3880 if (ops->read_write_prepare &&
3881 ops->read_write_prepare(vcpu, val, bytes))
3882 return X86EMUL_CONTINUE;
3883
3884 vcpu->mmio_nr_fragments = 0;
0f65dd70 3885
bbd9b64e
CO		 3886 /* Crossing a page boundary? */
3887 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 3888 int now;
bbd9b64e
CO		 3889
3890 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3891 rc = emulator_read_write_onepage(addr, val, now, exception,
3892 vcpu, ops);
3893
bbd9b64e
CO		 3894 if (rc != X86EMUL_CONTINUE)
3895 return rc;
3896 addr += now;
3897 val += now;
3898 bytes -= now;
3899 }
22388a3c 3900
f78146b0
AK		 3901 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3902 vcpu, ops);
3903 if (rc != X86EMUL_CONTINUE)
3904 return rc;
3905
3906 if (!vcpu->mmio_nr_fragments)
3907 return rc;
3908
3909 gpa = vcpu->mmio_fragments[0].gpa;
3910
3911 vcpu->mmio_needed = 1;
3912 vcpu->mmio_cur_fragment = 0;
3913
3914 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3915 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3916 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3917 vcpu->run->mmio.phys_addr = gpa;
3918
3919 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 3920}
3921
3922static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3923 unsigned long addr,
3924 void *val,
3925 unsigned int bytes,
3926 struct x86_exception *exception)
3927{
3928 return emulator_read_write(ctxt, addr, val, bytes,
3929 exception, &read_emultor);
3930}
3931
3932int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3933 unsigned long addr,
3934 const void *val,
3935 unsigned int bytes,
3936 struct x86_exception *exception)
3937{
3938 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3939 exception, &write_emultor);
bbd9b64e 3940}
bbd9b64e 3941
daea3e73
AK		 3942#define CMPXCHG_TYPE(t, ptr, old, new) \
3943 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3944
3945#ifdef CONFIG_X86_64
3946# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3947#else
3948# define CMPXCHG64(ptr, old, new) \
9749a6c0 3949 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3950#endif
3951
0f65dd70
AK		 3952static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3953 unsigned long addr,
bbd9b64e
CO		 3954 const void *old,
3955 const void *new,
3956 unsigned int bytes,
0f65dd70 3957 struct x86_exception *exception)
bbd9b64e 3958{
0f65dd70 3959 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3960 gpa_t gpa;
3961 struct page *page;
3962 char *kaddr;
3963 bool exchanged;
2bacc55c 3964
daea3e73
AK		 3965 /* guests cmpxchg8b have to be emulated atomically */
3966 if (bytes > 8 || (bytes & (bytes - 1)))
3967 goto emul_write;
10589a46 3968
daea3e73 3969 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3970
daea3e73
AK		 3971 if (gpa == UNMAPPED_GVA ||
3972 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3973 goto emul_write;
2bacc55c 3974
daea3e73
AK		 3975 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3976 goto emul_write;
72dc67a6 3977
daea3e73 3978 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 3979 if (is_error_page(page))
c19b8bd6 3980 goto emul_write;
72dc67a6 3981
8fd75e12 3982 kaddr = kmap_atomic(page);
daea3e73
AK		 3983 kaddr += offset_in_page(gpa);
3984 switch (bytes) {
3985 case 1:
3986 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3987 break;
3988 case 2:
3989 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3990 break;
3991 case 4:
3992 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3993 break;
3994 case 8:
3995 exchanged = CMPXCHG64(kaddr, old, new);
3996 break;
3997 default:
3998 BUG();
2bacc55c 3999 }
8fd75e12 4000 kunmap_atomic(kaddr);
daea3e73
AK		 4001 kvm_release_page_dirty(page);
4002
4003 if (!exchanged)
4004 return X86EMUL_CMPXCHG_FAILED;
4005
f57f2ef5 4006 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4007
4008 return X86EMUL_CONTINUE;
4a5f48f6 4009
3200f405 4010emul_write:
daea3e73 4011 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4012
0f65dd70 4013 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4014}
4015
cf8f70bf
GN		 4016static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4017{
4018 /* TODO: String I/O for in kernel device */
4019 int r;
4020
4021 if (vcpu->arch.pio.in)
4022 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4023 vcpu->arch.pio.size, pd);
4024 else
4025 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4026 vcpu->arch.pio.port, vcpu->arch.pio.size,
4027 pd);
4028 return r;
4029}
4030
6f6fbe98
XG		 4031static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4032 unsigned short port, void *val,
4033 unsigned int count, bool in)
cf8f70bf 4034{
6f6fbe98 4035 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4036
4037 vcpu->arch.pio.port = port;
6f6fbe98 4038 vcpu->arch.pio.in = in;
7972995b 4039 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4040 vcpu->arch.pio.size = size;
4041
4042 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4043 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4044 return 1;
4045 }
4046
4047 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4048 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4049 vcpu->run->io.size = size;
4050 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4051 vcpu->run->io.count = count;
4052 vcpu->run->io.port = port;
4053
4054 return 0;
4055}
4056
6f6fbe98
XG		 4057static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4058 int size, unsigned short port, void *val,
4059 unsigned int count)
cf8f70bf 4060{
ca1d4a9e 4061 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4062 int ret;
ca1d4a9e 4063
6f6fbe98
XG		 4064 if (vcpu->arch.pio.count)
4065 goto data_avail;
cf8f70bf 4066
6f6fbe98
XG		 4067 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4068 if (ret) {
4069data_avail:
4070 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4071 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4072 return 1;
4073 }
4074
cf8f70bf
GN		 4075 return 0;
4076}
4077
6f6fbe98
XG		 4078static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4079 int size, unsigned short port,
4080 const void *val, unsigned int count)
4081{
4082 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4083
4084 memcpy(vcpu->arch.pio_data, val, size * count);
4085 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4086}
4087
bbd9b64e
CO		 4088static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4089{
4090 return kvm_x86_ops->get_segment_base(vcpu, seg);
4091}
4092
3cb16fe7 4093static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4094{
3cb16fe7 4095 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4096}
4097
f5f48ee1
SY		 4098int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4099{
4100 if (!need_emulate_wbinvd(vcpu))
4101 return X86EMUL_CONTINUE;
4102
4103 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4104 int cpu = get_cpu();
4105
4106 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4107 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4108 wbinvd_ipi, NULL, 1);
2eec7343 4109 put_cpu();
f5f48ee1 4110 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4111 } else
4112 wbinvd();
f5f48ee1
SY		 4113 return X86EMUL_CONTINUE;
4114}
4115EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4116
bcaf5cc5
AK		 4117static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4118{
4119 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4120}
4121
717746e3 4122int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4123{
717746e3 4124 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4125}
4126
717746e3 4127int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4128{
338dbc97 4129
717746e3 4130 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4131}
4132
52a46617 4133static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4134{
52a46617 4135 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4136}
4137
717746e3 4138static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4139{
717746e3 4140 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4141 unsigned long value;
4142
4143 switch (cr) {
4144 case 0:
4145 value = kvm_read_cr0(vcpu);
4146 break;
4147 case 2:
4148 value = vcpu->arch.cr2;
4149 break;
4150 case 3:
9f8fe504 4151 value = kvm_read_cr3(vcpu);
52a46617
GN		 4152 break;
4153 case 4:
4154 value = kvm_read_cr4(vcpu);
4155 break;
4156 case 8:
4157 value = kvm_get_cr8(vcpu);
4158 break;
4159 default:
a737f256 4160 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4161 return 0;
4162 }
4163
4164 return value;
4165}
4166
717746e3 4167static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4168{
717746e3 4169 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4170 int res = 0;
4171
52a46617
GN		 4172 switch (cr) {
4173 case 0:
49a9b07e 4174 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4175 break;
4176 case 2:
4177 vcpu->arch.cr2 = val;
4178 break;
4179 case 3:
2390218b 4180 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4181 break;
4182 case 4:
a83b29c6 4183 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4184 break;
4185 case 8:
eea1cff9 4186 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4187 break;
4188 default:
a737f256 4189 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4190 res = -1;
52a46617 4191 }
0f12244f
GN		 4192
4193 return res;
52a46617
GN		 4194}
4195
4cee4798
KW		 4196static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4197{
4198 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4199}
4200
717746e3 4201static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4202{
717746e3 4203 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4204}
4205
4bff1e86 4206static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4207{
4bff1e86 4208 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4209}
4210
4bff1e86 4211static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4212{
4bff1e86 4213 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4214}
4215
1ac9d0cf
AK		 4216static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4217{
4218 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4219}
4220
4221static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4222{
4223 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4224}
4225
4bff1e86
AK		 4226static unsigned long emulator_get_cached_segment_base(
4227 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4228{
4bff1e86 4229 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4230}
4231
1aa36616
AK		 4232static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4233 struct desc_struct *desc, u32 *base3,
4234 int seg)
2dafc6c2
GN		 4235{
4236 struct kvm_segment var;
4237
4bff1e86 4238 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4239 *selector = var.selector;
2dafc6c2
GN		 4240
4241 if (var.unusable)
4242 return false;
4243
4244 if (var.g)
4245 var.limit >>= 12;
4246 set_desc_limit(desc, var.limit);
4247 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4248#ifdef CONFIG_X86_64
4249 if (base3)
4250 *base3 = var.base >> 32;
4251#endif
2dafc6c2
GN		 4252 desc->type = var.type;
4253 desc->s = var.s;
4254 desc->dpl = var.dpl;
4255 desc->p = var.present;
4256 desc->avl = var.avl;
4257 desc->l = var.l;
4258 desc->d = var.db;
4259 desc->g = var.g;
4260
4261 return true;
4262}
4263
1aa36616
AK		 4264static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4265 struct desc_struct *desc, u32 base3,
4266 int seg)
2dafc6c2 4267{
4bff1e86 4268 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4269 struct kvm_segment var;
4270
1aa36616 4271 var.selector = selector;
2dafc6c2 4272 var.base = get_desc_base(desc);
5601d05b
GN		 4273#ifdef CONFIG_X86_64
4274 var.base |= ((u64)base3) << 32;
4275#endif
2dafc6c2
GN		 4276 var.limit = get_desc_limit(desc);
4277 if (desc->g)
4278 var.limit = (var.limit << 12) | 0xfff;
4279 var.type = desc->type;
4280 var.present = desc->p;
4281 var.dpl = desc->dpl;
4282 var.db = desc->d;
4283 var.s = desc->s;
4284 var.l = desc->l;
4285 var.g = desc->g;
4286 var.avl = desc->avl;
4287 var.present = desc->p;
4288 var.unusable = !var.present;
4289 var.padding = 0;
4290
4291 kvm_set_segment(vcpu, &var, seg);
4292 return;
4293}
4294
717746e3
AK		 4295static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4296 u32 msr_index, u64 *pdata)
4297{
4298 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4299}
4300
4301static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4302 u32 msr_index, u64 data)
4303{
4304 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4305}
4306
222d21aa
AK		 4307static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4308 u32 pmc, u64 *pdata)
4309{
4310 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4311}
4312
6c3287f7
AK		 4313static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4314{
4315 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4316}
4317
5037f6f3
AK		 4318static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4319{
4320 preempt_disable();
5197b808 4321 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4322 /*
4323 * CR0.TS may reference the host fpu state, not the guest fpu state,
4324 * so it may be clear at this point.
4325 */
4326 clts();
4327}
4328
4329static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4330{
4331 preempt_enable();
4332}
4333
2953538e 4334static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4335 struct x86_instruction_info *info,
c4f035c6
AK		 4336 enum x86_intercept_stage stage)
4337{
2953538e 4338 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4339}
4340
0017f93a 4341static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4342 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4343{
0017f93a 4344 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4345}
4346
dd856efa
AK		 4347static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4348{
4349 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4350}
4351
4352static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4353{
4354 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4355}
4356
0225fb50 4357static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4358 .read_gpr = emulator_read_gpr,
4359 .write_gpr = emulator_write_gpr,
1871c602 4360 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4361 .write_std = kvm_write_guest_virt_system,
1871c602 4362 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4363 .read_emulated = emulator_read_emulated,
4364 .write_emulated = emulator_write_emulated,
4365 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4366 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4367 .pio_in_emulated = emulator_pio_in_emulated,
4368 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4369 .get_segment = emulator_get_segment,
4370 .set_segment = emulator_set_segment,
5951c442 4371 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4372 .get_gdt = emulator_get_gdt,
160ce1f1 4373 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4374 .set_gdt = emulator_set_gdt,
4375 .set_idt = emulator_set_idt,
52a46617
GN		 4376 .get_cr = emulator_get_cr,
4377 .set_cr = emulator_set_cr,
4cee4798 4378 .set_rflags = emulator_set_rflags,
9c537244 4379 .cpl = emulator_get_cpl,
35aa5375
GN		 4380 .get_dr = emulator_get_dr,
4381 .set_dr = emulator_set_dr,
717746e3
AK		 4382 .set_msr = emulator_set_msr,
4383 .get_msr = emulator_get_msr,
222d21aa 4384 .read_pmc = emulator_read_pmc,
6c3287f7 4385 .halt = emulator_halt,
bcaf5cc5 4386 .wbinvd = emulator_wbinvd,
d6aa1000 4387 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4388 .get_fpu = emulator_get_fpu,
4389 .put_fpu = emulator_put_fpu,
c4f035c6 4390 .intercept = emulator_intercept,
bdb42f5a 4391 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4392};
4393
95cb2295
GN		 4394static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4395{
4396 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4397 /*
4398 * an sti; sti; sequence only disable interrupts for the first
4399 * instruction. So, if the last instruction, be it emulated or
4400 * not, left the system with the INT_STI flag enabled, it
4401 * means that the last instruction is an sti. We should not
4402 * leave the flag on in this case. The same goes for mov ss
4403 */
4404 if (!(int_shadow & mask))
4405 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4406}
4407
54b8486f
GN		 4408static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4409{
4410 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4411 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4412 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4413 else if (ctxt->exception.error_code_valid)
4414 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4415 ctxt->exception.error_code);
54b8486f 4416 else
da9cb575 4417 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4418}
4419
dd856efa 4420static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4421{
9dac77fa 4422 memset(&ctxt->twobyte, 0,
dd856efa 4423 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4424
9dac77fa
AK		 4425 ctxt->fetch.start = 0;
4426 ctxt->fetch.end = 0;
4427 ctxt->io_read.pos = 0;
4428 ctxt->io_read.end = 0;
4429 ctxt->mem_read.pos = 0;
4430 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4431}
4432
8ec4722d
MG		 4433static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4434{
adf52235 4435 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4436 int cs_db, cs_l;
4437
8ec4722d
MG		 4438 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4439
adf52235
TY		 4440 ctxt->eflags = kvm_get_rflags(vcpu);
4441 ctxt->eip = kvm_rip_read(vcpu);
4442 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4443 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4444 cs_l ? X86EMUL_MODE_PROT64 :
4445 cs_db ? X86EMUL_MODE_PROT32 :
4446 X86EMUL_MODE_PROT16;
4447 ctxt->guest_mode = is_guest_mode(vcpu);
4448
dd856efa 4449 init_decode_cache(ctxt);
7ae441ea 4450 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4451}
4452
71f9833b 4453int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4454{
9d74191a 4455 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4456 int ret;
4457
4458 init_emulate_ctxt(vcpu);
4459
9dac77fa
AK		 4460 ctxt->op_bytes = 2;
4461 ctxt->ad_bytes = 2;
4462 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4463 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4464
4465 if (ret != X86EMUL_CONTINUE)
4466 return EMULATE_FAIL;
4467
9dac77fa 4468 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4469 kvm_rip_write(vcpu, ctxt->eip);
4470 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4471
4472 if (irq == NMI_VECTOR)
7460fb4a 4473 vcpu->arch.nmi_pending = 0;
63995653
MG		 4474 else
4475 vcpu->arch.interrupt.pending = false;
4476
4477 return EMULATE_DONE;
4478}
4479EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4480
6d77dbfc
GN		 4481static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4482{
fc3a9157
JR		 4483 int r = EMULATE_DONE;
4484
6d77dbfc
GN		 4485 ++vcpu->stat.insn_emulation_fail;
4486 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4487 if (!is_guest_mode(vcpu)) {
4488 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4489 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4490 vcpu->run->internal.ndata = 0;
4491 r = EMULATE_FAIL;
4492 }
6d77dbfc 4493 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4494
4495 return r;
6d77dbfc
GN		 4496}
4497
a6f177ef
GN		 4498static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4499{
4500 gpa_t gpa;
8e3d9d06 4501 pfn_t pfn;
a6f177ef 4502
68be0803
GN		 4503 if (tdp_enabled)
4504 return false;
4505
a6f177ef
GN		 4506 /*
4507 * if emulation was due to access to shadowed page table
4a969980 4508 * and it failed try to unshadow page and re-enter the
a6f177ef
GN		 4509 * guest to let CPU execute the instruction.
4510 */
4511 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4512 return true;
4513
4514 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4515
4516 if (gpa == UNMAPPED_GVA)
4517 return true; /* let cpu generate fault */
4518
8e3d9d06
XG		 4519 /*
4520 * Do not retry the unhandleable instruction if it faults on the
4521 * readonly host memory, otherwise it will goto a infinite loop:
4522 * retry instruction -> write #PF -> emulation fail -> retry
4523 * instruction -> ...
4524 */
4525 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
81c52c56 4526 if (!is_error_noslot_pfn(pfn)) {
8e3d9d06 4527 kvm_release_pfn_clean(pfn);
a6f177ef 4528 return true;
8e3d9d06 4529 }
a6f177ef
GN		 4530
4531 return false;
4532}
4533
1cb3f3ae
XG		 4534static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4535 unsigned long cr2, int emulation_type)
4536{
4537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4538 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4539
4540 last_retry_eip = vcpu->arch.last_retry_eip;
4541 last_retry_addr = vcpu->arch.last_retry_addr;
4542
4543 /*
4544 * If the emulation is caused by #PF and it is non-page_table
4545 * writing instruction, it means the VM-EXIT is caused by shadow
4546 * page protected, we can zap the shadow page and retry this
4547 * instruction directly.
4548 *
4549 * Note: if the guest uses a non-page-table modifying instruction
4550 * on the PDE that points to the instruction, then we will unmap
4551 * the instruction and go to an infinite loop. So, we cache the
4552 * last retried eip and the last fault address, if we meet the eip
4553 * and the address again, we can break out of the potential infinite
4554 * loop.
4555 */
4556 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4557
4558 if (!(emulation_type & EMULTYPE_RETRY))
4559 return false;
4560
4561 if (x86_page_table_writing_insn(ctxt))
4562 return false;
4563
4564 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4565 return false;
4566
4567 vcpu->arch.last_retry_eip = ctxt->eip;
4568 vcpu->arch.last_retry_addr = cr2;
4569
4570 if (!vcpu->arch.mmu.direct_map)
4571 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4572
4573 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4574
4575 return true;
4576}
4577
716d51ab
GN		 4578static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4579static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4580
51d8b661
AP		 4581int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4582 unsigned long cr2,
dc25e89e
AP		 4583 int emulation_type,
4584 void *insn,
4585 int insn_len)
bbd9b64e 4586{
95cb2295 4587 int r;
9d74191a 4588 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4589 bool writeback = true;
bbd9b64e 4590
26eef70c 4591 kvm_clear_exception_queue(vcpu);
8d7d8102 4592
571008da 4593 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4594 init_emulate_ctxt(vcpu);
9d74191a
TY		 4595 ctxt->interruptibility = 0;
4596 ctxt->have_exception = false;
4597 ctxt->perm_ok = false;
bbd9b64e 4598
9d74191a 4599 ctxt->only_vendor_specific_insn
4005996e
AK		 4600 = emulation_type & EMULTYPE_TRAP_UD;
4601
9d74191a 4602 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4603
e46479f8 4604 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4605 ++vcpu->stat.insn_emulation;
1d2887e2 4606 if (r != EMULATION_OK) {
4005996e
AK		 4607 if (emulation_type & EMULTYPE_TRAP_UD)
4608 return EMULATE_FAIL;
a6f177ef 4609 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4610 return EMULATE_DONE;
6d77dbfc
GN		 4611 if (emulation_type & EMULTYPE_SKIP)
4612 return EMULATE_FAIL;
4613 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4614 }
4615 }
4616
ba8afb6b 4617 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4618 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4619 return EMULATE_DONE;
4620 }
4621
1cb3f3ae
XG		 4622 if (retry_instruction(ctxt, cr2, emulation_type))
4623 return EMULATE_DONE;
4624
7ae441ea 4625 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4626 changes registers values during IO operation */
7ae441ea
GN		 4627 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4628 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4629 emulator_invalidate_register_cache(ctxt);
7ae441ea 4630 }
4d2179e1 4631
5cd21917 4632restart:
9d74191a 4633 r = x86_emulate_insn(ctxt);
bbd9b64e 4634
775fde86
JR		 4635 if (r == EMULATION_INTERCEPTED)
4636 return EMULATE_DONE;
4637
d2ddd1c4 4638 if (r == EMULATION_FAILED) {
a6f177ef 4639 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4640 return EMULATE_DONE;
4641
6d77dbfc 4642 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4643 }
4644
9d74191a 4645 if (ctxt->have_exception) {
54b8486f 4646 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4647 r = EMULATE_DONE;
4648 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4649 if (!vcpu->arch.pio.in)
4650 vcpu->arch.pio.count = 0;
716d51ab 4651 else {
7ae441ea 4652 writeback = false;
716d51ab
GN		 4653 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4654 }
e85d28f8 4655 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4656 } else if (vcpu->mmio_needed) {
4657 if (!vcpu->mmio_is_write)
4658 writeback = false;
e85d28f8 4659 r = EMULATE_DO_MMIO;
716d51ab 4660 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 4661 } else if (r == EMULATION_RESTART)
5cd21917 4662 goto restart;
d2ddd1c4
GN		 4663 else
4664 r = EMULATE_DONE;
f850e2e6 4665
7ae441ea 4666 if (writeback) {
9d74191a
TY		 4667 toggle_interruptibility(vcpu, ctxt->interruptibility);
4668 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4669 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 4670 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4671 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4672 } else
4673 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4674
4675 return r;
de7d789a 4676}
51d8b661 4677EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4678
cf8f70bf 4679int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4680{
cf8f70bf 4681 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4682 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4683 size, port, &val, 1);
cf8f70bf 4684 /* do not return to emulator after return from userspace */
7972995b 4685 vcpu->arch.pio.count = 0;
de7d789a
CO		 4686 return ret;
4687}
cf8f70bf 4688EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4689
8cfdc000
ZA		 4690static void tsc_bad(void *info)
4691{
0a3aee0d 4692 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4693}
4694
4695static void tsc_khz_changed(void *data)
c8076604 4696{
8cfdc000
ZA		 4697 struct cpufreq_freqs *freq = data;
4698 unsigned long khz = 0;
4699
4700 if (data)
4701 khz = freq->new;
4702 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4703 khz = cpufreq_quick_get(raw_smp_processor_id());
4704 if (!khz)
4705 khz = tsc_khz;
0a3aee0d 4706 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4707}
4708
c8076604
GH		 4709static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4710 void *data)
4711{
4712 struct cpufreq_freqs *freq = data;
4713 struct kvm *kvm;
4714 struct kvm_vcpu *vcpu;
4715 int i, send_ipi = 0;
4716
8cfdc000
ZA		 4717 /*
4718 * We allow guests to temporarily run on slowing clocks,
4719 * provided we notify them after, or to run on accelerating
4720 * clocks, provided we notify them before. Thus time never
4721 * goes backwards.
4722 *
4723 * However, we have a problem. We can't atomically update
4724 * the frequency of a given CPU from this function; it is
4725 * merely a notifier, which can be called from any CPU.
4726 * Changing the TSC frequency at arbitrary points in time
4727 * requires a recomputation of local variables related to
4728 * the TSC for each VCPU. We must flag these local variables
4729 * to be updated and be sure the update takes place with the
4730 * new frequency before any guests proceed.
4731 *
4732 * Unfortunately, the combination of hotplug CPU and frequency
4733 * change creates an intractable locking scenario; the order
4734 * of when these callouts happen is undefined with respect to
4735 * CPU hotplug, and they can race with each other. As such,
4736 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4737 * undefined; you can actually have a CPU frequency change take
4738 * place in between the computation of X and the setting of the
4739 * variable. To protect against this problem, all updates of
4740 * the per_cpu tsc_khz variable are done in an interrupt
4741 * protected IPI, and all callers wishing to update the value
4742 * must wait for a synchronous IPI to complete (which is trivial
4743 * if the caller is on the CPU already). This establishes the
4744 * necessary total order on variable updates.
4745 *
4746 * Note that because a guest time update may take place
4747 * anytime after the setting of the VCPU's request bit, the
4748 * correct TSC value must be set before the request. However,
4749 * to ensure the update actually makes it to any guest which
4750 * starts running in hardware virtualization between the set
4751 * and the acquisition of the spinlock, we must also ping the
4752 * CPU after setting the request bit.
4753 *
4754 */
4755
c8076604
GH		 4756 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4757 return 0;
4758 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4759 return 0;
8cfdc000
ZA		 4760
4761 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4762
e935b837 4763 raw_spin_lock(&kvm_lock);
c8076604 4764 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4765 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4766 if (vcpu->cpu != freq->cpu)
4767 continue;
c285545f 4768 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4769 if (vcpu->cpu != smp_processor_id())
8cfdc000 4770 send_ipi = 1;
c8076604
GH		 4771 }
4772 }
e935b837 4773 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4774
4775 if (freq->old < freq->new && send_ipi) {
4776 /*
4777 * We upscale the frequency. Must make the guest
4778 * doesn't see old kvmclock values while running with
4779 * the new frequency, otherwise we risk the guest sees
4780 * time go backwards.
4781 *
4782 * In case we update the frequency for another cpu
4783 * (which might be in guest context) send an interrupt
4784 * to kick the cpu out of guest context. Next time
4785 * guest context is entered kvmclock will be updated,
4786 * so the guest will not see stale values.
4787 */
8cfdc000 4788 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4789 }
4790 return 0;
4791}
4792
4793static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4794 .notifier_call = kvmclock_cpufreq_notifier
4795};
4796
4797static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4798 unsigned long action, void *hcpu)
4799{
4800 unsigned int cpu = (unsigned long)hcpu;
4801
4802 switch (action) {
4803 case CPU_ONLINE:
4804 case CPU_DOWN_FAILED:
4805 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4806 break;
4807 case CPU_DOWN_PREPARE:
4808 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4809 break;
4810 }
4811 return NOTIFY_OK;
4812}
4813
4814static struct notifier_block kvmclock_cpu_notifier_block = {
4815 .notifier_call = kvmclock_cpu_notifier,
4816 .priority = -INT_MAX
c8076604
GH		 4817};
4818
b820cc0c
ZA		 4819static void kvm_timer_init(void)
4820{
4821 int cpu;
4822
c285545f 4823 max_tsc_khz = tsc_khz;
8cfdc000 4824 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4825 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4826#ifdef CONFIG_CPU_FREQ
4827 struct cpufreq_policy policy;
4828 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4829 cpu = get_cpu();
4830 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4831 if (policy.cpuinfo.max_freq)
4832 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4833 put_cpu();
c285545f 4834#endif
b820cc0c
ZA		 4835 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4836 CPUFREQ_TRANSITION_NOTIFIER);
4837 }
c285545f 4838 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4839 for_each_online_cpu(cpu)
4840 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4841}
4842
ff9d07a0
ZY		 4843static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4844
f5132b01 4845int kvm_is_in_guest(void)
ff9d07a0 4846{
086c9855 4847 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4848}
4849
4850static int kvm_is_user_mode(void)
4851{
4852 int user_mode = 3;
dcf46b94 4853
086c9855
AS		 4854 if (__this_cpu_read(current_vcpu))
4855 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4856
ff9d07a0
ZY		 4857 return user_mode != 0;
4858}
4859
4860static unsigned long kvm_get_guest_ip(void)
4861{
4862 unsigned long ip = 0;
dcf46b94 4863
086c9855
AS		 4864 if (__this_cpu_read(current_vcpu))
4865 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4866
ff9d07a0
ZY		 4867 return ip;
4868}
4869
4870static struct perf_guest_info_callbacks kvm_guest_cbs = {
4871 .is_in_guest = kvm_is_in_guest,
4872 .is_user_mode = kvm_is_user_mode,
4873 .get_guest_ip = kvm_get_guest_ip,
4874};
4875
4876void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4877{
086c9855 4878 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4879}
4880EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4881
4882void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4883{
086c9855 4884 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4885}
4886EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4887
ce88decf
XG		 4888static void kvm_set_mmio_spte_mask(void)
4889{
4890 u64 mask;
4891 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4892
4893 /*
4894 * Set the reserved bits and the present bit of an paging-structure
4895 * entry to generate page fault with PFER.RSV = 1.
4896 */
4897 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4898 mask |= 1ull;
4899
4900#ifdef CONFIG_X86_64
4901 /*
4902 * If reserved bit is not supported, clear the present bit to disable
4903 * mmio page fault.
4904 */
4905 if (maxphyaddr == 52)
4906 mask &= ~1ull;
4907#endif
4908
4909 kvm_mmu_set_mmio_spte_mask(mask);
4910}
4911
16e8d74d
MT		 4912#ifdef CONFIG_X86_64
4913static void pvclock_gtod_update_fn(struct work_struct *work)
4914{
4915}
4916
4917static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
4918
4919/*
4920 * Notification about pvclock gtod data update.
4921 */
4922static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
4923 void *priv)
4924{
4925 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
4926 struct timekeeper *tk = priv;
4927
4928 update_pvclock_gtod(tk);
4929
4930 /* disable master clock if host does not trust, or does not
4931 * use, TSC clocksource
4932 */
4933 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
4934 atomic_read(&kvm_guest_has_master_clock) != 0)
4935 queue_work(system_long_wq, &pvclock_gtod_work);
4936
4937 return 0;
4938}
4939
4940static struct notifier_block pvclock_gtod_notifier = {
4941 .notifier_call = pvclock_gtod_notify,
4942};
4943#endif
4944
f8c16bba 4945int kvm_arch_init(void *opaque)
043405e1 4946{
b820cc0c 4947 int r;
f8c16bba
ZX		 4948 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4949
f8c16bba
ZX		 4950 if (kvm_x86_ops) {
4951 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4952 r = -EEXIST;
4953 goto out;
f8c16bba
ZX		 4954 }
4955
4956 if (!ops->cpu_has_kvm_support()) {
4957 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4958 r = -EOPNOTSUPP;
4959 goto out;
f8c16bba
ZX		 4960 }
4961 if (ops->disabled_by_bios()) {
4962 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4963 r = -EOPNOTSUPP;
4964 goto out;
f8c16bba
ZX		 4965 }
4966
97db56ce
AK		 4967 r = kvm_mmu_module_init();
4968 if (r)
4969 goto out;
4970
ce88decf 4971 kvm_set_mmio_spte_mask();
97db56ce
AK		 4972 kvm_init_msr_list();
4973
f8c16bba 4974 kvm_x86_ops = ops;
7b52345e 4975 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4976 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4977
b820cc0c 4978 kvm_timer_init();
c8076604 4979
ff9d07a0
ZY		 4980 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4981
2acf923e
DC		 4982 if (cpu_has_xsave)
4983 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4984
c5cc421b 4985 kvm_lapic_init();
16e8d74d
MT		 4986#ifdef CONFIG_X86_64
4987 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
4988#endif
4989
f8c16bba 4990 return 0;
56c6d28a
ZX		 4991
4992out:
56c6d28a 4993 return r;
043405e1 4994}
8776e519 4995
f8c16bba
ZX		 4996void kvm_arch_exit(void)
4997{
ff9d07a0
ZY		 4998 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4999
888d256e
JK		 5000 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5001 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5002 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5003 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5004#ifdef CONFIG_X86_64
5005 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5006#endif
f8c16bba 5007 kvm_x86_ops = NULL;
56c6d28a
ZX		 5008 kvm_mmu_module_exit();
5009}
f8c16bba 5010
8776e519
HB		 5011int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5012{
5013 ++vcpu->stat.halt_exits;
5014 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5015 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5016 return 1;
5017 } else {
5018 vcpu->run->exit_reason = KVM_EXIT_HLT;
5019 return 0;
5020 }
5021}
5022EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5023
55cd8e5a
GN		 5024int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5025{
5026 u64 param, ingpa, outgpa, ret;
5027 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5028 bool fast, longmode;
5029 int cs_db, cs_l;
5030
5031 /*
5032 * hypercall generates UD from non zero cpl and real mode
5033 * per HYPER-V spec
5034 */
3eeb3288 5035 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5036 kvm_queue_exception(vcpu, UD_VECTOR);
5037 return 0;
5038 }
5039
5040 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5041 longmode = is_long_mode(vcpu) && cs_l == 1;
5042
5043 if (!longmode) {
ccd46936
GN		 5044 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5045 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5046 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5047 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5048 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5049 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5050 }
5051#ifdef CONFIG_X86_64
5052 else {
5053 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5054 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5055 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5056 }
5057#endif
5058
5059 code = param & 0xffff;
5060 fast = (param >> 16) & 0x1;
5061 rep_cnt = (param >> 32) & 0xfff;
5062 rep_idx = (param >> 48) & 0xfff;
5063
5064 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5065
c25bc163
GN		 5066 switch (code) {
5067 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5068 kvm_vcpu_on_spin(vcpu);
5069 break;
5070 default:
5071 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5072 break;
5073 }
55cd8e5a
GN		 5074
5075 ret = res | (((u64)rep_done & 0xfff) << 32);
5076 if (longmode) {
5077 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5078 } else {
5079 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5080 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5081 }
5082
5083 return 1;
5084}
5085
8776e519
HB		 5086int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5087{
5088 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5089 int r = 1;
8776e519 5090
55cd8e5a
GN		 5091 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5092 return kvm_hv_hypercall(vcpu);
5093
5fdbf976
MT		 5094 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5095 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5096 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5097 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5098 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5099
229456fc 5100 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5101
8776e519
HB		 5102 if (!is_long_mode(vcpu)) {
5103 nr &= 0xFFFFFFFF;
5104 a0 &= 0xFFFFFFFF;
5105 a1 &= 0xFFFFFFFF;
5106 a2 &= 0xFFFFFFFF;
5107 a3 &= 0xFFFFFFFF;
5108 }
5109
07708c4a
JK		 5110 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5111 ret = -KVM_EPERM;
5112 goto out;
5113 }
5114
8776e519 5115 switch (nr) {
b93463aa
AK		 5116 case KVM_HC_VAPIC_POLL_IRQ:
5117 ret = 0;
5118 break;
8776e519
HB		 5119 default:
5120 ret = -KVM_ENOSYS;
5121 break;
5122 }
07708c4a 5123out:
5fdbf976 5124 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5125 ++vcpu->stat.hypercalls;
2f333bcb 5126 return r;
8776e519
HB		 5127}
5128EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5129
b6785def 5130static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5131{
d6aa1000 5132 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5133 char instruction[3];
5fdbf976 5134 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5135
8776e519
HB		 5136 /*
5137 * Blow out the MMU to ensure that no other VCPU has an active mapping
5138 * to ensure that the updated hypercall appears atomically across all
5139 * VCPUs.
5140 */
5141 kvm_mmu_zap_all(vcpu->kvm);
5142
8776e519 5143 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5144
9d74191a 5145 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5146}
5147
b6c7a5dc
HB		 5148/*
5149 * Check if userspace requested an interrupt window, and that the
5150 * interrupt window is open.
5151 *
5152 * No need to exit to userspace if we already have an interrupt queued.
5153 */
851ba692 5154static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5155{
8061823a 5156 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5157 vcpu->run->request_interrupt_window &&
5df56646 5158 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5159}
5160
851ba692 5161static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5162{
851ba692
AK		 5163 struct kvm_run *kvm_run = vcpu->run;
5164
91586a3b 5165 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5166 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5167 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5168 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5169 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5170 else
b6c7a5dc 5171 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5172 kvm_arch_interrupt_allowed(vcpu) &&
5173 !kvm_cpu_has_interrupt(vcpu) &&
5174 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5175}
5176
4484141a 5177static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5178{
5179 struct kvm_lapic *apic = vcpu->arch.apic;
5180 struct page *page;
5181
5182 if (!apic || !apic->vapic_addr)
4484141a 5183 return 0;
b93463aa
AK		 5184
5185 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5186 if (is_error_page(page))
5187 return -EFAULT;
72dc67a6
IE		 5188
5189 vcpu->arch.apic->vapic_page = page;
4484141a 5190 return 0;
b93463aa
AK		 5191}
5192
5193static void vapic_exit(struct kvm_vcpu *vcpu)
5194{
5195 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5196 int idx;
b93463aa
AK		 5197
5198 if (!apic || !apic->vapic_addr)
5199 return;
5200
f656ce01 5201 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5202 kvm_release_page_dirty(apic->vapic_page);
5203 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5204 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5205}
5206
95ba8273
GN		 5207static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5208{
5209 int max_irr, tpr;
5210
5211 if (!kvm_x86_ops->update_cr8_intercept)
5212 return;
5213
88c808fd
AK		 5214 if (!vcpu->arch.apic)
5215 return;
5216
8db3baa2
GN		 5217 if (!vcpu->arch.apic->vapic_addr)
5218 max_irr = kvm_lapic_find_highest_irr(vcpu);
5219 else
5220 max_irr = -1;
95ba8273
GN		 5221
5222 if (max_irr != -1)
5223 max_irr >>= 4;
5224
5225 tpr = kvm_lapic_get_cr8(vcpu);
5226
5227 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5228}
5229
851ba692 5230static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5231{
5232 /* try to reinject previous events if any */
b59bb7bd 5233 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5234 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5235 vcpu->arch.exception.has_error_code,
5236 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5237 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5238 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5239 vcpu->arch.exception.error_code,
5240 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5241 return;
5242 }
5243
95ba8273
GN		 5244 if (vcpu->arch.nmi_injected) {
5245 kvm_x86_ops->set_nmi(vcpu);
5246 return;
5247 }
5248
5249 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5250 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5251 return;
5252 }
5253
5254 /* try to inject new event if pending */
5255 if (vcpu->arch.nmi_pending) {
5256 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5257 --vcpu->arch.nmi_pending;
95ba8273
GN		 5258 vcpu->arch.nmi_injected = true;
5259 kvm_x86_ops->set_nmi(vcpu);
5260 }
5261 } else if (kvm_cpu_has_interrupt(vcpu)) {
5262 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5263 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5264 false);
5265 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5266 }
5267 }
5268}
5269
2acf923e
DC		 5270static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5271{
5272 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5273 !vcpu->guest_xcr0_loaded) {
5274 /* kvm_set_xcr() also depends on this */
5275 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5276 vcpu->guest_xcr0_loaded = 1;
5277 }
5278}
5279
5280static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5281{
5282 if (vcpu->guest_xcr0_loaded) {
5283 if (vcpu->arch.xcr0 != host_xcr0)
5284 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5285 vcpu->guest_xcr0_loaded = 0;
5286 }
5287}
5288
7460fb4a
AK		 5289static void process_nmi(struct kvm_vcpu *vcpu)
5290{
5291 unsigned limit = 2;
5292
5293 /*
5294 * x86 is limited to one NMI running, and one NMI pending after it.
5295 * If an NMI is already in progress, limit further NMIs to just one.
5296 * Otherwise, allow two (and we'll inject the first one immediately).
5297 */
5298 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5299 limit = 1;
5300
5301 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5302 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5303 kvm_make_request(KVM_REQ_EVENT, vcpu);
5304}
5305
851ba692 5306static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5307{
5308 int r;
6a8b1d13 5309 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5310 vcpu->run->request_interrupt_window;
d6185f20 5311 bool req_immediate_exit = 0;
b6c7a5dc 5312
3e007509 5313 if (vcpu->requests) {
a8eeb04a 5314 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5315 kvm_mmu_unload(vcpu);
a8eeb04a 5316 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5317 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5318 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5319 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5320 if (unlikely(r))
5321 goto out;
5322 }
a8eeb04a 5323 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5324 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5325 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5326 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5327 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5328 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5329 r = 0;
5330 goto out;
5331 }
a8eeb04a 5332 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5333 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5334 r = 0;
5335 goto out;
5336 }
a8eeb04a 5337 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5338 vcpu->fpu_active = 0;
5339 kvm_x86_ops->fpu_deactivate(vcpu);
5340 }
af585b92
GN		 5341 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5342 /* Page is swapped out. Do synthetic halt */
5343 vcpu->arch.apf.halted = true;
5344 r = 1;
5345 goto out;
5346 }
c9aaa895
GC		 5347 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5348 record_steal_time(vcpu);
7460fb4a
AK		 5349 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5350 process_nmi(vcpu);
d6185f20
NHE		 5351 req_immediate_exit =
5352 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5353 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5354 kvm_handle_pmu_event(vcpu);
5355 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5356 kvm_deliver_pmi(vcpu);
2f52d58c 5357 }
b93463aa 5358
b463a6f7
AK		 5359 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5360 inject_pending_event(vcpu);
5361
5362 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5363 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5364 kvm_x86_ops->enable_nmi_window(vcpu);
5365 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5366 kvm_x86_ops->enable_irq_window(vcpu);
5367
5368 if (kvm_lapic_enabled(vcpu)) {
5369 update_cr8_intercept(vcpu);
5370 kvm_lapic_sync_to_vapic(vcpu);
5371 }
5372 }
5373
d8368af8
AK		 5374 r = kvm_mmu_reload(vcpu);
5375 if (unlikely(r)) {
d905c069 5376 goto cancel_injection;
d8368af8
AK		 5377 }
5378
b6c7a5dc
HB		 5379 preempt_disable();
5380
5381 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5382 if (vcpu->fpu_active)
5383 kvm_load_guest_fpu(vcpu);
2acf923e 5384 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5385
6b7e2d09
XG		 5386 vcpu->mode = IN_GUEST_MODE;
5387
5388 /* We should set ->mode before check ->requests,
5389 * see the comment in make_all_cpus_request.
5390 */
5391 smp_mb();
b6c7a5dc 5392
d94e1dc9 5393 local_irq_disable();
32f88400 5394
6b7e2d09 5395 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5396 || need_resched() || signal_pending(current)) {
6b7e2d09 5397 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5398 smp_wmb();
6c142801
AK		 5399 local_irq_enable();
5400 preempt_enable();
5401 r = 1;
d905c069 5402 goto cancel_injection;
6c142801
AK		 5403 }
5404
f656ce01 5405 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5406
d6185f20
NHE		 5407 if (req_immediate_exit)
5408 smp_send_reschedule(vcpu->cpu);
5409
b6c7a5dc
HB		 5410 kvm_guest_enter();
5411
42dbaa5a 5412 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5413 set_debugreg(0, 7);
5414 set_debugreg(vcpu->arch.eff_db[0], 0);
5415 set_debugreg(vcpu->arch.eff_db[1], 1);
5416 set_debugreg(vcpu->arch.eff_db[2], 2);
5417 set_debugreg(vcpu->arch.eff_db[3], 3);
5418 }
b6c7a5dc 5419
229456fc 5420 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5421 kvm_x86_ops->run(vcpu);
b6c7a5dc 5422
24f1e32c
FW		 5423 /*
5424 * If the guest has used debug registers, at least dr7
5425 * will be disabled while returning to the host.
5426 * If we don't have active breakpoints in the host, we don't
5427 * care about the messed up debug address registers. But if
5428 * we have some of them active, restore the old state.
5429 */
59d8eb53 5430 if (hw_breakpoint_active())
24f1e32c 5431 hw_breakpoint_restore();
42dbaa5a 5432
886b470c
MT		 5433 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5434 native_read_tsc());
1d5f066e 5435
6b7e2d09 5436 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5437 smp_wmb();
b6c7a5dc
HB		 5438 local_irq_enable();
5439
5440 ++vcpu->stat.exits;
5441
5442 /*
5443 * We must have an instruction between local_irq_enable() and
5444 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5445 * the interrupt shadow. The stat.exits increment will do nicely.
5446 * But we need to prevent reordering, hence this barrier():
5447 */
5448 barrier();
5449
5450 kvm_guest_exit();
5451
5452 preempt_enable();
5453
f656ce01 5454 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5455
b6c7a5dc
HB		 5456 /*
5457 * Profile KVM exit RIPs:
5458 */
5459 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5460 unsigned long rip = kvm_rip_read(vcpu);
5461 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5462 }
5463
cc578287
ZA		 5464 if (unlikely(vcpu->arch.tsc_always_catchup))
5465 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5466
5cfb1d5a
MT		 5467 if (vcpu->arch.apic_attention)
5468 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5469
851ba692 5470 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5471 return r;
5472
5473cancel_injection:
5474 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5475 if (unlikely(vcpu->arch.apic_attention))
5476 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5477out:
5478 return r;
5479}
b6c7a5dc 5480
09cec754 5481
851ba692 5482static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5483{
5484 int r;
f656ce01 5485 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5486
5487 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5488 pr_debug("vcpu %d received sipi with vector # %x\n",
5489 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5490 kvm_lapic_reset(vcpu);
8b6e4547 5491 r = kvm_vcpu_reset(vcpu);
d7690175
MT		 5492 if (r)
5493 return r;
5494 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5495 }
5496
f656ce01 5497 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 5498 r = vapic_enter(vcpu);
5499 if (r) {
5500 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5501 return r;
5502 }
d7690175
MT		 5503
5504 r = 1;
5505 while (r > 0) {
af585b92
GN		 5506 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5507 !vcpu->arch.apf.halted)
851ba692 5508 r = vcpu_enter_guest(vcpu);
d7690175 5509 else {
f656ce01 5510 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5511 kvm_vcpu_block(vcpu);
f656ce01 5512 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5513 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5514 {
5515 switch(vcpu->arch.mp_state) {
5516 case KVM_MP_STATE_HALTED:
d7690175 5517 vcpu->arch.mp_state =
09cec754
GN		 5518 KVM_MP_STATE_RUNNABLE;
5519 case KVM_MP_STATE_RUNNABLE:
af585b92 5520 vcpu->arch.apf.halted = false;
09cec754
GN		 5521 break;
5522 case KVM_MP_STATE_SIPI_RECEIVED:
5523 default:
5524 r = -EINTR;
5525 break;
5526 }
5527 }
d7690175
MT		 5528 }
5529
09cec754
GN		 5530 if (r <= 0)
5531 break;
5532
5533 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5534 if (kvm_cpu_has_pending_timer(vcpu))
5535 kvm_inject_pending_timer_irqs(vcpu);
5536
851ba692 5537 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5538 r = -EINTR;
851ba692 5539 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5540 ++vcpu->stat.request_irq_exits;
5541 }
af585b92
GN		 5542
5543 kvm_check_async_pf_completion(vcpu);
5544
09cec754
GN		 5545 if (signal_pending(current)) {
5546 r = -EINTR;
851ba692 5547 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5548 ++vcpu->stat.signal_exits;
5549 }
5550 if (need_resched()) {
f656ce01 5551 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5552 kvm_resched(vcpu);
f656ce01 5553 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5554 }
b6c7a5dc
HB		 5555 }
5556
f656ce01 5557 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5558
b93463aa
AK		 5559 vapic_exit(vcpu);
5560
b6c7a5dc
HB		 5561 return r;
5562}
5563
716d51ab
GN		 5564static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5565{
5566 int r;
5567 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5568 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5569 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5570 if (r != EMULATE_DONE)
5571 return 0;
5572 return 1;
5573}
5574
5575static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5576{
5577 BUG_ON(!vcpu->arch.pio.count);
5578
5579 return complete_emulated_io(vcpu);
5580}
5581
f78146b0
AK		 5582/*
5583 * Implements the following, as a state machine:
5584 *
5585 * read:
5586 * for each fragment
5587 * write gpa, len
5588 * exit
5589 * copy data
5590 * execute insn
5591 *
5592 * write:
5593 * for each fragment
5594 * write gpa, len
5595 * copy data
5596 * exit
5597 */
716d51ab 5598static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 5599{
5600 struct kvm_run *run = vcpu->run;
f78146b0 5601 struct kvm_mmio_fragment *frag;
5287f194 5602
716d51ab 5603 BUG_ON(!vcpu->mmio_needed);
5287f194 5604
716d51ab
GN		 5605 /* Complete previous fragment */
5606 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5607 if (!vcpu->mmio_is_write)
5608 memcpy(frag->data, run->mmio.data, frag->len);
5609 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5610 vcpu->mmio_needed = 0;
cef4dea0 5611 if (vcpu->mmio_is_write)
716d51ab
GN		 5612 return 1;
5613 vcpu->mmio_read_completed = 1;
5614 return complete_emulated_io(vcpu);
5615 }
5616 /* Initiate next fragment */
5617 ++frag;
5618 run->exit_reason = KVM_EXIT_MMIO;
5619 run->mmio.phys_addr = frag->gpa;
5620 if (vcpu->mmio_is_write)
5621 memcpy(run->mmio.data, frag->data, frag->len);
5622 run->mmio.len = frag->len;
5623 run->mmio.is_write = vcpu->mmio_is_write;
5624 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5625 return 0;
5287f194
AK		 5626}
5627
716d51ab 5628
b6c7a5dc
HB		 5629int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5630{
5631 int r;
5632 sigset_t sigsaved;
5633
e5c30142
AK		 5634 if (!tsk_used_math(current) && init_fpu(current))
5635 return -ENOMEM;
5636
ac9f6dc0
AK		 5637 if (vcpu->sigset_active)
5638 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5639
a4535290 5640 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5641 kvm_vcpu_block(vcpu);
d7690175 5642 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5643 r = -EAGAIN;
5644 goto out;
b6c7a5dc
HB		 5645 }
5646
b6c7a5dc 5647 /* re-sync apic's tpr */
eea1cff9
AP		 5648 if (!irqchip_in_kernel(vcpu->kvm)) {
5649 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5650 r = -EINVAL;
5651 goto out;
5652 }
5653 }
b6c7a5dc 5654
716d51ab
GN		 5655 if (unlikely(vcpu->arch.complete_userspace_io)) {
5656 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
5657 vcpu->arch.complete_userspace_io = NULL;
5658 r = cui(vcpu);
5659 if (r <= 0)
5660 goto out;
5661 } else
5662 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 5663
851ba692 5664 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5665
5666out:
f1d86e46 5667 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5668 if (vcpu->sigset_active)
5669 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5670
b6c7a5dc
HB		 5671 return r;
5672}
5673
5674int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5675{
7ae441ea
GN		 5676 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5677 /*
5678 * We are here if userspace calls get_regs() in the middle of
5679 * instruction emulation. Registers state needs to be copied
4a969980 5680 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 5681 * that usually, but some bad designed PV devices (vmware
5682 * backdoor interface) need this to work
5683 */
dd856efa 5684 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 5685 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5686 }
5fdbf976
MT		 5687 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5688 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5689 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5690 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5691 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5692 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5693 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5694 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5695#ifdef CONFIG_X86_64
5fdbf976
MT		 5696 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5697 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5698 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5699 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5700 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5701 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5702 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5703 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5704#endif
5705
5fdbf976 5706 regs->rip = kvm_rip_read(vcpu);
91586a3b 5707 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5708
b6c7a5dc
HB		 5709 return 0;
5710}
5711
5712int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5713{
7ae441ea
GN		 5714 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5715 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5716
5fdbf976
MT		 5717 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5718 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5719 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5720 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5721 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5722 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5723 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5724 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5725#ifdef CONFIG_X86_64
5fdbf976
MT		 5726 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5727 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5728 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5729 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5730 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5731 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5732 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5733 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5734#endif
5735
5fdbf976 5736 kvm_rip_write(vcpu, regs->rip);
91586a3b 5737 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5738
b4f14abd
JK		 5739 vcpu->arch.exception.pending = false;
5740
3842d135
AK		 5741 kvm_make_request(KVM_REQ_EVENT, vcpu);
5742
b6c7a5dc
HB		 5743 return 0;
5744}
5745
b6c7a5dc
HB		 5746void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5747{
5748 struct kvm_segment cs;
5749
3e6e0aab 5750 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5751 *db = cs.db;
5752 *l = cs.l;
5753}
5754EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5755
5756int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5757 struct kvm_sregs *sregs)
5758{
89a27f4d 5759 struct desc_ptr dt;
b6c7a5dc 5760
3e6e0aab
GT		 5761 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5762 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5763 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5764 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5765 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5766 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5767
3e6e0aab
GT		 5768 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5769 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5770
5771 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5772 sregs->idt.limit = dt.size;
5773 sregs->idt.base = dt.address;
b6c7a5dc 5774 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5775 sregs->gdt.limit = dt.size;
5776 sregs->gdt.base = dt.address;
b6c7a5dc 5777
4d4ec087 5778 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5779 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5780 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5781 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5782 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5783 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5784 sregs->apic_base = kvm_get_apic_base(vcpu);
5785
923c61bb 5786 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5787
36752c9b 5788 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5789 set_bit(vcpu->arch.interrupt.nr,
5790 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5791
b6c7a5dc
HB		 5792 return 0;
5793}
5794
62d9f0db
MT		 5795int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5796 struct kvm_mp_state *mp_state)
5797{
62d9f0db 5798 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5799 return 0;
5800}
5801
5802int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5803 struct kvm_mp_state *mp_state)
5804{
62d9f0db 5805 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5806 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5807 return 0;
5808}
5809
7f3d35fd
KW		 5810int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5811 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 5812{
9d74191a 5813 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5814 int ret;
e01c2426 5815
8ec4722d 5816 init_emulate_ctxt(vcpu);
c697518a 5817
7f3d35fd 5818 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 5819 has_error_code, error_code);
c697518a 5820
c697518a 5821 if (ret)
19d04437 5822 return EMULATE_FAIL;
37817f29 5823
9d74191a
TY		 5824 kvm_rip_write(vcpu, ctxt->eip);
5825 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5826 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5827 return EMULATE_DONE;
37817f29
IE		 5828}
5829EXPORT_SYMBOL_GPL(kvm_task_switch);
5830
b6c7a5dc
HB		 5831int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5832 struct kvm_sregs *sregs)
5833{
5834 int mmu_reset_needed = 0;
63f42e02 5835 int pending_vec, max_bits, idx;
89a27f4d 5836 struct desc_ptr dt;
b6c7a5dc 5837
89a27f4d
GN		 5838 dt.size = sregs->idt.limit;
5839 dt.address = sregs->idt.base;
b6c7a5dc 5840 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5841 dt.size = sregs->gdt.limit;
5842 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5843 kvm_x86_ops->set_gdt(vcpu, &dt);
5844
ad312c7c 5845 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5846 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5847 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5848 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5849
2d3ad1f4 5850 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5851
f6801dff 5852 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5853 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5854 kvm_set_apic_base(vcpu, sregs->apic_base);
5855
4d4ec087 5856 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5857 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5858 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5859
fc78f519 5860 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5861 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5862 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5863 kvm_update_cpuid(vcpu);
63f42e02
XG		 5864
5865 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5866 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5867 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5868 mmu_reset_needed = 1;
5869 }
63f42e02 5870 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5871
5872 if (mmu_reset_needed)
5873 kvm_mmu_reset_context(vcpu);
5874
a50abc3b 5875 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 5876 pending_vec = find_first_bit(
5877 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5878 if (pending_vec < max_bits) {
66fd3f7f 5879 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5880 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5881 }
5882
3e6e0aab
GT		 5883 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5884 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5885 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5886 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5887 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5888 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5889
3e6e0aab
GT		 5890 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5891 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5892
5f0269f5
ME		 5893 update_cr8_intercept(vcpu);
5894
9c3e4aab 5895 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5896 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5897 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5898 !is_protmode(vcpu))
9c3e4aab
MT		 5899 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5900
3842d135
AK		 5901 kvm_make_request(KVM_REQ_EVENT, vcpu);
5902
b6c7a5dc
HB		 5903 return 0;
5904}
5905
d0bfb940
JK		 5906int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5907 struct kvm_guest_debug *dbg)
b6c7a5dc 5908{
355be0b9 5909 unsigned long rflags;
ae675ef0 5910 int i, r;
b6c7a5dc 5911
4f926bf2
JK		 5912 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5913 r = -EBUSY;
5914 if (vcpu->arch.exception.pending)
2122ff5e 5915 goto out;
4f926bf2
JK		 5916 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5917 kvm_queue_exception(vcpu, DB_VECTOR);
5918 else
5919 kvm_queue_exception(vcpu, BP_VECTOR);
5920 }
5921
91586a3b
JK		 5922 /*
5923 * Read rflags as long as potentially injected trace flags are still
5924 * filtered out.
5925 */
5926 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5927
5928 vcpu->guest_debug = dbg->control;
5929 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5930 vcpu->guest_debug = 0;
5931
5932 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5933 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5934 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 5935 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 5936 } else {
5937 for (i = 0; i < KVM_NR_DB_REGS; i++)
5938 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 5939 }
c8639010 5940 kvm_update_dr7(vcpu);
ae675ef0 5941
f92653ee
JK		 5942 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5943 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5944 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5945
91586a3b
JK		 5946 /*
5947 * Trigger an rflags update that will inject or remove the trace
5948 * flags.
5949 */
5950 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5951
c8639010 5952 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 5953
4f926bf2 5954 r = 0;
d0bfb940 5955
2122ff5e 5956out:
b6c7a5dc
HB		 5957
5958 return r;
5959}
5960
8b006791
ZX		 5961/*
5962 * Translate a guest virtual address to a guest physical address.
5963 */
5964int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5965 struct kvm_translation *tr)
5966{
5967 unsigned long vaddr = tr->linear_address;
5968 gpa_t gpa;
f656ce01 5969 int idx;
8b006791 5970
f656ce01 5971 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5972 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5973 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5974 tr->physical_address = gpa;
5975 tr->valid = gpa != UNMAPPED_GVA;
5976 tr->writeable = 1;
5977 tr->usermode = 0;
8b006791
ZX		 5978
5979 return 0;
5980}
5981
d0752060
HB		 5982int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5983{
98918833
SY		 5984 struct i387_fxsave_struct *fxsave =
5985 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5986
d0752060
HB		 5987 memcpy(fpu->fpr, fxsave->st_space, 128);
5988 fpu->fcw = fxsave->cwd;
5989 fpu->fsw = fxsave->swd;
5990 fpu->ftwx = fxsave->twd;
5991 fpu->last_opcode = fxsave->fop;
5992 fpu->last_ip = fxsave->rip;
5993 fpu->last_dp = fxsave->rdp;
5994 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5995
d0752060
HB		 5996 return 0;
5997}
5998
5999int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6000{
98918833
SY		 6001 struct i387_fxsave_struct *fxsave =
6002 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6003
d0752060
HB		 6004 memcpy(fxsave->st_space, fpu->fpr, 128);
6005 fxsave->cwd = fpu->fcw;
6006 fxsave->swd = fpu->fsw;
6007 fxsave->twd = fpu->ftwx;
6008 fxsave->fop = fpu->last_opcode;
6009 fxsave->rip = fpu->last_ip;
6010 fxsave->rdp = fpu->last_dp;
6011 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6012
d0752060
HB		 6013 return 0;
6014}
6015
10ab25cd 6016int fx_init(struct kvm_vcpu *vcpu)
d0752060 6017{
10ab25cd
JK		 6018 int err;
6019
6020 err = fpu_alloc(&vcpu->arch.guest_fpu);
6021 if (err)
6022 return err;
6023
98918833 6024 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6025
2acf923e
DC		 6026 /*
6027 * Ensure guest xcr0 is valid for loading
6028 */
6029 vcpu->arch.xcr0 = XSTATE_FP;
6030
ad312c7c 6031 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6032
6033 return 0;
d0752060
HB		 6034}
6035EXPORT_SYMBOL_GPL(fx_init);
6036
98918833
SY		 6037static void fx_free(struct kvm_vcpu *vcpu)
6038{
6039 fpu_free(&vcpu->arch.guest_fpu);
6040}
6041
d0752060
HB		 6042void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6043{
2608d7a1 6044 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6045 return;
6046
2acf923e
DC		 6047 /*
6048 * Restore all possible states in the guest,
6049 * and assume host would use all available bits.
6050 * Guest xcr0 would be loaded later.
6051 */
6052 kvm_put_guest_xcr0(vcpu);
d0752060 6053 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6054 __kernel_fpu_begin();
98918833 6055 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6056 trace_kvm_fpu(1);
d0752060 6057}
d0752060
HB		 6058
6059void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6060{
2acf923e
DC		 6061 kvm_put_guest_xcr0(vcpu);
6062
d0752060
HB		 6063 if (!vcpu->guest_fpu_loaded)
6064 return;
6065
6066 vcpu->guest_fpu_loaded = 0;
98918833 6067 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6068 __kernel_fpu_end();
f096ed85 6069 ++vcpu->stat.fpu_reload;
a8eeb04a 6070 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6071 trace_kvm_fpu(0);
d0752060 6072}
e9b11c17
ZX		 6073
6074void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6075{
12f9a48f 6076 kvmclock_reset(vcpu);
7f1ea208 6077
f5f48ee1 6078 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6079 fx_free(vcpu);
e9b11c17
ZX		 6080 kvm_x86_ops->vcpu_free(vcpu);
6081}
6082
6083struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6084 unsigned int id)
6085{
6755bae8
ZA		 6086 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6087 printk_once(KERN_WARNING
6088 "kvm: SMP vm created on host with unstable TSC; "
6089 "guest TSC will not be reliable\n");
26e5215f
AK		 6090 return kvm_x86_ops->vcpu_create(kvm, id);
6091}
e9b11c17 6092
26e5215f
AK		 6093int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6094{
6095 int r;
e9b11c17 6096
0bed3b56 6097 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6098 r = vcpu_load(vcpu);
6099 if (r)
6100 return r;
8b6e4547 6101 r = kvm_vcpu_reset(vcpu);
e9b11c17
ZX		 6102 if (r == 0)
6103 r = kvm_mmu_setup(vcpu);
6104 vcpu_put(vcpu);
e9b11c17 6105
26e5215f 6106 return r;
e9b11c17
ZX		 6107}
6108
d40ccc62 6109void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6110{
9fc77441 6111 int r;
344d9588
GN		 6112 vcpu->arch.apf.msr_val = 0;
6113
9fc77441
MT		 6114 r = vcpu_load(vcpu);
6115 BUG_ON(r);
e9b11c17
ZX		 6116 kvm_mmu_unload(vcpu);
6117 vcpu_put(vcpu);
6118
98918833 6119 fx_free(vcpu);
e9b11c17
ZX		 6120 kvm_x86_ops->vcpu_free(vcpu);
6121}
6122
8b6e4547 6123static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6124{
7460fb4a
AK		 6125 atomic_set(&vcpu->arch.nmi_queued, 0);
6126 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6127 vcpu->arch.nmi_injected = false;
6128
42dbaa5a
JK		 6129 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6130 vcpu->arch.dr6 = DR6_FIXED_1;
6131 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6132 kvm_update_dr7(vcpu);
42dbaa5a 6133
3842d135 6134 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6135 vcpu->arch.apf.msr_val = 0;
c9aaa895 6136 vcpu->arch.st.msr_val = 0;
3842d135 6137
12f9a48f
GC		 6138 kvmclock_reset(vcpu);
6139
af585b92
GN		 6140 kvm_clear_async_pf_completion_queue(vcpu);
6141 kvm_async_pf_hash_reset(vcpu);
6142 vcpu->arch.apf.halted = false;
3842d135 6143
f5132b01
GN		 6144 kvm_pmu_reset(vcpu);
6145
e9b11c17
ZX		 6146 return kvm_x86_ops->vcpu_reset(vcpu);
6147}
6148
10474ae8 6149int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6150{
ca84d1a2
ZA		 6151 struct kvm *kvm;
6152 struct kvm_vcpu *vcpu;
6153 int i;
0dd6a6ed
ZA		 6154 int ret;
6155 u64 local_tsc;
6156 u64 max_tsc = 0;
6157 bool stable, backwards_tsc = false;
18863bdd
AK		 6158
6159 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6160 ret = kvm_x86_ops->hardware_enable(garbage);
6161 if (ret != 0)
6162 return ret;
6163
6164 local_tsc = native_read_tsc();
6165 stable = !check_tsc_unstable();
6166 list_for_each_entry(kvm, &vm_list, vm_list) {
6167 kvm_for_each_vcpu(i, vcpu, kvm) {
6168 if (!stable && vcpu->cpu == smp_processor_id())
6169 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6170 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6171 backwards_tsc = true;
6172 if (vcpu->arch.last_host_tsc > max_tsc)
6173 max_tsc = vcpu->arch.last_host_tsc;
6174 }
6175 }
6176 }
6177
6178 /*
6179 * Sometimes, even reliable TSCs go backwards. This happens on
6180 * platforms that reset TSC during suspend or hibernate actions, but
6181 * maintain synchronization. We must compensate. Fortunately, we can
6182 * detect that condition here, which happens early in CPU bringup,
6183 * before any KVM threads can be running. Unfortunately, we can't
6184 * bring the TSCs fully up to date with real time, as we aren't yet far
6185 * enough into CPU bringup that we know how much real time has actually
6186 * elapsed; our helper function, get_kernel_ns() will be using boot
6187 * variables that haven't been updated yet.
6188 *
6189 * So we simply find the maximum observed TSC above, then record the
6190 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6191 * the adjustment will be applied. Note that we accumulate
6192 * adjustments, in case multiple suspend cycles happen before some VCPU
6193 * gets a chance to run again. In the event that no KVM threads get a
6194 * chance to run, we will miss the entire elapsed period, as we'll have
6195 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6196 * loose cycle time. This isn't too big a deal, since the loss will be
6197 * uniform across all VCPUs (not to mention the scenario is extremely
6198 * unlikely). It is possible that a second hibernate recovery happens
6199 * much faster than a first, causing the observed TSC here to be
6200 * smaller; this would require additional padding adjustment, which is
6201 * why we set last_host_tsc to the local tsc observed here.
6202 *
6203 * N.B. - this code below runs only on platforms with reliable TSC,
6204 * as that is the only way backwards_tsc is set above. Also note
6205 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6206 * have the same delta_cyc adjustment applied if backwards_tsc
6207 * is detected. Note further, this adjustment is only done once,
6208 * as we reset last_host_tsc on all VCPUs to stop this from being
6209 * called multiple times (one for each physical CPU bringup).
6210 *
4a969980 6211 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6212 * will be compensated by the logic in vcpu_load, which sets the TSC to
6213 * catchup mode. This will catchup all VCPUs to real time, but cannot
6214 * guarantee that they stay in perfect synchronization.
6215 */
6216 if (backwards_tsc) {
6217 u64 delta_cyc = max_tsc - local_tsc;
6218 list_for_each_entry(kvm, &vm_list, vm_list) {
6219 kvm_for_each_vcpu(i, vcpu, kvm) {
6220 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6221 vcpu->arch.last_host_tsc = local_tsc;
6222 }
6223
6224 /*
6225 * We have to disable TSC offset matching.. if you were
6226 * booting a VM while issuing an S4 host suspend....
6227 * you may have some problem. Solving this issue is
6228 * left as an exercise to the reader.
6229 */
6230 kvm->arch.last_tsc_nsec = 0;
6231 kvm->arch.last_tsc_write = 0;
6232 }
6233
6234 }
6235 return 0;
e9b11c17
ZX		 6236}
6237
6238void kvm_arch_hardware_disable(void *garbage)
6239{
6240 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6241 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6242}
6243
6244int kvm_arch_hardware_setup(void)
6245{
6246 return kvm_x86_ops->hardware_setup();
6247}
6248
6249void kvm_arch_hardware_unsetup(void)
6250{
6251 kvm_x86_ops->hardware_unsetup();
6252}
6253
6254void kvm_arch_check_processor_compat(void *rtn)
6255{
6256 kvm_x86_ops->check_processor_compatibility(rtn);
6257}
6258
3e515705
AK		 6259bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6260{
6261 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6262}
6263
54e9818f
GN		 6264struct static_key kvm_no_apic_vcpu __read_mostly;
6265
e9b11c17
ZX		 6266int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6267{
6268 struct page *page;
6269 struct kvm *kvm;
6270 int r;
6271
6272 BUG_ON(vcpu->kvm == NULL);
6273 kvm = vcpu->kvm;
6274
9aabc88f 6275 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6276 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6277 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6278 else
a4535290 6279 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6280
6281 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6282 if (!page) {
6283 r = -ENOMEM;
6284 goto fail;
6285 }
ad312c7c 6286 vcpu->arch.pio_data = page_address(page);
e9b11c17 6287
cc578287 6288 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6289
e9b11c17
ZX		 6290 r = kvm_mmu_create(vcpu);
6291 if (r < 0)
6292 goto fail_free_pio_data;
6293
6294 if (irqchip_in_kernel(kvm)) {
6295 r = kvm_create_lapic(vcpu);
6296 if (r < 0)
6297 goto fail_mmu_destroy;
54e9818f
GN		 6298 } else
6299 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6300
890ca9ae
HY		 6301 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6302 GFP_KERNEL);
6303 if (!vcpu->arch.mce_banks) {
6304 r = -ENOMEM;
443c39bc 6305 goto fail_free_lapic;
890ca9ae
HY		 6306 }
6307 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6308
f5f48ee1
SY		 6309 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6310 goto fail_free_mce_banks;
6311
af585b92 6312 kvm_async_pf_hash_reset(vcpu);
f5132b01 6313 kvm_pmu_init(vcpu);
af585b92 6314
e9b11c17 6315 return 0;
f5f48ee1
SY		 6316fail_free_mce_banks:
6317 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6318fail_free_lapic:
6319 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6320fail_mmu_destroy:
6321 kvm_mmu_destroy(vcpu);
6322fail_free_pio_data:
ad312c7c 6323 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6324fail:
6325 return r;
6326}
6327
6328void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6329{
f656ce01
MT		 6330 int idx;
6331
f5132b01 6332 kvm_pmu_destroy(vcpu);
36cb93fd 6333 kfree(vcpu->arch.mce_banks);
e9b11c17 6334 kvm_free_lapic(vcpu);
f656ce01 6335 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6336 kvm_mmu_destroy(vcpu);
f656ce01 6337 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6338 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6339 if (!irqchip_in_kernel(vcpu->kvm))
6340 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6341}
d19a9cd2 6342
e08b9637 6343int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6344{
e08b9637
CO		 6345 if (type)
6346 return -EINVAL;
6347
f05e70ac 6348 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6349 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6350
5550af4d
SY		 6351 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6352 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6353 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6354 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6355 &kvm->arch.irq_sources_bitmap);
5550af4d 6356
038f8c11 6357 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6358 mutex_init(&kvm->arch.apic_map_lock);
53f658b3 6359
d89f5eff 6360 return 0;
d19a9cd2
ZX		 6361}
6362
6363static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6364{
9fc77441
MT		 6365 int r;
6366 r = vcpu_load(vcpu);
6367 BUG_ON(r);
d19a9cd2
ZX		 6368 kvm_mmu_unload(vcpu);
6369 vcpu_put(vcpu);
6370}
6371
6372static void kvm_free_vcpus(struct kvm *kvm)
6373{
6374 unsigned int i;
988a2cae 6375 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6376
6377 /*
6378 * Unpin any mmu pages first.
6379 */
af585b92
GN		 6380 kvm_for_each_vcpu(i, vcpu, kvm) {
6381 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6382 kvm_unload_vcpu_mmu(vcpu);
af585b92 6383 }
988a2cae
GN		 6384 kvm_for_each_vcpu(i, vcpu, kvm)
6385 kvm_arch_vcpu_free(vcpu);
6386
6387 mutex_lock(&kvm->lock);
6388 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6389 kvm->vcpus[i] = NULL;
d19a9cd2 6390
988a2cae
GN		 6391 atomic_set(&kvm->online_vcpus, 0);
6392 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6393}
6394
ad8ba2cd
SY		 6395void kvm_arch_sync_events(struct kvm *kvm)
6396{
ba4cef31 6397 kvm_free_all_assigned_devices(kvm);
aea924f6 6398 kvm_free_pit(kvm);
ad8ba2cd
SY		 6399}
6400
d19a9cd2
ZX		 6401void kvm_arch_destroy_vm(struct kvm *kvm)
6402{
6eb55818 6403 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6404 kfree(kvm->arch.vpic);
6405 kfree(kvm->arch.vioapic);
d19a9cd2 6406 kvm_free_vcpus(kvm);
3d45830c
AK		 6407 if (kvm->arch.apic_access_page)
6408 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6409 if (kvm->arch.ept_identity_pagetable)
6410 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6411 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6412}
0de10343 6413
db3fe4eb
TY		 6414void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6415 struct kvm_memory_slot *dont)
6416{
6417 int i;
6418
d89cc617
TY		 6419 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6420 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6421 kvm_kvfree(free->arch.rmap[i]);
6422 free->arch.rmap[i] = NULL;
77d11309 6423 }
d89cc617
TY		 6424 if (i == 0)
6425 continue;
6426
6427 if (!dont || free->arch.lpage_info[i - 1] !=
6428 dont->arch.lpage_info[i - 1]) {
6429 kvm_kvfree(free->arch.lpage_info[i - 1]);
6430 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6431 }
6432 }
6433}
6434
6435int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6436{
6437 int i;
6438
d89cc617 6439 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6440 unsigned long ugfn;
6441 int lpages;
d89cc617 6442 int level = i + 1;
db3fe4eb
TY		 6443
6444 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6445 slot->base_gfn, level) + 1;
6446
d89cc617
TY		 6447 slot->arch.rmap[i] =
6448 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6449 if (!slot->arch.rmap[i])
77d11309 6450 goto out_free;
d89cc617
TY		 6451 if (i == 0)
6452 continue;
77d11309 6453
d89cc617
TY		 6454 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6455 sizeof(*slot->arch.lpage_info[i - 1]));
6456 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6457 goto out_free;
6458
6459 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6460 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6461 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6462 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6463 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6464 /*
6465 * If the gfn and userspace address are not aligned wrt each
6466 * other, or if explicitly asked to, disable large page
6467 * support for this slot
6468 */
6469 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6470 !kvm_largepages_enabled()) {
6471 unsigned long j;
6472
6473 for (j = 0; j < lpages; ++j)
d89cc617 6474 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6475 }
6476 }
6477
6478 return 0;
6479
6480out_free:
d89cc617
TY		 6481 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6482 kvm_kvfree(slot->arch.rmap[i]);
6483 slot->arch.rmap[i] = NULL;
6484 if (i == 0)
6485 continue;
6486
6487 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6488 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6489 }
6490 return -ENOMEM;
6491}
6492
f7784b8e
MT		 6493int kvm_arch_prepare_memory_region(struct kvm *kvm,
6494 struct kvm_memory_slot *memslot,
0de10343 6495 struct kvm_memory_slot old,
f7784b8e 6496 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6497 int user_alloc)
6498{
f7784b8e 6499 int npages = memslot->npages;
7ac77099
AK		 6500 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6501
6502 /* Prevent internal slot pages from being moved by fork()/COW. */
6503 if (memslot->id >= KVM_MEMORY_SLOTS)
6504 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6505
6506 /*To keep backward compatibility with older userspace,
4a969980 6507 *x86 needs to handle !user_alloc case.
0de10343
ZX		 6508 */
6509 if (!user_alloc) {
aab2eb7a 6510 if (npages && !old.npages) {
604b38ac
AA		 6511 unsigned long userspace_addr;
6512
6be5ceb0 6513 userspace_addr = vm_mmap(NULL, 0,
604b38ac
AA		 6514 npages * PAGE_SIZE,
6515 PROT_READ | PROT_WRITE,
7ac77099 6516 map_flags,
604b38ac 6517 0);
0de10343 6518
604b38ac
AA		 6519 if (IS_ERR((void *)userspace_addr))
6520 return PTR_ERR((void *)userspace_addr);
6521
604b38ac 6522 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6523 }
6524 }
6525
f7784b8e
MT		 6526
6527 return 0;
6528}
6529
6530void kvm_arch_commit_memory_region(struct kvm *kvm,
6531 struct kvm_userspace_memory_region *mem,
6532 struct kvm_memory_slot old,
6533 int user_alloc)
6534{
6535
48c0e4e9 6536 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e 6537
aab2eb7a 6538 if (!user_alloc && !old.user_alloc && old.npages && !npages) {
f7784b8e
MT		 6539 int ret;
6540
bfce281c 6541 ret = vm_munmap(old.userspace_addr,
f7784b8e 6542 old.npages * PAGE_SIZE);
f7784b8e
MT		 6543 if (ret < 0)
6544 printk(KERN_WARNING
6545 "kvm_vm_ioctl_set_memory_region: "
6546 "failed to munmap memory\n");
6547 }
6548
48c0e4e9
XG		 6549 if (!kvm->arch.n_requested_mmu_pages)
6550 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6551
7c8a83b7 6552 spin_lock(&kvm->mmu_lock);
48c0e4e9 6553 if (nr_mmu_pages)
0de10343 6554 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6555 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6556 spin_unlock(&kvm->mmu_lock);
3b4dc3a0
MT		 6557 /*
6558 * If memory slot is created, or moved, we need to clear all
6559 * mmio sptes.
6560 */
6561 if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) {
6562 kvm_mmu_zap_all(kvm);
6563 kvm_reload_remote_mmus(kvm);
6564 }
0de10343 6565}
1d737c8a 6566
2df72e9b 6567void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 6568{
6569 kvm_mmu_zap_all(kvm);
8986ecc0 6570 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6571}
6572
2df72e9b
MT		 6573void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6574 struct kvm_memory_slot *slot)
6575{
6576 kvm_arch_flush_shadow_all(kvm);
6577}
6578
1d737c8a
ZX		 6579int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6580{
af585b92
GN		 6581 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6582 !vcpu->arch.apf.halted)
6583 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6584 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6585 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6586 (kvm_arch_interrupt_allowed(vcpu) &&
6587 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6588}
5736199a 6589
b6d33834 6590int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 6591{
b6d33834 6592 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 6593}
78646121
GN		 6594
6595int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6596{
6597 return kvm_x86_ops->interrupt_allowed(vcpu);
6598}
229456fc 6599
f92653ee
JK		 6600bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6601{
6602 unsigned long current_rip = kvm_rip_read(vcpu) +
6603 get_segment_base(vcpu, VCPU_SREG_CS);
6604
6605 return current_rip == linear_rip;
6606}
6607EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6608
94fe45da
JK		 6609unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6610{
6611 unsigned long rflags;
6612
6613 rflags = kvm_x86_ops->get_rflags(vcpu);
6614 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6615 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6616 return rflags;
6617}
6618EXPORT_SYMBOL_GPL(kvm_get_rflags);
6619
6620void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6621{
6622 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6623 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6624 rflags |= X86_EFLAGS_TF;
94fe45da 6625 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6626 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6627}
6628EXPORT_SYMBOL_GPL(kvm_set_rflags);
6629
56028d08
GN		 6630void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6631{
6632 int r;
6633
fb67e14f 6634 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6635 is_error_page(work->page))
56028d08
GN		 6636 return;
6637
6638 r = kvm_mmu_reload(vcpu);
6639 if (unlikely(r))
6640 return;
6641
fb67e14f
XG		 6642 if (!vcpu->arch.mmu.direct_map &&
6643 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6644 return;
6645
56028d08
GN		 6646 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6647}
6648
af585b92
GN		 6649static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6650{
6651 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6652}
6653
6654static inline u32 kvm_async_pf_next_probe(u32 key)
6655{
6656 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6657}
6658
6659static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6660{
6661 u32 key = kvm_async_pf_hash_fn(gfn);
6662
6663 while (vcpu->arch.apf.gfns[key] != ~0)
6664 key = kvm_async_pf_next_probe(key);
6665
6666 vcpu->arch.apf.gfns[key] = gfn;
6667}
6668
6669static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6670{
6671 int i;
6672 u32 key = kvm_async_pf_hash_fn(gfn);
6673
6674 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6675 (vcpu->arch.apf.gfns[key] != gfn &&
6676 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6677 key = kvm_async_pf_next_probe(key);
6678
6679 return key;
6680}
6681
6682bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6683{
6684 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6685}
6686
6687static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6688{
6689 u32 i, j, k;
6690
6691 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6692 while (true) {
6693 vcpu->arch.apf.gfns[i] = ~0;
6694 do {
6695 j = kvm_async_pf_next_probe(j);
6696 if (vcpu->arch.apf.gfns[j] == ~0)
6697 return;
6698 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6699 /*
6700 * k lies cyclically in ]i,j]
6701 * | i.k.j |
6702 * |....j i.k.| or |.k..j i...|
6703 */
6704 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6705 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6706 i = j;
6707 }
6708}
6709
7c90705b
GN		 6710static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6711{
6712
6713 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6714 sizeof(val));
6715}
6716
af585b92
GN		 6717void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6718 struct kvm_async_pf *work)
6719{
6389ee94
AK		 6720 struct x86_exception fault;
6721
7c90705b 6722 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6723 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6724
6725 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6726 (vcpu->arch.apf.send_user_only &&
6727 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6728 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6729 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6730 fault.vector = PF_VECTOR;
6731 fault.error_code_valid = true;
6732 fault.error_code = 0;
6733 fault.nested_page_fault = false;
6734 fault.address = work->arch.token;
6735 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6736 }
af585b92
GN		 6737}
6738
6739void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6740 struct kvm_async_pf *work)
6741{
6389ee94
AK		 6742 struct x86_exception fault;
6743
7c90705b
GN		 6744 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6745 if (is_error_page(work->page))
6746 work->arch.token = ~0; /* broadcast wakeup */
6747 else
6748 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6749
6750 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6751 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6752 fault.vector = PF_VECTOR;
6753 fault.error_code_valid = true;
6754 fault.error_code = 0;
6755 fault.nested_page_fault = false;
6756 fault.address = work->arch.token;
6757 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6758 }
e6d53e3b 6759 vcpu->arch.apf.halted = false;
a4fa1635 6760 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 6761}
6762
6763bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6764{
6765 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6766 return true;
6767 else
6768 return !kvm_event_needs_reinjection(vcpu) &&
6769 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6770}
6771
229456fc
MT		 6772EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6773EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6774EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6775EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6776EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6777EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6778EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6779EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6780EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6781EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6782EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6783EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 6.x block layer and io_uring tree(s)