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x86/kvm/mmu: introduce guest_mmu
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
3b8a5df6 139unsigned int __read_mostly lapic_timer_advance_ns = 1000;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
c595ceee 198 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 199 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
200 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
201 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
202 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
203 { "mmu_flooded", VM_STAT(mmu_flooded) },
204 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 205 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 206 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 207 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 208 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 209 { "max_mmu_page_hash_collisions",
210 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 211 { NULL }
212};
213
2acf923e
DC		 214u64 __read_mostly host_xcr0;
215
b6785def 216static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 217
af585b92
GN		 218static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
219{
220 int i;
221 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
222 vcpu->arch.apf.gfns[i] = ~0;
223}
224
18863bdd
AK		 225static void kvm_on_user_return(struct user_return_notifier *urn)
226{
227 unsigned slot;
18863bdd
AK		 228 struct kvm_shared_msrs *locals
229 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 230 struct kvm_shared_msr_values *values;
1650b4eb
IA		 231 unsigned long flags;
232
233 /*
234 * Disabling irqs at this point since the following code could be
235 * interrupted and executed through kvm_arch_hardware_disable()
236 */
237 local_irq_save(flags);
238 if (locals->registered) {
239 locals->registered = false;
240 user_return_notifier_unregister(urn);
241 }
242 local_irq_restore(flags);
18863bdd 243 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 244 values = &locals->values[slot];
245 if (values->host != values->curr) {
246 wrmsrl(shared_msrs_global.msrs[slot], values->host);
247 values->curr = values->host;
18863bdd
AK		 248 }
249 }
18863bdd
AK		 250}
251
2bf78fa7 252static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 253{
18863bdd 254 u64 value;
013f6a5d
MT		 255 unsigned int cpu = smp_processor_id();
256 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 257
2bf78fa7
SY		 258 /* only read, and nobody should modify it at this time,
259 * so don't need lock */
260 if (slot >= shared_msrs_global.nr) {
261 printk(KERN_ERR "kvm: invalid MSR slot!");
262 return;
263 }
264 rdmsrl_safe(msr, &value);
265 smsr->values[slot].host = value;
266 smsr->values[slot].curr = value;
267}
268
269void kvm_define_shared_msr(unsigned slot, u32 msr)
270{
0123be42 271 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 272 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 273 if (slot >= shared_msrs_global.nr)
274 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 275}
276EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
277
278static void kvm_shared_msr_cpu_online(void)
279{
280 unsigned i;
18863bdd
AK		 281
282 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 283 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 284}
285
8b3c3104 286int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 287{
013f6a5d
MT		 288 unsigned int cpu = smp_processor_id();
289 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 290 int err;
18863bdd 291
2bf78fa7 292 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 293 return 0;
2bf78fa7 294 smsr->values[slot].curr = value;
8b3c3104
AH		 295 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
296 if (err)
297 return 1;
298
18863bdd
AK		 299 if (!smsr->registered) {
300 smsr->urn.on_user_return = kvm_on_user_return;
301 user_return_notifier_register(&smsr->urn);
302 smsr->registered = true;
303 }
8b3c3104 304 return 0;
18863bdd
AK		 305}
306EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
307
13a34e06 308static void drop_user_return_notifiers(void)
3548bab5 309{
013f6a5d
MT		 310 unsigned int cpu = smp_processor_id();
311 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 312
313 if (smsr->registered)
314 kvm_on_user_return(&smsr->urn);
315}
316
6866b83e
CO		 317u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
318{
8a5a87d9 319 return vcpu->arch.apic_base;
6866b83e
CO		 320}
321EXPORT_SYMBOL_GPL(kvm_get_apic_base);
322
58871649
JM		 323enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
324{
325 return kvm_apic_mode(kvm_get_apic_base(vcpu));
326}
327EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
328
58cb628d
JK		 329int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
330{
58871649
JM		 331 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
332 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 333 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
334 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 335
58871649 336 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 337 return 1;
58871649
JM		 338 if (!msr_info->host_initiated) {
339 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
340 return 1;
341 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
342 return 1;
343 }
58cb628d
JK		 344
345 kvm_lapic_set_base(vcpu, msr_info->data);
346 return 0;
6866b83e
CO		 347}
348EXPORT_SYMBOL_GPL(kvm_set_apic_base);
349
2605fc21 350asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 351{
352 /* Fault while not rebooting. We want the trace. */
353 BUG();
354}
355EXPORT_SYMBOL_GPL(kvm_spurious_fault);
356
3fd28fce
ED		 357#define EXCPT_BENIGN 0
358#define EXCPT_CONTRIBUTORY 1
359#define EXCPT_PF 2
360
361static int exception_class(int vector)
362{
363 switch (vector) {
364 case PF_VECTOR:
365 return EXCPT_PF;
366 case DE_VECTOR:
367 case TS_VECTOR:
368 case NP_VECTOR:
369 case SS_VECTOR:
370 case GP_VECTOR:
371 return EXCPT_CONTRIBUTORY;
372 default:
373 break;
374 }
375 return EXCPT_BENIGN;
376}
377
d6e8c854
NA		 378#define EXCPT_FAULT 0
379#define EXCPT_TRAP 1
380#define EXCPT_ABORT 2
381#define EXCPT_INTERRUPT 3
382
383static int exception_type(int vector)
384{
385 unsigned int mask;
386
387 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
388 return EXCPT_INTERRUPT;
389
390 mask = 1 << vector;
391
392 /* #DB is trap, as instruction watchpoints are handled elsewhere */
393 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
394 return EXCPT_TRAP;
395
396 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
397 return EXCPT_ABORT;
398
399 /* Reserved exceptions will result in fault */
400 return EXCPT_FAULT;
401}
402
3fd28fce 403static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 404 unsigned nr, bool has_error, u32 error_code,
405 bool reinject)
3fd28fce
ED		 406{
407 u32 prev_nr;
408 int class1, class2;
409
3842d135
AK		 410 kvm_make_request(KVM_REQ_EVENT, vcpu);
411
664f8e26 412 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 413 queue:
3ffb2468
NA		 414 if (has_error && !is_protmode(vcpu))
415 has_error = false;
664f8e26
WL		 416 if (reinject) {
417 /*
418 * On vmentry, vcpu->arch.exception.pending is only
419 * true if an event injection was blocked by
420 * nested_run_pending. In that case, however,
421 * vcpu_enter_guest requests an immediate exit,
422 * and the guest shouldn't proceed far enough to
423 * need reinjection.
424 */
425 WARN_ON_ONCE(vcpu->arch.exception.pending);
426 vcpu->arch.exception.injected = true;
427 } else {
428 vcpu->arch.exception.pending = true;
429 vcpu->arch.exception.injected = false;
430 }
3fd28fce
ED		 431 vcpu->arch.exception.has_error_code = has_error;
432 vcpu->arch.exception.nr = nr;
433 vcpu->arch.exception.error_code = error_code;
434 return;
435 }
436
437 /* to check exception */
438 prev_nr = vcpu->arch.exception.nr;
439 if (prev_nr == DF_VECTOR) {
440 /* triple fault -> shutdown */
a8eeb04a 441 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 442 return;
443 }
444 class1 = exception_class(prev_nr);
445 class2 = exception_class(nr);
446 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
447 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 448 /*
449 * Generate double fault per SDM Table 5-5. Set
450 * exception.pending = true so that the double fault
451 * can trigger a nested vmexit.
452 */
3fd28fce 453 vcpu->arch.exception.pending = true;
664f8e26 454 vcpu->arch.exception.injected = false;
3fd28fce
ED		 455 vcpu->arch.exception.has_error_code = true;
456 vcpu->arch.exception.nr = DF_VECTOR;
457 vcpu->arch.exception.error_code = 0;
458 } else
459 /* replace previous exception with a new one in a hope
460 that instruction re-execution will regenerate lost
461 exception */
462 goto queue;
463}
464
298101da
AK		 465void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
466{
ce7ddec4 467 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 468}
469EXPORT_SYMBOL_GPL(kvm_queue_exception);
470
ce7ddec4
JR		 471void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
472{
473 kvm_multiple_exception(vcpu, nr, false, 0, true);
474}
475EXPORT_SYMBOL_GPL(kvm_requeue_exception);
476
6affcbed 477int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 478{
db8fcefa
AP		 479 if (err)
480 kvm_inject_gp(vcpu, 0);
481 else
6affcbed
KH		 482 return kvm_skip_emulated_instruction(vcpu);
483
484 return 1;
db8fcefa
AP		 485}
486EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 487
6389ee94 488void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 489{
490 ++vcpu->stat.pf_guest;
adfe20fb
WL		 491 vcpu->arch.exception.nested_apf =
492 is_guest_mode(vcpu) && fault->async_page_fault;
493 if (vcpu->arch.exception.nested_apf)
494 vcpu->arch.apf.nested_apf_token = fault->address;
495 else
496 vcpu->arch.cr2 = fault->address;
6389ee94 497 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 498}
27d6c865 499EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 500
ef54bcfe 501static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 502{
6389ee94
AK		 503 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
504 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 505 else
44dd3ffa 506 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 507
508 return fault->nested_page_fault;
d4f8cf66
JR		 509}
510
3419ffc8
SY		 511void kvm_inject_nmi(struct kvm_vcpu *vcpu)
512{
7460fb4a
AK		 513 atomic_inc(&vcpu->arch.nmi_queued);
514 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 515}
516EXPORT_SYMBOL_GPL(kvm_inject_nmi);
517
298101da
AK		 518void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
519{
ce7ddec4 520 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 521}
522EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
523
ce7ddec4
JR		 524void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
525{
526 kvm_multiple_exception(vcpu, nr, true, error_code, true);
527}
528EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
529
0a79b009
AK		 530/*
531 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
532 * a #GP and return false.
533 */
534bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 535{
0a79b009
AK		 536 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
537 return true;
538 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
539 return false;
298101da 540}
0a79b009 541EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 542
16f8a6f9
NA		 543bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
544{
545 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
546 return true;
547
548 kvm_queue_exception(vcpu, UD_VECTOR);
549 return false;
550}
551EXPORT_SYMBOL_GPL(kvm_require_dr);
552
ec92fe44
JR		 553/*
554 * This function will be used to read from the physical memory of the currently
54bf36aa 555 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 556 * can read from guest physical or from the guest's guest physical memory.
557 */
558int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
559 gfn_t ngfn, void *data, int offset, int len,
560 u32 access)
561{
54987b7a 562 struct x86_exception exception;
ec92fe44
JR		 563 gfn_t real_gfn;
564 gpa_t ngpa;
565
566 ngpa = gfn_to_gpa(ngfn);
54987b7a 567 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 568 if (real_gfn == UNMAPPED_GVA)
569 return -EFAULT;
570
571 real_gfn = gpa_to_gfn(real_gfn);
572
54bf36aa 573 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 574}
575EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
576
69b0049a 577static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 578 void *data, int offset, int len, u32 access)
579{
580 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
581 data, offset, len, access);
582}
583
a03490ed
CO		 584/*
585 * Load the pae pdptrs. Return true is they are all valid.
586 */
ff03a073 587int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 588{
589 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
590 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
591 int i;
592 int ret;
ff03a073 593 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 594
ff03a073
JR		 595 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
596 offset * sizeof(u64), sizeof(pdpte),
597 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 598 if (ret < 0) {
599 ret = 0;
600 goto out;
601 }
602 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 603 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 604 (pdpte[i] &
44dd3ffa 605 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 606 ret = 0;
607 goto out;
608 }
609 }
610 ret = 1;
611
ff03a073 612 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 613 __set_bit(VCPU_EXREG_PDPTR,
614 (unsigned long *)&vcpu->arch.regs_avail);
615 __set_bit(VCPU_EXREG_PDPTR,
616 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 617out:
a03490ed
CO		 618
619 return ret;
620}
cc4b6871 621EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 622
9ed38ffa 623bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 624{
ff03a073 625 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 626 bool changed = true;
3d06b8bf
JR		 627 int offset;
628 gfn_t gfn;
d835dfec
AK		 629 int r;
630
d35b34a9 631 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
d835dfec
AK		 632 return false;
633
6de4f3ad
AK		 634 if (!test_bit(VCPU_EXREG_PDPTR,
635 (unsigned long *)&vcpu->arch.regs_avail))
636 return true;
637
a512177e
PB		 638 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
639 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 640 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
641 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 642 if (r < 0)
643 goto out;
ff03a073 644 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 645out:
d835dfec
AK		 646
647 return changed;
648}
9ed38ffa 649EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 650
49a9b07e 651int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 652{
aad82703 653 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 654 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 655
f9a48e6a
AK		 656 cr0 |= X86_CR0_ET;
657
ab344828 658#ifdef CONFIG_X86_64
0f12244f
GN		 659 if (cr0 & 0xffffffff00000000UL)
660 return 1;
ab344828
GN		 661#endif
662
663 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 664
0f12244f
GN		 665 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
666 return 1;
a03490ed 667
0f12244f
GN		 668 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
669 return 1;
a03490ed
CO		 670
671 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
672#ifdef CONFIG_X86_64
f6801dff 673 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 674 int cs_db, cs_l;
675
0f12244f
GN		 676 if (!is_pae(vcpu))
677 return 1;
a03490ed 678 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 679 if (cs_l)
680 return 1;
a03490ed
CO		 681 } else
682#endif
ff03a073 683 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 684 kvm_read_cr3(vcpu)))
0f12244f 685 return 1;
a03490ed
CO		 686 }
687
ad756a16
MJ		 688 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
689 return 1;
690
a03490ed 691 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 692
d170c419 693 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 694 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 695 kvm_async_pf_hash_reset(vcpu);
696 }
e5f3f027 697
aad82703
SY		 698 if ((cr0 ^ old_cr0) & update_bits)
699 kvm_mmu_reset_context(vcpu);
b18d5431 700
879ae188
LE		 701 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
702 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
703 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 704 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
705
0f12244f
GN		 706 return 0;
707}
2d3ad1f4 708EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 709
2d3ad1f4 710void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 711{
49a9b07e 712 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 713}
2d3ad1f4 714EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 715
42bdf991
MT		 716static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
717{
718 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
719 !vcpu->guest_xcr0_loaded) {
720 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 721 if (vcpu->arch.xcr0 != host_xcr0)
722 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 723 vcpu->guest_xcr0_loaded = 1;
724 }
725}
726
727static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
728{
729 if (vcpu->guest_xcr0_loaded) {
730 if (vcpu->arch.xcr0 != host_xcr0)
731 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
732 vcpu->guest_xcr0_loaded = 0;
733 }
734}
735
69b0049a 736static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 737{
56c103ec
LJ		 738 u64 xcr0 = xcr;
739 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 740 u64 valid_bits;
2acf923e
DC		 741
742 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
743 if (index != XCR_XFEATURE_ENABLED_MASK)
744 return 1;
d91cab78 745 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 746 return 1;
d91cab78 747 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 748 return 1;
46c34cb0
PB		 749
750 /*
751 * Do not allow the guest to set bits that we do not support
752 * saving. However, xcr0 bit 0 is always set, even if the
753 * emulated CPU does not support XSAVE (see fx_init).
754 */
d91cab78 755 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 756 if (xcr0 & ~valid_bits)
2acf923e 757 return 1;
46c34cb0 758
d91cab78
DH		 759 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
760 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 761 return 1;
762
d91cab78
DH		 763 if (xcr0 & XFEATURE_MASK_AVX512) {
764 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 765 return 1;
d91cab78 766 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 767 return 1;
768 }
2acf923e 769 vcpu->arch.xcr0 = xcr0;
56c103ec 770
d91cab78 771 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 772 kvm_update_cpuid(vcpu);
2acf923e
DC		 773 return 0;
774}
775
776int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
777{
764bcbc5
Z		 778 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
779 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 780 kvm_inject_gp(vcpu, 0);
781 return 1;
782 }
783 return 0;
784}
785EXPORT_SYMBOL_GPL(kvm_set_xcr);
786
a83b29c6 787int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 788{
fc78f519 789 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 790 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 791 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 792
0f12244f
GN		 793 if (cr4 & CR4_RESERVED_BITS)
794 return 1;
a03490ed 795
d6321d49 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 797 return 1;
798
d6321d49 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 800 return 1;
801
d6321d49 802 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 803 return 1;
804
d6321d49 805 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 806 return 1;
807
d6321d49 808 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 809 return 1;
810
fd8cb433 811 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 812 return 1;
813
ae3e61e1
PB		 814 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
815 return 1;
816
a03490ed 817 if (is_long_mode(vcpu)) {
0f12244f
GN		 818 if (!(cr4 & X86_CR4_PAE))
819 return 1;
a2edf57f
AK		 820 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
821 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 822 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
823 kvm_read_cr3(vcpu)))
0f12244f
GN		 824 return 1;
825
ad756a16 826 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 827 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 828 return 1;
829
830 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
831 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
832 return 1;
833 }
834
5e1746d6 835 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 836 return 1;
a03490ed 837
ad756a16
MJ		 838 if (((cr4 ^ old_cr4) & pdptr_bits) ||
839 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 840 kvm_mmu_reset_context(vcpu);
0f12244f 841
b9baba86 842 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 843 kvm_update_cpuid(vcpu);
2acf923e 844
0f12244f
GN		 845 return 0;
846}
2d3ad1f4 847EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 848
2390218b 849int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 850{
ade61e28 851 bool skip_tlb_flush = false;
ac146235 852#ifdef CONFIG_X86_64
c19986fe
JS		 853 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
854
ade61e28 855 if (pcid_enabled) {
208320ba
JS		 856 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
857 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 858 }
ac146235 859#endif
9d88fca7 860
9f8fe504 861 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 862 if (!skip_tlb_flush) {
863 kvm_mmu_sync_roots(vcpu);
ade61e28 864 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 865 }
0f12244f 866 return 0;
d835dfec
AK		 867 }
868
d1cd3ce9 869 if (is_long_mode(vcpu) &&
a780a3ea 870 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 871 return 1;
872 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 873 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 874 return 1;
a03490ed 875
ade61e28 876 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 877 vcpu->arch.cr3 = cr3;
aff48baa 878 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 879
0f12244f
GN		 880 return 0;
881}
2d3ad1f4 882EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 883
eea1cff9 884int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 885{
0f12244f
GN		 886 if (cr8 & CR8_RESERVED_BITS)
887 return 1;
35754c98 888 if (lapic_in_kernel(vcpu))
a03490ed
CO		 889 kvm_lapic_set_tpr(vcpu, cr8);
890 else
ad312c7c 891 vcpu->arch.cr8 = cr8;
0f12244f
GN		 892 return 0;
893}
2d3ad1f4 894EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 895
2d3ad1f4 896unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 897{
35754c98 898 if (lapic_in_kernel(vcpu))
a03490ed
CO		 899 return kvm_lapic_get_cr8(vcpu);
900 else
ad312c7c 901 return vcpu->arch.cr8;
a03490ed 902}
2d3ad1f4 903EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 904
ae561ede
NA		 905static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
906{
907 int i;
908
909 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
910 for (i = 0; i < KVM_NR_DB_REGS; i++)
911 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
912 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
913 }
914}
915
73aaf249
JK		 916static void kvm_update_dr6(struct kvm_vcpu *vcpu)
917{
918 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
919 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
920}
921
c8639010
JK		 922static void kvm_update_dr7(struct kvm_vcpu *vcpu)
923{
924 unsigned long dr7;
925
926 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
927 dr7 = vcpu->arch.guest_debug_dr7;
928 else
929 dr7 = vcpu->arch.dr7;
930 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 931 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
932 if (dr7 & DR7_BP_EN_MASK)
933 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 934}
935
6f43ed01
NA		 936static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
937{
938 u64 fixed = DR6_FIXED_1;
939
d6321d49 940 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 941 fixed |= DR6_RTM;
942 return fixed;
943}
944
338dbc97 945static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 946{
947 switch (dr) {
948 case 0 ... 3:
949 vcpu->arch.db[dr] = val;
950 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
951 vcpu->arch.eff_db[dr] = val;
952 break;
953 case 4:
020df079
GN		 954 /* fall through */
955 case 6:
338dbc97
GN		 956 if (val & 0xffffffff00000000ULL)
957 return -1; /* #GP */
6f43ed01 958 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 959 kvm_update_dr6(vcpu);
020df079
GN		 960 break;
961 case 5:
020df079
GN		 962 /* fall through */
963 default: /* 7 */
338dbc97
GN		 964 if (val & 0xffffffff00000000ULL)
965 return -1; /* #GP */
020df079 966 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 967 kvm_update_dr7(vcpu);
020df079
GN		 968 break;
969 }
970
971 return 0;
972}
338dbc97
GN		 973
974int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
975{
16f8a6f9 976 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 977 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 978 return 1;
979 }
980 return 0;
338dbc97 981}
020df079
GN		 982EXPORT_SYMBOL_GPL(kvm_set_dr);
983
16f8a6f9 984int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 985{
986 switch (dr) {
987 case 0 ... 3:
988 *val = vcpu->arch.db[dr];
989 break;
990 case 4:
020df079
GN		 991 /* fall through */
992 case 6:
73aaf249
JK		 993 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
994 *val = vcpu->arch.dr6;
995 else
996 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 997 break;
998 case 5:
020df079
GN		 999 /* fall through */
1000 default: /* 7 */
1001 *val = vcpu->arch.dr7;
1002 break;
1003 }
338dbc97
GN		 1004 return 0;
1005}
020df079
GN		 1006EXPORT_SYMBOL_GPL(kvm_get_dr);
1007
022cd0e8
AK		 1008bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1009{
1010 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1011 u64 data;
1012 int err;
1013
c6702c9d 1014 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1015 if (err)
1016 return err;
1017 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1018 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1019 return err;
1020}
1021EXPORT_SYMBOL_GPL(kvm_rdpmc);
1022
043405e1
CO		 1023/*
1024 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1025 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1026 *
1027 * This list is modified at module load time to reflect the
e3267cbb 1028 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1029 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1030 * may depend on host virtualization features rather than host cpu features.
043405e1 1031 */
e3267cbb 1032
043405e1
CO		 1033static u32 msrs_to_save[] = {
1034 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1035 MSR_STAR,
043405e1
CO		 1036#ifdef CONFIG_X86_64
1037 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1038#endif
b3897a49 1039 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1040 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1041 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1042};
1043
1044static unsigned num_msrs_to_save;
1045
62ef68bb
PB		 1046static u32 emulated_msrs[] = {
1047 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1048 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1049 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1050 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1051 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1052 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1053 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1054 HV_X64_MSR_RESET,
11c4b1ca 1055 HV_X64_MSR_VP_INDEX,
9eec50b8 1056 HV_X64_MSR_VP_RUNTIME,
5c919412 1057 HV_X64_MSR_SCONTROL,
1f4b34f8 1058 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1059 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1060 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1061 HV_X64_MSR_TSC_EMULATION_STATUS,
1062
1063 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1064 MSR_KVM_PV_EOI_EN,
1065
ba904635 1066 MSR_IA32_TSC_ADJUST,
a3e06bbe 1067 MSR_IA32_TSCDEADLINE,
043405e1 1068 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1069 MSR_IA32_MCG_STATUS,
1070 MSR_IA32_MCG_CTL,
c45dcc71 1071 MSR_IA32_MCG_EXT_CTL,
64d60670 1072 MSR_IA32_SMBASE,
52797bf9 1073 MSR_SMI_COUNT,
db2336a8
KH		 1074 MSR_PLATFORM_INFO,
1075 MSR_MISC_FEATURES_ENABLES,
bc226f07 1076 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1077};
1078
62ef68bb
PB		 1079static unsigned num_emulated_msrs;
1080
801e459a
TL		 1081/*
1082 * List of msr numbers which are used to expose MSR-based features that
1083 * can be used by a hypervisor to validate requested CPU features.
1084 */
1085static u32 msr_based_features[] = {
1389309c
PB		 1086 MSR_IA32_VMX_BASIC,
1087 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1088 MSR_IA32_VMX_PINBASED_CTLS,
1089 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1090 MSR_IA32_VMX_PROCBASED_CTLS,
1091 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1092 MSR_IA32_VMX_EXIT_CTLS,
1093 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1094 MSR_IA32_VMX_ENTRY_CTLS,
1095 MSR_IA32_VMX_MISC,
1096 MSR_IA32_VMX_CR0_FIXED0,
1097 MSR_IA32_VMX_CR0_FIXED1,
1098 MSR_IA32_VMX_CR4_FIXED0,
1099 MSR_IA32_VMX_CR4_FIXED1,
1100 MSR_IA32_VMX_VMCS_ENUM,
1101 MSR_IA32_VMX_PROCBASED_CTLS2,
1102 MSR_IA32_VMX_EPT_VPID_CAP,
1103 MSR_IA32_VMX_VMFUNC,
1104
d1d93fa9 1105 MSR_F10H_DECFG,
518e7b94 1106 MSR_IA32_UCODE_REV,
cd283252 1107 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1108};
1109
1110static unsigned int num_msr_based_features;
1111
5b76a3cf
PB		 1112u64 kvm_get_arch_capabilities(void)
1113{
1114 u64 data;
1115
1116 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1117
1118 /*
1119 * If we're doing cache flushes (either "always" or "cond")
1120 * we will do one whenever the guest does a vmlaunch/vmresume.
1121 * If an outer hypervisor is doing the cache flush for us
1122 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1123 * capability to the guest too, and if EPT is disabled we're not
1124 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1125 * require a nested hypervisor to do a flush of its own.
1126 */
1127 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1128 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1129
1130 return data;
1131}
1132EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1133
66421c1e
WL		 1134static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1135{
1136 switch (msr->index) {
cd283252 1137 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1138 msr->data = kvm_get_arch_capabilities();
1139 break;
1140 case MSR_IA32_UCODE_REV:
cd283252 1141 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1142 break;
66421c1e
WL		 1143 default:
1144 if (kvm_x86_ops->get_msr_feature(msr))
1145 return 1;
1146 }
1147 return 0;
1148}
1149
801e459a
TL		 1150static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1151{
1152 struct kvm_msr_entry msr;
66421c1e 1153 int r;
801e459a
TL		 1154
1155 msr.index = index;
66421c1e
WL		 1156 r = kvm_get_msr_feature(&msr);
1157 if (r)
1158 return r;
801e459a
TL		 1159
1160 *data = msr.data;
1161
1162 return 0;
1163}
1164
384bb783 1165bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1166{
b69e8cae 1167 if (efer & efer_reserved_bits)
384bb783 1168 return false;
15c4a640 1169
1b4d56b8 1170 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1171 return false;
1b2fd70c 1172
1b4d56b8 1173 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1174 return false;
d8017474 1175
384bb783
JK		 1176 return true;
1177}
1178EXPORT_SYMBOL_GPL(kvm_valid_efer);
1179
1180static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1181{
1182 u64 old_efer = vcpu->arch.efer;
1183
1184 if (!kvm_valid_efer(vcpu, efer))
1185 return 1;
1186
1187 if (is_paging(vcpu)
1188 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1189 return 1;
1190
15c4a640 1191 efer &= ~EFER_LMA;
f6801dff 1192 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1193
a3d204e2
SY		 1194 kvm_x86_ops->set_efer(vcpu, efer);
1195
aad82703
SY		 1196 /* Update reserved bits */
1197 if ((efer ^ old_efer) & EFER_NX)
1198 kvm_mmu_reset_context(vcpu);
1199
b69e8cae 1200 return 0;
15c4a640
CO		 1201}
1202
f2b4b7dd
JR		 1203void kvm_enable_efer_bits(u64 mask)
1204{
1205 efer_reserved_bits &= ~mask;
1206}
1207EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1208
15c4a640
CO		 1209/*
1210 * Writes msr value into into the appropriate "register".
1211 * Returns 0 on success, non-0 otherwise.
1212 * Assumes vcpu_load() was already called.
1213 */
8fe8ab46 1214int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1215{
854e8bb1
NA		 1216 switch (msr->index) {
1217 case MSR_FS_BASE:
1218 case MSR_GS_BASE:
1219 case MSR_KERNEL_GS_BASE:
1220 case MSR_CSTAR:
1221 case MSR_LSTAR:
fd8cb433 1222 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1223 return 1;
1224 break;
1225 case MSR_IA32_SYSENTER_EIP:
1226 case MSR_IA32_SYSENTER_ESP:
1227 /*
1228 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1229 * non-canonical address is written on Intel but not on
1230 * AMD (which ignores the top 32-bits, because it does
1231 * not implement 64-bit SYSENTER).
1232 *
1233 * 64-bit code should hence be able to write a non-canonical
1234 * value on AMD. Making the address canonical ensures that
1235 * vmentry does not fail on Intel after writing a non-canonical
1236 * value, and that something deterministic happens if the guest
1237 * invokes 64-bit SYSENTER.
1238 */
fd8cb433 1239 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1240 }
8fe8ab46 1241 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1242}
854e8bb1 1243EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1244
313a3dc7
CO		 1245/*
1246 * Adapt set_msr() to msr_io()'s calling convention
1247 */
609e36d3
PB		 1248static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1249{
1250 struct msr_data msr;
1251 int r;
1252
1253 msr.index = index;
1254 msr.host_initiated = true;
1255 r = kvm_get_msr(vcpu, &msr);
1256 if (r)
1257 return r;
1258
1259 *data = msr.data;
1260 return 0;
1261}
1262
313a3dc7
CO		 1263static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1264{
8fe8ab46
WA		 1265 struct msr_data msr;
1266
1267 msr.data = *data;
1268 msr.index = index;
1269 msr.host_initiated = true;
1270 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1271}
1272
16e8d74d
MT		 1273#ifdef CONFIG_X86_64
1274struct pvclock_gtod_data {
1275 seqcount_t seq;
1276
1277 struct { /* extract of a clocksource struct */
1278 int vclock_mode;
a5a1d1c2
TG		 1279 u64 cycle_last;
1280 u64 mask;
16e8d74d
MT		 1281 u32 mult;
1282 u32 shift;
1283 } clock;
1284
cbcf2dd3
TG		 1285 u64 boot_ns;
1286 u64 nsec_base;
55dd00a7 1287 u64 wall_time_sec;
16e8d74d
MT		 1288};
1289
1290static struct pvclock_gtod_data pvclock_gtod_data;
1291
1292static void update_pvclock_gtod(struct timekeeper *tk)
1293{
1294 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1295 u64 boot_ns;
1296
876e7881 1297 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1298
1299 write_seqcount_begin(&vdata->seq);
1300
1301 /* copy pvclock gtod data */
876e7881
PZ		 1302 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1303 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1304 vdata->clock.mask = tk->tkr_mono.mask;
1305 vdata->clock.mult = tk->tkr_mono.mult;
1306 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1307
cbcf2dd3 1308 vdata->boot_ns = boot_ns;
876e7881 1309 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1310
55dd00a7
MT		 1311 vdata->wall_time_sec = tk->xtime_sec;
1312
16e8d74d
MT		 1313 write_seqcount_end(&vdata->seq);
1314}
1315#endif
1316
bab5bb39
NK		 1317void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1318{
1319 /*
1320 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1321 * vcpu_enter_guest. This function is only called from
1322 * the physical CPU that is running vcpu.
1323 */
1324 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1325}
16e8d74d 1326
18068523
GOC		 1327static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1328{
9ed3c444
AK		 1329 int version;
1330 int r;
50d0a0f9 1331 struct pvclock_wall_clock wc;
87aeb54f 1332 struct timespec64 boot;
18068523
GOC		 1333
1334 if (!wall_clock)
1335 return;
1336
9ed3c444
AK		 1337 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1338 if (r)
1339 return;
1340
1341 if (version & 1)
1342 ++version; /* first time write, random junk */
1343
1344 ++version;
18068523 1345
1dab1345
NK		 1346 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1347 return;
18068523 1348
50d0a0f9
GH		 1349 /*
1350 * The guest calculates current wall clock time by adding
34c238a1 1351 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1352 * wall clock specified here. guest system time equals host
1353 * system time for us, thus we must fill in host boot time here.
1354 */
87aeb54f 1355 getboottime64(&boot);
50d0a0f9 1356
4b648665 1357 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1358 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1359 boot = timespec64_sub(boot, ts);
4b648665 1360 }
87aeb54f 1361 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1362 wc.nsec = boot.tv_nsec;
1363 wc.version = version;
18068523
GOC		 1364
1365 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1366
1367 version++;
1368 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1369}
1370
50d0a0f9
GH		 1371static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1372{
b51012de
PB		 1373 do_shl32_div32(dividend, divisor);
1374 return dividend;
50d0a0f9
GH		 1375}
1376
3ae13faa 1377static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1378 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1379{
5f4e3f88 1380 uint64_t scaled64;
50d0a0f9
GH		 1381 int32_t shift = 0;
1382 uint64_t tps64;
1383 uint32_t tps32;
1384
3ae13faa
PB		 1385 tps64 = base_hz;
1386 scaled64 = scaled_hz;
50933623 1387 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1388 tps64 >>= 1;
1389 shift--;
1390 }
1391
1392 tps32 = (uint32_t)tps64;
50933623
JK		 1393 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1394 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1395 scaled64 >>= 1;
1396 else
1397 tps32 <<= 1;
50d0a0f9
GH		 1398 shift++;
1399 }
1400
5f4e3f88
ZA		 1401 *pshift = shift;
1402 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1403
3ae13faa
PB		 1404 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1405 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1406}
1407
d828199e 1408#ifdef CONFIG_X86_64
16e8d74d 1409static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1410#endif
16e8d74d 1411
c8076604 1412static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1413static unsigned long max_tsc_khz;
c8076604 1414
cc578287 1415static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1416{
cc578287
ZA		 1417 u64 v = (u64)khz * (1000000 + ppm);
1418 do_div(v, 1000000);
1419 return v;
1e993611
JR		 1420}
1421
381d585c
HZ		 1422static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1423{
1424 u64 ratio;
1425
1426 /* Guest TSC same frequency as host TSC? */
1427 if (!scale) {
1428 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1429 return 0;
1430 }
1431
1432 /* TSC scaling supported? */
1433 if (!kvm_has_tsc_control) {
1434 if (user_tsc_khz > tsc_khz) {
1435 vcpu->arch.tsc_catchup = 1;
1436 vcpu->arch.tsc_always_catchup = 1;
1437 return 0;
1438 } else {
1439 WARN(1, "user requested TSC rate below hardware speed\n");
1440 return -1;
1441 }
1442 }
1443
1444 /* TSC scaling required - calculate ratio */
1445 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1446 user_tsc_khz, tsc_khz);
1447
1448 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1449 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1450 user_tsc_khz);
1451 return -1;
1452 }
1453
1454 vcpu->arch.tsc_scaling_ratio = ratio;
1455 return 0;
1456}
1457
4941b8cb 1458static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1459{
cc578287
ZA		 1460 u32 thresh_lo, thresh_hi;
1461 int use_scaling = 0;
217fc9cf 1462
03ba32ca 1463 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1464 if (user_tsc_khz == 0) {
ad721883
HZ		 1465 /* set tsc_scaling_ratio to a safe value */
1466 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1467 return -1;
ad721883 1468 }
03ba32ca 1469
c285545f 1470 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1471 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1472 &vcpu->arch.virtual_tsc_shift,
1473 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1474 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1475
1476 /*
1477 * Compute the variation in TSC rate which is acceptable
1478 * within the range of tolerance and decide if the
1479 * rate being applied is within that bounds of the hardware
1480 * rate. If so, no scaling or compensation need be done.
1481 */
1482 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1483 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1484 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1485 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1486 use_scaling = 1;
1487 }
4941b8cb 1488 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1489}
1490
1491static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1492{
e26101b1 1493 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1494 vcpu->arch.virtual_tsc_mult,
1495 vcpu->arch.virtual_tsc_shift);
e26101b1 1496 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1497 return tsc;
1498}
1499
b0c39dc6
VK		 1500static inline int gtod_is_based_on_tsc(int mode)
1501{
1502 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1503}
1504
69b0049a 1505static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1506{
1507#ifdef CONFIG_X86_64
1508 bool vcpus_matched;
b48aa97e
MT		 1509 struct kvm_arch *ka = &vcpu->kvm->arch;
1510 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1511
1512 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1513 atomic_read(&vcpu->kvm->online_vcpus));
1514
7f187922
MT		 1515 /*
1516 * Once the masterclock is enabled, always perform request in
1517 * order to update it.
1518 *
1519 * In order to enable masterclock, the host clocksource must be TSC
1520 * and the vcpus need to have matched TSCs. When that happens,
1521 * perform request to enable masterclock.
1522 */
1523 if (ka->use_master_clock ||
b0c39dc6 1524 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1525 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1526
1527 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1528 atomic_read(&vcpu->kvm->online_vcpus),
1529 ka->use_master_clock, gtod->clock.vclock_mode);
1530#endif
1531}
1532
ba904635
WA		 1533static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1534{
e79f245d 1535 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1536 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1537}
1538
35181e86
HZ		 1539/*
1540 * Multiply tsc by a fixed point number represented by ratio.
1541 *
1542 * The most significant 64-N bits (mult) of ratio represent the
1543 * integral part of the fixed point number; the remaining N bits
1544 * (frac) represent the fractional part, ie. ratio represents a fixed
1545 * point number (mult + frac * 2^(-N)).
1546 *
1547 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1548 */
1549static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1550{
1551 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1552}
1553
1554u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1555{
1556 u64 _tsc = tsc;
1557 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1558
1559 if (ratio != kvm_default_tsc_scaling_ratio)
1560 _tsc = __scale_tsc(ratio, tsc);
1561
1562 return _tsc;
1563}
1564EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1565
07c1419a
HZ		 1566static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1567{
1568 u64 tsc;
1569
1570 tsc = kvm_scale_tsc(vcpu, rdtsc());
1571
1572 return target_tsc - tsc;
1573}
1574
4ba76538
HZ		 1575u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1576{
e79f245d
KA		 1577 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1578
1579 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1580}
1581EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1582
a545ab6a
LC		 1583static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1584{
1585 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1586 vcpu->arch.tsc_offset = offset;
1587}
1588
b0c39dc6
VK		 1589static inline bool kvm_check_tsc_unstable(void)
1590{
1591#ifdef CONFIG_X86_64
1592 /*
1593 * TSC is marked unstable when we're running on Hyper-V,
1594 * 'TSC page' clocksource is good.
1595 */
1596 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1597 return false;
1598#endif
1599 return check_tsc_unstable();
1600}
1601
8fe8ab46 1602void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1603{
1604 struct kvm *kvm = vcpu->kvm;
f38e098f 1605 u64 offset, ns, elapsed;
99e3e30a 1606 unsigned long flags;
b48aa97e 1607 bool matched;
0d3da0d2 1608 bool already_matched;
8fe8ab46 1609 u64 data = msr->data;
c5e8ec8e 1610 bool synchronizing = false;
99e3e30a 1611
038f8c11 1612 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1613 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1614 ns = ktime_get_boot_ns();
f38e098f 1615 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1616
03ba32ca 1617 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1618 if (data == 0 && msr->host_initiated) {
1619 /*
1620 * detection of vcpu initialization -- need to sync
1621 * with other vCPUs. This particularly helps to keep
1622 * kvm_clock stable after CPU hotplug
1623 */
1624 synchronizing = true;
1625 } else {
1626 u64 tsc_exp = kvm->arch.last_tsc_write +
1627 nsec_to_cycles(vcpu, elapsed);
1628 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1629 /*
1630 * Special case: TSC write with a small delta (1 second)
1631 * of virtual cycle time against real time is
1632 * interpreted as an attempt to synchronize the CPU.
1633 */
1634 synchronizing = data < tsc_exp + tsc_hz &&
1635 data + tsc_hz > tsc_exp;
1636 }
c5e8ec8e 1637 }
f38e098f
ZA		 1638
1639 /*
5d3cb0f6
ZA		 1640 * For a reliable TSC, we can match TSC offsets, and for an unstable
1641 * TSC, we add elapsed time in this computation. We could let the
1642 * compensation code attempt to catch up if we fall behind, but
1643 * it's better to try to match offsets from the beginning.
1644 */
c5e8ec8e 1645 if (synchronizing &&
5d3cb0f6 1646 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1647 if (!kvm_check_tsc_unstable()) {
e26101b1 1648 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1649 pr_debug("kvm: matched tsc offset for %llu\n", data);
1650 } else {
857e4099 1651 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1652 data += delta;
07c1419a 1653 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1654 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1655 }
b48aa97e 1656 matched = true;
0d3da0d2 1657 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1658 } else {
1659 /*
1660 * We split periods of matched TSC writes into generations.
1661 * For each generation, we track the original measured
1662 * nanosecond time, offset, and write, so if TSCs are in
1663 * sync, we can match exact offset, and if not, we can match
4a969980 1664 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1665 *
1666 * These values are tracked in kvm->arch.cur_xxx variables.
1667 */
1668 kvm->arch.cur_tsc_generation++;
1669 kvm->arch.cur_tsc_nsec = ns;
1670 kvm->arch.cur_tsc_write = data;
1671 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1672 matched = false;
0d3da0d2 1673 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1674 kvm->arch.cur_tsc_generation, data);
f38e098f 1675 }
e26101b1
ZA		 1676
1677 /*
1678 * We also track th most recent recorded KHZ, write and time to
1679 * allow the matching interval to be extended at each write.
1680 */
f38e098f
ZA		 1681 kvm->arch.last_tsc_nsec = ns;
1682 kvm->arch.last_tsc_write = data;
5d3cb0f6 1683 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1684
b183aa58 1685 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1686
1687 /* Keep track of which generation this VCPU has synchronized to */
1688 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1689 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1690 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1691
d6321d49 1692 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1693 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1694
a545ab6a 1695 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1696 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1697
1698 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1699 if (!matched) {
b48aa97e 1700 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1701 } else if (!already_matched) {
1702 kvm->arch.nr_vcpus_matched_tsc++;
1703 }
b48aa97e
MT		 1704
1705 kvm_track_tsc_matching(vcpu);
1706 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1707}
e26101b1 1708
99e3e30a
ZA		 1709EXPORT_SYMBOL_GPL(kvm_write_tsc);
1710
58ea6767
HZ		 1711static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1712 s64 adjustment)
1713{
ea26e4ec 1714 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1715}
1716
1717static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1718{
1719 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1720 WARN_ON(adjustment < 0);
1721 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1722 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1723}
1724
d828199e
MT		 1725#ifdef CONFIG_X86_64
1726
a5a1d1c2 1727static u64 read_tsc(void)
d828199e 1728{
a5a1d1c2 1729 u64 ret = (u64)rdtsc_ordered();
03b9730b 1730 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1731
1732 if (likely(ret >= last))
1733 return ret;
1734
1735 /*
1736 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1737 * predictable (it's just a function of time and the likely is
d828199e
MT		 1738 * very likely) and there's a data dependence, so force GCC
1739 * to generate a branch instead. I don't barrier() because
1740 * we don't actually need a barrier, and if this function
1741 * ever gets inlined it will generate worse code.
1742 */
1743 asm volatile ("");
1744 return last;
1745}
1746
b0c39dc6 1747static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1748{
1749 long v;
1750 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1751 u64 tsc_pg_val;
1752
1753 switch (gtod->clock.vclock_mode) {
1754 case VCLOCK_HVCLOCK:
1755 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1756 tsc_timestamp);
1757 if (tsc_pg_val != U64_MAX) {
1758 /* TSC page valid */
1759 *mode = VCLOCK_HVCLOCK;
1760 v = (tsc_pg_val - gtod->clock.cycle_last) &
1761 gtod->clock.mask;
1762 } else {
1763 /* TSC page invalid */
1764 *mode = VCLOCK_NONE;
1765 }
1766 break;
1767 case VCLOCK_TSC:
1768 *mode = VCLOCK_TSC;
1769 *tsc_timestamp = read_tsc();
1770 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1771 gtod->clock.mask;
1772 break;
1773 default:
1774 *mode = VCLOCK_NONE;
1775 }
d828199e 1776
b0c39dc6
VK		 1777 if (*mode == VCLOCK_NONE)
1778 *tsc_timestamp = v = 0;
d828199e 1779
d828199e
MT		 1780 return v * gtod->clock.mult;
1781}
1782
b0c39dc6 1783static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1784{
cbcf2dd3 1785 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1786 unsigned long seq;
d828199e 1787 int mode;
cbcf2dd3 1788 u64 ns;
d828199e 1789
d828199e
MT		 1790 do {
1791 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1792 ns = gtod->nsec_base;
b0c39dc6 1793 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1794 ns >>= gtod->clock.shift;
cbcf2dd3 1795 ns += gtod->boot_ns;
d828199e 1796 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1797 *t = ns;
d828199e
MT		 1798
1799 return mode;
1800}
1801
899a31f5 1802static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1803{
1804 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1805 unsigned long seq;
1806 int mode;
1807 u64 ns;
1808
1809 do {
1810 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1811 ts->tv_sec = gtod->wall_time_sec;
1812 ns = gtod->nsec_base;
b0c39dc6 1813 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1814 ns >>= gtod->clock.shift;
1815 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1816
1817 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1818 ts->tv_nsec = ns;
1819
1820 return mode;
1821}
1822
b0c39dc6
VK		 1823/* returns true if host is using TSC based clocksource */
1824static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1825{
d828199e 1826 /* checked again under seqlock below */
b0c39dc6 1827 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1828 return false;
1829
b0c39dc6
VK		 1830 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1831 tsc_timestamp));
d828199e 1832}
55dd00a7 1833
b0c39dc6 1834/* returns true if host is using TSC based clocksource */
899a31f5 1835static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1836 u64 *tsc_timestamp)
55dd00a7
MT		 1837{
1838 /* checked again under seqlock below */
b0c39dc6 1839 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1840 return false;
1841
b0c39dc6 1842 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1843}
d828199e
MT		 1844#endif
1845
1846/*
1847 *
b48aa97e
MT		 1848 * Assuming a stable TSC across physical CPUS, and a stable TSC
1849 * across virtual CPUs, the following condition is possible.
1850 * Each numbered line represents an event visible to both
d828199e
MT		 1851 * CPUs at the next numbered event.
1852 *
1853 * "timespecX" represents host monotonic time. "tscX" represents
1854 * RDTSC value.
1855 *
1856 * VCPU0 on CPU0 | VCPU1 on CPU1
1857 *
1858 * 1. read timespec0,tsc0
1859 * 2. | timespec1 = timespec0 + N
1860 * | tsc1 = tsc0 + M
1861 * 3. transition to guest | transition to guest
1862 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1863 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1864 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1865 *
1866 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1867 *
1868 * - ret0 < ret1
1869 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1870 * ...
1871 * - 0 < N - M => M < N
1872 *
1873 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1874 * always the case (the difference between two distinct xtime instances
1875 * might be smaller then the difference between corresponding TSC reads,
1876 * when updating guest vcpus pvclock areas).
1877 *
1878 * To avoid that problem, do not allow visibility of distinct
1879 * system_timestamp/tsc_timestamp values simultaneously: use a master
1880 * copy of host monotonic time values. Update that master copy
1881 * in lockstep.
1882 *
b48aa97e 1883 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1884 *
1885 */
1886
1887static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1888{
1889#ifdef CONFIG_X86_64
1890 struct kvm_arch *ka = &kvm->arch;
1891 int vclock_mode;
b48aa97e
MT		 1892 bool host_tsc_clocksource, vcpus_matched;
1893
1894 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1895 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1896
1897 /*
1898 * If the host uses TSC clock, then passthrough TSC as stable
1899 * to the guest.
1900 */
b48aa97e 1901 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1902 &ka->master_kernel_ns,
1903 &ka->master_cycle_now);
1904
16a96021 1905 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1906 && !ka->backwards_tsc_observed
54750f2c 1907 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1908
d828199e
MT		 1909 if (ka->use_master_clock)
1910 atomic_set(&kvm_guest_has_master_clock, 1);
1911
1912 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1913 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1914 vcpus_matched);
d828199e
MT		 1915#endif
1916}
1917
2860c4b1
PB		 1918void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1919{
1920 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1921}
1922
2e762ff7
MT		 1923static void kvm_gen_update_masterclock(struct kvm *kvm)
1924{
1925#ifdef CONFIG_X86_64
1926 int i;
1927 struct kvm_vcpu *vcpu;
1928 struct kvm_arch *ka = &kvm->arch;
1929
1930 spin_lock(&ka->pvclock_gtod_sync_lock);
1931 kvm_make_mclock_inprogress_request(kvm);
1932 /* no guest entries from this point */
1933 pvclock_update_vm_gtod_copy(kvm);
1934
1935 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1936 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1937
1938 /* guest entries allowed */
1939 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1940 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1941
1942 spin_unlock(&ka->pvclock_gtod_sync_lock);
1943#endif
1944}
1945
e891a32e 1946u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1947{
108b249c 1948 struct kvm_arch *ka = &kvm->arch;
8b953440 1949 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1950 u64 ret;
108b249c 1951
8b953440
PB		 1952 spin_lock(&ka->pvclock_gtod_sync_lock);
1953 if (!ka->use_master_clock) {
1954 spin_unlock(&ka->pvclock_gtod_sync_lock);
1955 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1956 }
1957
8b953440
PB		 1958 hv_clock.tsc_timestamp = ka->master_cycle_now;
1959 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1960 spin_unlock(&ka->pvclock_gtod_sync_lock);
1961
e2c2206a
WL		 1962 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1963 get_cpu();
1964
e70b57a6
WL		 1965 if (__this_cpu_read(cpu_tsc_khz)) {
1966 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1967 &hv_clock.tsc_shift,
1968 &hv_clock.tsc_to_system_mul);
1969 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1970 } else
1971 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1972
1973 put_cpu();
1974
1975 return ret;
108b249c
PB		 1976}
1977
0d6dd2ff
PB		 1978static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1979{
1980 struct kvm_vcpu_arch *vcpu = &v->arch;
1981 struct pvclock_vcpu_time_info guest_hv_clock;
1982
4e335d9e 1983 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1984 &guest_hv_clock, sizeof(guest_hv_clock))))
1985 return;
1986
1987 /* This VCPU is paused, but it's legal for a guest to read another
1988 * VCPU's kvmclock, so we really have to follow the specification where
1989 * it says that version is odd if data is being modified, and even after
1990 * it is consistent.
1991 *
1992 * Version field updates must be kept separate. This is because
1993 * kvm_write_guest_cached might use a "rep movs" instruction, and
1994 * writes within a string instruction are weakly ordered. So there
1995 * are three writes overall.
1996 *
1997 * As a small optimization, only write the version field in the first
1998 * and third write. The vcpu->pv_time cache is still valid, because the
1999 * version field is the first in the struct.
2000 */
2001 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2002
51c4b8bb
LA		 2003 if (guest_hv_clock.version & 1)
2004 ++guest_hv_clock.version; /* first time write, random junk */
2005
0d6dd2ff 2006 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2007 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2008 &vcpu->hv_clock,
2009 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2010
2011 smp_wmb();
2012
2013 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2014 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2015
2016 if (vcpu->pvclock_set_guest_stopped_request) {
2017 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2018 vcpu->pvclock_set_guest_stopped_request = false;
2019 }
2020
2021 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2022
4e335d9e
PB		 2023 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2024 &vcpu->hv_clock,
2025 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2026
2027 smp_wmb();
2028
2029 vcpu->hv_clock.version++;
4e335d9e
PB		 2030 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2031 &vcpu->hv_clock,
2032 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2033}
2034
34c238a1 2035static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2036{
78db6a50 2037 unsigned long flags, tgt_tsc_khz;
18068523 2038 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2039 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2040 s64 kernel_ns;
d828199e 2041 u64 tsc_timestamp, host_tsc;
51d59c6b 2042 u8 pvclock_flags;
d828199e
MT		 2043 bool use_master_clock;
2044
2045 kernel_ns = 0;
2046 host_tsc = 0;
18068523 2047
d828199e
MT		 2048 /*
2049 * If the host uses TSC clock, then passthrough TSC as stable
2050 * to the guest.
2051 */
2052 spin_lock(&ka->pvclock_gtod_sync_lock);
2053 use_master_clock = ka->use_master_clock;
2054 if (use_master_clock) {
2055 host_tsc = ka->master_cycle_now;
2056 kernel_ns = ka->master_kernel_ns;
2057 }
2058 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2059
2060 /* Keep irq disabled to prevent changes to the clock */
2061 local_irq_save(flags);
78db6a50
PB		 2062 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2063 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2064 local_irq_restore(flags);
2065 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2066 return 1;
2067 }
d828199e 2068 if (!use_master_clock) {
4ea1636b 2069 host_tsc = rdtsc();
108b249c 2070 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2071 }
2072
4ba76538 2073 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2074
c285545f
ZA		 2075 /*
2076 * We may have to catch up the TSC to match elapsed wall clock
2077 * time for two reasons, even if kvmclock is used.
2078 * 1) CPU could have been running below the maximum TSC rate
2079 * 2) Broken TSC compensation resets the base at each VCPU
2080 * entry to avoid unknown leaps of TSC even when running
2081 * again on the same CPU. This may cause apparent elapsed
2082 * time to disappear, and the guest to stand still or run
2083 * very slowly.
2084 */
2085 if (vcpu->tsc_catchup) {
2086 u64 tsc = compute_guest_tsc(v, kernel_ns);
2087 if (tsc > tsc_timestamp) {
f1e2b260 2088 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2089 tsc_timestamp = tsc;
2090 }
50d0a0f9
GH		 2091 }
2092
18068523
GOC		 2093 local_irq_restore(flags);
2094
0d6dd2ff 2095 /* With all the info we got, fill in the values */
18068523 2096
78db6a50
PB		 2097 if (kvm_has_tsc_control)
2098 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2099
2100 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2101 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2102 &vcpu->hv_clock.tsc_shift,
2103 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2104 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2105 }
2106
1d5f066e 2107 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2108 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2109 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2110
d828199e 2111 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2112 pvclock_flags = 0;
d828199e
MT		 2113 if (use_master_clock)
2114 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2115
78c0337a
MT		 2116 vcpu->hv_clock.flags = pvclock_flags;
2117
095cf55d
PB		 2118 if (vcpu->pv_time_enabled)
2119 kvm_setup_pvclock_page(v);
2120 if (v == kvm_get_vcpu(v->kvm, 0))
2121 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2122 return 0;
c8076604
GH		 2123}
2124
0061d53d
MT		 2125/*
2126 * kvmclock updates which are isolated to a given vcpu, such as
2127 * vcpu->cpu migration, should not allow system_timestamp from
2128 * the rest of the vcpus to remain static. Otherwise ntp frequency
2129 * correction applies to one vcpu's system_timestamp but not
2130 * the others.
2131 *
2132 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2133 * We need to rate-limit these requests though, as they can
2134 * considerably slow guests that have a large number of vcpus.
2135 * The time for a remote vcpu to update its kvmclock is bound
2136 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2137 */
2138
7e44e449
AJ		 2139#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2140
2141static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2142{
2143 int i;
7e44e449
AJ		 2144 struct delayed_work *dwork = to_delayed_work(work);
2145 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2146 kvmclock_update_work);
2147 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2148 struct kvm_vcpu *vcpu;
2149
2150 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2151 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2152 kvm_vcpu_kick(vcpu);
2153 }
2154}
2155
7e44e449
AJ		 2156static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2157{
2158 struct kvm *kvm = v->kvm;
2159
105b21bb 2160 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2161 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2162 KVMCLOCK_UPDATE_DELAY);
2163}
2164
332967a3
AJ		 2165#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2166
2167static void kvmclock_sync_fn(struct work_struct *work)
2168{
2169 struct delayed_work *dwork = to_delayed_work(work);
2170 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2171 kvmclock_sync_work);
2172 struct kvm *kvm = container_of(ka, struct kvm, arch);
2173
630994b3
MT		 2174 if (!kvmclock_periodic_sync)
2175 return;
2176
332967a3
AJ		 2177 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2178 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2179 KVMCLOCK_SYNC_PERIOD);
2180}
2181
9ffd986c 2182static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2183{
890ca9ae
HY		 2184 u64 mcg_cap = vcpu->arch.mcg_cap;
2185 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2186 u32 msr = msr_info->index;
2187 u64 data = msr_info->data;
890ca9ae 2188
15c4a640 2189 switch (msr) {
15c4a640 2190 case MSR_IA32_MCG_STATUS:
890ca9ae 2191 vcpu->arch.mcg_status = data;
15c4a640 2192 break;
c7ac679c 2193 case MSR_IA32_MCG_CTL:
44883f01
PB		 2194 if (!(mcg_cap & MCG_CTL_P) &&
2195 (data || !msr_info->host_initiated))
890ca9ae
HY		 2196 return 1;
2197 if (data != 0 && data != ~(u64)0)
44883f01 2198 return 1;
890ca9ae
HY		 2199 vcpu->arch.mcg_ctl = data;
2200 break;
2201 default:
2202 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2203 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2204 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2205 /* only 0 or all 1s can be written to IA32_MCi_CTL
2206 * some Linux kernels though clear bit 10 in bank 4 to
2207 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2208 * this to avoid an uncatched #GP in the guest
2209 */
890ca9ae 2210 if ((offset & 0x3) == 0 &&
114be429 2211 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2212 return -1;
9ffd986c
WL		 2213 if (!msr_info->host_initiated &&
2214 (offset & 0x3) == 1 && data != 0)
2215 return -1;
890ca9ae
HY		 2216 vcpu->arch.mce_banks[offset] = data;
2217 break;
2218 }
2219 return 1;
2220 }
2221 return 0;
2222}
2223
ffde22ac
ES		 2224static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2225{
2226 struct kvm *kvm = vcpu->kvm;
2227 int lm = is_long_mode(vcpu);
2228 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2229 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2230 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2231 : kvm->arch.xen_hvm_config.blob_size_32;
2232 u32 page_num = data & ~PAGE_MASK;
2233 u64 page_addr = data & PAGE_MASK;
2234 u8 *page;
2235 int r;
2236
2237 r = -E2BIG;
2238 if (page_num >= blob_size)
2239 goto out;
2240 r = -ENOMEM;
ff5c2c03
SL		 2241 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2242 if (IS_ERR(page)) {
2243 r = PTR_ERR(page);
ffde22ac 2244 goto out;
ff5c2c03 2245 }
54bf36aa 2246 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2247 goto out_free;
2248 r = 0;
2249out_free:
2250 kfree(page);
2251out:
2252 return r;
2253}
2254
344d9588
GN		 2255static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2256{
2257 gpa_t gpa = data & ~0x3f;
2258
52a5c155
WL		 2259 /* Bits 3:5 are reserved, Should be zero */
2260 if (data & 0x38)
344d9588
GN		 2261 return 1;
2262
2263 vcpu->arch.apf.msr_val = data;
2264
2265 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2266 kvm_clear_async_pf_completion_queue(vcpu);
2267 kvm_async_pf_hash_reset(vcpu);
2268 return 0;
2269 }
2270
4e335d9e 2271 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2272 sizeof(u32)))
344d9588
GN		 2273 return 1;
2274
6adba527 2275 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2276 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2277 kvm_async_pf_wakeup_all(vcpu);
2278 return 0;
2279}
2280
12f9a48f
GC		 2281static void kvmclock_reset(struct kvm_vcpu *vcpu)
2282{
0b79459b 2283 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2284}
2285
f38a7b75
WL		 2286static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2287{
2288 ++vcpu->stat.tlb_flush;
2289 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2290}
2291
c9aaa895
GC		 2292static void record_steal_time(struct kvm_vcpu *vcpu)
2293{
2294 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2295 return;
2296
4e335d9e 2297 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2298 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2299 return;
2300
f38a7b75
WL		 2301 /*
2302 * Doing a TLB flush here, on the guest's behalf, can avoid
2303 * expensive IPIs.
2304 */
2305 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2306 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2307
35f3fae1
WL		 2308 if (vcpu->arch.st.steal.version & 1)
2309 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2310
2311 vcpu->arch.st.steal.version += 1;
2312
4e335d9e 2313 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2314 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2315
2316 smp_wmb();
2317
c54cdf14
LC		 2318 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2319 vcpu->arch.st.last_steal;
2320 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2321
4e335d9e 2322 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2323 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2324
2325 smp_wmb();
2326
2327 vcpu->arch.st.steal.version += 1;
c9aaa895 2328
4e335d9e 2329 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2330 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2331}
2332
8fe8ab46 2333int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2334{
5753785f 2335 bool pr = false;
8fe8ab46
WA		 2336 u32 msr = msr_info->index;
2337 u64 data = msr_info->data;
5753785f 2338
15c4a640 2339 switch (msr) {
2e32b719 2340 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2341 case MSR_IA32_UCODE_WRITE:
2342 case MSR_VM_HSAVE_PA:
2343 case MSR_AMD64_PATCH_LOADER:
2344 case MSR_AMD64_BU_CFG2:
405a353a 2345 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2346 break;
2347
518e7b94
WL		 2348 case MSR_IA32_UCODE_REV:
2349 if (msr_info->host_initiated)
2350 vcpu->arch.microcode_version = data;
2351 break;
15c4a640 2352 case MSR_EFER:
b69e8cae 2353 return set_efer(vcpu, data);
8f1589d9
AP		 2354 case MSR_K7_HWCR:
2355 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2356 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2357 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2358 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2359 if (data != 0) {
a737f256
CD		 2360 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2361 data);
8f1589d9
AP		 2362 return 1;
2363 }
15c4a640 2364 break;
f7c6d140
AP		 2365 case MSR_FAM10H_MMIO_CONF_BASE:
2366 if (data != 0) {
a737f256
CD		 2367 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2368 "0x%llx\n", data);
f7c6d140
AP		 2369 return 1;
2370 }
15c4a640 2371 break;
b5e2fec0
AG		 2372 case MSR_IA32_DEBUGCTLMSR:
2373 if (!data) {
2374 /* We support the non-activated case already */
2375 break;
2376 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2377 /* Values other than LBR and BTF are vendor-specific,
2378 thus reserved and should throw a #GP */
2379 return 1;
2380 }
a737f256
CD		 2381 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2382 __func__, data);
b5e2fec0 2383 break;
9ba075a6 2384 case 0x200 ... 0x2ff:
ff53604b 2385 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2386 case MSR_IA32_APICBASE:
58cb628d 2387 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2388 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2389 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2390 case MSR_IA32_TSCDEADLINE:
2391 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2392 break;
ba904635 2393 case MSR_IA32_TSC_ADJUST:
d6321d49 2394 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2395 if (!msr_info->host_initiated) {
d913b904 2396 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2397 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2398 }
2399 vcpu->arch.ia32_tsc_adjust_msr = data;
2400 }
2401 break;
15c4a640 2402 case MSR_IA32_MISC_ENABLE:
ad312c7c 2403 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2404 break;
64d60670
PB		 2405 case MSR_IA32_SMBASE:
2406 if (!msr_info->host_initiated)
2407 return 1;
2408 vcpu->arch.smbase = data;
2409 break;
dd259935
PB		 2410 case MSR_IA32_TSC:
2411 kvm_write_tsc(vcpu, msr_info);
2412 break;
52797bf9
LA		 2413 case MSR_SMI_COUNT:
2414 if (!msr_info->host_initiated)
2415 return 1;
2416 vcpu->arch.smi_count = data;
2417 break;
11c6bffa 2418 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2419 case MSR_KVM_WALL_CLOCK:
2420 vcpu->kvm->arch.wall_clock = data;
2421 kvm_write_wall_clock(vcpu->kvm, data);
2422 break;
11c6bffa 2423 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2424 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2425 struct kvm_arch *ka = &vcpu->kvm->arch;
2426
12f9a48f 2427 kvmclock_reset(vcpu);
18068523 2428
54750f2c
MT		 2429 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2430 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2431
2432 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2433 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2434
2435 ka->boot_vcpu_runs_old_kvmclock = tmp;
2436 }
2437
18068523 2438 vcpu->arch.time = data;
0061d53d 2439 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2440
2441 /* we verify if the enable bit is set... */
2442 if (!(data & 1))
2443 break;
2444
4e335d9e 2445 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2446 &vcpu->arch.pv_time, data & ~1ULL,
2447 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2448 vcpu->arch.pv_time_enabled = false;
2449 else
2450 vcpu->arch.pv_time_enabled = true;
32cad84f 2451
18068523
GOC		 2452 break;
2453 }
344d9588
GN		 2454 case MSR_KVM_ASYNC_PF_EN:
2455 if (kvm_pv_enable_async_pf(vcpu, data))
2456 return 1;
2457 break;
c9aaa895
GC		 2458 case MSR_KVM_STEAL_TIME:
2459
2460 if (unlikely(!sched_info_on()))
2461 return 1;
2462
2463 if (data & KVM_STEAL_RESERVED_MASK)
2464 return 1;
2465
4e335d9e 2466 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2467 data & KVM_STEAL_VALID_BITS,
2468 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2469 return 1;
2470
2471 vcpu->arch.st.msr_val = data;
2472
2473 if (!(data & KVM_MSR_ENABLED))
2474 break;
2475
c9aaa895
GC		 2476 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2477
2478 break;
ae7a2a3f
MT		 2479 case MSR_KVM_PV_EOI_EN:
2480 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2481 return 1;
2482 break;
c9aaa895 2483
890ca9ae
HY		 2484 case MSR_IA32_MCG_CTL:
2485 case MSR_IA32_MCG_STATUS:
81760dcc 2486 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2487 return set_msr_mce(vcpu, msr_info);
71db6023 2488
6912ac32
WH		 2489 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2490 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2491 pr = true; /* fall through */
2492 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2493 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2494 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2495 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2496
2497 if (pr || data != 0)
a737f256
CD		 2498 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2499 "0x%x data 0x%llx\n", msr, data);
5753785f 2500 break;
84e0cefa
JS		 2501 case MSR_K7_CLK_CTL:
2502 /*
2503 * Ignore all writes to this no longer documented MSR.
2504 * Writes are only relevant for old K7 processors,
2505 * all pre-dating SVM, but a recommended workaround from
4a969980 2506 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2507 * affected processor models on the command line, hence
2508 * the need to ignore the workaround.
2509 */
2510 break;
55cd8e5a 2511 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2512 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2513 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2514 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2515 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2516 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2517 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2518 return kvm_hv_set_msr_common(vcpu, msr, data,
2519 msr_info->host_initiated);
91c9c3ed 2520 case MSR_IA32_BBL_CR_CTL3:
2521 /* Drop writes to this legacy MSR -- see rdmsr
2522 * counterpart for further detail.
2523 */
fab0aa3b
EM		 2524 if (report_ignored_msrs)
2525 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2526 msr, data);
91c9c3ed 2527 break;
2b036c6b 2528 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2529 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2530 return 1;
2531 vcpu->arch.osvw.length = data;
2532 break;
2533 case MSR_AMD64_OSVW_STATUS:
d6321d49 2534 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2535 return 1;
2536 vcpu->arch.osvw.status = data;
2537 break;
db2336a8
KH		 2538 case MSR_PLATFORM_INFO:
2539 if (!msr_info->host_initiated ||
db2336a8
KH		 2540 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2541 cpuid_fault_enabled(vcpu)))
2542 return 1;
2543 vcpu->arch.msr_platform_info = data;
2544 break;
2545 case MSR_MISC_FEATURES_ENABLES:
2546 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2547 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2548 !supports_cpuid_fault(vcpu)))
2549 return 1;
2550 vcpu->arch.msr_misc_features_enables = data;
2551 break;
15c4a640 2552 default:
ffde22ac
ES		 2553 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2554 return xen_hvm_config(vcpu, data);
c6702c9d 2555 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2556 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2557 if (!ignore_msrs) {
ae0f5499 2558 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2559 msr, data);
ed85c068
AP		 2560 return 1;
2561 } else {
fab0aa3b
EM		 2562 if (report_ignored_msrs)
2563 vcpu_unimpl(vcpu,
2564 "ignored wrmsr: 0x%x data 0x%llx\n",
2565 msr, data);
ed85c068
AP		 2566 break;
2567 }
15c4a640
CO		 2568 }
2569 return 0;
2570}
2571EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2572
2573
2574/*
2575 * Reads an msr value (of 'msr_index') into 'pdata'.
2576 * Returns 0 on success, non-0 otherwise.
2577 * Assumes vcpu_load() was already called.
2578 */
609e36d3 2579int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2580{
609e36d3 2581 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2582}
ff651cb6 2583EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2584
44883f01 2585static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2586{
2587 u64 data;
890ca9ae
HY		 2588 u64 mcg_cap = vcpu->arch.mcg_cap;
2589 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2590
2591 switch (msr) {
15c4a640
CO		 2592 case MSR_IA32_P5_MC_ADDR:
2593 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2594 data = 0;
2595 break;
15c4a640 2596 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2597 data = vcpu->arch.mcg_cap;
2598 break;
c7ac679c 2599 case MSR_IA32_MCG_CTL:
44883f01 2600 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2601 return 1;
2602 data = vcpu->arch.mcg_ctl;
2603 break;
2604 case MSR_IA32_MCG_STATUS:
2605 data = vcpu->arch.mcg_status;
2606 break;
2607 default:
2608 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2609 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2610 u32 offset = msr - MSR_IA32_MC0_CTL;
2611 data = vcpu->arch.mce_banks[offset];
2612 break;
2613 }
2614 return 1;
2615 }
2616 *pdata = data;
2617 return 0;
2618}
2619
609e36d3 2620int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2621{
609e36d3 2622 switch (msr_info->index) {
890ca9ae 2623 case MSR_IA32_PLATFORM_ID:
15c4a640 2624 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2625 case MSR_IA32_DEBUGCTLMSR:
2626 case MSR_IA32_LASTBRANCHFROMIP:
2627 case MSR_IA32_LASTBRANCHTOIP:
2628 case MSR_IA32_LASTINTFROMIP:
2629 case MSR_IA32_LASTINTTOIP:
60af2ecd 2630 case MSR_K8_SYSCFG:
3afb1121
PB		 2631 case MSR_K8_TSEG_ADDR:
2632 case MSR_K8_TSEG_MASK:
60af2ecd 2633 case MSR_K7_HWCR:
61a6bd67 2634 case MSR_VM_HSAVE_PA:
1fdbd48c 2635 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2636 case MSR_AMD64_NB_CFG:
f7c6d140 2637 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2638 case MSR_AMD64_BU_CFG2:
0c2df2a1 2639 case MSR_IA32_PERF_CTL:
405a353a 2640 case MSR_AMD64_DC_CFG:
609e36d3 2641 msr_info->data = 0;
15c4a640 2642 break;
c51eb52b 2643 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2644 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2645 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2646 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2647 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2648 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2649 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2650 msr_info->data = 0;
5753785f 2651 break;
742bc670 2652 case MSR_IA32_UCODE_REV:
518e7b94 2653 msr_info->data = vcpu->arch.microcode_version;
742bc670 2654 break;
dd259935
PB		 2655 case MSR_IA32_TSC:
2656 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2657 break;
9ba075a6 2658 case MSR_MTRRcap:
9ba075a6 2659 case 0x200 ... 0x2ff:
ff53604b 2660 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2661 case 0xcd: /* fsb frequency */
609e36d3 2662 msr_info->data = 3;
15c4a640 2663 break;
7b914098
JS		 2664 /*
2665 * MSR_EBC_FREQUENCY_ID
2666 * Conservative value valid for even the basic CPU models.
2667 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2668 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2669 * and 266MHz for model 3, or 4. Set Core Clock
2670 * Frequency to System Bus Frequency Ratio to 1 (bits
2671 * 31:24) even though these are only valid for CPU
2672 * models > 2, however guests may end up dividing or
2673 * multiplying by zero otherwise.
2674 */
2675 case MSR_EBC_FREQUENCY_ID:
609e36d3 2676 msr_info->data = 1 << 24;
7b914098 2677 break;
15c4a640 2678 case MSR_IA32_APICBASE:
609e36d3 2679 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2680 break;
0105d1a5 2681 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2682 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2683 break;
a3e06bbe 2684 case MSR_IA32_TSCDEADLINE:
609e36d3 2685 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2686 break;
ba904635 2687 case MSR_IA32_TSC_ADJUST:
609e36d3 2688 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2689 break;
15c4a640 2690 case MSR_IA32_MISC_ENABLE:
609e36d3 2691 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2692 break;
64d60670
PB		 2693 case MSR_IA32_SMBASE:
2694 if (!msr_info->host_initiated)
2695 return 1;
2696 msr_info->data = vcpu->arch.smbase;
15c4a640 2697 break;
52797bf9
LA		 2698 case MSR_SMI_COUNT:
2699 msr_info->data = vcpu->arch.smi_count;
2700 break;
847f0ad8
AG		 2701 case MSR_IA32_PERF_STATUS:
2702 /* TSC increment by tick */
609e36d3 2703 msr_info->data = 1000ULL;
847f0ad8 2704 /* CPU multiplier */
b0996ae4 2705 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2706 break;
15c4a640 2707 case MSR_EFER:
609e36d3 2708 msr_info->data = vcpu->arch.efer;
15c4a640 2709 break;
18068523 2710 case MSR_KVM_WALL_CLOCK:
11c6bffa 2711 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2712 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2713 break;
2714 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2715 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2716 msr_info->data = vcpu->arch.time;
18068523 2717 break;
344d9588 2718 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2719 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2720 break;
c9aaa895 2721 case MSR_KVM_STEAL_TIME:
609e36d3 2722 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2723 break;
1d92128f 2724 case MSR_KVM_PV_EOI_EN:
609e36d3 2725 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2726 break;
890ca9ae
HY		 2727 case MSR_IA32_P5_MC_ADDR:
2728 case MSR_IA32_P5_MC_TYPE:
2729 case MSR_IA32_MCG_CAP:
2730 case MSR_IA32_MCG_CTL:
2731 case MSR_IA32_MCG_STATUS:
81760dcc 2732 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2733 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2734 msr_info->host_initiated);
84e0cefa
JS		 2735 case MSR_K7_CLK_CTL:
2736 /*
2737 * Provide expected ramp-up count for K7. All other
2738 * are set to zero, indicating minimum divisors for
2739 * every field.
2740 *
2741 * This prevents guest kernels on AMD host with CPU
2742 * type 6, model 8 and higher from exploding due to
2743 * the rdmsr failing.
2744 */
609e36d3 2745 msr_info->data = 0x20000000;
84e0cefa 2746 break;
55cd8e5a 2747 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2748 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2749 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2750 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2751 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2752 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2753 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2754 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2755 msr_info->index, &msr_info->data,
2756 msr_info->host_initiated);
55cd8e5a 2757 break;
91c9c3ed 2758 case MSR_IA32_BBL_CR_CTL3:
2759 /* This legacy MSR exists but isn't fully documented in current
2760 * silicon. It is however accessed by winxp in very narrow
2761 * scenarios where it sets bit #19, itself documented as
2762 * a "reserved" bit. Best effort attempt to source coherent
2763 * read data here should the balance of the register be
2764 * interpreted by the guest:
2765 *
2766 * L2 cache control register 3: 64GB range, 256KB size,
2767 * enabled, latency 0x1, configured
2768 */
609e36d3 2769 msr_info->data = 0xbe702111;
91c9c3ed 2770 break;
2b036c6b 2771 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2772 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2773 return 1;
609e36d3 2774 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2775 break;
2776 case MSR_AMD64_OSVW_STATUS:
d6321d49 2777 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2778 return 1;
609e36d3 2779 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2780 break;
db2336a8 2781 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2782 if (!msr_info->host_initiated &&
2783 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2784 return 1;
db2336a8
KH		 2785 msr_info->data = vcpu->arch.msr_platform_info;
2786 break;
2787 case MSR_MISC_FEATURES_ENABLES:
2788 msr_info->data = vcpu->arch.msr_misc_features_enables;
2789 break;
15c4a640 2790 default:
c6702c9d 2791 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2792 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2793 if (!ignore_msrs) {
ae0f5499
BD		 2794 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2795 msr_info->index);
ed85c068
AP		 2796 return 1;
2797 } else {
fab0aa3b
EM		 2798 if (report_ignored_msrs)
2799 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2800 msr_info->index);
609e36d3 2801 msr_info->data = 0;
ed85c068
AP		 2802 }
2803 break;
15c4a640 2804 }
15c4a640
CO		 2805 return 0;
2806}
2807EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2808
313a3dc7
CO		 2809/*
2810 * Read or write a bunch of msrs. All parameters are kernel addresses.
2811 *
2812 * @return number of msrs set successfully.
2813 */
2814static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2815 struct kvm_msr_entry *entries,
2816 int (*do_msr)(struct kvm_vcpu *vcpu,
2817 unsigned index, u64 *data))
2818{
801e459a 2819 int i;
313a3dc7 2820
313a3dc7
CO		 2821 for (i = 0; i < msrs->nmsrs; ++i)
2822 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2823 break;
2824
313a3dc7
CO		 2825 return i;
2826}
2827
2828/*
2829 * Read or write a bunch of msrs. Parameters are user addresses.
2830 *
2831 * @return number of msrs set successfully.
2832 */
2833static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2834 int (*do_msr)(struct kvm_vcpu *vcpu,
2835 unsigned index, u64 *data),
2836 int writeback)
2837{
2838 struct kvm_msrs msrs;
2839 struct kvm_msr_entry *entries;
2840 int r, n;
2841 unsigned size;
2842
2843 r = -EFAULT;
2844 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2845 goto out;
2846
2847 r = -E2BIG;
2848 if (msrs.nmsrs >= MAX_IO_MSRS)
2849 goto out;
2850
313a3dc7 2851 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2852 entries = memdup_user(user_msrs->entries, size);
2853 if (IS_ERR(entries)) {
2854 r = PTR_ERR(entries);
313a3dc7 2855 goto out;
ff5c2c03 2856 }
313a3dc7
CO		 2857
2858 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2859 if (r < 0)
2860 goto out_free;
2861
2862 r = -EFAULT;
2863 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2864 goto out_free;
2865
2866 r = n;
2867
2868out_free:
7a73c028 2869 kfree(entries);
313a3dc7
CO		 2870out:
2871 return r;
2872}
2873
4d5422ce
WL		 2874static inline bool kvm_can_mwait_in_guest(void)
2875{
2876 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2877 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2878 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2879}
2880
784aa3d7 2881int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2882{
4d5422ce 2883 int r = 0;
018d00d2
ZX		 2884
2885 switch (ext) {
2886 case KVM_CAP_IRQCHIP:
2887 case KVM_CAP_HLT:
2888 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2889 case KVM_CAP_SET_TSS_ADDR:
07716717 2890 case KVM_CAP_EXT_CPUID:
9c15bb1d 2891 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2892 case KVM_CAP_CLOCKSOURCE:
7837699f 2893 case KVM_CAP_PIT:
a28e4f5a 2894 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2895 case KVM_CAP_MP_STATE:
ed848624 2896 case KVM_CAP_SYNC_MMU:
a355c85c 2897 case KVM_CAP_USER_NMI:
52d939a0 2898 case KVM_CAP_REINJECT_CONTROL:
4925663a 2899 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2900 case KVM_CAP_IOEVENTFD:
f848a5a8 2901 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2902 case KVM_CAP_PIT2:
e9f42757 2903 case KVM_CAP_PIT_STATE2:
b927a3ce 2904 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2905 case KVM_CAP_XEN_HVM:
3cfc3092 2906 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2907 case KVM_CAP_HYPERV:
10388a07 2908 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2909 case KVM_CAP_HYPERV_SPIN:
5c919412 2910 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2911 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2912 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2913 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2914 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 2915 case KVM_CAP_HYPERV_SEND_IPI:
ab9f4ecb 2916 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2917 case KVM_CAP_DEBUGREGS:
d2be1651 2918 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2919 case KVM_CAP_XSAVE:
344d9588 2920 case KVM_CAP_ASYNC_PF:
92a1f12d 2921 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2922 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2923 case KVM_CAP_READONLY_MEM:
5f66b620 2924 case KVM_CAP_HYPERV_TIME:
100943c5 2925 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2926 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2927 case KVM_CAP_ENABLE_CAP_VM:
2928 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2929 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2930 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2931 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2932 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 2933 case KVM_CAP_MSR_PLATFORM_INFO:
018d00d2
ZX		 2934 r = 1;
2935 break;
01643c51
KH		 2936 case KVM_CAP_SYNC_REGS:
2937 r = KVM_SYNC_X86_VALID_FIELDS;
2938 break;
e3fd9a93
PB		 2939 case KVM_CAP_ADJUST_CLOCK:
2940 r = KVM_CLOCK_TSC_STABLE;
2941 break;
4d5422ce 2942 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 2943 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2944 if(kvm_can_mwait_in_guest())
2945 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2946 break;
6d396b55
PB		 2947 case KVM_CAP_X86_SMM:
2948 /* SMBASE is usually relocated above 1M on modern chipsets,
2949 * and SMM handlers might indeed rely on 4G segment limits,
2950 * so do not report SMM to be available if real mode is
2951 * emulated via vm86 mode. Still, do not go to great lengths
2952 * to avoid userspace's usage of the feature, because it is a
2953 * fringe case that is not enabled except via specific settings
2954 * of the module parameters.
2955 */
bc226f07 2956 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 2957 break;
774ead3a
AK		 2958 case KVM_CAP_VAPIC:
2959 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2960 break;
f725230a 2961 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2962 r = KVM_SOFT_MAX_VCPUS;
2963 break;
2964 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2965 r = KVM_MAX_VCPUS;
2966 break;
a988b910 2967 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2968 r = KVM_USER_MEM_SLOTS;
a988b910 2969 break;
a68a6a72
MT		 2970 case KVM_CAP_PV_MMU: /* obsolete */
2971 r = 0;
2f333bcb 2972 break;
890ca9ae
HY		 2973 case KVM_CAP_MCE:
2974 r = KVM_MAX_MCE_BANKS;
2975 break;
2d5b5a66 2976 case KVM_CAP_XCRS:
d366bf7e 2977 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2978 break;
92a1f12d
JR		 2979 case KVM_CAP_TSC_CONTROL:
2980 r = kvm_has_tsc_control;
2981 break;
37131313
RK		 2982 case KVM_CAP_X2APIC_API:
2983 r = KVM_X2APIC_API_VALID_FLAGS;
2984 break;
8fcc4b59
JM		 2985 case KVM_CAP_NESTED_STATE:
2986 r = kvm_x86_ops->get_nested_state ?
2987 kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
2988 break;
018d00d2 2989 default:
018d00d2
ZX		 2990 break;
2991 }
2992 return r;
2993
2994}
2995
043405e1
CO		 2996long kvm_arch_dev_ioctl(struct file *filp,
2997 unsigned int ioctl, unsigned long arg)
2998{
2999 void __user *argp = (void __user *)arg;
3000 long r;
3001
3002 switch (ioctl) {
3003 case KVM_GET_MSR_INDEX_LIST: {
3004 struct kvm_msr_list __user *user_msr_list = argp;
3005 struct kvm_msr_list msr_list;
3006 unsigned n;
3007
3008 r = -EFAULT;
3009 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
3010 goto out;
3011 n = msr_list.nmsrs;
62ef68bb 3012 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 3013 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
3014 goto out;
3015 r = -E2BIG;
e125e7b6 3016 if (n < msr_list.nmsrs)
043405e1
CO		 3017 goto out;
3018 r = -EFAULT;
3019 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3020 num_msrs_to_save * sizeof(u32)))
3021 goto out;
e125e7b6 3022 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3023 &emulated_msrs,
62ef68bb 3024 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3025 goto out;
3026 r = 0;
3027 break;
3028 }
9c15bb1d
BP		 3029 case KVM_GET_SUPPORTED_CPUID:
3030 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3031 struct kvm_cpuid2 __user *cpuid_arg = argp;
3032 struct kvm_cpuid2 cpuid;
3033
3034 r = -EFAULT;
3035 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3036 goto out;
9c15bb1d
BP		 3037
3038 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3039 ioctl);
674eea0f
AK		 3040 if (r)
3041 goto out;
3042
3043 r = -EFAULT;
3044 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3045 goto out;
3046 r = 0;
3047 break;
3048 }
890ca9ae 3049 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3050 r = -EFAULT;
c45dcc71
AR		 3051 if (copy_to_user(argp, &kvm_mce_cap_supported,
3052 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3053 goto out;
3054 r = 0;
3055 break;
801e459a
TL		 3056 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3057 struct kvm_msr_list __user *user_msr_list = argp;
3058 struct kvm_msr_list msr_list;
3059 unsigned int n;
3060
3061 r = -EFAULT;
3062 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3063 goto out;
3064 n = msr_list.nmsrs;
3065 msr_list.nmsrs = num_msr_based_features;
3066 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3067 goto out;
3068 r = -E2BIG;
3069 if (n < msr_list.nmsrs)
3070 goto out;
3071 r = -EFAULT;
3072 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3073 num_msr_based_features * sizeof(u32)))
3074 goto out;
3075 r = 0;
3076 break;
3077 }
3078 case KVM_GET_MSRS:
3079 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3080 break;
890ca9ae 3081 }
043405e1
CO		 3082 default:
3083 r = -EINVAL;
3084 }
3085out:
3086 return r;
3087}
3088
f5f48ee1
SY		 3089static void wbinvd_ipi(void *garbage)
3090{
3091 wbinvd();
3092}
3093
3094static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3095{
e0f0bbc5 3096 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3097}
3098
313a3dc7
CO		 3099void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3100{
f5f48ee1
SY		 3101 /* Address WBINVD may be executed by guest */
3102 if (need_emulate_wbinvd(vcpu)) {
3103 if (kvm_x86_ops->has_wbinvd_exit())
3104 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3105 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3106 smp_call_function_single(vcpu->cpu,
3107 wbinvd_ipi, NULL, 1);
3108 }
3109
313a3dc7 3110 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3111
0dd6a6ed
ZA		 3112 /* Apply any externally detected TSC adjustments (due to suspend) */
3113 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3114 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3115 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3116 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3117 }
8f6055cb 3118
b0c39dc6 3119 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3120 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3121 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3122 if (tsc_delta < 0)
3123 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3124
b0c39dc6 3125 if (kvm_check_tsc_unstable()) {
07c1419a 3126 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3127 vcpu->arch.last_guest_tsc);
a545ab6a 3128 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3129 vcpu->arch.tsc_catchup = 1;
c285545f 3130 }
a749e247
PB		 3131
3132 if (kvm_lapic_hv_timer_in_use(vcpu))
3133 kvm_lapic_restart_hv_timer(vcpu);
3134
d98d07ca
MT		 3135 /*
3136 * On a host with synchronized TSC, there is no need to update
3137 * kvmclock on vcpu->cpu migration
3138 */
3139 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3140 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3141 if (vcpu->cpu != cpu)
1bd2009e 3142 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3143 vcpu->cpu = cpu;
6b7d7e76 3144 }
c9aaa895 3145
c9aaa895 3146 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3147}
3148
0b9f6c46
PX		 3149static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3150{
3151 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3152 return;
3153
fa55eedd 3154 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3155
4e335d9e 3156 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3157 &vcpu->arch.st.steal.preempted,
3158 offsetof(struct kvm_steal_time, preempted),
3159 sizeof(vcpu->arch.st.steal.preempted));
3160}
3161
313a3dc7
CO		 3162void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3163{
cc0d907c 3164 int idx;
de63ad4c
LM		 3165
3166 if (vcpu->preempted)
3167 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3168
931f261b
AA		 3169 /*
3170 * Disable page faults because we're in atomic context here.
3171 * kvm_write_guest_offset_cached() would call might_fault()
3172 * that relies on pagefault_disable() to tell if there's a
3173 * bug. NOTE: the write to guest memory may not go through if
3174 * during postcopy live migration or if there's heavy guest
3175 * paging.
3176 */
3177 pagefault_disable();
cc0d907c
AA		 3178 /*
3179 * kvm_memslots() will be called by
3180 * kvm_write_guest_offset_cached() so take the srcu lock.
3181 */
3182 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3183 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3184 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3185 pagefault_enable();
02daab21 3186 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3187 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3188 /*
0e0a53c5
PB		 3189 * Here dr6 is either zero or, if the guest has run and userspace
3190 * has not set any breakpoints or watchpoints, it can be set to
3191 * the guest dr6 (stored in vcpu->arch.dr6). do_debug expects dr6
3192 * to be cleared after it runs, so clear the host register. However,
3193 * MOV to DR can be expensive when running nested, omit it if
3194 * vcpu->arch.dr6 is already zero: in that case, the host dr6 cannot
3195 * currently be nonzero.
efdab992 3196 */
0e0a53c5
PB		 3197 if (vcpu->arch.dr6)
3198 set_debugreg(0, 6);
313a3dc7
CO		 3199}
3200
313a3dc7
CO		 3201static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3202 struct kvm_lapic_state *s)
3203{
fa59cc00 3204 if (vcpu->arch.apicv_active)
d62caabb
AS		 3205 kvm_x86_ops->sync_pir_to_irr(vcpu);
3206
a92e2543 3207 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3208}
3209
3210static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3211 struct kvm_lapic_state *s)
3212{
a92e2543
RK		 3213 int r;
3214
3215 r = kvm_apic_set_state(vcpu, s);
3216 if (r)
3217 return r;
cb142eb7 3218 update_cr8_intercept(vcpu);
313a3dc7
CO		 3219
3220 return 0;
3221}
3222
127a457a
MG		 3223static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3224{
3225 return (!lapic_in_kernel(vcpu) ||
3226 kvm_apic_accept_pic_intr(vcpu));
3227}
3228
782d422b
MG		 3229/*
3230 * if userspace requested an interrupt window, check that the
3231 * interrupt window is open.
3232 *
3233 * No need to exit to userspace if we already have an interrupt queued.
3234 */
3235static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3236{
3237 return kvm_arch_interrupt_allowed(vcpu) &&
3238 !kvm_cpu_has_interrupt(vcpu) &&
3239 !kvm_event_needs_reinjection(vcpu) &&
3240 kvm_cpu_accept_dm_intr(vcpu);
3241}
3242
f77bc6a4
ZX		 3243static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3244 struct kvm_interrupt *irq)
3245{
02cdb50f 3246 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3247 return -EINVAL;
1c1a9ce9
SR		 3248
3249 if (!irqchip_in_kernel(vcpu->kvm)) {
3250 kvm_queue_interrupt(vcpu, irq->irq, false);
3251 kvm_make_request(KVM_REQ_EVENT, vcpu);
3252 return 0;
3253 }
3254
3255 /*
3256 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3257 * fail for in-kernel 8259.
3258 */
3259 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3260 return -ENXIO;
f77bc6a4 3261
1c1a9ce9
SR		 3262 if (vcpu->arch.pending_external_vector != -1)
3263 return -EEXIST;
f77bc6a4 3264
1c1a9ce9 3265 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3266 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3267 return 0;
3268}
3269
c4abb7c9
JK		 3270static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3271{
c4abb7c9 3272 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3273
3274 return 0;
3275}
3276
f077825a
PB		 3277static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3278{
64d60670
PB		 3279 kvm_make_request(KVM_REQ_SMI, vcpu);
3280
f077825a
PB		 3281 return 0;
3282}
3283
b209749f
AK		 3284static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3285 struct kvm_tpr_access_ctl *tac)
3286{
3287 if (tac->flags)
3288 return -EINVAL;
3289 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3290 return 0;
3291}
3292
890ca9ae
HY		 3293static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3294 u64 mcg_cap)
3295{
3296 int r;
3297 unsigned bank_num = mcg_cap & 0xff, bank;
3298
3299 r = -EINVAL;
a9e38c3e 3300 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3301 goto out;
c45dcc71 3302 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3303 goto out;
3304 r = 0;
3305 vcpu->arch.mcg_cap = mcg_cap;
3306 /* Init IA32_MCG_CTL to all 1s */
3307 if (mcg_cap & MCG_CTL_P)
3308 vcpu->arch.mcg_ctl = ~(u64)0;
3309 /* Init IA32_MCi_CTL to all 1s */
3310 for (bank = 0; bank < bank_num; bank++)
3311 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3312
3313 if (kvm_x86_ops->setup_mce)
3314 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3315out:
3316 return r;
3317}
3318
3319static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3320 struct kvm_x86_mce *mce)
3321{
3322 u64 mcg_cap = vcpu->arch.mcg_cap;
3323 unsigned bank_num = mcg_cap & 0xff;
3324 u64 *banks = vcpu->arch.mce_banks;
3325
3326 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3327 return -EINVAL;
3328 /*
3329 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3330 * reporting is disabled
3331 */
3332 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3333 vcpu->arch.mcg_ctl != ~(u64)0)
3334 return 0;
3335 banks += 4 * mce->bank;
3336 /*
3337 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3338 * reporting is disabled for the bank
3339 */
3340 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3341 return 0;
3342 if (mce->status & MCI_STATUS_UC) {
3343 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3344 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3345 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3346 return 0;
3347 }
3348 if (banks[1] & MCI_STATUS_VAL)
3349 mce->status |= MCI_STATUS_OVER;
3350 banks[2] = mce->addr;
3351 banks[3] = mce->misc;
3352 vcpu->arch.mcg_status = mce->mcg_status;
3353 banks[1] = mce->status;
3354 kvm_queue_exception(vcpu, MC_VECTOR);
3355 } else if (!(banks[1] & MCI_STATUS_VAL)
3356 || !(banks[1] & MCI_STATUS_UC)) {
3357 if (banks[1] & MCI_STATUS_VAL)
3358 mce->status |= MCI_STATUS_OVER;
3359 banks[2] = mce->addr;
3360 banks[3] = mce->misc;
3361 banks[1] = mce->status;
3362 } else
3363 banks[1] |= MCI_STATUS_OVER;
3364 return 0;
3365}
3366
3cfc3092
JK		 3367static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3368 struct kvm_vcpu_events *events)
3369{
7460fb4a 3370 process_nmi(vcpu);
664f8e26
WL		 3371 /*
3372 * FIXME: pass injected and pending separately. This is only
3373 * needed for nested virtualization, whose state cannot be
3374 * migrated yet. For now we can combine them.
3375 */
03b82a30 3376 events->exception.injected =
664f8e26
WL		 3377 (vcpu->arch.exception.pending ||
3378 vcpu->arch.exception.injected) &&
03b82a30 3379 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3380 events->exception.nr = vcpu->arch.exception.nr;
3381 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3382 events->exception.pad = 0;
3cfc3092
JK		 3383 events->exception.error_code = vcpu->arch.exception.error_code;
3384
03b82a30 3385 events->interrupt.injected =
04140b41 3386 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3387 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3388 events->interrupt.soft = 0;
37ccdcbe 3389 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3390
3391 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3392 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3393 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3394 events->nmi.pad = 0;
3cfc3092 3395
66450a21 3396 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3397
f077825a
PB		 3398 events->smi.smm = is_smm(vcpu);
3399 events->smi.pending = vcpu->arch.smi_pending;
3400 events->smi.smm_inside_nmi =
3401 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3402 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3403
dab4b911 3404 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3405 | KVM_VCPUEVENT_VALID_SHADOW
3406 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3407 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3408}
3409
6ef4e07e
XG		 3410static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3411
3cfc3092
JK		 3412static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3413 struct kvm_vcpu_events *events)
3414{
dab4b911 3415 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3416 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3417 | KVM_VCPUEVENT_VALID_SHADOW
3418 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3419 return -EINVAL;
3420
78e546c8 3421 if (events->exception.injected &&
28d06353
JM		 3422 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3423 is_guest_mode(vcpu)))
78e546c8
PB		 3424 return -EINVAL;
3425
28bf2888
DH		 3426 /* INITs are latched while in SMM */
3427 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3428 (events->smi.smm || events->smi.pending) &&
3429 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3430 return -EINVAL;
3431
7460fb4a 3432 process_nmi(vcpu);
664f8e26 3433 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3434 vcpu->arch.exception.pending = events->exception.injected;
3435 vcpu->arch.exception.nr = events->exception.nr;
3436 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3437 vcpu->arch.exception.error_code = events->exception.error_code;
3438
04140b41 3439 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3440 vcpu->arch.interrupt.nr = events->interrupt.nr;
3441 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3442 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3443 kvm_x86_ops->set_interrupt_shadow(vcpu,
3444 events->interrupt.shadow);
3cfc3092
JK		 3445
3446 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3447 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3448 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3449 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3450
66450a21 3451 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3452 lapic_in_kernel(vcpu))
66450a21 3453 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3454
f077825a 3455 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3456 u32 hflags = vcpu->arch.hflags;
f077825a 3457 if (events->smi.smm)
6ef4e07e 3458 hflags |= HF_SMM_MASK;
f077825a 3459 else
6ef4e07e
XG		 3460 hflags &= ~HF_SMM_MASK;
3461 kvm_set_hflags(vcpu, hflags);
3462
f077825a 3463 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3464
3465 if (events->smi.smm) {
3466 if (events->smi.smm_inside_nmi)
3467 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3468 else
f4ef1910
WL		 3469 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3470 if (lapic_in_kernel(vcpu)) {
3471 if (events->smi.latched_init)
3472 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3473 else
3474 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3475 }
f077825a
PB		 3476 }
3477 }
3478
3842d135
AK		 3479 kvm_make_request(KVM_REQ_EVENT, vcpu);
3480
3cfc3092
JK		 3481 return 0;
3482}
3483
a1efbe77
JK		 3484static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3485 struct kvm_debugregs *dbgregs)
3486{
73aaf249
JK		 3487 unsigned long val;
3488
a1efbe77 3489 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3490 kvm_get_dr(vcpu, 6, &val);
73aaf249 3491 dbgregs->dr6 = val;
a1efbe77
JK		 3492 dbgregs->dr7 = vcpu->arch.dr7;
3493 dbgregs->flags = 0;
97e69aa6 3494 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3495}
3496
3497static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3498 struct kvm_debugregs *dbgregs)
3499{
3500 if (dbgregs->flags)
3501 return -EINVAL;
3502
d14bdb55
PB		 3503 if (dbgregs->dr6 & ~0xffffffffull)
3504 return -EINVAL;
3505 if (dbgregs->dr7 & ~0xffffffffull)
3506 return -EINVAL;
3507
a1efbe77 3508 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3509 kvm_update_dr0123(vcpu);
a1efbe77 3510 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3511 kvm_update_dr6(vcpu);
a1efbe77 3512 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3513 kvm_update_dr7(vcpu);
a1efbe77 3514
a1efbe77
JK		 3515 return 0;
3516}
3517
df1daba7
PB		 3518#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3519
3520static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3521{
c47ada30 3522 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3523 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3524 u64 valid;
3525
3526 /*
3527 * Copy legacy XSAVE area, to avoid complications with CPUID
3528 * leaves 0 and 1 in the loop below.
3529 */
3530 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3531
3532 /* Set XSTATE_BV */
00c87e9a 3533 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3534 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3535
3536 /*
3537 * Copy each region from the possibly compacted offset to the
3538 * non-compacted offset.
3539 */
d91cab78 3540 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3541 while (valid) {
3542 u64 feature = valid & -valid;
3543 int index = fls64(feature) - 1;
3544 void *src = get_xsave_addr(xsave, feature);
3545
3546 if (src) {
3547 u32 size, offset, ecx, edx;
3548 cpuid_count(XSTATE_CPUID, index,
3549 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3550 if (feature == XFEATURE_MASK_PKRU)
3551 memcpy(dest + offset, &vcpu->arch.pkru,
3552 sizeof(vcpu->arch.pkru));
3553 else
3554 memcpy(dest + offset, src, size);
3555
df1daba7
PB		 3556 }
3557
3558 valid -= feature;
3559 }
3560}
3561
3562static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3563{
c47ada30 3564 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3565 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3566 u64 valid;
3567
3568 /*
3569 * Copy legacy XSAVE area, to avoid complications with CPUID
3570 * leaves 0 and 1 in the loop below.
3571 */
3572 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3573
3574 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3575 xsave->header.xfeatures = xstate_bv;
782511b0 3576 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3577 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3578
3579 /*
3580 * Copy each region from the non-compacted offset to the
3581 * possibly compacted offset.
3582 */
d91cab78 3583 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3584 while (valid) {
3585 u64 feature = valid & -valid;
3586 int index = fls64(feature) - 1;
3587 void *dest = get_xsave_addr(xsave, feature);
3588
3589 if (dest) {
3590 u32 size, offset, ecx, edx;
3591 cpuid_count(XSTATE_CPUID, index,
3592 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3593 if (feature == XFEATURE_MASK_PKRU)
3594 memcpy(&vcpu->arch.pkru, src + offset,
3595 sizeof(vcpu->arch.pkru));
3596 else
3597 memcpy(dest, src + offset, size);
ee4100da 3598 }
df1daba7
PB		 3599
3600 valid -= feature;
3601 }
3602}
3603
2d5b5a66
SY		 3604static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3605 struct kvm_xsave *guest_xsave)
3606{
d366bf7e 3607 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3608 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3609 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3610 } else {
2d5b5a66 3611 memcpy(guest_xsave->region,
7366ed77 3612 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3613 sizeof(struct fxregs_state));
2d5b5a66 3614 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3615 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3616 }
3617}
3618
a575813b
WL		 3619#define XSAVE_MXCSR_OFFSET 24
3620
2d5b5a66
SY		 3621static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3622 struct kvm_xsave *guest_xsave)
3623{
3624 u64 xstate_bv =
3625 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3626 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3627
d366bf7e 3628 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3629 /*
3630 * Here we allow setting states that are not present in
3631 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3632 * with old userspace.
3633 */
a575813b
WL		 3634 if (xstate_bv & ~kvm_supported_xcr0() ||
3635 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3636 return -EINVAL;
df1daba7 3637 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3638 } else {
a575813b
WL		 3639 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3640 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3641 return -EINVAL;
7366ed77 3642 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3643 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3644 }
3645 return 0;
3646}
3647
3648static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3649 struct kvm_xcrs *guest_xcrs)
3650{
d366bf7e 3651 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3652 guest_xcrs->nr_xcrs = 0;
3653 return;
3654 }
3655
3656 guest_xcrs->nr_xcrs = 1;
3657 guest_xcrs->flags = 0;
3658 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3659 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3660}
3661
3662static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3663 struct kvm_xcrs *guest_xcrs)
3664{
3665 int i, r = 0;
3666
d366bf7e 3667 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3668 return -EINVAL;
3669
3670 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3671 return -EINVAL;
3672
3673 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3674 /* Only support XCR0 currently */
c67a04cb 3675 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3676 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3677 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3678 break;
3679 }
3680 if (r)
3681 r = -EINVAL;
3682 return r;
3683}
3684
1c0b28c2
EM		 3685/*
3686 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3687 * stopped by the hypervisor. This function will be called from the host only.
3688 * EINVAL is returned when the host attempts to set the flag for a guest that
3689 * does not support pv clocks.
3690 */
3691static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3692{
0b79459b 3693 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3694 return -EINVAL;
51d59c6b 3695 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3696 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3697 return 0;
3698}
3699
5c919412
AS		 3700static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3701 struct kvm_enable_cap *cap)
3702{
3703 if (cap->flags)
3704 return -EINVAL;
3705
3706 switch (cap->cap) {
efc479e6
RK		 3707 case KVM_CAP_HYPERV_SYNIC2:
3708 if (cap->args[0])
3709 return -EINVAL;
5c919412 3710 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3711 if (!irqchip_in_kernel(vcpu->kvm))
3712 return -EINVAL;
efc479e6
RK		 3713 return kvm_hv_activate_synic(vcpu, cap->cap ==
3714 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3715 default:
3716 return -EINVAL;
3717 }
3718}
3719
313a3dc7
CO		 3720long kvm_arch_vcpu_ioctl(struct file *filp,
3721 unsigned int ioctl, unsigned long arg)
3722{
3723 struct kvm_vcpu *vcpu = filp->private_data;
3724 void __user *argp = (void __user *)arg;
3725 int r;
d1ac91d8
AK		 3726 union {
3727 struct kvm_lapic_state *lapic;
3728 struct kvm_xsave *xsave;
3729 struct kvm_xcrs *xcrs;
3730 void *buffer;
3731 } u;
3732
9b062471
CD		 3733 vcpu_load(vcpu);
3734
d1ac91d8 3735 u.buffer = NULL;
313a3dc7
CO		 3736 switch (ioctl) {
3737 case KVM_GET_LAPIC: {
2204ae3c 3738 r = -EINVAL;
bce87cce 3739 if (!lapic_in_kernel(vcpu))
2204ae3c 3740 goto out;
d1ac91d8 3741 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3742
b772ff36 3743 r = -ENOMEM;
d1ac91d8 3744 if (!u.lapic)
b772ff36 3745 goto out;
d1ac91d8 3746 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3747 if (r)
3748 goto out;
3749 r = -EFAULT;
d1ac91d8 3750 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3751 goto out;
3752 r = 0;
3753 break;
3754 }
3755 case KVM_SET_LAPIC: {
2204ae3c 3756 r = -EINVAL;
bce87cce 3757 if (!lapic_in_kernel(vcpu))
2204ae3c 3758 goto out;
ff5c2c03 3759 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3760 if (IS_ERR(u.lapic)) {
3761 r = PTR_ERR(u.lapic);
3762 goto out_nofree;
3763 }
ff5c2c03 3764
d1ac91d8 3765 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3766 break;
3767 }
f77bc6a4
ZX		 3768 case KVM_INTERRUPT: {
3769 struct kvm_interrupt irq;
3770
3771 r = -EFAULT;
3772 if (copy_from_user(&irq, argp, sizeof irq))
3773 goto out;
3774 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3775 break;
3776 }
c4abb7c9
JK		 3777 case KVM_NMI: {
3778 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3779 break;
3780 }
f077825a
PB		 3781 case KVM_SMI: {
3782 r = kvm_vcpu_ioctl_smi(vcpu);
3783 break;
3784 }
313a3dc7
CO		 3785 case KVM_SET_CPUID: {
3786 struct kvm_cpuid __user *cpuid_arg = argp;
3787 struct kvm_cpuid cpuid;
3788
3789 r = -EFAULT;
3790 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3791 goto out;
3792 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3793 break;
3794 }
07716717
DK		 3795 case KVM_SET_CPUID2: {
3796 struct kvm_cpuid2 __user *cpuid_arg = argp;
3797 struct kvm_cpuid2 cpuid;
3798
3799 r = -EFAULT;
3800 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3801 goto out;
3802 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3803 cpuid_arg->entries);
07716717
DK		 3804 break;
3805 }
3806 case KVM_GET_CPUID2: {
3807 struct kvm_cpuid2 __user *cpuid_arg = argp;
3808 struct kvm_cpuid2 cpuid;
3809
3810 r = -EFAULT;
3811 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3812 goto out;
3813 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3814 cpuid_arg->entries);
07716717
DK		 3815 if (r)
3816 goto out;
3817 r = -EFAULT;
3818 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3819 goto out;
3820 r = 0;
3821 break;
3822 }
801e459a
TL		 3823 case KVM_GET_MSRS: {
3824 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3825 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3826 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3827 break;
801e459a
TL		 3828 }
3829 case KVM_SET_MSRS: {
3830 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3831 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3832 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3833 break;
801e459a 3834 }
b209749f
AK		 3835 case KVM_TPR_ACCESS_REPORTING: {
3836 struct kvm_tpr_access_ctl tac;
3837
3838 r = -EFAULT;
3839 if (copy_from_user(&tac, argp, sizeof tac))
3840 goto out;
3841 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3842 if (r)
3843 goto out;
3844 r = -EFAULT;
3845 if (copy_to_user(argp, &tac, sizeof tac))
3846 goto out;
3847 r = 0;
3848 break;
3849 };
b93463aa
AK		 3850 case KVM_SET_VAPIC_ADDR: {
3851 struct kvm_vapic_addr va;
7301d6ab 3852 int idx;
b93463aa
AK		 3853
3854 r = -EINVAL;
35754c98 3855 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3856 goto out;
3857 r = -EFAULT;
3858 if (copy_from_user(&va, argp, sizeof va))
3859 goto out;
7301d6ab 3860 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3861 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3862 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3863 break;
3864 }
890ca9ae
HY		 3865 case KVM_X86_SETUP_MCE: {
3866 u64 mcg_cap;
3867
3868 r = -EFAULT;
3869 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3870 goto out;
3871 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3872 break;
3873 }
3874 case KVM_X86_SET_MCE: {
3875 struct kvm_x86_mce mce;
3876
3877 r = -EFAULT;
3878 if (copy_from_user(&mce, argp, sizeof mce))
3879 goto out;
3880 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3881 break;
3882 }
3cfc3092
JK		 3883 case KVM_GET_VCPU_EVENTS: {
3884 struct kvm_vcpu_events events;
3885
3886 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3887
3888 r = -EFAULT;
3889 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3890 break;
3891 r = 0;
3892 break;
3893 }
3894 case KVM_SET_VCPU_EVENTS: {
3895 struct kvm_vcpu_events events;
3896
3897 r = -EFAULT;
3898 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3899 break;
3900
3901 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3902 break;
3903 }
a1efbe77
JK		 3904 case KVM_GET_DEBUGREGS: {
3905 struct kvm_debugregs dbgregs;
3906
3907 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3908
3909 r = -EFAULT;
3910 if (copy_to_user(argp, &dbgregs,
3911 sizeof(struct kvm_debugregs)))
3912 break;
3913 r = 0;
3914 break;
3915 }
3916 case KVM_SET_DEBUGREGS: {
3917 struct kvm_debugregs dbgregs;
3918
3919 r = -EFAULT;
3920 if (copy_from_user(&dbgregs, argp,
3921 sizeof(struct kvm_debugregs)))
3922 break;
3923
3924 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3925 break;
3926 }
2d5b5a66 3927 case KVM_GET_XSAVE: {
d1ac91d8 3928 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3929 r = -ENOMEM;
d1ac91d8 3930 if (!u.xsave)
2d5b5a66
SY		 3931 break;
3932
d1ac91d8 3933 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3934
3935 r = -EFAULT;
d1ac91d8 3936 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3937 break;
3938 r = 0;
3939 break;
3940 }
3941 case KVM_SET_XSAVE: {
ff5c2c03 3942 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3943 if (IS_ERR(u.xsave)) {
3944 r = PTR_ERR(u.xsave);
3945 goto out_nofree;
3946 }
2d5b5a66 3947
d1ac91d8 3948 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3949 break;
3950 }
3951 case KVM_GET_XCRS: {
d1ac91d8 3952 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3953 r = -ENOMEM;
d1ac91d8 3954 if (!u.xcrs)
2d5b5a66
SY		 3955 break;
3956
d1ac91d8 3957 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3958
3959 r = -EFAULT;
d1ac91d8 3960 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3961 sizeof(struct kvm_xcrs)))
3962 break;
3963 r = 0;
3964 break;
3965 }
3966 case KVM_SET_XCRS: {
ff5c2c03 3967 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3968 if (IS_ERR(u.xcrs)) {
3969 r = PTR_ERR(u.xcrs);
3970 goto out_nofree;
3971 }
2d5b5a66 3972
d1ac91d8 3973 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3974 break;
3975 }
92a1f12d
JR		 3976 case KVM_SET_TSC_KHZ: {
3977 u32 user_tsc_khz;
3978
3979 r = -EINVAL;
92a1f12d
JR		 3980 user_tsc_khz = (u32)arg;
3981
3982 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3983 goto out;
3984
cc578287
ZA		 3985 if (user_tsc_khz == 0)
3986 user_tsc_khz = tsc_khz;
3987
381d585c
HZ		 3988 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3989 r = 0;
92a1f12d 3990
92a1f12d
JR		 3991 goto out;
3992 }
3993 case KVM_GET_TSC_KHZ: {
cc578287 3994 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3995 goto out;
3996 }
1c0b28c2
EM		 3997 case KVM_KVMCLOCK_CTRL: {
3998 r = kvm_set_guest_paused(vcpu);
3999 goto out;
4000 }
5c919412
AS		 4001 case KVM_ENABLE_CAP: {
4002 struct kvm_enable_cap cap;
4003
4004 r = -EFAULT;
4005 if (copy_from_user(&cap, argp, sizeof(cap)))
4006 goto out;
4007 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4008 break;
4009 }
8fcc4b59
JM		 4010 case KVM_GET_NESTED_STATE: {
4011 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4012 u32 user_data_size;
4013
4014 r = -EINVAL;
4015 if (!kvm_x86_ops->get_nested_state)
4016 break;
4017
4018 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4019 r = -EFAULT;
8fcc4b59 4020 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4021 break;
8fcc4b59
JM		 4022
4023 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4024 user_data_size);
4025 if (r < 0)
26b471c7 4026 break;
8fcc4b59
JM		 4027
4028 if (r > user_data_size) {
4029 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4030 r = -EFAULT;
4031 else
4032 r = -E2BIG;
4033 break;
8fcc4b59 4034 }
26b471c7 4035
8fcc4b59
JM		 4036 r = 0;
4037 break;
4038 }
4039 case KVM_SET_NESTED_STATE: {
4040 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4041 struct kvm_nested_state kvm_state;
4042
4043 r = -EINVAL;
4044 if (!kvm_x86_ops->set_nested_state)
4045 break;
4046
26b471c7 4047 r = -EFAULT;
8fcc4b59 4048 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4049 break;
8fcc4b59 4050
26b471c7 4051 r = -EINVAL;
8fcc4b59 4052 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4053 break;
8fcc4b59
JM		 4054
4055 if (kvm_state.flags &
4056 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4057 break;
8fcc4b59
JM		 4058
4059 /* nested_run_pending implies guest_mode. */
4060 if (kvm_state.flags == KVM_STATE_NESTED_RUN_PENDING)
26b471c7 4061 break;
8fcc4b59
JM		 4062
4063 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4064 break;
4065 }
313a3dc7
CO		 4066 default:
4067 r = -EINVAL;
4068 }
4069out:
d1ac91d8 4070 kfree(u.buffer);
9b062471
CD		 4071out_nofree:
4072 vcpu_put(vcpu);
313a3dc7
CO		 4073 return r;
4074}
4075
1499fa80 4076vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4077{
4078 return VM_FAULT_SIGBUS;
4079}
4080
1fe779f8
CO		 4081static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4082{
4083 int ret;
4084
4085 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4086 return -EINVAL;
1fe779f8
CO		 4087 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4088 return ret;
4089}
4090
b927a3ce
SY		 4091static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4092 u64 ident_addr)
4093{
2ac52ab8 4094 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4095}
4096
1fe779f8
CO		 4097static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4098 u32 kvm_nr_mmu_pages)
4099{
4100 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4101 return -EINVAL;
4102
79fac95e 4103 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4104
4105 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4106 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4107
79fac95e 4108 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4109 return 0;
4110}
4111
4112static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4113{
39de71ec 4114 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4115}
4116
1fe779f8
CO		 4117static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4118{
90bca052 4119 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4120 int r;
4121
4122 r = 0;
4123 switch (chip->chip_id) {
4124 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4125 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4126 sizeof(struct kvm_pic_state));
4127 break;
4128 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4129 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4130 sizeof(struct kvm_pic_state));
4131 break;
4132 case KVM_IRQCHIP_IOAPIC:
33392b49 4133 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4134 break;
4135 default:
4136 r = -EINVAL;
4137 break;
4138 }
4139 return r;
4140}
4141
4142static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4143{
90bca052 4144 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4145 int r;
4146
4147 r = 0;
4148 switch (chip->chip_id) {
4149 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4150 spin_lock(&pic->lock);
4151 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4152 sizeof(struct kvm_pic_state));
90bca052 4153 spin_unlock(&pic->lock);
1fe779f8
CO		 4154 break;
4155 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4156 spin_lock(&pic->lock);
4157 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4158 sizeof(struct kvm_pic_state));
90bca052 4159 spin_unlock(&pic->lock);
1fe779f8
CO		 4160 break;
4161 case KVM_IRQCHIP_IOAPIC:
33392b49 4162 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4163 break;
4164 default:
4165 r = -EINVAL;
4166 break;
4167 }
90bca052 4168 kvm_pic_update_irq(pic);
1fe779f8
CO		 4169 return r;
4170}
4171
e0f63cb9
SY		 4172static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4173{
34f3941c
RK		 4174 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4175
4176 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4177
4178 mutex_lock(&kps->lock);
4179 memcpy(ps, &kps->channels, sizeof(*ps));
4180 mutex_unlock(&kps->lock);
2da29bcc 4181 return 0;
e0f63cb9
SY		 4182}
4183
4184static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4185{
0185604c 4186 int i;
09edea72
RK		 4187 struct kvm_pit *pit = kvm->arch.vpit;
4188
4189 mutex_lock(&pit->pit_state.lock);
34f3941c 4190 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4191 for (i = 0; i < 3; i++)
09edea72
RK		 4192 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4193 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4194 return 0;
e9f42757
BK		 4195}
4196
4197static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4198{
e9f42757
BK		 4199 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4200 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4201 sizeof(ps->channels));
4202 ps->flags = kvm->arch.vpit->pit_state.flags;
4203 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4204 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4205 return 0;
e9f42757
BK		 4206}
4207
4208static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4209{
2da29bcc 4210 int start = 0;
0185604c 4211 int i;
e9f42757 4212 u32 prev_legacy, cur_legacy;
09edea72
RK		 4213 struct kvm_pit *pit = kvm->arch.vpit;
4214
4215 mutex_lock(&pit->pit_state.lock);
4216 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4217 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4218 if (!prev_legacy && cur_legacy)
4219 start = 1;
09edea72
RK		 4220 memcpy(&pit->pit_state.channels, &ps->channels,
4221 sizeof(pit->pit_state.channels));
4222 pit->pit_state.flags = ps->flags;
0185604c 4223 for (i = 0; i < 3; i++)
09edea72 4224 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4225 start && i == 0);
09edea72 4226 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4227 return 0;
e0f63cb9
SY		 4228}
4229
52d939a0
MT		 4230static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4231 struct kvm_reinject_control *control)
4232{
71474e2f
RK		 4233 struct kvm_pit *pit = kvm->arch.vpit;
4234
4235 if (!pit)
52d939a0 4236 return -ENXIO;
b39c90b6 4237
71474e2f
RK		 4238 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4239 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4240 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4241 */
4242 mutex_lock(&pit->pit_state.lock);
4243 kvm_pit_set_reinject(pit, control->pit_reinject);
4244 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4245
52d939a0
MT		 4246 return 0;
4247}
4248
95d4c16c 4249/**
60c34612
TY		 4250 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4251 * @kvm: kvm instance
4252 * @log: slot id and address to which we copy the log
95d4c16c 4253 *
e108ff2f
PB		 4254 * Steps 1-4 below provide general overview of dirty page logging. See
4255 * kvm_get_dirty_log_protect() function description for additional details.
4256 *
4257 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4258 * always flush the TLB (step 4) even if previous step failed and the dirty
4259 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4260 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4261 * writes will be marked dirty for next log read.
95d4c16c 4262 *
60c34612
TY		 4263 * 1. Take a snapshot of the bit and clear it if needed.
4264 * 2. Write protect the corresponding page.
e108ff2f
PB		 4265 * 3. Copy the snapshot to the userspace.
4266 * 4. Flush TLB's if needed.
5bb064dc 4267 */
60c34612 4268int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4269{
60c34612 4270 bool is_dirty = false;
e108ff2f 4271 int r;
5bb064dc 4272
79fac95e 4273 mutex_lock(&kvm->slots_lock);
5bb064dc 4274
88178fd4
KH		 4275 /*
4276 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4277 */
4278 if (kvm_x86_ops->flush_log_dirty)
4279 kvm_x86_ops->flush_log_dirty(kvm);
4280
e108ff2f 4281 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4282
4283 /*
4284 * All the TLBs can be flushed out of mmu lock, see the comments in
4285 * kvm_mmu_slot_remove_write_access().
4286 */
e108ff2f 4287 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4288 if (is_dirty)
4289 kvm_flush_remote_tlbs(kvm);
4290
79fac95e 4291 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4292 return r;
4293}
4294
aa2fbe6d
YZ		 4295int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4296 bool line_status)
23d43cf9
CD		 4297{
4298 if (!irqchip_in_kernel(kvm))
4299 return -ENXIO;
4300
4301 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4302 irq_event->irq, irq_event->level,
4303 line_status);
23d43cf9
CD		 4304 return 0;
4305}
4306
90de4a18
NA		 4307static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4308 struct kvm_enable_cap *cap)
4309{
4310 int r;
4311
4312 if (cap->flags)
4313 return -EINVAL;
4314
4315 switch (cap->cap) {
4316 case KVM_CAP_DISABLE_QUIRKS:
4317 kvm->arch.disabled_quirks = cap->args[0];
4318 r = 0;
4319 break;
49df6397
SR		 4320 case KVM_CAP_SPLIT_IRQCHIP: {
4321 mutex_lock(&kvm->lock);
b053b2ae
SR		 4322 r = -EINVAL;
4323 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4324 goto split_irqchip_unlock;
49df6397
SR		 4325 r = -EEXIST;
4326 if (irqchip_in_kernel(kvm))
4327 goto split_irqchip_unlock;
557abc40 4328 if (kvm->created_vcpus)
49df6397
SR		 4329 goto split_irqchip_unlock;
4330 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4331 if (r)
49df6397
SR		 4332 goto split_irqchip_unlock;
4333 /* Pairs with irqchip_in_kernel. */
4334 smp_wmb();
49776faf 4335 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4336 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4337 r = 0;
4338split_irqchip_unlock:
4339 mutex_unlock(&kvm->lock);
4340 break;
4341 }
37131313
RK		 4342 case KVM_CAP_X2APIC_API:
4343 r = -EINVAL;
4344 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4345 break;
4346
4347 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4348 kvm->arch.x2apic_format = true;
c519265f
RK		 4349 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4350 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4351
4352 r = 0;
4353 break;
4d5422ce
WL		 4354 case KVM_CAP_X86_DISABLE_EXITS:
4355 r = -EINVAL;
4356 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4357 break;
4358
4359 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4360 kvm_can_mwait_in_guest())
4361 kvm->arch.mwait_in_guest = true;
766d3571 4362 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4363 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4364 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4365 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4366 r = 0;
4367 break;
6fbbde9a
DS		 4368 case KVM_CAP_MSR_PLATFORM_INFO:
4369 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4370 r = 0;
4371 break;
90de4a18
NA		 4372 default:
4373 r = -EINVAL;
4374 break;
4375 }
4376 return r;
4377}
4378
1fe779f8
CO		 4379long kvm_arch_vm_ioctl(struct file *filp,
4380 unsigned int ioctl, unsigned long arg)
4381{
4382 struct kvm *kvm = filp->private_data;
4383 void __user *argp = (void __user *)arg;
367e1319 4384 int r = -ENOTTY;
f0d66275
DH		 4385 /*
4386 * This union makes it completely explicit to gcc-3.x
4387 * that these two variables' stack usage should be
4388 * combined, not added together.
4389 */
4390 union {
4391 struct kvm_pit_state ps;
e9f42757 4392 struct kvm_pit_state2 ps2;
c5ff41ce 4393 struct kvm_pit_config pit_config;
f0d66275 4394 } u;
1fe779f8
CO		 4395
4396 switch (ioctl) {
4397 case KVM_SET_TSS_ADDR:
4398 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4399 break;
b927a3ce
SY		 4400 case KVM_SET_IDENTITY_MAP_ADDR: {
4401 u64 ident_addr;
4402
1af1ac91
DH		 4403 mutex_lock(&kvm->lock);
4404 r = -EINVAL;
4405 if (kvm->created_vcpus)
4406 goto set_identity_unlock;
b927a3ce
SY		 4407 r = -EFAULT;
4408 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4409 goto set_identity_unlock;
b927a3ce 4410 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4411set_identity_unlock:
4412 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4413 break;
4414 }
1fe779f8
CO		 4415 case KVM_SET_NR_MMU_PAGES:
4416 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4417 break;
4418 case KVM_GET_NR_MMU_PAGES:
4419 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4420 break;
3ddea128 4421 case KVM_CREATE_IRQCHIP: {
3ddea128 4422 mutex_lock(&kvm->lock);
09941366 4423
3ddea128 4424 r = -EEXIST;
35e6eaa3 4425 if (irqchip_in_kernel(kvm))
3ddea128 4426 goto create_irqchip_unlock;
09941366 4427
3e515705 4428 r = -EINVAL;
557abc40 4429 if (kvm->created_vcpus)
3e515705 4430 goto create_irqchip_unlock;
09941366
RK		 4431
4432 r = kvm_pic_init(kvm);
4433 if (r)
3ddea128 4434 goto create_irqchip_unlock;
09941366
RK		 4435
4436 r = kvm_ioapic_init(kvm);
4437 if (r) {
09941366 4438 kvm_pic_destroy(kvm);
3ddea128 4439 goto create_irqchip_unlock;
09941366
RK		 4440 }
4441
399ec807
AK		 4442 r = kvm_setup_default_irq_routing(kvm);
4443 if (r) {
72bb2fcd 4444 kvm_ioapic_destroy(kvm);
09941366 4445 kvm_pic_destroy(kvm);
71ba994c 4446 goto create_irqchip_unlock;
399ec807 4447 }
49776faf 4448 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4449 smp_wmb();
49776faf 4450 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4451 create_irqchip_unlock:
4452 mutex_unlock(&kvm->lock);
1fe779f8 4453 break;
3ddea128 4454 }
7837699f 4455 case KVM_CREATE_PIT:
c5ff41ce
JK		 4456 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4457 goto create_pit;
4458 case KVM_CREATE_PIT2:
4459 r = -EFAULT;
4460 if (copy_from_user(&u.pit_config, argp,
4461 sizeof(struct kvm_pit_config)))
4462 goto out;
4463 create_pit:
250715a6 4464 mutex_lock(&kvm->lock);
269e05e4
AK		 4465 r = -EEXIST;
4466 if (kvm->arch.vpit)
4467 goto create_pit_unlock;
7837699f 4468 r = -ENOMEM;
c5ff41ce 4469 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4470 if (kvm->arch.vpit)
4471 r = 0;
269e05e4 4472 create_pit_unlock:
250715a6 4473 mutex_unlock(&kvm->lock);
7837699f 4474 break;
1fe779f8
CO		 4475 case KVM_GET_IRQCHIP: {
4476 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4477 struct kvm_irqchip *chip;
1fe779f8 4478
ff5c2c03
SL		 4479 chip = memdup_user(argp, sizeof(*chip));
4480 if (IS_ERR(chip)) {
4481 r = PTR_ERR(chip);
1fe779f8 4482 goto out;
ff5c2c03
SL		 4483 }
4484
1fe779f8 4485 r = -ENXIO;
826da321 4486 if (!irqchip_kernel(kvm))
f0d66275
DH		 4487 goto get_irqchip_out;
4488 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4489 if (r)
f0d66275 4490 goto get_irqchip_out;
1fe779f8 4491 r = -EFAULT;
f0d66275
DH		 4492 if (copy_to_user(argp, chip, sizeof *chip))
4493 goto get_irqchip_out;
1fe779f8 4494 r = 0;
f0d66275
DH		 4495 get_irqchip_out:
4496 kfree(chip);
1fe779f8
CO		 4497 break;
4498 }
4499 case KVM_SET_IRQCHIP: {
4500 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4501 struct kvm_irqchip *chip;
1fe779f8 4502
ff5c2c03
SL		 4503 chip = memdup_user(argp, sizeof(*chip));
4504 if (IS_ERR(chip)) {
4505 r = PTR_ERR(chip);
1fe779f8 4506 goto out;
ff5c2c03
SL		 4507 }
4508
1fe779f8 4509 r = -ENXIO;
826da321 4510 if (!irqchip_kernel(kvm))
f0d66275
DH		 4511 goto set_irqchip_out;
4512 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4513 if (r)
f0d66275 4514 goto set_irqchip_out;
1fe779f8 4515 r = 0;
f0d66275
DH		 4516 set_irqchip_out:
4517 kfree(chip);
1fe779f8
CO		 4518 break;
4519 }
e0f63cb9 4520 case KVM_GET_PIT: {
e0f63cb9 4521 r = -EFAULT;
f0d66275 4522 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4523 goto out;
4524 r = -ENXIO;
4525 if (!kvm->arch.vpit)
4526 goto out;
f0d66275 4527 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4528 if (r)
4529 goto out;
4530 r = -EFAULT;
f0d66275 4531 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4532 goto out;
4533 r = 0;
4534 break;
4535 }
4536 case KVM_SET_PIT: {
e0f63cb9 4537 r = -EFAULT;
f0d66275 4538 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4539 goto out;
4540 r = -ENXIO;
4541 if (!kvm->arch.vpit)
4542 goto out;
f0d66275 4543 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4544 break;
4545 }
e9f42757
BK		 4546 case KVM_GET_PIT2: {
4547 r = -ENXIO;
4548 if (!kvm->arch.vpit)
4549 goto out;
4550 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4551 if (r)
4552 goto out;
4553 r = -EFAULT;
4554 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4555 goto out;
4556 r = 0;
4557 break;
4558 }
4559 case KVM_SET_PIT2: {
4560 r = -EFAULT;
4561 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4562 goto out;
4563 r = -ENXIO;
4564 if (!kvm->arch.vpit)
4565 goto out;
4566 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4567 break;
4568 }
52d939a0
MT		 4569 case KVM_REINJECT_CONTROL: {
4570 struct kvm_reinject_control control;
4571 r = -EFAULT;
4572 if (copy_from_user(&control, argp, sizeof(control)))
4573 goto out;
4574 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4575 break;
4576 }
d71ba788
PB		 4577 case KVM_SET_BOOT_CPU_ID:
4578 r = 0;
4579 mutex_lock(&kvm->lock);
557abc40 4580 if (kvm->created_vcpus)
d71ba788
PB		 4581 r = -EBUSY;
4582 else
4583 kvm->arch.bsp_vcpu_id = arg;
4584 mutex_unlock(&kvm->lock);
4585 break;
ffde22ac 4586 case KVM_XEN_HVM_CONFIG: {
51776043 4587 struct kvm_xen_hvm_config xhc;
ffde22ac 4588 r = -EFAULT;
51776043 4589 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4590 goto out;
4591 r = -EINVAL;
51776043 4592 if (xhc.flags)
ffde22ac 4593 goto out;
51776043 4594 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4595 r = 0;
4596 break;
4597 }
afbcf7ab 4598 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4599 struct kvm_clock_data user_ns;
4600 u64 now_ns;
afbcf7ab
GC		 4601
4602 r = -EFAULT;
4603 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4604 goto out;
4605
4606 r = -EINVAL;
4607 if (user_ns.flags)
4608 goto out;
4609
4610 r = 0;
0bc48bea
RK		 4611 /*
4612 * TODO: userspace has to take care of races with VCPU_RUN, so
4613 * kvm_gen_update_masterclock() can be cut down to locked
4614 * pvclock_update_vm_gtod_copy().
4615 */
4616 kvm_gen_update_masterclock(kvm);
e891a32e 4617 now_ns = get_kvmclock_ns(kvm);
108b249c 4618 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4619 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4620 break;
4621 }
4622 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4623 struct kvm_clock_data user_ns;
4624 u64 now_ns;
4625
e891a32e 4626 now_ns = get_kvmclock_ns(kvm);
108b249c 4627 user_ns.clock = now_ns;
e3fd9a93 4628 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4629 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4630
4631 r = -EFAULT;
4632 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4633 goto out;
4634 r = 0;
4635 break;
4636 }
90de4a18
NA		 4637 case KVM_ENABLE_CAP: {
4638 struct kvm_enable_cap cap;
afbcf7ab 4639
90de4a18
NA		 4640 r = -EFAULT;
4641 if (copy_from_user(&cap, argp, sizeof(cap)))
4642 goto out;
4643 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4644 break;
4645 }
5acc5c06
BS		 4646 case KVM_MEMORY_ENCRYPT_OP: {
4647 r = -ENOTTY;
4648 if (kvm_x86_ops->mem_enc_op)
4649 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4650 break;
4651 }
69eaedee
BS		 4652 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4653 struct kvm_enc_region region;
4654
4655 r = -EFAULT;
4656 if (copy_from_user(&region, argp, sizeof(region)))
4657 goto out;
4658
4659 r = -ENOTTY;
4660 if (kvm_x86_ops->mem_enc_reg_region)
4661 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4662 break;
4663 }
4664 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4665 struct kvm_enc_region region;
4666
4667 r = -EFAULT;
4668 if (copy_from_user(&region, argp, sizeof(region)))
4669 goto out;
4670
4671 r = -ENOTTY;
4672 if (kvm_x86_ops->mem_enc_unreg_region)
4673 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4674 break;
4675 }
faeb7833
RK		 4676 case KVM_HYPERV_EVENTFD: {
4677 struct kvm_hyperv_eventfd hvevfd;
4678
4679 r = -EFAULT;
4680 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4681 goto out;
4682 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4683 break;
4684 }
1fe779f8 4685 default:
ad6260da 4686 r = -ENOTTY;
1fe779f8
CO		 4687 }
4688out:
4689 return r;
4690}
4691
a16b043c 4692static void kvm_init_msr_list(void)
043405e1
CO		 4693{
4694 u32 dummy[2];
4695 unsigned i, j;
4696
62ef68bb 4697 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4698 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4699 continue;
93c4adc7
PB		 4700
4701 /*
4702 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4703 * to the guests in some cases.
93c4adc7
PB		 4704 */
4705 switch (msrs_to_save[i]) {
4706 case MSR_IA32_BNDCFGS:
503234b3 4707 if (!kvm_mpx_supported())
93c4adc7
PB		 4708 continue;
4709 break;
9dbe6cf9
PB		 4710 case MSR_TSC_AUX:
4711 if (!kvm_x86_ops->rdtscp_supported())
4712 continue;
4713 break;
93c4adc7
PB		 4714 default:
4715 break;
4716 }
4717
043405e1
CO		 4718 if (j < i)
4719 msrs_to_save[j] = msrs_to_save[i];
4720 j++;
4721 }
4722 num_msrs_to_save = j;
62ef68bb
PB		 4723
4724 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4725 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4726 continue;
62ef68bb
PB		 4727
4728 if (j < i)
4729 emulated_msrs[j] = emulated_msrs[i];
4730 j++;
4731 }
4732 num_emulated_msrs = j;
801e459a
TL		 4733
4734 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4735 struct kvm_msr_entry msr;
4736
4737 msr.index = msr_based_features[i];
66421c1e 4738 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4739 continue;
4740
4741 if (j < i)
4742 msr_based_features[j] = msr_based_features[i];
4743 j++;
4744 }
4745 num_msr_based_features = j;
043405e1
CO		 4746}
4747
bda9020e
MT		 4748static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4749 const void *v)
bbd9b64e 4750{
70252a10
AK		 4751 int handled = 0;
4752 int n;
4753
4754 do {
4755 n = min(len, 8);
bce87cce 4756 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4757 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4758 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4759 break;
4760 handled += n;
4761 addr += n;
4762 len -= n;
4763 v += n;
4764 } while (len);
bbd9b64e 4765
70252a10 4766 return handled;
bbd9b64e
CO		 4767}
4768
bda9020e 4769static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4770{
70252a10
AK		 4771 int handled = 0;
4772 int n;
4773
4774 do {
4775 n = min(len, 8);
bce87cce 4776 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4777 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4778 addr, n, v))
4779 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4780 break;
e39d200f 4781 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4782 handled += n;
4783 addr += n;
4784 len -= n;
4785 v += n;
4786 } while (len);
bbd9b64e 4787
70252a10 4788 return handled;
bbd9b64e
CO		 4789}
4790
2dafc6c2
GN		 4791static void kvm_set_segment(struct kvm_vcpu *vcpu,
4792 struct kvm_segment *var, int seg)
4793{
4794 kvm_x86_ops->set_segment(vcpu, var, seg);
4795}
4796
4797void kvm_get_segment(struct kvm_vcpu *vcpu,
4798 struct kvm_segment *var, int seg)
4799{
4800 kvm_x86_ops->get_segment(vcpu, var, seg);
4801}
4802
54987b7a
PB		 4803gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4804 struct x86_exception *exception)
02f59dc9
JR		 4805{
4806 gpa_t t_gpa;
02f59dc9
JR		 4807
4808 BUG_ON(!mmu_is_nested(vcpu));
4809
4810 /* NPT walks are always user-walks */
4811 access |= PFERR_USER_MASK;
44dd3ffa 4812 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4813
4814 return t_gpa;
4815}
4816
ab9ae313
AK		 4817gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4818 struct x86_exception *exception)
1871c602
GN		 4819{
4820 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4821 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4822}
4823
ab9ae313
AK		 4824 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4825 struct x86_exception *exception)
1871c602
GN		 4826{
4827 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4828 access |= PFERR_FETCH_MASK;
ab9ae313 4829 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4830}
4831
ab9ae313
AK		 4832gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4833 struct x86_exception *exception)
1871c602
GN		 4834{
4835 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4836 access |= PFERR_WRITE_MASK;
ab9ae313 4837 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4838}
4839
4840/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4841gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4842 struct x86_exception *exception)
1871c602 4843{
ab9ae313 4844 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4845}
4846
4847static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4848 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4849 struct x86_exception *exception)
bbd9b64e
CO		 4850{
4851 void *data = val;
10589a46 4852 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4853
4854 while (bytes) {
14dfe855 4855 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4856 exception);
bbd9b64e 4857 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4858 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4859 int ret;
4860
bcc55cba 4861 if (gpa == UNMAPPED_GVA)
ab9ae313 4862 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4863 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4864 offset, toread);
10589a46 4865 if (ret < 0) {
c3cd7ffa 4866 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4867 goto out;
4868 }
bbd9b64e 4869
77c2002e
IE		 4870 bytes -= toread;
4871 data += toread;
4872 addr += toread;
bbd9b64e 4873 }
10589a46 4874out:
10589a46 4875 return r;
bbd9b64e 4876}
77c2002e 4877
1871c602 4878/* used for instruction fetching */
0f65dd70
AK		 4879static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4880 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4881 struct x86_exception *exception)
1871c602 4882{
0f65dd70 4883 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4884 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4885 unsigned offset;
4886 int ret;
0f65dd70 4887
44583cba
PB		 4888 /* Inline kvm_read_guest_virt_helper for speed. */
4889 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4890 exception);
4891 if (unlikely(gpa == UNMAPPED_GVA))
4892 return X86EMUL_PROPAGATE_FAULT;
4893
4894 offset = addr & (PAGE_SIZE-1);
4895 if (WARN_ON(offset + bytes > PAGE_SIZE))
4896 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4897 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4898 offset, bytes);
44583cba
PB		 4899 if (unlikely(ret < 0))
4900 return X86EMUL_IO_NEEDED;
4901
4902 return X86EMUL_CONTINUE;
1871c602
GN		 4903}
4904
ce14e868 4905int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 4906 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4907 struct x86_exception *exception)
1871c602
GN		 4908{
4909 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4910
1871c602 4911 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4912 exception);
1871c602 4913}
064aea77 4914EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4915
ce14e868
PB		 4916static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4917 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 4918 struct x86_exception *exception, bool system)
1871c602 4919{
0f65dd70 4920 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4921 u32 access = 0;
4922
4923 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4924 access |= PFERR_USER_MASK;
4925
4926 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 4927}
4928
7a036a6f
RK		 4929static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4930 unsigned long addr, void *val, unsigned int bytes)
4931{
4932 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4933 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4934
4935 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4936}
4937
ce14e868
PB		 4938static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4939 struct kvm_vcpu *vcpu, u32 access,
4940 struct x86_exception *exception)
77c2002e
IE		 4941{
4942 void *data = val;
4943 int r = X86EMUL_CONTINUE;
4944
4945 while (bytes) {
14dfe855 4946 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 4947 access,
ab9ae313 4948 exception);
77c2002e
IE		 4949 unsigned offset = addr & (PAGE_SIZE-1);
4950 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4951 int ret;
4952
bcc55cba 4953 if (gpa == UNMAPPED_GVA)
ab9ae313 4954 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4955 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4956 if (ret < 0) {
c3cd7ffa 4957 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4958 goto out;
4959 }
4960
4961 bytes -= towrite;
4962 data += towrite;
4963 addr += towrite;
4964 }
4965out:
4966 return r;
4967}
ce14e868
PB		 4968
4969static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 4970 unsigned int bytes, struct x86_exception *exception,
4971 bool system)
ce14e868
PB		 4972{
4973 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4974 u32 access = PFERR_WRITE_MASK;
4975
4976 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4977 access |= PFERR_USER_MASK;
ce14e868
PB		 4978
4979 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 4980 access, exception);
ce14e868
PB		 4981}
4982
4983int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
4984 unsigned int bytes, struct x86_exception *exception)
4985{
c595ceee
PB		 4986 /* kvm_write_guest_virt_system can pull in tons of pages. */
4987 vcpu->arch.l1tf_flush_l1d = true;
4988
ce14e868
PB		 4989 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4990 PFERR_WRITE_MASK, exception);
4991}
6a4d7550 4992EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4993
082d06ed
WL		 4994int handle_ud(struct kvm_vcpu *vcpu)
4995{
6c86eedc 4996 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 4997 enum emulation_result er;
6c86eedc
WL		 4998 char sig[5]; /* ud2; .ascii "kvm" */
4999 struct x86_exception e;
5000
5001 if (force_emulation_prefix &&
3c9fa24c
PB		 5002 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5003 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5004 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5005 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5006 emul_type = 0;
5007 }
082d06ed 5008
0ce97a2b 5009 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5010 if (er == EMULATE_USER_EXIT)
5011 return 0;
5012 if (er != EMULATE_DONE)
5013 kvm_queue_exception(vcpu, UD_VECTOR);
5014 return 1;
5015}
5016EXPORT_SYMBOL_GPL(handle_ud);
5017
0f89b207
TL		 5018static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5019 gpa_t gpa, bool write)
5020{
5021 /* For APIC access vmexit */
5022 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5023 return 1;
5024
5025 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5026 trace_vcpu_match_mmio(gva, gpa, write, true);
5027 return 1;
5028 }
5029
5030 return 0;
5031}
5032
af7cc7d1
XG		 5033static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5034 gpa_t *gpa, struct x86_exception *exception,
5035 bool write)
5036{
97d64b78
AK		 5037 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5038 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5039
be94f6b7
HH		 5040 /*
5041 * currently PKRU is only applied to ept enabled guest so
5042 * there is no pkey in EPT page table for L1 guest or EPT
5043 * shadow page table for L2 guest.
5044 */
97d64b78 5045 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5046 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5047 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5048 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5049 (gva & (PAGE_SIZE - 1));
4f022648 5050 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5051 return 1;
5052 }
5053
af7cc7d1
XG		 5054 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5055
5056 if (*gpa == UNMAPPED_GVA)
5057 return -1;
5058
0f89b207 5059 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5060}
5061
3200f405 5062int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5063 const void *val, int bytes)
bbd9b64e
CO		 5064{
5065 int ret;
5066
54bf36aa 5067 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5068 if (ret < 0)
bbd9b64e 5069 return 0;
0eb05bf2 5070 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5071 return 1;
5072}
5073
77d197b2
XG		 5074struct read_write_emulator_ops {
5075 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5076 int bytes);
5077 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5078 void *val, int bytes);
5079 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5080 int bytes, void *val);
5081 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5082 void *val, int bytes);
5083 bool write;
5084};
5085
5086static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5087{
5088 if (vcpu->mmio_read_completed) {
77d197b2 5089 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5090 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5091 vcpu->mmio_read_completed = 0;
5092 return 1;
5093 }
5094
5095 return 0;
5096}
5097
5098static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5099 void *val, int bytes)
5100{
54bf36aa 5101 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5102}
5103
5104static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5105 void *val, int bytes)
5106{
5107 return emulator_write_phys(vcpu, gpa, val, bytes);
5108}
5109
5110static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5111{
e39d200f 5112 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5113 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5114}
5115
5116static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5117 void *val, int bytes)
5118{
e39d200f 5119 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5120 return X86EMUL_IO_NEEDED;
5121}
5122
5123static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5124 void *val, int bytes)
5125{
f78146b0
AK		 5126 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5127
87da7e66 5128 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5129 return X86EMUL_CONTINUE;
5130}
5131
0fbe9b0b 5132static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5133 .read_write_prepare = read_prepare,
5134 .read_write_emulate = read_emulate,
5135 .read_write_mmio = vcpu_mmio_read,
5136 .read_write_exit_mmio = read_exit_mmio,
5137};
5138
0fbe9b0b 5139static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5140 .read_write_emulate = write_emulate,
5141 .read_write_mmio = write_mmio,
5142 .read_write_exit_mmio = write_exit_mmio,
5143 .write = true,
5144};
5145
22388a3c
XG		 5146static int emulator_read_write_onepage(unsigned long addr, void *val,
5147 unsigned int bytes,
5148 struct x86_exception *exception,
5149 struct kvm_vcpu *vcpu,
0fbe9b0b 5150 const struct read_write_emulator_ops *ops)
bbd9b64e 5151{
af7cc7d1
XG		 5152 gpa_t gpa;
5153 int handled, ret;
22388a3c 5154 bool write = ops->write;
f78146b0 5155 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5156 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5157
5158 /*
5159 * If the exit was due to a NPF we may already have a GPA.
5160 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5161 * Note, this cannot be used on string operations since string
5162 * operation using rep will only have the initial GPA from the NPF
5163 * occurred.
5164 */
5165 if (vcpu->arch.gpa_available &&
5166 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5167 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5168 gpa = vcpu->arch.gpa_val;
5169 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5170 } else {
5171 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5172 if (ret < 0)
5173 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5174 }
10589a46 5175
618232e2 5176 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5177 return X86EMUL_CONTINUE;
5178
bbd9b64e
CO		 5179 /*
5180 * Is this MMIO handled locally?
5181 */
22388a3c 5182 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5183 if (handled == bytes)
bbd9b64e 5184 return X86EMUL_CONTINUE;
bbd9b64e 5185
70252a10
AK		 5186 gpa += handled;
5187 bytes -= handled;
5188 val += handled;
5189
87da7e66
XG		 5190 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5191 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5192 frag->gpa = gpa;
5193 frag->data = val;
5194 frag->len = bytes;
f78146b0 5195 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5196}
5197
52eb5a6d
XL		 5198static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5199 unsigned long addr,
22388a3c
XG		 5200 void *val, unsigned int bytes,
5201 struct x86_exception *exception,
0fbe9b0b 5202 const struct read_write_emulator_ops *ops)
bbd9b64e 5203{
0f65dd70 5204 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5205 gpa_t gpa;
5206 int rc;
5207
5208 if (ops->read_write_prepare &&
5209 ops->read_write_prepare(vcpu, val, bytes))
5210 return X86EMUL_CONTINUE;
5211
5212 vcpu->mmio_nr_fragments = 0;
0f65dd70 5213
bbd9b64e
CO		 5214 /* Crossing a page boundary? */
5215 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5216 int now;
bbd9b64e
CO		 5217
5218 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5219 rc = emulator_read_write_onepage(addr, val, now, exception,
5220 vcpu, ops);
5221
bbd9b64e
CO		 5222 if (rc != X86EMUL_CONTINUE)
5223 return rc;
5224 addr += now;
bac15531
NA		 5225 if (ctxt->mode != X86EMUL_MODE_PROT64)
5226 addr = (u32)addr;
bbd9b64e
CO		 5227 val += now;
5228 bytes -= now;
5229 }
22388a3c 5230
f78146b0
AK		 5231 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5232 vcpu, ops);
5233 if (rc != X86EMUL_CONTINUE)
5234 return rc;
5235
5236 if (!vcpu->mmio_nr_fragments)
5237 return rc;
5238
5239 gpa = vcpu->mmio_fragments[0].gpa;
5240
5241 vcpu->mmio_needed = 1;
5242 vcpu->mmio_cur_fragment = 0;
5243
87da7e66 5244 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5245 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5246 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5247 vcpu->run->mmio.phys_addr = gpa;
5248
5249 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5250}
5251
5252static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5253 unsigned long addr,
5254 void *val,
5255 unsigned int bytes,
5256 struct x86_exception *exception)
5257{
5258 return emulator_read_write(ctxt, addr, val, bytes,
5259 exception, &read_emultor);
5260}
5261
52eb5a6d 5262static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5263 unsigned long addr,
5264 const void *val,
5265 unsigned int bytes,
5266 struct x86_exception *exception)
5267{
5268 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5269 exception, &write_emultor);
bbd9b64e 5270}
bbd9b64e 5271
daea3e73
AK		 5272#define CMPXCHG_TYPE(t, ptr, old, new) \
5273 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5274
5275#ifdef CONFIG_X86_64
5276# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5277#else
5278# define CMPXCHG64(ptr, old, new) \
9749a6c0 5279 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5280#endif
5281
0f65dd70
AK		 5282static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5283 unsigned long addr,
bbd9b64e
CO		 5284 const void *old,
5285 const void *new,
5286 unsigned int bytes,
0f65dd70 5287 struct x86_exception *exception)
bbd9b64e 5288{
0f65dd70 5289 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5290 gpa_t gpa;
5291 struct page *page;
5292 char *kaddr;
5293 bool exchanged;
2bacc55c 5294
daea3e73
AK		 5295 /* guests cmpxchg8b have to be emulated atomically */
5296 if (bytes > 8 || (bytes & (bytes - 1)))
5297 goto emul_write;
10589a46 5298
daea3e73 5299 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5300
daea3e73
AK		 5301 if (gpa == UNMAPPED_GVA ||
5302 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5303 goto emul_write;
2bacc55c 5304
daea3e73
AK		 5305 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5306 goto emul_write;
72dc67a6 5307
54bf36aa 5308 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5309 if (is_error_page(page))
c19b8bd6 5310 goto emul_write;
72dc67a6 5311
8fd75e12 5312 kaddr = kmap_atomic(page);
daea3e73
AK		 5313 kaddr += offset_in_page(gpa);
5314 switch (bytes) {
5315 case 1:
5316 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5317 break;
5318 case 2:
5319 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5320 break;
5321 case 4:
5322 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5323 break;
5324 case 8:
5325 exchanged = CMPXCHG64(kaddr, old, new);
5326 break;
5327 default:
5328 BUG();
2bacc55c 5329 }
8fd75e12 5330 kunmap_atomic(kaddr);
daea3e73
AK		 5331 kvm_release_page_dirty(page);
5332
5333 if (!exchanged)
5334 return X86EMUL_CMPXCHG_FAILED;
5335
54bf36aa 5336 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5337 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5338
5339 return X86EMUL_CONTINUE;
4a5f48f6 5340
3200f405 5341emul_write:
daea3e73 5342 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5343
0f65dd70 5344 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5345}
5346
cf8f70bf
GN		 5347static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5348{
cbfc6c91 5349 int r = 0, i;
cf8f70bf 5350
cbfc6c91
WL		 5351 for (i = 0; i < vcpu->arch.pio.count; i++) {
5352 if (vcpu->arch.pio.in)
5353 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5354 vcpu->arch.pio.size, pd);
5355 else
5356 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5357 vcpu->arch.pio.port, vcpu->arch.pio.size,
5358 pd);
5359 if (r)
5360 break;
5361 pd += vcpu->arch.pio.size;
5362 }
cf8f70bf
GN		 5363 return r;
5364}
5365
6f6fbe98
XG		 5366static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5367 unsigned short port, void *val,
5368 unsigned int count, bool in)
cf8f70bf 5369{
cf8f70bf 5370 vcpu->arch.pio.port = port;
6f6fbe98 5371 vcpu->arch.pio.in = in;
7972995b 5372 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5373 vcpu->arch.pio.size = size;
5374
5375 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5376 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5377 return 1;
5378 }
5379
5380 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5381 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5382 vcpu->run->io.size = size;
5383 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5384 vcpu->run->io.count = count;
5385 vcpu->run->io.port = port;
5386
5387 return 0;
5388}
5389
6f6fbe98
XG		 5390static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5391 int size, unsigned short port, void *val,
5392 unsigned int count)
cf8f70bf 5393{
ca1d4a9e 5394 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5395 int ret;
ca1d4a9e 5396
6f6fbe98
XG		 5397 if (vcpu->arch.pio.count)
5398 goto data_avail;
cf8f70bf 5399
cbfc6c91
WL		 5400 memset(vcpu->arch.pio_data, 0, size * count);
5401
6f6fbe98
XG		 5402 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5403 if (ret) {
5404data_avail:
5405 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5406 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5407 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5408 return 1;
5409 }
5410
cf8f70bf
GN		 5411 return 0;
5412}
5413
6f6fbe98
XG		 5414static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5415 int size, unsigned short port,
5416 const void *val, unsigned int count)
5417{
5418 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5419
5420 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5421 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5422 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5423}
5424
bbd9b64e
CO		 5425static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5426{
5427 return kvm_x86_ops->get_segment_base(vcpu, seg);
5428}
5429
3cb16fe7 5430static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5431{
3cb16fe7 5432 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5433}
5434
ae6a2375 5435static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5436{
5437 if (!need_emulate_wbinvd(vcpu))
5438 return X86EMUL_CONTINUE;
5439
5440 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5441 int cpu = get_cpu();
5442
5443 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5444 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5445 wbinvd_ipi, NULL, 1);
2eec7343 5446 put_cpu();
f5f48ee1 5447 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5448 } else
5449 wbinvd();
f5f48ee1
SY		 5450 return X86EMUL_CONTINUE;
5451}
5cb56059
JS		 5452
5453int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5454{
6affcbed
KH		 5455 kvm_emulate_wbinvd_noskip(vcpu);
5456 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5457}
f5f48ee1
SY		 5458EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5459
5cb56059
JS		 5460
5461
bcaf5cc5
AK		 5462static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5463{
5cb56059 5464 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5465}
5466
52eb5a6d
XL		 5467static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5468 unsigned long *dest)
bbd9b64e 5469{
16f8a6f9 5470 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5471}
5472
52eb5a6d
XL		 5473static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5474 unsigned long value)
bbd9b64e 5475{
338dbc97 5476
717746e3 5477 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5478}
5479
52a46617 5480static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5481{
52a46617 5482 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5483}
5484
717746e3 5485static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5486{
717746e3 5487 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5488 unsigned long value;
5489
5490 switch (cr) {
5491 case 0:
5492 value = kvm_read_cr0(vcpu);
5493 break;
5494 case 2:
5495 value = vcpu->arch.cr2;
5496 break;
5497 case 3:
9f8fe504 5498 value = kvm_read_cr3(vcpu);
52a46617
GN		 5499 break;
5500 case 4:
5501 value = kvm_read_cr4(vcpu);
5502 break;
5503 case 8:
5504 value = kvm_get_cr8(vcpu);
5505 break;
5506 default:
a737f256 5507 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5508 return 0;
5509 }
5510
5511 return value;
5512}
5513
717746e3 5514static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5515{
717746e3 5516 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5517 int res = 0;
5518
52a46617
GN		 5519 switch (cr) {
5520 case 0:
49a9b07e 5521 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5522 break;
5523 case 2:
5524 vcpu->arch.cr2 = val;
5525 break;
5526 case 3:
2390218b 5527 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5528 break;
5529 case 4:
a83b29c6 5530 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5531 break;
5532 case 8:
eea1cff9 5533 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5534 break;
5535 default:
a737f256 5536 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5537 res = -1;
52a46617 5538 }
0f12244f
GN		 5539
5540 return res;
52a46617
GN		 5541}
5542
717746e3 5543static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5544{
717746e3 5545 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5546}
5547
4bff1e86 5548static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5549{
4bff1e86 5550 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5551}
5552
4bff1e86 5553static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5554{
4bff1e86 5555 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5556}
5557
1ac9d0cf
AK		 5558static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5559{
5560 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5561}
5562
5563static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5564{
5565 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5566}
5567
4bff1e86
AK		 5568static unsigned long emulator_get_cached_segment_base(
5569 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5570{
4bff1e86 5571 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5572}
5573
1aa36616
AK		 5574static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5575 struct desc_struct *desc, u32 *base3,
5576 int seg)
2dafc6c2
GN		 5577{
5578 struct kvm_segment var;
5579
4bff1e86 5580 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5581 *selector = var.selector;
2dafc6c2 5582
378a8b09
GN		 5583 if (var.unusable) {
5584 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5585 if (base3)
5586 *base3 = 0;
2dafc6c2 5587 return false;
378a8b09 5588 }
2dafc6c2
GN		 5589
5590 if (var.g)
5591 var.limit >>= 12;
5592 set_desc_limit(desc, var.limit);
5593 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5594#ifdef CONFIG_X86_64
5595 if (base3)
5596 *base3 = var.base >> 32;
5597#endif
2dafc6c2
GN		 5598 desc->type = var.type;
5599 desc->s = var.s;
5600 desc->dpl = var.dpl;
5601 desc->p = var.present;
5602 desc->avl = var.avl;
5603 desc->l = var.l;
5604 desc->d = var.db;
5605 desc->g = var.g;
5606
5607 return true;
5608}
5609
1aa36616
AK		 5610static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5611 struct desc_struct *desc, u32 base3,
5612 int seg)
2dafc6c2 5613{
4bff1e86 5614 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5615 struct kvm_segment var;
5616
1aa36616 5617 var.selector = selector;
2dafc6c2 5618 var.base = get_desc_base(desc);
5601d05b
GN		 5619#ifdef CONFIG_X86_64
5620 var.base |= ((u64)base3) << 32;
5621#endif
2dafc6c2
GN		 5622 var.limit = get_desc_limit(desc);
5623 if (desc->g)
5624 var.limit = (var.limit << 12) | 0xfff;
5625 var.type = desc->type;
2dafc6c2
GN		 5626 var.dpl = desc->dpl;
5627 var.db = desc->d;
5628 var.s = desc->s;
5629 var.l = desc->l;
5630 var.g = desc->g;
5631 var.avl = desc->avl;
5632 var.present = desc->p;
5633 var.unusable = !var.present;
5634 var.padding = 0;
5635
5636 kvm_set_segment(vcpu, &var, seg);
5637 return;
5638}
5639
717746e3
AK		 5640static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5641 u32 msr_index, u64 *pdata)
5642{
609e36d3
PB		 5643 struct msr_data msr;
5644 int r;
5645
5646 msr.index = msr_index;
5647 msr.host_initiated = false;
5648 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5649 if (r)
5650 return r;
5651
5652 *pdata = msr.data;
5653 return 0;
717746e3
AK		 5654}
5655
5656static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5657 u32 msr_index, u64 data)
5658{
8fe8ab46
WA		 5659 struct msr_data msr;
5660
5661 msr.data = data;
5662 msr.index = msr_index;
5663 msr.host_initiated = false;
5664 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5665}
5666
64d60670
PB		 5667static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5668{
5669 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5670
5671 return vcpu->arch.smbase;
5672}
5673
5674static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5675{
5676 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5677
5678 vcpu->arch.smbase = smbase;
5679}
5680
67f4d428
NA		 5681static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5682 u32 pmc)
5683{
c6702c9d 5684 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5685}
5686
222d21aa
AK		 5687static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5688 u32 pmc, u64 *pdata)
5689{
c6702c9d 5690 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5691}
5692
6c3287f7
AK		 5693static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5694{
5695 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5696}
5697
2953538e 5698static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5699 struct x86_instruction_info *info,
c4f035c6
AK		 5700 enum x86_intercept_stage stage)
5701{
2953538e 5702 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5703}
5704
e911eb3b
YZ		 5705static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5706 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5707{
e911eb3b 5708 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5709}
5710
dd856efa
AK		 5711static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5712{
5713 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5714}
5715
5716static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5717{
5718 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5719}
5720
801806d9
NA		 5721static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5722{
5723 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5724}
5725
6ed071f0
LP		 5726static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5727{
5728 return emul_to_vcpu(ctxt)->arch.hflags;
5729}
5730
5731static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5732{
5733 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5734}
5735
0234bf88
LP		 5736static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5737{
5738 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5739}
5740
0225fb50 5741static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5742 .read_gpr = emulator_read_gpr,
5743 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5744 .read_std = emulator_read_std,
5745 .write_std = emulator_write_std,
7a036a6f 5746 .read_phys = kvm_read_guest_phys_system,
1871c602 5747 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5748 .read_emulated = emulator_read_emulated,
5749 .write_emulated = emulator_write_emulated,
5750 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5751 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5752 .pio_in_emulated = emulator_pio_in_emulated,
5753 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5754 .get_segment = emulator_get_segment,
5755 .set_segment = emulator_set_segment,
5951c442 5756 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5757 .get_gdt = emulator_get_gdt,
160ce1f1 5758 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5759 .set_gdt = emulator_set_gdt,
5760 .set_idt = emulator_set_idt,
52a46617
GN		 5761 .get_cr = emulator_get_cr,
5762 .set_cr = emulator_set_cr,
9c537244 5763 .cpl = emulator_get_cpl,
35aa5375
GN		 5764 .get_dr = emulator_get_dr,
5765 .set_dr = emulator_set_dr,
64d60670
PB		 5766 .get_smbase = emulator_get_smbase,
5767 .set_smbase = emulator_set_smbase,
717746e3
AK		 5768 .set_msr = emulator_set_msr,
5769 .get_msr = emulator_get_msr,
67f4d428 5770 .check_pmc = emulator_check_pmc,
222d21aa 5771 .read_pmc = emulator_read_pmc,
6c3287f7 5772 .halt = emulator_halt,
bcaf5cc5 5773 .wbinvd = emulator_wbinvd,
d6aa1000 5774 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5775 .intercept = emulator_intercept,
bdb42f5a 5776 .get_cpuid = emulator_get_cpuid,
801806d9 5777 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5778 .get_hflags = emulator_get_hflags,
5779 .set_hflags = emulator_set_hflags,
0234bf88 5780 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5781};
5782
95cb2295
GN		 5783static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5784{
37ccdcbe 5785 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5786 /*
5787 * an sti; sti; sequence only disable interrupts for the first
5788 * instruction. So, if the last instruction, be it emulated or
5789 * not, left the system with the INT_STI flag enabled, it
5790 * means that the last instruction is an sti. We should not
5791 * leave the flag on in this case. The same goes for mov ss
5792 */
37ccdcbe
PB		 5793 if (int_shadow & mask)
5794 mask = 0;
6addfc42 5795 if (unlikely(int_shadow || mask)) {
95cb2295 5796 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5797 if (!mask)
5798 kvm_make_request(KVM_REQ_EVENT, vcpu);
5799 }
95cb2295
GN		 5800}
5801
ef54bcfe 5802static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5803{
5804 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5805 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5806 return kvm_propagate_fault(vcpu, &ctxt->exception);
5807
5808 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5809 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5810 ctxt->exception.error_code);
54b8486f 5811 else
da9cb575 5812 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5813 return false;
54b8486f
GN		 5814}
5815
8ec4722d
MG		 5816static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5817{
adf52235 5818 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5819 int cs_db, cs_l;
5820
8ec4722d
MG		 5821 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5822
adf52235 5823 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5824 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5825
adf52235
TY		 5826 ctxt->eip = kvm_rip_read(vcpu);
5827 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5828 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5829 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5830 cs_db ? X86EMUL_MODE_PROT32 :
5831 X86EMUL_MODE_PROT16;
a584539b 5832 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5833 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5834 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5835
dd856efa 5836 init_decode_cache(ctxt);
7ae441ea 5837 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5838}
5839
71f9833b 5840int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5841{
9d74191a 5842 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5843 int ret;
5844
5845 init_emulate_ctxt(vcpu);
5846
9dac77fa
AK		 5847 ctxt->op_bytes = 2;
5848 ctxt->ad_bytes = 2;
5849 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5850 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5851
5852 if (ret != X86EMUL_CONTINUE)
5853 return EMULATE_FAIL;
5854
9dac77fa 5855 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5856 kvm_rip_write(vcpu, ctxt->eip);
5857 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5858
63995653
MG		 5859 return EMULATE_DONE;
5860}
5861EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5862
e2366171 5863static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5864{
fc3a9157
JR		 5865 int r = EMULATE_DONE;
5866
6d77dbfc
GN		 5867 ++vcpu->stat.insn_emulation_fail;
5868 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5869
5870 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5871 return EMULATE_FAIL;
5872
a2b9e6c1 5873 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5874 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5875 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5876 vcpu->run->internal.ndata = 0;
1f4dcb3b 5877 r = EMULATE_USER_EXIT;
fc3a9157 5878 }
e2366171 5879
6d77dbfc 5880 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5881
5882 return r;
6d77dbfc
GN		 5883}
5884
93c05d3e 5885static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5886 bool write_fault_to_shadow_pgtable,
5887 int emulation_type)
a6f177ef 5888{
95b3cf69 5889 gpa_t gpa = cr2;
ba049e93 5890 kvm_pfn_t pfn;
a6f177ef 5891
384bf221 5892 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 5893 return false;
5894
6c3dfeb6
SC		 5895 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
5896 return false;
5897
44dd3ffa 5898 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 5899 /*
5900 * Write permission should be allowed since only
5901 * write access need to be emulated.
5902 */
5903 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5904
95b3cf69
XG		 5905 /*
5906 * If the mapping is invalid in guest, let cpu retry
5907 * it to generate fault.
5908 */
5909 if (gpa == UNMAPPED_GVA)
5910 return true;
5911 }
a6f177ef 5912
8e3d9d06
XG		 5913 /*
5914 * Do not retry the unhandleable instruction if it faults on the
5915 * readonly host memory, otherwise it will goto a infinite loop:
5916 * retry instruction -> write #PF -> emulation fail -> retry
5917 * instruction -> ...
5918 */
5919 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5920
5921 /*
5922 * If the instruction failed on the error pfn, it can not be fixed,
5923 * report the error to userspace.
5924 */
5925 if (is_error_noslot_pfn(pfn))
5926 return false;
5927
5928 kvm_release_pfn_clean(pfn);
5929
5930 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 5931 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 5932 unsigned int indirect_shadow_pages;
5933
5934 spin_lock(&vcpu->kvm->mmu_lock);
5935 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5936 spin_unlock(&vcpu->kvm->mmu_lock);
5937
5938 if (indirect_shadow_pages)
5939 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5940
a6f177ef 5941 return true;
8e3d9d06 5942 }
a6f177ef 5943
95b3cf69
XG		 5944 /*
5945 * if emulation was due to access to shadowed page table
5946 * and it failed try to unshadow page and re-enter the
5947 * guest to let CPU execute the instruction.
5948 */
5949 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5950
5951 /*
5952 * If the access faults on its page table, it can not
5953 * be fixed by unprotecting shadow page and it should
5954 * be reported to userspace.
5955 */
5956 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5957}
5958
1cb3f3ae
XG		 5959static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5960 unsigned long cr2, int emulation_type)
5961{
5962 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5963 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5964
5965 last_retry_eip = vcpu->arch.last_retry_eip;
5966 last_retry_addr = vcpu->arch.last_retry_addr;
5967
5968 /*
5969 * If the emulation is caused by #PF and it is non-page_table
5970 * writing instruction, it means the VM-EXIT is caused by shadow
5971 * page protected, we can zap the shadow page and retry this
5972 * instruction directly.
5973 *
5974 * Note: if the guest uses a non-page-table modifying instruction
5975 * on the PDE that points to the instruction, then we will unmap
5976 * the instruction and go to an infinite loop. So, we cache the
5977 * last retried eip and the last fault address, if we meet the eip
5978 * and the address again, we can break out of the potential infinite
5979 * loop.
5980 */
5981 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5982
384bf221 5983 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 5984 return false;
5985
6c3dfeb6
SC		 5986 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
5987 return false;
5988
1cb3f3ae
XG		 5989 if (x86_page_table_writing_insn(ctxt))
5990 return false;
5991
5992 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5993 return false;
5994
5995 vcpu->arch.last_retry_eip = ctxt->eip;
5996 vcpu->arch.last_retry_addr = cr2;
5997
44dd3ffa 5998 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 5999 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6000
22368028 6001 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6002
6003 return true;
6004}
6005
716d51ab
GN		 6006static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6007static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6008
64d60670 6009static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6010{
64d60670 6011 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6012 /* This is a good place to trace that we are exiting SMM. */
6013 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6014
c43203ca
PB		 6015 /* Process a latched INIT or SMI, if any. */
6016 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6017 }
699023e2
PB		 6018
6019 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6020}
6021
6022static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6023{
6024 unsigned changed = vcpu->arch.hflags ^ emul_flags;
6025
a584539b 6026 vcpu->arch.hflags = emul_flags;
64d60670
PB		 6027
6028 if (changed & HF_SMM_MASK)
6029 kvm_smm_changed(vcpu);
a584539b
PB		 6030}
6031
4a1e10d5
PB		 6032static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6033 unsigned long *db)
6034{
6035 u32 dr6 = 0;
6036 int i;
6037 u32 enable, rwlen;
6038
6039 enable = dr7;
6040 rwlen = dr7 >> 16;
6041 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6042 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6043 dr6 |= (1 << i);
6044 return dr6;
6045}
6046
c8401dda 6047static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6048{
6049 struct kvm_run *kvm_run = vcpu->run;
6050
c8401dda
PB		 6051 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6052 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6053 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6054 kvm_run->debug.arch.exception = DB_VECTOR;
6055 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6056 *r = EMULATE_USER_EXIT;
6057 } else {
6058 /*
6059 * "Certain debug exceptions may clear bit 0-3. The
6060 * remaining contents of the DR6 register are never
6061 * cleared by the processor".
6062 */
6063 vcpu->arch.dr6 &= ~15;
6064 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
6065 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 6066 }
6067}
6068
6affcbed
KH		 6069int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6070{
6071 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6072 int r = EMULATE_DONE;
6073
6074 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6075
6076 /*
6077 * rflags is the old, "raw" value of the flags. The new value has
6078 * not been saved yet.
6079 *
6080 * This is correct even for TF set by the guest, because "the
6081 * processor will not generate this exception after the instruction
6082 * that sets the TF flag".
6083 */
6084 if (unlikely(rflags & X86_EFLAGS_TF))
6085 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6086 return r == EMULATE_DONE;
6087}
6088EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6089
4a1e10d5
PB		 6090static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6091{
4a1e10d5
PB		 6092 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6093 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6094 struct kvm_run *kvm_run = vcpu->run;
6095 unsigned long eip = kvm_get_linear_rip(vcpu);
6096 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6097 vcpu->arch.guest_debug_dr7,
6098 vcpu->arch.eff_db);
6099
6100 if (dr6 != 0) {
6f43ed01 6101 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6102 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6103 kvm_run->debug.arch.exception = DB_VECTOR;
6104 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6105 *r = EMULATE_USER_EXIT;
6106 return true;
6107 }
6108 }
6109
4161a569
NA		 6110 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6111 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6112 unsigned long eip = kvm_get_linear_rip(vcpu);
6113 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6114 vcpu->arch.dr7,
6115 vcpu->arch.db);
6116
6117 if (dr6 != 0) {
6118 vcpu->arch.dr6 &= ~15;
6f43ed01 6119 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6120 kvm_queue_exception(vcpu, DB_VECTOR);
6121 *r = EMULATE_DONE;
6122 return true;
6123 }
6124 }
6125
6126 return false;
6127}
6128
04789b66
LA		 6129static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6130{
2d7921c4
AM		 6131 switch (ctxt->opcode_len) {
6132 case 1:
6133 switch (ctxt->b) {
6134 case 0xe4: /* IN */
6135 case 0xe5:
6136 case 0xec:
6137 case 0xed:
6138 case 0xe6: /* OUT */
6139 case 0xe7:
6140 case 0xee:
6141 case 0xef:
6142 case 0x6c: /* INS */
6143 case 0x6d:
6144 case 0x6e: /* OUTS */
6145 case 0x6f:
6146 return true;
6147 }
6148 break;
6149 case 2:
6150 switch (ctxt->b) {
6151 case 0x33: /* RDPMC */
6152 return true;
6153 }
6154 break;
04789b66
LA		 6155 }
6156
6157 return false;
6158}
6159
51d8b661
AP		 6160int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6161 unsigned long cr2,
dc25e89e
AP		 6162 int emulation_type,
6163 void *insn,
6164 int insn_len)
bbd9b64e 6165{
95cb2295 6166 int r;
9d74191a 6167 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6168 bool writeback = true;
93c05d3e 6169 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6170
c595ceee
PB		 6171 vcpu->arch.l1tf_flush_l1d = true;
6172
93c05d3e
XG		 6173 /*
6174 * Clear write_fault_to_shadow_pgtable here to ensure it is
6175 * never reused.
6176 */
6177 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6178 kvm_clear_exception_queue(vcpu);
8d7d8102 6179
571008da 6180 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6181 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6182
6183 /*
6184 * We will reenter on the same instruction since
6185 * we do not set complete_userspace_io. This does not
6186 * handle watchpoints yet, those would be handled in
6187 * the emulate_ops.
6188 */
d391f120
VK		 6189 if (!(emulation_type & EMULTYPE_SKIP) &&
6190 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6191 return r;
6192
9d74191a
TY		 6193 ctxt->interruptibility = 0;
6194 ctxt->have_exception = false;
e0ad0b47 6195 ctxt->exception.vector = -1;
9d74191a 6196 ctxt->perm_ok = false;
bbd9b64e 6197
b51e974f 6198 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6199
9d74191a 6200 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6201
e46479f8 6202 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6203 ++vcpu->stat.insn_emulation;
1d2887e2 6204 if (r != EMULATION_OK) {
4005996e
AK		 6205 if (emulation_type & EMULTYPE_TRAP_UD)
6206 return EMULATE_FAIL;
991eebf9
GN		 6207 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6208 emulation_type))
bbd9b64e 6209 return EMULATE_DONE;
6ea6e843
PB		 6210 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6211 return EMULATE_DONE;
6d77dbfc
GN		 6212 if (emulation_type & EMULTYPE_SKIP)
6213 return EMULATE_FAIL;
e2366171 6214 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6215 }
6216 }
6217
04789b66
LA		 6218 if ((emulation_type & EMULTYPE_VMWARE) &&
6219 !is_vmware_backdoor_opcode(ctxt))
6220 return EMULATE_FAIL;
6221
ba8afb6b 6222 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6223 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6224 if (ctxt->eflags & X86_EFLAGS_RF)
6225 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6226 return EMULATE_DONE;
6227 }
6228
1cb3f3ae
XG		 6229 if (retry_instruction(ctxt, cr2, emulation_type))
6230 return EMULATE_DONE;
6231
7ae441ea 6232 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6233 changes registers values during IO operation */
7ae441ea
GN		 6234 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6235 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6236 emulator_invalidate_register_cache(ctxt);
7ae441ea 6237 }
4d2179e1 6238
5cd21917 6239restart:
0f89b207
TL		 6240 /* Save the faulting GPA (cr2) in the address field */
6241 ctxt->exception.address = cr2;
6242
9d74191a 6243 r = x86_emulate_insn(ctxt);
bbd9b64e 6244
775fde86
JR		 6245 if (r == EMULATION_INTERCEPTED)
6246 return EMULATE_DONE;
6247
d2ddd1c4 6248 if (r == EMULATION_FAILED) {
991eebf9
GN		 6249 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6250 emulation_type))
c3cd7ffa
GN		 6251 return EMULATE_DONE;
6252
e2366171 6253 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6254 }
6255
9d74191a 6256 if (ctxt->have_exception) {
d2ddd1c4 6257 r = EMULATE_DONE;
ef54bcfe
PB		 6258 if (inject_emulated_exception(vcpu))
6259 return r;
d2ddd1c4 6260 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6261 if (!vcpu->arch.pio.in) {
6262 /* FIXME: return into emulator if single-stepping. */
3457e419 6263 vcpu->arch.pio.count = 0;
0912c977 6264 } else {
7ae441ea 6265 writeback = false;
716d51ab
GN		 6266 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6267 }
ac0a48c3 6268 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6269 } else if (vcpu->mmio_needed) {
6270 if (!vcpu->mmio_is_write)
6271 writeback = false;
ac0a48c3 6272 r = EMULATE_USER_EXIT;
716d51ab 6273 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6274 } else if (r == EMULATION_RESTART)
5cd21917 6275 goto restart;
d2ddd1c4
GN		 6276 else
6277 r = EMULATE_DONE;
f850e2e6 6278
7ae441ea 6279 if (writeback) {
6addfc42 6280 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6281 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6282 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6283 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6284 if (r == EMULATE_DONE &&
6285 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6286 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6287 if (!ctxt->have_exception ||
6288 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6289 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6290
6291 /*
6292 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6293 * do nothing, and it will be requested again as soon as
6294 * the shadow expires. But we still need to check here,
6295 * because POPF has no interrupt shadow.
6296 */
6297 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6298 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6299 } else
6300 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6301
6302 return r;
de7d789a 6303}
c60658d1
SC		 6304
6305int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6306{
6307 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6308}
6309EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6310
6311int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6312 void *insn, int insn_len)
6313{
6314 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6315}
6316EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6317
dca7f128
SC		 6318static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6319 unsigned short port)
de7d789a 6320{
cf8f70bf 6321 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6322 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6323 size, port, &val, 1);
cf8f70bf 6324 /* do not return to emulator after return from userspace */
7972995b 6325 vcpu->arch.pio.count = 0;
de7d789a
CO		 6326 return ret;
6327}
de7d789a 6328
8370c3d0
TL		 6329static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6330{
6331 unsigned long val;
6332
6333 /* We should only ever be called with arch.pio.count equal to 1 */
6334 BUG_ON(vcpu->arch.pio.count != 1);
6335
6336 /* For size less than 4 we merge, else we zero extend */
6337 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6338 : 0;
6339
6340 /*
6341 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6342 * the copy and tracing
6343 */
6344 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6345 vcpu->arch.pio.port, &val, 1);
6346 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6347
6348 return 1;
6349}
6350
dca7f128
SC		 6351static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6352 unsigned short port)
8370c3d0
TL		 6353{
6354 unsigned long val;
6355 int ret;
6356
6357 /* For size less than 4 we merge, else we zero extend */
6358 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6359
6360 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6361 &val, 1);
6362 if (ret) {
6363 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6364 return ret;
6365 }
6366
6367 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6368
6369 return 0;
6370}
dca7f128
SC		 6371
6372int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6373{
6374 int ret = kvm_skip_emulated_instruction(vcpu);
6375
6376 /*
6377 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6378 * KVM_EXIT_DEBUG here.
6379 */
6380 if (in)
6381 return kvm_fast_pio_in(vcpu, size, port) && ret;
6382 else
6383 return kvm_fast_pio_out(vcpu, size, port) && ret;
6384}
6385EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6386
251a5fd6 6387static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6388{
0a3aee0d 6389 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6390 return 0;
8cfdc000
ZA		 6391}
6392
6393static void tsc_khz_changed(void *data)
c8076604 6394{
8cfdc000
ZA		 6395 struct cpufreq_freqs *freq = data;
6396 unsigned long khz = 0;
6397
6398 if (data)
6399 khz = freq->new;
6400 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6401 khz = cpufreq_quick_get(raw_smp_processor_id());
6402 if (!khz)
6403 khz = tsc_khz;
0a3aee0d 6404 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6405}
6406
5fa4ec9c 6407#ifdef CONFIG_X86_64
0092e434
VK		 6408static void kvm_hyperv_tsc_notifier(void)
6409{
0092e434
VK		 6410 struct kvm *kvm;
6411 struct kvm_vcpu *vcpu;
6412 int cpu;
6413
6414 spin_lock(&kvm_lock);
6415 list_for_each_entry(kvm, &vm_list, vm_list)
6416 kvm_make_mclock_inprogress_request(kvm);
6417
6418 hyperv_stop_tsc_emulation();
6419
6420 /* TSC frequency always matches when on Hyper-V */
6421 for_each_present_cpu(cpu)
6422 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6423 kvm_max_guest_tsc_khz = tsc_khz;
6424
6425 list_for_each_entry(kvm, &vm_list, vm_list) {
6426 struct kvm_arch *ka = &kvm->arch;
6427
6428 spin_lock(&ka->pvclock_gtod_sync_lock);
6429
6430 pvclock_update_vm_gtod_copy(kvm);
6431
6432 kvm_for_each_vcpu(cpu, vcpu, kvm)
6433 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6434
6435 kvm_for_each_vcpu(cpu, vcpu, kvm)
6436 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6437
6438 spin_unlock(&ka->pvclock_gtod_sync_lock);
6439 }
6440 spin_unlock(&kvm_lock);
0092e434 6441}
5fa4ec9c 6442#endif
0092e434 6443
c8076604
GH		 6444static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6445 void *data)
6446{
6447 struct cpufreq_freqs *freq = data;
6448 struct kvm *kvm;
6449 struct kvm_vcpu *vcpu;
6450 int i, send_ipi = 0;
6451
8cfdc000
ZA		 6452 /*
6453 * We allow guests to temporarily run on slowing clocks,
6454 * provided we notify them after, or to run on accelerating
6455 * clocks, provided we notify them before. Thus time never
6456 * goes backwards.
6457 *
6458 * However, we have a problem. We can't atomically update
6459 * the frequency of a given CPU from this function; it is
6460 * merely a notifier, which can be called from any CPU.
6461 * Changing the TSC frequency at arbitrary points in time
6462 * requires a recomputation of local variables related to
6463 * the TSC for each VCPU. We must flag these local variables
6464 * to be updated and be sure the update takes place with the
6465 * new frequency before any guests proceed.
6466 *
6467 * Unfortunately, the combination of hotplug CPU and frequency
6468 * change creates an intractable locking scenario; the order
6469 * of when these callouts happen is undefined with respect to
6470 * CPU hotplug, and they can race with each other. As such,
6471 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6472 * undefined; you can actually have a CPU frequency change take
6473 * place in between the computation of X and the setting of the
6474 * variable. To protect against this problem, all updates of
6475 * the per_cpu tsc_khz variable are done in an interrupt
6476 * protected IPI, and all callers wishing to update the value
6477 * must wait for a synchronous IPI to complete (which is trivial
6478 * if the caller is on the CPU already). This establishes the
6479 * necessary total order on variable updates.
6480 *
6481 * Note that because a guest time update may take place
6482 * anytime after the setting of the VCPU's request bit, the
6483 * correct TSC value must be set before the request. However,
6484 * to ensure the update actually makes it to any guest which
6485 * starts running in hardware virtualization between the set
6486 * and the acquisition of the spinlock, we must also ping the
6487 * CPU after setting the request bit.
6488 *
6489 */
6490
c8076604
GH		 6491 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6492 return 0;
6493 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6494 return 0;
8cfdc000
ZA		 6495
6496 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6497
2f303b74 6498 spin_lock(&kvm_lock);
c8076604 6499 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6500 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6501 if (vcpu->cpu != freq->cpu)
6502 continue;
c285545f 6503 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6504 if (vcpu->cpu != smp_processor_id())
8cfdc000 6505 send_ipi = 1;
c8076604
GH		 6506 }
6507 }
2f303b74 6508 spin_unlock(&kvm_lock);
c8076604
GH		 6509
6510 if (freq->old < freq->new && send_ipi) {
6511 /*
6512 * We upscale the frequency. Must make the guest
6513 * doesn't see old kvmclock values while running with
6514 * the new frequency, otherwise we risk the guest sees
6515 * time go backwards.
6516 *
6517 * In case we update the frequency for another cpu
6518 * (which might be in guest context) send an interrupt
6519 * to kick the cpu out of guest context. Next time
6520 * guest context is entered kvmclock will be updated,
6521 * so the guest will not see stale values.
6522 */
8cfdc000 6523 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6524 }
6525 return 0;
6526}
6527
6528static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6529 .notifier_call = kvmclock_cpufreq_notifier
6530};
6531
251a5fd6 6532static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6533{
251a5fd6
SAS		 6534 tsc_khz_changed(NULL);
6535 return 0;
8cfdc000
ZA		 6536}
6537
b820cc0c
ZA		 6538static void kvm_timer_init(void)
6539{
c285545f 6540 max_tsc_khz = tsc_khz;
460dd42e 6541
b820cc0c 6542 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6543#ifdef CONFIG_CPU_FREQ
6544 struct cpufreq_policy policy;
758f588d
BP		 6545 int cpu;
6546
c285545f 6547 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6548 cpu = get_cpu();
6549 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6550 if (policy.cpuinfo.max_freq)
6551 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6552 put_cpu();
c285545f 6553#endif
b820cc0c
ZA		 6554 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6555 CPUFREQ_TRANSITION_NOTIFIER);
6556 }
c285545f 6557 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6558
73c1b41e 6559 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6560 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6561}
6562
dd60d217
AK		 6563DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6564EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6565
f5132b01 6566int kvm_is_in_guest(void)
ff9d07a0 6567{
086c9855 6568 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6569}
6570
6571static int kvm_is_user_mode(void)
6572{
6573 int user_mode = 3;
dcf46b94 6574
086c9855
AS		 6575 if (__this_cpu_read(current_vcpu))
6576 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6577
ff9d07a0
ZY		 6578 return user_mode != 0;
6579}
6580
6581static unsigned long kvm_get_guest_ip(void)
6582{
6583 unsigned long ip = 0;
dcf46b94 6584
086c9855
AS		 6585 if (__this_cpu_read(current_vcpu))
6586 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6587
ff9d07a0
ZY		 6588 return ip;
6589}
6590
6591static struct perf_guest_info_callbacks kvm_guest_cbs = {
6592 .is_in_guest = kvm_is_in_guest,
6593 .is_user_mode = kvm_is_user_mode,
6594 .get_guest_ip = kvm_get_guest_ip,
6595};
6596
ce88decf
XG		 6597static void kvm_set_mmio_spte_mask(void)
6598{
6599 u64 mask;
6600 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6601
6602 /*
6603 * Set the reserved bits and the present bit of an paging-structure
6604 * entry to generate page fault with PFER.RSV = 1.
6605 */
28a1f3ac
JS		 6606
6607 /*
6608 * Mask the uppermost physical address bit, which would be reserved as
6609 * long as the supported physical address width is less than 52.
6610 */
6611 mask = 1ull << 51;
885032b9 6612
885032b9 6613 /* Set the present bit. */
ce88decf
XG		 6614 mask |= 1ull;
6615
ce88decf
XG		 6616 /*
6617 * If reserved bit is not supported, clear the present bit to disable
6618 * mmio page fault.
6619 */
7288bde1 6620 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
ce88decf 6621 mask &= ~1ull;
ce88decf 6622
dcdca5fe 6623 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6624}
6625
16e8d74d
MT		 6626#ifdef CONFIG_X86_64
6627static void pvclock_gtod_update_fn(struct work_struct *work)
6628{
d828199e
MT		 6629 struct kvm *kvm;
6630
6631 struct kvm_vcpu *vcpu;
6632 int i;
6633
2f303b74 6634 spin_lock(&kvm_lock);
d828199e
MT		 6635 list_for_each_entry(kvm, &vm_list, vm_list)
6636 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6637 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6638 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6639 spin_unlock(&kvm_lock);
16e8d74d
MT		 6640}
6641
6642static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6643
6644/*
6645 * Notification about pvclock gtod data update.
6646 */
6647static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6648 void *priv)
6649{
6650 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6651 struct timekeeper *tk = priv;
6652
6653 update_pvclock_gtod(tk);
6654
6655 /* disable master clock if host does not trust, or does not
b0c39dc6 6656 * use, TSC based clocksource.
16e8d74d 6657 */
b0c39dc6 6658 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6659 atomic_read(&kvm_guest_has_master_clock) != 0)
6660 queue_work(system_long_wq, &pvclock_gtod_work);
6661
6662 return 0;
6663}
6664
6665static struct notifier_block pvclock_gtod_notifier = {
6666 .notifier_call = pvclock_gtod_notify,
6667};
6668#endif
6669
f8c16bba 6670int kvm_arch_init(void *opaque)
043405e1 6671{
b820cc0c 6672 int r;
6b61edf7 6673 struct kvm_x86_ops *ops = opaque;
f8c16bba 6674
f8c16bba
ZX		 6675 if (kvm_x86_ops) {
6676 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6677 r = -EEXIST;
6678 goto out;
f8c16bba
ZX		 6679 }
6680
6681 if (!ops->cpu_has_kvm_support()) {
6682 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6683 r = -EOPNOTSUPP;
6684 goto out;
f8c16bba
ZX		 6685 }
6686 if (ops->disabled_by_bios()) {
6687 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6688 r = -EOPNOTSUPP;
6689 goto out;
f8c16bba
ZX		 6690 }
6691
013f6a5d
MT		 6692 r = -ENOMEM;
6693 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6694 if (!shared_msrs) {
6695 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6696 goto out;
6697 }
6698
97db56ce
AK		 6699 r = kvm_mmu_module_init();
6700 if (r)
013f6a5d 6701 goto out_free_percpu;
97db56ce 6702
ce88decf 6703 kvm_set_mmio_spte_mask();
97db56ce 6704
f8c16bba 6705 kvm_x86_ops = ops;
920c8377 6706
7b52345e 6707 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6708 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6709 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6710 kvm_timer_init();
c8076604 6711
ff9d07a0
ZY		 6712 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6713
d366bf7e 6714 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6715 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6716
c5cc421b 6717 kvm_lapic_init();
16e8d74d
MT		 6718#ifdef CONFIG_X86_64
6719 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6720
5fa4ec9c 6721 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6722 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6723#endif
6724
f8c16bba 6725 return 0;
56c6d28a 6726
013f6a5d
MT		 6727out_free_percpu:
6728 free_percpu(shared_msrs);
56c6d28a 6729out:
56c6d28a 6730 return r;
043405e1 6731}
8776e519 6732
f8c16bba
ZX		 6733void kvm_arch_exit(void)
6734{
0092e434 6735#ifdef CONFIG_X86_64
5fa4ec9c 6736 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6737 clear_hv_tscchange_cb();
6738#endif
cef84c30 6739 kvm_lapic_exit();
ff9d07a0
ZY		 6740 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6741
888d256e
JK		 6742 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6743 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6744 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6745 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6746#ifdef CONFIG_X86_64
6747 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6748#endif
f8c16bba 6749 kvm_x86_ops = NULL;
56c6d28a 6750 kvm_mmu_module_exit();
013f6a5d 6751 free_percpu(shared_msrs);
56c6d28a 6752}
f8c16bba 6753
5cb56059 6754int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6755{
6756 ++vcpu->stat.halt_exits;
35754c98 6757 if (lapic_in_kernel(vcpu)) {
a4535290 6758 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6759 return 1;
6760 } else {
6761 vcpu->run->exit_reason = KVM_EXIT_HLT;
6762 return 0;
6763 }
6764}
5cb56059
JS		 6765EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6766
6767int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6768{
6affcbed
KH		 6769 int ret = kvm_skip_emulated_instruction(vcpu);
6770 /*
6771 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6772 * KVM_EXIT_DEBUG here.
6773 */
6774 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6775}
8776e519
HB		 6776EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6777
8ef81a9a 6778#ifdef CONFIG_X86_64
55dd00a7
MT		 6779static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6780 unsigned long clock_type)
6781{
6782 struct kvm_clock_pairing clock_pairing;
899a31f5 6783 struct timespec64 ts;
80fbd89c 6784 u64 cycle;
55dd00a7
MT		 6785 int ret;
6786
6787 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6788 return -KVM_EOPNOTSUPP;
6789
6790 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6791 return -KVM_EOPNOTSUPP;
6792
6793 clock_pairing.sec = ts.tv_sec;
6794 clock_pairing.nsec = ts.tv_nsec;
6795 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6796 clock_pairing.flags = 0;
6797
6798 ret = 0;
6799 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6800 sizeof(struct kvm_clock_pairing)))
6801 ret = -KVM_EFAULT;
6802
6803 return ret;
6804}
8ef81a9a 6805#endif
55dd00a7 6806
6aef266c
SV		 6807/*
6808 * kvm_pv_kick_cpu_op: Kick a vcpu.
6809 *
6810 * @apicid - apicid of vcpu to be kicked.
6811 */
6812static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6813{
24d2166b 6814 struct kvm_lapic_irq lapic_irq;
6aef266c 6815
24d2166b
R		 6816 lapic_irq.shorthand = 0;
6817 lapic_irq.dest_mode = 0;
ebd28fcb 6818 lapic_irq.level = 0;
24d2166b 6819 lapic_irq.dest_id = apicid;
93bbf0b8 6820 lapic_irq.msi_redir_hint = false;
6aef266c 6821
24d2166b 6822 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6823 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6824}
6825
d62caabb
AS		 6826void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6827{
6828 vcpu->arch.apicv_active = false;
6829 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6830}
6831
8776e519
HB		 6832int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6833{
6834 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6835 int op_64_bit;
8776e519 6836
696ca779
RK		 6837 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6838 return kvm_hv_hypercall(vcpu);
55cd8e5a 6839
5fdbf976
MT		 6840 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6841 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6842 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6843 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6844 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6845
229456fc 6846 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6847
a449c7aa
NA		 6848 op_64_bit = is_64_bit_mode(vcpu);
6849 if (!op_64_bit) {
8776e519
HB		 6850 nr &= 0xFFFFFFFF;
6851 a0 &= 0xFFFFFFFF;
6852 a1 &= 0xFFFFFFFF;
6853 a2 &= 0xFFFFFFFF;
6854 a3 &= 0xFFFFFFFF;
6855 }
6856
07708c4a
JK		 6857 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6858 ret = -KVM_EPERM;
696ca779 6859 goto out;
07708c4a
JK		 6860 }
6861
8776e519 6862 switch (nr) {
b93463aa
AK		 6863 case KVM_HC_VAPIC_POLL_IRQ:
6864 ret = 0;
6865 break;
6aef266c
SV		 6866 case KVM_HC_KICK_CPU:
6867 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6868 ret = 0;
6869 break;
8ef81a9a 6870#ifdef CONFIG_X86_64
55dd00a7
MT		 6871 case KVM_HC_CLOCK_PAIRING:
6872 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6873 break;
4180bf1b
WL		 6874 case KVM_HC_SEND_IPI:
6875 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
6876 break;
8ef81a9a 6877#endif
8776e519
HB		 6878 default:
6879 ret = -KVM_ENOSYS;
6880 break;
6881 }
696ca779 6882out:
a449c7aa
NA		 6883 if (!op_64_bit)
6884 ret = (u32)ret;
5fdbf976 6885 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 6886
f11c3a8d 6887 ++vcpu->stat.hypercalls;
6356ee0c 6888 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6889}
6890EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6891
b6785def 6892static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6893{
d6aa1000 6894 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6895 char instruction[3];
5fdbf976 6896 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6897
8776e519 6898 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6899
ce2e852e
DV		 6900 return emulator_write_emulated(ctxt, rip, instruction, 3,
6901 &ctxt->exception);
8776e519
HB		 6902}
6903
851ba692 6904static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6905{
782d422b
MG		 6906 return vcpu->run->request_interrupt_window &&
6907 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6908}
6909
851ba692 6910static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6911{
851ba692
AK		 6912 struct kvm_run *kvm_run = vcpu->run;
6913
91586a3b 6914 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6915 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6916 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6917 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6918 kvm_run->ready_for_interrupt_injection =
6919 pic_in_kernel(vcpu->kvm) ||
782d422b 6920 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6921}
6922
95ba8273
GN		 6923static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6924{
6925 int max_irr, tpr;
6926
6927 if (!kvm_x86_ops->update_cr8_intercept)
6928 return;
6929
bce87cce 6930 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6931 return;
6932
d62caabb
AS		 6933 if (vcpu->arch.apicv_active)
6934 return;
6935
8db3baa2
GN		 6936 if (!vcpu->arch.apic->vapic_addr)
6937 max_irr = kvm_lapic_find_highest_irr(vcpu);
6938 else
6939 max_irr = -1;
95ba8273
GN		 6940
6941 if (max_irr != -1)
6942 max_irr >>= 4;
6943
6944 tpr = kvm_lapic_get_cr8(vcpu);
6945
6946 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6947}
6948
b6b8a145 6949static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6950{
b6b8a145
JK		 6951 int r;
6952
95ba8273 6953 /* try to reinject previous events if any */
664f8e26 6954
1a680e35
LA		 6955 if (vcpu->arch.exception.injected)
6956 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6957 /*
a042c26f
LA		 6958 * Do not inject an NMI or interrupt if there is a pending
6959 * exception. Exceptions and interrupts are recognized at
6960 * instruction boundaries, i.e. the start of an instruction.
6961 * Trap-like exceptions, e.g. #DB, have higher priority than
6962 * NMIs and interrupts, i.e. traps are recognized before an
6963 * NMI/interrupt that's pending on the same instruction.
6964 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6965 * priority, but are only generated (pended) during instruction
6966 * execution, i.e. a pending fault-like exception means the
6967 * fault occurred on the *previous* instruction and must be
6968 * serviced prior to recognizing any new events in order to
6969 * fully complete the previous instruction.
664f8e26 6970 */
1a680e35
LA		 6971 else if (!vcpu->arch.exception.pending) {
6972 if (vcpu->arch.nmi_injected)
664f8e26 6973 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6974 else if (vcpu->arch.interrupt.injected)
664f8e26 6975 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6976 }
6977
1a680e35
LA		 6978 /*
6979 * Call check_nested_events() even if we reinjected a previous event
6980 * in order for caller to determine if it should require immediate-exit
6981 * from L2 to L1 due to pending L1 events which require exit
6982 * from L2 to L1.
6983 */
664f8e26
WL		 6984 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6985 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6986 if (r != 0)
6987 return r;
6988 }
6989
6990 /* try to inject new event if pending */
b59bb7bd 6991 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6992 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6993 vcpu->arch.exception.has_error_code,
6994 vcpu->arch.exception.error_code);
d6e8c854 6995
1a680e35 6996 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 6997 vcpu->arch.exception.pending = false;
6998 vcpu->arch.exception.injected = true;
6999
d6e8c854
NA		 7000 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7001 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7002 X86_EFLAGS_RF);
7003
6bdf0662
NA		 7004 if (vcpu->arch.exception.nr == DB_VECTOR &&
7005 (vcpu->arch.dr7 & DR7_GD)) {
7006 vcpu->arch.dr7 &= ~DR7_GD;
7007 kvm_update_dr7(vcpu);
7008 }
7009
cfcd20e5 7010 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7011 }
7012
7013 /* Don't consider new event if we re-injected an event */
7014 if (kvm_event_needs_reinjection(vcpu))
7015 return 0;
7016
7017 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7018 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7019 vcpu->arch.smi_pending = false;
52797bf9 7020 ++vcpu->arch.smi_count;
ee2cd4b7 7021 enter_smm(vcpu);
c43203ca 7022 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7023 --vcpu->arch.nmi_pending;
7024 vcpu->arch.nmi_injected = true;
7025 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7026 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7027 /*
7028 * Because interrupts can be injected asynchronously, we are
7029 * calling check_nested_events again here to avoid a race condition.
7030 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7031 * proposal and current concerns. Perhaps we should be setting
7032 * KVM_REQ_EVENT only on certain events and not unconditionally?
7033 */
7034 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7035 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7036 if (r != 0)
7037 return r;
7038 }
95ba8273 7039 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7040 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7041 false);
7042 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7043 }
7044 }
ee2cd4b7 7045
b6b8a145 7046 return 0;
95ba8273
GN		 7047}
7048
7460fb4a
AK		 7049static void process_nmi(struct kvm_vcpu *vcpu)
7050{
7051 unsigned limit = 2;
7052
7053 /*
7054 * x86 is limited to one NMI running, and one NMI pending after it.
7055 * If an NMI is already in progress, limit further NMIs to just one.
7056 * Otherwise, allow two (and we'll inject the first one immediately).
7057 */
7058 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7059 limit = 1;
7060
7061 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7062 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7063 kvm_make_request(KVM_REQ_EVENT, vcpu);
7064}
7065
ee2cd4b7 7066static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7067{
7068 u32 flags = 0;
7069 flags |= seg->g << 23;
7070 flags |= seg->db << 22;
7071 flags |= seg->l << 21;
7072 flags |= seg->avl << 20;
7073 flags |= seg->present << 15;
7074 flags |= seg->dpl << 13;
7075 flags |= seg->s << 12;
7076 flags |= seg->type << 8;
7077 return flags;
7078}
7079
ee2cd4b7 7080static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7081{
7082 struct kvm_segment seg;
7083 int offset;
7084
7085 kvm_get_segment(vcpu, &seg, n);
7086 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7087
7088 if (n < 3)
7089 offset = 0x7f84 + n * 12;
7090 else
7091 offset = 0x7f2c + (n - 3) * 12;
7092
7093 put_smstate(u32, buf, offset + 8, seg.base);
7094 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7095 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7096}
7097
efbb288a 7098#ifdef CONFIG_X86_64
ee2cd4b7 7099static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7100{
7101 struct kvm_segment seg;
7102 int offset;
7103 u16 flags;
7104
7105 kvm_get_segment(vcpu, &seg, n);
7106 offset = 0x7e00 + n * 16;
7107
ee2cd4b7 7108 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7109 put_smstate(u16, buf, offset, seg.selector);
7110 put_smstate(u16, buf, offset + 2, flags);
7111 put_smstate(u32, buf, offset + 4, seg.limit);
7112 put_smstate(u64, buf, offset + 8, seg.base);
7113}
efbb288a 7114#endif
660a5d51 7115
ee2cd4b7 7116static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7117{
7118 struct desc_ptr dt;
7119 struct kvm_segment seg;
7120 unsigned long val;
7121 int i;
7122
7123 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7124 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7125 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7126 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7127
7128 for (i = 0; i < 8; i++)
7129 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7130
7131 kvm_get_dr(vcpu, 6, &val);
7132 put_smstate(u32, buf, 0x7fcc, (u32)val);
7133 kvm_get_dr(vcpu, 7, &val);
7134 put_smstate(u32, buf, 0x7fc8, (u32)val);
7135
7136 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7137 put_smstate(u32, buf, 0x7fc4, seg.selector);
7138 put_smstate(u32, buf, 0x7f64, seg.base);
7139 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7140 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7141
7142 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7143 put_smstate(u32, buf, 0x7fc0, seg.selector);
7144 put_smstate(u32, buf, 0x7f80, seg.base);
7145 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7146 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7147
7148 kvm_x86_ops->get_gdt(vcpu, &dt);
7149 put_smstate(u32, buf, 0x7f74, dt.address);
7150 put_smstate(u32, buf, 0x7f70, dt.size);
7151
7152 kvm_x86_ops->get_idt(vcpu, &dt);
7153 put_smstate(u32, buf, 0x7f58, dt.address);
7154 put_smstate(u32, buf, 0x7f54, dt.size);
7155
7156 for (i = 0; i < 6; i++)
ee2cd4b7 7157 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7158
7159 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7160
7161 /* revision id */
7162 put_smstate(u32, buf, 0x7efc, 0x00020000);
7163 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7164}
7165
ee2cd4b7 7166static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7167{
7168#ifdef CONFIG_X86_64
7169 struct desc_ptr dt;
7170 struct kvm_segment seg;
7171 unsigned long val;
7172 int i;
7173
7174 for (i = 0; i < 16; i++)
7175 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7176
7177 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7178 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7179
7180 kvm_get_dr(vcpu, 6, &val);
7181 put_smstate(u64, buf, 0x7f68, val);
7182 kvm_get_dr(vcpu, 7, &val);
7183 put_smstate(u64, buf, 0x7f60, val);
7184
7185 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7186 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7187 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7188
7189 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7190
7191 /* revision id */
7192 put_smstate(u32, buf, 0x7efc, 0x00020064);
7193
7194 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7195
7196 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7197 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7198 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7199 put_smstate(u32, buf, 0x7e94, seg.limit);
7200 put_smstate(u64, buf, 0x7e98, seg.base);
7201
7202 kvm_x86_ops->get_idt(vcpu, &dt);
7203 put_smstate(u32, buf, 0x7e84, dt.size);
7204 put_smstate(u64, buf, 0x7e88, dt.address);
7205
7206 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7207 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7208 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7209 put_smstate(u32, buf, 0x7e74, seg.limit);
7210 put_smstate(u64, buf, 0x7e78, seg.base);
7211
7212 kvm_x86_ops->get_gdt(vcpu, &dt);
7213 put_smstate(u32, buf, 0x7e64, dt.size);
7214 put_smstate(u64, buf, 0x7e68, dt.address);
7215
7216 for (i = 0; i < 6; i++)
ee2cd4b7 7217 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7218#else
7219 WARN_ON_ONCE(1);
7220#endif
7221}
7222
ee2cd4b7 7223static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7224{
660a5d51 7225 struct kvm_segment cs, ds;
18c3626e 7226 struct desc_ptr dt;
660a5d51
PB		 7227 char buf[512];
7228 u32 cr0;
7229
660a5d51 7230 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7231 memset(buf, 0, 512);
d6321d49 7232 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7233 enter_smm_save_state_64(vcpu, buf);
660a5d51 7234 else
ee2cd4b7 7235 enter_smm_save_state_32(vcpu, buf);
660a5d51 7236
0234bf88
LP		 7237 /*
7238 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7239 * vCPU state (e.g. leave guest mode) after we've saved the state into
7240 * the SMM state-save area.
7241 */
7242 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7243
7244 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7245 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7246
7247 if (kvm_x86_ops->get_nmi_mask(vcpu))
7248 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7249 else
7250 kvm_x86_ops->set_nmi_mask(vcpu, true);
7251
7252 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7253 kvm_rip_write(vcpu, 0x8000);
7254
7255 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7256 kvm_x86_ops->set_cr0(vcpu, cr0);
7257 vcpu->arch.cr0 = cr0;
7258
7259 kvm_x86_ops->set_cr4(vcpu, 0);
7260
18c3626e
PB		 7261 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7262 dt.address = dt.size = 0;
7263 kvm_x86_ops->set_idt(vcpu, &dt);
7264
660a5d51
PB		 7265 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7266
7267 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7268 cs.base = vcpu->arch.smbase;
7269
7270 ds.selector = 0;
7271 ds.base = 0;
7272
7273 cs.limit = ds.limit = 0xffffffff;
7274 cs.type = ds.type = 0x3;
7275 cs.dpl = ds.dpl = 0;
7276 cs.db = ds.db = 0;
7277 cs.s = ds.s = 1;
7278 cs.l = ds.l = 0;
7279 cs.g = ds.g = 1;
7280 cs.avl = ds.avl = 0;
7281 cs.present = ds.present = 1;
7282 cs.unusable = ds.unusable = 0;
7283 cs.padding = ds.padding = 0;
7284
7285 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7286 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7287 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7288 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7289 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7290 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7291
d6321d49 7292 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7293 kvm_x86_ops->set_efer(vcpu, 0);
7294
7295 kvm_update_cpuid(vcpu);
7296 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7297}
7298
ee2cd4b7 7299static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7300{
7301 vcpu->arch.smi_pending = true;
7302 kvm_make_request(KVM_REQ_EVENT, vcpu);
7303}
7304
2860c4b1
PB		 7305void kvm_make_scan_ioapic_request(struct kvm *kvm)
7306{
7307 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7308}
7309
3d81bc7e 7310static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7311{
3d81bc7e
YZ		 7312 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7313 return;
c7c9c56c 7314
6308630b 7315 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7316
b053b2ae 7317 if (irqchip_split(vcpu->kvm))
6308630b 7318 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7319 else {
fa59cc00 7320 if (vcpu->arch.apicv_active)
d62caabb 7321 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7322 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7323 }
e40ff1d6
LA		 7324
7325 if (is_guest_mode(vcpu))
7326 vcpu->arch.load_eoi_exitmap_pending = true;
7327 else
7328 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7329}
7330
7331static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7332{
7333 u64 eoi_exit_bitmap[4];
7334
7335 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7336 return;
7337
5c919412
AS		 7338 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7339 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7340 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7341}
7342
93065ac7
MH		 7343int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7344 unsigned long start, unsigned long end,
7345 bool blockable)
b1394e74
RK		 7346{
7347 unsigned long apic_address;
7348
7349 /*
7350 * The physical address of apic access page is stored in the VMCS.
7351 * Update it when it becomes invalid.
7352 */
7353 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7354 if (start <= apic_address && apic_address < end)
7355 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7356
7357 return 0;
b1394e74
RK		 7358}
7359
4256f43f
TC		 7360void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7361{
c24ae0dc
TC		 7362 struct page *page = NULL;
7363
35754c98 7364 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7365 return;
7366
4256f43f
TC		 7367 if (!kvm_x86_ops->set_apic_access_page_addr)
7368 return;
7369
c24ae0dc 7370 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7371 if (is_error_page(page))
7372 return;
c24ae0dc
TC		 7373 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7374
7375 /*
7376 * Do not pin apic access page in memory, the MMU notifier
7377 * will call us again if it is migrated or swapped out.
7378 */
7379 put_page(page);
4256f43f
TC		 7380}
7381EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7382
d264ee0c
SC		 7383void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7384{
7385 smp_send_reschedule(vcpu->cpu);
7386}
7387EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7388
9357d939 7389/*
362c698f 7390 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7391 * exiting to the userspace. Otherwise, the value will be returned to the
7392 * userspace.
7393 */
851ba692 7394static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7395{
7396 int r;
62a193ed
MG		 7397 bool req_int_win =
7398 dm_request_for_irq_injection(vcpu) &&
7399 kvm_cpu_accept_dm_intr(vcpu);
7400
730dca42 7401 bool req_immediate_exit = false;
b6c7a5dc 7402
2fa6e1e1 7403 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7404 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7405 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7406 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7407 kvm_mmu_unload(vcpu);
a8eeb04a 7408 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7409 __kvm_migrate_timers(vcpu);
d828199e
MT		 7410 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7411 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7412 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7413 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7414 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7415 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7416 if (unlikely(r))
7417 goto out;
7418 }
a8eeb04a 7419 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7420 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7421 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7422 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7423 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7424 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7425 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7426 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7427 r = 0;
7428 goto out;
7429 }
a8eeb04a 7430 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7431 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7432 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7433 r = 0;
7434 goto out;
7435 }
af585b92
GN		 7436 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7437 /* Page is swapped out. Do synthetic halt */
7438 vcpu->arch.apf.halted = true;
7439 r = 1;
7440 goto out;
7441 }
c9aaa895
GC		 7442 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7443 record_steal_time(vcpu);
64d60670
PB		 7444 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7445 process_smi(vcpu);
7460fb4a
AK		 7446 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7447 process_nmi(vcpu);
f5132b01 7448 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7449 kvm_pmu_handle_event(vcpu);
f5132b01 7450 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7451 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7452 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7453 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7454 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7455 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7456 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7457 vcpu->run->eoi.vector =
7458 vcpu->arch.pending_ioapic_eoi;
7459 r = 0;
7460 goto out;
7461 }
7462 }
3d81bc7e
YZ		 7463 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7464 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7465 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7466 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7467 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7468 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7469 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7470 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7471 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7472 r = 0;
7473 goto out;
7474 }
e516cebb
AS		 7475 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7476 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7477 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7478 r = 0;
7479 goto out;
7480 }
db397571
AS		 7481 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7482 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7483 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7484 r = 0;
7485 goto out;
7486 }
f3b138c5
AS		 7487
7488 /*
7489 * KVM_REQ_HV_STIMER has to be processed after
7490 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7491 * depend on the guest clock being up-to-date
7492 */
1f4b34f8
AS		 7493 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7494 kvm_hv_process_stimers(vcpu);
2f52d58c 7495 }
b93463aa 7496
b463a6f7 7497 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7498 ++vcpu->stat.req_event;
66450a21
JK		 7499 kvm_apic_accept_events(vcpu);
7500 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7501 r = 1;
7502 goto out;
7503 }
7504
b6b8a145
JK		 7505 if (inject_pending_event(vcpu, req_int_win) != 0)
7506 req_immediate_exit = true;
321c5658 7507 else {
cc3d967f 7508 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7509 *
cc3d967f
LP		 7510 * SMIs have three cases:
7511 * 1) They can be nested, and then there is nothing to
7512 * do here because RSM will cause a vmexit anyway.
7513 * 2) There is an ISA-specific reason why SMI cannot be
7514 * injected, and the moment when this changes can be
7515 * intercepted.
7516 * 3) Or the SMI can be pending because
7517 * inject_pending_event has completed the injection
7518 * of an IRQ or NMI from the previous vmexit, and
7519 * then we request an immediate exit to inject the
7520 * SMI.
c43203ca
PB		 7521 */
7522 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7523 if (!kvm_x86_ops->enable_smi_window(vcpu))
7524 req_immediate_exit = true;
321c5658
YS		 7525 if (vcpu->arch.nmi_pending)
7526 kvm_x86_ops->enable_nmi_window(vcpu);
7527 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7528 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7529 WARN_ON(vcpu->arch.exception.pending);
321c5658 7530 }
b463a6f7
AK		 7531
7532 if (kvm_lapic_enabled(vcpu)) {
7533 update_cr8_intercept(vcpu);
7534 kvm_lapic_sync_to_vapic(vcpu);
7535 }
7536 }
7537
d8368af8
AK		 7538 r = kvm_mmu_reload(vcpu);
7539 if (unlikely(r)) {
d905c069 7540 goto cancel_injection;
d8368af8
AK		 7541 }
7542
b6c7a5dc
HB		 7543 preempt_disable();
7544
7545 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7546
7547 /*
7548 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7549 * IPI are then delayed after guest entry, which ensures that they
7550 * result in virtual interrupt delivery.
7551 */
7552 local_irq_disable();
6b7e2d09
XG		 7553 vcpu->mode = IN_GUEST_MODE;
7554
01b71917
MT		 7555 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7556
0f127d12 7557 /*
b95234c8 7558 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7559 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7560 *
7561 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7562 * pairs with the memory barrier implicit in pi_test_and_set_on
7563 * (see vmx_deliver_posted_interrupt).
7564 *
7565 * 3) This also orders the write to mode from any reads to the page
7566 * tables done while the VCPU is running. Please see the comment
7567 * in kvm_flush_remote_tlbs.
6b7e2d09 7568 */
01b71917 7569 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7570
b95234c8
PB		 7571 /*
7572 * This handles the case where a posted interrupt was
7573 * notified with kvm_vcpu_kick.
7574 */
fa59cc00
LA		 7575 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7576 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7577
2fa6e1e1 7578 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7579 || need_resched() || signal_pending(current)) {
6b7e2d09 7580 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7581 smp_wmb();
6c142801
AK		 7582 local_irq_enable();
7583 preempt_enable();
01b71917 7584 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7585 r = 1;
d905c069 7586 goto cancel_injection;
6c142801
AK		 7587 }
7588
fc5b7f3b
DM		 7589 kvm_load_guest_xcr0(vcpu);
7590
c43203ca
PB		 7591 if (req_immediate_exit) {
7592 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7593 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7594 }
d6185f20 7595
8b89fe1f 7596 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7597 if (lapic_timer_advance_ns)
7598 wait_lapic_expire(vcpu);
6edaa530 7599 guest_enter_irqoff();
b6c7a5dc 7600
42dbaa5a 7601 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7602 set_debugreg(0, 7);
7603 set_debugreg(vcpu->arch.eff_db[0], 0);
7604 set_debugreg(vcpu->arch.eff_db[1], 1);
7605 set_debugreg(vcpu->arch.eff_db[2], 2);
7606 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7607 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7608 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7609 }
b6c7a5dc 7610
851ba692 7611 kvm_x86_ops->run(vcpu);
b6c7a5dc 7612
c77fb5fe
PB		 7613 /*
7614 * Do this here before restoring debug registers on the host. And
7615 * since we do this before handling the vmexit, a DR access vmexit
7616 * can (a) read the correct value of the debug registers, (b) set
7617 * KVM_DEBUGREG_WONT_EXIT again.
7618 */
7619 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7620 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7621 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7622 kvm_update_dr0123(vcpu);
7623 kvm_update_dr6(vcpu);
7624 kvm_update_dr7(vcpu);
7625 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7626 }
7627
24f1e32c
FW		 7628 /*
7629 * If the guest has used debug registers, at least dr7
7630 * will be disabled while returning to the host.
7631 * If we don't have active breakpoints in the host, we don't
7632 * care about the messed up debug address registers. But if
7633 * we have some of them active, restore the old state.
7634 */
59d8eb53 7635 if (hw_breakpoint_active())
24f1e32c 7636 hw_breakpoint_restore();
42dbaa5a 7637
4ba76538 7638 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7639
6b7e2d09 7640 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7641 smp_wmb();
a547c6db 7642
fc5b7f3b
DM		 7643 kvm_put_guest_xcr0(vcpu);
7644
dd60d217 7645 kvm_before_interrupt(vcpu);
a547c6db 7646 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7647 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7648
7649 ++vcpu->stat.exits;
7650
f2485b3e 7651 guest_exit_irqoff();
b6c7a5dc 7652
f2485b3e 7653 local_irq_enable();
b6c7a5dc
HB		 7654 preempt_enable();
7655
f656ce01 7656 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7657
b6c7a5dc
HB		 7658 /*
7659 * Profile KVM exit RIPs:
7660 */
7661 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7662 unsigned long rip = kvm_rip_read(vcpu);
7663 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7664 }
7665
cc578287
ZA		 7666 if (unlikely(vcpu->arch.tsc_always_catchup))
7667 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7668
5cfb1d5a
MT		 7669 if (vcpu->arch.apic_attention)
7670 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7671
618232e2 7672 vcpu->arch.gpa_available = false;
851ba692 7673 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7674 return r;
7675
7676cancel_injection:
7677 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7678 if (unlikely(vcpu->arch.apic_attention))
7679 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7680out:
7681 return r;
7682}
b6c7a5dc 7683
362c698f
PB		 7684static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7685{
bf9f6ac8
FW		 7686 if (!kvm_arch_vcpu_runnable(vcpu) &&
7687 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7688 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7689 kvm_vcpu_block(vcpu);
7690 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7691
7692 if (kvm_x86_ops->post_block)
7693 kvm_x86_ops->post_block(vcpu);
7694
9c8fd1ba
PB		 7695 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7696 return 1;
7697 }
362c698f
PB		 7698
7699 kvm_apic_accept_events(vcpu);
7700 switch(vcpu->arch.mp_state) {
7701 case KVM_MP_STATE_HALTED:
7702 vcpu->arch.pv.pv_unhalted = false;
7703 vcpu->arch.mp_state =
7704 KVM_MP_STATE_RUNNABLE;
7705 case KVM_MP_STATE_RUNNABLE:
7706 vcpu->arch.apf.halted = false;
7707 break;
7708 case KVM_MP_STATE_INIT_RECEIVED:
7709 break;
7710 default:
7711 return -EINTR;
7712 break;
7713 }
7714 return 1;
7715}
09cec754 7716
5d9bc648
PB		 7717static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7718{
0ad3bed6
PB		 7719 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7720 kvm_x86_ops->check_nested_events(vcpu, false);
7721
5d9bc648
PB		 7722 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7723 !vcpu->arch.apf.halted);
7724}
7725
362c698f 7726static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7727{
7728 int r;
f656ce01 7729 struct kvm *kvm = vcpu->kvm;
d7690175 7730
f656ce01 7731 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 7732 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7733
362c698f 7734 for (;;) {
58f800d5 7735 if (kvm_vcpu_running(vcpu)) {
851ba692 7736 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7737 } else {
362c698f 7738 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7739 }
7740
09cec754
GN		 7741 if (r <= 0)
7742 break;
7743
72875d8a 7744 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7745 if (kvm_cpu_has_pending_timer(vcpu))
7746 kvm_inject_pending_timer_irqs(vcpu);
7747
782d422b
MG		 7748 if (dm_request_for_irq_injection(vcpu) &&
7749 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7750 r = 0;
7751 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7752 ++vcpu->stat.request_irq_exits;
362c698f 7753 break;
09cec754 7754 }
af585b92
GN		 7755
7756 kvm_check_async_pf_completion(vcpu);
7757
09cec754
GN		 7758 if (signal_pending(current)) {
7759 r = -EINTR;
851ba692 7760 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7761 ++vcpu->stat.signal_exits;
362c698f 7762 break;
09cec754
GN		 7763 }
7764 if (need_resched()) {
f656ce01 7765 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7766 cond_resched();
f656ce01 7767 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7768 }
b6c7a5dc
HB		 7769 }
7770
f656ce01 7771 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7772
7773 return r;
7774}
7775
716d51ab
GN		 7776static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7777{
7778 int r;
7779 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 7780 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 7781 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7782 if (r != EMULATE_DONE)
7783 return 0;
7784 return 1;
7785}
7786
7787static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7788{
7789 BUG_ON(!vcpu->arch.pio.count);
7790
7791 return complete_emulated_io(vcpu);
7792}
7793
f78146b0
AK		 7794/*
7795 * Implements the following, as a state machine:
7796 *
7797 * read:
7798 * for each fragment
87da7e66
XG		 7799 * for each mmio piece in the fragment
7800 * write gpa, len
7801 * exit
7802 * copy data
f78146b0
AK		 7803 * execute insn
7804 *
7805 * write:
7806 * for each fragment
87da7e66
XG		 7807 * for each mmio piece in the fragment
7808 * write gpa, len
7809 * copy data
7810 * exit
f78146b0 7811 */
716d51ab 7812static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7813{
7814 struct kvm_run *run = vcpu->run;
f78146b0 7815 struct kvm_mmio_fragment *frag;
87da7e66 7816 unsigned len;
5287f194 7817
716d51ab 7818 BUG_ON(!vcpu->mmio_needed);
5287f194 7819
716d51ab 7820 /* Complete previous fragment */
87da7e66
XG		 7821 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7822 len = min(8u, frag->len);
716d51ab 7823 if (!vcpu->mmio_is_write)
87da7e66
XG		 7824 memcpy(frag->data, run->mmio.data, len);
7825
7826 if (frag->len <= 8) {
7827 /* Switch to the next fragment. */
7828 frag++;
7829 vcpu->mmio_cur_fragment++;
7830 } else {
7831 /* Go forward to the next mmio piece. */
7832 frag->data += len;
7833 frag->gpa += len;
7834 frag->len -= len;
7835 }
7836
a08d3b3b 7837 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7838 vcpu->mmio_needed = 0;
0912c977
PB		 7839
7840 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7841 if (vcpu->mmio_is_write)
716d51ab
GN		 7842 return 1;
7843 vcpu->mmio_read_completed = 1;
7844 return complete_emulated_io(vcpu);
7845 }
87da7e66 7846
716d51ab
GN		 7847 run->exit_reason = KVM_EXIT_MMIO;
7848 run->mmio.phys_addr = frag->gpa;
7849 if (vcpu->mmio_is_write)
87da7e66
XG		 7850 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7851 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7852 run->mmio.is_write = vcpu->mmio_is_write;
7853 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7854 return 0;
5287f194
AK		 7855}
7856
822f312d
SAS		 7857/* Swap (qemu) user FPU context for the guest FPU context. */
7858static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7859{
7860 preempt_disable();
7861 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
7862 /* PKRU is separately restored in kvm_x86_ops->run. */
7863 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7864 ~XFEATURE_MASK_PKRU);
7865 preempt_enable();
7866 trace_kvm_fpu(1);
7867}
7868
7869/* When vcpu_run ends, restore user space FPU context. */
7870static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7871{
7872 preempt_disable();
7873 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7874 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7875 preempt_enable();
7876 ++vcpu->stat.fpu_reload;
7877 trace_kvm_fpu(0);
7878}
7879
b6c7a5dc
HB		 7880int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7881{
7882 int r;
b6c7a5dc 7883
accb757d 7884 vcpu_load(vcpu);
20b7035c 7885 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7886 kvm_load_guest_fpu(vcpu);
7887
a4535290 7888 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7889 if (kvm_run->immediate_exit) {
7890 r = -EINTR;
7891 goto out;
7892 }
b6c7a5dc 7893 kvm_vcpu_block(vcpu);
66450a21 7894 kvm_apic_accept_events(vcpu);
72875d8a 7895 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7896 r = -EAGAIN;
a0595000
JS		 7897 if (signal_pending(current)) {
7898 r = -EINTR;
7899 vcpu->run->exit_reason = KVM_EXIT_INTR;
7900 ++vcpu->stat.signal_exits;
7901 }
ac9f6dc0 7902 goto out;
b6c7a5dc
HB		 7903 }
7904
01643c51
KH		 7905 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7906 r = -EINVAL;
7907 goto out;
7908 }
7909
7910 if (vcpu->run->kvm_dirty_regs) {
7911 r = sync_regs(vcpu);
7912 if (r != 0)
7913 goto out;
7914 }
7915
b6c7a5dc 7916 /* re-sync apic's tpr */
35754c98 7917 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7918 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7919 r = -EINVAL;
7920 goto out;
7921 }
7922 }
b6c7a5dc 7923
716d51ab
GN		 7924 if (unlikely(vcpu->arch.complete_userspace_io)) {
7925 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7926 vcpu->arch.complete_userspace_io = NULL;
7927 r = cui(vcpu);
7928 if (r <= 0)
5663d8f9 7929 goto out;
716d51ab
GN		 7930 } else
7931 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7932
460df4c1
PB		 7933 if (kvm_run->immediate_exit)
7934 r = -EINTR;
7935 else
7936 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7937
7938out:
5663d8f9 7939 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7940 if (vcpu->run->kvm_valid_regs)
7941 store_regs(vcpu);
f1d86e46 7942 post_kvm_run_save(vcpu);
20b7035c 7943 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7944
accb757d 7945 vcpu_put(vcpu);
b6c7a5dc
HB		 7946 return r;
7947}
7948
01643c51 7949static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7950{
7ae441ea
GN		 7951 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7952 /*
7953 * We are here if userspace calls get_regs() in the middle of
7954 * instruction emulation. Registers state needs to be copied
4a969980 7955 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7956 * that usually, but some bad designed PV devices (vmware
7957 * backdoor interface) need this to work
7958 */
dd856efa 7959 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7960 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7961 }
5fdbf976
MT		 7962 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7963 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7964 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7965 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7966 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7967 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7968 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7969 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7970#ifdef CONFIG_X86_64
5fdbf976
MT		 7971 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7972 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7973 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7974 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7975 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7976 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7977 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7978 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7979#endif
7980
5fdbf976 7981 regs->rip = kvm_rip_read(vcpu);
91586a3b 7982 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7983}
b6c7a5dc 7984
01643c51
KH		 7985int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7986{
7987 vcpu_load(vcpu);
7988 __get_regs(vcpu, regs);
1fc9b76b 7989 vcpu_put(vcpu);
b6c7a5dc
HB		 7990 return 0;
7991}
7992
01643c51 7993static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7994{
7ae441ea
GN		 7995 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7996 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7997
5fdbf976
MT		 7998 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7999 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8000 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8001 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8002 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8003 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8004 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8005 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 8006#ifdef CONFIG_X86_64
5fdbf976
MT		 8007 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8008 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8009 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8010 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8011 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8012 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8013 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8014 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 8015#endif
8016
5fdbf976 8017 kvm_rip_write(vcpu, regs->rip);
d73235d1 8018 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8019
b4f14abd
JK		 8020 vcpu->arch.exception.pending = false;
8021
3842d135 8022 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8023}
3842d135 8024
01643c51
KH		 8025int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8026{
8027 vcpu_load(vcpu);
8028 __set_regs(vcpu, regs);
875656fe 8029 vcpu_put(vcpu);
b6c7a5dc
HB		 8030 return 0;
8031}
8032
b6c7a5dc
HB		 8033void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8034{
8035 struct kvm_segment cs;
8036
3e6e0aab 8037 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8038 *db = cs.db;
8039 *l = cs.l;
8040}
8041EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8042
01643c51 8043static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8044{
89a27f4d 8045 struct desc_ptr dt;
b6c7a5dc 8046
3e6e0aab
GT		 8047 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8048 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8049 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8050 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8051 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8052 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8053
3e6e0aab
GT		 8054 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8055 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8056
8057 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8058 sregs->idt.limit = dt.size;
8059 sregs->idt.base = dt.address;
b6c7a5dc 8060 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8061 sregs->gdt.limit = dt.size;
8062 sregs->gdt.base = dt.address;
b6c7a5dc 8063
4d4ec087 8064 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8065 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8066 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8067 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8068 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8069 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8070 sregs->apic_base = kvm_get_apic_base(vcpu);
8071
923c61bb 8072 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 8073
04140b41 8074 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8075 set_bit(vcpu->arch.interrupt.nr,
8076 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8077}
16d7a191 8078
01643c51
KH		 8079int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8080 struct kvm_sregs *sregs)
8081{
8082 vcpu_load(vcpu);
8083 __get_sregs(vcpu, sregs);
bcdec41c 8084 vcpu_put(vcpu);
b6c7a5dc
HB		 8085 return 0;
8086}
8087
62d9f0db
MT		 8088int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8089 struct kvm_mp_state *mp_state)
8090{
fd232561
CD		 8091 vcpu_load(vcpu);
8092
66450a21 8093 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8094 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8095 vcpu->arch.pv.pv_unhalted)
8096 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8097 else
8098 mp_state->mp_state = vcpu->arch.mp_state;
8099
fd232561 8100 vcpu_put(vcpu);
62d9f0db
MT		 8101 return 0;
8102}
8103
8104int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8105 struct kvm_mp_state *mp_state)
8106{
e83dff5e
CD		 8107 int ret = -EINVAL;
8108
8109 vcpu_load(vcpu);
8110
bce87cce 8111 if (!lapic_in_kernel(vcpu) &&
66450a21 8112 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8113 goto out;
66450a21 8114
28bf2888
DH		 8115 /* INITs are latched while in SMM */
8116 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8117 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8118 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8119 goto out;
28bf2888 8120
66450a21
JK		 8121 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8122 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8123 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8124 } else
8125 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8126 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8127
8128 ret = 0;
8129out:
8130 vcpu_put(vcpu);
8131 return ret;
62d9f0db
MT		 8132}
8133
7f3d35fd
KW		 8134int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8135 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8136{
9d74191a 8137 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8138 int ret;
e01c2426 8139
8ec4722d 8140 init_emulate_ctxt(vcpu);
c697518a 8141
7f3d35fd 8142 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8143 has_error_code, error_code);
c697518a 8144
c697518a 8145 if (ret)
19d04437 8146 return EMULATE_FAIL;
37817f29 8147
9d74191a
TY		 8148 kvm_rip_write(vcpu, ctxt->eip);
8149 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8150 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8151 return EMULATE_DONE;
37817f29
IE		 8152}
8153EXPORT_SYMBOL_GPL(kvm_task_switch);
8154
3140c156 8155static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8156{
74fec5b9
TL		 8157 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8158 (sregs->cr4 & X86_CR4_OSXSAVE))
8159 return -EINVAL;
8160
37b95951 8161 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8162 /*
8163 * When EFER.LME and CR0.PG are set, the processor is in
8164 * 64-bit mode (though maybe in a 32-bit code segment).
8165 * CR4.PAE and EFER.LMA must be set.
8166 */
37b95951 8167 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8168 || !(sregs->efer & EFER_LMA))
8169 return -EINVAL;
8170 } else {
8171 /*
8172 * Not in 64-bit mode: EFER.LMA is clear and the code
8173 * segment cannot be 64-bit.
8174 */
8175 if (sregs->efer & EFER_LMA || sregs->cs.l)
8176 return -EINVAL;
8177 }
8178
8179 return 0;
8180}
8181
01643c51 8182static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8183{
58cb628d 8184 struct msr_data apic_base_msr;
b6c7a5dc 8185 int mmu_reset_needed = 0;
c4d21882 8186 int cpuid_update_needed = 0;
63f42e02 8187 int pending_vec, max_bits, idx;
89a27f4d 8188 struct desc_ptr dt;
b4ef9d4e
CD		 8189 int ret = -EINVAL;
8190
f2981033 8191 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8192 goto out;
f2981033 8193
d3802286
JM		 8194 apic_base_msr.data = sregs->apic_base;
8195 apic_base_msr.host_initiated = true;
8196 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8197 goto out;
6d1068b3 8198
89a27f4d
GN		 8199 dt.size = sregs->idt.limit;
8200 dt.address = sregs->idt.base;
b6c7a5dc 8201 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8202 dt.size = sregs->gdt.limit;
8203 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8204 kvm_x86_ops->set_gdt(vcpu, &dt);
8205
ad312c7c 8206 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8207 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8208 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8209 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8210
2d3ad1f4 8211 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8212
f6801dff 8213 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8214 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8215
4d4ec087 8216 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8217 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8218 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8219
fc78f519 8220 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8221 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8222 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8223 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8224 if (cpuid_update_needed)
00b27a3e 8225 kvm_update_cpuid(vcpu);
63f42e02
XG		 8226
8227 idx = srcu_read_lock(&vcpu->kvm->srcu);
d35b34a9 8228 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
9f8fe504 8229 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8230 mmu_reset_needed = 1;
8231 }
63f42e02 8232 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8233
8234 if (mmu_reset_needed)
8235 kvm_mmu_reset_context(vcpu);
8236
a50abc3b 8237 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8238 pending_vec = find_first_bit(
8239 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8240 if (pending_vec < max_bits) {
66fd3f7f 8241 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8242 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8243 }
8244
3e6e0aab
GT		 8245 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8246 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8247 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8248 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8249 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8250 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8251
3e6e0aab
GT		 8252 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8253 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8254
5f0269f5
ME		 8255 update_cr8_intercept(vcpu);
8256
9c3e4aab 8257 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8258 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8259 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8260 !is_protmode(vcpu))
9c3e4aab
MT		 8261 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8262
3842d135
AK		 8263 kvm_make_request(KVM_REQ_EVENT, vcpu);
8264
b4ef9d4e
CD		 8265 ret = 0;
8266out:
01643c51
KH		 8267 return ret;
8268}
8269
8270int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8271 struct kvm_sregs *sregs)
8272{
8273 int ret;
8274
8275 vcpu_load(vcpu);
8276 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8277 vcpu_put(vcpu);
8278 return ret;
b6c7a5dc
HB		 8279}
8280
d0bfb940
JK		 8281int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8282 struct kvm_guest_debug *dbg)
b6c7a5dc 8283{
355be0b9 8284 unsigned long rflags;
ae675ef0 8285 int i, r;
b6c7a5dc 8286
66b56562
CD		 8287 vcpu_load(vcpu);
8288
4f926bf2
JK		 8289 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8290 r = -EBUSY;
8291 if (vcpu->arch.exception.pending)
2122ff5e 8292 goto out;
4f926bf2
JK		 8293 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8294 kvm_queue_exception(vcpu, DB_VECTOR);
8295 else
8296 kvm_queue_exception(vcpu, BP_VECTOR);
8297 }
8298
91586a3b
JK		 8299 /*
8300 * Read rflags as long as potentially injected trace flags are still
8301 * filtered out.
8302 */
8303 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8304
8305 vcpu->guest_debug = dbg->control;
8306 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8307 vcpu->guest_debug = 0;
8308
8309 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8310 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8311 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8312 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8313 } else {
8314 for (i = 0; i < KVM_NR_DB_REGS; i++)
8315 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8316 }
c8639010 8317 kvm_update_dr7(vcpu);
ae675ef0 8318
f92653ee
JK		 8319 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8320 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8321 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8322
91586a3b
JK		 8323 /*
8324 * Trigger an rflags update that will inject or remove the trace
8325 * flags.
8326 */
8327 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8328
a96036b8 8329 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8330
4f926bf2 8331 r = 0;
d0bfb940 8332
2122ff5e 8333out:
66b56562 8334 vcpu_put(vcpu);
b6c7a5dc
HB		 8335 return r;
8336}
8337
8b006791
ZX		 8338/*
8339 * Translate a guest virtual address to a guest physical address.
8340 */
8341int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8342 struct kvm_translation *tr)
8343{
8344 unsigned long vaddr = tr->linear_address;
8345 gpa_t gpa;
f656ce01 8346 int idx;
8b006791 8347
1da5b61d
CD		 8348 vcpu_load(vcpu);
8349
f656ce01 8350 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8351 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8352 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8353 tr->physical_address = gpa;
8354 tr->valid = gpa != UNMAPPED_GVA;
8355 tr->writeable = 1;
8356 tr->usermode = 0;
8b006791 8357
1da5b61d 8358 vcpu_put(vcpu);
8b006791
ZX		 8359 return 0;
8360}
8361
d0752060
HB		 8362int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8363{
1393123e 8364 struct fxregs_state *fxsave;
d0752060 8365
1393123e 8366 vcpu_load(vcpu);
d0752060 8367
1393123e 8368 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8369 memcpy(fpu->fpr, fxsave->st_space, 128);
8370 fpu->fcw = fxsave->cwd;
8371 fpu->fsw = fxsave->swd;
8372 fpu->ftwx = fxsave->twd;
8373 fpu->last_opcode = fxsave->fop;
8374 fpu->last_ip = fxsave->rip;
8375 fpu->last_dp = fxsave->rdp;
8376 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8377
1393123e 8378 vcpu_put(vcpu);
d0752060
HB		 8379 return 0;
8380}
8381
8382int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8383{
6a96bc7f
CD		 8384 struct fxregs_state *fxsave;
8385
8386 vcpu_load(vcpu);
8387
8388 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8389
d0752060
HB		 8390 memcpy(fxsave->st_space, fpu->fpr, 128);
8391 fxsave->cwd = fpu->fcw;
8392 fxsave->swd = fpu->fsw;
8393 fxsave->twd = fpu->ftwx;
8394 fxsave->fop = fpu->last_opcode;
8395 fxsave->rip = fpu->last_ip;
8396 fxsave->rdp = fpu->last_dp;
8397 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8398
6a96bc7f 8399 vcpu_put(vcpu);
d0752060
HB		 8400 return 0;
8401}
8402
01643c51
KH		 8403static void store_regs(struct kvm_vcpu *vcpu)
8404{
8405 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8406
8407 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8408 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8409
8410 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8411 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8412
8413 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8414 kvm_vcpu_ioctl_x86_get_vcpu_events(
8415 vcpu, &vcpu->run->s.regs.events);
8416}
8417
8418static int sync_regs(struct kvm_vcpu *vcpu)
8419{
8420 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8421 return -EINVAL;
8422
8423 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8424 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8425 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8426 }
8427 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8428 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8429 return -EINVAL;
8430 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8431 }
8432 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8433 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8434 vcpu, &vcpu->run->s.regs.events))
8435 return -EINVAL;
8436 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8437 }
8438
8439 return 0;
8440}
8441
0ee6a517 8442static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8443{
bf935b0b 8444 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8445 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8446 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8447 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8448
2acf923e
DC		 8449 /*
8450 * Ensure guest xcr0 is valid for loading
8451 */
d91cab78 8452 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8453
ad312c7c 8454 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8455}
d0752060 8456
e9b11c17
ZX		 8457void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8458{
bd768e14
IY		 8459 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8460
12f9a48f 8461 kvmclock_reset(vcpu);
7f1ea208 8462
e9b11c17 8463 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8464 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8465}
8466
8467struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8468 unsigned int id)
8469{
c447e76b
LL		 8470 struct kvm_vcpu *vcpu;
8471
b0c39dc6 8472 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8473 printk_once(KERN_WARNING
8474 "kvm: SMP vm created on host with unstable TSC; "
8475 "guest TSC will not be reliable\n");
c447e76b
LL		 8476
8477 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8478
c447e76b 8479 return vcpu;
26e5215f 8480}
e9b11c17 8481
26e5215f
AK		 8482int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8483{
19efffa2 8484 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8485 vcpu_load(vcpu);
d28bc9dd 8486 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8487 kvm_mmu_setup(vcpu);
e9b11c17 8488 vcpu_put(vcpu);
ec7660cc 8489 return 0;
e9b11c17
ZX		 8490}
8491
31928aa5 8492void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8493{
8fe8ab46 8494 struct msr_data msr;
332967a3 8495 struct kvm *kvm = vcpu->kvm;
42897d86 8496
d3457c87
RK		 8497 kvm_hv_vcpu_postcreate(vcpu);
8498
ec7660cc 8499 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8500 return;
ec7660cc 8501 vcpu_load(vcpu);
8fe8ab46
WA		 8502 msr.data = 0x0;
8503 msr.index = MSR_IA32_TSC;
8504 msr.host_initiated = true;
8505 kvm_write_tsc(vcpu, &msr);
42897d86 8506 vcpu_put(vcpu);
ec7660cc 8507 mutex_unlock(&vcpu->mutex);
42897d86 8508
630994b3
MT		 8509 if (!kvmclock_periodic_sync)
8510 return;
8511
332967a3
AJ		 8512 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8513 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8514}
8515
d40ccc62 8516void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8517{
344d9588
GN		 8518 vcpu->arch.apf.msr_val = 0;
8519
ec7660cc 8520 vcpu_load(vcpu);
e9b11c17
ZX		 8521 kvm_mmu_unload(vcpu);
8522 vcpu_put(vcpu);
8523
8524 kvm_x86_ops->vcpu_free(vcpu);
8525}
8526
d28bc9dd 8527void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8528{
b7e31be3
RK		 8529 kvm_lapic_reset(vcpu, init_event);
8530
e69fab5d
PB		 8531 vcpu->arch.hflags = 0;
8532
c43203ca 8533 vcpu->arch.smi_pending = 0;
52797bf9 8534 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8535 atomic_set(&vcpu->arch.nmi_queued, 0);
8536 vcpu->arch.nmi_pending = 0;
448fa4a9 8537 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8538 kvm_clear_interrupt_queue(vcpu);
8539 kvm_clear_exception_queue(vcpu);
664f8e26 8540 vcpu->arch.exception.pending = false;
448fa4a9 8541
42dbaa5a 8542 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8543 kvm_update_dr0123(vcpu);
6f43ed01 8544 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8545 kvm_update_dr6(vcpu);
42dbaa5a 8546 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8547 kvm_update_dr7(vcpu);
42dbaa5a 8548
1119022c
NA		 8549 vcpu->arch.cr2 = 0;
8550
3842d135 8551 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8552 vcpu->arch.apf.msr_val = 0;
c9aaa895 8553 vcpu->arch.st.msr_val = 0;
3842d135 8554
12f9a48f
GC		 8555 kvmclock_reset(vcpu);
8556
af585b92
GN		 8557 kvm_clear_async_pf_completion_queue(vcpu);
8558 kvm_async_pf_hash_reset(vcpu);
8559 vcpu->arch.apf.halted = false;
3842d135 8560
a554d207
WL		 8561 if (kvm_mpx_supported()) {
8562 void *mpx_state_buffer;
8563
8564 /*
8565 * To avoid have the INIT path from kvm_apic_has_events() that be
8566 * called with loaded FPU and does not let userspace fix the state.
8567 */
f775b13e
RR		 8568 if (init_event)
8569 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8570 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8571 XFEATURE_MASK_BNDREGS);
8572 if (mpx_state_buffer)
8573 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8574 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8575 XFEATURE_MASK_BNDCSR);
8576 if (mpx_state_buffer)
8577 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8578 if (init_event)
8579 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8580 }
8581
64d60670 8582 if (!init_event) {
d28bc9dd 8583 kvm_pmu_reset(vcpu);
64d60670 8584 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8585
8586 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8587 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8588
8589 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8590 }
f5132b01 8591
66f7b72e
JS		 8592 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8593 vcpu->arch.regs_avail = ~0;
8594 vcpu->arch.regs_dirty = ~0;
8595
a554d207
WL		 8596 vcpu->arch.ia32_xss = 0;
8597
d28bc9dd 8598 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8599}
8600
2b4a273b 8601void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8602{
8603 struct kvm_segment cs;
8604
8605 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8606 cs.selector = vector << 8;
8607 cs.base = vector << 12;
8608 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8609 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8610}
8611
13a34e06 8612int kvm_arch_hardware_enable(void)
e9b11c17 8613{
ca84d1a2
ZA		 8614 struct kvm *kvm;
8615 struct kvm_vcpu *vcpu;
8616 int i;
0dd6a6ed
ZA		 8617 int ret;
8618 u64 local_tsc;
8619 u64 max_tsc = 0;
8620 bool stable, backwards_tsc = false;
18863bdd
AK		 8621
8622 kvm_shared_msr_cpu_online();
13a34e06 8623 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8624 if (ret != 0)
8625 return ret;
8626
4ea1636b 8627 local_tsc = rdtsc();
b0c39dc6 8628 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8629 list_for_each_entry(kvm, &vm_list, vm_list) {
8630 kvm_for_each_vcpu(i, vcpu, kvm) {
8631 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8632 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8633 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8634 backwards_tsc = true;
8635 if (vcpu->arch.last_host_tsc > max_tsc)
8636 max_tsc = vcpu->arch.last_host_tsc;
8637 }
8638 }
8639 }
8640
8641 /*
8642 * Sometimes, even reliable TSCs go backwards. This happens on
8643 * platforms that reset TSC during suspend or hibernate actions, but
8644 * maintain synchronization. We must compensate. Fortunately, we can
8645 * detect that condition here, which happens early in CPU bringup,
8646 * before any KVM threads can be running. Unfortunately, we can't
8647 * bring the TSCs fully up to date with real time, as we aren't yet far
8648 * enough into CPU bringup that we know how much real time has actually
108b249c 8649 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8650 * variables that haven't been updated yet.
8651 *
8652 * So we simply find the maximum observed TSC above, then record the
8653 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8654 * the adjustment will be applied. Note that we accumulate
8655 * adjustments, in case multiple suspend cycles happen before some VCPU
8656 * gets a chance to run again. In the event that no KVM threads get a
8657 * chance to run, we will miss the entire elapsed period, as we'll have
8658 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8659 * loose cycle time. This isn't too big a deal, since the loss will be
8660 * uniform across all VCPUs (not to mention the scenario is extremely
8661 * unlikely). It is possible that a second hibernate recovery happens
8662 * much faster than a first, causing the observed TSC here to be
8663 * smaller; this would require additional padding adjustment, which is
8664 * why we set last_host_tsc to the local tsc observed here.
8665 *
8666 * N.B. - this code below runs only on platforms with reliable TSC,
8667 * as that is the only way backwards_tsc is set above. Also note
8668 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8669 * have the same delta_cyc adjustment applied if backwards_tsc
8670 * is detected. Note further, this adjustment is only done once,
8671 * as we reset last_host_tsc on all VCPUs to stop this from being
8672 * called multiple times (one for each physical CPU bringup).
8673 *
4a969980 8674 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8675 * will be compensated by the logic in vcpu_load, which sets the TSC to
8676 * catchup mode. This will catchup all VCPUs to real time, but cannot
8677 * guarantee that they stay in perfect synchronization.
8678 */
8679 if (backwards_tsc) {
8680 u64 delta_cyc = max_tsc - local_tsc;
8681 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8682 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8683 kvm_for_each_vcpu(i, vcpu, kvm) {
8684 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8685 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8686 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8687 }
8688
8689 /*
8690 * We have to disable TSC offset matching.. if you were
8691 * booting a VM while issuing an S4 host suspend....
8692 * you may have some problem. Solving this issue is
8693 * left as an exercise to the reader.
8694 */
8695 kvm->arch.last_tsc_nsec = 0;
8696 kvm->arch.last_tsc_write = 0;
8697 }
8698
8699 }
8700 return 0;
e9b11c17
ZX		 8701}
8702
13a34e06 8703void kvm_arch_hardware_disable(void)
e9b11c17 8704{
13a34e06
RK		 8705 kvm_x86_ops->hardware_disable();
8706 drop_user_return_notifiers();
e9b11c17
ZX		 8707}
8708
8709int kvm_arch_hardware_setup(void)
8710{
9e9c3fe4
NA		 8711 int r;
8712
8713 r = kvm_x86_ops->hardware_setup();
8714 if (r != 0)
8715 return r;
8716
35181e86
HZ		 8717 if (kvm_has_tsc_control) {
8718 /*
8719 * Make sure the user can only configure tsc_khz values that
8720 * fit into a signed integer.
273ba457 8721 * A min value is not calculated because it will always
35181e86
HZ		 8722 * be 1 on all machines.
8723 */
8724 u64 max = min(0x7fffffffULL,
8725 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8726 kvm_max_guest_tsc_khz = max;
8727
ad721883 8728 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8729 }
ad721883 8730
9e9c3fe4
NA		 8731 kvm_init_msr_list();
8732 return 0;
e9b11c17
ZX		 8733}
8734
8735void kvm_arch_hardware_unsetup(void)
8736{
8737 kvm_x86_ops->hardware_unsetup();
8738}
8739
8740void kvm_arch_check_processor_compat(void *rtn)
8741{
8742 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8743}
8744
8745bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8746{
8747 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8748}
8749EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8750
8751bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8752{
8753 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8754}
8755
54e9818f 8756struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8757EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8758
e9b11c17
ZX		 8759int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8760{
8761 struct page *page;
e9b11c17
ZX		 8762 int r;
8763
b2a05fef 8764 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8765 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8766 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8767 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8768 else
a4535290 8769 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8770
8771 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8772 if (!page) {
8773 r = -ENOMEM;
8774 goto fail;
8775 }
ad312c7c 8776 vcpu->arch.pio_data = page_address(page);
e9b11c17 8777
cc578287 8778 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8779
e9b11c17
ZX		 8780 r = kvm_mmu_create(vcpu);
8781 if (r < 0)
8782 goto fail_free_pio_data;
8783
26de7988 8784 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8785 r = kvm_create_lapic(vcpu);
8786 if (r < 0)
8787 goto fail_mmu_destroy;
54e9818f
GN		 8788 } else
8789 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8790
890ca9ae
HY		 8791 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8792 GFP_KERNEL);
8793 if (!vcpu->arch.mce_banks) {
8794 r = -ENOMEM;
443c39bc 8795 goto fail_free_lapic;
890ca9ae
HY		 8796 }
8797 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8798
f1797359
WY		 8799 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8800 r = -ENOMEM;
f5f48ee1 8801 goto fail_free_mce_banks;
f1797359 8802 }
f5f48ee1 8803
0ee6a517 8804 fx_init(vcpu);
66f7b72e 8805
4344ee98 8806 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8807
5a4f55cd
EK		 8808 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8809
74545705
RK		 8810 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8811
af585b92 8812 kvm_async_pf_hash_reset(vcpu);
f5132b01 8813 kvm_pmu_init(vcpu);
af585b92 8814
1c1a9ce9 8815 vcpu->arch.pending_external_vector = -1;
de63ad4c 8816 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8817
5c919412
AS		 8818 kvm_hv_vcpu_init(vcpu);
8819
e9b11c17 8820 return 0;
0ee6a517 8821
f5f48ee1
SY		 8822fail_free_mce_banks:
8823 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8824fail_free_lapic:
8825 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8826fail_mmu_destroy:
8827 kvm_mmu_destroy(vcpu);
8828fail_free_pio_data:
ad312c7c 8829 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8830fail:
8831 return r;
8832}
8833
8834void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8835{
f656ce01
MT		 8836 int idx;
8837
1f4b34f8 8838 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8839 kvm_pmu_destroy(vcpu);
36cb93fd 8840 kfree(vcpu->arch.mce_banks);
e9b11c17 8841 kvm_free_lapic(vcpu);
f656ce01 8842 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8843 kvm_mmu_destroy(vcpu);
f656ce01 8844 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8845 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8846 if (!lapic_in_kernel(vcpu))
54e9818f 8847 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8848}
d19a9cd2 8849
e790d9ef
RK		 8850void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8851{
c595ceee 8852 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 8853 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8854}
8855
e08b9637 8856int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8857{
e08b9637
CO		 8858 if (type)
8859 return -EINVAL;
8860
6ef768fa 8861 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8862 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8863 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8864 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8865 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8866
5550af4d
SY		 8867 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8868 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8869 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8870 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8871 &kvm->arch.irq_sources_bitmap);
5550af4d 8872
038f8c11 8873 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8874 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8875 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8876
108b249c 8877 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8878 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8879
6fbbde9a
DS		 8880 kvm->arch.guest_can_read_msr_platform_info = true;
8881
7e44e449 8882 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8883 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8884
cbc0236a 8885 kvm_hv_init_vm(kvm);
0eb05bf2 8886 kvm_page_track_init(kvm);
13d268ca 8887 kvm_mmu_init_vm(kvm);
0eb05bf2 8888
03543133
SS		 8889 if (kvm_x86_ops->vm_init)
8890 return kvm_x86_ops->vm_init(kvm);
8891
d89f5eff 8892 return 0;
d19a9cd2
ZX		 8893}
8894
8895static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8896{
ec7660cc 8897 vcpu_load(vcpu);
d19a9cd2
ZX		 8898 kvm_mmu_unload(vcpu);
8899 vcpu_put(vcpu);
8900}
8901
8902static void kvm_free_vcpus(struct kvm *kvm)
8903{
8904 unsigned int i;
988a2cae 8905 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8906
8907 /*
8908 * Unpin any mmu pages first.
8909 */
af585b92
GN		 8910 kvm_for_each_vcpu(i, vcpu, kvm) {
8911 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8912 kvm_unload_vcpu_mmu(vcpu);
af585b92 8913 }
988a2cae
GN		 8914 kvm_for_each_vcpu(i, vcpu, kvm)
8915 kvm_arch_vcpu_free(vcpu);
8916
8917 mutex_lock(&kvm->lock);
8918 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8919 kvm->vcpus[i] = NULL;
d19a9cd2 8920
988a2cae
GN		 8921 atomic_set(&kvm->online_vcpus, 0);
8922 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8923}
8924
ad8ba2cd
SY		 8925void kvm_arch_sync_events(struct kvm *kvm)
8926{
332967a3 8927 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8928 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8929 kvm_free_pit(kvm);
ad8ba2cd
SY		 8930}
8931
1d8007bd 8932int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8933{
8934 int i, r;
25188b99 8935 unsigned long hva;
f0d648bd
PB		 8936 struct kvm_memslots *slots = kvm_memslots(kvm);
8937 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8938
8939 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8940 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8941 return -EINVAL;
9da0e4d5 8942
f0d648bd
PB		 8943 slot = id_to_memslot(slots, id);
8944 if (size) {
b21629da 8945 if (slot->npages)
f0d648bd
PB		 8946 return -EEXIST;
8947
8948 /*
8949 * MAP_SHARED to prevent internal slot pages from being moved
8950 * by fork()/COW.
8951 */
8952 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8953 MAP_SHARED | MAP_ANONYMOUS, 0);
8954 if (IS_ERR((void *)hva))
8955 return PTR_ERR((void *)hva);
8956 } else {
8957 if (!slot->npages)
8958 return 0;
8959
8960 hva = 0;
8961 }
8962
8963 old = *slot;
9da0e4d5 8964 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8965 struct kvm_userspace_memory_region m;
9da0e4d5 8966
1d8007bd
PB		 8967 m.slot = id | (i << 16);
8968 m.flags = 0;
8969 m.guest_phys_addr = gpa;
f0d648bd 8970 m.userspace_addr = hva;
1d8007bd 8971 m.memory_size = size;
9da0e4d5
PB		 8972 r = __kvm_set_memory_region(kvm, &m);
8973 if (r < 0)
8974 return r;
8975 }
8976
103c763c
EB		 8977 if (!size)
8978 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8979
9da0e4d5
PB		 8980 return 0;
8981}
8982EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8983
1d8007bd 8984int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8985{
8986 int r;
8987
8988 mutex_lock(&kvm->slots_lock);
1d8007bd 8989 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8990 mutex_unlock(&kvm->slots_lock);
8991
8992 return r;
8993}
8994EXPORT_SYMBOL_GPL(x86_set_memory_region);
8995
d19a9cd2
ZX		 8996void kvm_arch_destroy_vm(struct kvm *kvm)
8997{
27469d29
AH		 8998 if (current->mm == kvm->mm) {
8999 /*
9000 * Free memory regions allocated on behalf of userspace,
9001 * unless the the memory map has changed due to process exit
9002 * or fd copying.
9003 */
1d8007bd
PB		 9004 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9005 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9006 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9007 }
03543133
SS		 9008 if (kvm_x86_ops->vm_destroy)
9009 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9010 kvm_pic_destroy(kvm);
9011 kvm_ioapic_destroy(kvm);
d19a9cd2 9012 kvm_free_vcpus(kvm);
af1bae54 9013 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 9014 kvm_mmu_uninit_vm(kvm);
2beb6dad 9015 kvm_page_track_cleanup(kvm);
cbc0236a 9016 kvm_hv_destroy_vm(kvm);
d19a9cd2 9017}
0de10343 9018
5587027c 9019void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9020 struct kvm_memory_slot *dont)
9021{
9022 int i;
9023
d89cc617
TY		 9024 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9025 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9026 kvfree(free->arch.rmap[i]);
d89cc617 9027 free->arch.rmap[i] = NULL;
77d11309 9028 }
d89cc617
TY		 9029 if (i == 0)
9030 continue;
9031
9032 if (!dont || free->arch.lpage_info[i - 1] !=
9033 dont->arch.lpage_info[i - 1]) {
548ef284 9034 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9035 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9036 }
9037 }
21ebbeda
XG		 9038
9039 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9040}
9041
5587027c
AK		 9042int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9043 unsigned long npages)
db3fe4eb
TY		 9044{
9045 int i;
9046
d89cc617 9047 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9048 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9049 unsigned long ugfn;
9050 int lpages;
d89cc617 9051 int level = i + 1;
db3fe4eb
TY		 9052
9053 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9054 slot->base_gfn, level) + 1;
9055
d89cc617 9056 slot->arch.rmap[i] =
778e1cdd
KC		 9057 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9058 GFP_KERNEL);
d89cc617 9059 if (!slot->arch.rmap[i])
77d11309 9060 goto out_free;
d89cc617
TY		 9061 if (i == 0)
9062 continue;
77d11309 9063
778e1cdd 9064 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
92f94f1e 9065 if (!linfo)
db3fe4eb
TY		 9066 goto out_free;
9067
92f94f1e
XG		 9068 slot->arch.lpage_info[i - 1] = linfo;
9069
db3fe4eb 9070 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9071 linfo[0].disallow_lpage = 1;
db3fe4eb 9072 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9073 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9074 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9075 /*
9076 * If the gfn and userspace address are not aligned wrt each
9077 * other, or if explicitly asked to, disable large page
9078 * support for this slot
9079 */
9080 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9081 !kvm_largepages_enabled()) {
9082 unsigned long j;
9083
9084 for (j = 0; j < lpages; ++j)
92f94f1e 9085 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9086 }
9087 }
9088
21ebbeda
XG		 9089 if (kvm_page_track_create_memslot(slot, npages))
9090 goto out_free;
9091
db3fe4eb
TY		 9092 return 0;
9093
9094out_free:
d89cc617 9095 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9096 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9097 slot->arch.rmap[i] = NULL;
9098 if (i == 0)
9099 continue;
9100
548ef284 9101 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9102 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9103 }
9104 return -ENOMEM;
9105}
9106
15f46015 9107void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 9108{
e6dff7d1
TY		 9109 /*
9110 * memslots->generation has been incremented.
9111 * mmio generation may have reached its maximum value.
9112 */
54bf36aa 9113 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 9114}
9115
f7784b8e
MT		 9116int kvm_arch_prepare_memory_region(struct kvm *kvm,
9117 struct kvm_memory_slot *memslot,
09170a49 9118 const struct kvm_userspace_memory_region *mem,
7b6195a9 9119 enum kvm_mr_change change)
0de10343 9120{
f7784b8e
MT		 9121 return 0;
9122}
9123
88178fd4
KH		 9124static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9125 struct kvm_memory_slot *new)
9126{
9127 /* Still write protect RO slot */
9128 if (new->flags & KVM_MEM_READONLY) {
9129 kvm_mmu_slot_remove_write_access(kvm, new);
9130 return;
9131 }
9132
9133 /*
9134 * Call kvm_x86_ops dirty logging hooks when they are valid.
9135 *
9136 * kvm_x86_ops->slot_disable_log_dirty is called when:
9137 *
9138 * - KVM_MR_CREATE with dirty logging is disabled
9139 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9140 *
9141 * The reason is, in case of PML, we need to set D-bit for any slots
9142 * with dirty logging disabled in order to eliminate unnecessary GPA
9143 * logging in PML buffer (and potential PML buffer full VMEXT). This
9144 * guarantees leaving PML enabled during guest's lifetime won't have
9145 * any additonal overhead from PML when guest is running with dirty
9146 * logging disabled for memory slots.
9147 *
9148 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9149 * to dirty logging mode.
9150 *
9151 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9152 *
9153 * In case of write protect:
9154 *
9155 * Write protect all pages for dirty logging.
9156 *
9157 * All the sptes including the large sptes which point to this
9158 * slot are set to readonly. We can not create any new large
9159 * spte on this slot until the end of the logging.
9160 *
9161 * See the comments in fast_page_fault().
9162 */
9163 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9164 if (kvm_x86_ops->slot_enable_log_dirty)
9165 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9166 else
9167 kvm_mmu_slot_remove_write_access(kvm, new);
9168 } else {
9169 if (kvm_x86_ops->slot_disable_log_dirty)
9170 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9171 }
9172}
9173
f7784b8e 9174void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9175 const struct kvm_userspace_memory_region *mem,
8482644a 9176 const struct kvm_memory_slot *old,
f36f3f28 9177 const struct kvm_memory_slot *new,
8482644a 9178 enum kvm_mr_change change)
f7784b8e 9179{
8482644a 9180 int nr_mmu_pages = 0;
f7784b8e 9181
48c0e4e9
XG		 9182 if (!kvm->arch.n_requested_mmu_pages)
9183 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9184
48c0e4e9 9185 if (nr_mmu_pages)
0de10343 9186 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9187
3ea3b7fa
WL		 9188 /*
9189 * Dirty logging tracks sptes in 4k granularity, meaning that large
9190 * sptes have to be split. If live migration is successful, the guest
9191 * in the source machine will be destroyed and large sptes will be
9192 * created in the destination. However, if the guest continues to run
9193 * in the source machine (for example if live migration fails), small
9194 * sptes will remain around and cause bad performance.
9195 *
9196 * Scan sptes if dirty logging has been stopped, dropping those
9197 * which can be collapsed into a single large-page spte. Later
9198 * page faults will create the large-page sptes.
9199 */
9200 if ((change != KVM_MR_DELETE) &&
9201 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9202 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9203 kvm_mmu_zap_collapsible_sptes(kvm, new);
9204
c972f3b1 9205 /*
88178fd4 9206 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9207 *
88178fd4
KH		 9208 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9209 * been zapped so no dirty logging staff is needed for old slot. For
9210 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9211 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9212 *
9213 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9214 */
88178fd4 9215 if (change != KVM_MR_DELETE)
f36f3f28 9216 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9217}
1d737c8a 9218
2df72e9b 9219void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9220{
6ca18b69 9221 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9222}
9223
2df72e9b
MT		 9224void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9225 struct kvm_memory_slot *slot)
9226{
ae7cd873 9227 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9228}
9229
e6c67d8c
LA		 9230static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9231{
9232 return (is_guest_mode(vcpu) &&
9233 kvm_x86_ops->guest_apic_has_interrupt &&
9234 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9235}
9236
5d9bc648
PB		 9237static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9238{
9239 if (!list_empty_careful(&vcpu->async_pf.done))
9240 return true;
9241
9242 if (kvm_apic_has_events(vcpu))
9243 return true;
9244
9245 if (vcpu->arch.pv.pv_unhalted)
9246 return true;
9247
a5f01f8e
WL		 9248 if (vcpu->arch.exception.pending)
9249 return true;
9250
47a66eed
Z		 9251 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9252 (vcpu->arch.nmi_pending &&
9253 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9254 return true;
9255
47a66eed
Z		 9256 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9257 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9258 return true;
9259
5d9bc648 9260 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9261 (kvm_cpu_has_interrupt(vcpu) ||
9262 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9263 return true;
9264
1f4b34f8
AS		 9265 if (kvm_hv_has_stimer_pending(vcpu))
9266 return true;
9267
5d9bc648
PB		 9268 return false;
9269}
9270
1d737c8a
ZX		 9271int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9272{
5d9bc648 9273 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9274}
5736199a 9275
199b5763
LM		 9276bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9277{
de63ad4c 9278 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9279}
9280
b6d33834 9281int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9282{
b6d33834 9283 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9284}
78646121
GN		 9285
9286int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9287{
9288 return kvm_x86_ops->interrupt_allowed(vcpu);
9289}
229456fc 9290
82b32774 9291unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9292{
82b32774
NA		 9293 if (is_64_bit_mode(vcpu))
9294 return kvm_rip_read(vcpu);
9295 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9296 kvm_rip_read(vcpu));
9297}
9298EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9299
82b32774
NA		 9300bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9301{
9302 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9303}
9304EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9305
94fe45da
JK		 9306unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9307{
9308 unsigned long rflags;
9309
9310 rflags = kvm_x86_ops->get_rflags(vcpu);
9311 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9312 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9313 return rflags;
9314}
9315EXPORT_SYMBOL_GPL(kvm_get_rflags);
9316
6addfc42 9317static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9318{
9319 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9320 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9321 rflags |= X86_EFLAGS_TF;
94fe45da 9322 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9323}
9324
9325void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9326{
9327 __kvm_set_rflags(vcpu, rflags);
3842d135 9328 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9329}
9330EXPORT_SYMBOL_GPL(kvm_set_rflags);
9331
56028d08
GN		 9332void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9333{
9334 int r;
9335
44dd3ffa 9336 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9337 work->wakeup_all)
56028d08
GN		 9338 return;
9339
9340 r = kvm_mmu_reload(vcpu);
9341 if (unlikely(r))
9342 return;
9343
44dd3ffa
VK		 9344 if (!vcpu->arch.mmu->direct_map &&
9345 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9346 return;
9347
44dd3ffa 9348 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9349}
9350
af585b92
GN		 9351static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9352{
9353 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9354}
9355
9356static inline u32 kvm_async_pf_next_probe(u32 key)
9357{
9358 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9359}
9360
9361static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9362{
9363 u32 key = kvm_async_pf_hash_fn(gfn);
9364
9365 while (vcpu->arch.apf.gfns[key] != ~0)
9366 key = kvm_async_pf_next_probe(key);
9367
9368 vcpu->arch.apf.gfns[key] = gfn;
9369}
9370
9371static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9372{
9373 int i;
9374 u32 key = kvm_async_pf_hash_fn(gfn);
9375
9376 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9377 (vcpu->arch.apf.gfns[key] != gfn &&
9378 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9379 key = kvm_async_pf_next_probe(key);
9380
9381 return key;
9382}
9383
9384bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9385{
9386 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9387}
9388
9389static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9390{
9391 u32 i, j, k;
9392
9393 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9394 while (true) {
9395 vcpu->arch.apf.gfns[i] = ~0;
9396 do {
9397 j = kvm_async_pf_next_probe(j);
9398 if (vcpu->arch.apf.gfns[j] == ~0)
9399 return;
9400 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9401 /*
9402 * k lies cyclically in ]i,j]
9403 * | i.k.j |
9404 * |....j i.k.| or |.k..j i...|
9405 */
9406 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9407 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9408 i = j;
9409 }
9410}
9411
7c90705b
GN		 9412static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9413{
4e335d9e
PB		 9414
9415 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9416 sizeof(val));
7c90705b
GN		 9417}
9418
9a6e7c39
WL		 9419static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9420{
9421
9422 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9423 sizeof(u32));
9424}
9425
af585b92
GN		 9426void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9427 struct kvm_async_pf *work)
9428{
6389ee94
AK		 9429 struct x86_exception fault;
9430
7c90705b 9431 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9432 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9433
9434 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9435 (vcpu->arch.apf.send_user_only &&
9436 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9437 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9438 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9439 fault.vector = PF_VECTOR;
9440 fault.error_code_valid = true;
9441 fault.error_code = 0;
9442 fault.nested_page_fault = false;
9443 fault.address = work->arch.token;
adfe20fb 9444 fault.async_page_fault = true;
6389ee94 9445 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9446 }
af585b92
GN		 9447}
9448
9449void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9450 struct kvm_async_pf *work)
9451{
6389ee94 9452 struct x86_exception fault;
9a6e7c39 9453 u32 val;
6389ee94 9454
f2e10669 9455 if (work->wakeup_all)
7c90705b
GN		 9456 work->arch.token = ~0; /* broadcast wakeup */
9457 else
9458 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9459 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9460
9a6e7c39
WL		 9461 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9462 !apf_get_user(vcpu, &val)) {
9463 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9464 vcpu->arch.exception.pending &&
9465 vcpu->arch.exception.nr == PF_VECTOR &&
9466 !apf_put_user(vcpu, 0)) {
9467 vcpu->arch.exception.injected = false;
9468 vcpu->arch.exception.pending = false;
9469 vcpu->arch.exception.nr = 0;
9470 vcpu->arch.exception.has_error_code = false;
9471 vcpu->arch.exception.error_code = 0;
9472 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9473 fault.vector = PF_VECTOR;
9474 fault.error_code_valid = true;
9475 fault.error_code = 0;
9476 fault.nested_page_fault = false;
9477 fault.address = work->arch.token;
9478 fault.async_page_fault = true;
9479 kvm_inject_page_fault(vcpu, &fault);
9480 }
7c90705b 9481 }
e6d53e3b 9482 vcpu->arch.apf.halted = false;
a4fa1635 9483 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9484}
9485
9486bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9487{
9488 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9489 return true;
9490 else
9bc1f09f 9491 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9492}
9493
5544eb9b
PB		 9494void kvm_arch_start_assignment(struct kvm *kvm)
9495{
9496 atomic_inc(&kvm->arch.assigned_device_count);
9497}
9498EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9499
9500void kvm_arch_end_assignment(struct kvm *kvm)
9501{
9502 atomic_dec(&kvm->arch.assigned_device_count);
9503}
9504EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9505
9506bool kvm_arch_has_assigned_device(struct kvm *kvm)
9507{
9508 return atomic_read(&kvm->arch.assigned_device_count);
9509}
9510EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9511
e0f0bbc5
AW		 9512void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9513{
9514 atomic_inc(&kvm->arch.noncoherent_dma_count);
9515}
9516EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9517
9518void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9519{
9520 atomic_dec(&kvm->arch.noncoherent_dma_count);
9521}
9522EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9523
9524bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9525{
9526 return atomic_read(&kvm->arch.noncoherent_dma_count);
9527}
9528EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9529
14717e20
AW		 9530bool kvm_arch_has_irq_bypass(void)
9531{
9532 return kvm_x86_ops->update_pi_irte != NULL;
9533}
9534
87276880
FW		 9535int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9536 struct irq_bypass_producer *prod)
9537{
9538 struct kvm_kernel_irqfd *irqfd =
9539 container_of(cons, struct kvm_kernel_irqfd, consumer);
9540
14717e20 9541 irqfd->producer = prod;
87276880 9542
14717e20
AW		 9543 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9544 prod->irq, irqfd->gsi, 1);
87276880
FW		 9545}
9546
9547void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9548 struct irq_bypass_producer *prod)
9549{
9550 int ret;
9551 struct kvm_kernel_irqfd *irqfd =
9552 container_of(cons, struct kvm_kernel_irqfd, consumer);
9553
87276880
FW		 9554 WARN_ON(irqfd->producer != prod);
9555 irqfd->producer = NULL;
9556
9557 /*
9558 * When producer of consumer is unregistered, we change back to
9559 * remapped mode, so we can re-use the current implementation
bb3541f1 9560 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9561 * int this case doesn't want to receive the interrupts.
9562 */
9563 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9564 if (ret)
9565 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9566 " fails: %d\n", irqfd->consumer.token, ret);
9567}
9568
9569int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9570 uint32_t guest_irq, bool set)
9571{
9572 if (!kvm_x86_ops->update_pi_irte)
9573 return -EINVAL;
9574
9575 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9576}
9577
52004014
FW		 9578bool kvm_vector_hashing_enabled(void)
9579{
9580 return vector_hashing;
9581}
9582EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9583
229456fc 9584EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9585EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9586EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9587EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9588EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9589EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9590EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9591EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9592EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9593EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9594EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9595EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9596EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9597EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9598EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9599EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9600EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9601EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9602EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)