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KVM: lapic: Fixup LDR on load in x2apic
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
fab0aa3b
EM		 110static bool __read_mostly report_ignored_msrs = true;
111module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
9ed96e87
MT		 113unsigned int min_timer_period_us = 500;
114module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
630994b3
MT		 116static bool __read_mostly kvmclock_periodic_sync = true;
117module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
893590c7 119bool __read_mostly kvm_has_tsc_control;
92a1f12d 120EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 121u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 123u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125u64 __read_mostly kvm_max_tsc_scaling_ratio;
126EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 127u64 __read_mostly kvm_default_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 129
cc578287 130/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 131static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 132module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
d0659d94 134/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 135unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 136module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
52004014
FW		 138static bool __read_mostly vector_hashing = true;
139module_param(vector_hashing, bool, S_IRUGO);
140
18863bdd
AK		 141#define KVM_NR_SHARED_MSRS 16
142
143struct kvm_shared_msrs_global {
144 int nr;
2bf78fa7 145 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 146};
147
148struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
2bf78fa7
SY		 151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 155};
156
157static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 158static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 159
417bc304 160struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 171 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 176 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 184 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 185 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 186 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 187 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
188 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
189 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
190 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
191 { "mmu_flooded", VM_STAT(mmu_flooded) },
192 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 193 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 194 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 195 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 196 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 197 { "max_mmu_page_hash_collisions",
198 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 199 { NULL }
200};
201
2acf923e
DC		 202u64 __read_mostly host_xcr0;
203
b6785def 204static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 205
af585b92
GN		 206static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
207{
208 int i;
209 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
210 vcpu->arch.apf.gfns[i] = ~0;
211}
212
18863bdd
AK		 213static void kvm_on_user_return(struct user_return_notifier *urn)
214{
215 unsigned slot;
18863bdd
AK		 216 struct kvm_shared_msrs *locals
217 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 218 struct kvm_shared_msr_values *values;
1650b4eb
IA		 219 unsigned long flags;
220
221 /*
222 * Disabling irqs at this point since the following code could be
223 * interrupted and executed through kvm_arch_hardware_disable()
224 */
225 local_irq_save(flags);
226 if (locals->registered) {
227 locals->registered = false;
228 user_return_notifier_unregister(urn);
229 }
230 local_irq_restore(flags);
18863bdd 231 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 232 values = &locals->values[slot];
233 if (values->host != values->curr) {
234 wrmsrl(shared_msrs_global.msrs[slot], values->host);
235 values->curr = values->host;
18863bdd
AK		 236 }
237 }
18863bdd
AK		 238}
239
2bf78fa7 240static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 241{
18863bdd 242 u64 value;
013f6a5d
MT		 243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 245
2bf78fa7
SY		 246 /* only read, and nobody should modify it at this time,
247 * so don't need lock */
248 if (slot >= shared_msrs_global.nr) {
249 printk(KERN_ERR "kvm: invalid MSR slot!");
250 return;
251 }
252 rdmsrl_safe(msr, &value);
253 smsr->values[slot].host = value;
254 smsr->values[slot].curr = value;
255}
256
257void kvm_define_shared_msr(unsigned slot, u32 msr)
258{
0123be42 259 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 260 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 261 if (slot >= shared_msrs_global.nr)
262 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 263}
264EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
265
266static void kvm_shared_msr_cpu_online(void)
267{
268 unsigned i;
18863bdd
AK		 269
270 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 271 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 272}
273
8b3c3104 274int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 275{
013f6a5d
MT		 276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 278 int err;
18863bdd 279
2bf78fa7 280 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 281 return 0;
2bf78fa7 282 smsr->values[slot].curr = value;
8b3c3104
AH		 283 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
284 if (err)
285 return 1;
286
18863bdd
AK		 287 if (!smsr->registered) {
288 smsr->urn.on_user_return = kvm_on_user_return;
289 user_return_notifier_register(&smsr->urn);
290 smsr->registered = true;
291 }
8b3c3104 292 return 0;
18863bdd
AK		 293}
294EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
295
13a34e06 296static void drop_user_return_notifiers(void)
3548bab5 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 300
301 if (smsr->registered)
302 kvm_on_user_return(&smsr->urn);
303}
304
6866b83e
CO		 305u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
306{
8a5a87d9 307 return vcpu->arch.apic_base;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_get_apic_base);
310
58cb628d
JK		 311int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
312{
313 u64 old_state = vcpu->arch.apic_base &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 new_state = msr_info->data &
316 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 317 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
318 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 319
d3802286
JM		 320 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
321 return 1;
58cb628d 322 if (!msr_info->host_initiated &&
d3802286 323 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 324 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
325 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
326 old_state == 0)))
327 return 1;
328
329 kvm_lapic_set_base(vcpu, msr_info->data);
330 return 0;
6866b83e
CO		 331}
332EXPORT_SYMBOL_GPL(kvm_set_apic_base);
333
2605fc21 334asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 335{
336 /* Fault while not rebooting. We want the trace. */
337 BUG();
338}
339EXPORT_SYMBOL_GPL(kvm_spurious_fault);
340
3fd28fce
ED		 341#define EXCPT_BENIGN 0
342#define EXCPT_CONTRIBUTORY 1
343#define EXCPT_PF 2
344
345static int exception_class(int vector)
346{
347 switch (vector) {
348 case PF_VECTOR:
349 return EXCPT_PF;
350 case DE_VECTOR:
351 case TS_VECTOR:
352 case NP_VECTOR:
353 case SS_VECTOR:
354 case GP_VECTOR:
355 return EXCPT_CONTRIBUTORY;
356 default:
357 break;
358 }
359 return EXCPT_BENIGN;
360}
361
d6e8c854
NA		 362#define EXCPT_FAULT 0
363#define EXCPT_TRAP 1
364#define EXCPT_ABORT 2
365#define EXCPT_INTERRUPT 3
366
367static int exception_type(int vector)
368{
369 unsigned int mask;
370
371 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
372 return EXCPT_INTERRUPT;
373
374 mask = 1 << vector;
375
376 /* #DB is trap, as instruction watchpoints are handled elsewhere */
377 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
378 return EXCPT_TRAP;
379
380 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
381 return EXCPT_ABORT;
382
383 /* Reserved exceptions will result in fault */
384 return EXCPT_FAULT;
385}
386
3fd28fce 387static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 388 unsigned nr, bool has_error, u32 error_code,
389 bool reinject)
3fd28fce
ED		 390{
391 u32 prev_nr;
392 int class1, class2;
393
3842d135
AK		 394 kvm_make_request(KVM_REQ_EVENT, vcpu);
395
664f8e26 396 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 397 queue:
3ffb2468
NA		 398 if (has_error && !is_protmode(vcpu))
399 has_error = false;
664f8e26
WL		 400 if (reinject) {
401 /*
402 * On vmentry, vcpu->arch.exception.pending is only
403 * true if an event injection was blocked by
404 * nested_run_pending. In that case, however,
405 * vcpu_enter_guest requests an immediate exit,
406 * and the guest shouldn't proceed far enough to
407 * need reinjection.
408 */
409 WARN_ON_ONCE(vcpu->arch.exception.pending);
410 vcpu->arch.exception.injected = true;
411 } else {
412 vcpu->arch.exception.pending = true;
413 vcpu->arch.exception.injected = false;
414 }
3fd28fce
ED		 415 vcpu->arch.exception.has_error_code = has_error;
416 vcpu->arch.exception.nr = nr;
417 vcpu->arch.exception.error_code = error_code;
418 return;
419 }
420
421 /* to check exception */
422 prev_nr = vcpu->arch.exception.nr;
423 if (prev_nr == DF_VECTOR) {
424 /* triple fault -> shutdown */
a8eeb04a 425 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 426 return;
427 }
428 class1 = exception_class(prev_nr);
429 class2 = exception_class(nr);
430 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
431 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 432 /*
433 * Generate double fault per SDM Table 5-5. Set
434 * exception.pending = true so that the double fault
435 * can trigger a nested vmexit.
436 */
3fd28fce 437 vcpu->arch.exception.pending = true;
664f8e26 438 vcpu->arch.exception.injected = false;
3fd28fce
ED		 439 vcpu->arch.exception.has_error_code = true;
440 vcpu->arch.exception.nr = DF_VECTOR;
441 vcpu->arch.exception.error_code = 0;
442 } else
443 /* replace previous exception with a new one in a hope
444 that instruction re-execution will regenerate lost
445 exception */
446 goto queue;
447}
448
298101da
AK		 449void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
450{
ce7ddec4 451 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 452}
453EXPORT_SYMBOL_GPL(kvm_queue_exception);
454
ce7ddec4
JR		 455void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
456{
457 kvm_multiple_exception(vcpu, nr, false, 0, true);
458}
459EXPORT_SYMBOL_GPL(kvm_requeue_exception);
460
6affcbed 461int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 462{
db8fcefa
AP		 463 if (err)
464 kvm_inject_gp(vcpu, 0);
465 else
6affcbed
KH		 466 return kvm_skip_emulated_instruction(vcpu);
467
468 return 1;
db8fcefa
AP		 469}
470EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 471
6389ee94 472void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 473{
474 ++vcpu->stat.pf_guest;
adfe20fb
WL		 475 vcpu->arch.exception.nested_apf =
476 is_guest_mode(vcpu) && fault->async_page_fault;
477 if (vcpu->arch.exception.nested_apf)
478 vcpu->arch.apf.nested_apf_token = fault->address;
479 else
480 vcpu->arch.cr2 = fault->address;
6389ee94 481 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 482}
27d6c865 483EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 484
ef54bcfe 485static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 486{
6389ee94
AK		 487 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
488 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 489 else
6389ee94 490 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 491
492 return fault->nested_page_fault;
d4f8cf66
JR		 493}
494
3419ffc8
SY		 495void kvm_inject_nmi(struct kvm_vcpu *vcpu)
496{
7460fb4a
AK		 497 atomic_inc(&vcpu->arch.nmi_queued);
498 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 499}
500EXPORT_SYMBOL_GPL(kvm_inject_nmi);
501
298101da
AK		 502void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
503{
ce7ddec4 504 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 505}
506EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
507
ce7ddec4
JR		 508void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
509{
510 kvm_multiple_exception(vcpu, nr, true, error_code, true);
511}
512EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
513
0a79b009
AK		 514/*
515 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
516 * a #GP and return false.
517 */
518bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 519{
0a79b009
AK		 520 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
521 return true;
522 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
523 return false;
298101da 524}
0a79b009 525EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 526
16f8a6f9
NA		 527bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
528{
529 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
530 return true;
531
532 kvm_queue_exception(vcpu, UD_VECTOR);
533 return false;
534}
535EXPORT_SYMBOL_GPL(kvm_require_dr);
536
ec92fe44
JR		 537/*
538 * This function will be used to read from the physical memory of the currently
54bf36aa 539 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 540 * can read from guest physical or from the guest's guest physical memory.
541 */
542int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
543 gfn_t ngfn, void *data, int offset, int len,
544 u32 access)
545{
54987b7a 546 struct x86_exception exception;
ec92fe44
JR		 547 gfn_t real_gfn;
548 gpa_t ngpa;
549
550 ngpa = gfn_to_gpa(ngfn);
54987b7a 551 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 552 if (real_gfn == UNMAPPED_GVA)
553 return -EFAULT;
554
555 real_gfn = gpa_to_gfn(real_gfn);
556
54bf36aa 557 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 558}
559EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
560
69b0049a 561static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 562 void *data, int offset, int len, u32 access)
563{
564 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
565 data, offset, len, access);
566}
567
a03490ed
CO		 568/*
569 * Load the pae pdptrs. Return true is they are all valid.
570 */
ff03a073 571int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 572{
573 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
574 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
575 int i;
576 int ret;
ff03a073 577 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 578
ff03a073
JR		 579 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
580 offset * sizeof(u64), sizeof(pdpte),
581 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 582 if (ret < 0) {
583 ret = 0;
584 goto out;
585 }
586 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 587 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 588 (pdpte[i] &
589 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 590 ret = 0;
591 goto out;
592 }
593 }
594 ret = 1;
595
ff03a073 596 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 597 __set_bit(VCPU_EXREG_PDPTR,
598 (unsigned long *)&vcpu->arch.regs_avail);
599 __set_bit(VCPU_EXREG_PDPTR,
600 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 601out:
a03490ed
CO		 602
603 return ret;
604}
cc4b6871 605EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 606
9ed38ffa 607bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 608{
ff03a073 609 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 610 bool changed = true;
3d06b8bf
JR		 611 int offset;
612 gfn_t gfn;
d835dfec
AK		 613 int r;
614
615 if (is_long_mode(vcpu) || !is_pae(vcpu))
616 return false;
617
6de4f3ad
AK		 618 if (!test_bit(VCPU_EXREG_PDPTR,
619 (unsigned long *)&vcpu->arch.regs_avail))
620 return true;
621
a512177e
PB		 622 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
623 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 624 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
625 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 626 if (r < 0)
627 goto out;
ff03a073 628 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 629out:
d835dfec
AK		 630
631 return changed;
632}
9ed38ffa 633EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 634
49a9b07e 635int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 636{
aad82703 637 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 638 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 639
f9a48e6a
AK		 640 cr0 |= X86_CR0_ET;
641
ab344828 642#ifdef CONFIG_X86_64
0f12244f
GN		 643 if (cr0 & 0xffffffff00000000UL)
644 return 1;
ab344828
GN		 645#endif
646
647 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 648
0f12244f
GN		 649 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
650 return 1;
a03490ed 651
0f12244f
GN		 652 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
653 return 1;
a03490ed
CO		 654
655 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
656#ifdef CONFIG_X86_64
f6801dff 657 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 658 int cs_db, cs_l;
659
0f12244f
GN		 660 if (!is_pae(vcpu))
661 return 1;
a03490ed 662 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 663 if (cs_l)
664 return 1;
a03490ed
CO		 665 } else
666#endif
ff03a073 667 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 668 kvm_read_cr3(vcpu)))
0f12244f 669 return 1;
a03490ed
CO		 670 }
671
ad756a16
MJ		 672 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
673 return 1;
674
a03490ed 675 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 676
d170c419 677 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 678 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 679 kvm_async_pf_hash_reset(vcpu);
680 }
e5f3f027 681
aad82703
SY		 682 if ((cr0 ^ old_cr0) & update_bits)
683 kvm_mmu_reset_context(vcpu);
b18d5431 684
879ae188
LE		 685 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
686 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
687 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 688 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
689
0f12244f
GN		 690 return 0;
691}
2d3ad1f4 692EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 693
2d3ad1f4 694void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 695{
49a9b07e 696 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 697}
2d3ad1f4 698EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 699
42bdf991
MT		 700static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
701{
702 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
703 !vcpu->guest_xcr0_loaded) {
704 /* kvm_set_xcr() also depends on this */
705 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
706 vcpu->guest_xcr0_loaded = 1;
707 }
708}
709
710static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
711{
712 if (vcpu->guest_xcr0_loaded) {
713 if (vcpu->arch.xcr0 != host_xcr0)
714 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
715 vcpu->guest_xcr0_loaded = 0;
716 }
717}
718
69b0049a 719static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 720{
56c103ec
LJ		 721 u64 xcr0 = xcr;
722 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 723 u64 valid_bits;
2acf923e
DC		 724
725 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
726 if (index != XCR_XFEATURE_ENABLED_MASK)
727 return 1;
d91cab78 728 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 729 return 1;
d91cab78 730 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 731 return 1;
46c34cb0
PB		 732
733 /*
734 * Do not allow the guest to set bits that we do not support
735 * saving. However, xcr0 bit 0 is always set, even if the
736 * emulated CPU does not support XSAVE (see fx_init).
737 */
d91cab78 738 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 739 if (xcr0 & ~valid_bits)
2acf923e 740 return 1;
46c34cb0 741
d91cab78
DH		 742 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
743 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 744 return 1;
745
d91cab78
DH		 746 if (xcr0 & XFEATURE_MASK_AVX512) {
747 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 748 return 1;
d91cab78 749 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 750 return 1;
751 }
2acf923e 752 vcpu->arch.xcr0 = xcr0;
56c103ec 753
d91cab78 754 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 755 kvm_update_cpuid(vcpu);
2acf923e
DC		 756 return 0;
757}
758
759int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
760{
764bcbc5
Z		 761 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
762 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 763 kvm_inject_gp(vcpu, 0);
764 return 1;
765 }
766 return 0;
767}
768EXPORT_SYMBOL_GPL(kvm_set_xcr);
769
a83b29c6 770int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 771{
fc78f519 772 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 773 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 774 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 775
0f12244f
GN		 776 if (cr4 & CR4_RESERVED_BITS)
777 return 1;
a03490ed 778
d6321d49 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 780 return 1;
781
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 783 return 1;
784
d6321d49 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 786 return 1;
787
d6321d49 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 789 return 1;
790
d6321d49 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 792 return 1;
793
fd8cb433 794 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 795 return 1;
796
a03490ed 797 if (is_long_mode(vcpu)) {
0f12244f
GN		 798 if (!(cr4 & X86_CR4_PAE))
799 return 1;
a2edf57f
AK		 800 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
801 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 802 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
803 kvm_read_cr3(vcpu)))
0f12244f
GN		 804 return 1;
805
ad756a16 806 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 807 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 808 return 1;
809
810 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
811 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
812 return 1;
813 }
814
5e1746d6 815 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 816 return 1;
a03490ed 817
ad756a16
MJ		 818 if (((cr4 ^ old_cr4) & pdptr_bits) ||
819 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 820 kvm_mmu_reset_context(vcpu);
0f12244f 821
b9baba86 822 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 823 kvm_update_cpuid(vcpu);
2acf923e 824
0f12244f
GN		 825 return 0;
826}
2d3ad1f4 827EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 828
2390218b 829int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 830{
ac146235 831#ifdef CONFIG_X86_64
9d88fca7 832 cr3 &= ~CR3_PCID_INVD;
ac146235 833#endif
9d88fca7 834
9f8fe504 835 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 836 kvm_mmu_sync_roots(vcpu);
77c3913b 837 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 838 return 0;
d835dfec
AK		 839 }
840
d1cd3ce9
YZ		 841 if (is_long_mode(vcpu) &&
842 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
843 return 1;
844 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 845 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 846 return 1;
a03490ed 847
0f12244f 848 vcpu->arch.cr3 = cr3;
aff48baa 849 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 850 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 851 return 0;
852}
2d3ad1f4 853EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 854
eea1cff9 855int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 856{
0f12244f
GN		 857 if (cr8 & CR8_RESERVED_BITS)
858 return 1;
35754c98 859 if (lapic_in_kernel(vcpu))
a03490ed
CO		 860 kvm_lapic_set_tpr(vcpu, cr8);
861 else
ad312c7c 862 vcpu->arch.cr8 = cr8;
0f12244f
GN		 863 return 0;
864}
2d3ad1f4 865EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 866
2d3ad1f4 867unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 868{
35754c98 869 if (lapic_in_kernel(vcpu))
a03490ed
CO		 870 return kvm_lapic_get_cr8(vcpu);
871 else
ad312c7c 872 return vcpu->arch.cr8;
a03490ed 873}
2d3ad1f4 874EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 875
ae561ede
NA		 876static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
877{
878 int i;
879
880 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
881 for (i = 0; i < KVM_NR_DB_REGS; i++)
882 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
883 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
884 }
885}
886
73aaf249
JK		 887static void kvm_update_dr6(struct kvm_vcpu *vcpu)
888{
889 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
890 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
891}
892
c8639010
JK		 893static void kvm_update_dr7(struct kvm_vcpu *vcpu)
894{
895 unsigned long dr7;
896
897 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
898 dr7 = vcpu->arch.guest_debug_dr7;
899 else
900 dr7 = vcpu->arch.dr7;
901 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 902 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
903 if (dr7 & DR7_BP_EN_MASK)
904 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 905}
906
6f43ed01
NA		 907static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
908{
909 u64 fixed = DR6_FIXED_1;
910
d6321d49 911 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 912 fixed |= DR6_RTM;
913 return fixed;
914}
915
338dbc97 916static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 917{
918 switch (dr) {
919 case 0 ... 3:
920 vcpu->arch.db[dr] = val;
921 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
922 vcpu->arch.eff_db[dr] = val;
923 break;
924 case 4:
020df079
GN		 925 /* fall through */
926 case 6:
338dbc97
GN		 927 if (val & 0xffffffff00000000ULL)
928 return -1; /* #GP */
6f43ed01 929 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 930 kvm_update_dr6(vcpu);
020df079
GN		 931 break;
932 case 5:
020df079
GN		 933 /* fall through */
934 default: /* 7 */
338dbc97
GN		 935 if (val & 0xffffffff00000000ULL)
936 return -1; /* #GP */
020df079 937 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 938 kvm_update_dr7(vcpu);
020df079
GN		 939 break;
940 }
941
942 return 0;
943}
338dbc97
GN		 944
945int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
946{
16f8a6f9 947 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 948 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 949 return 1;
950 }
951 return 0;
338dbc97 952}
020df079
GN		 953EXPORT_SYMBOL_GPL(kvm_set_dr);
954
16f8a6f9 955int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 956{
957 switch (dr) {
958 case 0 ... 3:
959 *val = vcpu->arch.db[dr];
960 break;
961 case 4:
020df079
GN		 962 /* fall through */
963 case 6:
73aaf249
JK		 964 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
965 *val = vcpu->arch.dr6;
966 else
967 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 968 break;
969 case 5:
020df079
GN		 970 /* fall through */
971 default: /* 7 */
972 *val = vcpu->arch.dr7;
973 break;
974 }
338dbc97
GN		 975 return 0;
976}
020df079
GN		 977EXPORT_SYMBOL_GPL(kvm_get_dr);
978
022cd0e8
AK		 979bool kvm_rdpmc(struct kvm_vcpu *vcpu)
980{
981 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
982 u64 data;
983 int err;
984
c6702c9d 985 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 986 if (err)
987 return err;
988 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
989 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
990 return err;
991}
992EXPORT_SYMBOL_GPL(kvm_rdpmc);
993
043405e1
CO		 994/*
995 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
996 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
997 *
998 * This list is modified at module load time to reflect the
e3267cbb 999 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1000 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1001 * may depend on host virtualization features rather than host cpu features.
043405e1 1002 */
e3267cbb 1003
043405e1
CO		 1004static u32 msrs_to_save[] = {
1005 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1006 MSR_STAR,
043405e1
CO		 1007#ifdef CONFIG_X86_64
1008 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1009#endif
b3897a49 1010 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1011 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 1012};
1013
1014static unsigned num_msrs_to_save;
1015
62ef68bb
PB		 1016static u32 emulated_msrs[] = {
1017 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1018 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1019 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1020 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1021 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1022 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1023 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1024 HV_X64_MSR_RESET,
11c4b1ca 1025 HV_X64_MSR_VP_INDEX,
9eec50b8 1026 HV_X64_MSR_VP_RUNTIME,
5c919412 1027 HV_X64_MSR_SCONTROL,
1f4b34f8 1028 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1029 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1030 MSR_KVM_PV_EOI_EN,
1031
ba904635 1032 MSR_IA32_TSC_ADJUST,
a3e06bbe 1033 MSR_IA32_TSCDEADLINE,
043405e1 1034 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1035 MSR_IA32_MCG_STATUS,
1036 MSR_IA32_MCG_CTL,
c45dcc71 1037 MSR_IA32_MCG_EXT_CTL,
64d60670 1038 MSR_IA32_SMBASE,
db2336a8
KH		 1039 MSR_PLATFORM_INFO,
1040 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1041};
1042
62ef68bb
PB		 1043static unsigned num_emulated_msrs;
1044
384bb783 1045bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1046{
b69e8cae 1047 if (efer & efer_reserved_bits)
384bb783 1048 return false;
15c4a640 1049
1b4d56b8 1050 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1051 return false;
1b2fd70c 1052
1b4d56b8 1053 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1054 return false;
d8017474 1055
384bb783
JK		 1056 return true;
1057}
1058EXPORT_SYMBOL_GPL(kvm_valid_efer);
1059
1060static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1061{
1062 u64 old_efer = vcpu->arch.efer;
1063
1064 if (!kvm_valid_efer(vcpu, efer))
1065 return 1;
1066
1067 if (is_paging(vcpu)
1068 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1069 return 1;
1070
15c4a640 1071 efer &= ~EFER_LMA;
f6801dff 1072 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1073
a3d204e2
SY		 1074 kvm_x86_ops->set_efer(vcpu, efer);
1075
aad82703
SY		 1076 /* Update reserved bits */
1077 if ((efer ^ old_efer) & EFER_NX)
1078 kvm_mmu_reset_context(vcpu);
1079
b69e8cae 1080 return 0;
15c4a640
CO		 1081}
1082
f2b4b7dd
JR		 1083void kvm_enable_efer_bits(u64 mask)
1084{
1085 efer_reserved_bits &= ~mask;
1086}
1087EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1088
15c4a640
CO		 1089/*
1090 * Writes msr value into into the appropriate "register".
1091 * Returns 0 on success, non-0 otherwise.
1092 * Assumes vcpu_load() was already called.
1093 */
8fe8ab46 1094int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1095{
854e8bb1
NA		 1096 switch (msr->index) {
1097 case MSR_FS_BASE:
1098 case MSR_GS_BASE:
1099 case MSR_KERNEL_GS_BASE:
1100 case MSR_CSTAR:
1101 case MSR_LSTAR:
fd8cb433 1102 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1103 return 1;
1104 break;
1105 case MSR_IA32_SYSENTER_EIP:
1106 case MSR_IA32_SYSENTER_ESP:
1107 /*
1108 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1109 * non-canonical address is written on Intel but not on
1110 * AMD (which ignores the top 32-bits, because it does
1111 * not implement 64-bit SYSENTER).
1112 *
1113 * 64-bit code should hence be able to write a non-canonical
1114 * value on AMD. Making the address canonical ensures that
1115 * vmentry does not fail on Intel after writing a non-canonical
1116 * value, and that something deterministic happens if the guest
1117 * invokes 64-bit SYSENTER.
1118 */
fd8cb433 1119 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1120 }
8fe8ab46 1121 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1122}
854e8bb1 1123EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1124
313a3dc7
CO		 1125/*
1126 * Adapt set_msr() to msr_io()'s calling convention
1127 */
609e36d3
PB		 1128static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1129{
1130 struct msr_data msr;
1131 int r;
1132
1133 msr.index = index;
1134 msr.host_initiated = true;
1135 r = kvm_get_msr(vcpu, &msr);
1136 if (r)
1137 return r;
1138
1139 *data = msr.data;
1140 return 0;
1141}
1142
313a3dc7
CO		 1143static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1144{
8fe8ab46
WA		 1145 struct msr_data msr;
1146
1147 msr.data = *data;
1148 msr.index = index;
1149 msr.host_initiated = true;
1150 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1151}
1152
16e8d74d
MT		 1153#ifdef CONFIG_X86_64
1154struct pvclock_gtod_data {
1155 seqcount_t seq;
1156
1157 struct { /* extract of a clocksource struct */
1158 int vclock_mode;
a5a1d1c2
TG		 1159 u64 cycle_last;
1160 u64 mask;
16e8d74d
MT		 1161 u32 mult;
1162 u32 shift;
1163 } clock;
1164
cbcf2dd3
TG		 1165 u64 boot_ns;
1166 u64 nsec_base;
55dd00a7 1167 u64 wall_time_sec;
16e8d74d
MT		 1168};
1169
1170static struct pvclock_gtod_data pvclock_gtod_data;
1171
1172static void update_pvclock_gtod(struct timekeeper *tk)
1173{
1174 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1175 u64 boot_ns;
1176
876e7881 1177 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1178
1179 write_seqcount_begin(&vdata->seq);
1180
1181 /* copy pvclock gtod data */
876e7881
PZ		 1182 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1183 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1184 vdata->clock.mask = tk->tkr_mono.mask;
1185 vdata->clock.mult = tk->tkr_mono.mult;
1186 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1187
cbcf2dd3 1188 vdata->boot_ns = boot_ns;
876e7881 1189 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1190
55dd00a7
MT		 1191 vdata->wall_time_sec = tk->xtime_sec;
1192
16e8d74d
MT		 1193 write_seqcount_end(&vdata->seq);
1194}
1195#endif
1196
bab5bb39
NK		 1197void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1198{
1199 /*
1200 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1201 * vcpu_enter_guest. This function is only called from
1202 * the physical CPU that is running vcpu.
1203 */
1204 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1205}
16e8d74d 1206
18068523
GOC		 1207static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1208{
9ed3c444
AK		 1209 int version;
1210 int r;
50d0a0f9 1211 struct pvclock_wall_clock wc;
87aeb54f 1212 struct timespec64 boot;
18068523
GOC		 1213
1214 if (!wall_clock)
1215 return;
1216
9ed3c444
AK		 1217 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1218 if (r)
1219 return;
1220
1221 if (version & 1)
1222 ++version; /* first time write, random junk */
1223
1224 ++version;
18068523 1225
1dab1345
NK		 1226 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1227 return;
18068523 1228
50d0a0f9
GH		 1229 /*
1230 * The guest calculates current wall clock time by adding
34c238a1 1231 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1232 * wall clock specified here. guest system time equals host
1233 * system time for us, thus we must fill in host boot time here.
1234 */
87aeb54f 1235 getboottime64(&boot);
50d0a0f9 1236
4b648665 1237 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1238 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1239 boot = timespec64_sub(boot, ts);
4b648665 1240 }
87aeb54f 1241 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1242 wc.nsec = boot.tv_nsec;
1243 wc.version = version;
18068523
GOC		 1244
1245 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1246
1247 version++;
1248 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1249}
1250
50d0a0f9
GH		 1251static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1252{
b51012de
PB		 1253 do_shl32_div32(dividend, divisor);
1254 return dividend;
50d0a0f9
GH		 1255}
1256
3ae13faa 1257static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1258 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1259{
5f4e3f88 1260 uint64_t scaled64;
50d0a0f9
GH		 1261 int32_t shift = 0;
1262 uint64_t tps64;
1263 uint32_t tps32;
1264
3ae13faa
PB		 1265 tps64 = base_hz;
1266 scaled64 = scaled_hz;
50933623 1267 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1268 tps64 >>= 1;
1269 shift--;
1270 }
1271
1272 tps32 = (uint32_t)tps64;
50933623
JK		 1273 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1274 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1275 scaled64 >>= 1;
1276 else
1277 tps32 <<= 1;
50d0a0f9
GH		 1278 shift++;
1279 }
1280
5f4e3f88
ZA		 1281 *pshift = shift;
1282 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1283
3ae13faa
PB		 1284 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1285 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1286}
1287
d828199e 1288#ifdef CONFIG_X86_64
16e8d74d 1289static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1290#endif
16e8d74d 1291
c8076604 1292static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1293static unsigned long max_tsc_khz;
c8076604 1294
cc578287 1295static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1296{
cc578287
ZA		 1297 u64 v = (u64)khz * (1000000 + ppm);
1298 do_div(v, 1000000);
1299 return v;
1e993611
JR		 1300}
1301
381d585c
HZ		 1302static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1303{
1304 u64 ratio;
1305
1306 /* Guest TSC same frequency as host TSC? */
1307 if (!scale) {
1308 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1309 return 0;
1310 }
1311
1312 /* TSC scaling supported? */
1313 if (!kvm_has_tsc_control) {
1314 if (user_tsc_khz > tsc_khz) {
1315 vcpu->arch.tsc_catchup = 1;
1316 vcpu->arch.tsc_always_catchup = 1;
1317 return 0;
1318 } else {
1319 WARN(1, "user requested TSC rate below hardware speed\n");
1320 return -1;
1321 }
1322 }
1323
1324 /* TSC scaling required - calculate ratio */
1325 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1326 user_tsc_khz, tsc_khz);
1327
1328 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1329 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1330 user_tsc_khz);
1331 return -1;
1332 }
1333
1334 vcpu->arch.tsc_scaling_ratio = ratio;
1335 return 0;
1336}
1337
4941b8cb 1338static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1339{
cc578287
ZA		 1340 u32 thresh_lo, thresh_hi;
1341 int use_scaling = 0;
217fc9cf 1342
03ba32ca 1343 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1344 if (user_tsc_khz == 0) {
ad721883
HZ		 1345 /* set tsc_scaling_ratio to a safe value */
1346 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1347 return -1;
ad721883 1348 }
03ba32ca 1349
c285545f 1350 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1351 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1352 &vcpu->arch.virtual_tsc_shift,
1353 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1354 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1355
1356 /*
1357 * Compute the variation in TSC rate which is acceptable
1358 * within the range of tolerance and decide if the
1359 * rate being applied is within that bounds of the hardware
1360 * rate. If so, no scaling or compensation need be done.
1361 */
1362 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1363 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1364 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1365 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1366 use_scaling = 1;
1367 }
4941b8cb 1368 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1369}
1370
1371static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1372{
e26101b1 1373 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1374 vcpu->arch.virtual_tsc_mult,
1375 vcpu->arch.virtual_tsc_shift);
e26101b1 1376 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1377 return tsc;
1378}
1379
69b0049a 1380static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1381{
1382#ifdef CONFIG_X86_64
1383 bool vcpus_matched;
b48aa97e
MT		 1384 struct kvm_arch *ka = &vcpu->kvm->arch;
1385 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1386
1387 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1388 atomic_read(&vcpu->kvm->online_vcpus));
1389
7f187922
MT		 1390 /*
1391 * Once the masterclock is enabled, always perform request in
1392 * order to update it.
1393 *
1394 * In order to enable masterclock, the host clocksource must be TSC
1395 * and the vcpus need to have matched TSCs. When that happens,
1396 * perform request to enable masterclock.
1397 */
1398 if (ka->use_master_clock ||
1399 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1400 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1401
1402 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1403 atomic_read(&vcpu->kvm->online_vcpus),
1404 ka->use_master_clock, gtod->clock.vclock_mode);
1405#endif
1406}
1407
ba904635
WA		 1408static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1409{
3e3f5026 1410 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1411 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1412}
1413
35181e86
HZ		 1414/*
1415 * Multiply tsc by a fixed point number represented by ratio.
1416 *
1417 * The most significant 64-N bits (mult) of ratio represent the
1418 * integral part of the fixed point number; the remaining N bits
1419 * (frac) represent the fractional part, ie. ratio represents a fixed
1420 * point number (mult + frac * 2^(-N)).
1421 *
1422 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1423 */
1424static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1425{
1426 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1427}
1428
1429u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1430{
1431 u64 _tsc = tsc;
1432 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1433
1434 if (ratio != kvm_default_tsc_scaling_ratio)
1435 _tsc = __scale_tsc(ratio, tsc);
1436
1437 return _tsc;
1438}
1439EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1440
07c1419a
HZ		 1441static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1442{
1443 u64 tsc;
1444
1445 tsc = kvm_scale_tsc(vcpu, rdtsc());
1446
1447 return target_tsc - tsc;
1448}
1449
4ba76538
HZ		 1450u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1451{
ea26e4ec 1452 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1453}
1454EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1455
a545ab6a
LC		 1456static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1457{
1458 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1459 vcpu->arch.tsc_offset = offset;
1460}
1461
8fe8ab46 1462void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1463{
1464 struct kvm *kvm = vcpu->kvm;
f38e098f 1465 u64 offset, ns, elapsed;
99e3e30a 1466 unsigned long flags;
b48aa97e 1467 bool matched;
0d3da0d2 1468 bool already_matched;
8fe8ab46 1469 u64 data = msr->data;
c5e8ec8e 1470 bool synchronizing = false;
99e3e30a 1471
038f8c11 1472 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1473 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1474 ns = ktime_get_boot_ns();
f38e098f 1475 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1476
03ba32ca 1477 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1478 if (data == 0 && msr->host_initiated) {
1479 /*
1480 * detection of vcpu initialization -- need to sync
1481 * with other vCPUs. This particularly helps to keep
1482 * kvm_clock stable after CPU hotplug
1483 */
1484 synchronizing = true;
1485 } else {
1486 u64 tsc_exp = kvm->arch.last_tsc_write +
1487 nsec_to_cycles(vcpu, elapsed);
1488 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1489 /*
1490 * Special case: TSC write with a small delta (1 second)
1491 * of virtual cycle time against real time is
1492 * interpreted as an attempt to synchronize the CPU.
1493 */
1494 synchronizing = data < tsc_exp + tsc_hz &&
1495 data + tsc_hz > tsc_exp;
1496 }
c5e8ec8e 1497 }
f38e098f
ZA		 1498
1499 /*
5d3cb0f6
ZA		 1500 * For a reliable TSC, we can match TSC offsets, and for an unstable
1501 * TSC, we add elapsed time in this computation. We could let the
1502 * compensation code attempt to catch up if we fall behind, but
1503 * it's better to try to match offsets from the beginning.
1504 */
c5e8ec8e 1505 if (synchronizing &&
5d3cb0f6 1506 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1507 if (!check_tsc_unstable()) {
e26101b1 1508 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1509 pr_debug("kvm: matched tsc offset for %llu\n", data);
1510 } else {
857e4099 1511 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1512 data += delta;
07c1419a 1513 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1514 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1515 }
b48aa97e 1516 matched = true;
0d3da0d2 1517 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1518 } else {
1519 /*
1520 * We split periods of matched TSC writes into generations.
1521 * For each generation, we track the original measured
1522 * nanosecond time, offset, and write, so if TSCs are in
1523 * sync, we can match exact offset, and if not, we can match
4a969980 1524 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1525 *
1526 * These values are tracked in kvm->arch.cur_xxx variables.
1527 */
1528 kvm->arch.cur_tsc_generation++;
1529 kvm->arch.cur_tsc_nsec = ns;
1530 kvm->arch.cur_tsc_write = data;
1531 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1532 matched = false;
0d3da0d2 1533 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1534 kvm->arch.cur_tsc_generation, data);
f38e098f 1535 }
e26101b1
ZA		 1536
1537 /*
1538 * We also track th most recent recorded KHZ, write and time to
1539 * allow the matching interval to be extended at each write.
1540 */
f38e098f
ZA		 1541 kvm->arch.last_tsc_nsec = ns;
1542 kvm->arch.last_tsc_write = data;
5d3cb0f6 1543 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1544
b183aa58 1545 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1546
1547 /* Keep track of which generation this VCPU has synchronized to */
1548 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1549 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1550 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1551
d6321d49 1552 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1553 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1554
a545ab6a 1555 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1556 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1557
1558 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1559 if (!matched) {
b48aa97e 1560 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1561 } else if (!already_matched) {
1562 kvm->arch.nr_vcpus_matched_tsc++;
1563 }
b48aa97e
MT		 1564
1565 kvm_track_tsc_matching(vcpu);
1566 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1567}
e26101b1 1568
99e3e30a
ZA		 1569EXPORT_SYMBOL_GPL(kvm_write_tsc);
1570
58ea6767
HZ		 1571static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1572 s64 adjustment)
1573{
ea26e4ec 1574 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1575}
1576
1577static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1578{
1579 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1580 WARN_ON(adjustment < 0);
1581 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1582 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1583}
1584
d828199e
MT		 1585#ifdef CONFIG_X86_64
1586
a5a1d1c2 1587static u64 read_tsc(void)
d828199e 1588{
a5a1d1c2 1589 u64 ret = (u64)rdtsc_ordered();
03b9730b 1590 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1591
1592 if (likely(ret >= last))
1593 return ret;
1594
1595 /*
1596 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1597 * predictable (it's just a function of time and the likely is
d828199e
MT		 1598 * very likely) and there's a data dependence, so force GCC
1599 * to generate a branch instead. I don't barrier() because
1600 * we don't actually need a barrier, and if this function
1601 * ever gets inlined it will generate worse code.
1602 */
1603 asm volatile ("");
1604 return last;
1605}
1606
a5a1d1c2 1607static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1608{
1609 long v;
1610 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1611
1612 *cycle_now = read_tsc();
1613
1614 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1615 return v * gtod->clock.mult;
1616}
1617
a5a1d1c2 1618static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1619{
cbcf2dd3 1620 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1621 unsigned long seq;
d828199e 1622 int mode;
cbcf2dd3 1623 u64 ns;
d828199e 1624
d828199e
MT		 1625 do {
1626 seq = read_seqcount_begin(&gtod->seq);
1627 mode = gtod->clock.vclock_mode;
cbcf2dd3 1628 ns = gtod->nsec_base;
d828199e
MT		 1629 ns += vgettsc(cycle_now);
1630 ns >>= gtod->clock.shift;
cbcf2dd3 1631 ns += gtod->boot_ns;
d828199e 1632 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1633 *t = ns;
d828199e
MT		 1634
1635 return mode;
1636}
1637
55dd00a7
MT		 1638static int do_realtime(struct timespec *ts, u64 *cycle_now)
1639{
1640 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1641 unsigned long seq;
1642 int mode;
1643 u64 ns;
1644
1645 do {
1646 seq = read_seqcount_begin(&gtod->seq);
1647 mode = gtod->clock.vclock_mode;
1648 ts->tv_sec = gtod->wall_time_sec;
1649 ns = gtod->nsec_base;
1650 ns += vgettsc(cycle_now);
1651 ns >>= gtod->clock.shift;
1652 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1653
1654 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1655 ts->tv_nsec = ns;
1656
1657 return mode;
1658}
1659
d828199e 1660/* returns true if host is using tsc clocksource */
a5a1d1c2 1661static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1662{
d828199e
MT		 1663 /* checked again under seqlock below */
1664 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1665 return false;
1666
cbcf2dd3 1667 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1668}
55dd00a7
MT		 1669
1670/* returns true if host is using tsc clocksource */
1671static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1672 u64 *cycle_now)
1673{
1674 /* checked again under seqlock below */
1675 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1676 return false;
1677
1678 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1679}
d828199e
MT		 1680#endif
1681
1682/*
1683 *
b48aa97e
MT		 1684 * Assuming a stable TSC across physical CPUS, and a stable TSC
1685 * across virtual CPUs, the following condition is possible.
1686 * Each numbered line represents an event visible to both
d828199e
MT		 1687 * CPUs at the next numbered event.
1688 *
1689 * "timespecX" represents host monotonic time. "tscX" represents
1690 * RDTSC value.
1691 *
1692 * VCPU0 on CPU0 | VCPU1 on CPU1
1693 *
1694 * 1. read timespec0,tsc0
1695 * 2. | timespec1 = timespec0 + N
1696 * | tsc1 = tsc0 + M
1697 * 3. transition to guest | transition to guest
1698 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1699 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1700 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1701 *
1702 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1703 *
1704 * - ret0 < ret1
1705 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1706 * ...
1707 * - 0 < N - M => M < N
1708 *
1709 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1710 * always the case (the difference between two distinct xtime instances
1711 * might be smaller then the difference between corresponding TSC reads,
1712 * when updating guest vcpus pvclock areas).
1713 *
1714 * To avoid that problem, do not allow visibility of distinct
1715 * system_timestamp/tsc_timestamp values simultaneously: use a master
1716 * copy of host monotonic time values. Update that master copy
1717 * in lockstep.
1718 *
b48aa97e 1719 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1720 *
1721 */
1722
1723static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1724{
1725#ifdef CONFIG_X86_64
1726 struct kvm_arch *ka = &kvm->arch;
1727 int vclock_mode;
b48aa97e
MT		 1728 bool host_tsc_clocksource, vcpus_matched;
1729
1730 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1731 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1732
1733 /*
1734 * If the host uses TSC clock, then passthrough TSC as stable
1735 * to the guest.
1736 */
b48aa97e 1737 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1738 &ka->master_kernel_ns,
1739 &ka->master_cycle_now);
1740
16a96021 1741 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1742 && !ka->backwards_tsc_observed
54750f2c 1743 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1744
d828199e
MT		 1745 if (ka->use_master_clock)
1746 atomic_set(&kvm_guest_has_master_clock, 1);
1747
1748 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1749 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1750 vcpus_matched);
d828199e
MT		 1751#endif
1752}
1753
2860c4b1
PB		 1754void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1755{
1756 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1757}
1758
2e762ff7
MT		 1759static void kvm_gen_update_masterclock(struct kvm *kvm)
1760{
1761#ifdef CONFIG_X86_64
1762 int i;
1763 struct kvm_vcpu *vcpu;
1764 struct kvm_arch *ka = &kvm->arch;
1765
1766 spin_lock(&ka->pvclock_gtod_sync_lock);
1767 kvm_make_mclock_inprogress_request(kvm);
1768 /* no guest entries from this point */
1769 pvclock_update_vm_gtod_copy(kvm);
1770
1771 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1772 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1773
1774 /* guest entries allowed */
1775 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1776 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1777
1778 spin_unlock(&ka->pvclock_gtod_sync_lock);
1779#endif
1780}
1781
e891a32e 1782u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1783{
108b249c 1784 struct kvm_arch *ka = &kvm->arch;
8b953440 1785 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1786 u64 ret;
108b249c 1787
8b953440
PB		 1788 spin_lock(&ka->pvclock_gtod_sync_lock);
1789 if (!ka->use_master_clock) {
1790 spin_unlock(&ka->pvclock_gtod_sync_lock);
1791 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1792 }
1793
8b953440
PB		 1794 hv_clock.tsc_timestamp = ka->master_cycle_now;
1795 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1796 spin_unlock(&ka->pvclock_gtod_sync_lock);
1797
e2c2206a
WL		 1798 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1799 get_cpu();
1800
8b953440
PB		 1801 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1802 &hv_clock.tsc_shift,
1803 &hv_clock.tsc_to_system_mul);
e2c2206a
WL		 1804 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1805
1806 put_cpu();
1807
1808 return ret;
108b249c
PB		 1809}
1810
0d6dd2ff
PB		 1811static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1812{
1813 struct kvm_vcpu_arch *vcpu = &v->arch;
1814 struct pvclock_vcpu_time_info guest_hv_clock;
1815
4e335d9e 1816 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1817 &guest_hv_clock, sizeof(guest_hv_clock))))
1818 return;
1819
1820 /* This VCPU is paused, but it's legal for a guest to read another
1821 * VCPU's kvmclock, so we really have to follow the specification where
1822 * it says that version is odd if data is being modified, and even after
1823 * it is consistent.
1824 *
1825 * Version field updates must be kept separate. This is because
1826 * kvm_write_guest_cached might use a "rep movs" instruction, and
1827 * writes within a string instruction are weakly ordered. So there
1828 * are three writes overall.
1829 *
1830 * As a small optimization, only write the version field in the first
1831 * and third write. The vcpu->pv_time cache is still valid, because the
1832 * version field is the first in the struct.
1833 */
1834 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1835
51c4b8bb
LA		 1836 if (guest_hv_clock.version & 1)
1837 ++guest_hv_clock.version; /* first time write, random junk */
1838
0d6dd2ff 1839 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1840 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1841 &vcpu->hv_clock,
1842 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1843
1844 smp_wmb();
1845
1846 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1847 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1848
1849 if (vcpu->pvclock_set_guest_stopped_request) {
1850 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1851 vcpu->pvclock_set_guest_stopped_request = false;
1852 }
1853
1854 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1855
4e335d9e
PB		 1856 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1857 &vcpu->hv_clock,
1858 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1859
1860 smp_wmb();
1861
1862 vcpu->hv_clock.version++;
4e335d9e
PB		 1863 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1864 &vcpu->hv_clock,
1865 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1866}
1867
34c238a1 1868static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1869{
78db6a50 1870 unsigned long flags, tgt_tsc_khz;
18068523 1871 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1872 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1873 s64 kernel_ns;
d828199e 1874 u64 tsc_timestamp, host_tsc;
51d59c6b 1875 u8 pvclock_flags;
d828199e
MT		 1876 bool use_master_clock;
1877
1878 kernel_ns = 0;
1879 host_tsc = 0;
18068523 1880
d828199e
MT		 1881 /*
1882 * If the host uses TSC clock, then passthrough TSC as stable
1883 * to the guest.
1884 */
1885 spin_lock(&ka->pvclock_gtod_sync_lock);
1886 use_master_clock = ka->use_master_clock;
1887 if (use_master_clock) {
1888 host_tsc = ka->master_cycle_now;
1889 kernel_ns = ka->master_kernel_ns;
1890 }
1891 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1892
1893 /* Keep irq disabled to prevent changes to the clock */
1894 local_irq_save(flags);
78db6a50
PB		 1895 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1896 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1897 local_irq_restore(flags);
1898 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1899 return 1;
1900 }
d828199e 1901 if (!use_master_clock) {
4ea1636b 1902 host_tsc = rdtsc();
108b249c 1903 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1904 }
1905
4ba76538 1906 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1907
c285545f
ZA		 1908 /*
1909 * We may have to catch up the TSC to match elapsed wall clock
1910 * time for two reasons, even if kvmclock is used.
1911 * 1) CPU could have been running below the maximum TSC rate
1912 * 2) Broken TSC compensation resets the base at each VCPU
1913 * entry to avoid unknown leaps of TSC even when running
1914 * again on the same CPU. This may cause apparent elapsed
1915 * time to disappear, and the guest to stand still or run
1916 * very slowly.
1917 */
1918 if (vcpu->tsc_catchup) {
1919 u64 tsc = compute_guest_tsc(v, kernel_ns);
1920 if (tsc > tsc_timestamp) {
f1e2b260 1921 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1922 tsc_timestamp = tsc;
1923 }
50d0a0f9
GH		 1924 }
1925
18068523
GOC		 1926 local_irq_restore(flags);
1927
0d6dd2ff 1928 /* With all the info we got, fill in the values */
18068523 1929
78db6a50
PB		 1930 if (kvm_has_tsc_control)
1931 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1932
1933 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1934 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1935 &vcpu->hv_clock.tsc_shift,
1936 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1937 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1938 }
1939
1d5f066e 1940 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1941 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1942 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1943
d828199e 1944 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1945 pvclock_flags = 0;
d828199e
MT		 1946 if (use_master_clock)
1947 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1948
78c0337a
MT		 1949 vcpu->hv_clock.flags = pvclock_flags;
1950
095cf55d
PB		 1951 if (vcpu->pv_time_enabled)
1952 kvm_setup_pvclock_page(v);
1953 if (v == kvm_get_vcpu(v->kvm, 0))
1954 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1955 return 0;
c8076604
GH		 1956}
1957
0061d53d
MT		 1958/*
1959 * kvmclock updates which are isolated to a given vcpu, such as
1960 * vcpu->cpu migration, should not allow system_timestamp from
1961 * the rest of the vcpus to remain static. Otherwise ntp frequency
1962 * correction applies to one vcpu's system_timestamp but not
1963 * the others.
1964 *
1965 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1966 * We need to rate-limit these requests though, as they can
1967 * considerably slow guests that have a large number of vcpus.
1968 * The time for a remote vcpu to update its kvmclock is bound
1969 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1970 */
1971
7e44e449
AJ		 1972#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1973
1974static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1975{
1976 int i;
7e44e449
AJ		 1977 struct delayed_work *dwork = to_delayed_work(work);
1978 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1979 kvmclock_update_work);
1980 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1981 struct kvm_vcpu *vcpu;
1982
1983 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1984 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1985 kvm_vcpu_kick(vcpu);
1986 }
1987}
1988
7e44e449
AJ		 1989static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1990{
1991 struct kvm *kvm = v->kvm;
1992
105b21bb 1993 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1994 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1995 KVMCLOCK_UPDATE_DELAY);
1996}
1997
332967a3
AJ		 1998#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1999
2000static void kvmclock_sync_fn(struct work_struct *work)
2001{
2002 struct delayed_work *dwork = to_delayed_work(work);
2003 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2004 kvmclock_sync_work);
2005 struct kvm *kvm = container_of(ka, struct kvm, arch);
2006
630994b3
MT		 2007 if (!kvmclock_periodic_sync)
2008 return;
2009
332967a3
AJ		 2010 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2011 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2012 KVMCLOCK_SYNC_PERIOD);
2013}
2014
9ffd986c 2015static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2016{
890ca9ae
HY		 2017 u64 mcg_cap = vcpu->arch.mcg_cap;
2018 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2019 u32 msr = msr_info->index;
2020 u64 data = msr_info->data;
890ca9ae 2021
15c4a640 2022 switch (msr) {
15c4a640 2023 case MSR_IA32_MCG_STATUS:
890ca9ae 2024 vcpu->arch.mcg_status = data;
15c4a640 2025 break;
c7ac679c 2026 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2027 if (!(mcg_cap & MCG_CTL_P))
2028 return 1;
2029 if (data != 0 && data != ~(u64)0)
2030 return -1;
2031 vcpu->arch.mcg_ctl = data;
2032 break;
2033 default:
2034 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2035 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2036 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2037 /* only 0 or all 1s can be written to IA32_MCi_CTL
2038 * some Linux kernels though clear bit 10 in bank 4 to
2039 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2040 * this to avoid an uncatched #GP in the guest
2041 */
890ca9ae 2042 if ((offset & 0x3) == 0 &&
114be429 2043 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2044 return -1;
9ffd986c
WL		 2045 if (!msr_info->host_initiated &&
2046 (offset & 0x3) == 1 && data != 0)
2047 return -1;
890ca9ae
HY		 2048 vcpu->arch.mce_banks[offset] = data;
2049 break;
2050 }
2051 return 1;
2052 }
2053 return 0;
2054}
2055
ffde22ac
ES		 2056static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2057{
2058 struct kvm *kvm = vcpu->kvm;
2059 int lm = is_long_mode(vcpu);
2060 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2061 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2062 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2063 : kvm->arch.xen_hvm_config.blob_size_32;
2064 u32 page_num = data & ~PAGE_MASK;
2065 u64 page_addr = data & PAGE_MASK;
2066 u8 *page;
2067 int r;
2068
2069 r = -E2BIG;
2070 if (page_num >= blob_size)
2071 goto out;
2072 r = -ENOMEM;
ff5c2c03
SL		 2073 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2074 if (IS_ERR(page)) {
2075 r = PTR_ERR(page);
ffde22ac 2076 goto out;
ff5c2c03 2077 }
54bf36aa 2078 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2079 goto out_free;
2080 r = 0;
2081out_free:
2082 kfree(page);
2083out:
2084 return r;
2085}
2086
344d9588
GN		 2087static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2088{
2089 gpa_t gpa = data & ~0x3f;
2090
52a5c155
WL		 2091 /* Bits 3:5 are reserved, Should be zero */
2092 if (data & 0x38)
344d9588
GN		 2093 return 1;
2094
2095 vcpu->arch.apf.msr_val = data;
2096
2097 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2098 kvm_clear_async_pf_completion_queue(vcpu);
2099 kvm_async_pf_hash_reset(vcpu);
2100 return 0;
2101 }
2102
4e335d9e 2103 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2104 sizeof(u32)))
344d9588
GN		 2105 return 1;
2106
6adba527 2107 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2108 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2109 kvm_async_pf_wakeup_all(vcpu);
2110 return 0;
2111}
2112
12f9a48f
GC		 2113static void kvmclock_reset(struct kvm_vcpu *vcpu)
2114{
0b79459b 2115 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2116}
2117
c9aaa895
GC		 2118static void record_steal_time(struct kvm_vcpu *vcpu)
2119{
2120 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2121 return;
2122
4e335d9e 2123 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2124 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2125 return;
2126
0b9f6c46
PX		 2127 vcpu->arch.st.steal.preempted = 0;
2128
35f3fae1
WL		 2129 if (vcpu->arch.st.steal.version & 1)
2130 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2131
2132 vcpu->arch.st.steal.version += 1;
2133
4e335d9e 2134 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2135 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2136
2137 smp_wmb();
2138
c54cdf14
LC		 2139 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2140 vcpu->arch.st.last_steal;
2141 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2142
4e335d9e 2143 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2144 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2145
2146 smp_wmb();
2147
2148 vcpu->arch.st.steal.version += 1;
c9aaa895 2149
4e335d9e 2150 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2151 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2152}
2153
8fe8ab46 2154int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2155{
5753785f 2156 bool pr = false;
8fe8ab46
WA		 2157 u32 msr = msr_info->index;
2158 u64 data = msr_info->data;
5753785f 2159
15c4a640 2160 switch (msr) {
2e32b719
BP		 2161 case MSR_AMD64_NB_CFG:
2162 case MSR_IA32_UCODE_REV:
2163 case MSR_IA32_UCODE_WRITE:
2164 case MSR_VM_HSAVE_PA:
2165 case MSR_AMD64_PATCH_LOADER:
2166 case MSR_AMD64_BU_CFG2:
405a353a 2167 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2168 break;
2169
15c4a640 2170 case MSR_EFER:
b69e8cae 2171 return set_efer(vcpu, data);
8f1589d9
AP		 2172 case MSR_K7_HWCR:
2173 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2174 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2175 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2176 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2177 if (data != 0) {
a737f256
CD		 2178 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2179 data);
8f1589d9
AP		 2180 return 1;
2181 }
15c4a640 2182 break;
f7c6d140
AP		 2183 case MSR_FAM10H_MMIO_CONF_BASE:
2184 if (data != 0) {
a737f256
CD		 2185 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2186 "0x%llx\n", data);
f7c6d140
AP		 2187 return 1;
2188 }
15c4a640 2189 break;
b5e2fec0
AG		 2190 case MSR_IA32_DEBUGCTLMSR:
2191 if (!data) {
2192 /* We support the non-activated case already */
2193 break;
2194 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2195 /* Values other than LBR and BTF are vendor-specific,
2196 thus reserved and should throw a #GP */
2197 return 1;
2198 }
a737f256
CD		 2199 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2200 __func__, data);
b5e2fec0 2201 break;
9ba075a6 2202 case 0x200 ... 0x2ff:
ff53604b 2203 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2204 case MSR_IA32_APICBASE:
58cb628d 2205 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2206 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2207 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2208 case MSR_IA32_TSCDEADLINE:
2209 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2210 break;
ba904635 2211 case MSR_IA32_TSC_ADJUST:
d6321d49 2212 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2213 if (!msr_info->host_initiated) {
d913b904 2214 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2215 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2216 }
2217 vcpu->arch.ia32_tsc_adjust_msr = data;
2218 }
2219 break;
15c4a640 2220 case MSR_IA32_MISC_ENABLE:
ad312c7c 2221 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2222 break;
64d60670
PB		 2223 case MSR_IA32_SMBASE:
2224 if (!msr_info->host_initiated)
2225 return 1;
2226 vcpu->arch.smbase = data;
2227 break;
11c6bffa 2228 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2229 case MSR_KVM_WALL_CLOCK:
2230 vcpu->kvm->arch.wall_clock = data;
2231 kvm_write_wall_clock(vcpu->kvm, data);
2232 break;
11c6bffa 2233 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2234 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2235 struct kvm_arch *ka = &vcpu->kvm->arch;
2236
12f9a48f 2237 kvmclock_reset(vcpu);
18068523 2238
54750f2c
MT		 2239 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2240 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2241
2242 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2243 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2244
2245 ka->boot_vcpu_runs_old_kvmclock = tmp;
2246 }
2247
18068523 2248 vcpu->arch.time = data;
0061d53d 2249 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2250
2251 /* we verify if the enable bit is set... */
2252 if (!(data & 1))
2253 break;
2254
4e335d9e 2255 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2256 &vcpu->arch.pv_time, data & ~1ULL,
2257 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2258 vcpu->arch.pv_time_enabled = false;
2259 else
2260 vcpu->arch.pv_time_enabled = true;
32cad84f 2261
18068523
GOC		 2262 break;
2263 }
344d9588
GN		 2264 case MSR_KVM_ASYNC_PF_EN:
2265 if (kvm_pv_enable_async_pf(vcpu, data))
2266 return 1;
2267 break;
c9aaa895
GC		 2268 case MSR_KVM_STEAL_TIME:
2269
2270 if (unlikely(!sched_info_on()))
2271 return 1;
2272
2273 if (data & KVM_STEAL_RESERVED_MASK)
2274 return 1;
2275
4e335d9e 2276 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2277 data & KVM_STEAL_VALID_BITS,
2278 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2279 return 1;
2280
2281 vcpu->arch.st.msr_val = data;
2282
2283 if (!(data & KVM_MSR_ENABLED))
2284 break;
2285
c9aaa895
GC		 2286 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2287
2288 break;
ae7a2a3f
MT		 2289 case MSR_KVM_PV_EOI_EN:
2290 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2291 return 1;
2292 break;
c9aaa895 2293
890ca9ae
HY		 2294 case MSR_IA32_MCG_CTL:
2295 case MSR_IA32_MCG_STATUS:
81760dcc 2296 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2297 return set_msr_mce(vcpu, msr_info);
71db6023 2298
6912ac32
WH		 2299 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2300 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2301 pr = true; /* fall through */
2302 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2303 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2304 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2305 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2306
2307 if (pr || data != 0)
a737f256
CD		 2308 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2309 "0x%x data 0x%llx\n", msr, data);
5753785f 2310 break;
84e0cefa
JS		 2311 case MSR_K7_CLK_CTL:
2312 /*
2313 * Ignore all writes to this no longer documented MSR.
2314 * Writes are only relevant for old K7 processors,
2315 * all pre-dating SVM, but a recommended workaround from
4a969980 2316 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2317 * affected processor models on the command line, hence
2318 * the need to ignore the workaround.
2319 */
2320 break;
55cd8e5a 2321 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2322 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2323 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2324 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2325 return kvm_hv_set_msr_common(vcpu, msr, data,
2326 msr_info->host_initiated);
91c9c3ed 2327 case MSR_IA32_BBL_CR_CTL3:
2328 /* Drop writes to this legacy MSR -- see rdmsr
2329 * counterpart for further detail.
2330 */
fab0aa3b
EM		 2331 if (report_ignored_msrs)
2332 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2333 msr, data);
91c9c3ed 2334 break;
2b036c6b 2335 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2336 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2337 return 1;
2338 vcpu->arch.osvw.length = data;
2339 break;
2340 case MSR_AMD64_OSVW_STATUS:
d6321d49 2341 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2342 return 1;
2343 vcpu->arch.osvw.status = data;
2344 break;
db2336a8
KH		 2345 case MSR_PLATFORM_INFO:
2346 if (!msr_info->host_initiated ||
2347 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2348 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2349 cpuid_fault_enabled(vcpu)))
2350 return 1;
2351 vcpu->arch.msr_platform_info = data;
2352 break;
2353 case MSR_MISC_FEATURES_ENABLES:
2354 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2355 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2356 !supports_cpuid_fault(vcpu)))
2357 return 1;
2358 vcpu->arch.msr_misc_features_enables = data;
2359 break;
15c4a640 2360 default:
ffde22ac
ES		 2361 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2362 return xen_hvm_config(vcpu, data);
c6702c9d 2363 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2364 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2365 if (!ignore_msrs) {
ae0f5499 2366 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2367 msr, data);
ed85c068
AP		 2368 return 1;
2369 } else {
fab0aa3b
EM		 2370 if (report_ignored_msrs)
2371 vcpu_unimpl(vcpu,
2372 "ignored wrmsr: 0x%x data 0x%llx\n",
2373 msr, data);
ed85c068
AP		 2374 break;
2375 }
15c4a640
CO		 2376 }
2377 return 0;
2378}
2379EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2380
2381
2382/*
2383 * Reads an msr value (of 'msr_index') into 'pdata'.
2384 * Returns 0 on success, non-0 otherwise.
2385 * Assumes vcpu_load() was already called.
2386 */
609e36d3 2387int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2388{
609e36d3 2389 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2390}
ff651cb6 2391EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2392
890ca9ae 2393static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2394{
2395 u64 data;
890ca9ae
HY		 2396 u64 mcg_cap = vcpu->arch.mcg_cap;
2397 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2398
2399 switch (msr) {
15c4a640
CO		 2400 case MSR_IA32_P5_MC_ADDR:
2401 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2402 data = 0;
2403 break;
15c4a640 2404 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2405 data = vcpu->arch.mcg_cap;
2406 break;
c7ac679c 2407 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2408 if (!(mcg_cap & MCG_CTL_P))
2409 return 1;
2410 data = vcpu->arch.mcg_ctl;
2411 break;
2412 case MSR_IA32_MCG_STATUS:
2413 data = vcpu->arch.mcg_status;
2414 break;
2415 default:
2416 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2417 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2418 u32 offset = msr - MSR_IA32_MC0_CTL;
2419 data = vcpu->arch.mce_banks[offset];
2420 break;
2421 }
2422 return 1;
2423 }
2424 *pdata = data;
2425 return 0;
2426}
2427
609e36d3 2428int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2429{
609e36d3 2430 switch (msr_info->index) {
890ca9ae 2431 case MSR_IA32_PLATFORM_ID:
15c4a640 2432 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2433 case MSR_IA32_DEBUGCTLMSR:
2434 case MSR_IA32_LASTBRANCHFROMIP:
2435 case MSR_IA32_LASTBRANCHTOIP:
2436 case MSR_IA32_LASTINTFROMIP:
2437 case MSR_IA32_LASTINTTOIP:
60af2ecd 2438 case MSR_K8_SYSCFG:
3afb1121
PB		 2439 case MSR_K8_TSEG_ADDR:
2440 case MSR_K8_TSEG_MASK:
60af2ecd 2441 case MSR_K7_HWCR:
61a6bd67 2442 case MSR_VM_HSAVE_PA:
1fdbd48c 2443 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2444 case MSR_AMD64_NB_CFG:
f7c6d140 2445 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2446 case MSR_AMD64_BU_CFG2:
0c2df2a1 2447 case MSR_IA32_PERF_CTL:
405a353a 2448 case MSR_AMD64_DC_CFG:
609e36d3 2449 msr_info->data = 0;
15c4a640 2450 break;
6912ac32
WH		 2451 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2452 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2453 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2454 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2455 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2456 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2457 msr_info->data = 0;
5753785f 2458 break;
742bc670 2459 case MSR_IA32_UCODE_REV:
609e36d3 2460 msr_info->data = 0x100000000ULL;
742bc670 2461 break;
9ba075a6 2462 case MSR_MTRRcap:
9ba075a6 2463 case 0x200 ... 0x2ff:
ff53604b 2464 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2465 case 0xcd: /* fsb frequency */
609e36d3 2466 msr_info->data = 3;
15c4a640 2467 break;
7b914098
JS		 2468 /*
2469 * MSR_EBC_FREQUENCY_ID
2470 * Conservative value valid for even the basic CPU models.
2471 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2472 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2473 * and 266MHz for model 3, or 4. Set Core Clock
2474 * Frequency to System Bus Frequency Ratio to 1 (bits
2475 * 31:24) even though these are only valid for CPU
2476 * models > 2, however guests may end up dividing or
2477 * multiplying by zero otherwise.
2478 */
2479 case MSR_EBC_FREQUENCY_ID:
609e36d3 2480 msr_info->data = 1 << 24;
7b914098 2481 break;
15c4a640 2482 case MSR_IA32_APICBASE:
609e36d3 2483 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2484 break;
0105d1a5 2485 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2486 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2487 break;
a3e06bbe 2488 case MSR_IA32_TSCDEADLINE:
609e36d3 2489 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2490 break;
ba904635 2491 case MSR_IA32_TSC_ADJUST:
609e36d3 2492 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2493 break;
15c4a640 2494 case MSR_IA32_MISC_ENABLE:
609e36d3 2495 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2496 break;
64d60670
PB		 2497 case MSR_IA32_SMBASE:
2498 if (!msr_info->host_initiated)
2499 return 1;
2500 msr_info->data = vcpu->arch.smbase;
15c4a640 2501 break;
847f0ad8
AG		 2502 case MSR_IA32_PERF_STATUS:
2503 /* TSC increment by tick */
609e36d3 2504 msr_info->data = 1000ULL;
847f0ad8 2505 /* CPU multiplier */
b0996ae4 2506 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2507 break;
15c4a640 2508 case MSR_EFER:
609e36d3 2509 msr_info->data = vcpu->arch.efer;
15c4a640 2510 break;
18068523 2511 case MSR_KVM_WALL_CLOCK:
11c6bffa 2512 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2513 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2514 break;
2515 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2516 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2517 msr_info->data = vcpu->arch.time;
18068523 2518 break;
344d9588 2519 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2520 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2521 break;
c9aaa895 2522 case MSR_KVM_STEAL_TIME:
609e36d3 2523 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2524 break;
1d92128f 2525 case MSR_KVM_PV_EOI_EN:
609e36d3 2526 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2527 break;
890ca9ae
HY		 2528 case MSR_IA32_P5_MC_ADDR:
2529 case MSR_IA32_P5_MC_TYPE:
2530 case MSR_IA32_MCG_CAP:
2531 case MSR_IA32_MCG_CTL:
2532 case MSR_IA32_MCG_STATUS:
81760dcc 2533 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2534 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2535 case MSR_K7_CLK_CTL:
2536 /*
2537 * Provide expected ramp-up count for K7. All other
2538 * are set to zero, indicating minimum divisors for
2539 * every field.
2540 *
2541 * This prevents guest kernels on AMD host with CPU
2542 * type 6, model 8 and higher from exploding due to
2543 * the rdmsr failing.
2544 */
609e36d3 2545 msr_info->data = 0x20000000;
84e0cefa 2546 break;
55cd8e5a 2547 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2548 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2549 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2550 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2551 return kvm_hv_get_msr_common(vcpu,
2552 msr_info->index, &msr_info->data);
55cd8e5a 2553 break;
91c9c3ed 2554 case MSR_IA32_BBL_CR_CTL3:
2555 /* This legacy MSR exists but isn't fully documented in current
2556 * silicon. It is however accessed by winxp in very narrow
2557 * scenarios where it sets bit #19, itself documented as
2558 * a "reserved" bit. Best effort attempt to source coherent
2559 * read data here should the balance of the register be
2560 * interpreted by the guest:
2561 *
2562 * L2 cache control register 3: 64GB range, 256KB size,
2563 * enabled, latency 0x1, configured
2564 */
609e36d3 2565 msr_info->data = 0xbe702111;
91c9c3ed 2566 break;
2b036c6b 2567 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2568 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2569 return 1;
609e36d3 2570 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2571 break;
2572 case MSR_AMD64_OSVW_STATUS:
d6321d49 2573 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2574 return 1;
609e36d3 2575 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2576 break;
db2336a8
KH		 2577 case MSR_PLATFORM_INFO:
2578 msr_info->data = vcpu->arch.msr_platform_info;
2579 break;
2580 case MSR_MISC_FEATURES_ENABLES:
2581 msr_info->data = vcpu->arch.msr_misc_features_enables;
2582 break;
15c4a640 2583 default:
c6702c9d 2584 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2585 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2586 if (!ignore_msrs) {
ae0f5499
BD		 2587 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2588 msr_info->index);
ed85c068
AP		 2589 return 1;
2590 } else {
fab0aa3b
EM		 2591 if (report_ignored_msrs)
2592 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2593 msr_info->index);
609e36d3 2594 msr_info->data = 0;
ed85c068
AP		 2595 }
2596 break;
15c4a640 2597 }
15c4a640
CO		 2598 return 0;
2599}
2600EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2601
313a3dc7
CO		 2602/*
2603 * Read or write a bunch of msrs. All parameters are kernel addresses.
2604 *
2605 * @return number of msrs set successfully.
2606 */
2607static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2608 struct kvm_msr_entry *entries,
2609 int (*do_msr)(struct kvm_vcpu *vcpu,
2610 unsigned index, u64 *data))
2611{
f656ce01 2612 int i, idx;
313a3dc7 2613
f656ce01 2614 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2615 for (i = 0; i < msrs->nmsrs; ++i)
2616 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2617 break;
f656ce01 2618 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2619
313a3dc7
CO		 2620 return i;
2621}
2622
2623/*
2624 * Read or write a bunch of msrs. Parameters are user addresses.
2625 *
2626 * @return number of msrs set successfully.
2627 */
2628static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2629 int (*do_msr)(struct kvm_vcpu *vcpu,
2630 unsigned index, u64 *data),
2631 int writeback)
2632{
2633 struct kvm_msrs msrs;
2634 struct kvm_msr_entry *entries;
2635 int r, n;
2636 unsigned size;
2637
2638 r = -EFAULT;
2639 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2640 goto out;
2641
2642 r = -E2BIG;
2643 if (msrs.nmsrs >= MAX_IO_MSRS)
2644 goto out;
2645
313a3dc7 2646 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2647 entries = memdup_user(user_msrs->entries, size);
2648 if (IS_ERR(entries)) {
2649 r = PTR_ERR(entries);
313a3dc7 2650 goto out;
ff5c2c03 2651 }
313a3dc7
CO		 2652
2653 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2654 if (r < 0)
2655 goto out_free;
2656
2657 r = -EFAULT;
2658 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2659 goto out_free;
2660
2661 r = n;
2662
2663out_free:
7a73c028 2664 kfree(entries);
313a3dc7
CO		 2665out:
2666 return r;
2667}
2668
784aa3d7 2669int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2670{
2671 int r;
2672
2673 switch (ext) {
2674 case KVM_CAP_IRQCHIP:
2675 case KVM_CAP_HLT:
2676 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2677 case KVM_CAP_SET_TSS_ADDR:
07716717 2678 case KVM_CAP_EXT_CPUID:
9c15bb1d 2679 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2680 case KVM_CAP_CLOCKSOURCE:
7837699f 2681 case KVM_CAP_PIT:
a28e4f5a 2682 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2683 case KVM_CAP_MP_STATE:
ed848624 2684 case KVM_CAP_SYNC_MMU:
a355c85c 2685 case KVM_CAP_USER_NMI:
52d939a0 2686 case KVM_CAP_REINJECT_CONTROL:
4925663a 2687 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2688 case KVM_CAP_IOEVENTFD:
f848a5a8 2689 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2690 case KVM_CAP_PIT2:
e9f42757 2691 case KVM_CAP_PIT_STATE2:
b927a3ce 2692 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2693 case KVM_CAP_XEN_HVM:
3cfc3092 2694 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2695 case KVM_CAP_HYPERV:
10388a07 2696 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2697 case KVM_CAP_HYPERV_SPIN:
5c919412 2698 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2699 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2700 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2701 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2702 case KVM_CAP_DEBUGREGS:
d2be1651 2703 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2704 case KVM_CAP_XSAVE:
344d9588 2705 case KVM_CAP_ASYNC_PF:
92a1f12d 2706 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2707 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2708 case KVM_CAP_READONLY_MEM:
5f66b620 2709 case KVM_CAP_HYPERV_TIME:
100943c5 2710 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2711 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2712 case KVM_CAP_ENABLE_CAP_VM:
2713 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2714 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2715 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2716 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2717 r = 1;
2718 break;
e3fd9a93
PB		 2719 case KVM_CAP_ADJUST_CLOCK:
2720 r = KVM_CLOCK_TSC_STABLE;
2721 break;
668fffa3
MT		 2722 case KVM_CAP_X86_GUEST_MWAIT:
2723 r = kvm_mwait_in_guest();
2724 break;
6d396b55
PB		 2725 case KVM_CAP_X86_SMM:
2726 /* SMBASE is usually relocated above 1M on modern chipsets,
2727 * and SMM handlers might indeed rely on 4G segment limits,
2728 * so do not report SMM to be available if real mode is
2729 * emulated via vm86 mode. Still, do not go to great lengths
2730 * to avoid userspace's usage of the feature, because it is a
2731 * fringe case that is not enabled except via specific settings
2732 * of the module parameters.
2733 */
2734 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2735 break;
774ead3a
AK		 2736 case KVM_CAP_VAPIC:
2737 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2738 break;
f725230a 2739 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2740 r = KVM_SOFT_MAX_VCPUS;
2741 break;
2742 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2743 r = KVM_MAX_VCPUS;
2744 break;
a988b910 2745 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2746 r = KVM_USER_MEM_SLOTS;
a988b910 2747 break;
a68a6a72
MT		 2748 case KVM_CAP_PV_MMU: /* obsolete */
2749 r = 0;
2f333bcb 2750 break;
890ca9ae
HY		 2751 case KVM_CAP_MCE:
2752 r = KVM_MAX_MCE_BANKS;
2753 break;
2d5b5a66 2754 case KVM_CAP_XCRS:
d366bf7e 2755 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2756 break;
92a1f12d
JR		 2757 case KVM_CAP_TSC_CONTROL:
2758 r = kvm_has_tsc_control;
2759 break;
37131313
RK		 2760 case KVM_CAP_X2APIC_API:
2761 r = KVM_X2APIC_API_VALID_FLAGS;
2762 break;
018d00d2
ZX		 2763 default:
2764 r = 0;
2765 break;
2766 }
2767 return r;
2768
2769}
2770
043405e1
CO		 2771long kvm_arch_dev_ioctl(struct file *filp,
2772 unsigned int ioctl, unsigned long arg)
2773{
2774 void __user *argp = (void __user *)arg;
2775 long r;
2776
2777 switch (ioctl) {
2778 case KVM_GET_MSR_INDEX_LIST: {
2779 struct kvm_msr_list __user *user_msr_list = argp;
2780 struct kvm_msr_list msr_list;
2781 unsigned n;
2782
2783 r = -EFAULT;
2784 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2785 goto out;
2786 n = msr_list.nmsrs;
62ef68bb 2787 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2788 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2789 goto out;
2790 r = -E2BIG;
e125e7b6 2791 if (n < msr_list.nmsrs)
043405e1
CO		 2792 goto out;
2793 r = -EFAULT;
2794 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2795 num_msrs_to_save * sizeof(u32)))
2796 goto out;
e125e7b6 2797 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2798 &emulated_msrs,
62ef68bb 2799 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2800 goto out;
2801 r = 0;
2802 break;
2803 }
9c15bb1d
BP		 2804 case KVM_GET_SUPPORTED_CPUID:
2805 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2806 struct kvm_cpuid2 __user *cpuid_arg = argp;
2807 struct kvm_cpuid2 cpuid;
2808
2809 r = -EFAULT;
2810 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2811 goto out;
9c15bb1d
BP		 2812
2813 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2814 ioctl);
674eea0f
AK		 2815 if (r)
2816 goto out;
2817
2818 r = -EFAULT;
2819 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2820 goto out;
2821 r = 0;
2822 break;
2823 }
890ca9ae 2824 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2825 r = -EFAULT;
c45dcc71
AR		 2826 if (copy_to_user(argp, &kvm_mce_cap_supported,
2827 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2828 goto out;
2829 r = 0;
2830 break;
2831 }
043405e1
CO		 2832 default:
2833 r = -EINVAL;
2834 }
2835out:
2836 return r;
2837}
2838
f5f48ee1
SY		 2839static void wbinvd_ipi(void *garbage)
2840{
2841 wbinvd();
2842}
2843
2844static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2845{
e0f0bbc5 2846 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2847}
2848
313a3dc7
CO		 2849void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2850{
f5f48ee1
SY		 2851 /* Address WBINVD may be executed by guest */
2852 if (need_emulate_wbinvd(vcpu)) {
2853 if (kvm_x86_ops->has_wbinvd_exit())
2854 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2855 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2856 smp_call_function_single(vcpu->cpu,
2857 wbinvd_ipi, NULL, 1);
2858 }
2859
313a3dc7 2860 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2861
0dd6a6ed
ZA		 2862 /* Apply any externally detected TSC adjustments (due to suspend) */
2863 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2864 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2865 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2866 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2867 }
8f6055cb 2868
48434c20 2869 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2870 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2871 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2872 if (tsc_delta < 0)
2873 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2874
c285545f 2875 if (check_tsc_unstable()) {
07c1419a 2876 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2877 vcpu->arch.last_guest_tsc);
a545ab6a 2878 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2879 vcpu->arch.tsc_catchup = 1;
c285545f 2880 }
a749e247
PB		 2881
2882 if (kvm_lapic_hv_timer_in_use(vcpu))
2883 kvm_lapic_restart_hv_timer(vcpu);
2884
d98d07ca
MT		 2885 /*
2886 * On a host with synchronized TSC, there is no need to update
2887 * kvmclock on vcpu->cpu migration
2888 */
2889 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2890 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2891 if (vcpu->cpu != cpu)
1bd2009e 2892 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2893 vcpu->cpu = cpu;
6b7d7e76 2894 }
c9aaa895 2895
c9aaa895 2896 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2897}
2898
0b9f6c46
PX		 2899static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2900{
2901 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2902 return;
2903
2904 vcpu->arch.st.steal.preempted = 1;
2905
4e335d9e 2906 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2907 &vcpu->arch.st.steal.preempted,
2908 offsetof(struct kvm_steal_time, preempted),
2909 sizeof(vcpu->arch.st.steal.preempted));
2910}
2911
313a3dc7
CO		 2912void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2913{
cc0d907c 2914 int idx;
de63ad4c
LM		 2915
2916 if (vcpu->preempted)
2917 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2918
931f261b
AA		 2919 /*
2920 * Disable page faults because we're in atomic context here.
2921 * kvm_write_guest_offset_cached() would call might_fault()
2922 * that relies on pagefault_disable() to tell if there's a
2923 * bug. NOTE: the write to guest memory may not go through if
2924 * during postcopy live migration or if there's heavy guest
2925 * paging.
2926 */
2927 pagefault_disable();
cc0d907c
AA		 2928 /*
2929 * kvm_memslots() will be called by
2930 * kvm_write_guest_offset_cached() so take the srcu lock.
2931 */
2932 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2933 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2934 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2935 pagefault_enable();
02daab21 2936 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2937 kvm_put_guest_fpu(vcpu);
4ea1636b 2938 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2939}
2940
313a3dc7
CO		 2941static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2942 struct kvm_lapic_state *s)
2943{
76dfafd5 2944 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2945 kvm_x86_ops->sync_pir_to_irr(vcpu);
2946
a92e2543 2947 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2948}
2949
2950static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2951 struct kvm_lapic_state *s)
2952{
a92e2543
RK		 2953 int r;
2954
2955 r = kvm_apic_set_state(vcpu, s);
2956 if (r)
2957 return r;
cb142eb7 2958 update_cr8_intercept(vcpu);
313a3dc7
CO		 2959
2960 return 0;
2961}
2962
127a457a
MG		 2963static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2964{
2965 return (!lapic_in_kernel(vcpu) ||
2966 kvm_apic_accept_pic_intr(vcpu));
2967}
2968
782d422b
MG		 2969/*
2970 * if userspace requested an interrupt window, check that the
2971 * interrupt window is open.
2972 *
2973 * No need to exit to userspace if we already have an interrupt queued.
2974 */
2975static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2976{
2977 return kvm_arch_interrupt_allowed(vcpu) &&
2978 !kvm_cpu_has_interrupt(vcpu) &&
2979 !kvm_event_needs_reinjection(vcpu) &&
2980 kvm_cpu_accept_dm_intr(vcpu);
2981}
2982
f77bc6a4
ZX		 2983static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2984 struct kvm_interrupt *irq)
2985{
02cdb50f 2986 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2987 return -EINVAL;
1c1a9ce9
SR		 2988
2989 if (!irqchip_in_kernel(vcpu->kvm)) {
2990 kvm_queue_interrupt(vcpu, irq->irq, false);
2991 kvm_make_request(KVM_REQ_EVENT, vcpu);
2992 return 0;
2993 }
2994
2995 /*
2996 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2997 * fail for in-kernel 8259.
2998 */
2999 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3000 return -ENXIO;
f77bc6a4 3001
1c1a9ce9
SR		 3002 if (vcpu->arch.pending_external_vector != -1)
3003 return -EEXIST;
f77bc6a4 3004
1c1a9ce9 3005 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3006 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3007 return 0;
3008}
3009
c4abb7c9
JK		 3010static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3011{
c4abb7c9 3012 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3013
3014 return 0;
3015}
3016
f077825a
PB		 3017static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3018{
64d60670
PB		 3019 kvm_make_request(KVM_REQ_SMI, vcpu);
3020
f077825a
PB		 3021 return 0;
3022}
3023
b209749f
AK		 3024static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3025 struct kvm_tpr_access_ctl *tac)
3026{
3027 if (tac->flags)
3028 return -EINVAL;
3029 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3030 return 0;
3031}
3032
890ca9ae
HY		 3033static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3034 u64 mcg_cap)
3035{
3036 int r;
3037 unsigned bank_num = mcg_cap & 0xff, bank;
3038
3039 r = -EINVAL;
a9e38c3e 3040 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3041 goto out;
c45dcc71 3042 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3043 goto out;
3044 r = 0;
3045 vcpu->arch.mcg_cap = mcg_cap;
3046 /* Init IA32_MCG_CTL to all 1s */
3047 if (mcg_cap & MCG_CTL_P)
3048 vcpu->arch.mcg_ctl = ~(u64)0;
3049 /* Init IA32_MCi_CTL to all 1s */
3050 for (bank = 0; bank < bank_num; bank++)
3051 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3052
3053 if (kvm_x86_ops->setup_mce)
3054 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3055out:
3056 return r;
3057}
3058
3059static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3060 struct kvm_x86_mce *mce)
3061{
3062 u64 mcg_cap = vcpu->arch.mcg_cap;
3063 unsigned bank_num = mcg_cap & 0xff;
3064 u64 *banks = vcpu->arch.mce_banks;
3065
3066 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3067 return -EINVAL;
3068 /*
3069 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3070 * reporting is disabled
3071 */
3072 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3073 vcpu->arch.mcg_ctl != ~(u64)0)
3074 return 0;
3075 banks += 4 * mce->bank;
3076 /*
3077 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3078 * reporting is disabled for the bank
3079 */
3080 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3081 return 0;
3082 if (mce->status & MCI_STATUS_UC) {
3083 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3084 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3085 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3086 return 0;
3087 }
3088 if (banks[1] & MCI_STATUS_VAL)
3089 mce->status |= MCI_STATUS_OVER;
3090 banks[2] = mce->addr;
3091 banks[3] = mce->misc;
3092 vcpu->arch.mcg_status = mce->mcg_status;
3093 banks[1] = mce->status;
3094 kvm_queue_exception(vcpu, MC_VECTOR);
3095 } else if (!(banks[1] & MCI_STATUS_VAL)
3096 || !(banks[1] & MCI_STATUS_UC)) {
3097 if (banks[1] & MCI_STATUS_VAL)
3098 mce->status |= MCI_STATUS_OVER;
3099 banks[2] = mce->addr;
3100 banks[3] = mce->misc;
3101 banks[1] = mce->status;
3102 } else
3103 banks[1] |= MCI_STATUS_OVER;
3104 return 0;
3105}
3106
3cfc3092
JK		 3107static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3108 struct kvm_vcpu_events *events)
3109{
7460fb4a 3110 process_nmi(vcpu);
664f8e26
WL		 3111 /*
3112 * FIXME: pass injected and pending separately. This is only
3113 * needed for nested virtualization, whose state cannot be
3114 * migrated yet. For now we can combine them.
3115 */
03b82a30 3116 events->exception.injected =
664f8e26
WL		 3117 (vcpu->arch.exception.pending ||
3118 vcpu->arch.exception.injected) &&
03b82a30 3119 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3120 events->exception.nr = vcpu->arch.exception.nr;
3121 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3122 events->exception.pad = 0;
3cfc3092
JK		 3123 events->exception.error_code = vcpu->arch.exception.error_code;
3124
03b82a30
JK		 3125 events->interrupt.injected =
3126 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3127 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3128 events->interrupt.soft = 0;
37ccdcbe 3129 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3130
3131 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3132 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3133 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3134 events->nmi.pad = 0;
3cfc3092 3135
66450a21 3136 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3137
f077825a
PB		 3138 events->smi.smm = is_smm(vcpu);
3139 events->smi.pending = vcpu->arch.smi_pending;
3140 events->smi.smm_inside_nmi =
3141 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3142 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3143
dab4b911 3144 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3145 | KVM_VCPUEVENT_VALID_SHADOW
3146 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3147 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3148}
3149
6ef4e07e
XG		 3150static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3151
3cfc3092
JK		 3152static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3153 struct kvm_vcpu_events *events)
3154{
dab4b911 3155 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3156 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3157 | KVM_VCPUEVENT_VALID_SHADOW
3158 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3159 return -EINVAL;
3160
78e546c8 3161 if (events->exception.injected &&
28d06353
JM		 3162 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3163 is_guest_mode(vcpu)))
78e546c8
PB		 3164 return -EINVAL;
3165
28bf2888
DH		 3166 /* INITs are latched while in SMM */
3167 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3168 (events->smi.smm || events->smi.pending) &&
3169 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3170 return -EINVAL;
3171
7460fb4a 3172 process_nmi(vcpu);
664f8e26 3173 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3174 vcpu->arch.exception.pending = events->exception.injected;
3175 vcpu->arch.exception.nr = events->exception.nr;
3176 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3177 vcpu->arch.exception.error_code = events->exception.error_code;
3178
3179 vcpu->arch.interrupt.pending = events->interrupt.injected;
3180 vcpu->arch.interrupt.nr = events->interrupt.nr;
3181 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3182 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3183 kvm_x86_ops->set_interrupt_shadow(vcpu,
3184 events->interrupt.shadow);
3cfc3092
JK		 3185
3186 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3187 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3188 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3189 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3190
66450a21 3191 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3192 lapic_in_kernel(vcpu))
66450a21 3193 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3194
f077825a 3195 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3196 u32 hflags = vcpu->arch.hflags;
f077825a 3197 if (events->smi.smm)
6ef4e07e 3198 hflags |= HF_SMM_MASK;
f077825a 3199 else
6ef4e07e
XG		 3200 hflags &= ~HF_SMM_MASK;
3201 kvm_set_hflags(vcpu, hflags);
3202
f077825a 3203 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3204
3205 if (events->smi.smm) {
3206 if (events->smi.smm_inside_nmi)
3207 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3208 else
f4ef1910
WL		 3209 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3210 if (lapic_in_kernel(vcpu)) {
3211 if (events->smi.latched_init)
3212 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3213 else
3214 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3215 }
f077825a
PB		 3216 }
3217 }
3218
3842d135
AK		 3219 kvm_make_request(KVM_REQ_EVENT, vcpu);
3220
3cfc3092
JK		 3221 return 0;
3222}
3223
a1efbe77
JK		 3224static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3225 struct kvm_debugregs *dbgregs)
3226{
73aaf249
JK		 3227 unsigned long val;
3228
a1efbe77 3229 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3230 kvm_get_dr(vcpu, 6, &val);
73aaf249 3231 dbgregs->dr6 = val;
a1efbe77
JK		 3232 dbgregs->dr7 = vcpu->arch.dr7;
3233 dbgregs->flags = 0;
97e69aa6 3234 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3235}
3236
3237static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3238 struct kvm_debugregs *dbgregs)
3239{
3240 if (dbgregs->flags)
3241 return -EINVAL;
3242
d14bdb55
PB		 3243 if (dbgregs->dr6 & ~0xffffffffull)
3244 return -EINVAL;
3245 if (dbgregs->dr7 & ~0xffffffffull)
3246 return -EINVAL;
3247
a1efbe77 3248 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3249 kvm_update_dr0123(vcpu);
a1efbe77 3250 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3251 kvm_update_dr6(vcpu);
a1efbe77 3252 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3253 kvm_update_dr7(vcpu);
a1efbe77 3254
a1efbe77
JK		 3255 return 0;
3256}
3257
df1daba7
PB		 3258#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3259
3260static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3261{
c47ada30 3262 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3263 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3264 u64 valid;
3265
3266 /*
3267 * Copy legacy XSAVE area, to avoid complications with CPUID
3268 * leaves 0 and 1 in the loop below.
3269 */
3270 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3271
3272 /* Set XSTATE_BV */
00c87e9a 3273 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3274 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3275
3276 /*
3277 * Copy each region from the possibly compacted offset to the
3278 * non-compacted offset.
3279 */
d91cab78 3280 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3281 while (valid) {
3282 u64 feature = valid & -valid;
3283 int index = fls64(feature) - 1;
3284 void *src = get_xsave_addr(xsave, feature);
3285
3286 if (src) {
3287 u32 size, offset, ecx, edx;
3288 cpuid_count(XSTATE_CPUID, index,
3289 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3290 if (feature == XFEATURE_MASK_PKRU)
3291 memcpy(dest + offset, &vcpu->arch.pkru,
3292 sizeof(vcpu->arch.pkru));
3293 else
3294 memcpy(dest + offset, src, size);
3295
df1daba7
PB		 3296 }
3297
3298 valid -= feature;
3299 }
3300}
3301
3302static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3303{
c47ada30 3304 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3305 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3306 u64 valid;
3307
3308 /*
3309 * Copy legacy XSAVE area, to avoid complications with CPUID
3310 * leaves 0 and 1 in the loop below.
3311 */
3312 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3313
3314 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3315 xsave->header.xfeatures = xstate_bv;
782511b0 3316 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3317 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3318
3319 /*
3320 * Copy each region from the non-compacted offset to the
3321 * possibly compacted offset.
3322 */
d91cab78 3323 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3324 while (valid) {
3325 u64 feature = valid & -valid;
3326 int index = fls64(feature) - 1;
3327 void *dest = get_xsave_addr(xsave, feature);
3328
3329 if (dest) {
3330 u32 size, offset, ecx, edx;
3331 cpuid_count(XSTATE_CPUID, index,
3332 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3333 if (feature == XFEATURE_MASK_PKRU)
3334 memcpy(&vcpu->arch.pkru, src + offset,
3335 sizeof(vcpu->arch.pkru));
3336 else
3337 memcpy(dest, src + offset, size);
ee4100da 3338 }
df1daba7
PB		 3339
3340 valid -= feature;
3341 }
3342}
3343
2d5b5a66
SY		 3344static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3345 struct kvm_xsave *guest_xsave)
3346{
d366bf7e 3347 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3348 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3349 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3350 } else {
2d5b5a66 3351 memcpy(guest_xsave->region,
7366ed77 3352 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3353 sizeof(struct fxregs_state));
2d5b5a66 3354 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3355 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3356 }
3357}
3358
a575813b
WL		 3359#define XSAVE_MXCSR_OFFSET 24
3360
2d5b5a66
SY		 3361static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3362 struct kvm_xsave *guest_xsave)
3363{
3364 u64 xstate_bv =
3365 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3366 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3367
d366bf7e 3368 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3369 /*
3370 * Here we allow setting states that are not present in
3371 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3372 * with old userspace.
3373 */
a575813b
WL		 3374 if (xstate_bv & ~kvm_supported_xcr0() ||
3375 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3376 return -EINVAL;
df1daba7 3377 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3378 } else {
a575813b
WL		 3379 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3380 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3381 return -EINVAL;
7366ed77 3382 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3383 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3384 }
3385 return 0;
3386}
3387
3388static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3389 struct kvm_xcrs *guest_xcrs)
3390{
d366bf7e 3391 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3392 guest_xcrs->nr_xcrs = 0;
3393 return;
3394 }
3395
3396 guest_xcrs->nr_xcrs = 1;
3397 guest_xcrs->flags = 0;
3398 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3399 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3400}
3401
3402static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3403 struct kvm_xcrs *guest_xcrs)
3404{
3405 int i, r = 0;
3406
d366bf7e 3407 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3408 return -EINVAL;
3409
3410 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3411 return -EINVAL;
3412
3413 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3414 /* Only support XCR0 currently */
c67a04cb 3415 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3416 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3417 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3418 break;
3419 }
3420 if (r)
3421 r = -EINVAL;
3422 return r;
3423}
3424
1c0b28c2
EM		 3425/*
3426 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3427 * stopped by the hypervisor. This function will be called from the host only.
3428 * EINVAL is returned when the host attempts to set the flag for a guest that
3429 * does not support pv clocks.
3430 */
3431static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3432{
0b79459b 3433 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3434 return -EINVAL;
51d59c6b 3435 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3436 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3437 return 0;
3438}
3439
5c919412
AS		 3440static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3441 struct kvm_enable_cap *cap)
3442{
3443 if (cap->flags)
3444 return -EINVAL;
3445
3446 switch (cap->cap) {
efc479e6
RK		 3447 case KVM_CAP_HYPERV_SYNIC2:
3448 if (cap->args[0])
3449 return -EINVAL;
5c919412 3450 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3451 if (!irqchip_in_kernel(vcpu->kvm))
3452 return -EINVAL;
efc479e6
RK		 3453 return kvm_hv_activate_synic(vcpu, cap->cap ==
3454 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3455 default:
3456 return -EINVAL;
3457 }
3458}
3459
313a3dc7
CO		 3460long kvm_arch_vcpu_ioctl(struct file *filp,
3461 unsigned int ioctl, unsigned long arg)
3462{
3463 struct kvm_vcpu *vcpu = filp->private_data;
3464 void __user *argp = (void __user *)arg;
3465 int r;
d1ac91d8
AK		 3466 union {
3467 struct kvm_lapic_state *lapic;
3468 struct kvm_xsave *xsave;
3469 struct kvm_xcrs *xcrs;
3470 void *buffer;
3471 } u;
3472
3473 u.buffer = NULL;
313a3dc7
CO		 3474 switch (ioctl) {
3475 case KVM_GET_LAPIC: {
2204ae3c 3476 r = -EINVAL;
bce87cce 3477 if (!lapic_in_kernel(vcpu))
2204ae3c 3478 goto out;
d1ac91d8 3479 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3480
b772ff36 3481 r = -ENOMEM;
d1ac91d8 3482 if (!u.lapic)
b772ff36 3483 goto out;
d1ac91d8 3484 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3485 if (r)
3486 goto out;
3487 r = -EFAULT;
d1ac91d8 3488 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3489 goto out;
3490 r = 0;
3491 break;
3492 }
3493 case KVM_SET_LAPIC: {
2204ae3c 3494 r = -EINVAL;
bce87cce 3495 if (!lapic_in_kernel(vcpu))
2204ae3c 3496 goto out;
ff5c2c03 3497 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3498 if (IS_ERR(u.lapic))
3499 return PTR_ERR(u.lapic);
ff5c2c03 3500
d1ac91d8 3501 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3502 break;
3503 }
f77bc6a4
ZX		 3504 case KVM_INTERRUPT: {
3505 struct kvm_interrupt irq;
3506
3507 r = -EFAULT;
3508 if (copy_from_user(&irq, argp, sizeof irq))
3509 goto out;
3510 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3511 break;
3512 }
c4abb7c9
JK		 3513 case KVM_NMI: {
3514 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3515 break;
3516 }
f077825a
PB		 3517 case KVM_SMI: {
3518 r = kvm_vcpu_ioctl_smi(vcpu);
3519 break;
3520 }
313a3dc7
CO		 3521 case KVM_SET_CPUID: {
3522 struct kvm_cpuid __user *cpuid_arg = argp;
3523 struct kvm_cpuid cpuid;
3524
3525 r = -EFAULT;
3526 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3527 goto out;
3528 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3529 break;
3530 }
07716717
DK		 3531 case KVM_SET_CPUID2: {
3532 struct kvm_cpuid2 __user *cpuid_arg = argp;
3533 struct kvm_cpuid2 cpuid;
3534
3535 r = -EFAULT;
3536 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3537 goto out;
3538 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3539 cpuid_arg->entries);
07716717
DK		 3540 break;
3541 }
3542 case KVM_GET_CPUID2: {
3543 struct kvm_cpuid2 __user *cpuid_arg = argp;
3544 struct kvm_cpuid2 cpuid;
3545
3546 r = -EFAULT;
3547 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3548 goto out;
3549 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3550 cpuid_arg->entries);
07716717
DK		 3551 if (r)
3552 goto out;
3553 r = -EFAULT;
3554 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3555 goto out;
3556 r = 0;
3557 break;
3558 }
313a3dc7 3559 case KVM_GET_MSRS:
609e36d3 3560 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3561 break;
3562 case KVM_SET_MSRS:
3563 r = msr_io(vcpu, argp, do_set_msr, 0);
3564 break;
b209749f
AK		 3565 case KVM_TPR_ACCESS_REPORTING: {
3566 struct kvm_tpr_access_ctl tac;
3567
3568 r = -EFAULT;
3569 if (copy_from_user(&tac, argp, sizeof tac))
3570 goto out;
3571 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3572 if (r)
3573 goto out;
3574 r = -EFAULT;
3575 if (copy_to_user(argp, &tac, sizeof tac))
3576 goto out;
3577 r = 0;
3578 break;
3579 };
b93463aa
AK		 3580 case KVM_SET_VAPIC_ADDR: {
3581 struct kvm_vapic_addr va;
7301d6ab 3582 int idx;
b93463aa
AK		 3583
3584 r = -EINVAL;
35754c98 3585 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3586 goto out;
3587 r = -EFAULT;
3588 if (copy_from_user(&va, argp, sizeof va))
3589 goto out;
7301d6ab 3590 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3591 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3592 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3593 break;
3594 }
890ca9ae
HY		 3595 case KVM_X86_SETUP_MCE: {
3596 u64 mcg_cap;
3597
3598 r = -EFAULT;
3599 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3600 goto out;
3601 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3602 break;
3603 }
3604 case KVM_X86_SET_MCE: {
3605 struct kvm_x86_mce mce;
3606
3607 r = -EFAULT;
3608 if (copy_from_user(&mce, argp, sizeof mce))
3609 goto out;
3610 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3611 break;
3612 }
3cfc3092
JK		 3613 case KVM_GET_VCPU_EVENTS: {
3614 struct kvm_vcpu_events events;
3615
3616 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3617
3618 r = -EFAULT;
3619 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3620 break;
3621 r = 0;
3622 break;
3623 }
3624 case KVM_SET_VCPU_EVENTS: {
3625 struct kvm_vcpu_events events;
3626
3627 r = -EFAULT;
3628 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3629 break;
3630
3631 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3632 break;
3633 }
a1efbe77
JK		 3634 case KVM_GET_DEBUGREGS: {
3635 struct kvm_debugregs dbgregs;
3636
3637 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3638
3639 r = -EFAULT;
3640 if (copy_to_user(argp, &dbgregs,
3641 sizeof(struct kvm_debugregs)))
3642 break;
3643 r = 0;
3644 break;
3645 }
3646 case KVM_SET_DEBUGREGS: {
3647 struct kvm_debugregs dbgregs;
3648
3649 r = -EFAULT;
3650 if (copy_from_user(&dbgregs, argp,
3651 sizeof(struct kvm_debugregs)))
3652 break;
3653
3654 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3655 break;
3656 }
2d5b5a66 3657 case KVM_GET_XSAVE: {
d1ac91d8 3658 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3659 r = -ENOMEM;
d1ac91d8 3660 if (!u.xsave)
2d5b5a66
SY		 3661 break;
3662
d1ac91d8 3663 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3664
3665 r = -EFAULT;
d1ac91d8 3666 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3667 break;
3668 r = 0;
3669 break;
3670 }
3671 case KVM_SET_XSAVE: {
ff5c2c03 3672 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3673 if (IS_ERR(u.xsave))
3674 return PTR_ERR(u.xsave);
2d5b5a66 3675
d1ac91d8 3676 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3677 break;
3678 }
3679 case KVM_GET_XCRS: {
d1ac91d8 3680 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3681 r = -ENOMEM;
d1ac91d8 3682 if (!u.xcrs)
2d5b5a66
SY		 3683 break;
3684
d1ac91d8 3685 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3686
3687 r = -EFAULT;
d1ac91d8 3688 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3689 sizeof(struct kvm_xcrs)))
3690 break;
3691 r = 0;
3692 break;
3693 }
3694 case KVM_SET_XCRS: {
ff5c2c03 3695 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3696 if (IS_ERR(u.xcrs))
3697 return PTR_ERR(u.xcrs);
2d5b5a66 3698
d1ac91d8 3699 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3700 break;
3701 }
92a1f12d
JR		 3702 case KVM_SET_TSC_KHZ: {
3703 u32 user_tsc_khz;
3704
3705 r = -EINVAL;
92a1f12d
JR		 3706 user_tsc_khz = (u32)arg;
3707
3708 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3709 goto out;
3710
cc578287
ZA		 3711 if (user_tsc_khz == 0)
3712 user_tsc_khz = tsc_khz;
3713
381d585c
HZ		 3714 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3715 r = 0;
92a1f12d 3716
92a1f12d
JR		 3717 goto out;
3718 }
3719 case KVM_GET_TSC_KHZ: {
cc578287 3720 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3721 goto out;
3722 }
1c0b28c2
EM		 3723 case KVM_KVMCLOCK_CTRL: {
3724 r = kvm_set_guest_paused(vcpu);
3725 goto out;
3726 }
5c919412
AS		 3727 case KVM_ENABLE_CAP: {
3728 struct kvm_enable_cap cap;
3729
3730 r = -EFAULT;
3731 if (copy_from_user(&cap, argp, sizeof(cap)))
3732 goto out;
3733 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3734 break;
3735 }
313a3dc7
CO		 3736 default:
3737 r = -EINVAL;
3738 }
3739out:
d1ac91d8 3740 kfree(u.buffer);
313a3dc7
CO		 3741 return r;
3742}
3743
5b1c1493
CO		 3744int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3745{
3746 return VM_FAULT_SIGBUS;
3747}
3748
1fe779f8
CO		 3749static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3750{
3751 int ret;
3752
3753 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3754 return -EINVAL;
1fe779f8
CO		 3755 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3756 return ret;
3757}
3758
b927a3ce
SY		 3759static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3760 u64 ident_addr)
3761{
3762 kvm->arch.ept_identity_map_addr = ident_addr;
3763 return 0;
3764}
3765
1fe779f8
CO		 3766static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3767 u32 kvm_nr_mmu_pages)
3768{
3769 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3770 return -EINVAL;
3771
79fac95e 3772 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3773
3774 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3775 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3776
79fac95e 3777 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3778 return 0;
3779}
3780
3781static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3782{
39de71ec 3783 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3784}
3785
1fe779f8
CO		 3786static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3787{
90bca052 3788 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3789 int r;
3790
3791 r = 0;
3792 switch (chip->chip_id) {
3793 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3794 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3795 sizeof(struct kvm_pic_state));
3796 break;
3797 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3798 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3799 sizeof(struct kvm_pic_state));
3800 break;
3801 case KVM_IRQCHIP_IOAPIC:
33392b49 3802 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3803 break;
3804 default:
3805 r = -EINVAL;
3806 break;
3807 }
3808 return r;
3809}
3810
3811static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3812{
90bca052 3813 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3814 int r;
3815
3816 r = 0;
3817 switch (chip->chip_id) {
3818 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3819 spin_lock(&pic->lock);
3820 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3821 sizeof(struct kvm_pic_state));
90bca052 3822 spin_unlock(&pic->lock);
1fe779f8
CO		 3823 break;
3824 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3825 spin_lock(&pic->lock);
3826 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3827 sizeof(struct kvm_pic_state));
90bca052 3828 spin_unlock(&pic->lock);
1fe779f8
CO		 3829 break;
3830 case KVM_IRQCHIP_IOAPIC:
33392b49 3831 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3832 break;
3833 default:
3834 r = -EINVAL;
3835 break;
3836 }
90bca052 3837 kvm_pic_update_irq(pic);
1fe779f8
CO		 3838 return r;
3839}
3840
e0f63cb9
SY		 3841static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3842{
34f3941c
RK		 3843 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3844
3845 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3846
3847 mutex_lock(&kps->lock);
3848 memcpy(ps, &kps->channels, sizeof(*ps));
3849 mutex_unlock(&kps->lock);
2da29bcc 3850 return 0;
e0f63cb9
SY		 3851}
3852
3853static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3854{
0185604c 3855 int i;
09edea72
RK		 3856 struct kvm_pit *pit = kvm->arch.vpit;
3857
3858 mutex_lock(&pit->pit_state.lock);
34f3941c 3859 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3860 for (i = 0; i < 3; i++)
09edea72
RK		 3861 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3862 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3863 return 0;
e9f42757
BK		 3864}
3865
3866static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3867{
e9f42757
BK		 3868 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3869 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3870 sizeof(ps->channels));
3871 ps->flags = kvm->arch.vpit->pit_state.flags;
3872 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3873 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3874 return 0;
e9f42757
BK		 3875}
3876
3877static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3878{
2da29bcc 3879 int start = 0;
0185604c 3880 int i;
e9f42757 3881 u32 prev_legacy, cur_legacy;
09edea72
RK		 3882 struct kvm_pit *pit = kvm->arch.vpit;
3883
3884 mutex_lock(&pit->pit_state.lock);
3885 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3886 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3887 if (!prev_legacy && cur_legacy)
3888 start = 1;
09edea72
RK		 3889 memcpy(&pit->pit_state.channels, &ps->channels,
3890 sizeof(pit->pit_state.channels));
3891 pit->pit_state.flags = ps->flags;
0185604c 3892 for (i = 0; i < 3; i++)
09edea72 3893 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3894 start && i == 0);
09edea72 3895 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3896 return 0;
e0f63cb9
SY		 3897}
3898
52d939a0
MT		 3899static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3900 struct kvm_reinject_control *control)
3901{
71474e2f
RK		 3902 struct kvm_pit *pit = kvm->arch.vpit;
3903
3904 if (!pit)
52d939a0 3905 return -ENXIO;
b39c90b6 3906
71474e2f
RK		 3907 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3908 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3909 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3910 */
3911 mutex_lock(&pit->pit_state.lock);
3912 kvm_pit_set_reinject(pit, control->pit_reinject);
3913 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3914
52d939a0
MT		 3915 return 0;
3916}
3917
95d4c16c 3918/**
60c34612
TY		 3919 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3920 * @kvm: kvm instance
3921 * @log: slot id and address to which we copy the log
95d4c16c 3922 *
e108ff2f
PB		 3923 * Steps 1-4 below provide general overview of dirty page logging. See
3924 * kvm_get_dirty_log_protect() function description for additional details.
3925 *
3926 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3927 * always flush the TLB (step 4) even if previous step failed and the dirty
3928 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3929 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3930 * writes will be marked dirty for next log read.
95d4c16c 3931 *
60c34612
TY		 3932 * 1. Take a snapshot of the bit and clear it if needed.
3933 * 2. Write protect the corresponding page.
e108ff2f
PB		 3934 * 3. Copy the snapshot to the userspace.
3935 * 4. Flush TLB's if needed.
5bb064dc 3936 */
60c34612 3937int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3938{
60c34612 3939 bool is_dirty = false;
e108ff2f 3940 int r;
5bb064dc 3941
79fac95e 3942 mutex_lock(&kvm->slots_lock);
5bb064dc 3943
88178fd4
KH		 3944 /*
3945 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3946 */
3947 if (kvm_x86_ops->flush_log_dirty)
3948 kvm_x86_ops->flush_log_dirty(kvm);
3949
e108ff2f 3950 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3951
3952 /*
3953 * All the TLBs can be flushed out of mmu lock, see the comments in
3954 * kvm_mmu_slot_remove_write_access().
3955 */
e108ff2f 3956 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3957 if (is_dirty)
3958 kvm_flush_remote_tlbs(kvm);
3959
79fac95e 3960 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3961 return r;
3962}
3963
aa2fbe6d
YZ		 3964int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3965 bool line_status)
23d43cf9
CD		 3966{
3967 if (!irqchip_in_kernel(kvm))
3968 return -ENXIO;
3969
3970 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3971 irq_event->irq, irq_event->level,
3972 line_status);
23d43cf9
CD		 3973 return 0;
3974}
3975
90de4a18
NA		 3976static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3977 struct kvm_enable_cap *cap)
3978{
3979 int r;
3980
3981 if (cap->flags)
3982 return -EINVAL;
3983
3984 switch (cap->cap) {
3985 case KVM_CAP_DISABLE_QUIRKS:
3986 kvm->arch.disabled_quirks = cap->args[0];
3987 r = 0;
3988 break;
49df6397
SR		 3989 case KVM_CAP_SPLIT_IRQCHIP: {
3990 mutex_lock(&kvm->lock);
b053b2ae
SR		 3991 r = -EINVAL;
3992 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3993 goto split_irqchip_unlock;
49df6397
SR		 3994 r = -EEXIST;
3995 if (irqchip_in_kernel(kvm))
3996 goto split_irqchip_unlock;
557abc40 3997 if (kvm->created_vcpus)
49df6397
SR		 3998 goto split_irqchip_unlock;
3999 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4000 if (r)
49df6397
SR		 4001 goto split_irqchip_unlock;
4002 /* Pairs with irqchip_in_kernel. */
4003 smp_wmb();
49776faf 4004 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4005 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4006 r = 0;
4007split_irqchip_unlock:
4008 mutex_unlock(&kvm->lock);
4009 break;
4010 }
37131313
RK		 4011 case KVM_CAP_X2APIC_API:
4012 r = -EINVAL;
4013 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4014 break;
4015
4016 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4017 kvm->arch.x2apic_format = true;
c519265f
RK		 4018 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4019 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4020
4021 r = 0;
4022 break;
90de4a18
NA		 4023 default:
4024 r = -EINVAL;
4025 break;
4026 }
4027 return r;
4028}
4029
1fe779f8
CO		 4030long kvm_arch_vm_ioctl(struct file *filp,
4031 unsigned int ioctl, unsigned long arg)
4032{
4033 struct kvm *kvm = filp->private_data;
4034 void __user *argp = (void __user *)arg;
367e1319 4035 int r = -ENOTTY;
f0d66275
DH		 4036 /*
4037 * This union makes it completely explicit to gcc-3.x
4038 * that these two variables' stack usage should be
4039 * combined, not added together.
4040 */
4041 union {
4042 struct kvm_pit_state ps;
e9f42757 4043 struct kvm_pit_state2 ps2;
c5ff41ce 4044 struct kvm_pit_config pit_config;
f0d66275 4045 } u;
1fe779f8
CO		 4046
4047 switch (ioctl) {
4048 case KVM_SET_TSS_ADDR:
4049 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4050 break;
b927a3ce
SY		 4051 case KVM_SET_IDENTITY_MAP_ADDR: {
4052 u64 ident_addr;
4053
1af1ac91
DH		 4054 mutex_lock(&kvm->lock);
4055 r = -EINVAL;
4056 if (kvm->created_vcpus)
4057 goto set_identity_unlock;
b927a3ce
SY		 4058 r = -EFAULT;
4059 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4060 goto set_identity_unlock;
b927a3ce 4061 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4062set_identity_unlock:
4063 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4064 break;
4065 }
1fe779f8
CO		 4066 case KVM_SET_NR_MMU_PAGES:
4067 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4068 break;
4069 case KVM_GET_NR_MMU_PAGES:
4070 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4071 break;
3ddea128 4072 case KVM_CREATE_IRQCHIP: {
3ddea128 4073 mutex_lock(&kvm->lock);
09941366 4074
3ddea128 4075 r = -EEXIST;
35e6eaa3 4076 if (irqchip_in_kernel(kvm))
3ddea128 4077 goto create_irqchip_unlock;
09941366 4078
3e515705 4079 r = -EINVAL;
557abc40 4080 if (kvm->created_vcpus)
3e515705 4081 goto create_irqchip_unlock;
09941366
RK		 4082
4083 r = kvm_pic_init(kvm);
4084 if (r)
3ddea128 4085 goto create_irqchip_unlock;
09941366
RK		 4086
4087 r = kvm_ioapic_init(kvm);
4088 if (r) {
09941366 4089 kvm_pic_destroy(kvm);
3ddea128 4090 goto create_irqchip_unlock;
09941366
RK		 4091 }
4092
399ec807
AK		 4093 r = kvm_setup_default_irq_routing(kvm);
4094 if (r) {
72bb2fcd 4095 kvm_ioapic_destroy(kvm);
09941366 4096 kvm_pic_destroy(kvm);
71ba994c 4097 goto create_irqchip_unlock;
399ec807 4098 }
49776faf 4099 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4100 smp_wmb();
49776faf 4101 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4102 create_irqchip_unlock:
4103 mutex_unlock(&kvm->lock);
1fe779f8 4104 break;
3ddea128 4105 }
7837699f 4106 case KVM_CREATE_PIT:
c5ff41ce
JK		 4107 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4108 goto create_pit;
4109 case KVM_CREATE_PIT2:
4110 r = -EFAULT;
4111 if (copy_from_user(&u.pit_config, argp,
4112 sizeof(struct kvm_pit_config)))
4113 goto out;
4114 create_pit:
250715a6 4115 mutex_lock(&kvm->lock);
269e05e4
AK		 4116 r = -EEXIST;
4117 if (kvm->arch.vpit)
4118 goto create_pit_unlock;
7837699f 4119 r = -ENOMEM;
c5ff41ce 4120 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4121 if (kvm->arch.vpit)
4122 r = 0;
269e05e4 4123 create_pit_unlock:
250715a6 4124 mutex_unlock(&kvm->lock);
7837699f 4125 break;
1fe779f8
CO		 4126 case KVM_GET_IRQCHIP: {
4127 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4128 struct kvm_irqchip *chip;
1fe779f8 4129
ff5c2c03
SL		 4130 chip = memdup_user(argp, sizeof(*chip));
4131 if (IS_ERR(chip)) {
4132 r = PTR_ERR(chip);
1fe779f8 4133 goto out;
ff5c2c03
SL		 4134 }
4135
1fe779f8 4136 r = -ENXIO;
826da321 4137 if (!irqchip_kernel(kvm))
f0d66275
DH		 4138 goto get_irqchip_out;
4139 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4140 if (r)
f0d66275 4141 goto get_irqchip_out;
1fe779f8 4142 r = -EFAULT;
f0d66275
DH		 4143 if (copy_to_user(argp, chip, sizeof *chip))
4144 goto get_irqchip_out;
1fe779f8 4145 r = 0;
f0d66275
DH		 4146 get_irqchip_out:
4147 kfree(chip);
1fe779f8
CO		 4148 break;
4149 }
4150 case KVM_SET_IRQCHIP: {
4151 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4152 struct kvm_irqchip *chip;
1fe779f8 4153
ff5c2c03
SL		 4154 chip = memdup_user(argp, sizeof(*chip));
4155 if (IS_ERR(chip)) {
4156 r = PTR_ERR(chip);
1fe779f8 4157 goto out;
ff5c2c03
SL		 4158 }
4159
1fe779f8 4160 r = -ENXIO;
826da321 4161 if (!irqchip_kernel(kvm))
f0d66275
DH		 4162 goto set_irqchip_out;
4163 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4164 if (r)
f0d66275 4165 goto set_irqchip_out;
1fe779f8 4166 r = 0;
f0d66275
DH		 4167 set_irqchip_out:
4168 kfree(chip);
1fe779f8
CO		 4169 break;
4170 }
e0f63cb9 4171 case KVM_GET_PIT: {
e0f63cb9 4172 r = -EFAULT;
f0d66275 4173 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4174 goto out;
4175 r = -ENXIO;
4176 if (!kvm->arch.vpit)
4177 goto out;
f0d66275 4178 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4179 if (r)
4180 goto out;
4181 r = -EFAULT;
f0d66275 4182 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4183 goto out;
4184 r = 0;
4185 break;
4186 }
4187 case KVM_SET_PIT: {
e0f63cb9 4188 r = -EFAULT;
f0d66275 4189 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4190 goto out;
4191 r = -ENXIO;
4192 if (!kvm->arch.vpit)
4193 goto out;
f0d66275 4194 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4195 break;
4196 }
e9f42757
BK		 4197 case KVM_GET_PIT2: {
4198 r = -ENXIO;
4199 if (!kvm->arch.vpit)
4200 goto out;
4201 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4202 if (r)
4203 goto out;
4204 r = -EFAULT;
4205 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4206 goto out;
4207 r = 0;
4208 break;
4209 }
4210 case KVM_SET_PIT2: {
4211 r = -EFAULT;
4212 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4213 goto out;
4214 r = -ENXIO;
4215 if (!kvm->arch.vpit)
4216 goto out;
4217 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4218 break;
4219 }
52d939a0
MT		 4220 case KVM_REINJECT_CONTROL: {
4221 struct kvm_reinject_control control;
4222 r = -EFAULT;
4223 if (copy_from_user(&control, argp, sizeof(control)))
4224 goto out;
4225 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4226 break;
4227 }
d71ba788
PB		 4228 case KVM_SET_BOOT_CPU_ID:
4229 r = 0;
4230 mutex_lock(&kvm->lock);
557abc40 4231 if (kvm->created_vcpus)
d71ba788
PB		 4232 r = -EBUSY;
4233 else
4234 kvm->arch.bsp_vcpu_id = arg;
4235 mutex_unlock(&kvm->lock);
4236 break;
ffde22ac
ES		 4237 case KVM_XEN_HVM_CONFIG: {
4238 r = -EFAULT;
4239 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4240 sizeof(struct kvm_xen_hvm_config)))
4241 goto out;
4242 r = -EINVAL;
4243 if (kvm->arch.xen_hvm_config.flags)
4244 goto out;
4245 r = 0;
4246 break;
4247 }
afbcf7ab 4248 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4249 struct kvm_clock_data user_ns;
4250 u64 now_ns;
afbcf7ab
GC		 4251
4252 r = -EFAULT;
4253 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4254 goto out;
4255
4256 r = -EINVAL;
4257 if (user_ns.flags)
4258 goto out;
4259
4260 r = 0;
0bc48bea
RK		 4261 /*
4262 * TODO: userspace has to take care of races with VCPU_RUN, so
4263 * kvm_gen_update_masterclock() can be cut down to locked
4264 * pvclock_update_vm_gtod_copy().
4265 */
4266 kvm_gen_update_masterclock(kvm);
e891a32e 4267 now_ns = get_kvmclock_ns(kvm);
108b249c 4268 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4269 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4270 break;
4271 }
4272 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4273 struct kvm_clock_data user_ns;
4274 u64 now_ns;
4275
e891a32e 4276 now_ns = get_kvmclock_ns(kvm);
108b249c 4277 user_ns.clock = now_ns;
e3fd9a93 4278 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4279 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4280
4281 r = -EFAULT;
4282 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4283 goto out;
4284 r = 0;
4285 break;
4286 }
90de4a18
NA		 4287 case KVM_ENABLE_CAP: {
4288 struct kvm_enable_cap cap;
afbcf7ab 4289
90de4a18
NA		 4290 r = -EFAULT;
4291 if (copy_from_user(&cap, argp, sizeof(cap)))
4292 goto out;
4293 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4294 break;
4295 }
1fe779f8 4296 default:
ad6260da 4297 r = -ENOTTY;
1fe779f8
CO		 4298 }
4299out:
4300 return r;
4301}
4302
a16b043c 4303static void kvm_init_msr_list(void)
043405e1
CO		 4304{
4305 u32 dummy[2];
4306 unsigned i, j;
4307
62ef68bb 4308 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4309 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4310 continue;
93c4adc7
PB		 4311
4312 /*
4313 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4314 * to the guests in some cases.
93c4adc7
PB		 4315 */
4316 switch (msrs_to_save[i]) {
4317 case MSR_IA32_BNDCFGS:
4318 if (!kvm_x86_ops->mpx_supported())
4319 continue;
4320 break;
9dbe6cf9
PB		 4321 case MSR_TSC_AUX:
4322 if (!kvm_x86_ops->rdtscp_supported())
4323 continue;
4324 break;
93c4adc7
PB		 4325 default:
4326 break;
4327 }
4328
043405e1
CO		 4329 if (j < i)
4330 msrs_to_save[j] = msrs_to_save[i];
4331 j++;
4332 }
4333 num_msrs_to_save = j;
62ef68bb
PB		 4334
4335 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4336 switch (emulated_msrs[i]) {
6d396b55
PB		 4337 case MSR_IA32_SMBASE:
4338 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4339 continue;
4340 break;
62ef68bb
PB		 4341 default:
4342 break;
4343 }
4344
4345 if (j < i)
4346 emulated_msrs[j] = emulated_msrs[i];
4347 j++;
4348 }
4349 num_emulated_msrs = j;
043405e1
CO		 4350}
4351
bda9020e
MT		 4352static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4353 const void *v)
bbd9b64e 4354{
70252a10
AK		 4355 int handled = 0;
4356 int n;
4357
4358 do {
4359 n = min(len, 8);
bce87cce 4360 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4361 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4362 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4363 break;
4364 handled += n;
4365 addr += n;
4366 len -= n;
4367 v += n;
4368 } while (len);
bbd9b64e 4369
70252a10 4370 return handled;
bbd9b64e
CO		 4371}
4372
bda9020e 4373static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4374{
70252a10
AK		 4375 int handled = 0;
4376 int n;
4377
4378 do {
4379 n = min(len, 8);
bce87cce 4380 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4381 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4382 addr, n, v))
4383 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4384 break;
4385 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4386 handled += n;
4387 addr += n;
4388 len -= n;
4389 v += n;
4390 } while (len);
bbd9b64e 4391
70252a10 4392 return handled;
bbd9b64e
CO		 4393}
4394
2dafc6c2
GN		 4395static void kvm_set_segment(struct kvm_vcpu *vcpu,
4396 struct kvm_segment *var, int seg)
4397{
4398 kvm_x86_ops->set_segment(vcpu, var, seg);
4399}
4400
4401void kvm_get_segment(struct kvm_vcpu *vcpu,
4402 struct kvm_segment *var, int seg)
4403{
4404 kvm_x86_ops->get_segment(vcpu, var, seg);
4405}
4406
54987b7a
PB		 4407gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4408 struct x86_exception *exception)
02f59dc9
JR		 4409{
4410 gpa_t t_gpa;
02f59dc9
JR		 4411
4412 BUG_ON(!mmu_is_nested(vcpu));
4413
4414 /* NPT walks are always user-walks */
4415 access |= PFERR_USER_MASK;
54987b7a 4416 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4417
4418 return t_gpa;
4419}
4420
ab9ae313
AK		 4421gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4422 struct x86_exception *exception)
1871c602
GN		 4423{
4424 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4425 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4426}
4427
ab9ae313
AK		 4428 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4429 struct x86_exception *exception)
1871c602
GN		 4430{
4431 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4432 access |= PFERR_FETCH_MASK;
ab9ae313 4433 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4434}
4435
ab9ae313
AK		 4436gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4437 struct x86_exception *exception)
1871c602
GN		 4438{
4439 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4440 access |= PFERR_WRITE_MASK;
ab9ae313 4441 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4442}
4443
4444/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4445gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4446 struct x86_exception *exception)
1871c602 4447{
ab9ae313 4448 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4449}
4450
4451static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4452 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4453 struct x86_exception *exception)
bbd9b64e
CO		 4454{
4455 void *data = val;
10589a46 4456 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4457
4458 while (bytes) {
14dfe855 4459 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4460 exception);
bbd9b64e 4461 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4462 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4463 int ret;
4464
bcc55cba 4465 if (gpa == UNMAPPED_GVA)
ab9ae313 4466 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4467 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4468 offset, toread);
10589a46 4469 if (ret < 0) {
c3cd7ffa 4470 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4471 goto out;
4472 }
bbd9b64e 4473
77c2002e
IE		 4474 bytes -= toread;
4475 data += toread;
4476 addr += toread;
bbd9b64e 4477 }
10589a46 4478out:
10589a46 4479 return r;
bbd9b64e 4480}
77c2002e 4481
1871c602 4482/* used for instruction fetching */
0f65dd70
AK		 4483static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4484 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4485 struct x86_exception *exception)
1871c602 4486{
0f65dd70 4487 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4488 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4489 unsigned offset;
4490 int ret;
0f65dd70 4491
44583cba
PB		 4492 /* Inline kvm_read_guest_virt_helper for speed. */
4493 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4494 exception);
4495 if (unlikely(gpa == UNMAPPED_GVA))
4496 return X86EMUL_PROPAGATE_FAULT;
4497
4498 offset = addr & (PAGE_SIZE-1);
4499 if (WARN_ON(offset + bytes > PAGE_SIZE))
4500 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4501 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4502 offset, bytes);
44583cba
PB		 4503 if (unlikely(ret < 0))
4504 return X86EMUL_IO_NEEDED;
4505
4506 return X86EMUL_CONTINUE;
1871c602
GN		 4507}
4508
064aea77 4509int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4510 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4511 struct x86_exception *exception)
1871c602 4512{
0f65dd70 4513 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4514 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4515
1871c602 4516 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4517 exception);
1871c602 4518}
064aea77 4519EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4520
0f65dd70
AK		 4521static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4522 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4523 struct x86_exception *exception)
1871c602 4524{
0f65dd70 4525 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4526 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4527}
4528
7a036a6f
RK		 4529static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4530 unsigned long addr, void *val, unsigned int bytes)
4531{
4532 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4533 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4534
4535 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4536}
4537
6a4d7550 4538int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4539 gva_t addr, void *val,
2dafc6c2 4540 unsigned int bytes,
bcc55cba 4541 struct x86_exception *exception)
77c2002e 4542{
0f65dd70 4543 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4544 void *data = val;
4545 int r = X86EMUL_CONTINUE;
4546
4547 while (bytes) {
14dfe855
JR		 4548 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4549 PFERR_WRITE_MASK,
ab9ae313 4550 exception);
77c2002e
IE		 4551 unsigned offset = addr & (PAGE_SIZE-1);
4552 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4553 int ret;
4554
bcc55cba 4555 if (gpa == UNMAPPED_GVA)
ab9ae313 4556 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4557 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4558 if (ret < 0) {
c3cd7ffa 4559 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4560 goto out;
4561 }
4562
4563 bytes -= towrite;
4564 data += towrite;
4565 addr += towrite;
4566 }
4567out:
4568 return r;
4569}
6a4d7550 4570EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4571
0f89b207
TL		 4572static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4573 gpa_t gpa, bool write)
4574{
4575 /* For APIC access vmexit */
4576 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4577 return 1;
4578
4579 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4580 trace_vcpu_match_mmio(gva, gpa, write, true);
4581 return 1;
4582 }
4583
4584 return 0;
4585}
4586
af7cc7d1
XG		 4587static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4588 gpa_t *gpa, struct x86_exception *exception,
4589 bool write)
4590{
97d64b78
AK		 4591 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4592 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4593
be94f6b7
HH		 4594 /*
4595 * currently PKRU is only applied to ept enabled guest so
4596 * there is no pkey in EPT page table for L1 guest or EPT
4597 * shadow page table for L2 guest.
4598 */
97d64b78 4599 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4600 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4601 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4602 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4603 (gva & (PAGE_SIZE - 1));
4f022648 4604 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4605 return 1;
4606 }
4607
af7cc7d1
XG		 4608 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4609
4610 if (*gpa == UNMAPPED_GVA)
4611 return -1;
4612
0f89b207 4613 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4614}
4615
3200f405 4616int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4617 const void *val, int bytes)
bbd9b64e
CO		 4618{
4619 int ret;
4620
54bf36aa 4621 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4622 if (ret < 0)
bbd9b64e 4623 return 0;
0eb05bf2 4624 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4625 return 1;
4626}
4627
77d197b2
XG		 4628struct read_write_emulator_ops {
4629 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4630 int bytes);
4631 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4632 void *val, int bytes);
4633 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4634 int bytes, void *val);
4635 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4636 void *val, int bytes);
4637 bool write;
4638};
4639
4640static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4641{
4642 if (vcpu->mmio_read_completed) {
77d197b2 4643 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4644 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4645 vcpu->mmio_read_completed = 0;
4646 return 1;
4647 }
4648
4649 return 0;
4650}
4651
4652static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4653 void *val, int bytes)
4654{
54bf36aa 4655 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4656}
4657
4658static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4659 void *val, int bytes)
4660{
4661 return emulator_write_phys(vcpu, gpa, val, bytes);
4662}
4663
4664static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4665{
4666 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4667 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4668}
4669
4670static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4671 void *val, int bytes)
4672{
4673 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4674 return X86EMUL_IO_NEEDED;
4675}
4676
4677static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4678 void *val, int bytes)
4679{
f78146b0
AK		 4680 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4681
87da7e66 4682 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4683 return X86EMUL_CONTINUE;
4684}
4685
0fbe9b0b 4686static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4687 .read_write_prepare = read_prepare,
4688 .read_write_emulate = read_emulate,
4689 .read_write_mmio = vcpu_mmio_read,
4690 .read_write_exit_mmio = read_exit_mmio,
4691};
4692
0fbe9b0b 4693static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4694 .read_write_emulate = write_emulate,
4695 .read_write_mmio = write_mmio,
4696 .read_write_exit_mmio = write_exit_mmio,
4697 .write = true,
4698};
4699
22388a3c
XG		 4700static int emulator_read_write_onepage(unsigned long addr, void *val,
4701 unsigned int bytes,
4702 struct x86_exception *exception,
4703 struct kvm_vcpu *vcpu,
0fbe9b0b 4704 const struct read_write_emulator_ops *ops)
bbd9b64e 4705{
af7cc7d1
XG		 4706 gpa_t gpa;
4707 int handled, ret;
22388a3c 4708 bool write = ops->write;
f78146b0 4709 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4710 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4711
4712 /*
4713 * If the exit was due to a NPF we may already have a GPA.
4714 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4715 * Note, this cannot be used on string operations since string
4716 * operation using rep will only have the initial GPA from the NPF
4717 * occurred.
4718 */
4719 if (vcpu->arch.gpa_available &&
4720 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4721 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4722 gpa = vcpu->arch.gpa_val;
4723 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4724 } else {
4725 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4726 if (ret < 0)
4727 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4728 }
10589a46 4729
618232e2 4730 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4731 return X86EMUL_CONTINUE;
4732
bbd9b64e
CO		 4733 /*
4734 * Is this MMIO handled locally?
4735 */
22388a3c 4736 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4737 if (handled == bytes)
bbd9b64e 4738 return X86EMUL_CONTINUE;
bbd9b64e 4739
70252a10
AK		 4740 gpa += handled;
4741 bytes -= handled;
4742 val += handled;
4743
87da7e66
XG		 4744 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4745 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4746 frag->gpa = gpa;
4747 frag->data = val;
4748 frag->len = bytes;
f78146b0 4749 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4750}
4751
52eb5a6d
XL		 4752static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4753 unsigned long addr,
22388a3c
XG		 4754 void *val, unsigned int bytes,
4755 struct x86_exception *exception,
0fbe9b0b 4756 const struct read_write_emulator_ops *ops)
bbd9b64e 4757{
0f65dd70 4758 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4759 gpa_t gpa;
4760 int rc;
4761
4762 if (ops->read_write_prepare &&
4763 ops->read_write_prepare(vcpu, val, bytes))
4764 return X86EMUL_CONTINUE;
4765
4766 vcpu->mmio_nr_fragments = 0;
0f65dd70 4767
bbd9b64e
CO		 4768 /* Crossing a page boundary? */
4769 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4770 int now;
bbd9b64e
CO		 4771
4772 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4773 rc = emulator_read_write_onepage(addr, val, now, exception,
4774 vcpu, ops);
4775
bbd9b64e
CO		 4776 if (rc != X86EMUL_CONTINUE)
4777 return rc;
4778 addr += now;
bac15531
NA		 4779 if (ctxt->mode != X86EMUL_MODE_PROT64)
4780 addr = (u32)addr;
bbd9b64e
CO		 4781 val += now;
4782 bytes -= now;
4783 }
22388a3c 4784
f78146b0
AK		 4785 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4786 vcpu, ops);
4787 if (rc != X86EMUL_CONTINUE)
4788 return rc;
4789
4790 if (!vcpu->mmio_nr_fragments)
4791 return rc;
4792
4793 gpa = vcpu->mmio_fragments[0].gpa;
4794
4795 vcpu->mmio_needed = 1;
4796 vcpu->mmio_cur_fragment = 0;
4797
87da7e66 4798 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4799 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4800 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4801 vcpu->run->mmio.phys_addr = gpa;
4802
4803 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4804}
4805
4806static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4807 unsigned long addr,
4808 void *val,
4809 unsigned int bytes,
4810 struct x86_exception *exception)
4811{
4812 return emulator_read_write(ctxt, addr, val, bytes,
4813 exception, &read_emultor);
4814}
4815
52eb5a6d 4816static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4817 unsigned long addr,
4818 const void *val,
4819 unsigned int bytes,
4820 struct x86_exception *exception)
4821{
4822 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4823 exception, &write_emultor);
bbd9b64e 4824}
bbd9b64e 4825
daea3e73
AK		 4826#define CMPXCHG_TYPE(t, ptr, old, new) \
4827 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4828
4829#ifdef CONFIG_X86_64
4830# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4831#else
4832# define CMPXCHG64(ptr, old, new) \
9749a6c0 4833 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4834#endif
4835
0f65dd70
AK		 4836static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4837 unsigned long addr,
bbd9b64e
CO		 4838 const void *old,
4839 const void *new,
4840 unsigned int bytes,
0f65dd70 4841 struct x86_exception *exception)
bbd9b64e 4842{
0f65dd70 4843 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4844 gpa_t gpa;
4845 struct page *page;
4846 char *kaddr;
4847 bool exchanged;
2bacc55c 4848
daea3e73
AK		 4849 /* guests cmpxchg8b have to be emulated atomically */
4850 if (bytes > 8 || (bytes & (bytes - 1)))
4851 goto emul_write;
10589a46 4852
daea3e73 4853 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4854
daea3e73
AK		 4855 if (gpa == UNMAPPED_GVA ||
4856 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4857 goto emul_write;
2bacc55c 4858
daea3e73
AK		 4859 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4860 goto emul_write;
72dc67a6 4861
54bf36aa 4862 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4863 if (is_error_page(page))
c19b8bd6 4864 goto emul_write;
72dc67a6 4865
8fd75e12 4866 kaddr = kmap_atomic(page);
daea3e73
AK		 4867 kaddr += offset_in_page(gpa);
4868 switch (bytes) {
4869 case 1:
4870 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4871 break;
4872 case 2:
4873 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4874 break;
4875 case 4:
4876 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4877 break;
4878 case 8:
4879 exchanged = CMPXCHG64(kaddr, old, new);
4880 break;
4881 default:
4882 BUG();
2bacc55c 4883 }
8fd75e12 4884 kunmap_atomic(kaddr);
daea3e73
AK		 4885 kvm_release_page_dirty(page);
4886
4887 if (!exchanged)
4888 return X86EMUL_CMPXCHG_FAILED;
4889
54bf36aa 4890 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4891 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4892
4893 return X86EMUL_CONTINUE;
4a5f48f6 4894
3200f405 4895emul_write:
daea3e73 4896 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4897
0f65dd70 4898 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4899}
4900
cf8f70bf
GN		 4901static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4902{
cbfc6c91 4903 int r = 0, i;
cf8f70bf 4904
cbfc6c91
WL		 4905 for (i = 0; i < vcpu->arch.pio.count; i++) {
4906 if (vcpu->arch.pio.in)
4907 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4908 vcpu->arch.pio.size, pd);
4909 else
4910 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4911 vcpu->arch.pio.port, vcpu->arch.pio.size,
4912 pd);
4913 if (r)
4914 break;
4915 pd += vcpu->arch.pio.size;
4916 }
cf8f70bf
GN		 4917 return r;
4918}
4919
6f6fbe98
XG		 4920static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4921 unsigned short port, void *val,
4922 unsigned int count, bool in)
cf8f70bf 4923{
cf8f70bf 4924 vcpu->arch.pio.port = port;
6f6fbe98 4925 vcpu->arch.pio.in = in;
7972995b 4926 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4927 vcpu->arch.pio.size = size;
4928
4929 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4930 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4931 return 1;
4932 }
4933
4934 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4935 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4936 vcpu->run->io.size = size;
4937 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4938 vcpu->run->io.count = count;
4939 vcpu->run->io.port = port;
4940
4941 return 0;
4942}
4943
6f6fbe98
XG		 4944static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4945 int size, unsigned short port, void *val,
4946 unsigned int count)
cf8f70bf 4947{
ca1d4a9e 4948 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4949 int ret;
ca1d4a9e 4950
6f6fbe98
XG		 4951 if (vcpu->arch.pio.count)
4952 goto data_avail;
cf8f70bf 4953
cbfc6c91
WL		 4954 memset(vcpu->arch.pio_data, 0, size * count);
4955
6f6fbe98
XG		 4956 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4957 if (ret) {
4958data_avail:
4959 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4960 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4961 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4962 return 1;
4963 }
4964
cf8f70bf
GN		 4965 return 0;
4966}
4967
6f6fbe98
XG		 4968static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4969 int size, unsigned short port,
4970 const void *val, unsigned int count)
4971{
4972 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4973
4974 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4975 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4976 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4977}
4978
bbd9b64e
CO		 4979static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4980{
4981 return kvm_x86_ops->get_segment_base(vcpu, seg);
4982}
4983
3cb16fe7 4984static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4985{
3cb16fe7 4986 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4987}
4988
ae6a2375 4989static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4990{
4991 if (!need_emulate_wbinvd(vcpu))
4992 return X86EMUL_CONTINUE;
4993
4994 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4995 int cpu = get_cpu();
4996
4997 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4998 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4999 wbinvd_ipi, NULL, 1);
2eec7343 5000 put_cpu();
f5f48ee1 5001 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5002 } else
5003 wbinvd();
f5f48ee1
SY		 5004 return X86EMUL_CONTINUE;
5005}
5cb56059
JS		 5006
5007int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5008{
6affcbed
KH		 5009 kvm_emulate_wbinvd_noskip(vcpu);
5010 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5011}
f5f48ee1
SY		 5012EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5013
5cb56059
JS		 5014
5015
bcaf5cc5
AK		 5016static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5017{
5cb56059 5018 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5019}
5020
52eb5a6d
XL		 5021static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5022 unsigned long *dest)
bbd9b64e 5023{
16f8a6f9 5024 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5025}
5026
52eb5a6d
XL		 5027static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5028 unsigned long value)
bbd9b64e 5029{
338dbc97 5030
717746e3 5031 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5032}
5033
52a46617 5034static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5035{
52a46617 5036 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5037}
5038
717746e3 5039static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5040{
717746e3 5041 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5042 unsigned long value;
5043
5044 switch (cr) {
5045 case 0:
5046 value = kvm_read_cr0(vcpu);
5047 break;
5048 case 2:
5049 value = vcpu->arch.cr2;
5050 break;
5051 case 3:
9f8fe504 5052 value = kvm_read_cr3(vcpu);
52a46617
GN		 5053 break;
5054 case 4:
5055 value = kvm_read_cr4(vcpu);
5056 break;
5057 case 8:
5058 value = kvm_get_cr8(vcpu);
5059 break;
5060 default:
a737f256 5061 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5062 return 0;
5063 }
5064
5065 return value;
5066}
5067
717746e3 5068static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5069{
717746e3 5070 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5071 int res = 0;
5072
52a46617
GN		 5073 switch (cr) {
5074 case 0:
49a9b07e 5075 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5076 break;
5077 case 2:
5078 vcpu->arch.cr2 = val;
5079 break;
5080 case 3:
2390218b 5081 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5082 break;
5083 case 4:
a83b29c6 5084 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5085 break;
5086 case 8:
eea1cff9 5087 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5088 break;
5089 default:
a737f256 5090 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5091 res = -1;
52a46617 5092 }
0f12244f
GN		 5093
5094 return res;
52a46617
GN		 5095}
5096
717746e3 5097static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5098{
717746e3 5099 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5100}
5101
4bff1e86 5102static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5103{
4bff1e86 5104 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5105}
5106
4bff1e86 5107static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5108{
4bff1e86 5109 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5110}
5111
1ac9d0cf
AK		 5112static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5113{
5114 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5115}
5116
5117static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5118{
5119 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5120}
5121
4bff1e86
AK		 5122static unsigned long emulator_get_cached_segment_base(
5123 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5124{
4bff1e86 5125 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5126}
5127
1aa36616
AK		 5128static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5129 struct desc_struct *desc, u32 *base3,
5130 int seg)
2dafc6c2
GN		 5131{
5132 struct kvm_segment var;
5133
4bff1e86 5134 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5135 *selector = var.selector;
2dafc6c2 5136
378a8b09
GN		 5137 if (var.unusable) {
5138 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5139 if (base3)
5140 *base3 = 0;
2dafc6c2 5141 return false;
378a8b09 5142 }
2dafc6c2
GN		 5143
5144 if (var.g)
5145 var.limit >>= 12;
5146 set_desc_limit(desc, var.limit);
5147 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5148#ifdef CONFIG_X86_64
5149 if (base3)
5150 *base3 = var.base >> 32;
5151#endif
2dafc6c2
GN		 5152 desc->type = var.type;
5153 desc->s = var.s;
5154 desc->dpl = var.dpl;
5155 desc->p = var.present;
5156 desc->avl = var.avl;
5157 desc->l = var.l;
5158 desc->d = var.db;
5159 desc->g = var.g;
5160
5161 return true;
5162}
5163
1aa36616
AK		 5164static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5165 struct desc_struct *desc, u32 base3,
5166 int seg)
2dafc6c2 5167{
4bff1e86 5168 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5169 struct kvm_segment var;
5170
1aa36616 5171 var.selector = selector;
2dafc6c2 5172 var.base = get_desc_base(desc);
5601d05b
GN		 5173#ifdef CONFIG_X86_64
5174 var.base |= ((u64)base3) << 32;
5175#endif
2dafc6c2
GN		 5176 var.limit = get_desc_limit(desc);
5177 if (desc->g)
5178 var.limit = (var.limit << 12) | 0xfff;
5179 var.type = desc->type;
2dafc6c2
GN		 5180 var.dpl = desc->dpl;
5181 var.db = desc->d;
5182 var.s = desc->s;
5183 var.l = desc->l;
5184 var.g = desc->g;
5185 var.avl = desc->avl;
5186 var.present = desc->p;
5187 var.unusable = !var.present;
5188 var.padding = 0;
5189
5190 kvm_set_segment(vcpu, &var, seg);
5191 return;
5192}
5193
717746e3
AK		 5194static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5195 u32 msr_index, u64 *pdata)
5196{
609e36d3
PB		 5197 struct msr_data msr;
5198 int r;
5199
5200 msr.index = msr_index;
5201 msr.host_initiated = false;
5202 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5203 if (r)
5204 return r;
5205
5206 *pdata = msr.data;
5207 return 0;
717746e3
AK		 5208}
5209
5210static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5211 u32 msr_index, u64 data)
5212{
8fe8ab46
WA		 5213 struct msr_data msr;
5214
5215 msr.data = data;
5216 msr.index = msr_index;
5217 msr.host_initiated = false;
5218 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5219}
5220
64d60670
PB		 5221static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5222{
5223 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5224
5225 return vcpu->arch.smbase;
5226}
5227
5228static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5229{
5230 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5231
5232 vcpu->arch.smbase = smbase;
5233}
5234
67f4d428
NA		 5235static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5236 u32 pmc)
5237{
c6702c9d 5238 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5239}
5240
222d21aa
AK		 5241static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5242 u32 pmc, u64 *pdata)
5243{
c6702c9d 5244 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5245}
5246
6c3287f7
AK		 5247static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5248{
5249 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5250}
5251
5037f6f3
AK		 5252static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5253{
5254 preempt_disable();
5197b808 5255 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5256}
5257
5258static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5259{
5260 preempt_enable();
5261}
5262
2953538e 5263static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5264 struct x86_instruction_info *info,
c4f035c6
AK		 5265 enum x86_intercept_stage stage)
5266{
2953538e 5267 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5268}
5269
e911eb3b
YZ		 5270static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5271 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5272{
e911eb3b 5273 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5274}
5275
dd856efa
AK		 5276static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5277{
5278 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5279}
5280
5281static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5282{
5283 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5284}
5285
801806d9
NA		 5286static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5287{
5288 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5289}
5290
6ed071f0
LP		 5291static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5292{
5293 return emul_to_vcpu(ctxt)->arch.hflags;
5294}
5295
5296static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5297{
5298 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5299}
5300
0234bf88
LP		 5301static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5302{
5303 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5304}
5305
0225fb50 5306static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5307 .read_gpr = emulator_read_gpr,
5308 .write_gpr = emulator_write_gpr,
1871c602 5309 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5310 .write_std = kvm_write_guest_virt_system,
7a036a6f 5311 .read_phys = kvm_read_guest_phys_system,
1871c602 5312 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5313 .read_emulated = emulator_read_emulated,
5314 .write_emulated = emulator_write_emulated,
5315 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5316 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5317 .pio_in_emulated = emulator_pio_in_emulated,
5318 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5319 .get_segment = emulator_get_segment,
5320 .set_segment = emulator_set_segment,
5951c442 5321 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5322 .get_gdt = emulator_get_gdt,
160ce1f1 5323 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5324 .set_gdt = emulator_set_gdt,
5325 .set_idt = emulator_set_idt,
52a46617
GN		 5326 .get_cr = emulator_get_cr,
5327 .set_cr = emulator_set_cr,
9c537244 5328 .cpl = emulator_get_cpl,
35aa5375
GN		 5329 .get_dr = emulator_get_dr,
5330 .set_dr = emulator_set_dr,
64d60670
PB		 5331 .get_smbase = emulator_get_smbase,
5332 .set_smbase = emulator_set_smbase,
717746e3
AK		 5333 .set_msr = emulator_set_msr,
5334 .get_msr = emulator_get_msr,
67f4d428 5335 .check_pmc = emulator_check_pmc,
222d21aa 5336 .read_pmc = emulator_read_pmc,
6c3287f7 5337 .halt = emulator_halt,
bcaf5cc5 5338 .wbinvd = emulator_wbinvd,
d6aa1000 5339 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5340 .get_fpu = emulator_get_fpu,
5341 .put_fpu = emulator_put_fpu,
c4f035c6 5342 .intercept = emulator_intercept,
bdb42f5a 5343 .get_cpuid = emulator_get_cpuid,
801806d9 5344 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5345 .get_hflags = emulator_get_hflags,
5346 .set_hflags = emulator_set_hflags,
0234bf88 5347 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5348};
5349
95cb2295
GN		 5350static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5351{
37ccdcbe 5352 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5353 /*
5354 * an sti; sti; sequence only disable interrupts for the first
5355 * instruction. So, if the last instruction, be it emulated or
5356 * not, left the system with the INT_STI flag enabled, it
5357 * means that the last instruction is an sti. We should not
5358 * leave the flag on in this case. The same goes for mov ss
5359 */
37ccdcbe
PB		 5360 if (int_shadow & mask)
5361 mask = 0;
6addfc42 5362 if (unlikely(int_shadow || mask)) {
95cb2295 5363 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5364 if (!mask)
5365 kvm_make_request(KVM_REQ_EVENT, vcpu);
5366 }
95cb2295
GN		 5367}
5368
ef54bcfe 5369static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5370{
5371 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5372 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5373 return kvm_propagate_fault(vcpu, &ctxt->exception);
5374
5375 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5376 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5377 ctxt->exception.error_code);
54b8486f 5378 else
da9cb575 5379 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5380 return false;
54b8486f
GN		 5381}
5382
8ec4722d
MG		 5383static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5384{
adf52235 5385 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5386 int cs_db, cs_l;
5387
8ec4722d
MG		 5388 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5389
adf52235 5390 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5391 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5392
adf52235
TY		 5393 ctxt->eip = kvm_rip_read(vcpu);
5394 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5395 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5396 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5397 cs_db ? X86EMUL_MODE_PROT32 :
5398 X86EMUL_MODE_PROT16;
a584539b 5399 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5400 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5401 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5402
dd856efa 5403 init_decode_cache(ctxt);
7ae441ea 5404 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5405}
5406
71f9833b 5407int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5408{
9d74191a 5409 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5410 int ret;
5411
5412 init_emulate_ctxt(vcpu);
5413
9dac77fa
AK		 5414 ctxt->op_bytes = 2;
5415 ctxt->ad_bytes = 2;
5416 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5417 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5418
5419 if (ret != X86EMUL_CONTINUE)
5420 return EMULATE_FAIL;
5421
9dac77fa 5422 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5423 kvm_rip_write(vcpu, ctxt->eip);
5424 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5425
5426 if (irq == NMI_VECTOR)
7460fb4a 5427 vcpu->arch.nmi_pending = 0;
63995653
MG		 5428 else
5429 vcpu->arch.interrupt.pending = false;
5430
5431 return EMULATE_DONE;
5432}
5433EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5434
6d77dbfc
GN		 5435static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5436{
fc3a9157
JR		 5437 int r = EMULATE_DONE;
5438
6d77dbfc
GN		 5439 ++vcpu->stat.insn_emulation_fail;
5440 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5441 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5442 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5443 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5444 vcpu->run->internal.ndata = 0;
1f4dcb3b 5445 r = EMULATE_USER_EXIT;
fc3a9157 5446 }
6d77dbfc 5447 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5448
5449 return r;
6d77dbfc
GN		 5450}
5451
93c05d3e 5452static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5453 bool write_fault_to_shadow_pgtable,
5454 int emulation_type)
a6f177ef 5455{
95b3cf69 5456 gpa_t gpa = cr2;
ba049e93 5457 kvm_pfn_t pfn;
a6f177ef 5458
991eebf9
GN		 5459 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5460 return false;
5461
95b3cf69
XG		 5462 if (!vcpu->arch.mmu.direct_map) {
5463 /*
5464 * Write permission should be allowed since only
5465 * write access need to be emulated.
5466 */
5467 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5468
95b3cf69
XG		 5469 /*
5470 * If the mapping is invalid in guest, let cpu retry
5471 * it to generate fault.
5472 */
5473 if (gpa == UNMAPPED_GVA)
5474 return true;
5475 }
a6f177ef 5476
8e3d9d06
XG		 5477 /*
5478 * Do not retry the unhandleable instruction if it faults on the
5479 * readonly host memory, otherwise it will goto a infinite loop:
5480 * retry instruction -> write #PF -> emulation fail -> retry
5481 * instruction -> ...
5482 */
5483 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5484
5485 /*
5486 * If the instruction failed on the error pfn, it can not be fixed,
5487 * report the error to userspace.
5488 */
5489 if (is_error_noslot_pfn(pfn))
5490 return false;
5491
5492 kvm_release_pfn_clean(pfn);
5493
5494 /* The instructions are well-emulated on direct mmu. */
5495 if (vcpu->arch.mmu.direct_map) {
5496 unsigned int indirect_shadow_pages;
5497
5498 spin_lock(&vcpu->kvm->mmu_lock);
5499 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5500 spin_unlock(&vcpu->kvm->mmu_lock);
5501
5502 if (indirect_shadow_pages)
5503 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5504
a6f177ef 5505 return true;
8e3d9d06 5506 }
a6f177ef 5507
95b3cf69
XG		 5508 /*
5509 * if emulation was due to access to shadowed page table
5510 * and it failed try to unshadow page and re-enter the
5511 * guest to let CPU execute the instruction.
5512 */
5513 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5514
5515 /*
5516 * If the access faults on its page table, it can not
5517 * be fixed by unprotecting shadow page and it should
5518 * be reported to userspace.
5519 */
5520 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5521}
5522
1cb3f3ae
XG		 5523static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5524 unsigned long cr2, int emulation_type)
5525{
5526 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5527 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5528
5529 last_retry_eip = vcpu->arch.last_retry_eip;
5530 last_retry_addr = vcpu->arch.last_retry_addr;
5531
5532 /*
5533 * If the emulation is caused by #PF and it is non-page_table
5534 * writing instruction, it means the VM-EXIT is caused by shadow
5535 * page protected, we can zap the shadow page and retry this
5536 * instruction directly.
5537 *
5538 * Note: if the guest uses a non-page-table modifying instruction
5539 * on the PDE that points to the instruction, then we will unmap
5540 * the instruction and go to an infinite loop. So, we cache the
5541 * last retried eip and the last fault address, if we meet the eip
5542 * and the address again, we can break out of the potential infinite
5543 * loop.
5544 */
5545 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5546
5547 if (!(emulation_type & EMULTYPE_RETRY))
5548 return false;
5549
5550 if (x86_page_table_writing_insn(ctxt))
5551 return false;
5552
5553 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5554 return false;
5555
5556 vcpu->arch.last_retry_eip = ctxt->eip;
5557 vcpu->arch.last_retry_addr = cr2;
5558
5559 if (!vcpu->arch.mmu.direct_map)
5560 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5561
22368028 5562 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5563
5564 return true;
5565}
5566
716d51ab
GN		 5567static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5568static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5569
64d60670 5570static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5571{
64d60670 5572 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5573 /* This is a good place to trace that we are exiting SMM. */
5574 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5575
c43203ca
PB		 5576 /* Process a latched INIT or SMI, if any. */
5577 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5578 }
699023e2
PB		 5579
5580 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5581}
5582
5583static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5584{
5585 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5586
a584539b 5587 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5588
5589 if (changed & HF_SMM_MASK)
5590 kvm_smm_changed(vcpu);
a584539b
PB		 5591}
5592
4a1e10d5
PB		 5593static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5594 unsigned long *db)
5595{
5596 u32 dr6 = 0;
5597 int i;
5598 u32 enable, rwlen;
5599
5600 enable = dr7;
5601 rwlen = dr7 >> 16;
5602 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5603 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5604 dr6 |= (1 << i);
5605 return dr6;
5606}
5607
c8401dda 5608static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5609{
5610 struct kvm_run *kvm_run = vcpu->run;
5611
c8401dda
PB		 5612 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5613 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5614 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5615 kvm_run->debug.arch.exception = DB_VECTOR;
5616 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5617 *r = EMULATE_USER_EXIT;
5618 } else {
5619 /*
5620 * "Certain debug exceptions may clear bit 0-3. The
5621 * remaining contents of the DR6 register are never
5622 * cleared by the processor".
5623 */
5624 vcpu->arch.dr6 &= ~15;
5625 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5626 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5627 }
5628}
5629
6affcbed
KH		 5630int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5631{
5632 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5633 int r = EMULATE_DONE;
5634
5635 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5636
5637 /*
5638 * rflags is the old, "raw" value of the flags. The new value has
5639 * not been saved yet.
5640 *
5641 * This is correct even for TF set by the guest, because "the
5642 * processor will not generate this exception after the instruction
5643 * that sets the TF flag".
5644 */
5645 if (unlikely(rflags & X86_EFLAGS_TF))
5646 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5647 return r == EMULATE_DONE;
5648}
5649EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5650
4a1e10d5
PB		 5651static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5652{
4a1e10d5
PB		 5653 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5654 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5655 struct kvm_run *kvm_run = vcpu->run;
5656 unsigned long eip = kvm_get_linear_rip(vcpu);
5657 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5658 vcpu->arch.guest_debug_dr7,
5659 vcpu->arch.eff_db);
5660
5661 if (dr6 != 0) {
6f43ed01 5662 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5663 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5664 kvm_run->debug.arch.exception = DB_VECTOR;
5665 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5666 *r = EMULATE_USER_EXIT;
5667 return true;
5668 }
5669 }
5670
4161a569
NA		 5671 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5672 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5673 unsigned long eip = kvm_get_linear_rip(vcpu);
5674 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5675 vcpu->arch.dr7,
5676 vcpu->arch.db);
5677
5678 if (dr6 != 0) {
5679 vcpu->arch.dr6 &= ~15;
6f43ed01 5680 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5681 kvm_queue_exception(vcpu, DB_VECTOR);
5682 *r = EMULATE_DONE;
5683 return true;
5684 }
5685 }
5686
5687 return false;
5688}
5689
51d8b661
AP		 5690int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5691 unsigned long cr2,
dc25e89e
AP		 5692 int emulation_type,
5693 void *insn,
5694 int insn_len)
bbd9b64e 5695{
95cb2295 5696 int r;
9d74191a 5697 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5698 bool writeback = true;
93c05d3e 5699 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5700
93c05d3e
XG		 5701 /*
5702 * Clear write_fault_to_shadow_pgtable here to ensure it is
5703 * never reused.
5704 */
5705 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5706 kvm_clear_exception_queue(vcpu);
8d7d8102 5707
571008da 5708 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5709 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5710
5711 /*
5712 * We will reenter on the same instruction since
5713 * we do not set complete_userspace_io. This does not
5714 * handle watchpoints yet, those would be handled in
5715 * the emulate_ops.
5716 */
5717 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5718 return r;
5719
9d74191a
TY		 5720 ctxt->interruptibility = 0;
5721 ctxt->have_exception = false;
e0ad0b47 5722 ctxt->exception.vector = -1;
9d74191a 5723 ctxt->perm_ok = false;
bbd9b64e 5724
b51e974f 5725 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5726
9d74191a 5727 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5728
e46479f8 5729 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5730 ++vcpu->stat.insn_emulation;
1d2887e2 5731 if (r != EMULATION_OK) {
4005996e
AK		 5732 if (emulation_type & EMULTYPE_TRAP_UD)
5733 return EMULATE_FAIL;
991eebf9
GN		 5734 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5735 emulation_type))
bbd9b64e 5736 return EMULATE_DONE;
6ea6e843
PB		 5737 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5738 return EMULATE_DONE;
6d77dbfc
GN		 5739 if (emulation_type & EMULTYPE_SKIP)
5740 return EMULATE_FAIL;
5741 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5742 }
5743 }
5744
ba8afb6b 5745 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5746 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5747 if (ctxt->eflags & X86_EFLAGS_RF)
5748 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5749 return EMULATE_DONE;
5750 }
5751
1cb3f3ae
XG		 5752 if (retry_instruction(ctxt, cr2, emulation_type))
5753 return EMULATE_DONE;
5754
7ae441ea 5755 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5756 changes registers values during IO operation */
7ae441ea
GN		 5757 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5758 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5759 emulator_invalidate_register_cache(ctxt);
7ae441ea 5760 }
4d2179e1 5761
5cd21917 5762restart:
0f89b207
TL		 5763 /* Save the faulting GPA (cr2) in the address field */
5764 ctxt->exception.address = cr2;
5765
9d74191a 5766 r = x86_emulate_insn(ctxt);
bbd9b64e 5767
775fde86
JR		 5768 if (r == EMULATION_INTERCEPTED)
5769 return EMULATE_DONE;
5770
d2ddd1c4 5771 if (r == EMULATION_FAILED) {
991eebf9
GN		 5772 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5773 emulation_type))
c3cd7ffa
GN		 5774 return EMULATE_DONE;
5775
6d77dbfc 5776 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5777 }
5778
9d74191a 5779 if (ctxt->have_exception) {
d2ddd1c4 5780 r = EMULATE_DONE;
ef54bcfe
PB		 5781 if (inject_emulated_exception(vcpu))
5782 return r;
d2ddd1c4 5783 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5784 if (!vcpu->arch.pio.in) {
5785 /* FIXME: return into emulator if single-stepping. */
3457e419 5786 vcpu->arch.pio.count = 0;
0912c977 5787 } else {
7ae441ea 5788 writeback = false;
716d51ab
GN		 5789 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5790 }
ac0a48c3 5791 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5792 } else if (vcpu->mmio_needed) {
5793 if (!vcpu->mmio_is_write)
5794 writeback = false;
ac0a48c3 5795 r = EMULATE_USER_EXIT;
716d51ab 5796 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5797 } else if (r == EMULATION_RESTART)
5cd21917 5798 goto restart;
d2ddd1c4
GN		 5799 else
5800 r = EMULATE_DONE;
f850e2e6 5801
7ae441ea 5802 if (writeback) {
6addfc42 5803 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5804 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5805 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5806 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5807 if (r == EMULATE_DONE &&
5808 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5809 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5810 if (!ctxt->have_exception ||
5811 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5812 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5813
5814 /*
5815 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5816 * do nothing, and it will be requested again as soon as
5817 * the shadow expires. But we still need to check here,
5818 * because POPF has no interrupt shadow.
5819 */
5820 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5821 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5822 } else
5823 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5824
5825 return r;
de7d789a 5826}
51d8b661 5827EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5828
cf8f70bf 5829int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5830{
cf8f70bf 5831 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5832 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5833 size, port, &val, 1);
cf8f70bf 5834 /* do not return to emulator after return from userspace */
7972995b 5835 vcpu->arch.pio.count = 0;
de7d789a
CO		 5836 return ret;
5837}
cf8f70bf 5838EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5839
8370c3d0
TL		 5840static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5841{
5842 unsigned long val;
5843
5844 /* We should only ever be called with arch.pio.count equal to 1 */
5845 BUG_ON(vcpu->arch.pio.count != 1);
5846
5847 /* For size less than 4 we merge, else we zero extend */
5848 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5849 : 0;
5850
5851 /*
5852 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5853 * the copy and tracing
5854 */
5855 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5856 vcpu->arch.pio.port, &val, 1);
5857 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5858
5859 return 1;
5860}
5861
5862int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5863{
5864 unsigned long val;
5865 int ret;
5866
5867 /* For size less than 4 we merge, else we zero extend */
5868 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5869
5870 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5871 &val, 1);
5872 if (ret) {
5873 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5874 return ret;
5875 }
5876
5877 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5878
5879 return 0;
5880}
5881EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5882
251a5fd6 5883static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5884{
0a3aee0d 5885 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5886 return 0;
8cfdc000
ZA		 5887}
5888
5889static void tsc_khz_changed(void *data)
c8076604 5890{
8cfdc000
ZA		 5891 struct cpufreq_freqs *freq = data;
5892 unsigned long khz = 0;
5893
5894 if (data)
5895 khz = freq->new;
5896 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5897 khz = cpufreq_quick_get(raw_smp_processor_id());
5898 if (!khz)
5899 khz = tsc_khz;
0a3aee0d 5900 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5901}
5902
c8076604
GH		 5903static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5904 void *data)
5905{
5906 struct cpufreq_freqs *freq = data;
5907 struct kvm *kvm;
5908 struct kvm_vcpu *vcpu;
5909 int i, send_ipi = 0;
5910
8cfdc000
ZA		 5911 /*
5912 * We allow guests to temporarily run on slowing clocks,
5913 * provided we notify them after, or to run on accelerating
5914 * clocks, provided we notify them before. Thus time never
5915 * goes backwards.
5916 *
5917 * However, we have a problem. We can't atomically update
5918 * the frequency of a given CPU from this function; it is
5919 * merely a notifier, which can be called from any CPU.
5920 * Changing the TSC frequency at arbitrary points in time
5921 * requires a recomputation of local variables related to
5922 * the TSC for each VCPU. We must flag these local variables
5923 * to be updated and be sure the update takes place with the
5924 * new frequency before any guests proceed.
5925 *
5926 * Unfortunately, the combination of hotplug CPU and frequency
5927 * change creates an intractable locking scenario; the order
5928 * of when these callouts happen is undefined with respect to
5929 * CPU hotplug, and they can race with each other. As such,
5930 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5931 * undefined; you can actually have a CPU frequency change take
5932 * place in between the computation of X and the setting of the
5933 * variable. To protect against this problem, all updates of
5934 * the per_cpu tsc_khz variable are done in an interrupt
5935 * protected IPI, and all callers wishing to update the value
5936 * must wait for a synchronous IPI to complete (which is trivial
5937 * if the caller is on the CPU already). This establishes the
5938 * necessary total order on variable updates.
5939 *
5940 * Note that because a guest time update may take place
5941 * anytime after the setting of the VCPU's request bit, the
5942 * correct TSC value must be set before the request. However,
5943 * to ensure the update actually makes it to any guest which
5944 * starts running in hardware virtualization between the set
5945 * and the acquisition of the spinlock, we must also ping the
5946 * CPU after setting the request bit.
5947 *
5948 */
5949
c8076604
GH		 5950 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5951 return 0;
5952 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5953 return 0;
8cfdc000
ZA		 5954
5955 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5956
2f303b74 5957 spin_lock(&kvm_lock);
c8076604 5958 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5959 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5960 if (vcpu->cpu != freq->cpu)
5961 continue;
c285545f 5962 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5963 if (vcpu->cpu != smp_processor_id())
8cfdc000 5964 send_ipi = 1;
c8076604
GH		 5965 }
5966 }
2f303b74 5967 spin_unlock(&kvm_lock);
c8076604
GH		 5968
5969 if (freq->old < freq->new && send_ipi) {
5970 /*
5971 * We upscale the frequency. Must make the guest
5972 * doesn't see old kvmclock values while running with
5973 * the new frequency, otherwise we risk the guest sees
5974 * time go backwards.
5975 *
5976 * In case we update the frequency for another cpu
5977 * (which might be in guest context) send an interrupt
5978 * to kick the cpu out of guest context. Next time
5979 * guest context is entered kvmclock will be updated,
5980 * so the guest will not see stale values.
5981 */
8cfdc000 5982 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5983 }
5984 return 0;
5985}
5986
5987static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5988 .notifier_call = kvmclock_cpufreq_notifier
5989};
5990
251a5fd6 5991static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5992{
251a5fd6
SAS		 5993 tsc_khz_changed(NULL);
5994 return 0;
8cfdc000
ZA		 5995}
5996
b820cc0c
ZA		 5997static void kvm_timer_init(void)
5998{
c285545f 5999 max_tsc_khz = tsc_khz;
460dd42e 6000
b820cc0c 6001 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6002#ifdef CONFIG_CPU_FREQ
6003 struct cpufreq_policy policy;
758f588d
BP		 6004 int cpu;
6005
c285545f 6006 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6007 cpu = get_cpu();
6008 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6009 if (policy.cpuinfo.max_freq)
6010 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6011 put_cpu();
c285545f 6012#endif
b820cc0c
ZA		 6013 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6014 CPUFREQ_TRANSITION_NOTIFIER);
6015 }
c285545f 6016 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6017
73c1b41e 6018 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6019 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6020}
6021
ff9d07a0
ZY		 6022static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6023
f5132b01 6024int kvm_is_in_guest(void)
ff9d07a0 6025{
086c9855 6026 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6027}
6028
6029static int kvm_is_user_mode(void)
6030{
6031 int user_mode = 3;
dcf46b94 6032
086c9855
AS		 6033 if (__this_cpu_read(current_vcpu))
6034 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6035
ff9d07a0
ZY		 6036 return user_mode != 0;
6037}
6038
6039static unsigned long kvm_get_guest_ip(void)
6040{
6041 unsigned long ip = 0;
dcf46b94 6042
086c9855
AS		 6043 if (__this_cpu_read(current_vcpu))
6044 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6045
ff9d07a0
ZY		 6046 return ip;
6047}
6048
6049static struct perf_guest_info_callbacks kvm_guest_cbs = {
6050 .is_in_guest = kvm_is_in_guest,
6051 .is_user_mode = kvm_is_user_mode,
6052 .get_guest_ip = kvm_get_guest_ip,
6053};
6054
6055void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6056{
086c9855 6057 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6058}
6059EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6060
6061void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6062{
086c9855 6063 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6064}
6065EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6066
ce88decf
XG		 6067static void kvm_set_mmio_spte_mask(void)
6068{
6069 u64 mask;
6070 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6071
6072 /*
6073 * Set the reserved bits and the present bit of an paging-structure
6074 * entry to generate page fault with PFER.RSV = 1.
6075 */
885032b9 6076 /* Mask the reserved physical address bits. */
d1431483 6077 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6078
885032b9 6079 /* Set the present bit. */
ce88decf
XG		 6080 mask |= 1ull;
6081
6082#ifdef CONFIG_X86_64
6083 /*
6084 * If reserved bit is not supported, clear the present bit to disable
6085 * mmio page fault.
6086 */
6087 if (maxphyaddr == 52)
6088 mask &= ~1ull;
6089#endif
6090
dcdca5fe 6091 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6092}
6093
16e8d74d
MT		 6094#ifdef CONFIG_X86_64
6095static void pvclock_gtod_update_fn(struct work_struct *work)
6096{
d828199e
MT		 6097 struct kvm *kvm;
6098
6099 struct kvm_vcpu *vcpu;
6100 int i;
6101
2f303b74 6102 spin_lock(&kvm_lock);
d828199e
MT		 6103 list_for_each_entry(kvm, &vm_list, vm_list)
6104 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6105 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6106 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6107 spin_unlock(&kvm_lock);
16e8d74d
MT		 6108}
6109
6110static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6111
6112/*
6113 * Notification about pvclock gtod data update.
6114 */
6115static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6116 void *priv)
6117{
6118 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6119 struct timekeeper *tk = priv;
6120
6121 update_pvclock_gtod(tk);
6122
6123 /* disable master clock if host does not trust, or does not
6124 * use, TSC clocksource
6125 */
6126 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6127 atomic_read(&kvm_guest_has_master_clock) != 0)
6128 queue_work(system_long_wq, &pvclock_gtod_work);
6129
6130 return 0;
6131}
6132
6133static struct notifier_block pvclock_gtod_notifier = {
6134 .notifier_call = pvclock_gtod_notify,
6135};
6136#endif
6137
f8c16bba 6138int kvm_arch_init(void *opaque)
043405e1 6139{
b820cc0c 6140 int r;
6b61edf7 6141 struct kvm_x86_ops *ops = opaque;
f8c16bba 6142
f8c16bba
ZX		 6143 if (kvm_x86_ops) {
6144 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6145 r = -EEXIST;
6146 goto out;
f8c16bba
ZX		 6147 }
6148
6149 if (!ops->cpu_has_kvm_support()) {
6150 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6151 r = -EOPNOTSUPP;
6152 goto out;
f8c16bba
ZX		 6153 }
6154 if (ops->disabled_by_bios()) {
6155 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6156 r = -EOPNOTSUPP;
6157 goto out;
f8c16bba
ZX		 6158 }
6159
013f6a5d
MT		 6160 r = -ENOMEM;
6161 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6162 if (!shared_msrs) {
6163 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6164 goto out;
6165 }
6166
97db56ce
AK		 6167 r = kvm_mmu_module_init();
6168 if (r)
013f6a5d 6169 goto out_free_percpu;
97db56ce 6170
ce88decf 6171 kvm_set_mmio_spte_mask();
97db56ce 6172
f8c16bba 6173 kvm_x86_ops = ops;
920c8377 6174
7b52345e 6175 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6176 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6177 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6178 kvm_timer_init();
c8076604 6179
ff9d07a0
ZY		 6180 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6181
d366bf7e 6182 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6183 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6184
c5cc421b 6185 kvm_lapic_init();
16e8d74d
MT		 6186#ifdef CONFIG_X86_64
6187 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6188#endif
6189
f8c16bba 6190 return 0;
56c6d28a 6191
013f6a5d
MT		 6192out_free_percpu:
6193 free_percpu(shared_msrs);
56c6d28a 6194out:
56c6d28a 6195 return r;
043405e1 6196}
8776e519 6197
f8c16bba
ZX		 6198void kvm_arch_exit(void)
6199{
cef84c30 6200 kvm_lapic_exit();
ff9d07a0
ZY		 6201 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6202
888d256e
JK		 6203 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6204 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6205 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6206 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6207#ifdef CONFIG_X86_64
6208 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6209#endif
f8c16bba 6210 kvm_x86_ops = NULL;
56c6d28a 6211 kvm_mmu_module_exit();
013f6a5d 6212 free_percpu(shared_msrs);
56c6d28a 6213}
f8c16bba 6214
5cb56059 6215int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6216{
6217 ++vcpu->stat.halt_exits;
35754c98 6218 if (lapic_in_kernel(vcpu)) {
a4535290 6219 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6220 return 1;
6221 } else {
6222 vcpu->run->exit_reason = KVM_EXIT_HLT;
6223 return 0;
6224 }
6225}
5cb56059
JS		 6226EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6227
6228int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6229{
6affcbed
KH		 6230 int ret = kvm_skip_emulated_instruction(vcpu);
6231 /*
6232 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6233 * KVM_EXIT_DEBUG here.
6234 */
6235 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6236}
8776e519
HB		 6237EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6238
8ef81a9a 6239#ifdef CONFIG_X86_64
55dd00a7
MT		 6240static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6241 unsigned long clock_type)
6242{
6243 struct kvm_clock_pairing clock_pairing;
6244 struct timespec ts;
80fbd89c 6245 u64 cycle;
55dd00a7
MT		 6246 int ret;
6247
6248 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6249 return -KVM_EOPNOTSUPP;
6250
6251 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6252 return -KVM_EOPNOTSUPP;
6253
6254 clock_pairing.sec = ts.tv_sec;
6255 clock_pairing.nsec = ts.tv_nsec;
6256 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6257 clock_pairing.flags = 0;
6258
6259 ret = 0;
6260 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6261 sizeof(struct kvm_clock_pairing)))
6262 ret = -KVM_EFAULT;
6263
6264 return ret;
6265}
8ef81a9a 6266#endif
55dd00a7 6267
6aef266c
SV		 6268/*
6269 * kvm_pv_kick_cpu_op: Kick a vcpu.
6270 *
6271 * @apicid - apicid of vcpu to be kicked.
6272 */
6273static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6274{
24d2166b 6275 struct kvm_lapic_irq lapic_irq;
6aef266c 6276
24d2166b
R		 6277 lapic_irq.shorthand = 0;
6278 lapic_irq.dest_mode = 0;
ebd28fcb 6279 lapic_irq.level = 0;
24d2166b 6280 lapic_irq.dest_id = apicid;
93bbf0b8 6281 lapic_irq.msi_redir_hint = false;
6aef266c 6282
24d2166b 6283 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6284 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6285}
6286
d62caabb
AS		 6287void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6288{
6289 vcpu->arch.apicv_active = false;
6290 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6291}
6292
8776e519
HB		 6293int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6294{
6295 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6296 int op_64_bit, r;
8776e519 6297
6affcbed 6298 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6299
55cd8e5a
GN		 6300 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6301 return kvm_hv_hypercall(vcpu);
6302
5fdbf976
MT		 6303 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6304 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6305 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6306 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6307 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6308
229456fc 6309 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6310
a449c7aa
NA		 6311 op_64_bit = is_64_bit_mode(vcpu);
6312 if (!op_64_bit) {
8776e519
HB		 6313 nr &= 0xFFFFFFFF;
6314 a0 &= 0xFFFFFFFF;
6315 a1 &= 0xFFFFFFFF;
6316 a2 &= 0xFFFFFFFF;
6317 a3 &= 0xFFFFFFFF;
6318 }
6319
07708c4a
JK		 6320 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6321 ret = -KVM_EPERM;
6322 goto out;
6323 }
6324
8776e519 6325 switch (nr) {
b93463aa
AK		 6326 case KVM_HC_VAPIC_POLL_IRQ:
6327 ret = 0;
6328 break;
6aef266c
SV		 6329 case KVM_HC_KICK_CPU:
6330 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6331 ret = 0;
6332 break;
8ef81a9a 6333#ifdef CONFIG_X86_64
55dd00a7
MT		 6334 case KVM_HC_CLOCK_PAIRING:
6335 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6336 break;
8ef81a9a 6337#endif
8776e519
HB		 6338 default:
6339 ret = -KVM_ENOSYS;
6340 break;
6341 }
07708c4a 6342out:
a449c7aa
NA		 6343 if (!op_64_bit)
6344 ret = (u32)ret;
5fdbf976 6345 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6346 ++vcpu->stat.hypercalls;
2f333bcb 6347 return r;
8776e519
HB		 6348}
6349EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6350
b6785def 6351static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6352{
d6aa1000 6353 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6354 char instruction[3];
5fdbf976 6355 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6356
8776e519 6357 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6358
ce2e852e
DV		 6359 return emulator_write_emulated(ctxt, rip, instruction, 3,
6360 &ctxt->exception);
8776e519
HB		 6361}
6362
851ba692 6363static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6364{
782d422b
MG		 6365 return vcpu->run->request_interrupt_window &&
6366 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6367}
6368
851ba692 6369static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6370{
851ba692
AK		 6371 struct kvm_run *kvm_run = vcpu->run;
6372
91586a3b 6373 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6374 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6375 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6376 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6377 kvm_run->ready_for_interrupt_injection =
6378 pic_in_kernel(vcpu->kvm) ||
782d422b 6379 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6380}
6381
95ba8273
GN		 6382static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6383{
6384 int max_irr, tpr;
6385
6386 if (!kvm_x86_ops->update_cr8_intercept)
6387 return;
6388
bce87cce 6389 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6390 return;
6391
d62caabb
AS		 6392 if (vcpu->arch.apicv_active)
6393 return;
6394
8db3baa2
GN		 6395 if (!vcpu->arch.apic->vapic_addr)
6396 max_irr = kvm_lapic_find_highest_irr(vcpu);
6397 else
6398 max_irr = -1;
95ba8273
GN		 6399
6400 if (max_irr != -1)
6401 max_irr >>= 4;
6402
6403 tpr = kvm_lapic_get_cr8(vcpu);
6404
6405 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6406}
6407
b6b8a145 6408static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6409{
b6b8a145
JK		 6410 int r;
6411
95ba8273 6412 /* try to reinject previous events if any */
664f8e26
WL		 6413 if (vcpu->arch.exception.injected) {
6414 kvm_x86_ops->queue_exception(vcpu);
6415 return 0;
6416 }
6417
6418 /*
6419 * Exceptions must be injected immediately, or the exception
6420 * frame will have the address of the NMI or interrupt handler.
6421 */
6422 if (!vcpu->arch.exception.pending) {
6423 if (vcpu->arch.nmi_injected) {
6424 kvm_x86_ops->set_nmi(vcpu);
6425 return 0;
6426 }
6427
6428 if (vcpu->arch.interrupt.pending) {
6429 kvm_x86_ops->set_irq(vcpu);
6430 return 0;
6431 }
6432 }
6433
6434 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6435 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6436 if (r != 0)
6437 return r;
6438 }
6439
6440 /* try to inject new event if pending */
b59bb7bd 6441 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6442 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6443 vcpu->arch.exception.has_error_code,
6444 vcpu->arch.exception.error_code);
d6e8c854 6445
664f8e26
WL		 6446 vcpu->arch.exception.pending = false;
6447 vcpu->arch.exception.injected = true;
6448
d6e8c854
NA		 6449 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6450 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6451 X86_EFLAGS_RF);
6452
6bdf0662
NA		 6453 if (vcpu->arch.exception.nr == DB_VECTOR &&
6454 (vcpu->arch.dr7 & DR7_GD)) {
6455 vcpu->arch.dr7 &= ~DR7_GD;
6456 kvm_update_dr7(vcpu);
6457 }
6458
cfcd20e5 6459 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6460 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6461 vcpu->arch.smi_pending = false;
ee2cd4b7 6462 enter_smm(vcpu);
c43203ca 6463 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6464 --vcpu->arch.nmi_pending;
6465 vcpu->arch.nmi_injected = true;
6466 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6467 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6468 /*
6469 * Because interrupts can be injected asynchronously, we are
6470 * calling check_nested_events again here to avoid a race condition.
6471 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6472 * proposal and current concerns. Perhaps we should be setting
6473 * KVM_REQ_EVENT only on certain events and not unconditionally?
6474 */
6475 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6476 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6477 if (r != 0)
6478 return r;
6479 }
95ba8273 6480 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6481 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6482 false);
6483 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6484 }
6485 }
ee2cd4b7 6486
b6b8a145 6487 return 0;
95ba8273
GN		 6488}
6489
7460fb4a
AK		 6490static void process_nmi(struct kvm_vcpu *vcpu)
6491{
6492 unsigned limit = 2;
6493
6494 /*
6495 * x86 is limited to one NMI running, and one NMI pending after it.
6496 * If an NMI is already in progress, limit further NMIs to just one.
6497 * Otherwise, allow two (and we'll inject the first one immediately).
6498 */
6499 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6500 limit = 1;
6501
6502 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6503 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6504 kvm_make_request(KVM_REQ_EVENT, vcpu);
6505}
6506
ee2cd4b7 6507static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6508{
6509 u32 flags = 0;
6510 flags |= seg->g << 23;
6511 flags |= seg->db << 22;
6512 flags |= seg->l << 21;
6513 flags |= seg->avl << 20;
6514 flags |= seg->present << 15;
6515 flags |= seg->dpl << 13;
6516 flags |= seg->s << 12;
6517 flags |= seg->type << 8;
6518 return flags;
6519}
6520
ee2cd4b7 6521static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6522{
6523 struct kvm_segment seg;
6524 int offset;
6525
6526 kvm_get_segment(vcpu, &seg, n);
6527 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6528
6529 if (n < 3)
6530 offset = 0x7f84 + n * 12;
6531 else
6532 offset = 0x7f2c + (n - 3) * 12;
6533
6534 put_smstate(u32, buf, offset + 8, seg.base);
6535 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6536 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6537}
6538
efbb288a 6539#ifdef CONFIG_X86_64
ee2cd4b7 6540static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6541{
6542 struct kvm_segment seg;
6543 int offset;
6544 u16 flags;
6545
6546 kvm_get_segment(vcpu, &seg, n);
6547 offset = 0x7e00 + n * 16;
6548
ee2cd4b7 6549 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6550 put_smstate(u16, buf, offset, seg.selector);
6551 put_smstate(u16, buf, offset + 2, flags);
6552 put_smstate(u32, buf, offset + 4, seg.limit);
6553 put_smstate(u64, buf, offset + 8, seg.base);
6554}
efbb288a 6555#endif
660a5d51 6556
ee2cd4b7 6557static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6558{
6559 struct desc_ptr dt;
6560 struct kvm_segment seg;
6561 unsigned long val;
6562 int i;
6563
6564 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6565 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6566 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6567 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6568
6569 for (i = 0; i < 8; i++)
6570 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6571
6572 kvm_get_dr(vcpu, 6, &val);
6573 put_smstate(u32, buf, 0x7fcc, (u32)val);
6574 kvm_get_dr(vcpu, 7, &val);
6575 put_smstate(u32, buf, 0x7fc8, (u32)val);
6576
6577 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6578 put_smstate(u32, buf, 0x7fc4, seg.selector);
6579 put_smstate(u32, buf, 0x7f64, seg.base);
6580 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6581 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6582
6583 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6584 put_smstate(u32, buf, 0x7fc0, seg.selector);
6585 put_smstate(u32, buf, 0x7f80, seg.base);
6586 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6587 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6588
6589 kvm_x86_ops->get_gdt(vcpu, &dt);
6590 put_smstate(u32, buf, 0x7f74, dt.address);
6591 put_smstate(u32, buf, 0x7f70, dt.size);
6592
6593 kvm_x86_ops->get_idt(vcpu, &dt);
6594 put_smstate(u32, buf, 0x7f58, dt.address);
6595 put_smstate(u32, buf, 0x7f54, dt.size);
6596
6597 for (i = 0; i < 6; i++)
ee2cd4b7 6598 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6599
6600 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6601
6602 /* revision id */
6603 put_smstate(u32, buf, 0x7efc, 0x00020000);
6604 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6605}
6606
ee2cd4b7 6607static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6608{
6609#ifdef CONFIG_X86_64
6610 struct desc_ptr dt;
6611 struct kvm_segment seg;
6612 unsigned long val;
6613 int i;
6614
6615 for (i = 0; i < 16; i++)
6616 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6617
6618 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6619 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6620
6621 kvm_get_dr(vcpu, 6, &val);
6622 put_smstate(u64, buf, 0x7f68, val);
6623 kvm_get_dr(vcpu, 7, &val);
6624 put_smstate(u64, buf, 0x7f60, val);
6625
6626 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6627 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6628 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6629
6630 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6631
6632 /* revision id */
6633 put_smstate(u32, buf, 0x7efc, 0x00020064);
6634
6635 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6636
6637 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6638 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6639 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6640 put_smstate(u32, buf, 0x7e94, seg.limit);
6641 put_smstate(u64, buf, 0x7e98, seg.base);
6642
6643 kvm_x86_ops->get_idt(vcpu, &dt);
6644 put_smstate(u32, buf, 0x7e84, dt.size);
6645 put_smstate(u64, buf, 0x7e88, dt.address);
6646
6647 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6648 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6649 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6650 put_smstate(u32, buf, 0x7e74, seg.limit);
6651 put_smstate(u64, buf, 0x7e78, seg.base);
6652
6653 kvm_x86_ops->get_gdt(vcpu, &dt);
6654 put_smstate(u32, buf, 0x7e64, dt.size);
6655 put_smstate(u64, buf, 0x7e68, dt.address);
6656
6657 for (i = 0; i < 6; i++)
ee2cd4b7 6658 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6659#else
6660 WARN_ON_ONCE(1);
6661#endif
6662}
6663
ee2cd4b7 6664static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6665{
660a5d51 6666 struct kvm_segment cs, ds;
18c3626e 6667 struct desc_ptr dt;
660a5d51
PB		 6668 char buf[512];
6669 u32 cr0;
6670
660a5d51 6671 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6672 memset(buf, 0, 512);
d6321d49 6673 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6674 enter_smm_save_state_64(vcpu, buf);
660a5d51 6675 else
ee2cd4b7 6676 enter_smm_save_state_32(vcpu, buf);
660a5d51 6677
0234bf88
LP		 6678 /*
6679 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6680 * vCPU state (e.g. leave guest mode) after we've saved the state into
6681 * the SMM state-save area.
6682 */
6683 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6684
6685 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6686 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6687
6688 if (kvm_x86_ops->get_nmi_mask(vcpu))
6689 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6690 else
6691 kvm_x86_ops->set_nmi_mask(vcpu, true);
6692
6693 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6694 kvm_rip_write(vcpu, 0x8000);
6695
6696 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6697 kvm_x86_ops->set_cr0(vcpu, cr0);
6698 vcpu->arch.cr0 = cr0;
6699
6700 kvm_x86_ops->set_cr4(vcpu, 0);
6701
18c3626e
PB		 6702 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6703 dt.address = dt.size = 0;
6704 kvm_x86_ops->set_idt(vcpu, &dt);
6705
660a5d51
PB		 6706 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6707
6708 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6709 cs.base = vcpu->arch.smbase;
6710
6711 ds.selector = 0;
6712 ds.base = 0;
6713
6714 cs.limit = ds.limit = 0xffffffff;
6715 cs.type = ds.type = 0x3;
6716 cs.dpl = ds.dpl = 0;
6717 cs.db = ds.db = 0;
6718 cs.s = ds.s = 1;
6719 cs.l = ds.l = 0;
6720 cs.g = ds.g = 1;
6721 cs.avl = ds.avl = 0;
6722 cs.present = ds.present = 1;
6723 cs.unusable = ds.unusable = 0;
6724 cs.padding = ds.padding = 0;
6725
6726 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6727 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6728 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6729 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6730 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6731 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6732
d6321d49 6733 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6734 kvm_x86_ops->set_efer(vcpu, 0);
6735
6736 kvm_update_cpuid(vcpu);
6737 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6738}
6739
ee2cd4b7 6740static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6741{
6742 vcpu->arch.smi_pending = true;
6743 kvm_make_request(KVM_REQ_EVENT, vcpu);
6744}
6745
2860c4b1
PB		 6746void kvm_make_scan_ioapic_request(struct kvm *kvm)
6747{
6748 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6749}
6750
3d81bc7e 6751static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6752{
5c919412
AS		 6753 u64 eoi_exit_bitmap[4];
6754
3d81bc7e
YZ		 6755 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6756 return;
c7c9c56c 6757
6308630b 6758 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6759
b053b2ae 6760 if (irqchip_split(vcpu->kvm))
6308630b 6761 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6762 else {
76dfafd5 6763 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6764 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6765 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6766 }
5c919412
AS		 6767 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6768 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6769 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6770}
6771
a70656b6
RK		 6772static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6773{
6774 ++vcpu->stat.tlb_flush;
6775 kvm_x86_ops->tlb_flush(vcpu);
6776}
6777
4256f43f
TC		 6778void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6779{
c24ae0dc
TC		 6780 struct page *page = NULL;
6781
35754c98 6782 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6783 return;
6784
4256f43f
TC		 6785 if (!kvm_x86_ops->set_apic_access_page_addr)
6786 return;
6787
c24ae0dc 6788 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6789 if (is_error_page(page))
6790 return;
c24ae0dc
TC		 6791 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6792
6793 /*
6794 * Do not pin apic access page in memory, the MMU notifier
6795 * will call us again if it is migrated or swapped out.
6796 */
6797 put_page(page);
4256f43f
TC		 6798}
6799EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6800
9357d939 6801/*
362c698f 6802 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6803 * exiting to the userspace. Otherwise, the value will be returned to the
6804 * userspace.
6805 */
851ba692 6806static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6807{
6808 int r;
62a193ed
MG		 6809 bool req_int_win =
6810 dm_request_for_irq_injection(vcpu) &&
6811 kvm_cpu_accept_dm_intr(vcpu);
6812
730dca42 6813 bool req_immediate_exit = false;
b6c7a5dc 6814
2fa6e1e1 6815 if (kvm_request_pending(vcpu)) {
a8eeb04a 6816 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6817 kvm_mmu_unload(vcpu);
a8eeb04a 6818 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6819 __kvm_migrate_timers(vcpu);
d828199e
MT		 6820 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6821 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6822 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6823 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6824 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6825 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6826 if (unlikely(r))
6827 goto out;
6828 }
a8eeb04a 6829 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6830 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6831 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6832 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6833 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6834 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6835 r = 0;
6836 goto out;
6837 }
a8eeb04a 6838 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6839 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6840 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6841 r = 0;
6842 goto out;
6843 }
af585b92
GN		 6844 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6845 /* Page is swapped out. Do synthetic halt */
6846 vcpu->arch.apf.halted = true;
6847 r = 1;
6848 goto out;
6849 }
c9aaa895
GC		 6850 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6851 record_steal_time(vcpu);
64d60670
PB		 6852 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6853 process_smi(vcpu);
7460fb4a
AK		 6854 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6855 process_nmi(vcpu);
f5132b01 6856 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6857 kvm_pmu_handle_event(vcpu);
f5132b01 6858 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6859 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6860 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6861 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6862 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6863 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6864 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6865 vcpu->run->eoi.vector =
6866 vcpu->arch.pending_ioapic_eoi;
6867 r = 0;
6868 goto out;
6869 }
6870 }
3d81bc7e
YZ		 6871 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6872 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6873 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6874 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6875 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6876 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6877 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6878 r = 0;
6879 goto out;
6880 }
e516cebb
AS		 6881 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6882 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6883 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6884 r = 0;
6885 goto out;
6886 }
db397571
AS		 6887 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6888 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6889 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6890 r = 0;
6891 goto out;
6892 }
f3b138c5
AS		 6893
6894 /*
6895 * KVM_REQ_HV_STIMER has to be processed after
6896 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6897 * depend on the guest clock being up-to-date
6898 */
1f4b34f8
AS		 6899 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6900 kvm_hv_process_stimers(vcpu);
2f52d58c 6901 }
b93463aa 6902
b463a6f7 6903 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6904 ++vcpu->stat.req_event;
66450a21
JK		 6905 kvm_apic_accept_events(vcpu);
6906 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6907 r = 1;
6908 goto out;
6909 }
6910
b6b8a145
JK		 6911 if (inject_pending_event(vcpu, req_int_win) != 0)
6912 req_immediate_exit = true;
321c5658 6913 else {
cc3d967f 6914 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 6915 *
cc3d967f
LP		 6916 * SMIs have three cases:
6917 * 1) They can be nested, and then there is nothing to
6918 * do here because RSM will cause a vmexit anyway.
6919 * 2) There is an ISA-specific reason why SMI cannot be
6920 * injected, and the moment when this changes can be
6921 * intercepted.
6922 * 3) Or the SMI can be pending because
6923 * inject_pending_event has completed the injection
6924 * of an IRQ or NMI from the previous vmexit, and
6925 * then we request an immediate exit to inject the
6926 * SMI.
c43203ca
PB		 6927 */
6928 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 6929 if (!kvm_x86_ops->enable_smi_window(vcpu))
6930 req_immediate_exit = true;
321c5658
YS		 6931 if (vcpu->arch.nmi_pending)
6932 kvm_x86_ops->enable_nmi_window(vcpu);
6933 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6934 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6935 WARN_ON(vcpu->arch.exception.pending);
321c5658 6936 }
b463a6f7
AK		 6937
6938 if (kvm_lapic_enabled(vcpu)) {
6939 update_cr8_intercept(vcpu);
6940 kvm_lapic_sync_to_vapic(vcpu);
6941 }
6942 }
6943
d8368af8
AK		 6944 r = kvm_mmu_reload(vcpu);
6945 if (unlikely(r)) {
d905c069 6946 goto cancel_injection;
d8368af8
AK		 6947 }
6948
b6c7a5dc
HB		 6949 preempt_disable();
6950
6951 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6952 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6953
6954 /*
6955 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6956 * IPI are then delayed after guest entry, which ensures that they
6957 * result in virtual interrupt delivery.
6958 */
6959 local_irq_disable();
6b7e2d09
XG		 6960 vcpu->mode = IN_GUEST_MODE;
6961
01b71917
MT		 6962 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6963
0f127d12 6964 /*
b95234c8 6965 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6966 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6967 *
6968 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6969 * pairs with the memory barrier implicit in pi_test_and_set_on
6970 * (see vmx_deliver_posted_interrupt).
6971 *
6972 * 3) This also orders the write to mode from any reads to the page
6973 * tables done while the VCPU is running. Please see the comment
6974 * in kvm_flush_remote_tlbs.
6b7e2d09 6975 */
01b71917 6976 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6977
b95234c8
PB		 6978 /*
6979 * This handles the case where a posted interrupt was
6980 * notified with kvm_vcpu_kick.
6981 */
6982 if (kvm_lapic_enabled(vcpu)) {
6983 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6984 kvm_x86_ops->sync_pir_to_irr(vcpu);
6985 }
32f88400 6986
2fa6e1e1 6987 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 6988 || need_resched() || signal_pending(current)) {
6b7e2d09 6989 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6990 smp_wmb();
6c142801
AK		 6991 local_irq_enable();
6992 preempt_enable();
01b71917 6993 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6994 r = 1;
d905c069 6995 goto cancel_injection;
6c142801
AK		 6996 }
6997
fc5b7f3b
DM		 6998 kvm_load_guest_xcr0(vcpu);
6999
c43203ca
PB		 7000 if (req_immediate_exit) {
7001 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7002 smp_send_reschedule(vcpu->cpu);
c43203ca 7003 }
d6185f20 7004
8b89fe1f
PB		 7005 trace_kvm_entry(vcpu->vcpu_id);
7006 wait_lapic_expire(vcpu);
6edaa530 7007 guest_enter_irqoff();
b6c7a5dc 7008
42dbaa5a 7009 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7010 set_debugreg(0, 7);
7011 set_debugreg(vcpu->arch.eff_db[0], 0);
7012 set_debugreg(vcpu->arch.eff_db[1], 1);
7013 set_debugreg(vcpu->arch.eff_db[2], 2);
7014 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7015 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7016 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7017 }
b6c7a5dc 7018
851ba692 7019 kvm_x86_ops->run(vcpu);
b6c7a5dc 7020
c77fb5fe
PB		 7021 /*
7022 * Do this here before restoring debug registers on the host. And
7023 * since we do this before handling the vmexit, a DR access vmexit
7024 * can (a) read the correct value of the debug registers, (b) set
7025 * KVM_DEBUGREG_WONT_EXIT again.
7026 */
7027 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7028 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7029 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7030 kvm_update_dr0123(vcpu);
7031 kvm_update_dr6(vcpu);
7032 kvm_update_dr7(vcpu);
7033 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7034 }
7035
24f1e32c
FW		 7036 /*
7037 * If the guest has used debug registers, at least dr7
7038 * will be disabled while returning to the host.
7039 * If we don't have active breakpoints in the host, we don't
7040 * care about the messed up debug address registers. But if
7041 * we have some of them active, restore the old state.
7042 */
59d8eb53 7043 if (hw_breakpoint_active())
24f1e32c 7044 hw_breakpoint_restore();
42dbaa5a 7045
4ba76538 7046 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7047
6b7e2d09 7048 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7049 smp_wmb();
a547c6db 7050
fc5b7f3b
DM		 7051 kvm_put_guest_xcr0(vcpu);
7052
a547c6db 7053 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7054
7055 ++vcpu->stat.exits;
7056
f2485b3e 7057 guest_exit_irqoff();
b6c7a5dc 7058
f2485b3e 7059 local_irq_enable();
b6c7a5dc
HB		 7060 preempt_enable();
7061
f656ce01 7062 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7063
b6c7a5dc
HB		 7064 /*
7065 * Profile KVM exit RIPs:
7066 */
7067 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7068 unsigned long rip = kvm_rip_read(vcpu);
7069 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7070 }
7071
cc578287
ZA		 7072 if (unlikely(vcpu->arch.tsc_always_catchup))
7073 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7074
5cfb1d5a
MT		 7075 if (vcpu->arch.apic_attention)
7076 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7077
618232e2 7078 vcpu->arch.gpa_available = false;
851ba692 7079 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7080 return r;
7081
7082cancel_injection:
7083 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7084 if (unlikely(vcpu->arch.apic_attention))
7085 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7086out:
7087 return r;
7088}
b6c7a5dc 7089
362c698f
PB		 7090static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7091{
bf9f6ac8
FW		 7092 if (!kvm_arch_vcpu_runnable(vcpu) &&
7093 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7094 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7095 kvm_vcpu_block(vcpu);
7096 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7097
7098 if (kvm_x86_ops->post_block)
7099 kvm_x86_ops->post_block(vcpu);
7100
9c8fd1ba
PB		 7101 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7102 return 1;
7103 }
362c698f
PB		 7104
7105 kvm_apic_accept_events(vcpu);
7106 switch(vcpu->arch.mp_state) {
7107 case KVM_MP_STATE_HALTED:
7108 vcpu->arch.pv.pv_unhalted = false;
7109 vcpu->arch.mp_state =
7110 KVM_MP_STATE_RUNNABLE;
7111 case KVM_MP_STATE_RUNNABLE:
7112 vcpu->arch.apf.halted = false;
7113 break;
7114 case KVM_MP_STATE_INIT_RECEIVED:
7115 break;
7116 default:
7117 return -EINTR;
7118 break;
7119 }
7120 return 1;
7121}
09cec754 7122
5d9bc648
PB		 7123static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7124{
0ad3bed6
PB		 7125 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7126 kvm_x86_ops->check_nested_events(vcpu, false);
7127
5d9bc648
PB		 7128 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7129 !vcpu->arch.apf.halted);
7130}
7131
362c698f 7132static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7133{
7134 int r;
f656ce01 7135 struct kvm *kvm = vcpu->kvm;
d7690175 7136
f656ce01 7137 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7138
362c698f 7139 for (;;) {
58f800d5 7140 if (kvm_vcpu_running(vcpu)) {
851ba692 7141 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7142 } else {
362c698f 7143 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7144 }
7145
09cec754
GN		 7146 if (r <= 0)
7147 break;
7148
72875d8a 7149 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7150 if (kvm_cpu_has_pending_timer(vcpu))
7151 kvm_inject_pending_timer_irqs(vcpu);
7152
782d422b
MG		 7153 if (dm_request_for_irq_injection(vcpu) &&
7154 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7155 r = 0;
7156 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7157 ++vcpu->stat.request_irq_exits;
362c698f 7158 break;
09cec754 7159 }
af585b92
GN		 7160
7161 kvm_check_async_pf_completion(vcpu);
7162
09cec754
GN		 7163 if (signal_pending(current)) {
7164 r = -EINTR;
851ba692 7165 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7166 ++vcpu->stat.signal_exits;
362c698f 7167 break;
09cec754
GN		 7168 }
7169 if (need_resched()) {
f656ce01 7170 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7171 cond_resched();
f656ce01 7172 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7173 }
b6c7a5dc
HB		 7174 }
7175
f656ce01 7176 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7177
7178 return r;
7179}
7180
716d51ab
GN		 7181static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7182{
7183 int r;
7184 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7185 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7186 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7187 if (r != EMULATE_DONE)
7188 return 0;
7189 return 1;
7190}
7191
7192static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7193{
7194 BUG_ON(!vcpu->arch.pio.count);
7195
7196 return complete_emulated_io(vcpu);
7197}
7198
f78146b0
AK		 7199/*
7200 * Implements the following, as a state machine:
7201 *
7202 * read:
7203 * for each fragment
87da7e66
XG		 7204 * for each mmio piece in the fragment
7205 * write gpa, len
7206 * exit
7207 * copy data
f78146b0
AK		 7208 * execute insn
7209 *
7210 * write:
7211 * for each fragment
87da7e66
XG		 7212 * for each mmio piece in the fragment
7213 * write gpa, len
7214 * copy data
7215 * exit
f78146b0 7216 */
716d51ab 7217static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7218{
7219 struct kvm_run *run = vcpu->run;
f78146b0 7220 struct kvm_mmio_fragment *frag;
87da7e66 7221 unsigned len;
5287f194 7222
716d51ab 7223 BUG_ON(!vcpu->mmio_needed);
5287f194 7224
716d51ab 7225 /* Complete previous fragment */
87da7e66
XG		 7226 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7227 len = min(8u, frag->len);
716d51ab 7228 if (!vcpu->mmio_is_write)
87da7e66
XG		 7229 memcpy(frag->data, run->mmio.data, len);
7230
7231 if (frag->len <= 8) {
7232 /* Switch to the next fragment. */
7233 frag++;
7234 vcpu->mmio_cur_fragment++;
7235 } else {
7236 /* Go forward to the next mmio piece. */
7237 frag->data += len;
7238 frag->gpa += len;
7239 frag->len -= len;
7240 }
7241
a08d3b3b 7242 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7243 vcpu->mmio_needed = 0;
0912c977
PB		 7244
7245 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7246 if (vcpu->mmio_is_write)
716d51ab
GN		 7247 return 1;
7248 vcpu->mmio_read_completed = 1;
7249 return complete_emulated_io(vcpu);
7250 }
87da7e66 7251
716d51ab
GN		 7252 run->exit_reason = KVM_EXIT_MMIO;
7253 run->mmio.phys_addr = frag->gpa;
7254 if (vcpu->mmio_is_write)
87da7e66
XG		 7255 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7256 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7257 run->mmio.is_write = vcpu->mmio_is_write;
7258 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7259 return 0;
5287f194
AK		 7260}
7261
716d51ab 7262
b6c7a5dc
HB		 7263int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7264{
c5bedc68 7265 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7266 int r;
7267 sigset_t sigsaved;
7268
2ce03d85 7269 fpu__initialize(fpu);
e5c30142 7270
ac9f6dc0
AK		 7271 if (vcpu->sigset_active)
7272 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7273
a4535290 7274 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7275 if (kvm_run->immediate_exit) {
7276 r = -EINTR;
7277 goto out;
7278 }
b6c7a5dc 7279 kvm_vcpu_block(vcpu);
66450a21 7280 kvm_apic_accept_events(vcpu);
72875d8a 7281 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7282 r = -EAGAIN;
a0595000
JS		 7283 if (signal_pending(current)) {
7284 r = -EINTR;
7285 vcpu->run->exit_reason = KVM_EXIT_INTR;
7286 ++vcpu->stat.signal_exits;
7287 }
ac9f6dc0 7288 goto out;
b6c7a5dc
HB		 7289 }
7290
b6c7a5dc 7291 /* re-sync apic's tpr */
35754c98 7292 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7293 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7294 r = -EINVAL;
7295 goto out;
7296 }
7297 }
b6c7a5dc 7298
716d51ab
GN		 7299 if (unlikely(vcpu->arch.complete_userspace_io)) {
7300 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7301 vcpu->arch.complete_userspace_io = NULL;
7302 r = cui(vcpu);
7303 if (r <= 0)
7304 goto out;
7305 } else
7306 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7307
460df4c1
PB		 7308 if (kvm_run->immediate_exit)
7309 r = -EINTR;
7310 else
7311 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7312
7313out:
f1d86e46 7314 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7315 if (vcpu->sigset_active)
7316 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7317
b6c7a5dc
HB		 7318 return r;
7319}
7320
7321int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7322{
7ae441ea
GN		 7323 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7324 /*
7325 * We are here if userspace calls get_regs() in the middle of
7326 * instruction emulation. Registers state needs to be copied
4a969980 7327 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7328 * that usually, but some bad designed PV devices (vmware
7329 * backdoor interface) need this to work
7330 */
dd856efa 7331 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7332 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7333 }
5fdbf976
MT		 7334 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7335 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7336 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7337 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7338 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7339 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7340 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7341 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7342#ifdef CONFIG_X86_64
5fdbf976
MT		 7343 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7344 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7345 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7346 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7347 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7348 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7349 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7350 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7351#endif
7352
5fdbf976 7353 regs->rip = kvm_rip_read(vcpu);
91586a3b 7354 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7355
b6c7a5dc
HB		 7356 return 0;
7357}
7358
7359int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7360{
7ae441ea
GN		 7361 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7362 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7363
5fdbf976
MT		 7364 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7365 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7366 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7367 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7368 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7369 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7370 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7371 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7372#ifdef CONFIG_X86_64
5fdbf976
MT		 7373 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7374 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7375 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7376 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7377 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7378 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7379 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7380 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7381#endif
7382
5fdbf976 7383 kvm_rip_write(vcpu, regs->rip);
91586a3b 7384 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7385
b4f14abd
JK		 7386 vcpu->arch.exception.pending = false;
7387
3842d135
AK		 7388 kvm_make_request(KVM_REQ_EVENT, vcpu);
7389
b6c7a5dc
HB		 7390 return 0;
7391}
7392
b6c7a5dc
HB		 7393void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7394{
7395 struct kvm_segment cs;
7396
3e6e0aab 7397 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7398 *db = cs.db;
7399 *l = cs.l;
7400}
7401EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7402
7403int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7404 struct kvm_sregs *sregs)
7405{
89a27f4d 7406 struct desc_ptr dt;
b6c7a5dc 7407
3e6e0aab
GT		 7408 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7409 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7410 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7411 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7412 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7413 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7414
3e6e0aab
GT		 7415 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7416 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7417
7418 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7419 sregs->idt.limit = dt.size;
7420 sregs->idt.base = dt.address;
b6c7a5dc 7421 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7422 sregs->gdt.limit = dt.size;
7423 sregs->gdt.base = dt.address;
b6c7a5dc 7424
4d4ec087 7425 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7426 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7427 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7428 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7429 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7430 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7431 sregs->apic_base = kvm_get_apic_base(vcpu);
7432
923c61bb 7433 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7434
36752c9b 7435 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7436 set_bit(vcpu->arch.interrupt.nr,
7437 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7438
b6c7a5dc
HB		 7439 return 0;
7440}
7441
62d9f0db
MT		 7442int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7443 struct kvm_mp_state *mp_state)
7444{
66450a21 7445 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7446 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7447 vcpu->arch.pv.pv_unhalted)
7448 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7449 else
7450 mp_state->mp_state = vcpu->arch.mp_state;
7451
62d9f0db
MT		 7452 return 0;
7453}
7454
7455int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7456 struct kvm_mp_state *mp_state)
7457{
bce87cce 7458 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7459 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7460 return -EINVAL;
7461
28bf2888
DH		 7462 /* INITs are latched while in SMM */
7463 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7464 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7465 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7466 return -EINVAL;
7467
66450a21
JK		 7468 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7469 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7470 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7471 } else
7472 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7473 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7474 return 0;
7475}
7476
7f3d35fd
KW		 7477int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7478 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7479{
9d74191a 7480 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7481 int ret;
e01c2426 7482
8ec4722d 7483 init_emulate_ctxt(vcpu);
c697518a 7484
7f3d35fd 7485 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7486 has_error_code, error_code);
c697518a 7487
c697518a 7488 if (ret)
19d04437 7489 return EMULATE_FAIL;
37817f29 7490
9d74191a
TY		 7491 kvm_rip_write(vcpu, ctxt->eip);
7492 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7493 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7494 return EMULATE_DONE;
37817f29
IE		 7495}
7496EXPORT_SYMBOL_GPL(kvm_task_switch);
7497
b6c7a5dc
HB		 7498int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7499 struct kvm_sregs *sregs)
7500{
58cb628d 7501 struct msr_data apic_base_msr;
b6c7a5dc 7502 int mmu_reset_needed = 0;
63f42e02 7503 int pending_vec, max_bits, idx;
89a27f4d 7504 struct desc_ptr dt;
b6c7a5dc 7505
d6321d49
RK		 7506 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7507 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7508 return -EINVAL;
7509
d3802286
JM		 7510 apic_base_msr.data = sregs->apic_base;
7511 apic_base_msr.host_initiated = true;
7512 if (kvm_set_apic_base(vcpu, &apic_base_msr))
6d1068b3
PM		 7513 return -EINVAL;
7514
89a27f4d
GN		 7515 dt.size = sregs->idt.limit;
7516 dt.address = sregs->idt.base;
b6c7a5dc 7517 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7518 dt.size = sregs->gdt.limit;
7519 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7520 kvm_x86_ops->set_gdt(vcpu, &dt);
7521
ad312c7c 7522 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7523 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7524 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7525 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7526
2d3ad1f4 7527 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7528
f6801dff 7529 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7530 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7531
4d4ec087 7532 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7533 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7534 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7535
fc78f519 7536 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7537 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7538 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7539 kvm_update_cpuid(vcpu);
63f42e02
XG		 7540
7541 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7542 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7543 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7544 mmu_reset_needed = 1;
7545 }
63f42e02 7546 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7547
7548 if (mmu_reset_needed)
7549 kvm_mmu_reset_context(vcpu);
7550
a50abc3b 7551 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7552 pending_vec = find_first_bit(
7553 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7554 if (pending_vec < max_bits) {
66fd3f7f 7555 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7556 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7557 }
7558
3e6e0aab
GT		 7559 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7560 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7561 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7562 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7563 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7564 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7565
3e6e0aab
GT		 7566 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7567 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7568
5f0269f5
ME		 7569 update_cr8_intercept(vcpu);
7570
9c3e4aab 7571 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7572 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7573 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7574 !is_protmode(vcpu))
9c3e4aab
MT		 7575 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7576
3842d135
AK		 7577 kvm_make_request(KVM_REQ_EVENT, vcpu);
7578
b6c7a5dc
HB		 7579 return 0;
7580}
7581
d0bfb940
JK		 7582int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7583 struct kvm_guest_debug *dbg)
b6c7a5dc 7584{
355be0b9 7585 unsigned long rflags;
ae675ef0 7586 int i, r;
b6c7a5dc 7587
4f926bf2
JK		 7588 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7589 r = -EBUSY;
7590 if (vcpu->arch.exception.pending)
2122ff5e 7591 goto out;
4f926bf2
JK		 7592 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7593 kvm_queue_exception(vcpu, DB_VECTOR);
7594 else
7595 kvm_queue_exception(vcpu, BP_VECTOR);
7596 }
7597
91586a3b
JK		 7598 /*
7599 * Read rflags as long as potentially injected trace flags are still
7600 * filtered out.
7601 */
7602 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7603
7604 vcpu->guest_debug = dbg->control;
7605 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7606 vcpu->guest_debug = 0;
7607
7608 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7609 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7610 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7611 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7612 } else {
7613 for (i = 0; i < KVM_NR_DB_REGS; i++)
7614 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7615 }
c8639010 7616 kvm_update_dr7(vcpu);
ae675ef0 7617
f92653ee
JK		 7618 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7619 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7620 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7621
91586a3b
JK		 7622 /*
7623 * Trigger an rflags update that will inject or remove the trace
7624 * flags.
7625 */
7626 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7627
a96036b8 7628 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7629
4f926bf2 7630 r = 0;
d0bfb940 7631
2122ff5e 7632out:
b6c7a5dc
HB		 7633
7634 return r;
7635}
7636
8b006791
ZX		 7637/*
7638 * Translate a guest virtual address to a guest physical address.
7639 */
7640int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7641 struct kvm_translation *tr)
7642{
7643 unsigned long vaddr = tr->linear_address;
7644 gpa_t gpa;
f656ce01 7645 int idx;
8b006791 7646
f656ce01 7647 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7648 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7649 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7650 tr->physical_address = gpa;
7651 tr->valid = gpa != UNMAPPED_GVA;
7652 tr->writeable = 1;
7653 tr->usermode = 0;
8b006791
ZX		 7654
7655 return 0;
7656}
7657
d0752060
HB		 7658int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7659{
c47ada30 7660 struct fxregs_state *fxsave =
7366ed77 7661 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7662
d0752060
HB		 7663 memcpy(fpu->fpr, fxsave->st_space, 128);
7664 fpu->fcw = fxsave->cwd;
7665 fpu->fsw = fxsave->swd;
7666 fpu->ftwx = fxsave->twd;
7667 fpu->last_opcode = fxsave->fop;
7668 fpu->last_ip = fxsave->rip;
7669 fpu->last_dp = fxsave->rdp;
7670 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7671
d0752060
HB		 7672 return 0;
7673}
7674
7675int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7676{
c47ada30 7677 struct fxregs_state *fxsave =
7366ed77 7678 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7679
d0752060
HB		 7680 memcpy(fxsave->st_space, fpu->fpr, 128);
7681 fxsave->cwd = fpu->fcw;
7682 fxsave->swd = fpu->fsw;
7683 fxsave->twd = fpu->ftwx;
7684 fxsave->fop = fpu->last_opcode;
7685 fxsave->rip = fpu->last_ip;
7686 fxsave->rdp = fpu->last_dp;
7687 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7688
d0752060
HB		 7689 return 0;
7690}
7691
0ee6a517 7692static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7693{
bf935b0b 7694 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7695 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7696 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7697 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7698
2acf923e
DC		 7699 /*
7700 * Ensure guest xcr0 is valid for loading
7701 */
d91cab78 7702 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7703
ad312c7c 7704 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7705}
d0752060
HB		 7706
7707void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7708{
2608d7a1 7709 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7710 return;
7711
2acf923e
DC		 7712 /*
7713 * Restore all possible states in the guest,
7714 * and assume host would use all available bits.
7715 * Guest xcr0 would be loaded later.
7716 */
d0752060 7717 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7718 __kernel_fpu_begin();
38cfd5e3
PB		 7719 /* PKRU is separately restored in kvm_x86_ops->run. */
7720 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7721 ~XFEATURE_MASK_PKRU);
0c04851c 7722 trace_kvm_fpu(1);
d0752060 7723}
d0752060
HB		 7724
7725void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7726{
3d42de25 7727 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7728 return;
7729
7730 vcpu->guest_fpu_loaded = 0;
4f836347 7731 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7732 __kernel_fpu_end();
f096ed85 7733 ++vcpu->stat.fpu_reload;
0c04851c 7734 trace_kvm_fpu(0);
d0752060 7735}
e9b11c17
ZX		 7736
7737void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7738{
bd768e14
IY		 7739 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7740
12f9a48f 7741 kvmclock_reset(vcpu);
7f1ea208 7742
e9b11c17 7743 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7744 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7745}
7746
7747struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7748 unsigned int id)
7749{
c447e76b
LL		 7750 struct kvm_vcpu *vcpu;
7751
6755bae8
ZA		 7752 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7753 printk_once(KERN_WARNING
7754 "kvm: SMP vm created on host with unstable TSC; "
7755 "guest TSC will not be reliable\n");
c447e76b
LL		 7756
7757 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7758
c447e76b 7759 return vcpu;
26e5215f 7760}
e9b11c17 7761
26e5215f
AK		 7762int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7763{
7764 int r;
e9b11c17 7765
19efffa2 7766 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7767 r = vcpu_load(vcpu);
7768 if (r)
7769 return r;
d28bc9dd 7770 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7771 kvm_mmu_setup(vcpu);
e9b11c17 7772 vcpu_put(vcpu);
26e5215f 7773 return r;
e9b11c17
ZX		 7774}
7775
31928aa5 7776void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7777{
8fe8ab46 7778 struct msr_data msr;
332967a3 7779 struct kvm *kvm = vcpu->kvm;
42897d86 7780
d3457c87
RK		 7781 kvm_hv_vcpu_postcreate(vcpu);
7782
31928aa5
DD		 7783 if (vcpu_load(vcpu))
7784 return;
8fe8ab46
WA		 7785 msr.data = 0x0;
7786 msr.index = MSR_IA32_TSC;
7787 msr.host_initiated = true;
7788 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7789 vcpu_put(vcpu);
7790
630994b3
MT		 7791 if (!kvmclock_periodic_sync)
7792 return;
7793
332967a3
AJ		 7794 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7795 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7796}
7797
d40ccc62 7798void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7799{
9fc77441 7800 int r;
344d9588
GN		 7801 vcpu->arch.apf.msr_val = 0;
7802
9fc77441
MT		 7803 r = vcpu_load(vcpu);
7804 BUG_ON(r);
e9b11c17
ZX		 7805 kvm_mmu_unload(vcpu);
7806 vcpu_put(vcpu);
7807
7808 kvm_x86_ops->vcpu_free(vcpu);
7809}
7810
d28bc9dd 7811void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7812{
e69fab5d
PB		 7813 vcpu->arch.hflags = 0;
7814
c43203ca 7815 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7816 atomic_set(&vcpu->arch.nmi_queued, 0);
7817 vcpu->arch.nmi_pending = 0;
448fa4a9 7818 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7819 kvm_clear_interrupt_queue(vcpu);
7820 kvm_clear_exception_queue(vcpu);
664f8e26 7821 vcpu->arch.exception.pending = false;
448fa4a9 7822
42dbaa5a 7823 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7824 kvm_update_dr0123(vcpu);
6f43ed01 7825 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7826 kvm_update_dr6(vcpu);
42dbaa5a 7827 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7828 kvm_update_dr7(vcpu);
42dbaa5a 7829
1119022c
NA		 7830 vcpu->arch.cr2 = 0;
7831
3842d135 7832 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7833 vcpu->arch.apf.msr_val = 0;
c9aaa895 7834 vcpu->arch.st.msr_val = 0;
3842d135 7835
12f9a48f
GC		 7836 kvmclock_reset(vcpu);
7837
af585b92
GN		 7838 kvm_clear_async_pf_completion_queue(vcpu);
7839 kvm_async_pf_hash_reset(vcpu);
7840 vcpu->arch.apf.halted = false;
3842d135 7841
a554d207
WL		 7842 if (kvm_mpx_supported()) {
7843 void *mpx_state_buffer;
7844
7845 /*
7846 * To avoid have the INIT path from kvm_apic_has_events() that be
7847 * called with loaded FPU and does not let userspace fix the state.
7848 */
7849 kvm_put_guest_fpu(vcpu);
7850 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7851 XFEATURE_MASK_BNDREGS);
7852 if (mpx_state_buffer)
7853 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7854 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7855 XFEATURE_MASK_BNDCSR);
7856 if (mpx_state_buffer)
7857 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
7858 }
7859
64d60670 7860 if (!init_event) {
d28bc9dd 7861 kvm_pmu_reset(vcpu);
64d60670 7862 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7863
7864 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7865 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 7866
7867 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7868 }
f5132b01 7869
66f7b72e
JS		 7870 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7871 vcpu->arch.regs_avail = ~0;
7872 vcpu->arch.regs_dirty = ~0;
7873
a554d207
WL		 7874 vcpu->arch.ia32_xss = 0;
7875
d28bc9dd 7876 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7877}
7878
2b4a273b 7879void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7880{
7881 struct kvm_segment cs;
7882
7883 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7884 cs.selector = vector << 8;
7885 cs.base = vector << 12;
7886 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7887 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7888}
7889
13a34e06 7890int kvm_arch_hardware_enable(void)
e9b11c17 7891{
ca84d1a2
ZA		 7892 struct kvm *kvm;
7893 struct kvm_vcpu *vcpu;
7894 int i;
0dd6a6ed
ZA		 7895 int ret;
7896 u64 local_tsc;
7897 u64 max_tsc = 0;
7898 bool stable, backwards_tsc = false;
18863bdd
AK		 7899
7900 kvm_shared_msr_cpu_online();
13a34e06 7901 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7902 if (ret != 0)
7903 return ret;
7904
4ea1636b 7905 local_tsc = rdtsc();
0dd6a6ed
ZA		 7906 stable = !check_tsc_unstable();
7907 list_for_each_entry(kvm, &vm_list, vm_list) {
7908 kvm_for_each_vcpu(i, vcpu, kvm) {
7909 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7910 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7911 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7912 backwards_tsc = true;
7913 if (vcpu->arch.last_host_tsc > max_tsc)
7914 max_tsc = vcpu->arch.last_host_tsc;
7915 }
7916 }
7917 }
7918
7919 /*
7920 * Sometimes, even reliable TSCs go backwards. This happens on
7921 * platforms that reset TSC during suspend or hibernate actions, but
7922 * maintain synchronization. We must compensate. Fortunately, we can
7923 * detect that condition here, which happens early in CPU bringup,
7924 * before any KVM threads can be running. Unfortunately, we can't
7925 * bring the TSCs fully up to date with real time, as we aren't yet far
7926 * enough into CPU bringup that we know how much real time has actually
108b249c 7927 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7928 * variables that haven't been updated yet.
7929 *
7930 * So we simply find the maximum observed TSC above, then record the
7931 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7932 * the adjustment will be applied. Note that we accumulate
7933 * adjustments, in case multiple suspend cycles happen before some VCPU
7934 * gets a chance to run again. In the event that no KVM threads get a
7935 * chance to run, we will miss the entire elapsed period, as we'll have
7936 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7937 * loose cycle time. This isn't too big a deal, since the loss will be
7938 * uniform across all VCPUs (not to mention the scenario is extremely
7939 * unlikely). It is possible that a second hibernate recovery happens
7940 * much faster than a first, causing the observed TSC here to be
7941 * smaller; this would require additional padding adjustment, which is
7942 * why we set last_host_tsc to the local tsc observed here.
7943 *
7944 * N.B. - this code below runs only on platforms with reliable TSC,
7945 * as that is the only way backwards_tsc is set above. Also note
7946 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7947 * have the same delta_cyc adjustment applied if backwards_tsc
7948 * is detected. Note further, this adjustment is only done once,
7949 * as we reset last_host_tsc on all VCPUs to stop this from being
7950 * called multiple times (one for each physical CPU bringup).
7951 *
4a969980 7952 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7953 * will be compensated by the logic in vcpu_load, which sets the TSC to
7954 * catchup mode. This will catchup all VCPUs to real time, but cannot
7955 * guarantee that they stay in perfect synchronization.
7956 */
7957 if (backwards_tsc) {
7958 u64 delta_cyc = max_tsc - local_tsc;
7959 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7960 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7961 kvm_for_each_vcpu(i, vcpu, kvm) {
7962 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7963 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7964 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7965 }
7966
7967 /*
7968 * We have to disable TSC offset matching.. if you were
7969 * booting a VM while issuing an S4 host suspend....
7970 * you may have some problem. Solving this issue is
7971 * left as an exercise to the reader.
7972 */
7973 kvm->arch.last_tsc_nsec = 0;
7974 kvm->arch.last_tsc_write = 0;
7975 }
7976
7977 }
7978 return 0;
e9b11c17
ZX		 7979}
7980
13a34e06 7981void kvm_arch_hardware_disable(void)
e9b11c17 7982{
13a34e06
RK		 7983 kvm_x86_ops->hardware_disable();
7984 drop_user_return_notifiers();
e9b11c17
ZX		 7985}
7986
7987int kvm_arch_hardware_setup(void)
7988{
9e9c3fe4
NA		 7989 int r;
7990
7991 r = kvm_x86_ops->hardware_setup();
7992 if (r != 0)
7993 return r;
7994
35181e86
HZ		 7995 if (kvm_has_tsc_control) {
7996 /*
7997 * Make sure the user can only configure tsc_khz values that
7998 * fit into a signed integer.
7999 * A min value is not calculated needed because it will always
8000 * be 1 on all machines.
8001 */
8002 u64 max = min(0x7fffffffULL,
8003 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8004 kvm_max_guest_tsc_khz = max;
8005
ad721883 8006 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8007 }
ad721883 8008
9e9c3fe4
NA		 8009 kvm_init_msr_list();
8010 return 0;
e9b11c17
ZX		 8011}
8012
8013void kvm_arch_hardware_unsetup(void)
8014{
8015 kvm_x86_ops->hardware_unsetup();
8016}
8017
8018void kvm_arch_check_processor_compat(void *rtn)
8019{
8020 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8021}
8022
8023bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8024{
8025 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8026}
8027EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8028
8029bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8030{
8031 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8032}
8033
54e9818f 8034struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8035EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8036
e9b11c17
ZX		 8037int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8038{
8039 struct page *page;
e9b11c17
ZX		 8040 int r;
8041
b2a05fef 8042 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8043 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8044 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8045 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8046 else
a4535290 8047 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8048
8049 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8050 if (!page) {
8051 r = -ENOMEM;
8052 goto fail;
8053 }
ad312c7c 8054 vcpu->arch.pio_data = page_address(page);
e9b11c17 8055
cc578287 8056 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8057
e9b11c17
ZX		 8058 r = kvm_mmu_create(vcpu);
8059 if (r < 0)
8060 goto fail_free_pio_data;
8061
26de7988 8062 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8063 r = kvm_create_lapic(vcpu);
8064 if (r < 0)
8065 goto fail_mmu_destroy;
54e9818f
GN		 8066 } else
8067 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8068
890ca9ae
HY		 8069 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8070 GFP_KERNEL);
8071 if (!vcpu->arch.mce_banks) {
8072 r = -ENOMEM;
443c39bc 8073 goto fail_free_lapic;
890ca9ae
HY		 8074 }
8075 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8076
f1797359
WY		 8077 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8078 r = -ENOMEM;
f5f48ee1 8079 goto fail_free_mce_banks;
f1797359 8080 }
f5f48ee1 8081
0ee6a517 8082 fx_init(vcpu);
66f7b72e 8083
4344ee98 8084 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8085
5a4f55cd
EK		 8086 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8087
74545705
RK		 8088 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8089
af585b92 8090 kvm_async_pf_hash_reset(vcpu);
f5132b01 8091 kvm_pmu_init(vcpu);
af585b92 8092
1c1a9ce9 8093 vcpu->arch.pending_external_vector = -1;
de63ad4c 8094 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8095
5c919412
AS		 8096 kvm_hv_vcpu_init(vcpu);
8097
e9b11c17 8098 return 0;
0ee6a517 8099
f5f48ee1
SY		 8100fail_free_mce_banks:
8101 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8102fail_free_lapic:
8103 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8104fail_mmu_destroy:
8105 kvm_mmu_destroy(vcpu);
8106fail_free_pio_data:
ad312c7c 8107 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8108fail:
8109 return r;
8110}
8111
8112void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8113{
f656ce01
MT		 8114 int idx;
8115
1f4b34f8 8116 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8117 kvm_pmu_destroy(vcpu);
36cb93fd 8118 kfree(vcpu->arch.mce_banks);
e9b11c17 8119 kvm_free_lapic(vcpu);
f656ce01 8120 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8121 kvm_mmu_destroy(vcpu);
f656ce01 8122 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8123 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8124 if (!lapic_in_kernel(vcpu))
54e9818f 8125 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8126}
d19a9cd2 8127
e790d9ef
RK		 8128void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8129{
ae97a3b8 8130 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8131}
8132
e08b9637 8133int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8134{
e08b9637
CO		 8135 if (type)
8136 return -EINVAL;
8137
6ef768fa 8138 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8139 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8140 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8141 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8142 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8143
5550af4d
SY		 8144 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8145 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8146 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8147 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8148 &kvm->arch.irq_sources_bitmap);
5550af4d 8149
038f8c11 8150 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8151 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8152 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8153 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8154
108b249c 8155 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8156 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8157
7e44e449 8158 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8159 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8160
0eb05bf2 8161 kvm_page_track_init(kvm);
13d268ca 8162 kvm_mmu_init_vm(kvm);
0eb05bf2 8163
03543133
SS		 8164 if (kvm_x86_ops->vm_init)
8165 return kvm_x86_ops->vm_init(kvm);
8166
d89f5eff 8167 return 0;
d19a9cd2
ZX		 8168}
8169
8170static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8171{
9fc77441
MT		 8172 int r;
8173 r = vcpu_load(vcpu);
8174 BUG_ON(r);
d19a9cd2
ZX		 8175 kvm_mmu_unload(vcpu);
8176 vcpu_put(vcpu);
8177}
8178
8179static void kvm_free_vcpus(struct kvm *kvm)
8180{
8181 unsigned int i;
988a2cae 8182 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8183
8184 /*
8185 * Unpin any mmu pages first.
8186 */
af585b92
GN		 8187 kvm_for_each_vcpu(i, vcpu, kvm) {
8188 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8189 kvm_unload_vcpu_mmu(vcpu);
af585b92 8190 }
988a2cae
GN		 8191 kvm_for_each_vcpu(i, vcpu, kvm)
8192 kvm_arch_vcpu_free(vcpu);
8193
8194 mutex_lock(&kvm->lock);
8195 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8196 kvm->vcpus[i] = NULL;
d19a9cd2 8197
988a2cae
GN		 8198 atomic_set(&kvm->online_vcpus, 0);
8199 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8200}
8201
ad8ba2cd
SY		 8202void kvm_arch_sync_events(struct kvm *kvm)
8203{
332967a3 8204 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8205 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8206 kvm_free_pit(kvm);
ad8ba2cd
SY		 8207}
8208
1d8007bd 8209int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8210{
8211 int i, r;
25188b99 8212 unsigned long hva;
f0d648bd
PB		 8213 struct kvm_memslots *slots = kvm_memslots(kvm);
8214 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8215
8216 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8217 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8218 return -EINVAL;
9da0e4d5 8219
f0d648bd
PB		 8220 slot = id_to_memslot(slots, id);
8221 if (size) {
b21629da 8222 if (slot->npages)
f0d648bd
PB		 8223 return -EEXIST;
8224
8225 /*
8226 * MAP_SHARED to prevent internal slot pages from being moved
8227 * by fork()/COW.
8228 */
8229 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8230 MAP_SHARED | MAP_ANONYMOUS, 0);
8231 if (IS_ERR((void *)hva))
8232 return PTR_ERR((void *)hva);
8233 } else {
8234 if (!slot->npages)
8235 return 0;
8236
8237 hva = 0;
8238 }
8239
8240 old = *slot;
9da0e4d5 8241 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8242 struct kvm_userspace_memory_region m;
9da0e4d5 8243
1d8007bd
PB		 8244 m.slot = id | (i << 16);
8245 m.flags = 0;
8246 m.guest_phys_addr = gpa;
f0d648bd 8247 m.userspace_addr = hva;
1d8007bd 8248 m.memory_size = size;
9da0e4d5
PB		 8249 r = __kvm_set_memory_region(kvm, &m);
8250 if (r < 0)
8251 return r;
8252 }
8253
f0d648bd
PB		 8254 if (!size) {
8255 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8256 WARN_ON(r < 0);
8257 }
8258
9da0e4d5
PB		 8259 return 0;
8260}
8261EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8262
1d8007bd 8263int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8264{
8265 int r;
8266
8267 mutex_lock(&kvm->slots_lock);
1d8007bd 8268 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8269 mutex_unlock(&kvm->slots_lock);
8270
8271 return r;
8272}
8273EXPORT_SYMBOL_GPL(x86_set_memory_region);
8274
d19a9cd2
ZX		 8275void kvm_arch_destroy_vm(struct kvm *kvm)
8276{
27469d29
AH		 8277 if (current->mm == kvm->mm) {
8278 /*
8279 * Free memory regions allocated on behalf of userspace,
8280 * unless the the memory map has changed due to process exit
8281 * or fd copying.
8282 */
1d8007bd
PB		 8283 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8284 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8285 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8286 }
03543133
SS		 8287 if (kvm_x86_ops->vm_destroy)
8288 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8289 kvm_pic_destroy(kvm);
8290 kvm_ioapic_destroy(kvm);
d19a9cd2 8291 kvm_free_vcpus(kvm);
af1bae54 8292 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8293 kvm_mmu_uninit_vm(kvm);
2beb6dad 8294 kvm_page_track_cleanup(kvm);
d19a9cd2 8295}
0de10343 8296
5587027c 8297void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8298 struct kvm_memory_slot *dont)
8299{
8300 int i;
8301
d89cc617
TY		 8302 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8303 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8304 kvfree(free->arch.rmap[i]);
d89cc617 8305 free->arch.rmap[i] = NULL;
77d11309 8306 }
d89cc617
TY		 8307 if (i == 0)
8308 continue;
8309
8310 if (!dont || free->arch.lpage_info[i - 1] !=
8311 dont->arch.lpage_info[i - 1]) {
548ef284 8312 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8313 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8314 }
8315 }
21ebbeda
XG		 8316
8317 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8318}
8319
5587027c
AK		 8320int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8321 unsigned long npages)
db3fe4eb
TY		 8322{
8323 int i;
8324
d89cc617 8325 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8326 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8327 unsigned long ugfn;
8328 int lpages;
d89cc617 8329 int level = i + 1;
db3fe4eb
TY		 8330
8331 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8332 slot->base_gfn, level) + 1;
8333
d89cc617 8334 slot->arch.rmap[i] =
a7c3e901 8335 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8336 if (!slot->arch.rmap[i])
77d11309 8337 goto out_free;
d89cc617
TY		 8338 if (i == 0)
8339 continue;
77d11309 8340
a7c3e901 8341 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8342 if (!linfo)
db3fe4eb
TY		 8343 goto out_free;
8344
92f94f1e
XG		 8345 slot->arch.lpage_info[i - 1] = linfo;
8346
db3fe4eb 8347 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8348 linfo[0].disallow_lpage = 1;
db3fe4eb 8349 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8350 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8351 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8352 /*
8353 * If the gfn and userspace address are not aligned wrt each
8354 * other, or if explicitly asked to, disable large page
8355 * support for this slot
8356 */
8357 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8358 !kvm_largepages_enabled()) {
8359 unsigned long j;
8360
8361 for (j = 0; j < lpages; ++j)
92f94f1e 8362 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8363 }
8364 }
8365
21ebbeda
XG		 8366 if (kvm_page_track_create_memslot(slot, npages))
8367 goto out_free;
8368
db3fe4eb
TY		 8369 return 0;
8370
8371out_free:
d89cc617 8372 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8373 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8374 slot->arch.rmap[i] = NULL;
8375 if (i == 0)
8376 continue;
8377
548ef284 8378 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8379 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8380 }
8381 return -ENOMEM;
8382}
8383
15f46015 8384void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8385{
e6dff7d1
TY		 8386 /*
8387 * memslots->generation has been incremented.
8388 * mmio generation may have reached its maximum value.
8389 */
54bf36aa 8390 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8391}
8392
f7784b8e
MT		 8393int kvm_arch_prepare_memory_region(struct kvm *kvm,
8394 struct kvm_memory_slot *memslot,
09170a49 8395 const struct kvm_userspace_memory_region *mem,
7b6195a9 8396 enum kvm_mr_change change)
0de10343 8397{
f7784b8e
MT		 8398 return 0;
8399}
8400
88178fd4
KH		 8401static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8402 struct kvm_memory_slot *new)
8403{
8404 /* Still write protect RO slot */
8405 if (new->flags & KVM_MEM_READONLY) {
8406 kvm_mmu_slot_remove_write_access(kvm, new);
8407 return;
8408 }
8409
8410 /*
8411 * Call kvm_x86_ops dirty logging hooks when they are valid.
8412 *
8413 * kvm_x86_ops->slot_disable_log_dirty is called when:
8414 *
8415 * - KVM_MR_CREATE with dirty logging is disabled
8416 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8417 *
8418 * The reason is, in case of PML, we need to set D-bit for any slots
8419 * with dirty logging disabled in order to eliminate unnecessary GPA
8420 * logging in PML buffer (and potential PML buffer full VMEXT). This
8421 * guarantees leaving PML enabled during guest's lifetime won't have
8422 * any additonal overhead from PML when guest is running with dirty
8423 * logging disabled for memory slots.
8424 *
8425 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8426 * to dirty logging mode.
8427 *
8428 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8429 *
8430 * In case of write protect:
8431 *
8432 * Write protect all pages for dirty logging.
8433 *
8434 * All the sptes including the large sptes which point to this
8435 * slot are set to readonly. We can not create any new large
8436 * spte on this slot until the end of the logging.
8437 *
8438 * See the comments in fast_page_fault().
8439 */
8440 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8441 if (kvm_x86_ops->slot_enable_log_dirty)
8442 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8443 else
8444 kvm_mmu_slot_remove_write_access(kvm, new);
8445 } else {
8446 if (kvm_x86_ops->slot_disable_log_dirty)
8447 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8448 }
8449}
8450
f7784b8e 8451void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8452 const struct kvm_userspace_memory_region *mem,
8482644a 8453 const struct kvm_memory_slot *old,
f36f3f28 8454 const struct kvm_memory_slot *new,
8482644a 8455 enum kvm_mr_change change)
f7784b8e 8456{
8482644a 8457 int nr_mmu_pages = 0;
f7784b8e 8458
48c0e4e9
XG		 8459 if (!kvm->arch.n_requested_mmu_pages)
8460 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8461
48c0e4e9 8462 if (nr_mmu_pages)
0de10343 8463 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8464
3ea3b7fa
WL		 8465 /*
8466 * Dirty logging tracks sptes in 4k granularity, meaning that large
8467 * sptes have to be split. If live migration is successful, the guest
8468 * in the source machine will be destroyed and large sptes will be
8469 * created in the destination. However, if the guest continues to run
8470 * in the source machine (for example if live migration fails), small
8471 * sptes will remain around and cause bad performance.
8472 *
8473 * Scan sptes if dirty logging has been stopped, dropping those
8474 * which can be collapsed into a single large-page spte. Later
8475 * page faults will create the large-page sptes.
8476 */
8477 if ((change != KVM_MR_DELETE) &&
8478 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8479 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8480 kvm_mmu_zap_collapsible_sptes(kvm, new);
8481
c972f3b1 8482 /*
88178fd4 8483 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8484 *
88178fd4
KH		 8485 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8486 * been zapped so no dirty logging staff is needed for old slot. For
8487 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8488 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8489 *
8490 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8491 */
88178fd4 8492 if (change != KVM_MR_DELETE)
f36f3f28 8493 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8494}
1d737c8a 8495
2df72e9b 8496void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8497{
6ca18b69 8498 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8499}
8500
2df72e9b
MT		 8501void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8502 struct kvm_memory_slot *slot)
8503{
ae7cd873 8504 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8505}
8506
5d9bc648
PB		 8507static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8508{
8509 if (!list_empty_careful(&vcpu->async_pf.done))
8510 return true;
8511
8512 if (kvm_apic_has_events(vcpu))
8513 return true;
8514
8515 if (vcpu->arch.pv.pv_unhalted)
8516 return true;
8517
a5f01f8e
WL		 8518 if (vcpu->arch.exception.pending)
8519 return true;
8520
47a66eed
Z		 8521 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8522 (vcpu->arch.nmi_pending &&
8523 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8524 return true;
8525
47a66eed
Z		 8526 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8527 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8528 return true;
8529
5d9bc648
PB		 8530 if (kvm_arch_interrupt_allowed(vcpu) &&
8531 kvm_cpu_has_interrupt(vcpu))
8532 return true;
8533
1f4b34f8
AS		 8534 if (kvm_hv_has_stimer_pending(vcpu))
8535 return true;
8536
5d9bc648
PB		 8537 return false;
8538}
8539
1d737c8a
ZX		 8540int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8541{
5d9bc648 8542 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8543}
5736199a 8544
199b5763
LM		 8545bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8546{
de63ad4c 8547 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8548}
8549
b6d33834 8550int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8551{
b6d33834 8552 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8553}
78646121
GN		 8554
8555int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8556{
8557 return kvm_x86_ops->interrupt_allowed(vcpu);
8558}
229456fc 8559
82b32774 8560unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8561{
82b32774
NA		 8562 if (is_64_bit_mode(vcpu))
8563 return kvm_rip_read(vcpu);
8564 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8565 kvm_rip_read(vcpu));
8566}
8567EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8568
82b32774
NA		 8569bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8570{
8571 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8572}
8573EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8574
94fe45da
JK		 8575unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8576{
8577 unsigned long rflags;
8578
8579 rflags = kvm_x86_ops->get_rflags(vcpu);
8580 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8581 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8582 return rflags;
8583}
8584EXPORT_SYMBOL_GPL(kvm_get_rflags);
8585
6addfc42 8586static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8587{
8588 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8589 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8590 rflags |= X86_EFLAGS_TF;
94fe45da 8591 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8592}
8593
8594void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8595{
8596 __kvm_set_rflags(vcpu, rflags);
3842d135 8597 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8598}
8599EXPORT_SYMBOL_GPL(kvm_set_rflags);
8600
56028d08
GN		 8601void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8602{
8603 int r;
8604
fb67e14f 8605 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8606 work->wakeup_all)
56028d08
GN		 8607 return;
8608
8609 r = kvm_mmu_reload(vcpu);
8610 if (unlikely(r))
8611 return;
8612
fb67e14f
XG		 8613 if (!vcpu->arch.mmu.direct_map &&
8614 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8615 return;
8616
56028d08
GN		 8617 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8618}
8619
af585b92
GN		 8620static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8621{
8622 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8623}
8624
8625static inline u32 kvm_async_pf_next_probe(u32 key)
8626{
8627 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8628}
8629
8630static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8631{
8632 u32 key = kvm_async_pf_hash_fn(gfn);
8633
8634 while (vcpu->arch.apf.gfns[key] != ~0)
8635 key = kvm_async_pf_next_probe(key);
8636
8637 vcpu->arch.apf.gfns[key] = gfn;
8638}
8639
8640static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8641{
8642 int i;
8643 u32 key = kvm_async_pf_hash_fn(gfn);
8644
8645 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8646 (vcpu->arch.apf.gfns[key] != gfn &&
8647 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8648 key = kvm_async_pf_next_probe(key);
8649
8650 return key;
8651}
8652
8653bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8654{
8655 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8656}
8657
8658static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8659{
8660 u32 i, j, k;
8661
8662 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8663 while (true) {
8664 vcpu->arch.apf.gfns[i] = ~0;
8665 do {
8666 j = kvm_async_pf_next_probe(j);
8667 if (vcpu->arch.apf.gfns[j] == ~0)
8668 return;
8669 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8670 /*
8671 * k lies cyclically in ]i,j]
8672 * | i.k.j |
8673 * |....j i.k.| or |.k..j i...|
8674 */
8675 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8676 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8677 i = j;
8678 }
8679}
8680
7c90705b
GN		 8681static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8682{
4e335d9e
PB		 8683
8684 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8685 sizeof(val));
7c90705b
GN		 8686}
8687
9a6e7c39
WL		 8688static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8689{
8690
8691 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8692 sizeof(u32));
8693}
8694
af585b92
GN		 8695void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8696 struct kvm_async_pf *work)
8697{
6389ee94
AK		 8698 struct x86_exception fault;
8699
7c90705b 8700 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8701 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8702
8703 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8704 (vcpu->arch.apf.send_user_only &&
8705 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8706 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8707 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8708 fault.vector = PF_VECTOR;
8709 fault.error_code_valid = true;
8710 fault.error_code = 0;
8711 fault.nested_page_fault = false;
8712 fault.address = work->arch.token;
adfe20fb 8713 fault.async_page_fault = true;
6389ee94 8714 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8715 }
af585b92
GN		 8716}
8717
8718void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8719 struct kvm_async_pf *work)
8720{
6389ee94 8721 struct x86_exception fault;
9a6e7c39 8722 u32 val;
6389ee94 8723
f2e10669 8724 if (work->wakeup_all)
7c90705b
GN		 8725 work->arch.token = ~0; /* broadcast wakeup */
8726 else
8727 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8728 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8729
9a6e7c39
WL		 8730 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8731 !apf_get_user(vcpu, &val)) {
8732 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8733 vcpu->arch.exception.pending &&
8734 vcpu->arch.exception.nr == PF_VECTOR &&
8735 !apf_put_user(vcpu, 0)) {
8736 vcpu->arch.exception.injected = false;
8737 vcpu->arch.exception.pending = false;
8738 vcpu->arch.exception.nr = 0;
8739 vcpu->arch.exception.has_error_code = false;
8740 vcpu->arch.exception.error_code = 0;
8741 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8742 fault.vector = PF_VECTOR;
8743 fault.error_code_valid = true;
8744 fault.error_code = 0;
8745 fault.nested_page_fault = false;
8746 fault.address = work->arch.token;
8747 fault.async_page_fault = true;
8748 kvm_inject_page_fault(vcpu, &fault);
8749 }
7c90705b 8750 }
e6d53e3b 8751 vcpu->arch.apf.halted = false;
a4fa1635 8752 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8753}
8754
8755bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8756{
8757 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8758 return true;
8759 else
9bc1f09f 8760 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8761}
8762
5544eb9b
PB		 8763void kvm_arch_start_assignment(struct kvm *kvm)
8764{
8765 atomic_inc(&kvm->arch.assigned_device_count);
8766}
8767EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8768
8769void kvm_arch_end_assignment(struct kvm *kvm)
8770{
8771 atomic_dec(&kvm->arch.assigned_device_count);
8772}
8773EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8774
8775bool kvm_arch_has_assigned_device(struct kvm *kvm)
8776{
8777 return atomic_read(&kvm->arch.assigned_device_count);
8778}
8779EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8780
e0f0bbc5
AW		 8781void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8782{
8783 atomic_inc(&kvm->arch.noncoherent_dma_count);
8784}
8785EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8786
8787void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8788{
8789 atomic_dec(&kvm->arch.noncoherent_dma_count);
8790}
8791EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8792
8793bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8794{
8795 return atomic_read(&kvm->arch.noncoherent_dma_count);
8796}
8797EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8798
14717e20
AW		 8799bool kvm_arch_has_irq_bypass(void)
8800{
8801 return kvm_x86_ops->update_pi_irte != NULL;
8802}
8803
87276880
FW		 8804int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8805 struct irq_bypass_producer *prod)
8806{
8807 struct kvm_kernel_irqfd *irqfd =
8808 container_of(cons, struct kvm_kernel_irqfd, consumer);
8809
14717e20 8810 irqfd->producer = prod;
87276880 8811
14717e20
AW		 8812 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8813 prod->irq, irqfd->gsi, 1);
87276880
FW		 8814}
8815
8816void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8817 struct irq_bypass_producer *prod)
8818{
8819 int ret;
8820 struct kvm_kernel_irqfd *irqfd =
8821 container_of(cons, struct kvm_kernel_irqfd, consumer);
8822
87276880
FW		 8823 WARN_ON(irqfd->producer != prod);
8824 irqfd->producer = NULL;
8825
8826 /*
8827 * When producer of consumer is unregistered, we change back to
8828 * remapped mode, so we can re-use the current implementation
bb3541f1 8829 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8830 * int this case doesn't want to receive the interrupts.
8831 */
8832 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8833 if (ret)
8834 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8835 " fails: %d\n", irqfd->consumer.token, ret);
8836}
8837
8838int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8839 uint32_t guest_irq, bool set)
8840{
8841 if (!kvm_x86_ops->update_pi_irte)
8842 return -EINVAL;
8843
8844 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8845}
8846
52004014
FW		 8847bool kvm_vector_hashing_enabled(void)
8848{
8849 return vector_hashing;
8850}
8851EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8852
229456fc 8853EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8854EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8855EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8856EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8857EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8858EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8859EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8860EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8861EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8862EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8863EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8864EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8865EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8866EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8867EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8868EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8869EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8870EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8871EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)