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KVM: x86: Handle emulation failure directly in kvm_task_switch()
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
043405e1
CO		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 17 */
18
edf88417 19#include <linux/kvm_host.h>
313a3dc7 20#include "irq.h"
1d737c8a 21#include "mmu.h"
7837699f 22#include "i8254.h"
37817f29 23#include "tss.h"
5fdbf976 24#include "kvm_cache_regs.h"
26eef70c 25#include "x86.h"
00b27a3e 26#include "cpuid.h"
474a5bb9 27#include "pmu.h"
e83d5887 28#include "hyperv.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
1767e931
PG		 35#include <linux/export.h>
36#include <linux/moduleparam.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
87276880
FW		 51#include <linux/kvm_irqfd.h>
52#include <linux/irqbypass.h>
3905f9ad 53#include <linux/sched/stat.h>
0c5f81da 54#include <linux/sched/isolation.h>
d0ec49d4 55#include <linux/mem_encrypt.h>
3905f9ad 56
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
b0c39dc6 68#include <asm/mshyperv.h>
0092e434 69#include <asm/hypervisor.h>
bf8c55d8 70#include <asm/intel_pt.h>
dd2cb348 71#include <clocksource/hyperv_timer.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
c3941d9e
SC		 138/*
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
143 */
144static int __read_mostly lapic_timer_advance_ns = -1;
0e6edceb 145module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
d0659d94 146
52004014
FW		 147static bool __read_mostly vector_hashing = true;
148module_param(vector_hashing, bool, S_IRUGO);
149
c4ae60e4
LA		 150bool __read_mostly enable_vmware_backdoor = false;
151module_param(enable_vmware_backdoor, bool, S_IRUGO);
152EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
153
6c86eedc
WL		 154static bool __read_mostly force_emulation_prefix = false;
155module_param(force_emulation_prefix, bool, S_IRUGO);
156
0c5f81da
WL		 157int __read_mostly pi_inject_timer = -1;
158module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
159
18863bdd
AK		 160#define KVM_NR_SHARED_MSRS 16
161
162struct kvm_shared_msrs_global {
163 int nr;
2bf78fa7 164 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 165};
166
167struct kvm_shared_msrs {
168 struct user_return_notifier urn;
169 bool registered;
2bf78fa7
SY		 170 struct kvm_shared_msr_values {
171 u64 host;
172 u64 curr;
173 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 174};
175
176static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 177static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 178
417bc304 179struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 190 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 195 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 202 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 203 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 204 { "req_event", VCPU_STAT(req_event) },
c595ceee 205 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 213 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 215 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 218 { NULL }
219};
220
2acf923e
DC		 221u64 __read_mostly host_xcr0;
222
b666a4b6
MO		 223struct kmem_cache *x86_fpu_cache;
224EXPORT_SYMBOL_GPL(x86_fpu_cache);
225
b6785def 226static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 227
af585b92
GN		 228static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
229{
230 int i;
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
233}
234
18863bdd
AK		 235static void kvm_on_user_return(struct user_return_notifier *urn)
236{
237 unsigned slot;
18863bdd
AK		 238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 240 struct kvm_shared_msr_values *values;
1650b4eb
IA		 241 unsigned long flags;
242
243 /*
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
246 */
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
251 }
252 local_irq_restore(flags);
18863bdd 253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
18863bdd
AK		 258 }
259 }
18863bdd
AK		 260}
261
2bf78fa7 262static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 263{
18863bdd 264 u64 value;
013f6a5d
MT		 265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 267
2bf78fa7
SY		 268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
272 return;
273 }
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
277}
278
279void kvm_define_shared_msr(unsigned slot, u32 msr)
280{
0123be42 281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 282 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 285}
286EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
287
288static void kvm_shared_msr_cpu_online(void)
289{
290 unsigned i;
18863bdd
AK		 291
292 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 293 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 294}
295
8b3c3104 296int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 300 int err;
18863bdd 301
2bf78fa7 302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 303 return 0;
2bf78fa7 304 smsr->values[slot].curr = value;
8b3c3104
AH		 305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
306 if (err)
307 return 1;
308
18863bdd
AK		 309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
313 }
8b3c3104 314 return 0;
18863bdd
AK		 315}
316EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
317
13a34e06 318static void drop_user_return_notifiers(void)
3548bab5 319{
013f6a5d
MT		 320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 322
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
325}
326
6866b83e
CO		 327u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
328{
8a5a87d9 329 return vcpu->arch.apic_base;
6866b83e
CO		 330}
331EXPORT_SYMBOL_GPL(kvm_get_apic_base);
332
58871649
JM		 333enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
334{
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
336}
337EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
338
58cb628d
JK		 339int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
340{
58871649
JM		 341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 345
58871649 346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 347 return 1;
58871649
JM		 348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
350 return 1;
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
352 return 1;
353 }
58cb628d
JK		 354
355 kvm_lapic_set_base(vcpu, msr_info->data);
356 return 0;
6866b83e
CO		 357}
358EXPORT_SYMBOL_GPL(kvm_set_apic_base);
359
2605fc21 360asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 361{
362 /* Fault while not rebooting. We want the trace. */
363 BUG();
364}
365EXPORT_SYMBOL_GPL(kvm_spurious_fault);
366
3fd28fce
ED		 367#define EXCPT_BENIGN 0
368#define EXCPT_CONTRIBUTORY 1
369#define EXCPT_PF 2
370
371static int exception_class(int vector)
372{
373 switch (vector) {
374 case PF_VECTOR:
375 return EXCPT_PF;
376 case DE_VECTOR:
377 case TS_VECTOR:
378 case NP_VECTOR:
379 case SS_VECTOR:
380 case GP_VECTOR:
381 return EXCPT_CONTRIBUTORY;
382 default:
383 break;
384 }
385 return EXCPT_BENIGN;
386}
387
d6e8c854
NA		 388#define EXCPT_FAULT 0
389#define EXCPT_TRAP 1
390#define EXCPT_ABORT 2
391#define EXCPT_INTERRUPT 3
392
393static int exception_type(int vector)
394{
395 unsigned int mask;
396
397 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
398 return EXCPT_INTERRUPT;
399
400 mask = 1 << vector;
401
402 /* #DB is trap, as instruction watchpoints are handled elsewhere */
403 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
404 return EXCPT_TRAP;
405
406 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
407 return EXCPT_ABORT;
408
409 /* Reserved exceptions will result in fault */
410 return EXCPT_FAULT;
411}
412
da998b46
JM		 413void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
414{
415 unsigned nr = vcpu->arch.exception.nr;
416 bool has_payload = vcpu->arch.exception.has_payload;
417 unsigned long payload = vcpu->arch.exception.payload;
418
419 if (!has_payload)
420 return;
421
422 switch (nr) {
f10c729f
JM		 423 case DB_VECTOR:
424 /*
425 * "Certain debug exceptions may clear bit 0-3. The
426 * remaining contents of the DR6 register are never
427 * cleared by the processor".
428 */
429 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
430 /*
431 * DR6.RTM is set by all #DB exceptions that don't clear it.
432 */
433 vcpu->arch.dr6 |= DR6_RTM;
434 vcpu->arch.dr6 |= payload;
435 /*
436 * Bit 16 should be set in the payload whenever the #DB
437 * exception should clear DR6.RTM. This makes the payload
438 * compatible with the pending debug exceptions under VMX.
439 * Though not currently documented in the SDM, this also
440 * makes the payload compatible with the exit qualification
441 * for #DB exceptions under VMX.
442 */
443 vcpu->arch.dr6 ^= payload & DR6_RTM;
444 break;
da998b46
JM		 445 case PF_VECTOR:
446 vcpu->arch.cr2 = payload;
447 break;
448 }
449
450 vcpu->arch.exception.has_payload = false;
451 vcpu->arch.exception.payload = 0;
452}
453EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
454
3fd28fce 455static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 456 unsigned nr, bool has_error, u32 error_code,
91e86d22 457 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 458{
459 u32 prev_nr;
460 int class1, class2;
461
3842d135
AK		 462 kvm_make_request(KVM_REQ_EVENT, vcpu);
463
664f8e26 464 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 465 queue:
3ffb2468
NA		 466 if (has_error && !is_protmode(vcpu))
467 has_error = false;
664f8e26
WL		 468 if (reinject) {
469 /*
470 * On vmentry, vcpu->arch.exception.pending is only
471 * true if an event injection was blocked by
472 * nested_run_pending. In that case, however,
473 * vcpu_enter_guest requests an immediate exit,
474 * and the guest shouldn't proceed far enough to
475 * need reinjection.
476 */
477 WARN_ON_ONCE(vcpu->arch.exception.pending);
478 vcpu->arch.exception.injected = true;
91e86d22
JM		 479 if (WARN_ON_ONCE(has_payload)) {
480 /*
481 * A reinjected event has already
482 * delivered its payload.
483 */
484 has_payload = false;
485 payload = 0;
486 }
664f8e26
WL		 487 } else {
488 vcpu->arch.exception.pending = true;
489 vcpu->arch.exception.injected = false;
490 }
3fd28fce
ED		 491 vcpu->arch.exception.has_error_code = has_error;
492 vcpu->arch.exception.nr = nr;
493 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 494 vcpu->arch.exception.has_payload = has_payload;
495 vcpu->arch.exception.payload = payload;
da998b46
JM		 496 /*
497 * In guest mode, payload delivery should be deferred,
498 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 499 * CR2 is modified (or intercept #DB before DR6 is
500 * modified under nVMX). However, for ABI
501 * compatibility with KVM_GET_VCPU_EVENTS and
502 * KVM_SET_VCPU_EVENTS, we can't delay payload
503 * delivery unless userspace has enabled this
504 * functionality via the per-VM capability,
505 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 506 */
507 if (!vcpu->kvm->arch.exception_payload_enabled ||
508 !is_guest_mode(vcpu))
509 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 510 return;
511 }
512
513 /* to check exception */
514 prev_nr = vcpu->arch.exception.nr;
515 if (prev_nr == DF_VECTOR) {
516 /* triple fault -> shutdown */
a8eeb04a 517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 518 return;
519 }
520 class1 = exception_class(prev_nr);
521 class2 = exception_class(nr);
522 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
523 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 524 /*
525 * Generate double fault per SDM Table 5-5. Set
526 * exception.pending = true so that the double fault
527 * can trigger a nested vmexit.
528 */
3fd28fce 529 vcpu->arch.exception.pending = true;
664f8e26 530 vcpu->arch.exception.injected = false;
3fd28fce
ED		 531 vcpu->arch.exception.has_error_code = true;
532 vcpu->arch.exception.nr = DF_VECTOR;
533 vcpu->arch.exception.error_code = 0;
c851436a
JM		 534 vcpu->arch.exception.has_payload = false;
535 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 536 } else
537 /* replace previous exception with a new one in a hope
538 that instruction re-execution will regenerate lost
539 exception */
540 goto queue;
541}
542
298101da
AK		 543void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544{
91e86d22 545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 546}
547EXPORT_SYMBOL_GPL(kvm_queue_exception);
548
ce7ddec4
JR		 549void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
550{
91e86d22 551 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 552}
553EXPORT_SYMBOL_GPL(kvm_requeue_exception);
554
f10c729f
JM		 555static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
556 unsigned long payload)
557{
558 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
559}
560
da998b46
JM		 561static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
562 u32 error_code, unsigned long payload)
563{
564 kvm_multiple_exception(vcpu, nr, true, error_code,
565 true, payload, false);
566}
567
6affcbed 568int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 569{
db8fcefa
AP		 570 if (err)
571 kvm_inject_gp(vcpu, 0);
572 else
6affcbed
KH		 573 return kvm_skip_emulated_instruction(vcpu);
574
575 return 1;
db8fcefa
AP		 576}
577EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 578
6389ee94 579void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 580{
581 ++vcpu->stat.pf_guest;
adfe20fb
WL		 582 vcpu->arch.exception.nested_apf =
583 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 584 if (vcpu->arch.exception.nested_apf) {
adfe20fb 585 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 586 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
587 } else {
588 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
589 fault->address);
590 }
c3c91fee 591}
27d6c865 592EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 593
ef54bcfe 594static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 595{
6389ee94
AK		 596 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
597 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 598 else
44dd3ffa 599 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 600
601 return fault->nested_page_fault;
d4f8cf66
JR		 602}
603
3419ffc8
SY		 604void kvm_inject_nmi(struct kvm_vcpu *vcpu)
605{
7460fb4a
AK		 606 atomic_inc(&vcpu->arch.nmi_queued);
607 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 608}
609EXPORT_SYMBOL_GPL(kvm_inject_nmi);
610
298101da
AK		 611void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612{
91e86d22 613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 614}
615EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
616
ce7ddec4
JR		 617void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
618{
91e86d22 619 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 620}
621EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
622
0a79b009
AK		 623/*
624 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
625 * a #GP and return false.
626 */
627bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 628{
0a79b009
AK		 629 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
630 return true;
631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
632 return false;
298101da 633}
0a79b009 634EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 635
16f8a6f9
NA		 636bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
637{
638 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
639 return true;
640
641 kvm_queue_exception(vcpu, UD_VECTOR);
642 return false;
643}
644EXPORT_SYMBOL_GPL(kvm_require_dr);
645
ec92fe44
JR		 646/*
647 * This function will be used to read from the physical memory of the currently
54bf36aa 648 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 649 * can read from guest physical or from the guest's guest physical memory.
650 */
651int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
652 gfn_t ngfn, void *data, int offset, int len,
653 u32 access)
654{
54987b7a 655 struct x86_exception exception;
ec92fe44
JR		 656 gfn_t real_gfn;
657 gpa_t ngpa;
658
659 ngpa = gfn_to_gpa(ngfn);
54987b7a 660 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 661 if (real_gfn == UNMAPPED_GVA)
662 return -EFAULT;
663
664 real_gfn = gpa_to_gfn(real_gfn);
665
54bf36aa 666 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 667}
668EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
669
69b0049a 670static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 671 void *data, int offset, int len, u32 access)
672{
673 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
674 data, offset, len, access);
675}
676
16cfacc8
SC		 677static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
678{
679 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
680 rsvd_bits(1, 2);
681}
682
a03490ed 683/*
16cfacc8 684 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
a03490ed 685 */
ff03a073 686int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 687{
688 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
689 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
690 int i;
691 int ret;
ff03a073 692 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 693
ff03a073
JR		 694 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
695 offset * sizeof(u64), sizeof(pdpte),
696 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 697 if (ret < 0) {
698 ret = 0;
699 goto out;
700 }
701 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 702 if ((pdpte[i] & PT_PRESENT_MASK) &&
16cfacc8 703 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
a03490ed
CO		 704 ret = 0;
705 goto out;
706 }
707 }
708 ret = 1;
709
ff03a073 710 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 711 __set_bit(VCPU_EXREG_PDPTR,
712 (unsigned long *)&vcpu->arch.regs_avail);
713 __set_bit(VCPU_EXREG_PDPTR,
714 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 715out:
a03490ed
CO		 716
717 return ret;
718}
cc4b6871 719EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 720
9ed38ffa 721bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 722{
ff03a073 723 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 724 bool changed = true;
3d06b8bf
JR		 725 int offset;
726 gfn_t gfn;
d835dfec
AK		 727 int r;
728
bf03d4f9 729 if (!is_pae_paging(vcpu))
d835dfec
AK		 730 return false;
731
6de4f3ad
AK		 732 if (!test_bit(VCPU_EXREG_PDPTR,
733 (unsigned long *)&vcpu->arch.regs_avail))
734 return true;
735
a512177e
PB		 736 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
737 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 738 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
739 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 740 if (r < 0)
741 goto out;
ff03a073 742 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 743out:
d835dfec
AK		 744
745 return changed;
746}
9ed38ffa 747EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 748
49a9b07e 749int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 750{
aad82703 751 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 752 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 753
f9a48e6a
AK		 754 cr0 |= X86_CR0_ET;
755
ab344828 756#ifdef CONFIG_X86_64
0f12244f
GN		 757 if (cr0 & 0xffffffff00000000UL)
758 return 1;
ab344828
GN		 759#endif
760
761 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 762
0f12244f
GN		 763 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
764 return 1;
a03490ed 765
0f12244f
GN		 766 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
767 return 1;
a03490ed
CO		 768
769 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
770#ifdef CONFIG_X86_64
f6801dff 771 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 772 int cs_db, cs_l;
773
0f12244f
GN		 774 if (!is_pae(vcpu))
775 return 1;
a03490ed 776 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 777 if (cs_l)
778 return 1;
a03490ed
CO		 779 } else
780#endif
ff03a073 781 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 782 kvm_read_cr3(vcpu)))
0f12244f 783 return 1;
a03490ed
CO		 784 }
785
ad756a16
MJ		 786 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
787 return 1;
788
a03490ed 789 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 790
d170c419 791 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 792 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 793 kvm_async_pf_hash_reset(vcpu);
794 }
e5f3f027 795
aad82703
SY		 796 if ((cr0 ^ old_cr0) & update_bits)
797 kvm_mmu_reset_context(vcpu);
b18d5431 798
879ae188
LE		 799 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
800 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
801 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 802 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
803
0f12244f
GN		 804 return 0;
805}
2d3ad1f4 806EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 807
2d3ad1f4 808void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 809{
49a9b07e 810 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 811}
2d3ad1f4 812EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 813
1811d979 814void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 815{
816 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
817 !vcpu->guest_xcr0_loaded) {
818 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 819 if (vcpu->arch.xcr0 != host_xcr0)
820 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 821 vcpu->guest_xcr0_loaded = 1;
822 }
823}
1811d979 824EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
42bdf991 825
1811d979 826void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 827{
828 if (vcpu->guest_xcr0_loaded) {
829 if (vcpu->arch.xcr0 != host_xcr0)
830 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
831 vcpu->guest_xcr0_loaded = 0;
832 }
833}
1811d979 834EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
42bdf991 835
69b0049a 836static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 837{
56c103ec
LJ		 838 u64 xcr0 = xcr;
839 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 840 u64 valid_bits;
2acf923e
DC		 841
842 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
843 if (index != XCR_XFEATURE_ENABLED_MASK)
844 return 1;
d91cab78 845 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 846 return 1;
d91cab78 847 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 848 return 1;
46c34cb0
PB		 849
850 /*
851 * Do not allow the guest to set bits that we do not support
852 * saving. However, xcr0 bit 0 is always set, even if the
853 * emulated CPU does not support XSAVE (see fx_init).
854 */
d91cab78 855 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 856 if (xcr0 & ~valid_bits)
2acf923e 857 return 1;
46c34cb0 858
d91cab78
DH		 859 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
860 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 861 return 1;
862
d91cab78
DH		 863 if (xcr0 & XFEATURE_MASK_AVX512) {
864 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 865 return 1;
d91cab78 866 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 867 return 1;
868 }
2acf923e 869 vcpu->arch.xcr0 = xcr0;
56c103ec 870
d91cab78 871 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 872 kvm_update_cpuid(vcpu);
2acf923e
DC		 873 return 0;
874}
875
876int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
877{
764bcbc5
Z		 878 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
879 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 880 kvm_inject_gp(vcpu, 0);
881 return 1;
882 }
883 return 0;
884}
885EXPORT_SYMBOL_GPL(kvm_set_xcr);
886
a83b29c6 887int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 888{
fc78f519 889 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 890 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 891 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 892
0f12244f
GN		 893 if (cr4 & CR4_RESERVED_BITS)
894 return 1;
a03490ed 895
d6321d49 896 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 897 return 1;
898
d6321d49 899 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 900 return 1;
901
d6321d49 902 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 903 return 1;
904
d6321d49 905 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 906 return 1;
907
d6321d49 908 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 909 return 1;
910
fd8cb433 911 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 912 return 1;
913
ae3e61e1
PB		 914 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
915 return 1;
916
a03490ed 917 if (is_long_mode(vcpu)) {
0f12244f
GN		 918 if (!(cr4 & X86_CR4_PAE))
919 return 1;
a2edf57f
AK		 920 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
921 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 922 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
923 kvm_read_cr3(vcpu)))
0f12244f
GN		 924 return 1;
925
ad756a16 926 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 927 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 928 return 1;
929
930 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
931 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
932 return 1;
933 }
934
5e1746d6 935 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 936 return 1;
a03490ed 937
ad756a16
MJ		 938 if (((cr4 ^ old_cr4) & pdptr_bits) ||
939 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 940 kvm_mmu_reset_context(vcpu);
0f12244f 941
b9baba86 942 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 943 kvm_update_cpuid(vcpu);
2acf923e 944
0f12244f
GN		 945 return 0;
946}
2d3ad1f4 947EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 948
2390218b 949int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 950{
ade61e28 951 bool skip_tlb_flush = false;
ac146235 952#ifdef CONFIG_X86_64
c19986fe
JS		 953 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
954
ade61e28 955 if (pcid_enabled) {
208320ba
JS		 956 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
957 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 958 }
ac146235 959#endif
9d88fca7 960
9f8fe504 961 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 962 if (!skip_tlb_flush) {
963 kvm_mmu_sync_roots(vcpu);
ade61e28 964 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 965 }
0f12244f 966 return 0;
d835dfec
AK		 967 }
968
d1cd3ce9 969 if (is_long_mode(vcpu) &&
a780a3ea 970 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9 971 return 1;
bf03d4f9
PB		 972 else if (is_pae_paging(vcpu) &&
973 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 974 return 1;
a03490ed 975
ade61e28 976 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 977 vcpu->arch.cr3 = cr3;
aff48baa 978 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 979
0f12244f
GN		 980 return 0;
981}
2d3ad1f4 982EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 983
eea1cff9 984int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 985{
0f12244f
GN		 986 if (cr8 & CR8_RESERVED_BITS)
987 return 1;
35754c98 988 if (lapic_in_kernel(vcpu))
a03490ed
CO		 989 kvm_lapic_set_tpr(vcpu, cr8);
990 else
ad312c7c 991 vcpu->arch.cr8 = cr8;
0f12244f
GN		 992 return 0;
993}
2d3ad1f4 994EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 995
2d3ad1f4 996unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 997{
35754c98 998 if (lapic_in_kernel(vcpu))
a03490ed
CO		 999 return kvm_lapic_get_cr8(vcpu);
1000 else
ad312c7c 1001 return vcpu->arch.cr8;
a03490ed 1002}
2d3ad1f4 1003EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 1004
ae561ede
NA		 1005static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1006{
1007 int i;
1008
1009 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1010 for (i = 0; i < KVM_NR_DB_REGS; i++)
1011 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1012 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1013 }
1014}
1015
73aaf249
JK		 1016static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1017{
1018 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1019 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1020}
1021
c8639010
JK		 1022static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1023{
1024 unsigned long dr7;
1025
1026 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1027 dr7 = vcpu->arch.guest_debug_dr7;
1028 else
1029 dr7 = vcpu->arch.dr7;
1030 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1031 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1032 if (dr7 & DR7_BP_EN_MASK)
1033 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1034}
1035
6f43ed01
NA		 1036static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1037{
1038 u64 fixed = DR6_FIXED_1;
1039
d6321d49 1040 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1041 fixed |= DR6_RTM;
1042 return fixed;
1043}
1044
338dbc97 1045static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1046{
1047 switch (dr) {
1048 case 0 ... 3:
1049 vcpu->arch.db[dr] = val;
1050 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1051 vcpu->arch.eff_db[dr] = val;
1052 break;
1053 case 4:
020df079
GN		 1054 /* fall through */
1055 case 6:
338dbc97
GN		 1056 if (val & 0xffffffff00000000ULL)
1057 return -1; /* #GP */
6f43ed01 1058 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1059 kvm_update_dr6(vcpu);
020df079
GN		 1060 break;
1061 case 5:
020df079
GN		 1062 /* fall through */
1063 default: /* 7 */
338dbc97
GN		 1064 if (val & 0xffffffff00000000ULL)
1065 return -1; /* #GP */
020df079 1066 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1067 kvm_update_dr7(vcpu);
020df079
GN		 1068 break;
1069 }
1070
1071 return 0;
1072}
338dbc97
GN		 1073
1074int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1075{
16f8a6f9 1076 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1077 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1078 return 1;
1079 }
1080 return 0;
338dbc97 1081}
020df079
GN		 1082EXPORT_SYMBOL_GPL(kvm_set_dr);
1083
16f8a6f9 1084int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1085{
1086 switch (dr) {
1087 case 0 ... 3:
1088 *val = vcpu->arch.db[dr];
1089 break;
1090 case 4:
020df079
GN		 1091 /* fall through */
1092 case 6:
73aaf249
JK		 1093 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1094 *val = vcpu->arch.dr6;
1095 else
1096 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1097 break;
1098 case 5:
020df079
GN		 1099 /* fall through */
1100 default: /* 7 */
1101 *val = vcpu->arch.dr7;
1102 break;
1103 }
338dbc97
GN		 1104 return 0;
1105}
020df079
GN		 1106EXPORT_SYMBOL_GPL(kvm_get_dr);
1107
022cd0e8
AK		 1108bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1109{
de3cd117 1110 u32 ecx = kvm_rcx_read(vcpu);
022cd0e8
AK		 1111 u64 data;
1112 int err;
1113
c6702c9d 1114 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1115 if (err)
1116 return err;
de3cd117
SC		 1117 kvm_rax_write(vcpu, (u32)data);
1118 kvm_rdx_write(vcpu, data >> 32);
022cd0e8
AK		 1119 return err;
1120}
1121EXPORT_SYMBOL_GPL(kvm_rdpmc);
1122
043405e1
CO		 1123/*
1124 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1125 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1126 *
1127 * This list is modified at module load time to reflect the
e3267cbb 1128 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1129 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1130 * may depend on host virtualization features rather than host cpu features.
043405e1 1131 */
e3267cbb 1132
043405e1
CO		 1133static u32 msrs_to_save[] = {
1134 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1135 MSR_STAR,
043405e1
CO		 1136#ifdef CONFIG_X86_64
1137 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1138#endif
b3897a49 1139 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1140 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1141 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1142 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1143 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1144 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1145 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1146 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1147 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
e2ada66e
JM		 1148 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1149 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1150 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1151 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1152 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1153 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1154 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1155 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1156 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1157 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1158 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1159 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1160 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1161 MSR_ARCH_PERFMON_PERFCTR0 + 18, MSR_ARCH_PERFMON_PERFCTR0 + 19,
1162 MSR_ARCH_PERFMON_PERFCTR0 + 20, MSR_ARCH_PERFMON_PERFCTR0 + 21,
1163 MSR_ARCH_PERFMON_PERFCTR0 + 22, MSR_ARCH_PERFMON_PERFCTR0 + 23,
1164 MSR_ARCH_PERFMON_PERFCTR0 + 24, MSR_ARCH_PERFMON_PERFCTR0 + 25,
1165 MSR_ARCH_PERFMON_PERFCTR0 + 26, MSR_ARCH_PERFMON_PERFCTR0 + 27,
1166 MSR_ARCH_PERFMON_PERFCTR0 + 28, MSR_ARCH_PERFMON_PERFCTR0 + 29,
1167 MSR_ARCH_PERFMON_PERFCTR0 + 30, MSR_ARCH_PERFMON_PERFCTR0 + 31,
1168 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1169 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1170 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1171 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1172 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1173 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1174 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1175 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1176 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1177 MSR_ARCH_PERFMON_EVENTSEL0 + 18, MSR_ARCH_PERFMON_EVENTSEL0 + 19,
1178 MSR_ARCH_PERFMON_EVENTSEL0 + 20, MSR_ARCH_PERFMON_EVENTSEL0 + 21,
1179 MSR_ARCH_PERFMON_EVENTSEL0 + 22, MSR_ARCH_PERFMON_EVENTSEL0 + 23,
1180 MSR_ARCH_PERFMON_EVENTSEL0 + 24, MSR_ARCH_PERFMON_EVENTSEL0 + 25,
1181 MSR_ARCH_PERFMON_EVENTSEL0 + 26, MSR_ARCH_PERFMON_EVENTSEL0 + 27,
1182 MSR_ARCH_PERFMON_EVENTSEL0 + 28, MSR_ARCH_PERFMON_EVENTSEL0 + 29,
1183 MSR_ARCH_PERFMON_EVENTSEL0 + 30, MSR_ARCH_PERFMON_EVENTSEL0 + 31,
043405e1
CO		 1184};
1185
1186static unsigned num_msrs_to_save;
1187
62ef68bb
PB		 1188static u32 emulated_msrs[] = {
1189 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1190 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1191 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1192 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1193 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1194 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1195 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1196 HV_X64_MSR_RESET,
11c4b1ca 1197 HV_X64_MSR_VP_INDEX,
9eec50b8 1198 HV_X64_MSR_VP_RUNTIME,
5c919412 1199 HV_X64_MSR_SCONTROL,
1f4b34f8 1200 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1201 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1202 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1203 HV_X64_MSR_TSC_EMULATION_STATUS,
1204
1205 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1206 MSR_KVM_PV_EOI_EN,
1207
ba904635 1208 MSR_IA32_TSC_ADJUST,
a3e06bbe 1209 MSR_IA32_TSCDEADLINE,
2bdb76c0 1210 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1211 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1212 MSR_IA32_MCG_STATUS,
1213 MSR_IA32_MCG_CTL,
c45dcc71 1214 MSR_IA32_MCG_EXT_CTL,
64d60670 1215 MSR_IA32_SMBASE,
52797bf9 1216 MSR_SMI_COUNT,
db2336a8
KH		 1217 MSR_PLATFORM_INFO,
1218 MSR_MISC_FEATURES_ENABLES,
bc226f07 1219 MSR_AMD64_VIRT_SPEC_CTRL,
6c6a2ab9 1220 MSR_IA32_POWER_CTL,
191c8137 1221
95c5c7c7
PB		 1222 /*
1223 * The following list leaves out MSRs whose values are determined
1224 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1225 * We always support the "true" VMX control MSRs, even if the host
1226 * processor does not, so I am putting these registers here rather
1227 * than in msrs_to_save.
1228 */
1229 MSR_IA32_VMX_BASIC,
1230 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1231 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1232 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1233 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1234 MSR_IA32_VMX_MISC,
1235 MSR_IA32_VMX_CR0_FIXED0,
1236 MSR_IA32_VMX_CR4_FIXED0,
1237 MSR_IA32_VMX_VMCS_ENUM,
1238 MSR_IA32_VMX_PROCBASED_CTLS2,
1239 MSR_IA32_VMX_EPT_VPID_CAP,
1240 MSR_IA32_VMX_VMFUNC,
1241
191c8137 1242 MSR_K7_HWCR,
2d5ba19b 1243 MSR_KVM_POLL_CONTROL,
043405e1
CO		 1244};
1245
62ef68bb
PB		 1246static unsigned num_emulated_msrs;
1247
801e459a
TL		 1248/*
1249 * List of msr numbers which are used to expose MSR-based features that
1250 * can be used by a hypervisor to validate requested CPU features.
1251 */
1252static u32 msr_based_features[] = {
1389309c
PB		 1253 MSR_IA32_VMX_BASIC,
1254 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1255 MSR_IA32_VMX_PINBASED_CTLS,
1256 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1257 MSR_IA32_VMX_PROCBASED_CTLS,
1258 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1259 MSR_IA32_VMX_EXIT_CTLS,
1260 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1261 MSR_IA32_VMX_ENTRY_CTLS,
1262 MSR_IA32_VMX_MISC,
1263 MSR_IA32_VMX_CR0_FIXED0,
1264 MSR_IA32_VMX_CR0_FIXED1,
1265 MSR_IA32_VMX_CR4_FIXED0,
1266 MSR_IA32_VMX_CR4_FIXED1,
1267 MSR_IA32_VMX_VMCS_ENUM,
1268 MSR_IA32_VMX_PROCBASED_CTLS2,
1269 MSR_IA32_VMX_EPT_VPID_CAP,
1270 MSR_IA32_VMX_VMFUNC,
1271
d1d93fa9 1272 MSR_F10H_DECFG,
518e7b94 1273 MSR_IA32_UCODE_REV,
cd283252 1274 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1275};
1276
1277static unsigned int num_msr_based_features;
1278
4d22c17c 1279static u64 kvm_get_arch_capabilities(void)
5b76a3cf 1280{
4d22c17c 1281 u64 data = 0;
5b76a3cf 1282
4d22c17c
XL		 1283 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1284 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
5b76a3cf
PB		 1285
1286 /*
1287 * If we're doing cache flushes (either "always" or "cond")
1288 * we will do one whenever the guest does a vmlaunch/vmresume.
1289 * If an outer hypervisor is doing the cache flush for us
1290 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1291 * capability to the guest too, and if EPT is disabled we're not
1292 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1293 * require a nested hypervisor to do a flush of its own.
1294 */
1295 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1296 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1297
0c54914d
PB		 1298 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1299 data |= ARCH_CAP_RDCL_NO;
1300 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1301 data |= ARCH_CAP_SSB_NO;
1302 if (!boot_cpu_has_bug(X86_BUG_MDS))
1303 data |= ARCH_CAP_MDS_NO;
1304
5b76a3cf
PB		 1305 return data;
1306}
5b76a3cf 1307
66421c1e
WL		 1308static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1309{
1310 switch (msr->index) {
cd283252 1311 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1312 msr->data = kvm_get_arch_capabilities();
1313 break;
1314 case MSR_IA32_UCODE_REV:
cd283252 1315 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1316 break;
66421c1e
WL		 1317 default:
1318 if (kvm_x86_ops->get_msr_feature(msr))
1319 return 1;
1320 }
1321 return 0;
1322}
1323
801e459a
TL		 1324static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1325{
1326 struct kvm_msr_entry msr;
66421c1e 1327 int r;
801e459a
TL		 1328
1329 msr.index = index;
66421c1e
WL		 1330 r = kvm_get_msr_feature(&msr);
1331 if (r)
1332 return r;
801e459a
TL		 1333
1334 *data = msr.data;
1335
1336 return 0;
1337}
1338
11988499 1339static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1340{
1b4d56b8 1341 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
11988499 1342 return false;
1b2fd70c 1343
1b4d56b8 1344 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
11988499 1345 return false;
d8017474 1346
0a629563
SC		 1347 if (efer & (EFER_LME | EFER_LMA) &&
1348 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1349 return false;
1350
1351 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1352 return false;
d8017474 1353
384bb783 1354 return true;
11988499
SC		 1355
1356}
1357bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1358{
1359 if (efer & efer_reserved_bits)
1360 return false;
1361
1362 return __kvm_valid_efer(vcpu, efer);
384bb783
JK		 1363}
1364EXPORT_SYMBOL_GPL(kvm_valid_efer);
1365
11988499 1366static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
384bb783
JK		 1367{
1368 u64 old_efer = vcpu->arch.efer;
11988499 1369 u64 efer = msr_info->data;
384bb783 1370
11988499 1371 if (efer & efer_reserved_bits)
66f61c92 1372 return 1;
384bb783 1373
11988499
SC		 1374 if (!msr_info->host_initiated) {
1375 if (!__kvm_valid_efer(vcpu, efer))
1376 return 1;
1377
1378 if (is_paging(vcpu) &&
1379 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1380 return 1;
1381 }
384bb783 1382
15c4a640 1383 efer &= ~EFER_LMA;
f6801dff 1384 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1385
a3d204e2
SY		 1386 kvm_x86_ops->set_efer(vcpu, efer);
1387
aad82703
SY		 1388 /* Update reserved bits */
1389 if ((efer ^ old_efer) & EFER_NX)
1390 kvm_mmu_reset_context(vcpu);
1391
b69e8cae 1392 return 0;
15c4a640
CO		 1393}
1394
f2b4b7dd
JR		 1395void kvm_enable_efer_bits(u64 mask)
1396{
1397 efer_reserved_bits &= ~mask;
1398}
1399EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1400
15c4a640 1401/*
f20935d8
SC		 1402 * Write @data into the MSR specified by @index. Select MSR specific fault
1403 * checks are bypassed if @host_initiated is %true.
15c4a640
CO		 1404 * Returns 0 on success, non-0 otherwise.
1405 * Assumes vcpu_load() was already called.
1406 */
f20935d8
SC		 1407static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1408 bool host_initiated)
15c4a640 1409{
f20935d8
SC		 1410 struct msr_data msr;
1411
1412 switch (index) {
854e8bb1
NA		 1413 case MSR_FS_BASE:
1414 case MSR_GS_BASE:
1415 case MSR_KERNEL_GS_BASE:
1416 case MSR_CSTAR:
1417 case MSR_LSTAR:
f20935d8 1418 if (is_noncanonical_address(data, vcpu))
854e8bb1
NA		 1419 return 1;
1420 break;
1421 case MSR_IA32_SYSENTER_EIP:
1422 case MSR_IA32_SYSENTER_ESP:
1423 /*
1424 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1425 * non-canonical address is written on Intel but not on
1426 * AMD (which ignores the top 32-bits, because it does
1427 * not implement 64-bit SYSENTER).
1428 *
1429 * 64-bit code should hence be able to write a non-canonical
1430 * value on AMD. Making the address canonical ensures that
1431 * vmentry does not fail on Intel after writing a non-canonical
1432 * value, and that something deterministic happens if the guest
1433 * invokes 64-bit SYSENTER.
1434 */
f20935d8 1435 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1436 }
f20935d8
SC		 1437
1438 msr.data = data;
1439 msr.index = index;
1440 msr.host_initiated = host_initiated;
1441
1442 return kvm_x86_ops->set_msr(vcpu, &msr);
15c4a640
CO		 1443}
1444
313a3dc7 1445/*
f20935d8
SC		 1446 * Read the MSR specified by @index into @data. Select MSR specific fault
1447 * checks are bypassed if @host_initiated is %true.
1448 * Returns 0 on success, non-0 otherwise.
1449 * Assumes vcpu_load() was already called.
313a3dc7 1450 */
f20935d8
SC		 1451static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1452 bool host_initiated)
609e36d3
PB		 1453{
1454 struct msr_data msr;
f20935d8 1455 int ret;
609e36d3
PB		 1456
1457 msr.index = index;
f20935d8 1458 msr.host_initiated = host_initiated;
609e36d3 1459
f20935d8
SC		 1460 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1461 if (!ret)
1462 *data = msr.data;
1463 return ret;
609e36d3
PB		 1464}
1465
f20935d8 1466int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
313a3dc7 1467{
f20935d8
SC		 1468 return __kvm_get_msr(vcpu, index, data, false);
1469}
1470EXPORT_SYMBOL_GPL(kvm_get_msr);
8fe8ab46 1471
f20935d8
SC		 1472int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1473{
1474 return __kvm_set_msr(vcpu, index, data, false);
1475}
1476EXPORT_SYMBOL_GPL(kvm_set_msr);
1477
1edce0a9
SC		 1478int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1479{
1480 u32 ecx = kvm_rcx_read(vcpu);
1481 u64 data;
1482
1483 if (kvm_get_msr(vcpu, ecx, &data)) {
1484 trace_kvm_msr_read_ex(ecx);
1485 kvm_inject_gp(vcpu, 0);
1486 return 1;
1487 }
1488
1489 trace_kvm_msr_read(ecx, data);
1490
1491 kvm_rax_write(vcpu, data & -1u);
1492 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1493 return kvm_skip_emulated_instruction(vcpu);
1494}
1495EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1496
1497int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1498{
1499 u32 ecx = kvm_rcx_read(vcpu);
1500 u64 data = kvm_read_edx_eax(vcpu);
1501
1502 if (kvm_set_msr(vcpu, ecx, data)) {
1503 trace_kvm_msr_write_ex(ecx, data);
1504 kvm_inject_gp(vcpu, 0);
1505 return 1;
1506 }
1507
1508 trace_kvm_msr_write(ecx, data);
1509 return kvm_skip_emulated_instruction(vcpu);
1510}
1511EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1512
f20935d8
SC		 1513/*
1514 * Adapt set_msr() to msr_io()'s calling convention
1515 */
1516static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1517{
1518 return __kvm_get_msr(vcpu, index, data, true);
1519}
1520
1521static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1522{
1523 return __kvm_set_msr(vcpu, index, *data, true);
313a3dc7
CO		 1524}
1525
16e8d74d
MT		 1526#ifdef CONFIG_X86_64
1527struct pvclock_gtod_data {
1528 seqcount_t seq;
1529
1530 struct { /* extract of a clocksource struct */
1531 int vclock_mode;
a5a1d1c2
TG		 1532 u64 cycle_last;
1533 u64 mask;
16e8d74d
MT		 1534 u32 mult;
1535 u32 shift;
1536 } clock;
1537
cbcf2dd3
TG		 1538 u64 boot_ns;
1539 u64 nsec_base;
55dd00a7 1540 u64 wall_time_sec;
16e8d74d
MT		 1541};
1542
1543static struct pvclock_gtod_data pvclock_gtod_data;
1544
1545static void update_pvclock_gtod(struct timekeeper *tk)
1546{
1547 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1548 u64 boot_ns;
1549
876e7881 1550 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1551
1552 write_seqcount_begin(&vdata->seq);
1553
1554 /* copy pvclock gtod data */
876e7881
PZ		 1555 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1556 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1557 vdata->clock.mask = tk->tkr_mono.mask;
1558 vdata->clock.mult = tk->tkr_mono.mult;
1559 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1560
cbcf2dd3 1561 vdata->boot_ns = boot_ns;
876e7881 1562 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1563
55dd00a7
MT		 1564 vdata->wall_time_sec = tk->xtime_sec;
1565
16e8d74d
MT		 1566 write_seqcount_end(&vdata->seq);
1567}
1568#endif
1569
bab5bb39
NK		 1570void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1571{
bab5bb39 1572 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
4d151bf3 1573 kvm_vcpu_kick(vcpu);
bab5bb39 1574}
16e8d74d 1575
18068523
GOC		 1576static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1577{
9ed3c444
AK		 1578 int version;
1579 int r;
50d0a0f9 1580 struct pvclock_wall_clock wc;
87aeb54f 1581 struct timespec64 boot;
18068523
GOC		 1582
1583 if (!wall_clock)
1584 return;
1585
9ed3c444
AK		 1586 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1587 if (r)
1588 return;
1589
1590 if (version & 1)
1591 ++version; /* first time write, random junk */
1592
1593 ++version;
18068523 1594
1dab1345
NK		 1595 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1596 return;
18068523 1597
50d0a0f9
GH		 1598 /*
1599 * The guest calculates current wall clock time by adding
34c238a1 1600 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1601 * wall clock specified here. guest system time equals host
1602 * system time for us, thus we must fill in host boot time here.
1603 */
87aeb54f 1604 getboottime64(&boot);
50d0a0f9 1605
4b648665 1606 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1607 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1608 boot = timespec64_sub(boot, ts);
4b648665 1609 }
87aeb54f 1610 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1611 wc.nsec = boot.tv_nsec;
1612 wc.version = version;
18068523
GOC		 1613
1614 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1615
1616 version++;
1617 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1618}
1619
50d0a0f9
GH		 1620static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1621{
b51012de
PB		 1622 do_shl32_div32(dividend, divisor);
1623 return dividend;
50d0a0f9
GH		 1624}
1625
3ae13faa 1626static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1627 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1628{
5f4e3f88 1629 uint64_t scaled64;
50d0a0f9
GH		 1630 int32_t shift = 0;
1631 uint64_t tps64;
1632 uint32_t tps32;
1633
3ae13faa
PB		 1634 tps64 = base_hz;
1635 scaled64 = scaled_hz;
50933623 1636 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1637 tps64 >>= 1;
1638 shift--;
1639 }
1640
1641 tps32 = (uint32_t)tps64;
50933623
JK		 1642 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1643 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1644 scaled64 >>= 1;
1645 else
1646 tps32 <<= 1;
50d0a0f9
GH		 1647 shift++;
1648 }
1649
5f4e3f88
ZA		 1650 *pshift = shift;
1651 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9
GH		 1652}
1653
d828199e 1654#ifdef CONFIG_X86_64
16e8d74d 1655static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1656#endif
16e8d74d 1657
c8076604 1658static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1659static unsigned long max_tsc_khz;
c8076604 1660
cc578287 1661static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1662{
cc578287
ZA		 1663 u64 v = (u64)khz * (1000000 + ppm);
1664 do_div(v, 1000000);
1665 return v;
1e993611
JR		 1666}
1667
381d585c
HZ		 1668static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1669{
1670 u64 ratio;
1671
1672 /* Guest TSC same frequency as host TSC? */
1673 if (!scale) {
1674 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1675 return 0;
1676 }
1677
1678 /* TSC scaling supported? */
1679 if (!kvm_has_tsc_control) {
1680 if (user_tsc_khz > tsc_khz) {
1681 vcpu->arch.tsc_catchup = 1;
1682 vcpu->arch.tsc_always_catchup = 1;
1683 return 0;
1684 } else {
3f16a5c3 1685 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
381d585c
HZ		 1686 return -1;
1687 }
1688 }
1689
1690 /* TSC scaling required - calculate ratio */
1691 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1692 user_tsc_khz, tsc_khz);
1693
1694 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
3f16a5c3
PB		 1695 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1696 user_tsc_khz);
381d585c
HZ		 1697 return -1;
1698 }
1699
1700 vcpu->arch.tsc_scaling_ratio = ratio;
1701 return 0;
1702}
1703
4941b8cb 1704static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1705{
cc578287
ZA		 1706 u32 thresh_lo, thresh_hi;
1707 int use_scaling = 0;
217fc9cf 1708
03ba32ca 1709 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1710 if (user_tsc_khz == 0) {
ad721883
HZ		 1711 /* set tsc_scaling_ratio to a safe value */
1712 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1713 return -1;
ad721883 1714 }
03ba32ca 1715
c285545f 1716 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1717 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1718 &vcpu->arch.virtual_tsc_shift,
1719 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1720 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1721
1722 /*
1723 * Compute the variation in TSC rate which is acceptable
1724 * within the range of tolerance and decide if the
1725 * rate being applied is within that bounds of the hardware
1726 * rate. If so, no scaling or compensation need be done.
1727 */
1728 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1729 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1730 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1731 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1732 use_scaling = 1;
1733 }
4941b8cb 1734 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1735}
1736
1737static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1738{
e26101b1 1739 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1740 vcpu->arch.virtual_tsc_mult,
1741 vcpu->arch.virtual_tsc_shift);
e26101b1 1742 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1743 return tsc;
1744}
1745
b0c39dc6
VK		 1746static inline int gtod_is_based_on_tsc(int mode)
1747{
1748 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1749}
1750
69b0049a 1751static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1752{
1753#ifdef CONFIG_X86_64
1754 bool vcpus_matched;
b48aa97e
MT		 1755 struct kvm_arch *ka = &vcpu->kvm->arch;
1756 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1757
1758 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1759 atomic_read(&vcpu->kvm->online_vcpus));
1760
7f187922
MT		 1761 /*
1762 * Once the masterclock is enabled, always perform request in
1763 * order to update it.
1764 *
1765 * In order to enable masterclock, the host clocksource must be TSC
1766 * and the vcpus need to have matched TSCs. When that happens,
1767 * perform request to enable masterclock.
1768 */
1769 if (ka->use_master_clock ||
b0c39dc6 1770 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1771 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1772
1773 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1774 atomic_read(&vcpu->kvm->online_vcpus),
1775 ka->use_master_clock, gtod->clock.vclock_mode);
1776#endif
1777}
1778
ba904635
WA		 1779static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1780{
e79f245d 1781 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1782 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1783}
1784
35181e86
HZ		 1785/*
1786 * Multiply tsc by a fixed point number represented by ratio.
1787 *
1788 * The most significant 64-N bits (mult) of ratio represent the
1789 * integral part of the fixed point number; the remaining N bits
1790 * (frac) represent the fractional part, ie. ratio represents a fixed
1791 * point number (mult + frac * 2^(-N)).
1792 *
1793 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1794 */
1795static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1796{
1797 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1798}
1799
1800u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1801{
1802 u64 _tsc = tsc;
1803 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1804
1805 if (ratio != kvm_default_tsc_scaling_ratio)
1806 _tsc = __scale_tsc(ratio, tsc);
1807
1808 return _tsc;
1809}
1810EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1811
07c1419a
HZ		 1812static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1813{
1814 u64 tsc;
1815
1816 tsc = kvm_scale_tsc(vcpu, rdtsc());
1817
1818 return target_tsc - tsc;
1819}
1820
4ba76538
HZ		 1821u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1822{
e79f245d
KA		 1823 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1824
1825 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1826}
1827EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1828
a545ab6a
LC		 1829static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1830{
326e7425 1831 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1832}
1833
b0c39dc6
VK		 1834static inline bool kvm_check_tsc_unstable(void)
1835{
1836#ifdef CONFIG_X86_64
1837 /*
1838 * TSC is marked unstable when we're running on Hyper-V,
1839 * 'TSC page' clocksource is good.
1840 */
1841 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1842 return false;
1843#endif
1844 return check_tsc_unstable();
1845}
1846
8fe8ab46 1847void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1848{
1849 struct kvm *kvm = vcpu->kvm;
f38e098f 1850 u64 offset, ns, elapsed;
99e3e30a 1851 unsigned long flags;
b48aa97e 1852 bool matched;
0d3da0d2 1853 bool already_matched;
8fe8ab46 1854 u64 data = msr->data;
c5e8ec8e 1855 bool synchronizing = false;
99e3e30a 1856
038f8c11 1857 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1858 offset = kvm_compute_tsc_offset(vcpu, data);
9285ec4c 1859 ns = ktime_get_boottime_ns();
f38e098f 1860 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1861
03ba32ca 1862 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1863 if (data == 0 && msr->host_initiated) {
1864 /*
1865 * detection of vcpu initialization -- need to sync
1866 * with other vCPUs. This particularly helps to keep
1867 * kvm_clock stable after CPU hotplug
1868 */
1869 synchronizing = true;
1870 } else {
1871 u64 tsc_exp = kvm->arch.last_tsc_write +
1872 nsec_to_cycles(vcpu, elapsed);
1873 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1874 /*
1875 * Special case: TSC write with a small delta (1 second)
1876 * of virtual cycle time against real time is
1877 * interpreted as an attempt to synchronize the CPU.
1878 */
1879 synchronizing = data < tsc_exp + tsc_hz &&
1880 data + tsc_hz > tsc_exp;
1881 }
c5e8ec8e 1882 }
f38e098f
ZA		 1883
1884 /*
5d3cb0f6
ZA		 1885 * For a reliable TSC, we can match TSC offsets, and for an unstable
1886 * TSC, we add elapsed time in this computation. We could let the
1887 * compensation code attempt to catch up if we fall behind, but
1888 * it's better to try to match offsets from the beginning.
1889 */
c5e8ec8e 1890 if (synchronizing &&
5d3cb0f6 1891 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1892 if (!kvm_check_tsc_unstable()) {
e26101b1 1893 offset = kvm->arch.cur_tsc_offset;
f38e098f 1894 } else {
857e4099 1895 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1896 data += delta;
07c1419a 1897 offset = kvm_compute_tsc_offset(vcpu, data);
f38e098f 1898 }
b48aa97e 1899 matched = true;
0d3da0d2 1900 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1901 } else {
1902 /*
1903 * We split periods of matched TSC writes into generations.
1904 * For each generation, we track the original measured
1905 * nanosecond time, offset, and write, so if TSCs are in
1906 * sync, we can match exact offset, and if not, we can match
4a969980 1907 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1908 *
1909 * These values are tracked in kvm->arch.cur_xxx variables.
1910 */
1911 kvm->arch.cur_tsc_generation++;
1912 kvm->arch.cur_tsc_nsec = ns;
1913 kvm->arch.cur_tsc_write = data;
1914 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1915 matched = false;
f38e098f 1916 }
e26101b1
ZA		 1917
1918 /*
1919 * We also track th most recent recorded KHZ, write and time to
1920 * allow the matching interval to be extended at each write.
1921 */
f38e098f
ZA		 1922 kvm->arch.last_tsc_nsec = ns;
1923 kvm->arch.last_tsc_write = data;
5d3cb0f6 1924 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1925
b183aa58 1926 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1927
1928 /* Keep track of which generation this VCPU has synchronized to */
1929 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1930 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1931 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1932
d6321d49 1933 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1934 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1935
a545ab6a 1936 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1937 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1938
1939 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1940 if (!matched) {
b48aa97e 1941 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1942 } else if (!already_matched) {
1943 kvm->arch.nr_vcpus_matched_tsc++;
1944 }
b48aa97e
MT		 1945
1946 kvm_track_tsc_matching(vcpu);
1947 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1948}
e26101b1 1949
99e3e30a
ZA		 1950EXPORT_SYMBOL_GPL(kvm_write_tsc);
1951
58ea6767
HZ		 1952static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1953 s64 adjustment)
1954{
326e7425
LS		 1955 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1956 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1957}
1958
1959static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1960{
1961 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1962 WARN_ON(adjustment < 0);
1963 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1964 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1965}
1966
d828199e
MT		 1967#ifdef CONFIG_X86_64
1968
a5a1d1c2 1969static u64 read_tsc(void)
d828199e 1970{
a5a1d1c2 1971 u64 ret = (u64)rdtsc_ordered();
03b9730b 1972 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1973
1974 if (likely(ret >= last))
1975 return ret;
1976
1977 /*
1978 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1979 * predictable (it's just a function of time and the likely is
d828199e
MT		 1980 * very likely) and there's a data dependence, so force GCC
1981 * to generate a branch instead. I don't barrier() because
1982 * we don't actually need a barrier, and if this function
1983 * ever gets inlined it will generate worse code.
1984 */
1985 asm volatile ("");
1986 return last;
1987}
1988
b0c39dc6 1989static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1990{
1991 long v;
1992 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1993 u64 tsc_pg_val;
1994
1995 switch (gtod->clock.vclock_mode) {
1996 case VCLOCK_HVCLOCK:
1997 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1998 tsc_timestamp);
1999 if (tsc_pg_val != U64_MAX) {
2000 /* TSC page valid */
2001 *mode = VCLOCK_HVCLOCK;
2002 v = (tsc_pg_val - gtod->clock.cycle_last) &
2003 gtod->clock.mask;
2004 } else {
2005 /* TSC page invalid */
2006 *mode = VCLOCK_NONE;
2007 }
2008 break;
2009 case VCLOCK_TSC:
2010 *mode = VCLOCK_TSC;
2011 *tsc_timestamp = read_tsc();
2012 v = (*tsc_timestamp - gtod->clock.cycle_last) &
2013 gtod->clock.mask;
2014 break;
2015 default:
2016 *mode = VCLOCK_NONE;
2017 }
d828199e 2018
b0c39dc6
VK		 2019 if (*mode == VCLOCK_NONE)
2020 *tsc_timestamp = v = 0;
d828199e 2021
d828199e
MT		 2022 return v * gtod->clock.mult;
2023}
2024
b0c39dc6 2025static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 2026{
cbcf2dd3 2027 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 2028 unsigned long seq;
d828199e 2029 int mode;
cbcf2dd3 2030 u64 ns;
d828199e 2031
d828199e
MT		 2032 do {
2033 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 2034 ns = gtod->nsec_base;
b0c39dc6 2035 ns += vgettsc(tsc_timestamp, &mode);
d828199e 2036 ns >>= gtod->clock.shift;
cbcf2dd3 2037 ns += gtod->boot_ns;
d828199e 2038 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 2039 *t = ns;
d828199e
MT		 2040
2041 return mode;
2042}
2043
899a31f5 2044static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 2045{
2046 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2047 unsigned long seq;
2048 int mode;
2049 u64 ns;
2050
2051 do {
2052 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 2053 ts->tv_sec = gtod->wall_time_sec;
2054 ns = gtod->nsec_base;
b0c39dc6 2055 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 2056 ns >>= gtod->clock.shift;
2057 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2058
2059 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2060 ts->tv_nsec = ns;
2061
2062 return mode;
2063}
2064
b0c39dc6
VK		 2065/* returns true if host is using TSC based clocksource */
2066static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 2067{
d828199e 2068 /* checked again under seqlock below */
b0c39dc6 2069 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 2070 return false;
2071
b0c39dc6
VK		 2072 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
2073 tsc_timestamp));
d828199e 2074}
55dd00a7 2075
b0c39dc6 2076/* returns true if host is using TSC based clocksource */
899a31f5 2077static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 2078 u64 *tsc_timestamp)
55dd00a7
MT		 2079{
2080 /* checked again under seqlock below */
b0c39dc6 2081 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 2082 return false;
2083
b0c39dc6 2084 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 2085}
d828199e
MT		 2086#endif
2087
2088/*
2089 *
b48aa97e
MT		 2090 * Assuming a stable TSC across physical CPUS, and a stable TSC
2091 * across virtual CPUs, the following condition is possible.
2092 * Each numbered line represents an event visible to both
d828199e
MT		 2093 * CPUs at the next numbered event.
2094 *
2095 * "timespecX" represents host monotonic time. "tscX" represents
2096 * RDTSC value.
2097 *
2098 * VCPU0 on CPU0 | VCPU1 on CPU1
2099 *
2100 * 1. read timespec0,tsc0
2101 * 2. | timespec1 = timespec0 + N
2102 * | tsc1 = tsc0 + M
2103 * 3. transition to guest | transition to guest
2104 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2105 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2106 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2107 *
2108 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2109 *
2110 * - ret0 < ret1
2111 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2112 * ...
2113 * - 0 < N - M => M < N
2114 *
2115 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2116 * always the case (the difference between two distinct xtime instances
2117 * might be smaller then the difference between corresponding TSC reads,
2118 * when updating guest vcpus pvclock areas).
2119 *
2120 * To avoid that problem, do not allow visibility of distinct
2121 * system_timestamp/tsc_timestamp values simultaneously: use a master
2122 * copy of host monotonic time values. Update that master copy
2123 * in lockstep.
2124 *
b48aa97e 2125 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 2126 *
2127 */
2128
2129static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2130{
2131#ifdef CONFIG_X86_64
2132 struct kvm_arch *ka = &kvm->arch;
2133 int vclock_mode;
b48aa97e
MT		 2134 bool host_tsc_clocksource, vcpus_matched;
2135
2136 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2137 atomic_read(&kvm->online_vcpus));
d828199e
MT		 2138
2139 /*
2140 * If the host uses TSC clock, then passthrough TSC as stable
2141 * to the guest.
2142 */
b48aa97e 2143 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 2144 &ka->master_kernel_ns,
2145 &ka->master_cycle_now);
2146
16a96021 2147 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2148 && !ka->backwards_tsc_observed
54750f2c 2149 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2150
d828199e
MT		 2151 if (ka->use_master_clock)
2152 atomic_set(&kvm_guest_has_master_clock, 1);
2153
2154 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2155 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2156 vcpus_matched);
d828199e
MT		 2157#endif
2158}
2159
2860c4b1
PB		 2160void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2161{
2162 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2163}
2164
2e762ff7
MT		 2165static void kvm_gen_update_masterclock(struct kvm *kvm)
2166{
2167#ifdef CONFIG_X86_64
2168 int i;
2169 struct kvm_vcpu *vcpu;
2170 struct kvm_arch *ka = &kvm->arch;
2171
2172 spin_lock(&ka->pvclock_gtod_sync_lock);
2173 kvm_make_mclock_inprogress_request(kvm);
2174 /* no guest entries from this point */
2175 pvclock_update_vm_gtod_copy(kvm);
2176
2177 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2178 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2179
2180 /* guest entries allowed */
2181 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2182 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2183
2184 spin_unlock(&ka->pvclock_gtod_sync_lock);
2185#endif
2186}
2187
e891a32e 2188u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2189{
108b249c 2190 struct kvm_arch *ka = &kvm->arch;
8b953440 2191 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2192 u64 ret;
108b249c 2193
8b953440
PB		 2194 spin_lock(&ka->pvclock_gtod_sync_lock);
2195 if (!ka->use_master_clock) {
2196 spin_unlock(&ka->pvclock_gtod_sync_lock);
9285ec4c 2197 return ktime_get_boottime_ns() + ka->kvmclock_offset;
108b249c
PB		 2198 }
2199
8b953440
PB		 2200 hv_clock.tsc_timestamp = ka->master_cycle_now;
2201 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2202 spin_unlock(&ka->pvclock_gtod_sync_lock);
2203
e2c2206a
WL		 2204 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2205 get_cpu();
2206
e70b57a6
WL		 2207 if (__this_cpu_read(cpu_tsc_khz)) {
2208 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2209 &hv_clock.tsc_shift,
2210 &hv_clock.tsc_to_system_mul);
2211 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2212 } else
9285ec4c 2213 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2214
2215 put_cpu();
2216
2217 return ret;
108b249c
PB		 2218}
2219
0d6dd2ff
PB		 2220static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2221{
2222 struct kvm_vcpu_arch *vcpu = &v->arch;
2223 struct pvclock_vcpu_time_info guest_hv_clock;
2224
4e335d9e 2225 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2226 &guest_hv_clock, sizeof(guest_hv_clock))))
2227 return;
2228
2229 /* This VCPU is paused, but it's legal for a guest to read another
2230 * VCPU's kvmclock, so we really have to follow the specification where
2231 * it says that version is odd if data is being modified, and even after
2232 * it is consistent.
2233 *
2234 * Version field updates must be kept separate. This is because
2235 * kvm_write_guest_cached might use a "rep movs" instruction, and
2236 * writes within a string instruction are weakly ordered. So there
2237 * are three writes overall.
2238 *
2239 * As a small optimization, only write the version field in the first
2240 * and third write. The vcpu->pv_time cache is still valid, because the
2241 * version field is the first in the struct.
2242 */
2243 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2244
51c4b8bb
LA		 2245 if (guest_hv_clock.version & 1)
2246 ++guest_hv_clock.version; /* first time write, random junk */
2247
0d6dd2ff 2248 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2249 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2250 &vcpu->hv_clock,
2251 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2252
2253 smp_wmb();
2254
2255 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2256 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2257
2258 if (vcpu->pvclock_set_guest_stopped_request) {
2259 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2260 vcpu->pvclock_set_guest_stopped_request = false;
2261 }
2262
2263 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2264
4e335d9e
PB		 2265 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2266 &vcpu->hv_clock,
2267 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2268
2269 smp_wmb();
2270
2271 vcpu->hv_clock.version++;
4e335d9e
PB		 2272 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2273 &vcpu->hv_clock,
2274 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2275}
2276
34c238a1 2277static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2278{
78db6a50 2279 unsigned long flags, tgt_tsc_khz;
18068523 2280 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2281 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2282 s64 kernel_ns;
d828199e 2283 u64 tsc_timestamp, host_tsc;
51d59c6b 2284 u8 pvclock_flags;
d828199e
MT		 2285 bool use_master_clock;
2286
2287 kernel_ns = 0;
2288 host_tsc = 0;
18068523 2289
d828199e
MT		 2290 /*
2291 * If the host uses TSC clock, then passthrough TSC as stable
2292 * to the guest.
2293 */
2294 spin_lock(&ka->pvclock_gtod_sync_lock);
2295 use_master_clock = ka->use_master_clock;
2296 if (use_master_clock) {
2297 host_tsc = ka->master_cycle_now;
2298 kernel_ns = ka->master_kernel_ns;
2299 }
2300 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2301
2302 /* Keep irq disabled to prevent changes to the clock */
2303 local_irq_save(flags);
78db6a50
PB		 2304 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2305 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2306 local_irq_restore(flags);
2307 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2308 return 1;
2309 }
d828199e 2310 if (!use_master_clock) {
4ea1636b 2311 host_tsc = rdtsc();
9285ec4c 2312 kernel_ns = ktime_get_boottime_ns();
d828199e
MT		 2313 }
2314
4ba76538 2315 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2316
c285545f
ZA		 2317 /*
2318 * We may have to catch up the TSC to match elapsed wall clock
2319 * time for two reasons, even if kvmclock is used.
2320 * 1) CPU could have been running below the maximum TSC rate
2321 * 2) Broken TSC compensation resets the base at each VCPU
2322 * entry to avoid unknown leaps of TSC even when running
2323 * again on the same CPU. This may cause apparent elapsed
2324 * time to disappear, and the guest to stand still or run
2325 * very slowly.
2326 */
2327 if (vcpu->tsc_catchup) {
2328 u64 tsc = compute_guest_tsc(v, kernel_ns);
2329 if (tsc > tsc_timestamp) {
f1e2b260 2330 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2331 tsc_timestamp = tsc;
2332 }
50d0a0f9
GH		 2333 }
2334
18068523
GOC		 2335 local_irq_restore(flags);
2336
0d6dd2ff 2337 /* With all the info we got, fill in the values */
18068523 2338
78db6a50
PB		 2339 if (kvm_has_tsc_control)
2340 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2341
2342 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2343 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2344 &vcpu->hv_clock.tsc_shift,
2345 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2346 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2347 }
2348
1d5f066e 2349 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2350 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2351 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2352
d828199e 2353 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2354 pvclock_flags = 0;
d828199e
MT		 2355 if (use_master_clock)
2356 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2357
78c0337a
MT		 2358 vcpu->hv_clock.flags = pvclock_flags;
2359
095cf55d
PB		 2360 if (vcpu->pv_time_enabled)
2361 kvm_setup_pvclock_page(v);
2362 if (v == kvm_get_vcpu(v->kvm, 0))
2363 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2364 return 0;
c8076604
GH		 2365}
2366
0061d53d
MT		 2367/*
2368 * kvmclock updates which are isolated to a given vcpu, such as
2369 * vcpu->cpu migration, should not allow system_timestamp from
2370 * the rest of the vcpus to remain static. Otherwise ntp frequency
2371 * correction applies to one vcpu's system_timestamp but not
2372 * the others.
2373 *
2374 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2375 * We need to rate-limit these requests though, as they can
2376 * considerably slow guests that have a large number of vcpus.
2377 * The time for a remote vcpu to update its kvmclock is bound
2378 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2379 */
2380
7e44e449
AJ		 2381#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2382
2383static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2384{
2385 int i;
7e44e449
AJ		 2386 struct delayed_work *dwork = to_delayed_work(work);
2387 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2388 kvmclock_update_work);
2389 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2390 struct kvm_vcpu *vcpu;
2391
2392 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2393 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2394 kvm_vcpu_kick(vcpu);
2395 }
2396}
2397
7e44e449
AJ		 2398static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2399{
2400 struct kvm *kvm = v->kvm;
2401
105b21bb 2402 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2403 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2404 KVMCLOCK_UPDATE_DELAY);
2405}
2406
332967a3
AJ		 2407#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2408
2409static void kvmclock_sync_fn(struct work_struct *work)
2410{
2411 struct delayed_work *dwork = to_delayed_work(work);
2412 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2413 kvmclock_sync_work);
2414 struct kvm *kvm = container_of(ka, struct kvm, arch);
2415
630994b3
MT		 2416 if (!kvmclock_periodic_sync)
2417 return;
2418
332967a3
AJ		 2419 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2420 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2421 KVMCLOCK_SYNC_PERIOD);
2422}
2423
191c8137
BP		 2424/*
2425 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2426 */
2427static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2428{
2429 /* McStatusWrEn enabled? */
2430 if (guest_cpuid_is_amd(vcpu))
2431 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2432
2433 return false;
2434}
2435
9ffd986c 2436static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2437{
890ca9ae
HY		 2438 u64 mcg_cap = vcpu->arch.mcg_cap;
2439 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2440 u32 msr = msr_info->index;
2441 u64 data = msr_info->data;
890ca9ae 2442
15c4a640 2443 switch (msr) {
15c4a640 2444 case MSR_IA32_MCG_STATUS:
890ca9ae 2445 vcpu->arch.mcg_status = data;
15c4a640 2446 break;
c7ac679c 2447 case MSR_IA32_MCG_CTL:
44883f01
PB		 2448 if (!(mcg_cap & MCG_CTL_P) &&
2449 (data || !msr_info->host_initiated))
890ca9ae
HY		 2450 return 1;
2451 if (data != 0 && data != ~(u64)0)
44883f01 2452 return 1;
890ca9ae
HY		 2453 vcpu->arch.mcg_ctl = data;
2454 break;
2455 default:
2456 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2457 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2458 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2459 /* only 0 or all 1s can be written to IA32_MCi_CTL
2460 * some Linux kernels though clear bit 10 in bank 4 to
2461 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2462 * this to avoid an uncatched #GP in the guest
2463 */
890ca9ae 2464 if ((offset & 0x3) == 0 &&
114be429 2465 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2466 return -1;
191c8137
BP		 2467
2468 /* MCi_STATUS */
9ffd986c 2469 if (!msr_info->host_initiated &&
191c8137
BP		 2470 (offset & 0x3) == 1 && data != 0) {
2471 if (!can_set_mci_status(vcpu))
2472 return -1;
2473 }
2474
890ca9ae
HY		 2475 vcpu->arch.mce_banks[offset] = data;
2476 break;
2477 }
2478 return 1;
2479 }
2480 return 0;
2481}
2482
ffde22ac
ES		 2483static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2484{
2485 struct kvm *kvm = vcpu->kvm;
2486 int lm = is_long_mode(vcpu);
2487 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2488 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2489 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2490 : kvm->arch.xen_hvm_config.blob_size_32;
2491 u32 page_num = data & ~PAGE_MASK;
2492 u64 page_addr = data & PAGE_MASK;
2493 u8 *page;
2494 int r;
2495
2496 r = -E2BIG;
2497 if (page_num >= blob_size)
2498 goto out;
2499 r = -ENOMEM;
ff5c2c03
SL		 2500 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2501 if (IS_ERR(page)) {
2502 r = PTR_ERR(page);
ffde22ac 2503 goto out;
ff5c2c03 2504 }
54bf36aa 2505 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2506 goto out_free;
2507 r = 0;
2508out_free:
2509 kfree(page);
2510out:
2511 return r;
2512}
2513
344d9588
GN		 2514static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2515{
2516 gpa_t gpa = data & ~0x3f;
2517
52a5c155
WL		 2518 /* Bits 3:5 are reserved, Should be zero */
2519 if (data & 0x38)
344d9588
GN		 2520 return 1;
2521
2522 vcpu->arch.apf.msr_val = data;
2523
2524 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2525 kvm_clear_async_pf_completion_queue(vcpu);
2526 kvm_async_pf_hash_reset(vcpu);
2527 return 0;
2528 }
2529
4e335d9e 2530 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2531 sizeof(u32)))
344d9588
GN		 2532 return 1;
2533
6adba527 2534 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2535 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2536 kvm_async_pf_wakeup_all(vcpu);
2537 return 0;
2538}
2539
12f9a48f
GC		 2540static void kvmclock_reset(struct kvm_vcpu *vcpu)
2541{
0b79459b 2542 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2543}
2544
f38a7b75
WL		 2545static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2546{
2547 ++vcpu->stat.tlb_flush;
2548 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2549}
2550
c9aaa895
GC		 2551static void record_steal_time(struct kvm_vcpu *vcpu)
2552{
2553 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2554 return;
2555
4e335d9e 2556 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2557 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2558 return;
2559
f38a7b75
WL		 2560 /*
2561 * Doing a TLB flush here, on the guest's behalf, can avoid
2562 * expensive IPIs.
2563 */
b382f44e
WL		 2564 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2565 vcpu->arch.st.steal.preempted & KVM_VCPU_FLUSH_TLB);
f38a7b75
WL		 2566 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2567 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2568
35f3fae1
WL		 2569 if (vcpu->arch.st.steal.version & 1)
2570 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2571
2572 vcpu->arch.st.steal.version += 1;
2573
4e335d9e 2574 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2575 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2576
2577 smp_wmb();
2578
c54cdf14
LC		 2579 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2580 vcpu->arch.st.last_steal;
2581 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2582
4e335d9e 2583 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2584 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2585
2586 smp_wmb();
2587
2588 vcpu->arch.st.steal.version += 1;
c9aaa895 2589
4e335d9e 2590 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2591 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2592}
2593
8fe8ab46 2594int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2595{
5753785f 2596 bool pr = false;
8fe8ab46
WA		 2597 u32 msr = msr_info->index;
2598 u64 data = msr_info->data;
5753785f 2599
15c4a640 2600 switch (msr) {
2e32b719 2601 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2602 case MSR_IA32_UCODE_WRITE:
2603 case MSR_VM_HSAVE_PA:
2604 case MSR_AMD64_PATCH_LOADER:
2605 case MSR_AMD64_BU_CFG2:
405a353a 2606 case MSR_AMD64_DC_CFG:
0e1b869f 2607 case MSR_F15H_EX_CFG:
2e32b719
BP		 2608 break;
2609
518e7b94
WL		 2610 case MSR_IA32_UCODE_REV:
2611 if (msr_info->host_initiated)
2612 vcpu->arch.microcode_version = data;
2613 break;
0cf9135b
SC		 2614 case MSR_IA32_ARCH_CAPABILITIES:
2615 if (!msr_info->host_initiated)
2616 return 1;
2617 vcpu->arch.arch_capabilities = data;
2618 break;
15c4a640 2619 case MSR_EFER:
11988499 2620 return set_efer(vcpu, msr_info);
8f1589d9
AP		 2621 case MSR_K7_HWCR:
2622 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2623 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2624 data &= ~(u64)0x8; /* ignore TLB cache disable */
191c8137
BP		 2625
2626 /* Handle McStatusWrEn */
2627 if (data == BIT_ULL(18)) {
2628 vcpu->arch.msr_hwcr = data;
2629 } else if (data != 0) {
a737f256
CD		 2630 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2631 data);
8f1589d9
AP		 2632 return 1;
2633 }
15c4a640 2634 break;
f7c6d140
AP		 2635 case MSR_FAM10H_MMIO_CONF_BASE:
2636 if (data != 0) {
a737f256
CD		 2637 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2638 "0x%llx\n", data);
f7c6d140
AP		 2639 return 1;
2640 }
15c4a640 2641 break;
b5e2fec0
AG		 2642 case MSR_IA32_DEBUGCTLMSR:
2643 if (!data) {
2644 /* We support the non-activated case already */
2645 break;
2646 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2647 /* Values other than LBR and BTF are vendor-specific,
2648 thus reserved and should throw a #GP */
2649 return 1;
2650 }
a737f256
CD		 2651 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2652 __func__, data);
b5e2fec0 2653 break;
9ba075a6 2654 case 0x200 ... 0x2ff:
ff53604b 2655 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2656 case MSR_IA32_APICBASE:
58cb628d 2657 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2658 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2659 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2660 case MSR_IA32_TSCDEADLINE:
2661 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2662 break;
ba904635 2663 case MSR_IA32_TSC_ADJUST:
d6321d49 2664 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2665 if (!msr_info->host_initiated) {
d913b904 2666 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2667 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2668 }
2669 vcpu->arch.ia32_tsc_adjust_msr = data;
2670 }
2671 break;
15c4a640 2672 case MSR_IA32_MISC_ENABLE:
511a8556
WL		 2673 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2674 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2675 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2676 return 1;
2677 vcpu->arch.ia32_misc_enable_msr = data;
2678 kvm_update_cpuid(vcpu);
2679 } else {
2680 vcpu->arch.ia32_misc_enable_msr = data;
2681 }
15c4a640 2682 break;
64d60670
PB		 2683 case MSR_IA32_SMBASE:
2684 if (!msr_info->host_initiated)
2685 return 1;
2686 vcpu->arch.smbase = data;
2687 break;
73f624f4
PB		 2688 case MSR_IA32_POWER_CTL:
2689 vcpu->arch.msr_ia32_power_ctl = data;
2690 break;
dd259935
PB		 2691 case MSR_IA32_TSC:
2692 kvm_write_tsc(vcpu, msr_info);
2693 break;
52797bf9
LA		 2694 case MSR_SMI_COUNT:
2695 if (!msr_info->host_initiated)
2696 return 1;
2697 vcpu->arch.smi_count = data;
2698 break;
11c6bffa 2699 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2700 case MSR_KVM_WALL_CLOCK:
2701 vcpu->kvm->arch.wall_clock = data;
2702 kvm_write_wall_clock(vcpu->kvm, data);
2703 break;
11c6bffa 2704 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2705 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2706 struct kvm_arch *ka = &vcpu->kvm->arch;
2707
12f9a48f 2708 kvmclock_reset(vcpu);
18068523 2709
54750f2c
MT		 2710 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2711 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2712
2713 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2714 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2715
2716 ka->boot_vcpu_runs_old_kvmclock = tmp;
2717 }
2718
18068523 2719 vcpu->arch.time = data;
0061d53d 2720 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2721
2722 /* we verify if the enable bit is set... */
2723 if (!(data & 1))
2724 break;
2725
4e335d9e 2726 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2727 &vcpu->arch.pv_time, data & ~1ULL,
2728 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2729 vcpu->arch.pv_time_enabled = false;
2730 else
2731 vcpu->arch.pv_time_enabled = true;
32cad84f 2732
18068523
GOC		 2733 break;
2734 }
344d9588
GN		 2735 case MSR_KVM_ASYNC_PF_EN:
2736 if (kvm_pv_enable_async_pf(vcpu, data))
2737 return 1;
2738 break;
c9aaa895
GC		 2739 case MSR_KVM_STEAL_TIME:
2740
2741 if (unlikely(!sched_info_on()))
2742 return 1;
2743
2744 if (data & KVM_STEAL_RESERVED_MASK)
2745 return 1;
2746
4e335d9e 2747 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2748 data & KVM_STEAL_VALID_BITS,
2749 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2750 return 1;
2751
2752 vcpu->arch.st.msr_val = data;
2753
2754 if (!(data & KVM_MSR_ENABLED))
2755 break;
2756
c9aaa895
GC		 2757 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2758
2759 break;
ae7a2a3f 2760 case MSR_KVM_PV_EOI_EN:
72bbf935 2761 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2762 return 1;
2763 break;
c9aaa895 2764
2d5ba19b
MT		 2765 case MSR_KVM_POLL_CONTROL:
2766 /* only enable bit supported */
2767 if (data & (-1ULL << 1))
2768 return 1;
2769
2770 vcpu->arch.msr_kvm_poll_control = data;
2771 break;
2772
890ca9ae
HY		 2773 case MSR_IA32_MCG_CTL:
2774 case MSR_IA32_MCG_STATUS:
81760dcc 2775 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2776 return set_msr_mce(vcpu, msr_info);
71db6023 2777
6912ac32
WH		 2778 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2779 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2780 pr = true; /* fall through */
2781 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2782 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2783 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2784 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2785
2786 if (pr || data != 0)
a737f256
CD		 2787 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2788 "0x%x data 0x%llx\n", msr, data);
5753785f 2789 break;
84e0cefa
JS		 2790 case MSR_K7_CLK_CTL:
2791 /*
2792 * Ignore all writes to this no longer documented MSR.
2793 * Writes are only relevant for old K7 processors,
2794 * all pre-dating SVM, but a recommended workaround from
4a969980 2795 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2796 * affected processor models on the command line, hence
2797 * the need to ignore the workaround.
2798 */
2799 break;
55cd8e5a 2800 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2801 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2802 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2803 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2804 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2805 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2806 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2807 return kvm_hv_set_msr_common(vcpu, msr, data,
2808 msr_info->host_initiated);
91c9c3ed 2809 case MSR_IA32_BBL_CR_CTL3:
2810 /* Drop writes to this legacy MSR -- see rdmsr
2811 * counterpart for further detail.
2812 */
fab0aa3b
EM		 2813 if (report_ignored_msrs)
2814 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2815 msr, data);
91c9c3ed 2816 break;
2b036c6b 2817 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2818 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2819 return 1;
2820 vcpu->arch.osvw.length = data;
2821 break;
2822 case MSR_AMD64_OSVW_STATUS:
d6321d49 2823 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2824 return 1;
2825 vcpu->arch.osvw.status = data;
2826 break;
db2336a8
KH		 2827 case MSR_PLATFORM_INFO:
2828 if (!msr_info->host_initiated ||
db2336a8
KH		 2829 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2830 cpuid_fault_enabled(vcpu)))
2831 return 1;
2832 vcpu->arch.msr_platform_info = data;
2833 break;
2834 case MSR_MISC_FEATURES_ENABLES:
2835 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2836 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2837 !supports_cpuid_fault(vcpu)))
2838 return 1;
2839 vcpu->arch.msr_misc_features_enables = data;
2840 break;
15c4a640 2841 default:
ffde22ac
ES		 2842 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2843 return xen_hvm_config(vcpu, data);
c6702c9d 2844 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2845 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2846 if (!ignore_msrs) {
ae0f5499 2847 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2848 msr, data);
ed85c068
AP		 2849 return 1;
2850 } else {
fab0aa3b
EM		 2851 if (report_ignored_msrs)
2852 vcpu_unimpl(vcpu,
2853 "ignored wrmsr: 0x%x data 0x%llx\n",
2854 msr, data);
ed85c068
AP		 2855 break;
2856 }
15c4a640
CO		 2857 }
2858 return 0;
2859}
2860EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2861
44883f01 2862static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2863{
2864 u64 data;
890ca9ae
HY		 2865 u64 mcg_cap = vcpu->arch.mcg_cap;
2866 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2867
2868 switch (msr) {
15c4a640
CO		 2869 case MSR_IA32_P5_MC_ADDR:
2870 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2871 data = 0;
2872 break;
15c4a640 2873 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2874 data = vcpu->arch.mcg_cap;
2875 break;
c7ac679c 2876 case MSR_IA32_MCG_CTL:
44883f01 2877 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2878 return 1;
2879 data = vcpu->arch.mcg_ctl;
2880 break;
2881 case MSR_IA32_MCG_STATUS:
2882 data = vcpu->arch.mcg_status;
2883 break;
2884 default:
2885 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2886 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2887 u32 offset = msr - MSR_IA32_MC0_CTL;
2888 data = vcpu->arch.mce_banks[offset];
2889 break;
2890 }
2891 return 1;
2892 }
2893 *pdata = data;
2894 return 0;
2895}
2896
609e36d3 2897int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2898{
609e36d3 2899 switch (msr_info->index) {
890ca9ae 2900 case MSR_IA32_PLATFORM_ID:
15c4a640 2901 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2902 case MSR_IA32_DEBUGCTLMSR:
2903 case MSR_IA32_LASTBRANCHFROMIP:
2904 case MSR_IA32_LASTBRANCHTOIP:
2905 case MSR_IA32_LASTINTFROMIP:
2906 case MSR_IA32_LASTINTTOIP:
60af2ecd 2907 case MSR_K8_SYSCFG:
3afb1121
PB		 2908 case MSR_K8_TSEG_ADDR:
2909 case MSR_K8_TSEG_MASK:
61a6bd67 2910 case MSR_VM_HSAVE_PA:
1fdbd48c 2911 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2912 case MSR_AMD64_NB_CFG:
f7c6d140 2913 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2914 case MSR_AMD64_BU_CFG2:
0c2df2a1 2915 case MSR_IA32_PERF_CTL:
405a353a 2916 case MSR_AMD64_DC_CFG:
0e1b869f 2917 case MSR_F15H_EX_CFG:
609e36d3 2918 msr_info->data = 0;
15c4a640 2919 break;
c51eb52b 2920 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2921 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2922 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2923 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2924 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2925 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2926 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2927 msr_info->data = 0;
5753785f 2928 break;
742bc670 2929 case MSR_IA32_UCODE_REV:
518e7b94 2930 msr_info->data = vcpu->arch.microcode_version;
742bc670 2931 break;
0cf9135b
SC		 2932 case MSR_IA32_ARCH_CAPABILITIES:
2933 if (!msr_info->host_initiated &&
2934 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2935 return 1;
2936 msr_info->data = vcpu->arch.arch_capabilities;
2937 break;
73f624f4
PB		 2938 case MSR_IA32_POWER_CTL:
2939 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2940 break;
dd259935
PB		 2941 case MSR_IA32_TSC:
2942 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2943 break;
9ba075a6 2944 case MSR_MTRRcap:
9ba075a6 2945 case 0x200 ... 0x2ff:
ff53604b 2946 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2947 case 0xcd: /* fsb frequency */
609e36d3 2948 msr_info->data = 3;
15c4a640 2949 break;
7b914098
JS		 2950 /*
2951 * MSR_EBC_FREQUENCY_ID
2952 * Conservative value valid for even the basic CPU models.
2953 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2954 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2955 * and 266MHz for model 3, or 4. Set Core Clock
2956 * Frequency to System Bus Frequency Ratio to 1 (bits
2957 * 31:24) even though these are only valid for CPU
2958 * models > 2, however guests may end up dividing or
2959 * multiplying by zero otherwise.
2960 */
2961 case MSR_EBC_FREQUENCY_ID:
609e36d3 2962 msr_info->data = 1 << 24;
7b914098 2963 break;
15c4a640 2964 case MSR_IA32_APICBASE:
609e36d3 2965 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2966 break;
0105d1a5 2967 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2968 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2969 break;
a3e06bbe 2970 case MSR_IA32_TSCDEADLINE:
609e36d3 2971 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2972 break;
ba904635 2973 case MSR_IA32_TSC_ADJUST:
609e36d3 2974 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2975 break;
15c4a640 2976 case MSR_IA32_MISC_ENABLE:
609e36d3 2977 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2978 break;
64d60670
PB		 2979 case MSR_IA32_SMBASE:
2980 if (!msr_info->host_initiated)
2981 return 1;
2982 msr_info->data = vcpu->arch.smbase;
15c4a640 2983 break;
52797bf9
LA		 2984 case MSR_SMI_COUNT:
2985 msr_info->data = vcpu->arch.smi_count;
2986 break;
847f0ad8
AG		 2987 case MSR_IA32_PERF_STATUS:
2988 /* TSC increment by tick */
609e36d3 2989 msr_info->data = 1000ULL;
847f0ad8 2990 /* CPU multiplier */
b0996ae4 2991 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2992 break;
15c4a640 2993 case MSR_EFER:
609e36d3 2994 msr_info->data = vcpu->arch.efer;
15c4a640 2995 break;
18068523 2996 case MSR_KVM_WALL_CLOCK:
11c6bffa 2997 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2998 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2999 break;
3000 case MSR_KVM_SYSTEM_TIME:
11c6bffa 3001 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 3002 msr_info->data = vcpu->arch.time;
18068523 3003 break;
344d9588 3004 case MSR_KVM_ASYNC_PF_EN:
609e36d3 3005 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 3006 break;
c9aaa895 3007 case MSR_KVM_STEAL_TIME:
609e36d3 3008 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 3009 break;
1d92128f 3010 case MSR_KVM_PV_EOI_EN:
609e36d3 3011 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 3012 break;
2d5ba19b
MT		 3013 case MSR_KVM_POLL_CONTROL:
3014 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3015 break;
890ca9ae
HY		 3016 case MSR_IA32_P5_MC_ADDR:
3017 case MSR_IA32_P5_MC_TYPE:
3018 case MSR_IA32_MCG_CAP:
3019 case MSR_IA32_MCG_CTL:
3020 case MSR_IA32_MCG_STATUS:
81760dcc 3021 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 3022 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3023 msr_info->host_initiated);
84e0cefa
JS		 3024 case MSR_K7_CLK_CTL:
3025 /*
3026 * Provide expected ramp-up count for K7. All other
3027 * are set to zero, indicating minimum divisors for
3028 * every field.
3029 *
3030 * This prevents guest kernels on AMD host with CPU
3031 * type 6, model 8 and higher from exploding due to
3032 * the rdmsr failing.
3033 */
609e36d3 3034 msr_info->data = 0x20000000;
84e0cefa 3035 break;
55cd8e5a 3036 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 3037 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3038 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 3039 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 3040 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3041 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3042 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 3043 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 3044 msr_info->index, &msr_info->data,
3045 msr_info->host_initiated);
55cd8e5a 3046 break;
91c9c3ed 3047 case MSR_IA32_BBL_CR_CTL3:
3048 /* This legacy MSR exists but isn't fully documented in current
3049 * silicon. It is however accessed by winxp in very narrow
3050 * scenarios where it sets bit #19, itself documented as
3051 * a "reserved" bit. Best effort attempt to source coherent
3052 * read data here should the balance of the register be
3053 * interpreted by the guest:
3054 *
3055 * L2 cache control register 3: 64GB range, 256KB size,
3056 * enabled, latency 0x1, configured
3057 */
609e36d3 3058 msr_info->data = 0xbe702111;
91c9c3ed 3059 break;
2b036c6b 3060 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 3061 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 3062 return 1;
609e36d3 3063 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 3064 break;
3065 case MSR_AMD64_OSVW_STATUS:
d6321d49 3066 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 3067 return 1;
609e36d3 3068 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 3069 break;
db2336a8 3070 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 3071 if (!msr_info->host_initiated &&
3072 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3073 return 1;
db2336a8
KH		 3074 msr_info->data = vcpu->arch.msr_platform_info;
3075 break;
3076 case MSR_MISC_FEATURES_ENABLES:
3077 msr_info->data = vcpu->arch.msr_misc_features_enables;
3078 break;
191c8137
BP		 3079 case MSR_K7_HWCR:
3080 msr_info->data = vcpu->arch.msr_hwcr;
3081 break;
15c4a640 3082 default:
c6702c9d 3083 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 3084 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 3085 if (!ignore_msrs) {
ae0f5499
BD		 3086 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3087 msr_info->index);
ed85c068
AP		 3088 return 1;
3089 } else {
fab0aa3b
EM		 3090 if (report_ignored_msrs)
3091 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3092 msr_info->index);
609e36d3 3093 msr_info->data = 0;
ed85c068
AP		 3094 }
3095 break;
15c4a640 3096 }
15c4a640
CO		 3097 return 0;
3098}
3099EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3100
313a3dc7
CO		 3101/*
3102 * Read or write a bunch of msrs. All parameters are kernel addresses.
3103 *
3104 * @return number of msrs set successfully.
3105 */
3106static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3107 struct kvm_msr_entry *entries,
3108 int (*do_msr)(struct kvm_vcpu *vcpu,
3109 unsigned index, u64 *data))
3110{
801e459a 3111 int i;
313a3dc7 3112
313a3dc7
CO		 3113 for (i = 0; i < msrs->nmsrs; ++i)
3114 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3115 break;
3116
313a3dc7
CO		 3117 return i;
3118}
3119
3120/*
3121 * Read or write a bunch of msrs. Parameters are user addresses.
3122 *
3123 * @return number of msrs set successfully.
3124 */
3125static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3126 int (*do_msr)(struct kvm_vcpu *vcpu,
3127 unsigned index, u64 *data),
3128 int writeback)
3129{
3130 struct kvm_msrs msrs;
3131 struct kvm_msr_entry *entries;
3132 int r, n;
3133 unsigned size;
3134
3135 r = -EFAULT;
0e96f31e 3136 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 3137 goto out;
3138
3139 r = -E2BIG;
3140 if (msrs.nmsrs >= MAX_IO_MSRS)
3141 goto out;
3142
313a3dc7 3143 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 3144 entries = memdup_user(user_msrs->entries, size);
3145 if (IS_ERR(entries)) {
3146 r = PTR_ERR(entries);
313a3dc7 3147 goto out;
ff5c2c03 3148 }
313a3dc7
CO		 3149
3150 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3151 if (r < 0)
3152 goto out_free;
3153
3154 r = -EFAULT;
3155 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3156 goto out_free;
3157
3158 r = n;
3159
3160out_free:
7a73c028 3161 kfree(entries);
313a3dc7
CO		 3162out:
3163 return r;
3164}
3165
4d5422ce
WL		 3166static inline bool kvm_can_mwait_in_guest(void)
3167{
3168 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 3169 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3170 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 3171}
3172
784aa3d7 3173int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 3174{
4d5422ce 3175 int r = 0;
018d00d2
ZX		 3176
3177 switch (ext) {
3178 case KVM_CAP_IRQCHIP:
3179 case KVM_CAP_HLT:
3180 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 3181 case KVM_CAP_SET_TSS_ADDR:
07716717 3182 case KVM_CAP_EXT_CPUID:
9c15bb1d 3183 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3184 case KVM_CAP_CLOCKSOURCE:
7837699f 3185 case KVM_CAP_PIT:
a28e4f5a 3186 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3187 case KVM_CAP_MP_STATE:
ed848624 3188 case KVM_CAP_SYNC_MMU:
a355c85c 3189 case KVM_CAP_USER_NMI:
52d939a0 3190 case KVM_CAP_REINJECT_CONTROL:
4925663a 3191 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3192 case KVM_CAP_IOEVENTFD:
f848a5a8 3193 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3194 case KVM_CAP_PIT2:
e9f42757 3195 case KVM_CAP_PIT_STATE2:
b927a3ce 3196 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3197 case KVM_CAP_XEN_HVM:
3cfc3092 3198 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3199 case KVM_CAP_HYPERV:
10388a07 3200 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3201 case KVM_CAP_HYPERV_SPIN:
5c919412 3202 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3203 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3204 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3205 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3206 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3207 case KVM_CAP_HYPERV_SEND_IPI:
2bc39970 3208 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3209 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3210 case KVM_CAP_DEBUGREGS:
d2be1651 3211 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3212 case KVM_CAP_XSAVE:
344d9588 3213 case KVM_CAP_ASYNC_PF:
92a1f12d 3214 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3215 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3216 case KVM_CAP_READONLY_MEM:
5f66b620 3217 case KVM_CAP_HYPERV_TIME:
100943c5 3218 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3219 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3220 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3221 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3222 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3223 case KVM_CAP_IMMEDIATE_EXIT:
66bb8a06 3224 case KVM_CAP_PMU_EVENT_FILTER:
801e459a 3225 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3226 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3227 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3228 r = 1;
3229 break;
01643c51
KH		 3230 case KVM_CAP_SYNC_REGS:
3231 r = KVM_SYNC_X86_VALID_FIELDS;
3232 break;
e3fd9a93
PB		 3233 case KVM_CAP_ADJUST_CLOCK:
3234 r = KVM_CLOCK_TSC_STABLE;
3235 break;
4d5422ce 3236 case KVM_CAP_X86_DISABLE_EXITS:
b5170063
WL		 3237 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3238 KVM_X86_DISABLE_EXITS_CSTATE;
4d5422ce
WL		 3239 if(kvm_can_mwait_in_guest())
3240 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3241 break;
6d396b55
PB		 3242 case KVM_CAP_X86_SMM:
3243 /* SMBASE is usually relocated above 1M on modern chipsets,
3244 * and SMM handlers might indeed rely on 4G segment limits,
3245 * so do not report SMM to be available if real mode is
3246 * emulated via vm86 mode. Still, do not go to great lengths
3247 * to avoid userspace's usage of the feature, because it is a
3248 * fringe case that is not enabled except via specific settings
3249 * of the module parameters.
3250 */
bc226f07 3251 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3252 break;
774ead3a
AK		 3253 case KVM_CAP_VAPIC:
3254 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3255 break;
f725230a 3256 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3257 r = KVM_SOFT_MAX_VCPUS;
3258 break;
3259 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3260 r = KVM_MAX_VCPUS;
3261 break;
a86cb413
TH		 3262 case KVM_CAP_MAX_VCPU_ID:
3263 r = KVM_MAX_VCPU_ID;
3264 break;
a68a6a72
MT		 3265 case KVM_CAP_PV_MMU: /* obsolete */
3266 r = 0;
2f333bcb 3267 break;
890ca9ae
HY		 3268 case KVM_CAP_MCE:
3269 r = KVM_MAX_MCE_BANKS;
3270 break;
2d5b5a66 3271 case KVM_CAP_XCRS:
d366bf7e 3272 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3273 break;
92a1f12d
JR		 3274 case KVM_CAP_TSC_CONTROL:
3275 r = kvm_has_tsc_control;
3276 break;
37131313
RK		 3277 case KVM_CAP_X2APIC_API:
3278 r = KVM_X2APIC_API_VALID_FLAGS;
3279 break;
8fcc4b59
JM		 3280 case KVM_CAP_NESTED_STATE:
3281 r = kvm_x86_ops->get_nested_state ?
be43c440 3282 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3283 break;
344c6c80 3284 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5a0165f6
VK		 3285 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3286 break;
3287 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3288 r = kvm_x86_ops->nested_enable_evmcs != NULL;
344c6c80 3289 break;
018d00d2 3290 default:
018d00d2
ZX		 3291 break;
3292 }
3293 return r;
3294
3295}
3296
043405e1
CO		 3297long kvm_arch_dev_ioctl(struct file *filp,
3298 unsigned int ioctl, unsigned long arg)
3299{
3300 void __user *argp = (void __user *)arg;
3301 long r;
3302
3303 switch (ioctl) {
3304 case KVM_GET_MSR_INDEX_LIST: {
3305 struct kvm_msr_list __user *user_msr_list = argp;
3306 struct kvm_msr_list msr_list;
3307 unsigned n;
3308
3309 r = -EFAULT;
0e96f31e 3310 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3311 goto out;
3312 n = msr_list.nmsrs;
62ef68bb 3313 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3314 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3315 goto out;
3316 r = -E2BIG;
e125e7b6 3317 if (n < msr_list.nmsrs)
043405e1
CO		 3318 goto out;
3319 r = -EFAULT;
3320 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3321 num_msrs_to_save * sizeof(u32)))
3322 goto out;
e125e7b6 3323 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3324 &emulated_msrs,
62ef68bb 3325 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3326 goto out;
3327 r = 0;
3328 break;
3329 }
9c15bb1d
BP		 3330 case KVM_GET_SUPPORTED_CPUID:
3331 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3332 struct kvm_cpuid2 __user *cpuid_arg = argp;
3333 struct kvm_cpuid2 cpuid;
3334
3335 r = -EFAULT;
0e96f31e 3336 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3337 goto out;
9c15bb1d
BP		 3338
3339 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3340 ioctl);
674eea0f
AK		 3341 if (r)
3342 goto out;
3343
3344 r = -EFAULT;
0e96f31e 3345 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3346 goto out;
3347 r = 0;
3348 break;
3349 }
890ca9ae 3350 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3351 r = -EFAULT;
c45dcc71
AR		 3352 if (copy_to_user(argp, &kvm_mce_cap_supported,
3353 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3354 goto out;
3355 r = 0;
3356 break;
801e459a
TL		 3357 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3358 struct kvm_msr_list __user *user_msr_list = argp;
3359 struct kvm_msr_list msr_list;
3360 unsigned int n;
3361
3362 r = -EFAULT;
3363 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3364 goto out;
3365 n = msr_list.nmsrs;
3366 msr_list.nmsrs = num_msr_based_features;
3367 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3368 goto out;
3369 r = -E2BIG;
3370 if (n < msr_list.nmsrs)
3371 goto out;
3372 r = -EFAULT;
3373 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3374 num_msr_based_features * sizeof(u32)))
3375 goto out;
3376 r = 0;
3377 break;
3378 }
3379 case KVM_GET_MSRS:
3380 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3381 break;
890ca9ae 3382 }
043405e1
CO		 3383 default:
3384 r = -EINVAL;
3385 }
3386out:
3387 return r;
3388}
3389
f5f48ee1
SY		 3390static void wbinvd_ipi(void *garbage)
3391{
3392 wbinvd();
3393}
3394
3395static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3396{
e0f0bbc5 3397 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3398}
3399
313a3dc7
CO		 3400void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3401{
f5f48ee1
SY		 3402 /* Address WBINVD may be executed by guest */
3403 if (need_emulate_wbinvd(vcpu)) {
3404 if (kvm_x86_ops->has_wbinvd_exit())
3405 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3406 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3407 smp_call_function_single(vcpu->cpu,
3408 wbinvd_ipi, NULL, 1);
3409 }
3410
313a3dc7 3411 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3412
e7517324
WL		 3413 fpregs_assert_state_consistent();
3414 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3415 switch_fpu_return();
3416
0dd6a6ed
ZA		 3417 /* Apply any externally detected TSC adjustments (due to suspend) */
3418 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3419 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3420 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3421 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3422 }
8f6055cb 3423
b0c39dc6 3424 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3425 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3426 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3427 if (tsc_delta < 0)
3428 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3429
b0c39dc6 3430 if (kvm_check_tsc_unstable()) {
07c1419a 3431 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3432 vcpu->arch.last_guest_tsc);
a545ab6a 3433 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3434 vcpu->arch.tsc_catchup = 1;
c285545f 3435 }
a749e247
PB		 3436
3437 if (kvm_lapic_hv_timer_in_use(vcpu))
3438 kvm_lapic_restart_hv_timer(vcpu);
3439
d98d07ca
MT		 3440 /*
3441 * On a host with synchronized TSC, there is no need to update
3442 * kvmclock on vcpu->cpu migration
3443 */
3444 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3445 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3446 if (vcpu->cpu != cpu)
1bd2009e 3447 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3448 vcpu->cpu = cpu;
6b7d7e76 3449 }
c9aaa895 3450
c9aaa895 3451 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3452}
3453
0b9f6c46
PX		 3454static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3455{
3456 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3457 return;
3458
fa55eedd 3459 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3460
4e335d9e 3461 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3462 &vcpu->arch.st.steal.preempted,
3463 offsetof(struct kvm_steal_time, preempted),
3464 sizeof(vcpu->arch.st.steal.preempted));
3465}
3466
313a3dc7
CO		 3467void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3468{
cc0d907c 3469 int idx;
de63ad4c
LM		 3470
3471 if (vcpu->preempted)
3472 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3473
931f261b
AA		 3474 /*
3475 * Disable page faults because we're in atomic context here.
3476 * kvm_write_guest_offset_cached() would call might_fault()
3477 * that relies on pagefault_disable() to tell if there's a
3478 * bug. NOTE: the write to guest memory may not go through if
3479 * during postcopy live migration or if there's heavy guest
3480 * paging.
3481 */
3482 pagefault_disable();
cc0d907c
AA		 3483 /*
3484 * kvm_memslots() will be called by
3485 * kvm_write_guest_offset_cached() so take the srcu lock.
3486 */
3487 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3488 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3489 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3490 pagefault_enable();
02daab21 3491 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3492 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3493 /*
f9dcf08e
RK		 3494 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3495 * on every vmexit, but if not, we might have a stale dr6 from the
3496 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3497 */
f9dcf08e 3498 set_debugreg(0, 6);
313a3dc7
CO		 3499}
3500
313a3dc7
CO		 3501static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3502 struct kvm_lapic_state *s)
3503{
fa59cc00 3504 if (vcpu->arch.apicv_active)
d62caabb
AS		 3505 kvm_x86_ops->sync_pir_to_irr(vcpu);
3506
a92e2543 3507 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3508}
3509
3510static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3511 struct kvm_lapic_state *s)
3512{
a92e2543
RK		 3513 int r;
3514
3515 r = kvm_apic_set_state(vcpu, s);
3516 if (r)
3517 return r;
cb142eb7 3518 update_cr8_intercept(vcpu);
313a3dc7
CO		 3519
3520 return 0;
3521}
3522
127a457a
MG		 3523static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3524{
3525 return (!lapic_in_kernel(vcpu) ||
3526 kvm_apic_accept_pic_intr(vcpu));
3527}
3528
782d422b
MG		 3529/*
3530 * if userspace requested an interrupt window, check that the
3531 * interrupt window is open.
3532 *
3533 * No need to exit to userspace if we already have an interrupt queued.
3534 */
3535static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3536{
3537 return kvm_arch_interrupt_allowed(vcpu) &&
3538 !kvm_cpu_has_interrupt(vcpu) &&
3539 !kvm_event_needs_reinjection(vcpu) &&
3540 kvm_cpu_accept_dm_intr(vcpu);
3541}
3542
f77bc6a4
ZX		 3543static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3544 struct kvm_interrupt *irq)
3545{
02cdb50f 3546 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3547 return -EINVAL;
1c1a9ce9
SR		 3548
3549 if (!irqchip_in_kernel(vcpu->kvm)) {
3550 kvm_queue_interrupt(vcpu, irq->irq, false);
3551 kvm_make_request(KVM_REQ_EVENT, vcpu);
3552 return 0;
3553 }
3554
3555 /*
3556 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3557 * fail for in-kernel 8259.
3558 */
3559 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3560 return -ENXIO;
f77bc6a4 3561
1c1a9ce9
SR		 3562 if (vcpu->arch.pending_external_vector != -1)
3563 return -EEXIST;
f77bc6a4 3564
1c1a9ce9 3565 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3566 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3567 return 0;
3568}
3569
c4abb7c9
JK		 3570static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3571{
c4abb7c9 3572 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3573
3574 return 0;
3575}
3576
f077825a
PB		 3577static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3578{
64d60670
PB		 3579 kvm_make_request(KVM_REQ_SMI, vcpu);
3580
f077825a
PB		 3581 return 0;
3582}
3583
b209749f
AK		 3584static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3585 struct kvm_tpr_access_ctl *tac)
3586{
3587 if (tac->flags)
3588 return -EINVAL;
3589 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3590 return 0;
3591}
3592
890ca9ae
HY		 3593static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3594 u64 mcg_cap)
3595{
3596 int r;
3597 unsigned bank_num = mcg_cap & 0xff, bank;
3598
3599 r = -EINVAL;
a9e38c3e 3600 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3601 goto out;
c45dcc71 3602 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3603 goto out;
3604 r = 0;
3605 vcpu->arch.mcg_cap = mcg_cap;
3606 /* Init IA32_MCG_CTL to all 1s */
3607 if (mcg_cap & MCG_CTL_P)
3608 vcpu->arch.mcg_ctl = ~(u64)0;
3609 /* Init IA32_MCi_CTL to all 1s */
3610 for (bank = 0; bank < bank_num; bank++)
3611 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71 3612
92735b1b 3613 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3614out:
3615 return r;
3616}
3617
3618static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3619 struct kvm_x86_mce *mce)
3620{
3621 u64 mcg_cap = vcpu->arch.mcg_cap;
3622 unsigned bank_num = mcg_cap & 0xff;
3623 u64 *banks = vcpu->arch.mce_banks;
3624
3625 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3626 return -EINVAL;
3627 /*
3628 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3629 * reporting is disabled
3630 */
3631 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3632 vcpu->arch.mcg_ctl != ~(u64)0)
3633 return 0;
3634 banks += 4 * mce->bank;
3635 /*
3636 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3637 * reporting is disabled for the bank
3638 */
3639 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3640 return 0;
3641 if (mce->status & MCI_STATUS_UC) {
3642 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3643 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3644 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3645 return 0;
3646 }
3647 if (banks[1] & MCI_STATUS_VAL)
3648 mce->status |= MCI_STATUS_OVER;
3649 banks[2] = mce->addr;
3650 banks[3] = mce->misc;
3651 vcpu->arch.mcg_status = mce->mcg_status;
3652 banks[1] = mce->status;
3653 kvm_queue_exception(vcpu, MC_VECTOR);
3654 } else if (!(banks[1] & MCI_STATUS_VAL)
3655 || !(banks[1] & MCI_STATUS_UC)) {
3656 if (banks[1] & MCI_STATUS_VAL)
3657 mce->status |= MCI_STATUS_OVER;
3658 banks[2] = mce->addr;
3659 banks[3] = mce->misc;
3660 banks[1] = mce->status;
3661 } else
3662 banks[1] |= MCI_STATUS_OVER;
3663 return 0;
3664}
3665
3cfc3092
JK		 3666static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3667 struct kvm_vcpu_events *events)
3668{
7460fb4a 3669 process_nmi(vcpu);
59073aaf 3670
664f8e26 3671 /*
59073aaf
JM		 3672 * The API doesn't provide the instruction length for software
3673 * exceptions, so don't report them. As long as the guest RIP
3674 * isn't advanced, we should expect to encounter the exception
3675 * again.
664f8e26 3676 */
59073aaf
JM		 3677 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3678 events->exception.injected = 0;
3679 events->exception.pending = 0;
3680 } else {
3681 events->exception.injected = vcpu->arch.exception.injected;
3682 events->exception.pending = vcpu->arch.exception.pending;
3683 /*
3684 * For ABI compatibility, deliberately conflate
3685 * pending and injected exceptions when
3686 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3687 */
3688 if (!vcpu->kvm->arch.exception_payload_enabled)
3689 events->exception.injected |=
3690 vcpu->arch.exception.pending;
3691 }
3cfc3092
JK		 3692 events->exception.nr = vcpu->arch.exception.nr;
3693 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3694 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3695 events->exception_has_payload = vcpu->arch.exception.has_payload;
3696 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3697
03b82a30 3698 events->interrupt.injected =
04140b41 3699 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3700 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3701 events->interrupt.soft = 0;
37ccdcbe 3702 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3703
3704 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3705 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3706 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3707 events->nmi.pad = 0;
3cfc3092 3708
66450a21 3709 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3710
f077825a
PB		 3711 events->smi.smm = is_smm(vcpu);
3712 events->smi.pending = vcpu->arch.smi_pending;
3713 events->smi.smm_inside_nmi =
3714 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3715 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3716
dab4b911 3717 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3718 | KVM_VCPUEVENT_VALID_SHADOW
3719 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3720 if (vcpu->kvm->arch.exception_payload_enabled)
3721 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3722
97e69aa6 3723 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3724}
3725
c5833c7a 3726static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3727
3cfc3092
JK		 3728static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3729 struct kvm_vcpu_events *events)
3730{
dab4b911 3731 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3732 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3733 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3734 | KVM_VCPUEVENT_VALID_SMM
3735 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3736 return -EINVAL;
3737
59073aaf
JM		 3738 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3739 if (!vcpu->kvm->arch.exception_payload_enabled)
3740 return -EINVAL;
3741 if (events->exception.pending)
3742 events->exception.injected = 0;
3743 else
3744 events->exception_has_payload = 0;
3745 } else {
3746 events->exception.pending = 0;
3747 events->exception_has_payload = 0;
3748 }
3749
3750 if ((events->exception.injected || events->exception.pending) &&
3751 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3752 return -EINVAL;
3753
28bf2888
DH		 3754 /* INITs are latched while in SMM */
3755 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3756 (events->smi.smm || events->smi.pending) &&
3757 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3758 return -EINVAL;
3759
7460fb4a 3760 process_nmi(vcpu);
59073aaf
JM		 3761 vcpu->arch.exception.injected = events->exception.injected;
3762 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3763 vcpu->arch.exception.nr = events->exception.nr;
3764 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3765 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3766 vcpu->arch.exception.has_payload = events->exception_has_payload;
3767 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3768
04140b41 3769 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3770 vcpu->arch.interrupt.nr = events->interrupt.nr;
3771 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3772 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3773 kvm_x86_ops->set_interrupt_shadow(vcpu,
3774 events->interrupt.shadow);
3cfc3092
JK		 3775
3776 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3777 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3778 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3779 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3780
66450a21 3781 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3782 lapic_in_kernel(vcpu))
66450a21 3783 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3784
f077825a 3785 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3786 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3787 if (events->smi.smm)
3788 vcpu->arch.hflags |= HF_SMM_MASK;
3789 else
3790 vcpu->arch.hflags &= ~HF_SMM_MASK;
3791 kvm_smm_changed(vcpu);
3792 }
6ef4e07e 3793
f077825a 3794 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3795
3796 if (events->smi.smm) {
3797 if (events->smi.smm_inside_nmi)
3798 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3799 else
f4ef1910
WL		 3800 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3801 if (lapic_in_kernel(vcpu)) {
3802 if (events->smi.latched_init)
3803 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3804 else
3805 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3806 }
f077825a
PB		 3807 }
3808 }
3809
3842d135
AK		 3810 kvm_make_request(KVM_REQ_EVENT, vcpu);
3811
3cfc3092
JK		 3812 return 0;
3813}
3814
a1efbe77
JK		 3815static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3816 struct kvm_debugregs *dbgregs)
3817{
73aaf249
JK		 3818 unsigned long val;
3819
a1efbe77 3820 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3821 kvm_get_dr(vcpu, 6, &val);
73aaf249 3822 dbgregs->dr6 = val;
a1efbe77
JK		 3823 dbgregs->dr7 = vcpu->arch.dr7;
3824 dbgregs->flags = 0;
97e69aa6 3825 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3826}
3827
3828static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3829 struct kvm_debugregs *dbgregs)
3830{
3831 if (dbgregs->flags)
3832 return -EINVAL;
3833
d14bdb55
PB		 3834 if (dbgregs->dr6 & ~0xffffffffull)
3835 return -EINVAL;
3836 if (dbgregs->dr7 & ~0xffffffffull)
3837 return -EINVAL;
3838
a1efbe77 3839 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3840 kvm_update_dr0123(vcpu);
a1efbe77 3841 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3842 kvm_update_dr6(vcpu);
a1efbe77 3843 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3844 kvm_update_dr7(vcpu);
a1efbe77 3845
a1efbe77
JK		 3846 return 0;
3847}
3848
df1daba7
PB		 3849#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3850
3851static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3852{
b666a4b6 3853 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3854 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3855 u64 valid;
3856
3857 /*
3858 * Copy legacy XSAVE area, to avoid complications with CPUID
3859 * leaves 0 and 1 in the loop below.
3860 */
3861 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3862
3863 /* Set XSTATE_BV */
00c87e9a 3864 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3865 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3866
3867 /*
3868 * Copy each region from the possibly compacted offset to the
3869 * non-compacted offset.
3870 */
d91cab78 3871 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3872 while (valid) {
abd16d68
SAS		 3873 u64 xfeature_mask = valid & -valid;
3874 int xfeature_nr = fls64(xfeature_mask) - 1;
3875 void *src = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3876
3877 if (src) {
3878 u32 size, offset, ecx, edx;
abd16d68 3879 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3880 &size, &offset, &ecx, &edx);
abd16d68 3881 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3882 memcpy(dest + offset, &vcpu->arch.pkru,
3883 sizeof(vcpu->arch.pkru));
3884 else
3885 memcpy(dest + offset, src, size);
3886
df1daba7
PB		 3887 }
3888
abd16d68 3889 valid -= xfeature_mask;
df1daba7
PB		 3890 }
3891}
3892
3893static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3894{
b666a4b6 3895 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3896 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3897 u64 valid;
3898
3899 /*
3900 * Copy legacy XSAVE area, to avoid complications with CPUID
3901 * leaves 0 and 1 in the loop below.
3902 */
3903 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3904
3905 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3906 xsave->header.xfeatures = xstate_bv;
782511b0 3907 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3908 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3909
3910 /*
3911 * Copy each region from the non-compacted offset to the
3912 * possibly compacted offset.
3913 */
d91cab78 3914 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3915 while (valid) {
abd16d68
SAS		 3916 u64 xfeature_mask = valid & -valid;
3917 int xfeature_nr = fls64(xfeature_mask) - 1;
3918 void *dest = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3919
3920 if (dest) {
3921 u32 size, offset, ecx, edx;
abd16d68 3922 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3923 &size, &offset, &ecx, &edx);
abd16d68 3924 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3925 memcpy(&vcpu->arch.pkru, src + offset,
3926 sizeof(vcpu->arch.pkru));
3927 else
3928 memcpy(dest, src + offset, size);
ee4100da 3929 }
df1daba7 3930
abd16d68 3931 valid -= xfeature_mask;
df1daba7
PB		 3932 }
3933}
3934
2d5b5a66
SY		 3935static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3936 struct kvm_xsave *guest_xsave)
3937{
d366bf7e 3938 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3939 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3940 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3941 } else {
2d5b5a66 3942 memcpy(guest_xsave->region,
b666a4b6 3943 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3944 sizeof(struct fxregs_state));
2d5b5a66 3945 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3946 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3947 }
3948}
3949
a575813b
WL		 3950#define XSAVE_MXCSR_OFFSET 24
3951
2d5b5a66
SY		 3952static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3953 struct kvm_xsave *guest_xsave)
3954{
3955 u64 xstate_bv =
3956 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3957 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3958
d366bf7e 3959 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3960 /*
3961 * Here we allow setting states that are not present in
3962 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3963 * with old userspace.
3964 */
a575813b
WL		 3965 if (xstate_bv & ~kvm_supported_xcr0() ||
3966 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3967 return -EINVAL;
df1daba7 3968 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3969 } else {
a575813b
WL		 3970 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3971 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3972 return -EINVAL;
b666a4b6 3973 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3974 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3975 }
3976 return 0;
3977}
3978
3979static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3980 struct kvm_xcrs *guest_xcrs)
3981{
d366bf7e 3982 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3983 guest_xcrs->nr_xcrs = 0;
3984 return;
3985 }
3986
3987 guest_xcrs->nr_xcrs = 1;
3988 guest_xcrs->flags = 0;
3989 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3990 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3991}
3992
3993static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3994 struct kvm_xcrs *guest_xcrs)
3995{
3996 int i, r = 0;
3997
d366bf7e 3998 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3999 return -EINVAL;
4000
4001 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4002 return -EINVAL;
4003
4004 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4005 /* Only support XCR0 currently */
c67a04cb 4006 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 4007 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 4008 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 4009 break;
4010 }
4011 if (r)
4012 r = -EINVAL;
4013 return r;
4014}
4015
1c0b28c2
EM		 4016/*
4017 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4018 * stopped by the hypervisor. This function will be called from the host only.
4019 * EINVAL is returned when the host attempts to set the flag for a guest that
4020 * does not support pv clocks.
4021 */
4022static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4023{
0b79459b 4024 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 4025 return -EINVAL;
51d59c6b 4026 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 4027 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4028 return 0;
4029}
4030
5c919412
AS		 4031static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4032 struct kvm_enable_cap *cap)
4033{
57b119da
VK		 4034 int r;
4035 uint16_t vmcs_version;
4036 void __user *user_ptr;
4037
5c919412
AS		 4038 if (cap->flags)
4039 return -EINVAL;
4040
4041 switch (cap->cap) {
efc479e6
RK		 4042 case KVM_CAP_HYPERV_SYNIC2:
4043 if (cap->args[0])
4044 return -EINVAL;
b2869f28
GS		 4045 /* fall through */
4046
5c919412 4047 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 4048 if (!irqchip_in_kernel(vcpu->kvm))
4049 return -EINVAL;
efc479e6
RK		 4050 return kvm_hv_activate_synic(vcpu, cap->cap ==
4051 KVM_CAP_HYPERV_SYNIC2);
57b119da 4052 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 4053 if (!kvm_x86_ops->nested_enable_evmcs)
4054 return -ENOTTY;
57b119da
VK		 4055 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4056 if (!r) {
4057 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4058 if (copy_to_user(user_ptr, &vmcs_version,
4059 sizeof(vmcs_version)))
4060 r = -EFAULT;
4061 }
4062 return r;
344c6c80
TL		 4063 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4064 if (!kvm_x86_ops->enable_direct_tlbflush)
4065 return -ENOTTY;
4066
4067 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
57b119da 4068
5c919412
AS		 4069 default:
4070 return -EINVAL;
4071 }
4072}
4073
313a3dc7
CO		 4074long kvm_arch_vcpu_ioctl(struct file *filp,
4075 unsigned int ioctl, unsigned long arg)
4076{
4077 struct kvm_vcpu *vcpu = filp->private_data;
4078 void __user *argp = (void __user *)arg;
4079 int r;
d1ac91d8
AK		 4080 union {
4081 struct kvm_lapic_state *lapic;
4082 struct kvm_xsave *xsave;
4083 struct kvm_xcrs *xcrs;
4084 void *buffer;
4085 } u;
4086
9b062471
CD		 4087 vcpu_load(vcpu);
4088
d1ac91d8 4089 u.buffer = NULL;
313a3dc7
CO		 4090 switch (ioctl) {
4091 case KVM_GET_LAPIC: {
2204ae3c 4092 r = -EINVAL;
bce87cce 4093 if (!lapic_in_kernel(vcpu))
2204ae3c 4094 goto out;
254272ce
BG		 4095 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4096 GFP_KERNEL_ACCOUNT);
313a3dc7 4097
b772ff36 4098 r = -ENOMEM;
d1ac91d8 4099 if (!u.lapic)
b772ff36 4100 goto out;
d1ac91d8 4101 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 4102 if (r)
4103 goto out;
4104 r = -EFAULT;
d1ac91d8 4105 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 4106 goto out;
4107 r = 0;
4108 break;
4109 }
4110 case KVM_SET_LAPIC: {
2204ae3c 4111 r = -EINVAL;
bce87cce 4112 if (!lapic_in_kernel(vcpu))
2204ae3c 4113 goto out;
ff5c2c03 4114 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 4115 if (IS_ERR(u.lapic)) {
4116 r = PTR_ERR(u.lapic);
4117 goto out_nofree;
4118 }
ff5c2c03 4119
d1ac91d8 4120 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 4121 break;
4122 }
f77bc6a4
ZX		 4123 case KVM_INTERRUPT: {
4124 struct kvm_interrupt irq;
4125
4126 r = -EFAULT;
0e96f31e 4127 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 4128 goto out;
4129 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 4130 break;
4131 }
c4abb7c9
JK		 4132 case KVM_NMI: {
4133 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 4134 break;
4135 }
f077825a
PB		 4136 case KVM_SMI: {
4137 r = kvm_vcpu_ioctl_smi(vcpu);
4138 break;
4139 }
313a3dc7
CO		 4140 case KVM_SET_CPUID: {
4141 struct kvm_cpuid __user *cpuid_arg = argp;
4142 struct kvm_cpuid cpuid;
4143
4144 r = -EFAULT;
0e96f31e 4145 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 4146 goto out;
4147 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 4148 break;
4149 }
07716717
DK		 4150 case KVM_SET_CPUID2: {
4151 struct kvm_cpuid2 __user *cpuid_arg = argp;
4152 struct kvm_cpuid2 cpuid;
4153
4154 r = -EFAULT;
0e96f31e 4155 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4156 goto out;
4157 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 4158 cpuid_arg->entries);
07716717
DK		 4159 break;
4160 }
4161 case KVM_GET_CPUID2: {
4162 struct kvm_cpuid2 __user *cpuid_arg = argp;
4163 struct kvm_cpuid2 cpuid;
4164
4165 r = -EFAULT;
0e96f31e 4166 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4167 goto out;
4168 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 4169 cpuid_arg->entries);
07716717
DK		 4170 if (r)
4171 goto out;
4172 r = -EFAULT;
0e96f31e 4173 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 4174 goto out;
4175 r = 0;
4176 break;
4177 }
801e459a
TL		 4178 case KVM_GET_MSRS: {
4179 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 4180 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 4181 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4182 break;
801e459a
TL		 4183 }
4184 case KVM_SET_MSRS: {
4185 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 4186 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 4187 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4188 break;
801e459a 4189 }
b209749f
AK		 4190 case KVM_TPR_ACCESS_REPORTING: {
4191 struct kvm_tpr_access_ctl tac;
4192
4193 r = -EFAULT;
0e96f31e 4194 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 4195 goto out;
4196 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4197 if (r)
4198 goto out;
4199 r = -EFAULT;
0e96f31e 4200 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4201 goto out;
4202 r = 0;
4203 break;
4204 };
b93463aa
AK		 4205 case KVM_SET_VAPIC_ADDR: {
4206 struct kvm_vapic_addr va;
7301d6ab 4207 int idx;
b93463aa
AK		 4208
4209 r = -EINVAL;
35754c98 4210 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4211 goto out;
4212 r = -EFAULT;
0e96f31e 4213 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4214 goto out;
7301d6ab 4215 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4216 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4217 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4218 break;
4219 }
890ca9ae
HY		 4220 case KVM_X86_SETUP_MCE: {
4221 u64 mcg_cap;
4222
4223 r = -EFAULT;
0e96f31e 4224 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4225 goto out;
4226 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4227 break;
4228 }
4229 case KVM_X86_SET_MCE: {
4230 struct kvm_x86_mce mce;
4231
4232 r = -EFAULT;
0e96f31e 4233 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4234 goto out;
4235 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4236 break;
4237 }
3cfc3092
JK		 4238 case KVM_GET_VCPU_EVENTS: {
4239 struct kvm_vcpu_events events;
4240
4241 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4242
4243 r = -EFAULT;
4244 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4245 break;
4246 r = 0;
4247 break;
4248 }
4249 case KVM_SET_VCPU_EVENTS: {
4250 struct kvm_vcpu_events events;
4251
4252 r = -EFAULT;
4253 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4254 break;
4255
4256 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4257 break;
4258 }
a1efbe77
JK		 4259 case KVM_GET_DEBUGREGS: {
4260 struct kvm_debugregs dbgregs;
4261
4262 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4263
4264 r = -EFAULT;
4265 if (copy_to_user(argp, &dbgregs,
4266 sizeof(struct kvm_debugregs)))
4267 break;
4268 r = 0;
4269 break;
4270 }
4271 case KVM_SET_DEBUGREGS: {
4272 struct kvm_debugregs dbgregs;
4273
4274 r = -EFAULT;
4275 if (copy_from_user(&dbgregs, argp,
4276 sizeof(struct kvm_debugregs)))
4277 break;
4278
4279 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4280 break;
4281 }
2d5b5a66 4282 case KVM_GET_XSAVE: {
254272ce 4283 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4284 r = -ENOMEM;
d1ac91d8 4285 if (!u.xsave)
2d5b5a66
SY		 4286 break;
4287
d1ac91d8 4288 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4289
4290 r = -EFAULT;
d1ac91d8 4291 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4292 break;
4293 r = 0;
4294 break;
4295 }
4296 case KVM_SET_XSAVE: {
ff5c2c03 4297 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4298 if (IS_ERR(u.xsave)) {
4299 r = PTR_ERR(u.xsave);
4300 goto out_nofree;
4301 }
2d5b5a66 4302
d1ac91d8 4303 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4304 break;
4305 }
4306 case KVM_GET_XCRS: {
254272ce 4307 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4308 r = -ENOMEM;
d1ac91d8 4309 if (!u.xcrs)
2d5b5a66
SY		 4310 break;
4311
d1ac91d8 4312 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4313
4314 r = -EFAULT;
d1ac91d8 4315 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4316 sizeof(struct kvm_xcrs)))
4317 break;
4318 r = 0;
4319 break;
4320 }
4321 case KVM_SET_XCRS: {
ff5c2c03 4322 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4323 if (IS_ERR(u.xcrs)) {
4324 r = PTR_ERR(u.xcrs);
4325 goto out_nofree;
4326 }
2d5b5a66 4327
d1ac91d8 4328 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4329 break;
4330 }
92a1f12d
JR		 4331 case KVM_SET_TSC_KHZ: {
4332 u32 user_tsc_khz;
4333
4334 r = -EINVAL;
92a1f12d
JR		 4335 user_tsc_khz = (u32)arg;
4336
4337 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4338 goto out;
4339
cc578287
ZA		 4340 if (user_tsc_khz == 0)
4341 user_tsc_khz = tsc_khz;
4342
381d585c
HZ		 4343 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4344 r = 0;
92a1f12d 4345
92a1f12d
JR		 4346 goto out;
4347 }
4348 case KVM_GET_TSC_KHZ: {
cc578287 4349 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4350 goto out;
4351 }
1c0b28c2
EM		 4352 case KVM_KVMCLOCK_CTRL: {
4353 r = kvm_set_guest_paused(vcpu);
4354 goto out;
4355 }
5c919412
AS		 4356 case KVM_ENABLE_CAP: {
4357 struct kvm_enable_cap cap;
4358
4359 r = -EFAULT;
4360 if (copy_from_user(&cap, argp, sizeof(cap)))
4361 goto out;
4362 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4363 break;
4364 }
8fcc4b59
JM		 4365 case KVM_GET_NESTED_STATE: {
4366 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4367 u32 user_data_size;
4368
4369 r = -EINVAL;
4370 if (!kvm_x86_ops->get_nested_state)
4371 break;
4372
4373 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4374 r = -EFAULT;
8fcc4b59 4375 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4376 break;
8fcc4b59
JM		 4377
4378 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4379 user_data_size);
4380 if (r < 0)
26b471c7 4381 break;
8fcc4b59
JM		 4382
4383 if (r > user_data_size) {
4384 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4385 r = -EFAULT;
4386 else
4387 r = -E2BIG;
4388 break;
8fcc4b59 4389 }
26b471c7 4390
8fcc4b59
JM		 4391 r = 0;
4392 break;
4393 }
4394 case KVM_SET_NESTED_STATE: {
4395 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4396 struct kvm_nested_state kvm_state;
4397
4398 r = -EINVAL;
4399 if (!kvm_x86_ops->set_nested_state)
4400 break;
4401
26b471c7 4402 r = -EFAULT;
8fcc4b59 4403 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4404 break;
8fcc4b59 4405
26b471c7 4406 r = -EINVAL;
8fcc4b59 4407 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4408 break;
8fcc4b59
JM		 4409
4410 if (kvm_state.flags &
8cab6507
VK		 4411 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4412 | KVM_STATE_NESTED_EVMCS))
26b471c7 4413 break;
8fcc4b59
JM		 4414
4415 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4416 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4417 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4418 break;
8fcc4b59
JM		 4419
4420 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4421 break;
4422 }
2bc39970
VK		 4423 case KVM_GET_SUPPORTED_HV_CPUID: {
4424 struct kvm_cpuid2 __user *cpuid_arg = argp;
4425 struct kvm_cpuid2 cpuid;
4426
4427 r = -EFAULT;
4428 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4429 goto out;
4430
4431 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4432 cpuid_arg->entries);
4433 if (r)
4434 goto out;
4435
4436 r = -EFAULT;
4437 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4438 goto out;
4439 r = 0;
4440 break;
4441 }
313a3dc7
CO		 4442 default:
4443 r = -EINVAL;
4444 }
4445out:
d1ac91d8 4446 kfree(u.buffer);
9b062471
CD		 4447out_nofree:
4448 vcpu_put(vcpu);
313a3dc7
CO		 4449 return r;
4450}
4451
1499fa80 4452vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4453{
4454 return VM_FAULT_SIGBUS;
4455}
4456
1fe779f8
CO		 4457static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4458{
4459 int ret;
4460
4461 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4462 return -EINVAL;
1fe779f8
CO		 4463 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4464 return ret;
4465}
4466
b927a3ce
SY		 4467static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4468 u64 ident_addr)
4469{
2ac52ab8 4470 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4471}
4472
1fe779f8 4473static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4474 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4475{
4476 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4477 return -EINVAL;
4478
79fac95e 4479 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4480
4481 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4482 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4483
79fac95e 4484 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4485 return 0;
4486}
4487
bc8a3d89 4488static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4489{
39de71ec 4490 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4491}
4492
1fe779f8
CO		 4493static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4494{
90bca052 4495 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4496 int r;
4497
4498 r = 0;
4499 switch (chip->chip_id) {
4500 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4501 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4502 sizeof(struct kvm_pic_state));
4503 break;
4504 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4505 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4506 sizeof(struct kvm_pic_state));
4507 break;
4508 case KVM_IRQCHIP_IOAPIC:
33392b49 4509 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4510 break;
4511 default:
4512 r = -EINVAL;
4513 break;
4514 }
4515 return r;
4516}
4517
4518static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4519{
90bca052 4520 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4521 int r;
4522
4523 r = 0;
4524 switch (chip->chip_id) {
4525 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4526 spin_lock(&pic->lock);
4527 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4528 sizeof(struct kvm_pic_state));
90bca052 4529 spin_unlock(&pic->lock);
1fe779f8
CO		 4530 break;
4531 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4532 spin_lock(&pic->lock);
4533 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4534 sizeof(struct kvm_pic_state));
90bca052 4535 spin_unlock(&pic->lock);
1fe779f8
CO		 4536 break;
4537 case KVM_IRQCHIP_IOAPIC:
33392b49 4538 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4539 break;
4540 default:
4541 r = -EINVAL;
4542 break;
4543 }
90bca052 4544 kvm_pic_update_irq(pic);
1fe779f8
CO		 4545 return r;
4546}
4547
e0f63cb9
SY		 4548static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4549{
34f3941c
RK		 4550 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4551
4552 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4553
4554 mutex_lock(&kps->lock);
4555 memcpy(ps, &kps->channels, sizeof(*ps));
4556 mutex_unlock(&kps->lock);
2da29bcc 4557 return 0;
e0f63cb9
SY		 4558}
4559
4560static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4561{
0185604c 4562 int i;
09edea72
RK		 4563 struct kvm_pit *pit = kvm->arch.vpit;
4564
4565 mutex_lock(&pit->pit_state.lock);
34f3941c 4566 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4567 for (i = 0; i < 3; i++)
09edea72
RK		 4568 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4569 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4570 return 0;
e9f42757
BK		 4571}
4572
4573static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4574{
e9f42757
BK		 4575 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4576 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4577 sizeof(ps->channels));
4578 ps->flags = kvm->arch.vpit->pit_state.flags;
4579 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4580 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4581 return 0;
e9f42757
BK		 4582}
4583
4584static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4585{
2da29bcc 4586 int start = 0;
0185604c 4587 int i;
e9f42757 4588 u32 prev_legacy, cur_legacy;
09edea72
RK		 4589 struct kvm_pit *pit = kvm->arch.vpit;
4590
4591 mutex_lock(&pit->pit_state.lock);
4592 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4593 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4594 if (!prev_legacy && cur_legacy)
4595 start = 1;
09edea72
RK		 4596 memcpy(&pit->pit_state.channels, &ps->channels,
4597 sizeof(pit->pit_state.channels));
4598 pit->pit_state.flags = ps->flags;
0185604c 4599 for (i = 0; i < 3; i++)
09edea72 4600 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4601 start && i == 0);
09edea72 4602 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4603 return 0;
e0f63cb9
SY		 4604}
4605
52d939a0
MT		 4606static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4607 struct kvm_reinject_control *control)
4608{
71474e2f
RK		 4609 struct kvm_pit *pit = kvm->arch.vpit;
4610
4611 if (!pit)
52d939a0 4612 return -ENXIO;
b39c90b6 4613
71474e2f
RK		 4614 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4615 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4616 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4617 */
4618 mutex_lock(&pit->pit_state.lock);
4619 kvm_pit_set_reinject(pit, control->pit_reinject);
4620 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4621
52d939a0
MT		 4622 return 0;
4623}
4624
95d4c16c 4625/**
60c34612
TY		 4626 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4627 * @kvm: kvm instance
4628 * @log: slot id and address to which we copy the log
95d4c16c 4629 *
e108ff2f
PB		 4630 * Steps 1-4 below provide general overview of dirty page logging. See
4631 * kvm_get_dirty_log_protect() function description for additional details.
4632 *
4633 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4634 * always flush the TLB (step 4) even if previous step failed and the dirty
4635 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4636 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4637 * writes will be marked dirty for next log read.
95d4c16c 4638 *
60c34612
TY		 4639 * 1. Take a snapshot of the bit and clear it if needed.
4640 * 2. Write protect the corresponding page.
e108ff2f
PB		 4641 * 3. Copy the snapshot to the userspace.
4642 * 4. Flush TLB's if needed.
5bb064dc 4643 */
60c34612 4644int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4645{
8fe65a82 4646 bool flush = false;
e108ff2f 4647 int r;
5bb064dc 4648
79fac95e 4649 mutex_lock(&kvm->slots_lock);
5bb064dc 4650
88178fd4
KH		 4651 /*
4652 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4653 */
4654 if (kvm_x86_ops->flush_log_dirty)
4655 kvm_x86_ops->flush_log_dirty(kvm);
4656
8fe65a82 4657 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4658
4659 /*
4660 * All the TLBs can be flushed out of mmu lock, see the comments in
4661 * kvm_mmu_slot_remove_write_access().
4662 */
e108ff2f 4663 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4664 if (flush)
2a31b9db
PB		 4665 kvm_flush_remote_tlbs(kvm);
4666
4667 mutex_unlock(&kvm->slots_lock);
4668 return r;
4669}
4670
4671int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4672{
4673 bool flush = false;
4674 int r;
4675
4676 mutex_lock(&kvm->slots_lock);
4677
4678 /*
4679 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4680 */
4681 if (kvm_x86_ops->flush_log_dirty)
4682 kvm_x86_ops->flush_log_dirty(kvm);
4683
4684 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4685
4686 /*
4687 * All the TLBs can be flushed out of mmu lock, see the comments in
4688 * kvm_mmu_slot_remove_write_access().
4689 */
4690 lockdep_assert_held(&kvm->slots_lock);
4691 if (flush)
198c74f4
XG		 4692 kvm_flush_remote_tlbs(kvm);
4693
79fac95e 4694 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4695 return r;
4696}
4697
aa2fbe6d
YZ		 4698int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4699 bool line_status)
23d43cf9
CD		 4700{
4701 if (!irqchip_in_kernel(kvm))
4702 return -ENXIO;
4703
4704 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4705 irq_event->irq, irq_event->level,
4706 line_status);
23d43cf9
CD		 4707 return 0;
4708}
4709
e5d83c74
PB		 4710int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4711 struct kvm_enable_cap *cap)
90de4a18
NA		 4712{
4713 int r;
4714
4715 if (cap->flags)
4716 return -EINVAL;
4717
4718 switch (cap->cap) {
4719 case KVM_CAP_DISABLE_QUIRKS:
4720 kvm->arch.disabled_quirks = cap->args[0];
4721 r = 0;
4722 break;
49df6397
SR		 4723 case KVM_CAP_SPLIT_IRQCHIP: {
4724 mutex_lock(&kvm->lock);
b053b2ae
SR		 4725 r = -EINVAL;
4726 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4727 goto split_irqchip_unlock;
49df6397
SR		 4728 r = -EEXIST;
4729 if (irqchip_in_kernel(kvm))
4730 goto split_irqchip_unlock;
557abc40 4731 if (kvm->created_vcpus)
49df6397
SR		 4732 goto split_irqchip_unlock;
4733 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4734 if (r)
49df6397
SR		 4735 goto split_irqchip_unlock;
4736 /* Pairs with irqchip_in_kernel. */
4737 smp_wmb();
49776faf 4738 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4739 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4740 r = 0;
4741split_irqchip_unlock:
4742 mutex_unlock(&kvm->lock);
4743 break;
4744 }
37131313
RK		 4745 case KVM_CAP_X2APIC_API:
4746 r = -EINVAL;
4747 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4748 break;
4749
4750 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4751 kvm->arch.x2apic_format = true;
c519265f
RK		 4752 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4753 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4754
4755 r = 0;
4756 break;
4d5422ce
WL		 4757 case KVM_CAP_X86_DISABLE_EXITS:
4758 r = -EINVAL;
4759 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4760 break;
4761
4762 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4763 kvm_can_mwait_in_guest())
4764 kvm->arch.mwait_in_guest = true;
766d3571 4765 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4766 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4767 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4768 kvm->arch.pause_in_guest = true;
b5170063
WL		 4769 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4770 kvm->arch.cstate_in_guest = true;
4d5422ce
WL		 4771 r = 0;
4772 break;
6fbbde9a
DS		 4773 case KVM_CAP_MSR_PLATFORM_INFO:
4774 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4775 r = 0;
c4f55198
JM		 4776 break;
4777 case KVM_CAP_EXCEPTION_PAYLOAD:
4778 kvm->arch.exception_payload_enabled = cap->args[0];
4779 r = 0;
6fbbde9a 4780 break;
90de4a18
NA		 4781 default:
4782 r = -EINVAL;
4783 break;
4784 }
4785 return r;
4786}
4787
1fe779f8
CO		 4788long kvm_arch_vm_ioctl(struct file *filp,
4789 unsigned int ioctl, unsigned long arg)
4790{
4791 struct kvm *kvm = filp->private_data;
4792 void __user *argp = (void __user *)arg;
367e1319 4793 int r = -ENOTTY;
f0d66275
DH		 4794 /*
4795 * This union makes it completely explicit to gcc-3.x
4796 * that these two variables' stack usage should be
4797 * combined, not added together.
4798 */
4799 union {
4800 struct kvm_pit_state ps;
e9f42757 4801 struct kvm_pit_state2 ps2;
c5ff41ce 4802 struct kvm_pit_config pit_config;
f0d66275 4803 } u;
1fe779f8
CO		 4804
4805 switch (ioctl) {
4806 case KVM_SET_TSS_ADDR:
4807 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4808 break;
b927a3ce
SY		 4809 case KVM_SET_IDENTITY_MAP_ADDR: {
4810 u64 ident_addr;
4811
1af1ac91
DH		 4812 mutex_lock(&kvm->lock);
4813 r = -EINVAL;
4814 if (kvm->created_vcpus)
4815 goto set_identity_unlock;
b927a3ce 4816 r = -EFAULT;
0e96f31e 4817 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4818 goto set_identity_unlock;
b927a3ce 4819 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4820set_identity_unlock:
4821 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4822 break;
4823 }
1fe779f8
CO		 4824 case KVM_SET_NR_MMU_PAGES:
4825 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4826 break;
4827 case KVM_GET_NR_MMU_PAGES:
4828 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4829 break;
3ddea128 4830 case KVM_CREATE_IRQCHIP: {
3ddea128 4831 mutex_lock(&kvm->lock);
09941366 4832
3ddea128 4833 r = -EEXIST;
35e6eaa3 4834 if (irqchip_in_kernel(kvm))
3ddea128 4835 goto create_irqchip_unlock;
09941366 4836
3e515705 4837 r = -EINVAL;
557abc40 4838 if (kvm->created_vcpus)
3e515705 4839 goto create_irqchip_unlock;
09941366
RK		 4840
4841 r = kvm_pic_init(kvm);
4842 if (r)
3ddea128 4843 goto create_irqchip_unlock;
09941366
RK		 4844
4845 r = kvm_ioapic_init(kvm);
4846 if (r) {
09941366 4847 kvm_pic_destroy(kvm);
3ddea128 4848 goto create_irqchip_unlock;
09941366
RK		 4849 }
4850
399ec807
AK		 4851 r = kvm_setup_default_irq_routing(kvm);
4852 if (r) {
72bb2fcd 4853 kvm_ioapic_destroy(kvm);
09941366 4854 kvm_pic_destroy(kvm);
71ba994c 4855 goto create_irqchip_unlock;
399ec807 4856 }
49776faf 4857 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4858 smp_wmb();
49776faf 4859 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4860 create_irqchip_unlock:
4861 mutex_unlock(&kvm->lock);
1fe779f8 4862 break;
3ddea128 4863 }
7837699f 4864 case KVM_CREATE_PIT:
c5ff41ce
JK		 4865 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4866 goto create_pit;
4867 case KVM_CREATE_PIT2:
4868 r = -EFAULT;
4869 if (copy_from_user(&u.pit_config, argp,
4870 sizeof(struct kvm_pit_config)))
4871 goto out;
4872 create_pit:
250715a6 4873 mutex_lock(&kvm->lock);
269e05e4
AK		 4874 r = -EEXIST;
4875 if (kvm->arch.vpit)
4876 goto create_pit_unlock;
7837699f 4877 r = -ENOMEM;
c5ff41ce 4878 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4879 if (kvm->arch.vpit)
4880 r = 0;
269e05e4 4881 create_pit_unlock:
250715a6 4882 mutex_unlock(&kvm->lock);
7837699f 4883 break;
1fe779f8
CO		 4884 case KVM_GET_IRQCHIP: {
4885 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4886 struct kvm_irqchip *chip;
1fe779f8 4887
ff5c2c03
SL		 4888 chip = memdup_user(argp, sizeof(*chip));
4889 if (IS_ERR(chip)) {
4890 r = PTR_ERR(chip);
1fe779f8 4891 goto out;
ff5c2c03
SL		 4892 }
4893
1fe779f8 4894 r = -ENXIO;
826da321 4895 if (!irqchip_kernel(kvm))
f0d66275
DH		 4896 goto get_irqchip_out;
4897 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4898 if (r)
f0d66275 4899 goto get_irqchip_out;
1fe779f8 4900 r = -EFAULT;
0e96f31e 4901 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4902 goto get_irqchip_out;
1fe779f8 4903 r = 0;
f0d66275
DH		 4904 get_irqchip_out:
4905 kfree(chip);
1fe779f8
CO		 4906 break;
4907 }
4908 case KVM_SET_IRQCHIP: {
4909 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4910 struct kvm_irqchip *chip;
1fe779f8 4911
ff5c2c03
SL		 4912 chip = memdup_user(argp, sizeof(*chip));
4913 if (IS_ERR(chip)) {
4914 r = PTR_ERR(chip);
1fe779f8 4915 goto out;
ff5c2c03
SL		 4916 }
4917
1fe779f8 4918 r = -ENXIO;
826da321 4919 if (!irqchip_kernel(kvm))
f0d66275
DH		 4920 goto set_irqchip_out;
4921 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4922 if (r)
f0d66275 4923 goto set_irqchip_out;
1fe779f8 4924 r = 0;
f0d66275
DH		 4925 set_irqchip_out:
4926 kfree(chip);
1fe779f8
CO		 4927 break;
4928 }
e0f63cb9 4929 case KVM_GET_PIT: {
e0f63cb9 4930 r = -EFAULT;
f0d66275 4931 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4932 goto out;
4933 r = -ENXIO;
4934 if (!kvm->arch.vpit)
4935 goto out;
f0d66275 4936 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4937 if (r)
4938 goto out;
4939 r = -EFAULT;
f0d66275 4940 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4941 goto out;
4942 r = 0;
4943 break;
4944 }
4945 case KVM_SET_PIT: {
e0f63cb9 4946 r = -EFAULT;
0e96f31e 4947 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4948 goto out;
4949 r = -ENXIO;
4950 if (!kvm->arch.vpit)
4951 goto out;
f0d66275 4952 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4953 break;
4954 }
e9f42757
BK		 4955 case KVM_GET_PIT2: {
4956 r = -ENXIO;
4957 if (!kvm->arch.vpit)
4958 goto out;
4959 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4960 if (r)
4961 goto out;
4962 r = -EFAULT;
4963 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4964 goto out;
4965 r = 0;
4966 break;
4967 }
4968 case KVM_SET_PIT2: {
4969 r = -EFAULT;
4970 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4971 goto out;
4972 r = -ENXIO;
4973 if (!kvm->arch.vpit)
4974 goto out;
4975 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4976 break;
4977 }
52d939a0
MT		 4978 case KVM_REINJECT_CONTROL: {
4979 struct kvm_reinject_control control;
4980 r = -EFAULT;
4981 if (copy_from_user(&control, argp, sizeof(control)))
4982 goto out;
4983 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4984 break;
4985 }
d71ba788
PB		 4986 case KVM_SET_BOOT_CPU_ID:
4987 r = 0;
4988 mutex_lock(&kvm->lock);
557abc40 4989 if (kvm->created_vcpus)
d71ba788
PB		 4990 r = -EBUSY;
4991 else
4992 kvm->arch.bsp_vcpu_id = arg;
4993 mutex_unlock(&kvm->lock);
4994 break;
ffde22ac 4995 case KVM_XEN_HVM_CONFIG: {
51776043 4996 struct kvm_xen_hvm_config xhc;
ffde22ac 4997 r = -EFAULT;
51776043 4998 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4999 goto out;
5000 r = -EINVAL;
51776043 5001 if (xhc.flags)
ffde22ac 5002 goto out;
51776043 5003 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 5004 r = 0;
5005 break;
5006 }
afbcf7ab 5007 case KVM_SET_CLOCK: {
afbcf7ab
GC		 5008 struct kvm_clock_data user_ns;
5009 u64 now_ns;
afbcf7ab
GC		 5010
5011 r = -EFAULT;
5012 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5013 goto out;
5014
5015 r = -EINVAL;
5016 if (user_ns.flags)
5017 goto out;
5018
5019 r = 0;
0bc48bea
RK		 5020 /*
5021 * TODO: userspace has to take care of races with VCPU_RUN, so
5022 * kvm_gen_update_masterclock() can be cut down to locked
5023 * pvclock_update_vm_gtod_copy().
5024 */
5025 kvm_gen_update_masterclock(kvm);
e891a32e 5026 now_ns = get_kvmclock_ns(kvm);
108b249c 5027 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 5028 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 5029 break;
5030 }
5031 case KVM_GET_CLOCK: {
afbcf7ab
GC		 5032 struct kvm_clock_data user_ns;
5033 u64 now_ns;
5034
e891a32e 5035 now_ns = get_kvmclock_ns(kvm);
108b249c 5036 user_ns.clock = now_ns;
e3fd9a93 5037 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 5038 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 5039
5040 r = -EFAULT;
5041 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5042 goto out;
5043 r = 0;
5044 break;
5045 }
5acc5c06
BS		 5046 case KVM_MEMORY_ENCRYPT_OP: {
5047 r = -ENOTTY;
5048 if (kvm_x86_ops->mem_enc_op)
5049 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5050 break;
5051 }
69eaedee
BS		 5052 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5053 struct kvm_enc_region region;
5054
5055 r = -EFAULT;
5056 if (copy_from_user(&region, argp, sizeof(region)))
5057 goto out;
5058
5059 r = -ENOTTY;
5060 if (kvm_x86_ops->mem_enc_reg_region)
5061 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5062 break;
5063 }
5064 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5065 struct kvm_enc_region region;
5066
5067 r = -EFAULT;
5068 if (copy_from_user(&region, argp, sizeof(region)))
5069 goto out;
5070
5071 r = -ENOTTY;
5072 if (kvm_x86_ops->mem_enc_unreg_region)
5073 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5074 break;
5075 }
faeb7833
RK		 5076 case KVM_HYPERV_EVENTFD: {
5077 struct kvm_hyperv_eventfd hvevfd;
5078
5079 r = -EFAULT;
5080 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5081 goto out;
5082 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5083 break;
5084 }
66bb8a06
EH		 5085 case KVM_SET_PMU_EVENT_FILTER:
5086 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5087 break;
1fe779f8 5088 default:
ad6260da 5089 r = -ENOTTY;
1fe779f8
CO		 5090 }
5091out:
5092 return r;
5093}
5094
a16b043c 5095static void kvm_init_msr_list(void)
043405e1
CO		 5096{
5097 u32 dummy[2];
5098 unsigned i, j;
5099
e2ada66e
JM		 5100 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5101 "Please update the fixed PMCs in msrs_to_save[]");
5102 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_GENERIC != 32,
5103 "Please update the generic perfctr/eventsel MSRs in msrs_to_save[]");
5104
62ef68bb 5105 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 5106 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
5107 continue;
93c4adc7
PB		 5108
5109 /*
5110 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 5111 * to the guests in some cases.
93c4adc7
PB		 5112 */
5113 switch (msrs_to_save[i]) {
5114 case MSR_IA32_BNDCFGS:
503234b3 5115 if (!kvm_mpx_supported())
93c4adc7
PB		 5116 continue;
5117 break;
9dbe6cf9
PB		 5118 case MSR_TSC_AUX:
5119 if (!kvm_x86_ops->rdtscp_supported())
5120 continue;
5121 break;
bf8c55d8
CP		 5122 case MSR_IA32_RTIT_CTL:
5123 case MSR_IA32_RTIT_STATUS:
5124 if (!kvm_x86_ops->pt_supported())
5125 continue;
5126 break;
5127 case MSR_IA32_RTIT_CR3_MATCH:
5128 if (!kvm_x86_ops->pt_supported() ||
5129 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5130 continue;
5131 break;
5132 case MSR_IA32_RTIT_OUTPUT_BASE:
5133 case MSR_IA32_RTIT_OUTPUT_MASK:
5134 if (!kvm_x86_ops->pt_supported() ||
5135 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5136 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5137 continue;
5138 break;
5139 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5140 if (!kvm_x86_ops->pt_supported() ||
5141 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5142 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5143 continue;
5144 break;
5145 }
93c4adc7
PB		 5146 default:
5147 break;
5148 }
5149
043405e1
CO		 5150 if (j < i)
5151 msrs_to_save[j] = msrs_to_save[i];
5152 j++;
5153 }
5154 num_msrs_to_save = j;
62ef68bb
PB		 5155
5156 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 5157 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5158 continue;
62ef68bb
PB		 5159
5160 if (j < i)
5161 emulated_msrs[j] = emulated_msrs[i];
5162 j++;
5163 }
5164 num_emulated_msrs = j;
801e459a
TL		 5165
5166 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5167 struct kvm_msr_entry msr;
5168
5169 msr.index = msr_based_features[i];
66421c1e 5170 if (kvm_get_msr_feature(&msr))
801e459a
TL		 5171 continue;
5172
5173 if (j < i)
5174 msr_based_features[j] = msr_based_features[i];
5175 j++;
5176 }
5177 num_msr_based_features = j;
043405e1
CO		 5178}
5179
bda9020e
MT		 5180static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5181 const void *v)
bbd9b64e 5182{
70252a10
AK		 5183 int handled = 0;
5184 int n;
5185
5186 do {
5187 n = min(len, 8);
bce87cce 5188 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5189 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5190 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 5191 break;
5192 handled += n;
5193 addr += n;
5194 len -= n;
5195 v += n;
5196 } while (len);
bbd9b64e 5197
70252a10 5198 return handled;
bbd9b64e
CO		 5199}
5200
bda9020e 5201static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 5202{
70252a10
AK		 5203 int handled = 0;
5204 int n;
5205
5206 do {
5207 n = min(len, 8);
bce87cce 5208 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5209 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5210 addr, n, v))
5211 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5212 break;
e39d200f 5213 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5214 handled += n;
5215 addr += n;
5216 len -= n;
5217 v += n;
5218 } while (len);
bbd9b64e 5219
70252a10 5220 return handled;
bbd9b64e
CO		 5221}
5222
2dafc6c2
GN		 5223static void kvm_set_segment(struct kvm_vcpu *vcpu,
5224 struct kvm_segment *var, int seg)
5225{
5226 kvm_x86_ops->set_segment(vcpu, var, seg);
5227}
5228
5229void kvm_get_segment(struct kvm_vcpu *vcpu,
5230 struct kvm_segment *var, int seg)
5231{
5232 kvm_x86_ops->get_segment(vcpu, var, seg);
5233}
5234
54987b7a
PB		 5235gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5236 struct x86_exception *exception)
02f59dc9
JR		 5237{
5238 gpa_t t_gpa;
02f59dc9
JR		 5239
5240 BUG_ON(!mmu_is_nested(vcpu));
5241
5242 /* NPT walks are always user-walks */
5243 access |= PFERR_USER_MASK;
44dd3ffa 5244 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5245
5246 return t_gpa;
5247}
5248
ab9ae313
AK		 5249gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5250 struct x86_exception *exception)
1871c602
GN		 5251{
5252 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5253 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5254}
5255
ab9ae313
AK		 5256 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5257 struct x86_exception *exception)
1871c602
GN		 5258{
5259 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5260 access |= PFERR_FETCH_MASK;
ab9ae313 5261 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5262}
5263
ab9ae313
AK		 5264gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5265 struct x86_exception *exception)
1871c602
GN		 5266{
5267 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5268 access |= PFERR_WRITE_MASK;
ab9ae313 5269 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5270}
5271
5272/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5273gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5274 struct x86_exception *exception)
1871c602 5275{
ab9ae313 5276 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5277}
5278
5279static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5280 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5281 struct x86_exception *exception)
bbd9b64e
CO		 5282{
5283 void *data = val;
10589a46 5284 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5285
5286 while (bytes) {
14dfe855 5287 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5288 exception);
bbd9b64e 5289 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5290 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5291 int ret;
5292
bcc55cba 5293 if (gpa == UNMAPPED_GVA)
ab9ae313 5294 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5295 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5296 offset, toread);
10589a46 5297 if (ret < 0) {
c3cd7ffa 5298 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5299 goto out;
5300 }
bbd9b64e 5301
77c2002e
IE		 5302 bytes -= toread;
5303 data += toread;
5304 addr += toread;
bbd9b64e 5305 }
10589a46 5306out:
10589a46 5307 return r;
bbd9b64e 5308}
77c2002e 5309
1871c602 5310/* used for instruction fetching */
0f65dd70
AK		 5311static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5312 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5313 struct x86_exception *exception)
1871c602 5314{
0f65dd70 5315 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5316 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5317 unsigned offset;
5318 int ret;
0f65dd70 5319
44583cba
PB		 5320 /* Inline kvm_read_guest_virt_helper for speed. */
5321 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5322 exception);
5323 if (unlikely(gpa == UNMAPPED_GVA))
5324 return X86EMUL_PROPAGATE_FAULT;
5325
5326 offset = addr & (PAGE_SIZE-1);
5327 if (WARN_ON(offset + bytes > PAGE_SIZE))
5328 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5329 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5330 offset, bytes);
44583cba
PB		 5331 if (unlikely(ret < 0))
5332 return X86EMUL_IO_NEEDED;
5333
5334 return X86EMUL_CONTINUE;
1871c602
GN		 5335}
5336
ce14e868 5337int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5338 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5339 struct x86_exception *exception)
1871c602
GN		 5340{
5341 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5342
353c0956
PB		 5343 /*
5344 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5345 * is returned, but our callers are not ready for that and they blindly
5346 * call kvm_inject_page_fault. Ensure that they at least do not leak
5347 * uninitialized kernel stack memory into cr2 and error code.
5348 */
5349 memset(exception, 0, sizeof(*exception));
1871c602 5350 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5351 exception);
1871c602 5352}
064aea77 5353EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5354
ce14e868
PB		 5355static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5356 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5357 struct x86_exception *exception, bool system)
1871c602 5358{
0f65dd70 5359 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5360 u32 access = 0;
5361
5362 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5363 access |= PFERR_USER_MASK;
5364
5365 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5366}
5367
7a036a6f
RK		 5368static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5369 unsigned long addr, void *val, unsigned int bytes)
5370{
5371 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5372 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5373
5374 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5375}
5376
ce14e868
PB		 5377static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5378 struct kvm_vcpu *vcpu, u32 access,
5379 struct x86_exception *exception)
77c2002e
IE		 5380{
5381 void *data = val;
5382 int r = X86EMUL_CONTINUE;
5383
5384 while (bytes) {
14dfe855 5385 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5386 access,
ab9ae313 5387 exception);
77c2002e
IE		 5388 unsigned offset = addr & (PAGE_SIZE-1);
5389 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5390 int ret;
5391
bcc55cba 5392 if (gpa == UNMAPPED_GVA)
ab9ae313 5393 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5394 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5395 if (ret < 0) {
c3cd7ffa 5396 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5397 goto out;
5398 }
5399
5400 bytes -= towrite;
5401 data += towrite;
5402 addr += towrite;
5403 }
5404out:
5405 return r;
5406}
ce14e868
PB		 5407
5408static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5409 unsigned int bytes, struct x86_exception *exception,
5410 bool system)
ce14e868
PB		 5411{
5412 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5413 u32 access = PFERR_WRITE_MASK;
5414
5415 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5416 access |= PFERR_USER_MASK;
ce14e868
PB		 5417
5418 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5419 access, exception);
ce14e868
PB		 5420}
5421
5422int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5423 unsigned int bytes, struct x86_exception *exception)
5424{
c595ceee
PB		 5425 /* kvm_write_guest_virt_system can pull in tons of pages. */
5426 vcpu->arch.l1tf_flush_l1d = true;
5427
541ab2ae
FH		 5428 /*
5429 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5430 * is returned, but our callers are not ready for that and they blindly
5431 * call kvm_inject_page_fault. Ensure that they at least do not leak
5432 * uninitialized kernel stack memory into cr2 and error code.
5433 */
5434 memset(exception, 0, sizeof(*exception));
ce14e868
PB		 5435 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5436 PFERR_WRITE_MASK, exception);
5437}
6a4d7550 5438EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5439
082d06ed
WL		 5440int handle_ud(struct kvm_vcpu *vcpu)
5441{
6c86eedc 5442 int emul_type = EMULTYPE_TRAP_UD;
6c86eedc
WL		 5443 char sig[5]; /* ud2; .ascii "kvm" */
5444 struct x86_exception e;
5445
5446 if (force_emulation_prefix &&
3c9fa24c
PB		 5447 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5448 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5449 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5450 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
b4000606 5451 emul_type = EMULTYPE_TRAP_UD_FORCED;
6c86eedc 5452 }
082d06ed 5453
c83fad65 5454 return kvm_emulate_instruction(vcpu, emul_type) != EMULATE_USER_EXIT;
082d06ed
WL		 5455}
5456EXPORT_SYMBOL_GPL(handle_ud);
5457
0f89b207
TL		 5458static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5459 gpa_t gpa, bool write)
5460{
5461 /* For APIC access vmexit */
5462 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5463 return 1;
5464
5465 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5466 trace_vcpu_match_mmio(gva, gpa, write, true);
5467 return 1;
5468 }
5469
5470 return 0;
5471}
5472
af7cc7d1
XG		 5473static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5474 gpa_t *gpa, struct x86_exception *exception,
5475 bool write)
5476{
97d64b78
AK		 5477 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5478 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5479
be94f6b7
HH		 5480 /*
5481 * currently PKRU is only applied to ept enabled guest so
5482 * there is no pkey in EPT page table for L1 guest or EPT
5483 * shadow page table for L2 guest.
5484 */
97d64b78 5485 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5486 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
871bd034 5487 vcpu->arch.mmio_access, 0, access)) {
bebb106a
XG		 5488 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5489 (gva & (PAGE_SIZE - 1));
4f022648 5490 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5491 return 1;
5492 }
5493
af7cc7d1
XG		 5494 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5495
5496 if (*gpa == UNMAPPED_GVA)
5497 return -1;
5498
0f89b207 5499 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5500}
5501
3200f405 5502int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5503 const void *val, int bytes)
bbd9b64e
CO		 5504{
5505 int ret;
5506
54bf36aa 5507 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5508 if (ret < 0)
bbd9b64e 5509 return 0;
0eb05bf2 5510 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5511 return 1;
5512}
5513
77d197b2
XG		 5514struct read_write_emulator_ops {
5515 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5516 int bytes);
5517 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5518 void *val, int bytes);
5519 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5520 int bytes, void *val);
5521 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5522 void *val, int bytes);
5523 bool write;
5524};
5525
5526static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5527{
5528 if (vcpu->mmio_read_completed) {
77d197b2 5529 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5530 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5531 vcpu->mmio_read_completed = 0;
5532 return 1;
5533 }
5534
5535 return 0;
5536}
5537
5538static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5539 void *val, int bytes)
5540{
54bf36aa 5541 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5542}
5543
5544static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5545 void *val, int bytes)
5546{
5547 return emulator_write_phys(vcpu, gpa, val, bytes);
5548}
5549
5550static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5551{
e39d200f 5552 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5553 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5554}
5555
5556static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5557 void *val, int bytes)
5558{
e39d200f 5559 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5560 return X86EMUL_IO_NEEDED;
5561}
5562
5563static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5564 void *val, int bytes)
5565{
f78146b0
AK		 5566 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5567
87da7e66 5568 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5569 return X86EMUL_CONTINUE;
5570}
5571
0fbe9b0b 5572static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5573 .read_write_prepare = read_prepare,
5574 .read_write_emulate = read_emulate,
5575 .read_write_mmio = vcpu_mmio_read,
5576 .read_write_exit_mmio = read_exit_mmio,
5577};
5578
0fbe9b0b 5579static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5580 .read_write_emulate = write_emulate,
5581 .read_write_mmio = write_mmio,
5582 .read_write_exit_mmio = write_exit_mmio,
5583 .write = true,
5584};
5585
22388a3c
XG		 5586static int emulator_read_write_onepage(unsigned long addr, void *val,
5587 unsigned int bytes,
5588 struct x86_exception *exception,
5589 struct kvm_vcpu *vcpu,
0fbe9b0b 5590 const struct read_write_emulator_ops *ops)
bbd9b64e 5591{
af7cc7d1
XG		 5592 gpa_t gpa;
5593 int handled, ret;
22388a3c 5594 bool write = ops->write;
f78146b0 5595 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5596 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5597
5598 /*
5599 * If the exit was due to a NPF we may already have a GPA.
5600 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5601 * Note, this cannot be used on string operations since string
5602 * operation using rep will only have the initial GPA from the NPF
5603 * occurred.
5604 */
5605 if (vcpu->arch.gpa_available &&
5606 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5607 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5608 gpa = vcpu->arch.gpa_val;
5609 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5610 } else {
5611 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5612 if (ret < 0)
5613 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5614 }
10589a46 5615
618232e2 5616 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5617 return X86EMUL_CONTINUE;
5618
bbd9b64e
CO		 5619 /*
5620 * Is this MMIO handled locally?
5621 */
22388a3c 5622 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5623 if (handled == bytes)
bbd9b64e 5624 return X86EMUL_CONTINUE;
bbd9b64e 5625
70252a10
AK		 5626 gpa += handled;
5627 bytes -= handled;
5628 val += handled;
5629
87da7e66
XG		 5630 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5631 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5632 frag->gpa = gpa;
5633 frag->data = val;
5634 frag->len = bytes;
f78146b0 5635 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5636}
5637
52eb5a6d
XL		 5638static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5639 unsigned long addr,
22388a3c
XG		 5640 void *val, unsigned int bytes,
5641 struct x86_exception *exception,
0fbe9b0b 5642 const struct read_write_emulator_ops *ops)
bbd9b64e 5643{
0f65dd70 5644 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5645 gpa_t gpa;
5646 int rc;
5647
5648 if (ops->read_write_prepare &&
5649 ops->read_write_prepare(vcpu, val, bytes))
5650 return X86EMUL_CONTINUE;
5651
5652 vcpu->mmio_nr_fragments = 0;
0f65dd70 5653
bbd9b64e
CO		 5654 /* Crossing a page boundary? */
5655 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5656 int now;
bbd9b64e
CO		 5657
5658 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5659 rc = emulator_read_write_onepage(addr, val, now, exception,
5660 vcpu, ops);
5661
bbd9b64e
CO		 5662 if (rc != X86EMUL_CONTINUE)
5663 return rc;
5664 addr += now;
bac15531
NA		 5665 if (ctxt->mode != X86EMUL_MODE_PROT64)
5666 addr = (u32)addr;
bbd9b64e
CO		 5667 val += now;
5668 bytes -= now;
5669 }
22388a3c 5670
f78146b0
AK		 5671 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5672 vcpu, ops);
5673 if (rc != X86EMUL_CONTINUE)
5674 return rc;
5675
5676 if (!vcpu->mmio_nr_fragments)
5677 return rc;
5678
5679 gpa = vcpu->mmio_fragments[0].gpa;
5680
5681 vcpu->mmio_needed = 1;
5682 vcpu->mmio_cur_fragment = 0;
5683
87da7e66 5684 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5685 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5686 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5687 vcpu->run->mmio.phys_addr = gpa;
5688
5689 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5690}
5691
5692static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5693 unsigned long addr,
5694 void *val,
5695 unsigned int bytes,
5696 struct x86_exception *exception)
5697{
5698 return emulator_read_write(ctxt, addr, val, bytes,
5699 exception, &read_emultor);
5700}
5701
52eb5a6d 5702static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5703 unsigned long addr,
5704 const void *val,
5705 unsigned int bytes,
5706 struct x86_exception *exception)
5707{
5708 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5709 exception, &write_emultor);
bbd9b64e 5710}
bbd9b64e 5711
daea3e73
AK		 5712#define CMPXCHG_TYPE(t, ptr, old, new) \
5713 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5714
5715#ifdef CONFIG_X86_64
5716# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5717#else
5718# define CMPXCHG64(ptr, old, new) \
9749a6c0 5719 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5720#endif
5721
0f65dd70
AK		 5722static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5723 unsigned long addr,
bbd9b64e
CO		 5724 const void *old,
5725 const void *new,
5726 unsigned int bytes,
0f65dd70 5727 struct x86_exception *exception)
bbd9b64e 5728{
42e35f80 5729 struct kvm_host_map map;
0f65dd70 5730 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73 5731 gpa_t gpa;
daea3e73
AK		 5732 char *kaddr;
5733 bool exchanged;
2bacc55c 5734
daea3e73
AK		 5735 /* guests cmpxchg8b have to be emulated atomically */
5736 if (bytes > 8 || (bytes & (bytes - 1)))
5737 goto emul_write;
10589a46 5738
daea3e73 5739 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5740
daea3e73
AK		 5741 if (gpa == UNMAPPED_GVA ||
5742 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5743 goto emul_write;
2bacc55c 5744
daea3e73
AK		 5745 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5746 goto emul_write;
72dc67a6 5747
42e35f80 5748 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
c19b8bd6 5749 goto emul_write;
72dc67a6 5750
42e35f80
KA		 5751 kaddr = map.hva + offset_in_page(gpa);
5752
daea3e73
AK		 5753 switch (bytes) {
5754 case 1:
5755 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5756 break;
5757 case 2:
5758 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5759 break;
5760 case 4:
5761 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5762 break;
5763 case 8:
5764 exchanged = CMPXCHG64(kaddr, old, new);
5765 break;
5766 default:
5767 BUG();
2bacc55c 5768 }
42e35f80
KA		 5769
5770 kvm_vcpu_unmap(vcpu, &map, true);
daea3e73
AK		 5771
5772 if (!exchanged)
5773 return X86EMUL_CMPXCHG_FAILED;
5774
0eb05bf2 5775 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5776
5777 return X86EMUL_CONTINUE;
4a5f48f6 5778
3200f405 5779emul_write:
daea3e73 5780 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5781
0f65dd70 5782 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5783}
5784
cf8f70bf
GN		 5785static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5786{
cbfc6c91 5787 int r = 0, i;
cf8f70bf 5788
cbfc6c91
WL		 5789 for (i = 0; i < vcpu->arch.pio.count; i++) {
5790 if (vcpu->arch.pio.in)
5791 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5792 vcpu->arch.pio.size, pd);
5793 else
5794 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5795 vcpu->arch.pio.port, vcpu->arch.pio.size,
5796 pd);
5797 if (r)
5798 break;
5799 pd += vcpu->arch.pio.size;
5800 }
cf8f70bf
GN		 5801 return r;
5802}
5803
6f6fbe98
XG		 5804static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5805 unsigned short port, void *val,
5806 unsigned int count, bool in)
cf8f70bf 5807{
cf8f70bf 5808 vcpu->arch.pio.port = port;
6f6fbe98 5809 vcpu->arch.pio.in = in;
7972995b 5810 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5811 vcpu->arch.pio.size = size;
5812
5813 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5814 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5815 return 1;
5816 }
5817
5818 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5819 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5820 vcpu->run->io.size = size;
5821 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5822 vcpu->run->io.count = count;
5823 vcpu->run->io.port = port;
5824
5825 return 0;
5826}
5827
6f6fbe98
XG		 5828static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5829 int size, unsigned short port, void *val,
5830 unsigned int count)
cf8f70bf 5831{
ca1d4a9e 5832 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5833 int ret;
ca1d4a9e 5834
6f6fbe98
XG		 5835 if (vcpu->arch.pio.count)
5836 goto data_avail;
cf8f70bf 5837
cbfc6c91
WL		 5838 memset(vcpu->arch.pio_data, 0, size * count);
5839
6f6fbe98
XG		 5840 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5841 if (ret) {
5842data_avail:
5843 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5844 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5845 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5846 return 1;
5847 }
5848
cf8f70bf
GN		 5849 return 0;
5850}
5851
6f6fbe98
XG		 5852static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5853 int size, unsigned short port,
5854 const void *val, unsigned int count)
5855{
5856 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5857
5858 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5859 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5860 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5861}
5862
bbd9b64e
CO		 5863static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5864{
5865 return kvm_x86_ops->get_segment_base(vcpu, seg);
5866}
5867
3cb16fe7 5868static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5869{
3cb16fe7 5870 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5871}
5872
ae6a2375 5873static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5874{
5875 if (!need_emulate_wbinvd(vcpu))
5876 return X86EMUL_CONTINUE;
5877
5878 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5879 int cpu = get_cpu();
5880
5881 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5882 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5883 wbinvd_ipi, NULL, 1);
2eec7343 5884 put_cpu();
f5f48ee1 5885 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5886 } else
5887 wbinvd();
f5f48ee1
SY		 5888 return X86EMUL_CONTINUE;
5889}
5cb56059
JS		 5890
5891int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5892{
6affcbed
KH		 5893 kvm_emulate_wbinvd_noskip(vcpu);
5894 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5895}
f5f48ee1
SY		 5896EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5897
5cb56059
JS		 5898
5899
bcaf5cc5
AK		 5900static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5901{
5cb56059 5902 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5903}
5904
52eb5a6d
XL		 5905static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5906 unsigned long *dest)
bbd9b64e 5907{
16f8a6f9 5908 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5909}
5910
52eb5a6d
XL		 5911static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5912 unsigned long value)
bbd9b64e 5913{
338dbc97 5914
717746e3 5915 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5916}
5917
52a46617 5918static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5919{
52a46617 5920 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5921}
5922
717746e3 5923static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5924{
717746e3 5925 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5926 unsigned long value;
5927
5928 switch (cr) {
5929 case 0:
5930 value = kvm_read_cr0(vcpu);
5931 break;
5932 case 2:
5933 value = vcpu->arch.cr2;
5934 break;
5935 case 3:
9f8fe504 5936 value = kvm_read_cr3(vcpu);
52a46617
GN		 5937 break;
5938 case 4:
5939 value = kvm_read_cr4(vcpu);
5940 break;
5941 case 8:
5942 value = kvm_get_cr8(vcpu);
5943 break;
5944 default:
a737f256 5945 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5946 return 0;
5947 }
5948
5949 return value;
5950}
5951
717746e3 5952static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5953{
717746e3 5954 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5955 int res = 0;
5956
52a46617
GN		 5957 switch (cr) {
5958 case 0:
49a9b07e 5959 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5960 break;
5961 case 2:
5962 vcpu->arch.cr2 = val;
5963 break;
5964 case 3:
2390218b 5965 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5966 break;
5967 case 4:
a83b29c6 5968 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5969 break;
5970 case 8:
eea1cff9 5971 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5972 break;
5973 default:
a737f256 5974 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5975 res = -1;
52a46617 5976 }
0f12244f
GN		 5977
5978 return res;
52a46617
GN		 5979}
5980
717746e3 5981static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5982{
717746e3 5983 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5984}
5985
4bff1e86 5986static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5987{
4bff1e86 5988 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5989}
5990
4bff1e86 5991static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5992{
4bff1e86 5993 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5994}
5995
1ac9d0cf
AK		 5996static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5997{
5998 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5999}
6000
6001static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6002{
6003 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6004}
6005
4bff1e86
AK		 6006static unsigned long emulator_get_cached_segment_base(
6007 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 6008{
4bff1e86 6009 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 6010}
6011
1aa36616
AK		 6012static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6013 struct desc_struct *desc, u32 *base3,
6014 int seg)
2dafc6c2
GN		 6015{
6016 struct kvm_segment var;
6017
4bff1e86 6018 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 6019 *selector = var.selector;
2dafc6c2 6020
378a8b09
GN		 6021 if (var.unusable) {
6022 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 6023 if (base3)
6024 *base3 = 0;
2dafc6c2 6025 return false;
378a8b09 6026 }
2dafc6c2
GN		 6027
6028 if (var.g)
6029 var.limit >>= 12;
6030 set_desc_limit(desc, var.limit);
6031 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 6032#ifdef CONFIG_X86_64
6033 if (base3)
6034 *base3 = var.base >> 32;
6035#endif
2dafc6c2
GN		 6036 desc->type = var.type;
6037 desc->s = var.s;
6038 desc->dpl = var.dpl;
6039 desc->p = var.present;
6040 desc->avl = var.avl;
6041 desc->l = var.l;
6042 desc->d = var.db;
6043 desc->g = var.g;
6044
6045 return true;
6046}
6047
1aa36616
AK		 6048static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6049 struct desc_struct *desc, u32 base3,
6050 int seg)
2dafc6c2 6051{
4bff1e86 6052 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 6053 struct kvm_segment var;
6054
1aa36616 6055 var.selector = selector;
2dafc6c2 6056 var.base = get_desc_base(desc);
5601d05b
GN		 6057#ifdef CONFIG_X86_64
6058 var.base |= ((u64)base3) << 32;
6059#endif
2dafc6c2
GN		 6060 var.limit = get_desc_limit(desc);
6061 if (desc->g)
6062 var.limit = (var.limit << 12) | 0xfff;
6063 var.type = desc->type;
2dafc6c2
GN		 6064 var.dpl = desc->dpl;
6065 var.db = desc->d;
6066 var.s = desc->s;
6067 var.l = desc->l;
6068 var.g = desc->g;
6069 var.avl = desc->avl;
6070 var.present = desc->p;
6071 var.unusable = !var.present;
6072 var.padding = 0;
6073
6074 kvm_set_segment(vcpu, &var, seg);
6075 return;
6076}
6077
717746e3
AK		 6078static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6079 u32 msr_index, u64 *pdata)
6080{
f20935d8 6081 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
717746e3
AK		 6082}
6083
6084static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6085 u32 msr_index, u64 data)
6086{
f20935d8 6087 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
717746e3
AK		 6088}
6089
64d60670
PB		 6090static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6091{
6092 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6093
6094 return vcpu->arch.smbase;
6095}
6096
6097static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6098{
6099 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6100
6101 vcpu->arch.smbase = smbase;
6102}
6103
67f4d428
NA		 6104static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6105 u32 pmc)
6106{
c6702c9d 6107 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 6108}
6109
222d21aa
AK		 6110static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6111 u32 pmc, u64 *pdata)
6112{
c6702c9d 6113 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 6114}
6115
6c3287f7
AK		 6116static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6117{
6118 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6119}
6120
2953538e 6121static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 6122 struct x86_instruction_info *info,
c4f035c6
AK		 6123 enum x86_intercept_stage stage)
6124{
2953538e 6125 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 6126}
6127
e911eb3b
YZ		 6128static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6129 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 6130{
e911eb3b 6131 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 6132}
6133
dd856efa
AK		 6134static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6135{
6136 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6137}
6138
6139static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6140{
6141 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6142}
6143
801806d9
NA		 6144static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6145{
6146 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6147}
6148
6ed071f0
LP		 6149static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6150{
6151 return emul_to_vcpu(ctxt)->arch.hflags;
6152}
6153
6154static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6155{
c5833c7a 6156 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 6157}
6158
ed19321f
SC		 6159static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6160 const char *smstate)
0234bf88 6161{
ed19321f 6162 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 6163}
6164
c5833c7a
SC		 6165static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6166{
6167 kvm_smm_changed(emul_to_vcpu(ctxt));
6168}
6169
02d4160f
VK		 6170static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6171{
6172 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6173}
6174
0225fb50 6175static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 6176 .read_gpr = emulator_read_gpr,
6177 .write_gpr = emulator_write_gpr,
ce14e868
PB		 6178 .read_std = emulator_read_std,
6179 .write_std = emulator_write_std,
7a036a6f 6180 .read_phys = kvm_read_guest_phys_system,
1871c602 6181 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 6182 .read_emulated = emulator_read_emulated,
6183 .write_emulated = emulator_write_emulated,
6184 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 6185 .invlpg = emulator_invlpg,
cf8f70bf
GN		 6186 .pio_in_emulated = emulator_pio_in_emulated,
6187 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 6188 .get_segment = emulator_get_segment,
6189 .set_segment = emulator_set_segment,
5951c442 6190 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 6191 .get_gdt = emulator_get_gdt,
160ce1f1 6192 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 6193 .set_gdt = emulator_set_gdt,
6194 .set_idt = emulator_set_idt,
52a46617
GN		 6195 .get_cr = emulator_get_cr,
6196 .set_cr = emulator_set_cr,
9c537244 6197 .cpl = emulator_get_cpl,
35aa5375
GN		 6198 .get_dr = emulator_get_dr,
6199 .set_dr = emulator_set_dr,
64d60670
PB		 6200 .get_smbase = emulator_get_smbase,
6201 .set_smbase = emulator_set_smbase,
717746e3
AK		 6202 .set_msr = emulator_set_msr,
6203 .get_msr = emulator_get_msr,
67f4d428 6204 .check_pmc = emulator_check_pmc,
222d21aa 6205 .read_pmc = emulator_read_pmc,
6c3287f7 6206 .halt = emulator_halt,
bcaf5cc5 6207 .wbinvd = emulator_wbinvd,
d6aa1000 6208 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6209 .intercept = emulator_intercept,
bdb42f5a 6210 .get_cpuid = emulator_get_cpuid,
801806d9 6211 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6212 .get_hflags = emulator_get_hflags,
6213 .set_hflags = emulator_set_hflags,
0234bf88 6214 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6215 .post_leave_smm = emulator_post_leave_smm,
02d4160f 6216 .set_xcr = emulator_set_xcr,
bbd9b64e
CO		 6217};
6218
95cb2295
GN		 6219static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6220{
37ccdcbe 6221 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6222 /*
6223 * an sti; sti; sequence only disable interrupts for the first
6224 * instruction. So, if the last instruction, be it emulated or
6225 * not, left the system with the INT_STI flag enabled, it
6226 * means that the last instruction is an sti. We should not
6227 * leave the flag on in this case. The same goes for mov ss
6228 */
37ccdcbe
PB		 6229 if (int_shadow & mask)
6230 mask = 0;
6addfc42 6231 if (unlikely(int_shadow || mask)) {
95cb2295 6232 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6233 if (!mask)
6234 kvm_make_request(KVM_REQ_EVENT, vcpu);
6235 }
95cb2295
GN		 6236}
6237
ef54bcfe 6238static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6239{
6240 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6241 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6242 return kvm_propagate_fault(vcpu, &ctxt->exception);
6243
6244 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6245 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6246 ctxt->exception.error_code);
54b8486f 6247 else
da9cb575 6248 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6249 return false;
54b8486f
GN		 6250}
6251
8ec4722d
MG		 6252static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6253{
adf52235 6254 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6255 int cs_db, cs_l;
6256
8ec4722d
MG		 6257 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6258
adf52235 6259 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6260 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6261
adf52235
TY		 6262 ctxt->eip = kvm_rip_read(vcpu);
6263 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6264 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6265 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6266 cs_db ? X86EMUL_MODE_PROT32 :
6267 X86EMUL_MODE_PROT16;
a584539b 6268 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6269 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6270 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6271
dd856efa 6272 init_decode_cache(ctxt);
7ae441ea 6273 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6274}
6275
71f9833b 6276int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6277{
9d74191a 6278 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6279 int ret;
6280
6281 init_emulate_ctxt(vcpu);
6282
9dac77fa
AK		 6283 ctxt->op_bytes = 2;
6284 ctxt->ad_bytes = 2;
6285 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6286 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6287
6288 if (ret != X86EMUL_CONTINUE)
6289 return EMULATE_FAIL;
6290
9dac77fa 6291 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6292 kvm_rip_write(vcpu, ctxt->eip);
6293 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6294
63995653
MG		 6295 return EMULATE_DONE;
6296}
6297EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6298
e2366171 6299static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6300{
6d77dbfc
GN		 6301 ++vcpu->stat.insn_emulation_fail;
6302 trace_kvm_emulate_insn_failed(vcpu);
e2366171 6303
42cbf068
SC		 6304 if (emulation_type & EMULTYPE_VMWARE_GP) {
6305 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6306 return EMULATE_DONE;
6307 }
e2366171 6308
738fece4
SC		 6309 if (emulation_type & EMULTYPE_SKIP) {
6310 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6311 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6312 vcpu->run->internal.ndata = 0;
6313 return EMULATE_USER_EXIT;
6314 }
6315
22da61c9
SC		 6316 kvm_queue_exception(vcpu, UD_VECTOR);
6317
a2b9e6c1 6318 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6319 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6320 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6321 vcpu->run->internal.ndata = 0;
22da61c9 6322 return EMULATE_USER_EXIT;
fc3a9157 6323 }
e2366171 6324
22da61c9 6325 return EMULATE_DONE;
6d77dbfc
GN		 6326}
6327
93c05d3e 6328static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6329 bool write_fault_to_shadow_pgtable,
6330 int emulation_type)
a6f177ef 6331{
95b3cf69 6332 gpa_t gpa = cr2;
ba049e93 6333 kvm_pfn_t pfn;
a6f177ef 6334
384bf221 6335 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6336 return false;
6337
6c3dfeb6
SC		 6338 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6339 return false;
6340
44dd3ffa 6341 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6342 /*
6343 * Write permission should be allowed since only
6344 * write access need to be emulated.
6345 */
6346 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6347
95b3cf69
XG		 6348 /*
6349 * If the mapping is invalid in guest, let cpu retry
6350 * it to generate fault.
6351 */
6352 if (gpa == UNMAPPED_GVA)
6353 return true;
6354 }
a6f177ef 6355
8e3d9d06
XG		 6356 /*
6357 * Do not retry the unhandleable instruction if it faults on the
6358 * readonly host memory, otherwise it will goto a infinite loop:
6359 * retry instruction -> write #PF -> emulation fail -> retry
6360 * instruction -> ...
6361 */
6362 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6363
6364 /*
6365 * If the instruction failed on the error pfn, it can not be fixed,
6366 * report the error to userspace.
6367 */
6368 if (is_error_noslot_pfn(pfn))
6369 return false;
6370
6371 kvm_release_pfn_clean(pfn);
6372
6373 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6374 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6375 unsigned int indirect_shadow_pages;
6376
6377 spin_lock(&vcpu->kvm->mmu_lock);
6378 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6379 spin_unlock(&vcpu->kvm->mmu_lock);
6380
6381 if (indirect_shadow_pages)
6382 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6383
a6f177ef 6384 return true;
8e3d9d06 6385 }
a6f177ef 6386
95b3cf69
XG		 6387 /*
6388 * if emulation was due to access to shadowed page table
6389 * and it failed try to unshadow page and re-enter the
6390 * guest to let CPU execute the instruction.
6391 */
6392 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6393
6394 /*
6395 * If the access faults on its page table, it can not
6396 * be fixed by unprotecting shadow page and it should
6397 * be reported to userspace.
6398 */
6399 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6400}
6401
1cb3f3ae
XG		 6402static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6403 unsigned long cr2, int emulation_type)
6404{
6405 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6406 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6407
6408 last_retry_eip = vcpu->arch.last_retry_eip;
6409 last_retry_addr = vcpu->arch.last_retry_addr;
6410
6411 /*
6412 * If the emulation is caused by #PF and it is non-page_table
6413 * writing instruction, it means the VM-EXIT is caused by shadow
6414 * page protected, we can zap the shadow page and retry this
6415 * instruction directly.
6416 *
6417 * Note: if the guest uses a non-page-table modifying instruction
6418 * on the PDE that points to the instruction, then we will unmap
6419 * the instruction and go to an infinite loop. So, we cache the
6420 * last retried eip and the last fault address, if we meet the eip
6421 * and the address again, we can break out of the potential infinite
6422 * loop.
6423 */
6424 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6425
384bf221 6426 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6427 return false;
6428
6c3dfeb6
SC		 6429 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6430 return false;
6431
1cb3f3ae
XG		 6432 if (x86_page_table_writing_insn(ctxt))
6433 return false;
6434
6435 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6436 return false;
6437
6438 vcpu->arch.last_retry_eip = ctxt->eip;
6439 vcpu->arch.last_retry_addr = cr2;
6440
44dd3ffa 6441 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6442 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6443
22368028 6444 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6445
6446 return true;
6447}
6448
716d51ab
GN		 6449static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6450static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6451
64d60670 6452static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6453{
64d60670 6454 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6455 /* This is a good place to trace that we are exiting SMM. */
6456 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6457
c43203ca
PB		 6458 /* Process a latched INIT or SMI, if any. */
6459 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6460 }
699023e2
PB		 6461
6462 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6463}
6464
4a1e10d5
PB		 6465static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6466 unsigned long *db)
6467{
6468 u32 dr6 = 0;
6469 int i;
6470 u32 enable, rwlen;
6471
6472 enable = dr7;
6473 rwlen = dr7 >> 16;
6474 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6475 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6476 dr6 |= (1 << i);
6477 return dr6;
6478}
6479
120c2c4f 6480static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
663f4c61
PB		 6481{
6482 struct kvm_run *kvm_run = vcpu->run;
6483
c8401dda
PB		 6484 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6485 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6486 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6487 kvm_run->debug.arch.exception = DB_VECTOR;
6488 kvm_run->exit_reason = KVM_EXIT_DEBUG;
120c2c4f 6489 return EMULATE_USER_EXIT;
663f4c61 6490 }
120c2c4f
SC		 6491 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6492 return EMULATE_DONE;
663f4c61
PB		 6493}
6494
6affcbed
KH		 6495int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6496{
6497 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
f8ea7c60 6498 int r;
6affcbed 6499
f8ea7c60
VK		 6500 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6501 if (unlikely(r != EMULATE_DONE))
6502 return 0;
c8401dda
PB		 6503
6504 /*
6505 * rflags is the old, "raw" value of the flags. The new value has
6506 * not been saved yet.
6507 *
6508 * This is correct even for TF set by the guest, because "the
6509 * processor will not generate this exception after the instruction
6510 * that sets the TF flag".
6511 */
6512 if (unlikely(rflags & X86_EFLAGS_TF))
120c2c4f 6513 r = kvm_vcpu_do_singlestep(vcpu);
6affcbed
KH		 6514 return r == EMULATE_DONE;
6515}
6516EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6517
4a1e10d5
PB		 6518static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6519{
4a1e10d5
PB		 6520 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6521 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6522 struct kvm_run *kvm_run = vcpu->run;
6523 unsigned long eip = kvm_get_linear_rip(vcpu);
6524 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6525 vcpu->arch.guest_debug_dr7,
6526 vcpu->arch.eff_db);
6527
6528 if (dr6 != 0) {
6f43ed01 6529 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6530 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6531 kvm_run->debug.arch.exception = DB_VECTOR;
6532 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6533 *r = EMULATE_USER_EXIT;
6534 return true;
6535 }
6536 }
6537
4161a569
NA		 6538 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6539 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6540 unsigned long eip = kvm_get_linear_rip(vcpu);
6541 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6542 vcpu->arch.dr7,
6543 vcpu->arch.db);
6544
6545 if (dr6 != 0) {
1fc5d194 6546 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 6547 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6548 kvm_queue_exception(vcpu, DB_VECTOR);
6549 *r = EMULATE_DONE;
6550 return true;
6551 }
6552 }
6553
6554 return false;
6555}
6556
04789b66
LA		 6557static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6558{
2d7921c4
AM		 6559 switch (ctxt->opcode_len) {
6560 case 1:
6561 switch (ctxt->b) {
6562 case 0xe4: /* IN */
6563 case 0xe5:
6564 case 0xec:
6565 case 0xed:
6566 case 0xe6: /* OUT */
6567 case 0xe7:
6568 case 0xee:
6569 case 0xef:
6570 case 0x6c: /* INS */
6571 case 0x6d:
6572 case 0x6e: /* OUTS */
6573 case 0x6f:
6574 return true;
6575 }
6576 break;
6577 case 2:
6578 switch (ctxt->b) {
6579 case 0x33: /* RDPMC */
6580 return true;
6581 }
6582 break;
04789b66
LA		 6583 }
6584
6585 return false;
6586}
6587
51d8b661
AP		 6588int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6589 unsigned long cr2,
dc25e89e
AP		 6590 int emulation_type,
6591 void *insn,
6592 int insn_len)
bbd9b64e 6593{
95cb2295 6594 int r;
9d74191a 6595 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6596 bool writeback = true;
93c05d3e 6597 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6598
c595ceee
PB		 6599 vcpu->arch.l1tf_flush_l1d = true;
6600
93c05d3e
XG		 6601 /*
6602 * Clear write_fault_to_shadow_pgtable here to ensure it is
6603 * never reused.
6604 */
6605 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6606 kvm_clear_exception_queue(vcpu);
8d7d8102 6607
571008da 6608 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6609 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6610
6611 /*
6612 * We will reenter on the same instruction since
6613 * we do not set complete_userspace_io. This does not
6614 * handle watchpoints yet, those would be handled in
6615 * the emulate_ops.
6616 */
d391f120
VK		 6617 if (!(emulation_type & EMULTYPE_SKIP) &&
6618 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6619 return r;
6620
9d74191a
TY		 6621 ctxt->interruptibility = 0;
6622 ctxt->have_exception = false;
e0ad0b47 6623 ctxt->exception.vector = -1;
9d74191a 6624 ctxt->perm_ok = false;
bbd9b64e 6625
b51e974f 6626 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6627
9d74191a 6628 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6629
e46479f8 6630 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6631 ++vcpu->stat.insn_emulation;
1d2887e2 6632 if (r != EMULATION_OK) {
b4000606 6633 if ((emulation_type & EMULTYPE_TRAP_UD) ||
c83fad65
SC		 6634 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6635 kvm_queue_exception(vcpu, UD_VECTOR);
6636 return EMULATE_DONE;
6637 }
991eebf9
GN		 6638 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6639 emulation_type))
bbd9b64e 6640 return EMULATE_DONE;
8530a79c 6641 if (ctxt->have_exception) {
c8848cee
JD		 6642 /*
6643 * #UD should result in just EMULATION_FAILED, and trap-like
6644 * exception should not be encountered during decode.
6645 */
6646 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6647 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8530a79c 6648 inject_emulated_exception(vcpu);
6ea6e843 6649 return EMULATE_DONE;
8530a79c 6650 }
e2366171 6651 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6652 }
6653 }
6654
42cbf068
SC		 6655 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6656 !is_vmware_backdoor_opcode(ctxt)) {
6657 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6658 return EMULATE_DONE;
6659 }
04789b66 6660
ba8afb6b 6661 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6662 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6663 if (ctxt->eflags & X86_EFLAGS_RF)
6664 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
97413d29 6665 kvm_x86_ops->set_interrupt_shadow(vcpu, 0);
ba8afb6b
GN		 6666 return EMULATE_DONE;
6667 }
6668
1cb3f3ae
XG		 6669 if (retry_instruction(ctxt, cr2, emulation_type))
6670 return EMULATE_DONE;
6671
7ae441ea 6672 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6673 changes registers values during IO operation */
7ae441ea
GN		 6674 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6675 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6676 emulator_invalidate_register_cache(ctxt);
7ae441ea 6677 }
4d2179e1 6678
5cd21917 6679restart:
0f89b207
TL		 6680 /* Save the faulting GPA (cr2) in the address field */
6681 ctxt->exception.address = cr2;
6682
9d74191a 6683 r = x86_emulate_insn(ctxt);
bbd9b64e 6684
775fde86
JR		 6685 if (r == EMULATION_INTERCEPTED)
6686 return EMULATE_DONE;
6687
d2ddd1c4 6688 if (r == EMULATION_FAILED) {
991eebf9
GN		 6689 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6690 emulation_type))
c3cd7ffa
GN		 6691 return EMULATE_DONE;
6692
e2366171 6693 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6694 }
6695
9d74191a 6696 if (ctxt->have_exception) {
d2ddd1c4 6697 r = EMULATE_DONE;
ef54bcfe
PB		 6698 if (inject_emulated_exception(vcpu))
6699 return r;
d2ddd1c4 6700 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6701 if (!vcpu->arch.pio.in) {
6702 /* FIXME: return into emulator if single-stepping. */
3457e419 6703 vcpu->arch.pio.count = 0;
0912c977 6704 } else {
7ae441ea 6705 writeback = false;
716d51ab
GN		 6706 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6707 }
ac0a48c3 6708 r = EMULATE_USER_EXIT;
7ae441ea 6709 } else if (vcpu->mmio_needed) {
bc8a0aaf
SC		 6710 ++vcpu->stat.mmio_exits;
6711
7ae441ea
GN		 6712 if (!vcpu->mmio_is_write)
6713 writeback = false;
ac0a48c3 6714 r = EMULATE_USER_EXIT;
716d51ab 6715 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6716 } else if (r == EMULATION_RESTART)
5cd21917 6717 goto restart;
d2ddd1c4
GN		 6718 else
6719 r = EMULATE_DONE;
f850e2e6 6720
7ae441ea 6721 if (writeback) {
6addfc42 6722 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6723 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6724 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
38827dbd 6725 if (!ctxt->have_exception ||
75ee23b3
SC		 6726 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6727 kvm_rip_write(vcpu, ctxt->eip);
6728 if (r == EMULATE_DONE && ctxt->tf)
120c2c4f 6729 r = kvm_vcpu_do_singlestep(vcpu);
38827dbd 6730 __kvm_set_rflags(vcpu, ctxt->eflags);
75ee23b3 6731 }
6addfc42
PB		 6732
6733 /*
6734 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6735 * do nothing, and it will be requested again as soon as
6736 * the shadow expires. But we still need to check here,
6737 * because POPF has no interrupt shadow.
6738 */
6739 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6740 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6741 } else
6742 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6743
6744 return r;
de7d789a 6745}
c60658d1
SC		 6746
6747int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6748{
6749 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6750}
6751EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6752
6753int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6754 void *insn, int insn_len)
6755{
6756 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6757}
6758EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6759
8764ed55
SC		 6760static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6761{
6762 vcpu->arch.pio.count = 0;
6763 return 1;
6764}
6765
45def77e
SC		 6766static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6767{
6768 vcpu->arch.pio.count = 0;
6769
6770 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6771 return 1;
6772
6773 return kvm_skip_emulated_instruction(vcpu);
6774}
6775
dca7f128
SC		 6776static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6777 unsigned short port)
de7d789a 6778{
de3cd117 6779 unsigned long val = kvm_rax_read(vcpu);
ca1d4a9e
AK		 6780 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6781 size, port, &val, 1);
8764ed55
SC		 6782 if (ret)
6783 return ret;
45def77e 6784
8764ed55
SC		 6785 /*
6786 * Workaround userspace that relies on old KVM behavior of %rip being
6787 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6788 */
6789 if (port == 0x7e &&
6790 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6791 vcpu->arch.complete_userspace_io =
6792 complete_fast_pio_out_port_0x7e;
6793 kvm_skip_emulated_instruction(vcpu);
6794 } else {
45def77e
SC		 6795 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6796 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6797 }
8764ed55 6798 return 0;
de7d789a 6799}
de7d789a 6800
8370c3d0
TL		 6801static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6802{
6803 unsigned long val;
6804
6805 /* We should only ever be called with arch.pio.count equal to 1 */
6806 BUG_ON(vcpu->arch.pio.count != 1);
6807
45def77e
SC		 6808 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6809 vcpu->arch.pio.count = 0;
6810 return 1;
6811 }
6812
8370c3d0 6813 /* For size less than 4 we merge, else we zero extend */
de3cd117 6814 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6815
6816 /*
6817 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6818 * the copy and tracing
6819 */
6820 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6821 vcpu->arch.pio.port, &val, 1);
de3cd117 6822 kvm_rax_write(vcpu, val);
8370c3d0 6823
45def77e 6824 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6825}
6826
dca7f128
SC		 6827static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6828 unsigned short port)
8370c3d0
TL		 6829{
6830 unsigned long val;
6831 int ret;
6832
6833 /* For size less than 4 we merge, else we zero extend */
de3cd117 6834 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6835
6836 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6837 &val, 1);
6838 if (ret) {
de3cd117 6839 kvm_rax_write(vcpu, val);
8370c3d0
TL		 6840 return ret;
6841 }
6842
45def77e 6843 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6844 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6845
6846 return 0;
6847}
dca7f128
SC		 6848
6849int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6850{
45def77e 6851 int ret;
dca7f128 6852
dca7f128 6853 if (in)
45def77e 6854 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6855 else
45def77e
SC		 6856 ret = kvm_fast_pio_out(vcpu, size, port);
6857 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 6858}
6859EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6860
251a5fd6 6861static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6862{
0a3aee0d 6863 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6864 return 0;
8cfdc000
ZA		 6865}
6866
6867static void tsc_khz_changed(void *data)
c8076604 6868{
8cfdc000
ZA		 6869 struct cpufreq_freqs *freq = data;
6870 unsigned long khz = 0;
6871
6872 if (data)
6873 khz = freq->new;
6874 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6875 khz = cpufreq_quick_get(raw_smp_processor_id());
6876 if (!khz)
6877 khz = tsc_khz;
0a3aee0d 6878 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6879}
6880
5fa4ec9c 6881#ifdef CONFIG_X86_64
0092e434
VK		 6882static void kvm_hyperv_tsc_notifier(void)
6883{
0092e434
VK		 6884 struct kvm *kvm;
6885 struct kvm_vcpu *vcpu;
6886 int cpu;
6887
0d9ce162 6888 mutex_lock(&kvm_lock);
0092e434
VK		 6889 list_for_each_entry(kvm, &vm_list, vm_list)
6890 kvm_make_mclock_inprogress_request(kvm);
6891
6892 hyperv_stop_tsc_emulation();
6893
6894 /* TSC frequency always matches when on Hyper-V */
6895 for_each_present_cpu(cpu)
6896 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6897 kvm_max_guest_tsc_khz = tsc_khz;
6898
6899 list_for_each_entry(kvm, &vm_list, vm_list) {
6900 struct kvm_arch *ka = &kvm->arch;
6901
6902 spin_lock(&ka->pvclock_gtod_sync_lock);
6903
6904 pvclock_update_vm_gtod_copy(kvm);
6905
6906 kvm_for_each_vcpu(cpu, vcpu, kvm)
6907 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6908
6909 kvm_for_each_vcpu(cpu, vcpu, kvm)
6910 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6911
6912 spin_unlock(&ka->pvclock_gtod_sync_lock);
6913 }
0d9ce162 6914 mutex_unlock(&kvm_lock);
0092e434 6915}
5fa4ec9c 6916#endif
0092e434 6917
df24014a 6918static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
c8076604 6919{
c8076604
GH		 6920 struct kvm *kvm;
6921 struct kvm_vcpu *vcpu;
6922 int i, send_ipi = 0;
6923
8cfdc000
ZA		 6924 /*
6925 * We allow guests to temporarily run on slowing clocks,
6926 * provided we notify them after, or to run on accelerating
6927 * clocks, provided we notify them before. Thus time never
6928 * goes backwards.
6929 *
6930 * However, we have a problem. We can't atomically update
6931 * the frequency of a given CPU from this function; it is
6932 * merely a notifier, which can be called from any CPU.
6933 * Changing the TSC frequency at arbitrary points in time
6934 * requires a recomputation of local variables related to
6935 * the TSC for each VCPU. We must flag these local variables
6936 * to be updated and be sure the update takes place with the
6937 * new frequency before any guests proceed.
6938 *
6939 * Unfortunately, the combination of hotplug CPU and frequency
6940 * change creates an intractable locking scenario; the order
6941 * of when these callouts happen is undefined with respect to
6942 * CPU hotplug, and they can race with each other. As such,
6943 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6944 * undefined; you can actually have a CPU frequency change take
6945 * place in between the computation of X and the setting of the
6946 * variable. To protect against this problem, all updates of
6947 * the per_cpu tsc_khz variable are done in an interrupt
6948 * protected IPI, and all callers wishing to update the value
6949 * must wait for a synchronous IPI to complete (which is trivial
6950 * if the caller is on the CPU already). This establishes the
6951 * necessary total order on variable updates.
6952 *
6953 * Note that because a guest time update may take place
6954 * anytime after the setting of the VCPU's request bit, the
6955 * correct TSC value must be set before the request. However,
6956 * to ensure the update actually makes it to any guest which
6957 * starts running in hardware virtualization between the set
6958 * and the acquisition of the spinlock, we must also ping the
6959 * CPU after setting the request bit.
6960 *
6961 */
6962
df24014a 6963 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6964
0d9ce162 6965 mutex_lock(&kvm_lock);
c8076604 6966 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6967 kvm_for_each_vcpu(i, vcpu, kvm) {
df24014a 6968 if (vcpu->cpu != cpu)
c8076604 6969 continue;
c285545f 6970 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0d9ce162 6971 if (vcpu->cpu != raw_smp_processor_id())
8cfdc000 6972 send_ipi = 1;
c8076604
GH		 6973 }
6974 }
0d9ce162 6975 mutex_unlock(&kvm_lock);
c8076604
GH		 6976
6977 if (freq->old < freq->new && send_ipi) {
6978 /*
6979 * We upscale the frequency. Must make the guest
6980 * doesn't see old kvmclock values while running with
6981 * the new frequency, otherwise we risk the guest sees
6982 * time go backwards.
6983 *
6984 * In case we update the frequency for another cpu
6985 * (which might be in guest context) send an interrupt
6986 * to kick the cpu out of guest context. Next time
6987 * guest context is entered kvmclock will be updated,
6988 * so the guest will not see stale values.
6989 */
df24014a 6990 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6991 }
df24014a
VK		 6992}
6993
6994static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6995 void *data)
6996{
6997 struct cpufreq_freqs *freq = data;
6998 int cpu;
6999
7000 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7001 return 0;
7002 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7003 return 0;
7004
7005 for_each_cpu(cpu, freq->policy->cpus)
7006 __kvmclock_cpufreq_notifier(freq, cpu);
7007
c8076604
GH		 7008 return 0;
7009}
7010
7011static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 7012 .notifier_call = kvmclock_cpufreq_notifier
7013};
7014
251a5fd6 7015static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 7016{
251a5fd6
SAS		 7017 tsc_khz_changed(NULL);
7018 return 0;
8cfdc000
ZA		 7019}
7020
b820cc0c
ZA		 7021static void kvm_timer_init(void)
7022{
c285545f 7023 max_tsc_khz = tsc_khz;
460dd42e 7024
b820cc0c 7025 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 7026#ifdef CONFIG_CPU_FREQ
7027 struct cpufreq_policy policy;
758f588d
BP		 7028 int cpu;
7029
c285545f 7030 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 7031 cpu = get_cpu();
7032 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 7033 if (policy.cpuinfo.max_freq)
7034 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 7035 put_cpu();
c285545f 7036#endif
b820cc0c
ZA		 7037 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7038 CPUFREQ_TRANSITION_NOTIFIER);
7039 }
460dd42e 7040
73c1b41e 7041 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 7042 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 7043}
7044
dd60d217
AK		 7045DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7046EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 7047
f5132b01 7048int kvm_is_in_guest(void)
ff9d07a0 7049{
086c9855 7050 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 7051}
7052
7053static int kvm_is_user_mode(void)
7054{
7055 int user_mode = 3;
dcf46b94 7056
086c9855
AS		 7057 if (__this_cpu_read(current_vcpu))
7058 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 7059
ff9d07a0
ZY		 7060 return user_mode != 0;
7061}
7062
7063static unsigned long kvm_get_guest_ip(void)
7064{
7065 unsigned long ip = 0;
dcf46b94 7066
086c9855
AS		 7067 if (__this_cpu_read(current_vcpu))
7068 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 7069
ff9d07a0
ZY		 7070 return ip;
7071}
7072
8479e04e
LK		 7073static void kvm_handle_intel_pt_intr(void)
7074{
7075 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7076
7077 kvm_make_request(KVM_REQ_PMI, vcpu);
7078 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7079 (unsigned long *)&vcpu->arch.pmu.global_status);
7080}
7081
ff9d07a0
ZY		 7082static struct perf_guest_info_callbacks kvm_guest_cbs = {
7083 .is_in_guest = kvm_is_in_guest,
7084 .is_user_mode = kvm_is_user_mode,
7085 .get_guest_ip = kvm_get_guest_ip,
8479e04e 7086 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
ff9d07a0
ZY		 7087};
7088
16e8d74d
MT		 7089#ifdef CONFIG_X86_64
7090static void pvclock_gtod_update_fn(struct work_struct *work)
7091{
d828199e
MT		 7092 struct kvm *kvm;
7093
7094 struct kvm_vcpu *vcpu;
7095 int i;
7096
0d9ce162 7097 mutex_lock(&kvm_lock);
d828199e
MT		 7098 list_for_each_entry(kvm, &vm_list, vm_list)
7099 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 7100 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 7101 atomic_set(&kvm_guest_has_master_clock, 0);
0d9ce162 7102 mutex_unlock(&kvm_lock);
16e8d74d
MT		 7103}
7104
7105static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7106
7107/*
7108 * Notification about pvclock gtod data update.
7109 */
7110static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7111 void *priv)
7112{
7113 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7114 struct timekeeper *tk = priv;
7115
7116 update_pvclock_gtod(tk);
7117
7118 /* disable master clock if host does not trust, or does not
b0c39dc6 7119 * use, TSC based clocksource.
16e8d74d 7120 */
b0c39dc6 7121 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 7122 atomic_read(&kvm_guest_has_master_clock) != 0)
7123 queue_work(system_long_wq, &pvclock_gtod_work);
7124
7125 return 0;
7126}
7127
7128static struct notifier_block pvclock_gtod_notifier = {
7129 .notifier_call = pvclock_gtod_notify,
7130};
7131#endif
7132
f8c16bba 7133int kvm_arch_init(void *opaque)
043405e1 7134{
b820cc0c 7135 int r;
6b61edf7 7136 struct kvm_x86_ops *ops = opaque;
f8c16bba 7137
f8c16bba
ZX		 7138 if (kvm_x86_ops) {
7139 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 7140 r = -EEXIST;
7141 goto out;
f8c16bba
ZX		 7142 }
7143
7144 if (!ops->cpu_has_kvm_support()) {
7145 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 7146 r = -EOPNOTSUPP;
7147 goto out;
f8c16bba
ZX		 7148 }
7149 if (ops->disabled_by_bios()) {
7150 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 7151 r = -EOPNOTSUPP;
7152 goto out;
f8c16bba
ZX		 7153 }
7154
b666a4b6
MO		 7155 /*
7156 * KVM explicitly assumes that the guest has an FPU and
7157 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7158 * vCPU's FPU state as a fxregs_state struct.
7159 */
7160 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7161 printk(KERN_ERR "kvm: inadequate fpu\n");
7162 r = -EOPNOTSUPP;
7163 goto out;
7164 }
7165
013f6a5d 7166 r = -ENOMEM;
ed8e4812 7167 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 7168 __alignof__(struct fpu), SLAB_ACCOUNT,
7169 NULL);
7170 if (!x86_fpu_cache) {
7171 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7172 goto out;
7173 }
7174
013f6a5d
MT		 7175 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7176 if (!shared_msrs) {
7177 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 7178 goto out_free_x86_fpu_cache;
013f6a5d
MT		 7179 }
7180
97db56ce
AK		 7181 r = kvm_mmu_module_init();
7182 if (r)
013f6a5d 7183 goto out_free_percpu;
97db56ce 7184
f8c16bba 7185 kvm_x86_ops = ops;
920c8377 7186
7b52345e 7187 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 7188 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 7189 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 7190 kvm_timer_init();
c8076604 7191
ff9d07a0
ZY		 7192 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7193
d366bf7e 7194 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 7195 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7196
c5cc421b 7197 kvm_lapic_init();
0c5f81da
WL		 7198 if (pi_inject_timer == -1)
7199 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
16e8d74d
MT		 7200#ifdef CONFIG_X86_64
7201 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 7202
5fa4ec9c 7203 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 7204 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 7205#endif
7206
f8c16bba 7207 return 0;
56c6d28a 7208
013f6a5d
MT		 7209out_free_percpu:
7210 free_percpu(shared_msrs);
b666a4b6
MO		 7211out_free_x86_fpu_cache:
7212 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7213out:
56c6d28a 7214 return r;
043405e1 7215}
8776e519 7216
f8c16bba
ZX		 7217void kvm_arch_exit(void)
7218{
0092e434 7219#ifdef CONFIG_X86_64
5fa4ec9c 7220 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 7221 clear_hv_tscchange_cb();
7222#endif
cef84c30 7223 kvm_lapic_exit();
ff9d07a0
ZY		 7224 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7225
888d256e
JK		 7226 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7227 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7228 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7229 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7230#ifdef CONFIG_X86_64
7231 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7232#endif
f8c16bba 7233 kvm_x86_ops = NULL;
56c6d28a 7234 kvm_mmu_module_exit();
013f6a5d 7235 free_percpu(shared_msrs);
b666a4b6 7236 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7237}
f8c16bba 7238
5cb56059 7239int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7240{
7241 ++vcpu->stat.halt_exits;
35754c98 7242 if (lapic_in_kernel(vcpu)) {
a4535290 7243 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7244 return 1;
7245 } else {
7246 vcpu->run->exit_reason = KVM_EXIT_HLT;
7247 return 0;
7248 }
7249}
5cb56059
JS		 7250EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7251
7252int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7253{
6affcbed
KH		 7254 int ret = kvm_skip_emulated_instruction(vcpu);
7255 /*
7256 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7257 * KVM_EXIT_DEBUG here.
7258 */
7259 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7260}
8776e519
HB		 7261EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7262
8ef81a9a 7263#ifdef CONFIG_X86_64
55dd00a7
MT		 7264static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7265 unsigned long clock_type)
7266{
7267 struct kvm_clock_pairing clock_pairing;
899a31f5 7268 struct timespec64 ts;
80fbd89c 7269 u64 cycle;
55dd00a7
MT		 7270 int ret;
7271
7272 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7273 return -KVM_EOPNOTSUPP;
7274
7275 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7276 return -KVM_EOPNOTSUPP;
7277
7278 clock_pairing.sec = ts.tv_sec;
7279 clock_pairing.nsec = ts.tv_nsec;
7280 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7281 clock_pairing.flags = 0;
bcbfbd8e 7282 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7283
7284 ret = 0;
7285 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7286 sizeof(struct kvm_clock_pairing)))
7287 ret = -KVM_EFAULT;
7288
7289 return ret;
7290}
8ef81a9a 7291#endif
55dd00a7 7292
6aef266c
SV		 7293/*
7294 * kvm_pv_kick_cpu_op: Kick a vcpu.
7295 *
7296 * @apicid - apicid of vcpu to be kicked.
7297 */
7298static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7299{
24d2166b 7300 struct kvm_lapic_irq lapic_irq;
6aef266c 7301
24d2166b
R		 7302 lapic_irq.shorthand = 0;
7303 lapic_irq.dest_mode = 0;
ebd28fcb 7304 lapic_irq.level = 0;
24d2166b 7305 lapic_irq.dest_id = apicid;
93bbf0b8 7306 lapic_irq.msi_redir_hint = false;
6aef266c 7307
24d2166b 7308 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7309 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7310}
7311
d62caabb
AS		 7312void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7313{
f7589cca
PB		 7314 if (!lapic_in_kernel(vcpu)) {
7315 WARN_ON_ONCE(vcpu->arch.apicv_active);
7316 return;
7317 }
7318 if (!vcpu->arch.apicv_active)
7319 return;
7320
d62caabb
AS		 7321 vcpu->arch.apicv_active = false;
7322 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7323}
7324
71506297
WL		 7325static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7326{
7327 struct kvm_vcpu *target = NULL;
7328 struct kvm_apic_map *map;
7329
7330 rcu_read_lock();
7331 map = rcu_dereference(kvm->arch.apic_map);
7332
7333 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7334 target = map->phys_map[dest_id]->vcpu;
7335
7336 rcu_read_unlock();
7337
266e85a5 7338 if (target && READ_ONCE(target->ready))
71506297
WL		 7339 kvm_vcpu_yield_to(target);
7340}
7341
8776e519
HB		 7342int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7343{
7344 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7345 int op_64_bit;
8776e519 7346
696ca779
RK		 7347 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7348 return kvm_hv_hypercall(vcpu);
55cd8e5a 7349
de3cd117
SC		 7350 nr = kvm_rax_read(vcpu);
7351 a0 = kvm_rbx_read(vcpu);
7352 a1 = kvm_rcx_read(vcpu);
7353 a2 = kvm_rdx_read(vcpu);
7354 a3 = kvm_rsi_read(vcpu);
8776e519 7355
229456fc 7356 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7357
a449c7aa
NA		 7358 op_64_bit = is_64_bit_mode(vcpu);
7359 if (!op_64_bit) {
8776e519
HB		 7360 nr &= 0xFFFFFFFF;
7361 a0 &= 0xFFFFFFFF;
7362 a1 &= 0xFFFFFFFF;
7363 a2 &= 0xFFFFFFFF;
7364 a3 &= 0xFFFFFFFF;
7365 }
7366
07708c4a
JK		 7367 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7368 ret = -KVM_EPERM;
696ca779 7369 goto out;
07708c4a
JK		 7370 }
7371
8776e519 7372 switch (nr) {
b93463aa
AK		 7373 case KVM_HC_VAPIC_POLL_IRQ:
7374 ret = 0;
7375 break;
6aef266c
SV		 7376 case KVM_HC_KICK_CPU:
7377 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
266e85a5 7378 kvm_sched_yield(vcpu->kvm, a1);
6aef266c
SV		 7379 ret = 0;
7380 break;
8ef81a9a 7381#ifdef CONFIG_X86_64
55dd00a7
MT		 7382 case KVM_HC_CLOCK_PAIRING:
7383 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7384 break;
1ed199a4 7385#endif
4180bf1b
WL		 7386 case KVM_HC_SEND_IPI:
7387 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7388 break;
71506297
WL		 7389 case KVM_HC_SCHED_YIELD:
7390 kvm_sched_yield(vcpu->kvm, a0);
7391 ret = 0;
7392 break;
8776e519
HB		 7393 default:
7394 ret = -KVM_ENOSYS;
7395 break;
7396 }
696ca779 7397out:
a449c7aa
NA		 7398 if (!op_64_bit)
7399 ret = (u32)ret;
de3cd117 7400 kvm_rax_write(vcpu, ret);
6356ee0c 7401
f11c3a8d 7402 ++vcpu->stat.hypercalls;
6356ee0c 7403 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7404}
7405EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7406
b6785def 7407static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7408{
d6aa1000 7409 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7410 char instruction[3];
5fdbf976 7411 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7412
8776e519 7413 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7414
ce2e852e
DV		 7415 return emulator_write_emulated(ctxt, rip, instruction, 3,
7416 &ctxt->exception);
8776e519
HB		 7417}
7418
851ba692 7419static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7420{
782d422b
MG		 7421 return vcpu->run->request_interrupt_window &&
7422 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7423}
7424
851ba692 7425static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7426{
851ba692
AK		 7427 struct kvm_run *kvm_run = vcpu->run;
7428
91586a3b 7429 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7430 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7431 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7432 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7433 kvm_run->ready_for_interrupt_injection =
7434 pic_in_kernel(vcpu->kvm) ||
782d422b 7435 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7436}
7437
95ba8273
GN		 7438static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7439{
7440 int max_irr, tpr;
7441
7442 if (!kvm_x86_ops->update_cr8_intercept)
7443 return;
7444
bce87cce 7445 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7446 return;
7447
d62caabb
AS		 7448 if (vcpu->arch.apicv_active)
7449 return;
7450
8db3baa2
GN		 7451 if (!vcpu->arch.apic->vapic_addr)
7452 max_irr = kvm_lapic_find_highest_irr(vcpu);
7453 else
7454 max_irr = -1;
95ba8273
GN		 7455
7456 if (max_irr != -1)
7457 max_irr >>= 4;
7458
7459 tpr = kvm_lapic_get_cr8(vcpu);
7460
7461 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7462}
7463
b6b8a145 7464static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7465{
b6b8a145
JK		 7466 int r;
7467
95ba8273 7468 /* try to reinject previous events if any */
664f8e26 7469
1a680e35
LA		 7470 if (vcpu->arch.exception.injected)
7471 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7472 /*
a042c26f
LA		 7473 * Do not inject an NMI or interrupt if there is a pending
7474 * exception. Exceptions and interrupts are recognized at
7475 * instruction boundaries, i.e. the start of an instruction.
7476 * Trap-like exceptions, e.g. #DB, have higher priority than
7477 * NMIs and interrupts, i.e. traps are recognized before an
7478 * NMI/interrupt that's pending on the same instruction.
7479 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7480 * priority, but are only generated (pended) during instruction
7481 * execution, i.e. a pending fault-like exception means the
7482 * fault occurred on the *previous* instruction and must be
7483 * serviced prior to recognizing any new events in order to
7484 * fully complete the previous instruction.
664f8e26 7485 */
1a680e35
LA		 7486 else if (!vcpu->arch.exception.pending) {
7487 if (vcpu->arch.nmi_injected)
664f8e26 7488 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7489 else if (vcpu->arch.interrupt.injected)
664f8e26 7490 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7491 }
7492
1a680e35
LA		 7493 /*
7494 * Call check_nested_events() even if we reinjected a previous event
7495 * in order for caller to determine if it should require immediate-exit
7496 * from L2 to L1 due to pending L1 events which require exit
7497 * from L2 to L1.
7498 */
664f8e26
WL		 7499 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7500 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7501 if (r != 0)
7502 return r;
7503 }
7504
7505 /* try to inject new event if pending */
b59bb7bd 7506 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7507 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7508 vcpu->arch.exception.has_error_code,
7509 vcpu->arch.exception.error_code);
d6e8c854 7510
1a680e35 7511 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7512 vcpu->arch.exception.pending = false;
7513 vcpu->arch.exception.injected = true;
7514
d6e8c854
NA		 7515 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7516 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7517 X86_EFLAGS_RF);
7518
f10c729f
JM		 7519 if (vcpu->arch.exception.nr == DB_VECTOR) {
7520 /*
7521 * This code assumes that nSVM doesn't use
7522 * check_nested_events(). If it does, the
7523 * DR6/DR7 changes should happen before L1
7524 * gets a #VMEXIT for an intercepted #DB in
7525 * L2. (Under VMX, on the other hand, the
7526 * DR6/DR7 changes should not happen in the
7527 * event of a VM-exit to L1 for an intercepted
7528 * #DB in L2.)
7529 */
7530 kvm_deliver_exception_payload(vcpu);
7531 if (vcpu->arch.dr7 & DR7_GD) {
7532 vcpu->arch.dr7 &= ~DR7_GD;
7533 kvm_update_dr7(vcpu);
7534 }
6bdf0662
NA		 7535 }
7536
cfcd20e5 7537 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7538 }
7539
7540 /* Don't consider new event if we re-injected an event */
7541 if (kvm_event_needs_reinjection(vcpu))
7542 return 0;
7543
7544 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7545 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7546 vcpu->arch.smi_pending = false;
52797bf9 7547 ++vcpu->arch.smi_count;
ee2cd4b7 7548 enter_smm(vcpu);
c43203ca 7549 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7550 --vcpu->arch.nmi_pending;
7551 vcpu->arch.nmi_injected = true;
7552 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7553 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7554 /*
7555 * Because interrupts can be injected asynchronously, we are
7556 * calling check_nested_events again here to avoid a race condition.
7557 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7558 * proposal and current concerns. Perhaps we should be setting
7559 * KVM_REQ_EVENT only on certain events and not unconditionally?
7560 */
7561 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7562 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7563 if (r != 0)
7564 return r;
7565 }
95ba8273 7566 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7567 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7568 false);
7569 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7570 }
7571 }
ee2cd4b7 7572
b6b8a145 7573 return 0;
95ba8273
GN		 7574}
7575
7460fb4a
AK		 7576static void process_nmi(struct kvm_vcpu *vcpu)
7577{
7578 unsigned limit = 2;
7579
7580 /*
7581 * x86 is limited to one NMI running, and one NMI pending after it.
7582 * If an NMI is already in progress, limit further NMIs to just one.
7583 * Otherwise, allow two (and we'll inject the first one immediately).
7584 */
7585 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7586 limit = 1;
7587
7588 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7589 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7590 kvm_make_request(KVM_REQ_EVENT, vcpu);
7591}
7592
ee2cd4b7 7593static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7594{
7595 u32 flags = 0;
7596 flags |= seg->g << 23;
7597 flags |= seg->db << 22;
7598 flags |= seg->l << 21;
7599 flags |= seg->avl << 20;
7600 flags |= seg->present << 15;
7601 flags |= seg->dpl << 13;
7602 flags |= seg->s << 12;
7603 flags |= seg->type << 8;
7604 return flags;
7605}
7606
ee2cd4b7 7607static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7608{
7609 struct kvm_segment seg;
7610 int offset;
7611
7612 kvm_get_segment(vcpu, &seg, n);
7613 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7614
7615 if (n < 3)
7616 offset = 0x7f84 + n * 12;
7617 else
7618 offset = 0x7f2c + (n - 3) * 12;
7619
7620 put_smstate(u32, buf, offset + 8, seg.base);
7621 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7622 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7623}
7624
efbb288a 7625#ifdef CONFIG_X86_64
ee2cd4b7 7626static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7627{
7628 struct kvm_segment seg;
7629 int offset;
7630 u16 flags;
7631
7632 kvm_get_segment(vcpu, &seg, n);
7633 offset = 0x7e00 + n * 16;
7634
ee2cd4b7 7635 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7636 put_smstate(u16, buf, offset, seg.selector);
7637 put_smstate(u16, buf, offset + 2, flags);
7638 put_smstate(u32, buf, offset + 4, seg.limit);
7639 put_smstate(u64, buf, offset + 8, seg.base);
7640}
efbb288a 7641#endif
660a5d51 7642
ee2cd4b7 7643static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7644{
7645 struct desc_ptr dt;
7646 struct kvm_segment seg;
7647 unsigned long val;
7648 int i;
7649
7650 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7651 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7652 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7653 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7654
7655 for (i = 0; i < 8; i++)
7656 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7657
7658 kvm_get_dr(vcpu, 6, &val);
7659 put_smstate(u32, buf, 0x7fcc, (u32)val);
7660 kvm_get_dr(vcpu, 7, &val);
7661 put_smstate(u32, buf, 0x7fc8, (u32)val);
7662
7663 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7664 put_smstate(u32, buf, 0x7fc4, seg.selector);
7665 put_smstate(u32, buf, 0x7f64, seg.base);
7666 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7667 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7668
7669 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7670 put_smstate(u32, buf, 0x7fc0, seg.selector);
7671 put_smstate(u32, buf, 0x7f80, seg.base);
7672 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7673 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7674
7675 kvm_x86_ops->get_gdt(vcpu, &dt);
7676 put_smstate(u32, buf, 0x7f74, dt.address);
7677 put_smstate(u32, buf, 0x7f70, dt.size);
7678
7679 kvm_x86_ops->get_idt(vcpu, &dt);
7680 put_smstate(u32, buf, 0x7f58, dt.address);
7681 put_smstate(u32, buf, 0x7f54, dt.size);
7682
7683 for (i = 0; i < 6; i++)
ee2cd4b7 7684 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7685
7686 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7687
7688 /* revision id */
7689 put_smstate(u32, buf, 0x7efc, 0x00020000);
7690 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7691}
7692
b68f3cc7 7693#ifdef CONFIG_X86_64
ee2cd4b7 7694static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7695{
660a5d51
PB		 7696 struct desc_ptr dt;
7697 struct kvm_segment seg;
7698 unsigned long val;
7699 int i;
7700
7701 for (i = 0; i < 16; i++)
7702 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7703
7704 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7705 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7706
7707 kvm_get_dr(vcpu, 6, &val);
7708 put_smstate(u64, buf, 0x7f68, val);
7709 kvm_get_dr(vcpu, 7, &val);
7710 put_smstate(u64, buf, 0x7f60, val);
7711
7712 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7713 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7714 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7715
7716 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7717
7718 /* revision id */
7719 put_smstate(u32, buf, 0x7efc, 0x00020064);
7720
7721 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7722
7723 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7724 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7725 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7726 put_smstate(u32, buf, 0x7e94, seg.limit);
7727 put_smstate(u64, buf, 0x7e98, seg.base);
7728
7729 kvm_x86_ops->get_idt(vcpu, &dt);
7730 put_smstate(u32, buf, 0x7e84, dt.size);
7731 put_smstate(u64, buf, 0x7e88, dt.address);
7732
7733 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7734 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7735 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7736 put_smstate(u32, buf, 0x7e74, seg.limit);
7737 put_smstate(u64, buf, 0x7e78, seg.base);
7738
7739 kvm_x86_ops->get_gdt(vcpu, &dt);
7740 put_smstate(u32, buf, 0x7e64, dt.size);
7741 put_smstate(u64, buf, 0x7e68, dt.address);
7742
7743 for (i = 0; i < 6; i++)
ee2cd4b7 7744 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7745}
b68f3cc7 7746#endif
660a5d51 7747
ee2cd4b7 7748static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7749{
660a5d51 7750 struct kvm_segment cs, ds;
18c3626e 7751 struct desc_ptr dt;
660a5d51
PB		 7752 char buf[512];
7753 u32 cr0;
7754
660a5d51 7755 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7756 memset(buf, 0, 512);
b68f3cc7 7757#ifdef CONFIG_X86_64
d6321d49 7758 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7759 enter_smm_save_state_64(vcpu, buf);
660a5d51 7760 else
b68f3cc7 7761#endif
ee2cd4b7 7762 enter_smm_save_state_32(vcpu, buf);
660a5d51 7763
0234bf88
LP		 7764 /*
7765 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7766 * vCPU state (e.g. leave guest mode) after we've saved the state into
7767 * the SMM state-save area.
7768 */
7769 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7770
7771 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7772 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7773
7774 if (kvm_x86_ops->get_nmi_mask(vcpu))
7775 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7776 else
7777 kvm_x86_ops->set_nmi_mask(vcpu, true);
7778
7779 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7780 kvm_rip_write(vcpu, 0x8000);
7781
7782 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7783 kvm_x86_ops->set_cr0(vcpu, cr0);
7784 vcpu->arch.cr0 = cr0;
7785
7786 kvm_x86_ops->set_cr4(vcpu, 0);
7787
18c3626e
PB		 7788 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7789 dt.address = dt.size = 0;
7790 kvm_x86_ops->set_idt(vcpu, &dt);
7791
660a5d51
PB		 7792 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7793
7794 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7795 cs.base = vcpu->arch.smbase;
7796
7797 ds.selector = 0;
7798 ds.base = 0;
7799
7800 cs.limit = ds.limit = 0xffffffff;
7801 cs.type = ds.type = 0x3;
7802 cs.dpl = ds.dpl = 0;
7803 cs.db = ds.db = 0;
7804 cs.s = ds.s = 1;
7805 cs.l = ds.l = 0;
7806 cs.g = ds.g = 1;
7807 cs.avl = ds.avl = 0;
7808 cs.present = ds.present = 1;
7809 cs.unusable = ds.unusable = 0;
7810 cs.padding = ds.padding = 0;
7811
7812 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7813 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7814 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7815 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7816 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7817 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7818
b68f3cc7 7819#ifdef CONFIG_X86_64
d6321d49 7820 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7821 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7822#endif
660a5d51
PB		 7823
7824 kvm_update_cpuid(vcpu);
7825 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7826}
7827
ee2cd4b7 7828static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7829{
7830 vcpu->arch.smi_pending = true;
7831 kvm_make_request(KVM_REQ_EVENT, vcpu);
7832}
7833
2860c4b1
PB		 7834void kvm_make_scan_ioapic_request(struct kvm *kvm)
7835{
7836 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7837}
7838
3d81bc7e 7839static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7840{
dcbd3e49 7841 if (!kvm_apic_present(vcpu))
3d81bc7e 7842 return;
c7c9c56c 7843
6308630b 7844 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7845
b053b2ae 7846 if (irqchip_split(vcpu->kvm))
6308630b 7847 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7848 else {
fa59cc00 7849 if (vcpu->arch.apicv_active)
d62caabb 7850 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7851 if (ioapic_in_kernel(vcpu->kvm))
7852 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7853 }
e40ff1d6
LA		 7854
7855 if (is_guest_mode(vcpu))
7856 vcpu->arch.load_eoi_exitmap_pending = true;
7857 else
7858 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7859}
7860
7861static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7862{
7863 u64 eoi_exit_bitmap[4];
7864
7865 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7866 return;
7867
5c919412
AS		 7868 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7869 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7870 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7871}
7872
93065ac7
MH		 7873int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7874 unsigned long start, unsigned long end,
7875 bool blockable)
b1394e74
RK		 7876{
7877 unsigned long apic_address;
7878
7879 /*
7880 * The physical address of apic access page is stored in the VMCS.
7881 * Update it when it becomes invalid.
7882 */
7883 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7884 if (start <= apic_address && apic_address < end)
7885 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7886
7887 return 0;
b1394e74
RK		 7888}
7889
4256f43f
TC		 7890void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7891{
c24ae0dc
TC		 7892 struct page *page = NULL;
7893
35754c98 7894 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7895 return;
7896
4256f43f
TC		 7897 if (!kvm_x86_ops->set_apic_access_page_addr)
7898 return;
7899
c24ae0dc 7900 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7901 if (is_error_page(page))
7902 return;
c24ae0dc
TC		 7903 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7904
7905 /*
7906 * Do not pin apic access page in memory, the MMU notifier
7907 * will call us again if it is migrated or swapped out.
7908 */
7909 put_page(page);
4256f43f
TC		 7910}
7911EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7912
d264ee0c
SC		 7913void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7914{
7915 smp_send_reschedule(vcpu->cpu);
7916}
7917EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7918
9357d939 7919/*
362c698f 7920 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7921 * exiting to the userspace. Otherwise, the value will be returned to the
7922 * userspace.
7923 */
851ba692 7924static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7925{
7926 int r;
62a193ed
MG		 7927 bool req_int_win =
7928 dm_request_for_irq_injection(vcpu) &&
7929 kvm_cpu_accept_dm_intr(vcpu);
7930
730dca42 7931 bool req_immediate_exit = false;
b6c7a5dc 7932
2fa6e1e1 7933 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7934 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7935 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7936 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7937 kvm_mmu_unload(vcpu);
a8eeb04a 7938 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7939 __kvm_migrate_timers(vcpu);
d828199e
MT		 7940 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7941 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7942 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7943 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7944 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7945 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7946 if (unlikely(r))
7947 goto out;
7948 }
a8eeb04a 7949 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7950 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7951 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7952 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7953 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7954 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7955 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7956 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7957 r = 0;
7958 goto out;
7959 }
a8eeb04a 7960 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7961 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7962 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7963 r = 0;
7964 goto out;
7965 }
af585b92
GN		 7966 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7967 /* Page is swapped out. Do synthetic halt */
7968 vcpu->arch.apf.halted = true;
7969 r = 1;
7970 goto out;
7971 }
c9aaa895
GC		 7972 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7973 record_steal_time(vcpu);
64d60670
PB		 7974 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7975 process_smi(vcpu);
7460fb4a
AK		 7976 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7977 process_nmi(vcpu);
f5132b01 7978 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7979 kvm_pmu_handle_event(vcpu);
f5132b01 7980 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7981 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7982 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7983 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7984 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7985 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7986 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7987 vcpu->run->eoi.vector =
7988 vcpu->arch.pending_ioapic_eoi;
7989 r = 0;
7990 goto out;
7991 }
7992 }
3d81bc7e
YZ		 7993 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7994 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7995 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7996 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7997 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7998 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7999 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8000 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8001 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8002 r = 0;
8003 goto out;
8004 }
e516cebb
AS		 8005 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8006 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8007 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8008 r = 0;
8009 goto out;
8010 }
db397571
AS		 8011 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8012 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8013 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8014 r = 0;
8015 goto out;
8016 }
f3b138c5
AS		 8017
8018 /*
8019 * KVM_REQ_HV_STIMER has to be processed after
8020 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8021 * depend on the guest clock being up-to-date
8022 */
1f4b34f8
AS		 8023 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8024 kvm_hv_process_stimers(vcpu);
2f52d58c 8025 }
b93463aa 8026
b463a6f7 8027 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 8028 ++vcpu->stat.req_event;
66450a21
JK		 8029 kvm_apic_accept_events(vcpu);
8030 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8031 r = 1;
8032 goto out;
8033 }
8034
b6b8a145
JK		 8035 if (inject_pending_event(vcpu, req_int_win) != 0)
8036 req_immediate_exit = true;
321c5658 8037 else {
cc3d967f 8038 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 8039 *
cc3d967f
LP		 8040 * SMIs have three cases:
8041 * 1) They can be nested, and then there is nothing to
8042 * do here because RSM will cause a vmexit anyway.
8043 * 2) There is an ISA-specific reason why SMI cannot be
8044 * injected, and the moment when this changes can be
8045 * intercepted.
8046 * 3) Or the SMI can be pending because
8047 * inject_pending_event has completed the injection
8048 * of an IRQ or NMI from the previous vmexit, and
8049 * then we request an immediate exit to inject the
8050 * SMI.
c43203ca
PB		 8051 */
8052 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 8053 if (!kvm_x86_ops->enable_smi_window(vcpu))
8054 req_immediate_exit = true;
321c5658
YS		 8055 if (vcpu->arch.nmi_pending)
8056 kvm_x86_ops->enable_nmi_window(vcpu);
8057 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8058 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 8059 WARN_ON(vcpu->arch.exception.pending);
321c5658 8060 }
b463a6f7
AK		 8061
8062 if (kvm_lapic_enabled(vcpu)) {
8063 update_cr8_intercept(vcpu);
8064 kvm_lapic_sync_to_vapic(vcpu);
8065 }
8066 }
8067
d8368af8
AK		 8068 r = kvm_mmu_reload(vcpu);
8069 if (unlikely(r)) {
d905c069 8070 goto cancel_injection;
d8368af8
AK		 8071 }
8072
b6c7a5dc
HB		 8073 preempt_disable();
8074
8075 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 8076
8077 /*
8078 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8079 * IPI are then delayed after guest entry, which ensures that they
8080 * result in virtual interrupt delivery.
8081 */
8082 local_irq_disable();
6b7e2d09
XG		 8083 vcpu->mode = IN_GUEST_MODE;
8084
01b71917
MT		 8085 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8086
0f127d12 8087 /*
b95234c8 8088 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 8089 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 8090 *
81b01667 8091 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 8092 * pairs with the memory barrier implicit in pi_test_and_set_on
8093 * (see vmx_deliver_posted_interrupt).
8094 *
8095 * 3) This also orders the write to mode from any reads to the page
8096 * tables done while the VCPU is running. Please see the comment
8097 * in kvm_flush_remote_tlbs.
6b7e2d09 8098 */
01b71917 8099 smp_mb__after_srcu_read_unlock();
b6c7a5dc 8100
b95234c8
PB		 8101 /*
8102 * This handles the case where a posted interrupt was
8103 * notified with kvm_vcpu_kick.
8104 */
fa59cc00
LA		 8105 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8106 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 8107
2fa6e1e1 8108 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 8109 || need_resched() || signal_pending(current)) {
6b7e2d09 8110 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8111 smp_wmb();
6c142801
AK		 8112 local_irq_enable();
8113 preempt_enable();
01b71917 8114 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 8115 r = 1;
d905c069 8116 goto cancel_injection;
6c142801
AK		 8117 }
8118
c43203ca
PB		 8119 if (req_immediate_exit) {
8120 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 8121 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 8122 }
d6185f20 8123
8b89fe1f 8124 trace_kvm_entry(vcpu->vcpu_id);
6edaa530 8125 guest_enter_irqoff();
b6c7a5dc 8126
e7517324
WL		 8127 /* The preempt notifier should have taken care of the FPU already. */
8128 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
5f409e20 8129
42dbaa5a 8130 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 8131 set_debugreg(0, 7);
8132 set_debugreg(vcpu->arch.eff_db[0], 0);
8133 set_debugreg(vcpu->arch.eff_db[1], 1);
8134 set_debugreg(vcpu->arch.eff_db[2], 2);
8135 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 8136 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 8137 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 8138 }
b6c7a5dc 8139
851ba692 8140 kvm_x86_ops->run(vcpu);
b6c7a5dc 8141
c77fb5fe
PB		 8142 /*
8143 * Do this here before restoring debug registers on the host. And
8144 * since we do this before handling the vmexit, a DR access vmexit
8145 * can (a) read the correct value of the debug registers, (b) set
8146 * KVM_DEBUGREG_WONT_EXIT again.
8147 */
8148 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 8149 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8150 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 8151 kvm_update_dr0123(vcpu);
8152 kvm_update_dr6(vcpu);
8153 kvm_update_dr7(vcpu);
8154 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 8155 }
8156
24f1e32c
FW		 8157 /*
8158 * If the guest has used debug registers, at least dr7
8159 * will be disabled while returning to the host.
8160 * If we don't have active breakpoints in the host, we don't
8161 * care about the messed up debug address registers. But if
8162 * we have some of them active, restore the old state.
8163 */
59d8eb53 8164 if (hw_breakpoint_active())
24f1e32c 8165 hw_breakpoint_restore();
42dbaa5a 8166
4ba76538 8167 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 8168
6b7e2d09 8169 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8170 smp_wmb();
a547c6db 8171
95b5a48c 8172 kvm_x86_ops->handle_exit_irqoff(vcpu);
b6c7a5dc 8173
d7a08882
SC		 8174 /*
8175 * Consume any pending interrupts, including the possible source of
8176 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8177 * An instruction is required after local_irq_enable() to fully unblock
8178 * interrupts on processors that implement an interrupt shadow, the
8179 * stat.exits increment will do nicely.
8180 */
8181 kvm_before_interrupt(vcpu);
8182 local_irq_enable();
b6c7a5dc 8183 ++vcpu->stat.exits;
d7a08882
SC		 8184 local_irq_disable();
8185 kvm_after_interrupt(vcpu);
b6c7a5dc 8186
f2485b3e 8187 guest_exit_irqoff();
ec0671d5
WL		 8188 if (lapic_in_kernel(vcpu)) {
8189 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8190 if (delta != S64_MIN) {
8191 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8192 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8193 }
8194 }
b6c7a5dc 8195
f2485b3e 8196 local_irq_enable();
b6c7a5dc
HB		 8197 preempt_enable();
8198
f656ce01 8199 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 8200
b6c7a5dc
HB		 8201 /*
8202 * Profile KVM exit RIPs:
8203 */
8204 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 8205 unsigned long rip = kvm_rip_read(vcpu);
8206 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 8207 }
8208
cc578287
ZA		 8209 if (unlikely(vcpu->arch.tsc_always_catchup))
8210 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 8211
5cfb1d5a
MT		 8212 if (vcpu->arch.apic_attention)
8213 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 8214
618232e2 8215 vcpu->arch.gpa_available = false;
851ba692 8216 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 8217 return r;
8218
8219cancel_injection:
8220 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 8221 if (unlikely(vcpu->arch.apic_attention))
8222 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 8223out:
8224 return r;
8225}
b6c7a5dc 8226
362c698f
PB		 8227static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8228{
bf9f6ac8
FW		 8229 if (!kvm_arch_vcpu_runnable(vcpu) &&
8230 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 8231 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8232 kvm_vcpu_block(vcpu);
8233 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 8234
8235 if (kvm_x86_ops->post_block)
8236 kvm_x86_ops->post_block(vcpu);
8237
9c8fd1ba
PB		 8238 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8239 return 1;
8240 }
362c698f
PB		 8241
8242 kvm_apic_accept_events(vcpu);
8243 switch(vcpu->arch.mp_state) {
8244 case KVM_MP_STATE_HALTED:
8245 vcpu->arch.pv.pv_unhalted = false;
8246 vcpu->arch.mp_state =
8247 KVM_MP_STATE_RUNNABLE;
b2869f28 8248 /* fall through */
362c698f
PB		 8249 case KVM_MP_STATE_RUNNABLE:
8250 vcpu->arch.apf.halted = false;
8251 break;
8252 case KVM_MP_STATE_INIT_RECEIVED:
8253 break;
8254 default:
8255 return -EINTR;
8256 break;
8257 }
8258 return 1;
8259}
09cec754 8260
5d9bc648
PB		 8261static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8262{
0ad3bed6
PB		 8263 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8264 kvm_x86_ops->check_nested_events(vcpu, false);
8265
5d9bc648
PB		 8266 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8267 !vcpu->arch.apf.halted);
8268}
8269
362c698f 8270static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8271{
8272 int r;
f656ce01 8273 struct kvm *kvm = vcpu->kvm;
d7690175 8274
f656ce01 8275 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8276 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8277
362c698f 8278 for (;;) {
58f800d5 8279 if (kvm_vcpu_running(vcpu)) {
851ba692 8280 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8281 } else {
362c698f 8282 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8283 }
8284
09cec754
GN		 8285 if (r <= 0)
8286 break;
8287
72875d8a 8288 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8289 if (kvm_cpu_has_pending_timer(vcpu))
8290 kvm_inject_pending_timer_irqs(vcpu);
8291
782d422b
MG		 8292 if (dm_request_for_irq_injection(vcpu) &&
8293 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8294 r = 0;
8295 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8296 ++vcpu->stat.request_irq_exits;
362c698f 8297 break;
09cec754 8298 }
af585b92
GN		 8299
8300 kvm_check_async_pf_completion(vcpu);
8301
09cec754
GN		 8302 if (signal_pending(current)) {
8303 r = -EINTR;
851ba692 8304 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8305 ++vcpu->stat.signal_exits;
362c698f 8306 break;
09cec754
GN		 8307 }
8308 if (need_resched()) {
f656ce01 8309 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8310 cond_resched();
f656ce01 8311 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8312 }
b6c7a5dc
HB		 8313 }
8314
f656ce01 8315 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8316
8317 return r;
8318}
8319
716d51ab
GN		 8320static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8321{
8322 int r;
8323 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8324 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 8325 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8326 if (r != EMULATE_DONE)
8327 return 0;
8328 return 1;
8329}
8330
8331static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8332{
8333 BUG_ON(!vcpu->arch.pio.count);
8334
8335 return complete_emulated_io(vcpu);
8336}
8337
f78146b0
AK		 8338/*
8339 * Implements the following, as a state machine:
8340 *
8341 * read:
8342 * for each fragment
87da7e66
XG		 8343 * for each mmio piece in the fragment
8344 * write gpa, len
8345 * exit
8346 * copy data
f78146b0
AK		 8347 * execute insn
8348 *
8349 * write:
8350 * for each fragment
87da7e66
XG		 8351 * for each mmio piece in the fragment
8352 * write gpa, len
8353 * copy data
8354 * exit
f78146b0 8355 */
716d51ab 8356static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8357{
8358 struct kvm_run *run = vcpu->run;
f78146b0 8359 struct kvm_mmio_fragment *frag;
87da7e66 8360 unsigned len;
5287f194 8361
716d51ab 8362 BUG_ON(!vcpu->mmio_needed);
5287f194 8363
716d51ab 8364 /* Complete previous fragment */
87da7e66
XG		 8365 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8366 len = min(8u, frag->len);
716d51ab 8367 if (!vcpu->mmio_is_write)
87da7e66
XG		 8368 memcpy(frag->data, run->mmio.data, len);
8369
8370 if (frag->len <= 8) {
8371 /* Switch to the next fragment. */
8372 frag++;
8373 vcpu->mmio_cur_fragment++;
8374 } else {
8375 /* Go forward to the next mmio piece. */
8376 frag->data += len;
8377 frag->gpa += len;
8378 frag->len -= len;
8379 }
8380
a08d3b3b 8381 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8382 vcpu->mmio_needed = 0;
0912c977
PB		 8383
8384 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8385 if (vcpu->mmio_is_write)
716d51ab
GN		 8386 return 1;
8387 vcpu->mmio_read_completed = 1;
8388 return complete_emulated_io(vcpu);
8389 }
87da7e66 8390
716d51ab
GN		 8391 run->exit_reason = KVM_EXIT_MMIO;
8392 run->mmio.phys_addr = frag->gpa;
8393 if (vcpu->mmio_is_write)
87da7e66
XG		 8394 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8395 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8396 run->mmio.is_write = vcpu->mmio_is_write;
8397 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8398 return 0;
5287f194
AK		 8399}
8400
822f312d
SAS		 8401/* Swap (qemu) user FPU context for the guest FPU context. */
8402static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8403{
5f409e20
RR		 8404 fpregs_lock();
8405
d9a710e5 8406 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
822f312d 8407 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8408 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d 8409 ~XFEATURE_MASK_PKRU);
5f409e20
RR		 8410
8411 fpregs_mark_activate();
8412 fpregs_unlock();
8413
822f312d
SAS		 8414 trace_kvm_fpu(1);
8415}
8416
8417/* When vcpu_run ends, restore user space FPU context. */
8418static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8419{
5f409e20
RR		 8420 fpregs_lock();
8421
b666a4b6 8422 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
d9a710e5 8423 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
5f409e20
RR		 8424
8425 fpregs_mark_activate();
8426 fpregs_unlock();
8427
822f312d
SAS		 8428 ++vcpu->stat.fpu_reload;
8429 trace_kvm_fpu(0);
8430}
8431
b6c7a5dc
HB		 8432int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8433{
8434 int r;
b6c7a5dc 8435
accb757d 8436 vcpu_load(vcpu);
20b7035c 8437 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8438 kvm_load_guest_fpu(vcpu);
8439
a4535290 8440 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8441 if (kvm_run->immediate_exit) {
8442 r = -EINTR;
8443 goto out;
8444 }
b6c7a5dc 8445 kvm_vcpu_block(vcpu);
66450a21 8446 kvm_apic_accept_events(vcpu);
72875d8a 8447 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8448 r = -EAGAIN;
a0595000
JS		 8449 if (signal_pending(current)) {
8450 r = -EINTR;
8451 vcpu->run->exit_reason = KVM_EXIT_INTR;
8452 ++vcpu->stat.signal_exits;
8453 }
ac9f6dc0 8454 goto out;
b6c7a5dc
HB		 8455 }
8456
01643c51
KH		 8457 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8458 r = -EINVAL;
8459 goto out;
8460 }
8461
8462 if (vcpu->run->kvm_dirty_regs) {
8463 r = sync_regs(vcpu);
8464 if (r != 0)
8465 goto out;
8466 }
8467
b6c7a5dc 8468 /* re-sync apic's tpr */
35754c98 8469 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8470 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8471 r = -EINVAL;
8472 goto out;
8473 }
8474 }
b6c7a5dc 8475
716d51ab
GN		 8476 if (unlikely(vcpu->arch.complete_userspace_io)) {
8477 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8478 vcpu->arch.complete_userspace_io = NULL;
8479 r = cui(vcpu);
8480 if (r <= 0)
5663d8f9 8481 goto out;
716d51ab
GN		 8482 } else
8483 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8484
460df4c1
PB		 8485 if (kvm_run->immediate_exit)
8486 r = -EINTR;
8487 else
8488 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8489
8490out:
5663d8f9 8491 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8492 if (vcpu->run->kvm_valid_regs)
8493 store_regs(vcpu);
f1d86e46 8494 post_kvm_run_save(vcpu);
20b7035c 8495 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8496
accb757d 8497 vcpu_put(vcpu);
b6c7a5dc
HB		 8498 return r;
8499}
8500
01643c51 8501static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8502{
7ae441ea
GN		 8503 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8504 /*
8505 * We are here if userspace calls get_regs() in the middle of
8506 * instruction emulation. Registers state needs to be copied
4a969980 8507 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8508 * that usually, but some bad designed PV devices (vmware
8509 * backdoor interface) need this to work
8510 */
dd856efa 8511 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8512 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8513 }
de3cd117
SC		 8514 regs->rax = kvm_rax_read(vcpu);
8515 regs->rbx = kvm_rbx_read(vcpu);
8516 regs->rcx = kvm_rcx_read(vcpu);
8517 regs->rdx = kvm_rdx_read(vcpu);
8518 regs->rsi = kvm_rsi_read(vcpu);
8519 regs->rdi = kvm_rdi_read(vcpu);
e9c16c78 8520 regs->rsp = kvm_rsp_read(vcpu);
de3cd117 8521 regs->rbp = kvm_rbp_read(vcpu);
b6c7a5dc 8522#ifdef CONFIG_X86_64
de3cd117
SC		 8523 regs->r8 = kvm_r8_read(vcpu);
8524 regs->r9 = kvm_r9_read(vcpu);
8525 regs->r10 = kvm_r10_read(vcpu);
8526 regs->r11 = kvm_r11_read(vcpu);
8527 regs->r12 = kvm_r12_read(vcpu);
8528 regs->r13 = kvm_r13_read(vcpu);
8529 regs->r14 = kvm_r14_read(vcpu);
8530 regs->r15 = kvm_r15_read(vcpu);
b6c7a5dc
HB		 8531#endif
8532
5fdbf976 8533 regs->rip = kvm_rip_read(vcpu);
91586a3b 8534 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8535}
b6c7a5dc 8536
01643c51
KH		 8537int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8538{
8539 vcpu_load(vcpu);
8540 __get_regs(vcpu, regs);
1fc9b76b 8541 vcpu_put(vcpu);
b6c7a5dc
HB		 8542 return 0;
8543}
8544
01643c51 8545static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8546{
7ae441ea
GN		 8547 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8548 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8549
de3cd117
SC		 8550 kvm_rax_write(vcpu, regs->rax);
8551 kvm_rbx_write(vcpu, regs->rbx);
8552 kvm_rcx_write(vcpu, regs->rcx);
8553 kvm_rdx_write(vcpu, regs->rdx);
8554 kvm_rsi_write(vcpu, regs->rsi);
8555 kvm_rdi_write(vcpu, regs->rdi);
e9c16c78 8556 kvm_rsp_write(vcpu, regs->rsp);
de3cd117 8557 kvm_rbp_write(vcpu, regs->rbp);
b6c7a5dc 8558#ifdef CONFIG_X86_64
de3cd117
SC		 8559 kvm_r8_write(vcpu, regs->r8);
8560 kvm_r9_write(vcpu, regs->r9);
8561 kvm_r10_write(vcpu, regs->r10);
8562 kvm_r11_write(vcpu, regs->r11);
8563 kvm_r12_write(vcpu, regs->r12);
8564 kvm_r13_write(vcpu, regs->r13);
8565 kvm_r14_write(vcpu, regs->r14);
8566 kvm_r15_write(vcpu, regs->r15);
b6c7a5dc
HB		 8567#endif
8568
5fdbf976 8569 kvm_rip_write(vcpu, regs->rip);
d73235d1 8570 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8571
b4f14abd
JK		 8572 vcpu->arch.exception.pending = false;
8573
3842d135 8574 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8575}
3842d135 8576
01643c51
KH		 8577int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8578{
8579 vcpu_load(vcpu);
8580 __set_regs(vcpu, regs);
875656fe 8581 vcpu_put(vcpu);
b6c7a5dc
HB		 8582 return 0;
8583}
8584
b6c7a5dc
HB		 8585void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8586{
8587 struct kvm_segment cs;
8588
3e6e0aab 8589 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8590 *db = cs.db;
8591 *l = cs.l;
8592}
8593EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8594
01643c51 8595static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8596{
89a27f4d 8597 struct desc_ptr dt;
b6c7a5dc 8598
3e6e0aab
GT		 8599 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8600 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8601 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8602 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8603 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8604 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8605
3e6e0aab
GT		 8606 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8607 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8608
8609 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8610 sregs->idt.limit = dt.size;
8611 sregs->idt.base = dt.address;
b6c7a5dc 8612 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8613 sregs->gdt.limit = dt.size;
8614 sregs->gdt.base = dt.address;
b6c7a5dc 8615
4d4ec087 8616 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8617 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8618 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8619 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8620 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8621 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8622 sregs->apic_base = kvm_get_apic_base(vcpu);
8623
0e96f31e 8624 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8625
04140b41 8626 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8627 set_bit(vcpu->arch.interrupt.nr,
8628 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8629}
16d7a191 8630
01643c51
KH		 8631int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8632 struct kvm_sregs *sregs)
8633{
8634 vcpu_load(vcpu);
8635 __get_sregs(vcpu, sregs);
bcdec41c 8636 vcpu_put(vcpu);
b6c7a5dc
HB		 8637 return 0;
8638}
8639
62d9f0db
MT		 8640int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8641 struct kvm_mp_state *mp_state)
8642{
fd232561
CD		 8643 vcpu_load(vcpu);
8644
66450a21 8645 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8646 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8647 vcpu->arch.pv.pv_unhalted)
8648 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8649 else
8650 mp_state->mp_state = vcpu->arch.mp_state;
8651
fd232561 8652 vcpu_put(vcpu);
62d9f0db
MT		 8653 return 0;
8654}
8655
8656int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8657 struct kvm_mp_state *mp_state)
8658{
e83dff5e
CD		 8659 int ret = -EINVAL;
8660
8661 vcpu_load(vcpu);
8662
bce87cce 8663 if (!lapic_in_kernel(vcpu) &&
66450a21 8664 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8665 goto out;
66450a21 8666
28bf2888
DH		 8667 /* INITs are latched while in SMM */
8668 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8669 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8670 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8671 goto out;
28bf2888 8672
66450a21
JK		 8673 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8674 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8675 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8676 } else
8677 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8678 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8679
8680 ret = 0;
8681out:
8682 vcpu_put(vcpu);
8683 return ret;
62d9f0db
MT		 8684}
8685
7f3d35fd
KW		 8686int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8687 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8688{
9d74191a 8689 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8690 int ret;
e01c2426 8691
8ec4722d 8692 init_emulate_ctxt(vcpu);
c697518a 8693
7f3d35fd 8694 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8695 has_error_code, error_code);
1051778f
SC		 8696 if (ret) {
8697 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8698 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8699 vcpu->run->internal.ndata = 0;
8700 return EMULATE_USER_EXIT;
8701 }
37817f29 8702
9d74191a
TY		 8703 kvm_rip_write(vcpu, ctxt->eip);
8704 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8705 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8706 return EMULATE_DONE;
37817f29
IE		 8707}
8708EXPORT_SYMBOL_GPL(kvm_task_switch);
8709
3140c156 8710static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8711{
74fec5b9
TL		 8712 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8713 (sregs->cr4 & X86_CR4_OSXSAVE))
8714 return -EINVAL;
8715
37b95951 8716 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8717 /*
8718 * When EFER.LME and CR0.PG are set, the processor is in
8719 * 64-bit mode (though maybe in a 32-bit code segment).
8720 * CR4.PAE and EFER.LMA must be set.
8721 */
37b95951 8722 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8723 || !(sregs->efer & EFER_LMA))
8724 return -EINVAL;
8725 } else {
8726 /*
8727 * Not in 64-bit mode: EFER.LMA is clear and the code
8728 * segment cannot be 64-bit.
8729 */
8730 if (sregs->efer & EFER_LMA || sregs->cs.l)
8731 return -EINVAL;
8732 }
8733
8734 return 0;
8735}
8736
01643c51 8737static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8738{
58cb628d 8739 struct msr_data apic_base_msr;
b6c7a5dc 8740 int mmu_reset_needed = 0;
c4d21882 8741 int cpuid_update_needed = 0;
63f42e02 8742 int pending_vec, max_bits, idx;
89a27f4d 8743 struct desc_ptr dt;
b4ef9d4e
CD		 8744 int ret = -EINVAL;
8745
f2981033 8746 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8747 goto out;
f2981033 8748
d3802286
JM		 8749 apic_base_msr.data = sregs->apic_base;
8750 apic_base_msr.host_initiated = true;
8751 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8752 goto out;
6d1068b3 8753
89a27f4d
GN		 8754 dt.size = sregs->idt.limit;
8755 dt.address = sregs->idt.base;
b6c7a5dc 8756 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8757 dt.size = sregs->gdt.limit;
8758 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8759 kvm_x86_ops->set_gdt(vcpu, &dt);
8760
ad312c7c 8761 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8762 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8763 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8764 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8765
2d3ad1f4 8766 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8767
f6801dff 8768 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8769 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8770
4d4ec087 8771 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8772 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8773 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8774
fc78f519 8775 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8776 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8777 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8778 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8779 if (cpuid_update_needed)
00b27a3e 8780 kvm_update_cpuid(vcpu);
63f42e02
XG		 8781
8782 idx = srcu_read_lock(&vcpu->kvm->srcu);
bf03d4f9 8783 if (is_pae_paging(vcpu)) {
9f8fe504 8784 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8785 mmu_reset_needed = 1;
8786 }
63f42e02 8787 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8788
8789 if (mmu_reset_needed)
8790 kvm_mmu_reset_context(vcpu);
8791
a50abc3b 8792 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8793 pending_vec = find_first_bit(
8794 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8795 if (pending_vec < max_bits) {
66fd3f7f 8796 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8797 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8798 }
8799
3e6e0aab
GT		 8800 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8801 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8802 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8803 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8804 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8805 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8806
3e6e0aab
GT		 8807 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8808 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8809
5f0269f5
ME		 8810 update_cr8_intercept(vcpu);
8811
9c3e4aab 8812 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8813 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8814 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8815 !is_protmode(vcpu))
9c3e4aab
MT		 8816 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8817
3842d135
AK		 8818 kvm_make_request(KVM_REQ_EVENT, vcpu);
8819
b4ef9d4e
CD		 8820 ret = 0;
8821out:
01643c51
KH		 8822 return ret;
8823}
8824
8825int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8826 struct kvm_sregs *sregs)
8827{
8828 int ret;
8829
8830 vcpu_load(vcpu);
8831 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8832 vcpu_put(vcpu);
8833 return ret;
b6c7a5dc
HB		 8834}
8835
d0bfb940
JK		 8836int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8837 struct kvm_guest_debug *dbg)
b6c7a5dc 8838{
355be0b9 8839 unsigned long rflags;
ae675ef0 8840 int i, r;
b6c7a5dc 8841
66b56562
CD		 8842 vcpu_load(vcpu);
8843
4f926bf2
JK		 8844 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8845 r = -EBUSY;
8846 if (vcpu->arch.exception.pending)
2122ff5e 8847 goto out;
4f926bf2
JK		 8848 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8849 kvm_queue_exception(vcpu, DB_VECTOR);
8850 else
8851 kvm_queue_exception(vcpu, BP_VECTOR);
8852 }
8853
91586a3b
JK		 8854 /*
8855 * Read rflags as long as potentially injected trace flags are still
8856 * filtered out.
8857 */
8858 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8859
8860 vcpu->guest_debug = dbg->control;
8861 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8862 vcpu->guest_debug = 0;
8863
8864 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8865 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8866 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8867 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8868 } else {
8869 for (i = 0; i < KVM_NR_DB_REGS; i++)
8870 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8871 }
c8639010 8872 kvm_update_dr7(vcpu);
ae675ef0 8873
f92653ee
JK		 8874 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8875 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8876 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8877
91586a3b
JK		 8878 /*
8879 * Trigger an rflags update that will inject or remove the trace
8880 * flags.
8881 */
8882 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8883
a96036b8 8884 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8885
4f926bf2 8886 r = 0;
d0bfb940 8887
2122ff5e 8888out:
66b56562 8889 vcpu_put(vcpu);
b6c7a5dc
HB		 8890 return r;
8891}
8892
8b006791
ZX		 8893/*
8894 * Translate a guest virtual address to a guest physical address.
8895 */
8896int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8897 struct kvm_translation *tr)
8898{
8899 unsigned long vaddr = tr->linear_address;
8900 gpa_t gpa;
f656ce01 8901 int idx;
8b006791 8902
1da5b61d
CD		 8903 vcpu_load(vcpu);
8904
f656ce01 8905 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8906 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8907 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8908 tr->physical_address = gpa;
8909 tr->valid = gpa != UNMAPPED_GVA;
8910 tr->writeable = 1;
8911 tr->usermode = 0;
8b006791 8912
1da5b61d 8913 vcpu_put(vcpu);
8b006791
ZX		 8914 return 0;
8915}
8916
d0752060
HB		 8917int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8918{
1393123e 8919 struct fxregs_state *fxsave;
d0752060 8920
1393123e 8921 vcpu_load(vcpu);
d0752060 8922
b666a4b6 8923 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8924 memcpy(fpu->fpr, fxsave->st_space, 128);
8925 fpu->fcw = fxsave->cwd;
8926 fpu->fsw = fxsave->swd;
8927 fpu->ftwx = fxsave->twd;
8928 fpu->last_opcode = fxsave->fop;
8929 fpu->last_ip = fxsave->rip;
8930 fpu->last_dp = fxsave->rdp;
0e96f31e 8931 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8932
1393123e 8933 vcpu_put(vcpu);
d0752060
HB		 8934 return 0;
8935}
8936
8937int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8938{
6a96bc7f
CD		 8939 struct fxregs_state *fxsave;
8940
8941 vcpu_load(vcpu);
8942
b666a4b6 8943 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8944
d0752060
HB		 8945 memcpy(fxsave->st_space, fpu->fpr, 128);
8946 fxsave->cwd = fpu->fcw;
8947 fxsave->swd = fpu->fsw;
8948 fxsave->twd = fpu->ftwx;
8949 fxsave->fop = fpu->last_opcode;
8950 fxsave->rip = fpu->last_ip;
8951 fxsave->rdp = fpu->last_dp;
0e96f31e 8952 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8953
6a96bc7f 8954 vcpu_put(vcpu);
d0752060
HB		 8955 return 0;
8956}
8957
01643c51
KH		 8958static void store_regs(struct kvm_vcpu *vcpu)
8959{
8960 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8961
8962 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8963 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8964
8965 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8966 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8967
8968 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8969 kvm_vcpu_ioctl_x86_get_vcpu_events(
8970 vcpu, &vcpu->run->s.regs.events);
8971}
8972
8973static int sync_regs(struct kvm_vcpu *vcpu)
8974{
8975 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8976 return -EINVAL;
8977
8978 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8979 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8980 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8981 }
8982 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8983 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8984 return -EINVAL;
8985 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8986 }
8987 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8988 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8989 vcpu, &vcpu->run->s.regs.events))
8990 return -EINVAL;
8991 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8992 }
8993
8994 return 0;
8995}
8996
0ee6a517 8997static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8998{
b666a4b6 8999 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 9000 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 9001 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 9002 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 9003
2acf923e
DC		 9004 /*
9005 * Ensure guest xcr0 is valid for loading
9006 */
d91cab78 9007 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 9008
ad312c7c 9009 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 9010}
d0752060 9011
e9b11c17
ZX		 9012void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
9013{
bd768e14
IY		 9014 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
9015
12f9a48f 9016 kvmclock_reset(vcpu);
7f1ea208 9017
e9b11c17 9018 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 9019 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 9020}
9021
9022struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
9023 unsigned int id)
9024{
c447e76b
LL		 9025 struct kvm_vcpu *vcpu;
9026
b0c39dc6 9027 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 9028 printk_once(KERN_WARNING
9029 "kvm: SMP vm created on host with unstable TSC; "
9030 "guest TSC will not be reliable\n");
c447e76b
LL		 9031
9032 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
9033
c447e76b 9034 return vcpu;
26e5215f 9035}
e9b11c17 9036
26e5215f
AK		 9037int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
9038{
0cf9135b 9039 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 9040 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 9041 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 9042 vcpu_load(vcpu);
d28bc9dd 9043 kvm_vcpu_reset(vcpu, false);
e1732991 9044 kvm_init_mmu(vcpu, false);
e9b11c17 9045 vcpu_put(vcpu);
ec7660cc 9046 return 0;
e9b11c17
ZX		 9047}
9048
31928aa5 9049void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 9050{
8fe8ab46 9051 struct msr_data msr;
332967a3 9052 struct kvm *kvm = vcpu->kvm;
42897d86 9053
d3457c87
RK		 9054 kvm_hv_vcpu_postcreate(vcpu);
9055
ec7660cc 9056 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 9057 return;
ec7660cc 9058 vcpu_load(vcpu);
8fe8ab46
WA		 9059 msr.data = 0x0;
9060 msr.index = MSR_IA32_TSC;
9061 msr.host_initiated = true;
9062 kvm_write_tsc(vcpu, &msr);
42897d86 9063 vcpu_put(vcpu);
2d5ba19b
MT		 9064
9065 /* poll control enabled by default */
9066 vcpu->arch.msr_kvm_poll_control = 1;
9067
ec7660cc 9068 mutex_unlock(&vcpu->mutex);
42897d86 9069
630994b3
MT		 9070 if (!kvmclock_periodic_sync)
9071 return;
9072
332967a3
AJ		 9073 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9074 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 9075}
9076
d40ccc62 9077void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 9078{
344d9588
GN		 9079 vcpu->arch.apf.msr_val = 0;
9080
ec7660cc 9081 vcpu_load(vcpu);
e9b11c17
ZX		 9082 kvm_mmu_unload(vcpu);
9083 vcpu_put(vcpu);
9084
9085 kvm_x86_ops->vcpu_free(vcpu);
9086}
9087
d28bc9dd 9088void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 9089{
b7e31be3
RK		 9090 kvm_lapic_reset(vcpu, init_event);
9091
e69fab5d
PB		 9092 vcpu->arch.hflags = 0;
9093
c43203ca 9094 vcpu->arch.smi_pending = 0;
52797bf9 9095 vcpu->arch.smi_count = 0;
7460fb4a
AK		 9096 atomic_set(&vcpu->arch.nmi_queued, 0);
9097 vcpu->arch.nmi_pending = 0;
448fa4a9 9098 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 9099 kvm_clear_interrupt_queue(vcpu);
9100 kvm_clear_exception_queue(vcpu);
664f8e26 9101 vcpu->arch.exception.pending = false;
448fa4a9 9102
42dbaa5a 9103 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 9104 kvm_update_dr0123(vcpu);
6f43ed01 9105 vcpu->arch.dr6 = DR6_INIT;
73aaf249 9106 kvm_update_dr6(vcpu);
42dbaa5a 9107 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 9108 kvm_update_dr7(vcpu);
42dbaa5a 9109
1119022c
NA		 9110 vcpu->arch.cr2 = 0;
9111
3842d135 9112 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 9113 vcpu->arch.apf.msr_val = 0;
c9aaa895 9114 vcpu->arch.st.msr_val = 0;
3842d135 9115
12f9a48f
GC		 9116 kvmclock_reset(vcpu);
9117
af585b92
GN		 9118 kvm_clear_async_pf_completion_queue(vcpu);
9119 kvm_async_pf_hash_reset(vcpu);
9120 vcpu->arch.apf.halted = false;
3842d135 9121
a554d207
WL		 9122 if (kvm_mpx_supported()) {
9123 void *mpx_state_buffer;
9124
9125 /*
9126 * To avoid have the INIT path from kvm_apic_has_events() that be
9127 * called with loaded FPU and does not let userspace fix the state.
9128 */
f775b13e
RR		 9129 if (init_event)
9130 kvm_put_guest_fpu(vcpu);
b666a4b6 9131 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9132 XFEATURE_BNDREGS);
a554d207
WL		 9133 if (mpx_state_buffer)
9134 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 9135 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9136 XFEATURE_BNDCSR);
a554d207
WL		 9137 if (mpx_state_buffer)
9138 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 9139 if (init_event)
9140 kvm_load_guest_fpu(vcpu);
a554d207
WL		 9141 }
9142
64d60670 9143 if (!init_event) {
d28bc9dd 9144 kvm_pmu_reset(vcpu);
64d60670 9145 vcpu->arch.smbase = 0x30000;
db2336a8 9146
db2336a8 9147 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 9148
9149 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 9150 }
f5132b01 9151
66f7b72e
JS		 9152 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9153 vcpu->arch.regs_avail = ~0;
9154 vcpu->arch.regs_dirty = ~0;
9155
a554d207
WL		 9156 vcpu->arch.ia32_xss = 0;
9157
d28bc9dd 9158 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 9159}
9160
2b4a273b 9161void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 9162{
9163 struct kvm_segment cs;
9164
9165 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9166 cs.selector = vector << 8;
9167 cs.base = vector << 12;
9168 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9169 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 9170}
9171
13a34e06 9172int kvm_arch_hardware_enable(void)
e9b11c17 9173{
ca84d1a2
ZA		 9174 struct kvm *kvm;
9175 struct kvm_vcpu *vcpu;
9176 int i;
0dd6a6ed
ZA		 9177 int ret;
9178 u64 local_tsc;
9179 u64 max_tsc = 0;
9180 bool stable, backwards_tsc = false;
18863bdd
AK		 9181
9182 kvm_shared_msr_cpu_online();
13a34e06 9183 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 9184 if (ret != 0)
9185 return ret;
9186
4ea1636b 9187 local_tsc = rdtsc();
b0c39dc6 9188 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 9189 list_for_each_entry(kvm, &vm_list, vm_list) {
9190 kvm_for_each_vcpu(i, vcpu, kvm) {
9191 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 9192 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9193 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9194 backwards_tsc = true;
9195 if (vcpu->arch.last_host_tsc > max_tsc)
9196 max_tsc = vcpu->arch.last_host_tsc;
9197 }
9198 }
9199 }
9200
9201 /*
9202 * Sometimes, even reliable TSCs go backwards. This happens on
9203 * platforms that reset TSC during suspend or hibernate actions, but
9204 * maintain synchronization. We must compensate. Fortunately, we can
9205 * detect that condition here, which happens early in CPU bringup,
9206 * before any KVM threads can be running. Unfortunately, we can't
9207 * bring the TSCs fully up to date with real time, as we aren't yet far
9208 * enough into CPU bringup that we know how much real time has actually
9285ec4c 9209 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
0dd6a6ed
ZA		 9210 * variables that haven't been updated yet.
9211 *
9212 * So we simply find the maximum observed TSC above, then record the
9213 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9214 * the adjustment will be applied. Note that we accumulate
9215 * adjustments, in case multiple suspend cycles happen before some VCPU
9216 * gets a chance to run again. In the event that no KVM threads get a
9217 * chance to run, we will miss the entire elapsed period, as we'll have
9218 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9219 * loose cycle time. This isn't too big a deal, since the loss will be
9220 * uniform across all VCPUs (not to mention the scenario is extremely
9221 * unlikely). It is possible that a second hibernate recovery happens
9222 * much faster than a first, causing the observed TSC here to be
9223 * smaller; this would require additional padding adjustment, which is
9224 * why we set last_host_tsc to the local tsc observed here.
9225 *
9226 * N.B. - this code below runs only on platforms with reliable TSC,
9227 * as that is the only way backwards_tsc is set above. Also note
9228 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9229 * have the same delta_cyc adjustment applied if backwards_tsc
9230 * is detected. Note further, this adjustment is only done once,
9231 * as we reset last_host_tsc on all VCPUs to stop this from being
9232 * called multiple times (one for each physical CPU bringup).
9233 *
4a969980 9234 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 9235 * will be compensated by the logic in vcpu_load, which sets the TSC to
9236 * catchup mode. This will catchup all VCPUs to real time, but cannot
9237 * guarantee that they stay in perfect synchronization.
9238 */
9239 if (backwards_tsc) {
9240 u64 delta_cyc = max_tsc - local_tsc;
9241 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 9242 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 9243 kvm_for_each_vcpu(i, vcpu, kvm) {
9244 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9245 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 9246 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9247 }
9248
9249 /*
9250 * We have to disable TSC offset matching.. if you were
9251 * booting a VM while issuing an S4 host suspend....
9252 * you may have some problem. Solving this issue is
9253 * left as an exercise to the reader.
9254 */
9255 kvm->arch.last_tsc_nsec = 0;
9256 kvm->arch.last_tsc_write = 0;
9257 }
9258
9259 }
9260 return 0;
e9b11c17
ZX		 9261}
9262
13a34e06 9263void kvm_arch_hardware_disable(void)
e9b11c17 9264{
13a34e06
RK		 9265 kvm_x86_ops->hardware_disable();
9266 drop_user_return_notifiers();
e9b11c17
ZX		 9267}
9268
9269int kvm_arch_hardware_setup(void)
9270{
9e9c3fe4
NA		 9271 int r;
9272
9273 r = kvm_x86_ops->hardware_setup();
9274 if (r != 0)
9275 return r;
9276
35181e86
HZ		 9277 if (kvm_has_tsc_control) {
9278 /*
9279 * Make sure the user can only configure tsc_khz values that
9280 * fit into a signed integer.
273ba457 9281 * A min value is not calculated because it will always
35181e86
HZ		 9282 * be 1 on all machines.
9283 */
9284 u64 max = min(0x7fffffffULL,
9285 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9286 kvm_max_guest_tsc_khz = max;
9287
ad721883 9288 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9289 }
ad721883 9290
9e9c3fe4
NA		 9291 kvm_init_msr_list();
9292 return 0;
e9b11c17
ZX		 9293}
9294
9295void kvm_arch_hardware_unsetup(void)
9296{
9297 kvm_x86_ops->hardware_unsetup();
9298}
9299
f257d6dc 9300int kvm_arch_check_processor_compat(void)
e9b11c17 9301{
f257d6dc 9302 return kvm_x86_ops->check_processor_compatibility();
d71ba788
PB		 9303}
9304
9305bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9306{
9307 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9308}
9309EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9310
9311bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9312{
9313 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9314}
9315
54e9818f 9316struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9317EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9318
e9b11c17
ZX		 9319int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9320{
9321 struct page *page;
e9b11c17
ZX		 9322 int r;
9323
9aabc88f 9324 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9325 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9326 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9327 else
a4535290 9328 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9329
9330 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9331 if (!page) {
9332 r = -ENOMEM;
9333 goto fail;
9334 }
ad312c7c 9335 vcpu->arch.pio_data = page_address(page);
e9b11c17 9336
cc578287 9337 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9338
e9b11c17
ZX		 9339 r = kvm_mmu_create(vcpu);
9340 if (r < 0)
9341 goto fail_free_pio_data;
9342
26de7988 9343 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9344 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
39497d76 9345 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
e9b11c17
ZX		 9346 if (r < 0)
9347 goto fail_mmu_destroy;
54e9818f
GN		 9348 } else
9349 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9350
890ca9ae 9351 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
254272ce 9352 GFP_KERNEL_ACCOUNT);
890ca9ae
HY		 9353 if (!vcpu->arch.mce_banks) {
9354 r = -ENOMEM;
443c39bc 9355 goto fail_free_lapic;
890ca9ae
HY		 9356 }
9357 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9358
254272ce
BG		 9359 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9360 GFP_KERNEL_ACCOUNT)) {
f1797359 9361 r = -ENOMEM;
f5f48ee1 9362 goto fail_free_mce_banks;
f1797359 9363 }
f5f48ee1 9364
0ee6a517 9365 fx_init(vcpu);
66f7b72e 9366
4344ee98 9367 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9368
5a4f55cd
EK		 9369 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9370
74545705
RK		 9371 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9372
af585b92 9373 kvm_async_pf_hash_reset(vcpu);
f5132b01 9374 kvm_pmu_init(vcpu);
af585b92 9375
1c1a9ce9 9376 vcpu->arch.pending_external_vector = -1;
de63ad4c 9377 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9378
5c919412
AS		 9379 kvm_hv_vcpu_init(vcpu);
9380
e9b11c17 9381 return 0;
0ee6a517 9382
f5f48ee1
SY		 9383fail_free_mce_banks:
9384 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9385fail_free_lapic:
9386 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9387fail_mmu_destroy:
9388 kvm_mmu_destroy(vcpu);
9389fail_free_pio_data:
ad312c7c 9390 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9391fail:
9392 return r;
9393}
9394
9395void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9396{
f656ce01
MT		 9397 int idx;
9398
1f4b34f8 9399 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9400 kvm_pmu_destroy(vcpu);
36cb93fd 9401 kfree(vcpu->arch.mce_banks);
e9b11c17 9402 kvm_free_lapic(vcpu);
f656ce01 9403 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9404 kvm_mmu_destroy(vcpu);
f656ce01 9405 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9406 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9407 if (!lapic_in_kernel(vcpu))
54e9818f 9408 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9409}
d19a9cd2 9410
e790d9ef
RK		 9411void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9412{
c595ceee 9413 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9414 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9415}
9416
e08b9637 9417int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9418{
e08b9637
CO		 9419 if (type)
9420 return -EINVAL;
9421
6ef768fa 9422 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9423 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 9424 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9425 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9426
5550af4d
SY		 9427 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9428 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9429 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9430 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9431 &kvm->arch.irq_sources_bitmap);
5550af4d 9432
038f8c11 9433 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9434 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9435 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9436
9285ec4c 9437 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
d828199e 9438 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9439
6fbbde9a
DS		 9440 kvm->arch.guest_can_read_msr_platform_info = true;
9441
7e44e449 9442 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9443 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9444
cbc0236a 9445 kvm_hv_init_vm(kvm);
0eb05bf2 9446 kvm_page_track_init(kvm);
13d268ca 9447 kvm_mmu_init_vm(kvm);
0eb05bf2 9448
92735b1b 9449 return kvm_x86_ops->vm_init(kvm);
d19a9cd2
ZX		 9450}
9451
9452static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9453{
ec7660cc 9454 vcpu_load(vcpu);
d19a9cd2
ZX		 9455 kvm_mmu_unload(vcpu);
9456 vcpu_put(vcpu);
9457}
9458
9459static void kvm_free_vcpus(struct kvm *kvm)
9460{
9461 unsigned int i;
988a2cae 9462 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9463
9464 /*
9465 * Unpin any mmu pages first.
9466 */
af585b92
GN		 9467 kvm_for_each_vcpu(i, vcpu, kvm) {
9468 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9469 kvm_unload_vcpu_mmu(vcpu);
af585b92 9470 }
988a2cae
GN		 9471 kvm_for_each_vcpu(i, vcpu, kvm)
9472 kvm_arch_vcpu_free(vcpu);
9473
9474 mutex_lock(&kvm->lock);
9475 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9476 kvm->vcpus[i] = NULL;
d19a9cd2 9477
988a2cae
GN		 9478 atomic_set(&kvm->online_vcpus, 0);
9479 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9480}
9481
ad8ba2cd
SY		 9482void kvm_arch_sync_events(struct kvm *kvm)
9483{
332967a3 9484 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9485 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9486 kvm_free_pit(kvm);
ad8ba2cd
SY		 9487}
9488
1d8007bd 9489int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9490{
9491 int i, r;
25188b99 9492 unsigned long hva;
f0d648bd
PB		 9493 struct kvm_memslots *slots = kvm_memslots(kvm);
9494 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9495
9496 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9497 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9498 return -EINVAL;
9da0e4d5 9499
f0d648bd
PB		 9500 slot = id_to_memslot(slots, id);
9501 if (size) {
b21629da 9502 if (slot->npages)
f0d648bd
PB		 9503 return -EEXIST;
9504
9505 /*
9506 * MAP_SHARED to prevent internal slot pages from being moved
9507 * by fork()/COW.
9508 */
9509 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9510 MAP_SHARED | MAP_ANONYMOUS, 0);
9511 if (IS_ERR((void *)hva))
9512 return PTR_ERR((void *)hva);
9513 } else {
9514 if (!slot->npages)
9515 return 0;
9516
9517 hva = 0;
9518 }
9519
9520 old = *slot;
9da0e4d5 9521 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9522 struct kvm_userspace_memory_region m;
9da0e4d5 9523
1d8007bd
PB		 9524 m.slot = id | (i << 16);
9525 m.flags = 0;
9526 m.guest_phys_addr = gpa;
f0d648bd 9527 m.userspace_addr = hva;
1d8007bd 9528 m.memory_size = size;
9da0e4d5
PB		 9529 r = __kvm_set_memory_region(kvm, &m);
9530 if (r < 0)
9531 return r;
9532 }
9533
103c763c
EB		 9534 if (!size)
9535 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9536
9da0e4d5
PB		 9537 return 0;
9538}
9539EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9540
1d8007bd 9541int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9542{
9543 int r;
9544
9545 mutex_lock(&kvm->slots_lock);
1d8007bd 9546 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9547 mutex_unlock(&kvm->slots_lock);
9548
9549 return r;
9550}
9551EXPORT_SYMBOL_GPL(x86_set_memory_region);
9552
d19a9cd2
ZX		 9553void kvm_arch_destroy_vm(struct kvm *kvm)
9554{
27469d29
AH		 9555 if (current->mm == kvm->mm) {
9556 /*
9557 * Free memory regions allocated on behalf of userspace,
9558 * unless the the memory map has changed due to process exit
9559 * or fd copying.
9560 */
1d8007bd
PB		 9561 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9562 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9563 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9564 }
03543133
SS		 9565 if (kvm_x86_ops->vm_destroy)
9566 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9567 kvm_pic_destroy(kvm);
9568 kvm_ioapic_destroy(kvm);
d19a9cd2 9569 kvm_free_vcpus(kvm);
af1bae54 9570 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
66bb8a06 9571 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
13d268ca 9572 kvm_mmu_uninit_vm(kvm);
2beb6dad 9573 kvm_page_track_cleanup(kvm);
cbc0236a 9574 kvm_hv_destroy_vm(kvm);
d19a9cd2 9575}
0de10343 9576
5587027c 9577void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9578 struct kvm_memory_slot *dont)
9579{
9580 int i;
9581
d89cc617
TY		 9582 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9583 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9584 kvfree(free->arch.rmap[i]);
d89cc617 9585 free->arch.rmap[i] = NULL;
77d11309 9586 }
d89cc617
TY		 9587 if (i == 0)
9588 continue;
9589
9590 if (!dont || free->arch.lpage_info[i - 1] !=
9591 dont->arch.lpage_info[i - 1]) {
548ef284 9592 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9593 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9594 }
9595 }
21ebbeda
XG		 9596
9597 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9598}
9599
5587027c
AK		 9600int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9601 unsigned long npages)
db3fe4eb
TY		 9602{
9603 int i;
9604
d89cc617 9605 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9606 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9607 unsigned long ugfn;
9608 int lpages;
d89cc617 9609 int level = i + 1;
db3fe4eb
TY		 9610
9611 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9612 slot->base_gfn, level) + 1;
9613
d89cc617 9614 slot->arch.rmap[i] =
778e1cdd 9615 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9616 GFP_KERNEL_ACCOUNT);
d89cc617 9617 if (!slot->arch.rmap[i])
77d11309 9618 goto out_free;
d89cc617
TY		 9619 if (i == 0)
9620 continue;
77d11309 9621
254272ce 9622 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9623 if (!linfo)
db3fe4eb
TY		 9624 goto out_free;
9625
92f94f1e
XG		 9626 slot->arch.lpage_info[i - 1] = linfo;
9627
db3fe4eb 9628 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9629 linfo[0].disallow_lpage = 1;
db3fe4eb 9630 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9631 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9632 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9633 /*
9634 * If the gfn and userspace address are not aligned wrt each
9635 * other, or if explicitly asked to, disable large page
9636 * support for this slot
9637 */
9638 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9639 !kvm_largepages_enabled()) {
9640 unsigned long j;
9641
9642 for (j = 0; j < lpages; ++j)
92f94f1e 9643 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9644 }
9645 }
9646
21ebbeda
XG		 9647 if (kvm_page_track_create_memslot(slot, npages))
9648 goto out_free;
9649
db3fe4eb
TY		 9650 return 0;
9651
9652out_free:
d89cc617 9653 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9654 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9655 slot->arch.rmap[i] = NULL;
9656 if (i == 0)
9657 continue;
9658
548ef284 9659 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9660 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9661 }
9662 return -ENOMEM;
9663}
9664
15248258 9665void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9666{
e6dff7d1
TY		 9667 /*
9668 * memslots->generation has been incremented.
9669 * mmio generation may have reached its maximum value.
9670 */
15248258 9671 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9672}
9673
f7784b8e
MT		 9674int kvm_arch_prepare_memory_region(struct kvm *kvm,
9675 struct kvm_memory_slot *memslot,
09170a49 9676 const struct kvm_userspace_memory_region *mem,
7b6195a9 9677 enum kvm_mr_change change)
0de10343 9678{
f7784b8e
MT		 9679 return 0;
9680}
9681
88178fd4
KH		 9682static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9683 struct kvm_memory_slot *new)
9684{
9685 /* Still write protect RO slot */
9686 if (new->flags & KVM_MEM_READONLY) {
9687 kvm_mmu_slot_remove_write_access(kvm, new);
9688 return;
9689 }
9690
9691 /*
9692 * Call kvm_x86_ops dirty logging hooks when they are valid.
9693 *
9694 * kvm_x86_ops->slot_disable_log_dirty is called when:
9695 *
9696 * - KVM_MR_CREATE with dirty logging is disabled
9697 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9698 *
9699 * The reason is, in case of PML, we need to set D-bit for any slots
9700 * with dirty logging disabled in order to eliminate unnecessary GPA
9701 * logging in PML buffer (and potential PML buffer full VMEXT). This
9702 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9703 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9704 * logging disabled for memory slots.
9705 *
9706 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9707 * to dirty logging mode.
9708 *
9709 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9710 *
9711 * In case of write protect:
9712 *
9713 * Write protect all pages for dirty logging.
9714 *
9715 * All the sptes including the large sptes which point to this
9716 * slot are set to readonly. We can not create any new large
9717 * spte on this slot until the end of the logging.
9718 *
9719 * See the comments in fast_page_fault().
9720 */
9721 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9722 if (kvm_x86_ops->slot_enable_log_dirty)
9723 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9724 else
9725 kvm_mmu_slot_remove_write_access(kvm, new);
9726 } else {
9727 if (kvm_x86_ops->slot_disable_log_dirty)
9728 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9729 }
9730}
9731
f7784b8e 9732void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9733 const struct kvm_userspace_memory_region *mem,
8482644a 9734 const struct kvm_memory_slot *old,
f36f3f28 9735 const struct kvm_memory_slot *new,
8482644a 9736 enum kvm_mr_change change)
f7784b8e 9737{
48c0e4e9 9738 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9739 kvm_mmu_change_mmu_pages(kvm,
9740 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9741
3ea3b7fa
WL		 9742 /*
9743 * Dirty logging tracks sptes in 4k granularity, meaning that large
9744 * sptes have to be split. If live migration is successful, the guest
9745 * in the source machine will be destroyed and large sptes will be
9746 * created in the destination. However, if the guest continues to run
9747 * in the source machine (for example if live migration fails), small
9748 * sptes will remain around and cause bad performance.
9749 *
9750 * Scan sptes if dirty logging has been stopped, dropping those
9751 * which can be collapsed into a single large-page spte. Later
9752 * page faults will create the large-page sptes.
319109a2
SC		 9753 *
9754 * There is no need to do this in any of the following cases:
9755 * CREATE: No dirty mappings will already exist.
9756 * MOVE/DELETE: The old mappings will already have been cleaned up by
9757 * kvm_arch_flush_shadow_memslot()
3ea3b7fa 9758 */
319109a2 9759 if (change == KVM_MR_FLAGS_ONLY &&
3ea3b7fa
WL		 9760 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9761 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9762 kvm_mmu_zap_collapsible_sptes(kvm, new);
9763
c972f3b1 9764 /*
88178fd4 9765 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9766 *
88178fd4
KH		 9767 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9768 * been zapped so no dirty logging staff is needed for old slot. For
9769 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9770 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9771 *
9772 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9773 */
88178fd4 9774 if (change != KVM_MR_DELETE)
f36f3f28 9775 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9776}
1d737c8a 9777
2df72e9b 9778void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9779{
7390de1e 9780 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9781}
9782
2df72e9b
MT		 9783void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9784 struct kvm_memory_slot *slot)
9785{
ae7cd873 9786 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9787}
9788
e6c67d8c
LA		 9789static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9790{
9791 return (is_guest_mode(vcpu) &&
9792 kvm_x86_ops->guest_apic_has_interrupt &&
9793 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9794}
9795
5d9bc648
PB		 9796static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9797{
9798 if (!list_empty_careful(&vcpu->async_pf.done))
9799 return true;
9800
9801 if (kvm_apic_has_events(vcpu))
9802 return true;
9803
9804 if (vcpu->arch.pv.pv_unhalted)
9805 return true;
9806
a5f01f8e
WL		 9807 if (vcpu->arch.exception.pending)
9808 return true;
9809
47a66eed
Z		 9810 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9811 (vcpu->arch.nmi_pending &&
9812 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9813 return true;
9814
47a66eed
Z		 9815 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9816 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9817 return true;
9818
5d9bc648 9819 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9820 (kvm_cpu_has_interrupt(vcpu) ||
9821 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9822 return true;
9823
1f4b34f8
AS		 9824 if (kvm_hv_has_stimer_pending(vcpu))
9825 return true;
9826
5d9bc648
PB		 9827 return false;
9828}
9829
1d737c8a
ZX		 9830int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9831{
5d9bc648 9832 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9833}
5736199a 9834
17e433b5
WL		 9835bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9836{
9837 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9838 return true;
9839
9840 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9841 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9842 kvm_test_request(KVM_REQ_EVENT, vcpu))
9843 return true;
9844
9845 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9846 return true;
9847
9848 return false;
9849}
9850
199b5763
LM		 9851bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9852{
de63ad4c 9853 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9854}
9855
b6d33834 9856int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9857{
b6d33834 9858 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9859}
78646121
GN		 9860
9861int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9862{
9863 return kvm_x86_ops->interrupt_allowed(vcpu);
9864}
229456fc 9865
82b32774 9866unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9867{
82b32774
NA		 9868 if (is_64_bit_mode(vcpu))
9869 return kvm_rip_read(vcpu);
9870 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9871 kvm_rip_read(vcpu));
9872}
9873EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9874
82b32774
NA		 9875bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9876{
9877 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9878}
9879EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9880
94fe45da
JK		 9881unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9882{
9883 unsigned long rflags;
9884
9885 rflags = kvm_x86_ops->get_rflags(vcpu);
9886 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9887 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9888 return rflags;
9889}
9890EXPORT_SYMBOL_GPL(kvm_get_rflags);
9891
6addfc42 9892static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9893{
9894 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9895 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9896 rflags |= X86_EFLAGS_TF;
94fe45da 9897 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9898}
9899
9900void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9901{
9902 __kvm_set_rflags(vcpu, rflags);
3842d135 9903 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9904}
9905EXPORT_SYMBOL_GPL(kvm_set_rflags);
9906
56028d08
GN		 9907void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9908{
9909 int r;
9910
44dd3ffa 9911 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9912 work->wakeup_all)
56028d08
GN		 9913 return;
9914
9915 r = kvm_mmu_reload(vcpu);
9916 if (unlikely(r))
9917 return;
9918
44dd3ffa
VK		 9919 if (!vcpu->arch.mmu->direct_map &&
9920 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9921 return;
9922
44dd3ffa 9923 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9924}
9925
af585b92
GN		 9926static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9927{
9928 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9929}
9930
9931static inline u32 kvm_async_pf_next_probe(u32 key)
9932{
9933 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9934}
9935
9936static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9937{
9938 u32 key = kvm_async_pf_hash_fn(gfn);
9939
9940 while (vcpu->arch.apf.gfns[key] != ~0)
9941 key = kvm_async_pf_next_probe(key);
9942
9943 vcpu->arch.apf.gfns[key] = gfn;
9944}
9945
9946static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9947{
9948 int i;
9949 u32 key = kvm_async_pf_hash_fn(gfn);
9950
9951 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9952 (vcpu->arch.apf.gfns[key] != gfn &&
9953 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9954 key = kvm_async_pf_next_probe(key);
9955
9956 return key;
9957}
9958
9959bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9960{
9961 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9962}
9963
9964static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9965{
9966 u32 i, j, k;
9967
9968 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9969 while (true) {
9970 vcpu->arch.apf.gfns[i] = ~0;
9971 do {
9972 j = kvm_async_pf_next_probe(j);
9973 if (vcpu->arch.apf.gfns[j] == ~0)
9974 return;
9975 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9976 /*
9977 * k lies cyclically in ]i,j]
9978 * | i.k.j |
9979 * |....j i.k.| or |.k..j i...|
9980 */
9981 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9982 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9983 i = j;
9984 }
9985}
9986
7c90705b
GN		 9987static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9988{
4e335d9e
PB		 9989
9990 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9991 sizeof(val));
7c90705b
GN		 9992}
9993
9a6e7c39
WL		 9994static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9995{
9996
9997 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9998 sizeof(u32));
9999}
10000
1dfdb45e
PB		 10001static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10002{
10003 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10004 return false;
10005
10006 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10007 (vcpu->arch.apf.send_user_only &&
10008 kvm_x86_ops->get_cpl(vcpu) == 0))
10009 return false;
10010
10011 return true;
10012}
10013
10014bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10015{
10016 if (unlikely(!lapic_in_kernel(vcpu) ||
10017 kvm_event_needs_reinjection(vcpu) ||
10018 vcpu->arch.exception.pending))
10019 return false;
10020
10021 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10022 return false;
10023
10024 /*
10025 * If interrupts are off we cannot even use an artificial
10026 * halt state.
10027 */
10028 return kvm_x86_ops->interrupt_allowed(vcpu);
10029}
10030
af585b92
GN		 10031void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10032 struct kvm_async_pf *work)
10033{
6389ee94
AK		 10034 struct x86_exception fault;
10035
7c90705b 10036 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 10037 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b 10038
1dfdb45e
PB		 10039 if (kvm_can_deliver_async_pf(vcpu) &&
10040 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 10041 fault.vector = PF_VECTOR;
10042 fault.error_code_valid = true;
10043 fault.error_code = 0;
10044 fault.nested_page_fault = false;
10045 fault.address = work->arch.token;
adfe20fb 10046 fault.async_page_fault = true;
6389ee94 10047 kvm_inject_page_fault(vcpu, &fault);
1dfdb45e
PB		 10048 } else {
10049 /*
10050 * It is not possible to deliver a paravirtualized asynchronous
10051 * page fault, but putting the guest in an artificial halt state
10052 * can be beneficial nevertheless: if an interrupt arrives, we
10053 * can deliver it timely and perhaps the guest will schedule
10054 * another process. When the instruction that triggered a page
10055 * fault is retried, hopefully the page will be ready in the host.
10056 */
10057 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7c90705b 10058 }
af585b92
GN		 10059}
10060
10061void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10062 struct kvm_async_pf *work)
10063{
6389ee94 10064 struct x86_exception fault;
9a6e7c39 10065 u32 val;
6389ee94 10066
f2e10669 10067 if (work->wakeup_all)
7c90705b
GN		 10068 work->arch.token = ~0; /* broadcast wakeup */
10069 else
10070 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 10071 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 10072
9a6e7c39
WL		 10073 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10074 !apf_get_user(vcpu, &val)) {
10075 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10076 vcpu->arch.exception.pending &&
10077 vcpu->arch.exception.nr == PF_VECTOR &&
10078 !apf_put_user(vcpu, 0)) {
10079 vcpu->arch.exception.injected = false;
10080 vcpu->arch.exception.pending = false;
10081 vcpu->arch.exception.nr = 0;
10082 vcpu->arch.exception.has_error_code = false;
10083 vcpu->arch.exception.error_code = 0;
c851436a
JM		 10084 vcpu->arch.exception.has_payload = false;
10085 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 10086 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10087 fault.vector = PF_VECTOR;
10088 fault.error_code_valid = true;
10089 fault.error_code = 0;
10090 fault.nested_page_fault = false;
10091 fault.address = work->arch.token;
10092 fault.async_page_fault = true;
10093 kvm_inject_page_fault(vcpu, &fault);
10094 }
7c90705b 10095 }
e6d53e3b 10096 vcpu->arch.apf.halted = false;
a4fa1635 10097 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 10098}
10099
10100bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10101{
10102 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10103 return true;
10104 else
9bc1f09f 10105 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 10106}
10107
5544eb9b
PB		 10108void kvm_arch_start_assignment(struct kvm *kvm)
10109{
10110 atomic_inc(&kvm->arch.assigned_device_count);
10111}
10112EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10113
10114void kvm_arch_end_assignment(struct kvm *kvm)
10115{
10116 atomic_dec(&kvm->arch.assigned_device_count);
10117}
10118EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10119
10120bool kvm_arch_has_assigned_device(struct kvm *kvm)
10121{
10122 return atomic_read(&kvm->arch.assigned_device_count);
10123}
10124EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10125
e0f0bbc5
AW		 10126void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10127{
10128 atomic_inc(&kvm->arch.noncoherent_dma_count);
10129}
10130EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10131
10132void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10133{
10134 atomic_dec(&kvm->arch.noncoherent_dma_count);
10135}
10136EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10137
10138bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10139{
10140 return atomic_read(&kvm->arch.noncoherent_dma_count);
10141}
10142EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10143
14717e20
AW		 10144bool kvm_arch_has_irq_bypass(void)
10145{
92735b1b 10146 return true;
14717e20
AW		 10147}
10148
87276880
FW		 10149int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10150 struct irq_bypass_producer *prod)
10151{
10152 struct kvm_kernel_irqfd *irqfd =
10153 container_of(cons, struct kvm_kernel_irqfd, consumer);
10154
14717e20 10155 irqfd->producer = prod;
87276880 10156
14717e20
AW		 10157 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10158 prod->irq, irqfd->gsi, 1);
87276880
FW		 10159}
10160
10161void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10162 struct irq_bypass_producer *prod)
10163{
10164 int ret;
10165 struct kvm_kernel_irqfd *irqfd =
10166 container_of(cons, struct kvm_kernel_irqfd, consumer);
10167
87276880
FW		 10168 WARN_ON(irqfd->producer != prod);
10169 irqfd->producer = NULL;
10170
10171 /*
10172 * When producer of consumer is unregistered, we change back to
10173 * remapped mode, so we can re-use the current implementation
bb3541f1 10174 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 10175 * int this case doesn't want to receive the interrupts.
10176 */
10177 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10178 if (ret)
10179 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10180 " fails: %d\n", irqfd->consumer.token, ret);
10181}
10182
10183int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10184 uint32_t guest_irq, bool set)
10185{
87276880
FW		 10186 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10187}
10188
52004014
FW		 10189bool kvm_vector_hashing_enabled(void)
10190{
10191 return vector_hashing;
10192}
10193EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10194
2d5ba19b
MT		 10195bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10196{
10197 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10198}
10199EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10200
10201
229456fc 10202EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 10203EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 10204EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10205EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10206EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10207EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 10208EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 10209EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 10210EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 10211EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
5497b955 10212EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
ec1ff790 10213EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 10214EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 10215EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 10216EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
4f75bcc3 10217EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
843e4330 10218EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 10219EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 10220EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10221EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)