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KVM: x86: add new KVMCLOCK cpuid feature
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
ff9d07a0 43#include <linux/perf_event.h>
aec51dc4 44#include <trace/events/kvm.h>
2ed152af 45
229456fc
MT		 46#define CREATE_TRACE_POINTS
47#include "trace.h"
043405e1 48
24f1e32c 49#include <asm/debugreg.h>
043405e1 50#include <asm/uaccess.h>
d825ed0a 51#include <asm/msr.h>
a5f61300 52#include <asm/desc.h>
0bed3b56 53#include <asm/mtrr.h>
890ca9ae 54#include <asm/mce.h>
043405e1 55
313a3dc7 56#define MAX_IO_MSRS 256
a03490ed
CO		 57#define CR0_RESERVED_BITS \
58 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
59 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
60 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
61#define CR4_RESERVED_BITS \
62 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
63 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
64 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
65 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
66
67#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 68
69#define KVM_MAX_MCE_BANKS 32
70#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
78#else
79static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 86static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
87 struct kvm_cpuid_entry2 __user *entries);
88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
ed85c068
AP		 92int ignore_msrs = 0;
93module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
18863bdd
AK		 95#define KVM_NR_SHARED_MSRS 16
96
97struct kvm_shared_msrs_global {
98 int nr;
2bf78fa7 99 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 100};
101
102struct kvm_shared_msrs {
103 struct user_return_notifier urn;
104 bool registered;
2bf78fa7
SY		 105 struct kvm_shared_msr_values {
106 u64 host;
107 u64 curr;
108 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
112static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
113
417bc304 114struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 115 { "pf_fixed", VCPU_STAT(pf_fixed) },
116 { "pf_guest", VCPU_STAT(pf_guest) },
117 { "tlb_flush", VCPU_STAT(tlb_flush) },
118 { "invlpg", VCPU_STAT(invlpg) },
119 { "exits", VCPU_STAT(exits) },
120 { "io_exits", VCPU_STAT(io_exits) },
121 { "mmio_exits", VCPU_STAT(mmio_exits) },
122 { "signal_exits", VCPU_STAT(signal_exits) },
123 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 124 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 125 { "halt_exits", VCPU_STAT(halt_exits) },
126 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 127 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 128 { "request_irq", VCPU_STAT(request_irq_exits) },
129 { "irq_exits", VCPU_STAT(irq_exits) },
130 { "host_state_reload", VCPU_STAT(host_state_reload) },
131 { "efer_reload", VCPU_STAT(efer_reload) },
132 { "fpu_reload", VCPU_STAT(fpu_reload) },
133 { "insn_emulation", VCPU_STAT(insn_emulation) },
134 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 135 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 136 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 137 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
138 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
139 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
140 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
141 { "mmu_flooded", VM_STAT(mmu_flooded) },
142 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 143 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 144 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 145 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 146 { "largepages", VM_STAT(lpages) },
417bc304
HB		 147 { NULL }
148};
149
18863bdd
AK		 150static void kvm_on_user_return(struct user_return_notifier *urn)
151{
152 unsigned slot;
18863bdd
AK		 153 struct kvm_shared_msrs *locals
154 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 155 struct kvm_shared_msr_values *values;
18863bdd
AK		 156
157 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 158 values = &locals->values[slot];
159 if (values->host != values->curr) {
160 wrmsrl(shared_msrs_global.msrs[slot], values->host);
161 values->curr = values->host;
18863bdd
AK		 162 }
163 }
164 locals->registered = false;
165 user_return_notifier_unregister(urn);
166}
167
2bf78fa7 168static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 169{
2bf78fa7 170 struct kvm_shared_msrs *smsr;
18863bdd
AK		 171 u64 value;
172
2bf78fa7
SY		 173 smsr = &__get_cpu_var(shared_msrs);
174 /* only read, and nobody should modify it at this time,
175 * so don't need lock */
176 if (slot >= shared_msrs_global.nr) {
177 printk(KERN_ERR "kvm: invalid MSR slot!");
178 return;
179 }
180 rdmsrl_safe(msr, &value);
181 smsr->values[slot].host = value;
182 smsr->values[slot].curr = value;
183}
184
185void kvm_define_shared_msr(unsigned slot, u32 msr)
186{
18863bdd
AK		 187 if (slot >= shared_msrs_global.nr)
188 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 189 shared_msrs_global.msrs[slot] = msr;
190 /* we need ensured the shared_msr_global have been updated */
191 smp_wmb();
18863bdd
AK		 192}
193EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
194
195static void kvm_shared_msr_cpu_online(void)
196{
197 unsigned i;
18863bdd
AK		 198
199 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 200 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 201}
202
d5696725 203void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 204{
205 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
206
2bf78fa7 207 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 208 return;
2bf78fa7
SY		 209 smsr->values[slot].curr = value;
210 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 211 if (!smsr->registered) {
212 smsr->urn.on_user_return = kvm_on_user_return;
213 user_return_notifier_register(&smsr->urn);
214 smsr->registered = true;
215 }
216}
217EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
218
3548bab5
AK		 219static void drop_user_return_notifiers(void *ignore)
220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
223 if (smsr->registered)
224 kvm_on_user_return(&smsr->urn);
225}
226
6866b83e
CO		 227u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
228{
229 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 230 return vcpu->arch.apic_base;
6866b83e 231 else
ad312c7c 232 return vcpu->arch.apic_base;
6866b83e
CO		 233}
234EXPORT_SYMBOL_GPL(kvm_get_apic_base);
235
236void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
237{
238 /* TODO: reserve bits check */
239 if (irqchip_in_kernel(vcpu->kvm))
240 kvm_lapic_set_base(vcpu, data);
241 else
ad312c7c 242 vcpu->arch.apic_base = data;
6866b83e
CO		 243}
244EXPORT_SYMBOL_GPL(kvm_set_apic_base);
245
3fd28fce
ED		 246#define EXCPT_BENIGN 0
247#define EXCPT_CONTRIBUTORY 1
248#define EXCPT_PF 2
249
250static int exception_class(int vector)
251{
252 switch (vector) {
253 case PF_VECTOR:
254 return EXCPT_PF;
255 case DE_VECTOR:
256 case TS_VECTOR:
257 case NP_VECTOR:
258 case SS_VECTOR:
259 case GP_VECTOR:
260 return EXCPT_CONTRIBUTORY;
261 default:
262 break;
263 }
264 return EXCPT_BENIGN;
265}
266
267static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 268 unsigned nr, bool has_error, u32 error_code,
269 bool reinject)
3fd28fce
ED		 270{
271 u32 prev_nr;
272 int class1, class2;
273
274 if (!vcpu->arch.exception.pending) {
275 queue:
276 vcpu->arch.exception.pending = true;
277 vcpu->arch.exception.has_error_code = has_error;
278 vcpu->arch.exception.nr = nr;
279 vcpu->arch.exception.error_code = error_code;
3f0fd292 280 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 281 return;
282 }
283
284 /* to check exception */
285 prev_nr = vcpu->arch.exception.nr;
286 if (prev_nr == DF_VECTOR) {
287 /* triple fault -> shutdown */
288 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
289 return;
290 }
291 class1 = exception_class(prev_nr);
292 class2 = exception_class(nr);
293 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
294 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
295 /* generate double fault per SDM Table 5-5 */
296 vcpu->arch.exception.pending = true;
297 vcpu->arch.exception.has_error_code = true;
298 vcpu->arch.exception.nr = DF_VECTOR;
299 vcpu->arch.exception.error_code = 0;
300 } else
301 /* replace previous exception with a new one in a hope
302 that instruction re-execution will regenerate lost
303 exception */
304 goto queue;
305}
306
298101da
AK		 307void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
308{
ce7ddec4 309 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 310}
311EXPORT_SYMBOL_GPL(kvm_queue_exception);
312
ce7ddec4
JR		 313void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
314{
315 kvm_multiple_exception(vcpu, nr, false, 0, true);
316}
317EXPORT_SYMBOL_GPL(kvm_requeue_exception);
318
c3c91fee
AK		 319void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
320 u32 error_code)
321{
322 ++vcpu->stat.pf_guest;
ad312c7c 323 vcpu->arch.cr2 = addr;
c3c91fee
AK		 324 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
325}
326
3419ffc8
SY		 327void kvm_inject_nmi(struct kvm_vcpu *vcpu)
328{
329 vcpu->arch.nmi_pending = 1;
330}
331EXPORT_SYMBOL_GPL(kvm_inject_nmi);
332
298101da
AK		 333void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
334{
ce7ddec4 335 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 336}
337EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
338
ce7ddec4
JR		 339void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
340{
341 kvm_multiple_exception(vcpu, nr, true, error_code, true);
342}
343EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
344
0a79b009
AK		 345/*
346 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
347 * a #GP and return false.
348 */
349bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 350{
0a79b009
AK		 351 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
352 return true;
353 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
354 return false;
298101da 355}
0a79b009 356EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 357
a03490ed
CO		 358/*
359 * Load the pae pdptrs. Return true is they are all valid.
360 */
361int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
362{
363 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
364 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
365 int i;
366 int ret;
ad312c7c 367 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 368
a03490ed
CO		 369 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
370 offset * sizeof(u64), sizeof(pdpte));
371 if (ret < 0) {
372 ret = 0;
373 goto out;
374 }
375 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 376 if (is_present_gpte(pdpte[i]) &&
20c466b5 377 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 378 ret = 0;
379 goto out;
380 }
381 }
382 ret = 1;
383
ad312c7c 384 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 385 __set_bit(VCPU_EXREG_PDPTR,
386 (unsigned long *)&vcpu->arch.regs_avail);
387 __set_bit(VCPU_EXREG_PDPTR,
388 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 389out:
a03490ed
CO		 390
391 return ret;
392}
cc4b6871 393EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 394
d835dfec
AK		 395static bool pdptrs_changed(struct kvm_vcpu *vcpu)
396{
ad312c7c 397 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 398 bool changed = true;
399 int r;
400
401 if (is_long_mode(vcpu) || !is_pae(vcpu))
402 return false;
403
6de4f3ad
AK		 404 if (!test_bit(VCPU_EXREG_PDPTR,
405 (unsigned long *)&vcpu->arch.regs_avail))
406 return true;
407
ad312c7c 408 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 409 if (r < 0)
410 goto out;
ad312c7c 411 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 412out:
d835dfec
AK		 413
414 return changed;
415}
416
2d3ad1f4 417void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 418{
f9a48e6a
AK		 419 cr0 |= X86_CR0_ET;
420
ab344828
GN		 421#ifdef CONFIG_X86_64
422 if (cr0 & 0xffffffff00000000UL) {
c1a5d4f9 423 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 424 return;
425 }
ab344828
GN		 426#endif
427
428 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 429
430 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
c1a5d4f9 431 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 432 return;
433 }
434
435 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438 }
439
440 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
441#ifdef CONFIG_X86_64
f6801dff 442 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 443 int cs_db, cs_l;
444
445 if (!is_pae(vcpu)) {
c1a5d4f9 446 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 447 return;
448 }
449 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
450 if (cs_l) {
c1a5d4f9 451 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 452 return;
453
454 }
455 } else
456#endif
ad312c7c 457 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 458 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 459 return;
460 }
461
462 }
463
464 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 465
a03490ed 466 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 467 return;
468}
2d3ad1f4 469EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 470
2d3ad1f4 471void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 472{
4d4ec087 473 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 474}
2d3ad1f4 475EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 476
2d3ad1f4 477void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 478{
fc78f519 479 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 480 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
481
a03490ed 482 if (cr4 & CR4_RESERVED_BITS) {
c1a5d4f9 483 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 484 return;
485 }
486
487 if (is_long_mode(vcpu)) {
488 if (!(cr4 & X86_CR4_PAE)) {
c1a5d4f9 489 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 490 return;
491 }
a2edf57f
AK		 492 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
493 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 494 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 495 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 496 return;
497 }
498
499 if (cr4 & X86_CR4_VMXE) {
c1a5d4f9 500 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 501 return;
502 }
503 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 504 vcpu->arch.cr4 = cr4;
a03490ed 505 kvm_mmu_reset_context(vcpu);
a03490ed 506}
2d3ad1f4 507EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 508
2d3ad1f4 509void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 510{
ad312c7c 511 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 512 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 513 kvm_mmu_flush_tlb(vcpu);
514 return;
515 }
516
a03490ed
CO		 517 if (is_long_mode(vcpu)) {
518 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
c1a5d4f9 519 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 520 return;
521 }
522 } else {
523 if (is_pae(vcpu)) {
524 if (cr3 & CR3_PAE_RESERVED_BITS) {
c1a5d4f9 525 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 526 return;
527 }
528 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
c1a5d4f9 529 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 530 return;
531 }
532 }
533 /*
534 * We don't check reserved bits in nonpae mode, because
535 * this isn't enforced, and VMware depends on this.
536 */
537 }
538
a03490ed
CO		 539 /*
540 * Does the new cr3 value map to physical memory? (Note, we
541 * catch an invalid cr3 even in real-mode, because it would
542 * cause trouble later on when we turn on paging anyway.)
543 *
544 * A real CPU would silently accept an invalid cr3 and would
545 * attempt to use it - with largely undefined (and often hard
546 * to debug) behavior on the guest side.
547 */
548 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 549 kvm_inject_gp(vcpu, 0);
a03490ed 550 else {
ad312c7c
ZX		 551 vcpu->arch.cr3 = cr3;
552 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 553 }
a03490ed 554}
2d3ad1f4 555EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 556
2d3ad1f4 557void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 558{
559 if (cr8 & CR8_RESERVED_BITS) {
c1a5d4f9 560 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 561 return;
562 }
563 if (irqchip_in_kernel(vcpu->kvm))
564 kvm_lapic_set_tpr(vcpu, cr8);
565 else
ad312c7c 566 vcpu->arch.cr8 = cr8;
a03490ed 567}
2d3ad1f4 568EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 569
2d3ad1f4 570unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 571{
572 if (irqchip_in_kernel(vcpu->kvm))
573 return kvm_lapic_get_cr8(vcpu);
574 else
ad312c7c 575 return vcpu->arch.cr8;
a03490ed 576}
2d3ad1f4 577EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 578
020df079
GN		 579int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
580{
581 switch (dr) {
582 case 0 ... 3:
583 vcpu->arch.db[dr] = val;
584 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
585 vcpu->arch.eff_db[dr] = val;
586 break;
587 case 4:
588 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
589 kvm_queue_exception(vcpu, UD_VECTOR);
590 return 1;
591 }
592 /* fall through */
593 case 6:
594 if (val & 0xffffffff00000000ULL) {
595 kvm_inject_gp(vcpu, 0);
596 return 1;
597 }
598 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
599 break;
600 case 5:
601 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
602 kvm_queue_exception(vcpu, UD_VECTOR);
603 return 1;
604 }
605 /* fall through */
606 default: /* 7 */
607 if (val & 0xffffffff00000000ULL) {
608 kvm_inject_gp(vcpu, 0);
609 return 1;
610 }
611 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
612 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
613 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
614 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
615 }
616 break;
617 }
618
619 return 0;
620}
621EXPORT_SYMBOL_GPL(kvm_set_dr);
622
623int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
624{
625 switch (dr) {
626 case 0 ... 3:
627 *val = vcpu->arch.db[dr];
628 break;
629 case 4:
630 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
631 kvm_queue_exception(vcpu, UD_VECTOR);
632 return 1;
633 }
634 /* fall through */
635 case 6:
636 *val = vcpu->arch.dr6;
637 break;
638 case 5:
639 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
640 kvm_queue_exception(vcpu, UD_VECTOR);
641 return 1;
642 }
643 /* fall through */
644 default: /* 7 */
645 *val = vcpu->arch.dr7;
646 break;
647 }
648
649 return 0;
650}
651EXPORT_SYMBOL_GPL(kvm_get_dr);
652
d8017474
AG		 653static inline u32 bit(int bitno)
654{
655 return 1 << (bitno & 31);
656}
657
043405e1
CO		 658/*
659 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
660 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
661 *
662 * This list is modified at module load time to reflect the
e3267cbb
GC		 663 * capabilities of the host cpu. This capabilities test skips MSRs that are
664 * kvm-specific. Those are put in the beginning of the list.
043405e1 665 */
e3267cbb 666
11c6bffa 667#define KVM_SAVE_MSRS_BEGIN 7
043405e1 668static u32 msrs_to_save[] = {
e3267cbb 669 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 670 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 671 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 672 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 673 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
674 MSR_K6_STAR,
675#ifdef CONFIG_X86_64
676 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
677#endif
e3267cbb 678 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 679};
680
681static unsigned num_msrs_to_save;
682
683static u32 emulated_msrs[] = {
684 MSR_IA32_MISC_ENABLE,
685};
686
b69e8cae 687static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 688{
b69e8cae
RJ		 689 if (efer & efer_reserved_bits)
690 return 1;
15c4a640
CO		 691
692 if (is_paging(vcpu)
b69e8cae
RJ		 693 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
694 return 1;
15c4a640 695
1b2fd70c
AG		 696 if (efer & EFER_FFXSR) {
697 struct kvm_cpuid_entry2 *feat;
698
699 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 700 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
701 return 1;
1b2fd70c
AG		 702 }
703
d8017474
AG		 704 if (efer & EFER_SVME) {
705 struct kvm_cpuid_entry2 *feat;
706
707 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 708 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
709 return 1;
d8017474
AG		 710 }
711
15c4a640
CO		 712 kvm_x86_ops->set_efer(vcpu, efer);
713
714 efer &= ~EFER_LMA;
f6801dff 715 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 716
f6801dff 717 vcpu->arch.efer = efer;
9645bb56
AK		 718
719 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
720 kvm_mmu_reset_context(vcpu);
b69e8cae
RJ		 721
722 return 0;
15c4a640
CO		 723}
724
f2b4b7dd
JR		 725void kvm_enable_efer_bits(u64 mask)
726{
727 efer_reserved_bits &= ~mask;
728}
729EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
730
731
15c4a640
CO		 732/*
733 * Writes msr value into into the appropriate "register".
734 * Returns 0 on success, non-0 otherwise.
735 * Assumes vcpu_load() was already called.
736 */
737int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
738{
739 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
740}
741
313a3dc7
CO		 742/*
743 * Adapt set_msr() to msr_io()'s calling convention
744 */
745static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
746{
747 return kvm_set_msr(vcpu, index, *data);
748}
749
18068523
GOC		 750static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
751{
9ed3c444
AK		 752 int version;
753 int r;
50d0a0f9 754 struct pvclock_wall_clock wc;
923de3cf 755 struct timespec boot;
18068523
GOC		 756
757 if (!wall_clock)
758 return;
759
9ed3c444
AK		 760 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
761 if (r)
762 return;
763
764 if (version & 1)
765 ++version; /* first time write, random junk */
766
767 ++version;
18068523 768
18068523
GOC		 769 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
770
50d0a0f9
GH		 771 /*
772 * The guest calculates current wall clock time by adding
773 * system time (updated by kvm_write_guest_time below) to the
774 * wall clock specified here. guest system time equals host
775 * system time for us, thus we must fill in host boot time here.
776 */
923de3cf 777 getboottime(&boot);
50d0a0f9
GH		 778
779 wc.sec = boot.tv_sec;
780 wc.nsec = boot.tv_nsec;
781 wc.version = version;
18068523
GOC		 782
783 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
784
785 version++;
786 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 787}
788
50d0a0f9
GH		 789static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
790{
791 uint32_t quotient, remainder;
792
793 /* Don't try to replace with do_div(), this one calculates
794 * "(dividend << 32) / divisor" */
795 __asm__ ( "divl %4"
796 : "=a" (quotient), "=d" (remainder)
797 : "0" (0), "1" (dividend), "r" (divisor) );
798 return quotient;
799}
800
801static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
802{
803 uint64_t nsecs = 1000000000LL;
804 int32_t shift = 0;
805 uint64_t tps64;
806 uint32_t tps32;
807
808 tps64 = tsc_khz * 1000LL;
809 while (tps64 > nsecs*2) {
810 tps64 >>= 1;
811 shift--;
812 }
813
814 tps32 = (uint32_t)tps64;
815 while (tps32 <= (uint32_t)nsecs) {
816 tps32 <<= 1;
817 shift++;
818 }
819
820 hv_clock->tsc_shift = shift;
821 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
822
823 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 824 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 825 hv_clock->tsc_to_system_mul);
826}
827
c8076604
GH		 828static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
829
18068523
GOC		 830static void kvm_write_guest_time(struct kvm_vcpu *v)
831{
832 struct timespec ts;
833 unsigned long flags;
834 struct kvm_vcpu_arch *vcpu = &v->arch;
835 void *shared_kaddr;
463656c0 836 unsigned long this_tsc_khz;
18068523
GOC		 837
838 if ((!vcpu->time_page))
839 return;
840
463656c0
AK		 841 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
842 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
843 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
844 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 845 }
463656c0 846 put_cpu_var(cpu_tsc_khz);
50d0a0f9 847
18068523
GOC		 848 /* Keep irq disabled to prevent changes to the clock */
849 local_irq_save(flags);
af24a4e4 850 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 851 ktime_get_ts(&ts);
923de3cf 852 monotonic_to_bootbased(&ts);
18068523
GOC		 853 local_irq_restore(flags);
854
855 /* With all the info we got, fill in the values */
856
857 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 858 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
859
18068523
GOC		 860 /*
861 * The interface expects us to write an even number signaling that the
862 * update is finished. Since the guest won't see the intermediate
50d0a0f9 863 * state, we just increase by 2 at the end.
18068523 864 */
50d0a0f9 865 vcpu->hv_clock.version += 2;
18068523
GOC		 866
867 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
868
869 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 870 sizeof(vcpu->hv_clock));
18068523
GOC		 871
872 kunmap_atomic(shared_kaddr, KM_USER0);
873
874 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
875}
876
c8076604
GH		 877static int kvm_request_guest_time_update(struct kvm_vcpu *v)
878{
879 struct kvm_vcpu_arch *vcpu = &v->arch;
880
881 if (!vcpu->time_page)
882 return 0;
883 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
884 return 1;
885}
886
9ba075a6
AK		 887static bool msr_mtrr_valid(unsigned msr)
888{
889 switch (msr) {
890 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
891 case MSR_MTRRfix64K_00000:
892 case MSR_MTRRfix16K_80000:
893 case MSR_MTRRfix16K_A0000:
894 case MSR_MTRRfix4K_C0000:
895 case MSR_MTRRfix4K_C8000:
896 case MSR_MTRRfix4K_D0000:
897 case MSR_MTRRfix4K_D8000:
898 case MSR_MTRRfix4K_E0000:
899 case MSR_MTRRfix4K_E8000:
900 case MSR_MTRRfix4K_F0000:
901 case MSR_MTRRfix4K_F8000:
902 case MSR_MTRRdefType:
903 case MSR_IA32_CR_PAT:
904 return true;
905 case 0x2f8:
906 return true;
907 }
908 return false;
909}
910
d6289b93
MT		 911static bool valid_pat_type(unsigned t)
912{
913 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
914}
915
916static bool valid_mtrr_type(unsigned t)
917{
918 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
919}
920
921static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
922{
923 int i;
924
925 if (!msr_mtrr_valid(msr))
926 return false;
927
928 if (msr == MSR_IA32_CR_PAT) {
929 for (i = 0; i < 8; i++)
930 if (!valid_pat_type((data >> (i * 8)) & 0xff))
931 return false;
932 return true;
933 } else if (msr == MSR_MTRRdefType) {
934 if (data & ~0xcff)
935 return false;
936 return valid_mtrr_type(data & 0xff);
937 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
938 for (i = 0; i < 8 ; i++)
939 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
940 return false;
941 return true;
942 }
943
944 /* variable MTRRs */
945 return valid_mtrr_type(data & 0xff);
946}
947
9ba075a6
AK		 948static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
949{
0bed3b56
SY		 950 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
951
d6289b93 952 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 953 return 1;
954
0bed3b56
SY		 955 if (msr == MSR_MTRRdefType) {
956 vcpu->arch.mtrr_state.def_type = data;
957 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
958 } else if (msr == MSR_MTRRfix64K_00000)
959 p[0] = data;
960 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
961 p[1 + msr - MSR_MTRRfix16K_80000] = data;
962 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
963 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
964 else if (msr == MSR_IA32_CR_PAT)
965 vcpu->arch.pat = data;
966 else { /* Variable MTRRs */
967 int idx, is_mtrr_mask;
968 u64 *pt;
969
970 idx = (msr - 0x200) / 2;
971 is_mtrr_mask = msr - 0x200 - 2 * idx;
972 if (!is_mtrr_mask)
973 pt =
974 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
975 else
976 pt =
977 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
978 *pt = data;
979 }
980
981 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 982 return 0;
983}
15c4a640 984
890ca9ae 985static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 986{
890ca9ae
HY		 987 u64 mcg_cap = vcpu->arch.mcg_cap;
988 unsigned bank_num = mcg_cap & 0xff;
989
15c4a640 990 switch (msr) {
15c4a640 991 case MSR_IA32_MCG_STATUS:
890ca9ae 992 vcpu->arch.mcg_status = data;
15c4a640 993 break;
c7ac679c 994 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 995 if (!(mcg_cap & MCG_CTL_P))
996 return 1;
997 if (data != 0 && data != ~(u64)0)
998 return -1;
999 vcpu->arch.mcg_ctl = data;
1000 break;
1001 default:
1002 if (msr >= MSR_IA32_MC0_CTL &&
1003 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1004 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1005 /* only 0 or all 1s can be written to IA32_MCi_CTL
1006 * some Linux kernels though clear bit 10 in bank 4 to
1007 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1008 * this to avoid an uncatched #GP in the guest
1009 */
890ca9ae 1010 if ((offset & 0x3) == 0 &&
114be429 1011 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1012 return -1;
1013 vcpu->arch.mce_banks[offset] = data;
1014 break;
1015 }
1016 return 1;
1017 }
1018 return 0;
1019}
1020
ffde22ac
ES		 1021static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1022{
1023 struct kvm *kvm = vcpu->kvm;
1024 int lm = is_long_mode(vcpu);
1025 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1026 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1027 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1028 : kvm->arch.xen_hvm_config.blob_size_32;
1029 u32 page_num = data & ~PAGE_MASK;
1030 u64 page_addr = data & PAGE_MASK;
1031 u8 *page;
1032 int r;
1033
1034 r = -E2BIG;
1035 if (page_num >= blob_size)
1036 goto out;
1037 r = -ENOMEM;
1038 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1039 if (!page)
1040 goto out;
1041 r = -EFAULT;
1042 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1043 goto out_free;
1044 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1045 goto out_free;
1046 r = 0;
1047out_free:
1048 kfree(page);
1049out:
1050 return r;
1051}
1052
55cd8e5a
GN		 1053static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1054{
1055 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1056}
1057
1058static bool kvm_hv_msr_partition_wide(u32 msr)
1059{
1060 bool r = false;
1061 switch (msr) {
1062 case HV_X64_MSR_GUEST_OS_ID:
1063 case HV_X64_MSR_HYPERCALL:
1064 r = true;
1065 break;
1066 }
1067
1068 return r;
1069}
1070
1071static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1072{
1073 struct kvm *kvm = vcpu->kvm;
1074
1075 switch (msr) {
1076 case HV_X64_MSR_GUEST_OS_ID:
1077 kvm->arch.hv_guest_os_id = data;
1078 /* setting guest os id to zero disables hypercall page */
1079 if (!kvm->arch.hv_guest_os_id)
1080 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1081 break;
1082 case HV_X64_MSR_HYPERCALL: {
1083 u64 gfn;
1084 unsigned long addr;
1085 u8 instructions[4];
1086
1087 /* if guest os id is not set hypercall should remain disabled */
1088 if (!kvm->arch.hv_guest_os_id)
1089 break;
1090 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1091 kvm->arch.hv_hypercall = data;
1092 break;
1093 }
1094 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1095 addr = gfn_to_hva(kvm, gfn);
1096 if (kvm_is_error_hva(addr))
1097 return 1;
1098 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1099 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1100 if (copy_to_user((void __user *)addr, instructions, 4))
1101 return 1;
1102 kvm->arch.hv_hypercall = data;
1103 break;
1104 }
1105 default:
1106 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1107 "data 0x%llx\n", msr, data);
1108 return 1;
1109 }
1110 return 0;
1111}
1112
1113static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1114{
10388a07
GN		 1115 switch (msr) {
1116 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1117 unsigned long addr;
55cd8e5a 1118
10388a07
GN		 1119 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1120 vcpu->arch.hv_vapic = data;
1121 break;
1122 }
1123 addr = gfn_to_hva(vcpu->kvm, data >>
1124 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1125 if (kvm_is_error_hva(addr))
1126 return 1;
1127 if (clear_user((void __user *)addr, PAGE_SIZE))
1128 return 1;
1129 vcpu->arch.hv_vapic = data;
1130 break;
1131 }
1132 case HV_X64_MSR_EOI:
1133 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1134 case HV_X64_MSR_ICR:
1135 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1136 case HV_X64_MSR_TPR:
1137 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1138 default:
1139 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1140 "data 0x%llx\n", msr, data);
1141 return 1;
1142 }
1143
1144 return 0;
55cd8e5a
GN		 1145}
1146
15c4a640
CO		 1147int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1148{
1149 switch (msr) {
15c4a640 1150 case MSR_EFER:
b69e8cae 1151 return set_efer(vcpu, data);
8f1589d9
AP		 1152 case MSR_K7_HWCR:
1153 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1154 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1155 if (data != 0) {
1156 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1157 data);
1158 return 1;
1159 }
15c4a640 1160 break;
f7c6d140
AP		 1161 case MSR_FAM10H_MMIO_CONF_BASE:
1162 if (data != 0) {
1163 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1164 "0x%llx\n", data);
1165 return 1;
1166 }
15c4a640 1167 break;
c323c0e5 1168 case MSR_AMD64_NB_CFG:
c7ac679c 1169 break;
b5e2fec0
AG		 1170 case MSR_IA32_DEBUGCTLMSR:
1171 if (!data) {
1172 /* We support the non-activated case already */
1173 break;
1174 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1175 /* Values other than LBR and BTF are vendor-specific,
1176 thus reserved and should throw a #GP */
1177 return 1;
1178 }
1179 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1180 __func__, data);
1181 break;
15c4a640
CO		 1182 case MSR_IA32_UCODE_REV:
1183 case MSR_IA32_UCODE_WRITE:
61a6bd67 1184 case MSR_VM_HSAVE_PA:
6098ca93 1185 case MSR_AMD64_PATCH_LOADER:
15c4a640 1186 break;
9ba075a6
AK		 1187 case 0x200 ... 0x2ff:
1188 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1189 case MSR_IA32_APICBASE:
1190 kvm_set_apic_base(vcpu, data);
1191 break;
0105d1a5
GN		 1192 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1193 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1194 case MSR_IA32_MISC_ENABLE:
ad312c7c 1195 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1196 break;
11c6bffa 1197 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1198 case MSR_KVM_WALL_CLOCK:
1199 vcpu->kvm->arch.wall_clock = data;
1200 kvm_write_wall_clock(vcpu->kvm, data);
1201 break;
11c6bffa 1202 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1203 case MSR_KVM_SYSTEM_TIME: {
1204 if (vcpu->arch.time_page) {
1205 kvm_release_page_dirty(vcpu->arch.time_page);
1206 vcpu->arch.time_page = NULL;
1207 }
1208
1209 vcpu->arch.time = data;
1210
1211 /* we verify if the enable bit is set... */
1212 if (!(data & 1))
1213 break;
1214
1215 /* ...but clean it before doing the actual write */
1216 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1217
18068523
GOC		 1218 vcpu->arch.time_page =
1219 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1220
1221 if (is_error_page(vcpu->arch.time_page)) {
1222 kvm_release_page_clean(vcpu->arch.time_page);
1223 vcpu->arch.time_page = NULL;
1224 }
1225
c8076604 1226 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1227 break;
1228 }
890ca9ae
HY		 1229 case MSR_IA32_MCG_CTL:
1230 case MSR_IA32_MCG_STATUS:
1231 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1232 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1233
1234 /* Performance counters are not protected by a CPUID bit,
1235 * so we should check all of them in the generic path for the sake of
1236 * cross vendor migration.
1237 * Writing a zero into the event select MSRs disables them,
1238 * which we perfectly emulate ;-). Any other value should be at least
1239 * reported, some guests depend on them.
1240 */
1241 case MSR_P6_EVNTSEL0:
1242 case MSR_P6_EVNTSEL1:
1243 case MSR_K7_EVNTSEL0:
1244 case MSR_K7_EVNTSEL1:
1245 case MSR_K7_EVNTSEL2:
1246 case MSR_K7_EVNTSEL3:
1247 if (data != 0)
1248 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1249 "0x%x data 0x%llx\n", msr, data);
1250 break;
1251 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1252 * so we ignore writes to make it happy.
1253 */
1254 case MSR_P6_PERFCTR0:
1255 case MSR_P6_PERFCTR1:
1256 case MSR_K7_PERFCTR0:
1257 case MSR_K7_PERFCTR1:
1258 case MSR_K7_PERFCTR2:
1259 case MSR_K7_PERFCTR3:
1260 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1261 "0x%x data 0x%llx\n", msr, data);
1262 break;
55cd8e5a
GN		 1263 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1264 if (kvm_hv_msr_partition_wide(msr)) {
1265 int r;
1266 mutex_lock(&vcpu->kvm->lock);
1267 r = set_msr_hyperv_pw(vcpu, msr, data);
1268 mutex_unlock(&vcpu->kvm->lock);
1269 return r;
1270 } else
1271 return set_msr_hyperv(vcpu, msr, data);
1272 break;
15c4a640 1273 default:
ffde22ac
ES		 1274 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1275 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1276 if (!ignore_msrs) {
1277 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1278 msr, data);
1279 return 1;
1280 } else {
1281 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1282 msr, data);
1283 break;
1284 }
15c4a640
CO		 1285 }
1286 return 0;
1287}
1288EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1289
1290
1291/*
1292 * Reads an msr value (of 'msr_index') into 'pdata'.
1293 * Returns 0 on success, non-0 otherwise.
1294 * Assumes vcpu_load() was already called.
1295 */
1296int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1297{
1298 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1299}
1300
9ba075a6
AK		 1301static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1302{
0bed3b56
SY		 1303 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1304
9ba075a6
AK		 1305 if (!msr_mtrr_valid(msr))
1306 return 1;
1307
0bed3b56
SY		 1308 if (msr == MSR_MTRRdefType)
1309 *pdata = vcpu->arch.mtrr_state.def_type +
1310 (vcpu->arch.mtrr_state.enabled << 10);
1311 else if (msr == MSR_MTRRfix64K_00000)
1312 *pdata = p[0];
1313 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1314 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1315 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1316 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1317 else if (msr == MSR_IA32_CR_PAT)
1318 *pdata = vcpu->arch.pat;
1319 else { /* Variable MTRRs */
1320 int idx, is_mtrr_mask;
1321 u64 *pt;
1322
1323 idx = (msr - 0x200) / 2;
1324 is_mtrr_mask = msr - 0x200 - 2 * idx;
1325 if (!is_mtrr_mask)
1326 pt =
1327 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1328 else
1329 pt =
1330 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1331 *pdata = *pt;
1332 }
1333
9ba075a6
AK		 1334 return 0;
1335}
1336
890ca9ae 1337static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1338{
1339 u64 data;
890ca9ae
HY		 1340 u64 mcg_cap = vcpu->arch.mcg_cap;
1341 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1342
1343 switch (msr) {
15c4a640
CO		 1344 case MSR_IA32_P5_MC_ADDR:
1345 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1346 data = 0;
1347 break;
15c4a640 1348 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1349 data = vcpu->arch.mcg_cap;
1350 break;
c7ac679c 1351 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1352 if (!(mcg_cap & MCG_CTL_P))
1353 return 1;
1354 data = vcpu->arch.mcg_ctl;
1355 break;
1356 case MSR_IA32_MCG_STATUS:
1357 data = vcpu->arch.mcg_status;
1358 break;
1359 default:
1360 if (msr >= MSR_IA32_MC0_CTL &&
1361 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1362 u32 offset = msr - MSR_IA32_MC0_CTL;
1363 data = vcpu->arch.mce_banks[offset];
1364 break;
1365 }
1366 return 1;
1367 }
1368 *pdata = data;
1369 return 0;
1370}
1371
55cd8e5a
GN		 1372static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1373{
1374 u64 data = 0;
1375 struct kvm *kvm = vcpu->kvm;
1376
1377 switch (msr) {
1378 case HV_X64_MSR_GUEST_OS_ID:
1379 data = kvm->arch.hv_guest_os_id;
1380 break;
1381 case HV_X64_MSR_HYPERCALL:
1382 data = kvm->arch.hv_hypercall;
1383 break;
1384 default:
1385 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1386 return 1;
1387 }
1388
1389 *pdata = data;
1390 return 0;
1391}
1392
1393static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1394{
1395 u64 data = 0;
1396
1397 switch (msr) {
1398 case HV_X64_MSR_VP_INDEX: {
1399 int r;
1400 struct kvm_vcpu *v;
1401 kvm_for_each_vcpu(r, v, vcpu->kvm)
1402 if (v == vcpu)
1403 data = r;
1404 break;
1405 }
10388a07
GN		 1406 case HV_X64_MSR_EOI:
1407 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1408 case HV_X64_MSR_ICR:
1409 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1410 case HV_X64_MSR_TPR:
1411 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1412 default:
1413 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1414 return 1;
1415 }
1416 *pdata = data;
1417 return 0;
1418}
1419
890ca9ae
HY		 1420int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1421{
1422 u64 data;
1423
1424 switch (msr) {
890ca9ae 1425 case MSR_IA32_PLATFORM_ID:
15c4a640 1426 case MSR_IA32_UCODE_REV:
15c4a640 1427 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1428 case MSR_IA32_DEBUGCTLMSR:
1429 case MSR_IA32_LASTBRANCHFROMIP:
1430 case MSR_IA32_LASTBRANCHTOIP:
1431 case MSR_IA32_LASTINTFROMIP:
1432 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1433 case MSR_K8_SYSCFG:
1434 case MSR_K7_HWCR:
61a6bd67 1435 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1436 case MSR_P6_PERFCTR0:
1437 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1438 case MSR_P6_EVNTSEL0:
1439 case MSR_P6_EVNTSEL1:
9e699624 1440 case MSR_K7_EVNTSEL0:
1f3ee616 1441 case MSR_K7_PERFCTR0:
1fdbd48c 1442 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1443 case MSR_AMD64_NB_CFG:
f7c6d140 1444 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1445 data = 0;
1446 break;
9ba075a6
AK		 1447 case MSR_MTRRcap:
1448 data = 0x500 | KVM_NR_VAR_MTRR;
1449 break;
1450 case 0x200 ... 0x2ff:
1451 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1452 case 0xcd: /* fsb frequency */
1453 data = 3;
1454 break;
1455 case MSR_IA32_APICBASE:
1456 data = kvm_get_apic_base(vcpu);
1457 break;
0105d1a5
GN		 1458 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1459 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1460 break;
15c4a640 1461 case MSR_IA32_MISC_ENABLE:
ad312c7c 1462 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1463 break;
847f0ad8
AG		 1464 case MSR_IA32_PERF_STATUS:
1465 /* TSC increment by tick */
1466 data = 1000ULL;
1467 /* CPU multiplier */
1468 data |= (((uint64_t)4ULL) << 40);
1469 break;
15c4a640 1470 case MSR_EFER:
f6801dff 1471 data = vcpu->arch.efer;
15c4a640 1472 break;
18068523 1473 case MSR_KVM_WALL_CLOCK:
11c6bffa 1474 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1475 data = vcpu->kvm->arch.wall_clock;
1476 break;
1477 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1478 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1479 data = vcpu->arch.time;
1480 break;
890ca9ae
HY		 1481 case MSR_IA32_P5_MC_ADDR:
1482 case MSR_IA32_P5_MC_TYPE:
1483 case MSR_IA32_MCG_CAP:
1484 case MSR_IA32_MCG_CTL:
1485 case MSR_IA32_MCG_STATUS:
1486 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1487 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1488 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1489 if (kvm_hv_msr_partition_wide(msr)) {
1490 int r;
1491 mutex_lock(&vcpu->kvm->lock);
1492 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1493 mutex_unlock(&vcpu->kvm->lock);
1494 return r;
1495 } else
1496 return get_msr_hyperv(vcpu, msr, pdata);
1497 break;
15c4a640 1498 default:
ed85c068
AP		 1499 if (!ignore_msrs) {
1500 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1501 return 1;
1502 } else {
1503 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1504 data = 0;
1505 }
1506 break;
15c4a640
CO		 1507 }
1508 *pdata = data;
1509 return 0;
1510}
1511EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1512
313a3dc7
CO		 1513/*
1514 * Read or write a bunch of msrs. All parameters are kernel addresses.
1515 *
1516 * @return number of msrs set successfully.
1517 */
1518static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1519 struct kvm_msr_entry *entries,
1520 int (*do_msr)(struct kvm_vcpu *vcpu,
1521 unsigned index, u64 *data))
1522{
f656ce01 1523 int i, idx;
313a3dc7
CO		 1524
1525 vcpu_load(vcpu);
1526
f656ce01 1527 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1528 for (i = 0; i < msrs->nmsrs; ++i)
1529 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1530 break;
f656ce01 1531 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1532
1533 vcpu_put(vcpu);
1534
1535 return i;
1536}
1537
1538/*
1539 * Read or write a bunch of msrs. Parameters are user addresses.
1540 *
1541 * @return number of msrs set successfully.
1542 */
1543static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1544 int (*do_msr)(struct kvm_vcpu *vcpu,
1545 unsigned index, u64 *data),
1546 int writeback)
1547{
1548 struct kvm_msrs msrs;
1549 struct kvm_msr_entry *entries;
1550 int r, n;
1551 unsigned size;
1552
1553 r = -EFAULT;
1554 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1555 goto out;
1556
1557 r = -E2BIG;
1558 if (msrs.nmsrs >= MAX_IO_MSRS)
1559 goto out;
1560
1561 r = -ENOMEM;
1562 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1563 entries = vmalloc(size);
1564 if (!entries)
1565 goto out;
1566
1567 r = -EFAULT;
1568 if (copy_from_user(entries, user_msrs->entries, size))
1569 goto out_free;
1570
1571 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1572 if (r < 0)
1573 goto out_free;
1574
1575 r = -EFAULT;
1576 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1577 goto out_free;
1578
1579 r = n;
1580
1581out_free:
1582 vfree(entries);
1583out:
1584 return r;
1585}
1586
018d00d2
ZX		 1587int kvm_dev_ioctl_check_extension(long ext)
1588{
1589 int r;
1590
1591 switch (ext) {
1592 case KVM_CAP_IRQCHIP:
1593 case KVM_CAP_HLT:
1594 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1595 case KVM_CAP_SET_TSS_ADDR:
07716717 1596 case KVM_CAP_EXT_CPUID:
c8076604 1597 case KVM_CAP_CLOCKSOURCE:
7837699f 1598 case KVM_CAP_PIT:
a28e4f5a 1599 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1600 case KVM_CAP_MP_STATE:
ed848624 1601 case KVM_CAP_SYNC_MMU:
52d939a0 1602 case KVM_CAP_REINJECT_CONTROL:
4925663a 1603 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1604 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1605 case KVM_CAP_IRQFD:
d34e6b17 1606 case KVM_CAP_IOEVENTFD:
c5ff41ce 1607 case KVM_CAP_PIT2:
e9f42757 1608 case KVM_CAP_PIT_STATE2:
b927a3ce 1609 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1610 case KVM_CAP_XEN_HVM:
afbcf7ab 1611 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1612 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1613 case KVM_CAP_HYPERV:
10388a07 1614 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1615 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1616 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1617 case KVM_CAP_DEBUGREGS:
d2be1651 1618 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1619 r = 1;
1620 break;
542472b5
LV		 1621 case KVM_CAP_COALESCED_MMIO:
1622 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1623 break;
774ead3a
AK		 1624 case KVM_CAP_VAPIC:
1625 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1626 break;
f725230a
AK		 1627 case KVM_CAP_NR_VCPUS:
1628 r = KVM_MAX_VCPUS;
1629 break;
a988b910
AK		 1630 case KVM_CAP_NR_MEMSLOTS:
1631 r = KVM_MEMORY_SLOTS;
1632 break;
a68a6a72
MT		 1633 case KVM_CAP_PV_MMU: /* obsolete */
1634 r = 0;
2f333bcb 1635 break;
62c476c7 1636 case KVM_CAP_IOMMU:
19de40a8 1637 r = iommu_found();
62c476c7 1638 break;
890ca9ae
HY		 1639 case KVM_CAP_MCE:
1640 r = KVM_MAX_MCE_BANKS;
1641 break;
018d00d2
ZX		 1642 default:
1643 r = 0;
1644 break;
1645 }
1646 return r;
1647
1648}
1649
043405e1
CO		 1650long kvm_arch_dev_ioctl(struct file *filp,
1651 unsigned int ioctl, unsigned long arg)
1652{
1653 void __user *argp = (void __user *)arg;
1654 long r;
1655
1656 switch (ioctl) {
1657 case KVM_GET_MSR_INDEX_LIST: {
1658 struct kvm_msr_list __user *user_msr_list = argp;
1659 struct kvm_msr_list msr_list;
1660 unsigned n;
1661
1662 r = -EFAULT;
1663 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1664 goto out;
1665 n = msr_list.nmsrs;
1666 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1667 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1668 goto out;
1669 r = -E2BIG;
e125e7b6 1670 if (n < msr_list.nmsrs)
043405e1
CO		 1671 goto out;
1672 r = -EFAULT;
1673 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1674 num_msrs_to_save * sizeof(u32)))
1675 goto out;
e125e7b6 1676 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1677 &emulated_msrs,
1678 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1679 goto out;
1680 r = 0;
1681 break;
1682 }
674eea0f
AK		 1683 case KVM_GET_SUPPORTED_CPUID: {
1684 struct kvm_cpuid2 __user *cpuid_arg = argp;
1685 struct kvm_cpuid2 cpuid;
1686
1687 r = -EFAULT;
1688 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1689 goto out;
1690 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1691 cpuid_arg->entries);
674eea0f
AK		 1692 if (r)
1693 goto out;
1694
1695 r = -EFAULT;
1696 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1697 goto out;
1698 r = 0;
1699 break;
1700 }
890ca9ae
HY		 1701 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1702 u64 mce_cap;
1703
1704 mce_cap = KVM_MCE_CAP_SUPPORTED;
1705 r = -EFAULT;
1706 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1707 goto out;
1708 r = 0;
1709 break;
1710 }
043405e1
CO		 1711 default:
1712 r = -EINVAL;
1713 }
1714out:
1715 return r;
1716}
1717
313a3dc7
CO		 1718void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1719{
1720 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1721 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1722 unsigned long khz = cpufreq_quick_get(cpu);
1723 if (!khz)
1724 khz = tsc_khz;
1725 per_cpu(cpu_tsc_khz, cpu) = khz;
1726 }
c8076604 1727 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1728}
1729
1730void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1731{
9327fd11 1732 kvm_put_guest_fpu(vcpu);
02daab21 1733 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1734}
1735
07716717 1736static int is_efer_nx(void)
313a3dc7 1737{
e286e86e 1738 unsigned long long efer = 0;
313a3dc7 1739
e286e86e 1740 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1741 return efer & EFER_NX;
1742}
1743
1744static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1745{
1746 int i;
1747 struct kvm_cpuid_entry2 *e, *entry;
1748
313a3dc7 1749 entry = NULL;
ad312c7c
ZX		 1750 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1751 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1752 if (e->function == 0x80000001) {
1753 entry = e;
1754 break;
1755 }
1756 }
07716717 1757 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1758 entry->edx &= ~(1 << 20);
1759 printk(KERN_INFO "kvm: guest NX capability removed\n");
1760 }
1761}
1762
07716717 1763/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1764static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1765 struct kvm_cpuid *cpuid,
1766 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1767{
1768 int r, i;
1769 struct kvm_cpuid_entry *cpuid_entries;
1770
1771 r = -E2BIG;
1772 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1773 goto out;
1774 r = -ENOMEM;
1775 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1776 if (!cpuid_entries)
1777 goto out;
1778 r = -EFAULT;
1779 if (copy_from_user(cpuid_entries, entries,
1780 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1781 goto out_free;
1782 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1783 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1784 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1785 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1786 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1787 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1788 vcpu->arch.cpuid_entries[i].index = 0;
1789 vcpu->arch.cpuid_entries[i].flags = 0;
1790 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1791 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1792 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1793 }
1794 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1795 cpuid_fix_nx_cap(vcpu);
1796 r = 0;
fc61b800 1797 kvm_apic_set_version(vcpu);
0e851880 1798 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1799
1800out_free:
1801 vfree(cpuid_entries);
1802out:
1803 return r;
1804}
1805
1806static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1807 struct kvm_cpuid2 *cpuid,
1808 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1809{
1810 int r;
1811
1812 r = -E2BIG;
1813 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1814 goto out;
1815 r = -EFAULT;
ad312c7c 1816 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1817 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1818 goto out;
ad312c7c 1819 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1820 kvm_apic_set_version(vcpu);
0e851880 1821 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1822 return 0;
1823
1824out:
1825 return r;
1826}
1827
07716717 1828static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1829 struct kvm_cpuid2 *cpuid,
1830 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1831{
1832 int r;
1833
1834 r = -E2BIG;
ad312c7c 1835 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1836 goto out;
1837 r = -EFAULT;
ad312c7c 1838 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1839 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1840 goto out;
1841 return 0;
1842
1843out:
ad312c7c 1844 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1845 return r;
1846}
1847
07716717 1848static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1849 u32 index)
07716717
DK		 1850{
1851 entry->function = function;
1852 entry->index = index;
1853 cpuid_count(entry->function, entry->index,
19355475 1854 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1855 entry->flags = 0;
1856}
1857
7faa4ee1
AK		 1858#define F(x) bit(X86_FEATURE_##x)
1859
07716717
DK		 1860static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1861 u32 index, int *nent, int maxnent)
1862{
7faa4ee1 1863 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1864#ifdef CONFIG_X86_64
17cc3935
SY		 1865 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1866 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1867 unsigned f_lm = F(LM);
1868#else
17cc3935 1869 unsigned f_gbpages = 0;
7faa4ee1 1870 unsigned f_lm = 0;
07716717 1871#endif
4e47c7a6 1872 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1873
1874 /* cpuid 1.edx */
1875 const u32 kvm_supported_word0_x86_features =
1876 F(FPU) | F(VME) | F(DE) | F(PSE) |
1877 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1878 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1879 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1880 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1881 0 /* Reserved, DS, ACPI */ | F(MMX) |
1882 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1883 0 /* HTT, TM, Reserved, PBE */;
1884 /* cpuid 0x80000001.edx */
1885 const u32 kvm_supported_word1_x86_features =
1886 F(FPU) | F(VME) | F(DE) | F(PSE) |
1887 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1888 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1889 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1890 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1891 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1892 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1893 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1894 /* cpuid 1.ecx */
1895 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1896 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1897 0 /* DS-CPL, VMX, SMX, EST */ |
1898 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1899 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1900 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1901 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1902 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1903 /* cpuid 0x80000001.ecx */
07716717 1904 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1905 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1906 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1907 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1908 0 /* SKINIT */ | 0 /* WDT */;
07716717 1909
19355475 1910 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1911 get_cpu();
1912 do_cpuid_1_ent(entry, function, index);
1913 ++*nent;
1914
1915 switch (function) {
1916 case 0:
1917 entry->eax = min(entry->eax, (u32)0xb);
1918 break;
1919 case 1:
1920 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1921 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1922 /* we support x2apic emulation even if host does not support
1923 * it since we emulate x2apic in software */
1924 entry->ecx |= F(X2APIC);
07716717
DK		 1925 break;
1926 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1927 * may return different values. This forces us to get_cpu() before
1928 * issuing the first command, and also to emulate this annoying behavior
1929 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1930 case 2: {
1931 int t, times = entry->eax & 0xff;
1932
1933 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1934 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1935 for (t = 1; t < times && *nent < maxnent; ++t) {
1936 do_cpuid_1_ent(&entry[t], function, 0);
1937 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1938 ++*nent;
1939 }
1940 break;
1941 }
1942 /* function 4 and 0xb have additional index. */
1943 case 4: {
14af3f3c 1944 int i, cache_type;
07716717
DK		 1945
1946 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1947 /* read more entries until cache_type is zero */
14af3f3c
HH		 1948 for (i = 1; *nent < maxnent; ++i) {
1949 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1950 if (!cache_type)
1951 break;
14af3f3c
HH		 1952 do_cpuid_1_ent(&entry[i], function, i);
1953 entry[i].flags |=
07716717
DK		 1954 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1955 ++*nent;
1956 }
1957 break;
1958 }
1959 case 0xb: {
14af3f3c 1960 int i, level_type;
07716717
DK		 1961
1962 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1963 /* read more entries until level_type is zero */
14af3f3c 1964 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1965 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1966 if (!level_type)
1967 break;
14af3f3c
HH		 1968 do_cpuid_1_ent(&entry[i], function, i);
1969 entry[i].flags |=
07716717
DK		 1970 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1971 ++*nent;
1972 }
1973 break;
1974 }
1975 case 0x80000000:
1976 entry->eax = min(entry->eax, 0x8000001a);
1977 break;
1978 case 0x80000001:
1979 entry->edx &= kvm_supported_word1_x86_features;
1980 entry->ecx &= kvm_supported_word6_x86_features;
1981 break;
1982 }
d4330ef2
JR		 1983
1984 kvm_x86_ops->set_supported_cpuid(function, entry);
1985
07716717
DK		 1986 put_cpu();
1987}
1988
7faa4ee1
AK		 1989#undef F
1990
674eea0f 1991static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1992 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1993{
1994 struct kvm_cpuid_entry2 *cpuid_entries;
1995 int limit, nent = 0, r = -E2BIG;
1996 u32 func;
1997
1998 if (cpuid->nent < 1)
1999 goto out;
6a544355
AK		 2000 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2001 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2002 r = -ENOMEM;
2003 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2004 if (!cpuid_entries)
2005 goto out;
2006
2007 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2008 limit = cpuid_entries[0].eax;
2009 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2010 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2011 &nent, cpuid->nent);
07716717
DK		 2012 r = -E2BIG;
2013 if (nent >= cpuid->nent)
2014 goto out_free;
2015
2016 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2017 limit = cpuid_entries[nent - 1].eax;
2018 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2019 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2020 &nent, cpuid->nent);
cb007648
MM		 2021 r = -E2BIG;
2022 if (nent >= cpuid->nent)
2023 goto out_free;
2024
07716717
DK		 2025 r = -EFAULT;
2026 if (copy_to_user(entries, cpuid_entries,
19355475 2027 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2028 goto out_free;
2029 cpuid->nent = nent;
2030 r = 0;
2031
2032out_free:
2033 vfree(cpuid_entries);
2034out:
2035 return r;
2036}
2037
313a3dc7
CO		 2038static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2039 struct kvm_lapic_state *s)
2040{
2041 vcpu_load(vcpu);
ad312c7c 2042 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2043 vcpu_put(vcpu);
2044
2045 return 0;
2046}
2047
2048static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2049 struct kvm_lapic_state *s)
2050{
2051 vcpu_load(vcpu);
ad312c7c 2052 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2053 kvm_apic_post_state_restore(vcpu);
cb142eb7 2054 update_cr8_intercept(vcpu);
313a3dc7
CO		 2055 vcpu_put(vcpu);
2056
2057 return 0;
2058}
2059
f77bc6a4
ZX		 2060static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2061 struct kvm_interrupt *irq)
2062{
2063 if (irq->irq < 0 || irq->irq >= 256)
2064 return -EINVAL;
2065 if (irqchip_in_kernel(vcpu->kvm))
2066 return -ENXIO;
2067 vcpu_load(vcpu);
2068
66fd3f7f 2069 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2070
2071 vcpu_put(vcpu);
2072
2073 return 0;
2074}
2075
c4abb7c9
JK		 2076static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2077{
2078 vcpu_load(vcpu);
2079 kvm_inject_nmi(vcpu);
2080 vcpu_put(vcpu);
2081
2082 return 0;
2083}
2084
b209749f
AK		 2085static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2086 struct kvm_tpr_access_ctl *tac)
2087{
2088 if (tac->flags)
2089 return -EINVAL;
2090 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2091 return 0;
2092}
2093
890ca9ae
HY		 2094static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2095 u64 mcg_cap)
2096{
2097 int r;
2098 unsigned bank_num = mcg_cap & 0xff, bank;
2099
2100 r = -EINVAL;
a9e38c3e 2101 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2102 goto out;
2103 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2104 goto out;
2105 r = 0;
2106 vcpu->arch.mcg_cap = mcg_cap;
2107 /* Init IA32_MCG_CTL to all 1s */
2108 if (mcg_cap & MCG_CTL_P)
2109 vcpu->arch.mcg_ctl = ~(u64)0;
2110 /* Init IA32_MCi_CTL to all 1s */
2111 for (bank = 0; bank < bank_num; bank++)
2112 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2113out:
2114 return r;
2115}
2116
2117static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2118 struct kvm_x86_mce *mce)
2119{
2120 u64 mcg_cap = vcpu->arch.mcg_cap;
2121 unsigned bank_num = mcg_cap & 0xff;
2122 u64 *banks = vcpu->arch.mce_banks;
2123
2124 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2125 return -EINVAL;
2126 /*
2127 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2128 * reporting is disabled
2129 */
2130 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2131 vcpu->arch.mcg_ctl != ~(u64)0)
2132 return 0;
2133 banks += 4 * mce->bank;
2134 /*
2135 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2136 * reporting is disabled for the bank
2137 */
2138 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2139 return 0;
2140 if (mce->status & MCI_STATUS_UC) {
2141 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2142 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2143 printk(KERN_DEBUG "kvm: set_mce: "
2144 "injects mce exception while "
2145 "previous one is in progress!\n");
2146 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2147 return 0;
2148 }
2149 if (banks[1] & MCI_STATUS_VAL)
2150 mce->status |= MCI_STATUS_OVER;
2151 banks[2] = mce->addr;
2152 banks[3] = mce->misc;
2153 vcpu->arch.mcg_status = mce->mcg_status;
2154 banks[1] = mce->status;
2155 kvm_queue_exception(vcpu, MC_VECTOR);
2156 } else if (!(banks[1] & MCI_STATUS_VAL)
2157 || !(banks[1] & MCI_STATUS_UC)) {
2158 if (banks[1] & MCI_STATUS_VAL)
2159 mce->status |= MCI_STATUS_OVER;
2160 banks[2] = mce->addr;
2161 banks[3] = mce->misc;
2162 banks[1] = mce->status;
2163 } else
2164 banks[1] |= MCI_STATUS_OVER;
2165 return 0;
2166}
2167
3cfc3092
JK		 2168static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2169 struct kvm_vcpu_events *events)
2170{
2171 vcpu_load(vcpu);
2172
03b82a30
JK		 2173 events->exception.injected =
2174 vcpu->arch.exception.pending &&
2175 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2176 events->exception.nr = vcpu->arch.exception.nr;
2177 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2178 events->exception.error_code = vcpu->arch.exception.error_code;
2179
03b82a30
JK		 2180 events->interrupt.injected =
2181 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2182 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2183 events->interrupt.soft = 0;
48005f64
JK		 2184 events->interrupt.shadow =
2185 kvm_x86_ops->get_interrupt_shadow(vcpu,
2186 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2187
2188 events->nmi.injected = vcpu->arch.nmi_injected;
2189 events->nmi.pending = vcpu->arch.nmi_pending;
2190 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2191
2192 events->sipi_vector = vcpu->arch.sipi_vector;
2193
dab4b911 2194 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2195 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2196 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2197
2198 vcpu_put(vcpu);
2199}
2200
2201static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2202 struct kvm_vcpu_events *events)
2203{
dab4b911 2204 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2205 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2206 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2207 return -EINVAL;
2208
2209 vcpu_load(vcpu);
2210
2211 vcpu->arch.exception.pending = events->exception.injected;
2212 vcpu->arch.exception.nr = events->exception.nr;
2213 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2214 vcpu->arch.exception.error_code = events->exception.error_code;
2215
2216 vcpu->arch.interrupt.pending = events->interrupt.injected;
2217 vcpu->arch.interrupt.nr = events->interrupt.nr;
2218 vcpu->arch.interrupt.soft = events->interrupt.soft;
2219 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2220 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2221 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2222 kvm_x86_ops->set_interrupt_shadow(vcpu,
2223 events->interrupt.shadow);
3cfc3092
JK		 2224
2225 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2226 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2227 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2228 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2229
dab4b911
JK		 2230 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2231 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2232
2233 vcpu_put(vcpu);
2234
2235 return 0;
2236}
2237
a1efbe77
JK		 2238static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2239 struct kvm_debugregs *dbgregs)
2240{
2241 vcpu_load(vcpu);
2242
2243 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2244 dbgregs->dr6 = vcpu->arch.dr6;
2245 dbgregs->dr7 = vcpu->arch.dr7;
2246 dbgregs->flags = 0;
2247
2248 vcpu_put(vcpu);
2249}
2250
2251static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2252 struct kvm_debugregs *dbgregs)
2253{
2254 if (dbgregs->flags)
2255 return -EINVAL;
2256
2257 vcpu_load(vcpu);
2258
2259 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2260 vcpu->arch.dr6 = dbgregs->dr6;
2261 vcpu->arch.dr7 = dbgregs->dr7;
2262
2263 vcpu_put(vcpu);
2264
2265 return 0;
2266}
2267
313a3dc7
CO		 2268long kvm_arch_vcpu_ioctl(struct file *filp,
2269 unsigned int ioctl, unsigned long arg)
2270{
2271 struct kvm_vcpu *vcpu = filp->private_data;
2272 void __user *argp = (void __user *)arg;
2273 int r;
b772ff36 2274 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2275
2276 switch (ioctl) {
2277 case KVM_GET_LAPIC: {
2204ae3c
MT		 2278 r = -EINVAL;
2279 if (!vcpu->arch.apic)
2280 goto out;
b772ff36 2281 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2282
b772ff36
DH		 2283 r = -ENOMEM;
2284 if (!lapic)
2285 goto out;
2286 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2287 if (r)
2288 goto out;
2289 r = -EFAULT;
b772ff36 2290 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2291 goto out;
2292 r = 0;
2293 break;
2294 }
2295 case KVM_SET_LAPIC: {
2204ae3c
MT		 2296 r = -EINVAL;
2297 if (!vcpu->arch.apic)
2298 goto out;
b772ff36
DH		 2299 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2300 r = -ENOMEM;
2301 if (!lapic)
2302 goto out;
313a3dc7 2303 r = -EFAULT;
b772ff36 2304 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2305 goto out;
b772ff36 2306 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2307 if (r)
2308 goto out;
2309 r = 0;
2310 break;
2311 }
f77bc6a4
ZX		 2312 case KVM_INTERRUPT: {
2313 struct kvm_interrupt irq;
2314
2315 r = -EFAULT;
2316 if (copy_from_user(&irq, argp, sizeof irq))
2317 goto out;
2318 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2319 if (r)
2320 goto out;
2321 r = 0;
2322 break;
2323 }
c4abb7c9
JK		 2324 case KVM_NMI: {
2325 r = kvm_vcpu_ioctl_nmi(vcpu);
2326 if (r)
2327 goto out;
2328 r = 0;
2329 break;
2330 }
313a3dc7
CO		 2331 case KVM_SET_CPUID: {
2332 struct kvm_cpuid __user *cpuid_arg = argp;
2333 struct kvm_cpuid cpuid;
2334
2335 r = -EFAULT;
2336 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2337 goto out;
2338 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2339 if (r)
2340 goto out;
2341 break;
2342 }
07716717
DK		 2343 case KVM_SET_CPUID2: {
2344 struct kvm_cpuid2 __user *cpuid_arg = argp;
2345 struct kvm_cpuid2 cpuid;
2346
2347 r = -EFAULT;
2348 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2349 goto out;
2350 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2351 cpuid_arg->entries);
07716717
DK		 2352 if (r)
2353 goto out;
2354 break;
2355 }
2356 case KVM_GET_CPUID2: {
2357 struct kvm_cpuid2 __user *cpuid_arg = argp;
2358 struct kvm_cpuid2 cpuid;
2359
2360 r = -EFAULT;
2361 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2362 goto out;
2363 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2364 cpuid_arg->entries);
07716717
DK		 2365 if (r)
2366 goto out;
2367 r = -EFAULT;
2368 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2369 goto out;
2370 r = 0;
2371 break;
2372 }
313a3dc7
CO		 2373 case KVM_GET_MSRS:
2374 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2375 break;
2376 case KVM_SET_MSRS:
2377 r = msr_io(vcpu, argp, do_set_msr, 0);
2378 break;
b209749f
AK		 2379 case KVM_TPR_ACCESS_REPORTING: {
2380 struct kvm_tpr_access_ctl tac;
2381
2382 r = -EFAULT;
2383 if (copy_from_user(&tac, argp, sizeof tac))
2384 goto out;
2385 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2386 if (r)
2387 goto out;
2388 r = -EFAULT;
2389 if (copy_to_user(argp, &tac, sizeof tac))
2390 goto out;
2391 r = 0;
2392 break;
2393 };
b93463aa
AK		 2394 case KVM_SET_VAPIC_ADDR: {
2395 struct kvm_vapic_addr va;
2396
2397 r = -EINVAL;
2398 if (!irqchip_in_kernel(vcpu->kvm))
2399 goto out;
2400 r = -EFAULT;
2401 if (copy_from_user(&va, argp, sizeof va))
2402 goto out;
2403 r = 0;
2404 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2405 break;
2406 }
890ca9ae
HY		 2407 case KVM_X86_SETUP_MCE: {
2408 u64 mcg_cap;
2409
2410 r = -EFAULT;
2411 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2412 goto out;
2413 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2414 break;
2415 }
2416 case KVM_X86_SET_MCE: {
2417 struct kvm_x86_mce mce;
2418
2419 r = -EFAULT;
2420 if (copy_from_user(&mce, argp, sizeof mce))
2421 goto out;
2422 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2423 break;
2424 }
3cfc3092
JK		 2425 case KVM_GET_VCPU_EVENTS: {
2426 struct kvm_vcpu_events events;
2427
2428 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2429
2430 r = -EFAULT;
2431 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2432 break;
2433 r = 0;
2434 break;
2435 }
2436 case KVM_SET_VCPU_EVENTS: {
2437 struct kvm_vcpu_events events;
2438
2439 r = -EFAULT;
2440 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2441 break;
2442
2443 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2444 break;
2445 }
a1efbe77
JK		 2446 case KVM_GET_DEBUGREGS: {
2447 struct kvm_debugregs dbgregs;
2448
2449 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2450
2451 r = -EFAULT;
2452 if (copy_to_user(argp, &dbgregs,
2453 sizeof(struct kvm_debugregs)))
2454 break;
2455 r = 0;
2456 break;
2457 }
2458 case KVM_SET_DEBUGREGS: {
2459 struct kvm_debugregs dbgregs;
2460
2461 r = -EFAULT;
2462 if (copy_from_user(&dbgregs, argp,
2463 sizeof(struct kvm_debugregs)))
2464 break;
2465
2466 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2467 break;
2468 }
313a3dc7
CO		 2469 default:
2470 r = -EINVAL;
2471 }
2472out:
7a6ce84c 2473 kfree(lapic);
313a3dc7
CO		 2474 return r;
2475}
2476
1fe779f8
CO		 2477static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2478{
2479 int ret;
2480
2481 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2482 return -1;
2483 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2484 return ret;
2485}
2486
b927a3ce
SY		 2487static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2488 u64 ident_addr)
2489{
2490 kvm->arch.ept_identity_map_addr = ident_addr;
2491 return 0;
2492}
2493
1fe779f8
CO		 2494static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2495 u32 kvm_nr_mmu_pages)
2496{
2497 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2498 return -EINVAL;
2499
79fac95e 2500 mutex_lock(&kvm->slots_lock);
7c8a83b7 2501 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2502
2503 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2504 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2505
7c8a83b7 2506 spin_unlock(&kvm->mmu_lock);
79fac95e 2507 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2508 return 0;
2509}
2510
2511static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2512{
f05e70ac 2513 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2514}
2515
a983fb23
MT		 2516gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2517{
2518 int i;
2519 struct kvm_mem_alias *alias;
2520 struct kvm_mem_aliases *aliases;
2521
90d83dc3 2522 aliases = kvm_aliases(kvm);
a983fb23
MT		 2523
2524 for (i = 0; i < aliases->naliases; ++i) {
2525 alias = &aliases->aliases[i];
2526 if (alias->flags & KVM_ALIAS_INVALID)
2527 continue;
2528 if (gfn >= alias->base_gfn
2529 && gfn < alias->base_gfn + alias->npages)
2530 return alias->target_gfn + gfn - alias->base_gfn;
2531 }
2532 return gfn;
2533}
2534
e9f85cde
ZX		 2535gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2536{
2537 int i;
2538 struct kvm_mem_alias *alias;
a983fb23
MT		 2539 struct kvm_mem_aliases *aliases;
2540
90d83dc3 2541 aliases = kvm_aliases(kvm);
e9f85cde 2542
fef9cce0
MT		 2543 for (i = 0; i < aliases->naliases; ++i) {
2544 alias = &aliases->aliases[i];
e9f85cde
ZX		 2545 if (gfn >= alias->base_gfn
2546 && gfn < alias->base_gfn + alias->npages)
2547 return alias->target_gfn + gfn - alias->base_gfn;
2548 }
2549 return gfn;
2550}
2551
1fe779f8
CO		 2552/*
2553 * Set a new alias region. Aliases map a portion of physical memory into
2554 * another portion. This is useful for memory windows, for example the PC
2555 * VGA region.
2556 */
2557static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2558 struct kvm_memory_alias *alias)
2559{
2560 int r, n;
2561 struct kvm_mem_alias *p;
a983fb23 2562 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2563
2564 r = -EINVAL;
2565 /* General sanity checks */
2566 if (alias->memory_size & (PAGE_SIZE - 1))
2567 goto out;
2568 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2569 goto out;
2570 if (alias->slot >= KVM_ALIAS_SLOTS)
2571 goto out;
2572 if (alias->guest_phys_addr + alias->memory_size
2573 < alias->guest_phys_addr)
2574 goto out;
2575 if (alias->target_phys_addr + alias->memory_size
2576 < alias->target_phys_addr)
2577 goto out;
2578
a983fb23
MT		 2579 r = -ENOMEM;
2580 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2581 if (!aliases)
2582 goto out;
2583
79fac95e 2584 mutex_lock(&kvm->slots_lock);
1fe779f8 2585
a983fb23
MT		 2586 /* invalidate any gfn reference in case of deletion/shrinking */
2587 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2588 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2589 old_aliases = kvm->arch.aliases;
2590 rcu_assign_pointer(kvm->arch.aliases, aliases);
2591 synchronize_srcu_expedited(&kvm->srcu);
2592 kvm_mmu_zap_all(kvm);
2593 kfree(old_aliases);
2594
2595 r = -ENOMEM;
2596 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2597 if (!aliases)
2598 goto out_unlock;
2599
2600 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2601
2602 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2603 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2604 p->npages = alias->memory_size >> PAGE_SHIFT;
2605 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2606 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2607
2608 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2609 if (aliases->aliases[n - 1].npages)
1fe779f8 2610 break;
fef9cce0 2611 aliases->naliases = n;
1fe779f8 2612
a983fb23
MT		 2613 old_aliases = kvm->arch.aliases;
2614 rcu_assign_pointer(kvm->arch.aliases, aliases);
2615 synchronize_srcu_expedited(&kvm->srcu);
2616 kfree(old_aliases);
2617 r = 0;
1fe779f8 2618
a983fb23 2619out_unlock:
79fac95e 2620 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2621out:
2622 return r;
2623}
2624
2625static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2626{
2627 int r;
2628
2629 r = 0;
2630 switch (chip->chip_id) {
2631 case KVM_IRQCHIP_PIC_MASTER:
2632 memcpy(&chip->chip.pic,
2633 &pic_irqchip(kvm)->pics[0],
2634 sizeof(struct kvm_pic_state));
2635 break;
2636 case KVM_IRQCHIP_PIC_SLAVE:
2637 memcpy(&chip->chip.pic,
2638 &pic_irqchip(kvm)->pics[1],
2639 sizeof(struct kvm_pic_state));
2640 break;
2641 case KVM_IRQCHIP_IOAPIC:
eba0226b 2642 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2643 break;
2644 default:
2645 r = -EINVAL;
2646 break;
2647 }
2648 return r;
2649}
2650
2651static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2652{
2653 int r;
2654
2655 r = 0;
2656 switch (chip->chip_id) {
2657 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2658 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2659 memcpy(&pic_irqchip(kvm)->pics[0],
2660 &chip->chip.pic,
2661 sizeof(struct kvm_pic_state));
fa8273e9 2662 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2663 break;
2664 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2665 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2666 memcpy(&pic_irqchip(kvm)->pics[1],
2667 &chip->chip.pic,
2668 sizeof(struct kvm_pic_state));
fa8273e9 2669 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2670 break;
2671 case KVM_IRQCHIP_IOAPIC:
eba0226b 2672 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2673 break;
2674 default:
2675 r = -EINVAL;
2676 break;
2677 }
2678 kvm_pic_update_irq(pic_irqchip(kvm));
2679 return r;
2680}
2681
e0f63cb9
SY		 2682static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2683{
2684 int r = 0;
2685
894a9c55 2686 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2687 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2688 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2689 return r;
2690}
2691
2692static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2693{
2694 int r = 0;
2695
894a9c55 2696 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2697 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2698 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2699 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2700 return r;
2701}
2702
2703static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2704{
2705 int r = 0;
2706
2707 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2708 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2709 sizeof(ps->channels));
2710 ps->flags = kvm->arch.vpit->pit_state.flags;
2711 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2712 return r;
2713}
2714
2715static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2716{
2717 int r = 0, start = 0;
2718 u32 prev_legacy, cur_legacy;
2719 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2720 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2721 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2722 if (!prev_legacy && cur_legacy)
2723 start = 1;
2724 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2725 sizeof(kvm->arch.vpit->pit_state.channels));
2726 kvm->arch.vpit->pit_state.flags = ps->flags;
2727 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2728 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2729 return r;
2730}
2731
52d939a0
MT		 2732static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2733 struct kvm_reinject_control *control)
2734{
2735 if (!kvm->arch.vpit)
2736 return -ENXIO;
894a9c55 2737 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2738 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2739 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2740 return 0;
2741}
2742
5bb064dc
ZX		 2743/*
2744 * Get (and clear) the dirty memory log for a memory slot.
2745 */
2746int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2747 struct kvm_dirty_log *log)
2748{
87bf6e7d 2749 int r, i;
5bb064dc 2750 struct kvm_memory_slot *memslot;
87bf6e7d 2751 unsigned long n;
b050b015
MT		 2752 unsigned long is_dirty = 0;
2753 unsigned long *dirty_bitmap = NULL;
5bb064dc 2754
79fac95e 2755 mutex_lock(&kvm->slots_lock);
5bb064dc 2756
b050b015
MT		 2757 r = -EINVAL;
2758 if (log->slot >= KVM_MEMORY_SLOTS)
2759 goto out;
2760
2761 memslot = &kvm->memslots->memslots[log->slot];
2762 r = -ENOENT;
2763 if (!memslot->dirty_bitmap)
2764 goto out;
2765
87bf6e7d 2766 n = kvm_dirty_bitmap_bytes(memslot);
b050b015
MT		 2767
2768 r = -ENOMEM;
2769 dirty_bitmap = vmalloc(n);
2770 if (!dirty_bitmap)
5bb064dc 2771 goto out;
b050b015
MT		 2772 memset(dirty_bitmap, 0, n);
2773
2774 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2775 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2776
2777 /* If nothing is dirty, don't bother messing with page tables. */
2778 if (is_dirty) {
b050b015
MT		 2779 struct kvm_memslots *slots, *old_slots;
2780
7c8a83b7 2781 spin_lock(&kvm->mmu_lock);
5bb064dc 2782 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2783 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2784
2785 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2786 if (!slots)
2787 goto out_free;
2788
2789 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2790 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2791
2792 old_slots = kvm->memslots;
2793 rcu_assign_pointer(kvm->memslots, slots);
2794 synchronize_srcu_expedited(&kvm->srcu);
2795 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2796 kfree(old_slots);
5bb064dc 2797 }
b050b015 2798
5bb064dc 2799 r = 0;
b050b015
MT		 2800 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2801 r = -EFAULT;
2802out_free:
2803 vfree(dirty_bitmap);
5bb064dc 2804out:
79fac95e 2805 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2806 return r;
2807}
2808
1fe779f8
CO		 2809long kvm_arch_vm_ioctl(struct file *filp,
2810 unsigned int ioctl, unsigned long arg)
2811{
2812 struct kvm *kvm = filp->private_data;
2813 void __user *argp = (void __user *)arg;
367e1319 2814 int r = -ENOTTY;
f0d66275
DH		 2815 /*
2816 * This union makes it completely explicit to gcc-3.x
2817 * that these two variables' stack usage should be
2818 * combined, not added together.
2819 */
2820 union {
2821 struct kvm_pit_state ps;
e9f42757 2822 struct kvm_pit_state2 ps2;
f0d66275 2823 struct kvm_memory_alias alias;
c5ff41ce 2824 struct kvm_pit_config pit_config;
f0d66275 2825 } u;
1fe779f8
CO		 2826
2827 switch (ioctl) {
2828 case KVM_SET_TSS_ADDR:
2829 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2830 if (r < 0)
2831 goto out;
2832 break;
b927a3ce
SY		 2833 case KVM_SET_IDENTITY_MAP_ADDR: {
2834 u64 ident_addr;
2835
2836 r = -EFAULT;
2837 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2838 goto out;
2839 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2840 if (r < 0)
2841 goto out;
2842 break;
2843 }
1fe779f8
CO		 2844 case KVM_SET_MEMORY_REGION: {
2845 struct kvm_memory_region kvm_mem;
2846 struct kvm_userspace_memory_region kvm_userspace_mem;
2847
2848 r = -EFAULT;
2849 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2850 goto out;
2851 kvm_userspace_mem.slot = kvm_mem.slot;
2852 kvm_userspace_mem.flags = kvm_mem.flags;
2853 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2854 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2855 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2856 if (r)
2857 goto out;
2858 break;
2859 }
2860 case KVM_SET_NR_MMU_PAGES:
2861 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2862 if (r)
2863 goto out;
2864 break;
2865 case KVM_GET_NR_MMU_PAGES:
2866 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2867 break;
f0d66275 2868 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2869 r = -EFAULT;
f0d66275 2870 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2871 goto out;
f0d66275 2872 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2873 if (r)
2874 goto out;
2875 break;
3ddea128
MT		 2876 case KVM_CREATE_IRQCHIP: {
2877 struct kvm_pic *vpic;
2878
2879 mutex_lock(&kvm->lock);
2880 r = -EEXIST;
2881 if (kvm->arch.vpic)
2882 goto create_irqchip_unlock;
1fe779f8 2883 r = -ENOMEM;
3ddea128
MT		 2884 vpic = kvm_create_pic(kvm);
2885 if (vpic) {
1fe779f8
CO		 2886 r = kvm_ioapic_init(kvm);
2887 if (r) {
72bb2fcd
WY		 2888 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2889 &vpic->dev);
3ddea128
MT		 2890 kfree(vpic);
2891 goto create_irqchip_unlock;
1fe779f8
CO		 2892 }
2893 } else
3ddea128
MT		 2894 goto create_irqchip_unlock;
2895 smp_wmb();
2896 kvm->arch.vpic = vpic;
2897 smp_wmb();
399ec807
AK		 2898 r = kvm_setup_default_irq_routing(kvm);
2899 if (r) {
3ddea128 2900 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2901 kvm_ioapic_destroy(kvm);
2902 kvm_destroy_pic(kvm);
3ddea128 2903 mutex_unlock(&kvm->irq_lock);
399ec807 2904 }
3ddea128
MT		 2905 create_irqchip_unlock:
2906 mutex_unlock(&kvm->lock);
1fe779f8 2907 break;
3ddea128 2908 }
7837699f 2909 case KVM_CREATE_PIT:
c5ff41ce
JK		 2910 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2911 goto create_pit;
2912 case KVM_CREATE_PIT2:
2913 r = -EFAULT;
2914 if (copy_from_user(&u.pit_config, argp,
2915 sizeof(struct kvm_pit_config)))
2916 goto out;
2917 create_pit:
79fac95e 2918 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2919 r = -EEXIST;
2920 if (kvm->arch.vpit)
2921 goto create_pit_unlock;
7837699f 2922 r = -ENOMEM;
c5ff41ce 2923 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2924 if (kvm->arch.vpit)
2925 r = 0;
269e05e4 2926 create_pit_unlock:
79fac95e 2927 mutex_unlock(&kvm->slots_lock);
7837699f 2928 break;
4925663a 2929 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2930 case KVM_IRQ_LINE: {
2931 struct kvm_irq_level irq_event;
2932
2933 r = -EFAULT;
2934 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2935 goto out;
160d2f6c 2936 r = -ENXIO;
1fe779f8 2937 if (irqchip_in_kernel(kvm)) {
4925663a 2938 __s32 status;
4925663a
GN		 2939 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2940 irq_event.irq, irq_event.level);
4925663a 2941 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 2942 r = -EFAULT;
4925663a
GN		 2943 irq_event.status = status;
2944 if (copy_to_user(argp, &irq_event,
2945 sizeof irq_event))
2946 goto out;
2947 }
1fe779f8
CO		 2948 r = 0;
2949 }
2950 break;
2951 }
2952 case KVM_GET_IRQCHIP: {
2953 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2954 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2955
f0d66275
DH		 2956 r = -ENOMEM;
2957 if (!chip)
1fe779f8 2958 goto out;
f0d66275
DH		 2959 r = -EFAULT;
2960 if (copy_from_user(chip, argp, sizeof *chip))
2961 goto get_irqchip_out;
1fe779f8
CO		 2962 r = -ENXIO;
2963 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2964 goto get_irqchip_out;
2965 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2966 if (r)
f0d66275 2967 goto get_irqchip_out;
1fe779f8 2968 r = -EFAULT;
f0d66275
DH		 2969 if (copy_to_user(argp, chip, sizeof *chip))
2970 goto get_irqchip_out;
1fe779f8 2971 r = 0;
f0d66275
DH		 2972 get_irqchip_out:
2973 kfree(chip);
2974 if (r)
2975 goto out;
1fe779f8
CO		 2976 break;
2977 }
2978 case KVM_SET_IRQCHIP: {
2979 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2980 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2981
f0d66275
DH		 2982 r = -ENOMEM;
2983 if (!chip)
1fe779f8 2984 goto out;
f0d66275
DH		 2985 r = -EFAULT;
2986 if (copy_from_user(chip, argp, sizeof *chip))
2987 goto set_irqchip_out;
1fe779f8
CO		 2988 r = -ENXIO;
2989 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2990 goto set_irqchip_out;
2991 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2992 if (r)
f0d66275 2993 goto set_irqchip_out;
1fe779f8 2994 r = 0;
f0d66275
DH		 2995 set_irqchip_out:
2996 kfree(chip);
2997 if (r)
2998 goto out;
1fe779f8
CO		 2999 break;
3000 }
e0f63cb9 3001 case KVM_GET_PIT: {
e0f63cb9 3002 r = -EFAULT;
f0d66275 3003 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3004 goto out;
3005 r = -ENXIO;
3006 if (!kvm->arch.vpit)
3007 goto out;
f0d66275 3008 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3009 if (r)
3010 goto out;
3011 r = -EFAULT;
f0d66275 3012 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3013 goto out;
3014 r = 0;
3015 break;
3016 }
3017 case KVM_SET_PIT: {
e0f63cb9 3018 r = -EFAULT;
f0d66275 3019 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3020 goto out;
3021 r = -ENXIO;
3022 if (!kvm->arch.vpit)
3023 goto out;
f0d66275 3024 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3025 if (r)
3026 goto out;
3027 r = 0;
3028 break;
3029 }
e9f42757
BK		 3030 case KVM_GET_PIT2: {
3031 r = -ENXIO;
3032 if (!kvm->arch.vpit)
3033 goto out;
3034 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3035 if (r)
3036 goto out;
3037 r = -EFAULT;
3038 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3039 goto out;
3040 r = 0;
3041 break;
3042 }
3043 case KVM_SET_PIT2: {
3044 r = -EFAULT;
3045 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3046 goto out;
3047 r = -ENXIO;
3048 if (!kvm->arch.vpit)
3049 goto out;
3050 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3051 if (r)
3052 goto out;
3053 r = 0;
3054 break;
3055 }
52d939a0
MT		 3056 case KVM_REINJECT_CONTROL: {
3057 struct kvm_reinject_control control;
3058 r = -EFAULT;
3059 if (copy_from_user(&control, argp, sizeof(control)))
3060 goto out;
3061 r = kvm_vm_ioctl_reinject(kvm, &control);
3062 if (r)
3063 goto out;
3064 r = 0;
3065 break;
3066 }
ffde22ac
ES		 3067 case KVM_XEN_HVM_CONFIG: {
3068 r = -EFAULT;
3069 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3070 sizeof(struct kvm_xen_hvm_config)))
3071 goto out;
3072 r = -EINVAL;
3073 if (kvm->arch.xen_hvm_config.flags)
3074 goto out;
3075 r = 0;
3076 break;
3077 }
afbcf7ab
GC		 3078 case KVM_SET_CLOCK: {
3079 struct timespec now;
3080 struct kvm_clock_data user_ns;
3081 u64 now_ns;
3082 s64 delta;
3083
3084 r = -EFAULT;
3085 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3086 goto out;
3087
3088 r = -EINVAL;
3089 if (user_ns.flags)
3090 goto out;
3091
3092 r = 0;
3093 ktime_get_ts(&now);
3094 now_ns = timespec_to_ns(&now);
3095 delta = user_ns.clock - now_ns;
3096 kvm->arch.kvmclock_offset = delta;
3097 break;
3098 }
3099 case KVM_GET_CLOCK: {
3100 struct timespec now;
3101 struct kvm_clock_data user_ns;
3102 u64 now_ns;
3103
3104 ktime_get_ts(&now);
3105 now_ns = timespec_to_ns(&now);
3106 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3107 user_ns.flags = 0;
3108
3109 r = -EFAULT;
3110 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3111 goto out;
3112 r = 0;
3113 break;
3114 }
3115
1fe779f8
CO		 3116 default:
3117 ;
3118 }
3119out:
3120 return r;
3121}
3122
a16b043c 3123static void kvm_init_msr_list(void)
043405e1
CO		 3124{
3125 u32 dummy[2];
3126 unsigned i, j;
3127
e3267cbb
GC		 3128 /* skip the first msrs in the list. KVM-specific */
3129 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3130 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3131 continue;
3132 if (j < i)
3133 msrs_to_save[j] = msrs_to_save[i];
3134 j++;
3135 }
3136 num_msrs_to_save = j;
3137}
3138
bda9020e
MT		 3139static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3140 const void *v)
bbd9b64e 3141{
bda9020e
MT		 3142 if (vcpu->arch.apic &&
3143 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3144 return 0;
bbd9b64e 3145
e93f8a0f 3146 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3147}
3148
bda9020e 3149static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3150{
bda9020e
MT		 3151 if (vcpu->arch.apic &&
3152 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3153 return 0;
bbd9b64e 3154
e93f8a0f 3155 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3156}
3157
2dafc6c2
GN		 3158static void kvm_set_segment(struct kvm_vcpu *vcpu,
3159 struct kvm_segment *var, int seg)
3160{
3161 kvm_x86_ops->set_segment(vcpu, var, seg);
3162}
3163
3164void kvm_get_segment(struct kvm_vcpu *vcpu,
3165 struct kvm_segment *var, int seg)
3166{
3167 kvm_x86_ops->get_segment(vcpu, var, seg);
3168}
3169
1871c602
GN		 3170gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3171{
3172 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3173 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3174}
3175
3176 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3177{
3178 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3179 access |= PFERR_FETCH_MASK;
3180 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3181}
3182
3183gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3184{
3185 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3186 access |= PFERR_WRITE_MASK;
3187 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3188}
3189
3190/* uses this to access any guest's mapped memory without checking CPL */
3191gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3192{
3193 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3194}
3195
3196static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3197 struct kvm_vcpu *vcpu, u32 access,
3198 u32 *error)
bbd9b64e
CO		 3199{
3200 void *data = val;
10589a46 3201 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3202
3203 while (bytes) {
1871c602 3204 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3205 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3206 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3207 int ret;
3208
10589a46
MT		 3209 if (gpa == UNMAPPED_GVA) {
3210 r = X86EMUL_PROPAGATE_FAULT;
3211 goto out;
3212 }
77c2002e 3213 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3214 if (ret < 0) {
3215 r = X86EMUL_UNHANDLEABLE;
3216 goto out;
3217 }
bbd9b64e 3218
77c2002e
IE		 3219 bytes -= toread;
3220 data += toread;
3221 addr += toread;
bbd9b64e 3222 }
10589a46 3223out:
10589a46 3224 return r;
bbd9b64e 3225}
77c2002e 3226
1871c602
GN		 3227/* used for instruction fetching */
3228static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3229 struct kvm_vcpu *vcpu, u32 *error)
3230{
3231 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3232 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3233 access | PFERR_FETCH_MASK, error);
3234}
3235
3236static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3237 struct kvm_vcpu *vcpu, u32 *error)
3238{
3239 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3240 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3241 error);
3242}
3243
3244static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3245 struct kvm_vcpu *vcpu, u32 *error)
3246{
3247 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3248}
3249
7972995b 3250static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3251 unsigned int bytes,
7972995b 3252 struct kvm_vcpu *vcpu,
2dafc6c2 3253 u32 *error)
77c2002e
IE		 3254{
3255 void *data = val;
3256 int r = X86EMUL_CONTINUE;
3257
3258 while (bytes) {
7972995b
GN		 3259 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3260 PFERR_WRITE_MASK, error);
77c2002e
IE		 3261 unsigned offset = addr & (PAGE_SIZE-1);
3262 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3263 int ret;
3264
3265 if (gpa == UNMAPPED_GVA) {
3266 r = X86EMUL_PROPAGATE_FAULT;
3267 goto out;
3268 }
3269 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3270 if (ret < 0) {
3271 r = X86EMUL_UNHANDLEABLE;
3272 goto out;
3273 }
3274
3275 bytes -= towrite;
3276 data += towrite;
3277 addr += towrite;
3278 }
3279out:
3280 return r;
3281}
3282
bbd9b64e
CO		 3283static int emulator_read_emulated(unsigned long addr,
3284 void *val,
3285 unsigned int bytes,
3286 struct kvm_vcpu *vcpu)
3287{
bbd9b64e 3288 gpa_t gpa;
1871c602 3289 u32 error_code;
bbd9b64e
CO		 3290
3291 if (vcpu->mmio_read_completed) {
3292 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3293 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3294 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3295 vcpu->mmio_read_completed = 0;
3296 return X86EMUL_CONTINUE;
3297 }
3298
1871c602
GN		 3299 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3300
3301 if (gpa == UNMAPPED_GVA) {
3302 kvm_inject_page_fault(vcpu, addr, error_code);
3303 return X86EMUL_PROPAGATE_FAULT;
3304 }
bbd9b64e
CO		 3305
3306 /* For APIC access vmexit */
3307 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3308 goto mmio;
3309
1871c602 3310 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3311 == X86EMUL_CONTINUE)
bbd9b64e 3312 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3313
3314mmio:
3315 /*
3316 * Is this MMIO handled locally?
3317 */
aec51dc4
AK		 3318 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3319 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3320 return X86EMUL_CONTINUE;
3321 }
aec51dc4
AK		 3322
3323 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3324
3325 vcpu->mmio_needed = 1;
3326 vcpu->mmio_phys_addr = gpa;
3327 vcpu->mmio_size = bytes;
3328 vcpu->mmio_is_write = 0;
3329
3330 return X86EMUL_UNHANDLEABLE;
3331}
3332
3200f405 3333int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3334 const void *val, int bytes)
bbd9b64e
CO		 3335{
3336 int ret;
3337
3338 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3339 if (ret < 0)
bbd9b64e 3340 return 0;
ad218f85 3341 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3342 return 1;
3343}
3344
3345static int emulator_write_emulated_onepage(unsigned long addr,
3346 const void *val,
3347 unsigned int bytes,
8f6abd06 3348 struct kvm_vcpu *vcpu)
bbd9b64e 3349{
10589a46 3350 gpa_t gpa;
1871c602 3351 u32 error_code;
10589a46 3352
1871c602 3353 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3354
3355 if (gpa == UNMAPPED_GVA) {
1871c602 3356 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3357 return X86EMUL_PROPAGATE_FAULT;
3358 }
3359
3360 /* For APIC access vmexit */
3361 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3362 goto mmio;
3363
3364 if (emulator_write_phys(vcpu, gpa, val, bytes))
3365 return X86EMUL_CONTINUE;
3366
3367mmio:
aec51dc4 3368 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3369 /*
3370 * Is this MMIO handled locally?
3371 */
bda9020e 3372 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3373 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3374
3375 vcpu->mmio_needed = 1;
3376 vcpu->mmio_phys_addr = gpa;
3377 vcpu->mmio_size = bytes;
3378 vcpu->mmio_is_write = 1;
3379 memcpy(vcpu->mmio_data, val, bytes);
3380
3381 return X86EMUL_CONTINUE;
3382}
3383
8f6abd06
GN		 3384int emulator_write_emulated(unsigned long addr,
3385 const void *val,
3386 unsigned int bytes,
3387 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3388{
3389 /* Crossing a page boundary? */
3390 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3391 int rc, now;
3392
3393 now = -addr & ~PAGE_MASK;
8f6abd06 3394 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
bbd9b64e
CO		 3395 if (rc != X86EMUL_CONTINUE)
3396 return rc;
3397 addr += now;
3398 val += now;
3399 bytes -= now;
3400 }
8f6abd06 3401 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
bbd9b64e
CO		 3402}
3403EXPORT_SYMBOL_GPL(emulator_write_emulated);
3404
daea3e73
AK		 3405#define CMPXCHG_TYPE(t, ptr, old, new) \
3406 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3407
3408#ifdef CONFIG_X86_64
3409# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3410#else
3411# define CMPXCHG64(ptr, old, new) \
9749a6c0 3412 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3413#endif
3414
bbd9b64e
CO		 3415static int emulator_cmpxchg_emulated(unsigned long addr,
3416 const void *old,
3417 const void *new,
3418 unsigned int bytes,
3419 struct kvm_vcpu *vcpu)
3420{
daea3e73
AK		 3421 gpa_t gpa;
3422 struct page *page;
3423 char *kaddr;
3424 bool exchanged;
2bacc55c 3425
daea3e73
AK		 3426 /* guests cmpxchg8b have to be emulated atomically */
3427 if (bytes > 8 || (bytes & (bytes - 1)))
3428 goto emul_write;
10589a46 3429
daea3e73 3430 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3431
daea3e73
AK		 3432 if (gpa == UNMAPPED_GVA ||
3433 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3434 goto emul_write;
2bacc55c 3435
daea3e73
AK		 3436 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3437 goto emul_write;
72dc67a6 3438
daea3e73 3439 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3440
daea3e73
AK		 3441 kaddr = kmap_atomic(page, KM_USER0);
3442 kaddr += offset_in_page(gpa);
3443 switch (bytes) {
3444 case 1:
3445 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3446 break;
3447 case 2:
3448 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3449 break;
3450 case 4:
3451 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3452 break;
3453 case 8:
3454 exchanged = CMPXCHG64(kaddr, old, new);
3455 break;
3456 default:
3457 BUG();
2bacc55c 3458 }
daea3e73
AK		 3459 kunmap_atomic(kaddr, KM_USER0);
3460 kvm_release_page_dirty(page);
3461
3462 if (!exchanged)
3463 return X86EMUL_CMPXCHG_FAILED;
3464
8f6abd06
GN		 3465 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3466
3467 return X86EMUL_CONTINUE;
4a5f48f6 3468
3200f405 3469emul_write:
daea3e73 3470 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3471
bbd9b64e
CO		 3472 return emulator_write_emulated(addr, new, bytes, vcpu);
3473}
3474
cf8f70bf
GN		 3475static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3476{
3477 /* TODO: String I/O for in kernel device */
3478 int r;
3479
3480 if (vcpu->arch.pio.in)
3481 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3482 vcpu->arch.pio.size, pd);
3483 else
3484 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3485 vcpu->arch.pio.port, vcpu->arch.pio.size,
3486 pd);
3487 return r;
3488}
3489
3490
3491static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3492 unsigned int count, struct kvm_vcpu *vcpu)
3493{
7972995b 3494 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3495 goto data_avail;
3496
3497 trace_kvm_pio(1, port, size, 1);
3498
3499 vcpu->arch.pio.port = port;
3500 vcpu->arch.pio.in = 1;
7972995b 3501 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3502 vcpu->arch.pio.size = size;
3503
3504 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3505 data_avail:
3506 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3507 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3508 return 1;
3509 }
3510
3511 vcpu->run->exit_reason = KVM_EXIT_IO;
3512 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3513 vcpu->run->io.size = size;
3514 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3515 vcpu->run->io.count = count;
3516 vcpu->run->io.port = port;
3517
3518 return 0;
3519}
3520
3521static int emulator_pio_out_emulated(int size, unsigned short port,
3522 const void *val, unsigned int count,
3523 struct kvm_vcpu *vcpu)
3524{
3525 trace_kvm_pio(0, port, size, 1);
3526
3527 vcpu->arch.pio.port = port;
3528 vcpu->arch.pio.in = 0;
7972995b 3529 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3530 vcpu->arch.pio.size = size;
3531
3532 memcpy(vcpu->arch.pio_data, val, size * count);
3533
3534 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3535 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3536 return 1;
3537 }
3538
3539 vcpu->run->exit_reason = KVM_EXIT_IO;
3540 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3541 vcpu->run->io.size = size;
3542 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3543 vcpu->run->io.count = count;
3544 vcpu->run->io.port = port;
3545
3546 return 0;
3547}
3548
bbd9b64e
CO		 3549static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3550{
3551 return kvm_x86_ops->get_segment_base(vcpu, seg);
3552}
3553
3554int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3555{
a7052897 3556 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3557 return X86EMUL_CONTINUE;
3558}
3559
3560int emulate_clts(struct kvm_vcpu *vcpu)
3561{
4d4ec087 3562 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3563 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3564 return X86EMUL_CONTINUE;
3565}
3566
3567int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3568{
020df079 3569 return kvm_get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3570}
3571
3572int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3573{
3574 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3575
020df079 3576 return kvm_set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3577}
3578
3579void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3580{
bbd9b64e 3581 u8 opcodes[4];
5fdbf976 3582 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3583 unsigned long rip_linear;
3584
f76c710d 3585 if (!printk_ratelimit())
bbd9b64e
CO		 3586 return;
3587
25be4608
GC		 3588 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3589
1871c602 3590 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3591
3592 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3593 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3594}
3595EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3596
52a46617
GN		 3597static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3598{
3599 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3600}
3601
3602static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
3603{
3604 unsigned long value;
3605
3606 switch (cr) {
3607 case 0:
3608 value = kvm_read_cr0(vcpu);
3609 break;
3610 case 2:
3611 value = vcpu->arch.cr2;
3612 break;
3613 case 3:
3614 value = vcpu->arch.cr3;
3615 break;
3616 case 4:
3617 value = kvm_read_cr4(vcpu);
3618 break;
3619 case 8:
3620 value = kvm_get_cr8(vcpu);
3621 break;
3622 default:
3623 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3624 return 0;
3625 }
3626
3627 return value;
3628}
3629
3630static void emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
3631{
3632 switch (cr) {
3633 case 0:
3634 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
3635 break;
3636 case 2:
3637 vcpu->arch.cr2 = val;
3638 break;
3639 case 3:
3640 kvm_set_cr3(vcpu, val);
3641 break;
3642 case 4:
3643 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
3644 break;
3645 case 8:
3646 kvm_set_cr8(vcpu, val & 0xfUL);
3647 break;
3648 default:
3649 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3650 }
3651}
3652
9c537244
GN		 3653static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3654{
3655 return kvm_x86_ops->get_cpl(vcpu);
3656}
3657
2dafc6c2
GN		 3658static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3659{
3660 kvm_x86_ops->get_gdt(vcpu, dt);
3661}
3662
3663static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3664 struct kvm_vcpu *vcpu)
3665{
3666 struct kvm_segment var;
3667
3668 kvm_get_segment(vcpu, &var, seg);
3669
3670 if (var.unusable)
3671 return false;
3672
3673 if (var.g)
3674 var.limit >>= 12;
3675 set_desc_limit(desc, var.limit);
3676 set_desc_base(desc, (unsigned long)var.base);
3677 desc->type = var.type;
3678 desc->s = var.s;
3679 desc->dpl = var.dpl;
3680 desc->p = var.present;
3681 desc->avl = var.avl;
3682 desc->l = var.l;
3683 desc->d = var.db;
3684 desc->g = var.g;
3685
3686 return true;
3687}
3688
3689static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3690 struct kvm_vcpu *vcpu)
3691{
3692 struct kvm_segment var;
3693
3694 /* needed to preserve selector */
3695 kvm_get_segment(vcpu, &var, seg);
3696
3697 var.base = get_desc_base(desc);
3698 var.limit = get_desc_limit(desc);
3699 if (desc->g)
3700 var.limit = (var.limit << 12) | 0xfff;
3701 var.type = desc->type;
3702 var.present = desc->p;
3703 var.dpl = desc->dpl;
3704 var.db = desc->d;
3705 var.s = desc->s;
3706 var.l = desc->l;
3707 var.g = desc->g;
3708 var.avl = desc->avl;
3709 var.present = desc->p;
3710 var.unusable = !var.present;
3711 var.padding = 0;
3712
3713 kvm_set_segment(vcpu, &var, seg);
3714 return;
3715}
3716
3717static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3718{
3719 struct kvm_segment kvm_seg;
3720
3721 kvm_get_segment(vcpu, &kvm_seg, seg);
3722 return kvm_seg.selector;
3723}
3724
3725static void emulator_set_segment_selector(u16 sel, int seg,
3726 struct kvm_vcpu *vcpu)
3727{
3728 struct kvm_segment kvm_seg;
3729
3730 kvm_get_segment(vcpu, &kvm_seg, seg);
3731 kvm_seg.selector = sel;
3732 kvm_set_segment(vcpu, &kvm_seg, seg);
3733}
3734
482ac18a
GN		 3735static void emulator_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
3736{
3737 kvm_x86_ops->set_rflags(vcpu, rflags);
3738}
3739
14af3f3c 3740static struct x86_emulate_ops emulate_ops = {
1871c602 3741 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3742 .write_std = kvm_write_guest_virt_system,
1871c602 3743 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3744 .read_emulated = emulator_read_emulated,
3745 .write_emulated = emulator_write_emulated,
3746 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3747 .pio_in_emulated = emulator_pio_in_emulated,
3748 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3749 .get_cached_descriptor = emulator_get_cached_descriptor,
3750 .set_cached_descriptor = emulator_set_cached_descriptor,
3751 .get_segment_selector = emulator_get_segment_selector,
3752 .set_segment_selector = emulator_set_segment_selector,
3753 .get_gdt = emulator_get_gdt,
52a46617
GN		 3754 .get_cr = emulator_get_cr,
3755 .set_cr = emulator_set_cr,
9c537244 3756 .cpl = emulator_get_cpl,
482ac18a 3757 .set_rflags = emulator_set_rflags,
bbd9b64e
CO		 3758};
3759
5fdbf976
MT		 3760static void cache_all_regs(struct kvm_vcpu *vcpu)
3761{
3762 kvm_register_read(vcpu, VCPU_REGS_RAX);
3763 kvm_register_read(vcpu, VCPU_REGS_RSP);
3764 kvm_register_read(vcpu, VCPU_REGS_RIP);
3765 vcpu->arch.regs_dirty = ~0;
3766}
3767
bbd9b64e 3768int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3769 unsigned long cr2,
3770 u16 error_code,
571008da 3771 int emulation_type)
bbd9b64e 3772{
310b5d30 3773 int r, shadow_mask;
571008da 3774 struct decode_cache *c;
851ba692 3775 struct kvm_run *run = vcpu->run;
bbd9b64e 3776
26eef70c 3777 kvm_clear_exception_queue(vcpu);
ad312c7c 3778 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3779 /*
56e82318 3780 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3781 * instead of direct ->regs accesses, can save hundred cycles
3782 * on Intel for instructions that don't read/change RSP, for
3783 * for example.
3784 */
3785 cache_all_regs(vcpu);
bbd9b64e
CO		 3786
3787 vcpu->mmio_is_write = 0;
bbd9b64e 3788
571008da 3789 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3790 int cs_db, cs_l;
3791 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3792
ad312c7c 3793 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3794 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3795 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3796 vcpu->arch.emulate_ctxt.mode =
a0044755 3797 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3798 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3799 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3800 ? X86EMUL_MODE_PROT64 : cs_db
3801 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3802
ad312c7c 3803 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3804 trace_kvm_emulate_insn_start(vcpu);
571008da 3805
0cb5762e
AP		 3806 /* Only allow emulation of specific instructions on #UD
3807 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3808 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3809 if (emulation_type & EMULTYPE_TRAP_UD) {
3810 if (!c->twobyte)
3811 return EMULATE_FAIL;
3812 switch (c->b) {
3813 case 0x01: /* VMMCALL */
3814 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3815 return EMULATE_FAIL;
3816 break;
3817 case 0x34: /* sysenter */
3818 case 0x35: /* sysexit */
3819 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3820 return EMULATE_FAIL;
3821 break;
3822 case 0x05: /* syscall */
3823 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3824 return EMULATE_FAIL;
3825 break;
3826 default:
3827 return EMULATE_FAIL;
3828 }
3829
3830 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3831 return EMULATE_FAIL;
3832 }
571008da 3833
f2b5756b 3834 ++vcpu->stat.insn_emulation;
bbd9b64e 3835 if (r) {
f2b5756b 3836 ++vcpu->stat.insn_emulation_fail;
e46479f8 3837 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3838 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3839 return EMULATE_DONE;
3840 return EMULATE_FAIL;
3841 }
3842 }
3843
ba8afb6b
GN		 3844 if (emulation_type & EMULTYPE_SKIP) {
3845 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3846 return EMULATE_DONE;
3847 }
3848
5cd21917 3849restart:
ad312c7c 3850 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3851 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3852
3853 if (r == 0)
3854 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3855
7972995b 3856 if (vcpu->arch.pio.count) {
cf8f70bf 3857 if (!vcpu->arch.pio.in)
7972995b 3858 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3859 return EMULATE_DO_MMIO;
3860 }
3861
112592da 3862 if (r || vcpu->mmio_is_write) {
bbd9b64e
CO		 3863 run->exit_reason = KVM_EXIT_MMIO;
3864 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3865 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3866 run->mmio.len = vcpu->mmio_size;
3867 run->mmio.is_write = vcpu->mmio_is_write;
3868 }
3869
3870 if (r) {
3871 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
5cd21917 3872 goto done;
bbd9b64e 3873 if (!vcpu->mmio_needed) {
e46479f8
AK		 3874 ++vcpu->stat.insn_emulation_fail;
3875 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3876 kvm_report_emulation_failure(vcpu, "mmio");
3877 return EMULATE_FAIL;
3878 }
3879 return EMULATE_DO_MMIO;
3880 }
3881
bbd9b64e
CO		 3882 if (vcpu->mmio_is_write) {
3883 vcpu->mmio_needed = 0;
3884 return EMULATE_DO_MMIO;
3885 }
3886
5cd21917
GN		 3887done:
3888 if (vcpu->arch.exception.pending)
3889 vcpu->arch.emulate_ctxt.restart = false;
3890
3891 if (vcpu->arch.emulate_ctxt.restart)
3892 goto restart;
3893
bbd9b64e
CO		 3894 return EMULATE_DONE;
3895}
3896EXPORT_SYMBOL_GPL(emulate_instruction);
3897
cf8f70bf
GN		 3898int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
3899{
3900 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3901 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
3902 /* do not return to emulator after return from userspace */
7972995b 3903 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3904 return ret;
3905}
3906EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
3907
c8076604
GH		 3908static void bounce_off(void *info)
3909{
3910 /* nothing */
3911}
3912
c8076604
GH		 3913static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3914 void *data)
3915{
3916 struct cpufreq_freqs *freq = data;
3917 struct kvm *kvm;
3918 struct kvm_vcpu *vcpu;
3919 int i, send_ipi = 0;
3920
c8076604
GH		 3921 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3922 return 0;
3923 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3924 return 0;
0cca7907 3925 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3926
3927 spin_lock(&kvm_lock);
3928 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3929 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3930 if (vcpu->cpu != freq->cpu)
3931 continue;
3932 if (!kvm_request_guest_time_update(vcpu))
3933 continue;
3934 if (vcpu->cpu != smp_processor_id())
3935 send_ipi++;
3936 }
3937 }
3938 spin_unlock(&kvm_lock);
3939
3940 if (freq->old < freq->new && send_ipi) {
3941 /*
3942 * We upscale the frequency. Must make the guest
3943 * doesn't see old kvmclock values while running with
3944 * the new frequency, otherwise we risk the guest sees
3945 * time go backwards.
3946 *
3947 * In case we update the frequency for another cpu
3948 * (which might be in guest context) send an interrupt
3949 * to kick the cpu out of guest context. Next time
3950 * guest context is entered kvmclock will be updated,
3951 * so the guest will not see stale values.
3952 */
3953 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3954 }
3955 return 0;
3956}
3957
3958static struct notifier_block kvmclock_cpufreq_notifier_block = {
3959 .notifier_call = kvmclock_cpufreq_notifier
3960};
3961
b820cc0c
ZA		 3962static void kvm_timer_init(void)
3963{
3964 int cpu;
3965
b820cc0c 3966 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3967 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3968 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3969 for_each_online_cpu(cpu) {
3970 unsigned long khz = cpufreq_get(cpu);
3971 if (!khz)
3972 khz = tsc_khz;
3973 per_cpu(cpu_tsc_khz, cpu) = khz;
3974 }
0cca7907
ZA		 3975 } else {
3976 for_each_possible_cpu(cpu)
3977 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3978 }
3979}
3980
ff9d07a0
ZY		 3981static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
3982
3983static int kvm_is_in_guest(void)
3984{
3985 return percpu_read(current_vcpu) != NULL;
3986}
3987
3988static int kvm_is_user_mode(void)
3989{
3990 int user_mode = 3;
dcf46b94 3991
ff9d07a0
ZY		 3992 if (percpu_read(current_vcpu))
3993 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 3994
ff9d07a0
ZY		 3995 return user_mode != 0;
3996}
3997
3998static unsigned long kvm_get_guest_ip(void)
3999{
4000 unsigned long ip = 0;
dcf46b94 4001
ff9d07a0
ZY		 4002 if (percpu_read(current_vcpu))
4003 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4004
ff9d07a0
ZY		 4005 return ip;
4006}
4007
4008static struct perf_guest_info_callbacks kvm_guest_cbs = {
4009 .is_in_guest = kvm_is_in_guest,
4010 .is_user_mode = kvm_is_user_mode,
4011 .get_guest_ip = kvm_get_guest_ip,
4012};
4013
4014void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4015{
4016 percpu_write(current_vcpu, vcpu);
4017}
4018EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4019
4020void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4021{
4022 percpu_write(current_vcpu, NULL);
4023}
4024EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4025
f8c16bba 4026int kvm_arch_init(void *opaque)
043405e1 4027{
b820cc0c 4028 int r;
f8c16bba
ZX		 4029 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4030
f8c16bba
ZX		 4031 if (kvm_x86_ops) {
4032 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4033 r = -EEXIST;
4034 goto out;
f8c16bba
ZX		 4035 }
4036
4037 if (!ops->cpu_has_kvm_support()) {
4038 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4039 r = -EOPNOTSUPP;
4040 goto out;
f8c16bba
ZX		 4041 }
4042 if (ops->disabled_by_bios()) {
4043 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4044 r = -EOPNOTSUPP;
4045 goto out;
f8c16bba
ZX		 4046 }
4047
97db56ce
AK		 4048 r = kvm_mmu_module_init();
4049 if (r)
4050 goto out;
4051
4052 kvm_init_msr_list();
4053
f8c16bba 4054 kvm_x86_ops = ops;
56c6d28a 4055 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4056 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4057 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4058 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4059
b820cc0c 4060 kvm_timer_init();
c8076604 4061
ff9d07a0
ZY		 4062 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4063
f8c16bba 4064 return 0;
56c6d28a
ZX		 4065
4066out:
56c6d28a 4067 return r;
043405e1 4068}
8776e519 4069
f8c16bba
ZX		 4070void kvm_arch_exit(void)
4071{
ff9d07a0
ZY		 4072 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4073
888d256e
JK		 4074 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4075 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4076 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4077 kvm_x86_ops = NULL;
56c6d28a
ZX		 4078 kvm_mmu_module_exit();
4079}
f8c16bba 4080
8776e519
HB		 4081int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4082{
4083 ++vcpu->stat.halt_exits;
4084 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4085 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4086 return 1;
4087 } else {
4088 vcpu->run->exit_reason = KVM_EXIT_HLT;
4089 return 0;
4090 }
4091}
4092EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4093
2f333bcb
MT		 4094static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4095 unsigned long a1)
4096{
4097 if (is_long_mode(vcpu))
4098 return a0;
4099 else
4100 return a0 | ((gpa_t)a1 << 32);
4101}
4102
55cd8e5a
GN		 4103int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4104{
4105 u64 param, ingpa, outgpa, ret;
4106 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4107 bool fast, longmode;
4108 int cs_db, cs_l;
4109
4110 /*
4111 * hypercall generates UD from non zero cpl and real mode
4112 * per HYPER-V spec
4113 */
3eeb3288 4114 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4115 kvm_queue_exception(vcpu, UD_VECTOR);
4116 return 0;
4117 }
4118
4119 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4120 longmode = is_long_mode(vcpu) && cs_l == 1;
4121
4122 if (!longmode) {
ccd46936
GN		 4123 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4124 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4125 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4126 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4127 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4128 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4129 }
4130#ifdef CONFIG_X86_64
4131 else {
4132 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4133 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4134 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4135 }
4136#endif
4137
4138 code = param & 0xffff;
4139 fast = (param >> 16) & 0x1;
4140 rep_cnt = (param >> 32) & 0xfff;
4141 rep_idx = (param >> 48) & 0xfff;
4142
4143 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4144
c25bc163
GN		 4145 switch (code) {
4146 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4147 kvm_vcpu_on_spin(vcpu);
4148 break;
4149 default:
4150 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4151 break;
4152 }
55cd8e5a
GN		 4153
4154 ret = res | (((u64)rep_done & 0xfff) << 32);
4155 if (longmode) {
4156 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4157 } else {
4158 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4159 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4160 }
4161
4162 return 1;
4163}
4164
8776e519
HB		 4165int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4166{
4167 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4168 int r = 1;
8776e519 4169
55cd8e5a
GN		 4170 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4171 return kvm_hv_hypercall(vcpu);
4172
5fdbf976
MT		 4173 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4174 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4175 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4176 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4177 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4178
229456fc 4179 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4180
8776e519
HB		 4181 if (!is_long_mode(vcpu)) {
4182 nr &= 0xFFFFFFFF;
4183 a0 &= 0xFFFFFFFF;
4184 a1 &= 0xFFFFFFFF;
4185 a2 &= 0xFFFFFFFF;
4186 a3 &= 0xFFFFFFFF;
4187 }
4188
07708c4a
JK		 4189 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4190 ret = -KVM_EPERM;
4191 goto out;
4192 }
4193
8776e519 4194 switch (nr) {
b93463aa
AK		 4195 case KVM_HC_VAPIC_POLL_IRQ:
4196 ret = 0;
4197 break;
2f333bcb
MT		 4198 case KVM_HC_MMU_OP:
4199 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4200 break;
8776e519
HB		 4201 default:
4202 ret = -KVM_ENOSYS;
4203 break;
4204 }
07708c4a 4205out:
5fdbf976 4206 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4207 ++vcpu->stat.hypercalls;
2f333bcb 4208 return r;
8776e519
HB		 4209}
4210EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4211
4212int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4213{
4214 char instruction[3];
5fdbf976 4215 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4216
8776e519
HB		 4217 /*
4218 * Blow out the MMU to ensure that no other VCPU has an active mapping
4219 * to ensure that the updated hypercall appears atomically across all
4220 * VCPUs.
4221 */
4222 kvm_mmu_zap_all(vcpu->kvm);
4223
8776e519 4224 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4225
8f6abd06 4226 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 4227}
4228
8776e519
HB		 4229void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4230{
89a27f4d 4231 struct desc_ptr dt = { limit, base };
8776e519
HB		 4232
4233 kvm_x86_ops->set_gdt(vcpu, &dt);
4234}
4235
4236void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4237{
89a27f4d 4238 struct desc_ptr dt = { limit, base };
8776e519
HB		 4239
4240 kvm_x86_ops->set_idt(vcpu, &dt);
4241}
4242
07716717
DK		 4243static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4244{
ad312c7c
ZX		 4245 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4246 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4247
4248 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4249 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4250 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4251 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4252 if (ej->function == e->function) {
4253 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4254 return j;
4255 }
4256 }
4257 return 0; /* silence gcc, even though control never reaches here */
4258}
4259
4260/* find an entry with matching function, matching index (if needed), and that
4261 * should be read next (if it's stateful) */
4262static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4263 u32 function, u32 index)
4264{
4265 if (e->function != function)
4266 return 0;
4267 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4268 return 0;
4269 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4270 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4271 return 0;
4272 return 1;
4273}
4274
d8017474
AG		 4275struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4276 u32 function, u32 index)
8776e519
HB		 4277{
4278 int i;
d8017474 4279 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4280
ad312c7c 4281 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4282 struct kvm_cpuid_entry2 *e;
4283
ad312c7c 4284 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4285 if (is_matching_cpuid_entry(e, function, index)) {
4286 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4287 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4288 best = e;
4289 break;
4290 }
4291 /*
4292 * Both basic or both extended?
4293 */
4294 if (((e->function ^ function) & 0x80000000) == 0)
4295 if (!best || e->function > best->function)
4296 best = e;
4297 }
d8017474
AG		 4298 return best;
4299}
0e851880 4300EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4301
82725b20
DE		 4302int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4303{
4304 struct kvm_cpuid_entry2 *best;
4305
f7a71197
AK		 4306 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4307 if (!best || best->eax < 0x80000008)
4308 goto not_found;
82725b20
DE		 4309 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4310 if (best)
4311 return best->eax & 0xff;
f7a71197 4312not_found:
82725b20
DE		 4313 return 36;
4314}
4315
d8017474
AG		 4316void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4317{
4318 u32 function, index;
4319 struct kvm_cpuid_entry2 *best;
4320
4321 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4322 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4323 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4324 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4325 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4326 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4327 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4328 if (best) {
5fdbf976
MT		 4329 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4330 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4331 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4332 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4333 }
8776e519 4334 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4335 trace_kvm_cpuid(function,
4336 kvm_register_read(vcpu, VCPU_REGS_RAX),
4337 kvm_register_read(vcpu, VCPU_REGS_RBX),
4338 kvm_register_read(vcpu, VCPU_REGS_RCX),
4339 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4340}
4341EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4342
b6c7a5dc
HB		 4343/*
4344 * Check if userspace requested an interrupt window, and that the
4345 * interrupt window is open.
4346 *
4347 * No need to exit to userspace if we already have an interrupt queued.
4348 */
851ba692 4349static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4350{
8061823a 4351 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4352 vcpu->run->request_interrupt_window &&
5df56646 4353 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4354}
4355
851ba692 4356static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4357{
851ba692
AK		 4358 struct kvm_run *kvm_run = vcpu->run;
4359
91586a3b 4360 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4361 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4362 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4363 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4364 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4365 else
b6c7a5dc 4366 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4367 kvm_arch_interrupt_allowed(vcpu) &&
4368 !kvm_cpu_has_interrupt(vcpu) &&
4369 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4370}
4371
b93463aa
AK		 4372static void vapic_enter(struct kvm_vcpu *vcpu)
4373{
4374 struct kvm_lapic *apic = vcpu->arch.apic;
4375 struct page *page;
4376
4377 if (!apic || !apic->vapic_addr)
4378 return;
4379
4380 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4381
4382 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4383}
4384
4385static void vapic_exit(struct kvm_vcpu *vcpu)
4386{
4387 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4388 int idx;
b93463aa
AK		 4389
4390 if (!apic || !apic->vapic_addr)
4391 return;
4392
f656ce01 4393 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4394 kvm_release_page_dirty(apic->vapic_page);
4395 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4396 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4397}
4398
95ba8273
GN		 4399static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4400{
4401 int max_irr, tpr;
4402
4403 if (!kvm_x86_ops->update_cr8_intercept)
4404 return;
4405
88c808fd
AK		 4406 if (!vcpu->arch.apic)
4407 return;
4408
8db3baa2
GN		 4409 if (!vcpu->arch.apic->vapic_addr)
4410 max_irr = kvm_lapic_find_highest_irr(vcpu);
4411 else
4412 max_irr = -1;
95ba8273
GN		 4413
4414 if (max_irr != -1)
4415 max_irr >>= 4;
4416
4417 tpr = kvm_lapic_get_cr8(vcpu);
4418
4419 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4420}
4421
851ba692 4422static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4423{
4424 /* try to reinject previous events if any */
b59bb7bd 4425 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4426 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4427 vcpu->arch.exception.has_error_code,
4428 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4429 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4430 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4431 vcpu->arch.exception.error_code,
4432 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4433 return;
4434 }
4435
95ba8273
GN		 4436 if (vcpu->arch.nmi_injected) {
4437 kvm_x86_ops->set_nmi(vcpu);
4438 return;
4439 }
4440
4441 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4442 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4443 return;
4444 }
4445
4446 /* try to inject new event if pending */
4447 if (vcpu->arch.nmi_pending) {
4448 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4449 vcpu->arch.nmi_pending = false;
4450 vcpu->arch.nmi_injected = true;
4451 kvm_x86_ops->set_nmi(vcpu);
4452 }
4453 } else if (kvm_cpu_has_interrupt(vcpu)) {
4454 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4455 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4456 false);
4457 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4458 }
4459 }
4460}
4461
851ba692 4462static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4463{
4464 int r;
6a8b1d13 4465 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4466 vcpu->run->request_interrupt_window;
b6c7a5dc 4467
2e53d63a
MT		 4468 if (vcpu->requests)
4469 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4470 kvm_mmu_unload(vcpu);
4471
b6c7a5dc
HB		 4472 r = kvm_mmu_reload(vcpu);
4473 if (unlikely(r))
4474 goto out;
4475
2f52d58c
AK		 4476 if (vcpu->requests) {
4477 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4478 __kvm_migrate_timers(vcpu);
c8076604
GH		 4479 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4480 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4481 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4482 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4483 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4484 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4485 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4486 &vcpu->requests)) {
851ba692 4487 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4488 r = 0;
4489 goto out;
4490 }
71c4dfaf 4491 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4492 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4493 r = 0;
4494 goto out;
4495 }
02daab21
AK		 4496 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4497 vcpu->fpu_active = 0;
4498 kvm_x86_ops->fpu_deactivate(vcpu);
4499 }
2f52d58c 4500 }
b93463aa 4501
b6c7a5dc
HB		 4502 preempt_disable();
4503
4504 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4505 if (vcpu->fpu_active)
4506 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4507
4508 local_irq_disable();
4509
32f88400
MT		 4510 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4511 smp_mb__after_clear_bit();
4512
d7690175 4513 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4514 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4515 local_irq_enable();
4516 preempt_enable();
4517 r = 1;
4518 goto out;
4519 }
4520
851ba692 4521 inject_pending_event(vcpu);
b6c7a5dc 4522
6a8b1d13
GN		 4523 /* enable NMI/IRQ window open exits if needed */
4524 if (vcpu->arch.nmi_pending)
4525 kvm_x86_ops->enable_nmi_window(vcpu);
4526 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4527 kvm_x86_ops->enable_irq_window(vcpu);
4528
95ba8273 4529 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4530 update_cr8_intercept(vcpu);
4531 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4532 }
b93463aa 4533
f656ce01 4534 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4535
b6c7a5dc
HB		 4536 kvm_guest_enter();
4537
42dbaa5a 4538 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4539 set_debugreg(0, 7);
4540 set_debugreg(vcpu->arch.eff_db[0], 0);
4541 set_debugreg(vcpu->arch.eff_db[1], 1);
4542 set_debugreg(vcpu->arch.eff_db[2], 2);
4543 set_debugreg(vcpu->arch.eff_db[3], 3);
4544 }
b6c7a5dc 4545
229456fc 4546 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4547 kvm_x86_ops->run(vcpu);
b6c7a5dc 4548
24f1e32c
FW		 4549 /*
4550 * If the guest has used debug registers, at least dr7
4551 * will be disabled while returning to the host.
4552 * If we don't have active breakpoints in the host, we don't
4553 * care about the messed up debug address registers. But if
4554 * we have some of them active, restore the old state.
4555 */
59d8eb53 4556 if (hw_breakpoint_active())
24f1e32c 4557 hw_breakpoint_restore();
42dbaa5a 4558
32f88400 4559 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4560 local_irq_enable();
4561
4562 ++vcpu->stat.exits;
4563
4564 /*
4565 * We must have an instruction between local_irq_enable() and
4566 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4567 * the interrupt shadow. The stat.exits increment will do nicely.
4568 * But we need to prevent reordering, hence this barrier():
4569 */
4570 barrier();
4571
4572 kvm_guest_exit();
4573
4574 preempt_enable();
4575
f656ce01 4576 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4577
b6c7a5dc
HB		 4578 /*
4579 * Profile KVM exit RIPs:
4580 */
4581 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4582 unsigned long rip = kvm_rip_read(vcpu);
4583 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4584 }
4585
298101da 4586
b93463aa
AK		 4587 kvm_lapic_sync_from_vapic(vcpu);
4588
851ba692 4589 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4590out:
4591 return r;
4592}
b6c7a5dc 4593
09cec754 4594
851ba692 4595static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4596{
4597 int r;
f656ce01 4598 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4599
4600 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4601 pr_debug("vcpu %d received sipi with vector # %x\n",
4602 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4603 kvm_lapic_reset(vcpu);
5f179287 4604 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4605 if (r)
4606 return r;
4607 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4608 }
4609
f656ce01 4610 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4611 vapic_enter(vcpu);
4612
4613 r = 1;
4614 while (r > 0) {
af2152f5 4615 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4616 r = vcpu_enter_guest(vcpu);
d7690175 4617 else {
f656ce01 4618 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4619 kvm_vcpu_block(vcpu);
f656ce01 4620 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4621 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4622 {
4623 switch(vcpu->arch.mp_state) {
4624 case KVM_MP_STATE_HALTED:
d7690175 4625 vcpu->arch.mp_state =
09cec754
GN		 4626 KVM_MP_STATE_RUNNABLE;
4627 case KVM_MP_STATE_RUNNABLE:
4628 break;
4629 case KVM_MP_STATE_SIPI_RECEIVED:
4630 default:
4631 r = -EINTR;
4632 break;
4633 }
4634 }
d7690175
MT		 4635 }
4636
09cec754
GN		 4637 if (r <= 0)
4638 break;
4639
4640 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4641 if (kvm_cpu_has_pending_timer(vcpu))
4642 kvm_inject_pending_timer_irqs(vcpu);
4643
851ba692 4644 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4645 r = -EINTR;
851ba692 4646 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4647 ++vcpu->stat.request_irq_exits;
4648 }
4649 if (signal_pending(current)) {
4650 r = -EINTR;
851ba692 4651 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4652 ++vcpu->stat.signal_exits;
4653 }
4654 if (need_resched()) {
f656ce01 4655 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4656 kvm_resched(vcpu);
f656ce01 4657 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4658 }
b6c7a5dc
HB		 4659 }
4660
f656ce01 4661 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4662
b93463aa
AK		 4663 vapic_exit(vcpu);
4664
b6c7a5dc
HB		 4665 return r;
4666}
4667
4668int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4669{
4670 int r;
4671 sigset_t sigsaved;
4672
4673 vcpu_load(vcpu);
4674
ac9f6dc0
AK		 4675 if (vcpu->sigset_active)
4676 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4677
a4535290 4678 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4679 kvm_vcpu_block(vcpu);
d7690175 4680 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4681 r = -EAGAIN;
4682 goto out;
b6c7a5dc
HB		 4683 }
4684
b6c7a5dc
HB		 4685 /* re-sync apic's tpr */
4686 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4687 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4688
92bf9748
GN		 4689 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4690 vcpu->arch.emulate_ctxt.restart) {
4691 if (vcpu->mmio_needed) {
4692 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4693 vcpu->mmio_read_completed = 1;
4694 vcpu->mmio_needed = 0;
b6c7a5dc 4695 }
5cd21917
GN		 4696 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4697 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
4698 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4699 if (r == EMULATE_DO_MMIO) {
4700 r = 0;
4701 goto out;
4702 }
4703 }
5fdbf976
MT		 4704 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4705 kvm_register_write(vcpu, VCPU_REGS_RAX,
4706 kvm_run->hypercall.ret);
b6c7a5dc 4707
851ba692 4708 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4709
4710out:
f1d86e46 4711 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4712 if (vcpu->sigset_active)
4713 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4714
4715 vcpu_put(vcpu);
4716 return r;
4717}
4718
4719int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4720{
4721 vcpu_load(vcpu);
4722
5fdbf976
MT		 4723 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4724 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4725 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4726 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4727 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4728 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4729 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4730 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4731#ifdef CONFIG_X86_64
5fdbf976
MT		 4732 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4733 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4734 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4735 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4736 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4737 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4738 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4739 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4740#endif
4741
5fdbf976 4742 regs->rip = kvm_rip_read(vcpu);
91586a3b 4743 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4744
4745 vcpu_put(vcpu);
4746
4747 return 0;
4748}
4749
4750int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4751{
4752 vcpu_load(vcpu);
4753
5fdbf976
MT		 4754 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4755 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4756 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4757 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4758 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4759 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4760 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4761 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4762#ifdef CONFIG_X86_64
5fdbf976
MT		 4763 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4764 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4765 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4766 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4767 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4768 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4769 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4770 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4771#endif
4772
5fdbf976 4773 kvm_rip_write(vcpu, regs->rip);
91586a3b 4774 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4775
b4f14abd
JK		 4776 vcpu->arch.exception.pending = false;
4777
b6c7a5dc
HB		 4778 vcpu_put(vcpu);
4779
4780 return 0;
4781}
4782
b6c7a5dc
HB		 4783void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4784{
4785 struct kvm_segment cs;
4786
3e6e0aab 4787 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4788 *db = cs.db;
4789 *l = cs.l;
4790}
4791EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4792
4793int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4794 struct kvm_sregs *sregs)
4795{
89a27f4d 4796 struct desc_ptr dt;
b6c7a5dc
HB		 4797
4798 vcpu_load(vcpu);
4799
3e6e0aab
GT		 4800 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4801 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4802 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4803 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4804 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4805 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4806
3e6e0aab
GT		 4807 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4808 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4809
4810 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4811 sregs->idt.limit = dt.size;
4812 sregs->idt.base = dt.address;
b6c7a5dc 4813 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4814 sregs->gdt.limit = dt.size;
4815 sregs->gdt.base = dt.address;
b6c7a5dc 4816
4d4ec087 4817 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4818 sregs->cr2 = vcpu->arch.cr2;
4819 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4820 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4821 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4822 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4823 sregs->apic_base = kvm_get_apic_base(vcpu);
4824
923c61bb 4825 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4826
36752c9b 4827 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4828 set_bit(vcpu->arch.interrupt.nr,
4829 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4830
b6c7a5dc
HB		 4831 vcpu_put(vcpu);
4832
4833 return 0;
4834}
4835
62d9f0db
MT		 4836int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4837 struct kvm_mp_state *mp_state)
4838{
4839 vcpu_load(vcpu);
4840 mp_state->mp_state = vcpu->arch.mp_state;
4841 vcpu_put(vcpu);
4842 return 0;
4843}
4844
4845int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4846 struct kvm_mp_state *mp_state)
4847{
4848 vcpu_load(vcpu);
4849 vcpu->arch.mp_state = mp_state->mp_state;
4850 vcpu_put(vcpu);
4851 return 0;
4852}
4853
e269fb21
JK		 4854int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
4855 bool has_error_code, u32 error_code)
37817f29 4856{
ceffb459
GN		 4857 int cs_db, cs_l, ret;
4858 cache_all_regs(vcpu);
37817f29 4859
ceffb459 4860 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
b237ac37 4861
ceffb459
GN		 4862 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4863 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4864 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4865 vcpu->arch.emulate_ctxt.mode =
4866 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4867 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4868 ? X86EMUL_MODE_VM86 : cs_l
4869 ? X86EMUL_MODE_PROT64 : cs_db
4870 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
37817f29 4871
ceffb459 4872 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 4873 tss_selector, reason, has_error_code,
4874 error_code);
37817f29 4875
19d04437
GN		 4876 if (ret)
4877 return EMULATE_FAIL;
37817f29 4878
19d04437
GN		 4879 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4880 return EMULATE_DONE;
37817f29
IE		 4881}
4882EXPORT_SYMBOL_GPL(kvm_task_switch);
4883
b6c7a5dc
HB		 4884int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4885 struct kvm_sregs *sregs)
4886{
4887 int mmu_reset_needed = 0;
923c61bb 4888 int pending_vec, max_bits;
89a27f4d 4889 struct desc_ptr dt;
b6c7a5dc
HB		 4890
4891 vcpu_load(vcpu);
4892
89a27f4d
GN		 4893 dt.size = sregs->idt.limit;
4894 dt.address = sregs->idt.base;
b6c7a5dc 4895 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 4896 dt.size = sregs->gdt.limit;
4897 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 4898 kvm_x86_ops->set_gdt(vcpu, &dt);
4899
ad312c7c
ZX		 4900 vcpu->arch.cr2 = sregs->cr2;
4901 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4902 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4903
2d3ad1f4 4904 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4905
f6801dff 4906 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 4907 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4908 kvm_set_apic_base(vcpu, sregs->apic_base);
4909
4d4ec087 4910 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 4911 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4912 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4913
fc78f519 4914 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4915 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4916 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4917 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4918 mmu_reset_needed = 1;
4919 }
b6c7a5dc
HB		 4920
4921 if (mmu_reset_needed)
4922 kvm_mmu_reset_context(vcpu);
4923
923c61bb
GN		 4924 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4925 pending_vec = find_first_bit(
4926 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4927 if (pending_vec < max_bits) {
66fd3f7f 4928 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4929 pr_debug("Set back pending irq %d\n", pending_vec);
4930 if (irqchip_in_kernel(vcpu->kvm))
4931 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4932 }
4933
3e6e0aab
GT		 4934 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4935 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4936 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4937 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4938 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4939 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4940
3e6e0aab
GT		 4941 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4942 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4943
5f0269f5
ME		 4944 update_cr8_intercept(vcpu);
4945
9c3e4aab 4946 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4947 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 4948 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 4949 !is_protmode(vcpu))
9c3e4aab
MT		 4950 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4951
b6c7a5dc
HB		 4952 vcpu_put(vcpu);
4953
4954 return 0;
4955}
4956
d0bfb940
JK		 4957int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4958 struct kvm_guest_debug *dbg)
b6c7a5dc 4959{
355be0b9 4960 unsigned long rflags;
ae675ef0 4961 int i, r;
b6c7a5dc
HB		 4962
4963 vcpu_load(vcpu);
4964
4f926bf2
JK		 4965 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
4966 r = -EBUSY;
4967 if (vcpu->arch.exception.pending)
4968 goto unlock_out;
4969 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4970 kvm_queue_exception(vcpu, DB_VECTOR);
4971 else
4972 kvm_queue_exception(vcpu, BP_VECTOR);
4973 }
4974
91586a3b
JK		 4975 /*
4976 * Read rflags as long as potentially injected trace flags are still
4977 * filtered out.
4978 */
4979 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 4980
4981 vcpu->guest_debug = dbg->control;
4982 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
4983 vcpu->guest_debug = 0;
4984
4985 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 4986 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4987 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4988 vcpu->arch.switch_db_regs =
4989 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4990 } else {
4991 for (i = 0; i < KVM_NR_DB_REGS; i++)
4992 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4993 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4994 }
4995
f92653ee
JK		 4996 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4997 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
4998 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 4999
91586a3b
JK		 5000 /*
5001 * Trigger an rflags update that will inject or remove the trace
5002 * flags.
5003 */
5004 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5005
355be0b9 5006 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5007
4f926bf2 5008 r = 0;
d0bfb940 5009
4f926bf2 5010unlock_out:
b6c7a5dc
HB		 5011 vcpu_put(vcpu);
5012
5013 return r;
5014}
5015
d0752060
HB		 5016/*
5017 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5018 * we have asm/x86/processor.h
5019 */
5020struct fxsave {
5021 u16 cwd;
5022 u16 swd;
5023 u16 twd;
5024 u16 fop;
5025 u64 rip;
5026 u64 rdp;
5027 u32 mxcsr;
5028 u32 mxcsr_mask;
5029 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5030#ifdef CONFIG_X86_64
5031 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5032#else
5033 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5034#endif
5035};
5036
8b006791
ZX		 5037/*
5038 * Translate a guest virtual address to a guest physical address.
5039 */
5040int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5041 struct kvm_translation *tr)
5042{
5043 unsigned long vaddr = tr->linear_address;
5044 gpa_t gpa;
f656ce01 5045 int idx;
8b006791
ZX		 5046
5047 vcpu_load(vcpu);
f656ce01 5048 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5049 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5050 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5051 tr->physical_address = gpa;
5052 tr->valid = gpa != UNMAPPED_GVA;
5053 tr->writeable = 1;
5054 tr->usermode = 0;
8b006791
ZX		 5055 vcpu_put(vcpu);
5056
5057 return 0;
5058}
5059
d0752060
HB		 5060int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5061{
ad312c7c 5062 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5063
5064 vcpu_load(vcpu);
5065
5066 memcpy(fpu->fpr, fxsave->st_space, 128);
5067 fpu->fcw = fxsave->cwd;
5068 fpu->fsw = fxsave->swd;
5069 fpu->ftwx = fxsave->twd;
5070 fpu->last_opcode = fxsave->fop;
5071 fpu->last_ip = fxsave->rip;
5072 fpu->last_dp = fxsave->rdp;
5073 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5074
5075 vcpu_put(vcpu);
5076
5077 return 0;
5078}
5079
5080int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5081{
ad312c7c 5082 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5083
5084 vcpu_load(vcpu);
5085
5086 memcpy(fxsave->st_space, fpu->fpr, 128);
5087 fxsave->cwd = fpu->fcw;
5088 fxsave->swd = fpu->fsw;
5089 fxsave->twd = fpu->ftwx;
5090 fxsave->fop = fpu->last_opcode;
5091 fxsave->rip = fpu->last_ip;
5092 fxsave->rdp = fpu->last_dp;
5093 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5094
5095 vcpu_put(vcpu);
5096
5097 return 0;
5098}
5099
5100void fx_init(struct kvm_vcpu *vcpu)
5101{
5102 unsigned after_mxcsr_mask;
5103
bc1a34f1
AA		 5104 /*
5105 * Touch the fpu the first time in non atomic context as if
5106 * this is the first fpu instruction the exception handler
5107 * will fire before the instruction returns and it'll have to
5108 * allocate ram with GFP_KERNEL.
5109 */
5110 if (!used_math())
d6e88aec 5111 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5112
d0752060
HB		 5113 /* Initialize guest FPU by resetting ours and saving into guest's */
5114 preempt_disable();
d6e88aec
AK		 5115 kvm_fx_save(&vcpu->arch.host_fx_image);
5116 kvm_fx_finit();
5117 kvm_fx_save(&vcpu->arch.guest_fx_image);
5118 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5119 preempt_enable();
5120
ad312c7c 5121 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5122 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5123 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5124 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5125 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5126}
5127EXPORT_SYMBOL_GPL(fx_init);
5128
5129void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5130{
2608d7a1 5131 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5132 return;
5133
5134 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5135 kvm_fx_save(&vcpu->arch.host_fx_image);
5136 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5137 trace_kvm_fpu(1);
d0752060 5138}
d0752060
HB		 5139
5140void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5141{
5142 if (!vcpu->guest_fpu_loaded)
5143 return;
5144
5145 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5146 kvm_fx_save(&vcpu->arch.guest_fx_image);
5147 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5148 ++vcpu->stat.fpu_reload;
02daab21 5149 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5150 trace_kvm_fpu(0);
d0752060 5151}
e9b11c17
ZX		 5152
5153void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5154{
7f1ea208
JR		 5155 if (vcpu->arch.time_page) {
5156 kvm_release_page_dirty(vcpu->arch.time_page);
5157 vcpu->arch.time_page = NULL;
5158 }
5159
e9b11c17
ZX		 5160 kvm_x86_ops->vcpu_free(vcpu);
5161}
5162
5163struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5164 unsigned int id)
5165{
26e5215f
AK		 5166 return kvm_x86_ops->vcpu_create(kvm, id);
5167}
e9b11c17 5168
26e5215f
AK		 5169int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5170{
5171 int r;
e9b11c17
ZX		 5172
5173 /* We do fxsave: this must be aligned. */
ad312c7c 5174 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5175
0bed3b56 5176 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5177 vcpu_load(vcpu);
5178 r = kvm_arch_vcpu_reset(vcpu);
5179 if (r == 0)
5180 r = kvm_mmu_setup(vcpu);
5181 vcpu_put(vcpu);
5182 if (r < 0)
5183 goto free_vcpu;
5184
26e5215f 5185 return 0;
e9b11c17
ZX		 5186free_vcpu:
5187 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5188 return r;
e9b11c17
ZX		 5189}
5190
d40ccc62 5191void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5192{
5193 vcpu_load(vcpu);
5194 kvm_mmu_unload(vcpu);
5195 vcpu_put(vcpu);
5196
5197 kvm_x86_ops->vcpu_free(vcpu);
5198}
5199
5200int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5201{
448fa4a9
JK		 5202 vcpu->arch.nmi_pending = false;
5203 vcpu->arch.nmi_injected = false;
5204
42dbaa5a
JK		 5205 vcpu->arch.switch_db_regs = 0;
5206 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5207 vcpu->arch.dr6 = DR6_FIXED_1;
5208 vcpu->arch.dr7 = DR7_FIXED_1;
5209
e9b11c17
ZX		 5210 return kvm_x86_ops->vcpu_reset(vcpu);
5211}
5212
10474ae8 5213int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5214{
0cca7907
ZA		 5215 /*
5216 * Since this may be called from a hotplug notifcation,
5217 * we can't get the CPU frequency directly.
5218 */
5219 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5220 int cpu = raw_smp_processor_id();
5221 per_cpu(cpu_tsc_khz, cpu) = 0;
5222 }
18863bdd
AK		 5223
5224 kvm_shared_msr_cpu_online();
5225
10474ae8 5226 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5227}
5228
5229void kvm_arch_hardware_disable(void *garbage)
5230{
5231 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5232 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5233}
5234
5235int kvm_arch_hardware_setup(void)
5236{
5237 return kvm_x86_ops->hardware_setup();
5238}
5239
5240void kvm_arch_hardware_unsetup(void)
5241{
5242 kvm_x86_ops->hardware_unsetup();
5243}
5244
5245void kvm_arch_check_processor_compat(void *rtn)
5246{
5247 kvm_x86_ops->check_processor_compatibility(rtn);
5248}
5249
5250int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5251{
5252 struct page *page;
5253 struct kvm *kvm;
5254 int r;
5255
5256 BUG_ON(vcpu->kvm == NULL);
5257 kvm = vcpu->kvm;
5258
ad312c7c 5259 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5260 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5261 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5262 else
a4535290 5263 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5264
5265 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5266 if (!page) {
5267 r = -ENOMEM;
5268 goto fail;
5269 }
ad312c7c 5270 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5271
5272 r = kvm_mmu_create(vcpu);
5273 if (r < 0)
5274 goto fail_free_pio_data;
5275
5276 if (irqchip_in_kernel(kvm)) {
5277 r = kvm_create_lapic(vcpu);
5278 if (r < 0)
5279 goto fail_mmu_destroy;
5280 }
5281
890ca9ae
HY		 5282 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5283 GFP_KERNEL);
5284 if (!vcpu->arch.mce_banks) {
5285 r = -ENOMEM;
443c39bc 5286 goto fail_free_lapic;
890ca9ae
HY		 5287 }
5288 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5289
e9b11c17 5290 return 0;
443c39bc
WY		 5291fail_free_lapic:
5292 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5293fail_mmu_destroy:
5294 kvm_mmu_destroy(vcpu);
5295fail_free_pio_data:
ad312c7c 5296 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5297fail:
5298 return r;
5299}
5300
5301void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5302{
f656ce01
MT		 5303 int idx;
5304
36cb93fd 5305 kfree(vcpu->arch.mce_banks);
e9b11c17 5306 kvm_free_lapic(vcpu);
f656ce01 5307 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5308 kvm_mmu_destroy(vcpu);
f656ce01 5309 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5310 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5311}
d19a9cd2
ZX		 5312
5313struct kvm *kvm_arch_create_vm(void)
5314{
5315 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5316
5317 if (!kvm)
5318 return ERR_PTR(-ENOMEM);
5319
fef9cce0
MT		 5320 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5321 if (!kvm->arch.aliases) {
5322 kfree(kvm);
5323 return ERR_PTR(-ENOMEM);
5324 }
5325
f05e70ac 5326 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5327 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5328
5550af4d
SY		 5329 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5330 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5331
53f658b3
MT		 5332 rdtscll(kvm->arch.vm_init_tsc);
5333
d19a9cd2
ZX		 5334 return kvm;
5335}
5336
5337static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5338{
5339 vcpu_load(vcpu);
5340 kvm_mmu_unload(vcpu);
5341 vcpu_put(vcpu);
5342}
5343
5344static void kvm_free_vcpus(struct kvm *kvm)
5345{
5346 unsigned int i;
988a2cae 5347 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5348
5349 /*
5350 * Unpin any mmu pages first.
5351 */
988a2cae
GN		 5352 kvm_for_each_vcpu(i, vcpu, kvm)
5353 kvm_unload_vcpu_mmu(vcpu);
5354 kvm_for_each_vcpu(i, vcpu, kvm)
5355 kvm_arch_vcpu_free(vcpu);
5356
5357 mutex_lock(&kvm->lock);
5358 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5359 kvm->vcpus[i] = NULL;
d19a9cd2 5360
988a2cae
GN		 5361 atomic_set(&kvm->online_vcpus, 0);
5362 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5363}
5364
ad8ba2cd
SY		 5365void kvm_arch_sync_events(struct kvm *kvm)
5366{
ba4cef31 5367 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5368}
5369
d19a9cd2
ZX		 5370void kvm_arch_destroy_vm(struct kvm *kvm)
5371{
6eb55818 5372 kvm_iommu_unmap_guest(kvm);
7837699f 5373 kvm_free_pit(kvm);
d7deeeb0
ZX		 5374 kfree(kvm->arch.vpic);
5375 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5376 kvm_free_vcpus(kvm);
5377 kvm_free_physmem(kvm);
3d45830c
AK		 5378 if (kvm->arch.apic_access_page)
5379 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5380 if (kvm->arch.ept_identity_pagetable)
5381 put_page(kvm->arch.ept_identity_pagetable);
64749204 5382 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5383 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5384 kfree(kvm);
5385}
0de10343 5386
f7784b8e
MT		 5387int kvm_arch_prepare_memory_region(struct kvm *kvm,
5388 struct kvm_memory_slot *memslot,
0de10343 5389 struct kvm_memory_slot old,
f7784b8e 5390 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5391 int user_alloc)
5392{
f7784b8e 5393 int npages = memslot->npages;
0de10343
ZX		 5394
5395 /*To keep backward compatibility with older userspace,
5396 *x86 needs to hanlde !user_alloc case.
5397 */
5398 if (!user_alloc) {
5399 if (npages && !old.rmap) {
604b38ac
AA		 5400 unsigned long userspace_addr;
5401
72dc67a6 5402 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5403 userspace_addr = do_mmap(NULL, 0,
5404 npages * PAGE_SIZE,
5405 PROT_READ | PROT_WRITE,
acee3c04 5406 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5407 0);
72dc67a6 5408 up_write(&current->mm->mmap_sem);
0de10343 5409
604b38ac
AA		 5410 if (IS_ERR((void *)userspace_addr))
5411 return PTR_ERR((void *)userspace_addr);
5412
604b38ac 5413 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5414 }
5415 }
5416
f7784b8e
MT		 5417
5418 return 0;
5419}
5420
5421void kvm_arch_commit_memory_region(struct kvm *kvm,
5422 struct kvm_userspace_memory_region *mem,
5423 struct kvm_memory_slot old,
5424 int user_alloc)
5425{
5426
5427 int npages = mem->memory_size >> PAGE_SHIFT;
5428
5429 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5430 int ret;
5431
5432 down_write(&current->mm->mmap_sem);
5433 ret = do_munmap(current->mm, old.userspace_addr,
5434 old.npages * PAGE_SIZE);
5435 up_write(&current->mm->mmap_sem);
5436 if (ret < 0)
5437 printk(KERN_WARNING
5438 "kvm_vm_ioctl_set_memory_region: "
5439 "failed to munmap memory\n");
5440 }
5441
7c8a83b7 5442 spin_lock(&kvm->mmu_lock);
f05e70ac 5443 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5444 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5445 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5446 }
5447
5448 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5449 spin_unlock(&kvm->mmu_lock);
0de10343 5450}
1d737c8a 5451
34d4cb8f
MT		 5452void kvm_arch_flush_shadow(struct kvm *kvm)
5453{
5454 kvm_mmu_zap_all(kvm);
8986ecc0 5455 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5456}
5457
1d737c8a
ZX		 5458int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5459{
a4535290 5460 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5461 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5462 || vcpu->arch.nmi_pending ||
5463 (kvm_arch_interrupt_allowed(vcpu) &&
5464 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5465}
5736199a 5466
5736199a
ZX		 5467void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5468{
32f88400
MT		 5469 int me;
5470 int cpu = vcpu->cpu;
5736199a
ZX		 5471
5472 if (waitqueue_active(&vcpu->wq)) {
5473 wake_up_interruptible(&vcpu->wq);
5474 ++vcpu->stat.halt_wakeup;
5475 }
32f88400
MT		 5476
5477 me = get_cpu();
5478 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5479 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5480 smp_send_reschedule(cpu);
e9571ed5 5481 put_cpu();
5736199a 5482}
78646121
GN		 5483
5484int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5485{
5486 return kvm_x86_ops->interrupt_allowed(vcpu);
5487}
229456fc 5488
f92653ee
JK		 5489bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5490{
5491 unsigned long current_rip = kvm_rip_read(vcpu) +
5492 get_segment_base(vcpu, VCPU_SREG_CS);
5493
5494 return current_rip == linear_rip;
5495}
5496EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5497
94fe45da
JK		 5498unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5499{
5500 unsigned long rflags;
5501
5502 rflags = kvm_x86_ops->get_rflags(vcpu);
5503 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5504 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5505 return rflags;
5506}
5507EXPORT_SYMBOL_GPL(kvm_get_rflags);
5508
5509void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5510{
5511 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5512 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5513 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5514 kvm_x86_ops->set_rflags(vcpu, rflags);
5515}
5516EXPORT_SYMBOL_GPL(kvm_set_rflags);
5517
229456fc
MT		 5518EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5519EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5520EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5521EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5522EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5523EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5524EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5525EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5526EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5527EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5528EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5529EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 6.x block layer and io_uring tree(s)