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kvm: Convert kvm_lock to a mutex
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
bf8c55d8 72#include <asm/intel_pt.h>
043405e1 73
d1898b73
DH		 74#define CREATE_TRACE_POINTS
75#include "trace.h"
76
313a3dc7 77#define MAX_IO_MSRS 256
890ca9ae 78#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 79u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 81
0f65dd70
AK		 82#define emul_to_vcpu(ctxt) \
83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
84
50a37eb4
JR		 85/* EFER defaults:
86 * - enable syscall per default because its emulated by KVM
87 * - enable LME and LMA per default on 64 bit KVM
88 */
89#ifdef CONFIG_X86_64
1260edbe
LJ		 90static
91u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 92#else
1260edbe 93static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 94#endif
313a3dc7 95
ba1389b7
AK		 96#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
97#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 98
c519265f
RK		 99#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
100 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 101
cb142eb7 102static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 103static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 104static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 105static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 106static void store_regs(struct kvm_vcpu *vcpu);
107static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 108
893590c7 109struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 110EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 111
893590c7 112static bool __read_mostly ignore_msrs = 0;
476bc001 113module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 114
fab0aa3b
EM		 115static bool __read_mostly report_ignored_msrs = true;
116module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117
4c27625b 118unsigned int min_timer_period_us = 200;
9ed96e87
MT		 119module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120
630994b3
MT		 121static bool __read_mostly kvmclock_periodic_sync = true;
122module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123
893590c7 124bool __read_mostly kvm_has_tsc_control;
92a1f12d 125EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 126u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 127EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 128u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
129EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
130u64 __read_mostly kvm_max_tsc_scaling_ratio;
131EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 132u64 __read_mostly kvm_default_tsc_scaling_ratio;
133EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 134
cc578287 135/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 136static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 137module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
138
c3941d9e
SC		 139/*
140 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
141 * adaptive tuning starting from default advancment of 1000ns. '0' disables
142 * advancement entirely. Any other value is used as-is and disables adaptive
143 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
144 */
145static int __read_mostly lapic_timer_advance_ns = -1;
0e6edceb 146module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
d0659d94 147
52004014
FW		 148static bool __read_mostly vector_hashing = true;
149module_param(vector_hashing, bool, S_IRUGO);
150
c4ae60e4
LA		 151bool __read_mostly enable_vmware_backdoor = false;
152module_param(enable_vmware_backdoor, bool, S_IRUGO);
153EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
154
6c86eedc
WL		 155static bool __read_mostly force_emulation_prefix = false;
156module_param(force_emulation_prefix, bool, S_IRUGO);
157
18863bdd
AK		 158#define KVM_NR_SHARED_MSRS 16
159
160struct kvm_shared_msrs_global {
161 int nr;
2bf78fa7 162 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 163};
164
165struct kvm_shared_msrs {
166 struct user_return_notifier urn;
167 bool registered;
2bf78fa7
SY		 168 struct kvm_shared_msr_values {
169 u64 host;
170 u64 curr;
171 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 172};
173
174static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 175static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 176
417bc304 177struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 178 { "pf_fixed", VCPU_STAT(pf_fixed) },
179 { "pf_guest", VCPU_STAT(pf_guest) },
180 { "tlb_flush", VCPU_STAT(tlb_flush) },
181 { "invlpg", VCPU_STAT(invlpg) },
182 { "exits", VCPU_STAT(exits) },
183 { "io_exits", VCPU_STAT(io_exits) },
184 { "mmio_exits", VCPU_STAT(mmio_exits) },
185 { "signal_exits", VCPU_STAT(signal_exits) },
186 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 187 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 188 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 189 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 190 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 191 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 192 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 193 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 194 { "request_irq", VCPU_STAT(request_irq_exits) },
195 { "irq_exits", VCPU_STAT(irq_exits) },
196 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 197 { "fpu_reload", VCPU_STAT(fpu_reload) },
198 { "insn_emulation", VCPU_STAT(insn_emulation) },
199 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 200 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 201 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 202 { "req_event", VCPU_STAT(req_event) },
c595ceee 203 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 204 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
205 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
206 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
207 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
208 { "mmu_flooded", VM_STAT(mmu_flooded) },
209 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 210 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 211 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 212 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 213 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 214 { "max_mmu_page_hash_collisions",
215 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 216 { NULL }
217};
218
2acf923e
DC		 219u64 __read_mostly host_xcr0;
220
b666a4b6
MO		 221struct kmem_cache *x86_fpu_cache;
222EXPORT_SYMBOL_GPL(x86_fpu_cache);
223
b6785def 224static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 225
af585b92
GN		 226static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
227{
228 int i;
229 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
230 vcpu->arch.apf.gfns[i] = ~0;
231}
232
18863bdd
AK		 233static void kvm_on_user_return(struct user_return_notifier *urn)
234{
235 unsigned slot;
18863bdd
AK		 236 struct kvm_shared_msrs *locals
237 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 238 struct kvm_shared_msr_values *values;
1650b4eb
IA		 239 unsigned long flags;
240
241 /*
242 * Disabling irqs at this point since the following code could be
243 * interrupted and executed through kvm_arch_hardware_disable()
244 */
245 local_irq_save(flags);
246 if (locals->registered) {
247 locals->registered = false;
248 user_return_notifier_unregister(urn);
249 }
250 local_irq_restore(flags);
18863bdd 251 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 252 values = &locals->values[slot];
253 if (values->host != values->curr) {
254 wrmsrl(shared_msrs_global.msrs[slot], values->host);
255 values->curr = values->host;
18863bdd
AK		 256 }
257 }
18863bdd
AK		 258}
259
2bf78fa7 260static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 261{
18863bdd 262 u64 value;
013f6a5d
MT		 263 unsigned int cpu = smp_processor_id();
264 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 265
2bf78fa7
SY		 266 /* only read, and nobody should modify it at this time,
267 * so don't need lock */
268 if (slot >= shared_msrs_global.nr) {
269 printk(KERN_ERR "kvm: invalid MSR slot!");
270 return;
271 }
272 rdmsrl_safe(msr, &value);
273 smsr->values[slot].host = value;
274 smsr->values[slot].curr = value;
275}
276
277void kvm_define_shared_msr(unsigned slot, u32 msr)
278{
0123be42 279 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 280 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 281 if (slot >= shared_msrs_global.nr)
282 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 283}
284EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
285
286static void kvm_shared_msr_cpu_online(void)
287{
288 unsigned i;
18863bdd
AK		 289
290 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 291 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 292}
293
8b3c3104 294int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 295{
013f6a5d
MT		 296 unsigned int cpu = smp_processor_id();
297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 298 int err;
18863bdd 299
2bf78fa7 300 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 301 return 0;
2bf78fa7 302 smsr->values[slot].curr = value;
8b3c3104
AH		 303 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
304 if (err)
305 return 1;
306
18863bdd
AK		 307 if (!smsr->registered) {
308 smsr->urn.on_user_return = kvm_on_user_return;
309 user_return_notifier_register(&smsr->urn);
310 smsr->registered = true;
311 }
8b3c3104 312 return 0;
18863bdd
AK		 313}
314EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
315
13a34e06 316static void drop_user_return_notifiers(void)
3548bab5 317{
013f6a5d
MT		 318 unsigned int cpu = smp_processor_id();
319 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 320
321 if (smsr->registered)
322 kvm_on_user_return(&smsr->urn);
323}
324
6866b83e
CO		 325u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
326{
8a5a87d9 327 return vcpu->arch.apic_base;
6866b83e
CO		 328}
329EXPORT_SYMBOL_GPL(kvm_get_apic_base);
330
58871649
JM		 331enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
332{
333 return kvm_apic_mode(kvm_get_apic_base(vcpu));
334}
335EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
336
58cb628d
JK		 337int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
338{
58871649
JM		 339 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
340 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 341 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
342 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 343
58871649 344 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 345 return 1;
58871649
JM		 346 if (!msr_info->host_initiated) {
347 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
348 return 1;
349 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
350 return 1;
351 }
58cb628d
JK		 352
353 kvm_lapic_set_base(vcpu, msr_info->data);
354 return 0;
6866b83e
CO		 355}
356EXPORT_SYMBOL_GPL(kvm_set_apic_base);
357
2605fc21 358asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 359{
360 /* Fault while not rebooting. We want the trace. */
361 BUG();
362}
363EXPORT_SYMBOL_GPL(kvm_spurious_fault);
364
3fd28fce
ED		 365#define EXCPT_BENIGN 0
366#define EXCPT_CONTRIBUTORY 1
367#define EXCPT_PF 2
368
369static int exception_class(int vector)
370{
371 switch (vector) {
372 case PF_VECTOR:
373 return EXCPT_PF;
374 case DE_VECTOR:
375 case TS_VECTOR:
376 case NP_VECTOR:
377 case SS_VECTOR:
378 case GP_VECTOR:
379 return EXCPT_CONTRIBUTORY;
380 default:
381 break;
382 }
383 return EXCPT_BENIGN;
384}
385
d6e8c854
NA		 386#define EXCPT_FAULT 0
387#define EXCPT_TRAP 1
388#define EXCPT_ABORT 2
389#define EXCPT_INTERRUPT 3
390
391static int exception_type(int vector)
392{
393 unsigned int mask;
394
395 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
396 return EXCPT_INTERRUPT;
397
398 mask = 1 << vector;
399
400 /* #DB is trap, as instruction watchpoints are handled elsewhere */
401 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
402 return EXCPT_TRAP;
403
404 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
405 return EXCPT_ABORT;
406
407 /* Reserved exceptions will result in fault */
408 return EXCPT_FAULT;
409}
410
da998b46
JM		 411void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
412{
413 unsigned nr = vcpu->arch.exception.nr;
414 bool has_payload = vcpu->arch.exception.has_payload;
415 unsigned long payload = vcpu->arch.exception.payload;
416
417 if (!has_payload)
418 return;
419
420 switch (nr) {
f10c729f
JM		 421 case DB_VECTOR:
422 /*
423 * "Certain debug exceptions may clear bit 0-3. The
424 * remaining contents of the DR6 register are never
425 * cleared by the processor".
426 */
427 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
428 /*
429 * DR6.RTM is set by all #DB exceptions that don't clear it.
430 */
431 vcpu->arch.dr6 |= DR6_RTM;
432 vcpu->arch.dr6 |= payload;
433 /*
434 * Bit 16 should be set in the payload whenever the #DB
435 * exception should clear DR6.RTM. This makes the payload
436 * compatible with the pending debug exceptions under VMX.
437 * Though not currently documented in the SDM, this also
438 * makes the payload compatible with the exit qualification
439 * for #DB exceptions under VMX.
440 */
441 vcpu->arch.dr6 ^= payload & DR6_RTM;
442 break;
da998b46
JM		 443 case PF_VECTOR:
444 vcpu->arch.cr2 = payload;
445 break;
446 }
447
448 vcpu->arch.exception.has_payload = false;
449 vcpu->arch.exception.payload = 0;
450}
451EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
452
3fd28fce 453static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 454 unsigned nr, bool has_error, u32 error_code,
91e86d22 455 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 456{
457 u32 prev_nr;
458 int class1, class2;
459
3842d135
AK		 460 kvm_make_request(KVM_REQ_EVENT, vcpu);
461
664f8e26 462 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 463 queue:
3ffb2468
NA		 464 if (has_error && !is_protmode(vcpu))
465 has_error = false;
664f8e26
WL		 466 if (reinject) {
467 /*
468 * On vmentry, vcpu->arch.exception.pending is only
469 * true if an event injection was blocked by
470 * nested_run_pending. In that case, however,
471 * vcpu_enter_guest requests an immediate exit,
472 * and the guest shouldn't proceed far enough to
473 * need reinjection.
474 */
475 WARN_ON_ONCE(vcpu->arch.exception.pending);
476 vcpu->arch.exception.injected = true;
91e86d22
JM		 477 if (WARN_ON_ONCE(has_payload)) {
478 /*
479 * A reinjected event has already
480 * delivered its payload.
481 */
482 has_payload = false;
483 payload = 0;
484 }
664f8e26
WL		 485 } else {
486 vcpu->arch.exception.pending = true;
487 vcpu->arch.exception.injected = false;
488 }
3fd28fce
ED		 489 vcpu->arch.exception.has_error_code = has_error;
490 vcpu->arch.exception.nr = nr;
491 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 492 vcpu->arch.exception.has_payload = has_payload;
493 vcpu->arch.exception.payload = payload;
da998b46
JM		 494 /*
495 * In guest mode, payload delivery should be deferred,
496 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 497 * CR2 is modified (or intercept #DB before DR6 is
498 * modified under nVMX). However, for ABI
499 * compatibility with KVM_GET_VCPU_EVENTS and
500 * KVM_SET_VCPU_EVENTS, we can't delay payload
501 * delivery unless userspace has enabled this
502 * functionality via the per-VM capability,
503 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 504 */
505 if (!vcpu->kvm->arch.exception_payload_enabled ||
506 !is_guest_mode(vcpu))
507 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 508 return;
509 }
510
511 /* to check exception */
512 prev_nr = vcpu->arch.exception.nr;
513 if (prev_nr == DF_VECTOR) {
514 /* triple fault -> shutdown */
a8eeb04a 515 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 516 return;
517 }
518 class1 = exception_class(prev_nr);
519 class2 = exception_class(nr);
520 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
521 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 522 /*
523 * Generate double fault per SDM Table 5-5. Set
524 * exception.pending = true so that the double fault
525 * can trigger a nested vmexit.
526 */
3fd28fce 527 vcpu->arch.exception.pending = true;
664f8e26 528 vcpu->arch.exception.injected = false;
3fd28fce
ED		 529 vcpu->arch.exception.has_error_code = true;
530 vcpu->arch.exception.nr = DF_VECTOR;
531 vcpu->arch.exception.error_code = 0;
c851436a
JM		 532 vcpu->arch.exception.has_payload = false;
533 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 534 } else
535 /* replace previous exception with a new one in a hope
536 that instruction re-execution will regenerate lost
537 exception */
538 goto queue;
539}
540
298101da
AK		 541void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
542{
91e86d22 543 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 544}
545EXPORT_SYMBOL_GPL(kvm_queue_exception);
546
ce7ddec4
JR		 547void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
548{
91e86d22 549 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 550}
551EXPORT_SYMBOL_GPL(kvm_requeue_exception);
552
f10c729f
JM		 553static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
554 unsigned long payload)
555{
556 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
557}
558
da998b46
JM		 559static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
560 u32 error_code, unsigned long payload)
561{
562 kvm_multiple_exception(vcpu, nr, true, error_code,
563 true, payload, false);
564}
565
6affcbed 566int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 567{
db8fcefa
AP		 568 if (err)
569 kvm_inject_gp(vcpu, 0);
570 else
6affcbed
KH		 571 return kvm_skip_emulated_instruction(vcpu);
572
573 return 1;
db8fcefa
AP		 574}
575EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 576
6389ee94 577void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 578{
579 ++vcpu->stat.pf_guest;
adfe20fb
WL		 580 vcpu->arch.exception.nested_apf =
581 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 582 if (vcpu->arch.exception.nested_apf) {
adfe20fb 583 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 584 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
585 } else {
586 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
587 fault->address);
588 }
c3c91fee 589}
27d6c865 590EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 591
ef54bcfe 592static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 593{
6389ee94
AK		 594 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
595 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 596 else
44dd3ffa 597 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 598
599 return fault->nested_page_fault;
d4f8cf66
JR		 600}
601
3419ffc8
SY		 602void kvm_inject_nmi(struct kvm_vcpu *vcpu)
603{
7460fb4a
AK		 604 atomic_inc(&vcpu->arch.nmi_queued);
605 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 606}
607EXPORT_SYMBOL_GPL(kvm_inject_nmi);
608
298101da
AK		 609void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
610{
91e86d22 611 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 612}
613EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
614
ce7ddec4
JR		 615void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
616{
91e86d22 617 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 618}
619EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
620
0a79b009
AK		 621/*
622 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
623 * a #GP and return false.
624 */
625bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 626{
0a79b009
AK		 627 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
628 return true;
629 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
630 return false;
298101da 631}
0a79b009 632EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 633
16f8a6f9
NA		 634bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
635{
636 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
637 return true;
638
639 kvm_queue_exception(vcpu, UD_VECTOR);
640 return false;
641}
642EXPORT_SYMBOL_GPL(kvm_require_dr);
643
ec92fe44
JR		 644/*
645 * This function will be used to read from the physical memory of the currently
54bf36aa 646 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 647 * can read from guest physical or from the guest's guest physical memory.
648 */
649int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
650 gfn_t ngfn, void *data, int offset, int len,
651 u32 access)
652{
54987b7a 653 struct x86_exception exception;
ec92fe44
JR		 654 gfn_t real_gfn;
655 gpa_t ngpa;
656
657 ngpa = gfn_to_gpa(ngfn);
54987b7a 658 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 659 if (real_gfn == UNMAPPED_GVA)
660 return -EFAULT;
661
662 real_gfn = gpa_to_gfn(real_gfn);
663
54bf36aa 664 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 665}
666EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
667
69b0049a 668static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 669 void *data, int offset, int len, u32 access)
670{
671 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
672 data, offset, len, access);
673}
674
a03490ed
CO		 675/*
676 * Load the pae pdptrs. Return true is they are all valid.
677 */
ff03a073 678int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 679{
680 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
681 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
682 int i;
683 int ret;
ff03a073 684 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 685
ff03a073
JR		 686 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
687 offset * sizeof(u64), sizeof(pdpte),
688 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 689 if (ret < 0) {
690 ret = 0;
691 goto out;
692 }
693 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 694 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 695 (pdpte[i] &
44dd3ffa 696 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 697 ret = 0;
698 goto out;
699 }
700 }
701 ret = 1;
702
ff03a073 703 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 704 __set_bit(VCPU_EXREG_PDPTR,
705 (unsigned long *)&vcpu->arch.regs_avail);
706 __set_bit(VCPU_EXREG_PDPTR,
707 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 708out:
a03490ed
CO		 709
710 return ret;
711}
cc4b6871 712EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 713
9ed38ffa 714bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 715{
ff03a073 716 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 717 bool changed = true;
3d06b8bf
JR		 718 int offset;
719 gfn_t gfn;
d835dfec
AK		 720 int r;
721
d35b34a9 722 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
d835dfec
AK		 723 return false;
724
6de4f3ad
AK		 725 if (!test_bit(VCPU_EXREG_PDPTR,
726 (unsigned long *)&vcpu->arch.regs_avail))
727 return true;
728
a512177e
PB		 729 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
730 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 731 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
732 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 733 if (r < 0)
734 goto out;
ff03a073 735 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 736out:
d835dfec
AK		 737
738 return changed;
739}
9ed38ffa 740EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 741
49a9b07e 742int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 743{
aad82703 744 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 745 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 746
f9a48e6a
AK		 747 cr0 |= X86_CR0_ET;
748
ab344828 749#ifdef CONFIG_X86_64
0f12244f
GN		 750 if (cr0 & 0xffffffff00000000UL)
751 return 1;
ab344828
GN		 752#endif
753
754 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 755
0f12244f
GN		 756 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
757 return 1;
a03490ed 758
0f12244f
GN		 759 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
760 return 1;
a03490ed
CO		 761
762 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
763#ifdef CONFIG_X86_64
f6801dff 764 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 765 int cs_db, cs_l;
766
0f12244f
GN		 767 if (!is_pae(vcpu))
768 return 1;
a03490ed 769 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 770 if (cs_l)
771 return 1;
a03490ed
CO		 772 } else
773#endif
ff03a073 774 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 775 kvm_read_cr3(vcpu)))
0f12244f 776 return 1;
a03490ed
CO		 777 }
778
ad756a16
MJ		 779 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
780 return 1;
781
a03490ed 782 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 783
d170c419 784 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 785 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 786 kvm_async_pf_hash_reset(vcpu);
787 }
e5f3f027 788
aad82703
SY		 789 if ((cr0 ^ old_cr0) & update_bits)
790 kvm_mmu_reset_context(vcpu);
b18d5431 791
879ae188
LE		 792 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
793 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
794 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 795 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
796
0f12244f
GN		 797 return 0;
798}
2d3ad1f4 799EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 800
2d3ad1f4 801void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 802{
49a9b07e 803 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 804}
2d3ad1f4 805EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 806
1811d979 807void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 808{
809 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
810 !vcpu->guest_xcr0_loaded) {
811 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 812 if (vcpu->arch.xcr0 != host_xcr0)
813 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 814 vcpu->guest_xcr0_loaded = 1;
815 }
816}
1811d979 817EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
42bdf991 818
1811d979 819void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 820{
821 if (vcpu->guest_xcr0_loaded) {
822 if (vcpu->arch.xcr0 != host_xcr0)
823 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
824 vcpu->guest_xcr0_loaded = 0;
825 }
826}
1811d979 827EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
42bdf991 828
69b0049a 829static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 830{
56c103ec
LJ		 831 u64 xcr0 = xcr;
832 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 833 u64 valid_bits;
2acf923e
DC		 834
835 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
836 if (index != XCR_XFEATURE_ENABLED_MASK)
837 return 1;
d91cab78 838 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 839 return 1;
d91cab78 840 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 841 return 1;
46c34cb0
PB		 842
843 /*
844 * Do not allow the guest to set bits that we do not support
845 * saving. However, xcr0 bit 0 is always set, even if the
846 * emulated CPU does not support XSAVE (see fx_init).
847 */
d91cab78 848 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 849 if (xcr0 & ~valid_bits)
2acf923e 850 return 1;
46c34cb0 851
d91cab78
DH		 852 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
853 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 854 return 1;
855
d91cab78
DH		 856 if (xcr0 & XFEATURE_MASK_AVX512) {
857 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 858 return 1;
d91cab78 859 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 860 return 1;
861 }
2acf923e 862 vcpu->arch.xcr0 = xcr0;
56c103ec 863
d91cab78 864 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 865 kvm_update_cpuid(vcpu);
2acf923e
DC		 866 return 0;
867}
868
869int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
870{
764bcbc5
Z		 871 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
872 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 873 kvm_inject_gp(vcpu, 0);
874 return 1;
875 }
876 return 0;
877}
878EXPORT_SYMBOL_GPL(kvm_set_xcr);
879
a83b29c6 880int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 881{
fc78f519 882 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 883 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 884 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 885
0f12244f
GN		 886 if (cr4 & CR4_RESERVED_BITS)
887 return 1;
a03490ed 888
d6321d49 889 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 890 return 1;
891
d6321d49 892 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 893 return 1;
894
d6321d49 895 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 896 return 1;
897
d6321d49 898 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 899 return 1;
900
d6321d49 901 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 902 return 1;
903
fd8cb433 904 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 905 return 1;
906
ae3e61e1
PB		 907 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
908 return 1;
909
a03490ed 910 if (is_long_mode(vcpu)) {
0f12244f
GN		 911 if (!(cr4 & X86_CR4_PAE))
912 return 1;
a2edf57f
AK		 913 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
914 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 915 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
916 kvm_read_cr3(vcpu)))
0f12244f
GN		 917 return 1;
918
ad756a16 919 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 920 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 921 return 1;
922
923 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
924 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
925 return 1;
926 }
927
5e1746d6 928 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 929 return 1;
a03490ed 930
ad756a16
MJ		 931 if (((cr4 ^ old_cr4) & pdptr_bits) ||
932 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 933 kvm_mmu_reset_context(vcpu);
0f12244f 934
b9baba86 935 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 936 kvm_update_cpuid(vcpu);
2acf923e 937
0f12244f
GN		 938 return 0;
939}
2d3ad1f4 940EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 941
2390218b 942int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 943{
ade61e28 944 bool skip_tlb_flush = false;
ac146235 945#ifdef CONFIG_X86_64
c19986fe
JS		 946 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
947
ade61e28 948 if (pcid_enabled) {
208320ba
JS		 949 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
950 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 951 }
ac146235 952#endif
9d88fca7 953
9f8fe504 954 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 955 if (!skip_tlb_flush) {
956 kvm_mmu_sync_roots(vcpu);
ade61e28 957 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 958 }
0f12244f 959 return 0;
d835dfec
AK		 960 }
961
d1cd3ce9 962 if (is_long_mode(vcpu) &&
a780a3ea 963 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 964 return 1;
965 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 966 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 967 return 1;
a03490ed 968
ade61e28 969 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 970 vcpu->arch.cr3 = cr3;
aff48baa 971 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 972
0f12244f
GN		 973 return 0;
974}
2d3ad1f4 975EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 976
eea1cff9 977int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 978{
0f12244f
GN		 979 if (cr8 & CR8_RESERVED_BITS)
980 return 1;
35754c98 981 if (lapic_in_kernel(vcpu))
a03490ed
CO		 982 kvm_lapic_set_tpr(vcpu, cr8);
983 else
ad312c7c 984 vcpu->arch.cr8 = cr8;
0f12244f
GN		 985 return 0;
986}
2d3ad1f4 987EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 988
2d3ad1f4 989unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 990{
35754c98 991 if (lapic_in_kernel(vcpu))
a03490ed
CO		 992 return kvm_lapic_get_cr8(vcpu);
993 else
ad312c7c 994 return vcpu->arch.cr8;
a03490ed 995}
2d3ad1f4 996EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 997
ae561ede
NA		 998static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
999{
1000 int i;
1001
1002 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1003 for (i = 0; i < KVM_NR_DB_REGS; i++)
1004 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1005 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1006 }
1007}
1008
73aaf249
JK		 1009static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1010{
1011 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1012 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1013}
1014
c8639010
JK		 1015static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1016{
1017 unsigned long dr7;
1018
1019 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1020 dr7 = vcpu->arch.guest_debug_dr7;
1021 else
1022 dr7 = vcpu->arch.dr7;
1023 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1024 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1025 if (dr7 & DR7_BP_EN_MASK)
1026 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1027}
1028
6f43ed01
NA		 1029static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1030{
1031 u64 fixed = DR6_FIXED_1;
1032
d6321d49 1033 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1034 fixed |= DR6_RTM;
1035 return fixed;
1036}
1037
338dbc97 1038static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1039{
1040 switch (dr) {
1041 case 0 ... 3:
1042 vcpu->arch.db[dr] = val;
1043 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1044 vcpu->arch.eff_db[dr] = val;
1045 break;
1046 case 4:
020df079
GN		 1047 /* fall through */
1048 case 6:
338dbc97
GN		 1049 if (val & 0xffffffff00000000ULL)
1050 return -1; /* #GP */
6f43ed01 1051 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1052 kvm_update_dr6(vcpu);
020df079
GN		 1053 break;
1054 case 5:
020df079
GN		 1055 /* fall through */
1056 default: /* 7 */
338dbc97
GN		 1057 if (val & 0xffffffff00000000ULL)
1058 return -1; /* #GP */
020df079 1059 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1060 kvm_update_dr7(vcpu);
020df079
GN		 1061 break;
1062 }
1063
1064 return 0;
1065}
338dbc97
GN		 1066
1067int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1068{
16f8a6f9 1069 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1070 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1071 return 1;
1072 }
1073 return 0;
338dbc97 1074}
020df079
GN		 1075EXPORT_SYMBOL_GPL(kvm_set_dr);
1076
16f8a6f9 1077int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1078{
1079 switch (dr) {
1080 case 0 ... 3:
1081 *val = vcpu->arch.db[dr];
1082 break;
1083 case 4:
020df079
GN		 1084 /* fall through */
1085 case 6:
73aaf249
JK		 1086 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1087 *val = vcpu->arch.dr6;
1088 else
1089 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1090 break;
1091 case 5:
020df079
GN		 1092 /* fall through */
1093 default: /* 7 */
1094 *val = vcpu->arch.dr7;
1095 break;
1096 }
338dbc97
GN		 1097 return 0;
1098}
020df079
GN		 1099EXPORT_SYMBOL_GPL(kvm_get_dr);
1100
022cd0e8
AK		 1101bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1102{
de3cd117 1103 u32 ecx = kvm_rcx_read(vcpu);
022cd0e8
AK		 1104 u64 data;
1105 int err;
1106
c6702c9d 1107 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1108 if (err)
1109 return err;
de3cd117
SC		 1110 kvm_rax_write(vcpu, (u32)data);
1111 kvm_rdx_write(vcpu, data >> 32);
022cd0e8
AK		 1112 return err;
1113}
1114EXPORT_SYMBOL_GPL(kvm_rdpmc);
1115
043405e1
CO		 1116/*
1117 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1118 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1119 *
1120 * This list is modified at module load time to reflect the
e3267cbb 1121 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1122 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1123 * may depend on host virtualization features rather than host cpu features.
043405e1 1124 */
e3267cbb 1125
043405e1
CO		 1126static u32 msrs_to_save[] = {
1127 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1128 MSR_STAR,
043405e1
CO		 1129#ifdef CONFIG_X86_64
1130 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1131#endif
b3897a49 1132 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1133 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1134 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1135 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1136 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1137 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1138 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1139 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1140 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
043405e1
CO		 1141};
1142
1143static unsigned num_msrs_to_save;
1144
62ef68bb
PB		 1145static u32 emulated_msrs[] = {
1146 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1147 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1148 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1149 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1150 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1151 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1152 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1153 HV_X64_MSR_RESET,
11c4b1ca 1154 HV_X64_MSR_VP_INDEX,
9eec50b8 1155 HV_X64_MSR_VP_RUNTIME,
5c919412 1156 HV_X64_MSR_SCONTROL,
1f4b34f8 1157 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1158 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1159 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1160 HV_X64_MSR_TSC_EMULATION_STATUS,
1161
1162 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1163 MSR_KVM_PV_EOI_EN,
1164
ba904635 1165 MSR_IA32_TSC_ADJUST,
a3e06bbe 1166 MSR_IA32_TSCDEADLINE,
2bdb76c0 1167 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1168 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1169 MSR_IA32_MCG_STATUS,
1170 MSR_IA32_MCG_CTL,
c45dcc71 1171 MSR_IA32_MCG_EXT_CTL,
64d60670 1172 MSR_IA32_SMBASE,
52797bf9 1173 MSR_SMI_COUNT,
db2336a8
KH		 1174 MSR_PLATFORM_INFO,
1175 MSR_MISC_FEATURES_ENABLES,
bc226f07 1176 MSR_AMD64_VIRT_SPEC_CTRL,
6c6a2ab9 1177 MSR_IA32_POWER_CTL,
191c8137
BP		 1178
1179 MSR_K7_HWCR,
043405e1
CO		 1180};
1181
62ef68bb
PB		 1182static unsigned num_emulated_msrs;
1183
801e459a
TL		 1184/*
1185 * List of msr numbers which are used to expose MSR-based features that
1186 * can be used by a hypervisor to validate requested CPU features.
1187 */
1188static u32 msr_based_features[] = {
1389309c
PB		 1189 MSR_IA32_VMX_BASIC,
1190 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1191 MSR_IA32_VMX_PINBASED_CTLS,
1192 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1193 MSR_IA32_VMX_PROCBASED_CTLS,
1194 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1195 MSR_IA32_VMX_EXIT_CTLS,
1196 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1197 MSR_IA32_VMX_ENTRY_CTLS,
1198 MSR_IA32_VMX_MISC,
1199 MSR_IA32_VMX_CR0_FIXED0,
1200 MSR_IA32_VMX_CR0_FIXED1,
1201 MSR_IA32_VMX_CR4_FIXED0,
1202 MSR_IA32_VMX_CR4_FIXED1,
1203 MSR_IA32_VMX_VMCS_ENUM,
1204 MSR_IA32_VMX_PROCBASED_CTLS2,
1205 MSR_IA32_VMX_EPT_VPID_CAP,
1206 MSR_IA32_VMX_VMFUNC,
1207
d1d93fa9 1208 MSR_F10H_DECFG,
518e7b94 1209 MSR_IA32_UCODE_REV,
cd283252 1210 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1211};
1212
1213static unsigned int num_msr_based_features;
1214
4d22c17c 1215static u64 kvm_get_arch_capabilities(void)
5b76a3cf 1216{
4d22c17c 1217 u64 data = 0;
5b76a3cf 1218
4d22c17c
XL		 1219 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1220 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
5b76a3cf
PB		 1221
1222 /*
1223 * If we're doing cache flushes (either "always" or "cond")
1224 * we will do one whenever the guest does a vmlaunch/vmresume.
1225 * If an outer hypervisor is doing the cache flush for us
1226 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1227 * capability to the guest too, and if EPT is disabled we're not
1228 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1229 * require a nested hypervisor to do a flush of its own.
1230 */
1231 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1232 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1233
1234 return data;
1235}
5b76a3cf 1236
66421c1e
WL		 1237static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1238{
1239 switch (msr->index) {
cd283252 1240 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1241 msr->data = kvm_get_arch_capabilities();
1242 break;
1243 case MSR_IA32_UCODE_REV:
cd283252 1244 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1245 break;
66421c1e
WL		 1246 default:
1247 if (kvm_x86_ops->get_msr_feature(msr))
1248 return 1;
1249 }
1250 return 0;
1251}
1252
801e459a
TL		 1253static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1254{
1255 struct kvm_msr_entry msr;
66421c1e 1256 int r;
801e459a
TL		 1257
1258 msr.index = index;
66421c1e
WL		 1259 r = kvm_get_msr_feature(&msr);
1260 if (r)
1261 return r;
801e459a
TL		 1262
1263 *data = msr.data;
1264
1265 return 0;
1266}
1267
11988499 1268static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1269{
1b4d56b8 1270 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
11988499 1271 return false;
1b2fd70c 1272
1b4d56b8 1273 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
11988499 1274 return false;
d8017474 1275
0a629563
SC		 1276 if (efer & (EFER_LME | EFER_LMA) &&
1277 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1278 return false;
1279
1280 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1281 return false;
d8017474 1282
384bb783 1283 return true;
11988499
SC		 1284
1285}
1286bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1287{
1288 if (efer & efer_reserved_bits)
1289 return false;
1290
1291 return __kvm_valid_efer(vcpu, efer);
384bb783
JK		 1292}
1293EXPORT_SYMBOL_GPL(kvm_valid_efer);
1294
11988499 1295static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
384bb783
JK		 1296{
1297 u64 old_efer = vcpu->arch.efer;
11988499 1298 u64 efer = msr_info->data;
384bb783 1299
11988499 1300 if (efer & efer_reserved_bits)
66f61c92 1301 return 1;
384bb783 1302
11988499
SC		 1303 if (!msr_info->host_initiated) {
1304 if (!__kvm_valid_efer(vcpu, efer))
1305 return 1;
1306
1307 if (is_paging(vcpu) &&
1308 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1309 return 1;
1310 }
384bb783 1311
15c4a640 1312 efer &= ~EFER_LMA;
f6801dff 1313 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1314
a3d204e2
SY		 1315 kvm_x86_ops->set_efer(vcpu, efer);
1316
aad82703
SY		 1317 /* Update reserved bits */
1318 if ((efer ^ old_efer) & EFER_NX)
1319 kvm_mmu_reset_context(vcpu);
1320
b69e8cae 1321 return 0;
15c4a640
CO		 1322}
1323
f2b4b7dd
JR		 1324void kvm_enable_efer_bits(u64 mask)
1325{
1326 efer_reserved_bits &= ~mask;
1327}
1328EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1329
15c4a640
CO		 1330/*
1331 * Writes msr value into into the appropriate "register".
1332 * Returns 0 on success, non-0 otherwise.
1333 * Assumes vcpu_load() was already called.
1334 */
8fe8ab46 1335int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1336{
854e8bb1
NA		 1337 switch (msr->index) {
1338 case MSR_FS_BASE:
1339 case MSR_GS_BASE:
1340 case MSR_KERNEL_GS_BASE:
1341 case MSR_CSTAR:
1342 case MSR_LSTAR:
fd8cb433 1343 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1344 return 1;
1345 break;
1346 case MSR_IA32_SYSENTER_EIP:
1347 case MSR_IA32_SYSENTER_ESP:
1348 /*
1349 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1350 * non-canonical address is written on Intel but not on
1351 * AMD (which ignores the top 32-bits, because it does
1352 * not implement 64-bit SYSENTER).
1353 *
1354 * 64-bit code should hence be able to write a non-canonical
1355 * value on AMD. Making the address canonical ensures that
1356 * vmentry does not fail on Intel after writing a non-canonical
1357 * value, and that something deterministic happens if the guest
1358 * invokes 64-bit SYSENTER.
1359 */
fd8cb433 1360 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1361 }
8fe8ab46 1362 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1363}
854e8bb1 1364EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1365
313a3dc7
CO		 1366/*
1367 * Adapt set_msr() to msr_io()'s calling convention
1368 */
609e36d3
PB		 1369static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1370{
1371 struct msr_data msr;
1372 int r;
1373
1374 msr.index = index;
1375 msr.host_initiated = true;
1376 r = kvm_get_msr(vcpu, &msr);
1377 if (r)
1378 return r;
1379
1380 *data = msr.data;
1381 return 0;
1382}
1383
313a3dc7
CO		 1384static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1385{
8fe8ab46
WA		 1386 struct msr_data msr;
1387
1388 msr.data = *data;
1389 msr.index = index;
1390 msr.host_initiated = true;
1391 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1392}
1393
16e8d74d
MT		 1394#ifdef CONFIG_X86_64
1395struct pvclock_gtod_data {
1396 seqcount_t seq;
1397
1398 struct { /* extract of a clocksource struct */
1399 int vclock_mode;
a5a1d1c2
TG		 1400 u64 cycle_last;
1401 u64 mask;
16e8d74d
MT		 1402 u32 mult;
1403 u32 shift;
1404 } clock;
1405
cbcf2dd3
TG		 1406 u64 boot_ns;
1407 u64 nsec_base;
55dd00a7 1408 u64 wall_time_sec;
16e8d74d
MT		 1409};
1410
1411static struct pvclock_gtod_data pvclock_gtod_data;
1412
1413static void update_pvclock_gtod(struct timekeeper *tk)
1414{
1415 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1416 u64 boot_ns;
1417
876e7881 1418 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1419
1420 write_seqcount_begin(&vdata->seq);
1421
1422 /* copy pvclock gtod data */
876e7881
PZ		 1423 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1424 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1425 vdata->clock.mask = tk->tkr_mono.mask;
1426 vdata->clock.mult = tk->tkr_mono.mult;
1427 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1428
cbcf2dd3 1429 vdata->boot_ns = boot_ns;
876e7881 1430 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1431
55dd00a7
MT		 1432 vdata->wall_time_sec = tk->xtime_sec;
1433
16e8d74d
MT		 1434 write_seqcount_end(&vdata->seq);
1435}
1436#endif
1437
bab5bb39
NK		 1438void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1439{
1440 /*
1441 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1442 * vcpu_enter_guest. This function is only called from
1443 * the physical CPU that is running vcpu.
1444 */
1445 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1446}
16e8d74d 1447
18068523
GOC		 1448static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1449{
9ed3c444
AK		 1450 int version;
1451 int r;
50d0a0f9 1452 struct pvclock_wall_clock wc;
87aeb54f 1453 struct timespec64 boot;
18068523
GOC		 1454
1455 if (!wall_clock)
1456 return;
1457
9ed3c444
AK		 1458 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1459 if (r)
1460 return;
1461
1462 if (version & 1)
1463 ++version; /* first time write, random junk */
1464
1465 ++version;
18068523 1466
1dab1345
NK		 1467 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1468 return;
18068523 1469
50d0a0f9
GH		 1470 /*
1471 * The guest calculates current wall clock time by adding
34c238a1 1472 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1473 * wall clock specified here. guest system time equals host
1474 * system time for us, thus we must fill in host boot time here.
1475 */
87aeb54f 1476 getboottime64(&boot);
50d0a0f9 1477
4b648665 1478 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1479 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1480 boot = timespec64_sub(boot, ts);
4b648665 1481 }
87aeb54f 1482 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1483 wc.nsec = boot.tv_nsec;
1484 wc.version = version;
18068523
GOC		 1485
1486 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1487
1488 version++;
1489 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1490}
1491
50d0a0f9
GH		 1492static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1493{
b51012de
PB		 1494 do_shl32_div32(dividend, divisor);
1495 return dividend;
50d0a0f9
GH		 1496}
1497
3ae13faa 1498static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1499 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1500{
5f4e3f88 1501 uint64_t scaled64;
50d0a0f9
GH		 1502 int32_t shift = 0;
1503 uint64_t tps64;
1504 uint32_t tps32;
1505
3ae13faa
PB		 1506 tps64 = base_hz;
1507 scaled64 = scaled_hz;
50933623 1508 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1509 tps64 >>= 1;
1510 shift--;
1511 }
1512
1513 tps32 = (uint32_t)tps64;
50933623
JK		 1514 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1515 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1516 scaled64 >>= 1;
1517 else
1518 tps32 <<= 1;
50d0a0f9
GH		 1519 shift++;
1520 }
1521
5f4e3f88
ZA		 1522 *pshift = shift;
1523 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1524
3ae13faa
PB		 1525 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1526 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1527}
1528
d828199e 1529#ifdef CONFIG_X86_64
16e8d74d 1530static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1531#endif
16e8d74d 1532
c8076604 1533static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1534static unsigned long max_tsc_khz;
c8076604 1535
cc578287 1536static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1537{
cc578287
ZA		 1538 u64 v = (u64)khz * (1000000 + ppm);
1539 do_div(v, 1000000);
1540 return v;
1e993611
JR		 1541}
1542
381d585c
HZ		 1543static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1544{
1545 u64 ratio;
1546
1547 /* Guest TSC same frequency as host TSC? */
1548 if (!scale) {
1549 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1550 return 0;
1551 }
1552
1553 /* TSC scaling supported? */
1554 if (!kvm_has_tsc_control) {
1555 if (user_tsc_khz > tsc_khz) {
1556 vcpu->arch.tsc_catchup = 1;
1557 vcpu->arch.tsc_always_catchup = 1;
1558 return 0;
1559 } else {
1560 WARN(1, "user requested TSC rate below hardware speed\n");
1561 return -1;
1562 }
1563 }
1564
1565 /* TSC scaling required - calculate ratio */
1566 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1567 user_tsc_khz, tsc_khz);
1568
1569 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1570 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1571 user_tsc_khz);
1572 return -1;
1573 }
1574
1575 vcpu->arch.tsc_scaling_ratio = ratio;
1576 return 0;
1577}
1578
4941b8cb 1579static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1580{
cc578287
ZA		 1581 u32 thresh_lo, thresh_hi;
1582 int use_scaling = 0;
217fc9cf 1583
03ba32ca 1584 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1585 if (user_tsc_khz == 0) {
ad721883
HZ		 1586 /* set tsc_scaling_ratio to a safe value */
1587 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1588 return -1;
ad721883 1589 }
03ba32ca 1590
c285545f 1591 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1592 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1593 &vcpu->arch.virtual_tsc_shift,
1594 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1595 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1596
1597 /*
1598 * Compute the variation in TSC rate which is acceptable
1599 * within the range of tolerance and decide if the
1600 * rate being applied is within that bounds of the hardware
1601 * rate. If so, no scaling or compensation need be done.
1602 */
1603 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1604 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1605 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1606 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1607 use_scaling = 1;
1608 }
4941b8cb 1609 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1610}
1611
1612static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1613{
e26101b1 1614 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1615 vcpu->arch.virtual_tsc_mult,
1616 vcpu->arch.virtual_tsc_shift);
e26101b1 1617 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1618 return tsc;
1619}
1620
b0c39dc6
VK		 1621static inline int gtod_is_based_on_tsc(int mode)
1622{
1623 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1624}
1625
69b0049a 1626static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1627{
1628#ifdef CONFIG_X86_64
1629 bool vcpus_matched;
b48aa97e
MT		 1630 struct kvm_arch *ka = &vcpu->kvm->arch;
1631 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1632
1633 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1634 atomic_read(&vcpu->kvm->online_vcpus));
1635
7f187922
MT		 1636 /*
1637 * Once the masterclock is enabled, always perform request in
1638 * order to update it.
1639 *
1640 * In order to enable masterclock, the host clocksource must be TSC
1641 * and the vcpus need to have matched TSCs. When that happens,
1642 * perform request to enable masterclock.
1643 */
1644 if (ka->use_master_clock ||
b0c39dc6 1645 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1646 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1647
1648 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1649 atomic_read(&vcpu->kvm->online_vcpus),
1650 ka->use_master_clock, gtod->clock.vclock_mode);
1651#endif
1652}
1653
ba904635
WA		 1654static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1655{
e79f245d 1656 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1657 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1658}
1659
35181e86
HZ		 1660/*
1661 * Multiply tsc by a fixed point number represented by ratio.
1662 *
1663 * The most significant 64-N bits (mult) of ratio represent the
1664 * integral part of the fixed point number; the remaining N bits
1665 * (frac) represent the fractional part, ie. ratio represents a fixed
1666 * point number (mult + frac * 2^(-N)).
1667 *
1668 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1669 */
1670static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1671{
1672 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1673}
1674
1675u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1676{
1677 u64 _tsc = tsc;
1678 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1679
1680 if (ratio != kvm_default_tsc_scaling_ratio)
1681 _tsc = __scale_tsc(ratio, tsc);
1682
1683 return _tsc;
1684}
1685EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1686
07c1419a
HZ		 1687static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1688{
1689 u64 tsc;
1690
1691 tsc = kvm_scale_tsc(vcpu, rdtsc());
1692
1693 return target_tsc - tsc;
1694}
1695
4ba76538
HZ		 1696u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1697{
e79f245d
KA		 1698 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1699
1700 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1701}
1702EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1703
a545ab6a
LC		 1704static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1705{
326e7425 1706 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1707}
1708
b0c39dc6
VK		 1709static inline bool kvm_check_tsc_unstable(void)
1710{
1711#ifdef CONFIG_X86_64
1712 /*
1713 * TSC is marked unstable when we're running on Hyper-V,
1714 * 'TSC page' clocksource is good.
1715 */
1716 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1717 return false;
1718#endif
1719 return check_tsc_unstable();
1720}
1721
8fe8ab46 1722void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1723{
1724 struct kvm *kvm = vcpu->kvm;
f38e098f 1725 u64 offset, ns, elapsed;
99e3e30a 1726 unsigned long flags;
b48aa97e 1727 bool matched;
0d3da0d2 1728 bool already_matched;
8fe8ab46 1729 u64 data = msr->data;
c5e8ec8e 1730 bool synchronizing = false;
99e3e30a 1731
038f8c11 1732 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1733 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1734 ns = ktime_get_boot_ns();
f38e098f 1735 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1736
03ba32ca 1737 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1738 if (data == 0 && msr->host_initiated) {
1739 /*
1740 * detection of vcpu initialization -- need to sync
1741 * with other vCPUs. This particularly helps to keep
1742 * kvm_clock stable after CPU hotplug
1743 */
1744 synchronizing = true;
1745 } else {
1746 u64 tsc_exp = kvm->arch.last_tsc_write +
1747 nsec_to_cycles(vcpu, elapsed);
1748 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1749 /*
1750 * Special case: TSC write with a small delta (1 second)
1751 * of virtual cycle time against real time is
1752 * interpreted as an attempt to synchronize the CPU.
1753 */
1754 synchronizing = data < tsc_exp + tsc_hz &&
1755 data + tsc_hz > tsc_exp;
1756 }
c5e8ec8e 1757 }
f38e098f
ZA		 1758
1759 /*
5d3cb0f6
ZA		 1760 * For a reliable TSC, we can match TSC offsets, and for an unstable
1761 * TSC, we add elapsed time in this computation. We could let the
1762 * compensation code attempt to catch up if we fall behind, but
1763 * it's better to try to match offsets from the beginning.
1764 */
c5e8ec8e 1765 if (synchronizing &&
5d3cb0f6 1766 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1767 if (!kvm_check_tsc_unstable()) {
e26101b1 1768 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1769 pr_debug("kvm: matched tsc offset for %llu\n", data);
1770 } else {
857e4099 1771 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1772 data += delta;
07c1419a 1773 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1774 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1775 }
b48aa97e 1776 matched = true;
0d3da0d2 1777 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1778 } else {
1779 /*
1780 * We split periods of matched TSC writes into generations.
1781 * For each generation, we track the original measured
1782 * nanosecond time, offset, and write, so if TSCs are in
1783 * sync, we can match exact offset, and if not, we can match
4a969980 1784 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1785 *
1786 * These values are tracked in kvm->arch.cur_xxx variables.
1787 */
1788 kvm->arch.cur_tsc_generation++;
1789 kvm->arch.cur_tsc_nsec = ns;
1790 kvm->arch.cur_tsc_write = data;
1791 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1792 matched = false;
0d3da0d2 1793 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1794 kvm->arch.cur_tsc_generation, data);
f38e098f 1795 }
e26101b1
ZA		 1796
1797 /*
1798 * We also track th most recent recorded KHZ, write and time to
1799 * allow the matching interval to be extended at each write.
1800 */
f38e098f
ZA		 1801 kvm->arch.last_tsc_nsec = ns;
1802 kvm->arch.last_tsc_write = data;
5d3cb0f6 1803 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1804
b183aa58 1805 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1806
1807 /* Keep track of which generation this VCPU has synchronized to */
1808 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1809 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1810 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1811
d6321d49 1812 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1813 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1814
a545ab6a 1815 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1816 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1817
1818 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1819 if (!matched) {
b48aa97e 1820 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1821 } else if (!already_matched) {
1822 kvm->arch.nr_vcpus_matched_tsc++;
1823 }
b48aa97e
MT		 1824
1825 kvm_track_tsc_matching(vcpu);
1826 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1827}
e26101b1 1828
99e3e30a
ZA		 1829EXPORT_SYMBOL_GPL(kvm_write_tsc);
1830
58ea6767
HZ		 1831static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1832 s64 adjustment)
1833{
326e7425
LS		 1834 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1835 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1836}
1837
1838static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1839{
1840 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1841 WARN_ON(adjustment < 0);
1842 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1843 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1844}
1845
d828199e
MT		 1846#ifdef CONFIG_X86_64
1847
a5a1d1c2 1848static u64 read_tsc(void)
d828199e 1849{
a5a1d1c2 1850 u64 ret = (u64)rdtsc_ordered();
03b9730b 1851 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1852
1853 if (likely(ret >= last))
1854 return ret;
1855
1856 /*
1857 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1858 * predictable (it's just a function of time and the likely is
d828199e
MT		 1859 * very likely) and there's a data dependence, so force GCC
1860 * to generate a branch instead. I don't barrier() because
1861 * we don't actually need a barrier, and if this function
1862 * ever gets inlined it will generate worse code.
1863 */
1864 asm volatile ("");
1865 return last;
1866}
1867
b0c39dc6 1868static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1869{
1870 long v;
1871 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1872 u64 tsc_pg_val;
1873
1874 switch (gtod->clock.vclock_mode) {
1875 case VCLOCK_HVCLOCK:
1876 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1877 tsc_timestamp);
1878 if (tsc_pg_val != U64_MAX) {
1879 /* TSC page valid */
1880 *mode = VCLOCK_HVCLOCK;
1881 v = (tsc_pg_val - gtod->clock.cycle_last) &
1882 gtod->clock.mask;
1883 } else {
1884 /* TSC page invalid */
1885 *mode = VCLOCK_NONE;
1886 }
1887 break;
1888 case VCLOCK_TSC:
1889 *mode = VCLOCK_TSC;
1890 *tsc_timestamp = read_tsc();
1891 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1892 gtod->clock.mask;
1893 break;
1894 default:
1895 *mode = VCLOCK_NONE;
1896 }
d828199e 1897
b0c39dc6
VK		 1898 if (*mode == VCLOCK_NONE)
1899 *tsc_timestamp = v = 0;
d828199e 1900
d828199e
MT		 1901 return v * gtod->clock.mult;
1902}
1903
b0c39dc6 1904static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1905{
cbcf2dd3 1906 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1907 unsigned long seq;
d828199e 1908 int mode;
cbcf2dd3 1909 u64 ns;
d828199e 1910
d828199e
MT		 1911 do {
1912 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1913 ns = gtod->nsec_base;
b0c39dc6 1914 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1915 ns >>= gtod->clock.shift;
cbcf2dd3 1916 ns += gtod->boot_ns;
d828199e 1917 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1918 *t = ns;
d828199e
MT		 1919
1920 return mode;
1921}
1922
899a31f5 1923static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1924{
1925 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1926 unsigned long seq;
1927 int mode;
1928 u64 ns;
1929
1930 do {
1931 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1932 ts->tv_sec = gtod->wall_time_sec;
1933 ns = gtod->nsec_base;
b0c39dc6 1934 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1935 ns >>= gtod->clock.shift;
1936 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1937
1938 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1939 ts->tv_nsec = ns;
1940
1941 return mode;
1942}
1943
b0c39dc6
VK		 1944/* returns true if host is using TSC based clocksource */
1945static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1946{
d828199e 1947 /* checked again under seqlock below */
b0c39dc6 1948 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1949 return false;
1950
b0c39dc6
VK		 1951 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1952 tsc_timestamp));
d828199e 1953}
55dd00a7 1954
b0c39dc6 1955/* returns true if host is using TSC based clocksource */
899a31f5 1956static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1957 u64 *tsc_timestamp)
55dd00a7
MT		 1958{
1959 /* checked again under seqlock below */
b0c39dc6 1960 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1961 return false;
1962
b0c39dc6 1963 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1964}
d828199e
MT		 1965#endif
1966
1967/*
1968 *
b48aa97e
MT		 1969 * Assuming a stable TSC across physical CPUS, and a stable TSC
1970 * across virtual CPUs, the following condition is possible.
1971 * Each numbered line represents an event visible to both
d828199e
MT		 1972 * CPUs at the next numbered event.
1973 *
1974 * "timespecX" represents host monotonic time. "tscX" represents
1975 * RDTSC value.
1976 *
1977 * VCPU0 on CPU0 | VCPU1 on CPU1
1978 *
1979 * 1. read timespec0,tsc0
1980 * 2. | timespec1 = timespec0 + N
1981 * | tsc1 = tsc0 + M
1982 * 3. transition to guest | transition to guest
1983 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1984 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1985 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1986 *
1987 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1988 *
1989 * - ret0 < ret1
1990 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1991 * ...
1992 * - 0 < N - M => M < N
1993 *
1994 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1995 * always the case (the difference between two distinct xtime instances
1996 * might be smaller then the difference between corresponding TSC reads,
1997 * when updating guest vcpus pvclock areas).
1998 *
1999 * To avoid that problem, do not allow visibility of distinct
2000 * system_timestamp/tsc_timestamp values simultaneously: use a master
2001 * copy of host monotonic time values. Update that master copy
2002 * in lockstep.
2003 *
b48aa97e 2004 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 2005 *
2006 */
2007
2008static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2009{
2010#ifdef CONFIG_X86_64
2011 struct kvm_arch *ka = &kvm->arch;
2012 int vclock_mode;
b48aa97e
MT		 2013 bool host_tsc_clocksource, vcpus_matched;
2014
2015 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2016 atomic_read(&kvm->online_vcpus));
d828199e
MT		 2017
2018 /*
2019 * If the host uses TSC clock, then passthrough TSC as stable
2020 * to the guest.
2021 */
b48aa97e 2022 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 2023 &ka->master_kernel_ns,
2024 &ka->master_cycle_now);
2025
16a96021 2026 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2027 && !ka->backwards_tsc_observed
54750f2c 2028 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2029
d828199e
MT		 2030 if (ka->use_master_clock)
2031 atomic_set(&kvm_guest_has_master_clock, 1);
2032
2033 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2034 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2035 vcpus_matched);
d828199e
MT		 2036#endif
2037}
2038
2860c4b1
PB		 2039void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2040{
2041 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2042}
2043
2e762ff7
MT		 2044static void kvm_gen_update_masterclock(struct kvm *kvm)
2045{
2046#ifdef CONFIG_X86_64
2047 int i;
2048 struct kvm_vcpu *vcpu;
2049 struct kvm_arch *ka = &kvm->arch;
2050
2051 spin_lock(&ka->pvclock_gtod_sync_lock);
2052 kvm_make_mclock_inprogress_request(kvm);
2053 /* no guest entries from this point */
2054 pvclock_update_vm_gtod_copy(kvm);
2055
2056 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2057 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2058
2059 /* guest entries allowed */
2060 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2061 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2062
2063 spin_unlock(&ka->pvclock_gtod_sync_lock);
2064#endif
2065}
2066
e891a32e 2067u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2068{
108b249c 2069 struct kvm_arch *ka = &kvm->arch;
8b953440 2070 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2071 u64 ret;
108b249c 2072
8b953440
PB		 2073 spin_lock(&ka->pvclock_gtod_sync_lock);
2074 if (!ka->use_master_clock) {
2075 spin_unlock(&ka->pvclock_gtod_sync_lock);
2076 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 2077 }
2078
8b953440
PB		 2079 hv_clock.tsc_timestamp = ka->master_cycle_now;
2080 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2081 spin_unlock(&ka->pvclock_gtod_sync_lock);
2082
e2c2206a
WL		 2083 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2084 get_cpu();
2085
e70b57a6
WL		 2086 if (__this_cpu_read(cpu_tsc_khz)) {
2087 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2088 &hv_clock.tsc_shift,
2089 &hv_clock.tsc_to_system_mul);
2090 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2091 } else
2092 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2093
2094 put_cpu();
2095
2096 return ret;
108b249c
PB		 2097}
2098
0d6dd2ff
PB		 2099static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2100{
2101 struct kvm_vcpu_arch *vcpu = &v->arch;
2102 struct pvclock_vcpu_time_info guest_hv_clock;
2103
4e335d9e 2104 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2105 &guest_hv_clock, sizeof(guest_hv_clock))))
2106 return;
2107
2108 /* This VCPU is paused, but it's legal for a guest to read another
2109 * VCPU's kvmclock, so we really have to follow the specification where
2110 * it says that version is odd if data is being modified, and even after
2111 * it is consistent.
2112 *
2113 * Version field updates must be kept separate. This is because
2114 * kvm_write_guest_cached might use a "rep movs" instruction, and
2115 * writes within a string instruction are weakly ordered. So there
2116 * are three writes overall.
2117 *
2118 * As a small optimization, only write the version field in the first
2119 * and third write. The vcpu->pv_time cache is still valid, because the
2120 * version field is the first in the struct.
2121 */
2122 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2123
51c4b8bb
LA		 2124 if (guest_hv_clock.version & 1)
2125 ++guest_hv_clock.version; /* first time write, random junk */
2126
0d6dd2ff 2127 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2128 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2129 &vcpu->hv_clock,
2130 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2131
2132 smp_wmb();
2133
2134 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2135 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2136
2137 if (vcpu->pvclock_set_guest_stopped_request) {
2138 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2139 vcpu->pvclock_set_guest_stopped_request = false;
2140 }
2141
2142 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2143
4e335d9e
PB		 2144 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2145 &vcpu->hv_clock,
2146 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2147
2148 smp_wmb();
2149
2150 vcpu->hv_clock.version++;
4e335d9e
PB		 2151 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2152 &vcpu->hv_clock,
2153 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2154}
2155
34c238a1 2156static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2157{
78db6a50 2158 unsigned long flags, tgt_tsc_khz;
18068523 2159 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2160 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2161 s64 kernel_ns;
d828199e 2162 u64 tsc_timestamp, host_tsc;
51d59c6b 2163 u8 pvclock_flags;
d828199e
MT		 2164 bool use_master_clock;
2165
2166 kernel_ns = 0;
2167 host_tsc = 0;
18068523 2168
d828199e
MT		 2169 /*
2170 * If the host uses TSC clock, then passthrough TSC as stable
2171 * to the guest.
2172 */
2173 spin_lock(&ka->pvclock_gtod_sync_lock);
2174 use_master_clock = ka->use_master_clock;
2175 if (use_master_clock) {
2176 host_tsc = ka->master_cycle_now;
2177 kernel_ns = ka->master_kernel_ns;
2178 }
2179 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2180
2181 /* Keep irq disabled to prevent changes to the clock */
2182 local_irq_save(flags);
78db6a50
PB		 2183 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2184 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2185 local_irq_restore(flags);
2186 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2187 return 1;
2188 }
d828199e 2189 if (!use_master_clock) {
4ea1636b 2190 host_tsc = rdtsc();
108b249c 2191 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2192 }
2193
4ba76538 2194 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2195
c285545f
ZA		 2196 /*
2197 * We may have to catch up the TSC to match elapsed wall clock
2198 * time for two reasons, even if kvmclock is used.
2199 * 1) CPU could have been running below the maximum TSC rate
2200 * 2) Broken TSC compensation resets the base at each VCPU
2201 * entry to avoid unknown leaps of TSC even when running
2202 * again on the same CPU. This may cause apparent elapsed
2203 * time to disappear, and the guest to stand still or run
2204 * very slowly.
2205 */
2206 if (vcpu->tsc_catchup) {
2207 u64 tsc = compute_guest_tsc(v, kernel_ns);
2208 if (tsc > tsc_timestamp) {
f1e2b260 2209 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2210 tsc_timestamp = tsc;
2211 }
50d0a0f9
GH		 2212 }
2213
18068523
GOC		 2214 local_irq_restore(flags);
2215
0d6dd2ff 2216 /* With all the info we got, fill in the values */
18068523 2217
78db6a50
PB		 2218 if (kvm_has_tsc_control)
2219 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2220
2221 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2222 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2223 &vcpu->hv_clock.tsc_shift,
2224 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2225 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2226 }
2227
1d5f066e 2228 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2229 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2230 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2231
d828199e 2232 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2233 pvclock_flags = 0;
d828199e
MT		 2234 if (use_master_clock)
2235 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2236
78c0337a
MT		 2237 vcpu->hv_clock.flags = pvclock_flags;
2238
095cf55d
PB		 2239 if (vcpu->pv_time_enabled)
2240 kvm_setup_pvclock_page(v);
2241 if (v == kvm_get_vcpu(v->kvm, 0))
2242 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2243 return 0;
c8076604
GH		 2244}
2245
0061d53d
MT		 2246/*
2247 * kvmclock updates which are isolated to a given vcpu, such as
2248 * vcpu->cpu migration, should not allow system_timestamp from
2249 * the rest of the vcpus to remain static. Otherwise ntp frequency
2250 * correction applies to one vcpu's system_timestamp but not
2251 * the others.
2252 *
2253 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2254 * We need to rate-limit these requests though, as they can
2255 * considerably slow guests that have a large number of vcpus.
2256 * The time for a remote vcpu to update its kvmclock is bound
2257 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2258 */
2259
7e44e449
AJ		 2260#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2261
2262static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2263{
2264 int i;
7e44e449
AJ		 2265 struct delayed_work *dwork = to_delayed_work(work);
2266 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2267 kvmclock_update_work);
2268 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2269 struct kvm_vcpu *vcpu;
2270
2271 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2272 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2273 kvm_vcpu_kick(vcpu);
2274 }
2275}
2276
7e44e449
AJ		 2277static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2278{
2279 struct kvm *kvm = v->kvm;
2280
105b21bb 2281 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2282 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2283 KVMCLOCK_UPDATE_DELAY);
2284}
2285
332967a3
AJ		 2286#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2287
2288static void kvmclock_sync_fn(struct work_struct *work)
2289{
2290 struct delayed_work *dwork = to_delayed_work(work);
2291 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2292 kvmclock_sync_work);
2293 struct kvm *kvm = container_of(ka, struct kvm, arch);
2294
630994b3
MT		 2295 if (!kvmclock_periodic_sync)
2296 return;
2297
332967a3
AJ		 2298 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2299 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2300 KVMCLOCK_SYNC_PERIOD);
2301}
2302
191c8137
BP		 2303/*
2304 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2305 */
2306static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2307{
2308 /* McStatusWrEn enabled? */
2309 if (guest_cpuid_is_amd(vcpu))
2310 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2311
2312 return false;
2313}
2314
9ffd986c 2315static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2316{
890ca9ae
HY		 2317 u64 mcg_cap = vcpu->arch.mcg_cap;
2318 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2319 u32 msr = msr_info->index;
2320 u64 data = msr_info->data;
890ca9ae 2321
15c4a640 2322 switch (msr) {
15c4a640 2323 case MSR_IA32_MCG_STATUS:
890ca9ae 2324 vcpu->arch.mcg_status = data;
15c4a640 2325 break;
c7ac679c 2326 case MSR_IA32_MCG_CTL:
44883f01
PB		 2327 if (!(mcg_cap & MCG_CTL_P) &&
2328 (data || !msr_info->host_initiated))
890ca9ae
HY		 2329 return 1;
2330 if (data != 0 && data != ~(u64)0)
44883f01 2331 return 1;
890ca9ae
HY		 2332 vcpu->arch.mcg_ctl = data;
2333 break;
2334 default:
2335 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2336 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2337 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2338 /* only 0 or all 1s can be written to IA32_MCi_CTL
2339 * some Linux kernels though clear bit 10 in bank 4 to
2340 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2341 * this to avoid an uncatched #GP in the guest
2342 */
890ca9ae 2343 if ((offset & 0x3) == 0 &&
114be429 2344 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2345 return -1;
191c8137
BP		 2346
2347 /* MCi_STATUS */
9ffd986c 2348 if (!msr_info->host_initiated &&
191c8137
BP		 2349 (offset & 0x3) == 1 && data != 0) {
2350 if (!can_set_mci_status(vcpu))
2351 return -1;
2352 }
2353
890ca9ae
HY		 2354 vcpu->arch.mce_banks[offset] = data;
2355 break;
2356 }
2357 return 1;
2358 }
2359 return 0;
2360}
2361
ffde22ac
ES		 2362static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2363{
2364 struct kvm *kvm = vcpu->kvm;
2365 int lm = is_long_mode(vcpu);
2366 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2367 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2368 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2369 : kvm->arch.xen_hvm_config.blob_size_32;
2370 u32 page_num = data & ~PAGE_MASK;
2371 u64 page_addr = data & PAGE_MASK;
2372 u8 *page;
2373 int r;
2374
2375 r = -E2BIG;
2376 if (page_num >= blob_size)
2377 goto out;
2378 r = -ENOMEM;
ff5c2c03
SL		 2379 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2380 if (IS_ERR(page)) {
2381 r = PTR_ERR(page);
ffde22ac 2382 goto out;
ff5c2c03 2383 }
54bf36aa 2384 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2385 goto out_free;
2386 r = 0;
2387out_free:
2388 kfree(page);
2389out:
2390 return r;
2391}
2392
344d9588
GN		 2393static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2394{
2395 gpa_t gpa = data & ~0x3f;
2396
52a5c155
WL		 2397 /* Bits 3:5 are reserved, Should be zero */
2398 if (data & 0x38)
344d9588
GN		 2399 return 1;
2400
2401 vcpu->arch.apf.msr_val = data;
2402
2403 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2404 kvm_clear_async_pf_completion_queue(vcpu);
2405 kvm_async_pf_hash_reset(vcpu);
2406 return 0;
2407 }
2408
4e335d9e 2409 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2410 sizeof(u32)))
344d9588
GN		 2411 return 1;
2412
6adba527 2413 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2414 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2415 kvm_async_pf_wakeup_all(vcpu);
2416 return 0;
2417}
2418
12f9a48f
GC		 2419static void kvmclock_reset(struct kvm_vcpu *vcpu)
2420{
0b79459b 2421 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2422}
2423
f38a7b75
WL		 2424static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2425{
2426 ++vcpu->stat.tlb_flush;
2427 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2428}
2429
c9aaa895
GC		 2430static void record_steal_time(struct kvm_vcpu *vcpu)
2431{
2432 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2433 return;
2434
4e335d9e 2435 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2436 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2437 return;
2438
f38a7b75
WL		 2439 /*
2440 * Doing a TLB flush here, on the guest's behalf, can avoid
2441 * expensive IPIs.
2442 */
2443 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2444 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2445
35f3fae1
WL		 2446 if (vcpu->arch.st.steal.version & 1)
2447 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2448
2449 vcpu->arch.st.steal.version += 1;
2450
4e335d9e 2451 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2452 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2453
2454 smp_wmb();
2455
c54cdf14
LC		 2456 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2457 vcpu->arch.st.last_steal;
2458 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2459
4e335d9e 2460 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2461 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2462
2463 smp_wmb();
2464
2465 vcpu->arch.st.steal.version += 1;
c9aaa895 2466
4e335d9e 2467 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2468 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2469}
2470
8fe8ab46 2471int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2472{
5753785f 2473 bool pr = false;
8fe8ab46
WA		 2474 u32 msr = msr_info->index;
2475 u64 data = msr_info->data;
5753785f 2476
15c4a640 2477 switch (msr) {
2e32b719 2478 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2479 case MSR_IA32_UCODE_WRITE:
2480 case MSR_VM_HSAVE_PA:
2481 case MSR_AMD64_PATCH_LOADER:
2482 case MSR_AMD64_BU_CFG2:
405a353a 2483 case MSR_AMD64_DC_CFG:
0e1b869f 2484 case MSR_F15H_EX_CFG:
2e32b719
BP		 2485 break;
2486
518e7b94
WL		 2487 case MSR_IA32_UCODE_REV:
2488 if (msr_info->host_initiated)
2489 vcpu->arch.microcode_version = data;
2490 break;
0cf9135b
SC		 2491 case MSR_IA32_ARCH_CAPABILITIES:
2492 if (!msr_info->host_initiated)
2493 return 1;
2494 vcpu->arch.arch_capabilities = data;
2495 break;
15c4a640 2496 case MSR_EFER:
11988499 2497 return set_efer(vcpu, msr_info);
8f1589d9
AP		 2498 case MSR_K7_HWCR:
2499 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2500 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2501 data &= ~(u64)0x8; /* ignore TLB cache disable */
191c8137
BP		 2502
2503 /* Handle McStatusWrEn */
2504 if (data == BIT_ULL(18)) {
2505 vcpu->arch.msr_hwcr = data;
2506 } else if (data != 0) {
a737f256
CD		 2507 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2508 data);
8f1589d9
AP		 2509 return 1;
2510 }
15c4a640 2511 break;
f7c6d140
AP		 2512 case MSR_FAM10H_MMIO_CONF_BASE:
2513 if (data != 0) {
a737f256
CD		 2514 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2515 "0x%llx\n", data);
f7c6d140
AP		 2516 return 1;
2517 }
15c4a640 2518 break;
b5e2fec0
AG		 2519 case MSR_IA32_DEBUGCTLMSR:
2520 if (!data) {
2521 /* We support the non-activated case already */
2522 break;
2523 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2524 /* Values other than LBR and BTF are vendor-specific,
2525 thus reserved and should throw a #GP */
2526 return 1;
2527 }
a737f256
CD		 2528 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2529 __func__, data);
b5e2fec0 2530 break;
9ba075a6 2531 case 0x200 ... 0x2ff:
ff53604b 2532 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2533 case MSR_IA32_APICBASE:
58cb628d 2534 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2535 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2536 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2537 case MSR_IA32_TSCDEADLINE:
2538 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2539 break;
ba904635 2540 case MSR_IA32_TSC_ADJUST:
d6321d49 2541 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2542 if (!msr_info->host_initiated) {
d913b904 2543 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2544 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2545 }
2546 vcpu->arch.ia32_tsc_adjust_msr = data;
2547 }
2548 break;
15c4a640 2549 case MSR_IA32_MISC_ENABLE:
511a8556
WL		 2550 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2551 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2552 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2553 return 1;
2554 vcpu->arch.ia32_misc_enable_msr = data;
2555 kvm_update_cpuid(vcpu);
2556 } else {
2557 vcpu->arch.ia32_misc_enable_msr = data;
2558 }
15c4a640 2559 break;
64d60670
PB		 2560 case MSR_IA32_SMBASE:
2561 if (!msr_info->host_initiated)
2562 return 1;
2563 vcpu->arch.smbase = data;
2564 break;
dd259935
PB		 2565 case MSR_IA32_TSC:
2566 kvm_write_tsc(vcpu, msr_info);
2567 break;
52797bf9
LA		 2568 case MSR_SMI_COUNT:
2569 if (!msr_info->host_initiated)
2570 return 1;
2571 vcpu->arch.smi_count = data;
2572 break;
11c6bffa 2573 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2574 case MSR_KVM_WALL_CLOCK:
2575 vcpu->kvm->arch.wall_clock = data;
2576 kvm_write_wall_clock(vcpu->kvm, data);
2577 break;
11c6bffa 2578 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2579 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2580 struct kvm_arch *ka = &vcpu->kvm->arch;
2581
12f9a48f 2582 kvmclock_reset(vcpu);
18068523 2583
54750f2c
MT		 2584 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2585 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2586
2587 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2588 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2589
2590 ka->boot_vcpu_runs_old_kvmclock = tmp;
2591 }
2592
18068523 2593 vcpu->arch.time = data;
0061d53d 2594 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2595
2596 /* we verify if the enable bit is set... */
2597 if (!(data & 1))
2598 break;
2599
4e335d9e 2600 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2601 &vcpu->arch.pv_time, data & ~1ULL,
2602 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2603 vcpu->arch.pv_time_enabled = false;
2604 else
2605 vcpu->arch.pv_time_enabled = true;
32cad84f 2606
18068523
GOC		 2607 break;
2608 }
344d9588
GN		 2609 case MSR_KVM_ASYNC_PF_EN:
2610 if (kvm_pv_enable_async_pf(vcpu, data))
2611 return 1;
2612 break;
c9aaa895
GC		 2613 case MSR_KVM_STEAL_TIME:
2614
2615 if (unlikely(!sched_info_on()))
2616 return 1;
2617
2618 if (data & KVM_STEAL_RESERVED_MASK)
2619 return 1;
2620
4e335d9e 2621 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2622 data & KVM_STEAL_VALID_BITS,
2623 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2624 return 1;
2625
2626 vcpu->arch.st.msr_val = data;
2627
2628 if (!(data & KVM_MSR_ENABLED))
2629 break;
2630
c9aaa895
GC		 2631 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2632
2633 break;
ae7a2a3f 2634 case MSR_KVM_PV_EOI_EN:
72bbf935 2635 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2636 return 1;
2637 break;
c9aaa895 2638
890ca9ae
HY		 2639 case MSR_IA32_MCG_CTL:
2640 case MSR_IA32_MCG_STATUS:
81760dcc 2641 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2642 return set_msr_mce(vcpu, msr_info);
71db6023 2643
6912ac32
WH		 2644 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2645 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2646 pr = true; /* fall through */
2647 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2648 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2649 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2650 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2651
2652 if (pr || data != 0)
a737f256
CD		 2653 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2654 "0x%x data 0x%llx\n", msr, data);
5753785f 2655 break;
84e0cefa
JS		 2656 case MSR_K7_CLK_CTL:
2657 /*
2658 * Ignore all writes to this no longer documented MSR.
2659 * Writes are only relevant for old K7 processors,
2660 * all pre-dating SVM, but a recommended workaround from
4a969980 2661 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2662 * affected processor models on the command line, hence
2663 * the need to ignore the workaround.
2664 */
2665 break;
55cd8e5a 2666 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2667 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2668 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2669 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2670 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2671 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2672 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2673 return kvm_hv_set_msr_common(vcpu, msr, data,
2674 msr_info->host_initiated);
91c9c3ed 2675 case MSR_IA32_BBL_CR_CTL3:
2676 /* Drop writes to this legacy MSR -- see rdmsr
2677 * counterpart for further detail.
2678 */
fab0aa3b
EM		 2679 if (report_ignored_msrs)
2680 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2681 msr, data);
91c9c3ed 2682 break;
2b036c6b 2683 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2684 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2685 return 1;
2686 vcpu->arch.osvw.length = data;
2687 break;
2688 case MSR_AMD64_OSVW_STATUS:
d6321d49 2689 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2690 return 1;
2691 vcpu->arch.osvw.status = data;
2692 break;
db2336a8
KH		 2693 case MSR_PLATFORM_INFO:
2694 if (!msr_info->host_initiated ||
db2336a8
KH		 2695 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2696 cpuid_fault_enabled(vcpu)))
2697 return 1;
2698 vcpu->arch.msr_platform_info = data;
2699 break;
2700 case MSR_MISC_FEATURES_ENABLES:
2701 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2702 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2703 !supports_cpuid_fault(vcpu)))
2704 return 1;
2705 vcpu->arch.msr_misc_features_enables = data;
2706 break;
15c4a640 2707 default:
ffde22ac
ES		 2708 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2709 return xen_hvm_config(vcpu, data);
c6702c9d 2710 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2711 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2712 if (!ignore_msrs) {
ae0f5499 2713 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2714 msr, data);
ed85c068
AP		 2715 return 1;
2716 } else {
fab0aa3b
EM		 2717 if (report_ignored_msrs)
2718 vcpu_unimpl(vcpu,
2719 "ignored wrmsr: 0x%x data 0x%llx\n",
2720 msr, data);
ed85c068
AP		 2721 break;
2722 }
15c4a640
CO		 2723 }
2724 return 0;
2725}
2726EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2727
2728
2729/*
2730 * Reads an msr value (of 'msr_index') into 'pdata'.
2731 * Returns 0 on success, non-0 otherwise.
2732 * Assumes vcpu_load() was already called.
2733 */
609e36d3 2734int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2735{
609e36d3 2736 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2737}
ff651cb6 2738EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2739
44883f01 2740static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2741{
2742 u64 data;
890ca9ae
HY		 2743 u64 mcg_cap = vcpu->arch.mcg_cap;
2744 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2745
2746 switch (msr) {
15c4a640
CO		 2747 case MSR_IA32_P5_MC_ADDR:
2748 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2749 data = 0;
2750 break;
15c4a640 2751 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2752 data = vcpu->arch.mcg_cap;
2753 break;
c7ac679c 2754 case MSR_IA32_MCG_CTL:
44883f01 2755 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2756 return 1;
2757 data = vcpu->arch.mcg_ctl;
2758 break;
2759 case MSR_IA32_MCG_STATUS:
2760 data = vcpu->arch.mcg_status;
2761 break;
2762 default:
2763 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2764 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2765 u32 offset = msr - MSR_IA32_MC0_CTL;
2766 data = vcpu->arch.mce_banks[offset];
2767 break;
2768 }
2769 return 1;
2770 }
2771 *pdata = data;
2772 return 0;
2773}
2774
609e36d3 2775int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2776{
609e36d3 2777 switch (msr_info->index) {
890ca9ae 2778 case MSR_IA32_PLATFORM_ID:
15c4a640 2779 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2780 case MSR_IA32_DEBUGCTLMSR:
2781 case MSR_IA32_LASTBRANCHFROMIP:
2782 case MSR_IA32_LASTBRANCHTOIP:
2783 case MSR_IA32_LASTINTFROMIP:
2784 case MSR_IA32_LASTINTTOIP:
60af2ecd 2785 case MSR_K8_SYSCFG:
3afb1121
PB		 2786 case MSR_K8_TSEG_ADDR:
2787 case MSR_K8_TSEG_MASK:
61a6bd67 2788 case MSR_VM_HSAVE_PA:
1fdbd48c 2789 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2790 case MSR_AMD64_NB_CFG:
f7c6d140 2791 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2792 case MSR_AMD64_BU_CFG2:
0c2df2a1 2793 case MSR_IA32_PERF_CTL:
405a353a 2794 case MSR_AMD64_DC_CFG:
0e1b869f 2795 case MSR_F15H_EX_CFG:
609e36d3 2796 msr_info->data = 0;
15c4a640 2797 break;
c51eb52b 2798 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2799 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2800 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2801 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2802 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2803 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2804 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2805 msr_info->data = 0;
5753785f 2806 break;
742bc670 2807 case MSR_IA32_UCODE_REV:
518e7b94 2808 msr_info->data = vcpu->arch.microcode_version;
742bc670 2809 break;
0cf9135b
SC		 2810 case MSR_IA32_ARCH_CAPABILITIES:
2811 if (!msr_info->host_initiated &&
2812 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2813 return 1;
2814 msr_info->data = vcpu->arch.arch_capabilities;
2815 break;
dd259935
PB		 2816 case MSR_IA32_TSC:
2817 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2818 break;
9ba075a6 2819 case MSR_MTRRcap:
9ba075a6 2820 case 0x200 ... 0x2ff:
ff53604b 2821 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2822 case 0xcd: /* fsb frequency */
609e36d3 2823 msr_info->data = 3;
15c4a640 2824 break;
7b914098
JS		 2825 /*
2826 * MSR_EBC_FREQUENCY_ID
2827 * Conservative value valid for even the basic CPU models.
2828 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2829 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2830 * and 266MHz for model 3, or 4. Set Core Clock
2831 * Frequency to System Bus Frequency Ratio to 1 (bits
2832 * 31:24) even though these are only valid for CPU
2833 * models > 2, however guests may end up dividing or
2834 * multiplying by zero otherwise.
2835 */
2836 case MSR_EBC_FREQUENCY_ID:
609e36d3 2837 msr_info->data = 1 << 24;
7b914098 2838 break;
15c4a640 2839 case MSR_IA32_APICBASE:
609e36d3 2840 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2841 break;
0105d1a5 2842 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2843 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2844 break;
a3e06bbe 2845 case MSR_IA32_TSCDEADLINE:
609e36d3 2846 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2847 break;
ba904635 2848 case MSR_IA32_TSC_ADJUST:
609e36d3 2849 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2850 break;
15c4a640 2851 case MSR_IA32_MISC_ENABLE:
609e36d3 2852 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2853 break;
64d60670
PB		 2854 case MSR_IA32_SMBASE:
2855 if (!msr_info->host_initiated)
2856 return 1;
2857 msr_info->data = vcpu->arch.smbase;
15c4a640 2858 break;
52797bf9
LA		 2859 case MSR_SMI_COUNT:
2860 msr_info->data = vcpu->arch.smi_count;
2861 break;
847f0ad8
AG		 2862 case MSR_IA32_PERF_STATUS:
2863 /* TSC increment by tick */
609e36d3 2864 msr_info->data = 1000ULL;
847f0ad8 2865 /* CPU multiplier */
b0996ae4 2866 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2867 break;
15c4a640 2868 case MSR_EFER:
609e36d3 2869 msr_info->data = vcpu->arch.efer;
15c4a640 2870 break;
18068523 2871 case MSR_KVM_WALL_CLOCK:
11c6bffa 2872 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2873 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2874 break;
2875 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2876 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2877 msr_info->data = vcpu->arch.time;
18068523 2878 break;
344d9588 2879 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2880 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2881 break;
c9aaa895 2882 case MSR_KVM_STEAL_TIME:
609e36d3 2883 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2884 break;
1d92128f 2885 case MSR_KVM_PV_EOI_EN:
609e36d3 2886 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2887 break;
890ca9ae
HY		 2888 case MSR_IA32_P5_MC_ADDR:
2889 case MSR_IA32_P5_MC_TYPE:
2890 case MSR_IA32_MCG_CAP:
2891 case MSR_IA32_MCG_CTL:
2892 case MSR_IA32_MCG_STATUS:
81760dcc 2893 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2894 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2895 msr_info->host_initiated);
84e0cefa
JS		 2896 case MSR_K7_CLK_CTL:
2897 /*
2898 * Provide expected ramp-up count for K7. All other
2899 * are set to zero, indicating minimum divisors for
2900 * every field.
2901 *
2902 * This prevents guest kernels on AMD host with CPU
2903 * type 6, model 8 and higher from exploding due to
2904 * the rdmsr failing.
2905 */
609e36d3 2906 msr_info->data = 0x20000000;
84e0cefa 2907 break;
55cd8e5a 2908 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2909 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2910 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2911 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2912 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2913 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2914 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2915 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2916 msr_info->index, &msr_info->data,
2917 msr_info->host_initiated);
55cd8e5a 2918 break;
91c9c3ed 2919 case MSR_IA32_BBL_CR_CTL3:
2920 /* This legacy MSR exists but isn't fully documented in current
2921 * silicon. It is however accessed by winxp in very narrow
2922 * scenarios where it sets bit #19, itself documented as
2923 * a "reserved" bit. Best effort attempt to source coherent
2924 * read data here should the balance of the register be
2925 * interpreted by the guest:
2926 *
2927 * L2 cache control register 3: 64GB range, 256KB size,
2928 * enabled, latency 0x1, configured
2929 */
609e36d3 2930 msr_info->data = 0xbe702111;
91c9c3ed 2931 break;
2b036c6b 2932 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2933 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2934 return 1;
609e36d3 2935 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2936 break;
2937 case MSR_AMD64_OSVW_STATUS:
d6321d49 2938 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2939 return 1;
609e36d3 2940 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2941 break;
db2336a8 2942 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2943 if (!msr_info->host_initiated &&
2944 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2945 return 1;
db2336a8
KH		 2946 msr_info->data = vcpu->arch.msr_platform_info;
2947 break;
2948 case MSR_MISC_FEATURES_ENABLES:
2949 msr_info->data = vcpu->arch.msr_misc_features_enables;
2950 break;
191c8137
BP		 2951 case MSR_K7_HWCR:
2952 msr_info->data = vcpu->arch.msr_hwcr;
2953 break;
15c4a640 2954 default:
c6702c9d 2955 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2956 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2957 if (!ignore_msrs) {
ae0f5499
BD		 2958 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2959 msr_info->index);
ed85c068
AP		 2960 return 1;
2961 } else {
fab0aa3b
EM		 2962 if (report_ignored_msrs)
2963 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2964 msr_info->index);
609e36d3 2965 msr_info->data = 0;
ed85c068
AP		 2966 }
2967 break;
15c4a640 2968 }
15c4a640
CO		 2969 return 0;
2970}
2971EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2972
313a3dc7
CO		 2973/*
2974 * Read or write a bunch of msrs. All parameters are kernel addresses.
2975 *
2976 * @return number of msrs set successfully.
2977 */
2978static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2979 struct kvm_msr_entry *entries,
2980 int (*do_msr)(struct kvm_vcpu *vcpu,
2981 unsigned index, u64 *data))
2982{
801e459a 2983 int i;
313a3dc7 2984
313a3dc7
CO		 2985 for (i = 0; i < msrs->nmsrs; ++i)
2986 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2987 break;
2988
313a3dc7
CO		 2989 return i;
2990}
2991
2992/*
2993 * Read or write a bunch of msrs. Parameters are user addresses.
2994 *
2995 * @return number of msrs set successfully.
2996 */
2997static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2998 int (*do_msr)(struct kvm_vcpu *vcpu,
2999 unsigned index, u64 *data),
3000 int writeback)
3001{
3002 struct kvm_msrs msrs;
3003 struct kvm_msr_entry *entries;
3004 int r, n;
3005 unsigned size;
3006
3007 r = -EFAULT;
0e96f31e 3008 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 3009 goto out;
3010
3011 r = -E2BIG;
3012 if (msrs.nmsrs >= MAX_IO_MSRS)
3013 goto out;
3014
313a3dc7 3015 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 3016 entries = memdup_user(user_msrs->entries, size);
3017 if (IS_ERR(entries)) {
3018 r = PTR_ERR(entries);
313a3dc7 3019 goto out;
ff5c2c03 3020 }
313a3dc7
CO		 3021
3022 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3023 if (r < 0)
3024 goto out_free;
3025
3026 r = -EFAULT;
3027 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3028 goto out_free;
3029
3030 r = n;
3031
3032out_free:
7a73c028 3033 kfree(entries);
313a3dc7
CO		 3034out:
3035 return r;
3036}
3037
4d5422ce
WL		 3038static inline bool kvm_can_mwait_in_guest(void)
3039{
3040 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 3041 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3042 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 3043}
3044
784aa3d7 3045int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 3046{
4d5422ce 3047 int r = 0;
018d00d2
ZX		 3048
3049 switch (ext) {
3050 case KVM_CAP_IRQCHIP:
3051 case KVM_CAP_HLT:
3052 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 3053 case KVM_CAP_SET_TSS_ADDR:
07716717 3054 case KVM_CAP_EXT_CPUID:
9c15bb1d 3055 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3056 case KVM_CAP_CLOCKSOURCE:
7837699f 3057 case KVM_CAP_PIT:
a28e4f5a 3058 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3059 case KVM_CAP_MP_STATE:
ed848624 3060 case KVM_CAP_SYNC_MMU:
a355c85c 3061 case KVM_CAP_USER_NMI:
52d939a0 3062 case KVM_CAP_REINJECT_CONTROL:
4925663a 3063 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3064 case KVM_CAP_IOEVENTFD:
f848a5a8 3065 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3066 case KVM_CAP_PIT2:
e9f42757 3067 case KVM_CAP_PIT_STATE2:
b927a3ce 3068 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3069 case KVM_CAP_XEN_HVM:
3cfc3092 3070 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3071 case KVM_CAP_HYPERV:
10388a07 3072 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3073 case KVM_CAP_HYPERV_SPIN:
5c919412 3074 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3075 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3076 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3077 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3078 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3079 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 3080 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
2bc39970 3081 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3082 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3083 case KVM_CAP_DEBUGREGS:
d2be1651 3084 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3085 case KVM_CAP_XSAVE:
344d9588 3086 case KVM_CAP_ASYNC_PF:
92a1f12d 3087 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3088 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3089 case KVM_CAP_READONLY_MEM:
5f66b620 3090 case KVM_CAP_HYPERV_TIME:
100943c5 3091 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3092 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3093 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3094 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3095 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3096 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 3097 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3098 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3099 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3100 r = 1;
3101 break;
01643c51
KH		 3102 case KVM_CAP_SYNC_REGS:
3103 r = KVM_SYNC_X86_VALID_FIELDS;
3104 break;
e3fd9a93
PB		 3105 case KVM_CAP_ADJUST_CLOCK:
3106 r = KVM_CLOCK_TSC_STABLE;
3107 break;
4d5422ce 3108 case KVM_CAP_X86_DISABLE_EXITS:
b5170063
WL		 3109 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3110 KVM_X86_DISABLE_EXITS_CSTATE;
4d5422ce
WL		 3111 if(kvm_can_mwait_in_guest())
3112 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3113 break;
6d396b55
PB		 3114 case KVM_CAP_X86_SMM:
3115 /* SMBASE is usually relocated above 1M on modern chipsets,
3116 * and SMM handlers might indeed rely on 4G segment limits,
3117 * so do not report SMM to be available if real mode is
3118 * emulated via vm86 mode. Still, do not go to great lengths
3119 * to avoid userspace's usage of the feature, because it is a
3120 * fringe case that is not enabled except via specific settings
3121 * of the module parameters.
3122 */
bc226f07 3123 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3124 break;
774ead3a
AK		 3125 case KVM_CAP_VAPIC:
3126 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3127 break;
f725230a 3128 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3129 r = KVM_SOFT_MAX_VCPUS;
3130 break;
3131 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3132 r = KVM_MAX_VCPUS;
3133 break;
a86cb413
TH		 3134 case KVM_CAP_MAX_VCPU_ID:
3135 r = KVM_MAX_VCPU_ID;
3136 break;
a68a6a72
MT		 3137 case KVM_CAP_PV_MMU: /* obsolete */
3138 r = 0;
2f333bcb 3139 break;
890ca9ae
HY		 3140 case KVM_CAP_MCE:
3141 r = KVM_MAX_MCE_BANKS;
3142 break;
2d5b5a66 3143 case KVM_CAP_XCRS:
d366bf7e 3144 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3145 break;
92a1f12d
JR		 3146 case KVM_CAP_TSC_CONTROL:
3147 r = kvm_has_tsc_control;
3148 break;
37131313
RK		 3149 case KVM_CAP_X2APIC_API:
3150 r = KVM_X2APIC_API_VALID_FLAGS;
3151 break;
8fcc4b59
JM		 3152 case KVM_CAP_NESTED_STATE:
3153 r = kvm_x86_ops->get_nested_state ?
be43c440 3154 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3155 break;
018d00d2 3156 default:
018d00d2
ZX		 3157 break;
3158 }
3159 return r;
3160
3161}
3162
043405e1
CO		 3163long kvm_arch_dev_ioctl(struct file *filp,
3164 unsigned int ioctl, unsigned long arg)
3165{
3166 void __user *argp = (void __user *)arg;
3167 long r;
3168
3169 switch (ioctl) {
3170 case KVM_GET_MSR_INDEX_LIST: {
3171 struct kvm_msr_list __user *user_msr_list = argp;
3172 struct kvm_msr_list msr_list;
3173 unsigned n;
3174
3175 r = -EFAULT;
0e96f31e 3176 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3177 goto out;
3178 n = msr_list.nmsrs;
62ef68bb 3179 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3180 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3181 goto out;
3182 r = -E2BIG;
e125e7b6 3183 if (n < msr_list.nmsrs)
043405e1
CO		 3184 goto out;
3185 r = -EFAULT;
3186 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3187 num_msrs_to_save * sizeof(u32)))
3188 goto out;
e125e7b6 3189 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3190 &emulated_msrs,
62ef68bb 3191 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3192 goto out;
3193 r = 0;
3194 break;
3195 }
9c15bb1d
BP		 3196 case KVM_GET_SUPPORTED_CPUID:
3197 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3198 struct kvm_cpuid2 __user *cpuid_arg = argp;
3199 struct kvm_cpuid2 cpuid;
3200
3201 r = -EFAULT;
0e96f31e 3202 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3203 goto out;
9c15bb1d
BP		 3204
3205 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3206 ioctl);
674eea0f
AK		 3207 if (r)
3208 goto out;
3209
3210 r = -EFAULT;
0e96f31e 3211 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3212 goto out;
3213 r = 0;
3214 break;
3215 }
890ca9ae 3216 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3217 r = -EFAULT;
c45dcc71
AR		 3218 if (copy_to_user(argp, &kvm_mce_cap_supported,
3219 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3220 goto out;
3221 r = 0;
3222 break;
801e459a
TL		 3223 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3224 struct kvm_msr_list __user *user_msr_list = argp;
3225 struct kvm_msr_list msr_list;
3226 unsigned int n;
3227
3228 r = -EFAULT;
3229 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3230 goto out;
3231 n = msr_list.nmsrs;
3232 msr_list.nmsrs = num_msr_based_features;
3233 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3234 goto out;
3235 r = -E2BIG;
3236 if (n < msr_list.nmsrs)
3237 goto out;
3238 r = -EFAULT;
3239 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3240 num_msr_based_features * sizeof(u32)))
3241 goto out;
3242 r = 0;
3243 break;
3244 }
3245 case KVM_GET_MSRS:
3246 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3247 break;
890ca9ae 3248 }
043405e1
CO		 3249 default:
3250 r = -EINVAL;
3251 }
3252out:
3253 return r;
3254}
3255
f5f48ee1
SY		 3256static void wbinvd_ipi(void *garbage)
3257{
3258 wbinvd();
3259}
3260
3261static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3262{
e0f0bbc5 3263 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3264}
3265
313a3dc7
CO		 3266void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3267{
f5f48ee1
SY		 3268 /* Address WBINVD may be executed by guest */
3269 if (need_emulate_wbinvd(vcpu)) {
3270 if (kvm_x86_ops->has_wbinvd_exit())
3271 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3272 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3273 smp_call_function_single(vcpu->cpu,
3274 wbinvd_ipi, NULL, 1);
3275 }
3276
313a3dc7 3277 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3278
0dd6a6ed
ZA		 3279 /* Apply any externally detected TSC adjustments (due to suspend) */
3280 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3281 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3282 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3283 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3284 }
8f6055cb 3285
b0c39dc6 3286 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3287 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3288 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3289 if (tsc_delta < 0)
3290 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3291
b0c39dc6 3292 if (kvm_check_tsc_unstable()) {
07c1419a 3293 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3294 vcpu->arch.last_guest_tsc);
a545ab6a 3295 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3296 vcpu->arch.tsc_catchup = 1;
c285545f 3297 }
a749e247
PB		 3298
3299 if (kvm_lapic_hv_timer_in_use(vcpu))
3300 kvm_lapic_restart_hv_timer(vcpu);
3301
d98d07ca
MT		 3302 /*
3303 * On a host with synchronized TSC, there is no need to update
3304 * kvmclock on vcpu->cpu migration
3305 */
3306 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3307 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3308 if (vcpu->cpu != cpu)
1bd2009e 3309 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3310 vcpu->cpu = cpu;
6b7d7e76 3311 }
c9aaa895 3312
c9aaa895 3313 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3314}
3315
0b9f6c46
PX		 3316static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3317{
3318 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3319 return;
3320
fa55eedd 3321 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3322
4e335d9e 3323 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3324 &vcpu->arch.st.steal.preempted,
3325 offsetof(struct kvm_steal_time, preempted),
3326 sizeof(vcpu->arch.st.steal.preempted));
3327}
3328
313a3dc7
CO		 3329void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3330{
cc0d907c 3331 int idx;
de63ad4c
LM		 3332
3333 if (vcpu->preempted)
3334 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3335
931f261b
AA		 3336 /*
3337 * Disable page faults because we're in atomic context here.
3338 * kvm_write_guest_offset_cached() would call might_fault()
3339 * that relies on pagefault_disable() to tell if there's a
3340 * bug. NOTE: the write to guest memory may not go through if
3341 * during postcopy live migration or if there's heavy guest
3342 * paging.
3343 */
3344 pagefault_disable();
cc0d907c
AA		 3345 /*
3346 * kvm_memslots() will be called by
3347 * kvm_write_guest_offset_cached() so take the srcu lock.
3348 */
3349 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3350 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3351 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3352 pagefault_enable();
02daab21 3353 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3354 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3355 /*
f9dcf08e
RK		 3356 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3357 * on every vmexit, but if not, we might have a stale dr6 from the
3358 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3359 */
f9dcf08e 3360 set_debugreg(0, 6);
313a3dc7
CO		 3361}
3362
313a3dc7
CO		 3363static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3364 struct kvm_lapic_state *s)
3365{
fa59cc00 3366 if (vcpu->arch.apicv_active)
d62caabb
AS		 3367 kvm_x86_ops->sync_pir_to_irr(vcpu);
3368
a92e2543 3369 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3370}
3371
3372static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3373 struct kvm_lapic_state *s)
3374{
a92e2543
RK		 3375 int r;
3376
3377 r = kvm_apic_set_state(vcpu, s);
3378 if (r)
3379 return r;
cb142eb7 3380 update_cr8_intercept(vcpu);
313a3dc7
CO		 3381
3382 return 0;
3383}
3384
127a457a
MG		 3385static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3386{
3387 return (!lapic_in_kernel(vcpu) ||
3388 kvm_apic_accept_pic_intr(vcpu));
3389}
3390
782d422b
MG		 3391/*
3392 * if userspace requested an interrupt window, check that the
3393 * interrupt window is open.
3394 *
3395 * No need to exit to userspace if we already have an interrupt queued.
3396 */
3397static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3398{
3399 return kvm_arch_interrupt_allowed(vcpu) &&
3400 !kvm_cpu_has_interrupt(vcpu) &&
3401 !kvm_event_needs_reinjection(vcpu) &&
3402 kvm_cpu_accept_dm_intr(vcpu);
3403}
3404
f77bc6a4
ZX		 3405static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3406 struct kvm_interrupt *irq)
3407{
02cdb50f 3408 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3409 return -EINVAL;
1c1a9ce9
SR		 3410
3411 if (!irqchip_in_kernel(vcpu->kvm)) {
3412 kvm_queue_interrupt(vcpu, irq->irq, false);
3413 kvm_make_request(KVM_REQ_EVENT, vcpu);
3414 return 0;
3415 }
3416
3417 /*
3418 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3419 * fail for in-kernel 8259.
3420 */
3421 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3422 return -ENXIO;
f77bc6a4 3423
1c1a9ce9
SR		 3424 if (vcpu->arch.pending_external_vector != -1)
3425 return -EEXIST;
f77bc6a4 3426
1c1a9ce9 3427 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3428 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3429 return 0;
3430}
3431
c4abb7c9
JK		 3432static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3433{
c4abb7c9 3434 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3435
3436 return 0;
3437}
3438
f077825a
PB		 3439static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3440{
64d60670
PB		 3441 kvm_make_request(KVM_REQ_SMI, vcpu);
3442
f077825a
PB		 3443 return 0;
3444}
3445
b209749f
AK		 3446static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3447 struct kvm_tpr_access_ctl *tac)
3448{
3449 if (tac->flags)
3450 return -EINVAL;
3451 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3452 return 0;
3453}
3454
890ca9ae
HY		 3455static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3456 u64 mcg_cap)
3457{
3458 int r;
3459 unsigned bank_num = mcg_cap & 0xff, bank;
3460
3461 r = -EINVAL;
a9e38c3e 3462 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3463 goto out;
c45dcc71 3464 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3465 goto out;
3466 r = 0;
3467 vcpu->arch.mcg_cap = mcg_cap;
3468 /* Init IA32_MCG_CTL to all 1s */
3469 if (mcg_cap & MCG_CTL_P)
3470 vcpu->arch.mcg_ctl = ~(u64)0;
3471 /* Init IA32_MCi_CTL to all 1s */
3472 for (bank = 0; bank < bank_num; bank++)
3473 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3474
3475 if (kvm_x86_ops->setup_mce)
3476 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3477out:
3478 return r;
3479}
3480
3481static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3482 struct kvm_x86_mce *mce)
3483{
3484 u64 mcg_cap = vcpu->arch.mcg_cap;
3485 unsigned bank_num = mcg_cap & 0xff;
3486 u64 *banks = vcpu->arch.mce_banks;
3487
3488 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3489 return -EINVAL;
3490 /*
3491 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3492 * reporting is disabled
3493 */
3494 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3495 vcpu->arch.mcg_ctl != ~(u64)0)
3496 return 0;
3497 banks += 4 * mce->bank;
3498 /*
3499 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3500 * reporting is disabled for the bank
3501 */
3502 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3503 return 0;
3504 if (mce->status & MCI_STATUS_UC) {
3505 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3506 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3507 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3508 return 0;
3509 }
3510 if (banks[1] & MCI_STATUS_VAL)
3511 mce->status |= MCI_STATUS_OVER;
3512 banks[2] = mce->addr;
3513 banks[3] = mce->misc;
3514 vcpu->arch.mcg_status = mce->mcg_status;
3515 banks[1] = mce->status;
3516 kvm_queue_exception(vcpu, MC_VECTOR);
3517 } else if (!(banks[1] & MCI_STATUS_VAL)
3518 || !(banks[1] & MCI_STATUS_UC)) {
3519 if (banks[1] & MCI_STATUS_VAL)
3520 mce->status |= MCI_STATUS_OVER;
3521 banks[2] = mce->addr;
3522 banks[3] = mce->misc;
3523 banks[1] = mce->status;
3524 } else
3525 banks[1] |= MCI_STATUS_OVER;
3526 return 0;
3527}
3528
3cfc3092
JK		 3529static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3530 struct kvm_vcpu_events *events)
3531{
7460fb4a 3532 process_nmi(vcpu);
59073aaf 3533
664f8e26 3534 /*
59073aaf
JM		 3535 * The API doesn't provide the instruction length for software
3536 * exceptions, so don't report them. As long as the guest RIP
3537 * isn't advanced, we should expect to encounter the exception
3538 * again.
664f8e26 3539 */
59073aaf
JM		 3540 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3541 events->exception.injected = 0;
3542 events->exception.pending = 0;
3543 } else {
3544 events->exception.injected = vcpu->arch.exception.injected;
3545 events->exception.pending = vcpu->arch.exception.pending;
3546 /*
3547 * For ABI compatibility, deliberately conflate
3548 * pending and injected exceptions when
3549 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3550 */
3551 if (!vcpu->kvm->arch.exception_payload_enabled)
3552 events->exception.injected |=
3553 vcpu->arch.exception.pending;
3554 }
3cfc3092
JK		 3555 events->exception.nr = vcpu->arch.exception.nr;
3556 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3557 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3558 events->exception_has_payload = vcpu->arch.exception.has_payload;
3559 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3560
03b82a30 3561 events->interrupt.injected =
04140b41 3562 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3563 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3564 events->interrupt.soft = 0;
37ccdcbe 3565 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3566
3567 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3568 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3569 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3570 events->nmi.pad = 0;
3cfc3092 3571
66450a21 3572 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3573
f077825a
PB		 3574 events->smi.smm = is_smm(vcpu);
3575 events->smi.pending = vcpu->arch.smi_pending;
3576 events->smi.smm_inside_nmi =
3577 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3578 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3579
dab4b911 3580 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3581 | KVM_VCPUEVENT_VALID_SHADOW
3582 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3583 if (vcpu->kvm->arch.exception_payload_enabled)
3584 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3585
97e69aa6 3586 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3587}
3588
c5833c7a 3589static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3590
3cfc3092
JK		 3591static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3592 struct kvm_vcpu_events *events)
3593{
dab4b911 3594 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3595 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3596 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3597 | KVM_VCPUEVENT_VALID_SMM
3598 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3599 return -EINVAL;
3600
59073aaf
JM		 3601 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3602 if (!vcpu->kvm->arch.exception_payload_enabled)
3603 return -EINVAL;
3604 if (events->exception.pending)
3605 events->exception.injected = 0;
3606 else
3607 events->exception_has_payload = 0;
3608 } else {
3609 events->exception.pending = 0;
3610 events->exception_has_payload = 0;
3611 }
3612
3613 if ((events->exception.injected || events->exception.pending) &&
3614 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3615 return -EINVAL;
3616
28bf2888
DH		 3617 /* INITs are latched while in SMM */
3618 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3619 (events->smi.smm || events->smi.pending) &&
3620 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3621 return -EINVAL;
3622
7460fb4a 3623 process_nmi(vcpu);
59073aaf
JM		 3624 vcpu->arch.exception.injected = events->exception.injected;
3625 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3626 vcpu->arch.exception.nr = events->exception.nr;
3627 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3628 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3629 vcpu->arch.exception.has_payload = events->exception_has_payload;
3630 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3631
04140b41 3632 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3633 vcpu->arch.interrupt.nr = events->interrupt.nr;
3634 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3635 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3636 kvm_x86_ops->set_interrupt_shadow(vcpu,
3637 events->interrupt.shadow);
3cfc3092
JK		 3638
3639 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3640 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3641 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3642 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3643
66450a21 3644 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3645 lapic_in_kernel(vcpu))
66450a21 3646 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3647
f077825a 3648 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3649 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3650 if (events->smi.smm)
3651 vcpu->arch.hflags |= HF_SMM_MASK;
3652 else
3653 vcpu->arch.hflags &= ~HF_SMM_MASK;
3654 kvm_smm_changed(vcpu);
3655 }
6ef4e07e 3656
f077825a 3657 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3658
3659 if (events->smi.smm) {
3660 if (events->smi.smm_inside_nmi)
3661 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3662 else
f4ef1910
WL		 3663 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3664 if (lapic_in_kernel(vcpu)) {
3665 if (events->smi.latched_init)
3666 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3667 else
3668 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3669 }
f077825a
PB		 3670 }
3671 }
3672
3842d135
AK		 3673 kvm_make_request(KVM_REQ_EVENT, vcpu);
3674
3cfc3092
JK		 3675 return 0;
3676}
3677
a1efbe77
JK		 3678static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3679 struct kvm_debugregs *dbgregs)
3680{
73aaf249
JK		 3681 unsigned long val;
3682
a1efbe77 3683 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3684 kvm_get_dr(vcpu, 6, &val);
73aaf249 3685 dbgregs->dr6 = val;
a1efbe77
JK		 3686 dbgregs->dr7 = vcpu->arch.dr7;
3687 dbgregs->flags = 0;
97e69aa6 3688 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3689}
3690
3691static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3692 struct kvm_debugregs *dbgregs)
3693{
3694 if (dbgregs->flags)
3695 return -EINVAL;
3696
d14bdb55
PB		 3697 if (dbgregs->dr6 & ~0xffffffffull)
3698 return -EINVAL;
3699 if (dbgregs->dr7 & ~0xffffffffull)
3700 return -EINVAL;
3701
a1efbe77 3702 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3703 kvm_update_dr0123(vcpu);
a1efbe77 3704 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3705 kvm_update_dr6(vcpu);
a1efbe77 3706 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3707 kvm_update_dr7(vcpu);
a1efbe77 3708
a1efbe77
JK		 3709 return 0;
3710}
3711
df1daba7
PB		 3712#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3713
3714static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3715{
b666a4b6 3716 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3717 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3718 u64 valid;
3719
3720 /*
3721 * Copy legacy XSAVE area, to avoid complications with CPUID
3722 * leaves 0 and 1 in the loop below.
3723 */
3724 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3725
3726 /* Set XSTATE_BV */
00c87e9a 3727 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3728 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3729
3730 /*
3731 * Copy each region from the possibly compacted offset to the
3732 * non-compacted offset.
3733 */
d91cab78 3734 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3735 while (valid) {
abd16d68
SAS		 3736 u64 xfeature_mask = valid & -valid;
3737 int xfeature_nr = fls64(xfeature_mask) - 1;
3738 void *src = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3739
3740 if (src) {
3741 u32 size, offset, ecx, edx;
abd16d68 3742 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3743 &size, &offset, &ecx, &edx);
abd16d68 3744 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3745 memcpy(dest + offset, &vcpu->arch.pkru,
3746 sizeof(vcpu->arch.pkru));
3747 else
3748 memcpy(dest + offset, src, size);
3749
df1daba7
PB		 3750 }
3751
abd16d68 3752 valid -= xfeature_mask;
df1daba7
PB		 3753 }
3754}
3755
3756static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3757{
b666a4b6 3758 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3759 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3760 u64 valid;
3761
3762 /*
3763 * Copy legacy XSAVE area, to avoid complications with CPUID
3764 * leaves 0 and 1 in the loop below.
3765 */
3766 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3767
3768 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3769 xsave->header.xfeatures = xstate_bv;
782511b0 3770 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3771 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3772
3773 /*
3774 * Copy each region from the non-compacted offset to the
3775 * possibly compacted offset.
3776 */
d91cab78 3777 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3778 while (valid) {
abd16d68
SAS		 3779 u64 xfeature_mask = valid & -valid;
3780 int xfeature_nr = fls64(xfeature_mask) - 1;
3781 void *dest = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3782
3783 if (dest) {
3784 u32 size, offset, ecx, edx;
abd16d68 3785 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3786 &size, &offset, &ecx, &edx);
abd16d68 3787 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3788 memcpy(&vcpu->arch.pkru, src + offset,
3789 sizeof(vcpu->arch.pkru));
3790 else
3791 memcpy(dest, src + offset, size);
ee4100da 3792 }
df1daba7 3793
abd16d68 3794 valid -= xfeature_mask;
df1daba7
PB		 3795 }
3796}
3797
2d5b5a66
SY		 3798static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3799 struct kvm_xsave *guest_xsave)
3800{
d366bf7e 3801 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3802 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3803 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3804 } else {
2d5b5a66 3805 memcpy(guest_xsave->region,
b666a4b6 3806 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3807 sizeof(struct fxregs_state));
2d5b5a66 3808 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3809 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3810 }
3811}
3812
a575813b
WL		 3813#define XSAVE_MXCSR_OFFSET 24
3814
2d5b5a66
SY		 3815static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3816 struct kvm_xsave *guest_xsave)
3817{
3818 u64 xstate_bv =
3819 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3820 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3821
d366bf7e 3822 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3823 /*
3824 * Here we allow setting states that are not present in
3825 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3826 * with old userspace.
3827 */
a575813b
WL		 3828 if (xstate_bv & ~kvm_supported_xcr0() ||
3829 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3830 return -EINVAL;
df1daba7 3831 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3832 } else {
a575813b
WL		 3833 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3834 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3835 return -EINVAL;
b666a4b6 3836 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3837 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3838 }
3839 return 0;
3840}
3841
3842static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3843 struct kvm_xcrs *guest_xcrs)
3844{
d366bf7e 3845 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3846 guest_xcrs->nr_xcrs = 0;
3847 return;
3848 }
3849
3850 guest_xcrs->nr_xcrs = 1;
3851 guest_xcrs->flags = 0;
3852 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3853 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3854}
3855
3856static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3857 struct kvm_xcrs *guest_xcrs)
3858{
3859 int i, r = 0;
3860
d366bf7e 3861 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3862 return -EINVAL;
3863
3864 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3865 return -EINVAL;
3866
3867 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3868 /* Only support XCR0 currently */
c67a04cb 3869 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3870 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3871 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3872 break;
3873 }
3874 if (r)
3875 r = -EINVAL;
3876 return r;
3877}
3878
1c0b28c2
EM		 3879/*
3880 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3881 * stopped by the hypervisor. This function will be called from the host only.
3882 * EINVAL is returned when the host attempts to set the flag for a guest that
3883 * does not support pv clocks.
3884 */
3885static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3886{
0b79459b 3887 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3888 return -EINVAL;
51d59c6b 3889 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3890 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3891 return 0;
3892}
3893
5c919412
AS		 3894static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3895 struct kvm_enable_cap *cap)
3896{
57b119da
VK		 3897 int r;
3898 uint16_t vmcs_version;
3899 void __user *user_ptr;
3900
5c919412
AS		 3901 if (cap->flags)
3902 return -EINVAL;
3903
3904 switch (cap->cap) {
efc479e6
RK		 3905 case KVM_CAP_HYPERV_SYNIC2:
3906 if (cap->args[0])
3907 return -EINVAL;
b2869f28
GS		 3908 /* fall through */
3909
5c919412 3910 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3911 if (!irqchip_in_kernel(vcpu->kvm))
3912 return -EINVAL;
efc479e6
RK		 3913 return kvm_hv_activate_synic(vcpu, cap->cap ==
3914 KVM_CAP_HYPERV_SYNIC2);
57b119da 3915 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 3916 if (!kvm_x86_ops->nested_enable_evmcs)
3917 return -ENOTTY;
57b119da
VK		 3918 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3919 if (!r) {
3920 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3921 if (copy_to_user(user_ptr, &vmcs_version,
3922 sizeof(vmcs_version)))
3923 r = -EFAULT;
3924 }
3925 return r;
3926
5c919412
AS		 3927 default:
3928 return -EINVAL;
3929 }
3930}
3931
313a3dc7
CO		 3932long kvm_arch_vcpu_ioctl(struct file *filp,
3933 unsigned int ioctl, unsigned long arg)
3934{
3935 struct kvm_vcpu *vcpu = filp->private_data;
3936 void __user *argp = (void __user *)arg;
3937 int r;
d1ac91d8
AK		 3938 union {
3939 struct kvm_lapic_state *lapic;
3940 struct kvm_xsave *xsave;
3941 struct kvm_xcrs *xcrs;
3942 void *buffer;
3943 } u;
3944
9b062471
CD		 3945 vcpu_load(vcpu);
3946
d1ac91d8 3947 u.buffer = NULL;
313a3dc7
CO		 3948 switch (ioctl) {
3949 case KVM_GET_LAPIC: {
2204ae3c 3950 r = -EINVAL;
bce87cce 3951 if (!lapic_in_kernel(vcpu))
2204ae3c 3952 goto out;
254272ce
BG		 3953 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3954 GFP_KERNEL_ACCOUNT);
313a3dc7 3955
b772ff36 3956 r = -ENOMEM;
d1ac91d8 3957 if (!u.lapic)
b772ff36 3958 goto out;
d1ac91d8 3959 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3960 if (r)
3961 goto out;
3962 r = -EFAULT;
d1ac91d8 3963 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3964 goto out;
3965 r = 0;
3966 break;
3967 }
3968 case KVM_SET_LAPIC: {
2204ae3c 3969 r = -EINVAL;
bce87cce 3970 if (!lapic_in_kernel(vcpu))
2204ae3c 3971 goto out;
ff5c2c03 3972 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3973 if (IS_ERR(u.lapic)) {
3974 r = PTR_ERR(u.lapic);
3975 goto out_nofree;
3976 }
ff5c2c03 3977
d1ac91d8 3978 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3979 break;
3980 }
f77bc6a4
ZX		 3981 case KVM_INTERRUPT: {
3982 struct kvm_interrupt irq;
3983
3984 r = -EFAULT;
0e96f31e 3985 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 3986 goto out;
3987 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3988 break;
3989 }
c4abb7c9
JK		 3990 case KVM_NMI: {
3991 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3992 break;
3993 }
f077825a
PB		 3994 case KVM_SMI: {
3995 r = kvm_vcpu_ioctl_smi(vcpu);
3996 break;
3997 }
313a3dc7
CO		 3998 case KVM_SET_CPUID: {
3999 struct kvm_cpuid __user *cpuid_arg = argp;
4000 struct kvm_cpuid cpuid;
4001
4002 r = -EFAULT;
0e96f31e 4003 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 4004 goto out;
4005 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 4006 break;
4007 }
07716717
DK		 4008 case KVM_SET_CPUID2: {
4009 struct kvm_cpuid2 __user *cpuid_arg = argp;
4010 struct kvm_cpuid2 cpuid;
4011
4012 r = -EFAULT;
0e96f31e 4013 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4014 goto out;
4015 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 4016 cpuid_arg->entries);
07716717
DK		 4017 break;
4018 }
4019 case KVM_GET_CPUID2: {
4020 struct kvm_cpuid2 __user *cpuid_arg = argp;
4021 struct kvm_cpuid2 cpuid;
4022
4023 r = -EFAULT;
0e96f31e 4024 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4025 goto out;
4026 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 4027 cpuid_arg->entries);
07716717
DK		 4028 if (r)
4029 goto out;
4030 r = -EFAULT;
0e96f31e 4031 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 4032 goto out;
4033 r = 0;
4034 break;
4035 }
801e459a
TL		 4036 case KVM_GET_MSRS: {
4037 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 4038 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 4039 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4040 break;
801e459a
TL		 4041 }
4042 case KVM_SET_MSRS: {
4043 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 4044 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 4045 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4046 break;
801e459a 4047 }
b209749f
AK		 4048 case KVM_TPR_ACCESS_REPORTING: {
4049 struct kvm_tpr_access_ctl tac;
4050
4051 r = -EFAULT;
0e96f31e 4052 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 4053 goto out;
4054 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4055 if (r)
4056 goto out;
4057 r = -EFAULT;
0e96f31e 4058 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4059 goto out;
4060 r = 0;
4061 break;
4062 };
b93463aa
AK		 4063 case KVM_SET_VAPIC_ADDR: {
4064 struct kvm_vapic_addr va;
7301d6ab 4065 int idx;
b93463aa
AK		 4066
4067 r = -EINVAL;
35754c98 4068 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4069 goto out;
4070 r = -EFAULT;
0e96f31e 4071 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4072 goto out;
7301d6ab 4073 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4074 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4075 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4076 break;
4077 }
890ca9ae
HY		 4078 case KVM_X86_SETUP_MCE: {
4079 u64 mcg_cap;
4080
4081 r = -EFAULT;
0e96f31e 4082 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4083 goto out;
4084 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4085 break;
4086 }
4087 case KVM_X86_SET_MCE: {
4088 struct kvm_x86_mce mce;
4089
4090 r = -EFAULT;
0e96f31e 4091 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4092 goto out;
4093 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4094 break;
4095 }
3cfc3092
JK		 4096 case KVM_GET_VCPU_EVENTS: {
4097 struct kvm_vcpu_events events;
4098
4099 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4100
4101 r = -EFAULT;
4102 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4103 break;
4104 r = 0;
4105 break;
4106 }
4107 case KVM_SET_VCPU_EVENTS: {
4108 struct kvm_vcpu_events events;
4109
4110 r = -EFAULT;
4111 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4112 break;
4113
4114 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4115 break;
4116 }
a1efbe77
JK		 4117 case KVM_GET_DEBUGREGS: {
4118 struct kvm_debugregs dbgregs;
4119
4120 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4121
4122 r = -EFAULT;
4123 if (copy_to_user(argp, &dbgregs,
4124 sizeof(struct kvm_debugregs)))
4125 break;
4126 r = 0;
4127 break;
4128 }
4129 case KVM_SET_DEBUGREGS: {
4130 struct kvm_debugregs dbgregs;
4131
4132 r = -EFAULT;
4133 if (copy_from_user(&dbgregs, argp,
4134 sizeof(struct kvm_debugregs)))
4135 break;
4136
4137 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4138 break;
4139 }
2d5b5a66 4140 case KVM_GET_XSAVE: {
254272ce 4141 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4142 r = -ENOMEM;
d1ac91d8 4143 if (!u.xsave)
2d5b5a66
SY		 4144 break;
4145
d1ac91d8 4146 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4147
4148 r = -EFAULT;
d1ac91d8 4149 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4150 break;
4151 r = 0;
4152 break;
4153 }
4154 case KVM_SET_XSAVE: {
ff5c2c03 4155 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4156 if (IS_ERR(u.xsave)) {
4157 r = PTR_ERR(u.xsave);
4158 goto out_nofree;
4159 }
2d5b5a66 4160
d1ac91d8 4161 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4162 break;
4163 }
4164 case KVM_GET_XCRS: {
254272ce 4165 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4166 r = -ENOMEM;
d1ac91d8 4167 if (!u.xcrs)
2d5b5a66
SY		 4168 break;
4169
d1ac91d8 4170 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4171
4172 r = -EFAULT;
d1ac91d8 4173 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4174 sizeof(struct kvm_xcrs)))
4175 break;
4176 r = 0;
4177 break;
4178 }
4179 case KVM_SET_XCRS: {
ff5c2c03 4180 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4181 if (IS_ERR(u.xcrs)) {
4182 r = PTR_ERR(u.xcrs);
4183 goto out_nofree;
4184 }
2d5b5a66 4185
d1ac91d8 4186 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4187 break;
4188 }
92a1f12d
JR		 4189 case KVM_SET_TSC_KHZ: {
4190 u32 user_tsc_khz;
4191
4192 r = -EINVAL;
92a1f12d
JR		 4193 user_tsc_khz = (u32)arg;
4194
4195 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4196 goto out;
4197
cc578287
ZA		 4198 if (user_tsc_khz == 0)
4199 user_tsc_khz = tsc_khz;
4200
381d585c
HZ		 4201 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4202 r = 0;
92a1f12d 4203
92a1f12d
JR		 4204 goto out;
4205 }
4206 case KVM_GET_TSC_KHZ: {
cc578287 4207 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4208 goto out;
4209 }
1c0b28c2
EM		 4210 case KVM_KVMCLOCK_CTRL: {
4211 r = kvm_set_guest_paused(vcpu);
4212 goto out;
4213 }
5c919412
AS		 4214 case KVM_ENABLE_CAP: {
4215 struct kvm_enable_cap cap;
4216
4217 r = -EFAULT;
4218 if (copy_from_user(&cap, argp, sizeof(cap)))
4219 goto out;
4220 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4221 break;
4222 }
8fcc4b59
JM		 4223 case KVM_GET_NESTED_STATE: {
4224 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4225 u32 user_data_size;
4226
4227 r = -EINVAL;
4228 if (!kvm_x86_ops->get_nested_state)
4229 break;
4230
4231 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4232 r = -EFAULT;
8fcc4b59 4233 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4234 break;
8fcc4b59
JM		 4235
4236 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4237 user_data_size);
4238 if (r < 0)
26b471c7 4239 break;
8fcc4b59
JM		 4240
4241 if (r > user_data_size) {
4242 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4243 r = -EFAULT;
4244 else
4245 r = -E2BIG;
4246 break;
8fcc4b59 4247 }
26b471c7 4248
8fcc4b59
JM		 4249 r = 0;
4250 break;
4251 }
4252 case KVM_SET_NESTED_STATE: {
4253 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4254 struct kvm_nested_state kvm_state;
4255
4256 r = -EINVAL;
4257 if (!kvm_x86_ops->set_nested_state)
4258 break;
4259
26b471c7 4260 r = -EFAULT;
8fcc4b59 4261 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4262 break;
8fcc4b59 4263
26b471c7 4264 r = -EINVAL;
8fcc4b59 4265 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4266 break;
8fcc4b59
JM		 4267
4268 if (kvm_state.flags &
8cab6507
VK		 4269 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4270 | KVM_STATE_NESTED_EVMCS))
26b471c7 4271 break;
8fcc4b59
JM		 4272
4273 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4274 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4275 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4276 break;
8fcc4b59
JM		 4277
4278 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4279 break;
4280 }
2bc39970
VK		 4281 case KVM_GET_SUPPORTED_HV_CPUID: {
4282 struct kvm_cpuid2 __user *cpuid_arg = argp;
4283 struct kvm_cpuid2 cpuid;
4284
4285 r = -EFAULT;
4286 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4287 goto out;
4288
4289 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4290 cpuid_arg->entries);
4291 if (r)
4292 goto out;
4293
4294 r = -EFAULT;
4295 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4296 goto out;
4297 r = 0;
4298 break;
4299 }
313a3dc7
CO		 4300 default:
4301 r = -EINVAL;
4302 }
4303out:
d1ac91d8 4304 kfree(u.buffer);
9b062471
CD		 4305out_nofree:
4306 vcpu_put(vcpu);
313a3dc7
CO		 4307 return r;
4308}
4309
1499fa80 4310vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4311{
4312 return VM_FAULT_SIGBUS;
4313}
4314
1fe779f8
CO		 4315static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4316{
4317 int ret;
4318
4319 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4320 return -EINVAL;
1fe779f8
CO		 4321 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4322 return ret;
4323}
4324
b927a3ce
SY		 4325static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4326 u64 ident_addr)
4327{
2ac52ab8 4328 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4329}
4330
1fe779f8 4331static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4332 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4333{
4334 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4335 return -EINVAL;
4336
79fac95e 4337 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4338
4339 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4340 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4341
79fac95e 4342 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4343 return 0;
4344}
4345
bc8a3d89 4346static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4347{
39de71ec 4348 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4349}
4350
1fe779f8
CO		 4351static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4352{
90bca052 4353 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4354 int r;
4355
4356 r = 0;
4357 switch (chip->chip_id) {
4358 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4359 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4360 sizeof(struct kvm_pic_state));
4361 break;
4362 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4363 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4364 sizeof(struct kvm_pic_state));
4365 break;
4366 case KVM_IRQCHIP_IOAPIC:
33392b49 4367 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4368 break;
4369 default:
4370 r = -EINVAL;
4371 break;
4372 }
4373 return r;
4374}
4375
4376static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4377{
90bca052 4378 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4379 int r;
4380
4381 r = 0;
4382 switch (chip->chip_id) {
4383 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4384 spin_lock(&pic->lock);
4385 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4386 sizeof(struct kvm_pic_state));
90bca052 4387 spin_unlock(&pic->lock);
1fe779f8
CO		 4388 break;
4389 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4390 spin_lock(&pic->lock);
4391 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4392 sizeof(struct kvm_pic_state));
90bca052 4393 spin_unlock(&pic->lock);
1fe779f8
CO		 4394 break;
4395 case KVM_IRQCHIP_IOAPIC:
33392b49 4396 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4397 break;
4398 default:
4399 r = -EINVAL;
4400 break;
4401 }
90bca052 4402 kvm_pic_update_irq(pic);
1fe779f8
CO		 4403 return r;
4404}
4405
e0f63cb9
SY		 4406static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4407{
34f3941c
RK		 4408 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4409
4410 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4411
4412 mutex_lock(&kps->lock);
4413 memcpy(ps, &kps->channels, sizeof(*ps));
4414 mutex_unlock(&kps->lock);
2da29bcc 4415 return 0;
e0f63cb9
SY		 4416}
4417
4418static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4419{
0185604c 4420 int i;
09edea72
RK		 4421 struct kvm_pit *pit = kvm->arch.vpit;
4422
4423 mutex_lock(&pit->pit_state.lock);
34f3941c 4424 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4425 for (i = 0; i < 3; i++)
09edea72
RK		 4426 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4427 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4428 return 0;
e9f42757
BK		 4429}
4430
4431static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4432{
e9f42757
BK		 4433 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4434 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4435 sizeof(ps->channels));
4436 ps->flags = kvm->arch.vpit->pit_state.flags;
4437 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4438 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4439 return 0;
e9f42757
BK		 4440}
4441
4442static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4443{
2da29bcc 4444 int start = 0;
0185604c 4445 int i;
e9f42757 4446 u32 prev_legacy, cur_legacy;
09edea72
RK		 4447 struct kvm_pit *pit = kvm->arch.vpit;
4448
4449 mutex_lock(&pit->pit_state.lock);
4450 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4451 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4452 if (!prev_legacy && cur_legacy)
4453 start = 1;
09edea72
RK		 4454 memcpy(&pit->pit_state.channels, &ps->channels,
4455 sizeof(pit->pit_state.channels));
4456 pit->pit_state.flags = ps->flags;
0185604c 4457 for (i = 0; i < 3; i++)
09edea72 4458 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4459 start && i == 0);
09edea72 4460 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4461 return 0;
e0f63cb9
SY		 4462}
4463
52d939a0
MT		 4464static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4465 struct kvm_reinject_control *control)
4466{
71474e2f
RK		 4467 struct kvm_pit *pit = kvm->arch.vpit;
4468
4469 if (!pit)
52d939a0 4470 return -ENXIO;
b39c90b6 4471
71474e2f
RK		 4472 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4473 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4474 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4475 */
4476 mutex_lock(&pit->pit_state.lock);
4477 kvm_pit_set_reinject(pit, control->pit_reinject);
4478 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4479
52d939a0
MT		 4480 return 0;
4481}
4482
95d4c16c 4483/**
60c34612
TY		 4484 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4485 * @kvm: kvm instance
4486 * @log: slot id and address to which we copy the log
95d4c16c 4487 *
e108ff2f
PB		 4488 * Steps 1-4 below provide general overview of dirty page logging. See
4489 * kvm_get_dirty_log_protect() function description for additional details.
4490 *
4491 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4492 * always flush the TLB (step 4) even if previous step failed and the dirty
4493 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4494 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4495 * writes will be marked dirty for next log read.
95d4c16c 4496 *
60c34612
TY		 4497 * 1. Take a snapshot of the bit and clear it if needed.
4498 * 2. Write protect the corresponding page.
e108ff2f
PB		 4499 * 3. Copy the snapshot to the userspace.
4500 * 4. Flush TLB's if needed.
5bb064dc 4501 */
60c34612 4502int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4503{
8fe65a82 4504 bool flush = false;
e108ff2f 4505 int r;
5bb064dc 4506
79fac95e 4507 mutex_lock(&kvm->slots_lock);
5bb064dc 4508
88178fd4
KH		 4509 /*
4510 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4511 */
4512 if (kvm_x86_ops->flush_log_dirty)
4513 kvm_x86_ops->flush_log_dirty(kvm);
4514
8fe65a82 4515 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4516
4517 /*
4518 * All the TLBs can be flushed out of mmu lock, see the comments in
4519 * kvm_mmu_slot_remove_write_access().
4520 */
e108ff2f 4521 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4522 if (flush)
2a31b9db
PB		 4523 kvm_flush_remote_tlbs(kvm);
4524
4525 mutex_unlock(&kvm->slots_lock);
4526 return r;
4527}
4528
4529int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4530{
4531 bool flush = false;
4532 int r;
4533
4534 mutex_lock(&kvm->slots_lock);
4535
4536 /*
4537 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4538 */
4539 if (kvm_x86_ops->flush_log_dirty)
4540 kvm_x86_ops->flush_log_dirty(kvm);
4541
4542 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4543
4544 /*
4545 * All the TLBs can be flushed out of mmu lock, see the comments in
4546 * kvm_mmu_slot_remove_write_access().
4547 */
4548 lockdep_assert_held(&kvm->slots_lock);
4549 if (flush)
198c74f4
XG		 4550 kvm_flush_remote_tlbs(kvm);
4551
79fac95e 4552 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4553 return r;
4554}
4555
aa2fbe6d
YZ		 4556int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4557 bool line_status)
23d43cf9
CD		 4558{
4559 if (!irqchip_in_kernel(kvm))
4560 return -ENXIO;
4561
4562 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4563 irq_event->irq, irq_event->level,
4564 line_status);
23d43cf9
CD		 4565 return 0;
4566}
4567
e5d83c74
PB		 4568int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4569 struct kvm_enable_cap *cap)
90de4a18
NA		 4570{
4571 int r;
4572
4573 if (cap->flags)
4574 return -EINVAL;
4575
4576 switch (cap->cap) {
4577 case KVM_CAP_DISABLE_QUIRKS:
4578 kvm->arch.disabled_quirks = cap->args[0];
4579 r = 0;
4580 break;
49df6397
SR		 4581 case KVM_CAP_SPLIT_IRQCHIP: {
4582 mutex_lock(&kvm->lock);
b053b2ae
SR		 4583 r = -EINVAL;
4584 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4585 goto split_irqchip_unlock;
49df6397
SR		 4586 r = -EEXIST;
4587 if (irqchip_in_kernel(kvm))
4588 goto split_irqchip_unlock;
557abc40 4589 if (kvm->created_vcpus)
49df6397
SR		 4590 goto split_irqchip_unlock;
4591 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4592 if (r)
49df6397
SR		 4593 goto split_irqchip_unlock;
4594 /* Pairs with irqchip_in_kernel. */
4595 smp_wmb();
49776faf 4596 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4597 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4598 r = 0;
4599split_irqchip_unlock:
4600 mutex_unlock(&kvm->lock);
4601 break;
4602 }
37131313
RK		 4603 case KVM_CAP_X2APIC_API:
4604 r = -EINVAL;
4605 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4606 break;
4607
4608 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4609 kvm->arch.x2apic_format = true;
c519265f
RK		 4610 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4611 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4612
4613 r = 0;
4614 break;
4d5422ce
WL		 4615 case KVM_CAP_X86_DISABLE_EXITS:
4616 r = -EINVAL;
4617 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4618 break;
4619
4620 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4621 kvm_can_mwait_in_guest())
4622 kvm->arch.mwait_in_guest = true;
766d3571 4623 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4624 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4625 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4626 kvm->arch.pause_in_guest = true;
b5170063
WL		 4627 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4628 kvm->arch.cstate_in_guest = true;
4d5422ce
WL		 4629 r = 0;
4630 break;
6fbbde9a
DS		 4631 case KVM_CAP_MSR_PLATFORM_INFO:
4632 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4633 r = 0;
c4f55198
JM		 4634 break;
4635 case KVM_CAP_EXCEPTION_PAYLOAD:
4636 kvm->arch.exception_payload_enabled = cap->args[0];
4637 r = 0;
6fbbde9a 4638 break;
90de4a18
NA		 4639 default:
4640 r = -EINVAL;
4641 break;
4642 }
4643 return r;
4644}
4645
1fe779f8
CO		 4646long kvm_arch_vm_ioctl(struct file *filp,
4647 unsigned int ioctl, unsigned long arg)
4648{
4649 struct kvm *kvm = filp->private_data;
4650 void __user *argp = (void __user *)arg;
367e1319 4651 int r = -ENOTTY;
f0d66275
DH		 4652 /*
4653 * This union makes it completely explicit to gcc-3.x
4654 * that these two variables' stack usage should be
4655 * combined, not added together.
4656 */
4657 union {
4658 struct kvm_pit_state ps;
e9f42757 4659 struct kvm_pit_state2 ps2;
c5ff41ce 4660 struct kvm_pit_config pit_config;
f0d66275 4661 } u;
1fe779f8
CO		 4662
4663 switch (ioctl) {
4664 case KVM_SET_TSS_ADDR:
4665 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4666 break;
b927a3ce
SY		 4667 case KVM_SET_IDENTITY_MAP_ADDR: {
4668 u64 ident_addr;
4669
1af1ac91
DH		 4670 mutex_lock(&kvm->lock);
4671 r = -EINVAL;
4672 if (kvm->created_vcpus)
4673 goto set_identity_unlock;
b927a3ce 4674 r = -EFAULT;
0e96f31e 4675 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4676 goto set_identity_unlock;
b927a3ce 4677 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4678set_identity_unlock:
4679 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4680 break;
4681 }
1fe779f8
CO		 4682 case KVM_SET_NR_MMU_PAGES:
4683 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4684 break;
4685 case KVM_GET_NR_MMU_PAGES:
4686 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4687 break;
3ddea128 4688 case KVM_CREATE_IRQCHIP: {
3ddea128 4689 mutex_lock(&kvm->lock);
09941366 4690
3ddea128 4691 r = -EEXIST;
35e6eaa3 4692 if (irqchip_in_kernel(kvm))
3ddea128 4693 goto create_irqchip_unlock;
09941366 4694
3e515705 4695 r = -EINVAL;
557abc40 4696 if (kvm->created_vcpus)
3e515705 4697 goto create_irqchip_unlock;
09941366
RK		 4698
4699 r = kvm_pic_init(kvm);
4700 if (r)
3ddea128 4701 goto create_irqchip_unlock;
09941366
RK		 4702
4703 r = kvm_ioapic_init(kvm);
4704 if (r) {
09941366 4705 kvm_pic_destroy(kvm);
3ddea128 4706 goto create_irqchip_unlock;
09941366
RK		 4707 }
4708
399ec807
AK		 4709 r = kvm_setup_default_irq_routing(kvm);
4710 if (r) {
72bb2fcd 4711 kvm_ioapic_destroy(kvm);
09941366 4712 kvm_pic_destroy(kvm);
71ba994c 4713 goto create_irqchip_unlock;
399ec807 4714 }
49776faf 4715 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4716 smp_wmb();
49776faf 4717 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4718 create_irqchip_unlock:
4719 mutex_unlock(&kvm->lock);
1fe779f8 4720 break;
3ddea128 4721 }
7837699f 4722 case KVM_CREATE_PIT:
c5ff41ce
JK		 4723 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4724 goto create_pit;
4725 case KVM_CREATE_PIT2:
4726 r = -EFAULT;
4727 if (copy_from_user(&u.pit_config, argp,
4728 sizeof(struct kvm_pit_config)))
4729 goto out;
4730 create_pit:
250715a6 4731 mutex_lock(&kvm->lock);
269e05e4
AK		 4732 r = -EEXIST;
4733 if (kvm->arch.vpit)
4734 goto create_pit_unlock;
7837699f 4735 r = -ENOMEM;
c5ff41ce 4736 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4737 if (kvm->arch.vpit)
4738 r = 0;
269e05e4 4739 create_pit_unlock:
250715a6 4740 mutex_unlock(&kvm->lock);
7837699f 4741 break;
1fe779f8
CO		 4742 case KVM_GET_IRQCHIP: {
4743 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4744 struct kvm_irqchip *chip;
1fe779f8 4745
ff5c2c03
SL		 4746 chip = memdup_user(argp, sizeof(*chip));
4747 if (IS_ERR(chip)) {
4748 r = PTR_ERR(chip);
1fe779f8 4749 goto out;
ff5c2c03
SL		 4750 }
4751
1fe779f8 4752 r = -ENXIO;
826da321 4753 if (!irqchip_kernel(kvm))
f0d66275
DH		 4754 goto get_irqchip_out;
4755 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4756 if (r)
f0d66275 4757 goto get_irqchip_out;
1fe779f8 4758 r = -EFAULT;
0e96f31e 4759 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4760 goto get_irqchip_out;
1fe779f8 4761 r = 0;
f0d66275
DH		 4762 get_irqchip_out:
4763 kfree(chip);
1fe779f8
CO		 4764 break;
4765 }
4766 case KVM_SET_IRQCHIP: {
4767 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4768 struct kvm_irqchip *chip;
1fe779f8 4769
ff5c2c03
SL		 4770 chip = memdup_user(argp, sizeof(*chip));
4771 if (IS_ERR(chip)) {
4772 r = PTR_ERR(chip);
1fe779f8 4773 goto out;
ff5c2c03
SL		 4774 }
4775
1fe779f8 4776 r = -ENXIO;
826da321 4777 if (!irqchip_kernel(kvm))
f0d66275
DH		 4778 goto set_irqchip_out;
4779 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4780 if (r)
f0d66275 4781 goto set_irqchip_out;
1fe779f8 4782 r = 0;
f0d66275
DH		 4783 set_irqchip_out:
4784 kfree(chip);
1fe779f8
CO		 4785 break;
4786 }
e0f63cb9 4787 case KVM_GET_PIT: {
e0f63cb9 4788 r = -EFAULT;
f0d66275 4789 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4790 goto out;
4791 r = -ENXIO;
4792 if (!kvm->arch.vpit)
4793 goto out;
f0d66275 4794 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4795 if (r)
4796 goto out;
4797 r = -EFAULT;
f0d66275 4798 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4799 goto out;
4800 r = 0;
4801 break;
4802 }
4803 case KVM_SET_PIT: {
e0f63cb9 4804 r = -EFAULT;
0e96f31e 4805 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4806 goto out;
4807 r = -ENXIO;
4808 if (!kvm->arch.vpit)
4809 goto out;
f0d66275 4810 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4811 break;
4812 }
e9f42757
BK		 4813 case KVM_GET_PIT2: {
4814 r = -ENXIO;
4815 if (!kvm->arch.vpit)
4816 goto out;
4817 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4818 if (r)
4819 goto out;
4820 r = -EFAULT;
4821 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4822 goto out;
4823 r = 0;
4824 break;
4825 }
4826 case KVM_SET_PIT2: {
4827 r = -EFAULT;
4828 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4829 goto out;
4830 r = -ENXIO;
4831 if (!kvm->arch.vpit)
4832 goto out;
4833 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4834 break;
4835 }
52d939a0
MT		 4836 case KVM_REINJECT_CONTROL: {
4837 struct kvm_reinject_control control;
4838 r = -EFAULT;
4839 if (copy_from_user(&control, argp, sizeof(control)))
4840 goto out;
4841 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4842 break;
4843 }
d71ba788
PB		 4844 case KVM_SET_BOOT_CPU_ID:
4845 r = 0;
4846 mutex_lock(&kvm->lock);
557abc40 4847 if (kvm->created_vcpus)
d71ba788
PB		 4848 r = -EBUSY;
4849 else
4850 kvm->arch.bsp_vcpu_id = arg;
4851 mutex_unlock(&kvm->lock);
4852 break;
ffde22ac 4853 case KVM_XEN_HVM_CONFIG: {
51776043 4854 struct kvm_xen_hvm_config xhc;
ffde22ac 4855 r = -EFAULT;
51776043 4856 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4857 goto out;
4858 r = -EINVAL;
51776043 4859 if (xhc.flags)
ffde22ac 4860 goto out;
51776043 4861 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4862 r = 0;
4863 break;
4864 }
afbcf7ab 4865 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4866 struct kvm_clock_data user_ns;
4867 u64 now_ns;
afbcf7ab
GC		 4868
4869 r = -EFAULT;
4870 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4871 goto out;
4872
4873 r = -EINVAL;
4874 if (user_ns.flags)
4875 goto out;
4876
4877 r = 0;
0bc48bea
RK		 4878 /*
4879 * TODO: userspace has to take care of races with VCPU_RUN, so
4880 * kvm_gen_update_masterclock() can be cut down to locked
4881 * pvclock_update_vm_gtod_copy().
4882 */
4883 kvm_gen_update_masterclock(kvm);
e891a32e 4884 now_ns = get_kvmclock_ns(kvm);
108b249c 4885 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4886 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4887 break;
4888 }
4889 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4890 struct kvm_clock_data user_ns;
4891 u64 now_ns;
4892
e891a32e 4893 now_ns = get_kvmclock_ns(kvm);
108b249c 4894 user_ns.clock = now_ns;
e3fd9a93 4895 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4896 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4897
4898 r = -EFAULT;
4899 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4900 goto out;
4901 r = 0;
4902 break;
4903 }
5acc5c06
BS		 4904 case KVM_MEMORY_ENCRYPT_OP: {
4905 r = -ENOTTY;
4906 if (kvm_x86_ops->mem_enc_op)
4907 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4908 break;
4909 }
69eaedee
BS		 4910 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4911 struct kvm_enc_region region;
4912
4913 r = -EFAULT;
4914 if (copy_from_user(&region, argp, sizeof(region)))
4915 goto out;
4916
4917 r = -ENOTTY;
4918 if (kvm_x86_ops->mem_enc_reg_region)
4919 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4920 break;
4921 }
4922 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4923 struct kvm_enc_region region;
4924
4925 r = -EFAULT;
4926 if (copy_from_user(&region, argp, sizeof(region)))
4927 goto out;
4928
4929 r = -ENOTTY;
4930 if (kvm_x86_ops->mem_enc_unreg_region)
4931 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4932 break;
4933 }
faeb7833
RK		 4934 case KVM_HYPERV_EVENTFD: {
4935 struct kvm_hyperv_eventfd hvevfd;
4936
4937 r = -EFAULT;
4938 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4939 goto out;
4940 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4941 break;
4942 }
1fe779f8 4943 default:
ad6260da 4944 r = -ENOTTY;
1fe779f8
CO		 4945 }
4946out:
4947 return r;
4948}
4949
a16b043c 4950static void kvm_init_msr_list(void)
043405e1
CO		 4951{
4952 u32 dummy[2];
4953 unsigned i, j;
4954
62ef68bb 4955 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4956 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4957 continue;
93c4adc7
PB		 4958
4959 /*
4960 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4961 * to the guests in some cases.
93c4adc7
PB		 4962 */
4963 switch (msrs_to_save[i]) {
4964 case MSR_IA32_BNDCFGS:
503234b3 4965 if (!kvm_mpx_supported())
93c4adc7
PB		 4966 continue;
4967 break;
9dbe6cf9
PB		 4968 case MSR_TSC_AUX:
4969 if (!kvm_x86_ops->rdtscp_supported())
4970 continue;
4971 break;
bf8c55d8
CP		 4972 case MSR_IA32_RTIT_CTL:
4973 case MSR_IA32_RTIT_STATUS:
4974 if (!kvm_x86_ops->pt_supported())
4975 continue;
4976 break;
4977 case MSR_IA32_RTIT_CR3_MATCH:
4978 if (!kvm_x86_ops->pt_supported() ||
4979 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
4980 continue;
4981 break;
4982 case MSR_IA32_RTIT_OUTPUT_BASE:
4983 case MSR_IA32_RTIT_OUTPUT_MASK:
4984 if (!kvm_x86_ops->pt_supported() ||
4985 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
4986 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
4987 continue;
4988 break;
4989 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
4990 if (!kvm_x86_ops->pt_supported() ||
4991 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
4992 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
4993 continue;
4994 break;
4995 }
93c4adc7
PB		 4996 default:
4997 break;
4998 }
4999
043405e1
CO		 5000 if (j < i)
5001 msrs_to_save[j] = msrs_to_save[i];
5002 j++;
5003 }
5004 num_msrs_to_save = j;
62ef68bb
PB		 5005
5006 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 5007 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5008 continue;
62ef68bb
PB		 5009
5010 if (j < i)
5011 emulated_msrs[j] = emulated_msrs[i];
5012 j++;
5013 }
5014 num_emulated_msrs = j;
801e459a
TL		 5015
5016 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5017 struct kvm_msr_entry msr;
5018
5019 msr.index = msr_based_features[i];
66421c1e 5020 if (kvm_get_msr_feature(&msr))
801e459a
TL		 5021 continue;
5022
5023 if (j < i)
5024 msr_based_features[j] = msr_based_features[i];
5025 j++;
5026 }
5027 num_msr_based_features = j;
043405e1
CO		 5028}
5029
bda9020e
MT		 5030static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5031 const void *v)
bbd9b64e 5032{
70252a10
AK		 5033 int handled = 0;
5034 int n;
5035
5036 do {
5037 n = min(len, 8);
bce87cce 5038 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5039 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5040 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 5041 break;
5042 handled += n;
5043 addr += n;
5044 len -= n;
5045 v += n;
5046 } while (len);
bbd9b64e 5047
70252a10 5048 return handled;
bbd9b64e
CO		 5049}
5050
bda9020e 5051static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 5052{
70252a10
AK		 5053 int handled = 0;
5054 int n;
5055
5056 do {
5057 n = min(len, 8);
bce87cce 5058 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5059 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5060 addr, n, v))
5061 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5062 break;
e39d200f 5063 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5064 handled += n;
5065 addr += n;
5066 len -= n;
5067 v += n;
5068 } while (len);
bbd9b64e 5069
70252a10 5070 return handled;
bbd9b64e
CO		 5071}
5072
2dafc6c2
GN		 5073static void kvm_set_segment(struct kvm_vcpu *vcpu,
5074 struct kvm_segment *var, int seg)
5075{
5076 kvm_x86_ops->set_segment(vcpu, var, seg);
5077}
5078
5079void kvm_get_segment(struct kvm_vcpu *vcpu,
5080 struct kvm_segment *var, int seg)
5081{
5082 kvm_x86_ops->get_segment(vcpu, var, seg);
5083}
5084
54987b7a
PB		 5085gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5086 struct x86_exception *exception)
02f59dc9
JR		 5087{
5088 gpa_t t_gpa;
02f59dc9
JR		 5089
5090 BUG_ON(!mmu_is_nested(vcpu));
5091
5092 /* NPT walks are always user-walks */
5093 access |= PFERR_USER_MASK;
44dd3ffa 5094 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5095
5096 return t_gpa;
5097}
5098
ab9ae313
AK		 5099gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5100 struct x86_exception *exception)
1871c602
GN		 5101{
5102 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5103 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5104}
5105
ab9ae313
AK		 5106 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5107 struct x86_exception *exception)
1871c602
GN		 5108{
5109 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5110 access |= PFERR_FETCH_MASK;
ab9ae313 5111 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5112}
5113
ab9ae313
AK		 5114gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5115 struct x86_exception *exception)
1871c602
GN		 5116{
5117 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5118 access |= PFERR_WRITE_MASK;
ab9ae313 5119 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5120}
5121
5122/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5123gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5124 struct x86_exception *exception)
1871c602 5125{
ab9ae313 5126 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5127}
5128
5129static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5130 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5131 struct x86_exception *exception)
bbd9b64e
CO		 5132{
5133 void *data = val;
10589a46 5134 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5135
5136 while (bytes) {
14dfe855 5137 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5138 exception);
bbd9b64e 5139 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5140 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5141 int ret;
5142
bcc55cba 5143 if (gpa == UNMAPPED_GVA)
ab9ae313 5144 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5145 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5146 offset, toread);
10589a46 5147 if (ret < 0) {
c3cd7ffa 5148 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5149 goto out;
5150 }
bbd9b64e 5151
77c2002e
IE		 5152 bytes -= toread;
5153 data += toread;
5154 addr += toread;
bbd9b64e 5155 }
10589a46 5156out:
10589a46 5157 return r;
bbd9b64e 5158}
77c2002e 5159
1871c602 5160/* used for instruction fetching */
0f65dd70
AK		 5161static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5162 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5163 struct x86_exception *exception)
1871c602 5164{
0f65dd70 5165 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5166 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5167 unsigned offset;
5168 int ret;
0f65dd70 5169
44583cba
PB		 5170 /* Inline kvm_read_guest_virt_helper for speed. */
5171 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5172 exception);
5173 if (unlikely(gpa == UNMAPPED_GVA))
5174 return X86EMUL_PROPAGATE_FAULT;
5175
5176 offset = addr & (PAGE_SIZE-1);
5177 if (WARN_ON(offset + bytes > PAGE_SIZE))
5178 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5179 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5180 offset, bytes);
44583cba
PB		 5181 if (unlikely(ret < 0))
5182 return X86EMUL_IO_NEEDED;
5183
5184 return X86EMUL_CONTINUE;
1871c602
GN		 5185}
5186
ce14e868 5187int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5188 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5189 struct x86_exception *exception)
1871c602
GN		 5190{
5191 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5192
353c0956
PB		 5193 /*
5194 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5195 * is returned, but our callers are not ready for that and they blindly
5196 * call kvm_inject_page_fault. Ensure that they at least do not leak
5197 * uninitialized kernel stack memory into cr2 and error code.
5198 */
5199 memset(exception, 0, sizeof(*exception));
1871c602 5200 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5201 exception);
1871c602 5202}
064aea77 5203EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5204
ce14e868
PB		 5205static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5206 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5207 struct x86_exception *exception, bool system)
1871c602 5208{
0f65dd70 5209 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5210 u32 access = 0;
5211
5212 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5213 access |= PFERR_USER_MASK;
5214
5215 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5216}
5217
7a036a6f
RK		 5218static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5219 unsigned long addr, void *val, unsigned int bytes)
5220{
5221 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5222 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5223
5224 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5225}
5226
ce14e868
PB		 5227static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5228 struct kvm_vcpu *vcpu, u32 access,
5229 struct x86_exception *exception)
77c2002e
IE		 5230{
5231 void *data = val;
5232 int r = X86EMUL_CONTINUE;
5233
5234 while (bytes) {
14dfe855 5235 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5236 access,
ab9ae313 5237 exception);
77c2002e
IE		 5238 unsigned offset = addr & (PAGE_SIZE-1);
5239 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5240 int ret;
5241
bcc55cba 5242 if (gpa == UNMAPPED_GVA)
ab9ae313 5243 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5244 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5245 if (ret < 0) {
c3cd7ffa 5246 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5247 goto out;
5248 }
5249
5250 bytes -= towrite;
5251 data += towrite;
5252 addr += towrite;
5253 }
5254out:
5255 return r;
5256}
ce14e868
PB		 5257
5258static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5259 unsigned int bytes, struct x86_exception *exception,
5260 bool system)
ce14e868
PB		 5261{
5262 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5263 u32 access = PFERR_WRITE_MASK;
5264
5265 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5266 access |= PFERR_USER_MASK;
ce14e868
PB		 5267
5268 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5269 access, exception);
ce14e868
PB		 5270}
5271
5272int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5273 unsigned int bytes, struct x86_exception *exception)
5274{
c595ceee
PB		 5275 /* kvm_write_guest_virt_system can pull in tons of pages. */
5276 vcpu->arch.l1tf_flush_l1d = true;
5277
ce14e868
PB		 5278 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5279 PFERR_WRITE_MASK, exception);
5280}
6a4d7550 5281EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5282
082d06ed
WL		 5283int handle_ud(struct kvm_vcpu *vcpu)
5284{
6c86eedc 5285 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5286 enum emulation_result er;
6c86eedc
WL		 5287 char sig[5]; /* ud2; .ascii "kvm" */
5288 struct x86_exception e;
5289
5290 if (force_emulation_prefix &&
3c9fa24c
PB		 5291 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5292 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5293 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5294 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5295 emul_type = 0;
5296 }
082d06ed 5297
0ce97a2b 5298 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5299 if (er == EMULATE_USER_EXIT)
5300 return 0;
5301 if (er != EMULATE_DONE)
5302 kvm_queue_exception(vcpu, UD_VECTOR);
5303 return 1;
5304}
5305EXPORT_SYMBOL_GPL(handle_ud);
5306
0f89b207
TL		 5307static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5308 gpa_t gpa, bool write)
5309{
5310 /* For APIC access vmexit */
5311 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5312 return 1;
5313
5314 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5315 trace_vcpu_match_mmio(gva, gpa, write, true);
5316 return 1;
5317 }
5318
5319 return 0;
5320}
5321
af7cc7d1
XG		 5322static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5323 gpa_t *gpa, struct x86_exception *exception,
5324 bool write)
5325{
97d64b78
AK		 5326 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5327 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5328
be94f6b7
HH		 5329 /*
5330 * currently PKRU is only applied to ept enabled guest so
5331 * there is no pkey in EPT page table for L1 guest or EPT
5332 * shadow page table for L2 guest.
5333 */
97d64b78 5334 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5335 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5336 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5337 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5338 (gva & (PAGE_SIZE - 1));
4f022648 5339 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5340 return 1;
5341 }
5342
af7cc7d1
XG		 5343 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5344
5345 if (*gpa == UNMAPPED_GVA)
5346 return -1;
5347
0f89b207 5348 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5349}
5350
3200f405 5351int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5352 const void *val, int bytes)
bbd9b64e
CO		 5353{
5354 int ret;
5355
54bf36aa 5356 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5357 if (ret < 0)
bbd9b64e 5358 return 0;
0eb05bf2 5359 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5360 return 1;
5361}
5362
77d197b2
XG		 5363struct read_write_emulator_ops {
5364 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5365 int bytes);
5366 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5367 void *val, int bytes);
5368 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5369 int bytes, void *val);
5370 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5371 void *val, int bytes);
5372 bool write;
5373};
5374
5375static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5376{
5377 if (vcpu->mmio_read_completed) {
77d197b2 5378 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5379 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5380 vcpu->mmio_read_completed = 0;
5381 return 1;
5382 }
5383
5384 return 0;
5385}
5386
5387static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5388 void *val, int bytes)
5389{
54bf36aa 5390 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5391}
5392
5393static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5394 void *val, int bytes)
5395{
5396 return emulator_write_phys(vcpu, gpa, val, bytes);
5397}
5398
5399static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5400{
e39d200f 5401 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5402 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5403}
5404
5405static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5406 void *val, int bytes)
5407{
e39d200f 5408 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5409 return X86EMUL_IO_NEEDED;
5410}
5411
5412static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5413 void *val, int bytes)
5414{
f78146b0
AK		 5415 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5416
87da7e66 5417 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5418 return X86EMUL_CONTINUE;
5419}
5420
0fbe9b0b 5421static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5422 .read_write_prepare = read_prepare,
5423 .read_write_emulate = read_emulate,
5424 .read_write_mmio = vcpu_mmio_read,
5425 .read_write_exit_mmio = read_exit_mmio,
5426};
5427
0fbe9b0b 5428static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5429 .read_write_emulate = write_emulate,
5430 .read_write_mmio = write_mmio,
5431 .read_write_exit_mmio = write_exit_mmio,
5432 .write = true,
5433};
5434
22388a3c
XG		 5435static int emulator_read_write_onepage(unsigned long addr, void *val,
5436 unsigned int bytes,
5437 struct x86_exception *exception,
5438 struct kvm_vcpu *vcpu,
0fbe9b0b 5439 const struct read_write_emulator_ops *ops)
bbd9b64e 5440{
af7cc7d1
XG		 5441 gpa_t gpa;
5442 int handled, ret;
22388a3c 5443 bool write = ops->write;
f78146b0 5444 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5445 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5446
5447 /*
5448 * If the exit was due to a NPF we may already have a GPA.
5449 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5450 * Note, this cannot be used on string operations since string
5451 * operation using rep will only have the initial GPA from the NPF
5452 * occurred.
5453 */
5454 if (vcpu->arch.gpa_available &&
5455 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5456 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5457 gpa = vcpu->arch.gpa_val;
5458 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5459 } else {
5460 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5461 if (ret < 0)
5462 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5463 }
10589a46 5464
618232e2 5465 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5466 return X86EMUL_CONTINUE;
5467
bbd9b64e
CO		 5468 /*
5469 * Is this MMIO handled locally?
5470 */
22388a3c 5471 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5472 if (handled == bytes)
bbd9b64e 5473 return X86EMUL_CONTINUE;
bbd9b64e 5474
70252a10
AK		 5475 gpa += handled;
5476 bytes -= handled;
5477 val += handled;
5478
87da7e66
XG		 5479 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5480 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5481 frag->gpa = gpa;
5482 frag->data = val;
5483 frag->len = bytes;
f78146b0 5484 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5485}
5486
52eb5a6d
XL		 5487static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5488 unsigned long addr,
22388a3c
XG		 5489 void *val, unsigned int bytes,
5490 struct x86_exception *exception,
0fbe9b0b 5491 const struct read_write_emulator_ops *ops)
bbd9b64e 5492{
0f65dd70 5493 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5494 gpa_t gpa;
5495 int rc;
5496
5497 if (ops->read_write_prepare &&
5498 ops->read_write_prepare(vcpu, val, bytes))
5499 return X86EMUL_CONTINUE;
5500
5501 vcpu->mmio_nr_fragments = 0;
0f65dd70 5502
bbd9b64e
CO		 5503 /* Crossing a page boundary? */
5504 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5505 int now;
bbd9b64e
CO		 5506
5507 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5508 rc = emulator_read_write_onepage(addr, val, now, exception,
5509 vcpu, ops);
5510
bbd9b64e
CO		 5511 if (rc != X86EMUL_CONTINUE)
5512 return rc;
5513 addr += now;
bac15531
NA		 5514 if (ctxt->mode != X86EMUL_MODE_PROT64)
5515 addr = (u32)addr;
bbd9b64e
CO		 5516 val += now;
5517 bytes -= now;
5518 }
22388a3c 5519
f78146b0
AK		 5520 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5521 vcpu, ops);
5522 if (rc != X86EMUL_CONTINUE)
5523 return rc;
5524
5525 if (!vcpu->mmio_nr_fragments)
5526 return rc;
5527
5528 gpa = vcpu->mmio_fragments[0].gpa;
5529
5530 vcpu->mmio_needed = 1;
5531 vcpu->mmio_cur_fragment = 0;
5532
87da7e66 5533 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5534 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5535 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5536 vcpu->run->mmio.phys_addr = gpa;
5537
5538 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5539}
5540
5541static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5542 unsigned long addr,
5543 void *val,
5544 unsigned int bytes,
5545 struct x86_exception *exception)
5546{
5547 return emulator_read_write(ctxt, addr, val, bytes,
5548 exception, &read_emultor);
5549}
5550
52eb5a6d 5551static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5552 unsigned long addr,
5553 const void *val,
5554 unsigned int bytes,
5555 struct x86_exception *exception)
5556{
5557 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5558 exception, &write_emultor);
bbd9b64e 5559}
bbd9b64e 5560
daea3e73
AK		 5561#define CMPXCHG_TYPE(t, ptr, old, new) \
5562 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5563
5564#ifdef CONFIG_X86_64
5565# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5566#else
5567# define CMPXCHG64(ptr, old, new) \
9749a6c0 5568 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5569#endif
5570
0f65dd70
AK		 5571static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5572 unsigned long addr,
bbd9b64e
CO		 5573 const void *old,
5574 const void *new,
5575 unsigned int bytes,
0f65dd70 5576 struct x86_exception *exception)
bbd9b64e 5577{
42e35f80 5578 struct kvm_host_map map;
0f65dd70 5579 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73 5580 gpa_t gpa;
daea3e73
AK		 5581 char *kaddr;
5582 bool exchanged;
2bacc55c 5583
daea3e73
AK		 5584 /* guests cmpxchg8b have to be emulated atomically */
5585 if (bytes > 8 || (bytes & (bytes - 1)))
5586 goto emul_write;
10589a46 5587
daea3e73 5588 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5589
daea3e73
AK		 5590 if (gpa == UNMAPPED_GVA ||
5591 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5592 goto emul_write;
2bacc55c 5593
daea3e73
AK		 5594 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5595 goto emul_write;
72dc67a6 5596
42e35f80 5597 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
c19b8bd6 5598 goto emul_write;
72dc67a6 5599
42e35f80
KA		 5600 kaddr = map.hva + offset_in_page(gpa);
5601
daea3e73
AK		 5602 switch (bytes) {
5603 case 1:
5604 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5605 break;
5606 case 2:
5607 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5608 break;
5609 case 4:
5610 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5611 break;
5612 case 8:
5613 exchanged = CMPXCHG64(kaddr, old, new);
5614 break;
5615 default:
5616 BUG();
2bacc55c 5617 }
42e35f80
KA		 5618
5619 kvm_vcpu_unmap(vcpu, &map, true);
daea3e73
AK		 5620
5621 if (!exchanged)
5622 return X86EMUL_CMPXCHG_FAILED;
5623
0eb05bf2 5624 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5625
5626 return X86EMUL_CONTINUE;
4a5f48f6 5627
3200f405 5628emul_write:
daea3e73 5629 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5630
0f65dd70 5631 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5632}
5633
cf8f70bf
GN		 5634static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5635{
cbfc6c91 5636 int r = 0, i;
cf8f70bf 5637
cbfc6c91
WL		 5638 for (i = 0; i < vcpu->arch.pio.count; i++) {
5639 if (vcpu->arch.pio.in)
5640 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5641 vcpu->arch.pio.size, pd);
5642 else
5643 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5644 vcpu->arch.pio.port, vcpu->arch.pio.size,
5645 pd);
5646 if (r)
5647 break;
5648 pd += vcpu->arch.pio.size;
5649 }
cf8f70bf
GN		 5650 return r;
5651}
5652
6f6fbe98
XG		 5653static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5654 unsigned short port, void *val,
5655 unsigned int count, bool in)
cf8f70bf 5656{
cf8f70bf 5657 vcpu->arch.pio.port = port;
6f6fbe98 5658 vcpu->arch.pio.in = in;
7972995b 5659 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5660 vcpu->arch.pio.size = size;
5661
5662 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5663 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5664 return 1;
5665 }
5666
5667 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5668 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5669 vcpu->run->io.size = size;
5670 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5671 vcpu->run->io.count = count;
5672 vcpu->run->io.port = port;
5673
5674 return 0;
5675}
5676
6f6fbe98
XG		 5677static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5678 int size, unsigned short port, void *val,
5679 unsigned int count)
cf8f70bf 5680{
ca1d4a9e 5681 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5682 int ret;
ca1d4a9e 5683
6f6fbe98
XG		 5684 if (vcpu->arch.pio.count)
5685 goto data_avail;
cf8f70bf 5686
cbfc6c91
WL		 5687 memset(vcpu->arch.pio_data, 0, size * count);
5688
6f6fbe98
XG		 5689 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5690 if (ret) {
5691data_avail:
5692 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5693 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5694 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5695 return 1;
5696 }
5697
cf8f70bf
GN		 5698 return 0;
5699}
5700
6f6fbe98
XG		 5701static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5702 int size, unsigned short port,
5703 const void *val, unsigned int count)
5704{
5705 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5706
5707 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5708 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5709 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5710}
5711
bbd9b64e
CO		 5712static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5713{
5714 return kvm_x86_ops->get_segment_base(vcpu, seg);
5715}
5716
3cb16fe7 5717static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5718{
3cb16fe7 5719 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5720}
5721
ae6a2375 5722static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5723{
5724 if (!need_emulate_wbinvd(vcpu))
5725 return X86EMUL_CONTINUE;
5726
5727 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5728 int cpu = get_cpu();
5729
5730 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5731 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5732 wbinvd_ipi, NULL, 1);
2eec7343 5733 put_cpu();
f5f48ee1 5734 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5735 } else
5736 wbinvd();
f5f48ee1
SY		 5737 return X86EMUL_CONTINUE;
5738}
5cb56059
JS		 5739
5740int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5741{
6affcbed
KH		 5742 kvm_emulate_wbinvd_noskip(vcpu);
5743 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5744}
f5f48ee1
SY		 5745EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5746
5cb56059
JS		 5747
5748
bcaf5cc5
AK		 5749static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5750{
5cb56059 5751 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5752}
5753
52eb5a6d
XL		 5754static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5755 unsigned long *dest)
bbd9b64e 5756{
16f8a6f9 5757 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5758}
5759
52eb5a6d
XL		 5760static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5761 unsigned long value)
bbd9b64e 5762{
338dbc97 5763
717746e3 5764 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5765}
5766
52a46617 5767static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5768{
52a46617 5769 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5770}
5771
717746e3 5772static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5773{
717746e3 5774 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5775 unsigned long value;
5776
5777 switch (cr) {
5778 case 0:
5779 value = kvm_read_cr0(vcpu);
5780 break;
5781 case 2:
5782 value = vcpu->arch.cr2;
5783 break;
5784 case 3:
9f8fe504 5785 value = kvm_read_cr3(vcpu);
52a46617
GN		 5786 break;
5787 case 4:
5788 value = kvm_read_cr4(vcpu);
5789 break;
5790 case 8:
5791 value = kvm_get_cr8(vcpu);
5792 break;
5793 default:
a737f256 5794 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5795 return 0;
5796 }
5797
5798 return value;
5799}
5800
717746e3 5801static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5802{
717746e3 5803 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5804 int res = 0;
5805
52a46617
GN		 5806 switch (cr) {
5807 case 0:
49a9b07e 5808 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5809 break;
5810 case 2:
5811 vcpu->arch.cr2 = val;
5812 break;
5813 case 3:
2390218b 5814 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5815 break;
5816 case 4:
a83b29c6 5817 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5818 break;
5819 case 8:
eea1cff9 5820 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5821 break;
5822 default:
a737f256 5823 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5824 res = -1;
52a46617 5825 }
0f12244f
GN		 5826
5827 return res;
52a46617
GN		 5828}
5829
717746e3 5830static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5831{
717746e3 5832 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5833}
5834
4bff1e86 5835static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5836{
4bff1e86 5837 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5838}
5839
4bff1e86 5840static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5841{
4bff1e86 5842 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5843}
5844
1ac9d0cf
AK		 5845static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5846{
5847 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5848}
5849
5850static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5851{
5852 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5853}
5854
4bff1e86
AK		 5855static unsigned long emulator_get_cached_segment_base(
5856 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5857{
4bff1e86 5858 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5859}
5860
1aa36616
AK		 5861static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5862 struct desc_struct *desc, u32 *base3,
5863 int seg)
2dafc6c2
GN		 5864{
5865 struct kvm_segment var;
5866
4bff1e86 5867 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5868 *selector = var.selector;
2dafc6c2 5869
378a8b09
GN		 5870 if (var.unusable) {
5871 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5872 if (base3)
5873 *base3 = 0;
2dafc6c2 5874 return false;
378a8b09 5875 }
2dafc6c2
GN		 5876
5877 if (var.g)
5878 var.limit >>= 12;
5879 set_desc_limit(desc, var.limit);
5880 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5881#ifdef CONFIG_X86_64
5882 if (base3)
5883 *base3 = var.base >> 32;
5884#endif
2dafc6c2
GN		 5885 desc->type = var.type;
5886 desc->s = var.s;
5887 desc->dpl = var.dpl;
5888 desc->p = var.present;
5889 desc->avl = var.avl;
5890 desc->l = var.l;
5891 desc->d = var.db;
5892 desc->g = var.g;
5893
5894 return true;
5895}
5896
1aa36616
AK		 5897static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5898 struct desc_struct *desc, u32 base3,
5899 int seg)
2dafc6c2 5900{
4bff1e86 5901 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5902 struct kvm_segment var;
5903
1aa36616 5904 var.selector = selector;
2dafc6c2 5905 var.base = get_desc_base(desc);
5601d05b
GN		 5906#ifdef CONFIG_X86_64
5907 var.base |= ((u64)base3) << 32;
5908#endif
2dafc6c2
GN		 5909 var.limit = get_desc_limit(desc);
5910 if (desc->g)
5911 var.limit = (var.limit << 12) | 0xfff;
5912 var.type = desc->type;
2dafc6c2
GN		 5913 var.dpl = desc->dpl;
5914 var.db = desc->d;
5915 var.s = desc->s;
5916 var.l = desc->l;
5917 var.g = desc->g;
5918 var.avl = desc->avl;
5919 var.present = desc->p;
5920 var.unusable = !var.present;
5921 var.padding = 0;
5922
5923 kvm_set_segment(vcpu, &var, seg);
5924 return;
5925}
5926
717746e3
AK		 5927static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5928 u32 msr_index, u64 *pdata)
5929{
609e36d3
PB		 5930 struct msr_data msr;
5931 int r;
5932
5933 msr.index = msr_index;
5934 msr.host_initiated = false;
5935 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5936 if (r)
5937 return r;
5938
5939 *pdata = msr.data;
5940 return 0;
717746e3
AK		 5941}
5942
5943static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5944 u32 msr_index, u64 data)
5945{
8fe8ab46
WA		 5946 struct msr_data msr;
5947
5948 msr.data = data;
5949 msr.index = msr_index;
5950 msr.host_initiated = false;
5951 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5952}
5953
64d60670
PB		 5954static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5955{
5956 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5957
5958 return vcpu->arch.smbase;
5959}
5960
5961static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5962{
5963 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5964
5965 vcpu->arch.smbase = smbase;
5966}
5967
67f4d428
NA		 5968static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5969 u32 pmc)
5970{
c6702c9d 5971 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5972}
5973
222d21aa
AK		 5974static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5975 u32 pmc, u64 *pdata)
5976{
c6702c9d 5977 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5978}
5979
6c3287f7
AK		 5980static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5981{
5982 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5983}
5984
2953538e 5985static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5986 struct x86_instruction_info *info,
c4f035c6
AK		 5987 enum x86_intercept_stage stage)
5988{
2953538e 5989 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5990}
5991
e911eb3b
YZ		 5992static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5993 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5994{
e911eb3b 5995 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5996}
5997
dd856efa
AK		 5998static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5999{
6000 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6001}
6002
6003static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6004{
6005 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6006}
6007
801806d9
NA		 6008static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6009{
6010 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6011}
6012
6ed071f0
LP		 6013static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6014{
6015 return emul_to_vcpu(ctxt)->arch.hflags;
6016}
6017
6018static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6019{
c5833c7a 6020 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 6021}
6022
ed19321f
SC		 6023static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6024 const char *smstate)
0234bf88 6025{
ed19321f 6026 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 6027}
6028
c5833c7a
SC		 6029static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6030{
6031 kvm_smm_changed(emul_to_vcpu(ctxt));
6032}
6033
0225fb50 6034static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 6035 .read_gpr = emulator_read_gpr,
6036 .write_gpr = emulator_write_gpr,
ce14e868
PB		 6037 .read_std = emulator_read_std,
6038 .write_std = emulator_write_std,
7a036a6f 6039 .read_phys = kvm_read_guest_phys_system,
1871c602 6040 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 6041 .read_emulated = emulator_read_emulated,
6042 .write_emulated = emulator_write_emulated,
6043 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 6044 .invlpg = emulator_invlpg,
cf8f70bf
GN		 6045 .pio_in_emulated = emulator_pio_in_emulated,
6046 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 6047 .get_segment = emulator_get_segment,
6048 .set_segment = emulator_set_segment,
5951c442 6049 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 6050 .get_gdt = emulator_get_gdt,
160ce1f1 6051 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 6052 .set_gdt = emulator_set_gdt,
6053 .set_idt = emulator_set_idt,
52a46617
GN		 6054 .get_cr = emulator_get_cr,
6055 .set_cr = emulator_set_cr,
9c537244 6056 .cpl = emulator_get_cpl,
35aa5375
GN		 6057 .get_dr = emulator_get_dr,
6058 .set_dr = emulator_set_dr,
64d60670
PB		 6059 .get_smbase = emulator_get_smbase,
6060 .set_smbase = emulator_set_smbase,
717746e3
AK		 6061 .set_msr = emulator_set_msr,
6062 .get_msr = emulator_get_msr,
67f4d428 6063 .check_pmc = emulator_check_pmc,
222d21aa 6064 .read_pmc = emulator_read_pmc,
6c3287f7 6065 .halt = emulator_halt,
bcaf5cc5 6066 .wbinvd = emulator_wbinvd,
d6aa1000 6067 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6068 .intercept = emulator_intercept,
bdb42f5a 6069 .get_cpuid = emulator_get_cpuid,
801806d9 6070 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6071 .get_hflags = emulator_get_hflags,
6072 .set_hflags = emulator_set_hflags,
0234bf88 6073 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6074 .post_leave_smm = emulator_post_leave_smm,
bbd9b64e
CO		 6075};
6076
95cb2295
GN		 6077static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6078{
37ccdcbe 6079 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6080 /*
6081 * an sti; sti; sequence only disable interrupts for the first
6082 * instruction. So, if the last instruction, be it emulated or
6083 * not, left the system with the INT_STI flag enabled, it
6084 * means that the last instruction is an sti. We should not
6085 * leave the flag on in this case. The same goes for mov ss
6086 */
37ccdcbe
PB		 6087 if (int_shadow & mask)
6088 mask = 0;
6addfc42 6089 if (unlikely(int_shadow || mask)) {
95cb2295 6090 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6091 if (!mask)
6092 kvm_make_request(KVM_REQ_EVENT, vcpu);
6093 }
95cb2295
GN		 6094}
6095
ef54bcfe 6096static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6097{
6098 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6099 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6100 return kvm_propagate_fault(vcpu, &ctxt->exception);
6101
6102 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6103 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6104 ctxt->exception.error_code);
54b8486f 6105 else
da9cb575 6106 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6107 return false;
54b8486f
GN		 6108}
6109
8ec4722d
MG		 6110static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6111{
adf52235 6112 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6113 int cs_db, cs_l;
6114
8ec4722d
MG		 6115 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6116
adf52235 6117 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6118 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6119
adf52235
TY		 6120 ctxt->eip = kvm_rip_read(vcpu);
6121 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6122 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6123 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6124 cs_db ? X86EMUL_MODE_PROT32 :
6125 X86EMUL_MODE_PROT16;
a584539b 6126 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6127 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6128 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6129
dd856efa 6130 init_decode_cache(ctxt);
7ae441ea 6131 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6132}
6133
71f9833b 6134int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6135{
9d74191a 6136 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6137 int ret;
6138
6139 init_emulate_ctxt(vcpu);
6140
9dac77fa
AK		 6141 ctxt->op_bytes = 2;
6142 ctxt->ad_bytes = 2;
6143 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6144 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6145
6146 if (ret != X86EMUL_CONTINUE)
6147 return EMULATE_FAIL;
6148
9dac77fa 6149 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6150 kvm_rip_write(vcpu, ctxt->eip);
6151 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6152
63995653
MG		 6153 return EMULATE_DONE;
6154}
6155EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6156
e2366171 6157static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6158{
fc3a9157
JR		 6159 int r = EMULATE_DONE;
6160
6d77dbfc
GN		 6161 ++vcpu->stat.insn_emulation_fail;
6162 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6163
6164 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6165 return EMULATE_FAIL;
6166
a2b9e6c1 6167 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6168 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6169 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6170 vcpu->run->internal.ndata = 0;
1f4dcb3b 6171 r = EMULATE_USER_EXIT;
fc3a9157 6172 }
e2366171 6173
6d77dbfc 6174 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6175
6176 return r;
6d77dbfc
GN		 6177}
6178
93c05d3e 6179static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6180 bool write_fault_to_shadow_pgtable,
6181 int emulation_type)
a6f177ef 6182{
95b3cf69 6183 gpa_t gpa = cr2;
ba049e93 6184 kvm_pfn_t pfn;
a6f177ef 6185
384bf221 6186 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6187 return false;
6188
6c3dfeb6
SC		 6189 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6190 return false;
6191
44dd3ffa 6192 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6193 /*
6194 * Write permission should be allowed since only
6195 * write access need to be emulated.
6196 */
6197 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6198
95b3cf69
XG		 6199 /*
6200 * If the mapping is invalid in guest, let cpu retry
6201 * it to generate fault.
6202 */
6203 if (gpa == UNMAPPED_GVA)
6204 return true;
6205 }
a6f177ef 6206
8e3d9d06
XG		 6207 /*
6208 * Do not retry the unhandleable instruction if it faults on the
6209 * readonly host memory, otherwise it will goto a infinite loop:
6210 * retry instruction -> write #PF -> emulation fail -> retry
6211 * instruction -> ...
6212 */
6213 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6214
6215 /*
6216 * If the instruction failed on the error pfn, it can not be fixed,
6217 * report the error to userspace.
6218 */
6219 if (is_error_noslot_pfn(pfn))
6220 return false;
6221
6222 kvm_release_pfn_clean(pfn);
6223
6224 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6225 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6226 unsigned int indirect_shadow_pages;
6227
6228 spin_lock(&vcpu->kvm->mmu_lock);
6229 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6230 spin_unlock(&vcpu->kvm->mmu_lock);
6231
6232 if (indirect_shadow_pages)
6233 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6234
a6f177ef 6235 return true;
8e3d9d06 6236 }
a6f177ef 6237
95b3cf69
XG		 6238 /*
6239 * if emulation was due to access to shadowed page table
6240 * and it failed try to unshadow page and re-enter the
6241 * guest to let CPU execute the instruction.
6242 */
6243 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6244
6245 /*
6246 * If the access faults on its page table, it can not
6247 * be fixed by unprotecting shadow page and it should
6248 * be reported to userspace.
6249 */
6250 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6251}
6252
1cb3f3ae
XG		 6253static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6254 unsigned long cr2, int emulation_type)
6255{
6256 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6257 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6258
6259 last_retry_eip = vcpu->arch.last_retry_eip;
6260 last_retry_addr = vcpu->arch.last_retry_addr;
6261
6262 /*
6263 * If the emulation is caused by #PF and it is non-page_table
6264 * writing instruction, it means the VM-EXIT is caused by shadow
6265 * page protected, we can zap the shadow page and retry this
6266 * instruction directly.
6267 *
6268 * Note: if the guest uses a non-page-table modifying instruction
6269 * on the PDE that points to the instruction, then we will unmap
6270 * the instruction and go to an infinite loop. So, we cache the
6271 * last retried eip and the last fault address, if we meet the eip
6272 * and the address again, we can break out of the potential infinite
6273 * loop.
6274 */
6275 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6276
384bf221 6277 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6278 return false;
6279
6c3dfeb6
SC		 6280 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6281 return false;
6282
1cb3f3ae
XG		 6283 if (x86_page_table_writing_insn(ctxt))
6284 return false;
6285
6286 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6287 return false;
6288
6289 vcpu->arch.last_retry_eip = ctxt->eip;
6290 vcpu->arch.last_retry_addr = cr2;
6291
44dd3ffa 6292 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6293 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6294
22368028 6295 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6296
6297 return true;
6298}
6299
716d51ab
GN		 6300static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6301static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6302
64d60670 6303static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6304{
64d60670 6305 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6306 /* This is a good place to trace that we are exiting SMM. */
6307 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6308
c43203ca
PB		 6309 /* Process a latched INIT or SMI, if any. */
6310 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6311 }
699023e2
PB		 6312
6313 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6314}
6315
4a1e10d5
PB		 6316static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6317 unsigned long *db)
6318{
6319 u32 dr6 = 0;
6320 int i;
6321 u32 enable, rwlen;
6322
6323 enable = dr7;
6324 rwlen = dr7 >> 16;
6325 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6326 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6327 dr6 |= (1 << i);
6328 return dr6;
6329}
6330
c8401dda 6331static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6332{
6333 struct kvm_run *kvm_run = vcpu->run;
6334
c8401dda
PB		 6335 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6336 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6337 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6338 kvm_run->debug.arch.exception = DB_VECTOR;
6339 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6340 *r = EMULATE_USER_EXIT;
6341 } else {
f10c729f 6342 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6343 }
6344}
6345
6affcbed
KH		 6346int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6347{
6348 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6349 int r = EMULATE_DONE;
6350
6351 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6352
6353 /*
6354 * rflags is the old, "raw" value of the flags. The new value has
6355 * not been saved yet.
6356 *
6357 * This is correct even for TF set by the guest, because "the
6358 * processor will not generate this exception after the instruction
6359 * that sets the TF flag".
6360 */
6361 if (unlikely(rflags & X86_EFLAGS_TF))
6362 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6363 return r == EMULATE_DONE;
6364}
6365EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6366
4a1e10d5
PB		 6367static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6368{
4a1e10d5
PB		 6369 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6370 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6371 struct kvm_run *kvm_run = vcpu->run;
6372 unsigned long eip = kvm_get_linear_rip(vcpu);
6373 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6374 vcpu->arch.guest_debug_dr7,
6375 vcpu->arch.eff_db);
6376
6377 if (dr6 != 0) {
6f43ed01 6378 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6379 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6380 kvm_run->debug.arch.exception = DB_VECTOR;
6381 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6382 *r = EMULATE_USER_EXIT;
6383 return true;
6384 }
6385 }
6386
4161a569
NA		 6387 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6388 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6389 unsigned long eip = kvm_get_linear_rip(vcpu);
6390 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6391 vcpu->arch.dr7,
6392 vcpu->arch.db);
6393
6394 if (dr6 != 0) {
6395 vcpu->arch.dr6 &= ~15;
6f43ed01 6396 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6397 kvm_queue_exception(vcpu, DB_VECTOR);
6398 *r = EMULATE_DONE;
6399 return true;
6400 }
6401 }
6402
6403 return false;
6404}
6405
04789b66
LA		 6406static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6407{
2d7921c4
AM		 6408 switch (ctxt->opcode_len) {
6409 case 1:
6410 switch (ctxt->b) {
6411 case 0xe4: /* IN */
6412 case 0xe5:
6413 case 0xec:
6414 case 0xed:
6415 case 0xe6: /* OUT */
6416 case 0xe7:
6417 case 0xee:
6418 case 0xef:
6419 case 0x6c: /* INS */
6420 case 0x6d:
6421 case 0x6e: /* OUTS */
6422 case 0x6f:
6423 return true;
6424 }
6425 break;
6426 case 2:
6427 switch (ctxt->b) {
6428 case 0x33: /* RDPMC */
6429 return true;
6430 }
6431 break;
04789b66
LA		 6432 }
6433
6434 return false;
6435}
6436
51d8b661
AP		 6437int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6438 unsigned long cr2,
dc25e89e
AP		 6439 int emulation_type,
6440 void *insn,
6441 int insn_len)
bbd9b64e 6442{
95cb2295 6443 int r;
9d74191a 6444 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6445 bool writeback = true;
93c05d3e 6446 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6447
c595ceee
PB		 6448 vcpu->arch.l1tf_flush_l1d = true;
6449
93c05d3e
XG		 6450 /*
6451 * Clear write_fault_to_shadow_pgtable here to ensure it is
6452 * never reused.
6453 */
6454 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6455 kvm_clear_exception_queue(vcpu);
8d7d8102 6456
571008da 6457 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6458 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6459
6460 /*
6461 * We will reenter on the same instruction since
6462 * we do not set complete_userspace_io. This does not
6463 * handle watchpoints yet, those would be handled in
6464 * the emulate_ops.
6465 */
d391f120
VK		 6466 if (!(emulation_type & EMULTYPE_SKIP) &&
6467 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6468 return r;
6469
9d74191a
TY		 6470 ctxt->interruptibility = 0;
6471 ctxt->have_exception = false;
e0ad0b47 6472 ctxt->exception.vector = -1;
9d74191a 6473 ctxt->perm_ok = false;
bbd9b64e 6474
b51e974f 6475 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6476
9d74191a 6477 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6478
e46479f8 6479 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6480 ++vcpu->stat.insn_emulation;
1d2887e2 6481 if (r != EMULATION_OK) {
4005996e
AK		 6482 if (emulation_type & EMULTYPE_TRAP_UD)
6483 return EMULATE_FAIL;
991eebf9
GN		 6484 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6485 emulation_type))
bbd9b64e 6486 return EMULATE_DONE;
6ea6e843
PB		 6487 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6488 return EMULATE_DONE;
6d77dbfc
GN		 6489 if (emulation_type & EMULTYPE_SKIP)
6490 return EMULATE_FAIL;
e2366171 6491 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6492 }
6493 }
6494
04789b66
LA		 6495 if ((emulation_type & EMULTYPE_VMWARE) &&
6496 !is_vmware_backdoor_opcode(ctxt))
6497 return EMULATE_FAIL;
6498
ba8afb6b 6499 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6500 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6501 if (ctxt->eflags & X86_EFLAGS_RF)
6502 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6503 return EMULATE_DONE;
6504 }
6505
1cb3f3ae
XG		 6506 if (retry_instruction(ctxt, cr2, emulation_type))
6507 return EMULATE_DONE;
6508
7ae441ea 6509 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6510 changes registers values during IO operation */
7ae441ea
GN		 6511 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6512 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6513 emulator_invalidate_register_cache(ctxt);
7ae441ea 6514 }
4d2179e1 6515
5cd21917 6516restart:
0f89b207
TL		 6517 /* Save the faulting GPA (cr2) in the address field */
6518 ctxt->exception.address = cr2;
6519
9d74191a 6520 r = x86_emulate_insn(ctxt);
bbd9b64e 6521
775fde86
JR		 6522 if (r == EMULATION_INTERCEPTED)
6523 return EMULATE_DONE;
6524
d2ddd1c4 6525 if (r == EMULATION_FAILED) {
991eebf9
GN		 6526 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6527 emulation_type))
c3cd7ffa
GN		 6528 return EMULATE_DONE;
6529
e2366171 6530 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6531 }
6532
9d74191a 6533 if (ctxt->have_exception) {
d2ddd1c4 6534 r = EMULATE_DONE;
ef54bcfe
PB		 6535 if (inject_emulated_exception(vcpu))
6536 return r;
d2ddd1c4 6537 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6538 if (!vcpu->arch.pio.in) {
6539 /* FIXME: return into emulator if single-stepping. */
3457e419 6540 vcpu->arch.pio.count = 0;
0912c977 6541 } else {
7ae441ea 6542 writeback = false;
716d51ab
GN		 6543 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6544 }
ac0a48c3 6545 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6546 } else if (vcpu->mmio_needed) {
6547 if (!vcpu->mmio_is_write)
6548 writeback = false;
ac0a48c3 6549 r = EMULATE_USER_EXIT;
716d51ab 6550 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6551 } else if (r == EMULATION_RESTART)
5cd21917 6552 goto restart;
d2ddd1c4
GN		 6553 else
6554 r = EMULATE_DONE;
f850e2e6 6555
7ae441ea 6556 if (writeback) {
6addfc42 6557 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6558 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6559 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6560 kvm_rip_write(vcpu, ctxt->eip);
5cc244a2 6561 if (r == EMULATE_DONE && ctxt->tf)
c8401dda 6562 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6563 if (!ctxt->have_exception ||
6564 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6565 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6566
6567 /*
6568 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6569 * do nothing, and it will be requested again as soon as
6570 * the shadow expires. But we still need to check here,
6571 * because POPF has no interrupt shadow.
6572 */
6573 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6574 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6575 } else
6576 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6577
6578 return r;
de7d789a 6579}
c60658d1
SC		 6580
6581int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6582{
6583 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6584}
6585EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6586
6587int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6588 void *insn, int insn_len)
6589{
6590 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6591}
6592EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6593
8764ed55
SC		 6594static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6595{
6596 vcpu->arch.pio.count = 0;
6597 return 1;
6598}
6599
45def77e
SC		 6600static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6601{
6602 vcpu->arch.pio.count = 0;
6603
6604 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6605 return 1;
6606
6607 return kvm_skip_emulated_instruction(vcpu);
6608}
6609
dca7f128
SC		 6610static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6611 unsigned short port)
de7d789a 6612{
de3cd117 6613 unsigned long val = kvm_rax_read(vcpu);
ca1d4a9e
AK		 6614 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6615 size, port, &val, 1);
8764ed55
SC		 6616 if (ret)
6617 return ret;
45def77e 6618
8764ed55
SC		 6619 /*
6620 * Workaround userspace that relies on old KVM behavior of %rip being
6621 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6622 */
6623 if (port == 0x7e &&
6624 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6625 vcpu->arch.complete_userspace_io =
6626 complete_fast_pio_out_port_0x7e;
6627 kvm_skip_emulated_instruction(vcpu);
6628 } else {
45def77e
SC		 6629 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6630 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6631 }
8764ed55 6632 return 0;
de7d789a 6633}
de7d789a 6634
8370c3d0
TL		 6635static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6636{
6637 unsigned long val;
6638
6639 /* We should only ever be called with arch.pio.count equal to 1 */
6640 BUG_ON(vcpu->arch.pio.count != 1);
6641
45def77e
SC		 6642 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6643 vcpu->arch.pio.count = 0;
6644 return 1;
6645 }
6646
8370c3d0 6647 /* For size less than 4 we merge, else we zero extend */
de3cd117 6648 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6649
6650 /*
6651 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6652 * the copy and tracing
6653 */
6654 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6655 vcpu->arch.pio.port, &val, 1);
de3cd117 6656 kvm_rax_write(vcpu, val);
8370c3d0 6657
45def77e 6658 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6659}
6660
dca7f128
SC		 6661static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6662 unsigned short port)
8370c3d0
TL		 6663{
6664 unsigned long val;
6665 int ret;
6666
6667 /* For size less than 4 we merge, else we zero extend */
de3cd117 6668 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6669
6670 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6671 &val, 1);
6672 if (ret) {
de3cd117 6673 kvm_rax_write(vcpu, val);
8370c3d0
TL		 6674 return ret;
6675 }
6676
45def77e 6677 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6678 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6679
6680 return 0;
6681}
dca7f128
SC		 6682
6683int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6684{
45def77e 6685 int ret;
dca7f128 6686
dca7f128 6687 if (in)
45def77e 6688 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6689 else
45def77e
SC		 6690 ret = kvm_fast_pio_out(vcpu, size, port);
6691 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 6692}
6693EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6694
251a5fd6 6695static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6696{
0a3aee0d 6697 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6698 return 0;
8cfdc000
ZA		 6699}
6700
6701static void tsc_khz_changed(void *data)
c8076604 6702{
8cfdc000
ZA		 6703 struct cpufreq_freqs *freq = data;
6704 unsigned long khz = 0;
6705
6706 if (data)
6707 khz = freq->new;
6708 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6709 khz = cpufreq_quick_get(raw_smp_processor_id());
6710 if (!khz)
6711 khz = tsc_khz;
0a3aee0d 6712 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6713}
6714
5fa4ec9c 6715#ifdef CONFIG_X86_64
0092e434
VK		 6716static void kvm_hyperv_tsc_notifier(void)
6717{
0092e434
VK		 6718 struct kvm *kvm;
6719 struct kvm_vcpu *vcpu;
6720 int cpu;
6721
0d9ce162 6722 mutex_lock(&kvm_lock);
0092e434
VK		 6723 list_for_each_entry(kvm, &vm_list, vm_list)
6724 kvm_make_mclock_inprogress_request(kvm);
6725
6726 hyperv_stop_tsc_emulation();
6727
6728 /* TSC frequency always matches when on Hyper-V */
6729 for_each_present_cpu(cpu)
6730 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6731 kvm_max_guest_tsc_khz = tsc_khz;
6732
6733 list_for_each_entry(kvm, &vm_list, vm_list) {
6734 struct kvm_arch *ka = &kvm->arch;
6735
6736 spin_lock(&ka->pvclock_gtod_sync_lock);
6737
6738 pvclock_update_vm_gtod_copy(kvm);
6739
6740 kvm_for_each_vcpu(cpu, vcpu, kvm)
6741 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6742
6743 kvm_for_each_vcpu(cpu, vcpu, kvm)
6744 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6745
6746 spin_unlock(&ka->pvclock_gtod_sync_lock);
6747 }
0d9ce162 6748 mutex_unlock(&kvm_lock);
0092e434 6749}
5fa4ec9c 6750#endif
0092e434 6751
df24014a 6752static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
c8076604 6753{
c8076604
GH		 6754 struct kvm *kvm;
6755 struct kvm_vcpu *vcpu;
6756 int i, send_ipi = 0;
6757
8cfdc000
ZA		 6758 /*
6759 * We allow guests to temporarily run on slowing clocks,
6760 * provided we notify them after, or to run on accelerating
6761 * clocks, provided we notify them before. Thus time never
6762 * goes backwards.
6763 *
6764 * However, we have a problem. We can't atomically update
6765 * the frequency of a given CPU from this function; it is
6766 * merely a notifier, which can be called from any CPU.
6767 * Changing the TSC frequency at arbitrary points in time
6768 * requires a recomputation of local variables related to
6769 * the TSC for each VCPU. We must flag these local variables
6770 * to be updated and be sure the update takes place with the
6771 * new frequency before any guests proceed.
6772 *
6773 * Unfortunately, the combination of hotplug CPU and frequency
6774 * change creates an intractable locking scenario; the order
6775 * of when these callouts happen is undefined with respect to
6776 * CPU hotplug, and they can race with each other. As such,
6777 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6778 * undefined; you can actually have a CPU frequency change take
6779 * place in between the computation of X and the setting of the
6780 * variable. To protect against this problem, all updates of
6781 * the per_cpu tsc_khz variable are done in an interrupt
6782 * protected IPI, and all callers wishing to update the value
6783 * must wait for a synchronous IPI to complete (which is trivial
6784 * if the caller is on the CPU already). This establishes the
6785 * necessary total order on variable updates.
6786 *
6787 * Note that because a guest time update may take place
6788 * anytime after the setting of the VCPU's request bit, the
6789 * correct TSC value must be set before the request. However,
6790 * to ensure the update actually makes it to any guest which
6791 * starts running in hardware virtualization between the set
6792 * and the acquisition of the spinlock, we must also ping the
6793 * CPU after setting the request bit.
6794 *
6795 */
6796
df24014a 6797 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6798
0d9ce162 6799 mutex_lock(&kvm_lock);
c8076604 6800 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6801 kvm_for_each_vcpu(i, vcpu, kvm) {
df24014a 6802 if (vcpu->cpu != cpu)
c8076604 6803 continue;
c285545f 6804 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0d9ce162 6805 if (vcpu->cpu != raw_smp_processor_id())
8cfdc000 6806 send_ipi = 1;
c8076604
GH		 6807 }
6808 }
0d9ce162 6809 mutex_unlock(&kvm_lock);
c8076604
GH		 6810
6811 if (freq->old < freq->new && send_ipi) {
6812 /*
6813 * We upscale the frequency. Must make the guest
6814 * doesn't see old kvmclock values while running with
6815 * the new frequency, otherwise we risk the guest sees
6816 * time go backwards.
6817 *
6818 * In case we update the frequency for another cpu
6819 * (which might be in guest context) send an interrupt
6820 * to kick the cpu out of guest context. Next time
6821 * guest context is entered kvmclock will be updated,
6822 * so the guest will not see stale values.
6823 */
df24014a 6824 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6825 }
df24014a
VK		 6826}
6827
6828static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6829 void *data)
6830{
6831 struct cpufreq_freqs *freq = data;
6832 int cpu;
6833
6834 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6835 return 0;
6836 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6837 return 0;
6838
6839 for_each_cpu(cpu, freq->policy->cpus)
6840 __kvmclock_cpufreq_notifier(freq, cpu);
6841
c8076604
GH		 6842 return 0;
6843}
6844
6845static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6846 .notifier_call = kvmclock_cpufreq_notifier
6847};
6848
251a5fd6 6849static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6850{
251a5fd6
SAS		 6851 tsc_khz_changed(NULL);
6852 return 0;
8cfdc000
ZA		 6853}
6854
b820cc0c
ZA		 6855static void kvm_timer_init(void)
6856{
c285545f 6857 max_tsc_khz = tsc_khz;
460dd42e 6858
b820cc0c 6859 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6860#ifdef CONFIG_CPU_FREQ
6861 struct cpufreq_policy policy;
758f588d
BP		 6862 int cpu;
6863
c285545f 6864 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6865 cpu = get_cpu();
6866 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6867 if (policy.cpuinfo.max_freq)
6868 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6869 put_cpu();
c285545f 6870#endif
b820cc0c
ZA		 6871 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6872 CPUFREQ_TRANSITION_NOTIFIER);
6873 }
c285545f 6874 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6875
73c1b41e 6876 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6877 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6878}
6879
dd60d217
AK		 6880DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6881EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6882
f5132b01 6883int kvm_is_in_guest(void)
ff9d07a0 6884{
086c9855 6885 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6886}
6887
6888static int kvm_is_user_mode(void)
6889{
6890 int user_mode = 3;
dcf46b94 6891
086c9855
AS		 6892 if (__this_cpu_read(current_vcpu))
6893 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6894
ff9d07a0
ZY		 6895 return user_mode != 0;
6896}
6897
6898static unsigned long kvm_get_guest_ip(void)
6899{
6900 unsigned long ip = 0;
dcf46b94 6901
086c9855
AS		 6902 if (__this_cpu_read(current_vcpu))
6903 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6904
ff9d07a0
ZY		 6905 return ip;
6906}
6907
8479e04e
LK		 6908static void kvm_handle_intel_pt_intr(void)
6909{
6910 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6911
6912 kvm_make_request(KVM_REQ_PMI, vcpu);
6913 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6914 (unsigned long *)&vcpu->arch.pmu.global_status);
6915}
6916
ff9d07a0
ZY		 6917static struct perf_guest_info_callbacks kvm_guest_cbs = {
6918 .is_in_guest = kvm_is_in_guest,
6919 .is_user_mode = kvm_is_user_mode,
6920 .get_guest_ip = kvm_get_guest_ip,
8479e04e 6921 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
ff9d07a0
ZY		 6922};
6923
16e8d74d
MT		 6924#ifdef CONFIG_X86_64
6925static void pvclock_gtod_update_fn(struct work_struct *work)
6926{
d828199e
MT		 6927 struct kvm *kvm;
6928
6929 struct kvm_vcpu *vcpu;
6930 int i;
6931
0d9ce162 6932 mutex_lock(&kvm_lock);
d828199e
MT		 6933 list_for_each_entry(kvm, &vm_list, vm_list)
6934 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6935 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6936 atomic_set(&kvm_guest_has_master_clock, 0);
0d9ce162 6937 mutex_unlock(&kvm_lock);
16e8d74d
MT		 6938}
6939
6940static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6941
6942/*
6943 * Notification about pvclock gtod data update.
6944 */
6945static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6946 void *priv)
6947{
6948 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6949 struct timekeeper *tk = priv;
6950
6951 update_pvclock_gtod(tk);
6952
6953 /* disable master clock if host does not trust, or does not
b0c39dc6 6954 * use, TSC based clocksource.
16e8d74d 6955 */
b0c39dc6 6956 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6957 atomic_read(&kvm_guest_has_master_clock) != 0)
6958 queue_work(system_long_wq, &pvclock_gtod_work);
6959
6960 return 0;
6961}
6962
6963static struct notifier_block pvclock_gtod_notifier = {
6964 .notifier_call = pvclock_gtod_notify,
6965};
6966#endif
6967
f8c16bba 6968int kvm_arch_init(void *opaque)
043405e1 6969{
b820cc0c 6970 int r;
6b61edf7 6971 struct kvm_x86_ops *ops = opaque;
f8c16bba 6972
f8c16bba
ZX		 6973 if (kvm_x86_ops) {
6974 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6975 r = -EEXIST;
6976 goto out;
f8c16bba
ZX		 6977 }
6978
6979 if (!ops->cpu_has_kvm_support()) {
6980 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6981 r = -EOPNOTSUPP;
6982 goto out;
f8c16bba
ZX		 6983 }
6984 if (ops->disabled_by_bios()) {
6985 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6986 r = -EOPNOTSUPP;
6987 goto out;
f8c16bba
ZX		 6988 }
6989
b666a4b6
MO		 6990 /*
6991 * KVM explicitly assumes that the guest has an FPU and
6992 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
6993 * vCPU's FPU state as a fxregs_state struct.
6994 */
6995 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
6996 printk(KERN_ERR "kvm: inadequate fpu\n");
6997 r = -EOPNOTSUPP;
6998 goto out;
6999 }
7000
013f6a5d 7001 r = -ENOMEM;
ed8e4812 7002 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 7003 __alignof__(struct fpu), SLAB_ACCOUNT,
7004 NULL);
7005 if (!x86_fpu_cache) {
7006 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7007 goto out;
7008 }
7009
013f6a5d
MT		 7010 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7011 if (!shared_msrs) {
7012 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 7013 goto out_free_x86_fpu_cache;
013f6a5d
MT		 7014 }
7015
97db56ce
AK		 7016 r = kvm_mmu_module_init();
7017 if (r)
013f6a5d 7018 goto out_free_percpu;
97db56ce 7019
f8c16bba 7020 kvm_x86_ops = ops;
920c8377 7021
7b52345e 7022 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 7023 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 7024 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 7025 kvm_timer_init();
c8076604 7026
ff9d07a0
ZY		 7027 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7028
d366bf7e 7029 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 7030 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7031
c5cc421b 7032 kvm_lapic_init();
16e8d74d
MT		 7033#ifdef CONFIG_X86_64
7034 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 7035
5fa4ec9c 7036 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 7037 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 7038#endif
7039
f8c16bba 7040 return 0;
56c6d28a 7041
013f6a5d
MT		 7042out_free_percpu:
7043 free_percpu(shared_msrs);
b666a4b6
MO		 7044out_free_x86_fpu_cache:
7045 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7046out:
56c6d28a 7047 return r;
043405e1 7048}
8776e519 7049
f8c16bba
ZX		 7050void kvm_arch_exit(void)
7051{
0092e434 7052#ifdef CONFIG_X86_64
5fa4ec9c 7053 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 7054 clear_hv_tscchange_cb();
7055#endif
cef84c30 7056 kvm_lapic_exit();
ff9d07a0
ZY		 7057 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7058
888d256e
JK		 7059 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7060 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7061 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7062 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7063#ifdef CONFIG_X86_64
7064 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7065#endif
f8c16bba 7066 kvm_x86_ops = NULL;
56c6d28a 7067 kvm_mmu_module_exit();
013f6a5d 7068 free_percpu(shared_msrs);
b666a4b6 7069 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7070}
f8c16bba 7071
5cb56059 7072int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7073{
7074 ++vcpu->stat.halt_exits;
35754c98 7075 if (lapic_in_kernel(vcpu)) {
a4535290 7076 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7077 return 1;
7078 } else {
7079 vcpu->run->exit_reason = KVM_EXIT_HLT;
7080 return 0;
7081 }
7082}
5cb56059
JS		 7083EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7084
7085int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7086{
6affcbed
KH		 7087 int ret = kvm_skip_emulated_instruction(vcpu);
7088 /*
7089 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7090 * KVM_EXIT_DEBUG here.
7091 */
7092 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7093}
8776e519
HB		 7094EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7095
8ef81a9a 7096#ifdef CONFIG_X86_64
55dd00a7
MT		 7097static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7098 unsigned long clock_type)
7099{
7100 struct kvm_clock_pairing clock_pairing;
899a31f5 7101 struct timespec64 ts;
80fbd89c 7102 u64 cycle;
55dd00a7
MT		 7103 int ret;
7104
7105 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7106 return -KVM_EOPNOTSUPP;
7107
7108 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7109 return -KVM_EOPNOTSUPP;
7110
7111 clock_pairing.sec = ts.tv_sec;
7112 clock_pairing.nsec = ts.tv_nsec;
7113 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7114 clock_pairing.flags = 0;
bcbfbd8e 7115 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7116
7117 ret = 0;
7118 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7119 sizeof(struct kvm_clock_pairing)))
7120 ret = -KVM_EFAULT;
7121
7122 return ret;
7123}
8ef81a9a 7124#endif
55dd00a7 7125
6aef266c
SV		 7126/*
7127 * kvm_pv_kick_cpu_op: Kick a vcpu.
7128 *
7129 * @apicid - apicid of vcpu to be kicked.
7130 */
7131static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7132{
24d2166b 7133 struct kvm_lapic_irq lapic_irq;
6aef266c 7134
24d2166b
R		 7135 lapic_irq.shorthand = 0;
7136 lapic_irq.dest_mode = 0;
ebd28fcb 7137 lapic_irq.level = 0;
24d2166b 7138 lapic_irq.dest_id = apicid;
93bbf0b8 7139 lapic_irq.msi_redir_hint = false;
6aef266c 7140
24d2166b 7141 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7142 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7143}
7144
d62caabb
AS		 7145void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7146{
f7589cca
PB		 7147 if (!lapic_in_kernel(vcpu)) {
7148 WARN_ON_ONCE(vcpu->arch.apicv_active);
7149 return;
7150 }
7151 if (!vcpu->arch.apicv_active)
7152 return;
7153
d62caabb
AS		 7154 vcpu->arch.apicv_active = false;
7155 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7156}
7157
8776e519
HB		 7158int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7159{
7160 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7161 int op_64_bit;
8776e519 7162
696ca779
RK		 7163 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7164 return kvm_hv_hypercall(vcpu);
55cd8e5a 7165
de3cd117
SC		 7166 nr = kvm_rax_read(vcpu);
7167 a0 = kvm_rbx_read(vcpu);
7168 a1 = kvm_rcx_read(vcpu);
7169 a2 = kvm_rdx_read(vcpu);
7170 a3 = kvm_rsi_read(vcpu);
8776e519 7171
229456fc 7172 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7173
a449c7aa
NA		 7174 op_64_bit = is_64_bit_mode(vcpu);
7175 if (!op_64_bit) {
8776e519
HB		 7176 nr &= 0xFFFFFFFF;
7177 a0 &= 0xFFFFFFFF;
7178 a1 &= 0xFFFFFFFF;
7179 a2 &= 0xFFFFFFFF;
7180 a3 &= 0xFFFFFFFF;
7181 }
7182
07708c4a
JK		 7183 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7184 ret = -KVM_EPERM;
696ca779 7185 goto out;
07708c4a
JK		 7186 }
7187
8776e519 7188 switch (nr) {
b93463aa
AK		 7189 case KVM_HC_VAPIC_POLL_IRQ:
7190 ret = 0;
7191 break;
6aef266c
SV		 7192 case KVM_HC_KICK_CPU:
7193 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7194 ret = 0;
7195 break;
8ef81a9a 7196#ifdef CONFIG_X86_64
55dd00a7
MT		 7197 case KVM_HC_CLOCK_PAIRING:
7198 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7199 break;
1ed199a4 7200#endif
4180bf1b
WL		 7201 case KVM_HC_SEND_IPI:
7202 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7203 break;
8776e519
HB		 7204 default:
7205 ret = -KVM_ENOSYS;
7206 break;
7207 }
696ca779 7208out:
a449c7aa
NA		 7209 if (!op_64_bit)
7210 ret = (u32)ret;
de3cd117 7211 kvm_rax_write(vcpu, ret);
6356ee0c 7212
f11c3a8d 7213 ++vcpu->stat.hypercalls;
6356ee0c 7214 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7215}
7216EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7217
b6785def 7218static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7219{
d6aa1000 7220 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7221 char instruction[3];
5fdbf976 7222 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7223
8776e519 7224 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7225
ce2e852e
DV		 7226 return emulator_write_emulated(ctxt, rip, instruction, 3,
7227 &ctxt->exception);
8776e519
HB		 7228}
7229
851ba692 7230static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7231{
782d422b
MG		 7232 return vcpu->run->request_interrupt_window &&
7233 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7234}
7235
851ba692 7236static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7237{
851ba692
AK		 7238 struct kvm_run *kvm_run = vcpu->run;
7239
91586a3b 7240 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7241 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7242 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7243 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7244 kvm_run->ready_for_interrupt_injection =
7245 pic_in_kernel(vcpu->kvm) ||
782d422b 7246 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7247}
7248
95ba8273
GN		 7249static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7250{
7251 int max_irr, tpr;
7252
7253 if (!kvm_x86_ops->update_cr8_intercept)
7254 return;
7255
bce87cce 7256 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7257 return;
7258
d62caabb
AS		 7259 if (vcpu->arch.apicv_active)
7260 return;
7261
8db3baa2
GN		 7262 if (!vcpu->arch.apic->vapic_addr)
7263 max_irr = kvm_lapic_find_highest_irr(vcpu);
7264 else
7265 max_irr = -1;
95ba8273
GN		 7266
7267 if (max_irr != -1)
7268 max_irr >>= 4;
7269
7270 tpr = kvm_lapic_get_cr8(vcpu);
7271
7272 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7273}
7274
b6b8a145 7275static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7276{
b6b8a145
JK		 7277 int r;
7278
95ba8273 7279 /* try to reinject previous events if any */
664f8e26 7280
1a680e35
LA		 7281 if (vcpu->arch.exception.injected)
7282 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7283 /*
a042c26f
LA		 7284 * Do not inject an NMI or interrupt if there is a pending
7285 * exception. Exceptions and interrupts are recognized at
7286 * instruction boundaries, i.e. the start of an instruction.
7287 * Trap-like exceptions, e.g. #DB, have higher priority than
7288 * NMIs and interrupts, i.e. traps are recognized before an
7289 * NMI/interrupt that's pending on the same instruction.
7290 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7291 * priority, but are only generated (pended) during instruction
7292 * execution, i.e. a pending fault-like exception means the
7293 * fault occurred on the *previous* instruction and must be
7294 * serviced prior to recognizing any new events in order to
7295 * fully complete the previous instruction.
664f8e26 7296 */
1a680e35
LA		 7297 else if (!vcpu->arch.exception.pending) {
7298 if (vcpu->arch.nmi_injected)
664f8e26 7299 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7300 else if (vcpu->arch.interrupt.injected)
664f8e26 7301 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7302 }
7303
1a680e35
LA		 7304 /*
7305 * Call check_nested_events() even if we reinjected a previous event
7306 * in order for caller to determine if it should require immediate-exit
7307 * from L2 to L1 due to pending L1 events which require exit
7308 * from L2 to L1.
7309 */
664f8e26
WL		 7310 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7311 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7312 if (r != 0)
7313 return r;
7314 }
7315
7316 /* try to inject new event if pending */
b59bb7bd 7317 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7318 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7319 vcpu->arch.exception.has_error_code,
7320 vcpu->arch.exception.error_code);
d6e8c854 7321
1a680e35 7322 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7323 vcpu->arch.exception.pending = false;
7324 vcpu->arch.exception.injected = true;
7325
d6e8c854
NA		 7326 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7327 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7328 X86_EFLAGS_RF);
7329
f10c729f
JM		 7330 if (vcpu->arch.exception.nr == DB_VECTOR) {
7331 /*
7332 * This code assumes that nSVM doesn't use
7333 * check_nested_events(). If it does, the
7334 * DR6/DR7 changes should happen before L1
7335 * gets a #VMEXIT for an intercepted #DB in
7336 * L2. (Under VMX, on the other hand, the
7337 * DR6/DR7 changes should not happen in the
7338 * event of a VM-exit to L1 for an intercepted
7339 * #DB in L2.)
7340 */
7341 kvm_deliver_exception_payload(vcpu);
7342 if (vcpu->arch.dr7 & DR7_GD) {
7343 vcpu->arch.dr7 &= ~DR7_GD;
7344 kvm_update_dr7(vcpu);
7345 }
6bdf0662
NA		 7346 }
7347
cfcd20e5 7348 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7349 }
7350
7351 /* Don't consider new event if we re-injected an event */
7352 if (kvm_event_needs_reinjection(vcpu))
7353 return 0;
7354
7355 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7356 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7357 vcpu->arch.smi_pending = false;
52797bf9 7358 ++vcpu->arch.smi_count;
ee2cd4b7 7359 enter_smm(vcpu);
c43203ca 7360 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7361 --vcpu->arch.nmi_pending;
7362 vcpu->arch.nmi_injected = true;
7363 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7364 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7365 /*
7366 * Because interrupts can be injected asynchronously, we are
7367 * calling check_nested_events again here to avoid a race condition.
7368 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7369 * proposal and current concerns. Perhaps we should be setting
7370 * KVM_REQ_EVENT only on certain events and not unconditionally?
7371 */
7372 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7373 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7374 if (r != 0)
7375 return r;
7376 }
95ba8273 7377 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7378 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7379 false);
7380 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7381 }
7382 }
ee2cd4b7 7383
b6b8a145 7384 return 0;
95ba8273
GN		 7385}
7386
7460fb4a
AK		 7387static void process_nmi(struct kvm_vcpu *vcpu)
7388{
7389 unsigned limit = 2;
7390
7391 /*
7392 * x86 is limited to one NMI running, and one NMI pending after it.
7393 * If an NMI is already in progress, limit further NMIs to just one.
7394 * Otherwise, allow two (and we'll inject the first one immediately).
7395 */
7396 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7397 limit = 1;
7398
7399 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7400 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7401 kvm_make_request(KVM_REQ_EVENT, vcpu);
7402}
7403
ee2cd4b7 7404static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7405{
7406 u32 flags = 0;
7407 flags |= seg->g << 23;
7408 flags |= seg->db << 22;
7409 flags |= seg->l << 21;
7410 flags |= seg->avl << 20;
7411 flags |= seg->present << 15;
7412 flags |= seg->dpl << 13;
7413 flags |= seg->s << 12;
7414 flags |= seg->type << 8;
7415 return flags;
7416}
7417
ee2cd4b7 7418static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7419{
7420 struct kvm_segment seg;
7421 int offset;
7422
7423 kvm_get_segment(vcpu, &seg, n);
7424 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7425
7426 if (n < 3)
7427 offset = 0x7f84 + n * 12;
7428 else
7429 offset = 0x7f2c + (n - 3) * 12;
7430
7431 put_smstate(u32, buf, offset + 8, seg.base);
7432 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7433 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7434}
7435
efbb288a 7436#ifdef CONFIG_X86_64
ee2cd4b7 7437static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7438{
7439 struct kvm_segment seg;
7440 int offset;
7441 u16 flags;
7442
7443 kvm_get_segment(vcpu, &seg, n);
7444 offset = 0x7e00 + n * 16;
7445
ee2cd4b7 7446 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7447 put_smstate(u16, buf, offset, seg.selector);
7448 put_smstate(u16, buf, offset + 2, flags);
7449 put_smstate(u32, buf, offset + 4, seg.limit);
7450 put_smstate(u64, buf, offset + 8, seg.base);
7451}
efbb288a 7452#endif
660a5d51 7453
ee2cd4b7 7454static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7455{
7456 struct desc_ptr dt;
7457 struct kvm_segment seg;
7458 unsigned long val;
7459 int i;
7460
7461 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7462 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7463 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7464 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7465
7466 for (i = 0; i < 8; i++)
7467 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7468
7469 kvm_get_dr(vcpu, 6, &val);
7470 put_smstate(u32, buf, 0x7fcc, (u32)val);
7471 kvm_get_dr(vcpu, 7, &val);
7472 put_smstate(u32, buf, 0x7fc8, (u32)val);
7473
7474 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7475 put_smstate(u32, buf, 0x7fc4, seg.selector);
7476 put_smstate(u32, buf, 0x7f64, seg.base);
7477 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7478 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7479
7480 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7481 put_smstate(u32, buf, 0x7fc0, seg.selector);
7482 put_smstate(u32, buf, 0x7f80, seg.base);
7483 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7484 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7485
7486 kvm_x86_ops->get_gdt(vcpu, &dt);
7487 put_smstate(u32, buf, 0x7f74, dt.address);
7488 put_smstate(u32, buf, 0x7f70, dt.size);
7489
7490 kvm_x86_ops->get_idt(vcpu, &dt);
7491 put_smstate(u32, buf, 0x7f58, dt.address);
7492 put_smstate(u32, buf, 0x7f54, dt.size);
7493
7494 for (i = 0; i < 6; i++)
ee2cd4b7 7495 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7496
7497 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7498
7499 /* revision id */
7500 put_smstate(u32, buf, 0x7efc, 0x00020000);
7501 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7502}
7503
b68f3cc7 7504#ifdef CONFIG_X86_64
ee2cd4b7 7505static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7506{
660a5d51
PB		 7507 struct desc_ptr dt;
7508 struct kvm_segment seg;
7509 unsigned long val;
7510 int i;
7511
7512 for (i = 0; i < 16; i++)
7513 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7514
7515 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7516 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7517
7518 kvm_get_dr(vcpu, 6, &val);
7519 put_smstate(u64, buf, 0x7f68, val);
7520 kvm_get_dr(vcpu, 7, &val);
7521 put_smstate(u64, buf, 0x7f60, val);
7522
7523 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7524 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7525 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7526
7527 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7528
7529 /* revision id */
7530 put_smstate(u32, buf, 0x7efc, 0x00020064);
7531
7532 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7533
7534 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7535 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7536 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7537 put_smstate(u32, buf, 0x7e94, seg.limit);
7538 put_smstate(u64, buf, 0x7e98, seg.base);
7539
7540 kvm_x86_ops->get_idt(vcpu, &dt);
7541 put_smstate(u32, buf, 0x7e84, dt.size);
7542 put_smstate(u64, buf, 0x7e88, dt.address);
7543
7544 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7545 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7546 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7547 put_smstate(u32, buf, 0x7e74, seg.limit);
7548 put_smstate(u64, buf, 0x7e78, seg.base);
7549
7550 kvm_x86_ops->get_gdt(vcpu, &dt);
7551 put_smstate(u32, buf, 0x7e64, dt.size);
7552 put_smstate(u64, buf, 0x7e68, dt.address);
7553
7554 for (i = 0; i < 6; i++)
ee2cd4b7 7555 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7556}
b68f3cc7 7557#endif
660a5d51 7558
ee2cd4b7 7559static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7560{
660a5d51 7561 struct kvm_segment cs, ds;
18c3626e 7562 struct desc_ptr dt;
660a5d51
PB		 7563 char buf[512];
7564 u32 cr0;
7565
660a5d51 7566 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7567 memset(buf, 0, 512);
b68f3cc7 7568#ifdef CONFIG_X86_64
d6321d49 7569 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7570 enter_smm_save_state_64(vcpu, buf);
660a5d51 7571 else
b68f3cc7 7572#endif
ee2cd4b7 7573 enter_smm_save_state_32(vcpu, buf);
660a5d51 7574
0234bf88
LP		 7575 /*
7576 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7577 * vCPU state (e.g. leave guest mode) after we've saved the state into
7578 * the SMM state-save area.
7579 */
7580 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7581
7582 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7583 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7584
7585 if (kvm_x86_ops->get_nmi_mask(vcpu))
7586 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7587 else
7588 kvm_x86_ops->set_nmi_mask(vcpu, true);
7589
7590 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7591 kvm_rip_write(vcpu, 0x8000);
7592
7593 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7594 kvm_x86_ops->set_cr0(vcpu, cr0);
7595 vcpu->arch.cr0 = cr0;
7596
7597 kvm_x86_ops->set_cr4(vcpu, 0);
7598
18c3626e
PB		 7599 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7600 dt.address = dt.size = 0;
7601 kvm_x86_ops->set_idt(vcpu, &dt);
7602
660a5d51
PB		 7603 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7604
7605 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7606 cs.base = vcpu->arch.smbase;
7607
7608 ds.selector = 0;
7609 ds.base = 0;
7610
7611 cs.limit = ds.limit = 0xffffffff;
7612 cs.type = ds.type = 0x3;
7613 cs.dpl = ds.dpl = 0;
7614 cs.db = ds.db = 0;
7615 cs.s = ds.s = 1;
7616 cs.l = ds.l = 0;
7617 cs.g = ds.g = 1;
7618 cs.avl = ds.avl = 0;
7619 cs.present = ds.present = 1;
7620 cs.unusable = ds.unusable = 0;
7621 cs.padding = ds.padding = 0;
7622
7623 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7624 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7625 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7626 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7627 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7628 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7629
b68f3cc7 7630#ifdef CONFIG_X86_64
d6321d49 7631 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7632 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7633#endif
660a5d51
PB		 7634
7635 kvm_update_cpuid(vcpu);
7636 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7637}
7638
ee2cd4b7 7639static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7640{
7641 vcpu->arch.smi_pending = true;
7642 kvm_make_request(KVM_REQ_EVENT, vcpu);
7643}
7644
2860c4b1
PB		 7645void kvm_make_scan_ioapic_request(struct kvm *kvm)
7646{
7647 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7648}
7649
3d81bc7e 7650static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7651{
dcbd3e49 7652 if (!kvm_apic_present(vcpu))
3d81bc7e 7653 return;
c7c9c56c 7654
6308630b 7655 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7656
b053b2ae 7657 if (irqchip_split(vcpu->kvm))
6308630b 7658 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7659 else {
fa59cc00 7660 if (vcpu->arch.apicv_active)
d62caabb 7661 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7662 if (ioapic_in_kernel(vcpu->kvm))
7663 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7664 }
e40ff1d6
LA		 7665
7666 if (is_guest_mode(vcpu))
7667 vcpu->arch.load_eoi_exitmap_pending = true;
7668 else
7669 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7670}
7671
7672static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7673{
7674 u64 eoi_exit_bitmap[4];
7675
7676 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7677 return;
7678
5c919412
AS		 7679 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7680 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7681 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7682}
7683
93065ac7
MH		 7684int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7685 unsigned long start, unsigned long end,
7686 bool blockable)
b1394e74
RK		 7687{
7688 unsigned long apic_address;
7689
7690 /*
7691 * The physical address of apic access page is stored in the VMCS.
7692 * Update it when it becomes invalid.
7693 */
7694 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7695 if (start <= apic_address && apic_address < end)
7696 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7697
7698 return 0;
b1394e74
RK		 7699}
7700
4256f43f
TC		 7701void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7702{
c24ae0dc
TC		 7703 struct page *page = NULL;
7704
35754c98 7705 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7706 return;
7707
4256f43f
TC		 7708 if (!kvm_x86_ops->set_apic_access_page_addr)
7709 return;
7710
c24ae0dc 7711 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7712 if (is_error_page(page))
7713 return;
c24ae0dc
TC		 7714 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7715
7716 /*
7717 * Do not pin apic access page in memory, the MMU notifier
7718 * will call us again if it is migrated or swapped out.
7719 */
7720 put_page(page);
4256f43f
TC		 7721}
7722EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7723
d264ee0c
SC		 7724void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7725{
7726 smp_send_reschedule(vcpu->cpu);
7727}
7728EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7729
9357d939 7730/*
362c698f 7731 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7732 * exiting to the userspace. Otherwise, the value will be returned to the
7733 * userspace.
7734 */
851ba692 7735static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7736{
7737 int r;
62a193ed
MG		 7738 bool req_int_win =
7739 dm_request_for_irq_injection(vcpu) &&
7740 kvm_cpu_accept_dm_intr(vcpu);
7741
730dca42 7742 bool req_immediate_exit = false;
b6c7a5dc 7743
2fa6e1e1 7744 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7745 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7746 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7747 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7748 kvm_mmu_unload(vcpu);
a8eeb04a 7749 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7750 __kvm_migrate_timers(vcpu);
d828199e
MT		 7751 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7752 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7753 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7754 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7755 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7756 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7757 if (unlikely(r))
7758 goto out;
7759 }
a8eeb04a 7760 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7761 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7762 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7763 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7764 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7765 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7766 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7767 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7768 r = 0;
7769 goto out;
7770 }
a8eeb04a 7771 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7772 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7773 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7774 r = 0;
7775 goto out;
7776 }
af585b92
GN		 7777 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7778 /* Page is swapped out. Do synthetic halt */
7779 vcpu->arch.apf.halted = true;
7780 r = 1;
7781 goto out;
7782 }
c9aaa895
GC		 7783 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7784 record_steal_time(vcpu);
64d60670
PB		 7785 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7786 process_smi(vcpu);
7460fb4a
AK		 7787 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7788 process_nmi(vcpu);
f5132b01 7789 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7790 kvm_pmu_handle_event(vcpu);
f5132b01 7791 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7792 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7793 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7794 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7795 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7796 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7797 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7798 vcpu->run->eoi.vector =
7799 vcpu->arch.pending_ioapic_eoi;
7800 r = 0;
7801 goto out;
7802 }
7803 }
3d81bc7e
YZ		 7804 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7805 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7806 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7807 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7808 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7809 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7810 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7811 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7812 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7813 r = 0;
7814 goto out;
7815 }
e516cebb
AS		 7816 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7817 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7818 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7819 r = 0;
7820 goto out;
7821 }
db397571
AS		 7822 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7823 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7824 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7825 r = 0;
7826 goto out;
7827 }
f3b138c5
AS		 7828
7829 /*
7830 * KVM_REQ_HV_STIMER has to be processed after
7831 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7832 * depend on the guest clock being up-to-date
7833 */
1f4b34f8
AS		 7834 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7835 kvm_hv_process_stimers(vcpu);
2f52d58c 7836 }
b93463aa 7837
b463a6f7 7838 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7839 ++vcpu->stat.req_event;
66450a21
JK		 7840 kvm_apic_accept_events(vcpu);
7841 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7842 r = 1;
7843 goto out;
7844 }
7845
b6b8a145
JK		 7846 if (inject_pending_event(vcpu, req_int_win) != 0)
7847 req_immediate_exit = true;
321c5658 7848 else {
cc3d967f 7849 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7850 *
cc3d967f
LP		 7851 * SMIs have three cases:
7852 * 1) They can be nested, and then there is nothing to
7853 * do here because RSM will cause a vmexit anyway.
7854 * 2) There is an ISA-specific reason why SMI cannot be
7855 * injected, and the moment when this changes can be
7856 * intercepted.
7857 * 3) Or the SMI can be pending because
7858 * inject_pending_event has completed the injection
7859 * of an IRQ or NMI from the previous vmexit, and
7860 * then we request an immediate exit to inject the
7861 * SMI.
c43203ca
PB		 7862 */
7863 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7864 if (!kvm_x86_ops->enable_smi_window(vcpu))
7865 req_immediate_exit = true;
321c5658
YS		 7866 if (vcpu->arch.nmi_pending)
7867 kvm_x86_ops->enable_nmi_window(vcpu);
7868 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7869 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7870 WARN_ON(vcpu->arch.exception.pending);
321c5658 7871 }
b463a6f7
AK		 7872
7873 if (kvm_lapic_enabled(vcpu)) {
7874 update_cr8_intercept(vcpu);
7875 kvm_lapic_sync_to_vapic(vcpu);
7876 }
7877 }
7878
d8368af8
AK		 7879 r = kvm_mmu_reload(vcpu);
7880 if (unlikely(r)) {
d905c069 7881 goto cancel_injection;
d8368af8
AK		 7882 }
7883
b6c7a5dc
HB		 7884 preempt_disable();
7885
7886 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7887
7888 /*
7889 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7890 * IPI are then delayed after guest entry, which ensures that they
7891 * result in virtual interrupt delivery.
7892 */
7893 local_irq_disable();
6b7e2d09
XG		 7894 vcpu->mode = IN_GUEST_MODE;
7895
01b71917
MT		 7896 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7897
0f127d12 7898 /*
b95234c8 7899 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7900 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 7901 *
81b01667 7902 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 7903 * pairs with the memory barrier implicit in pi_test_and_set_on
7904 * (see vmx_deliver_posted_interrupt).
7905 *
7906 * 3) This also orders the write to mode from any reads to the page
7907 * tables done while the VCPU is running. Please see the comment
7908 * in kvm_flush_remote_tlbs.
6b7e2d09 7909 */
01b71917 7910 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7911
b95234c8
PB		 7912 /*
7913 * This handles the case where a posted interrupt was
7914 * notified with kvm_vcpu_kick.
7915 */
fa59cc00
LA		 7916 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7917 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7918
2fa6e1e1 7919 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7920 || need_resched() || signal_pending(current)) {
6b7e2d09 7921 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7922 smp_wmb();
6c142801
AK		 7923 local_irq_enable();
7924 preempt_enable();
01b71917 7925 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7926 r = 1;
d905c069 7927 goto cancel_injection;
6c142801
AK		 7928 }
7929
c43203ca
PB		 7930 if (req_immediate_exit) {
7931 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7932 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7933 }
d6185f20 7934
8b89fe1f 7935 trace_kvm_entry(vcpu->vcpu_id);
6edaa530 7936 guest_enter_irqoff();
b6c7a5dc 7937
5f409e20
RR		 7938 fpregs_assert_state_consistent();
7939 if (test_thread_flag(TIF_NEED_FPU_LOAD))
7940 switch_fpu_return();
7941
42dbaa5a 7942 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7943 set_debugreg(0, 7);
7944 set_debugreg(vcpu->arch.eff_db[0], 0);
7945 set_debugreg(vcpu->arch.eff_db[1], 1);
7946 set_debugreg(vcpu->arch.eff_db[2], 2);
7947 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7948 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7949 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7950 }
b6c7a5dc 7951
851ba692 7952 kvm_x86_ops->run(vcpu);
b6c7a5dc 7953
c77fb5fe
PB		 7954 /*
7955 * Do this here before restoring debug registers on the host. And
7956 * since we do this before handling the vmexit, a DR access vmexit
7957 * can (a) read the correct value of the debug registers, (b) set
7958 * KVM_DEBUGREG_WONT_EXIT again.
7959 */
7960 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7961 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7962 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7963 kvm_update_dr0123(vcpu);
7964 kvm_update_dr6(vcpu);
7965 kvm_update_dr7(vcpu);
7966 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7967 }
7968
24f1e32c
FW		 7969 /*
7970 * If the guest has used debug registers, at least dr7
7971 * will be disabled while returning to the host.
7972 * If we don't have active breakpoints in the host, we don't
7973 * care about the messed up debug address registers. But if
7974 * we have some of them active, restore the old state.
7975 */
59d8eb53 7976 if (hw_breakpoint_active())
24f1e32c 7977 hw_breakpoint_restore();
42dbaa5a 7978
4ba76538 7979 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7980
6b7e2d09 7981 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7982 smp_wmb();
a547c6db 7983
dd60d217 7984 kvm_before_interrupt(vcpu);
a547c6db 7985 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7986 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7987
7988 ++vcpu->stat.exits;
7989
f2485b3e 7990 guest_exit_irqoff();
ec0671d5
WL		 7991 if (lapic_in_kernel(vcpu)) {
7992 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
7993 if (delta != S64_MIN) {
7994 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
7995 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
7996 }
7997 }
b6c7a5dc 7998
f2485b3e 7999 local_irq_enable();
b6c7a5dc
HB		 8000 preempt_enable();
8001
f656ce01 8002 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 8003
b6c7a5dc
HB		 8004 /*
8005 * Profile KVM exit RIPs:
8006 */
8007 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 8008 unsigned long rip = kvm_rip_read(vcpu);
8009 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 8010 }
8011
cc578287
ZA		 8012 if (unlikely(vcpu->arch.tsc_always_catchup))
8013 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 8014
5cfb1d5a
MT		 8015 if (vcpu->arch.apic_attention)
8016 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 8017
618232e2 8018 vcpu->arch.gpa_available = false;
851ba692 8019 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 8020 return r;
8021
8022cancel_injection:
8023 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 8024 if (unlikely(vcpu->arch.apic_attention))
8025 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 8026out:
8027 return r;
8028}
b6c7a5dc 8029
362c698f
PB		 8030static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8031{
bf9f6ac8
FW		 8032 if (!kvm_arch_vcpu_runnable(vcpu) &&
8033 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 8034 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8035 kvm_vcpu_block(vcpu);
8036 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 8037
8038 if (kvm_x86_ops->post_block)
8039 kvm_x86_ops->post_block(vcpu);
8040
9c8fd1ba
PB		 8041 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8042 return 1;
8043 }
362c698f
PB		 8044
8045 kvm_apic_accept_events(vcpu);
8046 switch(vcpu->arch.mp_state) {
8047 case KVM_MP_STATE_HALTED:
8048 vcpu->arch.pv.pv_unhalted = false;
8049 vcpu->arch.mp_state =
8050 KVM_MP_STATE_RUNNABLE;
b2869f28 8051 /* fall through */
362c698f
PB		 8052 case KVM_MP_STATE_RUNNABLE:
8053 vcpu->arch.apf.halted = false;
8054 break;
8055 case KVM_MP_STATE_INIT_RECEIVED:
8056 break;
8057 default:
8058 return -EINTR;
8059 break;
8060 }
8061 return 1;
8062}
09cec754 8063
5d9bc648
PB		 8064static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8065{
0ad3bed6
PB		 8066 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8067 kvm_x86_ops->check_nested_events(vcpu, false);
8068
5d9bc648
PB		 8069 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8070 !vcpu->arch.apf.halted);
8071}
8072
362c698f 8073static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8074{
8075 int r;
f656ce01 8076 struct kvm *kvm = vcpu->kvm;
d7690175 8077
f656ce01 8078 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8079 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8080
362c698f 8081 for (;;) {
58f800d5 8082 if (kvm_vcpu_running(vcpu)) {
851ba692 8083 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8084 } else {
362c698f 8085 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8086 }
8087
09cec754
GN		 8088 if (r <= 0)
8089 break;
8090
72875d8a 8091 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8092 if (kvm_cpu_has_pending_timer(vcpu))
8093 kvm_inject_pending_timer_irqs(vcpu);
8094
782d422b
MG		 8095 if (dm_request_for_irq_injection(vcpu) &&
8096 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8097 r = 0;
8098 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8099 ++vcpu->stat.request_irq_exits;
362c698f 8100 break;
09cec754 8101 }
af585b92
GN		 8102
8103 kvm_check_async_pf_completion(vcpu);
8104
09cec754
GN		 8105 if (signal_pending(current)) {
8106 r = -EINTR;
851ba692 8107 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8108 ++vcpu->stat.signal_exits;
362c698f 8109 break;
09cec754
GN		 8110 }
8111 if (need_resched()) {
f656ce01 8112 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8113 cond_resched();
f656ce01 8114 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8115 }
b6c7a5dc
HB		 8116 }
8117
f656ce01 8118 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8119
8120 return r;
8121}
8122
716d51ab
GN		 8123static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8124{
8125 int r;
8126 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8127 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 8128 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8129 if (r != EMULATE_DONE)
8130 return 0;
8131 return 1;
8132}
8133
8134static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8135{
8136 BUG_ON(!vcpu->arch.pio.count);
8137
8138 return complete_emulated_io(vcpu);
8139}
8140
f78146b0
AK		 8141/*
8142 * Implements the following, as a state machine:
8143 *
8144 * read:
8145 * for each fragment
87da7e66
XG		 8146 * for each mmio piece in the fragment
8147 * write gpa, len
8148 * exit
8149 * copy data
f78146b0
AK		 8150 * execute insn
8151 *
8152 * write:
8153 * for each fragment
87da7e66
XG		 8154 * for each mmio piece in the fragment
8155 * write gpa, len
8156 * copy data
8157 * exit
f78146b0 8158 */
716d51ab 8159static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8160{
8161 struct kvm_run *run = vcpu->run;
f78146b0 8162 struct kvm_mmio_fragment *frag;
87da7e66 8163 unsigned len;
5287f194 8164
716d51ab 8165 BUG_ON(!vcpu->mmio_needed);
5287f194 8166
716d51ab 8167 /* Complete previous fragment */
87da7e66
XG		 8168 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8169 len = min(8u, frag->len);
716d51ab 8170 if (!vcpu->mmio_is_write)
87da7e66
XG		 8171 memcpy(frag->data, run->mmio.data, len);
8172
8173 if (frag->len <= 8) {
8174 /* Switch to the next fragment. */
8175 frag++;
8176 vcpu->mmio_cur_fragment++;
8177 } else {
8178 /* Go forward to the next mmio piece. */
8179 frag->data += len;
8180 frag->gpa += len;
8181 frag->len -= len;
8182 }
8183
a08d3b3b 8184 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8185 vcpu->mmio_needed = 0;
0912c977
PB		 8186
8187 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8188 if (vcpu->mmio_is_write)
716d51ab
GN		 8189 return 1;
8190 vcpu->mmio_read_completed = 1;
8191 return complete_emulated_io(vcpu);
8192 }
87da7e66 8193
716d51ab
GN		 8194 run->exit_reason = KVM_EXIT_MMIO;
8195 run->mmio.phys_addr = frag->gpa;
8196 if (vcpu->mmio_is_write)
87da7e66
XG		 8197 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8198 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8199 run->mmio.is_write = vcpu->mmio_is_write;
8200 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8201 return 0;
5287f194
AK		 8202}
8203
822f312d
SAS		 8204/* Swap (qemu) user FPU context for the guest FPU context. */
8205static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8206{
5f409e20
RR		 8207 fpregs_lock();
8208
240c35a3 8209 copy_fpregs_to_fpstate(&current->thread.fpu);
822f312d 8210 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8211 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d 8212 ~XFEATURE_MASK_PKRU);
5f409e20
RR		 8213
8214 fpregs_mark_activate();
8215 fpregs_unlock();
8216
822f312d
SAS		 8217 trace_kvm_fpu(1);
8218}
8219
8220/* When vcpu_run ends, restore user space FPU context. */
8221static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8222{
5f409e20
RR		 8223 fpregs_lock();
8224
b666a4b6 8225 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
240c35a3 8226 copy_kernel_to_fpregs(&current->thread.fpu.state);
5f409e20
RR		 8227
8228 fpregs_mark_activate();
8229 fpregs_unlock();
8230
822f312d
SAS		 8231 ++vcpu->stat.fpu_reload;
8232 trace_kvm_fpu(0);
8233}
8234
b6c7a5dc
HB		 8235int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8236{
8237 int r;
b6c7a5dc 8238
accb757d 8239 vcpu_load(vcpu);
20b7035c 8240 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8241 kvm_load_guest_fpu(vcpu);
8242
a4535290 8243 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8244 if (kvm_run->immediate_exit) {
8245 r = -EINTR;
8246 goto out;
8247 }
b6c7a5dc 8248 kvm_vcpu_block(vcpu);
66450a21 8249 kvm_apic_accept_events(vcpu);
72875d8a 8250 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8251 r = -EAGAIN;
a0595000
JS		 8252 if (signal_pending(current)) {
8253 r = -EINTR;
8254 vcpu->run->exit_reason = KVM_EXIT_INTR;
8255 ++vcpu->stat.signal_exits;
8256 }
ac9f6dc0 8257 goto out;
b6c7a5dc
HB		 8258 }
8259
01643c51
KH		 8260 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8261 r = -EINVAL;
8262 goto out;
8263 }
8264
8265 if (vcpu->run->kvm_dirty_regs) {
8266 r = sync_regs(vcpu);
8267 if (r != 0)
8268 goto out;
8269 }
8270
b6c7a5dc 8271 /* re-sync apic's tpr */
35754c98 8272 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8273 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8274 r = -EINVAL;
8275 goto out;
8276 }
8277 }
b6c7a5dc 8278
716d51ab
GN		 8279 if (unlikely(vcpu->arch.complete_userspace_io)) {
8280 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8281 vcpu->arch.complete_userspace_io = NULL;
8282 r = cui(vcpu);
8283 if (r <= 0)
5663d8f9 8284 goto out;
716d51ab
GN		 8285 } else
8286 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8287
460df4c1
PB		 8288 if (kvm_run->immediate_exit)
8289 r = -EINTR;
8290 else
8291 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8292
8293out:
5663d8f9 8294 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8295 if (vcpu->run->kvm_valid_regs)
8296 store_regs(vcpu);
f1d86e46 8297 post_kvm_run_save(vcpu);
20b7035c 8298 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8299
accb757d 8300 vcpu_put(vcpu);
b6c7a5dc
HB		 8301 return r;
8302}
8303
01643c51 8304static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8305{
7ae441ea
GN		 8306 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8307 /*
8308 * We are here if userspace calls get_regs() in the middle of
8309 * instruction emulation. Registers state needs to be copied
4a969980 8310 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8311 * that usually, but some bad designed PV devices (vmware
8312 * backdoor interface) need this to work
8313 */
dd856efa 8314 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8315 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8316 }
de3cd117
SC		 8317 regs->rax = kvm_rax_read(vcpu);
8318 regs->rbx = kvm_rbx_read(vcpu);
8319 regs->rcx = kvm_rcx_read(vcpu);
8320 regs->rdx = kvm_rdx_read(vcpu);
8321 regs->rsi = kvm_rsi_read(vcpu);
8322 regs->rdi = kvm_rdi_read(vcpu);
e9c16c78 8323 regs->rsp = kvm_rsp_read(vcpu);
de3cd117 8324 regs->rbp = kvm_rbp_read(vcpu);
b6c7a5dc 8325#ifdef CONFIG_X86_64
de3cd117
SC		 8326 regs->r8 = kvm_r8_read(vcpu);
8327 regs->r9 = kvm_r9_read(vcpu);
8328 regs->r10 = kvm_r10_read(vcpu);
8329 regs->r11 = kvm_r11_read(vcpu);
8330 regs->r12 = kvm_r12_read(vcpu);
8331 regs->r13 = kvm_r13_read(vcpu);
8332 regs->r14 = kvm_r14_read(vcpu);
8333 regs->r15 = kvm_r15_read(vcpu);
b6c7a5dc
HB		 8334#endif
8335
5fdbf976 8336 regs->rip = kvm_rip_read(vcpu);
91586a3b 8337 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8338}
b6c7a5dc 8339
01643c51
KH		 8340int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8341{
8342 vcpu_load(vcpu);
8343 __get_regs(vcpu, regs);
1fc9b76b 8344 vcpu_put(vcpu);
b6c7a5dc
HB		 8345 return 0;
8346}
8347
01643c51 8348static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8349{
7ae441ea
GN		 8350 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8351 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8352
de3cd117
SC		 8353 kvm_rax_write(vcpu, regs->rax);
8354 kvm_rbx_write(vcpu, regs->rbx);
8355 kvm_rcx_write(vcpu, regs->rcx);
8356 kvm_rdx_write(vcpu, regs->rdx);
8357 kvm_rsi_write(vcpu, regs->rsi);
8358 kvm_rdi_write(vcpu, regs->rdi);
e9c16c78 8359 kvm_rsp_write(vcpu, regs->rsp);
de3cd117 8360 kvm_rbp_write(vcpu, regs->rbp);
b6c7a5dc 8361#ifdef CONFIG_X86_64
de3cd117
SC		 8362 kvm_r8_write(vcpu, regs->r8);
8363 kvm_r9_write(vcpu, regs->r9);
8364 kvm_r10_write(vcpu, regs->r10);
8365 kvm_r11_write(vcpu, regs->r11);
8366 kvm_r12_write(vcpu, regs->r12);
8367 kvm_r13_write(vcpu, regs->r13);
8368 kvm_r14_write(vcpu, regs->r14);
8369 kvm_r15_write(vcpu, regs->r15);
b6c7a5dc
HB		 8370#endif
8371
5fdbf976 8372 kvm_rip_write(vcpu, regs->rip);
d73235d1 8373 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8374
b4f14abd
JK		 8375 vcpu->arch.exception.pending = false;
8376
3842d135 8377 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8378}
3842d135 8379
01643c51
KH		 8380int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8381{
8382 vcpu_load(vcpu);
8383 __set_regs(vcpu, regs);
875656fe 8384 vcpu_put(vcpu);
b6c7a5dc
HB		 8385 return 0;
8386}
8387
b6c7a5dc
HB		 8388void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8389{
8390 struct kvm_segment cs;
8391
3e6e0aab 8392 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8393 *db = cs.db;
8394 *l = cs.l;
8395}
8396EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8397
01643c51 8398static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8399{
89a27f4d 8400 struct desc_ptr dt;
b6c7a5dc 8401
3e6e0aab
GT		 8402 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8403 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8404 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8405 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8406 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8407 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8408
3e6e0aab
GT		 8409 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8410 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8411
8412 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8413 sregs->idt.limit = dt.size;
8414 sregs->idt.base = dt.address;
b6c7a5dc 8415 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8416 sregs->gdt.limit = dt.size;
8417 sregs->gdt.base = dt.address;
b6c7a5dc 8418
4d4ec087 8419 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8420 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8421 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8422 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8423 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8424 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8425 sregs->apic_base = kvm_get_apic_base(vcpu);
8426
0e96f31e 8427 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8428
04140b41 8429 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8430 set_bit(vcpu->arch.interrupt.nr,
8431 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8432}
16d7a191 8433
01643c51
KH		 8434int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8435 struct kvm_sregs *sregs)
8436{
8437 vcpu_load(vcpu);
8438 __get_sregs(vcpu, sregs);
bcdec41c 8439 vcpu_put(vcpu);
b6c7a5dc
HB		 8440 return 0;
8441}
8442
62d9f0db
MT		 8443int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8444 struct kvm_mp_state *mp_state)
8445{
fd232561
CD		 8446 vcpu_load(vcpu);
8447
66450a21 8448 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8449 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8450 vcpu->arch.pv.pv_unhalted)
8451 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8452 else
8453 mp_state->mp_state = vcpu->arch.mp_state;
8454
fd232561 8455 vcpu_put(vcpu);
62d9f0db
MT		 8456 return 0;
8457}
8458
8459int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8460 struct kvm_mp_state *mp_state)
8461{
e83dff5e
CD		 8462 int ret = -EINVAL;
8463
8464 vcpu_load(vcpu);
8465
bce87cce 8466 if (!lapic_in_kernel(vcpu) &&
66450a21 8467 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8468 goto out;
66450a21 8469
28bf2888
DH		 8470 /* INITs are latched while in SMM */
8471 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8472 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8473 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8474 goto out;
28bf2888 8475
66450a21
JK		 8476 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8477 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8478 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8479 } else
8480 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8481 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8482
8483 ret = 0;
8484out:
8485 vcpu_put(vcpu);
8486 return ret;
62d9f0db
MT		 8487}
8488
7f3d35fd
KW		 8489int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8490 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8491{
9d74191a 8492 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8493 int ret;
e01c2426 8494
8ec4722d 8495 init_emulate_ctxt(vcpu);
c697518a 8496
7f3d35fd 8497 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8498 has_error_code, error_code);
c697518a 8499
c697518a 8500 if (ret)
19d04437 8501 return EMULATE_FAIL;
37817f29 8502
9d74191a
TY		 8503 kvm_rip_write(vcpu, ctxt->eip);
8504 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8505 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8506 return EMULATE_DONE;
37817f29
IE		 8507}
8508EXPORT_SYMBOL_GPL(kvm_task_switch);
8509
3140c156 8510static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8511{
74fec5b9
TL		 8512 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8513 (sregs->cr4 & X86_CR4_OSXSAVE))
8514 return -EINVAL;
8515
37b95951 8516 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8517 /*
8518 * When EFER.LME and CR0.PG are set, the processor is in
8519 * 64-bit mode (though maybe in a 32-bit code segment).
8520 * CR4.PAE and EFER.LMA must be set.
8521 */
37b95951 8522 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8523 || !(sregs->efer & EFER_LMA))
8524 return -EINVAL;
8525 } else {
8526 /*
8527 * Not in 64-bit mode: EFER.LMA is clear and the code
8528 * segment cannot be 64-bit.
8529 */
8530 if (sregs->efer & EFER_LMA || sregs->cs.l)
8531 return -EINVAL;
8532 }
8533
8534 return 0;
8535}
8536
01643c51 8537static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8538{
58cb628d 8539 struct msr_data apic_base_msr;
b6c7a5dc 8540 int mmu_reset_needed = 0;
c4d21882 8541 int cpuid_update_needed = 0;
63f42e02 8542 int pending_vec, max_bits, idx;
89a27f4d 8543 struct desc_ptr dt;
b4ef9d4e
CD		 8544 int ret = -EINVAL;
8545
f2981033 8546 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8547 goto out;
f2981033 8548
d3802286
JM		 8549 apic_base_msr.data = sregs->apic_base;
8550 apic_base_msr.host_initiated = true;
8551 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8552 goto out;
6d1068b3 8553
89a27f4d
GN		 8554 dt.size = sregs->idt.limit;
8555 dt.address = sregs->idt.base;
b6c7a5dc 8556 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8557 dt.size = sregs->gdt.limit;
8558 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8559 kvm_x86_ops->set_gdt(vcpu, &dt);
8560
ad312c7c 8561 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8562 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8563 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8564 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8565
2d3ad1f4 8566 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8567
f6801dff 8568 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8569 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8570
4d4ec087 8571 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8572 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8573 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8574
fc78f519 8575 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8576 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8577 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8578 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8579 if (cpuid_update_needed)
00b27a3e 8580 kvm_update_cpuid(vcpu);
63f42e02
XG		 8581
8582 idx = srcu_read_lock(&vcpu->kvm->srcu);
d35b34a9 8583 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
9f8fe504 8584 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8585 mmu_reset_needed = 1;
8586 }
63f42e02 8587 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8588
8589 if (mmu_reset_needed)
8590 kvm_mmu_reset_context(vcpu);
8591
a50abc3b 8592 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8593 pending_vec = find_first_bit(
8594 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8595 if (pending_vec < max_bits) {
66fd3f7f 8596 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8597 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8598 }
8599
3e6e0aab
GT		 8600 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8601 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8602 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8603 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8604 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8605 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8606
3e6e0aab
GT		 8607 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8608 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8609
5f0269f5
ME		 8610 update_cr8_intercept(vcpu);
8611
9c3e4aab 8612 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8613 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8614 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8615 !is_protmode(vcpu))
9c3e4aab
MT		 8616 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8617
3842d135
AK		 8618 kvm_make_request(KVM_REQ_EVENT, vcpu);
8619
b4ef9d4e
CD		 8620 ret = 0;
8621out:
01643c51
KH		 8622 return ret;
8623}
8624
8625int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8626 struct kvm_sregs *sregs)
8627{
8628 int ret;
8629
8630 vcpu_load(vcpu);
8631 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8632 vcpu_put(vcpu);
8633 return ret;
b6c7a5dc
HB		 8634}
8635
d0bfb940
JK		 8636int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8637 struct kvm_guest_debug *dbg)
b6c7a5dc 8638{
355be0b9 8639 unsigned long rflags;
ae675ef0 8640 int i, r;
b6c7a5dc 8641
66b56562
CD		 8642 vcpu_load(vcpu);
8643
4f926bf2
JK		 8644 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8645 r = -EBUSY;
8646 if (vcpu->arch.exception.pending)
2122ff5e 8647 goto out;
4f926bf2
JK		 8648 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8649 kvm_queue_exception(vcpu, DB_VECTOR);
8650 else
8651 kvm_queue_exception(vcpu, BP_VECTOR);
8652 }
8653
91586a3b
JK		 8654 /*
8655 * Read rflags as long as potentially injected trace flags are still
8656 * filtered out.
8657 */
8658 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8659
8660 vcpu->guest_debug = dbg->control;
8661 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8662 vcpu->guest_debug = 0;
8663
8664 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8665 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8666 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8667 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8668 } else {
8669 for (i = 0; i < KVM_NR_DB_REGS; i++)
8670 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8671 }
c8639010 8672 kvm_update_dr7(vcpu);
ae675ef0 8673
f92653ee
JK		 8674 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8675 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8676 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8677
91586a3b
JK		 8678 /*
8679 * Trigger an rflags update that will inject or remove the trace
8680 * flags.
8681 */
8682 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8683
a96036b8 8684 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8685
4f926bf2 8686 r = 0;
d0bfb940 8687
2122ff5e 8688out:
66b56562 8689 vcpu_put(vcpu);
b6c7a5dc
HB		 8690 return r;
8691}
8692
8b006791
ZX		 8693/*
8694 * Translate a guest virtual address to a guest physical address.
8695 */
8696int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8697 struct kvm_translation *tr)
8698{
8699 unsigned long vaddr = tr->linear_address;
8700 gpa_t gpa;
f656ce01 8701 int idx;
8b006791 8702
1da5b61d
CD		 8703 vcpu_load(vcpu);
8704
f656ce01 8705 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8706 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8707 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8708 tr->physical_address = gpa;
8709 tr->valid = gpa != UNMAPPED_GVA;
8710 tr->writeable = 1;
8711 tr->usermode = 0;
8b006791 8712
1da5b61d 8713 vcpu_put(vcpu);
8b006791
ZX		 8714 return 0;
8715}
8716
d0752060
HB		 8717int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8718{
1393123e 8719 struct fxregs_state *fxsave;
d0752060 8720
1393123e 8721 vcpu_load(vcpu);
d0752060 8722
b666a4b6 8723 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8724 memcpy(fpu->fpr, fxsave->st_space, 128);
8725 fpu->fcw = fxsave->cwd;
8726 fpu->fsw = fxsave->swd;
8727 fpu->ftwx = fxsave->twd;
8728 fpu->last_opcode = fxsave->fop;
8729 fpu->last_ip = fxsave->rip;
8730 fpu->last_dp = fxsave->rdp;
0e96f31e 8731 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8732
1393123e 8733 vcpu_put(vcpu);
d0752060
HB		 8734 return 0;
8735}
8736
8737int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8738{
6a96bc7f
CD		 8739 struct fxregs_state *fxsave;
8740
8741 vcpu_load(vcpu);
8742
b666a4b6 8743 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8744
d0752060
HB		 8745 memcpy(fxsave->st_space, fpu->fpr, 128);
8746 fxsave->cwd = fpu->fcw;
8747 fxsave->swd = fpu->fsw;
8748 fxsave->twd = fpu->ftwx;
8749 fxsave->fop = fpu->last_opcode;
8750 fxsave->rip = fpu->last_ip;
8751 fxsave->rdp = fpu->last_dp;
0e96f31e 8752 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8753
6a96bc7f 8754 vcpu_put(vcpu);
d0752060
HB		 8755 return 0;
8756}
8757
01643c51
KH		 8758static void store_regs(struct kvm_vcpu *vcpu)
8759{
8760 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8761
8762 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8763 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8764
8765 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8766 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8767
8768 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8769 kvm_vcpu_ioctl_x86_get_vcpu_events(
8770 vcpu, &vcpu->run->s.regs.events);
8771}
8772
8773static int sync_regs(struct kvm_vcpu *vcpu)
8774{
8775 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8776 return -EINVAL;
8777
8778 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8779 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8780 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8781 }
8782 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8783 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8784 return -EINVAL;
8785 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8786 }
8787 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8788 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8789 vcpu, &vcpu->run->s.regs.events))
8790 return -EINVAL;
8791 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8792 }
8793
8794 return 0;
8795}
8796
0ee6a517 8797static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8798{
b666a4b6 8799 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 8800 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 8801 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 8802 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8803
2acf923e
DC		 8804 /*
8805 * Ensure guest xcr0 is valid for loading
8806 */
d91cab78 8807 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8808
ad312c7c 8809 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8810}
d0752060 8811
e9b11c17
ZX		 8812void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8813{
bd768e14
IY		 8814 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8815
12f9a48f 8816 kvmclock_reset(vcpu);
7f1ea208 8817
e9b11c17 8818 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8819 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8820}
8821
8822struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8823 unsigned int id)
8824{
c447e76b
LL		 8825 struct kvm_vcpu *vcpu;
8826
b0c39dc6 8827 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8828 printk_once(KERN_WARNING
8829 "kvm: SMP vm created on host with unstable TSC; "
8830 "guest TSC will not be reliable\n");
c447e76b
LL		 8831
8832 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8833
c447e76b 8834 return vcpu;
26e5215f 8835}
e9b11c17 8836
26e5215f
AK		 8837int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8838{
0cf9135b 8839 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 8840 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 8841 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8842 vcpu_load(vcpu);
d28bc9dd 8843 kvm_vcpu_reset(vcpu, false);
e1732991 8844 kvm_init_mmu(vcpu, false);
e9b11c17 8845 vcpu_put(vcpu);
ec7660cc 8846 return 0;
e9b11c17
ZX		 8847}
8848
31928aa5 8849void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8850{
8fe8ab46 8851 struct msr_data msr;
332967a3 8852 struct kvm *kvm = vcpu->kvm;
42897d86 8853
d3457c87
RK		 8854 kvm_hv_vcpu_postcreate(vcpu);
8855
ec7660cc 8856 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8857 return;
ec7660cc 8858 vcpu_load(vcpu);
8fe8ab46
WA		 8859 msr.data = 0x0;
8860 msr.index = MSR_IA32_TSC;
8861 msr.host_initiated = true;
8862 kvm_write_tsc(vcpu, &msr);
42897d86 8863 vcpu_put(vcpu);
ec7660cc 8864 mutex_unlock(&vcpu->mutex);
42897d86 8865
630994b3
MT		 8866 if (!kvmclock_periodic_sync)
8867 return;
8868
332967a3
AJ		 8869 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8870 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8871}
8872
d40ccc62 8873void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8874{
344d9588
GN		 8875 vcpu->arch.apf.msr_val = 0;
8876
ec7660cc 8877 vcpu_load(vcpu);
e9b11c17
ZX		 8878 kvm_mmu_unload(vcpu);
8879 vcpu_put(vcpu);
8880
8881 kvm_x86_ops->vcpu_free(vcpu);
8882}
8883
d28bc9dd 8884void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8885{
b7e31be3
RK		 8886 kvm_lapic_reset(vcpu, init_event);
8887
e69fab5d
PB		 8888 vcpu->arch.hflags = 0;
8889
c43203ca 8890 vcpu->arch.smi_pending = 0;
52797bf9 8891 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8892 atomic_set(&vcpu->arch.nmi_queued, 0);
8893 vcpu->arch.nmi_pending = 0;
448fa4a9 8894 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8895 kvm_clear_interrupt_queue(vcpu);
8896 kvm_clear_exception_queue(vcpu);
664f8e26 8897 vcpu->arch.exception.pending = false;
448fa4a9 8898
42dbaa5a 8899 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8900 kvm_update_dr0123(vcpu);
6f43ed01 8901 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8902 kvm_update_dr6(vcpu);
42dbaa5a 8903 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8904 kvm_update_dr7(vcpu);
42dbaa5a 8905
1119022c
NA		 8906 vcpu->arch.cr2 = 0;
8907
3842d135 8908 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8909 vcpu->arch.apf.msr_val = 0;
c9aaa895 8910 vcpu->arch.st.msr_val = 0;
3842d135 8911
12f9a48f
GC		 8912 kvmclock_reset(vcpu);
8913
af585b92
GN		 8914 kvm_clear_async_pf_completion_queue(vcpu);
8915 kvm_async_pf_hash_reset(vcpu);
8916 vcpu->arch.apf.halted = false;
3842d135 8917
a554d207
WL		 8918 if (kvm_mpx_supported()) {
8919 void *mpx_state_buffer;
8920
8921 /*
8922 * To avoid have the INIT path from kvm_apic_has_events() that be
8923 * called with loaded FPU and does not let userspace fix the state.
8924 */
f775b13e
RR		 8925 if (init_event)
8926 kvm_put_guest_fpu(vcpu);
b666a4b6 8927 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 8928 XFEATURE_BNDREGS);
a554d207
WL		 8929 if (mpx_state_buffer)
8930 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 8931 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 8932 XFEATURE_BNDCSR);
a554d207
WL		 8933 if (mpx_state_buffer)
8934 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8935 if (init_event)
8936 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8937 }
8938
64d60670 8939 if (!init_event) {
d28bc9dd 8940 kvm_pmu_reset(vcpu);
64d60670 8941 vcpu->arch.smbase = 0x30000;
db2336a8 8942
db2336a8 8943 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8944
8945 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8946 }
f5132b01 8947
66f7b72e
JS		 8948 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8949 vcpu->arch.regs_avail = ~0;
8950 vcpu->arch.regs_dirty = ~0;
8951
a554d207
WL		 8952 vcpu->arch.ia32_xss = 0;
8953
d28bc9dd 8954 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8955}
8956
2b4a273b 8957void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8958{
8959 struct kvm_segment cs;
8960
8961 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8962 cs.selector = vector << 8;
8963 cs.base = vector << 12;
8964 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8965 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8966}
8967
13a34e06 8968int kvm_arch_hardware_enable(void)
e9b11c17 8969{
ca84d1a2
ZA		 8970 struct kvm *kvm;
8971 struct kvm_vcpu *vcpu;
8972 int i;
0dd6a6ed
ZA		 8973 int ret;
8974 u64 local_tsc;
8975 u64 max_tsc = 0;
8976 bool stable, backwards_tsc = false;
18863bdd
AK		 8977
8978 kvm_shared_msr_cpu_online();
13a34e06 8979 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8980 if (ret != 0)
8981 return ret;
8982
4ea1636b 8983 local_tsc = rdtsc();
b0c39dc6 8984 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8985 list_for_each_entry(kvm, &vm_list, vm_list) {
8986 kvm_for_each_vcpu(i, vcpu, kvm) {
8987 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8988 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8989 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8990 backwards_tsc = true;
8991 if (vcpu->arch.last_host_tsc > max_tsc)
8992 max_tsc = vcpu->arch.last_host_tsc;
8993 }
8994 }
8995 }
8996
8997 /*
8998 * Sometimes, even reliable TSCs go backwards. This happens on
8999 * platforms that reset TSC during suspend or hibernate actions, but
9000 * maintain synchronization. We must compensate. Fortunately, we can
9001 * detect that condition here, which happens early in CPU bringup,
9002 * before any KVM threads can be running. Unfortunately, we can't
9003 * bring the TSCs fully up to date with real time, as we aren't yet far
9004 * enough into CPU bringup that we know how much real time has actually
108b249c 9005 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 9006 * variables that haven't been updated yet.
9007 *
9008 * So we simply find the maximum observed TSC above, then record the
9009 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9010 * the adjustment will be applied. Note that we accumulate
9011 * adjustments, in case multiple suspend cycles happen before some VCPU
9012 * gets a chance to run again. In the event that no KVM threads get a
9013 * chance to run, we will miss the entire elapsed period, as we'll have
9014 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9015 * loose cycle time. This isn't too big a deal, since the loss will be
9016 * uniform across all VCPUs (not to mention the scenario is extremely
9017 * unlikely). It is possible that a second hibernate recovery happens
9018 * much faster than a first, causing the observed TSC here to be
9019 * smaller; this would require additional padding adjustment, which is
9020 * why we set last_host_tsc to the local tsc observed here.
9021 *
9022 * N.B. - this code below runs only on platforms with reliable TSC,
9023 * as that is the only way backwards_tsc is set above. Also note
9024 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9025 * have the same delta_cyc adjustment applied if backwards_tsc
9026 * is detected. Note further, this adjustment is only done once,
9027 * as we reset last_host_tsc on all VCPUs to stop this from being
9028 * called multiple times (one for each physical CPU bringup).
9029 *
4a969980 9030 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 9031 * will be compensated by the logic in vcpu_load, which sets the TSC to
9032 * catchup mode. This will catchup all VCPUs to real time, but cannot
9033 * guarantee that they stay in perfect synchronization.
9034 */
9035 if (backwards_tsc) {
9036 u64 delta_cyc = max_tsc - local_tsc;
9037 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 9038 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 9039 kvm_for_each_vcpu(i, vcpu, kvm) {
9040 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9041 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 9042 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9043 }
9044
9045 /*
9046 * We have to disable TSC offset matching.. if you were
9047 * booting a VM while issuing an S4 host suspend....
9048 * you may have some problem. Solving this issue is
9049 * left as an exercise to the reader.
9050 */
9051 kvm->arch.last_tsc_nsec = 0;
9052 kvm->arch.last_tsc_write = 0;
9053 }
9054
9055 }
9056 return 0;
e9b11c17
ZX		 9057}
9058
13a34e06 9059void kvm_arch_hardware_disable(void)
e9b11c17 9060{
13a34e06
RK		 9061 kvm_x86_ops->hardware_disable();
9062 drop_user_return_notifiers();
e9b11c17
ZX		 9063}
9064
9065int kvm_arch_hardware_setup(void)
9066{
9e9c3fe4
NA		 9067 int r;
9068
9069 r = kvm_x86_ops->hardware_setup();
9070 if (r != 0)
9071 return r;
9072
35181e86
HZ		 9073 if (kvm_has_tsc_control) {
9074 /*
9075 * Make sure the user can only configure tsc_khz values that
9076 * fit into a signed integer.
273ba457 9077 * A min value is not calculated because it will always
35181e86
HZ		 9078 * be 1 on all machines.
9079 */
9080 u64 max = min(0x7fffffffULL,
9081 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9082 kvm_max_guest_tsc_khz = max;
9083
ad721883 9084 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9085 }
ad721883 9086
9e9c3fe4
NA		 9087 kvm_init_msr_list();
9088 return 0;
e9b11c17
ZX		 9089}
9090
9091void kvm_arch_hardware_unsetup(void)
9092{
9093 kvm_x86_ops->hardware_unsetup();
9094}
9095
f257d6dc 9096int kvm_arch_check_processor_compat(void)
e9b11c17 9097{
f257d6dc 9098 return kvm_x86_ops->check_processor_compatibility();
d71ba788
PB		 9099}
9100
9101bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9102{
9103 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9104}
9105EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9106
9107bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9108{
9109 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9110}
9111
54e9818f 9112struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9113EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9114
e9b11c17
ZX		 9115int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9116{
9117 struct page *page;
e9b11c17
ZX		 9118 int r;
9119
9aabc88f 9120 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9121 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9122 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9123 else
a4535290 9124 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9125
9126 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9127 if (!page) {
9128 r = -ENOMEM;
9129 goto fail;
9130 }
ad312c7c 9131 vcpu->arch.pio_data = page_address(page);
e9b11c17 9132
cc578287 9133 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9134
e9b11c17
ZX		 9135 r = kvm_mmu_create(vcpu);
9136 if (r < 0)
9137 goto fail_free_pio_data;
9138
26de7988 9139 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9140 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
39497d76 9141 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
e9b11c17
ZX		 9142 if (r < 0)
9143 goto fail_mmu_destroy;
54e9818f
GN		 9144 } else
9145 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9146
890ca9ae 9147 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
254272ce 9148 GFP_KERNEL_ACCOUNT);
890ca9ae
HY		 9149 if (!vcpu->arch.mce_banks) {
9150 r = -ENOMEM;
443c39bc 9151 goto fail_free_lapic;
890ca9ae
HY		 9152 }
9153 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9154
254272ce
BG		 9155 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9156 GFP_KERNEL_ACCOUNT)) {
f1797359 9157 r = -ENOMEM;
f5f48ee1 9158 goto fail_free_mce_banks;
f1797359 9159 }
f5f48ee1 9160
0ee6a517 9161 fx_init(vcpu);
66f7b72e 9162
4344ee98 9163 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9164
5a4f55cd
EK		 9165 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9166
74545705
RK		 9167 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9168
af585b92 9169 kvm_async_pf_hash_reset(vcpu);
f5132b01 9170 kvm_pmu_init(vcpu);
af585b92 9171
1c1a9ce9 9172 vcpu->arch.pending_external_vector = -1;
de63ad4c 9173 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9174
5c919412
AS		 9175 kvm_hv_vcpu_init(vcpu);
9176
e9b11c17 9177 return 0;
0ee6a517 9178
f5f48ee1
SY		 9179fail_free_mce_banks:
9180 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9181fail_free_lapic:
9182 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9183fail_mmu_destroy:
9184 kvm_mmu_destroy(vcpu);
9185fail_free_pio_data:
ad312c7c 9186 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9187fail:
9188 return r;
9189}
9190
9191void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9192{
f656ce01
MT		 9193 int idx;
9194
1f4b34f8 9195 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9196 kvm_pmu_destroy(vcpu);
36cb93fd 9197 kfree(vcpu->arch.mce_banks);
e9b11c17 9198 kvm_free_lapic(vcpu);
f656ce01 9199 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9200 kvm_mmu_destroy(vcpu);
f656ce01 9201 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9202 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9203 if (!lapic_in_kernel(vcpu))
54e9818f 9204 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9205}
d19a9cd2 9206
e790d9ef
RK		 9207void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9208{
c595ceee 9209 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9210 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9211}
9212
e08b9637 9213int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9214{
e08b9637
CO		 9215 if (type)
9216 return -EINVAL;
9217
6ef768fa 9218 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9219 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 9220 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9221 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9222
5550af4d
SY		 9223 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9224 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9225 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9226 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9227 &kvm->arch.irq_sources_bitmap);
5550af4d 9228
038f8c11 9229 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9230 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9231 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9232
108b249c 9233 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 9234 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9235
6fbbde9a
DS		 9236 kvm->arch.guest_can_read_msr_platform_info = true;
9237
7e44e449 9238 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9239 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9240
cbc0236a 9241 kvm_hv_init_vm(kvm);
0eb05bf2 9242 kvm_page_track_init(kvm);
13d268ca 9243 kvm_mmu_init_vm(kvm);
0eb05bf2 9244
03543133
SS		 9245 if (kvm_x86_ops->vm_init)
9246 return kvm_x86_ops->vm_init(kvm);
9247
d89f5eff 9248 return 0;
d19a9cd2
ZX		 9249}
9250
9251static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9252{
ec7660cc 9253 vcpu_load(vcpu);
d19a9cd2
ZX		 9254 kvm_mmu_unload(vcpu);
9255 vcpu_put(vcpu);
9256}
9257
9258static void kvm_free_vcpus(struct kvm *kvm)
9259{
9260 unsigned int i;
988a2cae 9261 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9262
9263 /*
9264 * Unpin any mmu pages first.
9265 */
af585b92
GN		 9266 kvm_for_each_vcpu(i, vcpu, kvm) {
9267 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9268 kvm_unload_vcpu_mmu(vcpu);
af585b92 9269 }
988a2cae
GN		 9270 kvm_for_each_vcpu(i, vcpu, kvm)
9271 kvm_arch_vcpu_free(vcpu);
9272
9273 mutex_lock(&kvm->lock);
9274 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9275 kvm->vcpus[i] = NULL;
d19a9cd2 9276
988a2cae
GN		 9277 atomic_set(&kvm->online_vcpus, 0);
9278 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9279}
9280
ad8ba2cd
SY		 9281void kvm_arch_sync_events(struct kvm *kvm)
9282{
332967a3 9283 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9284 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9285 kvm_free_pit(kvm);
ad8ba2cd
SY		 9286}
9287
1d8007bd 9288int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9289{
9290 int i, r;
25188b99 9291 unsigned long hva;
f0d648bd
PB		 9292 struct kvm_memslots *slots = kvm_memslots(kvm);
9293 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9294
9295 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9296 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9297 return -EINVAL;
9da0e4d5 9298
f0d648bd
PB		 9299 slot = id_to_memslot(slots, id);
9300 if (size) {
b21629da 9301 if (slot->npages)
f0d648bd
PB		 9302 return -EEXIST;
9303
9304 /*
9305 * MAP_SHARED to prevent internal slot pages from being moved
9306 * by fork()/COW.
9307 */
9308 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9309 MAP_SHARED | MAP_ANONYMOUS, 0);
9310 if (IS_ERR((void *)hva))
9311 return PTR_ERR((void *)hva);
9312 } else {
9313 if (!slot->npages)
9314 return 0;
9315
9316 hva = 0;
9317 }
9318
9319 old = *slot;
9da0e4d5 9320 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9321 struct kvm_userspace_memory_region m;
9da0e4d5 9322
1d8007bd
PB		 9323 m.slot = id | (i << 16);
9324 m.flags = 0;
9325 m.guest_phys_addr = gpa;
f0d648bd 9326 m.userspace_addr = hva;
1d8007bd 9327 m.memory_size = size;
9da0e4d5
PB		 9328 r = __kvm_set_memory_region(kvm, &m);
9329 if (r < 0)
9330 return r;
9331 }
9332
103c763c
EB		 9333 if (!size)
9334 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9335
9da0e4d5
PB		 9336 return 0;
9337}
9338EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9339
1d8007bd 9340int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9341{
9342 int r;
9343
9344 mutex_lock(&kvm->slots_lock);
1d8007bd 9345 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9346 mutex_unlock(&kvm->slots_lock);
9347
9348 return r;
9349}
9350EXPORT_SYMBOL_GPL(x86_set_memory_region);
9351
d19a9cd2
ZX		 9352void kvm_arch_destroy_vm(struct kvm *kvm)
9353{
27469d29
AH		 9354 if (current->mm == kvm->mm) {
9355 /*
9356 * Free memory regions allocated on behalf of userspace,
9357 * unless the the memory map has changed due to process exit
9358 * or fd copying.
9359 */
1d8007bd
PB		 9360 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9361 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9362 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9363 }
03543133
SS		 9364 if (kvm_x86_ops->vm_destroy)
9365 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9366 kvm_pic_destroy(kvm);
9367 kvm_ioapic_destroy(kvm);
d19a9cd2 9368 kvm_free_vcpus(kvm);
af1bae54 9369 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 9370 kvm_mmu_uninit_vm(kvm);
2beb6dad 9371 kvm_page_track_cleanup(kvm);
cbc0236a 9372 kvm_hv_destroy_vm(kvm);
d19a9cd2 9373}
0de10343 9374
5587027c 9375void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9376 struct kvm_memory_slot *dont)
9377{
9378 int i;
9379
d89cc617
TY		 9380 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9381 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9382 kvfree(free->arch.rmap[i]);
d89cc617 9383 free->arch.rmap[i] = NULL;
77d11309 9384 }
d89cc617
TY		 9385 if (i == 0)
9386 continue;
9387
9388 if (!dont || free->arch.lpage_info[i - 1] !=
9389 dont->arch.lpage_info[i - 1]) {
548ef284 9390 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9391 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9392 }
9393 }
21ebbeda
XG		 9394
9395 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9396}
9397
5587027c
AK		 9398int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9399 unsigned long npages)
db3fe4eb
TY		 9400{
9401 int i;
9402
d89cc617 9403 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9404 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9405 unsigned long ugfn;
9406 int lpages;
d89cc617 9407 int level = i + 1;
db3fe4eb
TY		 9408
9409 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9410 slot->base_gfn, level) + 1;
9411
d89cc617 9412 slot->arch.rmap[i] =
778e1cdd 9413 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9414 GFP_KERNEL_ACCOUNT);
d89cc617 9415 if (!slot->arch.rmap[i])
77d11309 9416 goto out_free;
d89cc617
TY		 9417 if (i == 0)
9418 continue;
77d11309 9419
254272ce 9420 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9421 if (!linfo)
db3fe4eb
TY		 9422 goto out_free;
9423
92f94f1e
XG		 9424 slot->arch.lpage_info[i - 1] = linfo;
9425
db3fe4eb 9426 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9427 linfo[0].disallow_lpage = 1;
db3fe4eb 9428 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9429 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9430 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9431 /*
9432 * If the gfn and userspace address are not aligned wrt each
9433 * other, or if explicitly asked to, disable large page
9434 * support for this slot
9435 */
9436 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9437 !kvm_largepages_enabled()) {
9438 unsigned long j;
9439
9440 for (j = 0; j < lpages; ++j)
92f94f1e 9441 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9442 }
9443 }
9444
21ebbeda
XG		 9445 if (kvm_page_track_create_memslot(slot, npages))
9446 goto out_free;
9447
db3fe4eb
TY		 9448 return 0;
9449
9450out_free:
d89cc617 9451 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9452 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9453 slot->arch.rmap[i] = NULL;
9454 if (i == 0)
9455 continue;
9456
548ef284 9457 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9458 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9459 }
9460 return -ENOMEM;
9461}
9462
15248258 9463void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9464{
e6dff7d1
TY		 9465 /*
9466 * memslots->generation has been incremented.
9467 * mmio generation may have reached its maximum value.
9468 */
15248258 9469 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9470}
9471
f7784b8e
MT		 9472int kvm_arch_prepare_memory_region(struct kvm *kvm,
9473 struct kvm_memory_slot *memslot,
09170a49 9474 const struct kvm_userspace_memory_region *mem,
7b6195a9 9475 enum kvm_mr_change change)
0de10343 9476{
f7784b8e
MT		 9477 return 0;
9478}
9479
88178fd4
KH		 9480static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9481 struct kvm_memory_slot *new)
9482{
9483 /* Still write protect RO slot */
9484 if (new->flags & KVM_MEM_READONLY) {
9485 kvm_mmu_slot_remove_write_access(kvm, new);
9486 return;
9487 }
9488
9489 /*
9490 * Call kvm_x86_ops dirty logging hooks when they are valid.
9491 *
9492 * kvm_x86_ops->slot_disable_log_dirty is called when:
9493 *
9494 * - KVM_MR_CREATE with dirty logging is disabled
9495 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9496 *
9497 * The reason is, in case of PML, we need to set D-bit for any slots
9498 * with dirty logging disabled in order to eliminate unnecessary GPA
9499 * logging in PML buffer (and potential PML buffer full VMEXT). This
9500 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9501 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9502 * logging disabled for memory slots.
9503 *
9504 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9505 * to dirty logging mode.
9506 *
9507 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9508 *
9509 * In case of write protect:
9510 *
9511 * Write protect all pages for dirty logging.
9512 *
9513 * All the sptes including the large sptes which point to this
9514 * slot are set to readonly. We can not create any new large
9515 * spte on this slot until the end of the logging.
9516 *
9517 * See the comments in fast_page_fault().
9518 */
9519 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9520 if (kvm_x86_ops->slot_enable_log_dirty)
9521 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9522 else
9523 kvm_mmu_slot_remove_write_access(kvm, new);
9524 } else {
9525 if (kvm_x86_ops->slot_disable_log_dirty)
9526 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9527 }
9528}
9529
f7784b8e 9530void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9531 const struct kvm_userspace_memory_region *mem,
8482644a 9532 const struct kvm_memory_slot *old,
f36f3f28 9533 const struct kvm_memory_slot *new,
8482644a 9534 enum kvm_mr_change change)
f7784b8e 9535{
48c0e4e9 9536 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9537 kvm_mmu_change_mmu_pages(kvm,
9538 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9539
3ea3b7fa
WL		 9540 /*
9541 * Dirty logging tracks sptes in 4k granularity, meaning that large
9542 * sptes have to be split. If live migration is successful, the guest
9543 * in the source machine will be destroyed and large sptes will be
9544 * created in the destination. However, if the guest continues to run
9545 * in the source machine (for example if live migration fails), small
9546 * sptes will remain around and cause bad performance.
9547 *
9548 * Scan sptes if dirty logging has been stopped, dropping those
9549 * which can be collapsed into a single large-page spte. Later
9550 * page faults will create the large-page sptes.
9551 */
9552 if ((change != KVM_MR_DELETE) &&
9553 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9554 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9555 kvm_mmu_zap_collapsible_sptes(kvm, new);
9556
c972f3b1 9557 /*
88178fd4 9558 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9559 *
88178fd4
KH		 9560 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9561 * been zapped so no dirty logging staff is needed for old slot. For
9562 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9563 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9564 *
9565 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9566 */
88178fd4 9567 if (change != KVM_MR_DELETE)
f36f3f28 9568 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9569}
1d737c8a 9570
2df72e9b 9571void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9572{
7390de1e 9573 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9574}
9575
2df72e9b
MT		 9576void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9577 struct kvm_memory_slot *slot)
9578{
ae7cd873 9579 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9580}
9581
e6c67d8c
LA		 9582static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9583{
9584 return (is_guest_mode(vcpu) &&
9585 kvm_x86_ops->guest_apic_has_interrupt &&
9586 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9587}
9588
5d9bc648
PB		 9589static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9590{
9591 if (!list_empty_careful(&vcpu->async_pf.done))
9592 return true;
9593
9594 if (kvm_apic_has_events(vcpu))
9595 return true;
9596
9597 if (vcpu->arch.pv.pv_unhalted)
9598 return true;
9599
a5f01f8e
WL		 9600 if (vcpu->arch.exception.pending)
9601 return true;
9602
47a66eed
Z		 9603 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9604 (vcpu->arch.nmi_pending &&
9605 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9606 return true;
9607
47a66eed
Z		 9608 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9609 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9610 return true;
9611
5d9bc648 9612 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9613 (kvm_cpu_has_interrupt(vcpu) ||
9614 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9615 return true;
9616
1f4b34f8
AS		 9617 if (kvm_hv_has_stimer_pending(vcpu))
9618 return true;
9619
5d9bc648
PB		 9620 return false;
9621}
9622
1d737c8a
ZX		 9623int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9624{
5d9bc648 9625 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9626}
5736199a 9627
199b5763
LM		 9628bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9629{
de63ad4c 9630 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9631}
9632
b6d33834 9633int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9634{
b6d33834 9635 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9636}
78646121
GN		 9637
9638int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9639{
9640 return kvm_x86_ops->interrupt_allowed(vcpu);
9641}
229456fc 9642
82b32774 9643unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9644{
82b32774
NA		 9645 if (is_64_bit_mode(vcpu))
9646 return kvm_rip_read(vcpu);
9647 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9648 kvm_rip_read(vcpu));
9649}
9650EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9651
82b32774
NA		 9652bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9653{
9654 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9655}
9656EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9657
94fe45da
JK		 9658unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9659{
9660 unsigned long rflags;
9661
9662 rflags = kvm_x86_ops->get_rflags(vcpu);
9663 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9664 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9665 return rflags;
9666}
9667EXPORT_SYMBOL_GPL(kvm_get_rflags);
9668
6addfc42 9669static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9670{
9671 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9672 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9673 rflags |= X86_EFLAGS_TF;
94fe45da 9674 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9675}
9676
9677void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9678{
9679 __kvm_set_rflags(vcpu, rflags);
3842d135 9680 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9681}
9682EXPORT_SYMBOL_GPL(kvm_set_rflags);
9683
56028d08
GN		 9684void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9685{
9686 int r;
9687
44dd3ffa 9688 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9689 work->wakeup_all)
56028d08
GN		 9690 return;
9691
9692 r = kvm_mmu_reload(vcpu);
9693 if (unlikely(r))
9694 return;
9695
44dd3ffa
VK		 9696 if (!vcpu->arch.mmu->direct_map &&
9697 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9698 return;
9699
44dd3ffa 9700 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9701}
9702
af585b92
GN		 9703static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9704{
9705 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9706}
9707
9708static inline u32 kvm_async_pf_next_probe(u32 key)
9709{
9710 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9711}
9712
9713static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9714{
9715 u32 key = kvm_async_pf_hash_fn(gfn);
9716
9717 while (vcpu->arch.apf.gfns[key] != ~0)
9718 key = kvm_async_pf_next_probe(key);
9719
9720 vcpu->arch.apf.gfns[key] = gfn;
9721}
9722
9723static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9724{
9725 int i;
9726 u32 key = kvm_async_pf_hash_fn(gfn);
9727
9728 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9729 (vcpu->arch.apf.gfns[key] != gfn &&
9730 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9731 key = kvm_async_pf_next_probe(key);
9732
9733 return key;
9734}
9735
9736bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9737{
9738 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9739}
9740
9741static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9742{
9743 u32 i, j, k;
9744
9745 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9746 while (true) {
9747 vcpu->arch.apf.gfns[i] = ~0;
9748 do {
9749 j = kvm_async_pf_next_probe(j);
9750 if (vcpu->arch.apf.gfns[j] == ~0)
9751 return;
9752 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9753 /*
9754 * k lies cyclically in ]i,j]
9755 * | i.k.j |
9756 * |....j i.k.| or |.k..j i...|
9757 */
9758 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9759 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9760 i = j;
9761 }
9762}
9763
7c90705b
GN		 9764static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9765{
4e335d9e
PB		 9766
9767 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9768 sizeof(val));
7c90705b
GN		 9769}
9770
9a6e7c39
WL		 9771static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9772{
9773
9774 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9775 sizeof(u32));
9776}
9777
af585b92
GN		 9778void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9779 struct kvm_async_pf *work)
9780{
6389ee94
AK		 9781 struct x86_exception fault;
9782
7c90705b 9783 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9784 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9785
9786 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9787 (vcpu->arch.apf.send_user_only &&
9788 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9789 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9790 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9791 fault.vector = PF_VECTOR;
9792 fault.error_code_valid = true;
9793 fault.error_code = 0;
9794 fault.nested_page_fault = false;
9795 fault.address = work->arch.token;
adfe20fb 9796 fault.async_page_fault = true;
6389ee94 9797 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9798 }
af585b92
GN		 9799}
9800
9801void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9802 struct kvm_async_pf *work)
9803{
6389ee94 9804 struct x86_exception fault;
9a6e7c39 9805 u32 val;
6389ee94 9806
f2e10669 9807 if (work->wakeup_all)
7c90705b
GN		 9808 work->arch.token = ~0; /* broadcast wakeup */
9809 else
9810 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9811 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9812
9a6e7c39
WL		 9813 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9814 !apf_get_user(vcpu, &val)) {
9815 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9816 vcpu->arch.exception.pending &&
9817 vcpu->arch.exception.nr == PF_VECTOR &&
9818 !apf_put_user(vcpu, 0)) {
9819 vcpu->arch.exception.injected = false;
9820 vcpu->arch.exception.pending = false;
9821 vcpu->arch.exception.nr = 0;
9822 vcpu->arch.exception.has_error_code = false;
9823 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9824 vcpu->arch.exception.has_payload = false;
9825 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9826 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9827 fault.vector = PF_VECTOR;
9828 fault.error_code_valid = true;
9829 fault.error_code = 0;
9830 fault.nested_page_fault = false;
9831 fault.address = work->arch.token;
9832 fault.async_page_fault = true;
9833 kvm_inject_page_fault(vcpu, &fault);
9834 }
7c90705b 9835 }
e6d53e3b 9836 vcpu->arch.apf.halted = false;
a4fa1635 9837 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9838}
9839
9840bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9841{
9842 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9843 return true;
9844 else
9bc1f09f 9845 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9846}
9847
5544eb9b
PB		 9848void kvm_arch_start_assignment(struct kvm *kvm)
9849{
9850 atomic_inc(&kvm->arch.assigned_device_count);
9851}
9852EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9853
9854void kvm_arch_end_assignment(struct kvm *kvm)
9855{
9856 atomic_dec(&kvm->arch.assigned_device_count);
9857}
9858EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9859
9860bool kvm_arch_has_assigned_device(struct kvm *kvm)
9861{
9862 return atomic_read(&kvm->arch.assigned_device_count);
9863}
9864EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9865
e0f0bbc5
AW		 9866void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9867{
9868 atomic_inc(&kvm->arch.noncoherent_dma_count);
9869}
9870EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9871
9872void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9873{
9874 atomic_dec(&kvm->arch.noncoherent_dma_count);
9875}
9876EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9877
9878bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9879{
9880 return atomic_read(&kvm->arch.noncoherent_dma_count);
9881}
9882EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9883
14717e20
AW		 9884bool kvm_arch_has_irq_bypass(void)
9885{
9886 return kvm_x86_ops->update_pi_irte != NULL;
9887}
9888
87276880
FW		 9889int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9890 struct irq_bypass_producer *prod)
9891{
9892 struct kvm_kernel_irqfd *irqfd =
9893 container_of(cons, struct kvm_kernel_irqfd, consumer);
9894
14717e20 9895 irqfd->producer = prod;
87276880 9896
14717e20
AW		 9897 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9898 prod->irq, irqfd->gsi, 1);
87276880
FW		 9899}
9900
9901void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9902 struct irq_bypass_producer *prod)
9903{
9904 int ret;
9905 struct kvm_kernel_irqfd *irqfd =
9906 container_of(cons, struct kvm_kernel_irqfd, consumer);
9907
87276880
FW		 9908 WARN_ON(irqfd->producer != prod);
9909 irqfd->producer = NULL;
9910
9911 /*
9912 * When producer of consumer is unregistered, we change back to
9913 * remapped mode, so we can re-use the current implementation
bb3541f1 9914 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9915 * int this case doesn't want to receive the interrupts.
9916 */
9917 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9918 if (ret)
9919 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9920 " fails: %d\n", irqfd->consumer.token, ret);
9921}
9922
9923int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9924 uint32_t guest_irq, bool set)
9925{
9926 if (!kvm_x86_ops->update_pi_irte)
9927 return -EINVAL;
9928
9929 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9930}
9931
52004014
FW		 9932bool kvm_vector_hashing_enabled(void)
9933{
9934 return vector_hashing;
9935}
9936EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9937
229456fc 9938EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9939EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9940EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9941EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9942EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9943EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9944EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9945EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9946EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9947EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9948EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9949EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9950EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9951EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9952EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9953EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9954EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9955EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9956EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)