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KVM: Handle MSR_IA32_PERF_CTL
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
52004014
FW		 126static bool __read_mostly vector_hashing = true;
127module_param(vector_hashing, bool, S_IRUGO);
128
893590c7 129static bool __read_mostly backwards_tsc_observed = false;
16a96021 130
18863bdd
AK		 131#define KVM_NR_SHARED_MSRS 16
132
133struct kvm_shared_msrs_global {
134 int nr;
2bf78fa7 135 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 136};
137
138struct kvm_shared_msrs {
139 struct user_return_notifier urn;
140 bool registered;
2bf78fa7
SY		 141 struct kvm_shared_msr_values {
142 u64 host;
143 u64 curr;
144 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 145};
146
147static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 148static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 149
417bc304 150struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 161 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 164 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 165 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 166 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 167 { "request_irq", VCPU_STAT(request_irq_exits) },
168 { "irq_exits", VCPU_STAT(irq_exits) },
169 { "host_state_reload", VCPU_STAT(host_state_reload) },
170 { "efer_reload", VCPU_STAT(efer_reload) },
171 { "fpu_reload", VCPU_STAT(fpu_reload) },
172 { "insn_emulation", VCPU_STAT(insn_emulation) },
173 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 174 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 175 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 176 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
177 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
178 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
179 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
180 { "mmu_flooded", VM_STAT(mmu_flooded) },
181 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 182 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 183 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 184 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 185 { "largepages", VM_STAT(lpages) },
417bc304
HB		 186 { NULL }
187};
188
2acf923e
DC		 189u64 __read_mostly host_xcr0;
190
b6785def 191static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 192
af585b92
GN		 193static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
194{
195 int i;
196 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
197 vcpu->arch.apf.gfns[i] = ~0;
198}
199
18863bdd
AK		 200static void kvm_on_user_return(struct user_return_notifier *urn)
201{
202 unsigned slot;
18863bdd
AK		 203 struct kvm_shared_msrs *locals
204 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 205 struct kvm_shared_msr_values *values;
18863bdd
AK		 206
207 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 208 values = &locals->values[slot];
209 if (values->host != values->curr) {
210 wrmsrl(shared_msrs_global.msrs[slot], values->host);
211 values->curr = values->host;
18863bdd
AK		 212 }
213 }
214 locals->registered = false;
215 user_return_notifier_unregister(urn);
216}
217
2bf78fa7 218static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 219{
18863bdd 220 u64 value;
013f6a5d
MT		 221 unsigned int cpu = smp_processor_id();
222 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 223
2bf78fa7
SY		 224 /* only read, and nobody should modify it at this time,
225 * so don't need lock */
226 if (slot >= shared_msrs_global.nr) {
227 printk(KERN_ERR "kvm: invalid MSR slot!");
228 return;
229 }
230 rdmsrl_safe(msr, &value);
231 smsr->values[slot].host = value;
232 smsr->values[slot].curr = value;
233}
234
235void kvm_define_shared_msr(unsigned slot, u32 msr)
236{
0123be42 237 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 238 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 239 if (slot >= shared_msrs_global.nr)
240 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 241}
242EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
243
244static void kvm_shared_msr_cpu_online(void)
245{
246 unsigned i;
18863bdd
AK		 247
248 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 249 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 250}
251
8b3c3104 252int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 253{
013f6a5d
MT		 254 unsigned int cpu = smp_processor_id();
255 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 256 int err;
18863bdd 257
2bf78fa7 258 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 259 return 0;
2bf78fa7 260 smsr->values[slot].curr = value;
8b3c3104
AH		 261 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
262 if (err)
263 return 1;
264
18863bdd
AK		 265 if (!smsr->registered) {
266 smsr->urn.on_user_return = kvm_on_user_return;
267 user_return_notifier_register(&smsr->urn);
268 smsr->registered = true;
269 }
8b3c3104 270 return 0;
18863bdd
AK		 271}
272EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
273
13a34e06 274static void drop_user_return_notifiers(void)
3548bab5 275{
013f6a5d
MT		 276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 278
279 if (smsr->registered)
280 kvm_on_user_return(&smsr->urn);
281}
282
6866b83e
CO		 283u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
284{
8a5a87d9 285 return vcpu->arch.apic_base;
6866b83e
CO		 286}
287EXPORT_SYMBOL_GPL(kvm_get_apic_base);
288
58cb628d
JK		 289int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
290{
291 u64 old_state = vcpu->arch.apic_base &
292 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
293 u64 new_state = msr_info->data &
294 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
295 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
296 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
297
298 if (!msr_info->host_initiated &&
299 ((msr_info->data & reserved_bits) != 0 ||
300 new_state == X2APIC_ENABLE ||
301 (new_state == MSR_IA32_APICBASE_ENABLE &&
302 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
303 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
304 old_state == 0)))
305 return 1;
306
307 kvm_lapic_set_base(vcpu, msr_info->data);
308 return 0;
6866b83e
CO		 309}
310EXPORT_SYMBOL_GPL(kvm_set_apic_base);
311
2605fc21 312asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 313{
314 /* Fault while not rebooting. We want the trace. */
315 BUG();
316}
317EXPORT_SYMBOL_GPL(kvm_spurious_fault);
318
3fd28fce
ED		 319#define EXCPT_BENIGN 0
320#define EXCPT_CONTRIBUTORY 1
321#define EXCPT_PF 2
322
323static int exception_class(int vector)
324{
325 switch (vector) {
326 case PF_VECTOR:
327 return EXCPT_PF;
328 case DE_VECTOR:
329 case TS_VECTOR:
330 case NP_VECTOR:
331 case SS_VECTOR:
332 case GP_VECTOR:
333 return EXCPT_CONTRIBUTORY;
334 default:
335 break;
336 }
337 return EXCPT_BENIGN;
338}
339
d6e8c854
NA		 340#define EXCPT_FAULT 0
341#define EXCPT_TRAP 1
342#define EXCPT_ABORT 2
343#define EXCPT_INTERRUPT 3
344
345static int exception_type(int vector)
346{
347 unsigned int mask;
348
349 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
350 return EXCPT_INTERRUPT;
351
352 mask = 1 << vector;
353
354 /* #DB is trap, as instruction watchpoints are handled elsewhere */
355 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
356 return EXCPT_TRAP;
357
358 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
359 return EXCPT_ABORT;
360
361 /* Reserved exceptions will result in fault */
362 return EXCPT_FAULT;
363}
364
3fd28fce 365static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 366 unsigned nr, bool has_error, u32 error_code,
367 bool reinject)
3fd28fce
ED		 368{
369 u32 prev_nr;
370 int class1, class2;
371
3842d135
AK		 372 kvm_make_request(KVM_REQ_EVENT, vcpu);
373
3fd28fce
ED		 374 if (!vcpu->arch.exception.pending) {
375 queue:
3ffb2468
NA		 376 if (has_error && !is_protmode(vcpu))
377 has_error = false;
3fd28fce
ED		 378 vcpu->arch.exception.pending = true;
379 vcpu->arch.exception.has_error_code = has_error;
380 vcpu->arch.exception.nr = nr;
381 vcpu->arch.exception.error_code = error_code;
3f0fd292 382 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 383 return;
384 }
385
386 /* to check exception */
387 prev_nr = vcpu->arch.exception.nr;
388 if (prev_nr == DF_VECTOR) {
389 /* triple fault -> shutdown */
a8eeb04a 390 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 391 return;
392 }
393 class1 = exception_class(prev_nr);
394 class2 = exception_class(nr);
395 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
396 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
397 /* generate double fault per SDM Table 5-5 */
398 vcpu->arch.exception.pending = true;
399 vcpu->arch.exception.has_error_code = true;
400 vcpu->arch.exception.nr = DF_VECTOR;
401 vcpu->arch.exception.error_code = 0;
402 } else
403 /* replace previous exception with a new one in a hope
404 that instruction re-execution will regenerate lost
405 exception */
406 goto queue;
407}
408
298101da
AK		 409void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
410{
ce7ddec4 411 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 412}
413EXPORT_SYMBOL_GPL(kvm_queue_exception);
414
ce7ddec4
JR		 415void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
416{
417 kvm_multiple_exception(vcpu, nr, false, 0, true);
418}
419EXPORT_SYMBOL_GPL(kvm_requeue_exception);
420
db8fcefa 421void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 422{
db8fcefa
AP		 423 if (err)
424 kvm_inject_gp(vcpu, 0);
425 else
426 kvm_x86_ops->skip_emulated_instruction(vcpu);
427}
428EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 429
6389ee94 430void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 431{
432 ++vcpu->stat.pf_guest;
6389ee94
AK		 433 vcpu->arch.cr2 = fault->address;
434 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 435}
27d6c865 436EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 437
ef54bcfe 438static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 439{
6389ee94
AK		 440 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
441 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 442 else
6389ee94 443 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 444
445 return fault->nested_page_fault;
d4f8cf66
JR		 446}
447
3419ffc8
SY		 448void kvm_inject_nmi(struct kvm_vcpu *vcpu)
449{
7460fb4a
AK		 450 atomic_inc(&vcpu->arch.nmi_queued);
451 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 452}
453EXPORT_SYMBOL_GPL(kvm_inject_nmi);
454
298101da
AK		 455void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
456{
ce7ddec4 457 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 458}
459EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
460
ce7ddec4
JR		 461void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
462{
463 kvm_multiple_exception(vcpu, nr, true, error_code, true);
464}
465EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
466
0a79b009
AK		 467/*
468 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
469 * a #GP and return false.
470 */
471bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 472{
0a79b009
AK		 473 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
474 return true;
475 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
476 return false;
298101da 477}
0a79b009 478EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 479
16f8a6f9
NA		 480bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
481{
482 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
483 return true;
484
485 kvm_queue_exception(vcpu, UD_VECTOR);
486 return false;
487}
488EXPORT_SYMBOL_GPL(kvm_require_dr);
489
ec92fe44
JR		 490/*
491 * This function will be used to read from the physical memory of the currently
54bf36aa 492 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 493 * can read from guest physical or from the guest's guest physical memory.
494 */
495int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
496 gfn_t ngfn, void *data, int offset, int len,
497 u32 access)
498{
54987b7a 499 struct x86_exception exception;
ec92fe44
JR		 500 gfn_t real_gfn;
501 gpa_t ngpa;
502
503 ngpa = gfn_to_gpa(ngfn);
54987b7a 504 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 505 if (real_gfn == UNMAPPED_GVA)
506 return -EFAULT;
507
508 real_gfn = gpa_to_gfn(real_gfn);
509
54bf36aa 510 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 511}
512EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
513
69b0049a 514static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 515 void *data, int offset, int len, u32 access)
516{
517 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
518 data, offset, len, access);
519}
520
a03490ed
CO		 521/*
522 * Load the pae pdptrs. Return true is they are all valid.
523 */
ff03a073 524int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 525{
526 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
527 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
528 int i;
529 int ret;
ff03a073 530 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 531
ff03a073
JR		 532 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
533 offset * sizeof(u64), sizeof(pdpte),
534 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 535 if (ret < 0) {
536 ret = 0;
537 goto out;
538 }
539 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 540 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 541 (pdpte[i] &
542 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 543 ret = 0;
544 goto out;
545 }
546 }
547 ret = 1;
548
ff03a073 549 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 550 __set_bit(VCPU_EXREG_PDPTR,
551 (unsigned long *)&vcpu->arch.regs_avail);
552 __set_bit(VCPU_EXREG_PDPTR,
553 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 554out:
a03490ed
CO		 555
556 return ret;
557}
cc4b6871 558EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 559
d835dfec
AK		 560static bool pdptrs_changed(struct kvm_vcpu *vcpu)
561{
ff03a073 562 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 563 bool changed = true;
3d06b8bf
JR		 564 int offset;
565 gfn_t gfn;
d835dfec
AK		 566 int r;
567
568 if (is_long_mode(vcpu) || !is_pae(vcpu))
569 return false;
570
6de4f3ad
AK		 571 if (!test_bit(VCPU_EXREG_PDPTR,
572 (unsigned long *)&vcpu->arch.regs_avail))
573 return true;
574
9f8fe504
AK		 575 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
576 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 577 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
578 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 579 if (r < 0)
580 goto out;
ff03a073 581 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 582out:
d835dfec
AK		 583
584 return changed;
585}
586
49a9b07e 587int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 588{
aad82703 589 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 590 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 591
f9a48e6a
AK		 592 cr0 |= X86_CR0_ET;
593
ab344828 594#ifdef CONFIG_X86_64
0f12244f
GN		 595 if (cr0 & 0xffffffff00000000UL)
596 return 1;
ab344828
GN		 597#endif
598
599 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 600
0f12244f
GN		 601 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
602 return 1;
a03490ed 603
0f12244f
GN		 604 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
605 return 1;
a03490ed
CO		 606
607 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
608#ifdef CONFIG_X86_64
f6801dff 609 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 610 int cs_db, cs_l;
611
0f12244f
GN		 612 if (!is_pae(vcpu))
613 return 1;
a03490ed 614 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 615 if (cs_l)
616 return 1;
a03490ed
CO		 617 } else
618#endif
ff03a073 619 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 620 kvm_read_cr3(vcpu)))
0f12244f 621 return 1;
a03490ed
CO		 622 }
623
ad756a16
MJ		 624 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
625 return 1;
626
a03490ed 627 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 628
d170c419 629 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 630 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 631 kvm_async_pf_hash_reset(vcpu);
632 }
e5f3f027 633
aad82703
SY		 634 if ((cr0 ^ old_cr0) & update_bits)
635 kvm_mmu_reset_context(vcpu);
b18d5431 636
879ae188
LE		 637 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
638 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
639 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 640 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
641
0f12244f
GN		 642 return 0;
643}
2d3ad1f4 644EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 645
2d3ad1f4 646void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 647{
49a9b07e 648 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 649}
2d3ad1f4 650EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 651
42bdf991
MT		 652static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
653{
654 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
655 !vcpu->guest_xcr0_loaded) {
656 /* kvm_set_xcr() also depends on this */
657 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
658 vcpu->guest_xcr0_loaded = 1;
659 }
660}
661
662static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
663{
664 if (vcpu->guest_xcr0_loaded) {
665 if (vcpu->arch.xcr0 != host_xcr0)
666 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
667 vcpu->guest_xcr0_loaded = 0;
668 }
669}
670
69b0049a 671static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 672{
56c103ec
LJ		 673 u64 xcr0 = xcr;
674 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 675 u64 valid_bits;
2acf923e
DC		 676
677 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
678 if (index != XCR_XFEATURE_ENABLED_MASK)
679 return 1;
d91cab78 680 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 681 return 1;
d91cab78 682 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 683 return 1;
46c34cb0
PB		 684
685 /*
686 * Do not allow the guest to set bits that we do not support
687 * saving. However, xcr0 bit 0 is always set, even if the
688 * emulated CPU does not support XSAVE (see fx_init).
689 */
d91cab78 690 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 691 if (xcr0 & ~valid_bits)
2acf923e 692 return 1;
46c34cb0 693
d91cab78
DH		 694 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
695 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 696 return 1;
697
d91cab78
DH		 698 if (xcr0 & XFEATURE_MASK_AVX512) {
699 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 700 return 1;
d91cab78 701 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 702 return 1;
703 }
2acf923e 704 vcpu->arch.xcr0 = xcr0;
56c103ec 705
d91cab78 706 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 707 kvm_update_cpuid(vcpu);
2acf923e
DC		 708 return 0;
709}
710
711int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
712{
764bcbc5
Z		 713 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
714 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 715 kvm_inject_gp(vcpu, 0);
716 return 1;
717 }
718 return 0;
719}
720EXPORT_SYMBOL_GPL(kvm_set_xcr);
721
a83b29c6 722int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 723{
fc78f519 724 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 725 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 726 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 727
0f12244f
GN		 728 if (cr4 & CR4_RESERVED_BITS)
729 return 1;
a03490ed 730
2acf923e
DC		 731 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
732 return 1;
733
c68b734f
YW		 734 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
735 return 1;
736
97ec8c06
FW		 737 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
738 return 1;
739
afcbf13f 740 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 741 return 1;
742
b9baba86
HH		 743 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
744 return 1;
745
a03490ed 746 if (is_long_mode(vcpu)) {
0f12244f
GN		 747 if (!(cr4 & X86_CR4_PAE))
748 return 1;
a2edf57f
AK		 749 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
750 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 751 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
752 kvm_read_cr3(vcpu)))
0f12244f
GN		 753 return 1;
754
ad756a16
MJ		 755 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
756 if (!guest_cpuid_has_pcid(vcpu))
757 return 1;
758
759 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
760 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
761 return 1;
762 }
763
5e1746d6 764 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 765 return 1;
a03490ed 766
ad756a16
MJ		 767 if (((cr4 ^ old_cr4) & pdptr_bits) ||
768 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 769 kvm_mmu_reset_context(vcpu);
0f12244f 770
b9baba86 771 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 772 kvm_update_cpuid(vcpu);
2acf923e 773
0f12244f
GN		 774 return 0;
775}
2d3ad1f4 776EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 777
2390218b 778int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 779{
ac146235 780#ifdef CONFIG_X86_64
9d88fca7 781 cr3 &= ~CR3_PCID_INVD;
ac146235 782#endif
9d88fca7 783
9f8fe504 784 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 785 kvm_mmu_sync_roots(vcpu);
77c3913b 786 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 787 return 0;
d835dfec
AK		 788 }
789
a03490ed 790 if (is_long_mode(vcpu)) {
d9f89b88
JK		 791 if (cr3 & CR3_L_MODE_RESERVED_BITS)
792 return 1;
793 } else if (is_pae(vcpu) && is_paging(vcpu) &&
794 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 795 return 1;
a03490ed 796
0f12244f 797 vcpu->arch.cr3 = cr3;
aff48baa 798 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 799 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 800 return 0;
801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 803
eea1cff9 804int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 805{
0f12244f
GN		 806 if (cr8 & CR8_RESERVED_BITS)
807 return 1;
35754c98 808 if (lapic_in_kernel(vcpu))
a03490ed
CO		 809 kvm_lapic_set_tpr(vcpu, cr8);
810 else
ad312c7c 811 vcpu->arch.cr8 = cr8;
0f12244f
GN		 812 return 0;
813}
2d3ad1f4 814EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 815
2d3ad1f4 816unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 817{
35754c98 818 if (lapic_in_kernel(vcpu))
a03490ed
CO		 819 return kvm_lapic_get_cr8(vcpu);
820 else
ad312c7c 821 return vcpu->arch.cr8;
a03490ed 822}
2d3ad1f4 823EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 824
ae561ede
NA		 825static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
826{
827 int i;
828
829 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
830 for (i = 0; i < KVM_NR_DB_REGS; i++)
831 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
833 }
834}
835
73aaf249
JK		 836static void kvm_update_dr6(struct kvm_vcpu *vcpu)
837{
838 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
839 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
840}
841
c8639010
JK		 842static void kvm_update_dr7(struct kvm_vcpu *vcpu)
843{
844 unsigned long dr7;
845
846 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
847 dr7 = vcpu->arch.guest_debug_dr7;
848 else
849 dr7 = vcpu->arch.dr7;
850 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 851 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
852 if (dr7 & DR7_BP_EN_MASK)
853 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 854}
855
6f43ed01
NA		 856static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
857{
858 u64 fixed = DR6_FIXED_1;
859
860 if (!guest_cpuid_has_rtm(vcpu))
861 fixed |= DR6_RTM;
862 return fixed;
863}
864
338dbc97 865static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 866{
867 switch (dr) {
868 case 0 ... 3:
869 vcpu->arch.db[dr] = val;
870 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
871 vcpu->arch.eff_db[dr] = val;
872 break;
873 case 4:
020df079
GN		 874 /* fall through */
875 case 6:
338dbc97
GN		 876 if (val & 0xffffffff00000000ULL)
877 return -1; /* #GP */
6f43ed01 878 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 879 kvm_update_dr6(vcpu);
020df079
GN		 880 break;
881 case 5:
020df079
GN		 882 /* fall through */
883 default: /* 7 */
338dbc97
GN		 884 if (val & 0xffffffff00000000ULL)
885 return -1; /* #GP */
020df079 886 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 887 kvm_update_dr7(vcpu);
020df079
GN		 888 break;
889 }
890
891 return 0;
892}
338dbc97
GN		 893
894int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
895{
16f8a6f9 896 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 897 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 898 return 1;
899 }
900 return 0;
338dbc97 901}
020df079
GN		 902EXPORT_SYMBOL_GPL(kvm_set_dr);
903
16f8a6f9 904int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 905{
906 switch (dr) {
907 case 0 ... 3:
908 *val = vcpu->arch.db[dr];
909 break;
910 case 4:
020df079
GN		 911 /* fall through */
912 case 6:
73aaf249
JK		 913 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
914 *val = vcpu->arch.dr6;
915 else
916 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 917 break;
918 case 5:
020df079
GN		 919 /* fall through */
920 default: /* 7 */
921 *val = vcpu->arch.dr7;
922 break;
923 }
338dbc97
GN		 924 return 0;
925}
020df079
GN		 926EXPORT_SYMBOL_GPL(kvm_get_dr);
927
022cd0e8
AK		 928bool kvm_rdpmc(struct kvm_vcpu *vcpu)
929{
930 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
931 u64 data;
932 int err;
933
c6702c9d 934 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 935 if (err)
936 return err;
937 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
938 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
939 return err;
940}
941EXPORT_SYMBOL_GPL(kvm_rdpmc);
942
043405e1
CO		 943/*
944 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
945 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
946 *
947 * This list is modified at module load time to reflect the
e3267cbb 948 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 949 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
950 * may depend on host virtualization features rather than host cpu features.
043405e1 951 */
e3267cbb 952
043405e1
CO		 953static u32 msrs_to_save[] = {
954 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 955 MSR_STAR,
043405e1
CO		 956#ifdef CONFIG_X86_64
957 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
958#endif
b3897a49 959 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 960 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 961};
962
963static unsigned num_msrs_to_save;
964
62ef68bb
PB		 965static u32 emulated_msrs[] = {
966 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
967 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
968 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
969 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 970 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
971 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 972 HV_X64_MSR_RESET,
11c4b1ca 973 HV_X64_MSR_VP_INDEX,
9eec50b8 974 HV_X64_MSR_VP_RUNTIME,
5c919412 975 HV_X64_MSR_SCONTROL,
1f4b34f8 976 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 977 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
978 MSR_KVM_PV_EOI_EN,
979
ba904635 980 MSR_IA32_TSC_ADJUST,
a3e06bbe 981 MSR_IA32_TSCDEADLINE,
043405e1 982 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 983 MSR_IA32_MCG_STATUS,
984 MSR_IA32_MCG_CTL,
64d60670 985 MSR_IA32_SMBASE,
043405e1
CO		 986};
987
62ef68bb
PB		 988static unsigned num_emulated_msrs;
989
384bb783 990bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 991{
b69e8cae 992 if (efer & efer_reserved_bits)
384bb783 993 return false;
15c4a640 994
1b2fd70c
AG		 995 if (efer & EFER_FFXSR) {
996 struct kvm_cpuid_entry2 *feat;
997
998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 999 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1000 return false;
1b2fd70c
AG		 1001 }
1002
d8017474
AG		 1003 if (efer & EFER_SVME) {
1004 struct kvm_cpuid_entry2 *feat;
1005
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1007 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1008 return false;
d8017474
AG		 1009 }
1010
384bb783
JK		 1011 return true;
1012}
1013EXPORT_SYMBOL_GPL(kvm_valid_efer);
1014
1015static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1016{
1017 u64 old_efer = vcpu->arch.efer;
1018
1019 if (!kvm_valid_efer(vcpu, efer))
1020 return 1;
1021
1022 if (is_paging(vcpu)
1023 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1024 return 1;
1025
15c4a640 1026 efer &= ~EFER_LMA;
f6801dff 1027 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1028
a3d204e2
SY		 1029 kvm_x86_ops->set_efer(vcpu, efer);
1030
aad82703
SY		 1031 /* Update reserved bits */
1032 if ((efer ^ old_efer) & EFER_NX)
1033 kvm_mmu_reset_context(vcpu);
1034
b69e8cae 1035 return 0;
15c4a640
CO		 1036}
1037
f2b4b7dd
JR		 1038void kvm_enable_efer_bits(u64 mask)
1039{
1040 efer_reserved_bits &= ~mask;
1041}
1042EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1043
15c4a640
CO		 1044/*
1045 * Writes msr value into into the appropriate "register".
1046 * Returns 0 on success, non-0 otherwise.
1047 * Assumes vcpu_load() was already called.
1048 */
8fe8ab46 1049int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1050{
854e8bb1
NA		 1051 switch (msr->index) {
1052 case MSR_FS_BASE:
1053 case MSR_GS_BASE:
1054 case MSR_KERNEL_GS_BASE:
1055 case MSR_CSTAR:
1056 case MSR_LSTAR:
1057 if (is_noncanonical_address(msr->data))
1058 return 1;
1059 break;
1060 case MSR_IA32_SYSENTER_EIP:
1061 case MSR_IA32_SYSENTER_ESP:
1062 /*
1063 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1064 * non-canonical address is written on Intel but not on
1065 * AMD (which ignores the top 32-bits, because it does
1066 * not implement 64-bit SYSENTER).
1067 *
1068 * 64-bit code should hence be able to write a non-canonical
1069 * value on AMD. Making the address canonical ensures that
1070 * vmentry does not fail on Intel after writing a non-canonical
1071 * value, and that something deterministic happens if the guest
1072 * invokes 64-bit SYSENTER.
1073 */
1074 msr->data = get_canonical(msr->data);
1075 }
8fe8ab46 1076 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1077}
854e8bb1 1078EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1079
313a3dc7
CO		 1080/*
1081 * Adapt set_msr() to msr_io()'s calling convention
1082 */
609e36d3
PB		 1083static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1084{
1085 struct msr_data msr;
1086 int r;
1087
1088 msr.index = index;
1089 msr.host_initiated = true;
1090 r = kvm_get_msr(vcpu, &msr);
1091 if (r)
1092 return r;
1093
1094 *data = msr.data;
1095 return 0;
1096}
1097
313a3dc7
CO		 1098static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1099{
8fe8ab46
WA		 1100 struct msr_data msr;
1101
1102 msr.data = *data;
1103 msr.index = index;
1104 msr.host_initiated = true;
1105 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1106}
1107
16e8d74d
MT		 1108#ifdef CONFIG_X86_64
1109struct pvclock_gtod_data {
1110 seqcount_t seq;
1111
1112 struct { /* extract of a clocksource struct */
1113 int vclock_mode;
1114 cycle_t cycle_last;
1115 cycle_t mask;
1116 u32 mult;
1117 u32 shift;
1118 } clock;
1119
cbcf2dd3
TG		 1120 u64 boot_ns;
1121 u64 nsec_base;
16e8d74d
MT		 1122};
1123
1124static struct pvclock_gtod_data pvclock_gtod_data;
1125
1126static void update_pvclock_gtod(struct timekeeper *tk)
1127{
1128 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1129 u64 boot_ns;
1130
876e7881 1131 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1132
1133 write_seqcount_begin(&vdata->seq);
1134
1135 /* copy pvclock gtod data */
876e7881
PZ		 1136 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1137 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1138 vdata->clock.mask = tk->tkr_mono.mask;
1139 vdata->clock.mult = tk->tkr_mono.mult;
1140 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1141
cbcf2dd3 1142 vdata->boot_ns = boot_ns;
876e7881 1143 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1144
1145 write_seqcount_end(&vdata->seq);
1146}
1147#endif
1148
bab5bb39
NK		 1149void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1150{
1151 /*
1152 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1153 * vcpu_enter_guest. This function is only called from
1154 * the physical CPU that is running vcpu.
1155 */
1156 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1157}
16e8d74d 1158
18068523
GOC		 1159static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1160{
9ed3c444
AK		 1161 int version;
1162 int r;
50d0a0f9 1163 struct pvclock_wall_clock wc;
923de3cf 1164 struct timespec boot;
18068523
GOC		 1165
1166 if (!wall_clock)
1167 return;
1168
9ed3c444
AK		 1169 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1170 if (r)
1171 return;
1172
1173 if (version & 1)
1174 ++version; /* first time write, random junk */
1175
1176 ++version;
18068523 1177
1dab1345
NK		 1178 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1179 return;
18068523 1180
50d0a0f9
GH		 1181 /*
1182 * The guest calculates current wall clock time by adding
34c238a1 1183 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1184 * wall clock specified here. guest system time equals host
1185 * system time for us, thus we must fill in host boot time here.
1186 */
923de3cf 1187 getboottime(&boot);
50d0a0f9 1188
4b648665
BR		 1189 if (kvm->arch.kvmclock_offset) {
1190 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1191 boot = timespec_sub(boot, ts);
1192 }
50d0a0f9
GH		 1193 wc.sec = boot.tv_sec;
1194 wc.nsec = boot.tv_nsec;
1195 wc.version = version;
18068523
GOC		 1196
1197 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1198
1199 version++;
1200 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1201}
1202
50d0a0f9
GH		 1203static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1204{
b51012de
PB		 1205 do_shl32_div32(dividend, divisor);
1206 return dividend;
50d0a0f9
GH		 1207}
1208
3ae13faa 1209static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1210 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1211{
5f4e3f88 1212 uint64_t scaled64;
50d0a0f9
GH		 1213 int32_t shift = 0;
1214 uint64_t tps64;
1215 uint32_t tps32;
1216
3ae13faa
PB		 1217 tps64 = base_hz;
1218 scaled64 = scaled_hz;
50933623 1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1220 tps64 >>= 1;
1221 shift--;
1222 }
1223
1224 tps32 = (uint32_t)tps64;
50933623
JK		 1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1227 scaled64 >>= 1;
1228 else
1229 tps32 <<= 1;
50d0a0f9
GH		 1230 shift++;
1231 }
1232
5f4e3f88
ZA		 1233 *pshift = shift;
1234 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1235
3ae13faa
PB		 1236 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1237 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1238}
1239
d828199e 1240#ifdef CONFIG_X86_64
16e8d74d 1241static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1242#endif
16e8d74d 1243
c8076604 1244static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1245static unsigned long max_tsc_khz;
c8076604 1246
cc578287 1247static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1248{
cc578287
ZA		 1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1250 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1251}
1252
cc578287 1253static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1254{
cc578287
ZA		 1255 u64 v = (u64)khz * (1000000 + ppm);
1256 do_div(v, 1000000);
1257 return v;
1e993611
JR		 1258}
1259
381d585c
HZ		 1260static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1261{
1262 u64 ratio;
1263
1264 /* Guest TSC same frequency as host TSC? */
1265 if (!scale) {
1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1267 return 0;
1268 }
1269
1270 /* TSC scaling supported? */
1271 if (!kvm_has_tsc_control) {
1272 if (user_tsc_khz > tsc_khz) {
1273 vcpu->arch.tsc_catchup = 1;
1274 vcpu->arch.tsc_always_catchup = 1;
1275 return 0;
1276 } else {
1277 WARN(1, "user requested TSC rate below hardware speed\n");
1278 return -1;
1279 }
1280 }
1281
1282 /* TSC scaling required - calculate ratio */
1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1284 user_tsc_khz, tsc_khz);
1285
1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1288 user_tsc_khz);
1289 return -1;
1290 }
1291
1292 vcpu->arch.tsc_scaling_ratio = ratio;
1293 return 0;
1294}
1295
4941b8cb 1296static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1297{
cc578287
ZA		 1298 u32 thresh_lo, thresh_hi;
1299 int use_scaling = 0;
217fc9cf 1300
03ba32ca 1301 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1302 if (user_tsc_khz == 0) {
ad721883
HZ		 1303 /* set tsc_scaling_ratio to a safe value */
1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1305 return -1;
ad721883 1306 }
03ba32ca 1307
c285545f 1308 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1309 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1310 &vcpu->arch.virtual_tsc_shift,
1311 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1312 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1313
1314 /*
1315 * Compute the variation in TSC rate which is acceptable
1316 * within the range of tolerance and decide if the
1317 * rate being applied is within that bounds of the hardware
1318 * rate. If so, no scaling or compensation need be done.
1319 */
1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1322 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1324 use_scaling = 1;
1325 }
4941b8cb 1326 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1327}
1328
1329static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1330{
e26101b1 1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1332 vcpu->arch.virtual_tsc_mult,
1333 vcpu->arch.virtual_tsc_shift);
e26101b1 1334 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1335 return tsc;
1336}
1337
69b0049a 1338static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1339{
1340#ifdef CONFIG_X86_64
1341 bool vcpus_matched;
b48aa97e
MT		 1342 struct kvm_arch *ka = &vcpu->kvm->arch;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1346 atomic_read(&vcpu->kvm->online_vcpus));
1347
7f187922
MT		 1348 /*
1349 * Once the masterclock is enabled, always perform request in
1350 * order to update it.
1351 *
1352 * In order to enable masterclock, the host clocksource must be TSC
1353 * and the vcpus need to have matched TSCs. When that happens,
1354 * perform request to enable masterclock.
1355 */
1356 if (ka->use_master_clock ||
1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1359
1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1361 atomic_read(&vcpu->kvm->online_vcpus),
1362 ka->use_master_clock, gtod->clock.vclock_mode);
1363#endif
1364}
1365
ba904635
WA		 1366static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1367{
1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1370}
1371
35181e86
HZ		 1372/*
1373 * Multiply tsc by a fixed point number represented by ratio.
1374 *
1375 * The most significant 64-N bits (mult) of ratio represent the
1376 * integral part of the fixed point number; the remaining N bits
1377 * (frac) represent the fractional part, ie. ratio represents a fixed
1378 * point number (mult + frac * 2^(-N)).
1379 *
1380 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1381 */
1382static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1383{
1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1385}
1386
1387u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1388{
1389 u64 _tsc = tsc;
1390 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1391
1392 if (ratio != kvm_default_tsc_scaling_ratio)
1393 _tsc = __scale_tsc(ratio, tsc);
1394
1395 return _tsc;
1396}
1397EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1398
07c1419a
HZ		 1399static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1400{
1401 u64 tsc;
1402
1403 tsc = kvm_scale_tsc(vcpu, rdtsc());
1404
1405 return target_tsc - tsc;
1406}
1407
4ba76538
HZ		 1408u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1409{
1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1411}
1412EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1413
8fe8ab46 1414void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1415{
1416 struct kvm *kvm = vcpu->kvm;
f38e098f 1417 u64 offset, ns, elapsed;
99e3e30a 1418 unsigned long flags;
02626b6a 1419 s64 usdiff;
b48aa97e 1420 bool matched;
0d3da0d2 1421 bool already_matched;
8fe8ab46 1422 u64 data = msr->data;
99e3e30a 1423
038f8c11 1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1425 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1426 ns = get_kernel_ns();
f38e098f 1427 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1428
03ba32ca 1429 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1430 int faulted = 0;
1431
03ba32ca
MT		 1432 /* n.b - signed multiplication and division required */
1433 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1434#ifdef CONFIG_X86_64
03ba32ca 1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1436#else
03ba32ca 1437 /* do_div() only does unsigned */
8915aa27
MT		 1438 asm("1: idivl %[divisor]\n"
1439 "2: xor %%edx, %%edx\n"
1440 " movl $0, %[faulted]\n"
1441 "3:\n"
1442 ".section .fixup,\"ax\"\n"
1443 "4: movl $1, %[faulted]\n"
1444 " jmp 3b\n"
1445 ".previous\n"
1446
1447 _ASM_EXTABLE(1b, 4b)
1448
1449 : "=A"(usdiff), [faulted] "=r" (faulted)
1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1451
5d3cb0f6 1452#endif
03ba32ca
MT		 1453 do_div(elapsed, 1000);
1454 usdiff -= elapsed;
1455 if (usdiff < 0)
1456 usdiff = -usdiff;
8915aa27
MT		 1457
1458 /* idivl overflow => difference is larger than USEC_PER_SEC */
1459 if (faulted)
1460 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1461 } else
1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1463
1464 /*
5d3cb0f6
ZA		 1465 * Special case: TSC write with a small delta (1 second) of virtual
1466 * cycle time against real time is interpreted as an attempt to
1467 * synchronize the CPU.
1468 *
1469 * For a reliable TSC, we can match TSC offsets, and for an unstable
1470 * TSC, we add elapsed time in this computation. We could let the
1471 * compensation code attempt to catch up if we fall behind, but
1472 * it's better to try to match offsets from the beginning.
1473 */
02626b6a 1474 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1476 if (!check_tsc_unstable()) {
e26101b1 1477 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1478 pr_debug("kvm: matched tsc offset for %llu\n", data);
1479 } else {
857e4099 1480 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1481 data += delta;
07c1419a 1482 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1484 }
b48aa97e 1485 matched = true;
0d3da0d2 1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1487 } else {
1488 /*
1489 * We split periods of matched TSC writes into generations.
1490 * For each generation, we track the original measured
1491 * nanosecond time, offset, and write, so if TSCs are in
1492 * sync, we can match exact offset, and if not, we can match
4a969980 1493 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1494 *
1495 * These values are tracked in kvm->arch.cur_xxx variables.
1496 */
1497 kvm->arch.cur_tsc_generation++;
1498 kvm->arch.cur_tsc_nsec = ns;
1499 kvm->arch.cur_tsc_write = data;
1500 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1501 matched = false;
0d3da0d2 1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1503 kvm->arch.cur_tsc_generation, data);
f38e098f 1504 }
e26101b1
ZA		 1505
1506 /*
1507 * We also track th most recent recorded KHZ, write and time to
1508 * allow the matching interval to be extended at each write.
1509 */
f38e098f
ZA		 1510 kvm->arch.last_tsc_nsec = ns;
1511 kvm->arch.last_tsc_write = data;
5d3cb0f6 1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1513
b183aa58 1514 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1515
1516 /* Keep track of which generation this VCPU has synchronized to */
1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1520
ba904635
WA		 1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1522 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1523 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1525
1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1527 if (!matched) {
b48aa97e 1528 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1529 } else if (!already_matched) {
1530 kvm->arch.nr_vcpus_matched_tsc++;
1531 }
b48aa97e
MT		 1532
1533 kvm_track_tsc_matching(vcpu);
1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1535}
e26101b1 1536
99e3e30a
ZA		 1537EXPORT_SYMBOL_GPL(kvm_write_tsc);
1538
58ea6767
HZ		 1539static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1540 s64 adjustment)
1541{
1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1543}
1544
1545static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1546{
1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1548 WARN_ON(adjustment < 0);
1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1551}
1552
d828199e
MT		 1553#ifdef CONFIG_X86_64
1554
1555static cycle_t read_tsc(void)
1556{
03b9730b
AL		 1557 cycle_t ret = (cycle_t)rdtsc_ordered();
1558 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1559
1560 if (likely(ret >= last))
1561 return ret;
1562
1563 /*
1564 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1565 * predictable (it's just a function of time and the likely is
d828199e
MT		 1566 * very likely) and there's a data dependence, so force GCC
1567 * to generate a branch instead. I don't barrier() because
1568 * we don't actually need a barrier, and if this function
1569 * ever gets inlined it will generate worse code.
1570 */
1571 asm volatile ("");
1572 return last;
1573}
1574
1575static inline u64 vgettsc(cycle_t *cycle_now)
1576{
1577 long v;
1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1579
1580 *cycle_now = read_tsc();
1581
1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1583 return v * gtod->clock.mult;
1584}
1585
cbcf2dd3 1586static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1587{
cbcf2dd3 1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1589 unsigned long seq;
d828199e 1590 int mode;
cbcf2dd3 1591 u64 ns;
d828199e 1592
d828199e
MT		 1593 do {
1594 seq = read_seqcount_begin(&gtod->seq);
1595 mode = gtod->clock.vclock_mode;
cbcf2dd3 1596 ns = gtod->nsec_base;
d828199e
MT		 1597 ns += vgettsc(cycle_now);
1598 ns >>= gtod->clock.shift;
cbcf2dd3 1599 ns += gtod->boot_ns;
d828199e 1600 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1601 *t = ns;
d828199e
MT		 1602
1603 return mode;
1604}
1605
1606/* returns true if host is using tsc clocksource */
1607static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1608{
d828199e
MT		 1609 /* checked again under seqlock below */
1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1611 return false;
1612
cbcf2dd3 1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1614}
1615#endif
1616
1617/*
1618 *
b48aa97e
MT		 1619 * Assuming a stable TSC across physical CPUS, and a stable TSC
1620 * across virtual CPUs, the following condition is possible.
1621 * Each numbered line represents an event visible to both
d828199e
MT		 1622 * CPUs at the next numbered event.
1623 *
1624 * "timespecX" represents host monotonic time. "tscX" represents
1625 * RDTSC value.
1626 *
1627 * VCPU0 on CPU0 | VCPU1 on CPU1
1628 *
1629 * 1. read timespec0,tsc0
1630 * 2. | timespec1 = timespec0 + N
1631 * | tsc1 = tsc0 + M
1632 * 3. transition to guest | transition to guest
1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1636 *
1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1638 *
1639 * - ret0 < ret1
1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1641 * ...
1642 * - 0 < N - M => M < N
1643 *
1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1645 * always the case (the difference between two distinct xtime instances
1646 * might be smaller then the difference between corresponding TSC reads,
1647 * when updating guest vcpus pvclock areas).
1648 *
1649 * To avoid that problem, do not allow visibility of distinct
1650 * system_timestamp/tsc_timestamp values simultaneously: use a master
1651 * copy of host monotonic time values. Update that master copy
1652 * in lockstep.
1653 *
b48aa97e 1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1655 *
1656 */
1657
1658static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1659{
1660#ifdef CONFIG_X86_64
1661 struct kvm_arch *ka = &kvm->arch;
1662 int vclock_mode;
b48aa97e
MT		 1663 bool host_tsc_clocksource, vcpus_matched;
1664
1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1666 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1667
1668 /*
1669 * If the host uses TSC clock, then passthrough TSC as stable
1670 * to the guest.
1671 */
b48aa97e 1672 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1673 &ka->master_kernel_ns,
1674 &ka->master_cycle_now);
1675
16a96021 1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1677 && !backwards_tsc_observed
1678 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1679
d828199e
MT		 1680 if (ka->use_master_clock)
1681 atomic_set(&kvm_guest_has_master_clock, 1);
1682
1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1685 vcpus_matched);
d828199e
MT		 1686#endif
1687}
1688
2860c4b1
PB		 1689void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1690{
1691 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1692}
1693
2e762ff7
MT		 1694static void kvm_gen_update_masterclock(struct kvm *kvm)
1695{
1696#ifdef CONFIG_X86_64
1697 int i;
1698 struct kvm_vcpu *vcpu;
1699 struct kvm_arch *ka = &kvm->arch;
1700
1701 spin_lock(&ka->pvclock_gtod_sync_lock);
1702 kvm_make_mclock_inprogress_request(kvm);
1703 /* no guest entries from this point */
1704 pvclock_update_vm_gtod_copy(kvm);
1705
1706 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1708
1709 /* guest entries allowed */
1710 kvm_for_each_vcpu(i, vcpu, kvm)
1711 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1712
1713 spin_unlock(&ka->pvclock_gtod_sync_lock);
1714#endif
1715}
1716
34c238a1 1717static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1718{
78db6a50 1719 unsigned long flags, tgt_tsc_khz;
18068523 1720 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1721 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1722 s64 kernel_ns;
d828199e 1723 u64 tsc_timestamp, host_tsc;
0b79459b 1724 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1725 u8 pvclock_flags;
d828199e
MT		 1726 bool use_master_clock;
1727
1728 kernel_ns = 0;
1729 host_tsc = 0;
18068523 1730
d828199e
MT		 1731 /*
1732 * If the host uses TSC clock, then passthrough TSC as stable
1733 * to the guest.
1734 */
1735 spin_lock(&ka->pvclock_gtod_sync_lock);
1736 use_master_clock = ka->use_master_clock;
1737 if (use_master_clock) {
1738 host_tsc = ka->master_cycle_now;
1739 kernel_ns = ka->master_kernel_ns;
1740 }
1741 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1742
1743 /* Keep irq disabled to prevent changes to the clock */
1744 local_irq_save(flags);
78db6a50
PB		 1745 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1746 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1747 local_irq_restore(flags);
1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1749 return 1;
1750 }
d828199e 1751 if (!use_master_clock) {
4ea1636b 1752 host_tsc = rdtsc();
d828199e
MT		 1753 kernel_ns = get_kernel_ns();
1754 }
1755
4ba76538 1756 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1757
c285545f
ZA		 1758 /*
1759 * We may have to catch up the TSC to match elapsed wall clock
1760 * time for two reasons, even if kvmclock is used.
1761 * 1) CPU could have been running below the maximum TSC rate
1762 * 2) Broken TSC compensation resets the base at each VCPU
1763 * entry to avoid unknown leaps of TSC even when running
1764 * again on the same CPU. This may cause apparent elapsed
1765 * time to disappear, and the guest to stand still or run
1766 * very slowly.
1767 */
1768 if (vcpu->tsc_catchup) {
1769 u64 tsc = compute_guest_tsc(v, kernel_ns);
1770 if (tsc > tsc_timestamp) {
f1e2b260 1771 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1772 tsc_timestamp = tsc;
1773 }
50d0a0f9
GH		 1774 }
1775
18068523
GOC		 1776 local_irq_restore(flags);
1777
0b79459b 1778 if (!vcpu->pv_time_enabled)
c285545f 1779 return 0;
18068523 1780
78db6a50
PB		 1781 if (kvm_has_tsc_control)
1782 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1783
1784 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1785 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1786 &vcpu->hv_clock.tsc_shift,
1787 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1788 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1789 }
1790
1791 /* With all the info we got, fill in the values */
1d5f066e 1792 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1793 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1794 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1795
09a0c3f1
OH		 1796 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1797 &guest_hv_clock, sizeof(guest_hv_clock))))
1798 return 0;
1799
5dca0d91
RK		 1800 /* This VCPU is paused, but it's legal for a guest to read another
1801 * VCPU's kvmclock, so we really have to follow the specification where
1802 * it says that version is odd if data is being modified, and even after
1803 * it is consistent.
1804 *
1805 * Version field updates must be kept separate. This is because
1806 * kvm_write_guest_cached might use a "rep movs" instruction, and
1807 * writes within a string instruction are weakly ordered. So there
1808 * are three writes overall.
1809 *
1810 * As a small optimization, only write the version field in the first
1811 * and third write. The vcpu->pv_time cache is still valid, because the
1812 * version field is the first in the struct.
18068523 1813 */
5dca0d91
RK		 1814 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1815
1816 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1817 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1818 &vcpu->hv_clock,
1819 sizeof(vcpu->hv_clock.version));
1820
1821 smp_wmb();
78c0337a
MT		 1822
1823 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1824 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1825
1826 if (vcpu->pvclock_set_guest_stopped_request) {
1827 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1828 vcpu->pvclock_set_guest_stopped_request = false;
1829 }
1830
d828199e
MT		 1831 /* If the host uses TSC clocksource, then it is stable */
1832 if (use_master_clock)
1833 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1834
78c0337a
MT		 1835 vcpu->hv_clock.flags = pvclock_flags;
1836
ce1a5e60
DM		 1837 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1838
0b79459b
AH		 1839 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1840 &vcpu->hv_clock,
1841 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1842
1843 smp_wmb();
1844
1845 vcpu->hv_clock.version++;
1846 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1847 &vcpu->hv_clock,
1848 sizeof(vcpu->hv_clock.version));
8cfdc000 1849 return 0;
c8076604
GH		 1850}
1851
0061d53d
MT		 1852/*
1853 * kvmclock updates which are isolated to a given vcpu, such as
1854 * vcpu->cpu migration, should not allow system_timestamp from
1855 * the rest of the vcpus to remain static. Otherwise ntp frequency
1856 * correction applies to one vcpu's system_timestamp but not
1857 * the others.
1858 *
1859 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1860 * We need to rate-limit these requests though, as they can
1861 * considerably slow guests that have a large number of vcpus.
1862 * The time for a remote vcpu to update its kvmclock is bound
1863 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1864 */
1865
7e44e449
AJ		 1866#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1867
1868static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1869{
1870 int i;
7e44e449
AJ		 1871 struct delayed_work *dwork = to_delayed_work(work);
1872 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1873 kvmclock_update_work);
1874 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1875 struct kvm_vcpu *vcpu;
1876
1877 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1879 kvm_vcpu_kick(vcpu);
1880 }
1881}
1882
7e44e449
AJ		 1883static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1884{
1885 struct kvm *kvm = v->kvm;
1886
105b21bb 1887 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1888 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1889 KVMCLOCK_UPDATE_DELAY);
1890}
1891
332967a3
AJ		 1892#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1893
1894static void kvmclock_sync_fn(struct work_struct *work)
1895{
1896 struct delayed_work *dwork = to_delayed_work(work);
1897 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1898 kvmclock_sync_work);
1899 struct kvm *kvm = container_of(ka, struct kvm, arch);
1900
630994b3
MT		 1901 if (!kvmclock_periodic_sync)
1902 return;
1903
332967a3
AJ		 1904 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1905 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1906 KVMCLOCK_SYNC_PERIOD);
1907}
1908
890ca9ae 1909static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1910{
890ca9ae
HY		 1911 u64 mcg_cap = vcpu->arch.mcg_cap;
1912 unsigned bank_num = mcg_cap & 0xff;
1913
15c4a640 1914 switch (msr) {
15c4a640 1915 case MSR_IA32_MCG_STATUS:
890ca9ae 1916 vcpu->arch.mcg_status = data;
15c4a640 1917 break;
c7ac679c 1918 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1919 if (!(mcg_cap & MCG_CTL_P))
1920 return 1;
1921 if (data != 0 && data != ~(u64)0)
1922 return -1;
1923 vcpu->arch.mcg_ctl = data;
1924 break;
1925 default:
1926 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1927 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1928 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1929 /* only 0 or all 1s can be written to IA32_MCi_CTL
1930 * some Linux kernels though clear bit 10 in bank 4 to
1931 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1932 * this to avoid an uncatched #GP in the guest
1933 */
890ca9ae 1934 if ((offset & 0x3) == 0 &&
114be429 1935 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1936 return -1;
1937 vcpu->arch.mce_banks[offset] = data;
1938 break;
1939 }
1940 return 1;
1941 }
1942 return 0;
1943}
1944
ffde22ac
ES		 1945static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1946{
1947 struct kvm *kvm = vcpu->kvm;
1948 int lm = is_long_mode(vcpu);
1949 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1950 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1951 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1952 : kvm->arch.xen_hvm_config.blob_size_32;
1953 u32 page_num = data & ~PAGE_MASK;
1954 u64 page_addr = data & PAGE_MASK;
1955 u8 *page;
1956 int r;
1957
1958 r = -E2BIG;
1959 if (page_num >= blob_size)
1960 goto out;
1961 r = -ENOMEM;
ff5c2c03
SL		 1962 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1963 if (IS_ERR(page)) {
1964 r = PTR_ERR(page);
ffde22ac 1965 goto out;
ff5c2c03 1966 }
54bf36aa 1967 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1968 goto out_free;
1969 r = 0;
1970out_free:
1971 kfree(page);
1972out:
1973 return r;
1974}
1975
344d9588
GN		 1976static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1977{
1978 gpa_t gpa = data & ~0x3f;
1979
4a969980 1980 /* Bits 2:5 are reserved, Should be zero */
6adba527 1981 if (data & 0x3c)
344d9588
GN		 1982 return 1;
1983
1984 vcpu->arch.apf.msr_val = data;
1985
1986 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1987 kvm_clear_async_pf_completion_queue(vcpu);
1988 kvm_async_pf_hash_reset(vcpu);
1989 return 0;
1990 }
1991
8f964525
AH		 1992 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1993 sizeof(u32)))
344d9588
GN		 1994 return 1;
1995
6adba527 1996 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1997 kvm_async_pf_wakeup_all(vcpu);
1998 return 0;
1999}
2000
12f9a48f
GC		 2001static void kvmclock_reset(struct kvm_vcpu *vcpu)
2002{
0b79459b 2003 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2004}
2005
c9aaa895
GC		 2006static void record_steal_time(struct kvm_vcpu *vcpu)
2007{
2008 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2009 return;
2010
2011 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2012 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2013 return;
2014
35f3fae1
WL		 2015 if (vcpu->arch.st.steal.version & 1)
2016 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2017
2018 vcpu->arch.st.steal.version += 1;
2019
2020 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2021 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2022
2023 smp_wmb();
2024
c54cdf14
LC		 2025 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2026 vcpu->arch.st.last_steal;
2027 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2028
2029 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2030 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2031
2032 smp_wmb();
2033
2034 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2035
2036 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2037 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2038}
2039
8fe8ab46 2040int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2041{
5753785f 2042 bool pr = false;
8fe8ab46
WA		 2043 u32 msr = msr_info->index;
2044 u64 data = msr_info->data;
5753785f 2045
15c4a640 2046 switch (msr) {
2e32b719
BP		 2047 case MSR_AMD64_NB_CFG:
2048 case MSR_IA32_UCODE_REV:
2049 case MSR_IA32_UCODE_WRITE:
2050 case MSR_VM_HSAVE_PA:
2051 case MSR_AMD64_PATCH_LOADER:
2052 case MSR_AMD64_BU_CFG2:
2053 break;
2054
15c4a640 2055 case MSR_EFER:
b69e8cae 2056 return set_efer(vcpu, data);
8f1589d9
AP		 2057 case MSR_K7_HWCR:
2058 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2059 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2060 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2061 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2062 if (data != 0) {
a737f256
CD		 2063 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2064 data);
8f1589d9
AP		 2065 return 1;
2066 }
15c4a640 2067 break;
f7c6d140
AP		 2068 case MSR_FAM10H_MMIO_CONF_BASE:
2069 if (data != 0) {
a737f256
CD		 2070 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2071 "0x%llx\n", data);
f7c6d140
AP		 2072 return 1;
2073 }
15c4a640 2074 break;
b5e2fec0
AG		 2075 case MSR_IA32_DEBUGCTLMSR:
2076 if (!data) {
2077 /* We support the non-activated case already */
2078 break;
2079 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2080 /* Values other than LBR and BTF are vendor-specific,
2081 thus reserved and should throw a #GP */
2082 return 1;
2083 }
a737f256
CD		 2084 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2085 __func__, data);
b5e2fec0 2086 break;
9ba075a6 2087 case 0x200 ... 0x2ff:
ff53604b 2088 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2089 case MSR_IA32_APICBASE:
58cb628d 2090 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2091 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2092 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2093 case MSR_IA32_TSCDEADLINE:
2094 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2095 break;
ba904635
WA		 2096 case MSR_IA32_TSC_ADJUST:
2097 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2098 if (!msr_info->host_initiated) {
d913b904 2099 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2100 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2101 }
2102 vcpu->arch.ia32_tsc_adjust_msr = data;
2103 }
2104 break;
15c4a640 2105 case MSR_IA32_MISC_ENABLE:
ad312c7c 2106 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2107 break;
64d60670
PB		 2108 case MSR_IA32_SMBASE:
2109 if (!msr_info->host_initiated)
2110 return 1;
2111 vcpu->arch.smbase = data;
2112 break;
11c6bffa 2113 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2114 case MSR_KVM_WALL_CLOCK:
2115 vcpu->kvm->arch.wall_clock = data;
2116 kvm_write_wall_clock(vcpu->kvm, data);
2117 break;
11c6bffa 2118 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2119 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2120 u64 gpa_offset;
54750f2c
MT		 2121 struct kvm_arch *ka = &vcpu->kvm->arch;
2122
12f9a48f 2123 kvmclock_reset(vcpu);
18068523 2124
54750f2c
MT		 2125 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2126 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2127
2128 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2129 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2130 &vcpu->requests);
2131
2132 ka->boot_vcpu_runs_old_kvmclock = tmp;
2133 }
2134
18068523 2135 vcpu->arch.time = data;
0061d53d 2136 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2137
2138 /* we verify if the enable bit is set... */
2139 if (!(data & 1))
2140 break;
2141
0b79459b 2142 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2143
0b79459b 2144 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2145 &vcpu->arch.pv_time, data & ~1ULL,
2146 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2147 vcpu->arch.pv_time_enabled = false;
2148 else
2149 vcpu->arch.pv_time_enabled = true;
32cad84f 2150
18068523
GOC		 2151 break;
2152 }
344d9588
GN		 2153 case MSR_KVM_ASYNC_PF_EN:
2154 if (kvm_pv_enable_async_pf(vcpu, data))
2155 return 1;
2156 break;
c9aaa895
GC		 2157 case MSR_KVM_STEAL_TIME:
2158
2159 if (unlikely(!sched_info_on()))
2160 return 1;
2161
2162 if (data & KVM_STEAL_RESERVED_MASK)
2163 return 1;
2164
2165 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2166 data & KVM_STEAL_VALID_BITS,
2167 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2168 return 1;
2169
2170 vcpu->arch.st.msr_val = data;
2171
2172 if (!(data & KVM_MSR_ENABLED))
2173 break;
2174
c9aaa895
GC		 2175 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2176
2177 break;
ae7a2a3f
MT		 2178 case MSR_KVM_PV_EOI_EN:
2179 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2180 return 1;
2181 break;
c9aaa895 2182
890ca9ae
HY		 2183 case MSR_IA32_MCG_CTL:
2184 case MSR_IA32_MCG_STATUS:
81760dcc 2185 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2186 return set_msr_mce(vcpu, msr, data);
71db6023 2187
6912ac32
WH		 2188 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2189 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2190 pr = true; /* fall through */
2191 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2192 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2193 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2194 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2195
2196 if (pr || data != 0)
a737f256
CD		 2197 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2198 "0x%x data 0x%llx\n", msr, data);
5753785f 2199 break;
84e0cefa
JS		 2200 case MSR_K7_CLK_CTL:
2201 /*
2202 * Ignore all writes to this no longer documented MSR.
2203 * Writes are only relevant for old K7 processors,
2204 * all pre-dating SVM, but a recommended workaround from
4a969980 2205 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2206 * affected processor models on the command line, hence
2207 * the need to ignore the workaround.
2208 */
2209 break;
55cd8e5a 2210 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2211 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2212 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2213 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2214 return kvm_hv_set_msr_common(vcpu, msr, data,
2215 msr_info->host_initiated);
91c9c3ed 2216 case MSR_IA32_BBL_CR_CTL3:
2217 /* Drop writes to this legacy MSR -- see rdmsr
2218 * counterpart for further detail.
2219 */
a737f256 2220 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2221 break;
2b036c6b
BO		 2222 case MSR_AMD64_OSVW_ID_LENGTH:
2223 if (!guest_cpuid_has_osvw(vcpu))
2224 return 1;
2225 vcpu->arch.osvw.length = data;
2226 break;
2227 case MSR_AMD64_OSVW_STATUS:
2228 if (!guest_cpuid_has_osvw(vcpu))
2229 return 1;
2230 vcpu->arch.osvw.status = data;
2231 break;
15c4a640 2232 default:
ffde22ac
ES		 2233 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2234 return xen_hvm_config(vcpu, data);
c6702c9d 2235 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2236 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2237 if (!ignore_msrs) {
a737f256
CD		 2238 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2239 msr, data);
ed85c068
AP		 2240 return 1;
2241 } else {
a737f256
CD		 2242 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2243 msr, data);
ed85c068
AP		 2244 break;
2245 }
15c4a640
CO		 2246 }
2247 return 0;
2248}
2249EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2250
2251
2252/*
2253 * Reads an msr value (of 'msr_index') into 'pdata'.
2254 * Returns 0 on success, non-0 otherwise.
2255 * Assumes vcpu_load() was already called.
2256 */
609e36d3 2257int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2258{
609e36d3 2259 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2260}
ff651cb6 2261EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2262
890ca9ae 2263static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2264{
2265 u64 data;
890ca9ae
HY		 2266 u64 mcg_cap = vcpu->arch.mcg_cap;
2267 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2268
2269 switch (msr) {
15c4a640
CO		 2270 case MSR_IA32_P5_MC_ADDR:
2271 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2272 data = 0;
2273 break;
15c4a640 2274 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2275 data = vcpu->arch.mcg_cap;
2276 break;
c7ac679c 2277 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2278 if (!(mcg_cap & MCG_CTL_P))
2279 return 1;
2280 data = vcpu->arch.mcg_ctl;
2281 break;
2282 case MSR_IA32_MCG_STATUS:
2283 data = vcpu->arch.mcg_status;
2284 break;
2285 default:
2286 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2287 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2288 u32 offset = msr - MSR_IA32_MC0_CTL;
2289 data = vcpu->arch.mce_banks[offset];
2290 break;
2291 }
2292 return 1;
2293 }
2294 *pdata = data;
2295 return 0;
2296}
2297
609e36d3 2298int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2299{
609e36d3 2300 switch (msr_info->index) {
890ca9ae 2301 case MSR_IA32_PLATFORM_ID:
15c4a640 2302 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2303 case MSR_IA32_DEBUGCTLMSR:
2304 case MSR_IA32_LASTBRANCHFROMIP:
2305 case MSR_IA32_LASTBRANCHTOIP:
2306 case MSR_IA32_LASTINTFROMIP:
2307 case MSR_IA32_LASTINTTOIP:
60af2ecd 2308 case MSR_K8_SYSCFG:
3afb1121
PB		 2309 case MSR_K8_TSEG_ADDR:
2310 case MSR_K8_TSEG_MASK:
60af2ecd 2311 case MSR_K7_HWCR:
61a6bd67 2312 case MSR_VM_HSAVE_PA:
1fdbd48c 2313 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2314 case MSR_AMD64_NB_CFG:
f7c6d140 2315 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2316 case MSR_AMD64_BU_CFG2:
0c2df2a1 2317 case MSR_IA32_PERF_CTL:
609e36d3 2318 msr_info->data = 0;
15c4a640 2319 break;
6912ac32
WH		 2320 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2321 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2322 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2323 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2324 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2325 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2326 msr_info->data = 0;
5753785f 2327 break;
742bc670 2328 case MSR_IA32_UCODE_REV:
609e36d3 2329 msr_info->data = 0x100000000ULL;
742bc670 2330 break;
9ba075a6 2331 case MSR_MTRRcap:
9ba075a6 2332 case 0x200 ... 0x2ff:
ff53604b 2333 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2334 case 0xcd: /* fsb frequency */
609e36d3 2335 msr_info->data = 3;
15c4a640 2336 break;
7b914098
JS		 2337 /*
2338 * MSR_EBC_FREQUENCY_ID
2339 * Conservative value valid for even the basic CPU models.
2340 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2341 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2342 * and 266MHz for model 3, or 4. Set Core Clock
2343 * Frequency to System Bus Frequency Ratio to 1 (bits
2344 * 31:24) even though these are only valid for CPU
2345 * models > 2, however guests may end up dividing or
2346 * multiplying by zero otherwise.
2347 */
2348 case MSR_EBC_FREQUENCY_ID:
609e36d3 2349 msr_info->data = 1 << 24;
7b914098 2350 break;
15c4a640 2351 case MSR_IA32_APICBASE:
609e36d3 2352 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2353 break;
0105d1a5 2354 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2355 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2356 break;
a3e06bbe 2357 case MSR_IA32_TSCDEADLINE:
609e36d3 2358 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2359 break;
ba904635 2360 case MSR_IA32_TSC_ADJUST:
609e36d3 2361 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2362 break;
15c4a640 2363 case MSR_IA32_MISC_ENABLE:
609e36d3 2364 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2365 break;
64d60670
PB		 2366 case MSR_IA32_SMBASE:
2367 if (!msr_info->host_initiated)
2368 return 1;
2369 msr_info->data = vcpu->arch.smbase;
15c4a640 2370 break;
847f0ad8
AG		 2371 case MSR_IA32_PERF_STATUS:
2372 /* TSC increment by tick */
609e36d3 2373 msr_info->data = 1000ULL;
847f0ad8 2374 /* CPU multiplier */
b0996ae4 2375 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2376 break;
15c4a640 2377 case MSR_EFER:
609e36d3 2378 msr_info->data = vcpu->arch.efer;
15c4a640 2379 break;
18068523 2380 case MSR_KVM_WALL_CLOCK:
11c6bffa 2381 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2382 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2383 break;
2384 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2385 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2386 msr_info->data = vcpu->arch.time;
18068523 2387 break;
344d9588 2388 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2389 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2390 break;
c9aaa895 2391 case MSR_KVM_STEAL_TIME:
609e36d3 2392 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2393 break;
1d92128f 2394 case MSR_KVM_PV_EOI_EN:
609e36d3 2395 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2396 break;
890ca9ae
HY		 2397 case MSR_IA32_P5_MC_ADDR:
2398 case MSR_IA32_P5_MC_TYPE:
2399 case MSR_IA32_MCG_CAP:
2400 case MSR_IA32_MCG_CTL:
2401 case MSR_IA32_MCG_STATUS:
81760dcc 2402 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2403 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2404 case MSR_K7_CLK_CTL:
2405 /*
2406 * Provide expected ramp-up count for K7. All other
2407 * are set to zero, indicating minimum divisors for
2408 * every field.
2409 *
2410 * This prevents guest kernels on AMD host with CPU
2411 * type 6, model 8 and higher from exploding due to
2412 * the rdmsr failing.
2413 */
609e36d3 2414 msr_info->data = 0x20000000;
84e0cefa 2415 break;
55cd8e5a 2416 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2417 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2418 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2419 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2420 return kvm_hv_get_msr_common(vcpu,
2421 msr_info->index, &msr_info->data);
55cd8e5a 2422 break;
91c9c3ed 2423 case MSR_IA32_BBL_CR_CTL3:
2424 /* This legacy MSR exists but isn't fully documented in current
2425 * silicon. It is however accessed by winxp in very narrow
2426 * scenarios where it sets bit #19, itself documented as
2427 * a "reserved" bit. Best effort attempt to source coherent
2428 * read data here should the balance of the register be
2429 * interpreted by the guest:
2430 *
2431 * L2 cache control register 3: 64GB range, 256KB size,
2432 * enabled, latency 0x1, configured
2433 */
609e36d3 2434 msr_info->data = 0xbe702111;
91c9c3ed 2435 break;
2b036c6b
BO		 2436 case MSR_AMD64_OSVW_ID_LENGTH:
2437 if (!guest_cpuid_has_osvw(vcpu))
2438 return 1;
609e36d3 2439 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2440 break;
2441 case MSR_AMD64_OSVW_STATUS:
2442 if (!guest_cpuid_has_osvw(vcpu))
2443 return 1;
609e36d3 2444 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2445 break;
15c4a640 2446 default:
c6702c9d 2447 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2448 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2449 if (!ignore_msrs) {
609e36d3 2450 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2451 return 1;
2452 } else {
609e36d3
PB		 2453 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2454 msr_info->data = 0;
ed85c068
AP		 2455 }
2456 break;
15c4a640 2457 }
15c4a640
CO		 2458 return 0;
2459}
2460EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2461
313a3dc7
CO		 2462/*
2463 * Read or write a bunch of msrs. All parameters are kernel addresses.
2464 *
2465 * @return number of msrs set successfully.
2466 */
2467static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2468 struct kvm_msr_entry *entries,
2469 int (*do_msr)(struct kvm_vcpu *vcpu,
2470 unsigned index, u64 *data))
2471{
f656ce01 2472 int i, idx;
313a3dc7 2473
f656ce01 2474 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2475 for (i = 0; i < msrs->nmsrs; ++i)
2476 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2477 break;
f656ce01 2478 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2479
313a3dc7
CO		 2480 return i;
2481}
2482
2483/*
2484 * Read or write a bunch of msrs. Parameters are user addresses.
2485 *
2486 * @return number of msrs set successfully.
2487 */
2488static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2489 int (*do_msr)(struct kvm_vcpu *vcpu,
2490 unsigned index, u64 *data),
2491 int writeback)
2492{
2493 struct kvm_msrs msrs;
2494 struct kvm_msr_entry *entries;
2495 int r, n;
2496 unsigned size;
2497
2498 r = -EFAULT;
2499 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2500 goto out;
2501
2502 r = -E2BIG;
2503 if (msrs.nmsrs >= MAX_IO_MSRS)
2504 goto out;
2505
313a3dc7 2506 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2507 entries = memdup_user(user_msrs->entries, size);
2508 if (IS_ERR(entries)) {
2509 r = PTR_ERR(entries);
313a3dc7 2510 goto out;
ff5c2c03 2511 }
313a3dc7
CO		 2512
2513 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2514 if (r < 0)
2515 goto out_free;
2516
2517 r = -EFAULT;
2518 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2519 goto out_free;
2520
2521 r = n;
2522
2523out_free:
7a73c028 2524 kfree(entries);
313a3dc7
CO		 2525out:
2526 return r;
2527}
2528
784aa3d7 2529int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2530{
2531 int r;
2532
2533 switch (ext) {
2534 case KVM_CAP_IRQCHIP:
2535 case KVM_CAP_HLT:
2536 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2537 case KVM_CAP_SET_TSS_ADDR:
07716717 2538 case KVM_CAP_EXT_CPUID:
9c15bb1d 2539 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2540 case KVM_CAP_CLOCKSOURCE:
7837699f 2541 case KVM_CAP_PIT:
a28e4f5a 2542 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2543 case KVM_CAP_MP_STATE:
ed848624 2544 case KVM_CAP_SYNC_MMU:
a355c85c 2545 case KVM_CAP_USER_NMI:
52d939a0 2546 case KVM_CAP_REINJECT_CONTROL:
4925663a 2547 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2548 case KVM_CAP_IOEVENTFD:
f848a5a8 2549 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2550 case KVM_CAP_PIT2:
e9f42757 2551 case KVM_CAP_PIT_STATE2:
b927a3ce 2552 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2553 case KVM_CAP_XEN_HVM:
afbcf7ab 2554 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2555 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2556 case KVM_CAP_HYPERV:
10388a07 2557 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2558 case KVM_CAP_HYPERV_SPIN:
5c919412 2559 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2560 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2561 case KVM_CAP_DEBUGREGS:
d2be1651 2562 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2563 case KVM_CAP_XSAVE:
344d9588 2564 case KVM_CAP_ASYNC_PF:
92a1f12d 2565 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2566 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2567 case KVM_CAP_READONLY_MEM:
5f66b620 2568 case KVM_CAP_HYPERV_TIME:
100943c5 2569 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2570 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2571 case KVM_CAP_ENABLE_CAP_VM:
2572 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2573 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2574 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2575#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2576 case KVM_CAP_ASSIGN_DEV_IRQ:
2577 case KVM_CAP_PCI_2_3:
2578#endif
018d00d2
ZX		 2579 r = 1;
2580 break;
6d396b55
PB		 2581 case KVM_CAP_X86_SMM:
2582 /* SMBASE is usually relocated above 1M on modern chipsets,
2583 * and SMM handlers might indeed rely on 4G segment limits,
2584 * so do not report SMM to be available if real mode is
2585 * emulated via vm86 mode. Still, do not go to great lengths
2586 * to avoid userspace's usage of the feature, because it is a
2587 * fringe case that is not enabled except via specific settings
2588 * of the module parameters.
2589 */
2590 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2591 break;
542472b5
LV		 2592 case KVM_CAP_COALESCED_MMIO:
2593 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2594 break;
774ead3a
AK		 2595 case KVM_CAP_VAPIC:
2596 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2597 break;
f725230a 2598 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2599 r = KVM_SOFT_MAX_VCPUS;
2600 break;
2601 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2602 r = KVM_MAX_VCPUS;
2603 break;
a988b910 2604 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2605 r = KVM_USER_MEM_SLOTS;
a988b910 2606 break;
a68a6a72
MT		 2607 case KVM_CAP_PV_MMU: /* obsolete */
2608 r = 0;
2f333bcb 2609 break;
4cee4b72 2610#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2611 case KVM_CAP_IOMMU:
a1b60c1c 2612 r = iommu_present(&pci_bus_type);
62c476c7 2613 break;
4cee4b72 2614#endif
890ca9ae
HY		 2615 case KVM_CAP_MCE:
2616 r = KVM_MAX_MCE_BANKS;
2617 break;
2d5b5a66 2618 case KVM_CAP_XCRS:
d366bf7e 2619 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2620 break;
92a1f12d
JR		 2621 case KVM_CAP_TSC_CONTROL:
2622 r = kvm_has_tsc_control;
2623 break;
018d00d2
ZX		 2624 default:
2625 r = 0;
2626 break;
2627 }
2628 return r;
2629
2630}
2631
043405e1
CO		 2632long kvm_arch_dev_ioctl(struct file *filp,
2633 unsigned int ioctl, unsigned long arg)
2634{
2635 void __user *argp = (void __user *)arg;
2636 long r;
2637
2638 switch (ioctl) {
2639 case KVM_GET_MSR_INDEX_LIST: {
2640 struct kvm_msr_list __user *user_msr_list = argp;
2641 struct kvm_msr_list msr_list;
2642 unsigned n;
2643
2644 r = -EFAULT;
2645 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2646 goto out;
2647 n = msr_list.nmsrs;
62ef68bb 2648 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2649 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2650 goto out;
2651 r = -E2BIG;
e125e7b6 2652 if (n < msr_list.nmsrs)
043405e1
CO		 2653 goto out;
2654 r = -EFAULT;
2655 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2656 num_msrs_to_save * sizeof(u32)))
2657 goto out;
e125e7b6 2658 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2659 &emulated_msrs,
62ef68bb 2660 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2661 goto out;
2662 r = 0;
2663 break;
2664 }
9c15bb1d
BP		 2665 case KVM_GET_SUPPORTED_CPUID:
2666 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2667 struct kvm_cpuid2 __user *cpuid_arg = argp;
2668 struct kvm_cpuid2 cpuid;
2669
2670 r = -EFAULT;
2671 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2672 goto out;
9c15bb1d
BP		 2673
2674 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2675 ioctl);
674eea0f
AK		 2676 if (r)
2677 goto out;
2678
2679 r = -EFAULT;
2680 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2681 goto out;
2682 r = 0;
2683 break;
2684 }
890ca9ae
HY		 2685 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2686 u64 mce_cap;
2687
2688 mce_cap = KVM_MCE_CAP_SUPPORTED;
2689 r = -EFAULT;
2690 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2691 goto out;
2692 r = 0;
2693 break;
2694 }
043405e1
CO		 2695 default:
2696 r = -EINVAL;
2697 }
2698out:
2699 return r;
2700}
2701
f5f48ee1
SY		 2702static void wbinvd_ipi(void *garbage)
2703{
2704 wbinvd();
2705}
2706
2707static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2708{
e0f0bbc5 2709 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2710}
2711
2860c4b1
PB		 2712static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2713{
2714 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2715}
2716
313a3dc7
CO		 2717void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2718{
f5f48ee1
SY		 2719 /* Address WBINVD may be executed by guest */
2720 if (need_emulate_wbinvd(vcpu)) {
2721 if (kvm_x86_ops->has_wbinvd_exit())
2722 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2723 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2724 smp_call_function_single(vcpu->cpu,
2725 wbinvd_ipi, NULL, 1);
2726 }
2727
313a3dc7 2728 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2729
0dd6a6ed
ZA		 2730 /* Apply any externally detected TSC adjustments (due to suspend) */
2731 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2732 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2733 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2734 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2735 }
8f6055cb 2736
48434c20 2737 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2738 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2739 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2740 if (tsc_delta < 0)
2741 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2742 if (check_tsc_unstable()) {
07c1419a 2743 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2744 vcpu->arch.last_guest_tsc);
2745 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2746 vcpu->arch.tsc_catchup = 1;
c285545f 2747 }
d98d07ca
MT		 2748 /*
2749 * On a host with synchronized TSC, there is no need to update
2750 * kvmclock on vcpu->cpu migration
2751 */
2752 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2753 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2754 if (vcpu->cpu != cpu)
2755 kvm_migrate_timers(vcpu);
e48672fa 2756 vcpu->cpu = cpu;
6b7d7e76 2757 }
c9aaa895 2758
c9aaa895 2759 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2760}
2761
2762void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2763{
02daab21 2764 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2765 kvm_put_guest_fpu(vcpu);
4ea1636b 2766 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2767}
2768
313a3dc7
CO		 2769static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2770 struct kvm_lapic_state *s)
2771{
d62caabb
AS		 2772 if (vcpu->arch.apicv_active)
2773 kvm_x86_ops->sync_pir_to_irr(vcpu);
2774
ad312c7c 2775 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2776
2777 return 0;
2778}
2779
2780static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2781 struct kvm_lapic_state *s)
2782{
64eb0620 2783 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2784 update_cr8_intercept(vcpu);
313a3dc7
CO		 2785
2786 return 0;
2787}
2788
127a457a
MG		 2789static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2790{
2791 return (!lapic_in_kernel(vcpu) ||
2792 kvm_apic_accept_pic_intr(vcpu));
2793}
2794
782d422b
MG		 2795/*
2796 * if userspace requested an interrupt window, check that the
2797 * interrupt window is open.
2798 *
2799 * No need to exit to userspace if we already have an interrupt queued.
2800 */
2801static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2802{
2803 return kvm_arch_interrupt_allowed(vcpu) &&
2804 !kvm_cpu_has_interrupt(vcpu) &&
2805 !kvm_event_needs_reinjection(vcpu) &&
2806 kvm_cpu_accept_dm_intr(vcpu);
2807}
2808
f77bc6a4
ZX		 2809static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2810 struct kvm_interrupt *irq)
2811{
02cdb50f 2812 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2813 return -EINVAL;
1c1a9ce9
SR		 2814
2815 if (!irqchip_in_kernel(vcpu->kvm)) {
2816 kvm_queue_interrupt(vcpu, irq->irq, false);
2817 kvm_make_request(KVM_REQ_EVENT, vcpu);
2818 return 0;
2819 }
2820
2821 /*
2822 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2823 * fail for in-kernel 8259.
2824 */
2825 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2826 return -ENXIO;
f77bc6a4 2827
1c1a9ce9
SR		 2828 if (vcpu->arch.pending_external_vector != -1)
2829 return -EEXIST;
f77bc6a4 2830
1c1a9ce9 2831 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2832 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2833 return 0;
2834}
2835
c4abb7c9
JK		 2836static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2837{
c4abb7c9 2838 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2839
2840 return 0;
2841}
2842
f077825a
PB		 2843static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2844{
64d60670
PB		 2845 kvm_make_request(KVM_REQ_SMI, vcpu);
2846
f077825a
PB		 2847 return 0;
2848}
2849
b209749f
AK		 2850static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2851 struct kvm_tpr_access_ctl *tac)
2852{
2853 if (tac->flags)
2854 return -EINVAL;
2855 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2856 return 0;
2857}
2858
890ca9ae
HY		 2859static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2860 u64 mcg_cap)
2861{
2862 int r;
2863 unsigned bank_num = mcg_cap & 0xff, bank;
2864
2865 r = -EINVAL;
a9e38c3e 2866 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2867 goto out;
2868 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2869 goto out;
2870 r = 0;
2871 vcpu->arch.mcg_cap = mcg_cap;
2872 /* Init IA32_MCG_CTL to all 1s */
2873 if (mcg_cap & MCG_CTL_P)
2874 vcpu->arch.mcg_ctl = ~(u64)0;
2875 /* Init IA32_MCi_CTL to all 1s */
2876 for (bank = 0; bank < bank_num; bank++)
2877 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2878out:
2879 return r;
2880}
2881
2882static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2883 struct kvm_x86_mce *mce)
2884{
2885 u64 mcg_cap = vcpu->arch.mcg_cap;
2886 unsigned bank_num = mcg_cap & 0xff;
2887 u64 *banks = vcpu->arch.mce_banks;
2888
2889 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2890 return -EINVAL;
2891 /*
2892 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2893 * reporting is disabled
2894 */
2895 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2896 vcpu->arch.mcg_ctl != ~(u64)0)
2897 return 0;
2898 banks += 4 * mce->bank;
2899 /*
2900 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2901 * reporting is disabled for the bank
2902 */
2903 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2904 return 0;
2905 if (mce->status & MCI_STATUS_UC) {
2906 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2907 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2908 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2909 return 0;
2910 }
2911 if (banks[1] & MCI_STATUS_VAL)
2912 mce->status |= MCI_STATUS_OVER;
2913 banks[2] = mce->addr;
2914 banks[3] = mce->misc;
2915 vcpu->arch.mcg_status = mce->mcg_status;
2916 banks[1] = mce->status;
2917 kvm_queue_exception(vcpu, MC_VECTOR);
2918 } else if (!(banks[1] & MCI_STATUS_VAL)
2919 || !(banks[1] & MCI_STATUS_UC)) {
2920 if (banks[1] & MCI_STATUS_VAL)
2921 mce->status |= MCI_STATUS_OVER;
2922 banks[2] = mce->addr;
2923 banks[3] = mce->misc;
2924 banks[1] = mce->status;
2925 } else
2926 banks[1] |= MCI_STATUS_OVER;
2927 return 0;
2928}
2929
3cfc3092
JK		 2930static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2931 struct kvm_vcpu_events *events)
2932{
7460fb4a 2933 process_nmi(vcpu);
03b82a30
JK		 2934 events->exception.injected =
2935 vcpu->arch.exception.pending &&
2936 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2937 events->exception.nr = vcpu->arch.exception.nr;
2938 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2939 events->exception.pad = 0;
3cfc3092
JK		 2940 events->exception.error_code = vcpu->arch.exception.error_code;
2941
03b82a30
JK		 2942 events->interrupt.injected =
2943 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2944 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2945 events->interrupt.soft = 0;
37ccdcbe 2946 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2947
2948 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2949 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2950 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2951 events->nmi.pad = 0;
3cfc3092 2952
66450a21 2953 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2954
f077825a
PB		 2955 events->smi.smm = is_smm(vcpu);
2956 events->smi.pending = vcpu->arch.smi_pending;
2957 events->smi.smm_inside_nmi =
2958 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2959 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2960
dab4b911 2961 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2962 | KVM_VCPUEVENT_VALID_SHADOW
2963 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2964 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2965}
2966
2967static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2968 struct kvm_vcpu_events *events)
2969{
dab4b911 2970 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2971 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2972 | KVM_VCPUEVENT_VALID_SHADOW
2973 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2974 return -EINVAL;
2975
7460fb4a 2976 process_nmi(vcpu);
3cfc3092
JK		 2977 vcpu->arch.exception.pending = events->exception.injected;
2978 vcpu->arch.exception.nr = events->exception.nr;
2979 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2980 vcpu->arch.exception.error_code = events->exception.error_code;
2981
2982 vcpu->arch.interrupt.pending = events->interrupt.injected;
2983 vcpu->arch.interrupt.nr = events->interrupt.nr;
2984 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2985 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2986 kvm_x86_ops->set_interrupt_shadow(vcpu,
2987 events->interrupt.shadow);
3cfc3092
JK		 2988
2989 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2990 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2991 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2992 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2993
66450a21 2994 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 2995 lapic_in_kernel(vcpu))
66450a21 2996 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2997
f077825a
PB		 2998 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2999 if (events->smi.smm)
3000 vcpu->arch.hflags |= HF_SMM_MASK;
3001 else
3002 vcpu->arch.hflags &= ~HF_SMM_MASK;
3003 vcpu->arch.smi_pending = events->smi.pending;
3004 if (events->smi.smm_inside_nmi)
3005 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3006 else
3007 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3008 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3009 if (events->smi.latched_init)
3010 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3011 else
3012 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3013 }
3014 }
3015
3842d135
AK		 3016 kvm_make_request(KVM_REQ_EVENT, vcpu);
3017
3cfc3092
JK		 3018 return 0;
3019}
3020
a1efbe77
JK		 3021static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3022 struct kvm_debugregs *dbgregs)
3023{
73aaf249
JK		 3024 unsigned long val;
3025
a1efbe77 3026 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3027 kvm_get_dr(vcpu, 6, &val);
73aaf249 3028 dbgregs->dr6 = val;
a1efbe77
JK		 3029 dbgregs->dr7 = vcpu->arch.dr7;
3030 dbgregs->flags = 0;
97e69aa6 3031 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3032}
3033
3034static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3035 struct kvm_debugregs *dbgregs)
3036{
3037 if (dbgregs->flags)
3038 return -EINVAL;
3039
a1efbe77 3040 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3041 kvm_update_dr0123(vcpu);
a1efbe77 3042 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3043 kvm_update_dr6(vcpu);
a1efbe77 3044 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3045 kvm_update_dr7(vcpu);
a1efbe77 3046
a1efbe77
JK		 3047 return 0;
3048}
3049
df1daba7
PB		 3050#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3051
3052static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3053{
c47ada30 3054 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3055 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3056 u64 valid;
3057
3058 /*
3059 * Copy legacy XSAVE area, to avoid complications with CPUID
3060 * leaves 0 and 1 in the loop below.
3061 */
3062 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3063
3064 /* Set XSTATE_BV */
3065 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3066
3067 /*
3068 * Copy each region from the possibly compacted offset to the
3069 * non-compacted offset.
3070 */
d91cab78 3071 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3072 while (valid) {
3073 u64 feature = valid & -valid;
3074 int index = fls64(feature) - 1;
3075 void *src = get_xsave_addr(xsave, feature);
3076
3077 if (src) {
3078 u32 size, offset, ecx, edx;
3079 cpuid_count(XSTATE_CPUID, index,
3080 &size, &offset, &ecx, &edx);
3081 memcpy(dest + offset, src, size);
3082 }
3083
3084 valid -= feature;
3085 }
3086}
3087
3088static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3089{
c47ada30 3090 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3091 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3092 u64 valid;
3093
3094 /*
3095 * Copy legacy XSAVE area, to avoid complications with CPUID
3096 * leaves 0 and 1 in the loop below.
3097 */
3098 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3099
3100 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3101 xsave->header.xfeatures = xstate_bv;
782511b0 3102 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3103 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3104
3105 /*
3106 * Copy each region from the non-compacted offset to the
3107 * possibly compacted offset.
3108 */
d91cab78 3109 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3110 while (valid) {
3111 u64 feature = valid & -valid;
3112 int index = fls64(feature) - 1;
3113 void *dest = get_xsave_addr(xsave, feature);
3114
3115 if (dest) {
3116 u32 size, offset, ecx, edx;
3117 cpuid_count(XSTATE_CPUID, index,
3118 &size, &offset, &ecx, &edx);
3119 memcpy(dest, src + offset, size);
ee4100da 3120 }
df1daba7
PB		 3121
3122 valid -= feature;
3123 }
3124}
3125
2d5b5a66
SY		 3126static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3127 struct kvm_xsave *guest_xsave)
3128{
d366bf7e 3129 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3130 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3131 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3132 } else {
2d5b5a66 3133 memcpy(guest_xsave->region,
7366ed77 3134 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3135 sizeof(struct fxregs_state));
2d5b5a66 3136 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3137 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3138 }
3139}
3140
3141static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3142 struct kvm_xsave *guest_xsave)
3143{
3144 u64 xstate_bv =
3145 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3146
d366bf7e 3147 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3148 /*
3149 * Here we allow setting states that are not present in
3150 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3151 * with old userspace.
3152 */
4ff41732 3153 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3154 return -EINVAL;
df1daba7 3155 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3156 } else {
d91cab78 3157 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3158 return -EINVAL;
7366ed77 3159 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3160 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3161 }
3162 return 0;
3163}
3164
3165static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3166 struct kvm_xcrs *guest_xcrs)
3167{
d366bf7e 3168 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3169 guest_xcrs->nr_xcrs = 0;
3170 return;
3171 }
3172
3173 guest_xcrs->nr_xcrs = 1;
3174 guest_xcrs->flags = 0;
3175 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3176 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3177}
3178
3179static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3180 struct kvm_xcrs *guest_xcrs)
3181{
3182 int i, r = 0;
3183
d366bf7e 3184 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3185 return -EINVAL;
3186
3187 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3188 return -EINVAL;
3189
3190 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3191 /* Only support XCR0 currently */
c67a04cb 3192 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3193 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3194 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3195 break;
3196 }
3197 if (r)
3198 r = -EINVAL;
3199 return r;
3200}
3201
1c0b28c2
EM		 3202/*
3203 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3204 * stopped by the hypervisor. This function will be called from the host only.
3205 * EINVAL is returned when the host attempts to set the flag for a guest that
3206 * does not support pv clocks.
3207 */
3208static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3209{
0b79459b 3210 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3211 return -EINVAL;
51d59c6b 3212 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3213 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3214 return 0;
3215}
3216
5c919412
AS		 3217static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3218 struct kvm_enable_cap *cap)
3219{
3220 if (cap->flags)
3221 return -EINVAL;
3222
3223 switch (cap->cap) {
3224 case KVM_CAP_HYPERV_SYNIC:
3225 return kvm_hv_activate_synic(vcpu);
3226 default:
3227 return -EINVAL;
3228 }
3229}
3230
313a3dc7
CO		 3231long kvm_arch_vcpu_ioctl(struct file *filp,
3232 unsigned int ioctl, unsigned long arg)
3233{
3234 struct kvm_vcpu *vcpu = filp->private_data;
3235 void __user *argp = (void __user *)arg;
3236 int r;
d1ac91d8
AK		 3237 union {
3238 struct kvm_lapic_state *lapic;
3239 struct kvm_xsave *xsave;
3240 struct kvm_xcrs *xcrs;
3241 void *buffer;
3242 } u;
3243
3244 u.buffer = NULL;
313a3dc7
CO		 3245 switch (ioctl) {
3246 case KVM_GET_LAPIC: {
2204ae3c 3247 r = -EINVAL;
bce87cce 3248 if (!lapic_in_kernel(vcpu))
2204ae3c 3249 goto out;
d1ac91d8 3250 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3251
b772ff36 3252 r = -ENOMEM;
d1ac91d8 3253 if (!u.lapic)
b772ff36 3254 goto out;
d1ac91d8 3255 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3256 if (r)
3257 goto out;
3258 r = -EFAULT;
d1ac91d8 3259 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3260 goto out;
3261 r = 0;
3262 break;
3263 }
3264 case KVM_SET_LAPIC: {
2204ae3c 3265 r = -EINVAL;
bce87cce 3266 if (!lapic_in_kernel(vcpu))
2204ae3c 3267 goto out;
ff5c2c03 3268 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3269 if (IS_ERR(u.lapic))
3270 return PTR_ERR(u.lapic);
ff5c2c03 3271
d1ac91d8 3272 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3273 break;
3274 }
f77bc6a4
ZX		 3275 case KVM_INTERRUPT: {
3276 struct kvm_interrupt irq;
3277
3278 r = -EFAULT;
3279 if (copy_from_user(&irq, argp, sizeof irq))
3280 goto out;
3281 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3282 break;
3283 }
c4abb7c9
JK		 3284 case KVM_NMI: {
3285 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3286 break;
3287 }
f077825a
PB		 3288 case KVM_SMI: {
3289 r = kvm_vcpu_ioctl_smi(vcpu);
3290 break;
3291 }
313a3dc7
CO		 3292 case KVM_SET_CPUID: {
3293 struct kvm_cpuid __user *cpuid_arg = argp;
3294 struct kvm_cpuid cpuid;
3295
3296 r = -EFAULT;
3297 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3298 goto out;
3299 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3300 break;
3301 }
07716717
DK		 3302 case KVM_SET_CPUID2: {
3303 struct kvm_cpuid2 __user *cpuid_arg = argp;
3304 struct kvm_cpuid2 cpuid;
3305
3306 r = -EFAULT;
3307 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3308 goto out;
3309 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3310 cpuid_arg->entries);
07716717
DK		 3311 break;
3312 }
3313 case KVM_GET_CPUID2: {
3314 struct kvm_cpuid2 __user *cpuid_arg = argp;
3315 struct kvm_cpuid2 cpuid;
3316
3317 r = -EFAULT;
3318 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3319 goto out;
3320 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3321 cpuid_arg->entries);
07716717
DK		 3322 if (r)
3323 goto out;
3324 r = -EFAULT;
3325 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3326 goto out;
3327 r = 0;
3328 break;
3329 }
313a3dc7 3330 case KVM_GET_MSRS:
609e36d3 3331 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3332 break;
3333 case KVM_SET_MSRS:
3334 r = msr_io(vcpu, argp, do_set_msr, 0);
3335 break;
b209749f
AK		 3336 case KVM_TPR_ACCESS_REPORTING: {
3337 struct kvm_tpr_access_ctl tac;
3338
3339 r = -EFAULT;
3340 if (copy_from_user(&tac, argp, sizeof tac))
3341 goto out;
3342 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3343 if (r)
3344 goto out;
3345 r = -EFAULT;
3346 if (copy_to_user(argp, &tac, sizeof tac))
3347 goto out;
3348 r = 0;
3349 break;
3350 };
b93463aa
AK		 3351 case KVM_SET_VAPIC_ADDR: {
3352 struct kvm_vapic_addr va;
3353
3354 r = -EINVAL;
35754c98 3355 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3356 goto out;
3357 r = -EFAULT;
3358 if (copy_from_user(&va, argp, sizeof va))
3359 goto out;
fda4e2e8 3360 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3361 break;
3362 }
890ca9ae
HY		 3363 case KVM_X86_SETUP_MCE: {
3364 u64 mcg_cap;
3365
3366 r = -EFAULT;
3367 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3368 goto out;
3369 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3370 break;
3371 }
3372 case KVM_X86_SET_MCE: {
3373 struct kvm_x86_mce mce;
3374
3375 r = -EFAULT;
3376 if (copy_from_user(&mce, argp, sizeof mce))
3377 goto out;
3378 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3379 break;
3380 }
3cfc3092
JK		 3381 case KVM_GET_VCPU_EVENTS: {
3382 struct kvm_vcpu_events events;
3383
3384 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3385
3386 r = -EFAULT;
3387 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3388 break;
3389 r = 0;
3390 break;
3391 }
3392 case KVM_SET_VCPU_EVENTS: {
3393 struct kvm_vcpu_events events;
3394
3395 r = -EFAULT;
3396 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3397 break;
3398
3399 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3400 break;
3401 }
a1efbe77
JK		 3402 case KVM_GET_DEBUGREGS: {
3403 struct kvm_debugregs dbgregs;
3404
3405 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3406
3407 r = -EFAULT;
3408 if (copy_to_user(argp, &dbgregs,
3409 sizeof(struct kvm_debugregs)))
3410 break;
3411 r = 0;
3412 break;
3413 }
3414 case KVM_SET_DEBUGREGS: {
3415 struct kvm_debugregs dbgregs;
3416
3417 r = -EFAULT;
3418 if (copy_from_user(&dbgregs, argp,
3419 sizeof(struct kvm_debugregs)))
3420 break;
3421
3422 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3423 break;
3424 }
2d5b5a66 3425 case KVM_GET_XSAVE: {
d1ac91d8 3426 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3427 r = -ENOMEM;
d1ac91d8 3428 if (!u.xsave)
2d5b5a66
SY		 3429 break;
3430
d1ac91d8 3431 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3432
3433 r = -EFAULT;
d1ac91d8 3434 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3435 break;
3436 r = 0;
3437 break;
3438 }
3439 case KVM_SET_XSAVE: {
ff5c2c03 3440 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3441 if (IS_ERR(u.xsave))
3442 return PTR_ERR(u.xsave);
2d5b5a66 3443
d1ac91d8 3444 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3445 break;
3446 }
3447 case KVM_GET_XCRS: {
d1ac91d8 3448 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3449 r = -ENOMEM;
d1ac91d8 3450 if (!u.xcrs)
2d5b5a66
SY		 3451 break;
3452
d1ac91d8 3453 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3454
3455 r = -EFAULT;
d1ac91d8 3456 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3457 sizeof(struct kvm_xcrs)))
3458 break;
3459 r = 0;
3460 break;
3461 }
3462 case KVM_SET_XCRS: {
ff5c2c03 3463 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3464 if (IS_ERR(u.xcrs))
3465 return PTR_ERR(u.xcrs);
2d5b5a66 3466
d1ac91d8 3467 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3468 break;
3469 }
92a1f12d
JR		 3470 case KVM_SET_TSC_KHZ: {
3471 u32 user_tsc_khz;
3472
3473 r = -EINVAL;
92a1f12d
JR		 3474 user_tsc_khz = (u32)arg;
3475
3476 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3477 goto out;
3478
cc578287
ZA		 3479 if (user_tsc_khz == 0)
3480 user_tsc_khz = tsc_khz;
3481
381d585c
HZ		 3482 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3483 r = 0;
92a1f12d 3484
92a1f12d
JR		 3485 goto out;
3486 }
3487 case KVM_GET_TSC_KHZ: {
cc578287 3488 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3489 goto out;
3490 }
1c0b28c2
EM		 3491 case KVM_KVMCLOCK_CTRL: {
3492 r = kvm_set_guest_paused(vcpu);
3493 goto out;
3494 }
5c919412
AS		 3495 case KVM_ENABLE_CAP: {
3496 struct kvm_enable_cap cap;
3497
3498 r = -EFAULT;
3499 if (copy_from_user(&cap, argp, sizeof(cap)))
3500 goto out;
3501 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3502 break;
3503 }
313a3dc7
CO		 3504 default:
3505 r = -EINVAL;
3506 }
3507out:
d1ac91d8 3508 kfree(u.buffer);
313a3dc7
CO		 3509 return r;
3510}
3511
5b1c1493
CO		 3512int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3513{
3514 return VM_FAULT_SIGBUS;
3515}
3516
1fe779f8
CO		 3517static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3518{
3519 int ret;
3520
3521 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3522 return -EINVAL;
1fe779f8
CO		 3523 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3524 return ret;
3525}
3526
b927a3ce
SY		 3527static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3528 u64 ident_addr)
3529{
3530 kvm->arch.ept_identity_map_addr = ident_addr;
3531 return 0;
3532}
3533
1fe779f8
CO		 3534static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3535 u32 kvm_nr_mmu_pages)
3536{
3537 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3538 return -EINVAL;
3539
79fac95e 3540 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3541
3542 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3543 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3544
79fac95e 3545 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3546 return 0;
3547}
3548
3549static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3550{
39de71ec 3551 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3552}
3553
1fe779f8
CO		 3554static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3555{
3556 int r;
3557
3558 r = 0;
3559 switch (chip->chip_id) {
3560 case KVM_IRQCHIP_PIC_MASTER:
3561 memcpy(&chip->chip.pic,
3562 &pic_irqchip(kvm)->pics[0],
3563 sizeof(struct kvm_pic_state));
3564 break;
3565 case KVM_IRQCHIP_PIC_SLAVE:
3566 memcpy(&chip->chip.pic,
3567 &pic_irqchip(kvm)->pics[1],
3568 sizeof(struct kvm_pic_state));
3569 break;
3570 case KVM_IRQCHIP_IOAPIC:
eba0226b 3571 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3572 break;
3573 default:
3574 r = -EINVAL;
3575 break;
3576 }
3577 return r;
3578}
3579
3580static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3581{
3582 int r;
3583
3584 r = 0;
3585 switch (chip->chip_id) {
3586 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3587 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3588 memcpy(&pic_irqchip(kvm)->pics[0],
3589 &chip->chip.pic,
3590 sizeof(struct kvm_pic_state));
f4f51050 3591 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3592 break;
3593 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3594 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3595 memcpy(&pic_irqchip(kvm)->pics[1],
3596 &chip->chip.pic,
3597 sizeof(struct kvm_pic_state));
f4f51050 3598 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3599 break;
3600 case KVM_IRQCHIP_IOAPIC:
eba0226b 3601 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3602 break;
3603 default:
3604 r = -EINVAL;
3605 break;
3606 }
3607 kvm_pic_update_irq(pic_irqchip(kvm));
3608 return r;
3609}
3610
e0f63cb9
SY		 3611static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3612{
34f3941c
RK		 3613 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3614
3615 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3616
3617 mutex_lock(&kps->lock);
3618 memcpy(ps, &kps->channels, sizeof(*ps));
3619 mutex_unlock(&kps->lock);
2da29bcc 3620 return 0;
e0f63cb9
SY		 3621}
3622
3623static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3624{
0185604c 3625 int i;
09edea72
RK		 3626 struct kvm_pit *pit = kvm->arch.vpit;
3627
3628 mutex_lock(&pit->pit_state.lock);
34f3941c 3629 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3630 for (i = 0; i < 3; i++)
09edea72
RK		 3631 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3632 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3633 return 0;
e9f42757
BK		 3634}
3635
3636static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3637{
e9f42757
BK		 3638 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3639 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3640 sizeof(ps->channels));
3641 ps->flags = kvm->arch.vpit->pit_state.flags;
3642 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3643 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3644 return 0;
e9f42757
BK		 3645}
3646
3647static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3648{
2da29bcc 3649 int start = 0;
0185604c 3650 int i;
e9f42757 3651 u32 prev_legacy, cur_legacy;
09edea72
RK		 3652 struct kvm_pit *pit = kvm->arch.vpit;
3653
3654 mutex_lock(&pit->pit_state.lock);
3655 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3656 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3657 if (!prev_legacy && cur_legacy)
3658 start = 1;
09edea72
RK		 3659 memcpy(&pit->pit_state.channels, &ps->channels,
3660 sizeof(pit->pit_state.channels));
3661 pit->pit_state.flags = ps->flags;
0185604c 3662 for (i = 0; i < 3; i++)
09edea72 3663 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3664 start && i == 0);
09edea72 3665 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3666 return 0;
e0f63cb9
SY		 3667}
3668
52d939a0
MT		 3669static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3670 struct kvm_reinject_control *control)
3671{
71474e2f
RK		 3672 struct kvm_pit *pit = kvm->arch.vpit;
3673
3674 if (!pit)
52d939a0 3675 return -ENXIO;
b39c90b6 3676
71474e2f
RK		 3677 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3678 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3679 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3680 */
3681 mutex_lock(&pit->pit_state.lock);
3682 kvm_pit_set_reinject(pit, control->pit_reinject);
3683 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3684
52d939a0
MT		 3685 return 0;
3686}
3687
95d4c16c 3688/**
60c34612
TY		 3689 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3690 * @kvm: kvm instance
3691 * @log: slot id and address to which we copy the log
95d4c16c 3692 *
e108ff2f
PB		 3693 * Steps 1-4 below provide general overview of dirty page logging. See
3694 * kvm_get_dirty_log_protect() function description for additional details.
3695 *
3696 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3697 * always flush the TLB (step 4) even if previous step failed and the dirty
3698 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3699 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3700 * writes will be marked dirty for next log read.
95d4c16c 3701 *
60c34612
TY		 3702 * 1. Take a snapshot of the bit and clear it if needed.
3703 * 2. Write protect the corresponding page.
e108ff2f
PB		 3704 * 3. Copy the snapshot to the userspace.
3705 * 4. Flush TLB's if needed.
5bb064dc 3706 */
60c34612 3707int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3708{
60c34612 3709 bool is_dirty = false;
e108ff2f 3710 int r;
5bb064dc 3711
79fac95e 3712 mutex_lock(&kvm->slots_lock);
5bb064dc 3713
88178fd4
KH		 3714 /*
3715 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3716 */
3717 if (kvm_x86_ops->flush_log_dirty)
3718 kvm_x86_ops->flush_log_dirty(kvm);
3719
e108ff2f 3720 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3721
3722 /*
3723 * All the TLBs can be flushed out of mmu lock, see the comments in
3724 * kvm_mmu_slot_remove_write_access().
3725 */
e108ff2f 3726 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3727 if (is_dirty)
3728 kvm_flush_remote_tlbs(kvm);
3729
79fac95e 3730 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3731 return r;
3732}
3733
aa2fbe6d
YZ		 3734int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3735 bool line_status)
23d43cf9
CD		 3736{
3737 if (!irqchip_in_kernel(kvm))
3738 return -ENXIO;
3739
3740 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3741 irq_event->irq, irq_event->level,
3742 line_status);
23d43cf9
CD		 3743 return 0;
3744}
3745
90de4a18
NA		 3746static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3747 struct kvm_enable_cap *cap)
3748{
3749 int r;
3750
3751 if (cap->flags)
3752 return -EINVAL;
3753
3754 switch (cap->cap) {
3755 case KVM_CAP_DISABLE_QUIRKS:
3756 kvm->arch.disabled_quirks = cap->args[0];
3757 r = 0;
3758 break;
49df6397
SR		 3759 case KVM_CAP_SPLIT_IRQCHIP: {
3760 mutex_lock(&kvm->lock);
b053b2ae
SR		 3761 r = -EINVAL;
3762 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3763 goto split_irqchip_unlock;
49df6397
SR		 3764 r = -EEXIST;
3765 if (irqchip_in_kernel(kvm))
3766 goto split_irqchip_unlock;
3767 if (atomic_read(&kvm->online_vcpus))
3768 goto split_irqchip_unlock;
3769 r = kvm_setup_empty_irq_routing(kvm);
3770 if (r)
3771 goto split_irqchip_unlock;
3772 /* Pairs with irqchip_in_kernel. */
3773 smp_wmb();
3774 kvm->arch.irqchip_split = true;
b053b2ae 3775 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3776 r = 0;
3777split_irqchip_unlock:
3778 mutex_unlock(&kvm->lock);
3779 break;
3780 }
90de4a18
NA		 3781 default:
3782 r = -EINVAL;
3783 break;
3784 }
3785 return r;
3786}
3787
1fe779f8
CO		 3788long kvm_arch_vm_ioctl(struct file *filp,
3789 unsigned int ioctl, unsigned long arg)
3790{
3791 struct kvm *kvm = filp->private_data;
3792 void __user *argp = (void __user *)arg;
367e1319 3793 int r = -ENOTTY;
f0d66275
DH		 3794 /*
3795 * This union makes it completely explicit to gcc-3.x
3796 * that these two variables' stack usage should be
3797 * combined, not added together.
3798 */
3799 union {
3800 struct kvm_pit_state ps;
e9f42757 3801 struct kvm_pit_state2 ps2;
c5ff41ce 3802 struct kvm_pit_config pit_config;
f0d66275 3803 } u;
1fe779f8
CO		 3804
3805 switch (ioctl) {
3806 case KVM_SET_TSS_ADDR:
3807 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3808 break;
b927a3ce
SY		 3809 case KVM_SET_IDENTITY_MAP_ADDR: {
3810 u64 ident_addr;
3811
3812 r = -EFAULT;
3813 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3814 goto out;
3815 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3816 break;
3817 }
1fe779f8
CO		 3818 case KVM_SET_NR_MMU_PAGES:
3819 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3820 break;
3821 case KVM_GET_NR_MMU_PAGES:
3822 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3823 break;
3ddea128
MT		 3824 case KVM_CREATE_IRQCHIP: {
3825 struct kvm_pic *vpic;
3826
3827 mutex_lock(&kvm->lock);
3828 r = -EEXIST;
3829 if (kvm->arch.vpic)
3830 goto create_irqchip_unlock;
3e515705
AK		 3831 r = -EINVAL;
3832 if (atomic_read(&kvm->online_vcpus))
3833 goto create_irqchip_unlock;
1fe779f8 3834 r = -ENOMEM;
3ddea128
MT		 3835 vpic = kvm_create_pic(kvm);
3836 if (vpic) {
1fe779f8
CO		 3837 r = kvm_ioapic_init(kvm);
3838 if (r) {
175504cd 3839 mutex_lock(&kvm->slots_lock);
71ba994c 3840 kvm_destroy_pic(vpic);
175504cd 3841 mutex_unlock(&kvm->slots_lock);
3ddea128 3842 goto create_irqchip_unlock;
1fe779f8
CO		 3843 }
3844 } else
3ddea128 3845 goto create_irqchip_unlock;
399ec807
AK		 3846 r = kvm_setup_default_irq_routing(kvm);
3847 if (r) {
175504cd 3848 mutex_lock(&kvm->slots_lock);
3ddea128 3849 mutex_lock(&kvm->irq_lock);
72bb2fcd 3850 kvm_ioapic_destroy(kvm);
71ba994c 3851 kvm_destroy_pic(vpic);
3ddea128 3852 mutex_unlock(&kvm->irq_lock);
175504cd 3853 mutex_unlock(&kvm->slots_lock);
71ba994c 3854 goto create_irqchip_unlock;
399ec807 3855 }
71ba994c
PB		 3856 /* Write kvm->irq_routing before kvm->arch.vpic. */
3857 smp_wmb();
3858 kvm->arch.vpic = vpic;
3ddea128
MT		 3859 create_irqchip_unlock:
3860 mutex_unlock(&kvm->lock);
1fe779f8 3861 break;
3ddea128 3862 }
7837699f 3863 case KVM_CREATE_PIT:
c5ff41ce
JK		 3864 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3865 goto create_pit;
3866 case KVM_CREATE_PIT2:
3867 r = -EFAULT;
3868 if (copy_from_user(&u.pit_config, argp,
3869 sizeof(struct kvm_pit_config)))
3870 goto out;
3871 create_pit:
79fac95e 3872 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3873 r = -EEXIST;
3874 if (kvm->arch.vpit)
3875 goto create_pit_unlock;
7837699f 3876 r = -ENOMEM;
c5ff41ce 3877 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3878 if (kvm->arch.vpit)
3879 r = 0;
269e05e4 3880 create_pit_unlock:
79fac95e 3881 mutex_unlock(&kvm->slots_lock);
7837699f 3882 break;
1fe779f8
CO		 3883 case KVM_GET_IRQCHIP: {
3884 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3885 struct kvm_irqchip *chip;
1fe779f8 3886
ff5c2c03
SL		 3887 chip = memdup_user(argp, sizeof(*chip));
3888 if (IS_ERR(chip)) {
3889 r = PTR_ERR(chip);
1fe779f8 3890 goto out;
ff5c2c03
SL		 3891 }
3892
1fe779f8 3893 r = -ENXIO;
49df6397 3894 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3895 goto get_irqchip_out;
3896 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3897 if (r)
f0d66275 3898 goto get_irqchip_out;
1fe779f8 3899 r = -EFAULT;
f0d66275
DH		 3900 if (copy_to_user(argp, chip, sizeof *chip))
3901 goto get_irqchip_out;
1fe779f8 3902 r = 0;
f0d66275
DH		 3903 get_irqchip_out:
3904 kfree(chip);
1fe779f8
CO		 3905 break;
3906 }
3907 case KVM_SET_IRQCHIP: {
3908 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3909 struct kvm_irqchip *chip;
1fe779f8 3910
ff5c2c03
SL		 3911 chip = memdup_user(argp, sizeof(*chip));
3912 if (IS_ERR(chip)) {
3913 r = PTR_ERR(chip);
1fe779f8 3914 goto out;
ff5c2c03
SL		 3915 }
3916
1fe779f8 3917 r = -ENXIO;
49df6397 3918 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3919 goto set_irqchip_out;
3920 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3921 if (r)
f0d66275 3922 goto set_irqchip_out;
1fe779f8 3923 r = 0;
f0d66275
DH		 3924 set_irqchip_out:
3925 kfree(chip);
1fe779f8
CO		 3926 break;
3927 }
e0f63cb9 3928 case KVM_GET_PIT: {
e0f63cb9 3929 r = -EFAULT;
f0d66275 3930 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3931 goto out;
3932 r = -ENXIO;
3933 if (!kvm->arch.vpit)
3934 goto out;
f0d66275 3935 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3936 if (r)
3937 goto out;
3938 r = -EFAULT;
f0d66275 3939 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3940 goto out;
3941 r = 0;
3942 break;
3943 }
3944 case KVM_SET_PIT: {
e0f63cb9 3945 r = -EFAULT;
f0d66275 3946 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3947 goto out;
3948 r = -ENXIO;
3949 if (!kvm->arch.vpit)
3950 goto out;
f0d66275 3951 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3952 break;
3953 }
e9f42757
BK		 3954 case KVM_GET_PIT2: {
3955 r = -ENXIO;
3956 if (!kvm->arch.vpit)
3957 goto out;
3958 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3959 if (r)
3960 goto out;
3961 r = -EFAULT;
3962 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3963 goto out;
3964 r = 0;
3965 break;
3966 }
3967 case KVM_SET_PIT2: {
3968 r = -EFAULT;
3969 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3970 goto out;
3971 r = -ENXIO;
3972 if (!kvm->arch.vpit)
3973 goto out;
3974 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3975 break;
3976 }
52d939a0
MT		 3977 case KVM_REINJECT_CONTROL: {
3978 struct kvm_reinject_control control;
3979 r = -EFAULT;
3980 if (copy_from_user(&control, argp, sizeof(control)))
3981 goto out;
3982 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3983 break;
3984 }
d71ba788
PB		 3985 case KVM_SET_BOOT_CPU_ID:
3986 r = 0;
3987 mutex_lock(&kvm->lock);
3988 if (atomic_read(&kvm->online_vcpus) != 0)
3989 r = -EBUSY;
3990 else
3991 kvm->arch.bsp_vcpu_id = arg;
3992 mutex_unlock(&kvm->lock);
3993 break;
ffde22ac
ES		 3994 case KVM_XEN_HVM_CONFIG: {
3995 r = -EFAULT;
3996 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3997 sizeof(struct kvm_xen_hvm_config)))
3998 goto out;
3999 r = -EINVAL;
4000 if (kvm->arch.xen_hvm_config.flags)
4001 goto out;
4002 r = 0;
4003 break;
4004 }
afbcf7ab 4005 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4006 struct kvm_clock_data user_ns;
4007 u64 now_ns;
4008 s64 delta;
4009
4010 r = -EFAULT;
4011 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4012 goto out;
4013
4014 r = -EINVAL;
4015 if (user_ns.flags)
4016 goto out;
4017
4018 r = 0;
395c6b0a 4019 local_irq_disable();
759379dd 4020 now_ns = get_kernel_ns();
afbcf7ab 4021 delta = user_ns.clock - now_ns;
395c6b0a 4022 local_irq_enable();
afbcf7ab 4023 kvm->arch.kvmclock_offset = delta;
2e762ff7 4024 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4025 break;
4026 }
4027 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4028 struct kvm_clock_data user_ns;
4029 u64 now_ns;
4030
395c6b0a 4031 local_irq_disable();
759379dd 4032 now_ns = get_kernel_ns();
afbcf7ab 4033 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4034 local_irq_enable();
afbcf7ab 4035 user_ns.flags = 0;
97e69aa6 4036 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4037
4038 r = -EFAULT;
4039 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4040 goto out;
4041 r = 0;
4042 break;
4043 }
90de4a18
NA		 4044 case KVM_ENABLE_CAP: {
4045 struct kvm_enable_cap cap;
afbcf7ab 4046
90de4a18
NA		 4047 r = -EFAULT;
4048 if (copy_from_user(&cap, argp, sizeof(cap)))
4049 goto out;
4050 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4051 break;
4052 }
1fe779f8 4053 default:
c274e03a 4054 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4055 }
4056out:
4057 return r;
4058}
4059
a16b043c 4060static void kvm_init_msr_list(void)
043405e1
CO		 4061{
4062 u32 dummy[2];
4063 unsigned i, j;
4064
62ef68bb 4065 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4066 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4067 continue;
93c4adc7
PB		 4068
4069 /*
4070 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4071 * to the guests in some cases.
93c4adc7
PB		 4072 */
4073 switch (msrs_to_save[i]) {
4074 case MSR_IA32_BNDCFGS:
4075 if (!kvm_x86_ops->mpx_supported())
4076 continue;
4077 break;
9dbe6cf9
PB		 4078 case MSR_TSC_AUX:
4079 if (!kvm_x86_ops->rdtscp_supported())
4080 continue;
4081 break;
93c4adc7
PB		 4082 default:
4083 break;
4084 }
4085
043405e1
CO		 4086 if (j < i)
4087 msrs_to_save[j] = msrs_to_save[i];
4088 j++;
4089 }
4090 num_msrs_to_save = j;
62ef68bb
PB		 4091
4092 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4093 switch (emulated_msrs[i]) {
6d396b55
PB		 4094 case MSR_IA32_SMBASE:
4095 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4096 continue;
4097 break;
62ef68bb
PB		 4098 default:
4099 break;
4100 }
4101
4102 if (j < i)
4103 emulated_msrs[j] = emulated_msrs[i];
4104 j++;
4105 }
4106 num_emulated_msrs = j;
043405e1
CO		 4107}
4108
bda9020e
MT		 4109static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4110 const void *v)
bbd9b64e 4111{
70252a10
AK		 4112 int handled = 0;
4113 int n;
4114
4115 do {
4116 n = min(len, 8);
bce87cce 4117 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4118 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4119 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4120 break;
4121 handled += n;
4122 addr += n;
4123 len -= n;
4124 v += n;
4125 } while (len);
bbd9b64e 4126
70252a10 4127 return handled;
bbd9b64e
CO		 4128}
4129
bda9020e 4130static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4131{
70252a10
AK		 4132 int handled = 0;
4133 int n;
4134
4135 do {
4136 n = min(len, 8);
bce87cce 4137 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4138 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4139 addr, n, v))
4140 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4141 break;
4142 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4143 handled += n;
4144 addr += n;
4145 len -= n;
4146 v += n;
4147 } while (len);
bbd9b64e 4148
70252a10 4149 return handled;
bbd9b64e
CO		 4150}
4151
2dafc6c2
GN		 4152static void kvm_set_segment(struct kvm_vcpu *vcpu,
4153 struct kvm_segment *var, int seg)
4154{
4155 kvm_x86_ops->set_segment(vcpu, var, seg);
4156}
4157
4158void kvm_get_segment(struct kvm_vcpu *vcpu,
4159 struct kvm_segment *var, int seg)
4160{
4161 kvm_x86_ops->get_segment(vcpu, var, seg);
4162}
4163
54987b7a
PB		 4164gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4165 struct x86_exception *exception)
02f59dc9
JR		 4166{
4167 gpa_t t_gpa;
02f59dc9
JR		 4168
4169 BUG_ON(!mmu_is_nested(vcpu));
4170
4171 /* NPT walks are always user-walks */
4172 access |= PFERR_USER_MASK;
54987b7a 4173 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4174
4175 return t_gpa;
4176}
4177
ab9ae313
AK		 4178gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4179 struct x86_exception *exception)
1871c602
GN		 4180{
4181 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4182 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4183}
4184
ab9ae313
AK		 4185 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4186 struct x86_exception *exception)
1871c602
GN		 4187{
4188 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4189 access |= PFERR_FETCH_MASK;
ab9ae313 4190 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4191}
4192
ab9ae313
AK		 4193gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4194 struct x86_exception *exception)
1871c602
GN		 4195{
4196 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4197 access |= PFERR_WRITE_MASK;
ab9ae313 4198 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4199}
4200
4201/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4202gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4203 struct x86_exception *exception)
1871c602 4204{
ab9ae313 4205 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4206}
4207
4208static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4209 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4210 struct x86_exception *exception)
bbd9b64e
CO		 4211{
4212 void *data = val;
10589a46 4213 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4214
4215 while (bytes) {
14dfe855 4216 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4217 exception);
bbd9b64e 4218 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4219 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4220 int ret;
4221
bcc55cba 4222 if (gpa == UNMAPPED_GVA)
ab9ae313 4223 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4224 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4225 offset, toread);
10589a46 4226 if (ret < 0) {
c3cd7ffa 4227 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4228 goto out;
4229 }
bbd9b64e 4230
77c2002e
IE		 4231 bytes -= toread;
4232 data += toread;
4233 addr += toread;
bbd9b64e 4234 }
10589a46 4235out:
10589a46 4236 return r;
bbd9b64e 4237}
77c2002e 4238
1871c602 4239/* used for instruction fetching */
0f65dd70
AK		 4240static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4241 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4242 struct x86_exception *exception)
1871c602 4243{
0f65dd70 4244 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4245 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4246 unsigned offset;
4247 int ret;
0f65dd70 4248
44583cba
PB		 4249 /* Inline kvm_read_guest_virt_helper for speed. */
4250 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4251 exception);
4252 if (unlikely(gpa == UNMAPPED_GVA))
4253 return X86EMUL_PROPAGATE_FAULT;
4254
4255 offset = addr & (PAGE_SIZE-1);
4256 if (WARN_ON(offset + bytes > PAGE_SIZE))
4257 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4258 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4259 offset, bytes);
44583cba
PB		 4260 if (unlikely(ret < 0))
4261 return X86EMUL_IO_NEEDED;
4262
4263 return X86EMUL_CONTINUE;
1871c602
GN		 4264}
4265
064aea77 4266int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4267 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4268 struct x86_exception *exception)
1871c602 4269{
0f65dd70 4270 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4271 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4272
1871c602 4273 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4274 exception);
1871c602 4275}
064aea77 4276EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4277
0f65dd70
AK		 4278static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4279 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4280 struct x86_exception *exception)
1871c602 4281{
0f65dd70 4282 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4283 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4284}
4285
7a036a6f
RK		 4286static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4287 unsigned long addr, void *val, unsigned int bytes)
4288{
4289 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4290 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4291
4292 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4293}
4294
6a4d7550 4295int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4296 gva_t addr, void *val,
2dafc6c2 4297 unsigned int bytes,
bcc55cba 4298 struct x86_exception *exception)
77c2002e 4299{
0f65dd70 4300 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4301 void *data = val;
4302 int r = X86EMUL_CONTINUE;
4303
4304 while (bytes) {
14dfe855
JR		 4305 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4306 PFERR_WRITE_MASK,
ab9ae313 4307 exception);
77c2002e
IE		 4308 unsigned offset = addr & (PAGE_SIZE-1);
4309 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4310 int ret;
4311
bcc55cba 4312 if (gpa == UNMAPPED_GVA)
ab9ae313 4313 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4314 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4315 if (ret < 0) {
c3cd7ffa 4316 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4317 goto out;
4318 }
4319
4320 bytes -= towrite;
4321 data += towrite;
4322 addr += towrite;
4323 }
4324out:
4325 return r;
4326}
6a4d7550 4327EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4328
af7cc7d1
XG		 4329static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4330 gpa_t *gpa, struct x86_exception *exception,
4331 bool write)
4332{
97d64b78
AK		 4333 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4334 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4335
be94f6b7
HH		 4336 /*
4337 * currently PKRU is only applied to ept enabled guest so
4338 * there is no pkey in EPT page table for L1 guest or EPT
4339 * shadow page table for L2 guest.
4340 */
97d64b78 4341 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4342 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4343 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4344 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4345 (gva & (PAGE_SIZE - 1));
4f022648 4346 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4347 return 1;
4348 }
4349
af7cc7d1
XG		 4350 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4351
4352 if (*gpa == UNMAPPED_GVA)
4353 return -1;
4354
4355 /* For APIC access vmexit */
4356 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4357 return 1;
4358
4f022648
XG		 4359 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4360 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4361 return 1;
4f022648 4362 }
bebb106a 4363
af7cc7d1
XG		 4364 return 0;
4365}
4366
3200f405 4367int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4368 const void *val, int bytes)
bbd9b64e
CO		 4369{
4370 int ret;
4371
54bf36aa 4372 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4373 if (ret < 0)
bbd9b64e 4374 return 0;
0eb05bf2 4375 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4376 return 1;
4377}
4378
77d197b2
XG		 4379struct read_write_emulator_ops {
4380 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4381 int bytes);
4382 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4383 void *val, int bytes);
4384 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4385 int bytes, void *val);
4386 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4387 void *val, int bytes);
4388 bool write;
4389};
4390
4391static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4392{
4393 if (vcpu->mmio_read_completed) {
77d197b2 4394 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4395 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4396 vcpu->mmio_read_completed = 0;
4397 return 1;
4398 }
4399
4400 return 0;
4401}
4402
4403static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4404 void *val, int bytes)
4405{
54bf36aa 4406 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4407}
4408
4409static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4410 void *val, int bytes)
4411{
4412 return emulator_write_phys(vcpu, gpa, val, bytes);
4413}
4414
4415static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4416{
4417 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4418 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4419}
4420
4421static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4422 void *val, int bytes)
4423{
4424 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4425 return X86EMUL_IO_NEEDED;
4426}
4427
4428static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4429 void *val, int bytes)
4430{
f78146b0
AK		 4431 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4432
87da7e66 4433 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4434 return X86EMUL_CONTINUE;
4435}
4436
0fbe9b0b 4437static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4438 .read_write_prepare = read_prepare,
4439 .read_write_emulate = read_emulate,
4440 .read_write_mmio = vcpu_mmio_read,
4441 .read_write_exit_mmio = read_exit_mmio,
4442};
4443
0fbe9b0b 4444static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4445 .read_write_emulate = write_emulate,
4446 .read_write_mmio = write_mmio,
4447 .read_write_exit_mmio = write_exit_mmio,
4448 .write = true,
4449};
4450
22388a3c
XG		 4451static int emulator_read_write_onepage(unsigned long addr, void *val,
4452 unsigned int bytes,
4453 struct x86_exception *exception,
4454 struct kvm_vcpu *vcpu,
0fbe9b0b 4455 const struct read_write_emulator_ops *ops)
bbd9b64e 4456{
af7cc7d1
XG		 4457 gpa_t gpa;
4458 int handled, ret;
22388a3c 4459 bool write = ops->write;
f78146b0 4460 struct kvm_mmio_fragment *frag;
10589a46 4461
22388a3c 4462 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4463
af7cc7d1 4464 if (ret < 0)
bbd9b64e 4465 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4466
4467 /* For APIC access vmexit */
af7cc7d1 4468 if (ret)
bbd9b64e
CO		 4469 goto mmio;
4470
22388a3c 4471 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4472 return X86EMUL_CONTINUE;
4473
4474mmio:
4475 /*
4476 * Is this MMIO handled locally?
4477 */
22388a3c 4478 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4479 if (handled == bytes)
bbd9b64e 4480 return X86EMUL_CONTINUE;
bbd9b64e 4481
70252a10
AK		 4482 gpa += handled;
4483 bytes -= handled;
4484 val += handled;
4485
87da7e66
XG		 4486 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4487 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4488 frag->gpa = gpa;
4489 frag->data = val;
4490 frag->len = bytes;
f78146b0 4491 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4492}
4493
52eb5a6d
XL		 4494static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4495 unsigned long addr,
22388a3c
XG		 4496 void *val, unsigned int bytes,
4497 struct x86_exception *exception,
0fbe9b0b 4498 const struct read_write_emulator_ops *ops)
bbd9b64e 4499{
0f65dd70 4500 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4501 gpa_t gpa;
4502 int rc;
4503
4504 if (ops->read_write_prepare &&
4505 ops->read_write_prepare(vcpu, val, bytes))
4506 return X86EMUL_CONTINUE;
4507
4508 vcpu->mmio_nr_fragments = 0;
0f65dd70 4509
bbd9b64e
CO		 4510 /* Crossing a page boundary? */
4511 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4512 int now;
bbd9b64e
CO		 4513
4514 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4515 rc = emulator_read_write_onepage(addr, val, now, exception,
4516 vcpu, ops);
4517
bbd9b64e
CO		 4518 if (rc != X86EMUL_CONTINUE)
4519 return rc;
4520 addr += now;
bac15531
NA		 4521 if (ctxt->mode != X86EMUL_MODE_PROT64)
4522 addr = (u32)addr;
bbd9b64e
CO		 4523 val += now;
4524 bytes -= now;
4525 }
22388a3c 4526
f78146b0
AK		 4527 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4528 vcpu, ops);
4529 if (rc != X86EMUL_CONTINUE)
4530 return rc;
4531
4532 if (!vcpu->mmio_nr_fragments)
4533 return rc;
4534
4535 gpa = vcpu->mmio_fragments[0].gpa;
4536
4537 vcpu->mmio_needed = 1;
4538 vcpu->mmio_cur_fragment = 0;
4539
87da7e66 4540 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4541 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4542 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4543 vcpu->run->mmio.phys_addr = gpa;
4544
4545 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4546}
4547
4548static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4549 unsigned long addr,
4550 void *val,
4551 unsigned int bytes,
4552 struct x86_exception *exception)
4553{
4554 return emulator_read_write(ctxt, addr, val, bytes,
4555 exception, &read_emultor);
4556}
4557
52eb5a6d 4558static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4559 unsigned long addr,
4560 const void *val,
4561 unsigned int bytes,
4562 struct x86_exception *exception)
4563{
4564 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4565 exception, &write_emultor);
bbd9b64e 4566}
bbd9b64e 4567
daea3e73
AK		 4568#define CMPXCHG_TYPE(t, ptr, old, new) \
4569 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4570
4571#ifdef CONFIG_X86_64
4572# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4573#else
4574# define CMPXCHG64(ptr, old, new) \
9749a6c0 4575 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4576#endif
4577
0f65dd70
AK		 4578static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4579 unsigned long addr,
bbd9b64e
CO		 4580 const void *old,
4581 const void *new,
4582 unsigned int bytes,
0f65dd70 4583 struct x86_exception *exception)
bbd9b64e 4584{
0f65dd70 4585 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4586 gpa_t gpa;
4587 struct page *page;
4588 char *kaddr;
4589 bool exchanged;
2bacc55c 4590
daea3e73
AK		 4591 /* guests cmpxchg8b have to be emulated atomically */
4592 if (bytes > 8 || (bytes & (bytes - 1)))
4593 goto emul_write;
10589a46 4594
daea3e73 4595 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4596
daea3e73
AK		 4597 if (gpa == UNMAPPED_GVA ||
4598 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4599 goto emul_write;
2bacc55c 4600
daea3e73
AK		 4601 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4602 goto emul_write;
72dc67a6 4603
54bf36aa 4604 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4605 if (is_error_page(page))
c19b8bd6 4606 goto emul_write;
72dc67a6 4607
8fd75e12 4608 kaddr = kmap_atomic(page);
daea3e73
AK		 4609 kaddr += offset_in_page(gpa);
4610 switch (bytes) {
4611 case 1:
4612 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4613 break;
4614 case 2:
4615 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4616 break;
4617 case 4:
4618 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4619 break;
4620 case 8:
4621 exchanged = CMPXCHG64(kaddr, old, new);
4622 break;
4623 default:
4624 BUG();
2bacc55c 4625 }
8fd75e12 4626 kunmap_atomic(kaddr);
daea3e73
AK		 4627 kvm_release_page_dirty(page);
4628
4629 if (!exchanged)
4630 return X86EMUL_CMPXCHG_FAILED;
4631
54bf36aa 4632 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4633 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4634
4635 return X86EMUL_CONTINUE;
4a5f48f6 4636
3200f405 4637emul_write:
daea3e73 4638 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4639
0f65dd70 4640 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4641}
4642
cf8f70bf
GN		 4643static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4644{
4645 /* TODO: String I/O for in kernel device */
4646 int r;
4647
4648 if (vcpu->arch.pio.in)
e32edf4f 4649 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4650 vcpu->arch.pio.size, pd);
4651 else
e32edf4f 4652 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4653 vcpu->arch.pio.port, vcpu->arch.pio.size,
4654 pd);
4655 return r;
4656}
4657
6f6fbe98
XG		 4658static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4659 unsigned short port, void *val,
4660 unsigned int count, bool in)
cf8f70bf 4661{
cf8f70bf 4662 vcpu->arch.pio.port = port;
6f6fbe98 4663 vcpu->arch.pio.in = in;
7972995b 4664 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4665 vcpu->arch.pio.size = size;
4666
4667 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4668 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4669 return 1;
4670 }
4671
4672 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4673 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4674 vcpu->run->io.size = size;
4675 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4676 vcpu->run->io.count = count;
4677 vcpu->run->io.port = port;
4678
4679 return 0;
4680}
4681
6f6fbe98
XG		 4682static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4683 int size, unsigned short port, void *val,
4684 unsigned int count)
cf8f70bf 4685{
ca1d4a9e 4686 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4687 int ret;
ca1d4a9e 4688
6f6fbe98
XG		 4689 if (vcpu->arch.pio.count)
4690 goto data_avail;
cf8f70bf 4691
6f6fbe98
XG		 4692 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4693 if (ret) {
4694data_avail:
4695 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4696 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4697 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4698 return 1;
4699 }
4700
cf8f70bf
GN		 4701 return 0;
4702}
4703
6f6fbe98
XG		 4704static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4705 int size, unsigned short port,
4706 const void *val, unsigned int count)
4707{
4708 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4709
4710 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4711 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4712 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4713}
4714
bbd9b64e
CO		 4715static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4716{
4717 return kvm_x86_ops->get_segment_base(vcpu, seg);
4718}
4719
3cb16fe7 4720static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4721{
3cb16fe7 4722 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4723}
4724
5cb56059 4725int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4726{
4727 if (!need_emulate_wbinvd(vcpu))
4728 return X86EMUL_CONTINUE;
4729
4730 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4731 int cpu = get_cpu();
4732
4733 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4734 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4735 wbinvd_ipi, NULL, 1);
2eec7343 4736 put_cpu();
f5f48ee1 4737 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4738 } else
4739 wbinvd();
f5f48ee1
SY		 4740 return X86EMUL_CONTINUE;
4741}
5cb56059
JS		 4742
4743int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4744{
4745 kvm_x86_ops->skip_emulated_instruction(vcpu);
4746 return kvm_emulate_wbinvd_noskip(vcpu);
4747}
f5f48ee1
SY		 4748EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4749
5cb56059
JS		 4750
4751
bcaf5cc5
AK		 4752static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4753{
5cb56059 4754 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4755}
4756
52eb5a6d
XL		 4757static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4758 unsigned long *dest)
bbd9b64e 4759{
16f8a6f9 4760 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4761}
4762
52eb5a6d
XL		 4763static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4764 unsigned long value)
bbd9b64e 4765{
338dbc97 4766
717746e3 4767 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4768}
4769
52a46617 4770static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4771{
52a46617 4772 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4773}
4774
717746e3 4775static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4776{
717746e3 4777 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4778 unsigned long value;
4779
4780 switch (cr) {
4781 case 0:
4782 value = kvm_read_cr0(vcpu);
4783 break;
4784 case 2:
4785 value = vcpu->arch.cr2;
4786 break;
4787 case 3:
9f8fe504 4788 value = kvm_read_cr3(vcpu);
52a46617
GN		 4789 break;
4790 case 4:
4791 value = kvm_read_cr4(vcpu);
4792 break;
4793 case 8:
4794 value = kvm_get_cr8(vcpu);
4795 break;
4796 default:
a737f256 4797 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4798 return 0;
4799 }
4800
4801 return value;
4802}
4803
717746e3 4804static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4805{
717746e3 4806 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4807 int res = 0;
4808
52a46617
GN		 4809 switch (cr) {
4810 case 0:
49a9b07e 4811 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4812 break;
4813 case 2:
4814 vcpu->arch.cr2 = val;
4815 break;
4816 case 3:
2390218b 4817 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4818 break;
4819 case 4:
a83b29c6 4820 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4821 break;
4822 case 8:
eea1cff9 4823 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4824 break;
4825 default:
a737f256 4826 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4827 res = -1;
52a46617 4828 }
0f12244f
GN		 4829
4830 return res;
52a46617
GN		 4831}
4832
717746e3 4833static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4834{
717746e3 4835 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4836}
4837
4bff1e86 4838static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4839{
4bff1e86 4840 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4841}
4842
4bff1e86 4843static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4844{
4bff1e86 4845 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4846}
4847
1ac9d0cf
AK		 4848static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4849{
4850 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4851}
4852
4853static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4854{
4855 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4856}
4857
4bff1e86
AK		 4858static unsigned long emulator_get_cached_segment_base(
4859 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4860{
4bff1e86 4861 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4862}
4863
1aa36616
AK		 4864static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4865 struct desc_struct *desc, u32 *base3,
4866 int seg)
2dafc6c2
GN		 4867{
4868 struct kvm_segment var;
4869
4bff1e86 4870 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4871 *selector = var.selector;
2dafc6c2 4872
378a8b09
GN		 4873 if (var.unusable) {
4874 memset(desc, 0, sizeof(*desc));
2dafc6c2 4875 return false;
378a8b09 4876 }
2dafc6c2
GN		 4877
4878 if (var.g)
4879 var.limit >>= 12;
4880 set_desc_limit(desc, var.limit);
4881 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4882#ifdef CONFIG_X86_64
4883 if (base3)
4884 *base3 = var.base >> 32;
4885#endif
2dafc6c2
GN		 4886 desc->type = var.type;
4887 desc->s = var.s;
4888 desc->dpl = var.dpl;
4889 desc->p = var.present;
4890 desc->avl = var.avl;
4891 desc->l = var.l;
4892 desc->d = var.db;
4893 desc->g = var.g;
4894
4895 return true;
4896}
4897
1aa36616
AK		 4898static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4899 struct desc_struct *desc, u32 base3,
4900 int seg)
2dafc6c2 4901{
4bff1e86 4902 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4903 struct kvm_segment var;
4904
1aa36616 4905 var.selector = selector;
2dafc6c2 4906 var.base = get_desc_base(desc);
5601d05b
GN		 4907#ifdef CONFIG_X86_64
4908 var.base |= ((u64)base3) << 32;
4909#endif
2dafc6c2
GN		 4910 var.limit = get_desc_limit(desc);
4911 if (desc->g)
4912 var.limit = (var.limit << 12) | 0xfff;
4913 var.type = desc->type;
2dafc6c2
GN		 4914 var.dpl = desc->dpl;
4915 var.db = desc->d;
4916 var.s = desc->s;
4917 var.l = desc->l;
4918 var.g = desc->g;
4919 var.avl = desc->avl;
4920 var.present = desc->p;
4921 var.unusable = !var.present;
4922 var.padding = 0;
4923
4924 kvm_set_segment(vcpu, &var, seg);
4925 return;
4926}
4927
717746e3
AK		 4928static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4929 u32 msr_index, u64 *pdata)
4930{
609e36d3
PB		 4931 struct msr_data msr;
4932 int r;
4933
4934 msr.index = msr_index;
4935 msr.host_initiated = false;
4936 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4937 if (r)
4938 return r;
4939
4940 *pdata = msr.data;
4941 return 0;
717746e3
AK		 4942}
4943
4944static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4945 u32 msr_index, u64 data)
4946{
8fe8ab46
WA		 4947 struct msr_data msr;
4948
4949 msr.data = data;
4950 msr.index = msr_index;
4951 msr.host_initiated = false;
4952 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4953}
4954
64d60670
PB		 4955static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4956{
4957 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4958
4959 return vcpu->arch.smbase;
4960}
4961
4962static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4963{
4964 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4965
4966 vcpu->arch.smbase = smbase;
4967}
4968
67f4d428
NA		 4969static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4970 u32 pmc)
4971{
c6702c9d 4972 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4973}
4974
222d21aa
AK		 4975static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4976 u32 pmc, u64 *pdata)
4977{
c6702c9d 4978 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4979}
4980
6c3287f7
AK		 4981static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4982{
4983 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4984}
4985
5037f6f3
AK		 4986static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4987{
4988 preempt_disable();
5197b808 4989 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4990 /*
4991 * CR0.TS may reference the host fpu state, not the guest fpu state,
4992 * so it may be clear at this point.
4993 */
4994 clts();
4995}
4996
4997static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4998{
4999 preempt_enable();
5000}
5001
2953538e 5002static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5003 struct x86_instruction_info *info,
c4f035c6
AK		 5004 enum x86_intercept_stage stage)
5005{
2953538e 5006 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5007}
5008
0017f93a 5009static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5010 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5011{
0017f93a 5012 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5013}
5014
dd856efa
AK		 5015static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5016{
5017 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5018}
5019
5020static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5021{
5022 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5023}
5024
801806d9
NA		 5025static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5026{
5027 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5028}
5029
0225fb50 5030static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5031 .read_gpr = emulator_read_gpr,
5032 .write_gpr = emulator_write_gpr,
1871c602 5033 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5034 .write_std = kvm_write_guest_virt_system,
7a036a6f 5035 .read_phys = kvm_read_guest_phys_system,
1871c602 5036 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5037 .read_emulated = emulator_read_emulated,
5038 .write_emulated = emulator_write_emulated,
5039 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5040 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5041 .pio_in_emulated = emulator_pio_in_emulated,
5042 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5043 .get_segment = emulator_get_segment,
5044 .set_segment = emulator_set_segment,
5951c442 5045 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5046 .get_gdt = emulator_get_gdt,
160ce1f1 5047 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5048 .set_gdt = emulator_set_gdt,
5049 .set_idt = emulator_set_idt,
52a46617
GN		 5050 .get_cr = emulator_get_cr,
5051 .set_cr = emulator_set_cr,
9c537244 5052 .cpl = emulator_get_cpl,
35aa5375
GN		 5053 .get_dr = emulator_get_dr,
5054 .set_dr = emulator_set_dr,
64d60670
PB		 5055 .get_smbase = emulator_get_smbase,
5056 .set_smbase = emulator_set_smbase,
717746e3
AK		 5057 .set_msr = emulator_set_msr,
5058 .get_msr = emulator_get_msr,
67f4d428 5059 .check_pmc = emulator_check_pmc,
222d21aa 5060 .read_pmc = emulator_read_pmc,
6c3287f7 5061 .halt = emulator_halt,
bcaf5cc5 5062 .wbinvd = emulator_wbinvd,
d6aa1000 5063 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5064 .get_fpu = emulator_get_fpu,
5065 .put_fpu = emulator_put_fpu,
c4f035c6 5066 .intercept = emulator_intercept,
bdb42f5a 5067 .get_cpuid = emulator_get_cpuid,
801806d9 5068 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5069};
5070
95cb2295
GN		 5071static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5072{
37ccdcbe 5073 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5074 /*
5075 * an sti; sti; sequence only disable interrupts for the first
5076 * instruction. So, if the last instruction, be it emulated or
5077 * not, left the system with the INT_STI flag enabled, it
5078 * means that the last instruction is an sti. We should not
5079 * leave the flag on in this case. The same goes for mov ss
5080 */
37ccdcbe
PB		 5081 if (int_shadow & mask)
5082 mask = 0;
6addfc42 5083 if (unlikely(int_shadow || mask)) {
95cb2295 5084 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5085 if (!mask)
5086 kvm_make_request(KVM_REQ_EVENT, vcpu);
5087 }
95cb2295
GN		 5088}
5089
ef54bcfe 5090static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5091{
5092 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5093 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5094 return kvm_propagate_fault(vcpu, &ctxt->exception);
5095
5096 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5097 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5098 ctxt->exception.error_code);
54b8486f 5099 else
da9cb575 5100 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5101 return false;
54b8486f
GN		 5102}
5103
8ec4722d
MG		 5104static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5105{
adf52235 5106 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5107 int cs_db, cs_l;
5108
8ec4722d
MG		 5109 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5110
adf52235
TY		 5111 ctxt->eflags = kvm_get_rflags(vcpu);
5112 ctxt->eip = kvm_rip_read(vcpu);
5113 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5114 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5115 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5116 cs_db ? X86EMUL_MODE_PROT32 :
5117 X86EMUL_MODE_PROT16;
a584539b 5118 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5119 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5120 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5121 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5122
dd856efa 5123 init_decode_cache(ctxt);
7ae441ea 5124 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5125}
5126
71f9833b 5127int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5128{
9d74191a 5129 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5130 int ret;
5131
5132 init_emulate_ctxt(vcpu);
5133
9dac77fa
AK		 5134 ctxt->op_bytes = 2;
5135 ctxt->ad_bytes = 2;
5136 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5137 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5138
5139 if (ret != X86EMUL_CONTINUE)
5140 return EMULATE_FAIL;
5141
9dac77fa 5142 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5143 kvm_rip_write(vcpu, ctxt->eip);
5144 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5145
5146 if (irq == NMI_VECTOR)
7460fb4a 5147 vcpu->arch.nmi_pending = 0;
63995653
MG		 5148 else
5149 vcpu->arch.interrupt.pending = false;
5150
5151 return EMULATE_DONE;
5152}
5153EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5154
6d77dbfc
GN		 5155static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5156{
fc3a9157
JR		 5157 int r = EMULATE_DONE;
5158
6d77dbfc
GN		 5159 ++vcpu->stat.insn_emulation_fail;
5160 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5161 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5162 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5163 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5164 vcpu->run->internal.ndata = 0;
5165 r = EMULATE_FAIL;
5166 }
6d77dbfc 5167 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5168
5169 return r;
6d77dbfc
GN		 5170}
5171
93c05d3e 5172static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5173 bool write_fault_to_shadow_pgtable,
5174 int emulation_type)
a6f177ef 5175{
95b3cf69 5176 gpa_t gpa = cr2;
ba049e93 5177 kvm_pfn_t pfn;
a6f177ef 5178
991eebf9
GN		 5179 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5180 return false;
5181
95b3cf69
XG		 5182 if (!vcpu->arch.mmu.direct_map) {
5183 /*
5184 * Write permission should be allowed since only
5185 * write access need to be emulated.
5186 */
5187 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5188
95b3cf69
XG		 5189 /*
5190 * If the mapping is invalid in guest, let cpu retry
5191 * it to generate fault.
5192 */
5193 if (gpa == UNMAPPED_GVA)
5194 return true;
5195 }
a6f177ef 5196
8e3d9d06
XG		 5197 /*
5198 * Do not retry the unhandleable instruction if it faults on the
5199 * readonly host memory, otherwise it will goto a infinite loop:
5200 * retry instruction -> write #PF -> emulation fail -> retry
5201 * instruction -> ...
5202 */
5203 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5204
5205 /*
5206 * If the instruction failed on the error pfn, it can not be fixed,
5207 * report the error to userspace.
5208 */
5209 if (is_error_noslot_pfn(pfn))
5210 return false;
5211
5212 kvm_release_pfn_clean(pfn);
5213
5214 /* The instructions are well-emulated on direct mmu. */
5215 if (vcpu->arch.mmu.direct_map) {
5216 unsigned int indirect_shadow_pages;
5217
5218 spin_lock(&vcpu->kvm->mmu_lock);
5219 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5220 spin_unlock(&vcpu->kvm->mmu_lock);
5221
5222 if (indirect_shadow_pages)
5223 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5224
a6f177ef 5225 return true;
8e3d9d06 5226 }
a6f177ef 5227
95b3cf69
XG		 5228 /*
5229 * if emulation was due to access to shadowed page table
5230 * and it failed try to unshadow page and re-enter the
5231 * guest to let CPU execute the instruction.
5232 */
5233 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5234
5235 /*
5236 * If the access faults on its page table, it can not
5237 * be fixed by unprotecting shadow page and it should
5238 * be reported to userspace.
5239 */
5240 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5241}
5242
1cb3f3ae
XG		 5243static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5244 unsigned long cr2, int emulation_type)
5245{
5246 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5247 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5248
5249 last_retry_eip = vcpu->arch.last_retry_eip;
5250 last_retry_addr = vcpu->arch.last_retry_addr;
5251
5252 /*
5253 * If the emulation is caused by #PF and it is non-page_table
5254 * writing instruction, it means the VM-EXIT is caused by shadow
5255 * page protected, we can zap the shadow page and retry this
5256 * instruction directly.
5257 *
5258 * Note: if the guest uses a non-page-table modifying instruction
5259 * on the PDE that points to the instruction, then we will unmap
5260 * the instruction and go to an infinite loop. So, we cache the
5261 * last retried eip and the last fault address, if we meet the eip
5262 * and the address again, we can break out of the potential infinite
5263 * loop.
5264 */
5265 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5266
5267 if (!(emulation_type & EMULTYPE_RETRY))
5268 return false;
5269
5270 if (x86_page_table_writing_insn(ctxt))
5271 return false;
5272
5273 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5274 return false;
5275
5276 vcpu->arch.last_retry_eip = ctxt->eip;
5277 vcpu->arch.last_retry_addr = cr2;
5278
5279 if (!vcpu->arch.mmu.direct_map)
5280 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5281
22368028 5282 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5283
5284 return true;
5285}
5286
716d51ab
GN		 5287static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5288static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5289
64d60670 5290static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5291{
64d60670 5292 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5293 /* This is a good place to trace that we are exiting SMM. */
5294 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5295
64d60670
PB		 5296 if (unlikely(vcpu->arch.smi_pending)) {
5297 kvm_make_request(KVM_REQ_SMI, vcpu);
5298 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5299 } else {
5300 /* Process a latched INIT, if any. */
5301 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5302 }
5303 }
699023e2
PB		 5304
5305 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5306}
5307
5308static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5309{
5310 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5311
a584539b 5312 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5313
5314 if (changed & HF_SMM_MASK)
5315 kvm_smm_changed(vcpu);
a584539b
PB		 5316}
5317
4a1e10d5
PB		 5318static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5319 unsigned long *db)
5320{
5321 u32 dr6 = 0;
5322 int i;
5323 u32 enable, rwlen;
5324
5325 enable = dr7;
5326 rwlen = dr7 >> 16;
5327 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5328 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5329 dr6 |= (1 << i);
5330 return dr6;
5331}
5332
6addfc42 5333static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5334{
5335 struct kvm_run *kvm_run = vcpu->run;
5336
5337 /*
6addfc42
PB		 5338 * rflags is the old, "raw" value of the flags. The new value has
5339 * not been saved yet.
663f4c61
PB		 5340 *
5341 * This is correct even for TF set by the guest, because "the
5342 * processor will not generate this exception after the instruction
5343 * that sets the TF flag".
5344 */
663f4c61
PB		 5345 if (unlikely(rflags & X86_EFLAGS_TF)) {
5346 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5347 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5348 DR6_RTM;
663f4c61
PB		 5349 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5350 kvm_run->debug.arch.exception = DB_VECTOR;
5351 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5352 *r = EMULATE_USER_EXIT;
5353 } else {
5354 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5355 /*
5356 * "Certain debug exceptions may clear bit 0-3. The
5357 * remaining contents of the DR6 register are never
5358 * cleared by the processor".
5359 */
5360 vcpu->arch.dr6 &= ~15;
6f43ed01 5361 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5362 kvm_queue_exception(vcpu, DB_VECTOR);
5363 }
5364 }
5365}
5366
4a1e10d5
PB		 5367static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5368{
4a1e10d5
PB		 5369 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5370 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5371 struct kvm_run *kvm_run = vcpu->run;
5372 unsigned long eip = kvm_get_linear_rip(vcpu);
5373 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5374 vcpu->arch.guest_debug_dr7,
5375 vcpu->arch.eff_db);
5376
5377 if (dr6 != 0) {
6f43ed01 5378 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5379 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5380 kvm_run->debug.arch.exception = DB_VECTOR;
5381 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5382 *r = EMULATE_USER_EXIT;
5383 return true;
5384 }
5385 }
5386
4161a569
NA		 5387 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5388 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5389 unsigned long eip = kvm_get_linear_rip(vcpu);
5390 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5391 vcpu->arch.dr7,
5392 vcpu->arch.db);
5393
5394 if (dr6 != 0) {
5395 vcpu->arch.dr6 &= ~15;
6f43ed01 5396 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5397 kvm_queue_exception(vcpu, DB_VECTOR);
5398 *r = EMULATE_DONE;
5399 return true;
5400 }
5401 }
5402
5403 return false;
5404}
5405
51d8b661
AP		 5406int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5407 unsigned long cr2,
dc25e89e
AP		 5408 int emulation_type,
5409 void *insn,
5410 int insn_len)
bbd9b64e 5411{
95cb2295 5412 int r;
9d74191a 5413 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5414 bool writeback = true;
93c05d3e 5415 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5416
93c05d3e
XG		 5417 /*
5418 * Clear write_fault_to_shadow_pgtable here to ensure it is
5419 * never reused.
5420 */
5421 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5422 kvm_clear_exception_queue(vcpu);
8d7d8102 5423
571008da 5424 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5425 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5426
5427 /*
5428 * We will reenter on the same instruction since
5429 * we do not set complete_userspace_io. This does not
5430 * handle watchpoints yet, those would be handled in
5431 * the emulate_ops.
5432 */
5433 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5434 return r;
5435
9d74191a
TY		 5436 ctxt->interruptibility = 0;
5437 ctxt->have_exception = false;
e0ad0b47 5438 ctxt->exception.vector = -1;
9d74191a 5439 ctxt->perm_ok = false;
bbd9b64e 5440
b51e974f 5441 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5442
9d74191a 5443 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5444
e46479f8 5445 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5446 ++vcpu->stat.insn_emulation;
1d2887e2 5447 if (r != EMULATION_OK) {
4005996e
AK		 5448 if (emulation_type & EMULTYPE_TRAP_UD)
5449 return EMULATE_FAIL;
991eebf9
GN		 5450 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5451 emulation_type))
bbd9b64e 5452 return EMULATE_DONE;
6d77dbfc
GN		 5453 if (emulation_type & EMULTYPE_SKIP)
5454 return EMULATE_FAIL;
5455 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5456 }
5457 }
5458
ba8afb6b 5459 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5460 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5461 if (ctxt->eflags & X86_EFLAGS_RF)
5462 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5463 return EMULATE_DONE;
5464 }
5465
1cb3f3ae
XG		 5466 if (retry_instruction(ctxt, cr2, emulation_type))
5467 return EMULATE_DONE;
5468
7ae441ea 5469 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5470 changes registers values during IO operation */
7ae441ea
GN		 5471 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5472 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5473 emulator_invalidate_register_cache(ctxt);
7ae441ea 5474 }
4d2179e1 5475
5cd21917 5476restart:
9d74191a 5477 r = x86_emulate_insn(ctxt);
bbd9b64e 5478
775fde86
JR		 5479 if (r == EMULATION_INTERCEPTED)
5480 return EMULATE_DONE;
5481
d2ddd1c4 5482 if (r == EMULATION_FAILED) {
991eebf9
GN		 5483 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5484 emulation_type))
c3cd7ffa
GN		 5485 return EMULATE_DONE;
5486
6d77dbfc 5487 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5488 }
5489
9d74191a 5490 if (ctxt->have_exception) {
d2ddd1c4 5491 r = EMULATE_DONE;
ef54bcfe
PB		 5492 if (inject_emulated_exception(vcpu))
5493 return r;
d2ddd1c4 5494 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5495 if (!vcpu->arch.pio.in) {
5496 /* FIXME: return into emulator if single-stepping. */
3457e419 5497 vcpu->arch.pio.count = 0;
0912c977 5498 } else {
7ae441ea 5499 writeback = false;
716d51ab
GN		 5500 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5501 }
ac0a48c3 5502 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5503 } else if (vcpu->mmio_needed) {
5504 if (!vcpu->mmio_is_write)
5505 writeback = false;
ac0a48c3 5506 r = EMULATE_USER_EXIT;
716d51ab 5507 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5508 } else if (r == EMULATION_RESTART)
5cd21917 5509 goto restart;
d2ddd1c4
GN		 5510 else
5511 r = EMULATE_DONE;
f850e2e6 5512
7ae441ea 5513 if (writeback) {
6addfc42 5514 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5515 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5516 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5517 if (vcpu->arch.hflags != ctxt->emul_flags)
5518 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5519 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5520 if (r == EMULATE_DONE)
6addfc42 5521 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5522 if (!ctxt->have_exception ||
5523 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5524 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5525
5526 /*
5527 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5528 * do nothing, and it will be requested again as soon as
5529 * the shadow expires. But we still need to check here,
5530 * because POPF has no interrupt shadow.
5531 */
5532 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5533 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5534 } else
5535 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5536
5537 return r;
de7d789a 5538}
51d8b661 5539EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5540
cf8f70bf 5541int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5542{
cf8f70bf 5543 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5544 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5545 size, port, &val, 1);
cf8f70bf 5546 /* do not return to emulator after return from userspace */
7972995b 5547 vcpu->arch.pio.count = 0;
de7d789a
CO		 5548 return ret;
5549}
cf8f70bf 5550EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5551
8cfdc000
ZA		 5552static void tsc_bad(void *info)
5553{
0a3aee0d 5554 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5555}
5556
5557static void tsc_khz_changed(void *data)
c8076604 5558{
8cfdc000
ZA		 5559 struct cpufreq_freqs *freq = data;
5560 unsigned long khz = 0;
5561
5562 if (data)
5563 khz = freq->new;
5564 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5565 khz = cpufreq_quick_get(raw_smp_processor_id());
5566 if (!khz)
5567 khz = tsc_khz;
0a3aee0d 5568 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5569}
5570
c8076604
GH		 5571static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5572 void *data)
5573{
5574 struct cpufreq_freqs *freq = data;
5575 struct kvm *kvm;
5576 struct kvm_vcpu *vcpu;
5577 int i, send_ipi = 0;
5578
8cfdc000
ZA		 5579 /*
5580 * We allow guests to temporarily run on slowing clocks,
5581 * provided we notify them after, or to run on accelerating
5582 * clocks, provided we notify them before. Thus time never
5583 * goes backwards.
5584 *
5585 * However, we have a problem. We can't atomically update
5586 * the frequency of a given CPU from this function; it is
5587 * merely a notifier, which can be called from any CPU.
5588 * Changing the TSC frequency at arbitrary points in time
5589 * requires a recomputation of local variables related to
5590 * the TSC for each VCPU. We must flag these local variables
5591 * to be updated and be sure the update takes place with the
5592 * new frequency before any guests proceed.
5593 *
5594 * Unfortunately, the combination of hotplug CPU and frequency
5595 * change creates an intractable locking scenario; the order
5596 * of when these callouts happen is undefined with respect to
5597 * CPU hotplug, and they can race with each other. As such,
5598 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5599 * undefined; you can actually have a CPU frequency change take
5600 * place in between the computation of X and the setting of the
5601 * variable. To protect against this problem, all updates of
5602 * the per_cpu tsc_khz variable are done in an interrupt
5603 * protected IPI, and all callers wishing to update the value
5604 * must wait for a synchronous IPI to complete (which is trivial
5605 * if the caller is on the CPU already). This establishes the
5606 * necessary total order on variable updates.
5607 *
5608 * Note that because a guest time update may take place
5609 * anytime after the setting of the VCPU's request bit, the
5610 * correct TSC value must be set before the request. However,
5611 * to ensure the update actually makes it to any guest which
5612 * starts running in hardware virtualization between the set
5613 * and the acquisition of the spinlock, we must also ping the
5614 * CPU after setting the request bit.
5615 *
5616 */
5617
c8076604
GH		 5618 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5619 return 0;
5620 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5621 return 0;
8cfdc000
ZA		 5622
5623 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5624
2f303b74 5625 spin_lock(&kvm_lock);
c8076604 5626 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5627 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5628 if (vcpu->cpu != freq->cpu)
5629 continue;
c285545f 5630 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5631 if (vcpu->cpu != smp_processor_id())
8cfdc000 5632 send_ipi = 1;
c8076604
GH		 5633 }
5634 }
2f303b74 5635 spin_unlock(&kvm_lock);
c8076604
GH		 5636
5637 if (freq->old < freq->new && send_ipi) {
5638 /*
5639 * We upscale the frequency. Must make the guest
5640 * doesn't see old kvmclock values while running with
5641 * the new frequency, otherwise we risk the guest sees
5642 * time go backwards.
5643 *
5644 * In case we update the frequency for another cpu
5645 * (which might be in guest context) send an interrupt
5646 * to kick the cpu out of guest context. Next time
5647 * guest context is entered kvmclock will be updated,
5648 * so the guest will not see stale values.
5649 */
8cfdc000 5650 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5651 }
5652 return 0;
5653}
5654
5655static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5656 .notifier_call = kvmclock_cpufreq_notifier
5657};
5658
5659static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5660 unsigned long action, void *hcpu)
5661{
5662 unsigned int cpu = (unsigned long)hcpu;
5663
5664 switch (action) {
5665 case CPU_ONLINE:
5666 case CPU_DOWN_FAILED:
5667 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5668 break;
5669 case CPU_DOWN_PREPARE:
5670 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5671 break;
5672 }
5673 return NOTIFY_OK;
5674}
5675
5676static struct notifier_block kvmclock_cpu_notifier_block = {
5677 .notifier_call = kvmclock_cpu_notifier,
5678 .priority = -INT_MAX
c8076604
GH		 5679};
5680
b820cc0c
ZA		 5681static void kvm_timer_init(void)
5682{
5683 int cpu;
5684
c285545f 5685 max_tsc_khz = tsc_khz;
460dd42e
SB		 5686
5687 cpu_notifier_register_begin();
b820cc0c 5688 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5689#ifdef CONFIG_CPU_FREQ
5690 struct cpufreq_policy policy;
5691 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5692 cpu = get_cpu();
5693 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5694 if (policy.cpuinfo.max_freq)
5695 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5696 put_cpu();
c285545f 5697#endif
b820cc0c
ZA		 5698 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5699 CPUFREQ_TRANSITION_NOTIFIER);
5700 }
c285545f 5701 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5702 for_each_online_cpu(cpu)
5703 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5704
5705 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5706 cpu_notifier_register_done();
5707
b820cc0c
ZA		 5708}
5709
ff9d07a0
ZY		 5710static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5711
f5132b01 5712int kvm_is_in_guest(void)
ff9d07a0 5713{
086c9855 5714 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5715}
5716
5717static int kvm_is_user_mode(void)
5718{
5719 int user_mode = 3;
dcf46b94 5720
086c9855
AS		 5721 if (__this_cpu_read(current_vcpu))
5722 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5723
ff9d07a0
ZY		 5724 return user_mode != 0;
5725}
5726
5727static unsigned long kvm_get_guest_ip(void)
5728{
5729 unsigned long ip = 0;
dcf46b94 5730
086c9855
AS		 5731 if (__this_cpu_read(current_vcpu))
5732 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5733
ff9d07a0
ZY		 5734 return ip;
5735}
5736
5737static struct perf_guest_info_callbacks kvm_guest_cbs = {
5738 .is_in_guest = kvm_is_in_guest,
5739 .is_user_mode = kvm_is_user_mode,
5740 .get_guest_ip = kvm_get_guest_ip,
5741};
5742
5743void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5744{
086c9855 5745 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5746}
5747EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5748
5749void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5750{
086c9855 5751 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5752}
5753EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5754
ce88decf
XG		 5755static void kvm_set_mmio_spte_mask(void)
5756{
5757 u64 mask;
5758 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5759
5760 /*
5761 * Set the reserved bits and the present bit of an paging-structure
5762 * entry to generate page fault with PFER.RSV = 1.
5763 */
885032b9 5764 /* Mask the reserved physical address bits. */
d1431483 5765 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5766
5767 /* Bit 62 is always reserved for 32bit host. */
5768 mask |= 0x3ull << 62;
5769
5770 /* Set the present bit. */
ce88decf
XG		 5771 mask |= 1ull;
5772
5773#ifdef CONFIG_X86_64
5774 /*
5775 * If reserved bit is not supported, clear the present bit to disable
5776 * mmio page fault.
5777 */
5778 if (maxphyaddr == 52)
5779 mask &= ~1ull;
5780#endif
5781
5782 kvm_mmu_set_mmio_spte_mask(mask);
5783}
5784
16e8d74d
MT		 5785#ifdef CONFIG_X86_64
5786static void pvclock_gtod_update_fn(struct work_struct *work)
5787{
d828199e
MT		 5788 struct kvm *kvm;
5789
5790 struct kvm_vcpu *vcpu;
5791 int i;
5792
2f303b74 5793 spin_lock(&kvm_lock);
d828199e
MT		 5794 list_for_each_entry(kvm, &vm_list, vm_list)
5795 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5796 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5797 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5798 spin_unlock(&kvm_lock);
16e8d74d
MT		 5799}
5800
5801static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5802
5803/*
5804 * Notification about pvclock gtod data update.
5805 */
5806static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5807 void *priv)
5808{
5809 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5810 struct timekeeper *tk = priv;
5811
5812 update_pvclock_gtod(tk);
5813
5814 /* disable master clock if host does not trust, or does not
5815 * use, TSC clocksource
5816 */
5817 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5818 atomic_read(&kvm_guest_has_master_clock) != 0)
5819 queue_work(system_long_wq, &pvclock_gtod_work);
5820
5821 return 0;
5822}
5823
5824static struct notifier_block pvclock_gtod_notifier = {
5825 .notifier_call = pvclock_gtod_notify,
5826};
5827#endif
5828
f8c16bba 5829int kvm_arch_init(void *opaque)
043405e1 5830{
b820cc0c 5831 int r;
6b61edf7 5832 struct kvm_x86_ops *ops = opaque;
f8c16bba 5833
f8c16bba
ZX		 5834 if (kvm_x86_ops) {
5835 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5836 r = -EEXIST;
5837 goto out;
f8c16bba
ZX		 5838 }
5839
5840 if (!ops->cpu_has_kvm_support()) {
5841 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5842 r = -EOPNOTSUPP;
5843 goto out;
f8c16bba
ZX		 5844 }
5845 if (ops->disabled_by_bios()) {
5846 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5847 r = -EOPNOTSUPP;
5848 goto out;
f8c16bba
ZX		 5849 }
5850
013f6a5d
MT		 5851 r = -ENOMEM;
5852 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5853 if (!shared_msrs) {
5854 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5855 goto out;
5856 }
5857
97db56ce
AK		 5858 r = kvm_mmu_module_init();
5859 if (r)
013f6a5d 5860 goto out_free_percpu;
97db56ce 5861
ce88decf 5862 kvm_set_mmio_spte_mask();
97db56ce 5863
f8c16bba 5864 kvm_x86_ops = ops;
920c8377 5865
7b52345e 5866 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5867 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5868
b820cc0c 5869 kvm_timer_init();
c8076604 5870
ff9d07a0
ZY		 5871 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5872
d366bf7e 5873 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 5874 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5875
c5cc421b 5876 kvm_lapic_init();
16e8d74d
MT		 5877#ifdef CONFIG_X86_64
5878 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5879#endif
5880
f8c16bba 5881 return 0;
56c6d28a 5882
013f6a5d
MT		 5883out_free_percpu:
5884 free_percpu(shared_msrs);
56c6d28a 5885out:
56c6d28a 5886 return r;
043405e1 5887}
8776e519 5888
f8c16bba
ZX		 5889void kvm_arch_exit(void)
5890{
ff9d07a0
ZY		 5891 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5892
888d256e
JK		 5893 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5894 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5895 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5896 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5897#ifdef CONFIG_X86_64
5898 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5899#endif
f8c16bba 5900 kvm_x86_ops = NULL;
56c6d28a 5901 kvm_mmu_module_exit();
013f6a5d 5902 free_percpu(shared_msrs);
56c6d28a 5903}
f8c16bba 5904
5cb56059 5905int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5906{
5907 ++vcpu->stat.halt_exits;
35754c98 5908 if (lapic_in_kernel(vcpu)) {
a4535290 5909 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5910 return 1;
5911 } else {
5912 vcpu->run->exit_reason = KVM_EXIT_HLT;
5913 return 0;
5914 }
5915}
5cb56059
JS		 5916EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5917
5918int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5919{
5920 kvm_x86_ops->skip_emulated_instruction(vcpu);
5921 return kvm_vcpu_halt(vcpu);
5922}
8776e519
HB		 5923EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5924
6aef266c
SV		 5925/*
5926 * kvm_pv_kick_cpu_op: Kick a vcpu.
5927 *
5928 * @apicid - apicid of vcpu to be kicked.
5929 */
5930static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5931{
24d2166b 5932 struct kvm_lapic_irq lapic_irq;
6aef266c 5933
24d2166b
R		 5934 lapic_irq.shorthand = 0;
5935 lapic_irq.dest_mode = 0;
5936 lapic_irq.dest_id = apicid;
93bbf0b8 5937 lapic_irq.msi_redir_hint = false;
6aef266c 5938
24d2166b 5939 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5940 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5941}
5942
d62caabb
AS		 5943void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5944{
5945 vcpu->arch.apicv_active = false;
5946 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5947}
5948
8776e519
HB		 5949int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5950{
5951 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5952 int op_64_bit, r = 1;
8776e519 5953
5cb56059
JS		 5954 kvm_x86_ops->skip_emulated_instruction(vcpu);
5955
55cd8e5a
GN		 5956 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5957 return kvm_hv_hypercall(vcpu);
5958
5fdbf976
MT		 5959 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5960 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5961 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5962 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5963 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5964
229456fc 5965 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5966
a449c7aa
NA		 5967 op_64_bit = is_64_bit_mode(vcpu);
5968 if (!op_64_bit) {
8776e519
HB		 5969 nr &= 0xFFFFFFFF;
5970 a0 &= 0xFFFFFFFF;
5971 a1 &= 0xFFFFFFFF;
5972 a2 &= 0xFFFFFFFF;
5973 a3 &= 0xFFFFFFFF;
5974 }
5975
07708c4a
JK		 5976 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5977 ret = -KVM_EPERM;
5978 goto out;
5979 }
5980
8776e519 5981 switch (nr) {
b93463aa
AK		 5982 case KVM_HC_VAPIC_POLL_IRQ:
5983 ret = 0;
5984 break;
6aef266c
SV		 5985 case KVM_HC_KICK_CPU:
5986 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5987 ret = 0;
5988 break;
8776e519
HB		 5989 default:
5990 ret = -KVM_ENOSYS;
5991 break;
5992 }
07708c4a 5993out:
a449c7aa
NA		 5994 if (!op_64_bit)
5995 ret = (u32)ret;
5fdbf976 5996 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5997 ++vcpu->stat.hypercalls;
2f333bcb 5998 return r;
8776e519
HB		 5999}
6000EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6001
b6785def 6002static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6003{
d6aa1000 6004 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6005 char instruction[3];
5fdbf976 6006 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6007
8776e519 6008 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6009
9d74191a 6010 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6011}
6012
851ba692 6013static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6014{
782d422b
MG		 6015 return vcpu->run->request_interrupt_window &&
6016 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6017}
6018
851ba692 6019static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6020{
851ba692
AK		 6021 struct kvm_run *kvm_run = vcpu->run;
6022
91586a3b 6023 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6024 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6025 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6026 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6027 kvm_run->ready_for_interrupt_injection =
6028 pic_in_kernel(vcpu->kvm) ||
782d422b 6029 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6030}
6031
95ba8273
GN		 6032static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6033{
6034 int max_irr, tpr;
6035
6036 if (!kvm_x86_ops->update_cr8_intercept)
6037 return;
6038
bce87cce 6039 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6040 return;
6041
d62caabb
AS		 6042 if (vcpu->arch.apicv_active)
6043 return;
6044
8db3baa2
GN		 6045 if (!vcpu->arch.apic->vapic_addr)
6046 max_irr = kvm_lapic_find_highest_irr(vcpu);
6047 else
6048 max_irr = -1;
95ba8273
GN		 6049
6050 if (max_irr != -1)
6051 max_irr >>= 4;
6052
6053 tpr = kvm_lapic_get_cr8(vcpu);
6054
6055 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6056}
6057
b6b8a145 6058static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6059{
b6b8a145
JK		 6060 int r;
6061
95ba8273 6062 /* try to reinject previous events if any */
b59bb7bd 6063 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6064 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6065 vcpu->arch.exception.has_error_code,
6066 vcpu->arch.exception.error_code);
d6e8c854
NA		 6067
6068 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6069 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6070 X86_EFLAGS_RF);
6071
6bdf0662
NA		 6072 if (vcpu->arch.exception.nr == DB_VECTOR &&
6073 (vcpu->arch.dr7 & DR7_GD)) {
6074 vcpu->arch.dr7 &= ~DR7_GD;
6075 kvm_update_dr7(vcpu);
6076 }
6077
b59bb7bd
GN		 6078 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6079 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6080 vcpu->arch.exception.error_code,
6081 vcpu->arch.exception.reinject);
b6b8a145 6082 return 0;
b59bb7bd
GN		 6083 }
6084
95ba8273
GN		 6085 if (vcpu->arch.nmi_injected) {
6086 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6087 return 0;
95ba8273
GN		 6088 }
6089
6090 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6091 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6092 return 0;
6093 }
6094
6095 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6096 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6097 if (r != 0)
6098 return r;
95ba8273
GN		 6099 }
6100
6101 /* try to inject new event if pending */
321c5658
YS		 6102 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6103 --vcpu->arch.nmi_pending;
6104 vcpu->arch.nmi_injected = true;
6105 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6106 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6107 /*
6108 * Because interrupts can be injected asynchronously, we are
6109 * calling check_nested_events again here to avoid a race condition.
6110 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6111 * proposal and current concerns. Perhaps we should be setting
6112 * KVM_REQ_EVENT only on certain events and not unconditionally?
6113 */
6114 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6115 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6116 if (r != 0)
6117 return r;
6118 }
95ba8273 6119 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6120 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6121 false);
6122 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6123 }
6124 }
b6b8a145 6125 return 0;
95ba8273
GN		 6126}
6127
7460fb4a
AK		 6128static void process_nmi(struct kvm_vcpu *vcpu)
6129{
6130 unsigned limit = 2;
6131
6132 /*
6133 * x86 is limited to one NMI running, and one NMI pending after it.
6134 * If an NMI is already in progress, limit further NMIs to just one.
6135 * Otherwise, allow two (and we'll inject the first one immediately).
6136 */
6137 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6138 limit = 1;
6139
6140 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6141 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6142 kvm_make_request(KVM_REQ_EVENT, vcpu);
6143}
6144
660a5d51
PB		 6145#define put_smstate(type, buf, offset, val) \
6146 *(type *)((buf) + (offset) - 0x7e00) = val
6147
6148static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6149{
6150 u32 flags = 0;
6151 flags |= seg->g << 23;
6152 flags |= seg->db << 22;
6153 flags |= seg->l << 21;
6154 flags |= seg->avl << 20;
6155 flags |= seg->present << 15;
6156 flags |= seg->dpl << 13;
6157 flags |= seg->s << 12;
6158 flags |= seg->type << 8;
6159 return flags;
6160}
6161
6162static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6163{
6164 struct kvm_segment seg;
6165 int offset;
6166
6167 kvm_get_segment(vcpu, &seg, n);
6168 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6169
6170 if (n < 3)
6171 offset = 0x7f84 + n * 12;
6172 else
6173 offset = 0x7f2c + (n - 3) * 12;
6174
6175 put_smstate(u32, buf, offset + 8, seg.base);
6176 put_smstate(u32, buf, offset + 4, seg.limit);
6177 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6178}
6179
efbb288a 6180#ifdef CONFIG_X86_64
660a5d51
PB		 6181static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6182{
6183 struct kvm_segment seg;
6184 int offset;
6185 u16 flags;
6186
6187 kvm_get_segment(vcpu, &seg, n);
6188 offset = 0x7e00 + n * 16;
6189
6190 flags = process_smi_get_segment_flags(&seg) >> 8;
6191 put_smstate(u16, buf, offset, seg.selector);
6192 put_smstate(u16, buf, offset + 2, flags);
6193 put_smstate(u32, buf, offset + 4, seg.limit);
6194 put_smstate(u64, buf, offset + 8, seg.base);
6195}
efbb288a 6196#endif
660a5d51
PB		 6197
6198static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6199{
6200 struct desc_ptr dt;
6201 struct kvm_segment seg;
6202 unsigned long val;
6203 int i;
6204
6205 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6206 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6207 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6208 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6209
6210 for (i = 0; i < 8; i++)
6211 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6212
6213 kvm_get_dr(vcpu, 6, &val);
6214 put_smstate(u32, buf, 0x7fcc, (u32)val);
6215 kvm_get_dr(vcpu, 7, &val);
6216 put_smstate(u32, buf, 0x7fc8, (u32)val);
6217
6218 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6219 put_smstate(u32, buf, 0x7fc4, seg.selector);
6220 put_smstate(u32, buf, 0x7f64, seg.base);
6221 put_smstate(u32, buf, 0x7f60, seg.limit);
6222 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6223
6224 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6225 put_smstate(u32, buf, 0x7fc0, seg.selector);
6226 put_smstate(u32, buf, 0x7f80, seg.base);
6227 put_smstate(u32, buf, 0x7f7c, seg.limit);
6228 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6229
6230 kvm_x86_ops->get_gdt(vcpu, &dt);
6231 put_smstate(u32, buf, 0x7f74, dt.address);
6232 put_smstate(u32, buf, 0x7f70, dt.size);
6233
6234 kvm_x86_ops->get_idt(vcpu, &dt);
6235 put_smstate(u32, buf, 0x7f58, dt.address);
6236 put_smstate(u32, buf, 0x7f54, dt.size);
6237
6238 for (i = 0; i < 6; i++)
6239 process_smi_save_seg_32(vcpu, buf, i);
6240
6241 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6242
6243 /* revision id */
6244 put_smstate(u32, buf, 0x7efc, 0x00020000);
6245 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6246}
6247
6248static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6249{
6250#ifdef CONFIG_X86_64
6251 struct desc_ptr dt;
6252 struct kvm_segment seg;
6253 unsigned long val;
6254 int i;
6255
6256 for (i = 0; i < 16; i++)
6257 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6258
6259 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6260 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6261
6262 kvm_get_dr(vcpu, 6, &val);
6263 put_smstate(u64, buf, 0x7f68, val);
6264 kvm_get_dr(vcpu, 7, &val);
6265 put_smstate(u64, buf, 0x7f60, val);
6266
6267 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6268 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6269 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6270
6271 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6272
6273 /* revision id */
6274 put_smstate(u32, buf, 0x7efc, 0x00020064);
6275
6276 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6277
6278 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6279 put_smstate(u16, buf, 0x7e90, seg.selector);
6280 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6281 put_smstate(u32, buf, 0x7e94, seg.limit);
6282 put_smstate(u64, buf, 0x7e98, seg.base);
6283
6284 kvm_x86_ops->get_idt(vcpu, &dt);
6285 put_smstate(u32, buf, 0x7e84, dt.size);
6286 put_smstate(u64, buf, 0x7e88, dt.address);
6287
6288 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6289 put_smstate(u16, buf, 0x7e70, seg.selector);
6290 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6291 put_smstate(u32, buf, 0x7e74, seg.limit);
6292 put_smstate(u64, buf, 0x7e78, seg.base);
6293
6294 kvm_x86_ops->get_gdt(vcpu, &dt);
6295 put_smstate(u32, buf, 0x7e64, dt.size);
6296 put_smstate(u64, buf, 0x7e68, dt.address);
6297
6298 for (i = 0; i < 6; i++)
6299 process_smi_save_seg_64(vcpu, buf, i);
6300#else
6301 WARN_ON_ONCE(1);
6302#endif
6303}
6304
64d60670
PB		 6305static void process_smi(struct kvm_vcpu *vcpu)
6306{
660a5d51 6307 struct kvm_segment cs, ds;
18c3626e 6308 struct desc_ptr dt;
660a5d51
PB		 6309 char buf[512];
6310 u32 cr0;
6311
64d60670
PB		 6312 if (is_smm(vcpu)) {
6313 vcpu->arch.smi_pending = true;
6314 return;
6315 }
6316
660a5d51
PB		 6317 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6318 vcpu->arch.hflags |= HF_SMM_MASK;
6319 memset(buf, 0, 512);
6320 if (guest_cpuid_has_longmode(vcpu))
6321 process_smi_save_state_64(vcpu, buf);
6322 else
6323 process_smi_save_state_32(vcpu, buf);
6324
54bf36aa 6325 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6326
6327 if (kvm_x86_ops->get_nmi_mask(vcpu))
6328 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6329 else
6330 kvm_x86_ops->set_nmi_mask(vcpu, true);
6331
6332 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6333 kvm_rip_write(vcpu, 0x8000);
6334
6335 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6336 kvm_x86_ops->set_cr0(vcpu, cr0);
6337 vcpu->arch.cr0 = cr0;
6338
6339 kvm_x86_ops->set_cr4(vcpu, 0);
6340
18c3626e
PB		 6341 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6342 dt.address = dt.size = 0;
6343 kvm_x86_ops->set_idt(vcpu, &dt);
6344
660a5d51
PB		 6345 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6346
6347 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6348 cs.base = vcpu->arch.smbase;
6349
6350 ds.selector = 0;
6351 ds.base = 0;
6352
6353 cs.limit = ds.limit = 0xffffffff;
6354 cs.type = ds.type = 0x3;
6355 cs.dpl = ds.dpl = 0;
6356 cs.db = ds.db = 0;
6357 cs.s = ds.s = 1;
6358 cs.l = ds.l = 0;
6359 cs.g = ds.g = 1;
6360 cs.avl = ds.avl = 0;
6361 cs.present = ds.present = 1;
6362 cs.unusable = ds.unusable = 0;
6363 cs.padding = ds.padding = 0;
6364
6365 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6366 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6367 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6368 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6369 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6370 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6371
6372 if (guest_cpuid_has_longmode(vcpu))
6373 kvm_x86_ops->set_efer(vcpu, 0);
6374
6375 kvm_update_cpuid(vcpu);
6376 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6377}
6378
2860c4b1
PB		 6379void kvm_make_scan_ioapic_request(struct kvm *kvm)
6380{
6381 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6382}
6383
3d81bc7e 6384static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6385{
5c919412
AS		 6386 u64 eoi_exit_bitmap[4];
6387
3d81bc7e
YZ		 6388 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6389 return;
c7c9c56c 6390
6308630b 6391 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6392
b053b2ae 6393 if (irqchip_split(vcpu->kvm))
6308630b 6394 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6395 else {
d62caabb
AS		 6396 if (vcpu->arch.apicv_active)
6397 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6398 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6399 }
5c919412
AS		 6400 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6401 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6402 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6403}
6404
a70656b6
RK		 6405static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6406{
6407 ++vcpu->stat.tlb_flush;
6408 kvm_x86_ops->tlb_flush(vcpu);
6409}
6410
4256f43f
TC		 6411void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6412{
c24ae0dc
TC		 6413 struct page *page = NULL;
6414
35754c98 6415 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6416 return;
6417
4256f43f
TC		 6418 if (!kvm_x86_ops->set_apic_access_page_addr)
6419 return;
6420
c24ae0dc 6421 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6422 if (is_error_page(page))
6423 return;
c24ae0dc
TC		 6424 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6425
6426 /*
6427 * Do not pin apic access page in memory, the MMU notifier
6428 * will call us again if it is migrated or swapped out.
6429 */
6430 put_page(page);
4256f43f
TC		 6431}
6432EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6433
fe71557a
TC		 6434void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6435 unsigned long address)
6436{
c24ae0dc
TC		 6437 /*
6438 * The physical address of apic access page is stored in the VMCS.
6439 * Update it when it becomes invalid.
6440 */
6441 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6442 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6443}
6444
9357d939 6445/*
362c698f 6446 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6447 * exiting to the userspace. Otherwise, the value will be returned to the
6448 * userspace.
6449 */
851ba692 6450static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6451{
6452 int r;
62a193ed
MG		 6453 bool req_int_win =
6454 dm_request_for_irq_injection(vcpu) &&
6455 kvm_cpu_accept_dm_intr(vcpu);
6456
730dca42 6457 bool req_immediate_exit = false;
b6c7a5dc 6458
3e007509 6459 if (vcpu->requests) {
a8eeb04a 6460 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6461 kvm_mmu_unload(vcpu);
a8eeb04a 6462 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6463 __kvm_migrate_timers(vcpu);
d828199e
MT		 6464 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6465 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6466 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6467 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6468 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6469 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6470 if (unlikely(r))
6471 goto out;
6472 }
a8eeb04a 6473 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6474 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6475 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6476 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6477 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6478 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6479 r = 0;
6480 goto out;
6481 }
a8eeb04a 6482 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6483 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6484 r = 0;
6485 goto out;
6486 }
a8eeb04a 6487 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6488 vcpu->fpu_active = 0;
6489 kvm_x86_ops->fpu_deactivate(vcpu);
6490 }
af585b92
GN		 6491 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6492 /* Page is swapped out. Do synthetic halt */
6493 vcpu->arch.apf.halted = true;
6494 r = 1;
6495 goto out;
6496 }
c9aaa895
GC		 6497 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6498 record_steal_time(vcpu);
64d60670
PB		 6499 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6500 process_smi(vcpu);
7460fb4a
AK		 6501 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6502 process_nmi(vcpu);
f5132b01 6503 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6504 kvm_pmu_handle_event(vcpu);
f5132b01 6505 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6506 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6507 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6508 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6509 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6510 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6511 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6512 vcpu->run->eoi.vector =
6513 vcpu->arch.pending_ioapic_eoi;
6514 r = 0;
6515 goto out;
6516 }
6517 }
3d81bc7e
YZ		 6518 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6519 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6520 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6521 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6522 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6523 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6524 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6525 r = 0;
6526 goto out;
6527 }
e516cebb
AS		 6528 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6529 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6530 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6531 r = 0;
6532 goto out;
6533 }
db397571
AS		 6534 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6535 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6536 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6537 r = 0;
6538 goto out;
6539 }
f3b138c5
AS		 6540
6541 /*
6542 * KVM_REQ_HV_STIMER has to be processed after
6543 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6544 * depend on the guest clock being up-to-date
6545 */
1f4b34f8
AS		 6546 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6547 kvm_hv_process_stimers(vcpu);
2f52d58c 6548 }
b93463aa 6549
bf9f6ac8
FW		 6550 /*
6551 * KVM_REQ_EVENT is not set when posted interrupts are set by
6552 * VT-d hardware, so we have to update RVI unconditionally.
6553 */
6554 if (kvm_lapic_enabled(vcpu)) {
6555 /*
6556 * Update architecture specific hints for APIC
6557 * virtual interrupt delivery.
6558 */
d62caabb 6559 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6560 kvm_x86_ops->hwapic_irr_update(vcpu,
6561 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6562 }
b93463aa 6563
b463a6f7 6564 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6565 kvm_apic_accept_events(vcpu);
6566 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6567 r = 1;
6568 goto out;
6569 }
6570
b6b8a145
JK		 6571 if (inject_pending_event(vcpu, req_int_win) != 0)
6572 req_immediate_exit = true;
b463a6f7 6573 /* enable NMI/IRQ window open exits if needed */
321c5658
YS		 6574 else {
6575 if (vcpu->arch.nmi_pending)
6576 kvm_x86_ops->enable_nmi_window(vcpu);
6577 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6578 kvm_x86_ops->enable_irq_window(vcpu);
6579 }
b463a6f7
AK		 6580
6581 if (kvm_lapic_enabled(vcpu)) {
6582 update_cr8_intercept(vcpu);
6583 kvm_lapic_sync_to_vapic(vcpu);
6584 }
6585 }
6586
d8368af8
AK		 6587 r = kvm_mmu_reload(vcpu);
6588 if (unlikely(r)) {
d905c069 6589 goto cancel_injection;
d8368af8
AK		 6590 }
6591
b6c7a5dc
HB		 6592 preempt_disable();
6593
6594 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6595 if (vcpu->fpu_active)
6596 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6597 vcpu->mode = IN_GUEST_MODE;
6598
01b71917
MT		 6599 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6600
0f127d12
LT		 6601 /*
6602 * We should set ->mode before check ->requests,
6603 * Please see the comment in kvm_make_all_cpus_request.
6604 * This also orders the write to mode from any reads
6605 * to the page tables done while the VCPU is running.
6606 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6607 */
01b71917 6608 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6609
d94e1dc9 6610 local_irq_disable();
32f88400 6611
6b7e2d09 6612 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6613 || need_resched() || signal_pending(current)) {
6b7e2d09 6614 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6615 smp_wmb();
6c142801
AK		 6616 local_irq_enable();
6617 preempt_enable();
01b71917 6618 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6619 r = 1;
d905c069 6620 goto cancel_injection;
6c142801
AK		 6621 }
6622
fc5b7f3b
DM		 6623 kvm_load_guest_xcr0(vcpu);
6624
d6185f20
NHE		 6625 if (req_immediate_exit)
6626 smp_send_reschedule(vcpu->cpu);
6627
8b89fe1f
PB		 6628 trace_kvm_entry(vcpu->vcpu_id);
6629 wait_lapic_expire(vcpu);
ccf73aaf 6630 __kvm_guest_enter();
b6c7a5dc 6631
42dbaa5a 6632 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6633 set_debugreg(0, 7);
6634 set_debugreg(vcpu->arch.eff_db[0], 0);
6635 set_debugreg(vcpu->arch.eff_db[1], 1);
6636 set_debugreg(vcpu->arch.eff_db[2], 2);
6637 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6638 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6639 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6640 }
b6c7a5dc 6641
851ba692 6642 kvm_x86_ops->run(vcpu);
b6c7a5dc 6643
c77fb5fe
PB		 6644 /*
6645 * Do this here before restoring debug registers on the host. And
6646 * since we do this before handling the vmexit, a DR access vmexit
6647 * can (a) read the correct value of the debug registers, (b) set
6648 * KVM_DEBUGREG_WONT_EXIT again.
6649 */
6650 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6651 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6652 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6653 kvm_update_dr0123(vcpu);
6654 kvm_update_dr6(vcpu);
6655 kvm_update_dr7(vcpu);
6656 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6657 }
6658
24f1e32c
FW		 6659 /*
6660 * If the guest has used debug registers, at least dr7
6661 * will be disabled while returning to the host.
6662 * If we don't have active breakpoints in the host, we don't
6663 * care about the messed up debug address registers. But if
6664 * we have some of them active, restore the old state.
6665 */
59d8eb53 6666 if (hw_breakpoint_active())
24f1e32c 6667 hw_breakpoint_restore();
42dbaa5a 6668
4ba76538 6669 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6670
6b7e2d09 6671 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6672 smp_wmb();
a547c6db 6673
fc5b7f3b
DM		 6674 kvm_put_guest_xcr0(vcpu);
6675
a547c6db
YZ		 6676 /* Interrupt is enabled by handle_external_intr() */
6677 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6678
6679 ++vcpu->stat.exits;
6680
6681 /*
6682 * We must have an instruction between local_irq_enable() and
6683 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6684 * the interrupt shadow. The stat.exits increment will do nicely.
6685 * But we need to prevent reordering, hence this barrier():
6686 */
6687 barrier();
6688
6689 kvm_guest_exit();
6690
6691 preempt_enable();
6692
f656ce01 6693 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6694
b6c7a5dc
HB		 6695 /*
6696 * Profile KVM exit RIPs:
6697 */
6698 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6699 unsigned long rip = kvm_rip_read(vcpu);
6700 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6701 }
6702
cc578287
ZA		 6703 if (unlikely(vcpu->arch.tsc_always_catchup))
6704 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6705
5cfb1d5a
MT		 6706 if (vcpu->arch.apic_attention)
6707 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6708
851ba692 6709 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6710 return r;
6711
6712cancel_injection:
6713 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6714 if (unlikely(vcpu->arch.apic_attention))
6715 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6716out:
6717 return r;
6718}
b6c7a5dc 6719
362c698f
PB		 6720static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6721{
bf9f6ac8
FW		 6722 if (!kvm_arch_vcpu_runnable(vcpu) &&
6723 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6724 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6725 kvm_vcpu_block(vcpu);
6726 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6727
6728 if (kvm_x86_ops->post_block)
6729 kvm_x86_ops->post_block(vcpu);
6730
9c8fd1ba
PB		 6731 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6732 return 1;
6733 }
362c698f
PB		 6734
6735 kvm_apic_accept_events(vcpu);
6736 switch(vcpu->arch.mp_state) {
6737 case KVM_MP_STATE_HALTED:
6738 vcpu->arch.pv.pv_unhalted = false;
6739 vcpu->arch.mp_state =
6740 KVM_MP_STATE_RUNNABLE;
6741 case KVM_MP_STATE_RUNNABLE:
6742 vcpu->arch.apf.halted = false;
6743 break;
6744 case KVM_MP_STATE_INIT_RECEIVED:
6745 break;
6746 default:
6747 return -EINTR;
6748 break;
6749 }
6750 return 1;
6751}
09cec754 6752
5d9bc648
PB		 6753static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6754{
6755 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6756 !vcpu->arch.apf.halted);
6757}
6758
362c698f 6759static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6760{
6761 int r;
f656ce01 6762 struct kvm *kvm = vcpu->kvm;
d7690175 6763
f656ce01 6764 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6765
362c698f 6766 for (;;) {
58f800d5 6767 if (kvm_vcpu_running(vcpu)) {
851ba692 6768 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6769 } else {
362c698f 6770 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6771 }
6772
09cec754
GN		 6773 if (r <= 0)
6774 break;
6775
6776 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6777 if (kvm_cpu_has_pending_timer(vcpu))
6778 kvm_inject_pending_timer_irqs(vcpu);
6779
782d422b
MG		 6780 if (dm_request_for_irq_injection(vcpu) &&
6781 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6782 r = 0;
6783 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6784 ++vcpu->stat.request_irq_exits;
362c698f 6785 break;
09cec754 6786 }
af585b92
GN		 6787
6788 kvm_check_async_pf_completion(vcpu);
6789
09cec754
GN		 6790 if (signal_pending(current)) {
6791 r = -EINTR;
851ba692 6792 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6793 ++vcpu->stat.signal_exits;
362c698f 6794 break;
09cec754
GN		 6795 }
6796 if (need_resched()) {
f656ce01 6797 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6798 cond_resched();
f656ce01 6799 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6800 }
b6c7a5dc
HB		 6801 }
6802
f656ce01 6803 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6804
6805 return r;
6806}
6807
716d51ab
GN		 6808static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6809{
6810 int r;
6811 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6812 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6813 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6814 if (r != EMULATE_DONE)
6815 return 0;
6816 return 1;
6817}
6818
6819static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6820{
6821 BUG_ON(!vcpu->arch.pio.count);
6822
6823 return complete_emulated_io(vcpu);
6824}
6825
f78146b0
AK		 6826/*
6827 * Implements the following, as a state machine:
6828 *
6829 * read:
6830 * for each fragment
87da7e66
XG		 6831 * for each mmio piece in the fragment
6832 * write gpa, len
6833 * exit
6834 * copy data
f78146b0
AK		 6835 * execute insn
6836 *
6837 * write:
6838 * for each fragment
87da7e66
XG		 6839 * for each mmio piece in the fragment
6840 * write gpa, len
6841 * copy data
6842 * exit
f78146b0 6843 */
716d51ab 6844static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6845{
6846 struct kvm_run *run = vcpu->run;
f78146b0 6847 struct kvm_mmio_fragment *frag;
87da7e66 6848 unsigned len;
5287f194 6849
716d51ab 6850 BUG_ON(!vcpu->mmio_needed);
5287f194 6851
716d51ab 6852 /* Complete previous fragment */
87da7e66
XG		 6853 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6854 len = min(8u, frag->len);
716d51ab 6855 if (!vcpu->mmio_is_write)
87da7e66
XG		 6856 memcpy(frag->data, run->mmio.data, len);
6857
6858 if (frag->len <= 8) {
6859 /* Switch to the next fragment. */
6860 frag++;
6861 vcpu->mmio_cur_fragment++;
6862 } else {
6863 /* Go forward to the next mmio piece. */
6864 frag->data += len;
6865 frag->gpa += len;
6866 frag->len -= len;
6867 }
6868
a08d3b3b 6869 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6870 vcpu->mmio_needed = 0;
0912c977
PB		 6871
6872 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6873 if (vcpu->mmio_is_write)
716d51ab
GN		 6874 return 1;
6875 vcpu->mmio_read_completed = 1;
6876 return complete_emulated_io(vcpu);
6877 }
87da7e66 6878
716d51ab
GN		 6879 run->exit_reason = KVM_EXIT_MMIO;
6880 run->mmio.phys_addr = frag->gpa;
6881 if (vcpu->mmio_is_write)
87da7e66
XG		 6882 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6883 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6884 run->mmio.is_write = vcpu->mmio_is_write;
6885 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6886 return 0;
5287f194
AK		 6887}
6888
716d51ab 6889
b6c7a5dc
HB		 6890int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6891{
c5bedc68 6892 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6893 int r;
6894 sigset_t sigsaved;
6895
c4d72e2d 6896 fpu__activate_curr(fpu);
e5c30142 6897
ac9f6dc0
AK		 6898 if (vcpu->sigset_active)
6899 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6900
a4535290 6901 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6902 kvm_vcpu_block(vcpu);
66450a21 6903 kvm_apic_accept_events(vcpu);
d7690175 6904 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6905 r = -EAGAIN;
6906 goto out;
b6c7a5dc
HB		 6907 }
6908
b6c7a5dc 6909 /* re-sync apic's tpr */
35754c98 6910 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6911 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6912 r = -EINVAL;
6913 goto out;
6914 }
6915 }
b6c7a5dc 6916
716d51ab
GN		 6917 if (unlikely(vcpu->arch.complete_userspace_io)) {
6918 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6919 vcpu->arch.complete_userspace_io = NULL;
6920 r = cui(vcpu);
6921 if (r <= 0)
6922 goto out;
6923 } else
6924 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6925
362c698f 6926 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6927
6928out:
f1d86e46 6929 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6930 if (vcpu->sigset_active)
6931 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6932
b6c7a5dc
HB		 6933 return r;
6934}
6935
6936int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6937{
7ae441ea
GN		 6938 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6939 /*
6940 * We are here if userspace calls get_regs() in the middle of
6941 * instruction emulation. Registers state needs to be copied
4a969980 6942 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6943 * that usually, but some bad designed PV devices (vmware
6944 * backdoor interface) need this to work
6945 */
dd856efa 6946 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6947 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6948 }
5fdbf976
MT		 6949 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6950 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6951 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6952 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6953 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6954 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6955 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6956 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6957#ifdef CONFIG_X86_64
5fdbf976
MT		 6958 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6959 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6960 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6961 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6962 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6963 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6964 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6965 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6966#endif
6967
5fdbf976 6968 regs->rip = kvm_rip_read(vcpu);
91586a3b 6969 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6970
b6c7a5dc
HB		 6971 return 0;
6972}
6973
6974int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6975{
7ae441ea
GN		 6976 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6977 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6978
5fdbf976
MT		 6979 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6980 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6981 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6982 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6983 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6984 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6985 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6986 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6987#ifdef CONFIG_X86_64
5fdbf976
MT		 6988 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6989 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6990 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6991 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6992 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6993 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6994 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6995 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6996#endif
6997
5fdbf976 6998 kvm_rip_write(vcpu, regs->rip);
91586a3b 6999 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7000
b4f14abd
JK		 7001 vcpu->arch.exception.pending = false;
7002
3842d135
AK		 7003 kvm_make_request(KVM_REQ_EVENT, vcpu);
7004
b6c7a5dc
HB		 7005 return 0;
7006}
7007
b6c7a5dc
HB		 7008void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7009{
7010 struct kvm_segment cs;
7011
3e6e0aab 7012 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7013 *db = cs.db;
7014 *l = cs.l;
7015}
7016EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7017
7018int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7019 struct kvm_sregs *sregs)
7020{
89a27f4d 7021 struct desc_ptr dt;
b6c7a5dc 7022
3e6e0aab
GT		 7023 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7024 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7025 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7026 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7027 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7028 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7029
3e6e0aab
GT		 7030 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7031 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7032
7033 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7034 sregs->idt.limit = dt.size;
7035 sregs->idt.base = dt.address;
b6c7a5dc 7036 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7037 sregs->gdt.limit = dt.size;
7038 sregs->gdt.base = dt.address;
b6c7a5dc 7039
4d4ec087 7040 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7041 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7042 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7043 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7044 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7045 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7046 sregs->apic_base = kvm_get_apic_base(vcpu);
7047
923c61bb 7048 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7049
36752c9b 7050 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7051 set_bit(vcpu->arch.interrupt.nr,
7052 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7053
b6c7a5dc
HB		 7054 return 0;
7055}
7056
62d9f0db
MT		 7057int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7058 struct kvm_mp_state *mp_state)
7059{
66450a21 7060 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7061 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7062 vcpu->arch.pv.pv_unhalted)
7063 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7064 else
7065 mp_state->mp_state = vcpu->arch.mp_state;
7066
62d9f0db
MT		 7067 return 0;
7068}
7069
7070int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7071 struct kvm_mp_state *mp_state)
7072{
bce87cce 7073 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7074 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7075 return -EINVAL;
7076
7077 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7078 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7079 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7080 } else
7081 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7082 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7083 return 0;
7084}
7085
7f3d35fd
KW		 7086int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7087 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7088{
9d74191a 7089 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7090 int ret;
e01c2426 7091
8ec4722d 7092 init_emulate_ctxt(vcpu);
c697518a 7093
7f3d35fd 7094 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7095 has_error_code, error_code);
c697518a 7096
c697518a 7097 if (ret)
19d04437 7098 return EMULATE_FAIL;
37817f29 7099
9d74191a
TY		 7100 kvm_rip_write(vcpu, ctxt->eip);
7101 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7102 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7103 return EMULATE_DONE;
37817f29
IE		 7104}
7105EXPORT_SYMBOL_GPL(kvm_task_switch);
7106
b6c7a5dc
HB		 7107int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7108 struct kvm_sregs *sregs)
7109{
58cb628d 7110 struct msr_data apic_base_msr;
b6c7a5dc 7111 int mmu_reset_needed = 0;
63f42e02 7112 int pending_vec, max_bits, idx;
89a27f4d 7113 struct desc_ptr dt;
b6c7a5dc 7114
6d1068b3
PM		 7115 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7116 return -EINVAL;
7117
89a27f4d
GN		 7118 dt.size = sregs->idt.limit;
7119 dt.address = sregs->idt.base;
b6c7a5dc 7120 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7121 dt.size = sregs->gdt.limit;
7122 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7123 kvm_x86_ops->set_gdt(vcpu, &dt);
7124
ad312c7c 7125 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7126 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7127 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7128 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7129
2d3ad1f4 7130 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7131
f6801dff 7132 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7133 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7134 apic_base_msr.data = sregs->apic_base;
7135 apic_base_msr.host_initiated = true;
7136 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7137
4d4ec087 7138 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7139 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7140 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7141
fc78f519 7142 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7143 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7144 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7145 kvm_update_cpuid(vcpu);
63f42e02
XG		 7146
7147 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7148 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7149 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7150 mmu_reset_needed = 1;
7151 }
63f42e02 7152 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7153
7154 if (mmu_reset_needed)
7155 kvm_mmu_reset_context(vcpu);
7156
a50abc3b 7157 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7158 pending_vec = find_first_bit(
7159 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7160 if (pending_vec < max_bits) {
66fd3f7f 7161 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7162 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7163 }
7164
3e6e0aab
GT		 7165 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7166 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7167 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7168 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7169 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7170 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7171
3e6e0aab
GT		 7172 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7173 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7174
5f0269f5
ME		 7175 update_cr8_intercept(vcpu);
7176
9c3e4aab 7177 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7178 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7179 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7180 !is_protmode(vcpu))
9c3e4aab
MT		 7181 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7182
3842d135
AK		 7183 kvm_make_request(KVM_REQ_EVENT, vcpu);
7184
b6c7a5dc
HB		 7185 return 0;
7186}
7187
d0bfb940
JK		 7188int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7189 struct kvm_guest_debug *dbg)
b6c7a5dc 7190{
355be0b9 7191 unsigned long rflags;
ae675ef0 7192 int i, r;
b6c7a5dc 7193
4f926bf2
JK		 7194 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7195 r = -EBUSY;
7196 if (vcpu->arch.exception.pending)
2122ff5e 7197 goto out;
4f926bf2
JK		 7198 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7199 kvm_queue_exception(vcpu, DB_VECTOR);
7200 else
7201 kvm_queue_exception(vcpu, BP_VECTOR);
7202 }
7203
91586a3b
JK		 7204 /*
7205 * Read rflags as long as potentially injected trace flags are still
7206 * filtered out.
7207 */
7208 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7209
7210 vcpu->guest_debug = dbg->control;
7211 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7212 vcpu->guest_debug = 0;
7213
7214 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7215 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7216 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7217 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7218 } else {
7219 for (i = 0; i < KVM_NR_DB_REGS; i++)
7220 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7221 }
c8639010 7222 kvm_update_dr7(vcpu);
ae675ef0 7223
f92653ee
JK		 7224 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7225 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7226 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7227
91586a3b
JK		 7228 /*
7229 * Trigger an rflags update that will inject or remove the trace
7230 * flags.
7231 */
7232 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7233
a96036b8 7234 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7235
4f926bf2 7236 r = 0;
d0bfb940 7237
2122ff5e 7238out:
b6c7a5dc
HB		 7239
7240 return r;
7241}
7242
8b006791
ZX		 7243/*
7244 * Translate a guest virtual address to a guest physical address.
7245 */
7246int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7247 struct kvm_translation *tr)
7248{
7249 unsigned long vaddr = tr->linear_address;
7250 gpa_t gpa;
f656ce01 7251 int idx;
8b006791 7252
f656ce01 7253 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7254 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7255 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7256 tr->physical_address = gpa;
7257 tr->valid = gpa != UNMAPPED_GVA;
7258 tr->writeable = 1;
7259 tr->usermode = 0;
8b006791
ZX		 7260
7261 return 0;
7262}
7263
d0752060
HB		 7264int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7265{
c47ada30 7266 struct fxregs_state *fxsave =
7366ed77 7267 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7268
d0752060
HB		 7269 memcpy(fpu->fpr, fxsave->st_space, 128);
7270 fpu->fcw = fxsave->cwd;
7271 fpu->fsw = fxsave->swd;
7272 fpu->ftwx = fxsave->twd;
7273 fpu->last_opcode = fxsave->fop;
7274 fpu->last_ip = fxsave->rip;
7275 fpu->last_dp = fxsave->rdp;
7276 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7277
d0752060
HB		 7278 return 0;
7279}
7280
7281int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7282{
c47ada30 7283 struct fxregs_state *fxsave =
7366ed77 7284 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7285
d0752060
HB		 7286 memcpy(fxsave->st_space, fpu->fpr, 128);
7287 fxsave->cwd = fpu->fcw;
7288 fxsave->swd = fpu->fsw;
7289 fxsave->twd = fpu->ftwx;
7290 fxsave->fop = fpu->last_opcode;
7291 fxsave->rip = fpu->last_ip;
7292 fxsave->rdp = fpu->last_dp;
7293 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7294
d0752060
HB		 7295 return 0;
7296}
7297
0ee6a517 7298static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7299{
bf935b0b 7300 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7301 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7302 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7303 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7304
2acf923e
DC		 7305 /*
7306 * Ensure guest xcr0 is valid for loading
7307 */
d91cab78 7308 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7309
ad312c7c 7310 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7311}
d0752060
HB		 7312
7313void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7314{
2608d7a1 7315 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7316 return;
7317
2acf923e
DC		 7318 /*
7319 * Restore all possible states in the guest,
7320 * and assume host would use all available bits.
7321 * Guest xcr0 would be loaded later.
7322 */
d0752060 7323 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7324 __kernel_fpu_begin();
003e2e8b 7325 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7326 trace_kvm_fpu(1);
d0752060 7327}
d0752060
HB		 7328
7329void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7330{
653f52c3
RR		 7331 if (!vcpu->guest_fpu_loaded) {
7332 vcpu->fpu_counter = 0;
d0752060 7333 return;
653f52c3 7334 }
d0752060
HB		 7335
7336 vcpu->guest_fpu_loaded = 0;
4f836347 7337 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7338 __kernel_fpu_end();
f096ed85 7339 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7340 /*
7341 * If using eager FPU mode, or if the guest is a frequent user
7342 * of the FPU, just leave the FPU active for next time.
7343 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7344 * the FPU in bursts will revert to loading it on demand.
7345 */
5a5fbdc0 7346 if (!use_eager_fpu()) {
653f52c3
RR		 7347 if (++vcpu->fpu_counter < 5)
7348 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7349 }
0c04851c 7350 trace_kvm_fpu(0);
d0752060 7351}
e9b11c17
ZX		 7352
7353void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7354{
12f9a48f 7355 kvmclock_reset(vcpu);
7f1ea208 7356
f5f48ee1 7357 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7358 kvm_x86_ops->vcpu_free(vcpu);
7359}
7360
7361struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7362 unsigned int id)
7363{
c447e76b
LL		 7364 struct kvm_vcpu *vcpu;
7365
6755bae8
ZA		 7366 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7367 printk_once(KERN_WARNING
7368 "kvm: SMP vm created on host with unstable TSC; "
7369 "guest TSC will not be reliable\n");
c447e76b
LL		 7370
7371 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7372
c447e76b 7373 return vcpu;
26e5215f 7374}
e9b11c17 7375
26e5215f
AK		 7376int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7377{
7378 int r;
e9b11c17 7379
19efffa2 7380 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7381 r = vcpu_load(vcpu);
7382 if (r)
7383 return r;
d28bc9dd 7384 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7385 kvm_mmu_setup(vcpu);
e9b11c17 7386 vcpu_put(vcpu);
26e5215f 7387 return r;
e9b11c17
ZX		 7388}
7389
31928aa5 7390void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7391{
8fe8ab46 7392 struct msr_data msr;
332967a3 7393 struct kvm *kvm = vcpu->kvm;
42897d86 7394
31928aa5
DD		 7395 if (vcpu_load(vcpu))
7396 return;
8fe8ab46
WA		 7397 msr.data = 0x0;
7398 msr.index = MSR_IA32_TSC;
7399 msr.host_initiated = true;
7400 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7401 vcpu_put(vcpu);
7402
630994b3
MT		 7403 if (!kvmclock_periodic_sync)
7404 return;
7405
332967a3
AJ		 7406 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7407 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7408}
7409
d40ccc62 7410void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7411{
9fc77441 7412 int r;
344d9588
GN		 7413 vcpu->arch.apf.msr_val = 0;
7414
9fc77441
MT		 7415 r = vcpu_load(vcpu);
7416 BUG_ON(r);
e9b11c17
ZX		 7417 kvm_mmu_unload(vcpu);
7418 vcpu_put(vcpu);
7419
7420 kvm_x86_ops->vcpu_free(vcpu);
7421}
7422
d28bc9dd 7423void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7424{
e69fab5d
PB		 7425 vcpu->arch.hflags = 0;
7426
7460fb4a
AK		 7427 atomic_set(&vcpu->arch.nmi_queued, 0);
7428 vcpu->arch.nmi_pending = 0;
448fa4a9 7429 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7430 kvm_clear_interrupt_queue(vcpu);
7431 kvm_clear_exception_queue(vcpu);
448fa4a9 7432
42dbaa5a 7433 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7434 kvm_update_dr0123(vcpu);
6f43ed01 7435 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7436 kvm_update_dr6(vcpu);
42dbaa5a 7437 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7438 kvm_update_dr7(vcpu);
42dbaa5a 7439
1119022c
NA		 7440 vcpu->arch.cr2 = 0;
7441
3842d135 7442 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7443 vcpu->arch.apf.msr_val = 0;
c9aaa895 7444 vcpu->arch.st.msr_val = 0;
3842d135 7445
12f9a48f
GC		 7446 kvmclock_reset(vcpu);
7447
af585b92
GN		 7448 kvm_clear_async_pf_completion_queue(vcpu);
7449 kvm_async_pf_hash_reset(vcpu);
7450 vcpu->arch.apf.halted = false;
3842d135 7451
64d60670 7452 if (!init_event) {
d28bc9dd 7453 kvm_pmu_reset(vcpu);
64d60670
PB		 7454 vcpu->arch.smbase = 0x30000;
7455 }
f5132b01 7456
66f7b72e
JS		 7457 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7458 vcpu->arch.regs_avail = ~0;
7459 vcpu->arch.regs_dirty = ~0;
7460
d28bc9dd 7461 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7462}
7463
2b4a273b 7464void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7465{
7466 struct kvm_segment cs;
7467
7468 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7469 cs.selector = vector << 8;
7470 cs.base = vector << 12;
7471 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7472 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7473}
7474
13a34e06 7475int kvm_arch_hardware_enable(void)
e9b11c17 7476{
ca84d1a2
ZA		 7477 struct kvm *kvm;
7478 struct kvm_vcpu *vcpu;
7479 int i;
0dd6a6ed
ZA		 7480 int ret;
7481 u64 local_tsc;
7482 u64 max_tsc = 0;
7483 bool stable, backwards_tsc = false;
18863bdd
AK		 7484
7485 kvm_shared_msr_cpu_online();
13a34e06 7486 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7487 if (ret != 0)
7488 return ret;
7489
4ea1636b 7490 local_tsc = rdtsc();
0dd6a6ed
ZA		 7491 stable = !check_tsc_unstable();
7492 list_for_each_entry(kvm, &vm_list, vm_list) {
7493 kvm_for_each_vcpu(i, vcpu, kvm) {
7494 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7495 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7496 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7497 backwards_tsc = true;
7498 if (vcpu->arch.last_host_tsc > max_tsc)
7499 max_tsc = vcpu->arch.last_host_tsc;
7500 }
7501 }
7502 }
7503
7504 /*
7505 * Sometimes, even reliable TSCs go backwards. This happens on
7506 * platforms that reset TSC during suspend or hibernate actions, but
7507 * maintain synchronization. We must compensate. Fortunately, we can
7508 * detect that condition here, which happens early in CPU bringup,
7509 * before any KVM threads can be running. Unfortunately, we can't
7510 * bring the TSCs fully up to date with real time, as we aren't yet far
7511 * enough into CPU bringup that we know how much real time has actually
7512 * elapsed; our helper function, get_kernel_ns() will be using boot
7513 * variables that haven't been updated yet.
7514 *
7515 * So we simply find the maximum observed TSC above, then record the
7516 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7517 * the adjustment will be applied. Note that we accumulate
7518 * adjustments, in case multiple suspend cycles happen before some VCPU
7519 * gets a chance to run again. In the event that no KVM threads get a
7520 * chance to run, we will miss the entire elapsed period, as we'll have
7521 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7522 * loose cycle time. This isn't too big a deal, since the loss will be
7523 * uniform across all VCPUs (not to mention the scenario is extremely
7524 * unlikely). It is possible that a second hibernate recovery happens
7525 * much faster than a first, causing the observed TSC here to be
7526 * smaller; this would require additional padding adjustment, which is
7527 * why we set last_host_tsc to the local tsc observed here.
7528 *
7529 * N.B. - this code below runs only on platforms with reliable TSC,
7530 * as that is the only way backwards_tsc is set above. Also note
7531 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7532 * have the same delta_cyc adjustment applied if backwards_tsc
7533 * is detected. Note further, this adjustment is only done once,
7534 * as we reset last_host_tsc on all VCPUs to stop this from being
7535 * called multiple times (one for each physical CPU bringup).
7536 *
4a969980 7537 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7538 * will be compensated by the logic in vcpu_load, which sets the TSC to
7539 * catchup mode. This will catchup all VCPUs to real time, but cannot
7540 * guarantee that they stay in perfect synchronization.
7541 */
7542 if (backwards_tsc) {
7543 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7544 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7545 list_for_each_entry(kvm, &vm_list, vm_list) {
7546 kvm_for_each_vcpu(i, vcpu, kvm) {
7547 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7548 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7549 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7550 }
7551
7552 /*
7553 * We have to disable TSC offset matching.. if you were
7554 * booting a VM while issuing an S4 host suspend....
7555 * you may have some problem. Solving this issue is
7556 * left as an exercise to the reader.
7557 */
7558 kvm->arch.last_tsc_nsec = 0;
7559 kvm->arch.last_tsc_write = 0;
7560 }
7561
7562 }
7563 return 0;
e9b11c17
ZX		 7564}
7565
13a34e06 7566void kvm_arch_hardware_disable(void)
e9b11c17 7567{
13a34e06
RK		 7568 kvm_x86_ops->hardware_disable();
7569 drop_user_return_notifiers();
e9b11c17
ZX		 7570}
7571
7572int kvm_arch_hardware_setup(void)
7573{
9e9c3fe4
NA		 7574 int r;
7575
7576 r = kvm_x86_ops->hardware_setup();
7577 if (r != 0)
7578 return r;
7579
35181e86
HZ		 7580 if (kvm_has_tsc_control) {
7581 /*
7582 * Make sure the user can only configure tsc_khz values that
7583 * fit into a signed integer.
7584 * A min value is not calculated needed because it will always
7585 * be 1 on all machines.
7586 */
7587 u64 max = min(0x7fffffffULL,
7588 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7589 kvm_max_guest_tsc_khz = max;
7590
ad721883 7591 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7592 }
ad721883 7593
9e9c3fe4
NA		 7594 kvm_init_msr_list();
7595 return 0;
e9b11c17
ZX		 7596}
7597
7598void kvm_arch_hardware_unsetup(void)
7599{
7600 kvm_x86_ops->hardware_unsetup();
7601}
7602
7603void kvm_arch_check_processor_compat(void *rtn)
7604{
7605 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7606}
7607
7608bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7609{
7610 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7611}
7612EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7613
7614bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7615{
7616 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7617}
7618
3e515705
AK		 7619bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7620{
35754c98 7621 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7622}
7623
54e9818f 7624struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7625EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7626
e9b11c17
ZX		 7627int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7628{
7629 struct page *page;
7630 struct kvm *kvm;
7631 int r;
7632
7633 BUG_ON(vcpu->kvm == NULL);
7634 kvm = vcpu->kvm;
7635
d62caabb 7636 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7637 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7638 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7639 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7640 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7641 else
a4535290 7642 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7643
7644 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7645 if (!page) {
7646 r = -ENOMEM;
7647 goto fail;
7648 }
ad312c7c 7649 vcpu->arch.pio_data = page_address(page);
e9b11c17 7650
cc578287 7651 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7652
e9b11c17
ZX		 7653 r = kvm_mmu_create(vcpu);
7654 if (r < 0)
7655 goto fail_free_pio_data;
7656
7657 if (irqchip_in_kernel(kvm)) {
7658 r = kvm_create_lapic(vcpu);
7659 if (r < 0)
7660 goto fail_mmu_destroy;
54e9818f
GN		 7661 } else
7662 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7663
890ca9ae
HY		 7664 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7665 GFP_KERNEL);
7666 if (!vcpu->arch.mce_banks) {
7667 r = -ENOMEM;
443c39bc 7668 goto fail_free_lapic;
890ca9ae
HY		 7669 }
7670 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7671
f1797359
WY		 7672 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7673 r = -ENOMEM;
f5f48ee1 7674 goto fail_free_mce_banks;
f1797359 7675 }
f5f48ee1 7676
0ee6a517 7677 fx_init(vcpu);
66f7b72e 7678
ba904635 7679 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7680 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7681
7682 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7683 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7684
5a4f55cd
EK		 7685 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7686
74545705
RK		 7687 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7688
af585b92 7689 kvm_async_pf_hash_reset(vcpu);
f5132b01 7690 kvm_pmu_init(vcpu);
af585b92 7691
1c1a9ce9
SR		 7692 vcpu->arch.pending_external_vector = -1;
7693
5c919412
AS		 7694 kvm_hv_vcpu_init(vcpu);
7695
e9b11c17 7696 return 0;
0ee6a517 7697
f5f48ee1
SY		 7698fail_free_mce_banks:
7699 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7700fail_free_lapic:
7701 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7702fail_mmu_destroy:
7703 kvm_mmu_destroy(vcpu);
7704fail_free_pio_data:
ad312c7c 7705 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7706fail:
7707 return r;
7708}
7709
7710void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7711{
f656ce01
MT		 7712 int idx;
7713
1f4b34f8 7714 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7715 kvm_pmu_destroy(vcpu);
36cb93fd 7716 kfree(vcpu->arch.mce_banks);
e9b11c17 7717 kvm_free_lapic(vcpu);
f656ce01 7718 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7719 kvm_mmu_destroy(vcpu);
f656ce01 7720 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7721 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7722 if (!lapic_in_kernel(vcpu))
54e9818f 7723 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7724}
d19a9cd2 7725
e790d9ef
RK		 7726void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7727{
ae97a3b8 7728 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7729}
7730
e08b9637 7731int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7732{
e08b9637
CO		 7733 if (type)
7734 return -EINVAL;
7735
6ef768fa 7736 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7737 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7738 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7739 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7740 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7741
5550af4d
SY		 7742 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7743 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7744 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7745 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7746 &kvm->arch.irq_sources_bitmap);
5550af4d 7747
038f8c11 7748 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7749 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7750 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7751
7752 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7753
7e44e449 7754 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7755 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7756
0eb05bf2 7757 kvm_page_track_init(kvm);
13d268ca 7758 kvm_mmu_init_vm(kvm);
0eb05bf2 7759
03543133
SS		 7760 if (kvm_x86_ops->vm_init)
7761 return kvm_x86_ops->vm_init(kvm);
7762
d89f5eff 7763 return 0;
d19a9cd2
ZX		 7764}
7765
7766static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7767{
9fc77441
MT		 7768 int r;
7769 r = vcpu_load(vcpu);
7770 BUG_ON(r);
d19a9cd2
ZX		 7771 kvm_mmu_unload(vcpu);
7772 vcpu_put(vcpu);
7773}
7774
7775static void kvm_free_vcpus(struct kvm *kvm)
7776{
7777 unsigned int i;
988a2cae 7778 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7779
7780 /*
7781 * Unpin any mmu pages first.
7782 */
af585b92
GN		 7783 kvm_for_each_vcpu(i, vcpu, kvm) {
7784 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7785 kvm_unload_vcpu_mmu(vcpu);
af585b92 7786 }
988a2cae
GN		 7787 kvm_for_each_vcpu(i, vcpu, kvm)
7788 kvm_arch_vcpu_free(vcpu);
7789
7790 mutex_lock(&kvm->lock);
7791 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7792 kvm->vcpus[i] = NULL;
d19a9cd2 7793
988a2cae
GN		 7794 atomic_set(&kvm->online_vcpus, 0);
7795 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7796}
7797
ad8ba2cd
SY		 7798void kvm_arch_sync_events(struct kvm *kvm)
7799{
332967a3 7800 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7801 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7802 kvm_free_all_assigned_devices(kvm);
aea924f6 7803 kvm_free_pit(kvm);
ad8ba2cd
SY		 7804}
7805
1d8007bd 7806int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7807{
7808 int i, r;
25188b99 7809 unsigned long hva;
f0d648bd
PB		 7810 struct kvm_memslots *slots = kvm_memslots(kvm);
7811 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7812
7813 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7814 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7815 return -EINVAL;
9da0e4d5 7816
f0d648bd
PB		 7817 slot = id_to_memslot(slots, id);
7818 if (size) {
7819 if (WARN_ON(slot->npages))
7820 return -EEXIST;
7821
7822 /*
7823 * MAP_SHARED to prevent internal slot pages from being moved
7824 * by fork()/COW.
7825 */
7826 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7827 MAP_SHARED | MAP_ANONYMOUS, 0);
7828 if (IS_ERR((void *)hva))
7829 return PTR_ERR((void *)hva);
7830 } else {
7831 if (!slot->npages)
7832 return 0;
7833
7834 hva = 0;
7835 }
7836
7837 old = *slot;
9da0e4d5 7838 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7839 struct kvm_userspace_memory_region m;
9da0e4d5 7840
1d8007bd
PB		 7841 m.slot = id | (i << 16);
7842 m.flags = 0;
7843 m.guest_phys_addr = gpa;
f0d648bd 7844 m.userspace_addr = hva;
1d8007bd 7845 m.memory_size = size;
9da0e4d5
PB		 7846 r = __kvm_set_memory_region(kvm, &m);
7847 if (r < 0)
7848 return r;
7849 }
7850
f0d648bd
PB		 7851 if (!size) {
7852 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7853 WARN_ON(r < 0);
7854 }
7855
9da0e4d5
PB		 7856 return 0;
7857}
7858EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7859
1d8007bd 7860int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7861{
7862 int r;
7863
7864 mutex_lock(&kvm->slots_lock);
1d8007bd 7865 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7866 mutex_unlock(&kvm->slots_lock);
7867
7868 return r;
7869}
7870EXPORT_SYMBOL_GPL(x86_set_memory_region);
7871
d19a9cd2
ZX		 7872void kvm_arch_destroy_vm(struct kvm *kvm)
7873{
27469d29
AH		 7874 if (current->mm == kvm->mm) {
7875 /*
7876 * Free memory regions allocated on behalf of userspace,
7877 * unless the the memory map has changed due to process exit
7878 * or fd copying.
7879 */
1d8007bd
PB		 7880 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7881 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7882 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7883 }
03543133
SS		 7884 if (kvm_x86_ops->vm_destroy)
7885 kvm_x86_ops->vm_destroy(kvm);
6eb55818 7886 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7887 kfree(kvm->arch.vpic);
7888 kfree(kvm->arch.vioapic);
d19a9cd2 7889 kvm_free_vcpus(kvm);
1e08ec4a 7890 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7891 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7892}
0de10343 7893
5587027c 7894void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7895 struct kvm_memory_slot *dont)
7896{
7897 int i;
7898
d89cc617
TY		 7899 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7900 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7901 kvfree(free->arch.rmap[i]);
d89cc617 7902 free->arch.rmap[i] = NULL;
77d11309 7903 }
d89cc617
TY		 7904 if (i == 0)
7905 continue;
7906
7907 if (!dont || free->arch.lpage_info[i - 1] !=
7908 dont->arch.lpage_info[i - 1]) {
548ef284 7909 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7910 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7911 }
7912 }
21ebbeda
XG		 7913
7914 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7915}
7916
5587027c
AK		 7917int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7918 unsigned long npages)
db3fe4eb
TY		 7919{
7920 int i;
7921
d89cc617 7922 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7923 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7924 unsigned long ugfn;
7925 int lpages;
d89cc617 7926 int level = i + 1;
db3fe4eb
TY		 7927
7928 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7929 slot->base_gfn, level) + 1;
7930
d89cc617
TY		 7931 slot->arch.rmap[i] =
7932 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7933 if (!slot->arch.rmap[i])
77d11309 7934 goto out_free;
d89cc617
TY		 7935 if (i == 0)
7936 continue;
77d11309 7937
92f94f1e
XG		 7938 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7939 if (!linfo)
db3fe4eb
TY		 7940 goto out_free;
7941
92f94f1e
XG		 7942 slot->arch.lpage_info[i - 1] = linfo;
7943
db3fe4eb 7944 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7945 linfo[0].disallow_lpage = 1;
db3fe4eb 7946 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7947 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7948 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7949 /*
7950 * If the gfn and userspace address are not aligned wrt each
7951 * other, or if explicitly asked to, disable large page
7952 * support for this slot
7953 */
7954 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7955 !kvm_largepages_enabled()) {
7956 unsigned long j;
7957
7958 for (j = 0; j < lpages; ++j)
92f94f1e 7959 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7960 }
7961 }
7962
21ebbeda
XG		 7963 if (kvm_page_track_create_memslot(slot, npages))
7964 goto out_free;
7965
db3fe4eb
TY		 7966 return 0;
7967
7968out_free:
d89cc617 7969 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7970 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7971 slot->arch.rmap[i] = NULL;
7972 if (i == 0)
7973 continue;
7974
548ef284 7975 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7976 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7977 }
7978 return -ENOMEM;
7979}
7980
15f46015 7981void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7982{
e6dff7d1
TY		 7983 /*
7984 * memslots->generation has been incremented.
7985 * mmio generation may have reached its maximum value.
7986 */
54bf36aa 7987 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7988}
7989
f7784b8e
MT		 7990int kvm_arch_prepare_memory_region(struct kvm *kvm,
7991 struct kvm_memory_slot *memslot,
09170a49 7992 const struct kvm_userspace_memory_region *mem,
7b6195a9 7993 enum kvm_mr_change change)
0de10343 7994{
f7784b8e
MT		 7995 return 0;
7996}
7997
88178fd4
KH		 7998static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7999 struct kvm_memory_slot *new)
8000{
8001 /* Still write protect RO slot */
8002 if (new->flags & KVM_MEM_READONLY) {
8003 kvm_mmu_slot_remove_write_access(kvm, new);
8004 return;
8005 }
8006
8007 /*
8008 * Call kvm_x86_ops dirty logging hooks when they are valid.
8009 *
8010 * kvm_x86_ops->slot_disable_log_dirty is called when:
8011 *
8012 * - KVM_MR_CREATE with dirty logging is disabled
8013 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8014 *
8015 * The reason is, in case of PML, we need to set D-bit for any slots
8016 * with dirty logging disabled in order to eliminate unnecessary GPA
8017 * logging in PML buffer (and potential PML buffer full VMEXT). This
8018 * guarantees leaving PML enabled during guest's lifetime won't have
8019 * any additonal overhead from PML when guest is running with dirty
8020 * logging disabled for memory slots.
8021 *
8022 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8023 * to dirty logging mode.
8024 *
8025 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8026 *
8027 * In case of write protect:
8028 *
8029 * Write protect all pages for dirty logging.
8030 *
8031 * All the sptes including the large sptes which point to this
8032 * slot are set to readonly. We can not create any new large
8033 * spte on this slot until the end of the logging.
8034 *
8035 * See the comments in fast_page_fault().
8036 */
8037 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8038 if (kvm_x86_ops->slot_enable_log_dirty)
8039 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8040 else
8041 kvm_mmu_slot_remove_write_access(kvm, new);
8042 } else {
8043 if (kvm_x86_ops->slot_disable_log_dirty)
8044 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8045 }
8046}
8047
f7784b8e 8048void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8049 const struct kvm_userspace_memory_region *mem,
8482644a 8050 const struct kvm_memory_slot *old,
f36f3f28 8051 const struct kvm_memory_slot *new,
8482644a 8052 enum kvm_mr_change change)
f7784b8e 8053{
8482644a 8054 int nr_mmu_pages = 0;
f7784b8e 8055
48c0e4e9
XG		 8056 if (!kvm->arch.n_requested_mmu_pages)
8057 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8058
48c0e4e9 8059 if (nr_mmu_pages)
0de10343 8060 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8061
3ea3b7fa
WL		 8062 /*
8063 * Dirty logging tracks sptes in 4k granularity, meaning that large
8064 * sptes have to be split. If live migration is successful, the guest
8065 * in the source machine will be destroyed and large sptes will be
8066 * created in the destination. However, if the guest continues to run
8067 * in the source machine (for example if live migration fails), small
8068 * sptes will remain around and cause bad performance.
8069 *
8070 * Scan sptes if dirty logging has been stopped, dropping those
8071 * which can be collapsed into a single large-page spte. Later
8072 * page faults will create the large-page sptes.
8073 */
8074 if ((change != KVM_MR_DELETE) &&
8075 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8076 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8077 kvm_mmu_zap_collapsible_sptes(kvm, new);
8078
c972f3b1 8079 /*
88178fd4 8080 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8081 *
88178fd4
KH		 8082 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8083 * been zapped so no dirty logging staff is needed for old slot. For
8084 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8085 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8086 *
8087 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8088 */
88178fd4 8089 if (change != KVM_MR_DELETE)
f36f3f28 8090 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8091}
1d737c8a 8092
2df72e9b 8093void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8094{
6ca18b69 8095 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8096}
8097
2df72e9b
MT		 8098void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8099 struct kvm_memory_slot *slot)
8100{
6ca18b69 8101 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8102}
8103
5d9bc648
PB		 8104static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8105{
8106 if (!list_empty_careful(&vcpu->async_pf.done))
8107 return true;
8108
8109 if (kvm_apic_has_events(vcpu))
8110 return true;
8111
8112 if (vcpu->arch.pv.pv_unhalted)
8113 return true;
8114
8115 if (atomic_read(&vcpu->arch.nmi_queued))
8116 return true;
8117
73917739
PB		 8118 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8119 return true;
8120
5d9bc648
PB		 8121 if (kvm_arch_interrupt_allowed(vcpu) &&
8122 kvm_cpu_has_interrupt(vcpu))
8123 return true;
8124
1f4b34f8
AS		 8125 if (kvm_hv_has_stimer_pending(vcpu))
8126 return true;
8127
5d9bc648
PB		 8128 return false;
8129}
8130
1d737c8a
ZX		 8131int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8132{
b6b8a145
JK		 8133 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8134 kvm_x86_ops->check_nested_events(vcpu, false);
8135
5d9bc648 8136 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8137}
5736199a 8138
b6d33834 8139int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8140{
b6d33834 8141 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8142}
78646121
GN		 8143
8144int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8145{
8146 return kvm_x86_ops->interrupt_allowed(vcpu);
8147}
229456fc 8148
82b32774 8149unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8150{
82b32774
NA		 8151 if (is_64_bit_mode(vcpu))
8152 return kvm_rip_read(vcpu);
8153 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8154 kvm_rip_read(vcpu));
8155}
8156EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8157
82b32774
NA		 8158bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8159{
8160 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8161}
8162EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8163
94fe45da
JK		 8164unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8165{
8166 unsigned long rflags;
8167
8168 rflags = kvm_x86_ops->get_rflags(vcpu);
8169 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8170 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8171 return rflags;
8172}
8173EXPORT_SYMBOL_GPL(kvm_get_rflags);
8174
6addfc42 8175static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8176{
8177 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8178 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8179 rflags |= X86_EFLAGS_TF;
94fe45da 8180 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8181}
8182
8183void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8184{
8185 __kvm_set_rflags(vcpu, rflags);
3842d135 8186 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8187}
8188EXPORT_SYMBOL_GPL(kvm_set_rflags);
8189
56028d08
GN		 8190void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8191{
8192 int r;
8193
fb67e14f 8194 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8195 work->wakeup_all)
56028d08
GN		 8196 return;
8197
8198 r = kvm_mmu_reload(vcpu);
8199 if (unlikely(r))
8200 return;
8201
fb67e14f
XG		 8202 if (!vcpu->arch.mmu.direct_map &&
8203 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8204 return;
8205
56028d08
GN		 8206 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8207}
8208
af585b92
GN		 8209static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8210{
8211 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8212}
8213
8214static inline u32 kvm_async_pf_next_probe(u32 key)
8215{
8216 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8217}
8218
8219static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8220{
8221 u32 key = kvm_async_pf_hash_fn(gfn);
8222
8223 while (vcpu->arch.apf.gfns[key] != ~0)
8224 key = kvm_async_pf_next_probe(key);
8225
8226 vcpu->arch.apf.gfns[key] = gfn;
8227}
8228
8229static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8230{
8231 int i;
8232 u32 key = kvm_async_pf_hash_fn(gfn);
8233
8234 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8235 (vcpu->arch.apf.gfns[key] != gfn &&
8236 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8237 key = kvm_async_pf_next_probe(key);
8238
8239 return key;
8240}
8241
8242bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8243{
8244 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8245}
8246
8247static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8248{
8249 u32 i, j, k;
8250
8251 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8252 while (true) {
8253 vcpu->arch.apf.gfns[i] = ~0;
8254 do {
8255 j = kvm_async_pf_next_probe(j);
8256 if (vcpu->arch.apf.gfns[j] == ~0)
8257 return;
8258 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8259 /*
8260 * k lies cyclically in ]i,j]
8261 * | i.k.j |
8262 * |....j i.k.| or |.k..j i...|
8263 */
8264 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8265 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8266 i = j;
8267 }
8268}
8269
7c90705b
GN		 8270static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8271{
8272
8273 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8274 sizeof(val));
8275}
8276
af585b92
GN		 8277void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8278 struct kvm_async_pf *work)
8279{
6389ee94
AK		 8280 struct x86_exception fault;
8281
7c90705b 8282 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8283 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8284
8285 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8286 (vcpu->arch.apf.send_user_only &&
8287 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8288 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8289 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8290 fault.vector = PF_VECTOR;
8291 fault.error_code_valid = true;
8292 fault.error_code = 0;
8293 fault.nested_page_fault = false;
8294 fault.address = work->arch.token;
8295 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8296 }
af585b92
GN		 8297}
8298
8299void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8300 struct kvm_async_pf *work)
8301{
6389ee94
AK		 8302 struct x86_exception fault;
8303
7c90705b 8304 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8305 if (work->wakeup_all)
7c90705b
GN		 8306 work->arch.token = ~0; /* broadcast wakeup */
8307 else
8308 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8309
8310 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8311 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8312 fault.vector = PF_VECTOR;
8313 fault.error_code_valid = true;
8314 fault.error_code = 0;
8315 fault.nested_page_fault = false;
8316 fault.address = work->arch.token;
8317 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8318 }
e6d53e3b 8319 vcpu->arch.apf.halted = false;
a4fa1635 8320 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8321}
8322
8323bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8324{
8325 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8326 return true;
8327 else
8328 return !kvm_event_needs_reinjection(vcpu) &&
8329 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8330}
8331
5544eb9b
PB		 8332void kvm_arch_start_assignment(struct kvm *kvm)
8333{
8334 atomic_inc(&kvm->arch.assigned_device_count);
8335}
8336EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8337
8338void kvm_arch_end_assignment(struct kvm *kvm)
8339{
8340 atomic_dec(&kvm->arch.assigned_device_count);
8341}
8342EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8343
8344bool kvm_arch_has_assigned_device(struct kvm *kvm)
8345{
8346 return atomic_read(&kvm->arch.assigned_device_count);
8347}
8348EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8349
e0f0bbc5
AW		 8350void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8351{
8352 atomic_inc(&kvm->arch.noncoherent_dma_count);
8353}
8354EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8355
8356void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8357{
8358 atomic_dec(&kvm->arch.noncoherent_dma_count);
8359}
8360EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8361
8362bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8363{
8364 return atomic_read(&kvm->arch.noncoherent_dma_count);
8365}
8366EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8367
14717e20
AW		 8368bool kvm_arch_has_irq_bypass(void)
8369{
8370 return kvm_x86_ops->update_pi_irte != NULL;
8371}
8372
87276880
FW		 8373int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8374 struct irq_bypass_producer *prod)
8375{
8376 struct kvm_kernel_irqfd *irqfd =
8377 container_of(cons, struct kvm_kernel_irqfd, consumer);
8378
14717e20 8379 irqfd->producer = prod;
87276880 8380
14717e20
AW		 8381 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8382 prod->irq, irqfd->gsi, 1);
87276880
FW		 8383}
8384
8385void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8386 struct irq_bypass_producer *prod)
8387{
8388 int ret;
8389 struct kvm_kernel_irqfd *irqfd =
8390 container_of(cons, struct kvm_kernel_irqfd, consumer);
8391
87276880
FW		 8392 WARN_ON(irqfd->producer != prod);
8393 irqfd->producer = NULL;
8394
8395 /*
8396 * When producer of consumer is unregistered, we change back to
8397 * remapped mode, so we can re-use the current implementation
8398 * when the irq is masked/disabed or the consumer side (KVM
8399 * int this case doesn't want to receive the interrupts.
8400 */
8401 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8402 if (ret)
8403 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8404 " fails: %d\n", irqfd->consumer.token, ret);
8405}
8406
8407int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8408 uint32_t guest_irq, bool set)
8409{
8410 if (!kvm_x86_ops->update_pi_irte)
8411 return -EINVAL;
8412
8413 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8414}
8415
52004014
FW		 8416bool kvm_vector_hashing_enabled(void)
8417{
8418 return vector_hashing;
8419}
8420EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8421
229456fc 8422EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8423EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8424EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8425EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8426EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8427EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8428EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8429EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8430EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8431EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8432EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8433EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8434EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8435EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8436EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8437EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8438EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8439EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8440EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)