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KVM: x86: Replace call-back compute_tsc_offset() with a common function
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
893590c7 126static bool __read_mostly backwards_tsc_observed = false;
16a96021 127
18863bdd
AK		 128#define KVM_NR_SHARED_MSRS 16
129
130struct kvm_shared_msrs_global {
131 int nr;
2bf78fa7 132 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 133};
134
135struct kvm_shared_msrs {
136 struct user_return_notifier urn;
137 bool registered;
2bf78fa7
SY		 138 struct kvm_shared_msr_values {
139 u64 host;
140 u64 curr;
141 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 145static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 146
417bc304 147struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 148 { "pf_fixed", VCPU_STAT(pf_fixed) },
149 { "pf_guest", VCPU_STAT(pf_guest) },
150 { "tlb_flush", VCPU_STAT(tlb_flush) },
151 { "invlpg", VCPU_STAT(invlpg) },
152 { "exits", VCPU_STAT(exits) },
153 { "io_exits", VCPU_STAT(io_exits) },
154 { "mmio_exits", VCPU_STAT(mmio_exits) },
155 { "signal_exits", VCPU_STAT(signal_exits) },
156 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 157 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 158 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 161 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 162 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 163 { "request_irq", VCPU_STAT(request_irq_exits) },
164 { "irq_exits", VCPU_STAT(irq_exits) },
165 { "host_state_reload", VCPU_STAT(host_state_reload) },
166 { "efer_reload", VCPU_STAT(efer_reload) },
167 { "fpu_reload", VCPU_STAT(fpu_reload) },
168 { "insn_emulation", VCPU_STAT(insn_emulation) },
169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 170 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 171 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
173 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
176 { "mmu_flooded", VM_STAT(mmu_flooded) },
177 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 179 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 181 { "largepages", VM_STAT(lpages) },
417bc304
HB		 182 { NULL }
183};
184
2acf923e
DC		 185u64 __read_mostly host_xcr0;
186
b6785def 187static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 188
af585b92
GN		 189static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
190{
191 int i;
192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
193 vcpu->arch.apf.gfns[i] = ~0;
194}
195
18863bdd
AK		 196static void kvm_on_user_return(struct user_return_notifier *urn)
197{
198 unsigned slot;
18863bdd
AK		 199 struct kvm_shared_msrs *locals
200 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 201 struct kvm_shared_msr_values *values;
18863bdd
AK		 202
203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 204 values = &locals->values[slot];
205 if (values->host != values->curr) {
206 wrmsrl(shared_msrs_global.msrs[slot], values->host);
207 values->curr = values->host;
18863bdd
AK		 208 }
209 }
210 locals->registered = false;
211 user_return_notifier_unregister(urn);
212}
213
2bf78fa7 214static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 215{
18863bdd 216 u64 value;
013f6a5d
MT		 217 unsigned int cpu = smp_processor_id();
218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 219
2bf78fa7
SY		 220 /* only read, and nobody should modify it at this time,
221 * so don't need lock */
222 if (slot >= shared_msrs_global.nr) {
223 printk(KERN_ERR "kvm: invalid MSR slot!");
224 return;
225 }
226 rdmsrl_safe(msr, &value);
227 smsr->values[slot].host = value;
228 smsr->values[slot].curr = value;
229}
230
231void kvm_define_shared_msr(unsigned slot, u32 msr)
232{
0123be42 233 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 234 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 235 if (slot >= shared_msrs_global.nr)
236 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 237}
238EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
239
240static void kvm_shared_msr_cpu_online(void)
241{
242 unsigned i;
18863bdd
AK		 243
244 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 245 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 246}
247
8b3c3104 248int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 249{
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 252 int err;
18863bdd 253
2bf78fa7 254 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 255 return 0;
2bf78fa7 256 smsr->values[slot].curr = value;
8b3c3104
AH		 257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
258 if (err)
259 return 1;
260
18863bdd
AK		 261 if (!smsr->registered) {
262 smsr->urn.on_user_return = kvm_on_user_return;
263 user_return_notifier_register(&smsr->urn);
264 smsr->registered = true;
265 }
8b3c3104 266 return 0;
18863bdd
AK		 267}
268EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
269
13a34e06 270static void drop_user_return_notifiers(void)
3548bab5 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 274
275 if (smsr->registered)
276 kvm_on_user_return(&smsr->urn);
277}
278
6866b83e
CO		 279u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
280{
8a5a87d9 281 return vcpu->arch.apic_base;
6866b83e
CO		 282}
283EXPORT_SYMBOL_GPL(kvm_get_apic_base);
284
58cb628d
JK		 285int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
286{
287 u64 old_state = vcpu->arch.apic_base &
288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
289 u64 new_state = msr_info->data &
290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
293
294 if (!msr_info->host_initiated &&
295 ((msr_info->data & reserved_bits) != 0 ||
296 new_state == X2APIC_ENABLE ||
297 (new_state == MSR_IA32_APICBASE_ENABLE &&
298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
300 old_state == 0)))
301 return 1;
302
303 kvm_lapic_set_base(vcpu, msr_info->data);
304 return 0;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_set_apic_base);
307
2605fc21 308asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 309{
310 /* Fault while not rebooting. We want the trace. */
311 BUG();
312}
313EXPORT_SYMBOL_GPL(kvm_spurious_fault);
314
3fd28fce
ED		 315#define EXCPT_BENIGN 0
316#define EXCPT_CONTRIBUTORY 1
317#define EXCPT_PF 2
318
319static int exception_class(int vector)
320{
321 switch (vector) {
322 case PF_VECTOR:
323 return EXCPT_PF;
324 case DE_VECTOR:
325 case TS_VECTOR:
326 case NP_VECTOR:
327 case SS_VECTOR:
328 case GP_VECTOR:
329 return EXCPT_CONTRIBUTORY;
330 default:
331 break;
332 }
333 return EXCPT_BENIGN;
334}
335
d6e8c854
NA		 336#define EXCPT_FAULT 0
337#define EXCPT_TRAP 1
338#define EXCPT_ABORT 2
339#define EXCPT_INTERRUPT 3
340
341static int exception_type(int vector)
342{
343 unsigned int mask;
344
345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
346 return EXCPT_INTERRUPT;
347
348 mask = 1 << vector;
349
350 /* #DB is trap, as instruction watchpoints are handled elsewhere */
351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
352 return EXCPT_TRAP;
353
354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
355 return EXCPT_ABORT;
356
357 /* Reserved exceptions will result in fault */
358 return EXCPT_FAULT;
359}
360
3fd28fce 361static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 362 unsigned nr, bool has_error, u32 error_code,
363 bool reinject)
3fd28fce
ED		 364{
365 u32 prev_nr;
366 int class1, class2;
367
3842d135
AK		 368 kvm_make_request(KVM_REQ_EVENT, vcpu);
369
3fd28fce
ED		 370 if (!vcpu->arch.exception.pending) {
371 queue:
3ffb2468
NA		 372 if (has_error && !is_protmode(vcpu))
373 has_error = false;
3fd28fce
ED		 374 vcpu->arch.exception.pending = true;
375 vcpu->arch.exception.has_error_code = has_error;
376 vcpu->arch.exception.nr = nr;
377 vcpu->arch.exception.error_code = error_code;
3f0fd292 378 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 379 return;
380 }
381
382 /* to check exception */
383 prev_nr = vcpu->arch.exception.nr;
384 if (prev_nr == DF_VECTOR) {
385 /* triple fault -> shutdown */
a8eeb04a 386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 387 return;
388 }
389 class1 = exception_class(prev_nr);
390 class2 = exception_class(nr);
391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
393 /* generate double fault per SDM Table 5-5 */
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = true;
396 vcpu->arch.exception.nr = DF_VECTOR;
397 vcpu->arch.exception.error_code = 0;
398 } else
399 /* replace previous exception with a new one in a hope
400 that instruction re-execution will regenerate lost
401 exception */
402 goto queue;
403}
404
298101da
AK		 405void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
406{
ce7ddec4 407 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 408}
409EXPORT_SYMBOL_GPL(kvm_queue_exception);
410
ce7ddec4
JR		 411void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
412{
413 kvm_multiple_exception(vcpu, nr, false, 0, true);
414}
415EXPORT_SYMBOL_GPL(kvm_requeue_exception);
416
db8fcefa 417void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 418{
db8fcefa
AP		 419 if (err)
420 kvm_inject_gp(vcpu, 0);
421 else
422 kvm_x86_ops->skip_emulated_instruction(vcpu);
423}
424EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 425
6389ee94 426void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 427{
428 ++vcpu->stat.pf_guest;
6389ee94
AK		 429 vcpu->arch.cr2 = fault->address;
430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 431}
27d6c865 432EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 433
ef54bcfe 434static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 435{
6389ee94
AK		 436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 438 else
6389ee94 439 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 440
441 return fault->nested_page_fault;
d4f8cf66
JR		 442}
443
3419ffc8
SY		 444void kvm_inject_nmi(struct kvm_vcpu *vcpu)
445{
7460fb4a
AK		 446 atomic_inc(&vcpu->arch.nmi_queued);
447 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 448}
449EXPORT_SYMBOL_GPL(kvm_inject_nmi);
450
298101da
AK		 451void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
452{
ce7ddec4 453 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 454}
455EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
456
ce7ddec4
JR		 457void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
458{
459 kvm_multiple_exception(vcpu, nr, true, error_code, true);
460}
461EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
462
0a79b009
AK		 463/*
464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
465 * a #GP and return false.
466 */
467bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 468{
0a79b009
AK		 469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
470 return true;
471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
472 return false;
298101da 473}
0a79b009 474EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 475
16f8a6f9
NA		 476bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
477{
478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
479 return true;
480
481 kvm_queue_exception(vcpu, UD_VECTOR);
482 return false;
483}
484EXPORT_SYMBOL_GPL(kvm_require_dr);
485
ec92fe44
JR		 486/*
487 * This function will be used to read from the physical memory of the currently
54bf36aa 488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 489 * can read from guest physical or from the guest's guest physical memory.
490 */
491int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
492 gfn_t ngfn, void *data, int offset, int len,
493 u32 access)
494{
54987b7a 495 struct x86_exception exception;
ec92fe44
JR		 496 gfn_t real_gfn;
497 gpa_t ngpa;
498
499 ngpa = gfn_to_gpa(ngfn);
54987b7a 500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 501 if (real_gfn == UNMAPPED_GVA)
502 return -EFAULT;
503
504 real_gfn = gpa_to_gfn(real_gfn);
505
54bf36aa 506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 507}
508EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
509
69b0049a 510static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 511 void *data, int offset, int len, u32 access)
512{
513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
514 data, offset, len, access);
515}
516
a03490ed
CO		 517/*
518 * Load the pae pdptrs. Return true is they are all valid.
519 */
ff03a073 520int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 521{
522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
524 int i;
525 int ret;
ff03a073 526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 527
ff03a073
JR		 528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
529 offset * sizeof(u64), sizeof(pdpte),
530 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 531 if (ret < 0) {
532 ret = 0;
533 goto out;
534 }
535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 536 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 537 (pdpte[i] &
538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 539 ret = 0;
540 goto out;
541 }
542 }
543 ret = 1;
544
ff03a073 545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 546 __set_bit(VCPU_EXREG_PDPTR,
547 (unsigned long *)&vcpu->arch.regs_avail);
548 __set_bit(VCPU_EXREG_PDPTR,
549 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 550out:
a03490ed
CO		 551
552 return ret;
553}
cc4b6871 554EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 555
d835dfec
AK		 556static bool pdptrs_changed(struct kvm_vcpu *vcpu)
557{
ff03a073 558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 559 bool changed = true;
3d06b8bf
JR		 560 int offset;
561 gfn_t gfn;
d835dfec
AK		 562 int r;
563
564 if (is_long_mode(vcpu) || !is_pae(vcpu))
565 return false;
566
6de4f3ad
AK		 567 if (!test_bit(VCPU_EXREG_PDPTR,
568 (unsigned long *)&vcpu->arch.regs_avail))
569 return true;
570
9f8fe504
AK		 571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
574 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 575 if (r < 0)
576 goto out;
ff03a073 577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 578out:
d835dfec
AK		 579
580 return changed;
581}
582
49a9b07e 583int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 584{
aad82703 585 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 587
f9a48e6a
AK		 588 cr0 |= X86_CR0_ET;
589
ab344828 590#ifdef CONFIG_X86_64
0f12244f
GN		 591 if (cr0 & 0xffffffff00000000UL)
592 return 1;
ab344828
GN		 593#endif
594
595 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 596
0f12244f
GN		 597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
598 return 1;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
601 return 1;
a03490ed
CO		 602
603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
604#ifdef CONFIG_X86_64
f6801dff 605 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 606 int cs_db, cs_l;
607
0f12244f
GN		 608 if (!is_pae(vcpu))
609 return 1;
a03490ed 610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 611 if (cs_l)
612 return 1;
a03490ed
CO		 613 } else
614#endif
ff03a073 615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 616 kvm_read_cr3(vcpu)))
0f12244f 617 return 1;
a03490ed
CO		 618 }
619
ad756a16
MJ		 620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
621 return 1;
622
a03490ed 623 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 624
d170c419 625 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 626 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 627 kvm_async_pf_hash_reset(vcpu);
628 }
e5f3f027 629
aad82703
SY		 630 if ((cr0 ^ old_cr0) & update_bits)
631 kvm_mmu_reset_context(vcpu);
b18d5431 632
879ae188
LE		 633 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
634 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
637
0f12244f
GN		 638 return 0;
639}
2d3ad1f4 640EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 641
2d3ad1f4 642void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 643{
49a9b07e 644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 645}
2d3ad1f4 646EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 647
42bdf991
MT		 648static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
649{
650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
651 !vcpu->guest_xcr0_loaded) {
652 /* kvm_set_xcr() also depends on this */
653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
654 vcpu->guest_xcr0_loaded = 1;
655 }
656}
657
658static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
659{
660 if (vcpu->guest_xcr0_loaded) {
661 if (vcpu->arch.xcr0 != host_xcr0)
662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
663 vcpu->guest_xcr0_loaded = 0;
664 }
665}
666
69b0049a 667static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 668{
56c103ec
LJ		 669 u64 xcr0 = xcr;
670 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 671 u64 valid_bits;
2acf923e
DC		 672
673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
674 if (index != XCR_XFEATURE_ENABLED_MASK)
675 return 1;
2acf923e
DC		 676 if (!(xcr0 & XSTATE_FP))
677 return 1;
678 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
679 return 1;
46c34cb0
PB		 680
681 /*
682 * Do not allow the guest to set bits that we do not support
683 * saving. However, xcr0 bit 0 is always set, even if the
684 * emulated CPU does not support XSAVE (see fx_init).
685 */
686 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
687 if (xcr0 & ~valid_bits)
2acf923e 688 return 1;
46c34cb0 689
390bd528
LJ		 690 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
691 return 1;
692
612263b3
CP		 693 if (xcr0 & XSTATE_AVX512) {
694 if (!(xcr0 & XSTATE_YMM))
695 return 1;
696 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
697 return 1;
698 }
42bdf991 699 kvm_put_guest_xcr0(vcpu);
2acf923e 700 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 701
702 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
703 kvm_update_cpuid(vcpu);
2acf923e
DC		 704 return 0;
705}
706
707int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
708{
764bcbc5
Z		 709 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
710 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 711 kvm_inject_gp(vcpu, 0);
712 return 1;
713 }
714 return 0;
715}
716EXPORT_SYMBOL_GPL(kvm_set_xcr);
717
a83b29c6 718int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 719{
fc78f519 720 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 721 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
722 X86_CR4_SMEP | X86_CR4_SMAP;
723
0f12244f
GN		 724 if (cr4 & CR4_RESERVED_BITS)
725 return 1;
a03490ed 726
2acf923e
DC		 727 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
728 return 1;
729
c68b734f
YW		 730 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
731 return 1;
732
97ec8c06
FW		 733 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
734 return 1;
735
afcbf13f 736 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 737 return 1;
738
a03490ed 739 if (is_long_mode(vcpu)) {
0f12244f
GN		 740 if (!(cr4 & X86_CR4_PAE))
741 return 1;
a2edf57f
AK		 742 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
743 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 744 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
745 kvm_read_cr3(vcpu)))
0f12244f
GN		 746 return 1;
747
ad756a16
MJ		 748 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
749 if (!guest_cpuid_has_pcid(vcpu))
750 return 1;
751
752 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
753 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
754 return 1;
755 }
756
5e1746d6 757 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 758 return 1;
a03490ed 759
ad756a16
MJ		 760 if (((cr4 ^ old_cr4) & pdptr_bits) ||
761 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 762 kvm_mmu_reset_context(vcpu);
0f12244f 763
2acf923e 764 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 765 kvm_update_cpuid(vcpu);
2acf923e 766
0f12244f
GN		 767 return 0;
768}
2d3ad1f4 769EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 770
2390218b 771int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 772{
ac146235 773#ifdef CONFIG_X86_64
9d88fca7 774 cr3 &= ~CR3_PCID_INVD;
ac146235 775#endif
9d88fca7 776
9f8fe504 777 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 778 kvm_mmu_sync_roots(vcpu);
77c3913b 779 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 780 return 0;
d835dfec
AK		 781 }
782
a03490ed 783 if (is_long_mode(vcpu)) {
d9f89b88
JK		 784 if (cr3 & CR3_L_MODE_RESERVED_BITS)
785 return 1;
786 } else if (is_pae(vcpu) && is_paging(vcpu) &&
787 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 788 return 1;
a03490ed 789
0f12244f 790 vcpu->arch.cr3 = cr3;
aff48baa 791 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 792 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 793 return 0;
794}
2d3ad1f4 795EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 796
eea1cff9 797int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 798{
0f12244f
GN		 799 if (cr8 & CR8_RESERVED_BITS)
800 return 1;
35754c98 801 if (lapic_in_kernel(vcpu))
a03490ed
CO		 802 kvm_lapic_set_tpr(vcpu, cr8);
803 else
ad312c7c 804 vcpu->arch.cr8 = cr8;
0f12244f
GN		 805 return 0;
806}
2d3ad1f4 807EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 808
2d3ad1f4 809unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 810{
35754c98 811 if (lapic_in_kernel(vcpu))
a03490ed
CO		 812 return kvm_lapic_get_cr8(vcpu);
813 else
ad312c7c 814 return vcpu->arch.cr8;
a03490ed 815}
2d3ad1f4 816EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 817
ae561ede
NA		 818static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
819{
820 int i;
821
822 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
823 for (i = 0; i < KVM_NR_DB_REGS; i++)
824 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
825 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
826 }
827}
828
73aaf249
JK		 829static void kvm_update_dr6(struct kvm_vcpu *vcpu)
830{
831 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
832 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
833}
834
c8639010
JK		 835static void kvm_update_dr7(struct kvm_vcpu *vcpu)
836{
837 unsigned long dr7;
838
839 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
840 dr7 = vcpu->arch.guest_debug_dr7;
841 else
842 dr7 = vcpu->arch.dr7;
843 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 844 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
845 if (dr7 & DR7_BP_EN_MASK)
846 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 847}
848
6f43ed01
NA		 849static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
850{
851 u64 fixed = DR6_FIXED_1;
852
853 if (!guest_cpuid_has_rtm(vcpu))
854 fixed |= DR6_RTM;
855 return fixed;
856}
857
338dbc97 858static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 859{
860 switch (dr) {
861 case 0 ... 3:
862 vcpu->arch.db[dr] = val;
863 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
864 vcpu->arch.eff_db[dr] = val;
865 break;
866 case 4:
020df079
GN		 867 /* fall through */
868 case 6:
338dbc97
GN		 869 if (val & 0xffffffff00000000ULL)
870 return -1; /* #GP */
6f43ed01 871 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 872 kvm_update_dr6(vcpu);
020df079
GN		 873 break;
874 case 5:
020df079
GN		 875 /* fall through */
876 default: /* 7 */
338dbc97
GN		 877 if (val & 0xffffffff00000000ULL)
878 return -1; /* #GP */
020df079 879 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 880 kvm_update_dr7(vcpu);
020df079
GN		 881 break;
882 }
883
884 return 0;
885}
338dbc97
GN		 886
887int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
888{
16f8a6f9 889 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 890 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 891 return 1;
892 }
893 return 0;
338dbc97 894}
020df079
GN		 895EXPORT_SYMBOL_GPL(kvm_set_dr);
896
16f8a6f9 897int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 898{
899 switch (dr) {
900 case 0 ... 3:
901 *val = vcpu->arch.db[dr];
902 break;
903 case 4:
020df079
GN		 904 /* fall through */
905 case 6:
73aaf249
JK		 906 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
907 *val = vcpu->arch.dr6;
908 else
909 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 910 break;
911 case 5:
020df079
GN		 912 /* fall through */
913 default: /* 7 */
914 *val = vcpu->arch.dr7;
915 break;
916 }
338dbc97
GN		 917 return 0;
918}
020df079
GN		 919EXPORT_SYMBOL_GPL(kvm_get_dr);
920
022cd0e8
AK		 921bool kvm_rdpmc(struct kvm_vcpu *vcpu)
922{
923 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
924 u64 data;
925 int err;
926
c6702c9d 927 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 928 if (err)
929 return err;
930 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
931 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
932 return err;
933}
934EXPORT_SYMBOL_GPL(kvm_rdpmc);
935
043405e1
CO		 936/*
937 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
938 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
939 *
940 * This list is modified at module load time to reflect the
e3267cbb 941 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 942 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
943 * may depend on host virtualization features rather than host cpu features.
043405e1 944 */
e3267cbb 945
043405e1
CO		 946static u32 msrs_to_save[] = {
947 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 948 MSR_STAR,
043405e1
CO		 949#ifdef CONFIG_X86_64
950 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
951#endif
b3897a49 952 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 953 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 954};
955
956static unsigned num_msrs_to_save;
957
62ef68bb
PB		 958static u32 emulated_msrs[] = {
959 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
960 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
961 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
962 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 963 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
964 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 965 HV_X64_MSR_RESET,
11c4b1ca 966 HV_X64_MSR_VP_INDEX,
9eec50b8 967 HV_X64_MSR_VP_RUNTIME,
62ef68bb
PB		 968 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
969 MSR_KVM_PV_EOI_EN,
970
ba904635 971 MSR_IA32_TSC_ADJUST,
a3e06bbe 972 MSR_IA32_TSCDEADLINE,
043405e1 973 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 974 MSR_IA32_MCG_STATUS,
975 MSR_IA32_MCG_CTL,
64d60670 976 MSR_IA32_SMBASE,
043405e1
CO		 977};
978
62ef68bb
PB		 979static unsigned num_emulated_msrs;
980
384bb783 981bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 982{
b69e8cae 983 if (efer & efer_reserved_bits)
384bb783 984 return false;
15c4a640 985
1b2fd70c
AG		 986 if (efer & EFER_FFXSR) {
987 struct kvm_cpuid_entry2 *feat;
988
989 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 990 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 991 return false;
1b2fd70c
AG		 992 }
993
d8017474
AG		 994 if (efer & EFER_SVME) {
995 struct kvm_cpuid_entry2 *feat;
996
997 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 998 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 999 return false;
d8017474
AG		 1000 }
1001
384bb783
JK		 1002 return true;
1003}
1004EXPORT_SYMBOL_GPL(kvm_valid_efer);
1005
1006static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1007{
1008 u64 old_efer = vcpu->arch.efer;
1009
1010 if (!kvm_valid_efer(vcpu, efer))
1011 return 1;
1012
1013 if (is_paging(vcpu)
1014 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1015 return 1;
1016
15c4a640 1017 efer &= ~EFER_LMA;
f6801dff 1018 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1019
a3d204e2
SY		 1020 kvm_x86_ops->set_efer(vcpu, efer);
1021
aad82703
SY		 1022 /* Update reserved bits */
1023 if ((efer ^ old_efer) & EFER_NX)
1024 kvm_mmu_reset_context(vcpu);
1025
b69e8cae 1026 return 0;
15c4a640
CO		 1027}
1028
f2b4b7dd
JR		 1029void kvm_enable_efer_bits(u64 mask)
1030{
1031 efer_reserved_bits &= ~mask;
1032}
1033EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1034
15c4a640
CO		 1035/*
1036 * Writes msr value into into the appropriate "register".
1037 * Returns 0 on success, non-0 otherwise.
1038 * Assumes vcpu_load() was already called.
1039 */
8fe8ab46 1040int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1041{
854e8bb1
NA		 1042 switch (msr->index) {
1043 case MSR_FS_BASE:
1044 case MSR_GS_BASE:
1045 case MSR_KERNEL_GS_BASE:
1046 case MSR_CSTAR:
1047 case MSR_LSTAR:
1048 if (is_noncanonical_address(msr->data))
1049 return 1;
1050 break;
1051 case MSR_IA32_SYSENTER_EIP:
1052 case MSR_IA32_SYSENTER_ESP:
1053 /*
1054 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1055 * non-canonical address is written on Intel but not on
1056 * AMD (which ignores the top 32-bits, because it does
1057 * not implement 64-bit SYSENTER).
1058 *
1059 * 64-bit code should hence be able to write a non-canonical
1060 * value on AMD. Making the address canonical ensures that
1061 * vmentry does not fail on Intel after writing a non-canonical
1062 * value, and that something deterministic happens if the guest
1063 * invokes 64-bit SYSENTER.
1064 */
1065 msr->data = get_canonical(msr->data);
1066 }
8fe8ab46 1067 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1068}
854e8bb1 1069EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1070
313a3dc7
CO		 1071/*
1072 * Adapt set_msr() to msr_io()'s calling convention
1073 */
609e36d3
PB		 1074static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1075{
1076 struct msr_data msr;
1077 int r;
1078
1079 msr.index = index;
1080 msr.host_initiated = true;
1081 r = kvm_get_msr(vcpu, &msr);
1082 if (r)
1083 return r;
1084
1085 *data = msr.data;
1086 return 0;
1087}
1088
313a3dc7
CO		 1089static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1090{
8fe8ab46
WA		 1091 struct msr_data msr;
1092
1093 msr.data = *data;
1094 msr.index = index;
1095 msr.host_initiated = true;
1096 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1097}
1098
16e8d74d
MT		 1099#ifdef CONFIG_X86_64
1100struct pvclock_gtod_data {
1101 seqcount_t seq;
1102
1103 struct { /* extract of a clocksource struct */
1104 int vclock_mode;
1105 cycle_t cycle_last;
1106 cycle_t mask;
1107 u32 mult;
1108 u32 shift;
1109 } clock;
1110
cbcf2dd3
TG		 1111 u64 boot_ns;
1112 u64 nsec_base;
16e8d74d
MT		 1113};
1114
1115static struct pvclock_gtod_data pvclock_gtod_data;
1116
1117static void update_pvclock_gtod(struct timekeeper *tk)
1118{
1119 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1120 u64 boot_ns;
1121
876e7881 1122 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1123
1124 write_seqcount_begin(&vdata->seq);
1125
1126 /* copy pvclock gtod data */
876e7881
PZ		 1127 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1128 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1129 vdata->clock.mask = tk->tkr_mono.mask;
1130 vdata->clock.mult = tk->tkr_mono.mult;
1131 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1132
cbcf2dd3 1133 vdata->boot_ns = boot_ns;
876e7881 1134 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1135
1136 write_seqcount_end(&vdata->seq);
1137}
1138#endif
1139
bab5bb39
NK		 1140void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1141{
1142 /*
1143 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1144 * vcpu_enter_guest. This function is only called from
1145 * the physical CPU that is running vcpu.
1146 */
1147 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1148}
16e8d74d 1149
18068523
GOC		 1150static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1151{
9ed3c444
AK		 1152 int version;
1153 int r;
50d0a0f9 1154 struct pvclock_wall_clock wc;
923de3cf 1155 struct timespec boot;
18068523
GOC		 1156
1157 if (!wall_clock)
1158 return;
1159
9ed3c444
AK		 1160 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1161 if (r)
1162 return;
1163
1164 if (version & 1)
1165 ++version; /* first time write, random junk */
1166
1167 ++version;
18068523 1168
18068523
GOC		 1169 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1170
50d0a0f9
GH		 1171 /*
1172 * The guest calculates current wall clock time by adding
34c238a1 1173 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1174 * wall clock specified here. guest system time equals host
1175 * system time for us, thus we must fill in host boot time here.
1176 */
923de3cf 1177 getboottime(&boot);
50d0a0f9 1178
4b648665
BR		 1179 if (kvm->arch.kvmclock_offset) {
1180 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1181 boot = timespec_sub(boot, ts);
1182 }
50d0a0f9
GH		 1183 wc.sec = boot.tv_sec;
1184 wc.nsec = boot.tv_nsec;
1185 wc.version = version;
18068523
GOC		 1186
1187 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1188
1189 version++;
1190 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1191}
1192
50d0a0f9
GH		 1193static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1194{
1195 uint32_t quotient, remainder;
1196
1197 /* Don't try to replace with do_div(), this one calculates
1198 * "(dividend << 32) / divisor" */
1199 __asm__ ( "divl %4"
1200 : "=a" (quotient), "=d" (remainder)
1201 : "0" (0), "1" (dividend), "r" (divisor) );
1202 return quotient;
1203}
1204
5f4e3f88
ZA		 1205static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1206 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1207{
5f4e3f88 1208 uint64_t scaled64;
50d0a0f9
GH		 1209 int32_t shift = 0;
1210 uint64_t tps64;
1211 uint32_t tps32;
1212
5f4e3f88
ZA		 1213 tps64 = base_khz * 1000LL;
1214 scaled64 = scaled_khz * 1000LL;
50933623 1215 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1216 tps64 >>= 1;
1217 shift--;
1218 }
1219
1220 tps32 = (uint32_t)tps64;
50933623
JK		 1221 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1222 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1223 scaled64 >>= 1;
1224 else
1225 tps32 <<= 1;
50d0a0f9
GH		 1226 shift++;
1227 }
1228
5f4e3f88
ZA		 1229 *pshift = shift;
1230 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1231
5f4e3f88
ZA		 1232 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1233 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1234}
1235
d828199e 1236#ifdef CONFIG_X86_64
16e8d74d 1237static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1238#endif
16e8d74d 1239
c8076604 1240static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1241static unsigned long max_tsc_khz;
c8076604 1242
cc578287 1243static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1244{
cc578287
ZA		 1245 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1246 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1247}
1248
cc578287 1249static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1250{
cc578287
ZA		 1251 u64 v = (u64)khz * (1000000 + ppm);
1252 do_div(v, 1000000);
1253 return v;
1e993611
JR		 1254}
1255
381d585c
HZ		 1256static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1257{
1258 u64 ratio;
1259
1260 /* Guest TSC same frequency as host TSC? */
1261 if (!scale) {
1262 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1263 return 0;
1264 }
1265
1266 /* TSC scaling supported? */
1267 if (!kvm_has_tsc_control) {
1268 if (user_tsc_khz > tsc_khz) {
1269 vcpu->arch.tsc_catchup = 1;
1270 vcpu->arch.tsc_always_catchup = 1;
1271 return 0;
1272 } else {
1273 WARN(1, "user requested TSC rate below hardware speed\n");
1274 return -1;
1275 }
1276 }
1277
1278 /* TSC scaling required - calculate ratio */
1279 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1280 user_tsc_khz, tsc_khz);
1281
1282 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1283 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1284 user_tsc_khz);
1285 return -1;
1286 }
1287
1288 vcpu->arch.tsc_scaling_ratio = ratio;
1289 return 0;
1290}
1291
1292static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1293{
cc578287
ZA		 1294 u32 thresh_lo, thresh_hi;
1295 int use_scaling = 0;
217fc9cf 1296
03ba32ca 1297 /* tsc_khz can be zero if TSC calibration fails */
ad721883
HZ		 1298 if (this_tsc_khz == 0) {
1299 /* set tsc_scaling_ratio to a safe value */
1300 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1301 return -1;
ad721883 1302 }
03ba32ca 1303
c285545f
ZA		 1304 /* Compute a scale to convert nanoseconds in TSC cycles */
1305 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1306 &vcpu->arch.virtual_tsc_shift,
1307 &vcpu->arch.virtual_tsc_mult);
1308 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1309
1310 /*
1311 * Compute the variation in TSC rate which is acceptable
1312 * within the range of tolerance and decide if the
1313 * rate being applied is within that bounds of the hardware
1314 * rate. If so, no scaling or compensation need be done.
1315 */
1316 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1317 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1318 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1319 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1320 use_scaling = 1;
1321 }
381d585c 1322 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1323}
1324
1325static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1326{
e26101b1 1327 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1328 vcpu->arch.virtual_tsc_mult,
1329 vcpu->arch.virtual_tsc_shift);
e26101b1 1330 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1331 return tsc;
1332}
1333
69b0049a 1334static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1335{
1336#ifdef CONFIG_X86_64
1337 bool vcpus_matched;
b48aa97e
MT		 1338 struct kvm_arch *ka = &vcpu->kvm->arch;
1339 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1340
1341 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1342 atomic_read(&vcpu->kvm->online_vcpus));
1343
7f187922
MT		 1344 /*
1345 * Once the masterclock is enabled, always perform request in
1346 * order to update it.
1347 *
1348 * In order to enable masterclock, the host clocksource must be TSC
1349 * and the vcpus need to have matched TSCs. When that happens,
1350 * perform request to enable masterclock.
1351 */
1352 if (ka->use_master_clock ||
1353 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1354 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1355
1356 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1357 atomic_read(&vcpu->kvm->online_vcpus),
1358 ka->use_master_clock, gtod->clock.vclock_mode);
1359#endif
1360}
1361
ba904635
WA		 1362static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1363{
1364 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1365 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1366}
1367
35181e86
HZ		 1368/*
1369 * Multiply tsc by a fixed point number represented by ratio.
1370 *
1371 * The most significant 64-N bits (mult) of ratio represent the
1372 * integral part of the fixed point number; the remaining N bits
1373 * (frac) represent the fractional part, ie. ratio represents a fixed
1374 * point number (mult + frac * 2^(-N)).
1375 *
1376 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1377 */
1378static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1379{
1380 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1381}
1382
1383u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1384{
1385 u64 _tsc = tsc;
1386 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1387
1388 if (ratio != kvm_default_tsc_scaling_ratio)
1389 _tsc = __scale_tsc(ratio, tsc);
1390
1391 return _tsc;
1392}
1393EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1394
07c1419a
HZ		 1395static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1396{
1397 u64 tsc;
1398
1399 tsc = kvm_scale_tsc(vcpu, rdtsc());
1400
1401 return target_tsc - tsc;
1402}
1403
8fe8ab46 1404void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1405{
1406 struct kvm *kvm = vcpu->kvm;
f38e098f 1407 u64 offset, ns, elapsed;
99e3e30a 1408 unsigned long flags;
02626b6a 1409 s64 usdiff;
b48aa97e 1410 bool matched;
0d3da0d2 1411 bool already_matched;
8fe8ab46 1412 u64 data = msr->data;
99e3e30a 1413
038f8c11 1414 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1415 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1416 ns = get_kernel_ns();
f38e098f 1417 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1418
03ba32ca 1419 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1420 int faulted = 0;
1421
03ba32ca
MT		 1422 /* n.b - signed multiplication and division required */
1423 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1424#ifdef CONFIG_X86_64
03ba32ca 1425 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1426#else
03ba32ca 1427 /* do_div() only does unsigned */
8915aa27
MT		 1428 asm("1: idivl %[divisor]\n"
1429 "2: xor %%edx, %%edx\n"
1430 " movl $0, %[faulted]\n"
1431 "3:\n"
1432 ".section .fixup,\"ax\"\n"
1433 "4: movl $1, %[faulted]\n"
1434 " jmp 3b\n"
1435 ".previous\n"
1436
1437 _ASM_EXTABLE(1b, 4b)
1438
1439 : "=A"(usdiff), [faulted] "=r" (faulted)
1440 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1441
5d3cb0f6 1442#endif
03ba32ca
MT		 1443 do_div(elapsed, 1000);
1444 usdiff -= elapsed;
1445 if (usdiff < 0)
1446 usdiff = -usdiff;
8915aa27
MT		 1447
1448 /* idivl overflow => difference is larger than USEC_PER_SEC */
1449 if (faulted)
1450 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1451 } else
1452 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1453
1454 /*
5d3cb0f6
ZA		 1455 * Special case: TSC write with a small delta (1 second) of virtual
1456 * cycle time against real time is interpreted as an attempt to
1457 * synchronize the CPU.
1458 *
1459 * For a reliable TSC, we can match TSC offsets, and for an unstable
1460 * TSC, we add elapsed time in this computation. We could let the
1461 * compensation code attempt to catch up if we fall behind, but
1462 * it's better to try to match offsets from the beginning.
1463 */
02626b6a 1464 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1465 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1466 if (!check_tsc_unstable()) {
e26101b1 1467 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1468 pr_debug("kvm: matched tsc offset for %llu\n", data);
1469 } else {
857e4099 1470 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1471 data += delta;
07c1419a 1472 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1473 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1474 }
b48aa97e 1475 matched = true;
0d3da0d2 1476 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1477 } else {
1478 /*
1479 * We split periods of matched TSC writes into generations.
1480 * For each generation, we track the original measured
1481 * nanosecond time, offset, and write, so if TSCs are in
1482 * sync, we can match exact offset, and if not, we can match
4a969980 1483 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1484 *
1485 * These values are tracked in kvm->arch.cur_xxx variables.
1486 */
1487 kvm->arch.cur_tsc_generation++;
1488 kvm->arch.cur_tsc_nsec = ns;
1489 kvm->arch.cur_tsc_write = data;
1490 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1491 matched = false;
0d3da0d2 1492 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1493 kvm->arch.cur_tsc_generation, data);
f38e098f 1494 }
e26101b1
ZA		 1495
1496 /*
1497 * We also track th most recent recorded KHZ, write and time to
1498 * allow the matching interval to be extended at each write.
1499 */
f38e098f
ZA		 1500 kvm->arch.last_tsc_nsec = ns;
1501 kvm->arch.last_tsc_write = data;
5d3cb0f6 1502 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1503
b183aa58 1504 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1505
1506 /* Keep track of which generation this VCPU has synchronized to */
1507 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1508 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1509 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1510
ba904635
WA		 1511 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1512 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1513 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1514 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1515
1516 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1517 if (!matched) {
b48aa97e 1518 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1519 } else if (!already_matched) {
1520 kvm->arch.nr_vcpus_matched_tsc++;
1521 }
b48aa97e
MT		 1522
1523 kvm_track_tsc_matching(vcpu);
1524 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1525}
e26101b1 1526
99e3e30a
ZA		 1527EXPORT_SYMBOL_GPL(kvm_write_tsc);
1528
d828199e
MT		 1529#ifdef CONFIG_X86_64
1530
1531static cycle_t read_tsc(void)
1532{
03b9730b
AL		 1533 cycle_t ret = (cycle_t)rdtsc_ordered();
1534 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1535
1536 if (likely(ret >= last))
1537 return ret;
1538
1539 /*
1540 * GCC likes to generate cmov here, but this branch is extremely
1541 * predictable (it's just a funciton of time and the likely is
1542 * very likely) and there's a data dependence, so force GCC
1543 * to generate a branch instead. I don't barrier() because
1544 * we don't actually need a barrier, and if this function
1545 * ever gets inlined it will generate worse code.
1546 */
1547 asm volatile ("");
1548 return last;
1549}
1550
1551static inline u64 vgettsc(cycle_t *cycle_now)
1552{
1553 long v;
1554 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1555
1556 *cycle_now = read_tsc();
1557
1558 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1559 return v * gtod->clock.mult;
1560}
1561
cbcf2dd3 1562static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1563{
cbcf2dd3 1564 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1565 unsigned long seq;
d828199e 1566 int mode;
cbcf2dd3 1567 u64 ns;
d828199e 1568
d828199e
MT		 1569 do {
1570 seq = read_seqcount_begin(&gtod->seq);
1571 mode = gtod->clock.vclock_mode;
cbcf2dd3 1572 ns = gtod->nsec_base;
d828199e
MT		 1573 ns += vgettsc(cycle_now);
1574 ns >>= gtod->clock.shift;
cbcf2dd3 1575 ns += gtod->boot_ns;
d828199e 1576 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1577 *t = ns;
d828199e
MT		 1578
1579 return mode;
1580}
1581
1582/* returns true if host is using tsc clocksource */
1583static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1584{
d828199e
MT		 1585 /* checked again under seqlock below */
1586 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1587 return false;
1588
cbcf2dd3 1589 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1590}
1591#endif
1592
1593/*
1594 *
b48aa97e
MT		 1595 * Assuming a stable TSC across physical CPUS, and a stable TSC
1596 * across virtual CPUs, the following condition is possible.
1597 * Each numbered line represents an event visible to both
d828199e
MT		 1598 * CPUs at the next numbered event.
1599 *
1600 * "timespecX" represents host monotonic time. "tscX" represents
1601 * RDTSC value.
1602 *
1603 * VCPU0 on CPU0 | VCPU1 on CPU1
1604 *
1605 * 1. read timespec0,tsc0
1606 * 2. | timespec1 = timespec0 + N
1607 * | tsc1 = tsc0 + M
1608 * 3. transition to guest | transition to guest
1609 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1610 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1611 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1612 *
1613 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1614 *
1615 * - ret0 < ret1
1616 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1617 * ...
1618 * - 0 < N - M => M < N
1619 *
1620 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1621 * always the case (the difference between two distinct xtime instances
1622 * might be smaller then the difference between corresponding TSC reads,
1623 * when updating guest vcpus pvclock areas).
1624 *
1625 * To avoid that problem, do not allow visibility of distinct
1626 * system_timestamp/tsc_timestamp values simultaneously: use a master
1627 * copy of host monotonic time values. Update that master copy
1628 * in lockstep.
1629 *
b48aa97e 1630 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1631 *
1632 */
1633
1634static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1635{
1636#ifdef CONFIG_X86_64
1637 struct kvm_arch *ka = &kvm->arch;
1638 int vclock_mode;
b48aa97e
MT		 1639 bool host_tsc_clocksource, vcpus_matched;
1640
1641 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1642 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1643
1644 /*
1645 * If the host uses TSC clock, then passthrough TSC as stable
1646 * to the guest.
1647 */
b48aa97e 1648 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1649 &ka->master_kernel_ns,
1650 &ka->master_cycle_now);
1651
16a96021 1652 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1653 && !backwards_tsc_observed
1654 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1655
d828199e
MT		 1656 if (ka->use_master_clock)
1657 atomic_set(&kvm_guest_has_master_clock, 1);
1658
1659 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1660 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1661 vcpus_matched);
d828199e
MT		 1662#endif
1663}
1664
2e762ff7
MT		 1665static void kvm_gen_update_masterclock(struct kvm *kvm)
1666{
1667#ifdef CONFIG_X86_64
1668 int i;
1669 struct kvm_vcpu *vcpu;
1670 struct kvm_arch *ka = &kvm->arch;
1671
1672 spin_lock(&ka->pvclock_gtod_sync_lock);
1673 kvm_make_mclock_inprogress_request(kvm);
1674 /* no guest entries from this point */
1675 pvclock_update_vm_gtod_copy(kvm);
1676
1677 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1678 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1679
1680 /* guest entries allowed */
1681 kvm_for_each_vcpu(i, vcpu, kvm)
1682 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1683
1684 spin_unlock(&ka->pvclock_gtod_sync_lock);
1685#endif
1686}
1687
34c238a1 1688static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1689{
d828199e 1690 unsigned long flags, this_tsc_khz;
18068523 1691 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1692 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1693 s64 kernel_ns;
d828199e 1694 u64 tsc_timestamp, host_tsc;
0b79459b 1695 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1696 u8 pvclock_flags;
d828199e
MT		 1697 bool use_master_clock;
1698
1699 kernel_ns = 0;
1700 host_tsc = 0;
18068523 1701
d828199e
MT		 1702 /*
1703 * If the host uses TSC clock, then passthrough TSC as stable
1704 * to the guest.
1705 */
1706 spin_lock(&ka->pvclock_gtod_sync_lock);
1707 use_master_clock = ka->use_master_clock;
1708 if (use_master_clock) {
1709 host_tsc = ka->master_cycle_now;
1710 kernel_ns = ka->master_kernel_ns;
1711 }
1712 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1713
1714 /* Keep irq disabled to prevent changes to the clock */
1715 local_irq_save(flags);
89cbc767 1716 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1717 if (unlikely(this_tsc_khz == 0)) {
1718 local_irq_restore(flags);
1719 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1720 return 1;
1721 }
d828199e 1722 if (!use_master_clock) {
4ea1636b 1723 host_tsc = rdtsc();
d828199e
MT		 1724 kernel_ns = get_kernel_ns();
1725 }
1726
1727 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1728
c285545f
ZA		 1729 /*
1730 * We may have to catch up the TSC to match elapsed wall clock
1731 * time for two reasons, even if kvmclock is used.
1732 * 1) CPU could have been running below the maximum TSC rate
1733 * 2) Broken TSC compensation resets the base at each VCPU
1734 * entry to avoid unknown leaps of TSC even when running
1735 * again on the same CPU. This may cause apparent elapsed
1736 * time to disappear, and the guest to stand still or run
1737 * very slowly.
1738 */
1739 if (vcpu->tsc_catchup) {
1740 u64 tsc = compute_guest_tsc(v, kernel_ns);
1741 if (tsc > tsc_timestamp) {
f1e2b260 1742 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1743 tsc_timestamp = tsc;
1744 }
50d0a0f9
GH		 1745 }
1746
18068523
GOC		 1747 local_irq_restore(flags);
1748
0b79459b 1749 if (!vcpu->pv_time_enabled)
c285545f 1750 return 0;
18068523 1751
e48672fa 1752 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1753 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1754 &vcpu->hv_clock.tsc_shift,
1755 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1756 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1757 }
1758
1759 /* With all the info we got, fill in the values */
1d5f066e 1760 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1761 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1762 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1763
09a0c3f1
OH		 1764 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1765 &guest_hv_clock, sizeof(guest_hv_clock))))
1766 return 0;
1767
5dca0d91
RK		 1768 /* This VCPU is paused, but it's legal for a guest to read another
1769 * VCPU's kvmclock, so we really have to follow the specification where
1770 * it says that version is odd if data is being modified, and even after
1771 * it is consistent.
1772 *
1773 * Version field updates must be kept separate. This is because
1774 * kvm_write_guest_cached might use a "rep movs" instruction, and
1775 * writes within a string instruction are weakly ordered. So there
1776 * are three writes overall.
1777 *
1778 * As a small optimization, only write the version field in the first
1779 * and third write. The vcpu->pv_time cache is still valid, because the
1780 * version field is the first in the struct.
18068523 1781 */
5dca0d91
RK		 1782 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1783
1784 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1785 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1786 &vcpu->hv_clock,
1787 sizeof(vcpu->hv_clock.version));
1788
1789 smp_wmb();
78c0337a
MT		 1790
1791 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1792 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1793
1794 if (vcpu->pvclock_set_guest_stopped_request) {
1795 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1796 vcpu->pvclock_set_guest_stopped_request = false;
1797 }
1798
d828199e
MT		 1799 /* If the host uses TSC clocksource, then it is stable */
1800 if (use_master_clock)
1801 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1802
78c0337a
MT		 1803 vcpu->hv_clock.flags = pvclock_flags;
1804
ce1a5e60
DM		 1805 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1806
0b79459b
AH		 1807 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1808 &vcpu->hv_clock,
1809 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1810
1811 smp_wmb();
1812
1813 vcpu->hv_clock.version++;
1814 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1815 &vcpu->hv_clock,
1816 sizeof(vcpu->hv_clock.version));
8cfdc000 1817 return 0;
c8076604
GH		 1818}
1819
0061d53d
MT		 1820/*
1821 * kvmclock updates which are isolated to a given vcpu, such as
1822 * vcpu->cpu migration, should not allow system_timestamp from
1823 * the rest of the vcpus to remain static. Otherwise ntp frequency
1824 * correction applies to one vcpu's system_timestamp but not
1825 * the others.
1826 *
1827 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1828 * We need to rate-limit these requests though, as they can
1829 * considerably slow guests that have a large number of vcpus.
1830 * The time for a remote vcpu to update its kvmclock is bound
1831 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1832 */
1833
7e44e449
AJ		 1834#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1835
1836static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1837{
1838 int i;
7e44e449
AJ		 1839 struct delayed_work *dwork = to_delayed_work(work);
1840 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1841 kvmclock_update_work);
1842 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1843 struct kvm_vcpu *vcpu;
1844
1845 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1846 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1847 kvm_vcpu_kick(vcpu);
1848 }
1849}
1850
7e44e449
AJ		 1851static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1852{
1853 struct kvm *kvm = v->kvm;
1854
105b21bb 1855 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1856 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1857 KVMCLOCK_UPDATE_DELAY);
1858}
1859
332967a3
AJ		 1860#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1861
1862static void kvmclock_sync_fn(struct work_struct *work)
1863{
1864 struct delayed_work *dwork = to_delayed_work(work);
1865 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1866 kvmclock_sync_work);
1867 struct kvm *kvm = container_of(ka, struct kvm, arch);
1868
630994b3
MT		 1869 if (!kvmclock_periodic_sync)
1870 return;
1871
332967a3
AJ		 1872 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1873 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1874 KVMCLOCK_SYNC_PERIOD);
1875}
1876
890ca9ae 1877static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1878{
890ca9ae
HY		 1879 u64 mcg_cap = vcpu->arch.mcg_cap;
1880 unsigned bank_num = mcg_cap & 0xff;
1881
15c4a640 1882 switch (msr) {
15c4a640 1883 case MSR_IA32_MCG_STATUS:
890ca9ae 1884 vcpu->arch.mcg_status = data;
15c4a640 1885 break;
c7ac679c 1886 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1887 if (!(mcg_cap & MCG_CTL_P))
1888 return 1;
1889 if (data != 0 && data != ~(u64)0)
1890 return -1;
1891 vcpu->arch.mcg_ctl = data;
1892 break;
1893 default:
1894 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1895 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1896 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1897 /* only 0 or all 1s can be written to IA32_MCi_CTL
1898 * some Linux kernels though clear bit 10 in bank 4 to
1899 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1900 * this to avoid an uncatched #GP in the guest
1901 */
890ca9ae 1902 if ((offset & 0x3) == 0 &&
114be429 1903 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1904 return -1;
1905 vcpu->arch.mce_banks[offset] = data;
1906 break;
1907 }
1908 return 1;
1909 }
1910 return 0;
1911}
1912
ffde22ac
ES		 1913static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1914{
1915 struct kvm *kvm = vcpu->kvm;
1916 int lm = is_long_mode(vcpu);
1917 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1918 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1919 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1920 : kvm->arch.xen_hvm_config.blob_size_32;
1921 u32 page_num = data & ~PAGE_MASK;
1922 u64 page_addr = data & PAGE_MASK;
1923 u8 *page;
1924 int r;
1925
1926 r = -E2BIG;
1927 if (page_num >= blob_size)
1928 goto out;
1929 r = -ENOMEM;
ff5c2c03
SL		 1930 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1931 if (IS_ERR(page)) {
1932 r = PTR_ERR(page);
ffde22ac 1933 goto out;
ff5c2c03 1934 }
54bf36aa 1935 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1936 goto out_free;
1937 r = 0;
1938out_free:
1939 kfree(page);
1940out:
1941 return r;
1942}
1943
344d9588
GN		 1944static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1945{
1946 gpa_t gpa = data & ~0x3f;
1947
4a969980 1948 /* Bits 2:5 are reserved, Should be zero */
6adba527 1949 if (data & 0x3c)
344d9588
GN		 1950 return 1;
1951
1952 vcpu->arch.apf.msr_val = data;
1953
1954 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1955 kvm_clear_async_pf_completion_queue(vcpu);
1956 kvm_async_pf_hash_reset(vcpu);
1957 return 0;
1958 }
1959
8f964525
AH		 1960 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1961 sizeof(u32)))
344d9588
GN		 1962 return 1;
1963
6adba527 1964 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1965 kvm_async_pf_wakeup_all(vcpu);
1966 return 0;
1967}
1968
12f9a48f
GC		 1969static void kvmclock_reset(struct kvm_vcpu *vcpu)
1970{
0b79459b 1971 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1972}
1973
c9aaa895
GC		 1974static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1975{
1976 u64 delta;
1977
1978 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1979 return;
1980
1981 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1982 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1983 vcpu->arch.st.accum_steal = delta;
1984}
1985
1986static void record_steal_time(struct kvm_vcpu *vcpu)
1987{
7cae2bed
MT		 1988 accumulate_steal_time(vcpu);
1989
c9aaa895
GC		 1990 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1991 return;
1992
1993 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1994 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1995 return;
1996
1997 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1998 vcpu->arch.st.steal.version += 2;
1999 vcpu->arch.st.accum_steal = 0;
2000
2001 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2002 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2003}
2004
8fe8ab46 2005int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2006{
5753785f 2007 bool pr = false;
8fe8ab46
WA		 2008 u32 msr = msr_info->index;
2009 u64 data = msr_info->data;
5753785f 2010
15c4a640 2011 switch (msr) {
2e32b719
BP		 2012 case MSR_AMD64_NB_CFG:
2013 case MSR_IA32_UCODE_REV:
2014 case MSR_IA32_UCODE_WRITE:
2015 case MSR_VM_HSAVE_PA:
2016 case MSR_AMD64_PATCH_LOADER:
2017 case MSR_AMD64_BU_CFG2:
2018 break;
2019
15c4a640 2020 case MSR_EFER:
b69e8cae 2021 return set_efer(vcpu, data);
8f1589d9
AP		 2022 case MSR_K7_HWCR:
2023 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2024 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2025 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2026 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2027 if (data != 0) {
a737f256
CD		 2028 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2029 data);
8f1589d9
AP		 2030 return 1;
2031 }
15c4a640 2032 break;
f7c6d140
AP		 2033 case MSR_FAM10H_MMIO_CONF_BASE:
2034 if (data != 0) {
a737f256
CD		 2035 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2036 "0x%llx\n", data);
f7c6d140
AP		 2037 return 1;
2038 }
15c4a640 2039 break;
b5e2fec0
AG		 2040 case MSR_IA32_DEBUGCTLMSR:
2041 if (!data) {
2042 /* We support the non-activated case already */
2043 break;
2044 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2045 /* Values other than LBR and BTF are vendor-specific,
2046 thus reserved and should throw a #GP */
2047 return 1;
2048 }
a737f256
CD		 2049 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2050 __func__, data);
b5e2fec0 2051 break;
9ba075a6 2052 case 0x200 ... 0x2ff:
ff53604b 2053 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2054 case MSR_IA32_APICBASE:
58cb628d 2055 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2056 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2057 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2058 case MSR_IA32_TSCDEADLINE:
2059 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2060 break;
ba904635
WA		 2061 case MSR_IA32_TSC_ADJUST:
2062 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2063 if (!msr_info->host_initiated) {
d913b904 2064 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2065 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2066 }
2067 vcpu->arch.ia32_tsc_adjust_msr = data;
2068 }
2069 break;
15c4a640 2070 case MSR_IA32_MISC_ENABLE:
ad312c7c 2071 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2072 break;
64d60670
PB		 2073 case MSR_IA32_SMBASE:
2074 if (!msr_info->host_initiated)
2075 return 1;
2076 vcpu->arch.smbase = data;
2077 break;
11c6bffa 2078 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2079 case MSR_KVM_WALL_CLOCK:
2080 vcpu->kvm->arch.wall_clock = data;
2081 kvm_write_wall_clock(vcpu->kvm, data);
2082 break;
11c6bffa 2083 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2084 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2085 u64 gpa_offset;
54750f2c
MT		 2086 struct kvm_arch *ka = &vcpu->kvm->arch;
2087
12f9a48f 2088 kvmclock_reset(vcpu);
18068523 2089
54750f2c
MT		 2090 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2091 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2092
2093 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2094 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2095 &vcpu->requests);
2096
2097 ka->boot_vcpu_runs_old_kvmclock = tmp;
2098 }
2099
18068523 2100 vcpu->arch.time = data;
0061d53d 2101 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2102
2103 /* we verify if the enable bit is set... */
2104 if (!(data & 1))
2105 break;
2106
0b79459b 2107 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2108
0b79459b 2109 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2110 &vcpu->arch.pv_time, data & ~1ULL,
2111 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2112 vcpu->arch.pv_time_enabled = false;
2113 else
2114 vcpu->arch.pv_time_enabled = true;
32cad84f 2115
18068523
GOC		 2116 break;
2117 }
344d9588
GN		 2118 case MSR_KVM_ASYNC_PF_EN:
2119 if (kvm_pv_enable_async_pf(vcpu, data))
2120 return 1;
2121 break;
c9aaa895
GC		 2122 case MSR_KVM_STEAL_TIME:
2123
2124 if (unlikely(!sched_info_on()))
2125 return 1;
2126
2127 if (data & KVM_STEAL_RESERVED_MASK)
2128 return 1;
2129
2130 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2131 data & KVM_STEAL_VALID_BITS,
2132 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2133 return 1;
2134
2135 vcpu->arch.st.msr_val = data;
2136
2137 if (!(data & KVM_MSR_ENABLED))
2138 break;
2139
c9aaa895
GC		 2140 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2141
2142 break;
ae7a2a3f
MT		 2143 case MSR_KVM_PV_EOI_EN:
2144 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2145 return 1;
2146 break;
c9aaa895 2147
890ca9ae
HY		 2148 case MSR_IA32_MCG_CTL:
2149 case MSR_IA32_MCG_STATUS:
81760dcc 2150 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2151 return set_msr_mce(vcpu, msr, data);
71db6023 2152
6912ac32
WH		 2153 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2154 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2155 pr = true; /* fall through */
2156 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2157 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2158 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2159 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2160
2161 if (pr || data != 0)
a737f256
CD		 2162 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2163 "0x%x data 0x%llx\n", msr, data);
5753785f 2164 break;
84e0cefa
JS		 2165 case MSR_K7_CLK_CTL:
2166 /*
2167 * Ignore all writes to this no longer documented MSR.
2168 * Writes are only relevant for old K7 processors,
2169 * all pre-dating SVM, but a recommended workaround from
4a969980 2170 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2171 * affected processor models on the command line, hence
2172 * the need to ignore the workaround.
2173 */
2174 break;
55cd8e5a 2175 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2176 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2177 case HV_X64_MSR_CRASH_CTL:
2178 return kvm_hv_set_msr_common(vcpu, msr, data,
2179 msr_info->host_initiated);
91c9c3ed 2180 case MSR_IA32_BBL_CR_CTL3:
2181 /* Drop writes to this legacy MSR -- see rdmsr
2182 * counterpart for further detail.
2183 */
a737f256 2184 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2185 break;
2b036c6b
BO		 2186 case MSR_AMD64_OSVW_ID_LENGTH:
2187 if (!guest_cpuid_has_osvw(vcpu))
2188 return 1;
2189 vcpu->arch.osvw.length = data;
2190 break;
2191 case MSR_AMD64_OSVW_STATUS:
2192 if (!guest_cpuid_has_osvw(vcpu))
2193 return 1;
2194 vcpu->arch.osvw.status = data;
2195 break;
15c4a640 2196 default:
ffde22ac
ES		 2197 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2198 return xen_hvm_config(vcpu, data);
c6702c9d 2199 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2200 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2201 if (!ignore_msrs) {
a737f256
CD		 2202 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2203 msr, data);
ed85c068
AP		 2204 return 1;
2205 } else {
a737f256
CD		 2206 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2207 msr, data);
ed85c068
AP		 2208 break;
2209 }
15c4a640
CO		 2210 }
2211 return 0;
2212}
2213EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2214
2215
2216/*
2217 * Reads an msr value (of 'msr_index') into 'pdata'.
2218 * Returns 0 on success, non-0 otherwise.
2219 * Assumes vcpu_load() was already called.
2220 */
609e36d3 2221int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2222{
609e36d3 2223 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2224}
ff651cb6 2225EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2226
890ca9ae 2227static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2228{
2229 u64 data;
890ca9ae
HY		 2230 u64 mcg_cap = vcpu->arch.mcg_cap;
2231 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2232
2233 switch (msr) {
15c4a640
CO		 2234 case MSR_IA32_P5_MC_ADDR:
2235 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2236 data = 0;
2237 break;
15c4a640 2238 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2239 data = vcpu->arch.mcg_cap;
2240 break;
c7ac679c 2241 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2242 if (!(mcg_cap & MCG_CTL_P))
2243 return 1;
2244 data = vcpu->arch.mcg_ctl;
2245 break;
2246 case MSR_IA32_MCG_STATUS:
2247 data = vcpu->arch.mcg_status;
2248 break;
2249 default:
2250 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2251 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2252 u32 offset = msr - MSR_IA32_MC0_CTL;
2253 data = vcpu->arch.mce_banks[offset];
2254 break;
2255 }
2256 return 1;
2257 }
2258 *pdata = data;
2259 return 0;
2260}
2261
609e36d3 2262int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2263{
609e36d3 2264 switch (msr_info->index) {
890ca9ae 2265 case MSR_IA32_PLATFORM_ID:
15c4a640 2266 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2267 case MSR_IA32_DEBUGCTLMSR:
2268 case MSR_IA32_LASTBRANCHFROMIP:
2269 case MSR_IA32_LASTBRANCHTOIP:
2270 case MSR_IA32_LASTINTFROMIP:
2271 case MSR_IA32_LASTINTTOIP:
60af2ecd 2272 case MSR_K8_SYSCFG:
3afb1121
PB		 2273 case MSR_K8_TSEG_ADDR:
2274 case MSR_K8_TSEG_MASK:
60af2ecd 2275 case MSR_K7_HWCR:
61a6bd67 2276 case MSR_VM_HSAVE_PA:
1fdbd48c 2277 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2278 case MSR_AMD64_NB_CFG:
f7c6d140 2279 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2280 case MSR_AMD64_BU_CFG2:
609e36d3 2281 msr_info->data = 0;
15c4a640 2282 break;
6912ac32
WH		 2283 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2284 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2285 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2286 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2287 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2288 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2289 msr_info->data = 0;
5753785f 2290 break;
742bc670 2291 case MSR_IA32_UCODE_REV:
609e36d3 2292 msr_info->data = 0x100000000ULL;
742bc670 2293 break;
9ba075a6 2294 case MSR_MTRRcap:
9ba075a6 2295 case 0x200 ... 0x2ff:
ff53604b 2296 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2297 case 0xcd: /* fsb frequency */
609e36d3 2298 msr_info->data = 3;
15c4a640 2299 break;
7b914098
JS		 2300 /*
2301 * MSR_EBC_FREQUENCY_ID
2302 * Conservative value valid for even the basic CPU models.
2303 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2304 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2305 * and 266MHz for model 3, or 4. Set Core Clock
2306 * Frequency to System Bus Frequency Ratio to 1 (bits
2307 * 31:24) even though these are only valid for CPU
2308 * models > 2, however guests may end up dividing or
2309 * multiplying by zero otherwise.
2310 */
2311 case MSR_EBC_FREQUENCY_ID:
609e36d3 2312 msr_info->data = 1 << 24;
7b914098 2313 break;
15c4a640 2314 case MSR_IA32_APICBASE:
609e36d3 2315 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2316 break;
0105d1a5 2317 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2318 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2319 break;
a3e06bbe 2320 case MSR_IA32_TSCDEADLINE:
609e36d3 2321 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2322 break;
ba904635 2323 case MSR_IA32_TSC_ADJUST:
609e36d3 2324 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2325 break;
15c4a640 2326 case MSR_IA32_MISC_ENABLE:
609e36d3 2327 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2328 break;
64d60670
PB		 2329 case MSR_IA32_SMBASE:
2330 if (!msr_info->host_initiated)
2331 return 1;
2332 msr_info->data = vcpu->arch.smbase;
15c4a640 2333 break;
847f0ad8
AG		 2334 case MSR_IA32_PERF_STATUS:
2335 /* TSC increment by tick */
609e36d3 2336 msr_info->data = 1000ULL;
847f0ad8 2337 /* CPU multiplier */
b0996ae4 2338 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2339 break;
15c4a640 2340 case MSR_EFER:
609e36d3 2341 msr_info->data = vcpu->arch.efer;
15c4a640 2342 break;
18068523 2343 case MSR_KVM_WALL_CLOCK:
11c6bffa 2344 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2345 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2346 break;
2347 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2348 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2349 msr_info->data = vcpu->arch.time;
18068523 2350 break;
344d9588 2351 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2352 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2353 break;
c9aaa895 2354 case MSR_KVM_STEAL_TIME:
609e36d3 2355 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2356 break;
1d92128f 2357 case MSR_KVM_PV_EOI_EN:
609e36d3 2358 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2359 break;
890ca9ae
HY		 2360 case MSR_IA32_P5_MC_ADDR:
2361 case MSR_IA32_P5_MC_TYPE:
2362 case MSR_IA32_MCG_CAP:
2363 case MSR_IA32_MCG_CTL:
2364 case MSR_IA32_MCG_STATUS:
81760dcc 2365 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2366 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2367 case MSR_K7_CLK_CTL:
2368 /*
2369 * Provide expected ramp-up count for K7. All other
2370 * are set to zero, indicating minimum divisors for
2371 * every field.
2372 *
2373 * This prevents guest kernels on AMD host with CPU
2374 * type 6, model 8 and higher from exploding due to
2375 * the rdmsr failing.
2376 */
609e36d3 2377 msr_info->data = 0x20000000;
84e0cefa 2378 break;
55cd8e5a 2379 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2380 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2381 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2382 return kvm_hv_get_msr_common(vcpu,
2383 msr_info->index, &msr_info->data);
55cd8e5a 2384 break;
91c9c3ed 2385 case MSR_IA32_BBL_CR_CTL3:
2386 /* This legacy MSR exists but isn't fully documented in current
2387 * silicon. It is however accessed by winxp in very narrow
2388 * scenarios where it sets bit #19, itself documented as
2389 * a "reserved" bit. Best effort attempt to source coherent
2390 * read data here should the balance of the register be
2391 * interpreted by the guest:
2392 *
2393 * L2 cache control register 3: 64GB range, 256KB size,
2394 * enabled, latency 0x1, configured
2395 */
609e36d3 2396 msr_info->data = 0xbe702111;
91c9c3ed 2397 break;
2b036c6b
BO		 2398 case MSR_AMD64_OSVW_ID_LENGTH:
2399 if (!guest_cpuid_has_osvw(vcpu))
2400 return 1;
609e36d3 2401 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2402 break;
2403 case MSR_AMD64_OSVW_STATUS:
2404 if (!guest_cpuid_has_osvw(vcpu))
2405 return 1;
609e36d3 2406 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2407 break;
15c4a640 2408 default:
c6702c9d 2409 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2410 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2411 if (!ignore_msrs) {
609e36d3 2412 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2413 return 1;
2414 } else {
609e36d3
PB		 2415 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2416 msr_info->data = 0;
ed85c068
AP		 2417 }
2418 break;
15c4a640 2419 }
15c4a640
CO		 2420 return 0;
2421}
2422EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2423
313a3dc7
CO		 2424/*
2425 * Read or write a bunch of msrs. All parameters are kernel addresses.
2426 *
2427 * @return number of msrs set successfully.
2428 */
2429static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2430 struct kvm_msr_entry *entries,
2431 int (*do_msr)(struct kvm_vcpu *vcpu,
2432 unsigned index, u64 *data))
2433{
f656ce01 2434 int i, idx;
313a3dc7 2435
f656ce01 2436 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2437 for (i = 0; i < msrs->nmsrs; ++i)
2438 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2439 break;
f656ce01 2440 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2441
313a3dc7
CO		 2442 return i;
2443}
2444
2445/*
2446 * Read or write a bunch of msrs. Parameters are user addresses.
2447 *
2448 * @return number of msrs set successfully.
2449 */
2450static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2451 int (*do_msr)(struct kvm_vcpu *vcpu,
2452 unsigned index, u64 *data),
2453 int writeback)
2454{
2455 struct kvm_msrs msrs;
2456 struct kvm_msr_entry *entries;
2457 int r, n;
2458 unsigned size;
2459
2460 r = -EFAULT;
2461 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2462 goto out;
2463
2464 r = -E2BIG;
2465 if (msrs.nmsrs >= MAX_IO_MSRS)
2466 goto out;
2467
313a3dc7 2468 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2469 entries = memdup_user(user_msrs->entries, size);
2470 if (IS_ERR(entries)) {
2471 r = PTR_ERR(entries);
313a3dc7 2472 goto out;
ff5c2c03 2473 }
313a3dc7
CO		 2474
2475 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2476 if (r < 0)
2477 goto out_free;
2478
2479 r = -EFAULT;
2480 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2481 goto out_free;
2482
2483 r = n;
2484
2485out_free:
7a73c028 2486 kfree(entries);
313a3dc7
CO		 2487out:
2488 return r;
2489}
2490
784aa3d7 2491int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2492{
2493 int r;
2494
2495 switch (ext) {
2496 case KVM_CAP_IRQCHIP:
2497 case KVM_CAP_HLT:
2498 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2499 case KVM_CAP_SET_TSS_ADDR:
07716717 2500 case KVM_CAP_EXT_CPUID:
9c15bb1d 2501 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2502 case KVM_CAP_CLOCKSOURCE:
7837699f 2503 case KVM_CAP_PIT:
a28e4f5a 2504 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2505 case KVM_CAP_MP_STATE:
ed848624 2506 case KVM_CAP_SYNC_MMU:
a355c85c 2507 case KVM_CAP_USER_NMI:
52d939a0 2508 case KVM_CAP_REINJECT_CONTROL:
4925663a 2509 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2510 case KVM_CAP_IOEVENTFD:
f848a5a8 2511 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2512 case KVM_CAP_PIT2:
e9f42757 2513 case KVM_CAP_PIT_STATE2:
b927a3ce 2514 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2515 case KVM_CAP_XEN_HVM:
afbcf7ab 2516 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2517 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2518 case KVM_CAP_HYPERV:
10388a07 2519 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2520 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2521 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2522 case KVM_CAP_DEBUGREGS:
d2be1651 2523 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2524 case KVM_CAP_XSAVE:
344d9588 2525 case KVM_CAP_ASYNC_PF:
92a1f12d 2526 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2527 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2528 case KVM_CAP_READONLY_MEM:
5f66b620 2529 case KVM_CAP_HYPERV_TIME:
100943c5 2530 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2531 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2532 case KVM_CAP_ENABLE_CAP_VM:
2533 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2534 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2535 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2536#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2537 case KVM_CAP_ASSIGN_DEV_IRQ:
2538 case KVM_CAP_PCI_2_3:
2539#endif
018d00d2
ZX		 2540 r = 1;
2541 break;
6d396b55
PB		 2542 case KVM_CAP_X86_SMM:
2543 /* SMBASE is usually relocated above 1M on modern chipsets,
2544 * and SMM handlers might indeed rely on 4G segment limits,
2545 * so do not report SMM to be available if real mode is
2546 * emulated via vm86 mode. Still, do not go to great lengths
2547 * to avoid userspace's usage of the feature, because it is a
2548 * fringe case that is not enabled except via specific settings
2549 * of the module parameters.
2550 */
2551 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2552 break;
542472b5
LV		 2553 case KVM_CAP_COALESCED_MMIO:
2554 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2555 break;
774ead3a
AK		 2556 case KVM_CAP_VAPIC:
2557 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2558 break;
f725230a 2559 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2560 r = KVM_SOFT_MAX_VCPUS;
2561 break;
2562 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2563 r = KVM_MAX_VCPUS;
2564 break;
a988b910 2565 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2566 r = KVM_USER_MEM_SLOTS;
a988b910 2567 break;
a68a6a72
MT		 2568 case KVM_CAP_PV_MMU: /* obsolete */
2569 r = 0;
2f333bcb 2570 break;
4cee4b72 2571#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2572 case KVM_CAP_IOMMU:
a1b60c1c 2573 r = iommu_present(&pci_bus_type);
62c476c7 2574 break;
4cee4b72 2575#endif
890ca9ae
HY		 2576 case KVM_CAP_MCE:
2577 r = KVM_MAX_MCE_BANKS;
2578 break;
2d5b5a66
SY		 2579 case KVM_CAP_XCRS:
2580 r = cpu_has_xsave;
2581 break;
92a1f12d
JR		 2582 case KVM_CAP_TSC_CONTROL:
2583 r = kvm_has_tsc_control;
2584 break;
018d00d2
ZX		 2585 default:
2586 r = 0;
2587 break;
2588 }
2589 return r;
2590
2591}
2592
043405e1
CO		 2593long kvm_arch_dev_ioctl(struct file *filp,
2594 unsigned int ioctl, unsigned long arg)
2595{
2596 void __user *argp = (void __user *)arg;
2597 long r;
2598
2599 switch (ioctl) {
2600 case KVM_GET_MSR_INDEX_LIST: {
2601 struct kvm_msr_list __user *user_msr_list = argp;
2602 struct kvm_msr_list msr_list;
2603 unsigned n;
2604
2605 r = -EFAULT;
2606 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2607 goto out;
2608 n = msr_list.nmsrs;
62ef68bb 2609 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2610 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2611 goto out;
2612 r = -E2BIG;
e125e7b6 2613 if (n < msr_list.nmsrs)
043405e1
CO		 2614 goto out;
2615 r = -EFAULT;
2616 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2617 num_msrs_to_save * sizeof(u32)))
2618 goto out;
e125e7b6 2619 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2620 &emulated_msrs,
62ef68bb 2621 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2622 goto out;
2623 r = 0;
2624 break;
2625 }
9c15bb1d
BP		 2626 case KVM_GET_SUPPORTED_CPUID:
2627 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2628 struct kvm_cpuid2 __user *cpuid_arg = argp;
2629 struct kvm_cpuid2 cpuid;
2630
2631 r = -EFAULT;
2632 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2633 goto out;
9c15bb1d
BP		 2634
2635 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2636 ioctl);
674eea0f
AK		 2637 if (r)
2638 goto out;
2639
2640 r = -EFAULT;
2641 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2642 goto out;
2643 r = 0;
2644 break;
2645 }
890ca9ae
HY		 2646 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2647 u64 mce_cap;
2648
2649 mce_cap = KVM_MCE_CAP_SUPPORTED;
2650 r = -EFAULT;
2651 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2652 goto out;
2653 r = 0;
2654 break;
2655 }
043405e1
CO		 2656 default:
2657 r = -EINVAL;
2658 }
2659out:
2660 return r;
2661}
2662
f5f48ee1
SY		 2663static void wbinvd_ipi(void *garbage)
2664{
2665 wbinvd();
2666}
2667
2668static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2669{
e0f0bbc5 2670 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2671}
2672
313a3dc7
CO		 2673void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2674{
f5f48ee1
SY		 2675 /* Address WBINVD may be executed by guest */
2676 if (need_emulate_wbinvd(vcpu)) {
2677 if (kvm_x86_ops->has_wbinvd_exit())
2678 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2679 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2680 smp_call_function_single(vcpu->cpu,
2681 wbinvd_ipi, NULL, 1);
2682 }
2683
313a3dc7 2684 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2685
0dd6a6ed
ZA		 2686 /* Apply any externally detected TSC adjustments (due to suspend) */
2687 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2688 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2689 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2690 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2691 }
8f6055cb 2692
48434c20 2693 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2694 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2695 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2696 if (tsc_delta < 0)
2697 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2698 if (check_tsc_unstable()) {
07c1419a 2699 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2700 vcpu->arch.last_guest_tsc);
2701 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2702 vcpu->arch.tsc_catchup = 1;
c285545f 2703 }
d98d07ca
MT		 2704 /*
2705 * On a host with synchronized TSC, there is no need to update
2706 * kvmclock on vcpu->cpu migration
2707 */
2708 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2709 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2710 if (vcpu->cpu != cpu)
2711 kvm_migrate_timers(vcpu);
e48672fa 2712 vcpu->cpu = cpu;
6b7d7e76 2713 }
c9aaa895 2714
c9aaa895 2715 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2716}
2717
2718void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2719{
02daab21 2720 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2721 kvm_put_guest_fpu(vcpu);
4ea1636b 2722 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2723}
2724
313a3dc7
CO		 2725static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2726 struct kvm_lapic_state *s)
2727{
5a71785d 2728 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2729 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2730
2731 return 0;
2732}
2733
2734static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2735 struct kvm_lapic_state *s)
2736{
64eb0620 2737 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2738 update_cr8_intercept(vcpu);
313a3dc7
CO		 2739
2740 return 0;
2741}
2742
f77bc6a4
ZX		 2743static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2744 struct kvm_interrupt *irq)
2745{
02cdb50f 2746 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2747 return -EINVAL;
1c1a9ce9
SR		 2748
2749 if (!irqchip_in_kernel(vcpu->kvm)) {
2750 kvm_queue_interrupt(vcpu, irq->irq, false);
2751 kvm_make_request(KVM_REQ_EVENT, vcpu);
2752 return 0;
2753 }
2754
2755 /*
2756 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2757 * fail for in-kernel 8259.
2758 */
2759 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2760 return -ENXIO;
f77bc6a4 2761
1c1a9ce9
SR		 2762 if (vcpu->arch.pending_external_vector != -1)
2763 return -EEXIST;
f77bc6a4 2764
1c1a9ce9 2765 vcpu->arch.pending_external_vector = irq->irq;
f77bc6a4
ZX		 2766 return 0;
2767}
2768
c4abb7c9
JK		 2769static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2770{
c4abb7c9 2771 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2772
2773 return 0;
2774}
2775
f077825a
PB		 2776static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2777{
64d60670
PB		 2778 kvm_make_request(KVM_REQ_SMI, vcpu);
2779
f077825a
PB		 2780 return 0;
2781}
2782
b209749f
AK		 2783static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2784 struct kvm_tpr_access_ctl *tac)
2785{
2786 if (tac->flags)
2787 return -EINVAL;
2788 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2789 return 0;
2790}
2791
890ca9ae
HY		 2792static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2793 u64 mcg_cap)
2794{
2795 int r;
2796 unsigned bank_num = mcg_cap & 0xff, bank;
2797
2798 r = -EINVAL;
a9e38c3e 2799 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2800 goto out;
2801 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2802 goto out;
2803 r = 0;
2804 vcpu->arch.mcg_cap = mcg_cap;
2805 /* Init IA32_MCG_CTL to all 1s */
2806 if (mcg_cap & MCG_CTL_P)
2807 vcpu->arch.mcg_ctl = ~(u64)0;
2808 /* Init IA32_MCi_CTL to all 1s */
2809 for (bank = 0; bank < bank_num; bank++)
2810 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2811out:
2812 return r;
2813}
2814
2815static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2816 struct kvm_x86_mce *mce)
2817{
2818 u64 mcg_cap = vcpu->arch.mcg_cap;
2819 unsigned bank_num = mcg_cap & 0xff;
2820 u64 *banks = vcpu->arch.mce_banks;
2821
2822 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2823 return -EINVAL;
2824 /*
2825 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2826 * reporting is disabled
2827 */
2828 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2829 vcpu->arch.mcg_ctl != ~(u64)0)
2830 return 0;
2831 banks += 4 * mce->bank;
2832 /*
2833 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2834 * reporting is disabled for the bank
2835 */
2836 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2837 return 0;
2838 if (mce->status & MCI_STATUS_UC) {
2839 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2840 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2841 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2842 return 0;
2843 }
2844 if (banks[1] & MCI_STATUS_VAL)
2845 mce->status |= MCI_STATUS_OVER;
2846 banks[2] = mce->addr;
2847 banks[3] = mce->misc;
2848 vcpu->arch.mcg_status = mce->mcg_status;
2849 banks[1] = mce->status;
2850 kvm_queue_exception(vcpu, MC_VECTOR);
2851 } else if (!(banks[1] & MCI_STATUS_VAL)
2852 || !(banks[1] & MCI_STATUS_UC)) {
2853 if (banks[1] & MCI_STATUS_VAL)
2854 mce->status |= MCI_STATUS_OVER;
2855 banks[2] = mce->addr;
2856 banks[3] = mce->misc;
2857 banks[1] = mce->status;
2858 } else
2859 banks[1] |= MCI_STATUS_OVER;
2860 return 0;
2861}
2862
3cfc3092
JK		 2863static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2864 struct kvm_vcpu_events *events)
2865{
7460fb4a 2866 process_nmi(vcpu);
03b82a30
JK		 2867 events->exception.injected =
2868 vcpu->arch.exception.pending &&
2869 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2870 events->exception.nr = vcpu->arch.exception.nr;
2871 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2872 events->exception.pad = 0;
3cfc3092
JK		 2873 events->exception.error_code = vcpu->arch.exception.error_code;
2874
03b82a30
JK		 2875 events->interrupt.injected =
2876 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2877 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2878 events->interrupt.soft = 0;
37ccdcbe 2879 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2880
2881 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2882 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2883 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2884 events->nmi.pad = 0;
3cfc3092 2885
66450a21 2886 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2887
f077825a
PB		 2888 events->smi.smm = is_smm(vcpu);
2889 events->smi.pending = vcpu->arch.smi_pending;
2890 events->smi.smm_inside_nmi =
2891 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2892 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2893
dab4b911 2894 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2895 | KVM_VCPUEVENT_VALID_SHADOW
2896 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2897 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2898}
2899
2900static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2901 struct kvm_vcpu_events *events)
2902{
dab4b911 2903 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2904 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2905 | KVM_VCPUEVENT_VALID_SHADOW
2906 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2907 return -EINVAL;
2908
7460fb4a 2909 process_nmi(vcpu);
3cfc3092
JK		 2910 vcpu->arch.exception.pending = events->exception.injected;
2911 vcpu->arch.exception.nr = events->exception.nr;
2912 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2913 vcpu->arch.exception.error_code = events->exception.error_code;
2914
2915 vcpu->arch.interrupt.pending = events->interrupt.injected;
2916 vcpu->arch.interrupt.nr = events->interrupt.nr;
2917 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2918 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2919 kvm_x86_ops->set_interrupt_shadow(vcpu,
2920 events->interrupt.shadow);
3cfc3092
JK		 2921
2922 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2923 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2924 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2925 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2926
66450a21
JK		 2927 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2928 kvm_vcpu_has_lapic(vcpu))
2929 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2930
f077825a
PB		 2931 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2932 if (events->smi.smm)
2933 vcpu->arch.hflags |= HF_SMM_MASK;
2934 else
2935 vcpu->arch.hflags &= ~HF_SMM_MASK;
2936 vcpu->arch.smi_pending = events->smi.pending;
2937 if (events->smi.smm_inside_nmi)
2938 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2939 else
2940 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2941 if (kvm_vcpu_has_lapic(vcpu)) {
2942 if (events->smi.latched_init)
2943 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2944 else
2945 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2946 }
2947 }
2948
3842d135
AK		 2949 kvm_make_request(KVM_REQ_EVENT, vcpu);
2950
3cfc3092
JK		 2951 return 0;
2952}
2953
a1efbe77
JK		 2954static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2955 struct kvm_debugregs *dbgregs)
2956{
73aaf249
JK		 2957 unsigned long val;
2958
a1efbe77 2959 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 2960 kvm_get_dr(vcpu, 6, &val);
73aaf249 2961 dbgregs->dr6 = val;
a1efbe77
JK		 2962 dbgregs->dr7 = vcpu->arch.dr7;
2963 dbgregs->flags = 0;
97e69aa6 2964 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2965}
2966
2967static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2968 struct kvm_debugregs *dbgregs)
2969{
2970 if (dbgregs->flags)
2971 return -EINVAL;
2972
a1efbe77 2973 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 2974 kvm_update_dr0123(vcpu);
a1efbe77 2975 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 2976 kvm_update_dr6(vcpu);
a1efbe77 2977 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 2978 kvm_update_dr7(vcpu);
a1efbe77 2979
a1efbe77
JK		 2980 return 0;
2981}
2982
df1daba7
PB		 2983#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2984
2985static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2986{
c47ada30 2987 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 2988 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 2989 u64 valid;
2990
2991 /*
2992 * Copy legacy XSAVE area, to avoid complications with CPUID
2993 * leaves 0 and 1 in the loop below.
2994 */
2995 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2996
2997 /* Set XSTATE_BV */
2998 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2999
3000 /*
3001 * Copy each region from the possibly compacted offset to the
3002 * non-compacted offset.
3003 */
3004 valid = xstate_bv & ~XSTATE_FPSSE;
3005 while (valid) {
3006 u64 feature = valid & -valid;
3007 int index = fls64(feature) - 1;
3008 void *src = get_xsave_addr(xsave, feature);
3009
3010 if (src) {
3011 u32 size, offset, ecx, edx;
3012 cpuid_count(XSTATE_CPUID, index,
3013 &size, &offset, &ecx, &edx);
3014 memcpy(dest + offset, src, size);
3015 }
3016
3017 valid -= feature;
3018 }
3019}
3020
3021static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3022{
c47ada30 3023 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3024 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3025 u64 valid;
3026
3027 /*
3028 * Copy legacy XSAVE area, to avoid complications with CPUID
3029 * leaves 0 and 1 in the loop below.
3030 */
3031 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3032
3033 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3034 xsave->header.xfeatures = xstate_bv;
df1daba7 3035 if (cpu_has_xsaves)
3a54450b 3036 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3037
3038 /*
3039 * Copy each region from the non-compacted offset to the
3040 * possibly compacted offset.
3041 */
3042 valid = xstate_bv & ~XSTATE_FPSSE;
3043 while (valid) {
3044 u64 feature = valid & -valid;
3045 int index = fls64(feature) - 1;
3046 void *dest = get_xsave_addr(xsave, feature);
3047
3048 if (dest) {
3049 u32 size, offset, ecx, edx;
3050 cpuid_count(XSTATE_CPUID, index,
3051 &size, &offset, &ecx, &edx);
3052 memcpy(dest, src + offset, size);
ee4100da 3053 }
df1daba7
PB		 3054
3055 valid -= feature;
3056 }
3057}
3058
2d5b5a66
SY		 3059static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3060 struct kvm_xsave *guest_xsave)
3061{
4344ee98 3062 if (cpu_has_xsave) {
df1daba7
PB		 3063 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3064 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3065 } else {
2d5b5a66 3066 memcpy(guest_xsave->region,
7366ed77 3067 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3068 sizeof(struct fxregs_state));
2d5b5a66
SY		 3069 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3070 XSTATE_FPSSE;
3071 }
3072}
3073
3074static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3075 struct kvm_xsave *guest_xsave)
3076{
3077 u64 xstate_bv =
3078 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3079
d7876f1b
PB		 3080 if (cpu_has_xsave) {
3081 /*
3082 * Here we allow setting states that are not present in
3083 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3084 * with old userspace.
3085 */
4ff41732 3086 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3087 return -EINVAL;
df1daba7 3088 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3089 } else {
2d5b5a66
SY		 3090 if (xstate_bv & ~XSTATE_FPSSE)
3091 return -EINVAL;
7366ed77 3092 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3093 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3094 }
3095 return 0;
3096}
3097
3098static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3099 struct kvm_xcrs *guest_xcrs)
3100{
3101 if (!cpu_has_xsave) {
3102 guest_xcrs->nr_xcrs = 0;
3103 return;
3104 }
3105
3106 guest_xcrs->nr_xcrs = 1;
3107 guest_xcrs->flags = 0;
3108 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3109 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3110}
3111
3112static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3113 struct kvm_xcrs *guest_xcrs)
3114{
3115 int i, r = 0;
3116
3117 if (!cpu_has_xsave)
3118 return -EINVAL;
3119
3120 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3121 return -EINVAL;
3122
3123 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3124 /* Only support XCR0 currently */
c67a04cb 3125 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3126 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3127 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3128 break;
3129 }
3130 if (r)
3131 r = -EINVAL;
3132 return r;
3133}
3134
1c0b28c2
EM		 3135/*
3136 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3137 * stopped by the hypervisor. This function will be called from the host only.
3138 * EINVAL is returned when the host attempts to set the flag for a guest that
3139 * does not support pv clocks.
3140 */
3141static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3142{
0b79459b 3143 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3144 return -EINVAL;
51d59c6b 3145 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3146 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3147 return 0;
3148}
3149
313a3dc7
CO		 3150long kvm_arch_vcpu_ioctl(struct file *filp,
3151 unsigned int ioctl, unsigned long arg)
3152{
3153 struct kvm_vcpu *vcpu = filp->private_data;
3154 void __user *argp = (void __user *)arg;
3155 int r;
d1ac91d8
AK		 3156 union {
3157 struct kvm_lapic_state *lapic;
3158 struct kvm_xsave *xsave;
3159 struct kvm_xcrs *xcrs;
3160 void *buffer;
3161 } u;
3162
3163 u.buffer = NULL;
313a3dc7
CO		 3164 switch (ioctl) {
3165 case KVM_GET_LAPIC: {
2204ae3c
MT		 3166 r = -EINVAL;
3167 if (!vcpu->arch.apic)
3168 goto out;
d1ac91d8 3169 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3170
b772ff36 3171 r = -ENOMEM;
d1ac91d8 3172 if (!u.lapic)
b772ff36 3173 goto out;
d1ac91d8 3174 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3175 if (r)
3176 goto out;
3177 r = -EFAULT;
d1ac91d8 3178 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3179 goto out;
3180 r = 0;
3181 break;
3182 }
3183 case KVM_SET_LAPIC: {
2204ae3c
MT		 3184 r = -EINVAL;
3185 if (!vcpu->arch.apic)
3186 goto out;
ff5c2c03 3187 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3188 if (IS_ERR(u.lapic))
3189 return PTR_ERR(u.lapic);
ff5c2c03 3190
d1ac91d8 3191 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3192 break;
3193 }
f77bc6a4
ZX		 3194 case KVM_INTERRUPT: {
3195 struct kvm_interrupt irq;
3196
3197 r = -EFAULT;
3198 if (copy_from_user(&irq, argp, sizeof irq))
3199 goto out;
3200 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3201 break;
3202 }
c4abb7c9
JK		 3203 case KVM_NMI: {
3204 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3205 break;
3206 }
f077825a
PB		 3207 case KVM_SMI: {
3208 r = kvm_vcpu_ioctl_smi(vcpu);
3209 break;
3210 }
313a3dc7
CO		 3211 case KVM_SET_CPUID: {
3212 struct kvm_cpuid __user *cpuid_arg = argp;
3213 struct kvm_cpuid cpuid;
3214
3215 r = -EFAULT;
3216 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3217 goto out;
3218 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3219 break;
3220 }
07716717
DK		 3221 case KVM_SET_CPUID2: {
3222 struct kvm_cpuid2 __user *cpuid_arg = argp;
3223 struct kvm_cpuid2 cpuid;
3224
3225 r = -EFAULT;
3226 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3227 goto out;
3228 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3229 cpuid_arg->entries);
07716717
DK		 3230 break;
3231 }
3232 case KVM_GET_CPUID2: {
3233 struct kvm_cpuid2 __user *cpuid_arg = argp;
3234 struct kvm_cpuid2 cpuid;
3235
3236 r = -EFAULT;
3237 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3238 goto out;
3239 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3240 cpuid_arg->entries);
07716717
DK		 3241 if (r)
3242 goto out;
3243 r = -EFAULT;
3244 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3245 goto out;
3246 r = 0;
3247 break;
3248 }
313a3dc7 3249 case KVM_GET_MSRS:
609e36d3 3250 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3251 break;
3252 case KVM_SET_MSRS:
3253 r = msr_io(vcpu, argp, do_set_msr, 0);
3254 break;
b209749f
AK		 3255 case KVM_TPR_ACCESS_REPORTING: {
3256 struct kvm_tpr_access_ctl tac;
3257
3258 r = -EFAULT;
3259 if (copy_from_user(&tac, argp, sizeof tac))
3260 goto out;
3261 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3262 if (r)
3263 goto out;
3264 r = -EFAULT;
3265 if (copy_to_user(argp, &tac, sizeof tac))
3266 goto out;
3267 r = 0;
3268 break;
3269 };
b93463aa
AK		 3270 case KVM_SET_VAPIC_ADDR: {
3271 struct kvm_vapic_addr va;
3272
3273 r = -EINVAL;
35754c98 3274 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3275 goto out;
3276 r = -EFAULT;
3277 if (copy_from_user(&va, argp, sizeof va))
3278 goto out;
fda4e2e8 3279 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3280 break;
3281 }
890ca9ae
HY		 3282 case KVM_X86_SETUP_MCE: {
3283 u64 mcg_cap;
3284
3285 r = -EFAULT;
3286 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3287 goto out;
3288 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3289 break;
3290 }
3291 case KVM_X86_SET_MCE: {
3292 struct kvm_x86_mce mce;
3293
3294 r = -EFAULT;
3295 if (copy_from_user(&mce, argp, sizeof mce))
3296 goto out;
3297 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3298 break;
3299 }
3cfc3092
JK		 3300 case KVM_GET_VCPU_EVENTS: {
3301 struct kvm_vcpu_events events;
3302
3303 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3304
3305 r = -EFAULT;
3306 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3307 break;
3308 r = 0;
3309 break;
3310 }
3311 case KVM_SET_VCPU_EVENTS: {
3312 struct kvm_vcpu_events events;
3313
3314 r = -EFAULT;
3315 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3316 break;
3317
3318 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3319 break;
3320 }
a1efbe77
JK		 3321 case KVM_GET_DEBUGREGS: {
3322 struct kvm_debugregs dbgregs;
3323
3324 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3325
3326 r = -EFAULT;
3327 if (copy_to_user(argp, &dbgregs,
3328 sizeof(struct kvm_debugregs)))
3329 break;
3330 r = 0;
3331 break;
3332 }
3333 case KVM_SET_DEBUGREGS: {
3334 struct kvm_debugregs dbgregs;
3335
3336 r = -EFAULT;
3337 if (copy_from_user(&dbgregs, argp,
3338 sizeof(struct kvm_debugregs)))
3339 break;
3340
3341 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3342 break;
3343 }
2d5b5a66 3344 case KVM_GET_XSAVE: {
d1ac91d8 3345 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3346 r = -ENOMEM;
d1ac91d8 3347 if (!u.xsave)
2d5b5a66
SY		 3348 break;
3349
d1ac91d8 3350 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3351
3352 r = -EFAULT;
d1ac91d8 3353 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3354 break;
3355 r = 0;
3356 break;
3357 }
3358 case KVM_SET_XSAVE: {
ff5c2c03 3359 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3360 if (IS_ERR(u.xsave))
3361 return PTR_ERR(u.xsave);
2d5b5a66 3362
d1ac91d8 3363 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3364 break;
3365 }
3366 case KVM_GET_XCRS: {
d1ac91d8 3367 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3368 r = -ENOMEM;
d1ac91d8 3369 if (!u.xcrs)
2d5b5a66
SY		 3370 break;
3371
d1ac91d8 3372 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3373
3374 r = -EFAULT;
d1ac91d8 3375 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3376 sizeof(struct kvm_xcrs)))
3377 break;
3378 r = 0;
3379 break;
3380 }
3381 case KVM_SET_XCRS: {
ff5c2c03 3382 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3383 if (IS_ERR(u.xcrs))
3384 return PTR_ERR(u.xcrs);
2d5b5a66 3385
d1ac91d8 3386 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3387 break;
3388 }
92a1f12d
JR		 3389 case KVM_SET_TSC_KHZ: {
3390 u32 user_tsc_khz;
3391
3392 r = -EINVAL;
92a1f12d
JR		 3393 user_tsc_khz = (u32)arg;
3394
3395 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3396 goto out;
3397
cc578287
ZA		 3398 if (user_tsc_khz == 0)
3399 user_tsc_khz = tsc_khz;
3400
381d585c
HZ		 3401 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3402 r = 0;
92a1f12d 3403
92a1f12d
JR		 3404 goto out;
3405 }
3406 case KVM_GET_TSC_KHZ: {
cc578287 3407 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3408 goto out;
3409 }
1c0b28c2
EM		 3410 case KVM_KVMCLOCK_CTRL: {
3411 r = kvm_set_guest_paused(vcpu);
3412 goto out;
3413 }
313a3dc7
CO		 3414 default:
3415 r = -EINVAL;
3416 }
3417out:
d1ac91d8 3418 kfree(u.buffer);
313a3dc7
CO		 3419 return r;
3420}
3421
5b1c1493
CO		 3422int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3423{
3424 return VM_FAULT_SIGBUS;
3425}
3426
1fe779f8
CO		 3427static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3428{
3429 int ret;
3430
3431 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3432 return -EINVAL;
1fe779f8
CO		 3433 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3434 return ret;
3435}
3436
b927a3ce
SY		 3437static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3438 u64 ident_addr)
3439{
3440 kvm->arch.ept_identity_map_addr = ident_addr;
3441 return 0;
3442}
3443
1fe779f8
CO		 3444static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3445 u32 kvm_nr_mmu_pages)
3446{
3447 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3448 return -EINVAL;
3449
79fac95e 3450 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3451
3452 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3453 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3454
79fac95e 3455 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3456 return 0;
3457}
3458
3459static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3460{
39de71ec 3461 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3462}
3463
1fe779f8
CO		 3464static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3465{
3466 int r;
3467
3468 r = 0;
3469 switch (chip->chip_id) {
3470 case KVM_IRQCHIP_PIC_MASTER:
3471 memcpy(&chip->chip.pic,
3472 &pic_irqchip(kvm)->pics[0],
3473 sizeof(struct kvm_pic_state));
3474 break;
3475 case KVM_IRQCHIP_PIC_SLAVE:
3476 memcpy(&chip->chip.pic,
3477 &pic_irqchip(kvm)->pics[1],
3478 sizeof(struct kvm_pic_state));
3479 break;
3480 case KVM_IRQCHIP_IOAPIC:
eba0226b 3481 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3482 break;
3483 default:
3484 r = -EINVAL;
3485 break;
3486 }
3487 return r;
3488}
3489
3490static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3491{
3492 int r;
3493
3494 r = 0;
3495 switch (chip->chip_id) {
3496 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3497 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3498 memcpy(&pic_irqchip(kvm)->pics[0],
3499 &chip->chip.pic,
3500 sizeof(struct kvm_pic_state));
f4f51050 3501 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3502 break;
3503 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3504 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3505 memcpy(&pic_irqchip(kvm)->pics[1],
3506 &chip->chip.pic,
3507 sizeof(struct kvm_pic_state));
f4f51050 3508 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3509 break;
3510 case KVM_IRQCHIP_IOAPIC:
eba0226b 3511 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3512 break;
3513 default:
3514 r = -EINVAL;
3515 break;
3516 }
3517 kvm_pic_update_irq(pic_irqchip(kvm));
3518 return r;
3519}
3520
e0f63cb9
SY		 3521static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3522{
894a9c55 3523 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3524 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3525 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3526 return 0;
e0f63cb9
SY		 3527}
3528
3529static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3530{
894a9c55 3531 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3532 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3533 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3534 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3535 return 0;
e9f42757
BK		 3536}
3537
3538static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3539{
e9f42757
BK		 3540 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3541 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3542 sizeof(ps->channels));
3543 ps->flags = kvm->arch.vpit->pit_state.flags;
3544 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3545 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3546 return 0;
e9f42757
BK		 3547}
3548
3549static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3550{
2da29bcc 3551 int start = 0;
e9f42757
BK		 3552 u32 prev_legacy, cur_legacy;
3553 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3554 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3555 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3556 if (!prev_legacy && cur_legacy)
3557 start = 1;
3558 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3559 sizeof(kvm->arch.vpit->pit_state.channels));
3560 kvm->arch.vpit->pit_state.flags = ps->flags;
3561 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3562 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3563 return 0;
e0f63cb9
SY		 3564}
3565
52d939a0
MT		 3566static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3567 struct kvm_reinject_control *control)
3568{
3569 if (!kvm->arch.vpit)
3570 return -ENXIO;
894a9c55 3571 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3572 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3573 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3574 return 0;
3575}
3576
95d4c16c 3577/**
60c34612
TY		 3578 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3579 * @kvm: kvm instance
3580 * @log: slot id and address to which we copy the log
95d4c16c 3581 *
e108ff2f
PB		 3582 * Steps 1-4 below provide general overview of dirty page logging. See
3583 * kvm_get_dirty_log_protect() function description for additional details.
3584 *
3585 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3586 * always flush the TLB (step 4) even if previous step failed and the dirty
3587 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3588 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3589 * writes will be marked dirty for next log read.
95d4c16c 3590 *
60c34612
TY		 3591 * 1. Take a snapshot of the bit and clear it if needed.
3592 * 2. Write protect the corresponding page.
e108ff2f
PB		 3593 * 3. Copy the snapshot to the userspace.
3594 * 4. Flush TLB's if needed.
5bb064dc 3595 */
60c34612 3596int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3597{
60c34612 3598 bool is_dirty = false;
e108ff2f 3599 int r;
5bb064dc 3600
79fac95e 3601 mutex_lock(&kvm->slots_lock);
5bb064dc 3602
88178fd4
KH		 3603 /*
3604 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3605 */
3606 if (kvm_x86_ops->flush_log_dirty)
3607 kvm_x86_ops->flush_log_dirty(kvm);
3608
e108ff2f 3609 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3610
3611 /*
3612 * All the TLBs can be flushed out of mmu lock, see the comments in
3613 * kvm_mmu_slot_remove_write_access().
3614 */
e108ff2f 3615 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3616 if (is_dirty)
3617 kvm_flush_remote_tlbs(kvm);
3618
79fac95e 3619 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3620 return r;
3621}
3622
aa2fbe6d
YZ		 3623int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3624 bool line_status)
23d43cf9
CD		 3625{
3626 if (!irqchip_in_kernel(kvm))
3627 return -ENXIO;
3628
3629 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3630 irq_event->irq, irq_event->level,
3631 line_status);
23d43cf9
CD		 3632 return 0;
3633}
3634
90de4a18
NA		 3635static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3636 struct kvm_enable_cap *cap)
3637{
3638 int r;
3639
3640 if (cap->flags)
3641 return -EINVAL;
3642
3643 switch (cap->cap) {
3644 case KVM_CAP_DISABLE_QUIRKS:
3645 kvm->arch.disabled_quirks = cap->args[0];
3646 r = 0;
3647 break;
49df6397
SR		 3648 case KVM_CAP_SPLIT_IRQCHIP: {
3649 mutex_lock(&kvm->lock);
b053b2ae
SR		 3650 r = -EINVAL;
3651 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3652 goto split_irqchip_unlock;
49df6397
SR		 3653 r = -EEXIST;
3654 if (irqchip_in_kernel(kvm))
3655 goto split_irqchip_unlock;
3656 if (atomic_read(&kvm->online_vcpus))
3657 goto split_irqchip_unlock;
3658 r = kvm_setup_empty_irq_routing(kvm);
3659 if (r)
3660 goto split_irqchip_unlock;
3661 /* Pairs with irqchip_in_kernel. */
3662 smp_wmb();
3663 kvm->arch.irqchip_split = true;
b053b2ae 3664 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3665 r = 0;
3666split_irqchip_unlock:
3667 mutex_unlock(&kvm->lock);
3668 break;
3669 }
90de4a18
NA		 3670 default:
3671 r = -EINVAL;
3672 break;
3673 }
3674 return r;
3675}
3676
1fe779f8
CO		 3677long kvm_arch_vm_ioctl(struct file *filp,
3678 unsigned int ioctl, unsigned long arg)
3679{
3680 struct kvm *kvm = filp->private_data;
3681 void __user *argp = (void __user *)arg;
367e1319 3682 int r = -ENOTTY;
f0d66275
DH		 3683 /*
3684 * This union makes it completely explicit to gcc-3.x
3685 * that these two variables' stack usage should be
3686 * combined, not added together.
3687 */
3688 union {
3689 struct kvm_pit_state ps;
e9f42757 3690 struct kvm_pit_state2 ps2;
c5ff41ce 3691 struct kvm_pit_config pit_config;
f0d66275 3692 } u;
1fe779f8
CO		 3693
3694 switch (ioctl) {
3695 case KVM_SET_TSS_ADDR:
3696 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3697 break;
b927a3ce
SY		 3698 case KVM_SET_IDENTITY_MAP_ADDR: {
3699 u64 ident_addr;
3700
3701 r = -EFAULT;
3702 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3703 goto out;
3704 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3705 break;
3706 }
1fe779f8
CO		 3707 case KVM_SET_NR_MMU_PAGES:
3708 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3709 break;
3710 case KVM_GET_NR_MMU_PAGES:
3711 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3712 break;
3ddea128
MT		 3713 case KVM_CREATE_IRQCHIP: {
3714 struct kvm_pic *vpic;
3715
3716 mutex_lock(&kvm->lock);
3717 r = -EEXIST;
3718 if (kvm->arch.vpic)
3719 goto create_irqchip_unlock;
3e515705
AK		 3720 r = -EINVAL;
3721 if (atomic_read(&kvm->online_vcpus))
3722 goto create_irqchip_unlock;
1fe779f8 3723 r = -ENOMEM;
3ddea128
MT		 3724 vpic = kvm_create_pic(kvm);
3725 if (vpic) {
1fe779f8
CO		 3726 r = kvm_ioapic_init(kvm);
3727 if (r) {
175504cd 3728 mutex_lock(&kvm->slots_lock);
71ba994c 3729 kvm_destroy_pic(vpic);
175504cd 3730 mutex_unlock(&kvm->slots_lock);
3ddea128 3731 goto create_irqchip_unlock;
1fe779f8
CO		 3732 }
3733 } else
3ddea128 3734 goto create_irqchip_unlock;
399ec807
AK		 3735 r = kvm_setup_default_irq_routing(kvm);
3736 if (r) {
175504cd 3737 mutex_lock(&kvm->slots_lock);
3ddea128 3738 mutex_lock(&kvm->irq_lock);
72bb2fcd 3739 kvm_ioapic_destroy(kvm);
71ba994c 3740 kvm_destroy_pic(vpic);
3ddea128 3741 mutex_unlock(&kvm->irq_lock);
175504cd 3742 mutex_unlock(&kvm->slots_lock);
71ba994c 3743 goto create_irqchip_unlock;
399ec807 3744 }
71ba994c
PB		 3745 /* Write kvm->irq_routing before kvm->arch.vpic. */
3746 smp_wmb();
3747 kvm->arch.vpic = vpic;
3ddea128
MT		 3748 create_irqchip_unlock:
3749 mutex_unlock(&kvm->lock);
1fe779f8 3750 break;
3ddea128 3751 }
7837699f 3752 case KVM_CREATE_PIT:
c5ff41ce
JK		 3753 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3754 goto create_pit;
3755 case KVM_CREATE_PIT2:
3756 r = -EFAULT;
3757 if (copy_from_user(&u.pit_config, argp,
3758 sizeof(struct kvm_pit_config)))
3759 goto out;
3760 create_pit:
79fac95e 3761 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3762 r = -EEXIST;
3763 if (kvm->arch.vpit)
3764 goto create_pit_unlock;
7837699f 3765 r = -ENOMEM;
c5ff41ce 3766 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3767 if (kvm->arch.vpit)
3768 r = 0;
269e05e4 3769 create_pit_unlock:
79fac95e 3770 mutex_unlock(&kvm->slots_lock);
7837699f 3771 break;
1fe779f8
CO		 3772 case KVM_GET_IRQCHIP: {
3773 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3774 struct kvm_irqchip *chip;
1fe779f8 3775
ff5c2c03
SL		 3776 chip = memdup_user(argp, sizeof(*chip));
3777 if (IS_ERR(chip)) {
3778 r = PTR_ERR(chip);
1fe779f8 3779 goto out;
ff5c2c03
SL		 3780 }
3781
1fe779f8 3782 r = -ENXIO;
49df6397 3783 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3784 goto get_irqchip_out;
3785 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3786 if (r)
f0d66275 3787 goto get_irqchip_out;
1fe779f8 3788 r = -EFAULT;
f0d66275
DH		 3789 if (copy_to_user(argp, chip, sizeof *chip))
3790 goto get_irqchip_out;
1fe779f8 3791 r = 0;
f0d66275
DH		 3792 get_irqchip_out:
3793 kfree(chip);
1fe779f8
CO		 3794 break;
3795 }
3796 case KVM_SET_IRQCHIP: {
3797 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3798 struct kvm_irqchip *chip;
1fe779f8 3799
ff5c2c03
SL		 3800 chip = memdup_user(argp, sizeof(*chip));
3801 if (IS_ERR(chip)) {
3802 r = PTR_ERR(chip);
1fe779f8 3803 goto out;
ff5c2c03
SL		 3804 }
3805
1fe779f8 3806 r = -ENXIO;
49df6397 3807 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3808 goto set_irqchip_out;
3809 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3810 if (r)
f0d66275 3811 goto set_irqchip_out;
1fe779f8 3812 r = 0;
f0d66275
DH		 3813 set_irqchip_out:
3814 kfree(chip);
1fe779f8
CO		 3815 break;
3816 }
e0f63cb9 3817 case KVM_GET_PIT: {
e0f63cb9 3818 r = -EFAULT;
f0d66275 3819 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3820 goto out;
3821 r = -ENXIO;
3822 if (!kvm->arch.vpit)
3823 goto out;
f0d66275 3824 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3825 if (r)
3826 goto out;
3827 r = -EFAULT;
f0d66275 3828 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3829 goto out;
3830 r = 0;
3831 break;
3832 }
3833 case KVM_SET_PIT: {
e0f63cb9 3834 r = -EFAULT;
f0d66275 3835 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3836 goto out;
3837 r = -ENXIO;
3838 if (!kvm->arch.vpit)
3839 goto out;
f0d66275 3840 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3841 break;
3842 }
e9f42757
BK		 3843 case KVM_GET_PIT2: {
3844 r = -ENXIO;
3845 if (!kvm->arch.vpit)
3846 goto out;
3847 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3848 if (r)
3849 goto out;
3850 r = -EFAULT;
3851 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3852 goto out;
3853 r = 0;
3854 break;
3855 }
3856 case KVM_SET_PIT2: {
3857 r = -EFAULT;
3858 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3859 goto out;
3860 r = -ENXIO;
3861 if (!kvm->arch.vpit)
3862 goto out;
3863 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3864 break;
3865 }
52d939a0
MT		 3866 case KVM_REINJECT_CONTROL: {
3867 struct kvm_reinject_control control;
3868 r = -EFAULT;
3869 if (copy_from_user(&control, argp, sizeof(control)))
3870 goto out;
3871 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3872 break;
3873 }
d71ba788
PB		 3874 case KVM_SET_BOOT_CPU_ID:
3875 r = 0;
3876 mutex_lock(&kvm->lock);
3877 if (atomic_read(&kvm->online_vcpus) != 0)
3878 r = -EBUSY;
3879 else
3880 kvm->arch.bsp_vcpu_id = arg;
3881 mutex_unlock(&kvm->lock);
3882 break;
ffde22ac
ES		 3883 case KVM_XEN_HVM_CONFIG: {
3884 r = -EFAULT;
3885 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3886 sizeof(struct kvm_xen_hvm_config)))
3887 goto out;
3888 r = -EINVAL;
3889 if (kvm->arch.xen_hvm_config.flags)
3890 goto out;
3891 r = 0;
3892 break;
3893 }
afbcf7ab 3894 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3895 struct kvm_clock_data user_ns;
3896 u64 now_ns;
3897 s64 delta;
3898
3899 r = -EFAULT;
3900 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3901 goto out;
3902
3903 r = -EINVAL;
3904 if (user_ns.flags)
3905 goto out;
3906
3907 r = 0;
395c6b0a 3908 local_irq_disable();
759379dd 3909 now_ns = get_kernel_ns();
afbcf7ab 3910 delta = user_ns.clock - now_ns;
395c6b0a 3911 local_irq_enable();
afbcf7ab 3912 kvm->arch.kvmclock_offset = delta;
2e762ff7 3913 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3914 break;
3915 }
3916 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3917 struct kvm_clock_data user_ns;
3918 u64 now_ns;
3919
395c6b0a 3920 local_irq_disable();
759379dd 3921 now_ns = get_kernel_ns();
afbcf7ab 3922 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3923 local_irq_enable();
afbcf7ab 3924 user_ns.flags = 0;
97e69aa6 3925 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3926
3927 r = -EFAULT;
3928 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3929 goto out;
3930 r = 0;
3931 break;
3932 }
90de4a18
NA		 3933 case KVM_ENABLE_CAP: {
3934 struct kvm_enable_cap cap;
afbcf7ab 3935
90de4a18
NA		 3936 r = -EFAULT;
3937 if (copy_from_user(&cap, argp, sizeof(cap)))
3938 goto out;
3939 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3940 break;
3941 }
1fe779f8 3942 default:
c274e03a 3943 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3944 }
3945out:
3946 return r;
3947}
3948
a16b043c 3949static void kvm_init_msr_list(void)
043405e1
CO		 3950{
3951 u32 dummy[2];
3952 unsigned i, j;
3953
62ef68bb 3954 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3955 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3956 continue;
93c4adc7
PB		 3957
3958 /*
3959 * Even MSRs that are valid in the host may not be exposed
3960 * to the guests in some cases. We could work around this
3961 * in VMX with the generic MSR save/load machinery, but it
3962 * is not really worthwhile since it will really only
3963 * happen with nested virtualization.
3964 */
3965 switch (msrs_to_save[i]) {
3966 case MSR_IA32_BNDCFGS:
3967 if (!kvm_x86_ops->mpx_supported())
3968 continue;
3969 break;
3970 default:
3971 break;
3972 }
3973
043405e1
CO		 3974 if (j < i)
3975 msrs_to_save[j] = msrs_to_save[i];
3976 j++;
3977 }
3978 num_msrs_to_save = j;
62ef68bb
PB		 3979
3980 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3981 switch (emulated_msrs[i]) {
6d396b55
PB		 3982 case MSR_IA32_SMBASE:
3983 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3984 continue;
3985 break;
62ef68bb
PB		 3986 default:
3987 break;
3988 }
3989
3990 if (j < i)
3991 emulated_msrs[j] = emulated_msrs[i];
3992 j++;
3993 }
3994 num_emulated_msrs = j;
043405e1
CO		 3995}
3996
bda9020e
MT		 3997static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3998 const void *v)
bbd9b64e 3999{
70252a10
AK		 4000 int handled = 0;
4001 int n;
4002
4003 do {
4004 n = min(len, 8);
4005 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4006 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4007 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4008 break;
4009 handled += n;
4010 addr += n;
4011 len -= n;
4012 v += n;
4013 } while (len);
bbd9b64e 4014
70252a10 4015 return handled;
bbd9b64e
CO		 4016}
4017
bda9020e 4018static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4019{
70252a10
AK		 4020 int handled = 0;
4021 int n;
4022
4023 do {
4024 n = min(len, 8);
4025 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4026 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4027 addr, n, v))
4028 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4029 break;
4030 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4031 handled += n;
4032 addr += n;
4033 len -= n;
4034 v += n;
4035 } while (len);
bbd9b64e 4036
70252a10 4037 return handled;
bbd9b64e
CO		 4038}
4039
2dafc6c2
GN		 4040static void kvm_set_segment(struct kvm_vcpu *vcpu,
4041 struct kvm_segment *var, int seg)
4042{
4043 kvm_x86_ops->set_segment(vcpu, var, seg);
4044}
4045
4046void kvm_get_segment(struct kvm_vcpu *vcpu,
4047 struct kvm_segment *var, int seg)
4048{
4049 kvm_x86_ops->get_segment(vcpu, var, seg);
4050}
4051
54987b7a
PB		 4052gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4053 struct x86_exception *exception)
02f59dc9
JR		 4054{
4055 gpa_t t_gpa;
02f59dc9
JR		 4056
4057 BUG_ON(!mmu_is_nested(vcpu));
4058
4059 /* NPT walks are always user-walks */
4060 access |= PFERR_USER_MASK;
54987b7a 4061 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4062
4063 return t_gpa;
4064}
4065
ab9ae313
AK		 4066gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4067 struct x86_exception *exception)
1871c602
GN		 4068{
4069 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4070 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4071}
4072
ab9ae313
AK		 4073 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4074 struct x86_exception *exception)
1871c602
GN		 4075{
4076 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4077 access |= PFERR_FETCH_MASK;
ab9ae313 4078 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4079}
4080
ab9ae313
AK		 4081gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4082 struct x86_exception *exception)
1871c602
GN		 4083{
4084 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4085 access |= PFERR_WRITE_MASK;
ab9ae313 4086 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4087}
4088
4089/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4090gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4091 struct x86_exception *exception)
1871c602 4092{
ab9ae313 4093 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4094}
4095
4096static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4097 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4098 struct x86_exception *exception)
bbd9b64e
CO		 4099{
4100 void *data = val;
10589a46 4101 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4102
4103 while (bytes) {
14dfe855 4104 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4105 exception);
bbd9b64e 4106 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4107 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4108 int ret;
4109
bcc55cba 4110 if (gpa == UNMAPPED_GVA)
ab9ae313 4111 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4112 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4113 offset, toread);
10589a46 4114 if (ret < 0) {
c3cd7ffa 4115 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4116 goto out;
4117 }
bbd9b64e 4118
77c2002e
IE		 4119 bytes -= toread;
4120 data += toread;
4121 addr += toread;
bbd9b64e 4122 }
10589a46 4123out:
10589a46 4124 return r;
bbd9b64e 4125}
77c2002e 4126
1871c602 4127/* used for instruction fetching */
0f65dd70
AK		 4128static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4129 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4130 struct x86_exception *exception)
1871c602 4131{
0f65dd70 4132 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4133 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4134 unsigned offset;
4135 int ret;
0f65dd70 4136
44583cba
PB		 4137 /* Inline kvm_read_guest_virt_helper for speed. */
4138 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4139 exception);
4140 if (unlikely(gpa == UNMAPPED_GVA))
4141 return X86EMUL_PROPAGATE_FAULT;
4142
4143 offset = addr & (PAGE_SIZE-1);
4144 if (WARN_ON(offset + bytes > PAGE_SIZE))
4145 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4146 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4147 offset, bytes);
44583cba
PB		 4148 if (unlikely(ret < 0))
4149 return X86EMUL_IO_NEEDED;
4150
4151 return X86EMUL_CONTINUE;
1871c602
GN		 4152}
4153
064aea77 4154int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4155 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4156 struct x86_exception *exception)
1871c602 4157{
0f65dd70 4158 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4159 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4160
1871c602 4161 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4162 exception);
1871c602 4163}
064aea77 4164EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4165
0f65dd70
AK		 4166static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4167 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4168 struct x86_exception *exception)
1871c602 4169{
0f65dd70 4170 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4171 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4172}
4173
7a036a6f
RK		 4174static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4175 unsigned long addr, void *val, unsigned int bytes)
4176{
4177 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4178 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4179
4180 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4181}
4182
6a4d7550 4183int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4184 gva_t addr, void *val,
2dafc6c2 4185 unsigned int bytes,
bcc55cba 4186 struct x86_exception *exception)
77c2002e 4187{
0f65dd70 4188 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4189 void *data = val;
4190 int r = X86EMUL_CONTINUE;
4191
4192 while (bytes) {
14dfe855
JR		 4193 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4194 PFERR_WRITE_MASK,
ab9ae313 4195 exception);
77c2002e
IE		 4196 unsigned offset = addr & (PAGE_SIZE-1);
4197 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4198 int ret;
4199
bcc55cba 4200 if (gpa == UNMAPPED_GVA)
ab9ae313 4201 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4202 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4203 if (ret < 0) {
c3cd7ffa 4204 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4205 goto out;
4206 }
4207
4208 bytes -= towrite;
4209 data += towrite;
4210 addr += towrite;
4211 }
4212out:
4213 return r;
4214}
6a4d7550 4215EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4216
af7cc7d1
XG		 4217static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4218 gpa_t *gpa, struct x86_exception *exception,
4219 bool write)
4220{
97d64b78
AK		 4221 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4222 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4223
97d64b78 4224 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4225 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4226 vcpu->arch.access, access)) {
bebb106a
XG		 4227 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4228 (gva & (PAGE_SIZE - 1));
4f022648 4229 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4230 return 1;
4231 }
4232
af7cc7d1
XG		 4233 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4234
4235 if (*gpa == UNMAPPED_GVA)
4236 return -1;
4237
4238 /* For APIC access vmexit */
4239 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4240 return 1;
4241
4f022648
XG		 4242 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4243 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4244 return 1;
4f022648 4245 }
bebb106a 4246
af7cc7d1
XG		 4247 return 0;
4248}
4249
3200f405 4250int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4251 const void *val, int bytes)
bbd9b64e
CO		 4252{
4253 int ret;
4254
54bf36aa 4255 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4256 if (ret < 0)
bbd9b64e 4257 return 0;
f57f2ef5 4258 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4259 return 1;
4260}
4261
77d197b2
XG		 4262struct read_write_emulator_ops {
4263 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4264 int bytes);
4265 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4266 void *val, int bytes);
4267 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4268 int bytes, void *val);
4269 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4270 void *val, int bytes);
4271 bool write;
4272};
4273
4274static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4275{
4276 if (vcpu->mmio_read_completed) {
77d197b2 4277 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4278 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4279 vcpu->mmio_read_completed = 0;
4280 return 1;
4281 }
4282
4283 return 0;
4284}
4285
4286static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4287 void *val, int bytes)
4288{
54bf36aa 4289 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4290}
4291
4292static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4293 void *val, int bytes)
4294{
4295 return emulator_write_phys(vcpu, gpa, val, bytes);
4296}
4297
4298static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4299{
4300 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4301 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4302}
4303
4304static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4305 void *val, int bytes)
4306{
4307 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4308 return X86EMUL_IO_NEEDED;
4309}
4310
4311static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4312 void *val, int bytes)
4313{
f78146b0
AK		 4314 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4315
87da7e66 4316 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4317 return X86EMUL_CONTINUE;
4318}
4319
0fbe9b0b 4320static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4321 .read_write_prepare = read_prepare,
4322 .read_write_emulate = read_emulate,
4323 .read_write_mmio = vcpu_mmio_read,
4324 .read_write_exit_mmio = read_exit_mmio,
4325};
4326
0fbe9b0b 4327static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4328 .read_write_emulate = write_emulate,
4329 .read_write_mmio = write_mmio,
4330 .read_write_exit_mmio = write_exit_mmio,
4331 .write = true,
4332};
4333
22388a3c
XG		 4334static int emulator_read_write_onepage(unsigned long addr, void *val,
4335 unsigned int bytes,
4336 struct x86_exception *exception,
4337 struct kvm_vcpu *vcpu,
0fbe9b0b 4338 const struct read_write_emulator_ops *ops)
bbd9b64e 4339{
af7cc7d1
XG		 4340 gpa_t gpa;
4341 int handled, ret;
22388a3c 4342 bool write = ops->write;
f78146b0 4343 struct kvm_mmio_fragment *frag;
10589a46 4344
22388a3c 4345 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4346
af7cc7d1 4347 if (ret < 0)
bbd9b64e 4348 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4349
4350 /* For APIC access vmexit */
af7cc7d1 4351 if (ret)
bbd9b64e
CO		 4352 goto mmio;
4353
22388a3c 4354 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4355 return X86EMUL_CONTINUE;
4356
4357mmio:
4358 /*
4359 * Is this MMIO handled locally?
4360 */
22388a3c 4361 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4362 if (handled == bytes)
bbd9b64e 4363 return X86EMUL_CONTINUE;
bbd9b64e 4364
70252a10
AK		 4365 gpa += handled;
4366 bytes -= handled;
4367 val += handled;
4368
87da7e66
XG		 4369 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4370 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4371 frag->gpa = gpa;
4372 frag->data = val;
4373 frag->len = bytes;
f78146b0 4374 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4375}
4376
52eb5a6d
XL		 4377static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4378 unsigned long addr,
22388a3c
XG		 4379 void *val, unsigned int bytes,
4380 struct x86_exception *exception,
0fbe9b0b 4381 const struct read_write_emulator_ops *ops)
bbd9b64e 4382{
0f65dd70 4383 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4384 gpa_t gpa;
4385 int rc;
4386
4387 if (ops->read_write_prepare &&
4388 ops->read_write_prepare(vcpu, val, bytes))
4389 return X86EMUL_CONTINUE;
4390
4391 vcpu->mmio_nr_fragments = 0;
0f65dd70 4392
bbd9b64e
CO		 4393 /* Crossing a page boundary? */
4394 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4395 int now;
bbd9b64e
CO		 4396
4397 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4398 rc = emulator_read_write_onepage(addr, val, now, exception,
4399 vcpu, ops);
4400
bbd9b64e
CO		 4401 if (rc != X86EMUL_CONTINUE)
4402 return rc;
4403 addr += now;
bac15531
NA		 4404 if (ctxt->mode != X86EMUL_MODE_PROT64)
4405 addr = (u32)addr;
bbd9b64e
CO		 4406 val += now;
4407 bytes -= now;
4408 }
22388a3c 4409
f78146b0
AK		 4410 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4411 vcpu, ops);
4412 if (rc != X86EMUL_CONTINUE)
4413 return rc;
4414
4415 if (!vcpu->mmio_nr_fragments)
4416 return rc;
4417
4418 gpa = vcpu->mmio_fragments[0].gpa;
4419
4420 vcpu->mmio_needed = 1;
4421 vcpu->mmio_cur_fragment = 0;
4422
87da7e66 4423 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4424 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4425 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4426 vcpu->run->mmio.phys_addr = gpa;
4427
4428 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4429}
4430
4431static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4432 unsigned long addr,
4433 void *val,
4434 unsigned int bytes,
4435 struct x86_exception *exception)
4436{
4437 return emulator_read_write(ctxt, addr, val, bytes,
4438 exception, &read_emultor);
4439}
4440
52eb5a6d 4441static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4442 unsigned long addr,
4443 const void *val,
4444 unsigned int bytes,
4445 struct x86_exception *exception)
4446{
4447 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4448 exception, &write_emultor);
bbd9b64e 4449}
bbd9b64e 4450
daea3e73
AK		 4451#define CMPXCHG_TYPE(t, ptr, old, new) \
4452 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4453
4454#ifdef CONFIG_X86_64
4455# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4456#else
4457# define CMPXCHG64(ptr, old, new) \
9749a6c0 4458 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4459#endif
4460
0f65dd70
AK		 4461static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4462 unsigned long addr,
bbd9b64e
CO		 4463 const void *old,
4464 const void *new,
4465 unsigned int bytes,
0f65dd70 4466 struct x86_exception *exception)
bbd9b64e 4467{
0f65dd70 4468 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4469 gpa_t gpa;
4470 struct page *page;
4471 char *kaddr;
4472 bool exchanged;
2bacc55c 4473
daea3e73
AK		 4474 /* guests cmpxchg8b have to be emulated atomically */
4475 if (bytes > 8 || (bytes & (bytes - 1)))
4476 goto emul_write;
10589a46 4477
daea3e73 4478 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4479
daea3e73
AK		 4480 if (gpa == UNMAPPED_GVA ||
4481 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4482 goto emul_write;
2bacc55c 4483
daea3e73
AK		 4484 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4485 goto emul_write;
72dc67a6 4486
54bf36aa 4487 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4488 if (is_error_page(page))
c19b8bd6 4489 goto emul_write;
72dc67a6 4490
8fd75e12 4491 kaddr = kmap_atomic(page);
daea3e73
AK		 4492 kaddr += offset_in_page(gpa);
4493 switch (bytes) {
4494 case 1:
4495 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4496 break;
4497 case 2:
4498 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4499 break;
4500 case 4:
4501 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4502 break;
4503 case 8:
4504 exchanged = CMPXCHG64(kaddr, old, new);
4505 break;
4506 default:
4507 BUG();
2bacc55c 4508 }
8fd75e12 4509 kunmap_atomic(kaddr);
daea3e73
AK		 4510 kvm_release_page_dirty(page);
4511
4512 if (!exchanged)
4513 return X86EMUL_CMPXCHG_FAILED;
4514
54bf36aa 4515 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4516 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4517
4518 return X86EMUL_CONTINUE;
4a5f48f6 4519
3200f405 4520emul_write:
daea3e73 4521 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4522
0f65dd70 4523 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4524}
4525
cf8f70bf
GN		 4526static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4527{
4528 /* TODO: String I/O for in kernel device */
4529 int r;
4530
4531 if (vcpu->arch.pio.in)
e32edf4f 4532 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4533 vcpu->arch.pio.size, pd);
4534 else
e32edf4f 4535 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4536 vcpu->arch.pio.port, vcpu->arch.pio.size,
4537 pd);
4538 return r;
4539}
4540
6f6fbe98
XG		 4541static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4542 unsigned short port, void *val,
4543 unsigned int count, bool in)
cf8f70bf 4544{
cf8f70bf 4545 vcpu->arch.pio.port = port;
6f6fbe98 4546 vcpu->arch.pio.in = in;
7972995b 4547 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4548 vcpu->arch.pio.size = size;
4549
4550 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4551 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4552 return 1;
4553 }
4554
4555 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4556 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4557 vcpu->run->io.size = size;
4558 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4559 vcpu->run->io.count = count;
4560 vcpu->run->io.port = port;
4561
4562 return 0;
4563}
4564
6f6fbe98
XG		 4565static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4566 int size, unsigned short port, void *val,
4567 unsigned int count)
cf8f70bf 4568{
ca1d4a9e 4569 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4570 int ret;
ca1d4a9e 4571
6f6fbe98
XG		 4572 if (vcpu->arch.pio.count)
4573 goto data_avail;
cf8f70bf 4574
6f6fbe98
XG		 4575 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4576 if (ret) {
4577data_avail:
4578 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4579 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4580 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4581 return 1;
4582 }
4583
cf8f70bf
GN		 4584 return 0;
4585}
4586
6f6fbe98
XG		 4587static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4588 int size, unsigned short port,
4589 const void *val, unsigned int count)
4590{
4591 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4592
4593 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4594 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4595 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4596}
4597
bbd9b64e
CO		 4598static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4599{
4600 return kvm_x86_ops->get_segment_base(vcpu, seg);
4601}
4602
3cb16fe7 4603static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4604{
3cb16fe7 4605 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4606}
4607
5cb56059 4608int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4609{
4610 if (!need_emulate_wbinvd(vcpu))
4611 return X86EMUL_CONTINUE;
4612
4613 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4614 int cpu = get_cpu();
4615
4616 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4617 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4618 wbinvd_ipi, NULL, 1);
2eec7343 4619 put_cpu();
f5f48ee1 4620 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4621 } else
4622 wbinvd();
f5f48ee1
SY		 4623 return X86EMUL_CONTINUE;
4624}
5cb56059
JS		 4625
4626int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4627{
4628 kvm_x86_ops->skip_emulated_instruction(vcpu);
4629 return kvm_emulate_wbinvd_noskip(vcpu);
4630}
f5f48ee1
SY		 4631EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4632
5cb56059
JS		 4633
4634
bcaf5cc5
AK		 4635static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4636{
5cb56059 4637 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4638}
4639
52eb5a6d
XL		 4640static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4641 unsigned long *dest)
bbd9b64e 4642{
16f8a6f9 4643 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4644}
4645
52eb5a6d
XL		 4646static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4647 unsigned long value)
bbd9b64e 4648{
338dbc97 4649
717746e3 4650 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4651}
4652
52a46617 4653static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4654{
52a46617 4655 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4656}
4657
717746e3 4658static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4659{
717746e3 4660 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4661 unsigned long value;
4662
4663 switch (cr) {
4664 case 0:
4665 value = kvm_read_cr0(vcpu);
4666 break;
4667 case 2:
4668 value = vcpu->arch.cr2;
4669 break;
4670 case 3:
9f8fe504 4671 value = kvm_read_cr3(vcpu);
52a46617
GN		 4672 break;
4673 case 4:
4674 value = kvm_read_cr4(vcpu);
4675 break;
4676 case 8:
4677 value = kvm_get_cr8(vcpu);
4678 break;
4679 default:
a737f256 4680 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4681 return 0;
4682 }
4683
4684 return value;
4685}
4686
717746e3 4687static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4688{
717746e3 4689 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4690 int res = 0;
4691
52a46617
GN		 4692 switch (cr) {
4693 case 0:
49a9b07e 4694 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4695 break;
4696 case 2:
4697 vcpu->arch.cr2 = val;
4698 break;
4699 case 3:
2390218b 4700 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4701 break;
4702 case 4:
a83b29c6 4703 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4704 break;
4705 case 8:
eea1cff9 4706 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4707 break;
4708 default:
a737f256 4709 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4710 res = -1;
52a46617 4711 }
0f12244f
GN		 4712
4713 return res;
52a46617
GN		 4714}
4715
717746e3 4716static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4717{
717746e3 4718 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4719}
4720
4bff1e86 4721static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4722{
4bff1e86 4723 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4724}
4725
4bff1e86 4726static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4727{
4bff1e86 4728 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4729}
4730
1ac9d0cf
AK		 4731static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4732{
4733 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4734}
4735
4736static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4737{
4738 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4739}
4740
4bff1e86
AK		 4741static unsigned long emulator_get_cached_segment_base(
4742 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4743{
4bff1e86 4744 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4745}
4746
1aa36616
AK		 4747static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4748 struct desc_struct *desc, u32 *base3,
4749 int seg)
2dafc6c2
GN		 4750{
4751 struct kvm_segment var;
4752
4bff1e86 4753 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4754 *selector = var.selector;
2dafc6c2 4755
378a8b09
GN		 4756 if (var.unusable) {
4757 memset(desc, 0, sizeof(*desc));
2dafc6c2 4758 return false;
378a8b09 4759 }
2dafc6c2
GN		 4760
4761 if (var.g)
4762 var.limit >>= 12;
4763 set_desc_limit(desc, var.limit);
4764 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4765#ifdef CONFIG_X86_64
4766 if (base3)
4767 *base3 = var.base >> 32;
4768#endif
2dafc6c2
GN		 4769 desc->type = var.type;
4770 desc->s = var.s;
4771 desc->dpl = var.dpl;
4772 desc->p = var.present;
4773 desc->avl = var.avl;
4774 desc->l = var.l;
4775 desc->d = var.db;
4776 desc->g = var.g;
4777
4778 return true;
4779}
4780
1aa36616
AK		 4781static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4782 struct desc_struct *desc, u32 base3,
4783 int seg)
2dafc6c2 4784{
4bff1e86 4785 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4786 struct kvm_segment var;
4787
1aa36616 4788 var.selector = selector;
2dafc6c2 4789 var.base = get_desc_base(desc);
5601d05b
GN		 4790#ifdef CONFIG_X86_64
4791 var.base |= ((u64)base3) << 32;
4792#endif
2dafc6c2
GN		 4793 var.limit = get_desc_limit(desc);
4794 if (desc->g)
4795 var.limit = (var.limit << 12) | 0xfff;
4796 var.type = desc->type;
2dafc6c2
GN		 4797 var.dpl = desc->dpl;
4798 var.db = desc->d;
4799 var.s = desc->s;
4800 var.l = desc->l;
4801 var.g = desc->g;
4802 var.avl = desc->avl;
4803 var.present = desc->p;
4804 var.unusable = !var.present;
4805 var.padding = 0;
4806
4807 kvm_set_segment(vcpu, &var, seg);
4808 return;
4809}
4810
717746e3
AK		 4811static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4812 u32 msr_index, u64 *pdata)
4813{
609e36d3
PB		 4814 struct msr_data msr;
4815 int r;
4816
4817 msr.index = msr_index;
4818 msr.host_initiated = false;
4819 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4820 if (r)
4821 return r;
4822
4823 *pdata = msr.data;
4824 return 0;
717746e3
AK		 4825}
4826
4827static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4828 u32 msr_index, u64 data)
4829{
8fe8ab46
WA		 4830 struct msr_data msr;
4831
4832 msr.data = data;
4833 msr.index = msr_index;
4834 msr.host_initiated = false;
4835 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4836}
4837
64d60670
PB		 4838static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4839{
4840 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4841
4842 return vcpu->arch.smbase;
4843}
4844
4845static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4846{
4847 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4848
4849 vcpu->arch.smbase = smbase;
4850}
4851
67f4d428
NA		 4852static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4853 u32 pmc)
4854{
c6702c9d 4855 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4856}
4857
222d21aa
AK		 4858static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4859 u32 pmc, u64 *pdata)
4860{
c6702c9d 4861 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4862}
4863
6c3287f7
AK		 4864static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4865{
4866 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4867}
4868
5037f6f3
AK		 4869static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4870{
4871 preempt_disable();
5197b808 4872 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4873 /*
4874 * CR0.TS may reference the host fpu state, not the guest fpu state,
4875 * so it may be clear at this point.
4876 */
4877 clts();
4878}
4879
4880static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4881{
4882 preempt_enable();
4883}
4884
2953538e 4885static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4886 struct x86_instruction_info *info,
c4f035c6
AK		 4887 enum x86_intercept_stage stage)
4888{
2953538e 4889 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4890}
4891
0017f93a 4892static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4893 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4894{
0017f93a 4895 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4896}
4897
dd856efa
AK		 4898static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4899{
4900 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4901}
4902
4903static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4904{
4905 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4906}
4907
801806d9
NA		 4908static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4909{
4910 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4911}
4912
0225fb50 4913static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4914 .read_gpr = emulator_read_gpr,
4915 .write_gpr = emulator_write_gpr,
1871c602 4916 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4917 .write_std = kvm_write_guest_virt_system,
7a036a6f 4918 .read_phys = kvm_read_guest_phys_system,
1871c602 4919 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4920 .read_emulated = emulator_read_emulated,
4921 .write_emulated = emulator_write_emulated,
4922 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4923 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4924 .pio_in_emulated = emulator_pio_in_emulated,
4925 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4926 .get_segment = emulator_get_segment,
4927 .set_segment = emulator_set_segment,
5951c442 4928 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4929 .get_gdt = emulator_get_gdt,
160ce1f1 4930 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4931 .set_gdt = emulator_set_gdt,
4932 .set_idt = emulator_set_idt,
52a46617
GN		 4933 .get_cr = emulator_get_cr,
4934 .set_cr = emulator_set_cr,
9c537244 4935 .cpl = emulator_get_cpl,
35aa5375
GN		 4936 .get_dr = emulator_get_dr,
4937 .set_dr = emulator_set_dr,
64d60670
PB		 4938 .get_smbase = emulator_get_smbase,
4939 .set_smbase = emulator_set_smbase,
717746e3
AK		 4940 .set_msr = emulator_set_msr,
4941 .get_msr = emulator_get_msr,
67f4d428 4942 .check_pmc = emulator_check_pmc,
222d21aa 4943 .read_pmc = emulator_read_pmc,
6c3287f7 4944 .halt = emulator_halt,
bcaf5cc5 4945 .wbinvd = emulator_wbinvd,
d6aa1000 4946 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4947 .get_fpu = emulator_get_fpu,
4948 .put_fpu = emulator_put_fpu,
c4f035c6 4949 .intercept = emulator_intercept,
bdb42f5a 4950 .get_cpuid = emulator_get_cpuid,
801806d9 4951 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4952};
4953
95cb2295
GN		 4954static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4955{
37ccdcbe 4956 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4957 /*
4958 * an sti; sti; sequence only disable interrupts for the first
4959 * instruction. So, if the last instruction, be it emulated or
4960 * not, left the system with the INT_STI flag enabled, it
4961 * means that the last instruction is an sti. We should not
4962 * leave the flag on in this case. The same goes for mov ss
4963 */
37ccdcbe
PB		 4964 if (int_shadow & mask)
4965 mask = 0;
6addfc42 4966 if (unlikely(int_shadow || mask)) {
95cb2295 4967 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4968 if (!mask)
4969 kvm_make_request(KVM_REQ_EVENT, vcpu);
4970 }
95cb2295
GN		 4971}
4972
ef54bcfe 4973static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4974{
4975 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4976 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4977 return kvm_propagate_fault(vcpu, &ctxt->exception);
4978
4979 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4980 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4981 ctxt->exception.error_code);
54b8486f 4982 else
da9cb575 4983 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4984 return false;
54b8486f
GN		 4985}
4986
8ec4722d
MG		 4987static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4988{
adf52235 4989 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4990 int cs_db, cs_l;
4991
8ec4722d
MG		 4992 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4993
adf52235
TY		 4994 ctxt->eflags = kvm_get_rflags(vcpu);
4995 ctxt->eip = kvm_rip_read(vcpu);
4996 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4997 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4998 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4999 cs_db ? X86EMUL_MODE_PROT32 :
5000 X86EMUL_MODE_PROT16;
a584539b 5001 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5002 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5003 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5004 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5005
dd856efa 5006 init_decode_cache(ctxt);
7ae441ea 5007 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5008}
5009
71f9833b 5010int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5011{
9d74191a 5012 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5013 int ret;
5014
5015 init_emulate_ctxt(vcpu);
5016
9dac77fa
AK		 5017 ctxt->op_bytes = 2;
5018 ctxt->ad_bytes = 2;
5019 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5020 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5021
5022 if (ret != X86EMUL_CONTINUE)
5023 return EMULATE_FAIL;
5024
9dac77fa 5025 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5026 kvm_rip_write(vcpu, ctxt->eip);
5027 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5028
5029 if (irq == NMI_VECTOR)
7460fb4a 5030 vcpu->arch.nmi_pending = 0;
63995653
MG		 5031 else
5032 vcpu->arch.interrupt.pending = false;
5033
5034 return EMULATE_DONE;
5035}
5036EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5037
6d77dbfc
GN		 5038static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5039{
fc3a9157
JR		 5040 int r = EMULATE_DONE;
5041
6d77dbfc
GN		 5042 ++vcpu->stat.insn_emulation_fail;
5043 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5044 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5045 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5046 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5047 vcpu->run->internal.ndata = 0;
5048 r = EMULATE_FAIL;
5049 }
6d77dbfc 5050 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5051
5052 return r;
6d77dbfc
GN		 5053}
5054
93c05d3e 5055static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5056 bool write_fault_to_shadow_pgtable,
5057 int emulation_type)
a6f177ef 5058{
95b3cf69 5059 gpa_t gpa = cr2;
8e3d9d06 5060 pfn_t pfn;
a6f177ef 5061
991eebf9
GN		 5062 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5063 return false;
5064
95b3cf69
XG		 5065 if (!vcpu->arch.mmu.direct_map) {
5066 /*
5067 * Write permission should be allowed since only
5068 * write access need to be emulated.
5069 */
5070 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5071
95b3cf69
XG		 5072 /*
5073 * If the mapping is invalid in guest, let cpu retry
5074 * it to generate fault.
5075 */
5076 if (gpa == UNMAPPED_GVA)
5077 return true;
5078 }
a6f177ef 5079
8e3d9d06
XG		 5080 /*
5081 * Do not retry the unhandleable instruction if it faults on the
5082 * readonly host memory, otherwise it will goto a infinite loop:
5083 * retry instruction -> write #PF -> emulation fail -> retry
5084 * instruction -> ...
5085 */
5086 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5087
5088 /*
5089 * If the instruction failed on the error pfn, it can not be fixed,
5090 * report the error to userspace.
5091 */
5092 if (is_error_noslot_pfn(pfn))
5093 return false;
5094
5095 kvm_release_pfn_clean(pfn);
5096
5097 /* The instructions are well-emulated on direct mmu. */
5098 if (vcpu->arch.mmu.direct_map) {
5099 unsigned int indirect_shadow_pages;
5100
5101 spin_lock(&vcpu->kvm->mmu_lock);
5102 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5103 spin_unlock(&vcpu->kvm->mmu_lock);
5104
5105 if (indirect_shadow_pages)
5106 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5107
a6f177ef 5108 return true;
8e3d9d06 5109 }
a6f177ef 5110
95b3cf69
XG		 5111 /*
5112 * if emulation was due to access to shadowed page table
5113 * and it failed try to unshadow page and re-enter the
5114 * guest to let CPU execute the instruction.
5115 */
5116 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5117
5118 /*
5119 * If the access faults on its page table, it can not
5120 * be fixed by unprotecting shadow page and it should
5121 * be reported to userspace.
5122 */
5123 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5124}
5125
1cb3f3ae
XG		 5126static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5127 unsigned long cr2, int emulation_type)
5128{
5129 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5130 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5131
5132 last_retry_eip = vcpu->arch.last_retry_eip;
5133 last_retry_addr = vcpu->arch.last_retry_addr;
5134
5135 /*
5136 * If the emulation is caused by #PF and it is non-page_table
5137 * writing instruction, it means the VM-EXIT is caused by shadow
5138 * page protected, we can zap the shadow page and retry this
5139 * instruction directly.
5140 *
5141 * Note: if the guest uses a non-page-table modifying instruction
5142 * on the PDE that points to the instruction, then we will unmap
5143 * the instruction and go to an infinite loop. So, we cache the
5144 * last retried eip and the last fault address, if we meet the eip
5145 * and the address again, we can break out of the potential infinite
5146 * loop.
5147 */
5148 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5149
5150 if (!(emulation_type & EMULTYPE_RETRY))
5151 return false;
5152
5153 if (x86_page_table_writing_insn(ctxt))
5154 return false;
5155
5156 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5157 return false;
5158
5159 vcpu->arch.last_retry_eip = ctxt->eip;
5160 vcpu->arch.last_retry_addr = cr2;
5161
5162 if (!vcpu->arch.mmu.direct_map)
5163 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5164
22368028 5165 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5166
5167 return true;
5168}
5169
716d51ab
GN		 5170static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5171static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5172
64d60670 5173static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5174{
64d60670 5175 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5176 /* This is a good place to trace that we are exiting SMM. */
5177 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5178
64d60670
PB		 5179 if (unlikely(vcpu->arch.smi_pending)) {
5180 kvm_make_request(KVM_REQ_SMI, vcpu);
5181 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5182 } else {
5183 /* Process a latched INIT, if any. */
5184 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5185 }
5186 }
699023e2
PB		 5187
5188 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5189}
5190
5191static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5192{
5193 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5194
a584539b 5195 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5196
5197 if (changed & HF_SMM_MASK)
5198 kvm_smm_changed(vcpu);
a584539b
PB		 5199}
5200
4a1e10d5
PB		 5201static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5202 unsigned long *db)
5203{
5204 u32 dr6 = 0;
5205 int i;
5206 u32 enable, rwlen;
5207
5208 enable = dr7;
5209 rwlen = dr7 >> 16;
5210 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5211 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5212 dr6 |= (1 << i);
5213 return dr6;
5214}
5215
6addfc42 5216static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5217{
5218 struct kvm_run *kvm_run = vcpu->run;
5219
5220 /*
6addfc42
PB		 5221 * rflags is the old, "raw" value of the flags. The new value has
5222 * not been saved yet.
663f4c61
PB		 5223 *
5224 * This is correct even for TF set by the guest, because "the
5225 * processor will not generate this exception after the instruction
5226 * that sets the TF flag".
5227 */
663f4c61
PB		 5228 if (unlikely(rflags & X86_EFLAGS_TF)) {
5229 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5230 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5231 DR6_RTM;
663f4c61
PB		 5232 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5233 kvm_run->debug.arch.exception = DB_VECTOR;
5234 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5235 *r = EMULATE_USER_EXIT;
5236 } else {
5237 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5238 /*
5239 * "Certain debug exceptions may clear bit 0-3. The
5240 * remaining contents of the DR6 register are never
5241 * cleared by the processor".
5242 */
5243 vcpu->arch.dr6 &= ~15;
6f43ed01 5244 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5245 kvm_queue_exception(vcpu, DB_VECTOR);
5246 }
5247 }
5248}
5249
4a1e10d5
PB		 5250static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5251{
4a1e10d5
PB		 5252 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5253 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5254 struct kvm_run *kvm_run = vcpu->run;
5255 unsigned long eip = kvm_get_linear_rip(vcpu);
5256 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5257 vcpu->arch.guest_debug_dr7,
5258 vcpu->arch.eff_db);
5259
5260 if (dr6 != 0) {
6f43ed01 5261 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5262 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5263 kvm_run->debug.arch.exception = DB_VECTOR;
5264 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5265 *r = EMULATE_USER_EXIT;
5266 return true;
5267 }
5268 }
5269
4161a569
NA		 5270 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5271 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5272 unsigned long eip = kvm_get_linear_rip(vcpu);
5273 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5274 vcpu->arch.dr7,
5275 vcpu->arch.db);
5276
5277 if (dr6 != 0) {
5278 vcpu->arch.dr6 &= ~15;
6f43ed01 5279 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5280 kvm_queue_exception(vcpu, DB_VECTOR);
5281 *r = EMULATE_DONE;
5282 return true;
5283 }
5284 }
5285
5286 return false;
5287}
5288
51d8b661
AP		 5289int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5290 unsigned long cr2,
dc25e89e
AP		 5291 int emulation_type,
5292 void *insn,
5293 int insn_len)
bbd9b64e 5294{
95cb2295 5295 int r;
9d74191a 5296 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5297 bool writeback = true;
93c05d3e 5298 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5299
93c05d3e
XG		 5300 /*
5301 * Clear write_fault_to_shadow_pgtable here to ensure it is
5302 * never reused.
5303 */
5304 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5305 kvm_clear_exception_queue(vcpu);
8d7d8102 5306
571008da 5307 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5308 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5309
5310 /*
5311 * We will reenter on the same instruction since
5312 * we do not set complete_userspace_io. This does not
5313 * handle watchpoints yet, those would be handled in
5314 * the emulate_ops.
5315 */
5316 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5317 return r;
5318
9d74191a
TY		 5319 ctxt->interruptibility = 0;
5320 ctxt->have_exception = false;
e0ad0b47 5321 ctxt->exception.vector = -1;
9d74191a 5322 ctxt->perm_ok = false;
bbd9b64e 5323
b51e974f 5324 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5325
9d74191a 5326 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5327
e46479f8 5328 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5329 ++vcpu->stat.insn_emulation;
1d2887e2 5330 if (r != EMULATION_OK) {
4005996e
AK		 5331 if (emulation_type & EMULTYPE_TRAP_UD)
5332 return EMULATE_FAIL;
991eebf9
GN		 5333 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5334 emulation_type))
bbd9b64e 5335 return EMULATE_DONE;
6d77dbfc
GN		 5336 if (emulation_type & EMULTYPE_SKIP)
5337 return EMULATE_FAIL;
5338 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5339 }
5340 }
5341
ba8afb6b 5342 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5343 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5344 if (ctxt->eflags & X86_EFLAGS_RF)
5345 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5346 return EMULATE_DONE;
5347 }
5348
1cb3f3ae
XG		 5349 if (retry_instruction(ctxt, cr2, emulation_type))
5350 return EMULATE_DONE;
5351
7ae441ea 5352 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5353 changes registers values during IO operation */
7ae441ea
GN		 5354 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5355 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5356 emulator_invalidate_register_cache(ctxt);
7ae441ea 5357 }
4d2179e1 5358
5cd21917 5359restart:
9d74191a 5360 r = x86_emulate_insn(ctxt);
bbd9b64e 5361
775fde86
JR		 5362 if (r == EMULATION_INTERCEPTED)
5363 return EMULATE_DONE;
5364
d2ddd1c4 5365 if (r == EMULATION_FAILED) {
991eebf9
GN		 5366 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5367 emulation_type))
c3cd7ffa
GN		 5368 return EMULATE_DONE;
5369
6d77dbfc 5370 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5371 }
5372
9d74191a 5373 if (ctxt->have_exception) {
d2ddd1c4 5374 r = EMULATE_DONE;
ef54bcfe
PB		 5375 if (inject_emulated_exception(vcpu))
5376 return r;
d2ddd1c4 5377 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5378 if (!vcpu->arch.pio.in) {
5379 /* FIXME: return into emulator if single-stepping. */
3457e419 5380 vcpu->arch.pio.count = 0;
0912c977 5381 } else {
7ae441ea 5382 writeback = false;
716d51ab
GN		 5383 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5384 }
ac0a48c3 5385 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5386 } else if (vcpu->mmio_needed) {
5387 if (!vcpu->mmio_is_write)
5388 writeback = false;
ac0a48c3 5389 r = EMULATE_USER_EXIT;
716d51ab 5390 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5391 } else if (r == EMULATION_RESTART)
5cd21917 5392 goto restart;
d2ddd1c4
GN		 5393 else
5394 r = EMULATE_DONE;
f850e2e6 5395
7ae441ea 5396 if (writeback) {
6addfc42 5397 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5398 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5399 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5400 if (vcpu->arch.hflags != ctxt->emul_flags)
5401 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5402 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5403 if (r == EMULATE_DONE)
6addfc42 5404 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5405 if (!ctxt->have_exception ||
5406 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5407 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5408
5409 /*
5410 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5411 * do nothing, and it will be requested again as soon as
5412 * the shadow expires. But we still need to check here,
5413 * because POPF has no interrupt shadow.
5414 */
5415 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5416 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5417 } else
5418 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5419
5420 return r;
de7d789a 5421}
51d8b661 5422EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5423
cf8f70bf 5424int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5425{
cf8f70bf 5426 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5427 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5428 size, port, &val, 1);
cf8f70bf 5429 /* do not return to emulator after return from userspace */
7972995b 5430 vcpu->arch.pio.count = 0;
de7d789a
CO		 5431 return ret;
5432}
cf8f70bf 5433EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5434
8cfdc000
ZA		 5435static void tsc_bad(void *info)
5436{
0a3aee0d 5437 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5438}
5439
5440static void tsc_khz_changed(void *data)
c8076604 5441{
8cfdc000
ZA		 5442 struct cpufreq_freqs *freq = data;
5443 unsigned long khz = 0;
5444
5445 if (data)
5446 khz = freq->new;
5447 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5448 khz = cpufreq_quick_get(raw_smp_processor_id());
5449 if (!khz)
5450 khz = tsc_khz;
0a3aee0d 5451 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5452}
5453
c8076604
GH		 5454static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5455 void *data)
5456{
5457 struct cpufreq_freqs *freq = data;
5458 struct kvm *kvm;
5459 struct kvm_vcpu *vcpu;
5460 int i, send_ipi = 0;
5461
8cfdc000
ZA		 5462 /*
5463 * We allow guests to temporarily run on slowing clocks,
5464 * provided we notify them after, or to run on accelerating
5465 * clocks, provided we notify them before. Thus time never
5466 * goes backwards.
5467 *
5468 * However, we have a problem. We can't atomically update
5469 * the frequency of a given CPU from this function; it is
5470 * merely a notifier, which can be called from any CPU.
5471 * Changing the TSC frequency at arbitrary points in time
5472 * requires a recomputation of local variables related to
5473 * the TSC for each VCPU. We must flag these local variables
5474 * to be updated and be sure the update takes place with the
5475 * new frequency before any guests proceed.
5476 *
5477 * Unfortunately, the combination of hotplug CPU and frequency
5478 * change creates an intractable locking scenario; the order
5479 * of when these callouts happen is undefined with respect to
5480 * CPU hotplug, and they can race with each other. As such,
5481 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5482 * undefined; you can actually have a CPU frequency change take
5483 * place in between the computation of X and the setting of the
5484 * variable. To protect against this problem, all updates of
5485 * the per_cpu tsc_khz variable are done in an interrupt
5486 * protected IPI, and all callers wishing to update the value
5487 * must wait for a synchronous IPI to complete (which is trivial
5488 * if the caller is on the CPU already). This establishes the
5489 * necessary total order on variable updates.
5490 *
5491 * Note that because a guest time update may take place
5492 * anytime after the setting of the VCPU's request bit, the
5493 * correct TSC value must be set before the request. However,
5494 * to ensure the update actually makes it to any guest which
5495 * starts running in hardware virtualization between the set
5496 * and the acquisition of the spinlock, we must also ping the
5497 * CPU after setting the request bit.
5498 *
5499 */
5500
c8076604
GH		 5501 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5502 return 0;
5503 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5504 return 0;
8cfdc000
ZA		 5505
5506 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5507
2f303b74 5508 spin_lock(&kvm_lock);
c8076604 5509 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5510 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5511 if (vcpu->cpu != freq->cpu)
5512 continue;
c285545f 5513 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5514 if (vcpu->cpu != smp_processor_id())
8cfdc000 5515 send_ipi = 1;
c8076604
GH		 5516 }
5517 }
2f303b74 5518 spin_unlock(&kvm_lock);
c8076604
GH		 5519
5520 if (freq->old < freq->new && send_ipi) {
5521 /*
5522 * We upscale the frequency. Must make the guest
5523 * doesn't see old kvmclock values while running with
5524 * the new frequency, otherwise we risk the guest sees
5525 * time go backwards.
5526 *
5527 * In case we update the frequency for another cpu
5528 * (which might be in guest context) send an interrupt
5529 * to kick the cpu out of guest context. Next time
5530 * guest context is entered kvmclock will be updated,
5531 * so the guest will not see stale values.
5532 */
8cfdc000 5533 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5534 }
5535 return 0;
5536}
5537
5538static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5539 .notifier_call = kvmclock_cpufreq_notifier
5540};
5541
5542static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5543 unsigned long action, void *hcpu)
5544{
5545 unsigned int cpu = (unsigned long)hcpu;
5546
5547 switch (action) {
5548 case CPU_ONLINE:
5549 case CPU_DOWN_FAILED:
5550 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5551 break;
5552 case CPU_DOWN_PREPARE:
5553 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5554 break;
5555 }
5556 return NOTIFY_OK;
5557}
5558
5559static struct notifier_block kvmclock_cpu_notifier_block = {
5560 .notifier_call = kvmclock_cpu_notifier,
5561 .priority = -INT_MAX
c8076604
GH		 5562};
5563
b820cc0c
ZA		 5564static void kvm_timer_init(void)
5565{
5566 int cpu;
5567
c285545f 5568 max_tsc_khz = tsc_khz;
460dd42e
SB		 5569
5570 cpu_notifier_register_begin();
b820cc0c 5571 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5572#ifdef CONFIG_CPU_FREQ
5573 struct cpufreq_policy policy;
5574 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5575 cpu = get_cpu();
5576 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5577 if (policy.cpuinfo.max_freq)
5578 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5579 put_cpu();
c285545f 5580#endif
b820cc0c
ZA		 5581 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5582 CPUFREQ_TRANSITION_NOTIFIER);
5583 }
c285545f 5584 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5585 for_each_online_cpu(cpu)
5586 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5587
5588 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5589 cpu_notifier_register_done();
5590
b820cc0c
ZA		 5591}
5592
ff9d07a0
ZY		 5593static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5594
f5132b01 5595int kvm_is_in_guest(void)
ff9d07a0 5596{
086c9855 5597 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5598}
5599
5600static int kvm_is_user_mode(void)
5601{
5602 int user_mode = 3;
dcf46b94 5603
086c9855
AS		 5604 if (__this_cpu_read(current_vcpu))
5605 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5606
ff9d07a0
ZY		 5607 return user_mode != 0;
5608}
5609
5610static unsigned long kvm_get_guest_ip(void)
5611{
5612 unsigned long ip = 0;
dcf46b94 5613
086c9855
AS		 5614 if (__this_cpu_read(current_vcpu))
5615 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5616
ff9d07a0
ZY		 5617 return ip;
5618}
5619
5620static struct perf_guest_info_callbacks kvm_guest_cbs = {
5621 .is_in_guest = kvm_is_in_guest,
5622 .is_user_mode = kvm_is_user_mode,
5623 .get_guest_ip = kvm_get_guest_ip,
5624};
5625
5626void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5627{
086c9855 5628 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5629}
5630EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5631
5632void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5633{
086c9855 5634 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5635}
5636EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5637
ce88decf
XG		 5638static void kvm_set_mmio_spte_mask(void)
5639{
5640 u64 mask;
5641 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5642
5643 /*
5644 * Set the reserved bits and the present bit of an paging-structure
5645 * entry to generate page fault with PFER.RSV = 1.
5646 */
885032b9 5647 /* Mask the reserved physical address bits. */
d1431483 5648 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5649
5650 /* Bit 62 is always reserved for 32bit host. */
5651 mask |= 0x3ull << 62;
5652
5653 /* Set the present bit. */
ce88decf
XG		 5654 mask |= 1ull;
5655
5656#ifdef CONFIG_X86_64
5657 /*
5658 * If reserved bit is not supported, clear the present bit to disable
5659 * mmio page fault.
5660 */
5661 if (maxphyaddr == 52)
5662 mask &= ~1ull;
5663#endif
5664
5665 kvm_mmu_set_mmio_spte_mask(mask);
5666}
5667
16e8d74d
MT		 5668#ifdef CONFIG_X86_64
5669static void pvclock_gtod_update_fn(struct work_struct *work)
5670{
d828199e
MT		 5671 struct kvm *kvm;
5672
5673 struct kvm_vcpu *vcpu;
5674 int i;
5675
2f303b74 5676 spin_lock(&kvm_lock);
d828199e
MT		 5677 list_for_each_entry(kvm, &vm_list, vm_list)
5678 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5679 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5680 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5681 spin_unlock(&kvm_lock);
16e8d74d
MT		 5682}
5683
5684static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5685
5686/*
5687 * Notification about pvclock gtod data update.
5688 */
5689static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5690 void *priv)
5691{
5692 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5693 struct timekeeper *tk = priv;
5694
5695 update_pvclock_gtod(tk);
5696
5697 /* disable master clock if host does not trust, or does not
5698 * use, TSC clocksource
5699 */
5700 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5701 atomic_read(&kvm_guest_has_master_clock) != 0)
5702 queue_work(system_long_wq, &pvclock_gtod_work);
5703
5704 return 0;
5705}
5706
5707static struct notifier_block pvclock_gtod_notifier = {
5708 .notifier_call = pvclock_gtod_notify,
5709};
5710#endif
5711
f8c16bba 5712int kvm_arch_init(void *opaque)
043405e1 5713{
b820cc0c 5714 int r;
6b61edf7 5715 struct kvm_x86_ops *ops = opaque;
f8c16bba 5716
f8c16bba
ZX		 5717 if (kvm_x86_ops) {
5718 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5719 r = -EEXIST;
5720 goto out;
f8c16bba
ZX		 5721 }
5722
5723 if (!ops->cpu_has_kvm_support()) {
5724 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5725 r = -EOPNOTSUPP;
5726 goto out;
f8c16bba
ZX		 5727 }
5728 if (ops->disabled_by_bios()) {
5729 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5730 r = -EOPNOTSUPP;
5731 goto out;
f8c16bba
ZX		 5732 }
5733
013f6a5d
MT		 5734 r = -ENOMEM;
5735 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5736 if (!shared_msrs) {
5737 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5738 goto out;
5739 }
5740
97db56ce
AK		 5741 r = kvm_mmu_module_init();
5742 if (r)
013f6a5d 5743 goto out_free_percpu;
97db56ce 5744
ce88decf 5745 kvm_set_mmio_spte_mask();
97db56ce 5746
f8c16bba 5747 kvm_x86_ops = ops;
920c8377 5748
7b52345e 5749 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5750 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5751
b820cc0c 5752 kvm_timer_init();
c8076604 5753
ff9d07a0
ZY		 5754 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5755
2acf923e
DC		 5756 if (cpu_has_xsave)
5757 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5758
c5cc421b 5759 kvm_lapic_init();
16e8d74d
MT		 5760#ifdef CONFIG_X86_64
5761 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5762#endif
5763
f8c16bba 5764 return 0;
56c6d28a 5765
013f6a5d
MT		 5766out_free_percpu:
5767 free_percpu(shared_msrs);
56c6d28a 5768out:
56c6d28a 5769 return r;
043405e1 5770}
8776e519 5771
f8c16bba
ZX		 5772void kvm_arch_exit(void)
5773{
ff9d07a0
ZY		 5774 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5775
888d256e
JK		 5776 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5777 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5778 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5779 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5780#ifdef CONFIG_X86_64
5781 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5782#endif
f8c16bba 5783 kvm_x86_ops = NULL;
56c6d28a 5784 kvm_mmu_module_exit();
013f6a5d 5785 free_percpu(shared_msrs);
56c6d28a 5786}
f8c16bba 5787
5cb56059 5788int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5789{
5790 ++vcpu->stat.halt_exits;
35754c98 5791 if (lapic_in_kernel(vcpu)) {
a4535290 5792 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5793 return 1;
5794 } else {
5795 vcpu->run->exit_reason = KVM_EXIT_HLT;
5796 return 0;
5797 }
5798}
5cb56059
JS		 5799EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5800
5801int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5802{
5803 kvm_x86_ops->skip_emulated_instruction(vcpu);
5804 return kvm_vcpu_halt(vcpu);
5805}
8776e519
HB		 5806EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5807
6aef266c
SV		 5808/*
5809 * kvm_pv_kick_cpu_op: Kick a vcpu.
5810 *
5811 * @apicid - apicid of vcpu to be kicked.
5812 */
5813static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5814{
24d2166b 5815 struct kvm_lapic_irq lapic_irq;
6aef266c 5816
24d2166b
R		 5817 lapic_irq.shorthand = 0;
5818 lapic_irq.dest_mode = 0;
5819 lapic_irq.dest_id = apicid;
93bbf0b8 5820 lapic_irq.msi_redir_hint = false;
6aef266c 5821
24d2166b 5822 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5823 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5824}
5825
8776e519
HB		 5826int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5827{
5828 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5829 int op_64_bit, r = 1;
8776e519 5830
5cb56059
JS		 5831 kvm_x86_ops->skip_emulated_instruction(vcpu);
5832
55cd8e5a
GN		 5833 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5834 return kvm_hv_hypercall(vcpu);
5835
5fdbf976
MT		 5836 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5837 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5838 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5839 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5840 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5841
229456fc 5842 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5843
a449c7aa
NA		 5844 op_64_bit = is_64_bit_mode(vcpu);
5845 if (!op_64_bit) {
8776e519
HB		 5846 nr &= 0xFFFFFFFF;
5847 a0 &= 0xFFFFFFFF;
5848 a1 &= 0xFFFFFFFF;
5849 a2 &= 0xFFFFFFFF;
5850 a3 &= 0xFFFFFFFF;
5851 }
5852
07708c4a
JK		 5853 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5854 ret = -KVM_EPERM;
5855 goto out;
5856 }
5857
8776e519 5858 switch (nr) {
b93463aa
AK		 5859 case KVM_HC_VAPIC_POLL_IRQ:
5860 ret = 0;
5861 break;
6aef266c
SV		 5862 case KVM_HC_KICK_CPU:
5863 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5864 ret = 0;
5865 break;
8776e519
HB		 5866 default:
5867 ret = -KVM_ENOSYS;
5868 break;
5869 }
07708c4a 5870out:
a449c7aa
NA		 5871 if (!op_64_bit)
5872 ret = (u32)ret;
5fdbf976 5873 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5874 ++vcpu->stat.hypercalls;
2f333bcb 5875 return r;
8776e519
HB		 5876}
5877EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5878
b6785def 5879static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5880{
d6aa1000 5881 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5882 char instruction[3];
5fdbf976 5883 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5884
8776e519 5885 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5886
9d74191a 5887 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5888}
5889
b6c7a5dc
HB		 5890/*
5891 * Check if userspace requested an interrupt window, and that the
5892 * interrupt window is open.
5893 *
5894 * No need to exit to userspace if we already have an interrupt queued.
5895 */
851ba692 5896static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5897{
1c1a9ce9
SR		 5898 if (!vcpu->run->request_interrupt_window || pic_in_kernel(vcpu->kvm))
5899 return false;
5900
5901 if (kvm_cpu_has_interrupt(vcpu))
5902 return false;
5903
5904 return (irqchip_split(vcpu->kvm)
5905 ? kvm_apic_accept_pic_intr(vcpu)
5906 : kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5907}
5908
851ba692 5909static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5910{
851ba692
AK		 5911 struct kvm_run *kvm_run = vcpu->run;
5912
91586a3b 5913 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5914 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5915 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5916 kvm_run->apic_base = kvm_get_apic_base(vcpu);
1c1a9ce9 5917 if (!irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5918 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5919 kvm_arch_interrupt_allowed(vcpu) &&
5920 !kvm_cpu_has_interrupt(vcpu) &&
5921 !kvm_event_needs_reinjection(vcpu);
1c1a9ce9
SR		 5922 else if (!pic_in_kernel(vcpu->kvm))
5923 kvm_run->ready_for_interrupt_injection =
5924 kvm_apic_accept_pic_intr(vcpu) &&
5925 !kvm_cpu_has_interrupt(vcpu);
5926 else
5927 kvm_run->ready_for_interrupt_injection = 1;
b6c7a5dc
HB		 5928}
5929
95ba8273
GN		 5930static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5931{
5932 int max_irr, tpr;
5933
5934 if (!kvm_x86_ops->update_cr8_intercept)
5935 return;
5936
88c808fd
AK		 5937 if (!vcpu->arch.apic)
5938 return;
5939
8db3baa2
GN		 5940 if (!vcpu->arch.apic->vapic_addr)
5941 max_irr = kvm_lapic_find_highest_irr(vcpu);
5942 else
5943 max_irr = -1;
95ba8273
GN		 5944
5945 if (max_irr != -1)
5946 max_irr >>= 4;
5947
5948 tpr = kvm_lapic_get_cr8(vcpu);
5949
5950 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5951}
5952
b6b8a145 5953static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5954{
b6b8a145
JK		 5955 int r;
5956
95ba8273 5957 /* try to reinject previous events if any */
b59bb7bd 5958 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5959 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5960 vcpu->arch.exception.has_error_code,
5961 vcpu->arch.exception.error_code);
d6e8c854
NA		 5962
5963 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5964 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5965 X86_EFLAGS_RF);
5966
6bdf0662
NA		 5967 if (vcpu->arch.exception.nr == DB_VECTOR &&
5968 (vcpu->arch.dr7 & DR7_GD)) {
5969 vcpu->arch.dr7 &= ~DR7_GD;
5970 kvm_update_dr7(vcpu);
5971 }
5972
b59bb7bd
GN		 5973 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5974 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5975 vcpu->arch.exception.error_code,
5976 vcpu->arch.exception.reinject);
b6b8a145 5977 return 0;
b59bb7bd
GN		 5978 }
5979
95ba8273
GN		 5980 if (vcpu->arch.nmi_injected) {
5981 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5982 return 0;
95ba8273
GN		 5983 }
5984
5985 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5986 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5987 return 0;
5988 }
5989
5990 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5991 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5992 if (r != 0)
5993 return r;
95ba8273
GN		 5994 }
5995
5996 /* try to inject new event if pending */
5997 if (vcpu->arch.nmi_pending) {
5998 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5999 --vcpu->arch.nmi_pending;
95ba8273
GN		 6000 vcpu->arch.nmi_injected = true;
6001 kvm_x86_ops->set_nmi(vcpu);
6002 }
c7c9c56c 6003 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6004 /*
6005 * Because interrupts can be injected asynchronously, we are
6006 * calling check_nested_events again here to avoid a race condition.
6007 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6008 * proposal and current concerns. Perhaps we should be setting
6009 * KVM_REQ_EVENT only on certain events and not unconditionally?
6010 */
6011 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6012 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6013 if (r != 0)
6014 return r;
6015 }
95ba8273 6016 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6017 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6018 false);
6019 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6020 }
6021 }
b6b8a145 6022 return 0;
95ba8273
GN		 6023}
6024
7460fb4a
AK		 6025static void process_nmi(struct kvm_vcpu *vcpu)
6026{
6027 unsigned limit = 2;
6028
6029 /*
6030 * x86 is limited to one NMI running, and one NMI pending after it.
6031 * If an NMI is already in progress, limit further NMIs to just one.
6032 * Otherwise, allow two (and we'll inject the first one immediately).
6033 */
6034 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6035 limit = 1;
6036
6037 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6038 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6039 kvm_make_request(KVM_REQ_EVENT, vcpu);
6040}
6041
660a5d51
PB		 6042#define put_smstate(type, buf, offset, val) \
6043 *(type *)((buf) + (offset) - 0x7e00) = val
6044
6045static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6046{
6047 u32 flags = 0;
6048 flags |= seg->g << 23;
6049 flags |= seg->db << 22;
6050 flags |= seg->l << 21;
6051 flags |= seg->avl << 20;
6052 flags |= seg->present << 15;
6053 flags |= seg->dpl << 13;
6054 flags |= seg->s << 12;
6055 flags |= seg->type << 8;
6056 return flags;
6057}
6058
6059static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6060{
6061 struct kvm_segment seg;
6062 int offset;
6063
6064 kvm_get_segment(vcpu, &seg, n);
6065 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6066
6067 if (n < 3)
6068 offset = 0x7f84 + n * 12;
6069 else
6070 offset = 0x7f2c + (n - 3) * 12;
6071
6072 put_smstate(u32, buf, offset + 8, seg.base);
6073 put_smstate(u32, buf, offset + 4, seg.limit);
6074 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6075}
6076
efbb288a 6077#ifdef CONFIG_X86_64
660a5d51
PB		 6078static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6079{
6080 struct kvm_segment seg;
6081 int offset;
6082 u16 flags;
6083
6084 kvm_get_segment(vcpu, &seg, n);
6085 offset = 0x7e00 + n * 16;
6086
6087 flags = process_smi_get_segment_flags(&seg) >> 8;
6088 put_smstate(u16, buf, offset, seg.selector);
6089 put_smstate(u16, buf, offset + 2, flags);
6090 put_smstate(u32, buf, offset + 4, seg.limit);
6091 put_smstate(u64, buf, offset + 8, seg.base);
6092}
efbb288a 6093#endif
660a5d51
PB		 6094
6095static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6096{
6097 struct desc_ptr dt;
6098 struct kvm_segment seg;
6099 unsigned long val;
6100 int i;
6101
6102 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6103 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6104 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6105 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6106
6107 for (i = 0; i < 8; i++)
6108 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6109
6110 kvm_get_dr(vcpu, 6, &val);
6111 put_smstate(u32, buf, 0x7fcc, (u32)val);
6112 kvm_get_dr(vcpu, 7, &val);
6113 put_smstate(u32, buf, 0x7fc8, (u32)val);
6114
6115 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6116 put_smstate(u32, buf, 0x7fc4, seg.selector);
6117 put_smstate(u32, buf, 0x7f64, seg.base);
6118 put_smstate(u32, buf, 0x7f60, seg.limit);
6119 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6120
6121 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6122 put_smstate(u32, buf, 0x7fc0, seg.selector);
6123 put_smstate(u32, buf, 0x7f80, seg.base);
6124 put_smstate(u32, buf, 0x7f7c, seg.limit);
6125 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6126
6127 kvm_x86_ops->get_gdt(vcpu, &dt);
6128 put_smstate(u32, buf, 0x7f74, dt.address);
6129 put_smstate(u32, buf, 0x7f70, dt.size);
6130
6131 kvm_x86_ops->get_idt(vcpu, &dt);
6132 put_smstate(u32, buf, 0x7f58, dt.address);
6133 put_smstate(u32, buf, 0x7f54, dt.size);
6134
6135 for (i = 0; i < 6; i++)
6136 process_smi_save_seg_32(vcpu, buf, i);
6137
6138 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6139
6140 /* revision id */
6141 put_smstate(u32, buf, 0x7efc, 0x00020000);
6142 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6143}
6144
6145static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6146{
6147#ifdef CONFIG_X86_64
6148 struct desc_ptr dt;
6149 struct kvm_segment seg;
6150 unsigned long val;
6151 int i;
6152
6153 for (i = 0; i < 16; i++)
6154 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6155
6156 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6157 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6158
6159 kvm_get_dr(vcpu, 6, &val);
6160 put_smstate(u64, buf, 0x7f68, val);
6161 kvm_get_dr(vcpu, 7, &val);
6162 put_smstate(u64, buf, 0x7f60, val);
6163
6164 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6165 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6166 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6167
6168 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6169
6170 /* revision id */
6171 put_smstate(u32, buf, 0x7efc, 0x00020064);
6172
6173 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6174
6175 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6176 put_smstate(u16, buf, 0x7e90, seg.selector);
6177 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6178 put_smstate(u32, buf, 0x7e94, seg.limit);
6179 put_smstate(u64, buf, 0x7e98, seg.base);
6180
6181 kvm_x86_ops->get_idt(vcpu, &dt);
6182 put_smstate(u32, buf, 0x7e84, dt.size);
6183 put_smstate(u64, buf, 0x7e88, dt.address);
6184
6185 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6186 put_smstate(u16, buf, 0x7e70, seg.selector);
6187 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6188 put_smstate(u32, buf, 0x7e74, seg.limit);
6189 put_smstate(u64, buf, 0x7e78, seg.base);
6190
6191 kvm_x86_ops->get_gdt(vcpu, &dt);
6192 put_smstate(u32, buf, 0x7e64, dt.size);
6193 put_smstate(u64, buf, 0x7e68, dt.address);
6194
6195 for (i = 0; i < 6; i++)
6196 process_smi_save_seg_64(vcpu, buf, i);
6197#else
6198 WARN_ON_ONCE(1);
6199#endif
6200}
6201
64d60670
PB		 6202static void process_smi(struct kvm_vcpu *vcpu)
6203{
660a5d51 6204 struct kvm_segment cs, ds;
18c3626e 6205 struct desc_ptr dt;
660a5d51
PB		 6206 char buf[512];
6207 u32 cr0;
6208
64d60670
PB		 6209 if (is_smm(vcpu)) {
6210 vcpu->arch.smi_pending = true;
6211 return;
6212 }
6213
660a5d51
PB		 6214 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6215 vcpu->arch.hflags |= HF_SMM_MASK;
6216 memset(buf, 0, 512);
6217 if (guest_cpuid_has_longmode(vcpu))
6218 process_smi_save_state_64(vcpu, buf);
6219 else
6220 process_smi_save_state_32(vcpu, buf);
6221
54bf36aa 6222 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6223
6224 if (kvm_x86_ops->get_nmi_mask(vcpu))
6225 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6226 else
6227 kvm_x86_ops->set_nmi_mask(vcpu, true);
6228
6229 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6230 kvm_rip_write(vcpu, 0x8000);
6231
6232 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6233 kvm_x86_ops->set_cr0(vcpu, cr0);
6234 vcpu->arch.cr0 = cr0;
6235
6236 kvm_x86_ops->set_cr4(vcpu, 0);
6237
18c3626e
PB		 6238 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6239 dt.address = dt.size = 0;
6240 kvm_x86_ops->set_idt(vcpu, &dt);
6241
660a5d51
PB		 6242 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6243
6244 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6245 cs.base = vcpu->arch.smbase;
6246
6247 ds.selector = 0;
6248 ds.base = 0;
6249
6250 cs.limit = ds.limit = 0xffffffff;
6251 cs.type = ds.type = 0x3;
6252 cs.dpl = ds.dpl = 0;
6253 cs.db = ds.db = 0;
6254 cs.s = ds.s = 1;
6255 cs.l = ds.l = 0;
6256 cs.g = ds.g = 1;
6257 cs.avl = ds.avl = 0;
6258 cs.present = ds.present = 1;
6259 cs.unusable = ds.unusable = 0;
6260 cs.padding = ds.padding = 0;
6261
6262 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6263 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6264 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6265 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6266 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6267 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6268
6269 if (guest_cpuid_has_longmode(vcpu))
6270 kvm_x86_ops->set_efer(vcpu, 0);
6271
6272 kvm_update_cpuid(vcpu);
6273 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6274}
6275
3d81bc7e 6276static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6277{
3d81bc7e
YZ		 6278 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6279 return;
c7c9c56c 6280
3bb345f3 6281 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
c7c9c56c 6282
b053b2ae
SR		 6283 if (irqchip_split(vcpu->kvm))
6284 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb
RK		 6285 else {
6286 kvm_x86_ops->sync_pir_to_irr(vcpu);
b053b2ae 6287 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb 6288 }
3bb345f3 6289 kvm_x86_ops->load_eoi_exitmap(vcpu);
c7c9c56c
YZ		 6290}
6291
a70656b6
RK		 6292static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6293{
6294 ++vcpu->stat.tlb_flush;
6295 kvm_x86_ops->tlb_flush(vcpu);
6296}
6297
4256f43f
TC		 6298void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6299{
c24ae0dc
TC		 6300 struct page *page = NULL;
6301
35754c98 6302 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6303 return;
6304
4256f43f
TC		 6305 if (!kvm_x86_ops->set_apic_access_page_addr)
6306 return;
6307
c24ae0dc 6308 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6309 if (is_error_page(page))
6310 return;
c24ae0dc
TC		 6311 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6312
6313 /*
6314 * Do not pin apic access page in memory, the MMU notifier
6315 * will call us again if it is migrated or swapped out.
6316 */
6317 put_page(page);
4256f43f
TC		 6318}
6319EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6320
fe71557a
TC		 6321void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6322 unsigned long address)
6323{
c24ae0dc
TC		 6324 /*
6325 * The physical address of apic access page is stored in the VMCS.
6326 * Update it when it becomes invalid.
6327 */
6328 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6329 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6330}
6331
9357d939 6332/*
362c698f 6333 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6334 * exiting to the userspace. Otherwise, the value will be returned to the
6335 * userspace.
6336 */
851ba692 6337static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6338{
6339 int r;
35754c98 6340 bool req_int_win = !lapic_in_kernel(vcpu) &&
851ba692 6341 vcpu->run->request_interrupt_window;
730dca42 6342 bool req_immediate_exit = false;
b6c7a5dc 6343
3e007509 6344 if (vcpu->requests) {
a8eeb04a 6345 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6346 kvm_mmu_unload(vcpu);
a8eeb04a 6347 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6348 __kvm_migrate_timers(vcpu);
d828199e
MT		 6349 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6350 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6351 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6352 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6353 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6354 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6355 if (unlikely(r))
6356 goto out;
6357 }
a8eeb04a 6358 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6359 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6360 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6361 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6362 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6363 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6364 r = 0;
6365 goto out;
6366 }
a8eeb04a 6367 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6368 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6369 r = 0;
6370 goto out;
6371 }
a8eeb04a 6372 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6373 vcpu->fpu_active = 0;
6374 kvm_x86_ops->fpu_deactivate(vcpu);
6375 }
af585b92
GN		 6376 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6377 /* Page is swapped out. Do synthetic halt */
6378 vcpu->arch.apf.halted = true;
6379 r = 1;
6380 goto out;
6381 }
c9aaa895
GC		 6382 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6383 record_steal_time(vcpu);
64d60670
PB		 6384 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6385 process_smi(vcpu);
7460fb4a
AK		 6386 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6387 process_nmi(vcpu);
f5132b01 6388 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6389 kvm_pmu_handle_event(vcpu);
f5132b01 6390 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6391 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6392 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6393 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6394 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6395 (void *) vcpu->arch.eoi_exit_bitmap)) {
6396 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6397 vcpu->run->eoi.vector =
6398 vcpu->arch.pending_ioapic_eoi;
6399 r = 0;
6400 goto out;
6401 }
6402 }
3d81bc7e
YZ		 6403 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6404 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6405 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6406 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6407 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6408 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6409 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6410 r = 0;
6411 goto out;
6412 }
e516cebb
AS		 6413 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6414 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6415 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6416 r = 0;
6417 goto out;
6418 }
2f52d58c 6419 }
b93463aa 6420
bf9f6ac8
FW		 6421 /*
6422 * KVM_REQ_EVENT is not set when posted interrupts are set by
6423 * VT-d hardware, so we have to update RVI unconditionally.
6424 */
6425 if (kvm_lapic_enabled(vcpu)) {
6426 /*
6427 * Update architecture specific hints for APIC
6428 * virtual interrupt delivery.
6429 */
6430 if (kvm_x86_ops->hwapic_irr_update)
6431 kvm_x86_ops->hwapic_irr_update(vcpu,
6432 kvm_lapic_find_highest_irr(vcpu));
6433 }
6434
b463a6f7 6435 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6436 kvm_apic_accept_events(vcpu);
6437 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6438 r = 1;
6439 goto out;
6440 }
6441
b6b8a145
JK		 6442 if (inject_pending_event(vcpu, req_int_win) != 0)
6443 req_immediate_exit = true;
b463a6f7 6444 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6445 else if (vcpu->arch.nmi_pending)
c9a7953f 6446 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6447 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6448 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6449
6450 if (kvm_lapic_enabled(vcpu)) {
6451 update_cr8_intercept(vcpu);
6452 kvm_lapic_sync_to_vapic(vcpu);
6453 }
6454 }
6455
d8368af8
AK		 6456 r = kvm_mmu_reload(vcpu);
6457 if (unlikely(r)) {
d905c069 6458 goto cancel_injection;
d8368af8
AK		 6459 }
6460
b6c7a5dc
HB		 6461 preempt_disable();
6462
6463 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6464 if (vcpu->fpu_active)
6465 kvm_load_guest_fpu(vcpu);
2acf923e 6466 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6467
6b7e2d09
XG		 6468 vcpu->mode = IN_GUEST_MODE;
6469
01b71917
MT		 6470 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6471
6b7e2d09
XG		 6472 /* We should set ->mode before check ->requests,
6473 * see the comment in make_all_cpus_request.
6474 */
01b71917 6475 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6476
d94e1dc9 6477 local_irq_disable();
32f88400 6478
6b7e2d09 6479 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6480 || need_resched() || signal_pending(current)) {
6b7e2d09 6481 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6482 smp_wmb();
6c142801
AK		 6483 local_irq_enable();
6484 preempt_enable();
01b71917 6485 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6486 r = 1;
d905c069 6487 goto cancel_injection;
6c142801
AK		 6488 }
6489
d6185f20
NHE		 6490 if (req_immediate_exit)
6491 smp_send_reschedule(vcpu->cpu);
6492
ccf73aaf 6493 __kvm_guest_enter();
b6c7a5dc 6494
42dbaa5a 6495 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6496 set_debugreg(0, 7);
6497 set_debugreg(vcpu->arch.eff_db[0], 0);
6498 set_debugreg(vcpu->arch.eff_db[1], 1);
6499 set_debugreg(vcpu->arch.eff_db[2], 2);
6500 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6501 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6502 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6503 }
b6c7a5dc 6504
229456fc 6505 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6506 wait_lapic_expire(vcpu);
851ba692 6507 kvm_x86_ops->run(vcpu);
b6c7a5dc 6508
c77fb5fe
PB		 6509 /*
6510 * Do this here before restoring debug registers on the host. And
6511 * since we do this before handling the vmexit, a DR access vmexit
6512 * can (a) read the correct value of the debug registers, (b) set
6513 * KVM_DEBUGREG_WONT_EXIT again.
6514 */
6515 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6516 int i;
6517
6518 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6519 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6520 for (i = 0; i < KVM_NR_DB_REGS; i++)
6521 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6522 }
6523
24f1e32c
FW		 6524 /*
6525 * If the guest has used debug registers, at least dr7
6526 * will be disabled while returning to the host.
6527 * If we don't have active breakpoints in the host, we don't
6528 * care about the messed up debug address registers. But if
6529 * we have some of them active, restore the old state.
6530 */
59d8eb53 6531 if (hw_breakpoint_active())
24f1e32c 6532 hw_breakpoint_restore();
42dbaa5a 6533
886b470c 6534 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
4ea1636b 6535 rdtsc());
1d5f066e 6536
6b7e2d09 6537 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6538 smp_wmb();
a547c6db
YZ		 6539
6540 /* Interrupt is enabled by handle_external_intr() */
6541 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6542
6543 ++vcpu->stat.exits;
6544
6545 /*
6546 * We must have an instruction between local_irq_enable() and
6547 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6548 * the interrupt shadow. The stat.exits increment will do nicely.
6549 * But we need to prevent reordering, hence this barrier():
6550 */
6551 barrier();
6552
6553 kvm_guest_exit();
6554
6555 preempt_enable();
6556
f656ce01 6557 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6558
b6c7a5dc
HB		 6559 /*
6560 * Profile KVM exit RIPs:
6561 */
6562 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6563 unsigned long rip = kvm_rip_read(vcpu);
6564 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6565 }
6566
cc578287
ZA		 6567 if (unlikely(vcpu->arch.tsc_always_catchup))
6568 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6569
5cfb1d5a
MT		 6570 if (vcpu->arch.apic_attention)
6571 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6572
851ba692 6573 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6574 return r;
6575
6576cancel_injection:
6577 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6578 if (unlikely(vcpu->arch.apic_attention))
6579 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6580out:
6581 return r;
6582}
b6c7a5dc 6583
362c698f
PB		 6584static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6585{
bf9f6ac8
FW		 6586 if (!kvm_arch_vcpu_runnable(vcpu) &&
6587 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6588 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6589 kvm_vcpu_block(vcpu);
6590 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6591
6592 if (kvm_x86_ops->post_block)
6593 kvm_x86_ops->post_block(vcpu);
6594
9c8fd1ba
PB		 6595 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6596 return 1;
6597 }
362c698f
PB		 6598
6599 kvm_apic_accept_events(vcpu);
6600 switch(vcpu->arch.mp_state) {
6601 case KVM_MP_STATE_HALTED:
6602 vcpu->arch.pv.pv_unhalted = false;
6603 vcpu->arch.mp_state =
6604 KVM_MP_STATE_RUNNABLE;
6605 case KVM_MP_STATE_RUNNABLE:
6606 vcpu->arch.apf.halted = false;
6607 break;
6608 case KVM_MP_STATE_INIT_RECEIVED:
6609 break;
6610 default:
6611 return -EINTR;
6612 break;
6613 }
6614 return 1;
6615}
09cec754 6616
5d9bc648
PB		 6617static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6618{
6619 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6620 !vcpu->arch.apf.halted);
6621}
6622
362c698f 6623static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6624{
6625 int r;
f656ce01 6626 struct kvm *kvm = vcpu->kvm;
d7690175 6627
f656ce01 6628 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6629
362c698f 6630 for (;;) {
58f800d5 6631 if (kvm_vcpu_running(vcpu)) {
851ba692 6632 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6633 } else {
362c698f 6634 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6635 }
6636
09cec754
GN		 6637 if (r <= 0)
6638 break;
6639
6640 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6641 if (kvm_cpu_has_pending_timer(vcpu))
6642 kvm_inject_pending_timer_irqs(vcpu);
6643
851ba692 6644 if (dm_request_for_irq_injection(vcpu)) {
4ca7dd8c
PB		 6645 r = 0;
6646 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6647 ++vcpu->stat.request_irq_exits;
362c698f 6648 break;
09cec754 6649 }
af585b92
GN		 6650
6651 kvm_check_async_pf_completion(vcpu);
6652
09cec754
GN		 6653 if (signal_pending(current)) {
6654 r = -EINTR;
851ba692 6655 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6656 ++vcpu->stat.signal_exits;
362c698f 6657 break;
09cec754
GN		 6658 }
6659 if (need_resched()) {
f656ce01 6660 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6661 cond_resched();
f656ce01 6662 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6663 }
b6c7a5dc
HB		 6664 }
6665
f656ce01 6666 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6667
6668 return r;
6669}
6670
716d51ab
GN		 6671static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6672{
6673 int r;
6674 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6675 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6676 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6677 if (r != EMULATE_DONE)
6678 return 0;
6679 return 1;
6680}
6681
6682static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6683{
6684 BUG_ON(!vcpu->arch.pio.count);
6685
6686 return complete_emulated_io(vcpu);
6687}
6688
f78146b0
AK		 6689/*
6690 * Implements the following, as a state machine:
6691 *
6692 * read:
6693 * for each fragment
87da7e66
XG		 6694 * for each mmio piece in the fragment
6695 * write gpa, len
6696 * exit
6697 * copy data
f78146b0
AK		 6698 * execute insn
6699 *
6700 * write:
6701 * for each fragment
87da7e66
XG		 6702 * for each mmio piece in the fragment
6703 * write gpa, len
6704 * copy data
6705 * exit
f78146b0 6706 */
716d51ab 6707static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6708{
6709 struct kvm_run *run = vcpu->run;
f78146b0 6710 struct kvm_mmio_fragment *frag;
87da7e66 6711 unsigned len;
5287f194 6712
716d51ab 6713 BUG_ON(!vcpu->mmio_needed);
5287f194 6714
716d51ab 6715 /* Complete previous fragment */
87da7e66
XG		 6716 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6717 len = min(8u, frag->len);
716d51ab 6718 if (!vcpu->mmio_is_write)
87da7e66
XG		 6719 memcpy(frag->data, run->mmio.data, len);
6720
6721 if (frag->len <= 8) {
6722 /* Switch to the next fragment. */
6723 frag++;
6724 vcpu->mmio_cur_fragment++;
6725 } else {
6726 /* Go forward to the next mmio piece. */
6727 frag->data += len;
6728 frag->gpa += len;
6729 frag->len -= len;
6730 }
6731
a08d3b3b 6732 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6733 vcpu->mmio_needed = 0;
0912c977
PB		 6734
6735 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6736 if (vcpu->mmio_is_write)
716d51ab
GN		 6737 return 1;
6738 vcpu->mmio_read_completed = 1;
6739 return complete_emulated_io(vcpu);
6740 }
87da7e66 6741
716d51ab
GN		 6742 run->exit_reason = KVM_EXIT_MMIO;
6743 run->mmio.phys_addr = frag->gpa;
6744 if (vcpu->mmio_is_write)
87da7e66
XG		 6745 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6746 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6747 run->mmio.is_write = vcpu->mmio_is_write;
6748 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6749 return 0;
5287f194
AK		 6750}
6751
716d51ab 6752
b6c7a5dc
HB		 6753int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6754{
c5bedc68 6755 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6756 int r;
6757 sigset_t sigsaved;
6758
c4d72e2d 6759 fpu__activate_curr(fpu);
e5c30142 6760
ac9f6dc0
AK		 6761 if (vcpu->sigset_active)
6762 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6763
a4535290 6764 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6765 kvm_vcpu_block(vcpu);
66450a21 6766 kvm_apic_accept_events(vcpu);
d7690175 6767 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6768 r = -EAGAIN;
6769 goto out;
b6c7a5dc
HB		 6770 }
6771
b6c7a5dc 6772 /* re-sync apic's tpr */
35754c98 6773 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6774 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6775 r = -EINVAL;
6776 goto out;
6777 }
6778 }
b6c7a5dc 6779
716d51ab
GN		 6780 if (unlikely(vcpu->arch.complete_userspace_io)) {
6781 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6782 vcpu->arch.complete_userspace_io = NULL;
6783 r = cui(vcpu);
6784 if (r <= 0)
6785 goto out;
6786 } else
6787 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6788
362c698f 6789 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6790
6791out:
f1d86e46 6792 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6793 if (vcpu->sigset_active)
6794 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6795
b6c7a5dc
HB		 6796 return r;
6797}
6798
6799int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6800{
7ae441ea
GN		 6801 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6802 /*
6803 * We are here if userspace calls get_regs() in the middle of
6804 * instruction emulation. Registers state needs to be copied
4a969980 6805 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6806 * that usually, but some bad designed PV devices (vmware
6807 * backdoor interface) need this to work
6808 */
dd856efa 6809 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6810 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6811 }
5fdbf976
MT		 6812 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6813 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6814 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6815 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6816 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6817 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6818 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6819 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6820#ifdef CONFIG_X86_64
5fdbf976
MT		 6821 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6822 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6823 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6824 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6825 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6826 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6827 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6828 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6829#endif
6830
5fdbf976 6831 regs->rip = kvm_rip_read(vcpu);
91586a3b 6832 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6833
b6c7a5dc
HB		 6834 return 0;
6835}
6836
6837int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6838{
7ae441ea
GN		 6839 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6840 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6841
5fdbf976
MT		 6842 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6843 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6844 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6845 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6846 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6847 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6848 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6849 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6850#ifdef CONFIG_X86_64
5fdbf976
MT		 6851 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6852 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6853 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6854 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6855 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6856 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6857 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6858 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6859#endif
6860
5fdbf976 6861 kvm_rip_write(vcpu, regs->rip);
91586a3b 6862 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6863
b4f14abd
JK		 6864 vcpu->arch.exception.pending = false;
6865
3842d135
AK		 6866 kvm_make_request(KVM_REQ_EVENT, vcpu);
6867
b6c7a5dc
HB		 6868 return 0;
6869}
6870
b6c7a5dc
HB		 6871void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6872{
6873 struct kvm_segment cs;
6874
3e6e0aab 6875 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6876 *db = cs.db;
6877 *l = cs.l;
6878}
6879EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6880
6881int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6882 struct kvm_sregs *sregs)
6883{
89a27f4d 6884 struct desc_ptr dt;
b6c7a5dc 6885
3e6e0aab
GT		 6886 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6887 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6888 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6889 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6890 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6891 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6892
3e6e0aab
GT		 6893 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6894 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6895
6896 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6897 sregs->idt.limit = dt.size;
6898 sregs->idt.base = dt.address;
b6c7a5dc 6899 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6900 sregs->gdt.limit = dt.size;
6901 sregs->gdt.base = dt.address;
b6c7a5dc 6902
4d4ec087 6903 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6904 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6905 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6906 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6907 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6908 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6909 sregs->apic_base = kvm_get_apic_base(vcpu);
6910
923c61bb 6911 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6912
36752c9b 6913 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6914 set_bit(vcpu->arch.interrupt.nr,
6915 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6916
b6c7a5dc
HB		 6917 return 0;
6918}
6919
62d9f0db
MT		 6920int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6921 struct kvm_mp_state *mp_state)
6922{
66450a21 6923 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6924 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6925 vcpu->arch.pv.pv_unhalted)
6926 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6927 else
6928 mp_state->mp_state = vcpu->arch.mp_state;
6929
62d9f0db
MT		 6930 return 0;
6931}
6932
6933int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6934 struct kvm_mp_state *mp_state)
6935{
66450a21
JK		 6936 if (!kvm_vcpu_has_lapic(vcpu) &&
6937 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6938 return -EINVAL;
6939
6940 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6941 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6942 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6943 } else
6944 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6945 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6946 return 0;
6947}
6948
7f3d35fd
KW		 6949int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6950 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6951{
9d74191a 6952 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6953 int ret;
e01c2426 6954
8ec4722d 6955 init_emulate_ctxt(vcpu);
c697518a 6956
7f3d35fd 6957 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6958 has_error_code, error_code);
c697518a 6959
c697518a 6960 if (ret)
19d04437 6961 return EMULATE_FAIL;
37817f29 6962
9d74191a
TY		 6963 kvm_rip_write(vcpu, ctxt->eip);
6964 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6965 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6966 return EMULATE_DONE;
37817f29
IE		 6967}
6968EXPORT_SYMBOL_GPL(kvm_task_switch);
6969
b6c7a5dc
HB		 6970int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6971 struct kvm_sregs *sregs)
6972{
58cb628d 6973 struct msr_data apic_base_msr;
b6c7a5dc 6974 int mmu_reset_needed = 0;
63f42e02 6975 int pending_vec, max_bits, idx;
89a27f4d 6976 struct desc_ptr dt;
b6c7a5dc 6977
6d1068b3
PM		 6978 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6979 return -EINVAL;
6980
89a27f4d
GN		 6981 dt.size = sregs->idt.limit;
6982 dt.address = sregs->idt.base;
b6c7a5dc 6983 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6984 dt.size = sregs->gdt.limit;
6985 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6986 kvm_x86_ops->set_gdt(vcpu, &dt);
6987
ad312c7c 6988 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6989 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6990 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6991 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6992
2d3ad1f4 6993 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6994
f6801dff 6995 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6996 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6997 apic_base_msr.data = sregs->apic_base;
6998 apic_base_msr.host_initiated = true;
6999 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7000
4d4ec087 7001 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7002 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7003 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7004
fc78f519 7005 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7006 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7007 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7008 kvm_update_cpuid(vcpu);
63f42e02
XG		 7009
7010 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7011 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7012 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7013 mmu_reset_needed = 1;
7014 }
63f42e02 7015 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7016
7017 if (mmu_reset_needed)
7018 kvm_mmu_reset_context(vcpu);
7019
a50abc3b 7020 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7021 pending_vec = find_first_bit(
7022 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7023 if (pending_vec < max_bits) {
66fd3f7f 7024 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7025 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7026 }
7027
3e6e0aab
GT		 7028 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7029 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7030 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7031 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7032 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7033 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7034
3e6e0aab
GT		 7035 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7036 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7037
5f0269f5
ME		 7038 update_cr8_intercept(vcpu);
7039
9c3e4aab 7040 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7041 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7042 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7043 !is_protmode(vcpu))
9c3e4aab
MT		 7044 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7045
3842d135
AK		 7046 kvm_make_request(KVM_REQ_EVENT, vcpu);
7047
b6c7a5dc
HB		 7048 return 0;
7049}
7050
d0bfb940
JK		 7051int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7052 struct kvm_guest_debug *dbg)
b6c7a5dc 7053{
355be0b9 7054 unsigned long rflags;
ae675ef0 7055 int i, r;
b6c7a5dc 7056
4f926bf2
JK		 7057 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7058 r = -EBUSY;
7059 if (vcpu->arch.exception.pending)
2122ff5e 7060 goto out;
4f926bf2
JK		 7061 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7062 kvm_queue_exception(vcpu, DB_VECTOR);
7063 else
7064 kvm_queue_exception(vcpu, BP_VECTOR);
7065 }
7066
91586a3b
JK		 7067 /*
7068 * Read rflags as long as potentially injected trace flags are still
7069 * filtered out.
7070 */
7071 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7072
7073 vcpu->guest_debug = dbg->control;
7074 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7075 vcpu->guest_debug = 0;
7076
7077 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7078 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7079 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7080 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7081 } else {
7082 for (i = 0; i < KVM_NR_DB_REGS; i++)
7083 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7084 }
c8639010 7085 kvm_update_dr7(vcpu);
ae675ef0 7086
f92653ee
JK		 7087 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7088 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7089 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7090
91586a3b
JK		 7091 /*
7092 * Trigger an rflags update that will inject or remove the trace
7093 * flags.
7094 */
7095 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7096
c8639010 7097 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7098
4f926bf2 7099 r = 0;
d0bfb940 7100
2122ff5e 7101out:
b6c7a5dc
HB		 7102
7103 return r;
7104}
7105
8b006791
ZX		 7106/*
7107 * Translate a guest virtual address to a guest physical address.
7108 */
7109int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7110 struct kvm_translation *tr)
7111{
7112 unsigned long vaddr = tr->linear_address;
7113 gpa_t gpa;
f656ce01 7114 int idx;
8b006791 7115
f656ce01 7116 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7117 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7118 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7119 tr->physical_address = gpa;
7120 tr->valid = gpa != UNMAPPED_GVA;
7121 tr->writeable = 1;
7122 tr->usermode = 0;
8b006791
ZX		 7123
7124 return 0;
7125}
7126
d0752060
HB		 7127int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7128{
c47ada30 7129 struct fxregs_state *fxsave =
7366ed77 7130 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7131
d0752060
HB		 7132 memcpy(fpu->fpr, fxsave->st_space, 128);
7133 fpu->fcw = fxsave->cwd;
7134 fpu->fsw = fxsave->swd;
7135 fpu->ftwx = fxsave->twd;
7136 fpu->last_opcode = fxsave->fop;
7137 fpu->last_ip = fxsave->rip;
7138 fpu->last_dp = fxsave->rdp;
7139 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7140
d0752060
HB		 7141 return 0;
7142}
7143
7144int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7145{
c47ada30 7146 struct fxregs_state *fxsave =
7366ed77 7147 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7148
d0752060
HB		 7149 memcpy(fxsave->st_space, fpu->fpr, 128);
7150 fxsave->cwd = fpu->fcw;
7151 fxsave->swd = fpu->fsw;
7152 fxsave->twd = fpu->ftwx;
7153 fxsave->fop = fpu->last_opcode;
7154 fxsave->rip = fpu->last_ip;
7155 fxsave->rdp = fpu->last_dp;
7156 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7157
d0752060
HB		 7158 return 0;
7159}
7160
0ee6a517 7161static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7162{
bf935b0b 7163 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7164 if (cpu_has_xsaves)
7366ed77 7165 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7166 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7167
2acf923e
DC		 7168 /*
7169 * Ensure guest xcr0 is valid for loading
7170 */
7171 vcpu->arch.xcr0 = XSTATE_FP;
7172
ad312c7c 7173 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7174}
d0752060
HB		 7175
7176void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7177{
2608d7a1 7178 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7179 return;
7180
2acf923e
DC		 7181 /*
7182 * Restore all possible states in the guest,
7183 * and assume host would use all available bits.
7184 * Guest xcr0 would be loaded later.
7185 */
7186 kvm_put_guest_xcr0(vcpu);
d0752060 7187 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7188 __kernel_fpu_begin();
003e2e8b 7189 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7190 trace_kvm_fpu(1);
d0752060 7191}
d0752060
HB		 7192
7193void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7194{
2acf923e
DC		 7195 kvm_put_guest_xcr0(vcpu);
7196
653f52c3
RR		 7197 if (!vcpu->guest_fpu_loaded) {
7198 vcpu->fpu_counter = 0;
d0752060 7199 return;
653f52c3 7200 }
d0752060
HB		 7201
7202 vcpu->guest_fpu_loaded = 0;
4f836347 7203 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7204 __kernel_fpu_end();
f096ed85 7205 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7206 /*
7207 * If using eager FPU mode, or if the guest is a frequent user
7208 * of the FPU, just leave the FPU active for next time.
7209 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7210 * the FPU in bursts will revert to loading it on demand.
7211 */
a9b4fb7e 7212 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7213 if (++vcpu->fpu_counter < 5)
7214 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7215 }
0c04851c 7216 trace_kvm_fpu(0);
d0752060 7217}
e9b11c17
ZX		 7218
7219void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7220{
12f9a48f 7221 kvmclock_reset(vcpu);
7f1ea208 7222
f5f48ee1 7223 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7224 kvm_x86_ops->vcpu_free(vcpu);
7225}
7226
7227struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7228 unsigned int id)
7229{
c447e76b
LL		 7230 struct kvm_vcpu *vcpu;
7231
6755bae8
ZA		 7232 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7233 printk_once(KERN_WARNING
7234 "kvm: SMP vm created on host with unstable TSC; "
7235 "guest TSC will not be reliable\n");
c447e76b
LL		 7236
7237 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7238
c447e76b 7239 return vcpu;
26e5215f 7240}
e9b11c17 7241
26e5215f
AK		 7242int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7243{
7244 int r;
e9b11c17 7245
19efffa2 7246 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7247 r = vcpu_load(vcpu);
7248 if (r)
7249 return r;
d28bc9dd 7250 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7251 kvm_mmu_setup(vcpu);
e9b11c17 7252 vcpu_put(vcpu);
26e5215f 7253 return r;
e9b11c17
ZX		 7254}
7255
31928aa5 7256void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7257{
8fe8ab46 7258 struct msr_data msr;
332967a3 7259 struct kvm *kvm = vcpu->kvm;
42897d86 7260
31928aa5
DD		 7261 if (vcpu_load(vcpu))
7262 return;
8fe8ab46
WA		 7263 msr.data = 0x0;
7264 msr.index = MSR_IA32_TSC;
7265 msr.host_initiated = true;
7266 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7267 vcpu_put(vcpu);
7268
630994b3
MT		 7269 if (!kvmclock_periodic_sync)
7270 return;
7271
332967a3
AJ		 7272 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7273 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7274}
7275
d40ccc62 7276void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7277{
9fc77441 7278 int r;
344d9588
GN		 7279 vcpu->arch.apf.msr_val = 0;
7280
9fc77441
MT		 7281 r = vcpu_load(vcpu);
7282 BUG_ON(r);
e9b11c17
ZX		 7283 kvm_mmu_unload(vcpu);
7284 vcpu_put(vcpu);
7285
7286 kvm_x86_ops->vcpu_free(vcpu);
7287}
7288
d28bc9dd 7289void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7290{
e69fab5d
PB		 7291 vcpu->arch.hflags = 0;
7292
7460fb4a
AK		 7293 atomic_set(&vcpu->arch.nmi_queued, 0);
7294 vcpu->arch.nmi_pending = 0;
448fa4a9 7295 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7296 kvm_clear_interrupt_queue(vcpu);
7297 kvm_clear_exception_queue(vcpu);
448fa4a9 7298
42dbaa5a 7299 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7300 kvm_update_dr0123(vcpu);
6f43ed01 7301 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7302 kvm_update_dr6(vcpu);
42dbaa5a 7303 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7304 kvm_update_dr7(vcpu);
42dbaa5a 7305
1119022c
NA		 7306 vcpu->arch.cr2 = 0;
7307
3842d135 7308 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7309 vcpu->arch.apf.msr_val = 0;
c9aaa895 7310 vcpu->arch.st.msr_val = 0;
3842d135 7311
12f9a48f
GC		 7312 kvmclock_reset(vcpu);
7313
af585b92
GN		 7314 kvm_clear_async_pf_completion_queue(vcpu);
7315 kvm_async_pf_hash_reset(vcpu);
7316 vcpu->arch.apf.halted = false;
3842d135 7317
64d60670 7318 if (!init_event) {
d28bc9dd 7319 kvm_pmu_reset(vcpu);
64d60670
PB		 7320 vcpu->arch.smbase = 0x30000;
7321 }
f5132b01 7322
66f7b72e
JS		 7323 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7324 vcpu->arch.regs_avail = ~0;
7325 vcpu->arch.regs_dirty = ~0;
7326
d28bc9dd 7327 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7328}
7329
2b4a273b 7330void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7331{
7332 struct kvm_segment cs;
7333
7334 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7335 cs.selector = vector << 8;
7336 cs.base = vector << 12;
7337 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7338 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7339}
7340
13a34e06 7341int kvm_arch_hardware_enable(void)
e9b11c17 7342{
ca84d1a2
ZA		 7343 struct kvm *kvm;
7344 struct kvm_vcpu *vcpu;
7345 int i;
0dd6a6ed
ZA		 7346 int ret;
7347 u64 local_tsc;
7348 u64 max_tsc = 0;
7349 bool stable, backwards_tsc = false;
18863bdd
AK		 7350
7351 kvm_shared_msr_cpu_online();
13a34e06 7352 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7353 if (ret != 0)
7354 return ret;
7355
4ea1636b 7356 local_tsc = rdtsc();
0dd6a6ed
ZA		 7357 stable = !check_tsc_unstable();
7358 list_for_each_entry(kvm, &vm_list, vm_list) {
7359 kvm_for_each_vcpu(i, vcpu, kvm) {
7360 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7361 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7362 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7363 backwards_tsc = true;
7364 if (vcpu->arch.last_host_tsc > max_tsc)
7365 max_tsc = vcpu->arch.last_host_tsc;
7366 }
7367 }
7368 }
7369
7370 /*
7371 * Sometimes, even reliable TSCs go backwards. This happens on
7372 * platforms that reset TSC during suspend or hibernate actions, but
7373 * maintain synchronization. We must compensate. Fortunately, we can
7374 * detect that condition here, which happens early in CPU bringup,
7375 * before any KVM threads can be running. Unfortunately, we can't
7376 * bring the TSCs fully up to date with real time, as we aren't yet far
7377 * enough into CPU bringup that we know how much real time has actually
7378 * elapsed; our helper function, get_kernel_ns() will be using boot
7379 * variables that haven't been updated yet.
7380 *
7381 * So we simply find the maximum observed TSC above, then record the
7382 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7383 * the adjustment will be applied. Note that we accumulate
7384 * adjustments, in case multiple suspend cycles happen before some VCPU
7385 * gets a chance to run again. In the event that no KVM threads get a
7386 * chance to run, we will miss the entire elapsed period, as we'll have
7387 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7388 * loose cycle time. This isn't too big a deal, since the loss will be
7389 * uniform across all VCPUs (not to mention the scenario is extremely
7390 * unlikely). It is possible that a second hibernate recovery happens
7391 * much faster than a first, causing the observed TSC here to be
7392 * smaller; this would require additional padding adjustment, which is
7393 * why we set last_host_tsc to the local tsc observed here.
7394 *
7395 * N.B. - this code below runs only on platforms with reliable TSC,
7396 * as that is the only way backwards_tsc is set above. Also note
7397 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7398 * have the same delta_cyc adjustment applied if backwards_tsc
7399 * is detected. Note further, this adjustment is only done once,
7400 * as we reset last_host_tsc on all VCPUs to stop this from being
7401 * called multiple times (one for each physical CPU bringup).
7402 *
4a969980 7403 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7404 * will be compensated by the logic in vcpu_load, which sets the TSC to
7405 * catchup mode. This will catchup all VCPUs to real time, but cannot
7406 * guarantee that they stay in perfect synchronization.
7407 */
7408 if (backwards_tsc) {
7409 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7410 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7411 list_for_each_entry(kvm, &vm_list, vm_list) {
7412 kvm_for_each_vcpu(i, vcpu, kvm) {
7413 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7414 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7415 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7416 }
7417
7418 /*
7419 * We have to disable TSC offset matching.. if you were
7420 * booting a VM while issuing an S4 host suspend....
7421 * you may have some problem. Solving this issue is
7422 * left as an exercise to the reader.
7423 */
7424 kvm->arch.last_tsc_nsec = 0;
7425 kvm->arch.last_tsc_write = 0;
7426 }
7427
7428 }
7429 return 0;
e9b11c17
ZX		 7430}
7431
13a34e06 7432void kvm_arch_hardware_disable(void)
e9b11c17 7433{
13a34e06
RK		 7434 kvm_x86_ops->hardware_disable();
7435 drop_user_return_notifiers();
e9b11c17
ZX		 7436}
7437
7438int kvm_arch_hardware_setup(void)
7439{
9e9c3fe4
NA		 7440 int r;
7441
7442 r = kvm_x86_ops->hardware_setup();
7443 if (r != 0)
7444 return r;
7445
35181e86
HZ		 7446 if (kvm_has_tsc_control) {
7447 /*
7448 * Make sure the user can only configure tsc_khz values that
7449 * fit into a signed integer.
7450 * A min value is not calculated needed because it will always
7451 * be 1 on all machines.
7452 */
7453 u64 max = min(0x7fffffffULL,
7454 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7455 kvm_max_guest_tsc_khz = max;
7456
ad721883 7457 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7458 }
ad721883 7459
9e9c3fe4
NA		 7460 kvm_init_msr_list();
7461 return 0;
e9b11c17
ZX		 7462}
7463
7464void kvm_arch_hardware_unsetup(void)
7465{
7466 kvm_x86_ops->hardware_unsetup();
7467}
7468
7469void kvm_arch_check_processor_compat(void *rtn)
7470{
7471 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7472}
7473
7474bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7475{
7476 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7477}
7478EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7479
7480bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7481{
7482 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7483}
7484
3e515705
AK		 7485bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7486{
35754c98 7487 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7488}
7489
54e9818f
GN		 7490struct static_key kvm_no_apic_vcpu __read_mostly;
7491
e9b11c17
ZX		 7492int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7493{
7494 struct page *page;
7495 struct kvm *kvm;
7496 int r;
7497
7498 BUG_ON(vcpu->kvm == NULL);
7499 kvm = vcpu->kvm;
7500
6aef266c 7501 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7502 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7503 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7504 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7505 else
a4535290 7506 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7507
7508 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7509 if (!page) {
7510 r = -ENOMEM;
7511 goto fail;
7512 }
ad312c7c 7513 vcpu->arch.pio_data = page_address(page);
e9b11c17 7514
cc578287 7515 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7516
e9b11c17
ZX		 7517 r = kvm_mmu_create(vcpu);
7518 if (r < 0)
7519 goto fail_free_pio_data;
7520
7521 if (irqchip_in_kernel(kvm)) {
7522 r = kvm_create_lapic(vcpu);
7523 if (r < 0)
7524 goto fail_mmu_destroy;
54e9818f
GN		 7525 } else
7526 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7527
890ca9ae
HY		 7528 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7529 GFP_KERNEL);
7530 if (!vcpu->arch.mce_banks) {
7531 r = -ENOMEM;
443c39bc 7532 goto fail_free_lapic;
890ca9ae
HY		 7533 }
7534 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7535
f1797359
WY		 7536 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7537 r = -ENOMEM;
f5f48ee1 7538 goto fail_free_mce_banks;
f1797359 7539 }
f5f48ee1 7540
0ee6a517 7541 fx_init(vcpu);
66f7b72e 7542
ba904635 7543 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7544 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7545
7546 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7547 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7548
5a4f55cd
EK		 7549 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7550
74545705
RK		 7551 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7552
af585b92 7553 kvm_async_pf_hash_reset(vcpu);
f5132b01 7554 kvm_pmu_init(vcpu);
af585b92 7555
1c1a9ce9
SR		 7556 vcpu->arch.pending_external_vector = -1;
7557
e9b11c17 7558 return 0;
0ee6a517 7559
f5f48ee1
SY		 7560fail_free_mce_banks:
7561 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7562fail_free_lapic:
7563 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7564fail_mmu_destroy:
7565 kvm_mmu_destroy(vcpu);
7566fail_free_pio_data:
ad312c7c 7567 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7568fail:
7569 return r;
7570}
7571
7572void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7573{
f656ce01
MT		 7574 int idx;
7575
f5132b01 7576 kvm_pmu_destroy(vcpu);
36cb93fd 7577 kfree(vcpu->arch.mce_banks);
e9b11c17 7578 kvm_free_lapic(vcpu);
f656ce01 7579 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7580 kvm_mmu_destroy(vcpu);
f656ce01 7581 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7582 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7583 if (!lapic_in_kernel(vcpu))
54e9818f 7584 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7585}
d19a9cd2 7586
e790d9ef
RK		 7587void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7588{
ae97a3b8 7589 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7590}
7591
e08b9637 7592int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7593{
e08b9637
CO		 7594 if (type)
7595 return -EINVAL;
7596
6ef768fa 7597 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7598 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7599 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7600 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7601 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7602
5550af4d
SY		 7603 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7604 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7605 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7606 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7607 &kvm->arch.irq_sources_bitmap);
5550af4d 7608
038f8c11 7609 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7610 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7611 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7612
7613 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7614
7e44e449 7615 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7616 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7617
d89f5eff 7618 return 0;
d19a9cd2
ZX		 7619}
7620
7621static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7622{
9fc77441
MT		 7623 int r;
7624 r = vcpu_load(vcpu);
7625 BUG_ON(r);
d19a9cd2
ZX		 7626 kvm_mmu_unload(vcpu);
7627 vcpu_put(vcpu);
7628}
7629
7630static void kvm_free_vcpus(struct kvm *kvm)
7631{
7632 unsigned int i;
988a2cae 7633 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7634
7635 /*
7636 * Unpin any mmu pages first.
7637 */
af585b92
GN		 7638 kvm_for_each_vcpu(i, vcpu, kvm) {
7639 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7640 kvm_unload_vcpu_mmu(vcpu);
af585b92 7641 }
988a2cae
GN		 7642 kvm_for_each_vcpu(i, vcpu, kvm)
7643 kvm_arch_vcpu_free(vcpu);
7644
7645 mutex_lock(&kvm->lock);
7646 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7647 kvm->vcpus[i] = NULL;
d19a9cd2 7648
988a2cae
GN		 7649 atomic_set(&kvm->online_vcpus, 0);
7650 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7651}
7652
ad8ba2cd
SY		 7653void kvm_arch_sync_events(struct kvm *kvm)
7654{
332967a3 7655 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7656 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7657 kvm_free_all_assigned_devices(kvm);
aea924f6 7658 kvm_free_pit(kvm);
ad8ba2cd
SY		 7659}
7660
1d8007bd 7661int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7662{
7663 int i, r;
25188b99 7664 unsigned long hva;
f0d648bd
PB		 7665 struct kvm_memslots *slots = kvm_memslots(kvm);
7666 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7667
7668 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7669 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7670 return -EINVAL;
9da0e4d5 7671
f0d648bd
PB		 7672 slot = id_to_memslot(slots, id);
7673 if (size) {
7674 if (WARN_ON(slot->npages))
7675 return -EEXIST;
7676
7677 /*
7678 * MAP_SHARED to prevent internal slot pages from being moved
7679 * by fork()/COW.
7680 */
7681 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7682 MAP_SHARED | MAP_ANONYMOUS, 0);
7683 if (IS_ERR((void *)hva))
7684 return PTR_ERR((void *)hva);
7685 } else {
7686 if (!slot->npages)
7687 return 0;
9da0e4d5 7688
f0d648bd
PB		 7689 hva = 0;
7690 }
7691
7692 old = *slot;
9da0e4d5 7693 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7694 struct kvm_userspace_memory_region m;
9da0e4d5 7695
1d8007bd
PB		 7696 m.slot = id | (i << 16);
7697 m.flags = 0;
7698 m.guest_phys_addr = gpa;
f0d648bd 7699 m.userspace_addr = hva;
1d8007bd 7700 m.memory_size = size;
9da0e4d5
PB		 7701 r = __kvm_set_memory_region(kvm, &m);
7702 if (r < 0)
7703 return r;
7704 }
7705
f0d648bd
PB		 7706 if (!size) {
7707 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7708 WARN_ON(r < 0);
7709 }
7710
9da0e4d5
PB		 7711 return 0;
7712}
7713EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7714
1d8007bd 7715int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7716{
7717 int r;
7718
7719 mutex_lock(&kvm->slots_lock);
1d8007bd 7720 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7721 mutex_unlock(&kvm->slots_lock);
7722
7723 return r;
7724}
7725EXPORT_SYMBOL_GPL(x86_set_memory_region);
7726
d19a9cd2
ZX		 7727void kvm_arch_destroy_vm(struct kvm *kvm)
7728{
27469d29
AH		 7729 if (current->mm == kvm->mm) {
7730 /*
7731 * Free memory regions allocated on behalf of userspace,
7732 * unless the the memory map has changed due to process exit
7733 * or fd copying.
7734 */
1d8007bd
PB		 7735 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7736 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7737 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7738 }
6eb55818 7739 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7740 kfree(kvm->arch.vpic);
7741 kfree(kvm->arch.vioapic);
d19a9cd2 7742 kvm_free_vcpus(kvm);
1e08ec4a 7743 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7744}
0de10343 7745
5587027c 7746void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7747 struct kvm_memory_slot *dont)
7748{
7749 int i;
7750
d89cc617
TY		 7751 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7752 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7753 kvfree(free->arch.rmap[i]);
d89cc617 7754 free->arch.rmap[i] = NULL;
77d11309 7755 }
d89cc617
TY		 7756 if (i == 0)
7757 continue;
7758
7759 if (!dont || free->arch.lpage_info[i - 1] !=
7760 dont->arch.lpage_info[i - 1]) {
548ef284 7761 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7762 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7763 }
7764 }
7765}
7766
5587027c
AK		 7767int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7768 unsigned long npages)
db3fe4eb
TY		 7769{
7770 int i;
7771
d89cc617 7772 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7773 unsigned long ugfn;
7774 int lpages;
d89cc617 7775 int level = i + 1;
db3fe4eb
TY		 7776
7777 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7778 slot->base_gfn, level) + 1;
7779
d89cc617
TY		 7780 slot->arch.rmap[i] =
7781 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7782 if (!slot->arch.rmap[i])
77d11309 7783 goto out_free;
d89cc617
TY		 7784 if (i == 0)
7785 continue;
77d11309 7786
d89cc617
TY		 7787 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7788 sizeof(*slot->arch.lpage_info[i - 1]));
7789 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7790 goto out_free;
7791
7792 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7793 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7794 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7795 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7796 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7797 /*
7798 * If the gfn and userspace address are not aligned wrt each
7799 * other, or if explicitly asked to, disable large page
7800 * support for this slot
7801 */
7802 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7803 !kvm_largepages_enabled()) {
7804 unsigned long j;
7805
7806 for (j = 0; j < lpages; ++j)
d89cc617 7807 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7808 }
7809 }
7810
7811 return 0;
7812
7813out_free:
d89cc617 7814 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7815 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7816 slot->arch.rmap[i] = NULL;
7817 if (i == 0)
7818 continue;
7819
548ef284 7820 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7821 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7822 }
7823 return -ENOMEM;
7824}
7825
15f46015 7826void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7827{
e6dff7d1
TY		 7828 /*
7829 * memslots->generation has been incremented.
7830 * mmio generation may have reached its maximum value.
7831 */
54bf36aa 7832 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7833}
7834
f7784b8e
MT		 7835int kvm_arch_prepare_memory_region(struct kvm *kvm,
7836 struct kvm_memory_slot *memslot,
09170a49 7837 const struct kvm_userspace_memory_region *mem,
7b6195a9 7838 enum kvm_mr_change change)
0de10343 7839{
f7784b8e
MT		 7840 return 0;
7841}
7842
88178fd4
KH		 7843static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7844 struct kvm_memory_slot *new)
7845{
7846 /* Still write protect RO slot */
7847 if (new->flags & KVM_MEM_READONLY) {
7848 kvm_mmu_slot_remove_write_access(kvm, new);
7849 return;
7850 }
7851
7852 /*
7853 * Call kvm_x86_ops dirty logging hooks when they are valid.
7854 *
7855 * kvm_x86_ops->slot_disable_log_dirty is called when:
7856 *
7857 * - KVM_MR_CREATE with dirty logging is disabled
7858 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7859 *
7860 * The reason is, in case of PML, we need to set D-bit for any slots
7861 * with dirty logging disabled in order to eliminate unnecessary GPA
7862 * logging in PML buffer (and potential PML buffer full VMEXT). This
7863 * guarantees leaving PML enabled during guest's lifetime won't have
7864 * any additonal overhead from PML when guest is running with dirty
7865 * logging disabled for memory slots.
7866 *
7867 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7868 * to dirty logging mode.
7869 *
7870 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7871 *
7872 * In case of write protect:
7873 *
7874 * Write protect all pages for dirty logging.
7875 *
7876 * All the sptes including the large sptes which point to this
7877 * slot are set to readonly. We can not create any new large
7878 * spte on this slot until the end of the logging.
7879 *
7880 * See the comments in fast_page_fault().
7881 */
7882 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7883 if (kvm_x86_ops->slot_enable_log_dirty)
7884 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7885 else
7886 kvm_mmu_slot_remove_write_access(kvm, new);
7887 } else {
7888 if (kvm_x86_ops->slot_disable_log_dirty)
7889 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7890 }
7891}
7892
f7784b8e 7893void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7894 const struct kvm_userspace_memory_region *mem,
8482644a 7895 const struct kvm_memory_slot *old,
f36f3f28 7896 const struct kvm_memory_slot *new,
8482644a 7897 enum kvm_mr_change change)
f7784b8e 7898{
8482644a 7899 int nr_mmu_pages = 0;
f7784b8e 7900
48c0e4e9
XG		 7901 if (!kvm->arch.n_requested_mmu_pages)
7902 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7903
48c0e4e9 7904 if (nr_mmu_pages)
0de10343 7905 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7906
3ea3b7fa
WL		 7907 /*
7908 * Dirty logging tracks sptes in 4k granularity, meaning that large
7909 * sptes have to be split. If live migration is successful, the guest
7910 * in the source machine will be destroyed and large sptes will be
7911 * created in the destination. However, if the guest continues to run
7912 * in the source machine (for example if live migration fails), small
7913 * sptes will remain around and cause bad performance.
7914 *
7915 * Scan sptes if dirty logging has been stopped, dropping those
7916 * which can be collapsed into a single large-page spte. Later
7917 * page faults will create the large-page sptes.
7918 */
7919 if ((change != KVM_MR_DELETE) &&
7920 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7921 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7922 kvm_mmu_zap_collapsible_sptes(kvm, new);
7923
c972f3b1 7924 /*
88178fd4 7925 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7926 *
88178fd4
KH		 7927 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7928 * been zapped so no dirty logging staff is needed for old slot. For
7929 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7930 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7931 *
7932 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7933 */
88178fd4 7934 if (change != KVM_MR_DELETE)
f36f3f28 7935 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7936}
1d737c8a 7937
2df72e9b 7938void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7939{
6ca18b69 7940 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7941}
7942
2df72e9b
MT		 7943void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7944 struct kvm_memory_slot *slot)
7945{
6ca18b69 7946 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7947}
7948
5d9bc648
PB		 7949static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
7950{
7951 if (!list_empty_careful(&vcpu->async_pf.done))
7952 return true;
7953
7954 if (kvm_apic_has_events(vcpu))
7955 return true;
7956
7957 if (vcpu->arch.pv.pv_unhalted)
7958 return true;
7959
7960 if (atomic_read(&vcpu->arch.nmi_queued))
7961 return true;
7962
73917739
PB		 7963 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
7964 return true;
7965
5d9bc648
PB		 7966 if (kvm_arch_interrupt_allowed(vcpu) &&
7967 kvm_cpu_has_interrupt(vcpu))
7968 return true;
7969
7970 return false;
7971}
7972
1d737c8a
ZX		 7973int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7974{
b6b8a145
JK		 7975 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7976 kvm_x86_ops->check_nested_events(vcpu, false);
7977
5d9bc648 7978 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 7979}
5736199a 7980
b6d33834 7981int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7982{
b6d33834 7983 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7984}
78646121
GN		 7985
7986int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7987{
7988 return kvm_x86_ops->interrupt_allowed(vcpu);
7989}
229456fc 7990
82b32774 7991unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7992{
82b32774
NA		 7993 if (is_64_bit_mode(vcpu))
7994 return kvm_rip_read(vcpu);
7995 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7996 kvm_rip_read(vcpu));
7997}
7998EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7999
82b32774
NA		 8000bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8001{
8002 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8003}
8004EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8005
94fe45da
JK		 8006unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8007{
8008 unsigned long rflags;
8009
8010 rflags = kvm_x86_ops->get_rflags(vcpu);
8011 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8012 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8013 return rflags;
8014}
8015EXPORT_SYMBOL_GPL(kvm_get_rflags);
8016
6addfc42 8017static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8018{
8019 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8020 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8021 rflags |= X86_EFLAGS_TF;
94fe45da 8022 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8023}
8024
8025void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8026{
8027 __kvm_set_rflags(vcpu, rflags);
3842d135 8028 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8029}
8030EXPORT_SYMBOL_GPL(kvm_set_rflags);
8031
56028d08
GN		 8032void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8033{
8034 int r;
8035
fb67e14f 8036 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8037 work->wakeup_all)
56028d08
GN		 8038 return;
8039
8040 r = kvm_mmu_reload(vcpu);
8041 if (unlikely(r))
8042 return;
8043
fb67e14f
XG		 8044 if (!vcpu->arch.mmu.direct_map &&
8045 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8046 return;
8047
56028d08
GN		 8048 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8049}
8050
af585b92
GN		 8051static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8052{
8053 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8054}
8055
8056static inline u32 kvm_async_pf_next_probe(u32 key)
8057{
8058 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8059}
8060
8061static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8062{
8063 u32 key = kvm_async_pf_hash_fn(gfn);
8064
8065 while (vcpu->arch.apf.gfns[key] != ~0)
8066 key = kvm_async_pf_next_probe(key);
8067
8068 vcpu->arch.apf.gfns[key] = gfn;
8069}
8070
8071static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8072{
8073 int i;
8074 u32 key = kvm_async_pf_hash_fn(gfn);
8075
8076 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8077 (vcpu->arch.apf.gfns[key] != gfn &&
8078 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8079 key = kvm_async_pf_next_probe(key);
8080
8081 return key;
8082}
8083
8084bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8085{
8086 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8087}
8088
8089static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8090{
8091 u32 i, j, k;
8092
8093 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8094 while (true) {
8095 vcpu->arch.apf.gfns[i] = ~0;
8096 do {
8097 j = kvm_async_pf_next_probe(j);
8098 if (vcpu->arch.apf.gfns[j] == ~0)
8099 return;
8100 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8101 /*
8102 * k lies cyclically in ]i,j]
8103 * | i.k.j |
8104 * |....j i.k.| or |.k..j i...|
8105 */
8106 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8107 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8108 i = j;
8109 }
8110}
8111
7c90705b
GN		 8112static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8113{
8114
8115 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8116 sizeof(val));
8117}
8118
af585b92
GN		 8119void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8120 struct kvm_async_pf *work)
8121{
6389ee94
AK		 8122 struct x86_exception fault;
8123
7c90705b 8124 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8125 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8126
8127 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8128 (vcpu->arch.apf.send_user_only &&
8129 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8130 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8131 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8132 fault.vector = PF_VECTOR;
8133 fault.error_code_valid = true;
8134 fault.error_code = 0;
8135 fault.nested_page_fault = false;
8136 fault.address = work->arch.token;
8137 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8138 }
af585b92
GN		 8139}
8140
8141void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8142 struct kvm_async_pf *work)
8143{
6389ee94
AK		 8144 struct x86_exception fault;
8145
7c90705b 8146 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8147 if (work->wakeup_all)
7c90705b
GN		 8148 work->arch.token = ~0; /* broadcast wakeup */
8149 else
8150 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8151
8152 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8153 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8154 fault.vector = PF_VECTOR;
8155 fault.error_code_valid = true;
8156 fault.error_code = 0;
8157 fault.nested_page_fault = false;
8158 fault.address = work->arch.token;
8159 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8160 }
e6d53e3b 8161 vcpu->arch.apf.halted = false;
a4fa1635 8162 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8163}
8164
8165bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8166{
8167 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8168 return true;
8169 else
8170 return !kvm_event_needs_reinjection(vcpu) &&
8171 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8172}
8173
5544eb9b
PB		 8174void kvm_arch_start_assignment(struct kvm *kvm)
8175{
8176 atomic_inc(&kvm->arch.assigned_device_count);
8177}
8178EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8179
8180void kvm_arch_end_assignment(struct kvm *kvm)
8181{
8182 atomic_dec(&kvm->arch.assigned_device_count);
8183}
8184EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8185
8186bool kvm_arch_has_assigned_device(struct kvm *kvm)
8187{
8188 return atomic_read(&kvm->arch.assigned_device_count);
8189}
8190EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8191
e0f0bbc5
AW		 8192void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8193{
8194 atomic_inc(&kvm->arch.noncoherent_dma_count);
8195}
8196EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8197
8198void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8199{
8200 atomic_dec(&kvm->arch.noncoherent_dma_count);
8201}
8202EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8203
8204bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8205{
8206 return atomic_read(&kvm->arch.noncoherent_dma_count);
8207}
8208EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8209
87276880
FW		 8210int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8211 struct irq_bypass_producer *prod)
8212{
8213 struct kvm_kernel_irqfd *irqfd =
8214 container_of(cons, struct kvm_kernel_irqfd, consumer);
8215
8216 if (kvm_x86_ops->update_pi_irte) {
8217 irqfd->producer = prod;
8218 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8219 prod->irq, irqfd->gsi, 1);
8220 }
8221
8222 return -EINVAL;
8223}
8224
8225void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8226 struct irq_bypass_producer *prod)
8227{
8228 int ret;
8229 struct kvm_kernel_irqfd *irqfd =
8230 container_of(cons, struct kvm_kernel_irqfd, consumer);
8231
8232 if (!kvm_x86_ops->update_pi_irte) {
8233 WARN_ON(irqfd->producer != NULL);
8234 return;
8235 }
8236
8237 WARN_ON(irqfd->producer != prod);
8238 irqfd->producer = NULL;
8239
8240 /*
8241 * When producer of consumer is unregistered, we change back to
8242 * remapped mode, so we can re-use the current implementation
8243 * when the irq is masked/disabed or the consumer side (KVM
8244 * int this case doesn't want to receive the interrupts.
8245 */
8246 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8247 if (ret)
8248 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8249 " fails: %d\n", irqfd->consumer.token, ret);
8250}
8251
8252int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8253 uint32_t guest_irq, bool set)
8254{
8255 if (!kvm_x86_ops->update_pi_irte)
8256 return -EINVAL;
8257
8258 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8259}
8260
229456fc 8261EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8262EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8263EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8264EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8265EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8266EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8267EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8268EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8269EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8270EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8271EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8272EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8273EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8274EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8275EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8276EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8277EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
Linux 6.x block layer and io_uring tree(s)