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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
bf8c55d8 72#include <asm/intel_pt.h>
043405e1 73
d1898b73
DH		 74#define CREATE_TRACE_POINTS
75#include "trace.h"
76
313a3dc7 77#define MAX_IO_MSRS 256
890ca9ae 78#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 79u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 81
0f65dd70
AK		 82#define emul_to_vcpu(ctxt) \
83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
84
50a37eb4
JR		 85/* EFER defaults:
86 * - enable syscall per default because its emulated by KVM
87 * - enable LME and LMA per default on 64 bit KVM
88 */
89#ifdef CONFIG_X86_64
1260edbe
LJ		 90static
91u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 92#else
1260edbe 93static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 94#endif
313a3dc7 95
ba1389b7
AK		 96#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
97#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 98
c519265f
RK		 99#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
100 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 101
cb142eb7 102static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 103static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 104static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 105static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 106static void store_regs(struct kvm_vcpu *vcpu);
107static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 108
893590c7 109struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 110EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 111
893590c7 112static bool __read_mostly ignore_msrs = 0;
476bc001 113module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 114
fab0aa3b
EM		 115static bool __read_mostly report_ignored_msrs = true;
116module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117
4c27625b 118unsigned int min_timer_period_us = 200;
9ed96e87
MT		 119module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120
630994b3
MT		 121static bool __read_mostly kvmclock_periodic_sync = true;
122module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123
893590c7 124bool __read_mostly kvm_has_tsc_control;
92a1f12d 125EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 126u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 127EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 128u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
129EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
130u64 __read_mostly kvm_max_tsc_scaling_ratio;
131EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 132u64 __read_mostly kvm_default_tsc_scaling_ratio;
133EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 134
cc578287 135/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 136static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 137module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
138
d0659d94 139/* lapic timer advance (tscdeadline mode only) in nanoseconds */
3b8a5df6 140unsigned int __read_mostly lapic_timer_advance_ns = 1000;
d0659d94 141module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 142EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 143
52004014
FW		 144static bool __read_mostly vector_hashing = true;
145module_param(vector_hashing, bool, S_IRUGO);
146
c4ae60e4
LA		 147bool __read_mostly enable_vmware_backdoor = false;
148module_param(enable_vmware_backdoor, bool, S_IRUGO);
149EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
150
6c86eedc
WL		 151static bool __read_mostly force_emulation_prefix = false;
152module_param(force_emulation_prefix, bool, S_IRUGO);
153
18863bdd
AK		 154#define KVM_NR_SHARED_MSRS 16
155
156struct kvm_shared_msrs_global {
157 int nr;
2bf78fa7 158 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 159};
160
161struct kvm_shared_msrs {
162 struct user_return_notifier urn;
163 bool registered;
2bf78fa7
SY		 164 struct kvm_shared_msr_values {
165 u64 host;
166 u64 curr;
167 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 168};
169
170static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 171static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 172
417bc304 173struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 174 { "pf_fixed", VCPU_STAT(pf_fixed) },
175 { "pf_guest", VCPU_STAT(pf_guest) },
176 { "tlb_flush", VCPU_STAT(tlb_flush) },
177 { "invlpg", VCPU_STAT(invlpg) },
178 { "exits", VCPU_STAT(exits) },
179 { "io_exits", VCPU_STAT(io_exits) },
180 { "mmio_exits", VCPU_STAT(mmio_exits) },
181 { "signal_exits", VCPU_STAT(signal_exits) },
182 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 183 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 184 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 185 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 186 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 187 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 188 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 189 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 190 { "request_irq", VCPU_STAT(request_irq_exits) },
191 { "irq_exits", VCPU_STAT(irq_exits) },
192 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 193 { "fpu_reload", VCPU_STAT(fpu_reload) },
194 { "insn_emulation", VCPU_STAT(insn_emulation) },
195 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 196 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 197 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 198 { "req_event", VCPU_STAT(req_event) },
c595ceee 199 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 200 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
201 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
202 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
203 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
204 { "mmu_flooded", VM_STAT(mmu_flooded) },
205 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 206 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 207 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 208 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 209 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 210 { "max_mmu_page_hash_collisions",
211 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 212 { NULL }
213};
214
2acf923e
DC		 215u64 __read_mostly host_xcr0;
216
b666a4b6
MO		 217struct kmem_cache *x86_fpu_cache;
218EXPORT_SYMBOL_GPL(x86_fpu_cache);
219
b6785def 220static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 221
af585b92
GN		 222static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
223{
224 int i;
225 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
226 vcpu->arch.apf.gfns[i] = ~0;
227}
228
18863bdd
AK		 229static void kvm_on_user_return(struct user_return_notifier *urn)
230{
231 unsigned slot;
18863bdd
AK		 232 struct kvm_shared_msrs *locals
233 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 234 struct kvm_shared_msr_values *values;
1650b4eb
IA		 235 unsigned long flags;
236
237 /*
238 * Disabling irqs at this point since the following code could be
239 * interrupted and executed through kvm_arch_hardware_disable()
240 */
241 local_irq_save(flags);
242 if (locals->registered) {
243 locals->registered = false;
244 user_return_notifier_unregister(urn);
245 }
246 local_irq_restore(flags);
18863bdd 247 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 248 values = &locals->values[slot];
249 if (values->host != values->curr) {
250 wrmsrl(shared_msrs_global.msrs[slot], values->host);
251 values->curr = values->host;
18863bdd
AK		 252 }
253 }
18863bdd
AK		 254}
255
2bf78fa7 256static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 257{
18863bdd 258 u64 value;
013f6a5d
MT		 259 unsigned int cpu = smp_processor_id();
260 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 261
2bf78fa7
SY		 262 /* only read, and nobody should modify it at this time,
263 * so don't need lock */
264 if (slot >= shared_msrs_global.nr) {
265 printk(KERN_ERR "kvm: invalid MSR slot!");
266 return;
267 }
268 rdmsrl_safe(msr, &value);
269 smsr->values[slot].host = value;
270 smsr->values[slot].curr = value;
271}
272
273void kvm_define_shared_msr(unsigned slot, u32 msr)
274{
0123be42 275 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 276 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 277 if (slot >= shared_msrs_global.nr)
278 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 279}
280EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
281
282static void kvm_shared_msr_cpu_online(void)
283{
284 unsigned i;
18863bdd
AK		 285
286 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 287 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 288}
289
8b3c3104 290int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 291{
013f6a5d
MT		 292 unsigned int cpu = smp_processor_id();
293 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 294 int err;
18863bdd 295
2bf78fa7 296 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 297 return 0;
2bf78fa7 298 smsr->values[slot].curr = value;
8b3c3104
AH		 299 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
300 if (err)
301 return 1;
302
18863bdd
AK		 303 if (!smsr->registered) {
304 smsr->urn.on_user_return = kvm_on_user_return;
305 user_return_notifier_register(&smsr->urn);
306 smsr->registered = true;
307 }
8b3c3104 308 return 0;
18863bdd
AK		 309}
310EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
311
13a34e06 312static void drop_user_return_notifiers(void)
3548bab5 313{
013f6a5d
MT		 314 unsigned int cpu = smp_processor_id();
315 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 316
317 if (smsr->registered)
318 kvm_on_user_return(&smsr->urn);
319}
320
6866b83e
CO		 321u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
322{
8a5a87d9 323 return vcpu->arch.apic_base;
6866b83e
CO		 324}
325EXPORT_SYMBOL_GPL(kvm_get_apic_base);
326
58871649
JM		 327enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
328{
329 return kvm_apic_mode(kvm_get_apic_base(vcpu));
330}
331EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
332
58cb628d
JK		 333int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
334{
58871649
JM		 335 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
336 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 337 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
338 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 339
58871649 340 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 341 return 1;
58871649
JM		 342 if (!msr_info->host_initiated) {
343 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
344 return 1;
345 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
346 return 1;
347 }
58cb628d
JK		 348
349 kvm_lapic_set_base(vcpu, msr_info->data);
350 return 0;
6866b83e
CO		 351}
352EXPORT_SYMBOL_GPL(kvm_set_apic_base);
353
2605fc21 354asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 355{
356 /* Fault while not rebooting. We want the trace. */
357 BUG();
358}
359EXPORT_SYMBOL_GPL(kvm_spurious_fault);
360
3fd28fce
ED		 361#define EXCPT_BENIGN 0
362#define EXCPT_CONTRIBUTORY 1
363#define EXCPT_PF 2
364
365static int exception_class(int vector)
366{
367 switch (vector) {
368 case PF_VECTOR:
369 return EXCPT_PF;
370 case DE_VECTOR:
371 case TS_VECTOR:
372 case NP_VECTOR:
373 case SS_VECTOR:
374 case GP_VECTOR:
375 return EXCPT_CONTRIBUTORY;
376 default:
377 break;
378 }
379 return EXCPT_BENIGN;
380}
381
d6e8c854
NA		 382#define EXCPT_FAULT 0
383#define EXCPT_TRAP 1
384#define EXCPT_ABORT 2
385#define EXCPT_INTERRUPT 3
386
387static int exception_type(int vector)
388{
389 unsigned int mask;
390
391 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
392 return EXCPT_INTERRUPT;
393
394 mask = 1 << vector;
395
396 /* #DB is trap, as instruction watchpoints are handled elsewhere */
397 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
398 return EXCPT_TRAP;
399
400 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
401 return EXCPT_ABORT;
402
403 /* Reserved exceptions will result in fault */
404 return EXCPT_FAULT;
405}
406
da998b46
JM		 407void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
408{
409 unsigned nr = vcpu->arch.exception.nr;
410 bool has_payload = vcpu->arch.exception.has_payload;
411 unsigned long payload = vcpu->arch.exception.payload;
412
413 if (!has_payload)
414 return;
415
416 switch (nr) {
f10c729f
JM		 417 case DB_VECTOR:
418 /*
419 * "Certain debug exceptions may clear bit 0-3. The
420 * remaining contents of the DR6 register are never
421 * cleared by the processor".
422 */
423 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
424 /*
425 * DR6.RTM is set by all #DB exceptions that don't clear it.
426 */
427 vcpu->arch.dr6 |= DR6_RTM;
428 vcpu->arch.dr6 |= payload;
429 /*
430 * Bit 16 should be set in the payload whenever the #DB
431 * exception should clear DR6.RTM. This makes the payload
432 * compatible with the pending debug exceptions under VMX.
433 * Though not currently documented in the SDM, this also
434 * makes the payload compatible with the exit qualification
435 * for #DB exceptions under VMX.
436 */
437 vcpu->arch.dr6 ^= payload & DR6_RTM;
438 break;
da998b46
JM		 439 case PF_VECTOR:
440 vcpu->arch.cr2 = payload;
441 break;
442 }
443
444 vcpu->arch.exception.has_payload = false;
445 vcpu->arch.exception.payload = 0;
446}
447EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
448
3fd28fce 449static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 450 unsigned nr, bool has_error, u32 error_code,
91e86d22 451 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 452{
453 u32 prev_nr;
454 int class1, class2;
455
3842d135
AK		 456 kvm_make_request(KVM_REQ_EVENT, vcpu);
457
664f8e26 458 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 459 queue:
3ffb2468
NA		 460 if (has_error && !is_protmode(vcpu))
461 has_error = false;
664f8e26
WL		 462 if (reinject) {
463 /*
464 * On vmentry, vcpu->arch.exception.pending is only
465 * true if an event injection was blocked by
466 * nested_run_pending. In that case, however,
467 * vcpu_enter_guest requests an immediate exit,
468 * and the guest shouldn't proceed far enough to
469 * need reinjection.
470 */
471 WARN_ON_ONCE(vcpu->arch.exception.pending);
472 vcpu->arch.exception.injected = true;
91e86d22
JM		 473 if (WARN_ON_ONCE(has_payload)) {
474 /*
475 * A reinjected event has already
476 * delivered its payload.
477 */
478 has_payload = false;
479 payload = 0;
480 }
664f8e26
WL		 481 } else {
482 vcpu->arch.exception.pending = true;
483 vcpu->arch.exception.injected = false;
484 }
3fd28fce
ED		 485 vcpu->arch.exception.has_error_code = has_error;
486 vcpu->arch.exception.nr = nr;
487 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 488 vcpu->arch.exception.has_payload = has_payload;
489 vcpu->arch.exception.payload = payload;
da998b46
JM		 490 /*
491 * In guest mode, payload delivery should be deferred,
492 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 493 * CR2 is modified (or intercept #DB before DR6 is
494 * modified under nVMX). However, for ABI
495 * compatibility with KVM_GET_VCPU_EVENTS and
496 * KVM_SET_VCPU_EVENTS, we can't delay payload
497 * delivery unless userspace has enabled this
498 * functionality via the per-VM capability,
499 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 500 */
501 if (!vcpu->kvm->arch.exception_payload_enabled ||
502 !is_guest_mode(vcpu))
503 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 504 return;
505 }
506
507 /* to check exception */
508 prev_nr = vcpu->arch.exception.nr;
509 if (prev_nr == DF_VECTOR) {
510 /* triple fault -> shutdown */
a8eeb04a 511 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 512 return;
513 }
514 class1 = exception_class(prev_nr);
515 class2 = exception_class(nr);
516 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
517 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 518 /*
519 * Generate double fault per SDM Table 5-5. Set
520 * exception.pending = true so that the double fault
521 * can trigger a nested vmexit.
522 */
3fd28fce 523 vcpu->arch.exception.pending = true;
664f8e26 524 vcpu->arch.exception.injected = false;
3fd28fce
ED		 525 vcpu->arch.exception.has_error_code = true;
526 vcpu->arch.exception.nr = DF_VECTOR;
527 vcpu->arch.exception.error_code = 0;
c851436a
JM		 528 vcpu->arch.exception.has_payload = false;
529 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 530 } else
531 /* replace previous exception with a new one in a hope
532 that instruction re-execution will regenerate lost
533 exception */
534 goto queue;
535}
536
298101da
AK		 537void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
538{
91e86d22 539 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 540}
541EXPORT_SYMBOL_GPL(kvm_queue_exception);
542
ce7ddec4
JR		 543void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544{
91e86d22 545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 546}
547EXPORT_SYMBOL_GPL(kvm_requeue_exception);
548
f10c729f
JM		 549static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
550 unsigned long payload)
551{
552 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
553}
554
da998b46
JM		 555static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
556 u32 error_code, unsigned long payload)
557{
558 kvm_multiple_exception(vcpu, nr, true, error_code,
559 true, payload, false);
560}
561
6affcbed 562int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 563{
db8fcefa
AP		 564 if (err)
565 kvm_inject_gp(vcpu, 0);
566 else
6affcbed
KH		 567 return kvm_skip_emulated_instruction(vcpu);
568
569 return 1;
db8fcefa
AP		 570}
571EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 572
6389ee94 573void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 574{
575 ++vcpu->stat.pf_guest;
adfe20fb
WL		 576 vcpu->arch.exception.nested_apf =
577 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 578 if (vcpu->arch.exception.nested_apf) {
adfe20fb 579 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 580 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
581 } else {
582 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
583 fault->address);
584 }
c3c91fee 585}
27d6c865 586EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 587
ef54bcfe 588static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 589{
6389ee94
AK		 590 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
591 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 592 else
44dd3ffa 593 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 594
595 return fault->nested_page_fault;
d4f8cf66
JR		 596}
597
3419ffc8
SY		 598void kvm_inject_nmi(struct kvm_vcpu *vcpu)
599{
7460fb4a
AK		 600 atomic_inc(&vcpu->arch.nmi_queued);
601 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 602}
603EXPORT_SYMBOL_GPL(kvm_inject_nmi);
604
298101da
AK		 605void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
606{
91e86d22 607 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 608}
609EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
610
ce7ddec4
JR		 611void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612{
91e86d22 613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 614}
615EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
616
0a79b009
AK		 617/*
618 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
619 * a #GP and return false.
620 */
621bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 622{
0a79b009
AK		 623 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
624 return true;
625 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
626 return false;
298101da 627}
0a79b009 628EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 629
16f8a6f9
NA		 630bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
631{
632 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
633 return true;
634
635 kvm_queue_exception(vcpu, UD_VECTOR);
636 return false;
637}
638EXPORT_SYMBOL_GPL(kvm_require_dr);
639
ec92fe44
JR		 640/*
641 * This function will be used to read from the physical memory of the currently
54bf36aa 642 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 643 * can read from guest physical or from the guest's guest physical memory.
644 */
645int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
646 gfn_t ngfn, void *data, int offset, int len,
647 u32 access)
648{
54987b7a 649 struct x86_exception exception;
ec92fe44
JR		 650 gfn_t real_gfn;
651 gpa_t ngpa;
652
653 ngpa = gfn_to_gpa(ngfn);
54987b7a 654 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 655 if (real_gfn == UNMAPPED_GVA)
656 return -EFAULT;
657
658 real_gfn = gpa_to_gfn(real_gfn);
659
54bf36aa 660 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 661}
662EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
663
69b0049a 664static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 665 void *data, int offset, int len, u32 access)
666{
667 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
668 data, offset, len, access);
669}
670
a03490ed
CO		 671/*
672 * Load the pae pdptrs. Return true is they are all valid.
673 */
ff03a073 674int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 675{
676 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
677 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
678 int i;
679 int ret;
ff03a073 680 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 681
ff03a073
JR		 682 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
683 offset * sizeof(u64), sizeof(pdpte),
684 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 685 if (ret < 0) {
686 ret = 0;
687 goto out;
688 }
689 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 690 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 691 (pdpte[i] &
44dd3ffa 692 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 693 ret = 0;
694 goto out;
695 }
696 }
697 ret = 1;
698
ff03a073 699 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 700 __set_bit(VCPU_EXREG_PDPTR,
701 (unsigned long *)&vcpu->arch.regs_avail);
702 __set_bit(VCPU_EXREG_PDPTR,
703 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 704out:
a03490ed
CO		 705
706 return ret;
707}
cc4b6871 708EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 709
9ed38ffa 710bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 711{
ff03a073 712 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 713 bool changed = true;
3d06b8bf
JR		 714 int offset;
715 gfn_t gfn;
d835dfec
AK		 716 int r;
717
d35b34a9 718 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
d835dfec
AK		 719 return false;
720
6de4f3ad
AK		 721 if (!test_bit(VCPU_EXREG_PDPTR,
722 (unsigned long *)&vcpu->arch.regs_avail))
723 return true;
724
a512177e
PB		 725 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
726 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 727 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
728 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 729 if (r < 0)
730 goto out;
ff03a073 731 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 732out:
d835dfec
AK		 733
734 return changed;
735}
9ed38ffa 736EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 737
49a9b07e 738int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 739{
aad82703 740 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 741 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 742
f9a48e6a
AK		 743 cr0 |= X86_CR0_ET;
744
ab344828 745#ifdef CONFIG_X86_64
0f12244f
GN		 746 if (cr0 & 0xffffffff00000000UL)
747 return 1;
ab344828
GN		 748#endif
749
750 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 751
0f12244f
GN		 752 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
753 return 1;
a03490ed 754
0f12244f
GN		 755 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
756 return 1;
a03490ed
CO		 757
758 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
759#ifdef CONFIG_X86_64
f6801dff 760 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 761 int cs_db, cs_l;
762
0f12244f
GN		 763 if (!is_pae(vcpu))
764 return 1;
a03490ed 765 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 766 if (cs_l)
767 return 1;
a03490ed
CO		 768 } else
769#endif
ff03a073 770 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 771 kvm_read_cr3(vcpu)))
0f12244f 772 return 1;
a03490ed
CO		 773 }
774
ad756a16
MJ		 775 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
776 return 1;
777
a03490ed 778 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 779
d170c419 780 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 781 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 782 kvm_async_pf_hash_reset(vcpu);
783 }
e5f3f027 784
aad82703
SY		 785 if ((cr0 ^ old_cr0) & update_bits)
786 kvm_mmu_reset_context(vcpu);
b18d5431 787
879ae188
LE		 788 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
789 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
790 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 791 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
792
0f12244f
GN		 793 return 0;
794}
2d3ad1f4 795EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 796
2d3ad1f4 797void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 798{
49a9b07e 799 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 802
42bdf991
MT		 803static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
804{
805 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
806 !vcpu->guest_xcr0_loaded) {
807 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 808 if (vcpu->arch.xcr0 != host_xcr0)
809 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 810 vcpu->guest_xcr0_loaded = 1;
811 }
812}
813
814static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
815{
816 if (vcpu->guest_xcr0_loaded) {
817 if (vcpu->arch.xcr0 != host_xcr0)
818 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
819 vcpu->guest_xcr0_loaded = 0;
820 }
821}
822
69b0049a 823static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 824{
56c103ec
LJ		 825 u64 xcr0 = xcr;
826 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 827 u64 valid_bits;
2acf923e
DC		 828
829 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
830 if (index != XCR_XFEATURE_ENABLED_MASK)
831 return 1;
d91cab78 832 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 833 return 1;
d91cab78 834 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 835 return 1;
46c34cb0
PB		 836
837 /*
838 * Do not allow the guest to set bits that we do not support
839 * saving. However, xcr0 bit 0 is always set, even if the
840 * emulated CPU does not support XSAVE (see fx_init).
841 */
d91cab78 842 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 843 if (xcr0 & ~valid_bits)
2acf923e 844 return 1;
46c34cb0 845
d91cab78
DH		 846 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
847 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 848 return 1;
849
d91cab78
DH		 850 if (xcr0 & XFEATURE_MASK_AVX512) {
851 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 852 return 1;
d91cab78 853 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 854 return 1;
855 }
2acf923e 856 vcpu->arch.xcr0 = xcr0;
56c103ec 857
d91cab78 858 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 859 kvm_update_cpuid(vcpu);
2acf923e
DC		 860 return 0;
861}
862
863int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
864{
764bcbc5
Z		 865 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
866 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 867 kvm_inject_gp(vcpu, 0);
868 return 1;
869 }
870 return 0;
871}
872EXPORT_SYMBOL_GPL(kvm_set_xcr);
873
a83b29c6 874int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 875{
fc78f519 876 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 877 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 878 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 879
0f12244f
GN		 880 if (cr4 & CR4_RESERVED_BITS)
881 return 1;
a03490ed 882
d6321d49 883 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 884 return 1;
885
d6321d49 886 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 887 return 1;
888
d6321d49 889 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 890 return 1;
891
d6321d49 892 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 893 return 1;
894
d6321d49 895 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 896 return 1;
897
fd8cb433 898 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 899 return 1;
900
ae3e61e1
PB		 901 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
902 return 1;
903
a03490ed 904 if (is_long_mode(vcpu)) {
0f12244f
GN		 905 if (!(cr4 & X86_CR4_PAE))
906 return 1;
a2edf57f
AK		 907 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
908 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 909 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
910 kvm_read_cr3(vcpu)))
0f12244f
GN		 911 return 1;
912
ad756a16 913 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 914 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 915 return 1;
916
917 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
918 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
919 return 1;
920 }
921
5e1746d6 922 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 923 return 1;
a03490ed 924
ad756a16
MJ		 925 if (((cr4 ^ old_cr4) & pdptr_bits) ||
926 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 927 kvm_mmu_reset_context(vcpu);
0f12244f 928
b9baba86 929 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 930 kvm_update_cpuid(vcpu);
2acf923e 931
0f12244f
GN		 932 return 0;
933}
2d3ad1f4 934EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 935
2390218b 936int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 937{
ade61e28 938 bool skip_tlb_flush = false;
ac146235 939#ifdef CONFIG_X86_64
c19986fe
JS		 940 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
941
ade61e28 942 if (pcid_enabled) {
208320ba
JS		 943 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
944 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 945 }
ac146235 946#endif
9d88fca7 947
9f8fe504 948 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 949 if (!skip_tlb_flush) {
950 kvm_mmu_sync_roots(vcpu);
ade61e28 951 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 952 }
0f12244f 953 return 0;
d835dfec
AK		 954 }
955
d1cd3ce9 956 if (is_long_mode(vcpu) &&
a780a3ea 957 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 958 return 1;
959 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 960 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 961 return 1;
a03490ed 962
ade61e28 963 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 964 vcpu->arch.cr3 = cr3;
aff48baa 965 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 966
0f12244f
GN		 967 return 0;
968}
2d3ad1f4 969EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 970
eea1cff9 971int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 972{
0f12244f
GN		 973 if (cr8 & CR8_RESERVED_BITS)
974 return 1;
35754c98 975 if (lapic_in_kernel(vcpu))
a03490ed
CO		 976 kvm_lapic_set_tpr(vcpu, cr8);
977 else
ad312c7c 978 vcpu->arch.cr8 = cr8;
0f12244f
GN		 979 return 0;
980}
2d3ad1f4 981EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 982
2d3ad1f4 983unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 984{
35754c98 985 if (lapic_in_kernel(vcpu))
a03490ed
CO		 986 return kvm_lapic_get_cr8(vcpu);
987 else
ad312c7c 988 return vcpu->arch.cr8;
a03490ed 989}
2d3ad1f4 990EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 991
ae561ede
NA		 992static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
993{
994 int i;
995
996 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
997 for (i = 0; i < KVM_NR_DB_REGS; i++)
998 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
999 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1000 }
1001}
1002
73aaf249
JK		 1003static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1004{
1005 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1006 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1007}
1008
c8639010
JK		 1009static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1010{
1011 unsigned long dr7;
1012
1013 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1014 dr7 = vcpu->arch.guest_debug_dr7;
1015 else
1016 dr7 = vcpu->arch.dr7;
1017 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1018 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1019 if (dr7 & DR7_BP_EN_MASK)
1020 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1021}
1022
6f43ed01
NA		 1023static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1024{
1025 u64 fixed = DR6_FIXED_1;
1026
d6321d49 1027 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1028 fixed |= DR6_RTM;
1029 return fixed;
1030}
1031
338dbc97 1032static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1033{
1034 switch (dr) {
1035 case 0 ... 3:
1036 vcpu->arch.db[dr] = val;
1037 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1038 vcpu->arch.eff_db[dr] = val;
1039 break;
1040 case 4:
020df079
GN		 1041 /* fall through */
1042 case 6:
338dbc97
GN		 1043 if (val & 0xffffffff00000000ULL)
1044 return -1; /* #GP */
6f43ed01 1045 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1046 kvm_update_dr6(vcpu);
020df079
GN		 1047 break;
1048 case 5:
020df079
GN		 1049 /* fall through */
1050 default: /* 7 */
338dbc97
GN		 1051 if (val & 0xffffffff00000000ULL)
1052 return -1; /* #GP */
020df079 1053 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1054 kvm_update_dr7(vcpu);
020df079
GN		 1055 break;
1056 }
1057
1058 return 0;
1059}
338dbc97
GN		 1060
1061int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1062{
16f8a6f9 1063 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1064 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1065 return 1;
1066 }
1067 return 0;
338dbc97 1068}
020df079
GN		 1069EXPORT_SYMBOL_GPL(kvm_set_dr);
1070
16f8a6f9 1071int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1072{
1073 switch (dr) {
1074 case 0 ... 3:
1075 *val = vcpu->arch.db[dr];
1076 break;
1077 case 4:
020df079
GN		 1078 /* fall through */
1079 case 6:
73aaf249
JK		 1080 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1081 *val = vcpu->arch.dr6;
1082 else
1083 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1084 break;
1085 case 5:
020df079
GN		 1086 /* fall through */
1087 default: /* 7 */
1088 *val = vcpu->arch.dr7;
1089 break;
1090 }
338dbc97
GN		 1091 return 0;
1092}
020df079
GN		 1093EXPORT_SYMBOL_GPL(kvm_get_dr);
1094
022cd0e8
AK		 1095bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1096{
1097 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1098 u64 data;
1099 int err;
1100
c6702c9d 1101 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1102 if (err)
1103 return err;
1104 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1105 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1106 return err;
1107}
1108EXPORT_SYMBOL_GPL(kvm_rdpmc);
1109
043405e1
CO		 1110/*
1111 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1112 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1113 *
1114 * This list is modified at module load time to reflect the
e3267cbb 1115 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1116 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1117 * may depend on host virtualization features rather than host cpu features.
043405e1 1118 */
e3267cbb 1119
043405e1
CO		 1120static u32 msrs_to_save[] = {
1121 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1122 MSR_STAR,
043405e1
CO		 1123#ifdef CONFIG_X86_64
1124 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1125#endif
b3897a49 1126 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1127 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1128 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1129 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1130 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1131 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1132 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1133 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1134 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
043405e1
CO		 1135};
1136
1137static unsigned num_msrs_to_save;
1138
62ef68bb
PB		 1139static u32 emulated_msrs[] = {
1140 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1141 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1142 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1143 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1144 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1145 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1146 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1147 HV_X64_MSR_RESET,
11c4b1ca 1148 HV_X64_MSR_VP_INDEX,
9eec50b8 1149 HV_X64_MSR_VP_RUNTIME,
5c919412 1150 HV_X64_MSR_SCONTROL,
1f4b34f8 1151 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1152 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1153 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1154 HV_X64_MSR_TSC_EMULATION_STATUS,
1155
1156 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1157 MSR_KVM_PV_EOI_EN,
1158
ba904635 1159 MSR_IA32_TSC_ADJUST,
a3e06bbe 1160 MSR_IA32_TSCDEADLINE,
2bdb76c0 1161 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1162 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1163 MSR_IA32_MCG_STATUS,
1164 MSR_IA32_MCG_CTL,
c45dcc71 1165 MSR_IA32_MCG_EXT_CTL,
64d60670 1166 MSR_IA32_SMBASE,
52797bf9 1167 MSR_SMI_COUNT,
db2336a8
KH		 1168 MSR_PLATFORM_INFO,
1169 MSR_MISC_FEATURES_ENABLES,
bc226f07 1170 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1171};
1172
62ef68bb
PB		 1173static unsigned num_emulated_msrs;
1174
801e459a
TL		 1175/*
1176 * List of msr numbers which are used to expose MSR-based features that
1177 * can be used by a hypervisor to validate requested CPU features.
1178 */
1179static u32 msr_based_features[] = {
1389309c
PB		 1180 MSR_IA32_VMX_BASIC,
1181 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1182 MSR_IA32_VMX_PINBASED_CTLS,
1183 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1184 MSR_IA32_VMX_PROCBASED_CTLS,
1185 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1186 MSR_IA32_VMX_EXIT_CTLS,
1187 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1188 MSR_IA32_VMX_ENTRY_CTLS,
1189 MSR_IA32_VMX_MISC,
1190 MSR_IA32_VMX_CR0_FIXED0,
1191 MSR_IA32_VMX_CR0_FIXED1,
1192 MSR_IA32_VMX_CR4_FIXED0,
1193 MSR_IA32_VMX_CR4_FIXED1,
1194 MSR_IA32_VMX_VMCS_ENUM,
1195 MSR_IA32_VMX_PROCBASED_CTLS2,
1196 MSR_IA32_VMX_EPT_VPID_CAP,
1197 MSR_IA32_VMX_VMFUNC,
1198
d1d93fa9 1199 MSR_F10H_DECFG,
518e7b94 1200 MSR_IA32_UCODE_REV,
cd283252 1201 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1202};
1203
1204static unsigned int num_msr_based_features;
1205
5b76a3cf
PB		 1206u64 kvm_get_arch_capabilities(void)
1207{
1208 u64 data;
1209
1210 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1211
1212 /*
1213 * If we're doing cache flushes (either "always" or "cond")
1214 * we will do one whenever the guest does a vmlaunch/vmresume.
1215 * If an outer hypervisor is doing the cache flush for us
1216 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1217 * capability to the guest too, and if EPT is disabled we're not
1218 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1219 * require a nested hypervisor to do a flush of its own.
1220 */
1221 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1222 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1223
1224 return data;
1225}
1226EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1227
66421c1e
WL		 1228static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1229{
1230 switch (msr->index) {
cd283252 1231 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1232 msr->data = kvm_get_arch_capabilities();
1233 break;
1234 case MSR_IA32_UCODE_REV:
cd283252 1235 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1236 break;
66421c1e
WL		 1237 default:
1238 if (kvm_x86_ops->get_msr_feature(msr))
1239 return 1;
1240 }
1241 return 0;
1242}
1243
801e459a
TL		 1244static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1245{
1246 struct kvm_msr_entry msr;
66421c1e 1247 int r;
801e459a
TL		 1248
1249 msr.index = index;
66421c1e
WL		 1250 r = kvm_get_msr_feature(&msr);
1251 if (r)
1252 return r;
801e459a
TL		 1253
1254 *data = msr.data;
1255
1256 return 0;
1257}
1258
384bb783 1259bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1260{
b69e8cae 1261 if (efer & efer_reserved_bits)
384bb783 1262 return false;
15c4a640 1263
1b4d56b8 1264 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1265 return false;
1b2fd70c 1266
1b4d56b8 1267 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1268 return false;
d8017474 1269
384bb783
JK		 1270 return true;
1271}
1272EXPORT_SYMBOL_GPL(kvm_valid_efer);
1273
1274static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1275{
1276 u64 old_efer = vcpu->arch.efer;
1277
1278 if (!kvm_valid_efer(vcpu, efer))
1279 return 1;
1280
1281 if (is_paging(vcpu)
1282 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1283 return 1;
1284
15c4a640 1285 efer &= ~EFER_LMA;
f6801dff 1286 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1287
a3d204e2
SY		 1288 kvm_x86_ops->set_efer(vcpu, efer);
1289
aad82703
SY		 1290 /* Update reserved bits */
1291 if ((efer ^ old_efer) & EFER_NX)
1292 kvm_mmu_reset_context(vcpu);
1293
b69e8cae 1294 return 0;
15c4a640
CO		 1295}
1296
f2b4b7dd
JR		 1297void kvm_enable_efer_bits(u64 mask)
1298{
1299 efer_reserved_bits &= ~mask;
1300}
1301EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1302
15c4a640
CO		 1303/*
1304 * Writes msr value into into the appropriate "register".
1305 * Returns 0 on success, non-0 otherwise.
1306 * Assumes vcpu_load() was already called.
1307 */
8fe8ab46 1308int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1309{
854e8bb1
NA		 1310 switch (msr->index) {
1311 case MSR_FS_BASE:
1312 case MSR_GS_BASE:
1313 case MSR_KERNEL_GS_BASE:
1314 case MSR_CSTAR:
1315 case MSR_LSTAR:
fd8cb433 1316 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1317 return 1;
1318 break;
1319 case MSR_IA32_SYSENTER_EIP:
1320 case MSR_IA32_SYSENTER_ESP:
1321 /*
1322 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1323 * non-canonical address is written on Intel but not on
1324 * AMD (which ignores the top 32-bits, because it does
1325 * not implement 64-bit SYSENTER).
1326 *
1327 * 64-bit code should hence be able to write a non-canonical
1328 * value on AMD. Making the address canonical ensures that
1329 * vmentry does not fail on Intel after writing a non-canonical
1330 * value, and that something deterministic happens if the guest
1331 * invokes 64-bit SYSENTER.
1332 */
fd8cb433 1333 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1334 }
8fe8ab46 1335 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1336}
854e8bb1 1337EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1338
313a3dc7
CO		 1339/*
1340 * Adapt set_msr() to msr_io()'s calling convention
1341 */
609e36d3
PB		 1342static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1343{
1344 struct msr_data msr;
1345 int r;
1346
1347 msr.index = index;
1348 msr.host_initiated = true;
1349 r = kvm_get_msr(vcpu, &msr);
1350 if (r)
1351 return r;
1352
1353 *data = msr.data;
1354 return 0;
1355}
1356
313a3dc7
CO		 1357static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1358{
8fe8ab46
WA		 1359 struct msr_data msr;
1360
1361 msr.data = *data;
1362 msr.index = index;
1363 msr.host_initiated = true;
1364 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1365}
1366
16e8d74d
MT		 1367#ifdef CONFIG_X86_64
1368struct pvclock_gtod_data {
1369 seqcount_t seq;
1370
1371 struct { /* extract of a clocksource struct */
1372 int vclock_mode;
a5a1d1c2
TG		 1373 u64 cycle_last;
1374 u64 mask;
16e8d74d
MT		 1375 u32 mult;
1376 u32 shift;
1377 } clock;
1378
cbcf2dd3
TG		 1379 u64 boot_ns;
1380 u64 nsec_base;
55dd00a7 1381 u64 wall_time_sec;
16e8d74d
MT		 1382};
1383
1384static struct pvclock_gtod_data pvclock_gtod_data;
1385
1386static void update_pvclock_gtod(struct timekeeper *tk)
1387{
1388 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1389 u64 boot_ns;
1390
876e7881 1391 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1392
1393 write_seqcount_begin(&vdata->seq);
1394
1395 /* copy pvclock gtod data */
876e7881
PZ		 1396 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1397 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1398 vdata->clock.mask = tk->tkr_mono.mask;
1399 vdata->clock.mult = tk->tkr_mono.mult;
1400 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1401
cbcf2dd3 1402 vdata->boot_ns = boot_ns;
876e7881 1403 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1404
55dd00a7
MT		 1405 vdata->wall_time_sec = tk->xtime_sec;
1406
16e8d74d
MT		 1407 write_seqcount_end(&vdata->seq);
1408}
1409#endif
1410
bab5bb39
NK		 1411void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1412{
1413 /*
1414 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1415 * vcpu_enter_guest. This function is only called from
1416 * the physical CPU that is running vcpu.
1417 */
1418 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1419}
16e8d74d 1420
18068523
GOC		 1421static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1422{
9ed3c444
AK		 1423 int version;
1424 int r;
50d0a0f9 1425 struct pvclock_wall_clock wc;
87aeb54f 1426 struct timespec64 boot;
18068523
GOC		 1427
1428 if (!wall_clock)
1429 return;
1430
9ed3c444
AK		 1431 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1432 if (r)
1433 return;
1434
1435 if (version & 1)
1436 ++version; /* first time write, random junk */
1437
1438 ++version;
18068523 1439
1dab1345
NK		 1440 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1441 return;
18068523 1442
50d0a0f9
GH		 1443 /*
1444 * The guest calculates current wall clock time by adding
34c238a1 1445 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1446 * wall clock specified here. guest system time equals host
1447 * system time for us, thus we must fill in host boot time here.
1448 */
87aeb54f 1449 getboottime64(&boot);
50d0a0f9 1450
4b648665 1451 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1452 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1453 boot = timespec64_sub(boot, ts);
4b648665 1454 }
87aeb54f 1455 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1456 wc.nsec = boot.tv_nsec;
1457 wc.version = version;
18068523
GOC		 1458
1459 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1460
1461 version++;
1462 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1463}
1464
50d0a0f9
GH		 1465static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1466{
b51012de
PB		 1467 do_shl32_div32(dividend, divisor);
1468 return dividend;
50d0a0f9
GH		 1469}
1470
3ae13faa 1471static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1472 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1473{
5f4e3f88 1474 uint64_t scaled64;
50d0a0f9
GH		 1475 int32_t shift = 0;
1476 uint64_t tps64;
1477 uint32_t tps32;
1478
3ae13faa
PB		 1479 tps64 = base_hz;
1480 scaled64 = scaled_hz;
50933623 1481 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1482 tps64 >>= 1;
1483 shift--;
1484 }
1485
1486 tps32 = (uint32_t)tps64;
50933623
JK		 1487 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1488 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1489 scaled64 >>= 1;
1490 else
1491 tps32 <<= 1;
50d0a0f9
GH		 1492 shift++;
1493 }
1494
5f4e3f88
ZA		 1495 *pshift = shift;
1496 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1497
3ae13faa
PB		 1498 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1499 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1500}
1501
d828199e 1502#ifdef CONFIG_X86_64
16e8d74d 1503static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1504#endif
16e8d74d 1505
c8076604 1506static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1507static unsigned long max_tsc_khz;
c8076604 1508
cc578287 1509static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1510{
cc578287
ZA		 1511 u64 v = (u64)khz * (1000000 + ppm);
1512 do_div(v, 1000000);
1513 return v;
1e993611
JR		 1514}
1515
381d585c
HZ		 1516static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1517{
1518 u64 ratio;
1519
1520 /* Guest TSC same frequency as host TSC? */
1521 if (!scale) {
1522 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1523 return 0;
1524 }
1525
1526 /* TSC scaling supported? */
1527 if (!kvm_has_tsc_control) {
1528 if (user_tsc_khz > tsc_khz) {
1529 vcpu->arch.tsc_catchup = 1;
1530 vcpu->arch.tsc_always_catchup = 1;
1531 return 0;
1532 } else {
1533 WARN(1, "user requested TSC rate below hardware speed\n");
1534 return -1;
1535 }
1536 }
1537
1538 /* TSC scaling required - calculate ratio */
1539 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1540 user_tsc_khz, tsc_khz);
1541
1542 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1543 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1544 user_tsc_khz);
1545 return -1;
1546 }
1547
1548 vcpu->arch.tsc_scaling_ratio = ratio;
1549 return 0;
1550}
1551
4941b8cb 1552static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1553{
cc578287
ZA		 1554 u32 thresh_lo, thresh_hi;
1555 int use_scaling = 0;
217fc9cf 1556
03ba32ca 1557 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1558 if (user_tsc_khz == 0) {
ad721883
HZ		 1559 /* set tsc_scaling_ratio to a safe value */
1560 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1561 return -1;
ad721883 1562 }
03ba32ca 1563
c285545f 1564 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1565 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1566 &vcpu->arch.virtual_tsc_shift,
1567 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1568 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1569
1570 /*
1571 * Compute the variation in TSC rate which is acceptable
1572 * within the range of tolerance and decide if the
1573 * rate being applied is within that bounds of the hardware
1574 * rate. If so, no scaling or compensation need be done.
1575 */
1576 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1577 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1578 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1579 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1580 use_scaling = 1;
1581 }
4941b8cb 1582 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1583}
1584
1585static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1586{
e26101b1 1587 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1588 vcpu->arch.virtual_tsc_mult,
1589 vcpu->arch.virtual_tsc_shift);
e26101b1 1590 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1591 return tsc;
1592}
1593
b0c39dc6
VK		 1594static inline int gtod_is_based_on_tsc(int mode)
1595{
1596 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1597}
1598
69b0049a 1599static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1600{
1601#ifdef CONFIG_X86_64
1602 bool vcpus_matched;
b48aa97e
MT		 1603 struct kvm_arch *ka = &vcpu->kvm->arch;
1604 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1605
1606 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1607 atomic_read(&vcpu->kvm->online_vcpus));
1608
7f187922
MT		 1609 /*
1610 * Once the masterclock is enabled, always perform request in
1611 * order to update it.
1612 *
1613 * In order to enable masterclock, the host clocksource must be TSC
1614 * and the vcpus need to have matched TSCs. When that happens,
1615 * perform request to enable masterclock.
1616 */
1617 if (ka->use_master_clock ||
b0c39dc6 1618 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1619 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1620
1621 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1622 atomic_read(&vcpu->kvm->online_vcpus),
1623 ka->use_master_clock, gtod->clock.vclock_mode);
1624#endif
1625}
1626
ba904635
WA		 1627static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1628{
e79f245d 1629 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1630 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1631}
1632
35181e86
HZ		 1633/*
1634 * Multiply tsc by a fixed point number represented by ratio.
1635 *
1636 * The most significant 64-N bits (mult) of ratio represent the
1637 * integral part of the fixed point number; the remaining N bits
1638 * (frac) represent the fractional part, ie. ratio represents a fixed
1639 * point number (mult + frac * 2^(-N)).
1640 *
1641 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1642 */
1643static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1644{
1645 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1646}
1647
1648u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1649{
1650 u64 _tsc = tsc;
1651 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1652
1653 if (ratio != kvm_default_tsc_scaling_ratio)
1654 _tsc = __scale_tsc(ratio, tsc);
1655
1656 return _tsc;
1657}
1658EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1659
07c1419a
HZ		 1660static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1661{
1662 u64 tsc;
1663
1664 tsc = kvm_scale_tsc(vcpu, rdtsc());
1665
1666 return target_tsc - tsc;
1667}
1668
4ba76538
HZ		 1669u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1670{
e79f245d
KA		 1671 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1672
1673 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1674}
1675EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1676
a545ab6a
LC		 1677static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1678{
326e7425 1679 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1680}
1681
b0c39dc6
VK		 1682static inline bool kvm_check_tsc_unstable(void)
1683{
1684#ifdef CONFIG_X86_64
1685 /*
1686 * TSC is marked unstable when we're running on Hyper-V,
1687 * 'TSC page' clocksource is good.
1688 */
1689 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1690 return false;
1691#endif
1692 return check_tsc_unstable();
1693}
1694
8fe8ab46 1695void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1696{
1697 struct kvm *kvm = vcpu->kvm;
f38e098f 1698 u64 offset, ns, elapsed;
99e3e30a 1699 unsigned long flags;
b48aa97e 1700 bool matched;
0d3da0d2 1701 bool already_matched;
8fe8ab46 1702 u64 data = msr->data;
c5e8ec8e 1703 bool synchronizing = false;
99e3e30a 1704
038f8c11 1705 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1706 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1707 ns = ktime_get_boot_ns();
f38e098f 1708 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1709
03ba32ca 1710 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1711 if (data == 0 && msr->host_initiated) {
1712 /*
1713 * detection of vcpu initialization -- need to sync
1714 * with other vCPUs. This particularly helps to keep
1715 * kvm_clock stable after CPU hotplug
1716 */
1717 synchronizing = true;
1718 } else {
1719 u64 tsc_exp = kvm->arch.last_tsc_write +
1720 nsec_to_cycles(vcpu, elapsed);
1721 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1722 /*
1723 * Special case: TSC write with a small delta (1 second)
1724 * of virtual cycle time against real time is
1725 * interpreted as an attempt to synchronize the CPU.
1726 */
1727 synchronizing = data < tsc_exp + tsc_hz &&
1728 data + tsc_hz > tsc_exp;
1729 }
c5e8ec8e 1730 }
f38e098f
ZA		 1731
1732 /*
5d3cb0f6
ZA		 1733 * For a reliable TSC, we can match TSC offsets, and for an unstable
1734 * TSC, we add elapsed time in this computation. We could let the
1735 * compensation code attempt to catch up if we fall behind, but
1736 * it's better to try to match offsets from the beginning.
1737 */
c5e8ec8e 1738 if (synchronizing &&
5d3cb0f6 1739 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1740 if (!kvm_check_tsc_unstable()) {
e26101b1 1741 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1742 pr_debug("kvm: matched tsc offset for %llu\n", data);
1743 } else {
857e4099 1744 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1745 data += delta;
07c1419a 1746 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1747 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1748 }
b48aa97e 1749 matched = true;
0d3da0d2 1750 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1751 } else {
1752 /*
1753 * We split periods of matched TSC writes into generations.
1754 * For each generation, we track the original measured
1755 * nanosecond time, offset, and write, so if TSCs are in
1756 * sync, we can match exact offset, and if not, we can match
4a969980 1757 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1758 *
1759 * These values are tracked in kvm->arch.cur_xxx variables.
1760 */
1761 kvm->arch.cur_tsc_generation++;
1762 kvm->arch.cur_tsc_nsec = ns;
1763 kvm->arch.cur_tsc_write = data;
1764 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1765 matched = false;
0d3da0d2 1766 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1767 kvm->arch.cur_tsc_generation, data);
f38e098f 1768 }
e26101b1
ZA		 1769
1770 /*
1771 * We also track th most recent recorded KHZ, write and time to
1772 * allow the matching interval to be extended at each write.
1773 */
f38e098f
ZA		 1774 kvm->arch.last_tsc_nsec = ns;
1775 kvm->arch.last_tsc_write = data;
5d3cb0f6 1776 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1777
b183aa58 1778 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1779
1780 /* Keep track of which generation this VCPU has synchronized to */
1781 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1782 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1783 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1784
d6321d49 1785 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1786 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1787
a545ab6a 1788 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1789 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1790
1791 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1792 if (!matched) {
b48aa97e 1793 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1794 } else if (!already_matched) {
1795 kvm->arch.nr_vcpus_matched_tsc++;
1796 }
b48aa97e
MT		 1797
1798 kvm_track_tsc_matching(vcpu);
1799 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1800}
e26101b1 1801
99e3e30a
ZA		 1802EXPORT_SYMBOL_GPL(kvm_write_tsc);
1803
58ea6767
HZ		 1804static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1805 s64 adjustment)
1806{
326e7425
LS		 1807 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1808 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1809}
1810
1811static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1812{
1813 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1814 WARN_ON(adjustment < 0);
1815 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1816 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1817}
1818
d828199e
MT		 1819#ifdef CONFIG_X86_64
1820
a5a1d1c2 1821static u64 read_tsc(void)
d828199e 1822{
a5a1d1c2 1823 u64 ret = (u64)rdtsc_ordered();
03b9730b 1824 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1825
1826 if (likely(ret >= last))
1827 return ret;
1828
1829 /*
1830 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1831 * predictable (it's just a function of time and the likely is
d828199e
MT		 1832 * very likely) and there's a data dependence, so force GCC
1833 * to generate a branch instead. I don't barrier() because
1834 * we don't actually need a barrier, and if this function
1835 * ever gets inlined it will generate worse code.
1836 */
1837 asm volatile ("");
1838 return last;
1839}
1840
b0c39dc6 1841static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1842{
1843 long v;
1844 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1845 u64 tsc_pg_val;
1846
1847 switch (gtod->clock.vclock_mode) {
1848 case VCLOCK_HVCLOCK:
1849 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1850 tsc_timestamp);
1851 if (tsc_pg_val != U64_MAX) {
1852 /* TSC page valid */
1853 *mode = VCLOCK_HVCLOCK;
1854 v = (tsc_pg_val - gtod->clock.cycle_last) &
1855 gtod->clock.mask;
1856 } else {
1857 /* TSC page invalid */
1858 *mode = VCLOCK_NONE;
1859 }
1860 break;
1861 case VCLOCK_TSC:
1862 *mode = VCLOCK_TSC;
1863 *tsc_timestamp = read_tsc();
1864 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1865 gtod->clock.mask;
1866 break;
1867 default:
1868 *mode = VCLOCK_NONE;
1869 }
d828199e 1870
b0c39dc6
VK		 1871 if (*mode == VCLOCK_NONE)
1872 *tsc_timestamp = v = 0;
d828199e 1873
d828199e
MT		 1874 return v * gtod->clock.mult;
1875}
1876
b0c39dc6 1877static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1878{
cbcf2dd3 1879 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1880 unsigned long seq;
d828199e 1881 int mode;
cbcf2dd3 1882 u64 ns;
d828199e 1883
d828199e
MT		 1884 do {
1885 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1886 ns = gtod->nsec_base;
b0c39dc6 1887 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1888 ns >>= gtod->clock.shift;
cbcf2dd3 1889 ns += gtod->boot_ns;
d828199e 1890 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1891 *t = ns;
d828199e
MT		 1892
1893 return mode;
1894}
1895
899a31f5 1896static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1897{
1898 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1899 unsigned long seq;
1900 int mode;
1901 u64 ns;
1902
1903 do {
1904 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1905 ts->tv_sec = gtod->wall_time_sec;
1906 ns = gtod->nsec_base;
b0c39dc6 1907 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1908 ns >>= gtod->clock.shift;
1909 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1910
1911 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1912 ts->tv_nsec = ns;
1913
1914 return mode;
1915}
1916
b0c39dc6
VK		 1917/* returns true if host is using TSC based clocksource */
1918static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1919{
d828199e 1920 /* checked again under seqlock below */
b0c39dc6 1921 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1922 return false;
1923
b0c39dc6
VK		 1924 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1925 tsc_timestamp));
d828199e 1926}
55dd00a7 1927
b0c39dc6 1928/* returns true if host is using TSC based clocksource */
899a31f5 1929static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1930 u64 *tsc_timestamp)
55dd00a7
MT		 1931{
1932 /* checked again under seqlock below */
b0c39dc6 1933 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1934 return false;
1935
b0c39dc6 1936 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1937}
d828199e
MT		 1938#endif
1939
1940/*
1941 *
b48aa97e
MT		 1942 * Assuming a stable TSC across physical CPUS, and a stable TSC
1943 * across virtual CPUs, the following condition is possible.
1944 * Each numbered line represents an event visible to both
d828199e
MT		 1945 * CPUs at the next numbered event.
1946 *
1947 * "timespecX" represents host monotonic time. "tscX" represents
1948 * RDTSC value.
1949 *
1950 * VCPU0 on CPU0 | VCPU1 on CPU1
1951 *
1952 * 1. read timespec0,tsc0
1953 * 2. | timespec1 = timespec0 + N
1954 * | tsc1 = tsc0 + M
1955 * 3. transition to guest | transition to guest
1956 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1957 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1958 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1959 *
1960 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1961 *
1962 * - ret0 < ret1
1963 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1964 * ...
1965 * - 0 < N - M => M < N
1966 *
1967 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1968 * always the case (the difference between two distinct xtime instances
1969 * might be smaller then the difference between corresponding TSC reads,
1970 * when updating guest vcpus pvclock areas).
1971 *
1972 * To avoid that problem, do not allow visibility of distinct
1973 * system_timestamp/tsc_timestamp values simultaneously: use a master
1974 * copy of host monotonic time values. Update that master copy
1975 * in lockstep.
1976 *
b48aa97e 1977 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1978 *
1979 */
1980
1981static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1982{
1983#ifdef CONFIG_X86_64
1984 struct kvm_arch *ka = &kvm->arch;
1985 int vclock_mode;
b48aa97e
MT		 1986 bool host_tsc_clocksource, vcpus_matched;
1987
1988 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1989 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1990
1991 /*
1992 * If the host uses TSC clock, then passthrough TSC as stable
1993 * to the guest.
1994 */
b48aa97e 1995 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1996 &ka->master_kernel_ns,
1997 &ka->master_cycle_now);
1998
16a96021 1999 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2000 && !ka->backwards_tsc_observed
54750f2c 2001 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2002
d828199e
MT		 2003 if (ka->use_master_clock)
2004 atomic_set(&kvm_guest_has_master_clock, 1);
2005
2006 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2007 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2008 vcpus_matched);
d828199e
MT		 2009#endif
2010}
2011
2860c4b1
PB		 2012void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2013{
2014 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2015}
2016
2e762ff7
MT		 2017static void kvm_gen_update_masterclock(struct kvm *kvm)
2018{
2019#ifdef CONFIG_X86_64
2020 int i;
2021 struct kvm_vcpu *vcpu;
2022 struct kvm_arch *ka = &kvm->arch;
2023
2024 spin_lock(&ka->pvclock_gtod_sync_lock);
2025 kvm_make_mclock_inprogress_request(kvm);
2026 /* no guest entries from this point */
2027 pvclock_update_vm_gtod_copy(kvm);
2028
2029 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2030 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2031
2032 /* guest entries allowed */
2033 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2034 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2035
2036 spin_unlock(&ka->pvclock_gtod_sync_lock);
2037#endif
2038}
2039
e891a32e 2040u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2041{
108b249c 2042 struct kvm_arch *ka = &kvm->arch;
8b953440 2043 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2044 u64 ret;
108b249c 2045
8b953440
PB		 2046 spin_lock(&ka->pvclock_gtod_sync_lock);
2047 if (!ka->use_master_clock) {
2048 spin_unlock(&ka->pvclock_gtod_sync_lock);
2049 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 2050 }
2051
8b953440
PB		 2052 hv_clock.tsc_timestamp = ka->master_cycle_now;
2053 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2054 spin_unlock(&ka->pvclock_gtod_sync_lock);
2055
e2c2206a
WL		 2056 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2057 get_cpu();
2058
e70b57a6
WL		 2059 if (__this_cpu_read(cpu_tsc_khz)) {
2060 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2061 &hv_clock.tsc_shift,
2062 &hv_clock.tsc_to_system_mul);
2063 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2064 } else
2065 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2066
2067 put_cpu();
2068
2069 return ret;
108b249c
PB		 2070}
2071
0d6dd2ff
PB		 2072static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2073{
2074 struct kvm_vcpu_arch *vcpu = &v->arch;
2075 struct pvclock_vcpu_time_info guest_hv_clock;
2076
4e335d9e 2077 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2078 &guest_hv_clock, sizeof(guest_hv_clock))))
2079 return;
2080
2081 /* This VCPU is paused, but it's legal for a guest to read another
2082 * VCPU's kvmclock, so we really have to follow the specification where
2083 * it says that version is odd if data is being modified, and even after
2084 * it is consistent.
2085 *
2086 * Version field updates must be kept separate. This is because
2087 * kvm_write_guest_cached might use a "rep movs" instruction, and
2088 * writes within a string instruction are weakly ordered. So there
2089 * are three writes overall.
2090 *
2091 * As a small optimization, only write the version field in the first
2092 * and third write. The vcpu->pv_time cache is still valid, because the
2093 * version field is the first in the struct.
2094 */
2095 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2096
51c4b8bb
LA		 2097 if (guest_hv_clock.version & 1)
2098 ++guest_hv_clock.version; /* first time write, random junk */
2099
0d6dd2ff 2100 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2101 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2102 &vcpu->hv_clock,
2103 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2104
2105 smp_wmb();
2106
2107 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2108 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2109
2110 if (vcpu->pvclock_set_guest_stopped_request) {
2111 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2112 vcpu->pvclock_set_guest_stopped_request = false;
2113 }
2114
2115 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2116
4e335d9e
PB		 2117 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2118 &vcpu->hv_clock,
2119 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2120
2121 smp_wmb();
2122
2123 vcpu->hv_clock.version++;
4e335d9e
PB		 2124 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2125 &vcpu->hv_clock,
2126 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2127}
2128
34c238a1 2129static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2130{
78db6a50 2131 unsigned long flags, tgt_tsc_khz;
18068523 2132 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2133 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2134 s64 kernel_ns;
d828199e 2135 u64 tsc_timestamp, host_tsc;
51d59c6b 2136 u8 pvclock_flags;
d828199e
MT		 2137 bool use_master_clock;
2138
2139 kernel_ns = 0;
2140 host_tsc = 0;
18068523 2141
d828199e
MT		 2142 /*
2143 * If the host uses TSC clock, then passthrough TSC as stable
2144 * to the guest.
2145 */
2146 spin_lock(&ka->pvclock_gtod_sync_lock);
2147 use_master_clock = ka->use_master_clock;
2148 if (use_master_clock) {
2149 host_tsc = ka->master_cycle_now;
2150 kernel_ns = ka->master_kernel_ns;
2151 }
2152 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2153
2154 /* Keep irq disabled to prevent changes to the clock */
2155 local_irq_save(flags);
78db6a50
PB		 2156 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2157 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2158 local_irq_restore(flags);
2159 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2160 return 1;
2161 }
d828199e 2162 if (!use_master_clock) {
4ea1636b 2163 host_tsc = rdtsc();
108b249c 2164 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2165 }
2166
4ba76538 2167 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2168
c285545f
ZA		 2169 /*
2170 * We may have to catch up the TSC to match elapsed wall clock
2171 * time for two reasons, even if kvmclock is used.
2172 * 1) CPU could have been running below the maximum TSC rate
2173 * 2) Broken TSC compensation resets the base at each VCPU
2174 * entry to avoid unknown leaps of TSC even when running
2175 * again on the same CPU. This may cause apparent elapsed
2176 * time to disappear, and the guest to stand still or run
2177 * very slowly.
2178 */
2179 if (vcpu->tsc_catchup) {
2180 u64 tsc = compute_guest_tsc(v, kernel_ns);
2181 if (tsc > tsc_timestamp) {
f1e2b260 2182 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2183 tsc_timestamp = tsc;
2184 }
50d0a0f9
GH		 2185 }
2186
18068523
GOC		 2187 local_irq_restore(flags);
2188
0d6dd2ff 2189 /* With all the info we got, fill in the values */
18068523 2190
78db6a50
PB		 2191 if (kvm_has_tsc_control)
2192 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2193
2194 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2195 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2196 &vcpu->hv_clock.tsc_shift,
2197 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2198 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2199 }
2200
1d5f066e 2201 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2202 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2203 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2204
d828199e 2205 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2206 pvclock_flags = 0;
d828199e
MT		 2207 if (use_master_clock)
2208 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2209
78c0337a
MT		 2210 vcpu->hv_clock.flags = pvclock_flags;
2211
095cf55d
PB		 2212 if (vcpu->pv_time_enabled)
2213 kvm_setup_pvclock_page(v);
2214 if (v == kvm_get_vcpu(v->kvm, 0))
2215 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2216 return 0;
c8076604
GH		 2217}
2218
0061d53d
MT		 2219/*
2220 * kvmclock updates which are isolated to a given vcpu, such as
2221 * vcpu->cpu migration, should not allow system_timestamp from
2222 * the rest of the vcpus to remain static. Otherwise ntp frequency
2223 * correction applies to one vcpu's system_timestamp but not
2224 * the others.
2225 *
2226 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2227 * We need to rate-limit these requests though, as they can
2228 * considerably slow guests that have a large number of vcpus.
2229 * The time for a remote vcpu to update its kvmclock is bound
2230 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2231 */
2232
7e44e449
AJ		 2233#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2234
2235static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2236{
2237 int i;
7e44e449
AJ		 2238 struct delayed_work *dwork = to_delayed_work(work);
2239 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2240 kvmclock_update_work);
2241 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2242 struct kvm_vcpu *vcpu;
2243
2244 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2245 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2246 kvm_vcpu_kick(vcpu);
2247 }
2248}
2249
7e44e449
AJ		 2250static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2251{
2252 struct kvm *kvm = v->kvm;
2253
105b21bb 2254 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2255 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2256 KVMCLOCK_UPDATE_DELAY);
2257}
2258
332967a3
AJ		 2259#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2260
2261static void kvmclock_sync_fn(struct work_struct *work)
2262{
2263 struct delayed_work *dwork = to_delayed_work(work);
2264 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2265 kvmclock_sync_work);
2266 struct kvm *kvm = container_of(ka, struct kvm, arch);
2267
630994b3
MT		 2268 if (!kvmclock_periodic_sync)
2269 return;
2270
332967a3
AJ		 2271 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2272 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2273 KVMCLOCK_SYNC_PERIOD);
2274}
2275
9ffd986c 2276static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2277{
890ca9ae
HY		 2278 u64 mcg_cap = vcpu->arch.mcg_cap;
2279 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2280 u32 msr = msr_info->index;
2281 u64 data = msr_info->data;
890ca9ae 2282
15c4a640 2283 switch (msr) {
15c4a640 2284 case MSR_IA32_MCG_STATUS:
890ca9ae 2285 vcpu->arch.mcg_status = data;
15c4a640 2286 break;
c7ac679c 2287 case MSR_IA32_MCG_CTL:
44883f01
PB		 2288 if (!(mcg_cap & MCG_CTL_P) &&
2289 (data || !msr_info->host_initiated))
890ca9ae
HY		 2290 return 1;
2291 if (data != 0 && data != ~(u64)0)
44883f01 2292 return 1;
890ca9ae
HY		 2293 vcpu->arch.mcg_ctl = data;
2294 break;
2295 default:
2296 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2297 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2298 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2299 /* only 0 or all 1s can be written to IA32_MCi_CTL
2300 * some Linux kernels though clear bit 10 in bank 4 to
2301 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2302 * this to avoid an uncatched #GP in the guest
2303 */
890ca9ae 2304 if ((offset & 0x3) == 0 &&
114be429 2305 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2306 return -1;
9ffd986c
WL		 2307 if (!msr_info->host_initiated &&
2308 (offset & 0x3) == 1 && data != 0)
2309 return -1;
890ca9ae
HY		 2310 vcpu->arch.mce_banks[offset] = data;
2311 break;
2312 }
2313 return 1;
2314 }
2315 return 0;
2316}
2317
ffde22ac
ES		 2318static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2319{
2320 struct kvm *kvm = vcpu->kvm;
2321 int lm = is_long_mode(vcpu);
2322 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2323 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2324 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2325 : kvm->arch.xen_hvm_config.blob_size_32;
2326 u32 page_num = data & ~PAGE_MASK;
2327 u64 page_addr = data & PAGE_MASK;
2328 u8 *page;
2329 int r;
2330
2331 r = -E2BIG;
2332 if (page_num >= blob_size)
2333 goto out;
2334 r = -ENOMEM;
ff5c2c03
SL		 2335 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2336 if (IS_ERR(page)) {
2337 r = PTR_ERR(page);
ffde22ac 2338 goto out;
ff5c2c03 2339 }
54bf36aa 2340 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2341 goto out_free;
2342 r = 0;
2343out_free:
2344 kfree(page);
2345out:
2346 return r;
2347}
2348
344d9588
GN		 2349static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2350{
2351 gpa_t gpa = data & ~0x3f;
2352
52a5c155
WL		 2353 /* Bits 3:5 are reserved, Should be zero */
2354 if (data & 0x38)
344d9588
GN		 2355 return 1;
2356
2357 vcpu->arch.apf.msr_val = data;
2358
2359 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2360 kvm_clear_async_pf_completion_queue(vcpu);
2361 kvm_async_pf_hash_reset(vcpu);
2362 return 0;
2363 }
2364
4e335d9e 2365 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2366 sizeof(u32)))
344d9588
GN		 2367 return 1;
2368
6adba527 2369 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2370 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2371 kvm_async_pf_wakeup_all(vcpu);
2372 return 0;
2373}
2374
12f9a48f
GC		 2375static void kvmclock_reset(struct kvm_vcpu *vcpu)
2376{
0b79459b 2377 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2378}
2379
f38a7b75
WL		 2380static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2381{
2382 ++vcpu->stat.tlb_flush;
2383 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2384}
2385
c9aaa895
GC		 2386static void record_steal_time(struct kvm_vcpu *vcpu)
2387{
2388 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2389 return;
2390
4e335d9e 2391 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2392 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2393 return;
2394
f38a7b75
WL		 2395 /*
2396 * Doing a TLB flush here, on the guest's behalf, can avoid
2397 * expensive IPIs.
2398 */
2399 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2400 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2401
35f3fae1
WL		 2402 if (vcpu->arch.st.steal.version & 1)
2403 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2404
2405 vcpu->arch.st.steal.version += 1;
2406
4e335d9e 2407 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2408 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2409
2410 smp_wmb();
2411
c54cdf14
LC		 2412 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2413 vcpu->arch.st.last_steal;
2414 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2415
4e335d9e 2416 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2417 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2418
2419 smp_wmb();
2420
2421 vcpu->arch.st.steal.version += 1;
c9aaa895 2422
4e335d9e 2423 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2424 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2425}
2426
8fe8ab46 2427int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2428{
5753785f 2429 bool pr = false;
8fe8ab46
WA		 2430 u32 msr = msr_info->index;
2431 u64 data = msr_info->data;
5753785f 2432
15c4a640 2433 switch (msr) {
2e32b719 2434 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2435 case MSR_IA32_UCODE_WRITE:
2436 case MSR_VM_HSAVE_PA:
2437 case MSR_AMD64_PATCH_LOADER:
2438 case MSR_AMD64_BU_CFG2:
405a353a 2439 case MSR_AMD64_DC_CFG:
0e1b869f 2440 case MSR_F15H_EX_CFG:
2e32b719
BP		 2441 break;
2442
518e7b94
WL		 2443 case MSR_IA32_UCODE_REV:
2444 if (msr_info->host_initiated)
2445 vcpu->arch.microcode_version = data;
2446 break;
0cf9135b
SC		 2447 case MSR_IA32_ARCH_CAPABILITIES:
2448 if (!msr_info->host_initiated)
2449 return 1;
2450 vcpu->arch.arch_capabilities = data;
2451 break;
15c4a640 2452 case MSR_EFER:
b69e8cae 2453 return set_efer(vcpu, data);
8f1589d9
AP		 2454 case MSR_K7_HWCR:
2455 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2456 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2457 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2458 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2459 if (data != 0) {
a737f256
CD		 2460 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2461 data);
8f1589d9
AP		 2462 return 1;
2463 }
15c4a640 2464 break;
f7c6d140
AP		 2465 case MSR_FAM10H_MMIO_CONF_BASE:
2466 if (data != 0) {
a737f256
CD		 2467 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2468 "0x%llx\n", data);
f7c6d140
AP		 2469 return 1;
2470 }
15c4a640 2471 break;
b5e2fec0
AG		 2472 case MSR_IA32_DEBUGCTLMSR:
2473 if (!data) {
2474 /* We support the non-activated case already */
2475 break;
2476 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2477 /* Values other than LBR and BTF are vendor-specific,
2478 thus reserved and should throw a #GP */
2479 return 1;
2480 }
a737f256
CD		 2481 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2482 __func__, data);
b5e2fec0 2483 break;
9ba075a6 2484 case 0x200 ... 0x2ff:
ff53604b 2485 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2486 case MSR_IA32_APICBASE:
58cb628d 2487 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2488 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2489 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2490 case MSR_IA32_TSCDEADLINE:
2491 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2492 break;
ba904635 2493 case MSR_IA32_TSC_ADJUST:
d6321d49 2494 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2495 if (!msr_info->host_initiated) {
d913b904 2496 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2497 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2498 }
2499 vcpu->arch.ia32_tsc_adjust_msr = data;
2500 }
2501 break;
15c4a640 2502 case MSR_IA32_MISC_ENABLE:
ad312c7c 2503 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2504 break;
64d60670
PB		 2505 case MSR_IA32_SMBASE:
2506 if (!msr_info->host_initiated)
2507 return 1;
2508 vcpu->arch.smbase = data;
2509 break;
dd259935
PB		 2510 case MSR_IA32_TSC:
2511 kvm_write_tsc(vcpu, msr_info);
2512 break;
52797bf9
LA		 2513 case MSR_SMI_COUNT:
2514 if (!msr_info->host_initiated)
2515 return 1;
2516 vcpu->arch.smi_count = data;
2517 break;
11c6bffa 2518 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2519 case MSR_KVM_WALL_CLOCK:
2520 vcpu->kvm->arch.wall_clock = data;
2521 kvm_write_wall_clock(vcpu->kvm, data);
2522 break;
11c6bffa 2523 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2524 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2525 struct kvm_arch *ka = &vcpu->kvm->arch;
2526
12f9a48f 2527 kvmclock_reset(vcpu);
18068523 2528
54750f2c
MT		 2529 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2530 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2531
2532 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2533 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2534
2535 ka->boot_vcpu_runs_old_kvmclock = tmp;
2536 }
2537
18068523 2538 vcpu->arch.time = data;
0061d53d 2539 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2540
2541 /* we verify if the enable bit is set... */
2542 if (!(data & 1))
2543 break;
2544
4e335d9e 2545 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2546 &vcpu->arch.pv_time, data & ~1ULL,
2547 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2548 vcpu->arch.pv_time_enabled = false;
2549 else
2550 vcpu->arch.pv_time_enabled = true;
32cad84f 2551
18068523
GOC		 2552 break;
2553 }
344d9588
GN		 2554 case MSR_KVM_ASYNC_PF_EN:
2555 if (kvm_pv_enable_async_pf(vcpu, data))
2556 return 1;
2557 break;
c9aaa895
GC		 2558 case MSR_KVM_STEAL_TIME:
2559
2560 if (unlikely(!sched_info_on()))
2561 return 1;
2562
2563 if (data & KVM_STEAL_RESERVED_MASK)
2564 return 1;
2565
4e335d9e 2566 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2567 data & KVM_STEAL_VALID_BITS,
2568 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2569 return 1;
2570
2571 vcpu->arch.st.msr_val = data;
2572
2573 if (!(data & KVM_MSR_ENABLED))
2574 break;
2575
c9aaa895
GC		 2576 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2577
2578 break;
ae7a2a3f 2579 case MSR_KVM_PV_EOI_EN:
72bbf935 2580 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2581 return 1;
2582 break;
c9aaa895 2583
890ca9ae
HY		 2584 case MSR_IA32_MCG_CTL:
2585 case MSR_IA32_MCG_STATUS:
81760dcc 2586 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2587 return set_msr_mce(vcpu, msr_info);
71db6023 2588
6912ac32
WH		 2589 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2590 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2591 pr = true; /* fall through */
2592 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2593 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2594 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2595 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2596
2597 if (pr || data != 0)
a737f256
CD		 2598 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2599 "0x%x data 0x%llx\n", msr, data);
5753785f 2600 break;
84e0cefa
JS		 2601 case MSR_K7_CLK_CTL:
2602 /*
2603 * Ignore all writes to this no longer documented MSR.
2604 * Writes are only relevant for old K7 processors,
2605 * all pre-dating SVM, but a recommended workaround from
4a969980 2606 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2607 * affected processor models on the command line, hence
2608 * the need to ignore the workaround.
2609 */
2610 break;
55cd8e5a 2611 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2612 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2613 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2614 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2615 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2616 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2617 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2618 return kvm_hv_set_msr_common(vcpu, msr, data,
2619 msr_info->host_initiated);
91c9c3ed 2620 case MSR_IA32_BBL_CR_CTL3:
2621 /* Drop writes to this legacy MSR -- see rdmsr
2622 * counterpart for further detail.
2623 */
fab0aa3b
EM		 2624 if (report_ignored_msrs)
2625 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2626 msr, data);
91c9c3ed 2627 break;
2b036c6b 2628 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2629 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2630 return 1;
2631 vcpu->arch.osvw.length = data;
2632 break;
2633 case MSR_AMD64_OSVW_STATUS:
d6321d49 2634 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2635 return 1;
2636 vcpu->arch.osvw.status = data;
2637 break;
db2336a8
KH		 2638 case MSR_PLATFORM_INFO:
2639 if (!msr_info->host_initiated ||
db2336a8
KH		 2640 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2641 cpuid_fault_enabled(vcpu)))
2642 return 1;
2643 vcpu->arch.msr_platform_info = data;
2644 break;
2645 case MSR_MISC_FEATURES_ENABLES:
2646 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2647 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2648 !supports_cpuid_fault(vcpu)))
2649 return 1;
2650 vcpu->arch.msr_misc_features_enables = data;
2651 break;
15c4a640 2652 default:
ffde22ac
ES		 2653 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2654 return xen_hvm_config(vcpu, data);
c6702c9d 2655 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2656 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2657 if (!ignore_msrs) {
ae0f5499 2658 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2659 msr, data);
ed85c068
AP		 2660 return 1;
2661 } else {
fab0aa3b
EM		 2662 if (report_ignored_msrs)
2663 vcpu_unimpl(vcpu,
2664 "ignored wrmsr: 0x%x data 0x%llx\n",
2665 msr, data);
ed85c068
AP		 2666 break;
2667 }
15c4a640
CO		 2668 }
2669 return 0;
2670}
2671EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2672
2673
2674/*
2675 * Reads an msr value (of 'msr_index') into 'pdata'.
2676 * Returns 0 on success, non-0 otherwise.
2677 * Assumes vcpu_load() was already called.
2678 */
609e36d3 2679int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2680{
609e36d3 2681 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2682}
ff651cb6 2683EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2684
44883f01 2685static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2686{
2687 u64 data;
890ca9ae
HY		 2688 u64 mcg_cap = vcpu->arch.mcg_cap;
2689 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2690
2691 switch (msr) {
15c4a640
CO		 2692 case MSR_IA32_P5_MC_ADDR:
2693 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2694 data = 0;
2695 break;
15c4a640 2696 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2697 data = vcpu->arch.mcg_cap;
2698 break;
c7ac679c 2699 case MSR_IA32_MCG_CTL:
44883f01 2700 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2701 return 1;
2702 data = vcpu->arch.mcg_ctl;
2703 break;
2704 case MSR_IA32_MCG_STATUS:
2705 data = vcpu->arch.mcg_status;
2706 break;
2707 default:
2708 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2709 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2710 u32 offset = msr - MSR_IA32_MC0_CTL;
2711 data = vcpu->arch.mce_banks[offset];
2712 break;
2713 }
2714 return 1;
2715 }
2716 *pdata = data;
2717 return 0;
2718}
2719
609e36d3 2720int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2721{
609e36d3 2722 switch (msr_info->index) {
890ca9ae 2723 case MSR_IA32_PLATFORM_ID:
15c4a640 2724 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2725 case MSR_IA32_DEBUGCTLMSR:
2726 case MSR_IA32_LASTBRANCHFROMIP:
2727 case MSR_IA32_LASTBRANCHTOIP:
2728 case MSR_IA32_LASTINTFROMIP:
2729 case MSR_IA32_LASTINTTOIP:
60af2ecd 2730 case MSR_K8_SYSCFG:
3afb1121
PB		 2731 case MSR_K8_TSEG_ADDR:
2732 case MSR_K8_TSEG_MASK:
60af2ecd 2733 case MSR_K7_HWCR:
61a6bd67 2734 case MSR_VM_HSAVE_PA:
1fdbd48c 2735 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2736 case MSR_AMD64_NB_CFG:
f7c6d140 2737 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2738 case MSR_AMD64_BU_CFG2:
0c2df2a1 2739 case MSR_IA32_PERF_CTL:
405a353a 2740 case MSR_AMD64_DC_CFG:
0e1b869f 2741 case MSR_F15H_EX_CFG:
609e36d3 2742 msr_info->data = 0;
15c4a640 2743 break;
c51eb52b 2744 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2745 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2746 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2747 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2748 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2749 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2750 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2751 msr_info->data = 0;
5753785f 2752 break;
742bc670 2753 case MSR_IA32_UCODE_REV:
518e7b94 2754 msr_info->data = vcpu->arch.microcode_version;
742bc670 2755 break;
0cf9135b
SC		 2756 case MSR_IA32_ARCH_CAPABILITIES:
2757 if (!msr_info->host_initiated &&
2758 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2759 return 1;
2760 msr_info->data = vcpu->arch.arch_capabilities;
2761 break;
dd259935
PB		 2762 case MSR_IA32_TSC:
2763 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2764 break;
9ba075a6 2765 case MSR_MTRRcap:
9ba075a6 2766 case 0x200 ... 0x2ff:
ff53604b 2767 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2768 case 0xcd: /* fsb frequency */
609e36d3 2769 msr_info->data = 3;
15c4a640 2770 break;
7b914098
JS		 2771 /*
2772 * MSR_EBC_FREQUENCY_ID
2773 * Conservative value valid for even the basic CPU models.
2774 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2775 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2776 * and 266MHz for model 3, or 4. Set Core Clock
2777 * Frequency to System Bus Frequency Ratio to 1 (bits
2778 * 31:24) even though these are only valid for CPU
2779 * models > 2, however guests may end up dividing or
2780 * multiplying by zero otherwise.
2781 */
2782 case MSR_EBC_FREQUENCY_ID:
609e36d3 2783 msr_info->data = 1 << 24;
7b914098 2784 break;
15c4a640 2785 case MSR_IA32_APICBASE:
609e36d3 2786 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2787 break;
0105d1a5 2788 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2789 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2790 break;
a3e06bbe 2791 case MSR_IA32_TSCDEADLINE:
609e36d3 2792 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2793 break;
ba904635 2794 case MSR_IA32_TSC_ADJUST:
609e36d3 2795 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2796 break;
15c4a640 2797 case MSR_IA32_MISC_ENABLE:
609e36d3 2798 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2799 break;
64d60670
PB		 2800 case MSR_IA32_SMBASE:
2801 if (!msr_info->host_initiated)
2802 return 1;
2803 msr_info->data = vcpu->arch.smbase;
15c4a640 2804 break;
52797bf9
LA		 2805 case MSR_SMI_COUNT:
2806 msr_info->data = vcpu->arch.smi_count;
2807 break;
847f0ad8
AG		 2808 case MSR_IA32_PERF_STATUS:
2809 /* TSC increment by tick */
609e36d3 2810 msr_info->data = 1000ULL;
847f0ad8 2811 /* CPU multiplier */
b0996ae4 2812 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2813 break;
15c4a640 2814 case MSR_EFER:
609e36d3 2815 msr_info->data = vcpu->arch.efer;
15c4a640 2816 break;
18068523 2817 case MSR_KVM_WALL_CLOCK:
11c6bffa 2818 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2819 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2820 break;
2821 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2822 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2823 msr_info->data = vcpu->arch.time;
18068523 2824 break;
344d9588 2825 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2826 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2827 break;
c9aaa895 2828 case MSR_KVM_STEAL_TIME:
609e36d3 2829 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2830 break;
1d92128f 2831 case MSR_KVM_PV_EOI_EN:
609e36d3 2832 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2833 break;
890ca9ae
HY		 2834 case MSR_IA32_P5_MC_ADDR:
2835 case MSR_IA32_P5_MC_TYPE:
2836 case MSR_IA32_MCG_CAP:
2837 case MSR_IA32_MCG_CTL:
2838 case MSR_IA32_MCG_STATUS:
81760dcc 2839 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2840 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2841 msr_info->host_initiated);
84e0cefa
JS		 2842 case MSR_K7_CLK_CTL:
2843 /*
2844 * Provide expected ramp-up count for K7. All other
2845 * are set to zero, indicating minimum divisors for
2846 * every field.
2847 *
2848 * This prevents guest kernels on AMD host with CPU
2849 * type 6, model 8 and higher from exploding due to
2850 * the rdmsr failing.
2851 */
609e36d3 2852 msr_info->data = 0x20000000;
84e0cefa 2853 break;
55cd8e5a 2854 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2855 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2856 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2857 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2858 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2859 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2860 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2861 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2862 msr_info->index, &msr_info->data,
2863 msr_info->host_initiated);
55cd8e5a 2864 break;
91c9c3ed 2865 case MSR_IA32_BBL_CR_CTL3:
2866 /* This legacy MSR exists but isn't fully documented in current
2867 * silicon. It is however accessed by winxp in very narrow
2868 * scenarios where it sets bit #19, itself documented as
2869 * a "reserved" bit. Best effort attempt to source coherent
2870 * read data here should the balance of the register be
2871 * interpreted by the guest:
2872 *
2873 * L2 cache control register 3: 64GB range, 256KB size,
2874 * enabled, latency 0x1, configured
2875 */
609e36d3 2876 msr_info->data = 0xbe702111;
91c9c3ed 2877 break;
2b036c6b 2878 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2879 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2880 return 1;
609e36d3 2881 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2882 break;
2883 case MSR_AMD64_OSVW_STATUS:
d6321d49 2884 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2885 return 1;
609e36d3 2886 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2887 break;
db2336a8 2888 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2889 if (!msr_info->host_initiated &&
2890 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2891 return 1;
db2336a8
KH		 2892 msr_info->data = vcpu->arch.msr_platform_info;
2893 break;
2894 case MSR_MISC_FEATURES_ENABLES:
2895 msr_info->data = vcpu->arch.msr_misc_features_enables;
2896 break;
15c4a640 2897 default:
c6702c9d 2898 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2899 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2900 if (!ignore_msrs) {
ae0f5499
BD		 2901 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2902 msr_info->index);
ed85c068
AP		 2903 return 1;
2904 } else {
fab0aa3b
EM		 2905 if (report_ignored_msrs)
2906 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2907 msr_info->index);
609e36d3 2908 msr_info->data = 0;
ed85c068
AP		 2909 }
2910 break;
15c4a640 2911 }
15c4a640
CO		 2912 return 0;
2913}
2914EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2915
313a3dc7
CO		 2916/*
2917 * Read or write a bunch of msrs. All parameters are kernel addresses.
2918 *
2919 * @return number of msrs set successfully.
2920 */
2921static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2922 struct kvm_msr_entry *entries,
2923 int (*do_msr)(struct kvm_vcpu *vcpu,
2924 unsigned index, u64 *data))
2925{
801e459a 2926 int i;
313a3dc7 2927
313a3dc7
CO		 2928 for (i = 0; i < msrs->nmsrs; ++i)
2929 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2930 break;
2931
313a3dc7
CO		 2932 return i;
2933}
2934
2935/*
2936 * Read or write a bunch of msrs. Parameters are user addresses.
2937 *
2938 * @return number of msrs set successfully.
2939 */
2940static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2941 int (*do_msr)(struct kvm_vcpu *vcpu,
2942 unsigned index, u64 *data),
2943 int writeback)
2944{
2945 struct kvm_msrs msrs;
2946 struct kvm_msr_entry *entries;
2947 int r, n;
2948 unsigned size;
2949
2950 r = -EFAULT;
0e96f31e 2951 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 2952 goto out;
2953
2954 r = -E2BIG;
2955 if (msrs.nmsrs >= MAX_IO_MSRS)
2956 goto out;
2957
313a3dc7 2958 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2959 entries = memdup_user(user_msrs->entries, size);
2960 if (IS_ERR(entries)) {
2961 r = PTR_ERR(entries);
313a3dc7 2962 goto out;
ff5c2c03 2963 }
313a3dc7
CO		 2964
2965 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2966 if (r < 0)
2967 goto out_free;
2968
2969 r = -EFAULT;
2970 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2971 goto out_free;
2972
2973 r = n;
2974
2975out_free:
7a73c028 2976 kfree(entries);
313a3dc7
CO		 2977out:
2978 return r;
2979}
2980
4d5422ce
WL		 2981static inline bool kvm_can_mwait_in_guest(void)
2982{
2983 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2984 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2985 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2986}
2987
784aa3d7 2988int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2989{
4d5422ce 2990 int r = 0;
018d00d2
ZX		 2991
2992 switch (ext) {
2993 case KVM_CAP_IRQCHIP:
2994 case KVM_CAP_HLT:
2995 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2996 case KVM_CAP_SET_TSS_ADDR:
07716717 2997 case KVM_CAP_EXT_CPUID:
9c15bb1d 2998 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2999 case KVM_CAP_CLOCKSOURCE:
7837699f 3000 case KVM_CAP_PIT:
a28e4f5a 3001 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3002 case KVM_CAP_MP_STATE:
ed848624 3003 case KVM_CAP_SYNC_MMU:
a355c85c 3004 case KVM_CAP_USER_NMI:
52d939a0 3005 case KVM_CAP_REINJECT_CONTROL:
4925663a 3006 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3007 case KVM_CAP_IOEVENTFD:
f848a5a8 3008 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3009 case KVM_CAP_PIT2:
e9f42757 3010 case KVM_CAP_PIT_STATE2:
b927a3ce 3011 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3012 case KVM_CAP_XEN_HVM:
3cfc3092 3013 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3014 case KVM_CAP_HYPERV:
10388a07 3015 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3016 case KVM_CAP_HYPERV_SPIN:
5c919412 3017 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3018 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3019 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3020 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3021 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3022 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 3023 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
2bc39970 3024 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3025 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3026 case KVM_CAP_DEBUGREGS:
d2be1651 3027 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3028 case KVM_CAP_XSAVE:
344d9588 3029 case KVM_CAP_ASYNC_PF:
92a1f12d 3030 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3031 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3032 case KVM_CAP_READONLY_MEM:
5f66b620 3033 case KVM_CAP_HYPERV_TIME:
100943c5 3034 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3035 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3036 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3037 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3038 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3039 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 3040 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3041 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3042 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3043 r = 1;
3044 break;
01643c51
KH		 3045 case KVM_CAP_SYNC_REGS:
3046 r = KVM_SYNC_X86_VALID_FIELDS;
3047 break;
e3fd9a93
PB		 3048 case KVM_CAP_ADJUST_CLOCK:
3049 r = KVM_CLOCK_TSC_STABLE;
3050 break;
4d5422ce 3051 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 3052 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 3053 if(kvm_can_mwait_in_guest())
3054 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3055 break;
6d396b55
PB		 3056 case KVM_CAP_X86_SMM:
3057 /* SMBASE is usually relocated above 1M on modern chipsets,
3058 * and SMM handlers might indeed rely on 4G segment limits,
3059 * so do not report SMM to be available if real mode is
3060 * emulated via vm86 mode. Still, do not go to great lengths
3061 * to avoid userspace's usage of the feature, because it is a
3062 * fringe case that is not enabled except via specific settings
3063 * of the module parameters.
3064 */
bc226f07 3065 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3066 break;
774ead3a
AK		 3067 case KVM_CAP_VAPIC:
3068 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3069 break;
f725230a 3070 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3071 r = KVM_SOFT_MAX_VCPUS;
3072 break;
3073 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3074 r = KVM_MAX_VCPUS;
3075 break;
a988b910 3076 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 3077 r = KVM_USER_MEM_SLOTS;
a988b910 3078 break;
a68a6a72
MT		 3079 case KVM_CAP_PV_MMU: /* obsolete */
3080 r = 0;
2f333bcb 3081 break;
890ca9ae
HY		 3082 case KVM_CAP_MCE:
3083 r = KVM_MAX_MCE_BANKS;
3084 break;
2d5b5a66 3085 case KVM_CAP_XCRS:
d366bf7e 3086 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3087 break;
92a1f12d
JR		 3088 case KVM_CAP_TSC_CONTROL:
3089 r = kvm_has_tsc_control;
3090 break;
37131313
RK		 3091 case KVM_CAP_X2APIC_API:
3092 r = KVM_X2APIC_API_VALID_FLAGS;
3093 break;
8fcc4b59
JM		 3094 case KVM_CAP_NESTED_STATE:
3095 r = kvm_x86_ops->get_nested_state ?
3096 kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
3097 break;
018d00d2 3098 default:
018d00d2
ZX		 3099 break;
3100 }
3101 return r;
3102
3103}
3104
043405e1
CO		 3105long kvm_arch_dev_ioctl(struct file *filp,
3106 unsigned int ioctl, unsigned long arg)
3107{
3108 void __user *argp = (void __user *)arg;
3109 long r;
3110
3111 switch (ioctl) {
3112 case KVM_GET_MSR_INDEX_LIST: {
3113 struct kvm_msr_list __user *user_msr_list = argp;
3114 struct kvm_msr_list msr_list;
3115 unsigned n;
3116
3117 r = -EFAULT;
0e96f31e 3118 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3119 goto out;
3120 n = msr_list.nmsrs;
62ef68bb 3121 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3122 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3123 goto out;
3124 r = -E2BIG;
e125e7b6 3125 if (n < msr_list.nmsrs)
043405e1
CO		 3126 goto out;
3127 r = -EFAULT;
3128 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3129 num_msrs_to_save * sizeof(u32)))
3130 goto out;
e125e7b6 3131 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3132 &emulated_msrs,
62ef68bb 3133 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3134 goto out;
3135 r = 0;
3136 break;
3137 }
9c15bb1d
BP		 3138 case KVM_GET_SUPPORTED_CPUID:
3139 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3140 struct kvm_cpuid2 __user *cpuid_arg = argp;
3141 struct kvm_cpuid2 cpuid;
3142
3143 r = -EFAULT;
0e96f31e 3144 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3145 goto out;
9c15bb1d
BP		 3146
3147 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3148 ioctl);
674eea0f
AK		 3149 if (r)
3150 goto out;
3151
3152 r = -EFAULT;
0e96f31e 3153 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3154 goto out;
3155 r = 0;
3156 break;
3157 }
890ca9ae 3158 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3159 r = -EFAULT;
c45dcc71
AR		 3160 if (copy_to_user(argp, &kvm_mce_cap_supported,
3161 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3162 goto out;
3163 r = 0;
3164 break;
801e459a
TL		 3165 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3166 struct kvm_msr_list __user *user_msr_list = argp;
3167 struct kvm_msr_list msr_list;
3168 unsigned int n;
3169
3170 r = -EFAULT;
3171 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3172 goto out;
3173 n = msr_list.nmsrs;
3174 msr_list.nmsrs = num_msr_based_features;
3175 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3176 goto out;
3177 r = -E2BIG;
3178 if (n < msr_list.nmsrs)
3179 goto out;
3180 r = -EFAULT;
3181 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3182 num_msr_based_features * sizeof(u32)))
3183 goto out;
3184 r = 0;
3185 break;
3186 }
3187 case KVM_GET_MSRS:
3188 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3189 break;
890ca9ae 3190 }
043405e1
CO		 3191 default:
3192 r = -EINVAL;
3193 }
3194out:
3195 return r;
3196}
3197
f5f48ee1
SY		 3198static void wbinvd_ipi(void *garbage)
3199{
3200 wbinvd();
3201}
3202
3203static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3204{
e0f0bbc5 3205 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3206}
3207
313a3dc7
CO		 3208void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3209{
f5f48ee1
SY		 3210 /* Address WBINVD may be executed by guest */
3211 if (need_emulate_wbinvd(vcpu)) {
3212 if (kvm_x86_ops->has_wbinvd_exit())
3213 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3214 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3215 smp_call_function_single(vcpu->cpu,
3216 wbinvd_ipi, NULL, 1);
3217 }
3218
313a3dc7 3219 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3220
0dd6a6ed
ZA		 3221 /* Apply any externally detected TSC adjustments (due to suspend) */
3222 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3223 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3224 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3225 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3226 }
8f6055cb 3227
b0c39dc6 3228 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3229 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3230 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3231 if (tsc_delta < 0)
3232 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3233
b0c39dc6 3234 if (kvm_check_tsc_unstable()) {
07c1419a 3235 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3236 vcpu->arch.last_guest_tsc);
a545ab6a 3237 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3238 vcpu->arch.tsc_catchup = 1;
c285545f 3239 }
a749e247
PB		 3240
3241 if (kvm_lapic_hv_timer_in_use(vcpu))
3242 kvm_lapic_restart_hv_timer(vcpu);
3243
d98d07ca
MT		 3244 /*
3245 * On a host with synchronized TSC, there is no need to update
3246 * kvmclock on vcpu->cpu migration
3247 */
3248 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3249 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3250 if (vcpu->cpu != cpu)
1bd2009e 3251 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3252 vcpu->cpu = cpu;
6b7d7e76 3253 }
c9aaa895 3254
c9aaa895 3255 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3256}
3257
0b9f6c46
PX		 3258static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3259{
3260 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3261 return;
3262
fa55eedd 3263 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3264
4e335d9e 3265 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3266 &vcpu->arch.st.steal.preempted,
3267 offsetof(struct kvm_steal_time, preempted),
3268 sizeof(vcpu->arch.st.steal.preempted));
3269}
3270
313a3dc7
CO		 3271void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3272{
cc0d907c 3273 int idx;
de63ad4c
LM		 3274
3275 if (vcpu->preempted)
3276 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3277
931f261b
AA		 3278 /*
3279 * Disable page faults because we're in atomic context here.
3280 * kvm_write_guest_offset_cached() would call might_fault()
3281 * that relies on pagefault_disable() to tell if there's a
3282 * bug. NOTE: the write to guest memory may not go through if
3283 * during postcopy live migration or if there's heavy guest
3284 * paging.
3285 */
3286 pagefault_disable();
cc0d907c
AA		 3287 /*
3288 * kvm_memslots() will be called by
3289 * kvm_write_guest_offset_cached() so take the srcu lock.
3290 */
3291 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3292 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3293 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3294 pagefault_enable();
02daab21 3295 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3296 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3297 /*
f9dcf08e
RK		 3298 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3299 * on every vmexit, but if not, we might have a stale dr6 from the
3300 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3301 */
f9dcf08e 3302 set_debugreg(0, 6);
313a3dc7
CO		 3303}
3304
313a3dc7
CO		 3305static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3306 struct kvm_lapic_state *s)
3307{
fa59cc00 3308 if (vcpu->arch.apicv_active)
d62caabb
AS		 3309 kvm_x86_ops->sync_pir_to_irr(vcpu);
3310
a92e2543 3311 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3312}
3313
3314static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3315 struct kvm_lapic_state *s)
3316{
a92e2543
RK		 3317 int r;
3318
3319 r = kvm_apic_set_state(vcpu, s);
3320 if (r)
3321 return r;
cb142eb7 3322 update_cr8_intercept(vcpu);
313a3dc7
CO		 3323
3324 return 0;
3325}
3326
127a457a
MG		 3327static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3328{
3329 return (!lapic_in_kernel(vcpu) ||
3330 kvm_apic_accept_pic_intr(vcpu));
3331}
3332
782d422b
MG		 3333/*
3334 * if userspace requested an interrupt window, check that the
3335 * interrupt window is open.
3336 *
3337 * No need to exit to userspace if we already have an interrupt queued.
3338 */
3339static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3340{
3341 return kvm_arch_interrupt_allowed(vcpu) &&
3342 !kvm_cpu_has_interrupt(vcpu) &&
3343 !kvm_event_needs_reinjection(vcpu) &&
3344 kvm_cpu_accept_dm_intr(vcpu);
3345}
3346
f77bc6a4
ZX		 3347static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3348 struct kvm_interrupt *irq)
3349{
02cdb50f 3350 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3351 return -EINVAL;
1c1a9ce9
SR		 3352
3353 if (!irqchip_in_kernel(vcpu->kvm)) {
3354 kvm_queue_interrupt(vcpu, irq->irq, false);
3355 kvm_make_request(KVM_REQ_EVENT, vcpu);
3356 return 0;
3357 }
3358
3359 /*
3360 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3361 * fail for in-kernel 8259.
3362 */
3363 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3364 return -ENXIO;
f77bc6a4 3365
1c1a9ce9
SR		 3366 if (vcpu->arch.pending_external_vector != -1)
3367 return -EEXIST;
f77bc6a4 3368
1c1a9ce9 3369 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3370 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3371 return 0;
3372}
3373
c4abb7c9
JK		 3374static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3375{
c4abb7c9 3376 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3377
3378 return 0;
3379}
3380
f077825a
PB		 3381static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3382{
64d60670
PB		 3383 kvm_make_request(KVM_REQ_SMI, vcpu);
3384
f077825a
PB		 3385 return 0;
3386}
3387
b209749f
AK		 3388static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3389 struct kvm_tpr_access_ctl *tac)
3390{
3391 if (tac->flags)
3392 return -EINVAL;
3393 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3394 return 0;
3395}
3396
890ca9ae
HY		 3397static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3398 u64 mcg_cap)
3399{
3400 int r;
3401 unsigned bank_num = mcg_cap & 0xff, bank;
3402
3403 r = -EINVAL;
a9e38c3e 3404 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3405 goto out;
c45dcc71 3406 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3407 goto out;
3408 r = 0;
3409 vcpu->arch.mcg_cap = mcg_cap;
3410 /* Init IA32_MCG_CTL to all 1s */
3411 if (mcg_cap & MCG_CTL_P)
3412 vcpu->arch.mcg_ctl = ~(u64)0;
3413 /* Init IA32_MCi_CTL to all 1s */
3414 for (bank = 0; bank < bank_num; bank++)
3415 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3416
3417 if (kvm_x86_ops->setup_mce)
3418 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3419out:
3420 return r;
3421}
3422
3423static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3424 struct kvm_x86_mce *mce)
3425{
3426 u64 mcg_cap = vcpu->arch.mcg_cap;
3427 unsigned bank_num = mcg_cap & 0xff;
3428 u64 *banks = vcpu->arch.mce_banks;
3429
3430 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3431 return -EINVAL;
3432 /*
3433 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3434 * reporting is disabled
3435 */
3436 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3437 vcpu->arch.mcg_ctl != ~(u64)0)
3438 return 0;
3439 banks += 4 * mce->bank;
3440 /*
3441 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3442 * reporting is disabled for the bank
3443 */
3444 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3445 return 0;
3446 if (mce->status & MCI_STATUS_UC) {
3447 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3448 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3449 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3450 return 0;
3451 }
3452 if (banks[1] & MCI_STATUS_VAL)
3453 mce->status |= MCI_STATUS_OVER;
3454 banks[2] = mce->addr;
3455 banks[3] = mce->misc;
3456 vcpu->arch.mcg_status = mce->mcg_status;
3457 banks[1] = mce->status;
3458 kvm_queue_exception(vcpu, MC_VECTOR);
3459 } else if (!(banks[1] & MCI_STATUS_VAL)
3460 || !(banks[1] & MCI_STATUS_UC)) {
3461 if (banks[1] & MCI_STATUS_VAL)
3462 mce->status |= MCI_STATUS_OVER;
3463 banks[2] = mce->addr;
3464 banks[3] = mce->misc;
3465 banks[1] = mce->status;
3466 } else
3467 banks[1] |= MCI_STATUS_OVER;
3468 return 0;
3469}
3470
3cfc3092
JK		 3471static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3472 struct kvm_vcpu_events *events)
3473{
7460fb4a 3474 process_nmi(vcpu);
59073aaf 3475
664f8e26 3476 /*
59073aaf
JM		 3477 * The API doesn't provide the instruction length for software
3478 * exceptions, so don't report them. As long as the guest RIP
3479 * isn't advanced, we should expect to encounter the exception
3480 * again.
664f8e26 3481 */
59073aaf
JM		 3482 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3483 events->exception.injected = 0;
3484 events->exception.pending = 0;
3485 } else {
3486 events->exception.injected = vcpu->arch.exception.injected;
3487 events->exception.pending = vcpu->arch.exception.pending;
3488 /*
3489 * For ABI compatibility, deliberately conflate
3490 * pending and injected exceptions when
3491 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3492 */
3493 if (!vcpu->kvm->arch.exception_payload_enabled)
3494 events->exception.injected |=
3495 vcpu->arch.exception.pending;
3496 }
3cfc3092
JK		 3497 events->exception.nr = vcpu->arch.exception.nr;
3498 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3499 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3500 events->exception_has_payload = vcpu->arch.exception.has_payload;
3501 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3502
03b82a30 3503 events->interrupt.injected =
04140b41 3504 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3505 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3506 events->interrupt.soft = 0;
37ccdcbe 3507 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3508
3509 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3510 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3511 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3512 events->nmi.pad = 0;
3cfc3092 3513
66450a21 3514 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3515
f077825a
PB		 3516 events->smi.smm = is_smm(vcpu);
3517 events->smi.pending = vcpu->arch.smi_pending;
3518 events->smi.smm_inside_nmi =
3519 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3520 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3521
dab4b911 3522 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3523 | KVM_VCPUEVENT_VALID_SHADOW
3524 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3525 if (vcpu->kvm->arch.exception_payload_enabled)
3526 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3527
97e69aa6 3528 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3529}
3530
6ef4e07e
XG		 3531static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3532
3cfc3092
JK		 3533static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3534 struct kvm_vcpu_events *events)
3535{
dab4b911 3536 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3537 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3538 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3539 | KVM_VCPUEVENT_VALID_SMM
3540 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3541 return -EINVAL;
3542
59073aaf
JM		 3543 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3544 if (!vcpu->kvm->arch.exception_payload_enabled)
3545 return -EINVAL;
3546 if (events->exception.pending)
3547 events->exception.injected = 0;
3548 else
3549 events->exception_has_payload = 0;
3550 } else {
3551 events->exception.pending = 0;
3552 events->exception_has_payload = 0;
3553 }
3554
3555 if ((events->exception.injected || events->exception.pending) &&
3556 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3557 return -EINVAL;
3558
28bf2888
DH		 3559 /* INITs are latched while in SMM */
3560 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3561 (events->smi.smm || events->smi.pending) &&
3562 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3563 return -EINVAL;
3564
7460fb4a 3565 process_nmi(vcpu);
59073aaf
JM		 3566 vcpu->arch.exception.injected = events->exception.injected;
3567 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3568 vcpu->arch.exception.nr = events->exception.nr;
3569 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3570 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3571 vcpu->arch.exception.has_payload = events->exception_has_payload;
3572 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3573
04140b41 3574 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3575 vcpu->arch.interrupt.nr = events->interrupt.nr;
3576 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3577 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3578 kvm_x86_ops->set_interrupt_shadow(vcpu,
3579 events->interrupt.shadow);
3cfc3092
JK		 3580
3581 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3582 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3583 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3584 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3585
66450a21 3586 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3587 lapic_in_kernel(vcpu))
66450a21 3588 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3589
f077825a 3590 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3591 u32 hflags = vcpu->arch.hflags;
f077825a 3592 if (events->smi.smm)
6ef4e07e 3593 hflags |= HF_SMM_MASK;
f077825a 3594 else
6ef4e07e
XG		 3595 hflags &= ~HF_SMM_MASK;
3596 kvm_set_hflags(vcpu, hflags);
3597
f077825a 3598 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3599
3600 if (events->smi.smm) {
3601 if (events->smi.smm_inside_nmi)
3602 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3603 else
f4ef1910
WL		 3604 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3605 if (lapic_in_kernel(vcpu)) {
3606 if (events->smi.latched_init)
3607 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3608 else
3609 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3610 }
f077825a
PB		 3611 }
3612 }
3613
3842d135
AK		 3614 kvm_make_request(KVM_REQ_EVENT, vcpu);
3615
3cfc3092
JK		 3616 return 0;
3617}
3618
a1efbe77
JK		 3619static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3620 struct kvm_debugregs *dbgregs)
3621{
73aaf249
JK		 3622 unsigned long val;
3623
a1efbe77 3624 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3625 kvm_get_dr(vcpu, 6, &val);
73aaf249 3626 dbgregs->dr6 = val;
a1efbe77
JK		 3627 dbgregs->dr7 = vcpu->arch.dr7;
3628 dbgregs->flags = 0;
97e69aa6 3629 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3630}
3631
3632static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3633 struct kvm_debugregs *dbgregs)
3634{
3635 if (dbgregs->flags)
3636 return -EINVAL;
3637
d14bdb55
PB		 3638 if (dbgregs->dr6 & ~0xffffffffull)
3639 return -EINVAL;
3640 if (dbgregs->dr7 & ~0xffffffffull)
3641 return -EINVAL;
3642
a1efbe77 3643 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3644 kvm_update_dr0123(vcpu);
a1efbe77 3645 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3646 kvm_update_dr6(vcpu);
a1efbe77 3647 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3648 kvm_update_dr7(vcpu);
a1efbe77 3649
a1efbe77
JK		 3650 return 0;
3651}
3652
df1daba7
PB		 3653#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3654
3655static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3656{
b666a4b6 3657 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3658 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3659 u64 valid;
3660
3661 /*
3662 * Copy legacy XSAVE area, to avoid complications with CPUID
3663 * leaves 0 and 1 in the loop below.
3664 */
3665 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3666
3667 /* Set XSTATE_BV */
00c87e9a 3668 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3669 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3670
3671 /*
3672 * Copy each region from the possibly compacted offset to the
3673 * non-compacted offset.
3674 */
d91cab78 3675 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3676 while (valid) {
3677 u64 feature = valid & -valid;
3678 int index = fls64(feature) - 1;
3679 void *src = get_xsave_addr(xsave, feature);
3680
3681 if (src) {
3682 u32 size, offset, ecx, edx;
3683 cpuid_count(XSTATE_CPUID, index,
3684 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3685 if (feature == XFEATURE_MASK_PKRU)
3686 memcpy(dest + offset, &vcpu->arch.pkru,
3687 sizeof(vcpu->arch.pkru));
3688 else
3689 memcpy(dest + offset, src, size);
3690
df1daba7
PB		 3691 }
3692
3693 valid -= feature;
3694 }
3695}
3696
3697static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3698{
b666a4b6 3699 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3700 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3701 u64 valid;
3702
3703 /*
3704 * Copy legacy XSAVE area, to avoid complications with CPUID
3705 * leaves 0 and 1 in the loop below.
3706 */
3707 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3708
3709 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3710 xsave->header.xfeatures = xstate_bv;
782511b0 3711 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3712 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3713
3714 /*
3715 * Copy each region from the non-compacted offset to the
3716 * possibly compacted offset.
3717 */
d91cab78 3718 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3719 while (valid) {
3720 u64 feature = valid & -valid;
3721 int index = fls64(feature) - 1;
3722 void *dest = get_xsave_addr(xsave, feature);
3723
3724 if (dest) {
3725 u32 size, offset, ecx, edx;
3726 cpuid_count(XSTATE_CPUID, index,
3727 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3728 if (feature == XFEATURE_MASK_PKRU)
3729 memcpy(&vcpu->arch.pkru, src + offset,
3730 sizeof(vcpu->arch.pkru));
3731 else
3732 memcpy(dest, src + offset, size);
ee4100da 3733 }
df1daba7
PB		 3734
3735 valid -= feature;
3736 }
3737}
3738
2d5b5a66
SY		 3739static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3740 struct kvm_xsave *guest_xsave)
3741{
d366bf7e 3742 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3743 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3744 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3745 } else {
2d5b5a66 3746 memcpy(guest_xsave->region,
b666a4b6 3747 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3748 sizeof(struct fxregs_state));
2d5b5a66 3749 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3750 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3751 }
3752}
3753
a575813b
WL		 3754#define XSAVE_MXCSR_OFFSET 24
3755
2d5b5a66
SY		 3756static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3757 struct kvm_xsave *guest_xsave)
3758{
3759 u64 xstate_bv =
3760 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3761 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3762
d366bf7e 3763 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3764 /*
3765 * Here we allow setting states that are not present in
3766 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3767 * with old userspace.
3768 */
a575813b
WL		 3769 if (xstate_bv & ~kvm_supported_xcr0() ||
3770 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3771 return -EINVAL;
df1daba7 3772 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3773 } else {
a575813b
WL		 3774 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3775 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3776 return -EINVAL;
b666a4b6 3777 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3778 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3779 }
3780 return 0;
3781}
3782
3783static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3784 struct kvm_xcrs *guest_xcrs)
3785{
d366bf7e 3786 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3787 guest_xcrs->nr_xcrs = 0;
3788 return;
3789 }
3790
3791 guest_xcrs->nr_xcrs = 1;
3792 guest_xcrs->flags = 0;
3793 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3794 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3795}
3796
3797static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3798 struct kvm_xcrs *guest_xcrs)
3799{
3800 int i, r = 0;
3801
d366bf7e 3802 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3803 return -EINVAL;
3804
3805 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3806 return -EINVAL;
3807
3808 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3809 /* Only support XCR0 currently */
c67a04cb 3810 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3811 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3812 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3813 break;
3814 }
3815 if (r)
3816 r = -EINVAL;
3817 return r;
3818}
3819
1c0b28c2
EM		 3820/*
3821 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3822 * stopped by the hypervisor. This function will be called from the host only.
3823 * EINVAL is returned when the host attempts to set the flag for a guest that
3824 * does not support pv clocks.
3825 */
3826static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3827{
0b79459b 3828 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3829 return -EINVAL;
51d59c6b 3830 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3831 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3832 return 0;
3833}
3834
5c919412
AS		 3835static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3836 struct kvm_enable_cap *cap)
3837{
57b119da
VK		 3838 int r;
3839 uint16_t vmcs_version;
3840 void __user *user_ptr;
3841
5c919412
AS		 3842 if (cap->flags)
3843 return -EINVAL;
3844
3845 switch (cap->cap) {
efc479e6
RK		 3846 case KVM_CAP_HYPERV_SYNIC2:
3847 if (cap->args[0])
3848 return -EINVAL;
b2869f28
GS		 3849 /* fall through */
3850
5c919412 3851 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3852 if (!irqchip_in_kernel(vcpu->kvm))
3853 return -EINVAL;
efc479e6
RK		 3854 return kvm_hv_activate_synic(vcpu, cap->cap ==
3855 KVM_CAP_HYPERV_SYNIC2);
57b119da 3856 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 3857 if (!kvm_x86_ops->nested_enable_evmcs)
3858 return -ENOTTY;
57b119da
VK		 3859 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3860 if (!r) {
3861 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3862 if (copy_to_user(user_ptr, &vmcs_version,
3863 sizeof(vmcs_version)))
3864 r = -EFAULT;
3865 }
3866 return r;
3867
5c919412
AS		 3868 default:
3869 return -EINVAL;
3870 }
3871}
3872
313a3dc7
CO		 3873long kvm_arch_vcpu_ioctl(struct file *filp,
3874 unsigned int ioctl, unsigned long arg)
3875{
3876 struct kvm_vcpu *vcpu = filp->private_data;
3877 void __user *argp = (void __user *)arg;
3878 int r;
d1ac91d8
AK		 3879 union {
3880 struct kvm_lapic_state *lapic;
3881 struct kvm_xsave *xsave;
3882 struct kvm_xcrs *xcrs;
3883 void *buffer;
3884 } u;
3885
9b062471
CD		 3886 vcpu_load(vcpu);
3887
d1ac91d8 3888 u.buffer = NULL;
313a3dc7
CO		 3889 switch (ioctl) {
3890 case KVM_GET_LAPIC: {
2204ae3c 3891 r = -EINVAL;
bce87cce 3892 if (!lapic_in_kernel(vcpu))
2204ae3c 3893 goto out;
254272ce
BG		 3894 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3895 GFP_KERNEL_ACCOUNT);
313a3dc7 3896
b772ff36 3897 r = -ENOMEM;
d1ac91d8 3898 if (!u.lapic)
b772ff36 3899 goto out;
d1ac91d8 3900 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3901 if (r)
3902 goto out;
3903 r = -EFAULT;
d1ac91d8 3904 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3905 goto out;
3906 r = 0;
3907 break;
3908 }
3909 case KVM_SET_LAPIC: {
2204ae3c 3910 r = -EINVAL;
bce87cce 3911 if (!lapic_in_kernel(vcpu))
2204ae3c 3912 goto out;
ff5c2c03 3913 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3914 if (IS_ERR(u.lapic)) {
3915 r = PTR_ERR(u.lapic);
3916 goto out_nofree;
3917 }
ff5c2c03 3918
d1ac91d8 3919 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3920 break;
3921 }
f77bc6a4
ZX		 3922 case KVM_INTERRUPT: {
3923 struct kvm_interrupt irq;
3924
3925 r = -EFAULT;
0e96f31e 3926 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 3927 goto out;
3928 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3929 break;
3930 }
c4abb7c9
JK		 3931 case KVM_NMI: {
3932 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3933 break;
3934 }
f077825a
PB		 3935 case KVM_SMI: {
3936 r = kvm_vcpu_ioctl_smi(vcpu);
3937 break;
3938 }
313a3dc7
CO		 3939 case KVM_SET_CPUID: {
3940 struct kvm_cpuid __user *cpuid_arg = argp;
3941 struct kvm_cpuid cpuid;
3942
3943 r = -EFAULT;
0e96f31e 3944 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 3945 goto out;
3946 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3947 break;
3948 }
07716717
DK		 3949 case KVM_SET_CPUID2: {
3950 struct kvm_cpuid2 __user *cpuid_arg = argp;
3951 struct kvm_cpuid2 cpuid;
3952
3953 r = -EFAULT;
0e96f31e 3954 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 3955 goto out;
3956 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3957 cpuid_arg->entries);
07716717
DK		 3958 break;
3959 }
3960 case KVM_GET_CPUID2: {
3961 struct kvm_cpuid2 __user *cpuid_arg = argp;
3962 struct kvm_cpuid2 cpuid;
3963
3964 r = -EFAULT;
0e96f31e 3965 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 3966 goto out;
3967 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3968 cpuid_arg->entries);
07716717
DK		 3969 if (r)
3970 goto out;
3971 r = -EFAULT;
0e96f31e 3972 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 3973 goto out;
3974 r = 0;
3975 break;
3976 }
801e459a
TL		 3977 case KVM_GET_MSRS: {
3978 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3979 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3980 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3981 break;
801e459a
TL		 3982 }
3983 case KVM_SET_MSRS: {
3984 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3985 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3986 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3987 break;
801e459a 3988 }
b209749f
AK		 3989 case KVM_TPR_ACCESS_REPORTING: {
3990 struct kvm_tpr_access_ctl tac;
3991
3992 r = -EFAULT;
0e96f31e 3993 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 3994 goto out;
3995 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3996 if (r)
3997 goto out;
3998 r = -EFAULT;
0e96f31e 3999 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4000 goto out;
4001 r = 0;
4002 break;
4003 };
b93463aa
AK		 4004 case KVM_SET_VAPIC_ADDR: {
4005 struct kvm_vapic_addr va;
7301d6ab 4006 int idx;
b93463aa
AK		 4007
4008 r = -EINVAL;
35754c98 4009 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4010 goto out;
4011 r = -EFAULT;
0e96f31e 4012 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4013 goto out;
7301d6ab 4014 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4015 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4016 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4017 break;
4018 }
890ca9ae
HY		 4019 case KVM_X86_SETUP_MCE: {
4020 u64 mcg_cap;
4021
4022 r = -EFAULT;
0e96f31e 4023 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4024 goto out;
4025 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4026 break;
4027 }
4028 case KVM_X86_SET_MCE: {
4029 struct kvm_x86_mce mce;
4030
4031 r = -EFAULT;
0e96f31e 4032 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4033 goto out;
4034 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4035 break;
4036 }
3cfc3092
JK		 4037 case KVM_GET_VCPU_EVENTS: {
4038 struct kvm_vcpu_events events;
4039
4040 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4041
4042 r = -EFAULT;
4043 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4044 break;
4045 r = 0;
4046 break;
4047 }
4048 case KVM_SET_VCPU_EVENTS: {
4049 struct kvm_vcpu_events events;
4050
4051 r = -EFAULT;
4052 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4053 break;
4054
4055 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4056 break;
4057 }
a1efbe77
JK		 4058 case KVM_GET_DEBUGREGS: {
4059 struct kvm_debugregs dbgregs;
4060
4061 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4062
4063 r = -EFAULT;
4064 if (copy_to_user(argp, &dbgregs,
4065 sizeof(struct kvm_debugregs)))
4066 break;
4067 r = 0;
4068 break;
4069 }
4070 case KVM_SET_DEBUGREGS: {
4071 struct kvm_debugregs dbgregs;
4072
4073 r = -EFAULT;
4074 if (copy_from_user(&dbgregs, argp,
4075 sizeof(struct kvm_debugregs)))
4076 break;
4077
4078 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4079 break;
4080 }
2d5b5a66 4081 case KVM_GET_XSAVE: {
254272ce 4082 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4083 r = -ENOMEM;
d1ac91d8 4084 if (!u.xsave)
2d5b5a66
SY		 4085 break;
4086
d1ac91d8 4087 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4088
4089 r = -EFAULT;
d1ac91d8 4090 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4091 break;
4092 r = 0;
4093 break;
4094 }
4095 case KVM_SET_XSAVE: {
ff5c2c03 4096 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4097 if (IS_ERR(u.xsave)) {
4098 r = PTR_ERR(u.xsave);
4099 goto out_nofree;
4100 }
2d5b5a66 4101
d1ac91d8 4102 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4103 break;
4104 }
4105 case KVM_GET_XCRS: {
254272ce 4106 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4107 r = -ENOMEM;
d1ac91d8 4108 if (!u.xcrs)
2d5b5a66
SY		 4109 break;
4110
d1ac91d8 4111 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4112
4113 r = -EFAULT;
d1ac91d8 4114 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4115 sizeof(struct kvm_xcrs)))
4116 break;
4117 r = 0;
4118 break;
4119 }
4120 case KVM_SET_XCRS: {
ff5c2c03 4121 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4122 if (IS_ERR(u.xcrs)) {
4123 r = PTR_ERR(u.xcrs);
4124 goto out_nofree;
4125 }
2d5b5a66 4126
d1ac91d8 4127 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4128 break;
4129 }
92a1f12d
JR		 4130 case KVM_SET_TSC_KHZ: {
4131 u32 user_tsc_khz;
4132
4133 r = -EINVAL;
92a1f12d
JR		 4134 user_tsc_khz = (u32)arg;
4135
4136 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4137 goto out;
4138
cc578287
ZA		 4139 if (user_tsc_khz == 0)
4140 user_tsc_khz = tsc_khz;
4141
381d585c
HZ		 4142 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4143 r = 0;
92a1f12d 4144
92a1f12d
JR		 4145 goto out;
4146 }
4147 case KVM_GET_TSC_KHZ: {
cc578287 4148 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4149 goto out;
4150 }
1c0b28c2
EM		 4151 case KVM_KVMCLOCK_CTRL: {
4152 r = kvm_set_guest_paused(vcpu);
4153 goto out;
4154 }
5c919412
AS		 4155 case KVM_ENABLE_CAP: {
4156 struct kvm_enable_cap cap;
4157
4158 r = -EFAULT;
4159 if (copy_from_user(&cap, argp, sizeof(cap)))
4160 goto out;
4161 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4162 break;
4163 }
8fcc4b59
JM		 4164 case KVM_GET_NESTED_STATE: {
4165 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4166 u32 user_data_size;
4167
4168 r = -EINVAL;
4169 if (!kvm_x86_ops->get_nested_state)
4170 break;
4171
4172 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4173 r = -EFAULT;
8fcc4b59 4174 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4175 break;
8fcc4b59
JM		 4176
4177 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4178 user_data_size);
4179 if (r < 0)
26b471c7 4180 break;
8fcc4b59
JM		 4181
4182 if (r > user_data_size) {
4183 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4184 r = -EFAULT;
4185 else
4186 r = -E2BIG;
4187 break;
8fcc4b59 4188 }
26b471c7 4189
8fcc4b59
JM		 4190 r = 0;
4191 break;
4192 }
4193 case KVM_SET_NESTED_STATE: {
4194 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4195 struct kvm_nested_state kvm_state;
4196
4197 r = -EINVAL;
4198 if (!kvm_x86_ops->set_nested_state)
4199 break;
4200
26b471c7 4201 r = -EFAULT;
8fcc4b59 4202 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4203 break;
8fcc4b59 4204
26b471c7 4205 r = -EINVAL;
8fcc4b59 4206 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4207 break;
8fcc4b59
JM		 4208
4209 if (kvm_state.flags &
8cab6507
VK		 4210 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4211 | KVM_STATE_NESTED_EVMCS))
26b471c7 4212 break;
8fcc4b59
JM		 4213
4214 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4215 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4216 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4217 break;
8fcc4b59
JM		 4218
4219 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4220 break;
4221 }
2bc39970
VK		 4222 case KVM_GET_SUPPORTED_HV_CPUID: {
4223 struct kvm_cpuid2 __user *cpuid_arg = argp;
4224 struct kvm_cpuid2 cpuid;
4225
4226 r = -EFAULT;
4227 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4228 goto out;
4229
4230 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4231 cpuid_arg->entries);
4232 if (r)
4233 goto out;
4234
4235 r = -EFAULT;
4236 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4237 goto out;
4238 r = 0;
4239 break;
4240 }
313a3dc7
CO		 4241 default:
4242 r = -EINVAL;
4243 }
4244out:
d1ac91d8 4245 kfree(u.buffer);
9b062471
CD		 4246out_nofree:
4247 vcpu_put(vcpu);
313a3dc7
CO		 4248 return r;
4249}
4250
1499fa80 4251vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4252{
4253 return VM_FAULT_SIGBUS;
4254}
4255
1fe779f8
CO		 4256static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4257{
4258 int ret;
4259
4260 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4261 return -EINVAL;
1fe779f8
CO		 4262 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4263 return ret;
4264}
4265
b927a3ce
SY		 4266static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4267 u64 ident_addr)
4268{
2ac52ab8 4269 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4270}
4271
1fe779f8
CO		 4272static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4273 u32 kvm_nr_mmu_pages)
4274{
4275 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4276 return -EINVAL;
4277
79fac95e 4278 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4279
4280 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4281 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4282
79fac95e 4283 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4284 return 0;
4285}
4286
4287static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4288{
39de71ec 4289 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4290}
4291
1fe779f8
CO		 4292static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4293{
90bca052 4294 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4295 int r;
4296
4297 r = 0;
4298 switch (chip->chip_id) {
4299 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4300 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4301 sizeof(struct kvm_pic_state));
4302 break;
4303 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4304 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4305 sizeof(struct kvm_pic_state));
4306 break;
4307 case KVM_IRQCHIP_IOAPIC:
33392b49 4308 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4309 break;
4310 default:
4311 r = -EINVAL;
4312 break;
4313 }
4314 return r;
4315}
4316
4317static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4318{
90bca052 4319 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4320 int r;
4321
4322 r = 0;
4323 switch (chip->chip_id) {
4324 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4325 spin_lock(&pic->lock);
4326 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4327 sizeof(struct kvm_pic_state));
90bca052 4328 spin_unlock(&pic->lock);
1fe779f8
CO		 4329 break;
4330 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4331 spin_lock(&pic->lock);
4332 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4333 sizeof(struct kvm_pic_state));
90bca052 4334 spin_unlock(&pic->lock);
1fe779f8
CO		 4335 break;
4336 case KVM_IRQCHIP_IOAPIC:
33392b49 4337 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4338 break;
4339 default:
4340 r = -EINVAL;
4341 break;
4342 }
90bca052 4343 kvm_pic_update_irq(pic);
1fe779f8
CO		 4344 return r;
4345}
4346
e0f63cb9
SY		 4347static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4348{
34f3941c
RK		 4349 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4350
4351 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4352
4353 mutex_lock(&kps->lock);
4354 memcpy(ps, &kps->channels, sizeof(*ps));
4355 mutex_unlock(&kps->lock);
2da29bcc 4356 return 0;
e0f63cb9
SY		 4357}
4358
4359static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4360{
0185604c 4361 int i;
09edea72
RK		 4362 struct kvm_pit *pit = kvm->arch.vpit;
4363
4364 mutex_lock(&pit->pit_state.lock);
34f3941c 4365 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4366 for (i = 0; i < 3; i++)
09edea72
RK		 4367 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4368 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4369 return 0;
e9f42757
BK		 4370}
4371
4372static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4373{
e9f42757
BK		 4374 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4375 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4376 sizeof(ps->channels));
4377 ps->flags = kvm->arch.vpit->pit_state.flags;
4378 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4379 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4380 return 0;
e9f42757
BK		 4381}
4382
4383static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4384{
2da29bcc 4385 int start = 0;
0185604c 4386 int i;
e9f42757 4387 u32 prev_legacy, cur_legacy;
09edea72
RK		 4388 struct kvm_pit *pit = kvm->arch.vpit;
4389
4390 mutex_lock(&pit->pit_state.lock);
4391 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4392 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4393 if (!prev_legacy && cur_legacy)
4394 start = 1;
09edea72
RK		 4395 memcpy(&pit->pit_state.channels, &ps->channels,
4396 sizeof(pit->pit_state.channels));
4397 pit->pit_state.flags = ps->flags;
0185604c 4398 for (i = 0; i < 3; i++)
09edea72 4399 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4400 start && i == 0);
09edea72 4401 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4402 return 0;
e0f63cb9
SY		 4403}
4404
52d939a0
MT		 4405static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4406 struct kvm_reinject_control *control)
4407{
71474e2f
RK		 4408 struct kvm_pit *pit = kvm->arch.vpit;
4409
4410 if (!pit)
52d939a0 4411 return -ENXIO;
b39c90b6 4412
71474e2f
RK		 4413 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4414 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4415 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4416 */
4417 mutex_lock(&pit->pit_state.lock);
4418 kvm_pit_set_reinject(pit, control->pit_reinject);
4419 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4420
52d939a0
MT		 4421 return 0;
4422}
4423
95d4c16c 4424/**
60c34612
TY		 4425 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4426 * @kvm: kvm instance
4427 * @log: slot id and address to which we copy the log
95d4c16c 4428 *
e108ff2f
PB		 4429 * Steps 1-4 below provide general overview of dirty page logging. See
4430 * kvm_get_dirty_log_protect() function description for additional details.
4431 *
4432 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4433 * always flush the TLB (step 4) even if previous step failed and the dirty
4434 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4435 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4436 * writes will be marked dirty for next log read.
95d4c16c 4437 *
60c34612
TY		 4438 * 1. Take a snapshot of the bit and clear it if needed.
4439 * 2. Write protect the corresponding page.
e108ff2f
PB		 4440 * 3. Copy the snapshot to the userspace.
4441 * 4. Flush TLB's if needed.
5bb064dc 4442 */
60c34612 4443int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4444{
8fe65a82 4445 bool flush = false;
e108ff2f 4446 int r;
5bb064dc 4447
79fac95e 4448 mutex_lock(&kvm->slots_lock);
5bb064dc 4449
88178fd4
KH		 4450 /*
4451 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4452 */
4453 if (kvm_x86_ops->flush_log_dirty)
4454 kvm_x86_ops->flush_log_dirty(kvm);
4455
8fe65a82 4456 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4457
4458 /*
4459 * All the TLBs can be flushed out of mmu lock, see the comments in
4460 * kvm_mmu_slot_remove_write_access().
4461 */
e108ff2f 4462 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4463 if (flush)
2a31b9db
PB		 4464 kvm_flush_remote_tlbs(kvm);
4465
4466 mutex_unlock(&kvm->slots_lock);
4467 return r;
4468}
4469
4470int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4471{
4472 bool flush = false;
4473 int r;
4474
4475 mutex_lock(&kvm->slots_lock);
4476
4477 /*
4478 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4479 */
4480 if (kvm_x86_ops->flush_log_dirty)
4481 kvm_x86_ops->flush_log_dirty(kvm);
4482
4483 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4484
4485 /*
4486 * All the TLBs can be flushed out of mmu lock, see the comments in
4487 * kvm_mmu_slot_remove_write_access().
4488 */
4489 lockdep_assert_held(&kvm->slots_lock);
4490 if (flush)
198c74f4
XG		 4491 kvm_flush_remote_tlbs(kvm);
4492
79fac95e 4493 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4494 return r;
4495}
4496
aa2fbe6d
YZ		 4497int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4498 bool line_status)
23d43cf9
CD		 4499{
4500 if (!irqchip_in_kernel(kvm))
4501 return -ENXIO;
4502
4503 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4504 irq_event->irq, irq_event->level,
4505 line_status);
23d43cf9
CD		 4506 return 0;
4507}
4508
e5d83c74
PB		 4509int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4510 struct kvm_enable_cap *cap)
90de4a18
NA		 4511{
4512 int r;
4513
4514 if (cap->flags)
4515 return -EINVAL;
4516
4517 switch (cap->cap) {
4518 case KVM_CAP_DISABLE_QUIRKS:
4519 kvm->arch.disabled_quirks = cap->args[0];
4520 r = 0;
4521 break;
49df6397
SR		 4522 case KVM_CAP_SPLIT_IRQCHIP: {
4523 mutex_lock(&kvm->lock);
b053b2ae
SR		 4524 r = -EINVAL;
4525 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4526 goto split_irqchip_unlock;
49df6397
SR		 4527 r = -EEXIST;
4528 if (irqchip_in_kernel(kvm))
4529 goto split_irqchip_unlock;
557abc40 4530 if (kvm->created_vcpus)
49df6397
SR		 4531 goto split_irqchip_unlock;
4532 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4533 if (r)
49df6397
SR		 4534 goto split_irqchip_unlock;
4535 /* Pairs with irqchip_in_kernel. */
4536 smp_wmb();
49776faf 4537 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4538 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4539 r = 0;
4540split_irqchip_unlock:
4541 mutex_unlock(&kvm->lock);
4542 break;
4543 }
37131313
RK		 4544 case KVM_CAP_X2APIC_API:
4545 r = -EINVAL;
4546 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4547 break;
4548
4549 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4550 kvm->arch.x2apic_format = true;
c519265f
RK		 4551 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4552 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4553
4554 r = 0;
4555 break;
4d5422ce
WL		 4556 case KVM_CAP_X86_DISABLE_EXITS:
4557 r = -EINVAL;
4558 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4559 break;
4560
4561 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4562 kvm_can_mwait_in_guest())
4563 kvm->arch.mwait_in_guest = true;
766d3571 4564 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4565 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4566 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4567 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4568 r = 0;
4569 break;
6fbbde9a
DS		 4570 case KVM_CAP_MSR_PLATFORM_INFO:
4571 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4572 r = 0;
c4f55198
JM		 4573 break;
4574 case KVM_CAP_EXCEPTION_PAYLOAD:
4575 kvm->arch.exception_payload_enabled = cap->args[0];
4576 r = 0;
6fbbde9a 4577 break;
90de4a18
NA		 4578 default:
4579 r = -EINVAL;
4580 break;
4581 }
4582 return r;
4583}
4584
1fe779f8
CO		 4585long kvm_arch_vm_ioctl(struct file *filp,
4586 unsigned int ioctl, unsigned long arg)
4587{
4588 struct kvm *kvm = filp->private_data;
4589 void __user *argp = (void __user *)arg;
367e1319 4590 int r = -ENOTTY;
f0d66275
DH		 4591 /*
4592 * This union makes it completely explicit to gcc-3.x
4593 * that these two variables' stack usage should be
4594 * combined, not added together.
4595 */
4596 union {
4597 struct kvm_pit_state ps;
e9f42757 4598 struct kvm_pit_state2 ps2;
c5ff41ce 4599 struct kvm_pit_config pit_config;
f0d66275 4600 } u;
1fe779f8
CO		 4601
4602 switch (ioctl) {
4603 case KVM_SET_TSS_ADDR:
4604 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4605 break;
b927a3ce
SY		 4606 case KVM_SET_IDENTITY_MAP_ADDR: {
4607 u64 ident_addr;
4608
1af1ac91
DH		 4609 mutex_lock(&kvm->lock);
4610 r = -EINVAL;
4611 if (kvm->created_vcpus)
4612 goto set_identity_unlock;
b927a3ce 4613 r = -EFAULT;
0e96f31e 4614 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4615 goto set_identity_unlock;
b927a3ce 4616 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4617set_identity_unlock:
4618 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4619 break;
4620 }
1fe779f8
CO		 4621 case KVM_SET_NR_MMU_PAGES:
4622 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4623 break;
4624 case KVM_GET_NR_MMU_PAGES:
4625 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4626 break;
3ddea128 4627 case KVM_CREATE_IRQCHIP: {
3ddea128 4628 mutex_lock(&kvm->lock);
09941366 4629
3ddea128 4630 r = -EEXIST;
35e6eaa3 4631 if (irqchip_in_kernel(kvm))
3ddea128 4632 goto create_irqchip_unlock;
09941366 4633
3e515705 4634 r = -EINVAL;
557abc40 4635 if (kvm->created_vcpus)
3e515705 4636 goto create_irqchip_unlock;
09941366
RK		 4637
4638 r = kvm_pic_init(kvm);
4639 if (r)
3ddea128 4640 goto create_irqchip_unlock;
09941366
RK		 4641
4642 r = kvm_ioapic_init(kvm);
4643 if (r) {
09941366 4644 kvm_pic_destroy(kvm);
3ddea128 4645 goto create_irqchip_unlock;
09941366
RK		 4646 }
4647
399ec807
AK		 4648 r = kvm_setup_default_irq_routing(kvm);
4649 if (r) {
72bb2fcd 4650 kvm_ioapic_destroy(kvm);
09941366 4651 kvm_pic_destroy(kvm);
71ba994c 4652 goto create_irqchip_unlock;
399ec807 4653 }
49776faf 4654 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4655 smp_wmb();
49776faf 4656 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4657 create_irqchip_unlock:
4658 mutex_unlock(&kvm->lock);
1fe779f8 4659 break;
3ddea128 4660 }
7837699f 4661 case KVM_CREATE_PIT:
c5ff41ce
JK		 4662 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4663 goto create_pit;
4664 case KVM_CREATE_PIT2:
4665 r = -EFAULT;
4666 if (copy_from_user(&u.pit_config, argp,
4667 sizeof(struct kvm_pit_config)))
4668 goto out;
4669 create_pit:
250715a6 4670 mutex_lock(&kvm->lock);
269e05e4
AK		 4671 r = -EEXIST;
4672 if (kvm->arch.vpit)
4673 goto create_pit_unlock;
7837699f 4674 r = -ENOMEM;
c5ff41ce 4675 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4676 if (kvm->arch.vpit)
4677 r = 0;
269e05e4 4678 create_pit_unlock:
250715a6 4679 mutex_unlock(&kvm->lock);
7837699f 4680 break;
1fe779f8
CO		 4681 case KVM_GET_IRQCHIP: {
4682 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4683 struct kvm_irqchip *chip;
1fe779f8 4684
ff5c2c03
SL		 4685 chip = memdup_user(argp, sizeof(*chip));
4686 if (IS_ERR(chip)) {
4687 r = PTR_ERR(chip);
1fe779f8 4688 goto out;
ff5c2c03
SL		 4689 }
4690
1fe779f8 4691 r = -ENXIO;
826da321 4692 if (!irqchip_kernel(kvm))
f0d66275
DH		 4693 goto get_irqchip_out;
4694 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4695 if (r)
f0d66275 4696 goto get_irqchip_out;
1fe779f8 4697 r = -EFAULT;
0e96f31e 4698 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4699 goto get_irqchip_out;
1fe779f8 4700 r = 0;
f0d66275
DH		 4701 get_irqchip_out:
4702 kfree(chip);
1fe779f8
CO		 4703 break;
4704 }
4705 case KVM_SET_IRQCHIP: {
4706 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4707 struct kvm_irqchip *chip;
1fe779f8 4708
ff5c2c03
SL		 4709 chip = memdup_user(argp, sizeof(*chip));
4710 if (IS_ERR(chip)) {
4711 r = PTR_ERR(chip);
1fe779f8 4712 goto out;
ff5c2c03
SL		 4713 }
4714
1fe779f8 4715 r = -ENXIO;
826da321 4716 if (!irqchip_kernel(kvm))
f0d66275
DH		 4717 goto set_irqchip_out;
4718 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4719 if (r)
f0d66275 4720 goto set_irqchip_out;
1fe779f8 4721 r = 0;
f0d66275
DH		 4722 set_irqchip_out:
4723 kfree(chip);
1fe779f8
CO		 4724 break;
4725 }
e0f63cb9 4726 case KVM_GET_PIT: {
e0f63cb9 4727 r = -EFAULT;
f0d66275 4728 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4729 goto out;
4730 r = -ENXIO;
4731 if (!kvm->arch.vpit)
4732 goto out;
f0d66275 4733 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4734 if (r)
4735 goto out;
4736 r = -EFAULT;
f0d66275 4737 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4738 goto out;
4739 r = 0;
4740 break;
4741 }
4742 case KVM_SET_PIT: {
e0f63cb9 4743 r = -EFAULT;
0e96f31e 4744 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4745 goto out;
4746 r = -ENXIO;
4747 if (!kvm->arch.vpit)
4748 goto out;
f0d66275 4749 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4750 break;
4751 }
e9f42757
BK		 4752 case KVM_GET_PIT2: {
4753 r = -ENXIO;
4754 if (!kvm->arch.vpit)
4755 goto out;
4756 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4757 if (r)
4758 goto out;
4759 r = -EFAULT;
4760 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4761 goto out;
4762 r = 0;
4763 break;
4764 }
4765 case KVM_SET_PIT2: {
4766 r = -EFAULT;
4767 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4768 goto out;
4769 r = -ENXIO;
4770 if (!kvm->arch.vpit)
4771 goto out;
4772 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4773 break;
4774 }
52d939a0
MT		 4775 case KVM_REINJECT_CONTROL: {
4776 struct kvm_reinject_control control;
4777 r = -EFAULT;
4778 if (copy_from_user(&control, argp, sizeof(control)))
4779 goto out;
4780 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4781 break;
4782 }
d71ba788
PB		 4783 case KVM_SET_BOOT_CPU_ID:
4784 r = 0;
4785 mutex_lock(&kvm->lock);
557abc40 4786 if (kvm->created_vcpus)
d71ba788
PB		 4787 r = -EBUSY;
4788 else
4789 kvm->arch.bsp_vcpu_id = arg;
4790 mutex_unlock(&kvm->lock);
4791 break;
ffde22ac 4792 case KVM_XEN_HVM_CONFIG: {
51776043 4793 struct kvm_xen_hvm_config xhc;
ffde22ac 4794 r = -EFAULT;
51776043 4795 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4796 goto out;
4797 r = -EINVAL;
51776043 4798 if (xhc.flags)
ffde22ac 4799 goto out;
51776043 4800 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4801 r = 0;
4802 break;
4803 }
afbcf7ab 4804 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4805 struct kvm_clock_data user_ns;
4806 u64 now_ns;
afbcf7ab
GC		 4807
4808 r = -EFAULT;
4809 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4810 goto out;
4811
4812 r = -EINVAL;
4813 if (user_ns.flags)
4814 goto out;
4815
4816 r = 0;
0bc48bea
RK		 4817 /*
4818 * TODO: userspace has to take care of races with VCPU_RUN, so
4819 * kvm_gen_update_masterclock() can be cut down to locked
4820 * pvclock_update_vm_gtod_copy().
4821 */
4822 kvm_gen_update_masterclock(kvm);
e891a32e 4823 now_ns = get_kvmclock_ns(kvm);
108b249c 4824 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4825 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4826 break;
4827 }
4828 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4829 struct kvm_clock_data user_ns;
4830 u64 now_ns;
4831
e891a32e 4832 now_ns = get_kvmclock_ns(kvm);
108b249c 4833 user_ns.clock = now_ns;
e3fd9a93 4834 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4835 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4836
4837 r = -EFAULT;
4838 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4839 goto out;
4840 r = 0;
4841 break;
4842 }
5acc5c06
BS		 4843 case KVM_MEMORY_ENCRYPT_OP: {
4844 r = -ENOTTY;
4845 if (kvm_x86_ops->mem_enc_op)
4846 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4847 break;
4848 }
69eaedee
BS		 4849 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4850 struct kvm_enc_region region;
4851
4852 r = -EFAULT;
4853 if (copy_from_user(&region, argp, sizeof(region)))
4854 goto out;
4855
4856 r = -ENOTTY;
4857 if (kvm_x86_ops->mem_enc_reg_region)
4858 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4859 break;
4860 }
4861 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4862 struct kvm_enc_region region;
4863
4864 r = -EFAULT;
4865 if (copy_from_user(&region, argp, sizeof(region)))
4866 goto out;
4867
4868 r = -ENOTTY;
4869 if (kvm_x86_ops->mem_enc_unreg_region)
4870 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4871 break;
4872 }
faeb7833
RK		 4873 case KVM_HYPERV_EVENTFD: {
4874 struct kvm_hyperv_eventfd hvevfd;
4875
4876 r = -EFAULT;
4877 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4878 goto out;
4879 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4880 break;
4881 }
1fe779f8 4882 default:
ad6260da 4883 r = -ENOTTY;
1fe779f8
CO		 4884 }
4885out:
4886 return r;
4887}
4888
a16b043c 4889static void kvm_init_msr_list(void)
043405e1
CO		 4890{
4891 u32 dummy[2];
4892 unsigned i, j;
4893
62ef68bb 4894 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4895 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4896 continue;
93c4adc7
PB		 4897
4898 /*
4899 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4900 * to the guests in some cases.
93c4adc7
PB		 4901 */
4902 switch (msrs_to_save[i]) {
4903 case MSR_IA32_BNDCFGS:
503234b3 4904 if (!kvm_mpx_supported())
93c4adc7
PB		 4905 continue;
4906 break;
9dbe6cf9
PB		 4907 case MSR_TSC_AUX:
4908 if (!kvm_x86_ops->rdtscp_supported())
4909 continue;
4910 break;
bf8c55d8
CP		 4911 case MSR_IA32_RTIT_CTL:
4912 case MSR_IA32_RTIT_STATUS:
4913 if (!kvm_x86_ops->pt_supported())
4914 continue;
4915 break;
4916 case MSR_IA32_RTIT_CR3_MATCH:
4917 if (!kvm_x86_ops->pt_supported() ||
4918 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
4919 continue;
4920 break;
4921 case MSR_IA32_RTIT_OUTPUT_BASE:
4922 case MSR_IA32_RTIT_OUTPUT_MASK:
4923 if (!kvm_x86_ops->pt_supported() ||
4924 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
4925 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
4926 continue;
4927 break;
4928 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
4929 if (!kvm_x86_ops->pt_supported() ||
4930 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
4931 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
4932 continue;
4933 break;
4934 }
93c4adc7
PB		 4935 default:
4936 break;
4937 }
4938
043405e1
CO		 4939 if (j < i)
4940 msrs_to_save[j] = msrs_to_save[i];
4941 j++;
4942 }
4943 num_msrs_to_save = j;
62ef68bb
PB		 4944
4945 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4946 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4947 continue;
62ef68bb
PB		 4948
4949 if (j < i)
4950 emulated_msrs[j] = emulated_msrs[i];
4951 j++;
4952 }
4953 num_emulated_msrs = j;
801e459a
TL		 4954
4955 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4956 struct kvm_msr_entry msr;
4957
4958 msr.index = msr_based_features[i];
66421c1e 4959 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4960 continue;
4961
4962 if (j < i)
4963 msr_based_features[j] = msr_based_features[i];
4964 j++;
4965 }
4966 num_msr_based_features = j;
043405e1
CO		 4967}
4968
bda9020e
MT		 4969static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4970 const void *v)
bbd9b64e 4971{
70252a10
AK		 4972 int handled = 0;
4973 int n;
4974
4975 do {
4976 n = min(len, 8);
bce87cce 4977 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4978 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4979 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4980 break;
4981 handled += n;
4982 addr += n;
4983 len -= n;
4984 v += n;
4985 } while (len);
bbd9b64e 4986
70252a10 4987 return handled;
bbd9b64e
CO		 4988}
4989
bda9020e 4990static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4991{
70252a10
AK		 4992 int handled = 0;
4993 int n;
4994
4995 do {
4996 n = min(len, 8);
bce87cce 4997 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4998 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4999 addr, n, v))
5000 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5001 break;
e39d200f 5002 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5003 handled += n;
5004 addr += n;
5005 len -= n;
5006 v += n;
5007 } while (len);
bbd9b64e 5008
70252a10 5009 return handled;
bbd9b64e
CO		 5010}
5011
2dafc6c2
GN		 5012static void kvm_set_segment(struct kvm_vcpu *vcpu,
5013 struct kvm_segment *var, int seg)
5014{
5015 kvm_x86_ops->set_segment(vcpu, var, seg);
5016}
5017
5018void kvm_get_segment(struct kvm_vcpu *vcpu,
5019 struct kvm_segment *var, int seg)
5020{
5021 kvm_x86_ops->get_segment(vcpu, var, seg);
5022}
5023
54987b7a
PB		 5024gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5025 struct x86_exception *exception)
02f59dc9
JR		 5026{
5027 gpa_t t_gpa;
02f59dc9
JR		 5028
5029 BUG_ON(!mmu_is_nested(vcpu));
5030
5031 /* NPT walks are always user-walks */
5032 access |= PFERR_USER_MASK;
44dd3ffa 5033 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5034
5035 return t_gpa;
5036}
5037
ab9ae313
AK		 5038gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5039 struct x86_exception *exception)
1871c602
GN		 5040{
5041 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5042 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5043}
5044
ab9ae313
AK		 5045 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5046 struct x86_exception *exception)
1871c602
GN		 5047{
5048 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5049 access |= PFERR_FETCH_MASK;
ab9ae313 5050 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5051}
5052
ab9ae313
AK		 5053gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5054 struct x86_exception *exception)
1871c602
GN		 5055{
5056 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5057 access |= PFERR_WRITE_MASK;
ab9ae313 5058 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5059}
5060
5061/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5062gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5063 struct x86_exception *exception)
1871c602 5064{
ab9ae313 5065 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5066}
5067
5068static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5069 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5070 struct x86_exception *exception)
bbd9b64e
CO		 5071{
5072 void *data = val;
10589a46 5073 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5074
5075 while (bytes) {
14dfe855 5076 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5077 exception);
bbd9b64e 5078 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5079 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5080 int ret;
5081
bcc55cba 5082 if (gpa == UNMAPPED_GVA)
ab9ae313 5083 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5084 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5085 offset, toread);
10589a46 5086 if (ret < 0) {
c3cd7ffa 5087 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5088 goto out;
5089 }
bbd9b64e 5090
77c2002e
IE		 5091 bytes -= toread;
5092 data += toread;
5093 addr += toread;
bbd9b64e 5094 }
10589a46 5095out:
10589a46 5096 return r;
bbd9b64e 5097}
77c2002e 5098
1871c602 5099/* used for instruction fetching */
0f65dd70
AK		 5100static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5101 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5102 struct x86_exception *exception)
1871c602 5103{
0f65dd70 5104 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5105 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5106 unsigned offset;
5107 int ret;
0f65dd70 5108
44583cba
PB		 5109 /* Inline kvm_read_guest_virt_helper for speed. */
5110 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5111 exception);
5112 if (unlikely(gpa == UNMAPPED_GVA))
5113 return X86EMUL_PROPAGATE_FAULT;
5114
5115 offset = addr & (PAGE_SIZE-1);
5116 if (WARN_ON(offset + bytes > PAGE_SIZE))
5117 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5118 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5119 offset, bytes);
44583cba
PB		 5120 if (unlikely(ret < 0))
5121 return X86EMUL_IO_NEEDED;
5122
5123 return X86EMUL_CONTINUE;
1871c602
GN		 5124}
5125
ce14e868 5126int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5127 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5128 struct x86_exception *exception)
1871c602
GN		 5129{
5130 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5131
353c0956
PB		 5132 /*
5133 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5134 * is returned, but our callers are not ready for that and they blindly
5135 * call kvm_inject_page_fault. Ensure that they at least do not leak
5136 * uninitialized kernel stack memory into cr2 and error code.
5137 */
5138 memset(exception, 0, sizeof(*exception));
1871c602 5139 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5140 exception);
1871c602 5141}
064aea77 5142EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5143
ce14e868
PB		 5144static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5145 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5146 struct x86_exception *exception, bool system)
1871c602 5147{
0f65dd70 5148 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5149 u32 access = 0;
5150
5151 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5152 access |= PFERR_USER_MASK;
5153
5154 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5155}
5156
7a036a6f
RK		 5157static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5158 unsigned long addr, void *val, unsigned int bytes)
5159{
5160 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5161 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5162
5163 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5164}
5165
ce14e868
PB		 5166static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5167 struct kvm_vcpu *vcpu, u32 access,
5168 struct x86_exception *exception)
77c2002e
IE		 5169{
5170 void *data = val;
5171 int r = X86EMUL_CONTINUE;
5172
5173 while (bytes) {
14dfe855 5174 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5175 access,
ab9ae313 5176 exception);
77c2002e
IE		 5177 unsigned offset = addr & (PAGE_SIZE-1);
5178 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5179 int ret;
5180
bcc55cba 5181 if (gpa == UNMAPPED_GVA)
ab9ae313 5182 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5183 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5184 if (ret < 0) {
c3cd7ffa 5185 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5186 goto out;
5187 }
5188
5189 bytes -= towrite;
5190 data += towrite;
5191 addr += towrite;
5192 }
5193out:
5194 return r;
5195}
ce14e868
PB		 5196
5197static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5198 unsigned int bytes, struct x86_exception *exception,
5199 bool system)
ce14e868
PB		 5200{
5201 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5202 u32 access = PFERR_WRITE_MASK;
5203
5204 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5205 access |= PFERR_USER_MASK;
ce14e868
PB		 5206
5207 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5208 access, exception);
ce14e868
PB		 5209}
5210
5211int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5212 unsigned int bytes, struct x86_exception *exception)
5213{
c595ceee
PB		 5214 /* kvm_write_guest_virt_system can pull in tons of pages. */
5215 vcpu->arch.l1tf_flush_l1d = true;
5216
ce14e868
PB		 5217 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5218 PFERR_WRITE_MASK, exception);
5219}
6a4d7550 5220EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5221
082d06ed
WL		 5222int handle_ud(struct kvm_vcpu *vcpu)
5223{
6c86eedc 5224 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5225 enum emulation_result er;
6c86eedc
WL		 5226 char sig[5]; /* ud2; .ascii "kvm" */
5227 struct x86_exception e;
5228
5229 if (force_emulation_prefix &&
3c9fa24c
PB		 5230 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5231 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5232 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5233 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5234 emul_type = 0;
5235 }
082d06ed 5236
0ce97a2b 5237 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5238 if (er == EMULATE_USER_EXIT)
5239 return 0;
5240 if (er != EMULATE_DONE)
5241 kvm_queue_exception(vcpu, UD_VECTOR);
5242 return 1;
5243}
5244EXPORT_SYMBOL_GPL(handle_ud);
5245
0f89b207
TL		 5246static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5247 gpa_t gpa, bool write)
5248{
5249 /* For APIC access vmexit */
5250 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5251 return 1;
5252
5253 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5254 trace_vcpu_match_mmio(gva, gpa, write, true);
5255 return 1;
5256 }
5257
5258 return 0;
5259}
5260
af7cc7d1
XG		 5261static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5262 gpa_t *gpa, struct x86_exception *exception,
5263 bool write)
5264{
97d64b78
AK		 5265 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5266 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5267
be94f6b7
HH		 5268 /*
5269 * currently PKRU is only applied to ept enabled guest so
5270 * there is no pkey in EPT page table for L1 guest or EPT
5271 * shadow page table for L2 guest.
5272 */
97d64b78 5273 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5274 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5275 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5276 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5277 (gva & (PAGE_SIZE - 1));
4f022648 5278 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5279 return 1;
5280 }
5281
af7cc7d1
XG		 5282 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5283
5284 if (*gpa == UNMAPPED_GVA)
5285 return -1;
5286
0f89b207 5287 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5288}
5289
3200f405 5290int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5291 const void *val, int bytes)
bbd9b64e
CO		 5292{
5293 int ret;
5294
54bf36aa 5295 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5296 if (ret < 0)
bbd9b64e 5297 return 0;
0eb05bf2 5298 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5299 return 1;
5300}
5301
77d197b2
XG		 5302struct read_write_emulator_ops {
5303 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5304 int bytes);
5305 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5306 void *val, int bytes);
5307 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5308 int bytes, void *val);
5309 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5310 void *val, int bytes);
5311 bool write;
5312};
5313
5314static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5315{
5316 if (vcpu->mmio_read_completed) {
77d197b2 5317 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5318 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5319 vcpu->mmio_read_completed = 0;
5320 return 1;
5321 }
5322
5323 return 0;
5324}
5325
5326static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5327 void *val, int bytes)
5328{
54bf36aa 5329 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5330}
5331
5332static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5333 void *val, int bytes)
5334{
5335 return emulator_write_phys(vcpu, gpa, val, bytes);
5336}
5337
5338static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5339{
e39d200f 5340 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5341 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5342}
5343
5344static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5345 void *val, int bytes)
5346{
e39d200f 5347 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5348 return X86EMUL_IO_NEEDED;
5349}
5350
5351static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5352 void *val, int bytes)
5353{
f78146b0
AK		 5354 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5355
87da7e66 5356 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5357 return X86EMUL_CONTINUE;
5358}
5359
0fbe9b0b 5360static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5361 .read_write_prepare = read_prepare,
5362 .read_write_emulate = read_emulate,
5363 .read_write_mmio = vcpu_mmio_read,
5364 .read_write_exit_mmio = read_exit_mmio,
5365};
5366
0fbe9b0b 5367static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5368 .read_write_emulate = write_emulate,
5369 .read_write_mmio = write_mmio,
5370 .read_write_exit_mmio = write_exit_mmio,
5371 .write = true,
5372};
5373
22388a3c
XG		 5374static int emulator_read_write_onepage(unsigned long addr, void *val,
5375 unsigned int bytes,
5376 struct x86_exception *exception,
5377 struct kvm_vcpu *vcpu,
0fbe9b0b 5378 const struct read_write_emulator_ops *ops)
bbd9b64e 5379{
af7cc7d1
XG		 5380 gpa_t gpa;
5381 int handled, ret;
22388a3c 5382 bool write = ops->write;
f78146b0 5383 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5384 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5385
5386 /*
5387 * If the exit was due to a NPF we may already have a GPA.
5388 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5389 * Note, this cannot be used on string operations since string
5390 * operation using rep will only have the initial GPA from the NPF
5391 * occurred.
5392 */
5393 if (vcpu->arch.gpa_available &&
5394 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5395 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5396 gpa = vcpu->arch.gpa_val;
5397 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5398 } else {
5399 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5400 if (ret < 0)
5401 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5402 }
10589a46 5403
618232e2 5404 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5405 return X86EMUL_CONTINUE;
5406
bbd9b64e
CO		 5407 /*
5408 * Is this MMIO handled locally?
5409 */
22388a3c 5410 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5411 if (handled == bytes)
bbd9b64e 5412 return X86EMUL_CONTINUE;
bbd9b64e 5413
70252a10
AK		 5414 gpa += handled;
5415 bytes -= handled;
5416 val += handled;
5417
87da7e66
XG		 5418 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5419 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5420 frag->gpa = gpa;
5421 frag->data = val;
5422 frag->len = bytes;
f78146b0 5423 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5424}
5425
52eb5a6d
XL		 5426static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5427 unsigned long addr,
22388a3c
XG		 5428 void *val, unsigned int bytes,
5429 struct x86_exception *exception,
0fbe9b0b 5430 const struct read_write_emulator_ops *ops)
bbd9b64e 5431{
0f65dd70 5432 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5433 gpa_t gpa;
5434 int rc;
5435
5436 if (ops->read_write_prepare &&
5437 ops->read_write_prepare(vcpu, val, bytes))
5438 return X86EMUL_CONTINUE;
5439
5440 vcpu->mmio_nr_fragments = 0;
0f65dd70 5441
bbd9b64e
CO		 5442 /* Crossing a page boundary? */
5443 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5444 int now;
bbd9b64e
CO		 5445
5446 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5447 rc = emulator_read_write_onepage(addr, val, now, exception,
5448 vcpu, ops);
5449
bbd9b64e
CO		 5450 if (rc != X86EMUL_CONTINUE)
5451 return rc;
5452 addr += now;
bac15531
NA		 5453 if (ctxt->mode != X86EMUL_MODE_PROT64)
5454 addr = (u32)addr;
bbd9b64e
CO		 5455 val += now;
5456 bytes -= now;
5457 }
22388a3c 5458
f78146b0
AK		 5459 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5460 vcpu, ops);
5461 if (rc != X86EMUL_CONTINUE)
5462 return rc;
5463
5464 if (!vcpu->mmio_nr_fragments)
5465 return rc;
5466
5467 gpa = vcpu->mmio_fragments[0].gpa;
5468
5469 vcpu->mmio_needed = 1;
5470 vcpu->mmio_cur_fragment = 0;
5471
87da7e66 5472 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5473 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5474 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5475 vcpu->run->mmio.phys_addr = gpa;
5476
5477 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5478}
5479
5480static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5481 unsigned long addr,
5482 void *val,
5483 unsigned int bytes,
5484 struct x86_exception *exception)
5485{
5486 return emulator_read_write(ctxt, addr, val, bytes,
5487 exception, &read_emultor);
5488}
5489
52eb5a6d 5490static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5491 unsigned long addr,
5492 const void *val,
5493 unsigned int bytes,
5494 struct x86_exception *exception)
5495{
5496 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5497 exception, &write_emultor);
bbd9b64e 5498}
bbd9b64e 5499
daea3e73
AK		 5500#define CMPXCHG_TYPE(t, ptr, old, new) \
5501 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5502
5503#ifdef CONFIG_X86_64
5504# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5505#else
5506# define CMPXCHG64(ptr, old, new) \
9749a6c0 5507 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5508#endif
5509
0f65dd70
AK		 5510static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5511 unsigned long addr,
bbd9b64e
CO		 5512 const void *old,
5513 const void *new,
5514 unsigned int bytes,
0f65dd70 5515 struct x86_exception *exception)
bbd9b64e 5516{
0f65dd70 5517 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5518 gpa_t gpa;
5519 struct page *page;
5520 char *kaddr;
5521 bool exchanged;
2bacc55c 5522
daea3e73
AK		 5523 /* guests cmpxchg8b have to be emulated atomically */
5524 if (bytes > 8 || (bytes & (bytes - 1)))
5525 goto emul_write;
10589a46 5526
daea3e73 5527 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5528
daea3e73
AK		 5529 if (gpa == UNMAPPED_GVA ||
5530 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5531 goto emul_write;
2bacc55c 5532
daea3e73
AK		 5533 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5534 goto emul_write;
72dc67a6 5535
54bf36aa 5536 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5537 if (is_error_page(page))
c19b8bd6 5538 goto emul_write;
72dc67a6 5539
8fd75e12 5540 kaddr = kmap_atomic(page);
daea3e73
AK		 5541 kaddr += offset_in_page(gpa);
5542 switch (bytes) {
5543 case 1:
5544 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5545 break;
5546 case 2:
5547 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5548 break;
5549 case 4:
5550 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5551 break;
5552 case 8:
5553 exchanged = CMPXCHG64(kaddr, old, new);
5554 break;
5555 default:
5556 BUG();
2bacc55c 5557 }
8fd75e12 5558 kunmap_atomic(kaddr);
daea3e73
AK		 5559 kvm_release_page_dirty(page);
5560
5561 if (!exchanged)
5562 return X86EMUL_CMPXCHG_FAILED;
5563
54bf36aa 5564 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5565 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5566
5567 return X86EMUL_CONTINUE;
4a5f48f6 5568
3200f405 5569emul_write:
daea3e73 5570 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5571
0f65dd70 5572 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5573}
5574
cf8f70bf
GN		 5575static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5576{
cbfc6c91 5577 int r = 0, i;
cf8f70bf 5578
cbfc6c91
WL		 5579 for (i = 0; i < vcpu->arch.pio.count; i++) {
5580 if (vcpu->arch.pio.in)
5581 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5582 vcpu->arch.pio.size, pd);
5583 else
5584 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5585 vcpu->arch.pio.port, vcpu->arch.pio.size,
5586 pd);
5587 if (r)
5588 break;
5589 pd += vcpu->arch.pio.size;
5590 }
cf8f70bf
GN		 5591 return r;
5592}
5593
6f6fbe98
XG		 5594static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5595 unsigned short port, void *val,
5596 unsigned int count, bool in)
cf8f70bf 5597{
cf8f70bf 5598 vcpu->arch.pio.port = port;
6f6fbe98 5599 vcpu->arch.pio.in = in;
7972995b 5600 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5601 vcpu->arch.pio.size = size;
5602
5603 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5604 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5605 return 1;
5606 }
5607
5608 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5609 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5610 vcpu->run->io.size = size;
5611 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5612 vcpu->run->io.count = count;
5613 vcpu->run->io.port = port;
5614
5615 return 0;
5616}
5617
6f6fbe98
XG		 5618static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5619 int size, unsigned short port, void *val,
5620 unsigned int count)
cf8f70bf 5621{
ca1d4a9e 5622 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5623 int ret;
ca1d4a9e 5624
6f6fbe98
XG		 5625 if (vcpu->arch.pio.count)
5626 goto data_avail;
cf8f70bf 5627
cbfc6c91
WL		 5628 memset(vcpu->arch.pio_data, 0, size * count);
5629
6f6fbe98
XG		 5630 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5631 if (ret) {
5632data_avail:
5633 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5634 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5635 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5636 return 1;
5637 }
5638
cf8f70bf
GN		 5639 return 0;
5640}
5641
6f6fbe98
XG		 5642static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5643 int size, unsigned short port,
5644 const void *val, unsigned int count)
5645{
5646 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5647
5648 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5649 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5650 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5651}
5652
bbd9b64e
CO		 5653static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5654{
5655 return kvm_x86_ops->get_segment_base(vcpu, seg);
5656}
5657
3cb16fe7 5658static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5659{
3cb16fe7 5660 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5661}
5662
ae6a2375 5663static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5664{
5665 if (!need_emulate_wbinvd(vcpu))
5666 return X86EMUL_CONTINUE;
5667
5668 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5669 int cpu = get_cpu();
5670
5671 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5672 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5673 wbinvd_ipi, NULL, 1);
2eec7343 5674 put_cpu();
f5f48ee1 5675 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5676 } else
5677 wbinvd();
f5f48ee1
SY		 5678 return X86EMUL_CONTINUE;
5679}
5cb56059
JS		 5680
5681int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5682{
6affcbed
KH		 5683 kvm_emulate_wbinvd_noskip(vcpu);
5684 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5685}
f5f48ee1
SY		 5686EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5687
5cb56059
JS		 5688
5689
bcaf5cc5
AK		 5690static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5691{
5cb56059 5692 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5693}
5694
52eb5a6d
XL		 5695static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5696 unsigned long *dest)
bbd9b64e 5697{
16f8a6f9 5698 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5699}
5700
52eb5a6d
XL		 5701static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5702 unsigned long value)
bbd9b64e 5703{
338dbc97 5704
717746e3 5705 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5706}
5707
52a46617 5708static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5709{
52a46617 5710 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5711}
5712
717746e3 5713static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5714{
717746e3 5715 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5716 unsigned long value;
5717
5718 switch (cr) {
5719 case 0:
5720 value = kvm_read_cr0(vcpu);
5721 break;
5722 case 2:
5723 value = vcpu->arch.cr2;
5724 break;
5725 case 3:
9f8fe504 5726 value = kvm_read_cr3(vcpu);
52a46617
GN		 5727 break;
5728 case 4:
5729 value = kvm_read_cr4(vcpu);
5730 break;
5731 case 8:
5732 value = kvm_get_cr8(vcpu);
5733 break;
5734 default:
a737f256 5735 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5736 return 0;
5737 }
5738
5739 return value;
5740}
5741
717746e3 5742static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5743{
717746e3 5744 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5745 int res = 0;
5746
52a46617
GN		 5747 switch (cr) {
5748 case 0:
49a9b07e 5749 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5750 break;
5751 case 2:
5752 vcpu->arch.cr2 = val;
5753 break;
5754 case 3:
2390218b 5755 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5756 break;
5757 case 4:
a83b29c6 5758 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5759 break;
5760 case 8:
eea1cff9 5761 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5762 break;
5763 default:
a737f256 5764 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5765 res = -1;
52a46617 5766 }
0f12244f
GN		 5767
5768 return res;
52a46617
GN		 5769}
5770
717746e3 5771static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5772{
717746e3 5773 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5774}
5775
4bff1e86 5776static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5777{
4bff1e86 5778 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5779}
5780
4bff1e86 5781static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5782{
4bff1e86 5783 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5784}
5785
1ac9d0cf
AK		 5786static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5787{
5788 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5789}
5790
5791static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5792{
5793 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5794}
5795
4bff1e86
AK		 5796static unsigned long emulator_get_cached_segment_base(
5797 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5798{
4bff1e86 5799 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5800}
5801
1aa36616
AK		 5802static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5803 struct desc_struct *desc, u32 *base3,
5804 int seg)
2dafc6c2
GN		 5805{
5806 struct kvm_segment var;
5807
4bff1e86 5808 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5809 *selector = var.selector;
2dafc6c2 5810
378a8b09
GN		 5811 if (var.unusable) {
5812 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5813 if (base3)
5814 *base3 = 0;
2dafc6c2 5815 return false;
378a8b09 5816 }
2dafc6c2
GN		 5817
5818 if (var.g)
5819 var.limit >>= 12;
5820 set_desc_limit(desc, var.limit);
5821 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5822#ifdef CONFIG_X86_64
5823 if (base3)
5824 *base3 = var.base >> 32;
5825#endif
2dafc6c2
GN		 5826 desc->type = var.type;
5827 desc->s = var.s;
5828 desc->dpl = var.dpl;
5829 desc->p = var.present;
5830 desc->avl = var.avl;
5831 desc->l = var.l;
5832 desc->d = var.db;
5833 desc->g = var.g;
5834
5835 return true;
5836}
5837
1aa36616
AK		 5838static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5839 struct desc_struct *desc, u32 base3,
5840 int seg)
2dafc6c2 5841{
4bff1e86 5842 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5843 struct kvm_segment var;
5844
1aa36616 5845 var.selector = selector;
2dafc6c2 5846 var.base = get_desc_base(desc);
5601d05b
GN		 5847#ifdef CONFIG_X86_64
5848 var.base |= ((u64)base3) << 32;
5849#endif
2dafc6c2
GN		 5850 var.limit = get_desc_limit(desc);
5851 if (desc->g)
5852 var.limit = (var.limit << 12) | 0xfff;
5853 var.type = desc->type;
2dafc6c2
GN		 5854 var.dpl = desc->dpl;
5855 var.db = desc->d;
5856 var.s = desc->s;
5857 var.l = desc->l;
5858 var.g = desc->g;
5859 var.avl = desc->avl;
5860 var.present = desc->p;
5861 var.unusable = !var.present;
5862 var.padding = 0;
5863
5864 kvm_set_segment(vcpu, &var, seg);
5865 return;
5866}
5867
717746e3
AK		 5868static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5869 u32 msr_index, u64 *pdata)
5870{
609e36d3
PB		 5871 struct msr_data msr;
5872 int r;
5873
5874 msr.index = msr_index;
5875 msr.host_initiated = false;
5876 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5877 if (r)
5878 return r;
5879
5880 *pdata = msr.data;
5881 return 0;
717746e3
AK		 5882}
5883
5884static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5885 u32 msr_index, u64 data)
5886{
8fe8ab46
WA		 5887 struct msr_data msr;
5888
5889 msr.data = data;
5890 msr.index = msr_index;
5891 msr.host_initiated = false;
5892 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5893}
5894
64d60670
PB		 5895static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5896{
5897 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5898
5899 return vcpu->arch.smbase;
5900}
5901
5902static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5903{
5904 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5905
5906 vcpu->arch.smbase = smbase;
5907}
5908
67f4d428
NA		 5909static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5910 u32 pmc)
5911{
c6702c9d 5912 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5913}
5914
222d21aa
AK		 5915static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5916 u32 pmc, u64 *pdata)
5917{
c6702c9d 5918 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5919}
5920
6c3287f7
AK		 5921static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5922{
5923 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5924}
5925
2953538e 5926static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5927 struct x86_instruction_info *info,
c4f035c6
AK		 5928 enum x86_intercept_stage stage)
5929{
2953538e 5930 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5931}
5932
e911eb3b
YZ		 5933static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5934 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5935{
e911eb3b 5936 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5937}
5938
dd856efa
AK		 5939static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5940{
5941 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5942}
5943
5944static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5945{
5946 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5947}
5948
801806d9
NA		 5949static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5950{
5951 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5952}
5953
6ed071f0
LP		 5954static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5955{
5956 return emul_to_vcpu(ctxt)->arch.hflags;
5957}
5958
5959static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5960{
5961 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5962}
5963
0234bf88
LP		 5964static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5965{
5966 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5967}
5968
0225fb50 5969static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5970 .read_gpr = emulator_read_gpr,
5971 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5972 .read_std = emulator_read_std,
5973 .write_std = emulator_write_std,
7a036a6f 5974 .read_phys = kvm_read_guest_phys_system,
1871c602 5975 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5976 .read_emulated = emulator_read_emulated,
5977 .write_emulated = emulator_write_emulated,
5978 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5979 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5980 .pio_in_emulated = emulator_pio_in_emulated,
5981 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5982 .get_segment = emulator_get_segment,
5983 .set_segment = emulator_set_segment,
5951c442 5984 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5985 .get_gdt = emulator_get_gdt,
160ce1f1 5986 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5987 .set_gdt = emulator_set_gdt,
5988 .set_idt = emulator_set_idt,
52a46617
GN		 5989 .get_cr = emulator_get_cr,
5990 .set_cr = emulator_set_cr,
9c537244 5991 .cpl = emulator_get_cpl,
35aa5375
GN		 5992 .get_dr = emulator_get_dr,
5993 .set_dr = emulator_set_dr,
64d60670
PB		 5994 .get_smbase = emulator_get_smbase,
5995 .set_smbase = emulator_set_smbase,
717746e3
AK		 5996 .set_msr = emulator_set_msr,
5997 .get_msr = emulator_get_msr,
67f4d428 5998 .check_pmc = emulator_check_pmc,
222d21aa 5999 .read_pmc = emulator_read_pmc,
6c3287f7 6000 .halt = emulator_halt,
bcaf5cc5 6001 .wbinvd = emulator_wbinvd,
d6aa1000 6002 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6003 .intercept = emulator_intercept,
bdb42f5a 6004 .get_cpuid = emulator_get_cpuid,
801806d9 6005 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6006 .get_hflags = emulator_get_hflags,
6007 .set_hflags = emulator_set_hflags,
0234bf88 6008 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 6009};
6010
95cb2295
GN		 6011static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6012{
37ccdcbe 6013 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6014 /*
6015 * an sti; sti; sequence only disable interrupts for the first
6016 * instruction. So, if the last instruction, be it emulated or
6017 * not, left the system with the INT_STI flag enabled, it
6018 * means that the last instruction is an sti. We should not
6019 * leave the flag on in this case. The same goes for mov ss
6020 */
37ccdcbe
PB		 6021 if (int_shadow & mask)
6022 mask = 0;
6addfc42 6023 if (unlikely(int_shadow || mask)) {
95cb2295 6024 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6025 if (!mask)
6026 kvm_make_request(KVM_REQ_EVENT, vcpu);
6027 }
95cb2295
GN		 6028}
6029
ef54bcfe 6030static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6031{
6032 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6033 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6034 return kvm_propagate_fault(vcpu, &ctxt->exception);
6035
6036 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6037 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6038 ctxt->exception.error_code);
54b8486f 6039 else
da9cb575 6040 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6041 return false;
54b8486f
GN		 6042}
6043
8ec4722d
MG		 6044static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6045{
adf52235 6046 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6047 int cs_db, cs_l;
6048
8ec4722d
MG		 6049 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6050
adf52235 6051 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6052 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6053
adf52235
TY		 6054 ctxt->eip = kvm_rip_read(vcpu);
6055 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6056 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6057 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6058 cs_db ? X86EMUL_MODE_PROT32 :
6059 X86EMUL_MODE_PROT16;
a584539b 6060 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6061 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6062 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6063
dd856efa 6064 init_decode_cache(ctxt);
7ae441ea 6065 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6066}
6067
71f9833b 6068int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6069{
9d74191a 6070 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6071 int ret;
6072
6073 init_emulate_ctxt(vcpu);
6074
9dac77fa
AK		 6075 ctxt->op_bytes = 2;
6076 ctxt->ad_bytes = 2;
6077 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6078 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6079
6080 if (ret != X86EMUL_CONTINUE)
6081 return EMULATE_FAIL;
6082
9dac77fa 6083 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6084 kvm_rip_write(vcpu, ctxt->eip);
6085 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6086
63995653
MG		 6087 return EMULATE_DONE;
6088}
6089EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6090
e2366171 6091static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6092{
fc3a9157
JR		 6093 int r = EMULATE_DONE;
6094
6d77dbfc
GN		 6095 ++vcpu->stat.insn_emulation_fail;
6096 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6097
6098 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6099 return EMULATE_FAIL;
6100
a2b9e6c1 6101 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6102 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6103 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6104 vcpu->run->internal.ndata = 0;
1f4dcb3b 6105 r = EMULATE_USER_EXIT;
fc3a9157 6106 }
e2366171 6107
6d77dbfc 6108 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6109
6110 return r;
6d77dbfc
GN		 6111}
6112
93c05d3e 6113static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6114 bool write_fault_to_shadow_pgtable,
6115 int emulation_type)
a6f177ef 6116{
95b3cf69 6117 gpa_t gpa = cr2;
ba049e93 6118 kvm_pfn_t pfn;
a6f177ef 6119
384bf221 6120 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6121 return false;
6122
6c3dfeb6
SC		 6123 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6124 return false;
6125
44dd3ffa 6126 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6127 /*
6128 * Write permission should be allowed since only
6129 * write access need to be emulated.
6130 */
6131 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6132
95b3cf69
XG		 6133 /*
6134 * If the mapping is invalid in guest, let cpu retry
6135 * it to generate fault.
6136 */
6137 if (gpa == UNMAPPED_GVA)
6138 return true;
6139 }
a6f177ef 6140
8e3d9d06
XG		 6141 /*
6142 * Do not retry the unhandleable instruction if it faults on the
6143 * readonly host memory, otherwise it will goto a infinite loop:
6144 * retry instruction -> write #PF -> emulation fail -> retry
6145 * instruction -> ...
6146 */
6147 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6148
6149 /*
6150 * If the instruction failed on the error pfn, it can not be fixed,
6151 * report the error to userspace.
6152 */
6153 if (is_error_noslot_pfn(pfn))
6154 return false;
6155
6156 kvm_release_pfn_clean(pfn);
6157
6158 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6159 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6160 unsigned int indirect_shadow_pages;
6161
6162 spin_lock(&vcpu->kvm->mmu_lock);
6163 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6164 spin_unlock(&vcpu->kvm->mmu_lock);
6165
6166 if (indirect_shadow_pages)
6167 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6168
a6f177ef 6169 return true;
8e3d9d06 6170 }
a6f177ef 6171
95b3cf69
XG		 6172 /*
6173 * if emulation was due to access to shadowed page table
6174 * and it failed try to unshadow page and re-enter the
6175 * guest to let CPU execute the instruction.
6176 */
6177 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6178
6179 /*
6180 * If the access faults on its page table, it can not
6181 * be fixed by unprotecting shadow page and it should
6182 * be reported to userspace.
6183 */
6184 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6185}
6186
1cb3f3ae
XG		 6187static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6188 unsigned long cr2, int emulation_type)
6189{
6190 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6191 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6192
6193 last_retry_eip = vcpu->arch.last_retry_eip;
6194 last_retry_addr = vcpu->arch.last_retry_addr;
6195
6196 /*
6197 * If the emulation is caused by #PF and it is non-page_table
6198 * writing instruction, it means the VM-EXIT is caused by shadow
6199 * page protected, we can zap the shadow page and retry this
6200 * instruction directly.
6201 *
6202 * Note: if the guest uses a non-page-table modifying instruction
6203 * on the PDE that points to the instruction, then we will unmap
6204 * the instruction and go to an infinite loop. So, we cache the
6205 * last retried eip and the last fault address, if we meet the eip
6206 * and the address again, we can break out of the potential infinite
6207 * loop.
6208 */
6209 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6210
384bf221 6211 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6212 return false;
6213
6c3dfeb6
SC		 6214 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6215 return false;
6216
1cb3f3ae
XG		 6217 if (x86_page_table_writing_insn(ctxt))
6218 return false;
6219
6220 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6221 return false;
6222
6223 vcpu->arch.last_retry_eip = ctxt->eip;
6224 vcpu->arch.last_retry_addr = cr2;
6225
44dd3ffa 6226 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6227 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6228
22368028 6229 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6230
6231 return true;
6232}
6233
716d51ab
GN		 6234static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6235static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6236
64d60670 6237static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6238{
64d60670 6239 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6240 /* This is a good place to trace that we are exiting SMM. */
6241 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6242
c43203ca
PB		 6243 /* Process a latched INIT or SMI, if any. */
6244 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6245 }
699023e2
PB		 6246
6247 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6248}
6249
6250static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6251{
6252 unsigned changed = vcpu->arch.hflags ^ emul_flags;
6253
a584539b 6254 vcpu->arch.hflags = emul_flags;
64d60670
PB		 6255
6256 if (changed & HF_SMM_MASK)
6257 kvm_smm_changed(vcpu);
a584539b
PB		 6258}
6259
4a1e10d5
PB		 6260static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6261 unsigned long *db)
6262{
6263 u32 dr6 = 0;
6264 int i;
6265 u32 enable, rwlen;
6266
6267 enable = dr7;
6268 rwlen = dr7 >> 16;
6269 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6270 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6271 dr6 |= (1 << i);
6272 return dr6;
6273}
6274
c8401dda 6275static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6276{
6277 struct kvm_run *kvm_run = vcpu->run;
6278
c8401dda
PB		 6279 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6280 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6281 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6282 kvm_run->debug.arch.exception = DB_VECTOR;
6283 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6284 *r = EMULATE_USER_EXIT;
6285 } else {
f10c729f 6286 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6287 }
6288}
6289
6affcbed
KH		 6290int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6291{
6292 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6293 int r = EMULATE_DONE;
6294
6295 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6296
6297 /*
6298 * rflags is the old, "raw" value of the flags. The new value has
6299 * not been saved yet.
6300 *
6301 * This is correct even for TF set by the guest, because "the
6302 * processor will not generate this exception after the instruction
6303 * that sets the TF flag".
6304 */
6305 if (unlikely(rflags & X86_EFLAGS_TF))
6306 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6307 return r == EMULATE_DONE;
6308}
6309EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6310
4a1e10d5
PB		 6311static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6312{
4a1e10d5
PB		 6313 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6314 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6315 struct kvm_run *kvm_run = vcpu->run;
6316 unsigned long eip = kvm_get_linear_rip(vcpu);
6317 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6318 vcpu->arch.guest_debug_dr7,
6319 vcpu->arch.eff_db);
6320
6321 if (dr6 != 0) {
6f43ed01 6322 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6323 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6324 kvm_run->debug.arch.exception = DB_VECTOR;
6325 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6326 *r = EMULATE_USER_EXIT;
6327 return true;
6328 }
6329 }
6330
4161a569
NA		 6331 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6332 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6333 unsigned long eip = kvm_get_linear_rip(vcpu);
6334 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6335 vcpu->arch.dr7,
6336 vcpu->arch.db);
6337
6338 if (dr6 != 0) {
6339 vcpu->arch.dr6 &= ~15;
6f43ed01 6340 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6341 kvm_queue_exception(vcpu, DB_VECTOR);
6342 *r = EMULATE_DONE;
6343 return true;
6344 }
6345 }
6346
6347 return false;
6348}
6349
04789b66
LA		 6350static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6351{
2d7921c4
AM		 6352 switch (ctxt->opcode_len) {
6353 case 1:
6354 switch (ctxt->b) {
6355 case 0xe4: /* IN */
6356 case 0xe5:
6357 case 0xec:
6358 case 0xed:
6359 case 0xe6: /* OUT */
6360 case 0xe7:
6361 case 0xee:
6362 case 0xef:
6363 case 0x6c: /* INS */
6364 case 0x6d:
6365 case 0x6e: /* OUTS */
6366 case 0x6f:
6367 return true;
6368 }
6369 break;
6370 case 2:
6371 switch (ctxt->b) {
6372 case 0x33: /* RDPMC */
6373 return true;
6374 }
6375 break;
04789b66
LA		 6376 }
6377
6378 return false;
6379}
6380
51d8b661
AP		 6381int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6382 unsigned long cr2,
dc25e89e
AP		 6383 int emulation_type,
6384 void *insn,
6385 int insn_len)
bbd9b64e 6386{
95cb2295 6387 int r;
9d74191a 6388 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6389 bool writeback = true;
93c05d3e 6390 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6391
c595ceee
PB		 6392 vcpu->arch.l1tf_flush_l1d = true;
6393
93c05d3e
XG		 6394 /*
6395 * Clear write_fault_to_shadow_pgtable here to ensure it is
6396 * never reused.
6397 */
6398 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6399 kvm_clear_exception_queue(vcpu);
8d7d8102 6400
571008da 6401 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6402 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6403
6404 /*
6405 * We will reenter on the same instruction since
6406 * we do not set complete_userspace_io. This does not
6407 * handle watchpoints yet, those would be handled in
6408 * the emulate_ops.
6409 */
d391f120
VK		 6410 if (!(emulation_type & EMULTYPE_SKIP) &&
6411 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6412 return r;
6413
9d74191a
TY		 6414 ctxt->interruptibility = 0;
6415 ctxt->have_exception = false;
e0ad0b47 6416 ctxt->exception.vector = -1;
9d74191a 6417 ctxt->perm_ok = false;
bbd9b64e 6418
b51e974f 6419 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6420
9d74191a 6421 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6422
e46479f8 6423 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6424 ++vcpu->stat.insn_emulation;
1d2887e2 6425 if (r != EMULATION_OK) {
4005996e
AK		 6426 if (emulation_type & EMULTYPE_TRAP_UD)
6427 return EMULATE_FAIL;
991eebf9
GN		 6428 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6429 emulation_type))
bbd9b64e 6430 return EMULATE_DONE;
6ea6e843
PB		 6431 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6432 return EMULATE_DONE;
6d77dbfc
GN		 6433 if (emulation_type & EMULTYPE_SKIP)
6434 return EMULATE_FAIL;
e2366171 6435 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6436 }
6437 }
6438
04789b66
LA		 6439 if ((emulation_type & EMULTYPE_VMWARE) &&
6440 !is_vmware_backdoor_opcode(ctxt))
6441 return EMULATE_FAIL;
6442
ba8afb6b 6443 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6444 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6445 if (ctxt->eflags & X86_EFLAGS_RF)
6446 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6447 return EMULATE_DONE;
6448 }
6449
1cb3f3ae
XG		 6450 if (retry_instruction(ctxt, cr2, emulation_type))
6451 return EMULATE_DONE;
6452
7ae441ea 6453 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6454 changes registers values during IO operation */
7ae441ea
GN		 6455 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6456 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6457 emulator_invalidate_register_cache(ctxt);
7ae441ea 6458 }
4d2179e1 6459
5cd21917 6460restart:
0f89b207
TL		 6461 /* Save the faulting GPA (cr2) in the address field */
6462 ctxt->exception.address = cr2;
6463
9d74191a 6464 r = x86_emulate_insn(ctxt);
bbd9b64e 6465
775fde86
JR		 6466 if (r == EMULATION_INTERCEPTED)
6467 return EMULATE_DONE;
6468
d2ddd1c4 6469 if (r == EMULATION_FAILED) {
991eebf9
GN		 6470 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6471 emulation_type))
c3cd7ffa
GN		 6472 return EMULATE_DONE;
6473
e2366171 6474 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6475 }
6476
9d74191a 6477 if (ctxt->have_exception) {
d2ddd1c4 6478 r = EMULATE_DONE;
ef54bcfe
PB		 6479 if (inject_emulated_exception(vcpu))
6480 return r;
d2ddd1c4 6481 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6482 if (!vcpu->arch.pio.in) {
6483 /* FIXME: return into emulator if single-stepping. */
3457e419 6484 vcpu->arch.pio.count = 0;
0912c977 6485 } else {
7ae441ea 6486 writeback = false;
716d51ab
GN		 6487 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6488 }
ac0a48c3 6489 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6490 } else if (vcpu->mmio_needed) {
6491 if (!vcpu->mmio_is_write)
6492 writeback = false;
ac0a48c3 6493 r = EMULATE_USER_EXIT;
716d51ab 6494 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6495 } else if (r == EMULATION_RESTART)
5cd21917 6496 goto restart;
d2ddd1c4
GN		 6497 else
6498 r = EMULATE_DONE;
f850e2e6 6499
7ae441ea 6500 if (writeback) {
6addfc42 6501 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6502 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6503 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6504 kvm_rip_write(vcpu, ctxt->eip);
5cc244a2 6505 if (r == EMULATE_DONE && ctxt->tf)
c8401dda 6506 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6507 if (!ctxt->have_exception ||
6508 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6509 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6510
6511 /*
6512 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6513 * do nothing, and it will be requested again as soon as
6514 * the shadow expires. But we still need to check here,
6515 * because POPF has no interrupt shadow.
6516 */
6517 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6518 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6519 } else
6520 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6521
6522 return r;
de7d789a 6523}
c60658d1
SC		 6524
6525int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6526{
6527 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6528}
6529EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6530
6531int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6532 void *insn, int insn_len)
6533{
6534 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6535}
6536EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6537
45def77e
SC		 6538static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6539{
6540 vcpu->arch.pio.count = 0;
6541
6542 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6543 return 1;
6544
6545 return kvm_skip_emulated_instruction(vcpu);
6546}
6547
dca7f128
SC		 6548static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6549 unsigned short port)
de7d789a 6550{
cf8f70bf 6551 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6552 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6553 size, port, &val, 1);
45def77e
SC		 6554
6555 if (!ret) {
6556 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6557 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6558 }
de7d789a
CO		 6559 return ret;
6560}
de7d789a 6561
8370c3d0
TL		 6562static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6563{
6564 unsigned long val;
6565
6566 /* We should only ever be called with arch.pio.count equal to 1 */
6567 BUG_ON(vcpu->arch.pio.count != 1);
6568
45def77e
SC		 6569 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6570 vcpu->arch.pio.count = 0;
6571 return 1;
6572 }
6573
8370c3d0
TL		 6574 /* For size less than 4 we merge, else we zero extend */
6575 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6576 : 0;
6577
6578 /*
6579 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6580 * the copy and tracing
6581 */
6582 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6583 vcpu->arch.pio.port, &val, 1);
6584 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6585
45def77e 6586 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6587}
6588
dca7f128
SC		 6589static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6590 unsigned short port)
8370c3d0
TL		 6591{
6592 unsigned long val;
6593 int ret;
6594
6595 /* For size less than 4 we merge, else we zero extend */
6596 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6597
6598 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6599 &val, 1);
6600 if (ret) {
6601 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6602 return ret;
6603 }
6604
45def77e 6605 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6606 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6607
6608 return 0;
6609}
dca7f128
SC		 6610
6611int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6612{
45def77e 6613 int ret;
dca7f128 6614
dca7f128 6615 if (in)
45def77e 6616 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6617 else
45def77e
SC		 6618 ret = kvm_fast_pio_out(vcpu, size, port);
6619 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 6620}
6621EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6622
251a5fd6 6623static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6624{
0a3aee0d 6625 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6626 return 0;
8cfdc000
ZA		 6627}
6628
6629static void tsc_khz_changed(void *data)
c8076604 6630{
8cfdc000
ZA		 6631 struct cpufreq_freqs *freq = data;
6632 unsigned long khz = 0;
6633
6634 if (data)
6635 khz = freq->new;
6636 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6637 khz = cpufreq_quick_get(raw_smp_processor_id());
6638 if (!khz)
6639 khz = tsc_khz;
0a3aee0d 6640 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6641}
6642
5fa4ec9c 6643#ifdef CONFIG_X86_64
0092e434
VK		 6644static void kvm_hyperv_tsc_notifier(void)
6645{
0092e434
VK		 6646 struct kvm *kvm;
6647 struct kvm_vcpu *vcpu;
6648 int cpu;
6649
6650 spin_lock(&kvm_lock);
6651 list_for_each_entry(kvm, &vm_list, vm_list)
6652 kvm_make_mclock_inprogress_request(kvm);
6653
6654 hyperv_stop_tsc_emulation();
6655
6656 /* TSC frequency always matches when on Hyper-V */
6657 for_each_present_cpu(cpu)
6658 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6659 kvm_max_guest_tsc_khz = tsc_khz;
6660
6661 list_for_each_entry(kvm, &vm_list, vm_list) {
6662 struct kvm_arch *ka = &kvm->arch;
6663
6664 spin_lock(&ka->pvclock_gtod_sync_lock);
6665
6666 pvclock_update_vm_gtod_copy(kvm);
6667
6668 kvm_for_each_vcpu(cpu, vcpu, kvm)
6669 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6670
6671 kvm_for_each_vcpu(cpu, vcpu, kvm)
6672 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6673
6674 spin_unlock(&ka->pvclock_gtod_sync_lock);
6675 }
6676 spin_unlock(&kvm_lock);
0092e434 6677}
5fa4ec9c 6678#endif
0092e434 6679
c8076604
GH		 6680static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6681 void *data)
6682{
6683 struct cpufreq_freqs *freq = data;
6684 struct kvm *kvm;
6685 struct kvm_vcpu *vcpu;
6686 int i, send_ipi = 0;
6687
8cfdc000
ZA		 6688 /*
6689 * We allow guests to temporarily run on slowing clocks,
6690 * provided we notify them after, or to run on accelerating
6691 * clocks, provided we notify them before. Thus time never
6692 * goes backwards.
6693 *
6694 * However, we have a problem. We can't atomically update
6695 * the frequency of a given CPU from this function; it is
6696 * merely a notifier, which can be called from any CPU.
6697 * Changing the TSC frequency at arbitrary points in time
6698 * requires a recomputation of local variables related to
6699 * the TSC for each VCPU. We must flag these local variables
6700 * to be updated and be sure the update takes place with the
6701 * new frequency before any guests proceed.
6702 *
6703 * Unfortunately, the combination of hotplug CPU and frequency
6704 * change creates an intractable locking scenario; the order
6705 * of when these callouts happen is undefined with respect to
6706 * CPU hotplug, and they can race with each other. As such,
6707 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6708 * undefined; you can actually have a CPU frequency change take
6709 * place in between the computation of X and the setting of the
6710 * variable. To protect against this problem, all updates of
6711 * the per_cpu tsc_khz variable are done in an interrupt
6712 * protected IPI, and all callers wishing to update the value
6713 * must wait for a synchronous IPI to complete (which is trivial
6714 * if the caller is on the CPU already). This establishes the
6715 * necessary total order on variable updates.
6716 *
6717 * Note that because a guest time update may take place
6718 * anytime after the setting of the VCPU's request bit, the
6719 * correct TSC value must be set before the request. However,
6720 * to ensure the update actually makes it to any guest which
6721 * starts running in hardware virtualization between the set
6722 * and the acquisition of the spinlock, we must also ping the
6723 * CPU after setting the request bit.
6724 *
6725 */
6726
c8076604
GH		 6727 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6728 return 0;
6729 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6730 return 0;
8cfdc000
ZA		 6731
6732 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6733
2f303b74 6734 spin_lock(&kvm_lock);
c8076604 6735 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6736 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6737 if (vcpu->cpu != freq->cpu)
6738 continue;
c285545f 6739 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6740 if (vcpu->cpu != smp_processor_id())
8cfdc000 6741 send_ipi = 1;
c8076604
GH		 6742 }
6743 }
2f303b74 6744 spin_unlock(&kvm_lock);
c8076604
GH		 6745
6746 if (freq->old < freq->new && send_ipi) {
6747 /*
6748 * We upscale the frequency. Must make the guest
6749 * doesn't see old kvmclock values while running with
6750 * the new frequency, otherwise we risk the guest sees
6751 * time go backwards.
6752 *
6753 * In case we update the frequency for another cpu
6754 * (which might be in guest context) send an interrupt
6755 * to kick the cpu out of guest context. Next time
6756 * guest context is entered kvmclock will be updated,
6757 * so the guest will not see stale values.
6758 */
8cfdc000 6759 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6760 }
6761 return 0;
6762}
6763
6764static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6765 .notifier_call = kvmclock_cpufreq_notifier
6766};
6767
251a5fd6 6768static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6769{
251a5fd6
SAS		 6770 tsc_khz_changed(NULL);
6771 return 0;
8cfdc000
ZA		 6772}
6773
b820cc0c
ZA		 6774static void kvm_timer_init(void)
6775{
c285545f 6776 max_tsc_khz = tsc_khz;
460dd42e 6777
b820cc0c 6778 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6779#ifdef CONFIG_CPU_FREQ
6780 struct cpufreq_policy policy;
758f588d
BP		 6781 int cpu;
6782
c285545f 6783 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6784 cpu = get_cpu();
6785 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6786 if (policy.cpuinfo.max_freq)
6787 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6788 put_cpu();
c285545f 6789#endif
b820cc0c
ZA		 6790 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6791 CPUFREQ_TRANSITION_NOTIFIER);
6792 }
c285545f 6793 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6794
73c1b41e 6795 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6796 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6797}
6798
dd60d217
AK		 6799DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6800EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6801
f5132b01 6802int kvm_is_in_guest(void)
ff9d07a0 6803{
086c9855 6804 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6805}
6806
6807static int kvm_is_user_mode(void)
6808{
6809 int user_mode = 3;
dcf46b94 6810
086c9855
AS		 6811 if (__this_cpu_read(current_vcpu))
6812 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6813
ff9d07a0
ZY		 6814 return user_mode != 0;
6815}
6816
6817static unsigned long kvm_get_guest_ip(void)
6818{
6819 unsigned long ip = 0;
dcf46b94 6820
086c9855
AS		 6821 if (__this_cpu_read(current_vcpu))
6822 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6823
ff9d07a0
ZY		 6824 return ip;
6825}
6826
6827static struct perf_guest_info_callbacks kvm_guest_cbs = {
6828 .is_in_guest = kvm_is_in_guest,
6829 .is_user_mode = kvm_is_user_mode,
6830 .get_guest_ip = kvm_get_guest_ip,
6831};
6832
ce88decf
XG		 6833static void kvm_set_mmio_spte_mask(void)
6834{
6835 u64 mask;
6836 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6837
6838 /*
6839 * Set the reserved bits and the present bit of an paging-structure
6840 * entry to generate page fault with PFER.RSV = 1.
6841 */
28a1f3ac
JS		 6842
6843 /*
6844 * Mask the uppermost physical address bit, which would be reserved as
6845 * long as the supported physical address width is less than 52.
6846 */
6847 mask = 1ull << 51;
885032b9 6848
885032b9 6849 /* Set the present bit. */
ce88decf
XG		 6850 mask |= 1ull;
6851
ce88decf
XG		 6852 /*
6853 * If reserved bit is not supported, clear the present bit to disable
6854 * mmio page fault.
6855 */
7288bde1 6856 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
ce88decf 6857 mask &= ~1ull;
ce88decf 6858
dcdca5fe 6859 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6860}
6861
16e8d74d
MT		 6862#ifdef CONFIG_X86_64
6863static void pvclock_gtod_update_fn(struct work_struct *work)
6864{
d828199e
MT		 6865 struct kvm *kvm;
6866
6867 struct kvm_vcpu *vcpu;
6868 int i;
6869
2f303b74 6870 spin_lock(&kvm_lock);
d828199e
MT		 6871 list_for_each_entry(kvm, &vm_list, vm_list)
6872 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6873 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6874 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6875 spin_unlock(&kvm_lock);
16e8d74d
MT		 6876}
6877
6878static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6879
6880/*
6881 * Notification about pvclock gtod data update.
6882 */
6883static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6884 void *priv)
6885{
6886 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6887 struct timekeeper *tk = priv;
6888
6889 update_pvclock_gtod(tk);
6890
6891 /* disable master clock if host does not trust, or does not
b0c39dc6 6892 * use, TSC based clocksource.
16e8d74d 6893 */
b0c39dc6 6894 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6895 atomic_read(&kvm_guest_has_master_clock) != 0)
6896 queue_work(system_long_wq, &pvclock_gtod_work);
6897
6898 return 0;
6899}
6900
6901static struct notifier_block pvclock_gtod_notifier = {
6902 .notifier_call = pvclock_gtod_notify,
6903};
6904#endif
6905
f8c16bba 6906int kvm_arch_init(void *opaque)
043405e1 6907{
b820cc0c 6908 int r;
6b61edf7 6909 struct kvm_x86_ops *ops = opaque;
f8c16bba 6910
f8c16bba
ZX		 6911 if (kvm_x86_ops) {
6912 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6913 r = -EEXIST;
6914 goto out;
f8c16bba
ZX		 6915 }
6916
6917 if (!ops->cpu_has_kvm_support()) {
6918 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6919 r = -EOPNOTSUPP;
6920 goto out;
f8c16bba
ZX		 6921 }
6922 if (ops->disabled_by_bios()) {
6923 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6924 r = -EOPNOTSUPP;
6925 goto out;
f8c16bba
ZX		 6926 }
6927
b666a4b6
MO		 6928 /*
6929 * KVM explicitly assumes that the guest has an FPU and
6930 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
6931 * vCPU's FPU state as a fxregs_state struct.
6932 */
6933 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
6934 printk(KERN_ERR "kvm: inadequate fpu\n");
6935 r = -EOPNOTSUPP;
6936 goto out;
6937 }
6938
013f6a5d 6939 r = -ENOMEM;
ed8e4812 6940 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 6941 __alignof__(struct fpu), SLAB_ACCOUNT,
6942 NULL);
6943 if (!x86_fpu_cache) {
6944 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
6945 goto out;
6946 }
6947
013f6a5d
MT		 6948 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6949 if (!shared_msrs) {
6950 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 6951 goto out_free_x86_fpu_cache;
013f6a5d
MT		 6952 }
6953
97db56ce
AK		 6954 r = kvm_mmu_module_init();
6955 if (r)
013f6a5d 6956 goto out_free_percpu;
97db56ce 6957
ce88decf 6958 kvm_set_mmio_spte_mask();
97db56ce 6959
f8c16bba 6960 kvm_x86_ops = ops;
920c8377 6961
7b52345e 6962 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6963 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6964 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6965 kvm_timer_init();
c8076604 6966
ff9d07a0
ZY		 6967 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6968
d366bf7e 6969 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6970 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6971
c5cc421b 6972 kvm_lapic_init();
16e8d74d
MT		 6973#ifdef CONFIG_X86_64
6974 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6975
5fa4ec9c 6976 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6977 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6978#endif
6979
f8c16bba 6980 return 0;
56c6d28a 6981
013f6a5d
MT		 6982out_free_percpu:
6983 free_percpu(shared_msrs);
b666a4b6
MO		 6984out_free_x86_fpu_cache:
6985 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 6986out:
56c6d28a 6987 return r;
043405e1 6988}
8776e519 6989
f8c16bba
ZX		 6990void kvm_arch_exit(void)
6991{
0092e434 6992#ifdef CONFIG_X86_64
5fa4ec9c 6993 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6994 clear_hv_tscchange_cb();
6995#endif
cef84c30 6996 kvm_lapic_exit();
ff9d07a0
ZY		 6997 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6998
888d256e
JK		 6999 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7000 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7001 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7002 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7003#ifdef CONFIG_X86_64
7004 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7005#endif
f8c16bba 7006 kvm_x86_ops = NULL;
56c6d28a 7007 kvm_mmu_module_exit();
013f6a5d 7008 free_percpu(shared_msrs);
b666a4b6 7009 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7010}
f8c16bba 7011
5cb56059 7012int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7013{
7014 ++vcpu->stat.halt_exits;
35754c98 7015 if (lapic_in_kernel(vcpu)) {
a4535290 7016 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7017 return 1;
7018 } else {
7019 vcpu->run->exit_reason = KVM_EXIT_HLT;
7020 return 0;
7021 }
7022}
5cb56059
JS		 7023EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7024
7025int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7026{
6affcbed
KH		 7027 int ret = kvm_skip_emulated_instruction(vcpu);
7028 /*
7029 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7030 * KVM_EXIT_DEBUG here.
7031 */
7032 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7033}
8776e519
HB		 7034EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7035
8ef81a9a 7036#ifdef CONFIG_X86_64
55dd00a7
MT		 7037static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7038 unsigned long clock_type)
7039{
7040 struct kvm_clock_pairing clock_pairing;
899a31f5 7041 struct timespec64 ts;
80fbd89c 7042 u64 cycle;
55dd00a7
MT		 7043 int ret;
7044
7045 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7046 return -KVM_EOPNOTSUPP;
7047
7048 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7049 return -KVM_EOPNOTSUPP;
7050
7051 clock_pairing.sec = ts.tv_sec;
7052 clock_pairing.nsec = ts.tv_nsec;
7053 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7054 clock_pairing.flags = 0;
bcbfbd8e 7055 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7056
7057 ret = 0;
7058 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7059 sizeof(struct kvm_clock_pairing)))
7060 ret = -KVM_EFAULT;
7061
7062 return ret;
7063}
8ef81a9a 7064#endif
55dd00a7 7065
6aef266c
SV		 7066/*
7067 * kvm_pv_kick_cpu_op: Kick a vcpu.
7068 *
7069 * @apicid - apicid of vcpu to be kicked.
7070 */
7071static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7072{
24d2166b 7073 struct kvm_lapic_irq lapic_irq;
6aef266c 7074
24d2166b
R		 7075 lapic_irq.shorthand = 0;
7076 lapic_irq.dest_mode = 0;
ebd28fcb 7077 lapic_irq.level = 0;
24d2166b 7078 lapic_irq.dest_id = apicid;
93bbf0b8 7079 lapic_irq.msi_redir_hint = false;
6aef266c 7080
24d2166b 7081 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7082 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7083}
7084
d62caabb
AS		 7085void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7086{
f7589cca
PB		 7087 if (!lapic_in_kernel(vcpu)) {
7088 WARN_ON_ONCE(vcpu->arch.apicv_active);
7089 return;
7090 }
7091 if (!vcpu->arch.apicv_active)
7092 return;
7093
d62caabb
AS		 7094 vcpu->arch.apicv_active = false;
7095 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7096}
7097
8776e519
HB		 7098int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7099{
7100 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7101 int op_64_bit;
8776e519 7102
696ca779
RK		 7103 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7104 return kvm_hv_hypercall(vcpu);
55cd8e5a 7105
5fdbf976
MT		 7106 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
7107 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
7108 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
7109 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
7110 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 7111
229456fc 7112 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7113
a449c7aa
NA		 7114 op_64_bit = is_64_bit_mode(vcpu);
7115 if (!op_64_bit) {
8776e519
HB		 7116 nr &= 0xFFFFFFFF;
7117 a0 &= 0xFFFFFFFF;
7118 a1 &= 0xFFFFFFFF;
7119 a2 &= 0xFFFFFFFF;
7120 a3 &= 0xFFFFFFFF;
7121 }
7122
07708c4a
JK		 7123 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7124 ret = -KVM_EPERM;
696ca779 7125 goto out;
07708c4a
JK		 7126 }
7127
8776e519 7128 switch (nr) {
b93463aa
AK		 7129 case KVM_HC_VAPIC_POLL_IRQ:
7130 ret = 0;
7131 break;
6aef266c
SV		 7132 case KVM_HC_KICK_CPU:
7133 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7134 ret = 0;
7135 break;
8ef81a9a 7136#ifdef CONFIG_X86_64
55dd00a7
MT		 7137 case KVM_HC_CLOCK_PAIRING:
7138 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7139 break;
1ed199a4 7140#endif
4180bf1b
WL		 7141 case KVM_HC_SEND_IPI:
7142 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7143 break;
8776e519
HB		 7144 default:
7145 ret = -KVM_ENOSYS;
7146 break;
7147 }
696ca779 7148out:
a449c7aa
NA		 7149 if (!op_64_bit)
7150 ret = (u32)ret;
5fdbf976 7151 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 7152
f11c3a8d 7153 ++vcpu->stat.hypercalls;
6356ee0c 7154 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7155}
7156EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7157
b6785def 7158static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7159{
d6aa1000 7160 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7161 char instruction[3];
5fdbf976 7162 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7163
8776e519 7164 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7165
ce2e852e
DV		 7166 return emulator_write_emulated(ctxt, rip, instruction, 3,
7167 &ctxt->exception);
8776e519
HB		 7168}
7169
851ba692 7170static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7171{
782d422b
MG		 7172 return vcpu->run->request_interrupt_window &&
7173 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7174}
7175
851ba692 7176static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7177{
851ba692
AK		 7178 struct kvm_run *kvm_run = vcpu->run;
7179
91586a3b 7180 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7181 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7182 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7183 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7184 kvm_run->ready_for_interrupt_injection =
7185 pic_in_kernel(vcpu->kvm) ||
782d422b 7186 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7187}
7188
95ba8273
GN		 7189static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7190{
7191 int max_irr, tpr;
7192
7193 if (!kvm_x86_ops->update_cr8_intercept)
7194 return;
7195
bce87cce 7196 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7197 return;
7198
d62caabb
AS		 7199 if (vcpu->arch.apicv_active)
7200 return;
7201
8db3baa2
GN		 7202 if (!vcpu->arch.apic->vapic_addr)
7203 max_irr = kvm_lapic_find_highest_irr(vcpu);
7204 else
7205 max_irr = -1;
95ba8273
GN		 7206
7207 if (max_irr != -1)
7208 max_irr >>= 4;
7209
7210 tpr = kvm_lapic_get_cr8(vcpu);
7211
7212 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7213}
7214
b6b8a145 7215static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7216{
b6b8a145
JK		 7217 int r;
7218
95ba8273 7219 /* try to reinject previous events if any */
664f8e26 7220
1a680e35
LA		 7221 if (vcpu->arch.exception.injected)
7222 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7223 /*
a042c26f
LA		 7224 * Do not inject an NMI or interrupt if there is a pending
7225 * exception. Exceptions and interrupts are recognized at
7226 * instruction boundaries, i.e. the start of an instruction.
7227 * Trap-like exceptions, e.g. #DB, have higher priority than
7228 * NMIs and interrupts, i.e. traps are recognized before an
7229 * NMI/interrupt that's pending on the same instruction.
7230 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7231 * priority, but are only generated (pended) during instruction
7232 * execution, i.e. a pending fault-like exception means the
7233 * fault occurred on the *previous* instruction and must be
7234 * serviced prior to recognizing any new events in order to
7235 * fully complete the previous instruction.
664f8e26 7236 */
1a680e35
LA		 7237 else if (!vcpu->arch.exception.pending) {
7238 if (vcpu->arch.nmi_injected)
664f8e26 7239 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7240 else if (vcpu->arch.interrupt.injected)
664f8e26 7241 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7242 }
7243
1a680e35
LA		 7244 /*
7245 * Call check_nested_events() even if we reinjected a previous event
7246 * in order for caller to determine if it should require immediate-exit
7247 * from L2 to L1 due to pending L1 events which require exit
7248 * from L2 to L1.
7249 */
664f8e26
WL		 7250 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7251 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7252 if (r != 0)
7253 return r;
7254 }
7255
7256 /* try to inject new event if pending */
b59bb7bd 7257 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7258 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7259 vcpu->arch.exception.has_error_code,
7260 vcpu->arch.exception.error_code);
d6e8c854 7261
1a680e35 7262 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7263 vcpu->arch.exception.pending = false;
7264 vcpu->arch.exception.injected = true;
7265
d6e8c854
NA		 7266 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7267 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7268 X86_EFLAGS_RF);
7269
f10c729f
JM		 7270 if (vcpu->arch.exception.nr == DB_VECTOR) {
7271 /*
7272 * This code assumes that nSVM doesn't use
7273 * check_nested_events(). If it does, the
7274 * DR6/DR7 changes should happen before L1
7275 * gets a #VMEXIT for an intercepted #DB in
7276 * L2. (Under VMX, on the other hand, the
7277 * DR6/DR7 changes should not happen in the
7278 * event of a VM-exit to L1 for an intercepted
7279 * #DB in L2.)
7280 */
7281 kvm_deliver_exception_payload(vcpu);
7282 if (vcpu->arch.dr7 & DR7_GD) {
7283 vcpu->arch.dr7 &= ~DR7_GD;
7284 kvm_update_dr7(vcpu);
7285 }
6bdf0662
NA		 7286 }
7287
cfcd20e5 7288 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7289 }
7290
7291 /* Don't consider new event if we re-injected an event */
7292 if (kvm_event_needs_reinjection(vcpu))
7293 return 0;
7294
7295 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7296 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7297 vcpu->arch.smi_pending = false;
52797bf9 7298 ++vcpu->arch.smi_count;
ee2cd4b7 7299 enter_smm(vcpu);
c43203ca 7300 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7301 --vcpu->arch.nmi_pending;
7302 vcpu->arch.nmi_injected = true;
7303 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7304 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7305 /*
7306 * Because interrupts can be injected asynchronously, we are
7307 * calling check_nested_events again here to avoid a race condition.
7308 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7309 * proposal and current concerns. Perhaps we should be setting
7310 * KVM_REQ_EVENT only on certain events and not unconditionally?
7311 */
7312 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7313 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7314 if (r != 0)
7315 return r;
7316 }
95ba8273 7317 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7318 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7319 false);
7320 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7321 }
7322 }
ee2cd4b7 7323
b6b8a145 7324 return 0;
95ba8273
GN		 7325}
7326
7460fb4a
AK		 7327static void process_nmi(struct kvm_vcpu *vcpu)
7328{
7329 unsigned limit = 2;
7330
7331 /*
7332 * x86 is limited to one NMI running, and one NMI pending after it.
7333 * If an NMI is already in progress, limit further NMIs to just one.
7334 * Otherwise, allow two (and we'll inject the first one immediately).
7335 */
7336 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7337 limit = 1;
7338
7339 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7340 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7341 kvm_make_request(KVM_REQ_EVENT, vcpu);
7342}
7343
ee2cd4b7 7344static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7345{
7346 u32 flags = 0;
7347 flags |= seg->g << 23;
7348 flags |= seg->db << 22;
7349 flags |= seg->l << 21;
7350 flags |= seg->avl << 20;
7351 flags |= seg->present << 15;
7352 flags |= seg->dpl << 13;
7353 flags |= seg->s << 12;
7354 flags |= seg->type << 8;
7355 return flags;
7356}
7357
ee2cd4b7 7358static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7359{
7360 struct kvm_segment seg;
7361 int offset;
7362
7363 kvm_get_segment(vcpu, &seg, n);
7364 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7365
7366 if (n < 3)
7367 offset = 0x7f84 + n * 12;
7368 else
7369 offset = 0x7f2c + (n - 3) * 12;
7370
7371 put_smstate(u32, buf, offset + 8, seg.base);
7372 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7373 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7374}
7375
efbb288a 7376#ifdef CONFIG_X86_64
ee2cd4b7 7377static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7378{
7379 struct kvm_segment seg;
7380 int offset;
7381 u16 flags;
7382
7383 kvm_get_segment(vcpu, &seg, n);
7384 offset = 0x7e00 + n * 16;
7385
ee2cd4b7 7386 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7387 put_smstate(u16, buf, offset, seg.selector);
7388 put_smstate(u16, buf, offset + 2, flags);
7389 put_smstate(u32, buf, offset + 4, seg.limit);
7390 put_smstate(u64, buf, offset + 8, seg.base);
7391}
efbb288a 7392#endif
660a5d51 7393
ee2cd4b7 7394static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7395{
7396 struct desc_ptr dt;
7397 struct kvm_segment seg;
7398 unsigned long val;
7399 int i;
7400
7401 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7402 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7403 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7404 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7405
7406 for (i = 0; i < 8; i++)
7407 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7408
7409 kvm_get_dr(vcpu, 6, &val);
7410 put_smstate(u32, buf, 0x7fcc, (u32)val);
7411 kvm_get_dr(vcpu, 7, &val);
7412 put_smstate(u32, buf, 0x7fc8, (u32)val);
7413
7414 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7415 put_smstate(u32, buf, 0x7fc4, seg.selector);
7416 put_smstate(u32, buf, 0x7f64, seg.base);
7417 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7418 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7419
7420 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7421 put_smstate(u32, buf, 0x7fc0, seg.selector);
7422 put_smstate(u32, buf, 0x7f80, seg.base);
7423 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7424 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7425
7426 kvm_x86_ops->get_gdt(vcpu, &dt);
7427 put_smstate(u32, buf, 0x7f74, dt.address);
7428 put_smstate(u32, buf, 0x7f70, dt.size);
7429
7430 kvm_x86_ops->get_idt(vcpu, &dt);
7431 put_smstate(u32, buf, 0x7f58, dt.address);
7432 put_smstate(u32, buf, 0x7f54, dt.size);
7433
7434 for (i = 0; i < 6; i++)
ee2cd4b7 7435 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7436
7437 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7438
7439 /* revision id */
7440 put_smstate(u32, buf, 0x7efc, 0x00020000);
7441 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7442}
7443
ee2cd4b7 7444static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7445{
7446#ifdef CONFIG_X86_64
7447 struct desc_ptr dt;
7448 struct kvm_segment seg;
7449 unsigned long val;
7450 int i;
7451
7452 for (i = 0; i < 16; i++)
7453 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7454
7455 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7456 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7457
7458 kvm_get_dr(vcpu, 6, &val);
7459 put_smstate(u64, buf, 0x7f68, val);
7460 kvm_get_dr(vcpu, 7, &val);
7461 put_smstate(u64, buf, 0x7f60, val);
7462
7463 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7464 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7465 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7466
7467 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7468
7469 /* revision id */
7470 put_smstate(u32, buf, 0x7efc, 0x00020064);
7471
7472 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7473
7474 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7475 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7476 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7477 put_smstate(u32, buf, 0x7e94, seg.limit);
7478 put_smstate(u64, buf, 0x7e98, seg.base);
7479
7480 kvm_x86_ops->get_idt(vcpu, &dt);
7481 put_smstate(u32, buf, 0x7e84, dt.size);
7482 put_smstate(u64, buf, 0x7e88, dt.address);
7483
7484 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7485 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7486 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7487 put_smstate(u32, buf, 0x7e74, seg.limit);
7488 put_smstate(u64, buf, 0x7e78, seg.base);
7489
7490 kvm_x86_ops->get_gdt(vcpu, &dt);
7491 put_smstate(u32, buf, 0x7e64, dt.size);
7492 put_smstate(u64, buf, 0x7e68, dt.address);
7493
7494 for (i = 0; i < 6; i++)
ee2cd4b7 7495 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7496#else
7497 WARN_ON_ONCE(1);
7498#endif
7499}
7500
ee2cd4b7 7501static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7502{
660a5d51 7503 struct kvm_segment cs, ds;
18c3626e 7504 struct desc_ptr dt;
660a5d51
PB		 7505 char buf[512];
7506 u32 cr0;
7507
660a5d51 7508 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7509 memset(buf, 0, 512);
d6321d49 7510 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7511 enter_smm_save_state_64(vcpu, buf);
660a5d51 7512 else
ee2cd4b7 7513 enter_smm_save_state_32(vcpu, buf);
660a5d51 7514
0234bf88
LP		 7515 /*
7516 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7517 * vCPU state (e.g. leave guest mode) after we've saved the state into
7518 * the SMM state-save area.
7519 */
7520 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7521
7522 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7523 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7524
7525 if (kvm_x86_ops->get_nmi_mask(vcpu))
7526 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7527 else
7528 kvm_x86_ops->set_nmi_mask(vcpu, true);
7529
7530 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7531 kvm_rip_write(vcpu, 0x8000);
7532
7533 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7534 kvm_x86_ops->set_cr0(vcpu, cr0);
7535 vcpu->arch.cr0 = cr0;
7536
7537 kvm_x86_ops->set_cr4(vcpu, 0);
7538
18c3626e
PB		 7539 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7540 dt.address = dt.size = 0;
7541 kvm_x86_ops->set_idt(vcpu, &dt);
7542
660a5d51
PB		 7543 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7544
7545 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7546 cs.base = vcpu->arch.smbase;
7547
7548 ds.selector = 0;
7549 ds.base = 0;
7550
7551 cs.limit = ds.limit = 0xffffffff;
7552 cs.type = ds.type = 0x3;
7553 cs.dpl = ds.dpl = 0;
7554 cs.db = ds.db = 0;
7555 cs.s = ds.s = 1;
7556 cs.l = ds.l = 0;
7557 cs.g = ds.g = 1;
7558 cs.avl = ds.avl = 0;
7559 cs.present = ds.present = 1;
7560 cs.unusable = ds.unusable = 0;
7561 cs.padding = ds.padding = 0;
7562
7563 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7564 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7565 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7566 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7567 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7568 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7569
d6321d49 7570 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7571 kvm_x86_ops->set_efer(vcpu, 0);
7572
7573 kvm_update_cpuid(vcpu);
7574 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7575}
7576
ee2cd4b7 7577static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7578{
7579 vcpu->arch.smi_pending = true;
7580 kvm_make_request(KVM_REQ_EVENT, vcpu);
7581}
7582
2860c4b1
PB		 7583void kvm_make_scan_ioapic_request(struct kvm *kvm)
7584{
7585 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7586}
7587
3d81bc7e 7588static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7589{
dcbd3e49 7590 if (!kvm_apic_present(vcpu))
3d81bc7e 7591 return;
c7c9c56c 7592
6308630b 7593 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7594
b053b2ae 7595 if (irqchip_split(vcpu->kvm))
6308630b 7596 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7597 else {
fa59cc00 7598 if (vcpu->arch.apicv_active)
d62caabb 7599 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7600 if (ioapic_in_kernel(vcpu->kvm))
7601 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7602 }
e40ff1d6
LA		 7603
7604 if (is_guest_mode(vcpu))
7605 vcpu->arch.load_eoi_exitmap_pending = true;
7606 else
7607 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7608}
7609
7610static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7611{
7612 u64 eoi_exit_bitmap[4];
7613
7614 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7615 return;
7616
5c919412
AS		 7617 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7618 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7619 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7620}
7621
93065ac7
MH		 7622int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7623 unsigned long start, unsigned long end,
7624 bool blockable)
b1394e74
RK		 7625{
7626 unsigned long apic_address;
7627
7628 /*
7629 * The physical address of apic access page is stored in the VMCS.
7630 * Update it when it becomes invalid.
7631 */
7632 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7633 if (start <= apic_address && apic_address < end)
7634 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7635
7636 return 0;
b1394e74
RK		 7637}
7638
4256f43f
TC		 7639void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7640{
c24ae0dc
TC		 7641 struct page *page = NULL;
7642
35754c98 7643 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7644 return;
7645
4256f43f
TC		 7646 if (!kvm_x86_ops->set_apic_access_page_addr)
7647 return;
7648
c24ae0dc 7649 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7650 if (is_error_page(page))
7651 return;
c24ae0dc
TC		 7652 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7653
7654 /*
7655 * Do not pin apic access page in memory, the MMU notifier
7656 * will call us again if it is migrated or swapped out.
7657 */
7658 put_page(page);
4256f43f
TC		 7659}
7660EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7661
d264ee0c
SC		 7662void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7663{
7664 smp_send_reschedule(vcpu->cpu);
7665}
7666EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7667
9357d939 7668/*
362c698f 7669 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7670 * exiting to the userspace. Otherwise, the value will be returned to the
7671 * userspace.
7672 */
851ba692 7673static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7674{
7675 int r;
62a193ed
MG		 7676 bool req_int_win =
7677 dm_request_for_irq_injection(vcpu) &&
7678 kvm_cpu_accept_dm_intr(vcpu);
7679
730dca42 7680 bool req_immediate_exit = false;
b6c7a5dc 7681
2fa6e1e1 7682 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7683 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7684 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7685 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7686 kvm_mmu_unload(vcpu);
a8eeb04a 7687 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7688 __kvm_migrate_timers(vcpu);
d828199e
MT		 7689 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7690 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7691 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7692 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7693 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7694 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7695 if (unlikely(r))
7696 goto out;
7697 }
a8eeb04a 7698 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7699 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7700 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7701 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7702 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7703 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7704 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7705 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7706 r = 0;
7707 goto out;
7708 }
a8eeb04a 7709 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7710 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7711 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7712 r = 0;
7713 goto out;
7714 }
af585b92
GN		 7715 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7716 /* Page is swapped out. Do synthetic halt */
7717 vcpu->arch.apf.halted = true;
7718 r = 1;
7719 goto out;
7720 }
c9aaa895
GC		 7721 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7722 record_steal_time(vcpu);
64d60670
PB		 7723 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7724 process_smi(vcpu);
7460fb4a
AK		 7725 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7726 process_nmi(vcpu);
f5132b01 7727 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7728 kvm_pmu_handle_event(vcpu);
f5132b01 7729 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7730 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7731 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7732 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7733 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7734 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7735 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7736 vcpu->run->eoi.vector =
7737 vcpu->arch.pending_ioapic_eoi;
7738 r = 0;
7739 goto out;
7740 }
7741 }
3d81bc7e
YZ		 7742 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7743 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7744 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7745 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7746 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7747 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7748 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7749 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7750 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7751 r = 0;
7752 goto out;
7753 }
e516cebb
AS		 7754 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7755 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7756 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7757 r = 0;
7758 goto out;
7759 }
db397571
AS		 7760 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7761 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7762 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7763 r = 0;
7764 goto out;
7765 }
f3b138c5
AS		 7766
7767 /*
7768 * KVM_REQ_HV_STIMER has to be processed after
7769 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7770 * depend on the guest clock being up-to-date
7771 */
1f4b34f8
AS		 7772 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7773 kvm_hv_process_stimers(vcpu);
2f52d58c 7774 }
b93463aa 7775
b463a6f7 7776 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7777 ++vcpu->stat.req_event;
66450a21
JK		 7778 kvm_apic_accept_events(vcpu);
7779 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7780 r = 1;
7781 goto out;
7782 }
7783
b6b8a145
JK		 7784 if (inject_pending_event(vcpu, req_int_win) != 0)
7785 req_immediate_exit = true;
321c5658 7786 else {
cc3d967f 7787 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7788 *
cc3d967f
LP		 7789 * SMIs have three cases:
7790 * 1) They can be nested, and then there is nothing to
7791 * do here because RSM will cause a vmexit anyway.
7792 * 2) There is an ISA-specific reason why SMI cannot be
7793 * injected, and the moment when this changes can be
7794 * intercepted.
7795 * 3) Or the SMI can be pending because
7796 * inject_pending_event has completed the injection
7797 * of an IRQ or NMI from the previous vmexit, and
7798 * then we request an immediate exit to inject the
7799 * SMI.
c43203ca
PB		 7800 */
7801 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7802 if (!kvm_x86_ops->enable_smi_window(vcpu))
7803 req_immediate_exit = true;
321c5658
YS		 7804 if (vcpu->arch.nmi_pending)
7805 kvm_x86_ops->enable_nmi_window(vcpu);
7806 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7807 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7808 WARN_ON(vcpu->arch.exception.pending);
321c5658 7809 }
b463a6f7
AK		 7810
7811 if (kvm_lapic_enabled(vcpu)) {
7812 update_cr8_intercept(vcpu);
7813 kvm_lapic_sync_to_vapic(vcpu);
7814 }
7815 }
7816
d8368af8
AK		 7817 r = kvm_mmu_reload(vcpu);
7818 if (unlikely(r)) {
d905c069 7819 goto cancel_injection;
d8368af8
AK		 7820 }
7821
b6c7a5dc
HB		 7822 preempt_disable();
7823
7824 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7825
7826 /*
7827 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7828 * IPI are then delayed after guest entry, which ensures that they
7829 * result in virtual interrupt delivery.
7830 */
7831 local_irq_disable();
6b7e2d09
XG		 7832 vcpu->mode = IN_GUEST_MODE;
7833
01b71917
MT		 7834 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7835
0f127d12 7836 /*
b95234c8 7837 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7838 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 7839 *
81b01667 7840 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 7841 * pairs with the memory barrier implicit in pi_test_and_set_on
7842 * (see vmx_deliver_posted_interrupt).
7843 *
7844 * 3) This also orders the write to mode from any reads to the page
7845 * tables done while the VCPU is running. Please see the comment
7846 * in kvm_flush_remote_tlbs.
6b7e2d09 7847 */
01b71917 7848 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7849
b95234c8
PB		 7850 /*
7851 * This handles the case where a posted interrupt was
7852 * notified with kvm_vcpu_kick.
7853 */
fa59cc00
LA		 7854 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7855 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7856
2fa6e1e1 7857 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7858 || need_resched() || signal_pending(current)) {
6b7e2d09 7859 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7860 smp_wmb();
6c142801
AK		 7861 local_irq_enable();
7862 preempt_enable();
01b71917 7863 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7864 r = 1;
d905c069 7865 goto cancel_injection;
6c142801
AK		 7866 }
7867
fc5b7f3b
DM		 7868 kvm_load_guest_xcr0(vcpu);
7869
c43203ca
PB		 7870 if (req_immediate_exit) {
7871 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7872 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7873 }
d6185f20 7874
8b89fe1f 7875 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7876 if (lapic_timer_advance_ns)
7877 wait_lapic_expire(vcpu);
6edaa530 7878 guest_enter_irqoff();
b6c7a5dc 7879
42dbaa5a 7880 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7881 set_debugreg(0, 7);
7882 set_debugreg(vcpu->arch.eff_db[0], 0);
7883 set_debugreg(vcpu->arch.eff_db[1], 1);
7884 set_debugreg(vcpu->arch.eff_db[2], 2);
7885 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7886 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7887 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7888 }
b6c7a5dc 7889
851ba692 7890 kvm_x86_ops->run(vcpu);
b6c7a5dc 7891
c77fb5fe
PB		 7892 /*
7893 * Do this here before restoring debug registers on the host. And
7894 * since we do this before handling the vmexit, a DR access vmexit
7895 * can (a) read the correct value of the debug registers, (b) set
7896 * KVM_DEBUGREG_WONT_EXIT again.
7897 */
7898 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7899 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7900 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7901 kvm_update_dr0123(vcpu);
7902 kvm_update_dr6(vcpu);
7903 kvm_update_dr7(vcpu);
7904 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7905 }
7906
24f1e32c
FW		 7907 /*
7908 * If the guest has used debug registers, at least dr7
7909 * will be disabled while returning to the host.
7910 * If we don't have active breakpoints in the host, we don't
7911 * care about the messed up debug address registers. But if
7912 * we have some of them active, restore the old state.
7913 */
59d8eb53 7914 if (hw_breakpoint_active())
24f1e32c 7915 hw_breakpoint_restore();
42dbaa5a 7916
4ba76538 7917 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7918
6b7e2d09 7919 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7920 smp_wmb();
a547c6db 7921
fc5b7f3b
DM		 7922 kvm_put_guest_xcr0(vcpu);
7923
dd60d217 7924 kvm_before_interrupt(vcpu);
a547c6db 7925 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7926 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7927
7928 ++vcpu->stat.exits;
7929
f2485b3e 7930 guest_exit_irqoff();
b6c7a5dc 7931
f2485b3e 7932 local_irq_enable();
b6c7a5dc
HB		 7933 preempt_enable();
7934
f656ce01 7935 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7936
b6c7a5dc
HB		 7937 /*
7938 * Profile KVM exit RIPs:
7939 */
7940 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7941 unsigned long rip = kvm_rip_read(vcpu);
7942 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7943 }
7944
cc578287
ZA		 7945 if (unlikely(vcpu->arch.tsc_always_catchup))
7946 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7947
5cfb1d5a
MT		 7948 if (vcpu->arch.apic_attention)
7949 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7950
618232e2 7951 vcpu->arch.gpa_available = false;
851ba692 7952 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7953 return r;
7954
7955cancel_injection:
7956 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7957 if (unlikely(vcpu->arch.apic_attention))
7958 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7959out:
7960 return r;
7961}
b6c7a5dc 7962
362c698f
PB		 7963static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7964{
bf9f6ac8
FW		 7965 if (!kvm_arch_vcpu_runnable(vcpu) &&
7966 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7967 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7968 kvm_vcpu_block(vcpu);
7969 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7970
7971 if (kvm_x86_ops->post_block)
7972 kvm_x86_ops->post_block(vcpu);
7973
9c8fd1ba
PB		 7974 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7975 return 1;
7976 }
362c698f
PB		 7977
7978 kvm_apic_accept_events(vcpu);
7979 switch(vcpu->arch.mp_state) {
7980 case KVM_MP_STATE_HALTED:
7981 vcpu->arch.pv.pv_unhalted = false;
7982 vcpu->arch.mp_state =
7983 KVM_MP_STATE_RUNNABLE;
b2869f28 7984 /* fall through */
362c698f
PB		 7985 case KVM_MP_STATE_RUNNABLE:
7986 vcpu->arch.apf.halted = false;
7987 break;
7988 case KVM_MP_STATE_INIT_RECEIVED:
7989 break;
7990 default:
7991 return -EINTR;
7992 break;
7993 }
7994 return 1;
7995}
09cec754 7996
5d9bc648
PB		 7997static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7998{
0ad3bed6
PB		 7999 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8000 kvm_x86_ops->check_nested_events(vcpu, false);
8001
5d9bc648
PB		 8002 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8003 !vcpu->arch.apf.halted);
8004}
8005
362c698f 8006static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8007{
8008 int r;
f656ce01 8009 struct kvm *kvm = vcpu->kvm;
d7690175 8010
f656ce01 8011 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8012 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8013
362c698f 8014 for (;;) {
58f800d5 8015 if (kvm_vcpu_running(vcpu)) {
851ba692 8016 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8017 } else {
362c698f 8018 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8019 }
8020
09cec754
GN		 8021 if (r <= 0)
8022 break;
8023
72875d8a 8024 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8025 if (kvm_cpu_has_pending_timer(vcpu))
8026 kvm_inject_pending_timer_irqs(vcpu);
8027
782d422b
MG		 8028 if (dm_request_for_irq_injection(vcpu) &&
8029 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8030 r = 0;
8031 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8032 ++vcpu->stat.request_irq_exits;
362c698f 8033 break;
09cec754 8034 }
af585b92
GN		 8035
8036 kvm_check_async_pf_completion(vcpu);
8037
09cec754
GN		 8038 if (signal_pending(current)) {
8039 r = -EINTR;
851ba692 8040 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8041 ++vcpu->stat.signal_exits;
362c698f 8042 break;
09cec754
GN		 8043 }
8044 if (need_resched()) {
f656ce01 8045 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8046 cond_resched();
f656ce01 8047 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8048 }
b6c7a5dc
HB		 8049 }
8050
f656ce01 8051 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8052
8053 return r;
8054}
8055
716d51ab
GN		 8056static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8057{
8058 int r;
8059 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8060 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 8061 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8062 if (r != EMULATE_DONE)
8063 return 0;
8064 return 1;
8065}
8066
8067static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8068{
8069 BUG_ON(!vcpu->arch.pio.count);
8070
8071 return complete_emulated_io(vcpu);
8072}
8073
f78146b0
AK		 8074/*
8075 * Implements the following, as a state machine:
8076 *
8077 * read:
8078 * for each fragment
87da7e66
XG		 8079 * for each mmio piece in the fragment
8080 * write gpa, len
8081 * exit
8082 * copy data
f78146b0
AK		 8083 * execute insn
8084 *
8085 * write:
8086 * for each fragment
87da7e66
XG		 8087 * for each mmio piece in the fragment
8088 * write gpa, len
8089 * copy data
8090 * exit
f78146b0 8091 */
716d51ab 8092static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8093{
8094 struct kvm_run *run = vcpu->run;
f78146b0 8095 struct kvm_mmio_fragment *frag;
87da7e66 8096 unsigned len;
5287f194 8097
716d51ab 8098 BUG_ON(!vcpu->mmio_needed);
5287f194 8099
716d51ab 8100 /* Complete previous fragment */
87da7e66
XG		 8101 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8102 len = min(8u, frag->len);
716d51ab 8103 if (!vcpu->mmio_is_write)
87da7e66
XG		 8104 memcpy(frag->data, run->mmio.data, len);
8105
8106 if (frag->len <= 8) {
8107 /* Switch to the next fragment. */
8108 frag++;
8109 vcpu->mmio_cur_fragment++;
8110 } else {
8111 /* Go forward to the next mmio piece. */
8112 frag->data += len;
8113 frag->gpa += len;
8114 frag->len -= len;
8115 }
8116
a08d3b3b 8117 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8118 vcpu->mmio_needed = 0;
0912c977
PB		 8119
8120 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8121 if (vcpu->mmio_is_write)
716d51ab
GN		 8122 return 1;
8123 vcpu->mmio_read_completed = 1;
8124 return complete_emulated_io(vcpu);
8125 }
87da7e66 8126
716d51ab
GN		 8127 run->exit_reason = KVM_EXIT_MMIO;
8128 run->mmio.phys_addr = frag->gpa;
8129 if (vcpu->mmio_is_write)
87da7e66
XG		 8130 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8131 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8132 run->mmio.is_write = vcpu->mmio_is_write;
8133 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8134 return 0;
5287f194
AK		 8135}
8136
822f312d
SAS		 8137/* Swap (qemu) user FPU context for the guest FPU context. */
8138static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8139{
8140 preempt_disable();
240c35a3 8141 copy_fpregs_to_fpstate(&current->thread.fpu);
822f312d 8142 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8143 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d
SAS		 8144 ~XFEATURE_MASK_PKRU);
8145 preempt_enable();
8146 trace_kvm_fpu(1);
8147}
8148
8149/* When vcpu_run ends, restore user space FPU context. */
8150static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8151{
8152 preempt_disable();
b666a4b6 8153 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
240c35a3 8154 copy_kernel_to_fpregs(&current->thread.fpu.state);
822f312d
SAS		 8155 preempt_enable();
8156 ++vcpu->stat.fpu_reload;
8157 trace_kvm_fpu(0);
8158}
8159
b6c7a5dc
HB		 8160int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8161{
8162 int r;
b6c7a5dc 8163
accb757d 8164 vcpu_load(vcpu);
20b7035c 8165 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8166 kvm_load_guest_fpu(vcpu);
8167
a4535290 8168 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8169 if (kvm_run->immediate_exit) {
8170 r = -EINTR;
8171 goto out;
8172 }
b6c7a5dc 8173 kvm_vcpu_block(vcpu);
66450a21 8174 kvm_apic_accept_events(vcpu);
72875d8a 8175 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8176 r = -EAGAIN;
a0595000
JS		 8177 if (signal_pending(current)) {
8178 r = -EINTR;
8179 vcpu->run->exit_reason = KVM_EXIT_INTR;
8180 ++vcpu->stat.signal_exits;
8181 }
ac9f6dc0 8182 goto out;
b6c7a5dc
HB		 8183 }
8184
01643c51
KH		 8185 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8186 r = -EINVAL;
8187 goto out;
8188 }
8189
8190 if (vcpu->run->kvm_dirty_regs) {
8191 r = sync_regs(vcpu);
8192 if (r != 0)
8193 goto out;
8194 }
8195
b6c7a5dc 8196 /* re-sync apic's tpr */
35754c98 8197 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8198 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8199 r = -EINVAL;
8200 goto out;
8201 }
8202 }
b6c7a5dc 8203
716d51ab
GN		 8204 if (unlikely(vcpu->arch.complete_userspace_io)) {
8205 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8206 vcpu->arch.complete_userspace_io = NULL;
8207 r = cui(vcpu);
8208 if (r <= 0)
5663d8f9 8209 goto out;
716d51ab
GN		 8210 } else
8211 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8212
460df4c1
PB		 8213 if (kvm_run->immediate_exit)
8214 r = -EINTR;
8215 else
8216 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8217
8218out:
5663d8f9 8219 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8220 if (vcpu->run->kvm_valid_regs)
8221 store_regs(vcpu);
f1d86e46 8222 post_kvm_run_save(vcpu);
20b7035c 8223 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8224
accb757d 8225 vcpu_put(vcpu);
b6c7a5dc
HB		 8226 return r;
8227}
8228
01643c51 8229static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8230{
7ae441ea
GN		 8231 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8232 /*
8233 * We are here if userspace calls get_regs() in the middle of
8234 * instruction emulation. Registers state needs to be copied
4a969980 8235 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8236 * that usually, but some bad designed PV devices (vmware
8237 * backdoor interface) need this to work
8238 */
dd856efa 8239 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8240 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8241 }
5fdbf976
MT		 8242 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
8243 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
8244 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
8245 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
8246 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
8247 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
8248 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8249 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 8250#ifdef CONFIG_X86_64
5fdbf976
MT		 8251 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
8252 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
8253 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
8254 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
8255 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
8256 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
8257 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
8258 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 8259#endif
8260
5fdbf976 8261 regs->rip = kvm_rip_read(vcpu);
91586a3b 8262 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8263}
b6c7a5dc 8264
01643c51
KH		 8265int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8266{
8267 vcpu_load(vcpu);
8268 __get_regs(vcpu, regs);
1fc9b76b 8269 vcpu_put(vcpu);
b6c7a5dc
HB		 8270 return 0;
8271}
8272
01643c51 8273static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8274{
7ae441ea
GN		 8275 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8276 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8277
5fdbf976
MT		 8278 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
8279 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8280 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8281 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8282 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8283 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8284 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8285 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 8286#ifdef CONFIG_X86_64
5fdbf976
MT		 8287 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8288 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8289 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8290 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8291 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8292 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8293 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8294 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 8295#endif
8296
5fdbf976 8297 kvm_rip_write(vcpu, regs->rip);
d73235d1 8298 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8299
b4f14abd
JK		 8300 vcpu->arch.exception.pending = false;
8301
3842d135 8302 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8303}
3842d135 8304
01643c51
KH		 8305int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8306{
8307 vcpu_load(vcpu);
8308 __set_regs(vcpu, regs);
875656fe 8309 vcpu_put(vcpu);
b6c7a5dc
HB		 8310 return 0;
8311}
8312
b6c7a5dc
HB		 8313void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8314{
8315 struct kvm_segment cs;
8316
3e6e0aab 8317 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8318 *db = cs.db;
8319 *l = cs.l;
8320}
8321EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8322
01643c51 8323static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8324{
89a27f4d 8325 struct desc_ptr dt;
b6c7a5dc 8326
3e6e0aab
GT		 8327 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8328 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8329 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8330 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8331 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8332 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8333
3e6e0aab
GT		 8334 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8335 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8336
8337 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8338 sregs->idt.limit = dt.size;
8339 sregs->idt.base = dt.address;
b6c7a5dc 8340 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8341 sregs->gdt.limit = dt.size;
8342 sregs->gdt.base = dt.address;
b6c7a5dc 8343
4d4ec087 8344 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8345 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8346 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8347 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8348 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8349 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8350 sregs->apic_base = kvm_get_apic_base(vcpu);
8351
0e96f31e 8352 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8353
04140b41 8354 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8355 set_bit(vcpu->arch.interrupt.nr,
8356 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8357}
16d7a191 8358
01643c51
KH		 8359int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8360 struct kvm_sregs *sregs)
8361{
8362 vcpu_load(vcpu);
8363 __get_sregs(vcpu, sregs);
bcdec41c 8364 vcpu_put(vcpu);
b6c7a5dc
HB		 8365 return 0;
8366}
8367
62d9f0db
MT		 8368int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8369 struct kvm_mp_state *mp_state)
8370{
fd232561
CD		 8371 vcpu_load(vcpu);
8372
66450a21 8373 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8374 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8375 vcpu->arch.pv.pv_unhalted)
8376 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8377 else
8378 mp_state->mp_state = vcpu->arch.mp_state;
8379
fd232561 8380 vcpu_put(vcpu);
62d9f0db
MT		 8381 return 0;
8382}
8383
8384int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8385 struct kvm_mp_state *mp_state)
8386{
e83dff5e
CD		 8387 int ret = -EINVAL;
8388
8389 vcpu_load(vcpu);
8390
bce87cce 8391 if (!lapic_in_kernel(vcpu) &&
66450a21 8392 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8393 goto out;
66450a21 8394
28bf2888
DH		 8395 /* INITs are latched while in SMM */
8396 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8397 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8398 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8399 goto out;
28bf2888 8400
66450a21
JK		 8401 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8402 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8403 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8404 } else
8405 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8406 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8407
8408 ret = 0;
8409out:
8410 vcpu_put(vcpu);
8411 return ret;
62d9f0db
MT		 8412}
8413
7f3d35fd
KW		 8414int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8415 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8416{
9d74191a 8417 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8418 int ret;
e01c2426 8419
8ec4722d 8420 init_emulate_ctxt(vcpu);
c697518a 8421
7f3d35fd 8422 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8423 has_error_code, error_code);
c697518a 8424
c697518a 8425 if (ret)
19d04437 8426 return EMULATE_FAIL;
37817f29 8427
9d74191a
TY		 8428 kvm_rip_write(vcpu, ctxt->eip);
8429 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8430 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8431 return EMULATE_DONE;
37817f29
IE		 8432}
8433EXPORT_SYMBOL_GPL(kvm_task_switch);
8434
3140c156 8435static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8436{
74fec5b9
TL		 8437 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8438 (sregs->cr4 & X86_CR4_OSXSAVE))
8439 return -EINVAL;
8440
37b95951 8441 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8442 /*
8443 * When EFER.LME and CR0.PG are set, the processor is in
8444 * 64-bit mode (though maybe in a 32-bit code segment).
8445 * CR4.PAE and EFER.LMA must be set.
8446 */
37b95951 8447 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8448 || !(sregs->efer & EFER_LMA))
8449 return -EINVAL;
8450 } else {
8451 /*
8452 * Not in 64-bit mode: EFER.LMA is clear and the code
8453 * segment cannot be 64-bit.
8454 */
8455 if (sregs->efer & EFER_LMA || sregs->cs.l)
8456 return -EINVAL;
8457 }
8458
8459 return 0;
8460}
8461
01643c51 8462static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8463{
58cb628d 8464 struct msr_data apic_base_msr;
b6c7a5dc 8465 int mmu_reset_needed = 0;
c4d21882 8466 int cpuid_update_needed = 0;
63f42e02 8467 int pending_vec, max_bits, idx;
89a27f4d 8468 struct desc_ptr dt;
b4ef9d4e
CD		 8469 int ret = -EINVAL;
8470
f2981033 8471 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8472 goto out;
f2981033 8473
d3802286
JM		 8474 apic_base_msr.data = sregs->apic_base;
8475 apic_base_msr.host_initiated = true;
8476 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8477 goto out;
6d1068b3 8478
89a27f4d
GN		 8479 dt.size = sregs->idt.limit;
8480 dt.address = sregs->idt.base;
b6c7a5dc 8481 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8482 dt.size = sregs->gdt.limit;
8483 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8484 kvm_x86_ops->set_gdt(vcpu, &dt);
8485
ad312c7c 8486 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8487 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8488 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8489 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8490
2d3ad1f4 8491 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8492
f6801dff 8493 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8494 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8495
4d4ec087 8496 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8497 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8498 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8499
fc78f519 8500 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8501 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8502 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8503 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8504 if (cpuid_update_needed)
00b27a3e 8505 kvm_update_cpuid(vcpu);
63f42e02
XG		 8506
8507 idx = srcu_read_lock(&vcpu->kvm->srcu);
d35b34a9 8508 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
9f8fe504 8509 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8510 mmu_reset_needed = 1;
8511 }
63f42e02 8512 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8513
8514 if (mmu_reset_needed)
8515 kvm_mmu_reset_context(vcpu);
8516
a50abc3b 8517 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8518 pending_vec = find_first_bit(
8519 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8520 if (pending_vec < max_bits) {
66fd3f7f 8521 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8522 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8523 }
8524
3e6e0aab
GT		 8525 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8526 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8527 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8528 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8529 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8530 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8531
3e6e0aab
GT		 8532 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8533 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8534
5f0269f5
ME		 8535 update_cr8_intercept(vcpu);
8536
9c3e4aab 8537 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8538 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8539 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8540 !is_protmode(vcpu))
9c3e4aab
MT		 8541 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8542
3842d135
AK		 8543 kvm_make_request(KVM_REQ_EVENT, vcpu);
8544
b4ef9d4e
CD		 8545 ret = 0;
8546out:
01643c51
KH		 8547 return ret;
8548}
8549
8550int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8551 struct kvm_sregs *sregs)
8552{
8553 int ret;
8554
8555 vcpu_load(vcpu);
8556 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8557 vcpu_put(vcpu);
8558 return ret;
b6c7a5dc
HB		 8559}
8560
d0bfb940
JK		 8561int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8562 struct kvm_guest_debug *dbg)
b6c7a5dc 8563{
355be0b9 8564 unsigned long rflags;
ae675ef0 8565 int i, r;
b6c7a5dc 8566
66b56562
CD		 8567 vcpu_load(vcpu);
8568
4f926bf2
JK		 8569 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8570 r = -EBUSY;
8571 if (vcpu->arch.exception.pending)
2122ff5e 8572 goto out;
4f926bf2
JK		 8573 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8574 kvm_queue_exception(vcpu, DB_VECTOR);
8575 else
8576 kvm_queue_exception(vcpu, BP_VECTOR);
8577 }
8578
91586a3b
JK		 8579 /*
8580 * Read rflags as long as potentially injected trace flags are still
8581 * filtered out.
8582 */
8583 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8584
8585 vcpu->guest_debug = dbg->control;
8586 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8587 vcpu->guest_debug = 0;
8588
8589 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8590 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8591 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8592 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8593 } else {
8594 for (i = 0; i < KVM_NR_DB_REGS; i++)
8595 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8596 }
c8639010 8597 kvm_update_dr7(vcpu);
ae675ef0 8598
f92653ee
JK		 8599 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8600 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8601 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8602
91586a3b
JK		 8603 /*
8604 * Trigger an rflags update that will inject or remove the trace
8605 * flags.
8606 */
8607 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8608
a96036b8 8609 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8610
4f926bf2 8611 r = 0;
d0bfb940 8612
2122ff5e 8613out:
66b56562 8614 vcpu_put(vcpu);
b6c7a5dc
HB		 8615 return r;
8616}
8617
8b006791
ZX		 8618/*
8619 * Translate a guest virtual address to a guest physical address.
8620 */
8621int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8622 struct kvm_translation *tr)
8623{
8624 unsigned long vaddr = tr->linear_address;
8625 gpa_t gpa;
f656ce01 8626 int idx;
8b006791 8627
1da5b61d
CD		 8628 vcpu_load(vcpu);
8629
f656ce01 8630 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8631 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8632 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8633 tr->physical_address = gpa;
8634 tr->valid = gpa != UNMAPPED_GVA;
8635 tr->writeable = 1;
8636 tr->usermode = 0;
8b006791 8637
1da5b61d 8638 vcpu_put(vcpu);
8b006791
ZX		 8639 return 0;
8640}
8641
d0752060
HB		 8642int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8643{
1393123e 8644 struct fxregs_state *fxsave;
d0752060 8645
1393123e 8646 vcpu_load(vcpu);
d0752060 8647
b666a4b6 8648 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8649 memcpy(fpu->fpr, fxsave->st_space, 128);
8650 fpu->fcw = fxsave->cwd;
8651 fpu->fsw = fxsave->swd;
8652 fpu->ftwx = fxsave->twd;
8653 fpu->last_opcode = fxsave->fop;
8654 fpu->last_ip = fxsave->rip;
8655 fpu->last_dp = fxsave->rdp;
0e96f31e 8656 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8657
1393123e 8658 vcpu_put(vcpu);
d0752060
HB		 8659 return 0;
8660}
8661
8662int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8663{
6a96bc7f
CD		 8664 struct fxregs_state *fxsave;
8665
8666 vcpu_load(vcpu);
8667
b666a4b6 8668 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8669
d0752060
HB		 8670 memcpy(fxsave->st_space, fpu->fpr, 128);
8671 fxsave->cwd = fpu->fcw;
8672 fxsave->swd = fpu->fsw;
8673 fxsave->twd = fpu->ftwx;
8674 fxsave->fop = fpu->last_opcode;
8675 fxsave->rip = fpu->last_ip;
8676 fxsave->rdp = fpu->last_dp;
0e96f31e 8677 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8678
6a96bc7f 8679 vcpu_put(vcpu);
d0752060
HB		 8680 return 0;
8681}
8682
01643c51
KH		 8683static void store_regs(struct kvm_vcpu *vcpu)
8684{
8685 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8686
8687 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8688 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8689
8690 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8691 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8692
8693 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8694 kvm_vcpu_ioctl_x86_get_vcpu_events(
8695 vcpu, &vcpu->run->s.regs.events);
8696}
8697
8698static int sync_regs(struct kvm_vcpu *vcpu)
8699{
8700 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8701 return -EINVAL;
8702
8703 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8704 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8705 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8706 }
8707 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8708 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8709 return -EINVAL;
8710 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8711 }
8712 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8713 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8714 vcpu, &vcpu->run->s.regs.events))
8715 return -EINVAL;
8716 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8717 }
8718
8719 return 0;
8720}
8721
0ee6a517 8722static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8723{
b666a4b6 8724 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 8725 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 8726 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 8727 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8728
2acf923e
DC		 8729 /*
8730 * Ensure guest xcr0 is valid for loading
8731 */
d91cab78 8732 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8733
ad312c7c 8734 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8735}
d0752060 8736
e9b11c17
ZX		 8737void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8738{
bd768e14
IY		 8739 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8740
12f9a48f 8741 kvmclock_reset(vcpu);
7f1ea208 8742
e9b11c17 8743 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8744 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8745}
8746
8747struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8748 unsigned int id)
8749{
c447e76b
LL		 8750 struct kvm_vcpu *vcpu;
8751
b0c39dc6 8752 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8753 printk_once(KERN_WARNING
8754 "kvm: SMP vm created on host with unstable TSC; "
8755 "guest TSC will not be reliable\n");
c447e76b
LL		 8756
8757 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8758
c447e76b 8759 return vcpu;
26e5215f 8760}
e9b11c17 8761
26e5215f
AK		 8762int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8763{
0cf9135b 8764 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 8765 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 8766 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8767 vcpu_load(vcpu);
d28bc9dd 8768 kvm_vcpu_reset(vcpu, false);
e1732991 8769 kvm_init_mmu(vcpu, false);
e9b11c17 8770 vcpu_put(vcpu);
ec7660cc 8771 return 0;
e9b11c17
ZX		 8772}
8773
31928aa5 8774void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8775{
8fe8ab46 8776 struct msr_data msr;
332967a3 8777 struct kvm *kvm = vcpu->kvm;
42897d86 8778
d3457c87
RK		 8779 kvm_hv_vcpu_postcreate(vcpu);
8780
ec7660cc 8781 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8782 return;
ec7660cc 8783 vcpu_load(vcpu);
8fe8ab46
WA		 8784 msr.data = 0x0;
8785 msr.index = MSR_IA32_TSC;
8786 msr.host_initiated = true;
8787 kvm_write_tsc(vcpu, &msr);
42897d86 8788 vcpu_put(vcpu);
ec7660cc 8789 mutex_unlock(&vcpu->mutex);
42897d86 8790
630994b3
MT		 8791 if (!kvmclock_periodic_sync)
8792 return;
8793
332967a3
AJ		 8794 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8795 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8796}
8797
d40ccc62 8798void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8799{
344d9588
GN		 8800 vcpu->arch.apf.msr_val = 0;
8801
ec7660cc 8802 vcpu_load(vcpu);
e9b11c17
ZX		 8803 kvm_mmu_unload(vcpu);
8804 vcpu_put(vcpu);
8805
8806 kvm_x86_ops->vcpu_free(vcpu);
8807}
8808
d28bc9dd 8809void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8810{
b7e31be3
RK		 8811 kvm_lapic_reset(vcpu, init_event);
8812
e69fab5d
PB		 8813 vcpu->arch.hflags = 0;
8814
c43203ca 8815 vcpu->arch.smi_pending = 0;
52797bf9 8816 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8817 atomic_set(&vcpu->arch.nmi_queued, 0);
8818 vcpu->arch.nmi_pending = 0;
448fa4a9 8819 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8820 kvm_clear_interrupt_queue(vcpu);
8821 kvm_clear_exception_queue(vcpu);
664f8e26 8822 vcpu->arch.exception.pending = false;
448fa4a9 8823
42dbaa5a 8824 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8825 kvm_update_dr0123(vcpu);
6f43ed01 8826 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8827 kvm_update_dr6(vcpu);
42dbaa5a 8828 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8829 kvm_update_dr7(vcpu);
42dbaa5a 8830
1119022c
NA		 8831 vcpu->arch.cr2 = 0;
8832
3842d135 8833 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8834 vcpu->arch.apf.msr_val = 0;
c9aaa895 8835 vcpu->arch.st.msr_val = 0;
3842d135 8836
12f9a48f
GC		 8837 kvmclock_reset(vcpu);
8838
af585b92
GN		 8839 kvm_clear_async_pf_completion_queue(vcpu);
8840 kvm_async_pf_hash_reset(vcpu);
8841 vcpu->arch.apf.halted = false;
3842d135 8842
a554d207
WL		 8843 if (kvm_mpx_supported()) {
8844 void *mpx_state_buffer;
8845
8846 /*
8847 * To avoid have the INIT path from kvm_apic_has_events() that be
8848 * called with loaded FPU and does not let userspace fix the state.
8849 */
f775b13e
RR		 8850 if (init_event)
8851 kvm_put_guest_fpu(vcpu);
b666a4b6 8852 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
a554d207
WL		 8853 XFEATURE_MASK_BNDREGS);
8854 if (mpx_state_buffer)
8855 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 8856 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
a554d207
WL		 8857 XFEATURE_MASK_BNDCSR);
8858 if (mpx_state_buffer)
8859 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8860 if (init_event)
8861 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8862 }
8863
64d60670 8864 if (!init_event) {
d28bc9dd 8865 kvm_pmu_reset(vcpu);
64d60670 8866 vcpu->arch.smbase = 0x30000;
db2336a8 8867
db2336a8 8868 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8869
8870 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8871 }
f5132b01 8872
66f7b72e
JS		 8873 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8874 vcpu->arch.regs_avail = ~0;
8875 vcpu->arch.regs_dirty = ~0;
8876
a554d207
WL		 8877 vcpu->arch.ia32_xss = 0;
8878
d28bc9dd 8879 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8880}
8881
2b4a273b 8882void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8883{
8884 struct kvm_segment cs;
8885
8886 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8887 cs.selector = vector << 8;
8888 cs.base = vector << 12;
8889 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8890 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8891}
8892
13a34e06 8893int kvm_arch_hardware_enable(void)
e9b11c17 8894{
ca84d1a2
ZA		 8895 struct kvm *kvm;
8896 struct kvm_vcpu *vcpu;
8897 int i;
0dd6a6ed
ZA		 8898 int ret;
8899 u64 local_tsc;
8900 u64 max_tsc = 0;
8901 bool stable, backwards_tsc = false;
18863bdd
AK		 8902
8903 kvm_shared_msr_cpu_online();
13a34e06 8904 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8905 if (ret != 0)
8906 return ret;
8907
4ea1636b 8908 local_tsc = rdtsc();
b0c39dc6 8909 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8910 list_for_each_entry(kvm, &vm_list, vm_list) {
8911 kvm_for_each_vcpu(i, vcpu, kvm) {
8912 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8913 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8914 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8915 backwards_tsc = true;
8916 if (vcpu->arch.last_host_tsc > max_tsc)
8917 max_tsc = vcpu->arch.last_host_tsc;
8918 }
8919 }
8920 }
8921
8922 /*
8923 * Sometimes, even reliable TSCs go backwards. This happens on
8924 * platforms that reset TSC during suspend or hibernate actions, but
8925 * maintain synchronization. We must compensate. Fortunately, we can
8926 * detect that condition here, which happens early in CPU bringup,
8927 * before any KVM threads can be running. Unfortunately, we can't
8928 * bring the TSCs fully up to date with real time, as we aren't yet far
8929 * enough into CPU bringup that we know how much real time has actually
108b249c 8930 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8931 * variables that haven't been updated yet.
8932 *
8933 * So we simply find the maximum observed TSC above, then record the
8934 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8935 * the adjustment will be applied. Note that we accumulate
8936 * adjustments, in case multiple suspend cycles happen before some VCPU
8937 * gets a chance to run again. In the event that no KVM threads get a
8938 * chance to run, we will miss the entire elapsed period, as we'll have
8939 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8940 * loose cycle time. This isn't too big a deal, since the loss will be
8941 * uniform across all VCPUs (not to mention the scenario is extremely
8942 * unlikely). It is possible that a second hibernate recovery happens
8943 * much faster than a first, causing the observed TSC here to be
8944 * smaller; this would require additional padding adjustment, which is
8945 * why we set last_host_tsc to the local tsc observed here.
8946 *
8947 * N.B. - this code below runs only on platforms with reliable TSC,
8948 * as that is the only way backwards_tsc is set above. Also note
8949 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8950 * have the same delta_cyc adjustment applied if backwards_tsc
8951 * is detected. Note further, this adjustment is only done once,
8952 * as we reset last_host_tsc on all VCPUs to stop this from being
8953 * called multiple times (one for each physical CPU bringup).
8954 *
4a969980 8955 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8956 * will be compensated by the logic in vcpu_load, which sets the TSC to
8957 * catchup mode. This will catchup all VCPUs to real time, but cannot
8958 * guarantee that they stay in perfect synchronization.
8959 */
8960 if (backwards_tsc) {
8961 u64 delta_cyc = max_tsc - local_tsc;
8962 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8963 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8964 kvm_for_each_vcpu(i, vcpu, kvm) {
8965 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8966 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8967 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8968 }
8969
8970 /*
8971 * We have to disable TSC offset matching.. if you were
8972 * booting a VM while issuing an S4 host suspend....
8973 * you may have some problem. Solving this issue is
8974 * left as an exercise to the reader.
8975 */
8976 kvm->arch.last_tsc_nsec = 0;
8977 kvm->arch.last_tsc_write = 0;
8978 }
8979
8980 }
8981 return 0;
e9b11c17
ZX		 8982}
8983
13a34e06 8984void kvm_arch_hardware_disable(void)
e9b11c17 8985{
13a34e06
RK		 8986 kvm_x86_ops->hardware_disable();
8987 drop_user_return_notifiers();
e9b11c17
ZX		 8988}
8989
8990int kvm_arch_hardware_setup(void)
8991{
9e9c3fe4
NA		 8992 int r;
8993
8994 r = kvm_x86_ops->hardware_setup();
8995 if (r != 0)
8996 return r;
8997
35181e86
HZ		 8998 if (kvm_has_tsc_control) {
8999 /*
9000 * Make sure the user can only configure tsc_khz values that
9001 * fit into a signed integer.
273ba457 9002 * A min value is not calculated because it will always
35181e86
HZ		 9003 * be 1 on all machines.
9004 */
9005 u64 max = min(0x7fffffffULL,
9006 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9007 kvm_max_guest_tsc_khz = max;
9008
ad721883 9009 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9010 }
ad721883 9011
9e9c3fe4
NA		 9012 kvm_init_msr_list();
9013 return 0;
e9b11c17
ZX		 9014}
9015
9016void kvm_arch_hardware_unsetup(void)
9017{
9018 kvm_x86_ops->hardware_unsetup();
9019}
9020
9021void kvm_arch_check_processor_compat(void *rtn)
9022{
9023 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 9024}
9025
9026bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9027{
9028 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9029}
9030EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9031
9032bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9033{
9034 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9035}
9036
54e9818f 9037struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9038EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9039
e9b11c17
ZX		 9040int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9041{
9042 struct page *page;
e9b11c17
ZX		 9043 int r;
9044
9aabc88f 9045 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9046 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9047 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9048 else
a4535290 9049 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9050
9051 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9052 if (!page) {
9053 r = -ENOMEM;
9054 goto fail;
9055 }
ad312c7c 9056 vcpu->arch.pio_data = page_address(page);
e9b11c17 9057
cc578287 9058 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9059
e9b11c17
ZX		 9060 r = kvm_mmu_create(vcpu);
9061 if (r < 0)
9062 goto fail_free_pio_data;
9063
26de7988 9064 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9065 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
e9b11c17
ZX		 9066 r = kvm_create_lapic(vcpu);
9067 if (r < 0)
9068 goto fail_mmu_destroy;
54e9818f
GN		 9069 } else
9070 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9071
890ca9ae 9072 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
254272ce 9073 GFP_KERNEL_ACCOUNT);
890ca9ae
HY		 9074 if (!vcpu->arch.mce_banks) {
9075 r = -ENOMEM;
443c39bc 9076 goto fail_free_lapic;
890ca9ae
HY		 9077 }
9078 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9079
254272ce
BG		 9080 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9081 GFP_KERNEL_ACCOUNT)) {
f1797359 9082 r = -ENOMEM;
f5f48ee1 9083 goto fail_free_mce_banks;
f1797359 9084 }
f5f48ee1 9085
0ee6a517 9086 fx_init(vcpu);
66f7b72e 9087
4344ee98 9088 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9089
5a4f55cd
EK		 9090 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9091
74545705
RK		 9092 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9093
af585b92 9094 kvm_async_pf_hash_reset(vcpu);
f5132b01 9095 kvm_pmu_init(vcpu);
af585b92 9096
1c1a9ce9 9097 vcpu->arch.pending_external_vector = -1;
de63ad4c 9098 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9099
5c919412
AS		 9100 kvm_hv_vcpu_init(vcpu);
9101
e9b11c17 9102 return 0;
0ee6a517 9103
f5f48ee1
SY		 9104fail_free_mce_banks:
9105 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9106fail_free_lapic:
9107 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9108fail_mmu_destroy:
9109 kvm_mmu_destroy(vcpu);
9110fail_free_pio_data:
ad312c7c 9111 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9112fail:
9113 return r;
9114}
9115
9116void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9117{
f656ce01
MT		 9118 int idx;
9119
1f4b34f8 9120 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9121 kvm_pmu_destroy(vcpu);
36cb93fd 9122 kfree(vcpu->arch.mce_banks);
e9b11c17 9123 kvm_free_lapic(vcpu);
f656ce01 9124 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9125 kvm_mmu_destroy(vcpu);
f656ce01 9126 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9127 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9128 if (!lapic_in_kernel(vcpu))
54e9818f 9129 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9130}
d19a9cd2 9131
e790d9ef
RK		 9132void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9133{
c595ceee 9134 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9135 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9136}
9137
e08b9637 9138int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9139{
e08b9637
CO		 9140 if (type)
9141 return -EINVAL;
9142
6ef768fa 9143 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9144 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 9145 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9146 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9147
5550af4d
SY		 9148 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9149 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9150 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9151 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9152 &kvm->arch.irq_sources_bitmap);
5550af4d 9153
038f8c11 9154 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9155 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9156 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9157
108b249c 9158 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 9159 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9160
6fbbde9a
DS		 9161 kvm->arch.guest_can_read_msr_platform_info = true;
9162
7e44e449 9163 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9164 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9165
cbc0236a 9166 kvm_hv_init_vm(kvm);
0eb05bf2 9167 kvm_page_track_init(kvm);
13d268ca 9168 kvm_mmu_init_vm(kvm);
0eb05bf2 9169
03543133
SS		 9170 if (kvm_x86_ops->vm_init)
9171 return kvm_x86_ops->vm_init(kvm);
9172
d89f5eff 9173 return 0;
d19a9cd2
ZX		 9174}
9175
9176static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9177{
ec7660cc 9178 vcpu_load(vcpu);
d19a9cd2
ZX		 9179 kvm_mmu_unload(vcpu);
9180 vcpu_put(vcpu);
9181}
9182
9183static void kvm_free_vcpus(struct kvm *kvm)
9184{
9185 unsigned int i;
988a2cae 9186 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9187
9188 /*
9189 * Unpin any mmu pages first.
9190 */
af585b92
GN		 9191 kvm_for_each_vcpu(i, vcpu, kvm) {
9192 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9193 kvm_unload_vcpu_mmu(vcpu);
af585b92 9194 }
988a2cae
GN		 9195 kvm_for_each_vcpu(i, vcpu, kvm)
9196 kvm_arch_vcpu_free(vcpu);
9197
9198 mutex_lock(&kvm->lock);
9199 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9200 kvm->vcpus[i] = NULL;
d19a9cd2 9201
988a2cae
GN		 9202 atomic_set(&kvm->online_vcpus, 0);
9203 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9204}
9205
ad8ba2cd
SY		 9206void kvm_arch_sync_events(struct kvm *kvm)
9207{
332967a3 9208 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9209 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9210 kvm_free_pit(kvm);
ad8ba2cd
SY		 9211}
9212
1d8007bd 9213int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9214{
9215 int i, r;
25188b99 9216 unsigned long hva;
f0d648bd
PB		 9217 struct kvm_memslots *slots = kvm_memslots(kvm);
9218 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9219
9220 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9221 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9222 return -EINVAL;
9da0e4d5 9223
f0d648bd
PB		 9224 slot = id_to_memslot(slots, id);
9225 if (size) {
b21629da 9226 if (slot->npages)
f0d648bd
PB		 9227 return -EEXIST;
9228
9229 /*
9230 * MAP_SHARED to prevent internal slot pages from being moved
9231 * by fork()/COW.
9232 */
9233 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9234 MAP_SHARED | MAP_ANONYMOUS, 0);
9235 if (IS_ERR((void *)hva))
9236 return PTR_ERR((void *)hva);
9237 } else {
9238 if (!slot->npages)
9239 return 0;
9240
9241 hva = 0;
9242 }
9243
9244 old = *slot;
9da0e4d5 9245 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9246 struct kvm_userspace_memory_region m;
9da0e4d5 9247
1d8007bd
PB		 9248 m.slot = id | (i << 16);
9249 m.flags = 0;
9250 m.guest_phys_addr = gpa;
f0d648bd 9251 m.userspace_addr = hva;
1d8007bd 9252 m.memory_size = size;
9da0e4d5
PB		 9253 r = __kvm_set_memory_region(kvm, &m);
9254 if (r < 0)
9255 return r;
9256 }
9257
103c763c
EB		 9258 if (!size)
9259 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9260
9da0e4d5
PB		 9261 return 0;
9262}
9263EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9264
1d8007bd 9265int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9266{
9267 int r;
9268
9269 mutex_lock(&kvm->slots_lock);
1d8007bd 9270 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9271 mutex_unlock(&kvm->slots_lock);
9272
9273 return r;
9274}
9275EXPORT_SYMBOL_GPL(x86_set_memory_region);
9276
d19a9cd2
ZX		 9277void kvm_arch_destroy_vm(struct kvm *kvm)
9278{
27469d29
AH		 9279 if (current->mm == kvm->mm) {
9280 /*
9281 * Free memory regions allocated on behalf of userspace,
9282 * unless the the memory map has changed due to process exit
9283 * or fd copying.
9284 */
1d8007bd
PB		 9285 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9286 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9287 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9288 }
03543133
SS		 9289 if (kvm_x86_ops->vm_destroy)
9290 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9291 kvm_pic_destroy(kvm);
9292 kvm_ioapic_destroy(kvm);
d19a9cd2 9293 kvm_free_vcpus(kvm);
af1bae54 9294 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 9295 kvm_mmu_uninit_vm(kvm);
2beb6dad 9296 kvm_page_track_cleanup(kvm);
cbc0236a 9297 kvm_hv_destroy_vm(kvm);
d19a9cd2 9298}
0de10343 9299
5587027c 9300void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9301 struct kvm_memory_slot *dont)
9302{
9303 int i;
9304
d89cc617
TY		 9305 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9306 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9307 kvfree(free->arch.rmap[i]);
d89cc617 9308 free->arch.rmap[i] = NULL;
77d11309 9309 }
d89cc617
TY		 9310 if (i == 0)
9311 continue;
9312
9313 if (!dont || free->arch.lpage_info[i - 1] !=
9314 dont->arch.lpage_info[i - 1]) {
548ef284 9315 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9316 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9317 }
9318 }
21ebbeda
XG		 9319
9320 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9321}
9322
5587027c
AK		 9323int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9324 unsigned long npages)
db3fe4eb
TY		 9325{
9326 int i;
9327
d89cc617 9328 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9329 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9330 unsigned long ugfn;
9331 int lpages;
d89cc617 9332 int level = i + 1;
db3fe4eb
TY		 9333
9334 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9335 slot->base_gfn, level) + 1;
9336
d89cc617 9337 slot->arch.rmap[i] =
778e1cdd 9338 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9339 GFP_KERNEL_ACCOUNT);
d89cc617 9340 if (!slot->arch.rmap[i])
77d11309 9341 goto out_free;
d89cc617
TY		 9342 if (i == 0)
9343 continue;
77d11309 9344
254272ce 9345 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9346 if (!linfo)
db3fe4eb
TY		 9347 goto out_free;
9348
92f94f1e
XG		 9349 slot->arch.lpage_info[i - 1] = linfo;
9350
db3fe4eb 9351 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9352 linfo[0].disallow_lpage = 1;
db3fe4eb 9353 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9354 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9355 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9356 /*
9357 * If the gfn and userspace address are not aligned wrt each
9358 * other, or if explicitly asked to, disable large page
9359 * support for this slot
9360 */
9361 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9362 !kvm_largepages_enabled()) {
9363 unsigned long j;
9364
9365 for (j = 0; j < lpages; ++j)
92f94f1e 9366 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9367 }
9368 }
9369
21ebbeda
XG		 9370 if (kvm_page_track_create_memslot(slot, npages))
9371 goto out_free;
9372
db3fe4eb
TY		 9373 return 0;
9374
9375out_free:
d89cc617 9376 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9377 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9378 slot->arch.rmap[i] = NULL;
9379 if (i == 0)
9380 continue;
9381
548ef284 9382 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9383 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9384 }
9385 return -ENOMEM;
9386}
9387
15248258 9388void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9389{
e6dff7d1
TY		 9390 /*
9391 * memslots->generation has been incremented.
9392 * mmio generation may have reached its maximum value.
9393 */
15248258 9394 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9395}
9396
f7784b8e
MT		 9397int kvm_arch_prepare_memory_region(struct kvm *kvm,
9398 struct kvm_memory_slot *memslot,
09170a49 9399 const struct kvm_userspace_memory_region *mem,
7b6195a9 9400 enum kvm_mr_change change)
0de10343 9401{
f7784b8e
MT		 9402 return 0;
9403}
9404
88178fd4
KH		 9405static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9406 struct kvm_memory_slot *new)
9407{
9408 /* Still write protect RO slot */
9409 if (new->flags & KVM_MEM_READONLY) {
9410 kvm_mmu_slot_remove_write_access(kvm, new);
9411 return;
9412 }
9413
9414 /*
9415 * Call kvm_x86_ops dirty logging hooks when they are valid.
9416 *
9417 * kvm_x86_ops->slot_disable_log_dirty is called when:
9418 *
9419 * - KVM_MR_CREATE with dirty logging is disabled
9420 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9421 *
9422 * The reason is, in case of PML, we need to set D-bit for any slots
9423 * with dirty logging disabled in order to eliminate unnecessary GPA
9424 * logging in PML buffer (and potential PML buffer full VMEXT). This
9425 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9426 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9427 * logging disabled for memory slots.
9428 *
9429 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9430 * to dirty logging mode.
9431 *
9432 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9433 *
9434 * In case of write protect:
9435 *
9436 * Write protect all pages for dirty logging.
9437 *
9438 * All the sptes including the large sptes which point to this
9439 * slot are set to readonly. We can not create any new large
9440 * spte on this slot until the end of the logging.
9441 *
9442 * See the comments in fast_page_fault().
9443 */
9444 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9445 if (kvm_x86_ops->slot_enable_log_dirty)
9446 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9447 else
9448 kvm_mmu_slot_remove_write_access(kvm, new);
9449 } else {
9450 if (kvm_x86_ops->slot_disable_log_dirty)
9451 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9452 }
9453}
9454
f7784b8e 9455void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9456 const struct kvm_userspace_memory_region *mem,
8482644a 9457 const struct kvm_memory_slot *old,
f36f3f28 9458 const struct kvm_memory_slot *new,
8482644a 9459 enum kvm_mr_change change)
f7784b8e 9460{
48c0e4e9 9461 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9462 kvm_mmu_change_mmu_pages(kvm,
9463 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9464
3ea3b7fa
WL		 9465 /*
9466 * Dirty logging tracks sptes in 4k granularity, meaning that large
9467 * sptes have to be split. If live migration is successful, the guest
9468 * in the source machine will be destroyed and large sptes will be
9469 * created in the destination. However, if the guest continues to run
9470 * in the source machine (for example if live migration fails), small
9471 * sptes will remain around and cause bad performance.
9472 *
9473 * Scan sptes if dirty logging has been stopped, dropping those
9474 * which can be collapsed into a single large-page spte. Later
9475 * page faults will create the large-page sptes.
9476 */
9477 if ((change != KVM_MR_DELETE) &&
9478 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9479 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9480 kvm_mmu_zap_collapsible_sptes(kvm, new);
9481
c972f3b1 9482 /*
88178fd4 9483 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9484 *
88178fd4
KH		 9485 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9486 * been zapped so no dirty logging staff is needed for old slot. For
9487 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9488 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9489 *
9490 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9491 */
88178fd4 9492 if (change != KVM_MR_DELETE)
f36f3f28 9493 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9494}
1d737c8a 9495
2df72e9b 9496void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9497{
7390de1e 9498 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9499}
9500
2df72e9b
MT		 9501void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9502 struct kvm_memory_slot *slot)
9503{
ae7cd873 9504 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9505}
9506
e6c67d8c
LA		 9507static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9508{
9509 return (is_guest_mode(vcpu) &&
9510 kvm_x86_ops->guest_apic_has_interrupt &&
9511 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9512}
9513
5d9bc648
PB		 9514static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9515{
9516 if (!list_empty_careful(&vcpu->async_pf.done))
9517 return true;
9518
9519 if (kvm_apic_has_events(vcpu))
9520 return true;
9521
9522 if (vcpu->arch.pv.pv_unhalted)
9523 return true;
9524
a5f01f8e
WL		 9525 if (vcpu->arch.exception.pending)
9526 return true;
9527
47a66eed
Z		 9528 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9529 (vcpu->arch.nmi_pending &&
9530 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9531 return true;
9532
47a66eed
Z		 9533 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9534 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9535 return true;
9536
5d9bc648 9537 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9538 (kvm_cpu_has_interrupt(vcpu) ||
9539 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9540 return true;
9541
1f4b34f8
AS		 9542 if (kvm_hv_has_stimer_pending(vcpu))
9543 return true;
9544
5d9bc648
PB		 9545 return false;
9546}
9547
1d737c8a
ZX		 9548int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9549{
5d9bc648 9550 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9551}
5736199a 9552
199b5763
LM		 9553bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9554{
de63ad4c 9555 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9556}
9557
b6d33834 9558int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9559{
b6d33834 9560 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9561}
78646121
GN		 9562
9563int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9564{
9565 return kvm_x86_ops->interrupt_allowed(vcpu);
9566}
229456fc 9567
82b32774 9568unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9569{
82b32774
NA		 9570 if (is_64_bit_mode(vcpu))
9571 return kvm_rip_read(vcpu);
9572 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9573 kvm_rip_read(vcpu));
9574}
9575EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9576
82b32774
NA		 9577bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9578{
9579 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9580}
9581EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9582
94fe45da
JK		 9583unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9584{
9585 unsigned long rflags;
9586
9587 rflags = kvm_x86_ops->get_rflags(vcpu);
9588 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9589 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9590 return rflags;
9591}
9592EXPORT_SYMBOL_GPL(kvm_get_rflags);
9593
6addfc42 9594static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9595{
9596 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9597 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9598 rflags |= X86_EFLAGS_TF;
94fe45da 9599 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9600}
9601
9602void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9603{
9604 __kvm_set_rflags(vcpu, rflags);
3842d135 9605 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9606}
9607EXPORT_SYMBOL_GPL(kvm_set_rflags);
9608
56028d08
GN		 9609void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9610{
9611 int r;
9612
44dd3ffa 9613 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9614 work->wakeup_all)
56028d08
GN		 9615 return;
9616
9617 r = kvm_mmu_reload(vcpu);
9618 if (unlikely(r))
9619 return;
9620
44dd3ffa
VK		 9621 if (!vcpu->arch.mmu->direct_map &&
9622 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9623 return;
9624
44dd3ffa 9625 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9626}
9627
af585b92
GN		 9628static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9629{
9630 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9631}
9632
9633static inline u32 kvm_async_pf_next_probe(u32 key)
9634{
9635 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9636}
9637
9638static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9639{
9640 u32 key = kvm_async_pf_hash_fn(gfn);
9641
9642 while (vcpu->arch.apf.gfns[key] != ~0)
9643 key = kvm_async_pf_next_probe(key);
9644
9645 vcpu->arch.apf.gfns[key] = gfn;
9646}
9647
9648static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9649{
9650 int i;
9651 u32 key = kvm_async_pf_hash_fn(gfn);
9652
9653 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9654 (vcpu->arch.apf.gfns[key] != gfn &&
9655 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9656 key = kvm_async_pf_next_probe(key);
9657
9658 return key;
9659}
9660
9661bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9662{
9663 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9664}
9665
9666static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9667{
9668 u32 i, j, k;
9669
9670 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9671 while (true) {
9672 vcpu->arch.apf.gfns[i] = ~0;
9673 do {
9674 j = kvm_async_pf_next_probe(j);
9675 if (vcpu->arch.apf.gfns[j] == ~0)
9676 return;
9677 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9678 /*
9679 * k lies cyclically in ]i,j]
9680 * | i.k.j |
9681 * |....j i.k.| or |.k..j i...|
9682 */
9683 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9684 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9685 i = j;
9686 }
9687}
9688
7c90705b
GN		 9689static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9690{
4e335d9e
PB		 9691
9692 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9693 sizeof(val));
7c90705b
GN		 9694}
9695
9a6e7c39
WL		 9696static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9697{
9698
9699 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9700 sizeof(u32));
9701}
9702
af585b92
GN		 9703void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9704 struct kvm_async_pf *work)
9705{
6389ee94
AK		 9706 struct x86_exception fault;
9707
7c90705b 9708 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9709 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9710
9711 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9712 (vcpu->arch.apf.send_user_only &&
9713 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9714 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9715 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9716 fault.vector = PF_VECTOR;
9717 fault.error_code_valid = true;
9718 fault.error_code = 0;
9719 fault.nested_page_fault = false;
9720 fault.address = work->arch.token;
adfe20fb 9721 fault.async_page_fault = true;
6389ee94 9722 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9723 }
af585b92
GN		 9724}
9725
9726void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9727 struct kvm_async_pf *work)
9728{
6389ee94 9729 struct x86_exception fault;
9a6e7c39 9730 u32 val;
6389ee94 9731
f2e10669 9732 if (work->wakeup_all)
7c90705b
GN		 9733 work->arch.token = ~0; /* broadcast wakeup */
9734 else
9735 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9736 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9737
9a6e7c39
WL		 9738 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9739 !apf_get_user(vcpu, &val)) {
9740 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9741 vcpu->arch.exception.pending &&
9742 vcpu->arch.exception.nr == PF_VECTOR &&
9743 !apf_put_user(vcpu, 0)) {
9744 vcpu->arch.exception.injected = false;
9745 vcpu->arch.exception.pending = false;
9746 vcpu->arch.exception.nr = 0;
9747 vcpu->arch.exception.has_error_code = false;
9748 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9749 vcpu->arch.exception.has_payload = false;
9750 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9751 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9752 fault.vector = PF_VECTOR;
9753 fault.error_code_valid = true;
9754 fault.error_code = 0;
9755 fault.nested_page_fault = false;
9756 fault.address = work->arch.token;
9757 fault.async_page_fault = true;
9758 kvm_inject_page_fault(vcpu, &fault);
9759 }
7c90705b 9760 }
e6d53e3b 9761 vcpu->arch.apf.halted = false;
a4fa1635 9762 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9763}
9764
9765bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9766{
9767 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9768 return true;
9769 else
9bc1f09f 9770 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9771}
9772
5544eb9b
PB		 9773void kvm_arch_start_assignment(struct kvm *kvm)
9774{
9775 atomic_inc(&kvm->arch.assigned_device_count);
9776}
9777EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9778
9779void kvm_arch_end_assignment(struct kvm *kvm)
9780{
9781 atomic_dec(&kvm->arch.assigned_device_count);
9782}
9783EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9784
9785bool kvm_arch_has_assigned_device(struct kvm *kvm)
9786{
9787 return atomic_read(&kvm->arch.assigned_device_count);
9788}
9789EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9790
e0f0bbc5
AW		 9791void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9792{
9793 atomic_inc(&kvm->arch.noncoherent_dma_count);
9794}
9795EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9796
9797void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9798{
9799 atomic_dec(&kvm->arch.noncoherent_dma_count);
9800}
9801EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9802
9803bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9804{
9805 return atomic_read(&kvm->arch.noncoherent_dma_count);
9806}
9807EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9808
14717e20
AW		 9809bool kvm_arch_has_irq_bypass(void)
9810{
9811 return kvm_x86_ops->update_pi_irte != NULL;
9812}
9813
87276880
FW		 9814int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9815 struct irq_bypass_producer *prod)
9816{
9817 struct kvm_kernel_irqfd *irqfd =
9818 container_of(cons, struct kvm_kernel_irqfd, consumer);
9819
14717e20 9820 irqfd->producer = prod;
87276880 9821
14717e20
AW		 9822 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9823 prod->irq, irqfd->gsi, 1);
87276880
FW		 9824}
9825
9826void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9827 struct irq_bypass_producer *prod)
9828{
9829 int ret;
9830 struct kvm_kernel_irqfd *irqfd =
9831 container_of(cons, struct kvm_kernel_irqfd, consumer);
9832
87276880
FW		 9833 WARN_ON(irqfd->producer != prod);
9834 irqfd->producer = NULL;
9835
9836 /*
9837 * When producer of consumer is unregistered, we change back to
9838 * remapped mode, so we can re-use the current implementation
bb3541f1 9839 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9840 * int this case doesn't want to receive the interrupts.
9841 */
9842 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9843 if (ret)
9844 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9845 " fails: %d\n", irqfd->consumer.token, ret);
9846}
9847
9848int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9849 uint32_t guest_irq, bool set)
9850{
9851 if (!kvm_x86_ops->update_pi_irte)
9852 return -EINVAL;
9853
9854 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9855}
9856
52004014
FW		 9857bool kvm_vector_hashing_enabled(void)
9858{
9859 return vector_hashing;
9860}
9861EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9862
229456fc 9863EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9864EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9865EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9866EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9867EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9868EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9869EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9870EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9871EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9872EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9873EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9874EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9875EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9876EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9877EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9878EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9879EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9880EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9881EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)