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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 | 17 | */ |
8d20bd63 | 18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
043405e1 | 19 | |
edf88417 | 20 | #include <linux/kvm_host.h> |
313a3dc7 | 21 | #include "irq.h" |
88197e6a | 22 | #include "ioapic.h" |
1d737c8a | 23 | #include "mmu.h" |
7837699f | 24 | #include "i8254.h" |
37817f29 | 25 | #include "tss.h" |
5fdbf976 | 26 | #include "kvm_cache_regs.h" |
2f728d66 | 27 | #include "kvm_emulate.h" |
26eef70c | 28 | #include "x86.h" |
00b27a3e | 29 | #include "cpuid.h" |
474a5bb9 | 30 | #include "pmu.h" |
e83d5887 | 31 | #include "hyperv.h" |
8df14af4 | 32 | #include "lapic.h" |
23200b7a | 33 | #include "xen.h" |
b0b42197 | 34 | #include "smm.h" |
313a3dc7 | 35 | |
18068523 | 36 | #include <linux/clocksource.h> |
4d5c5d0f | 37 | #include <linux/interrupt.h> |
313a3dc7 CO |
38 | #include <linux/kvm.h> |
39 | #include <linux/fs.h> | |
40 | #include <linux/vmalloc.h> | |
1767e931 PG |
41 | #include <linux/export.h> |
42 | #include <linux/moduleparam.h> | |
0de10343 | 43 | #include <linux/mman.h> |
2bacc55c | 44 | #include <linux/highmem.h> |
19de40a8 | 45 | #include <linux/iommu.h> |
c8076604 | 46 | #include <linux/cpufreq.h> |
18863bdd | 47 | #include <linux/user-return-notifier.h> |
a983fb23 | 48 | #include <linux/srcu.h> |
5a0e3ad6 | 49 | #include <linux/slab.h> |
ff9d07a0 | 50 | #include <linux/perf_event.h> |
7bee342a | 51 | #include <linux/uaccess.h> |
af585b92 | 52 | #include <linux/hash.h> |
a1b60c1c | 53 | #include <linux/pci.h> |
16e8d74d MT |
54 | #include <linux/timekeeper_internal.h> |
55 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
56 | #include <linux/kvm_irqfd.h> |
57 | #include <linux/irqbypass.h> | |
3905f9ad | 58 | #include <linux/sched/stat.h> |
0c5f81da | 59 | #include <linux/sched/isolation.h> |
d0ec49d4 | 60 | #include <linux/mem_encrypt.h> |
72c3c0fe | 61 | #include <linux/entry-kvm.h> |
7d62874f | 62 | #include <linux/suspend.h> |
4c8c3c7f | 63 | #include <linux/smp.h> |
3905f9ad | 64 | |
4c8c3c7f | 65 | #include <trace/events/ipi.h> |
aec51dc4 | 66 | #include <trace/events/kvm.h> |
2ed152af | 67 | |
24f1e32c | 68 | #include <asm/debugreg.h> |
d825ed0a | 69 | #include <asm/msr.h> |
a5f61300 | 70 | #include <asm/desc.h> |
890ca9ae | 71 | #include <asm/mce.h> |
784a4661 | 72 | #include <asm/pkru.h> |
f89e32e0 | 73 | #include <linux/kernel_stat.h> |
a0ff0611 TG |
74 | #include <asm/fpu/api.h> |
75 | #include <asm/fpu/xcr.h> | |
76 | #include <asm/fpu/xstate.h> | |
1d5f066e | 77 | #include <asm/pvclock.h> |
217fc9cf | 78 | #include <asm/div64.h> |
efc64404 | 79 | #include <asm/irq_remapping.h> |
b0c39dc6 | 80 | #include <asm/mshyperv.h> |
0092e434 | 81 | #include <asm/hypervisor.h> |
9715092f | 82 | #include <asm/tlbflush.h> |
bf8c55d8 | 83 | #include <asm/intel_pt.h> |
b3dc0695 | 84 | #include <asm/emulate_prefix.h> |
fe7e9488 | 85 | #include <asm/sgx.h> |
dd2cb348 | 86 | #include <clocksource/hyperv_timer.h> |
043405e1 | 87 | |
d1898b73 DH |
88 | #define CREATE_TRACE_POINTS |
89 | #include "trace.h" | |
90 | ||
313a3dc7 | 91 | #define MAX_IO_MSRS 256 |
890ca9ae | 92 | #define KVM_MAX_MCE_BANKS 32 |
938c8745 SC |
93 | |
94 | struct kvm_caps kvm_caps __read_mostly = { | |
95 | .supported_mce_cap = MCG_CTL_P | MCG_SER_P, | |
96 | }; | |
97 | EXPORT_SYMBOL_GPL(kvm_caps); | |
890ca9ae | 98 | |
6e37ec88 SC |
99 | #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) |
100 | ||
0f65dd70 | 101 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 102 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 103 | |
50a37eb4 JR |
104 | /* EFER defaults: |
105 | * - enable syscall per default because its emulated by KVM | |
106 | * - enable LME and LMA per default on 64 bit KVM | |
107 | */ | |
108 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
109 | static |
110 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 111 | #else |
1260edbe | 112 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 113 | #endif |
313a3dc7 | 114 | |
b11306b5 SC |
115 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
116 | ||
0dbb1123 AK |
117 | #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) |
118 | ||
ba7bb663 DD |
119 | #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE |
120 | ||
c519265f RK |
121 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
122 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 123 | |
cb142eb7 | 124 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 125 | static void process_nmi(struct kvm_vcpu *vcpu); |
6addfc42 | 126 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
127 | static void store_regs(struct kvm_vcpu *vcpu); |
128 | static int sync_regs(struct kvm_vcpu *vcpu); | |
d2f7d498 | 129 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu); |
674eea0f | 130 | |
6dba9403 ML |
131 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); |
132 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); | |
133 | ||
3af4a9e6 | 134 | static DEFINE_MUTEX(vendor_module_lock); |
afaf0b2f | 135 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
97896d04 | 136 | |
9af5471b JB |
137 | #define KVM_X86_OP(func) \ |
138 | DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ | |
139 | *(((struct kvm_x86_ops *)0)->func)); | |
e4fc23ba | 140 | #define KVM_X86_OP_OPTIONAL KVM_X86_OP |
5be2226f | 141 | #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP |
9af5471b JB |
142 | #include <asm/kvm-x86-ops.h> |
143 | EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); | |
144 | EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); | |
9af5471b | 145 | |
893590c7 | 146 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 147 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 148 | |
d855066f | 149 | bool __read_mostly report_ignored_msrs = true; |
fab0aa3b | 150 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); |
d855066f | 151 | EXPORT_SYMBOL_GPL(report_ignored_msrs); |
fab0aa3b | 152 | |
4c27625b | 153 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
154 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
155 | ||
630994b3 MT |
156 | static bool __read_mostly kvmclock_periodic_sync = true; |
157 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
158 | ||
cc578287 | 159 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 160 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
161 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
162 | ||
c3941d9e SC |
163 | /* |
164 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
d9f6e12f | 165 | * adaptive tuning starting from default advancement of 1000ns. '0' disables |
c3941d9e | 166 | * advancement entirely. Any other value is used as-is and disables adaptive |
d9f6e12f | 167 | * tuning, i.e. allows privileged userspace to set an exact advancement time. |
c3941d9e SC |
168 | */ |
169 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 170 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 171 | |
52004014 FW |
172 | static bool __read_mostly vector_hashing = true; |
173 | module_param(vector_hashing, bool, S_IRUGO); | |
174 | ||
c4ae60e4 LA |
175 | bool __read_mostly enable_vmware_backdoor = false; |
176 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
177 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
178 | ||
d500e1ed SC |
179 | /* |
180 | * Flags to manipulate forced emulation behavior (any non-zero value will | |
181 | * enable forced emulation). | |
182 | */ | |
183 | #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1) | |
184 | static int __read_mostly force_emulation_prefix; | |
40aaa5b6 | 185 | module_param(force_emulation_prefix, int, 0644); |
6c86eedc | 186 | |
0c5f81da WL |
187 | int __read_mostly pi_inject_timer = -1; |
188 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
189 | ||
4732f244 LX |
190 | /* Enable/disable PMU virtualization */ |
191 | bool __read_mostly enable_pmu = true; | |
192 | EXPORT_SYMBOL_GPL(enable_pmu); | |
193 | module_param(enable_pmu, bool, 0444); | |
194 | ||
cb00a70b | 195 | bool __read_mostly eager_page_split = true; |
a3fe5dbd DM |
196 | module_param(eager_page_split, bool, 0644); |
197 | ||
6f0f2d5e | 198 | /* Enable/disable SMT_RSB bug mitigation */ |
944a8dad | 199 | static bool __read_mostly mitigate_smt_rsb; |
6f0f2d5e TL |
200 | module_param(mitigate_smt_rsb, bool, 0444); |
201 | ||
7e34fbd0 SC |
202 | /* |
203 | * Restoring the host value for MSRs that are only consumed when running in | |
204 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
205 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
206 | */ | |
207 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 208 | |
7e34fbd0 | 209 | struct kvm_user_return_msrs { |
18863bdd AK |
210 | struct user_return_notifier urn; |
211 | bool registered; | |
7e34fbd0 | 212 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
213 | u64 host; |
214 | u64 curr; | |
7e34fbd0 | 215 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
216 | }; |
217 | ||
9cc39a5a SC |
218 | u32 __read_mostly kvm_nr_uret_msrs; |
219 | EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); | |
220 | static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; | |
7e34fbd0 | 221 | static struct kvm_user_return_msrs __percpu *user_return_msrs; |
18863bdd | 222 | |
cfc48181 SC |
223 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
224 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
225 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
86aff7a4 | 226 | | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) |
cfc48181 | 227 | |
91661989 SC |
228 | u64 __read_mostly host_efer; |
229 | EXPORT_SYMBOL_GPL(host_efer); | |
230 | ||
b96e6506 | 231 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
232 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
233 | ||
fdf513e3 VK |
234 | bool __read_mostly enable_apicv = true; |
235 | EXPORT_SYMBOL_GPL(enable_apicv); | |
236 | ||
86137773 TL |
237 | u64 __read_mostly host_xss; |
238 | EXPORT_SYMBOL_GPL(host_xss); | |
139a12cf | 239 | |
fcfe1bae JZ |
240 | const struct _kvm_stats_desc kvm_vm_stats_desc[] = { |
241 | KVM_GENERIC_VM_STATS(), | |
242 | STATS_DESC_COUNTER(VM, mmu_shadow_zapped), | |
243 | STATS_DESC_COUNTER(VM, mmu_pte_write), | |
244 | STATS_DESC_COUNTER(VM, mmu_pde_zapped), | |
245 | STATS_DESC_COUNTER(VM, mmu_flooded), | |
246 | STATS_DESC_COUNTER(VM, mmu_recycled), | |
247 | STATS_DESC_COUNTER(VM, mmu_cache_miss), | |
248 | STATS_DESC_ICOUNTER(VM, mmu_unsync), | |
71f51d2c MZ |
249 | STATS_DESC_ICOUNTER(VM, pages_4k), |
250 | STATS_DESC_ICOUNTER(VM, pages_2m), | |
251 | STATS_DESC_ICOUNTER(VM, pages_1g), | |
fcfe1bae | 252 | STATS_DESC_ICOUNTER(VM, nx_lpage_splits), |
ec1cf69c | 253 | STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), |
bc9e9e67 | 254 | STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) |
fcfe1bae | 255 | }; |
fcfe1bae JZ |
256 | |
257 | const struct kvm_stats_header kvm_vm_stats_header = { | |
258 | .name_size = KVM_STATS_NAME_SIZE, | |
259 | .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), | |
260 | .id_offset = sizeof(struct kvm_stats_header), | |
261 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
262 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
263 | sizeof(kvm_vm_stats_desc), | |
264 | }; | |
265 | ||
ce55c049 JZ |
266 | const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { |
267 | KVM_GENERIC_VCPU_STATS(), | |
1075d41e | 268 | STATS_DESC_COUNTER(VCPU, pf_taken), |
ce55c049 | 269 | STATS_DESC_COUNTER(VCPU, pf_fixed), |
1075d41e SC |
270 | STATS_DESC_COUNTER(VCPU, pf_emulate), |
271 | STATS_DESC_COUNTER(VCPU, pf_spurious), | |
272 | STATS_DESC_COUNTER(VCPU, pf_fast), | |
273 | STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created), | |
ce55c049 JZ |
274 | STATS_DESC_COUNTER(VCPU, pf_guest), |
275 | STATS_DESC_COUNTER(VCPU, tlb_flush), | |
276 | STATS_DESC_COUNTER(VCPU, invlpg), | |
277 | STATS_DESC_COUNTER(VCPU, exits), | |
278 | STATS_DESC_COUNTER(VCPU, io_exits), | |
279 | STATS_DESC_COUNTER(VCPU, mmio_exits), | |
280 | STATS_DESC_COUNTER(VCPU, signal_exits), | |
281 | STATS_DESC_COUNTER(VCPU, irq_window_exits), | |
282 | STATS_DESC_COUNTER(VCPU, nmi_window_exits), | |
283 | STATS_DESC_COUNTER(VCPU, l1d_flush), | |
284 | STATS_DESC_COUNTER(VCPU, halt_exits), | |
285 | STATS_DESC_COUNTER(VCPU, request_irq_exits), | |
286 | STATS_DESC_COUNTER(VCPU, irq_exits), | |
287 | STATS_DESC_COUNTER(VCPU, host_state_reload), | |
288 | STATS_DESC_COUNTER(VCPU, fpu_reload), | |
289 | STATS_DESC_COUNTER(VCPU, insn_emulation), | |
290 | STATS_DESC_COUNTER(VCPU, insn_emulation_fail), | |
291 | STATS_DESC_COUNTER(VCPU, hypercalls), | |
292 | STATS_DESC_COUNTER(VCPU, irq_injections), | |
293 | STATS_DESC_COUNTER(VCPU, nmi_injections), | |
294 | STATS_DESC_COUNTER(VCPU, req_event), | |
295 | STATS_DESC_COUNTER(VCPU, nested_run), | |
296 | STATS_DESC_COUNTER(VCPU, directed_yield_attempted), | |
297 | STATS_DESC_COUNTER(VCPU, directed_yield_successful), | |
6cd88243 PB |
298 | STATS_DESC_COUNTER(VCPU, preemption_reported), |
299 | STATS_DESC_COUNTER(VCPU, preemption_other), | |
63f4b210 | 300 | STATS_DESC_IBOOLEAN(VCPU, guest_mode), |
2f4073e0 | 301 | STATS_DESC_COUNTER(VCPU, notify_window_exits), |
ce55c049 | 302 | }; |
ce55c049 JZ |
303 | |
304 | const struct kvm_stats_header kvm_vcpu_stats_header = { | |
305 | .name_size = KVM_STATS_NAME_SIZE, | |
306 | .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), | |
307 | .id_offset = sizeof(struct kvm_stats_header), | |
308 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
309 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
310 | sizeof(kvm_vcpu_stats_desc), | |
311 | }; | |
312 | ||
2acf923e DC |
313 | u64 __read_mostly host_xcr0; |
314 | ||
c9b8b07c SC |
315 | static struct kmem_cache *x86_emulator_cache; |
316 | ||
6abe9c13 PX |
317 | /* |
318 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 319 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 320 | */ |
d632826f | 321 | static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) |
6abe9c13 PX |
322 | { |
323 | const char *op = write ? "wrmsr" : "rdmsr"; | |
324 | ||
325 | if (ignore_msrs) { | |
326 | if (report_ignored_msrs) | |
d383b314 TI |
327 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
328 | op, msr, data); | |
6abe9c13 | 329 | /* Mask the error */ |
cc4cb017 | 330 | return true; |
6abe9c13 | 331 | } else { |
d383b314 TI |
332 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
333 | op, msr, data); | |
cc4cb017 | 334 | return false; |
6abe9c13 PX |
335 | } |
336 | } | |
337 | ||
c9b8b07c SC |
338 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
339 | { | |
06add254 SC |
340 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
341 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
342 | ||
343 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 344 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
345 | SLAB_ACCOUNT, useroffset, |
346 | size - useroffset, NULL); | |
c9b8b07c SC |
347 | } |
348 | ||
b6785def | 349 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 350 | |
af585b92 GN |
351 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
352 | { | |
353 | int i; | |
dd03bcaa | 354 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
355 | vcpu->arch.apf.gfns[i] = ~0; |
356 | } | |
357 | ||
18863bdd AK |
358 | static void kvm_on_user_return(struct user_return_notifier *urn) |
359 | { | |
360 | unsigned slot; | |
7e34fbd0 SC |
361 | struct kvm_user_return_msrs *msrs |
362 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
363 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
364 | unsigned long flags; |
365 | ||
366 | /* | |
367 | * Disabling irqs at this point since the following code could be | |
368 | * interrupted and executed through kvm_arch_hardware_disable() | |
369 | */ | |
370 | local_irq_save(flags); | |
7e34fbd0 SC |
371 | if (msrs->registered) { |
372 | msrs->registered = false; | |
1650b4eb IA |
373 | user_return_notifier_unregister(urn); |
374 | } | |
375 | local_irq_restore(flags); | |
9cc39a5a | 376 | for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { |
7e34fbd0 | 377 | values = &msrs->values[slot]; |
2bf78fa7 | 378 | if (values->host != values->curr) { |
9cc39a5a | 379 | wrmsrl(kvm_uret_msrs_list[slot], values->host); |
2bf78fa7 | 380 | values->curr = values->host; |
18863bdd AK |
381 | } |
382 | } | |
18863bdd AK |
383 | } |
384 | ||
e5fda4bb | 385 | static int kvm_probe_user_return_msr(u32 msr) |
5104d7ff SC |
386 | { |
387 | u64 val; | |
388 | int ret; | |
389 | ||
390 | preempt_disable(); | |
391 | ret = rdmsrl_safe(msr, &val); | |
392 | if (ret) | |
393 | goto out; | |
394 | ret = wrmsrl_safe(msr, val); | |
395 | out: | |
396 | preempt_enable(); | |
397 | return ret; | |
398 | } | |
5104d7ff | 399 | |
e5fda4bb | 400 | int kvm_add_user_return_msr(u32 msr) |
2bf78fa7 | 401 | { |
e5fda4bb SC |
402 | BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); |
403 | ||
404 | if (kvm_probe_user_return_msr(msr)) | |
405 | return -1; | |
406 | ||
407 | kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; | |
408 | return kvm_nr_uret_msrs++; | |
18863bdd | 409 | } |
e5fda4bb | 410 | EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); |
18863bdd | 411 | |
8ea8b8d6 SC |
412 | int kvm_find_user_return_msr(u32 msr) |
413 | { | |
414 | int i; | |
415 | ||
9cc39a5a SC |
416 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
417 | if (kvm_uret_msrs_list[i] == msr) | |
8ea8b8d6 SC |
418 | return i; |
419 | } | |
420 | return -1; | |
421 | } | |
422 | EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); | |
423 | ||
7e34fbd0 | 424 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 425 | { |
05c19c2f | 426 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 427 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
428 | u64 value; |
429 | int i; | |
18863bdd | 430 | |
9cc39a5a SC |
431 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
432 | rdmsrl_safe(kvm_uret_msrs_list[i], &value); | |
7e34fbd0 SC |
433 | msrs->values[i].host = value; |
434 | msrs->values[i].curr = value; | |
05c19c2f | 435 | } |
18863bdd AK |
436 | } |
437 | ||
7e34fbd0 | 438 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 439 | { |
013f6a5d | 440 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 441 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 442 | int err; |
18863bdd | 443 | |
7e34fbd0 SC |
444 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
445 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 446 | return 0; |
9cc39a5a | 447 | err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); |
8b3c3104 AH |
448 | if (err) |
449 | return 1; | |
450 | ||
7e34fbd0 SC |
451 | msrs->values[slot].curr = value; |
452 | if (!msrs->registered) { | |
453 | msrs->urn.on_user_return = kvm_on_user_return; | |
454 | user_return_notifier_register(&msrs->urn); | |
455 | msrs->registered = true; | |
18863bdd | 456 | } |
8b3c3104 | 457 | return 0; |
18863bdd | 458 | } |
7e34fbd0 | 459 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 460 | |
13a34e06 | 461 | static void drop_user_return_notifiers(void) |
3548bab5 | 462 | { |
013f6a5d | 463 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 464 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 465 | |
7e34fbd0 SC |
466 | if (msrs->registered) |
467 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
468 | } |
469 | ||
6866b83e CO |
470 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
471 | { | |
8a5a87d9 | 472 | return vcpu->arch.apic_base; |
6866b83e | 473 | } |
6866b83e | 474 | |
58871649 JM |
475 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
476 | { | |
477 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
478 | } | |
479 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
480 | ||
58cb628d JK |
481 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
482 | { | |
58871649 JM |
483 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
484 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
a8ac864a | 485 | u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | |
d6321d49 | 486 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); |
58cb628d | 487 | |
58871649 | 488 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 489 | return 1; |
58871649 JM |
490 | if (!msr_info->host_initiated) { |
491 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
492 | return 1; | |
493 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
494 | return 1; | |
495 | } | |
58cb628d JK |
496 | |
497 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 498 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 499 | return 0; |
6866b83e | 500 | } |
6866b83e | 501 | |
ad0577c3 SC |
502 | /* |
503 | * Handle a fault on a hardware virtualization (VMX or SVM) instruction. | |
504 | * | |
505 | * Hardware virtualization extension instructions may fault if a reboot turns | |
506 | * off virtualization while processes are running. Usually after catching the | |
507 | * fault we just panic; during reboot instead the instruction is ignored. | |
508 | */ | |
509 | noinstr void kvm_spurious_fault(void) | |
e3ba45b8 GL |
510 | { |
511 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 512 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
513 | } |
514 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
515 | ||
3fd28fce ED |
516 | #define EXCPT_BENIGN 0 |
517 | #define EXCPT_CONTRIBUTORY 1 | |
518 | #define EXCPT_PF 2 | |
519 | ||
520 | static int exception_class(int vector) | |
521 | { | |
522 | switch (vector) { | |
523 | case PF_VECTOR: | |
524 | return EXCPT_PF; | |
525 | case DE_VECTOR: | |
526 | case TS_VECTOR: | |
527 | case NP_VECTOR: | |
528 | case SS_VECTOR: | |
529 | case GP_VECTOR: | |
530 | return EXCPT_CONTRIBUTORY; | |
531 | default: | |
532 | break; | |
533 | } | |
534 | return EXCPT_BENIGN; | |
535 | } | |
536 | ||
d6e8c854 NA |
537 | #define EXCPT_FAULT 0 |
538 | #define EXCPT_TRAP 1 | |
539 | #define EXCPT_ABORT 2 | |
540 | #define EXCPT_INTERRUPT 3 | |
5623f751 | 541 | #define EXCPT_DB 4 |
d6e8c854 NA |
542 | |
543 | static int exception_type(int vector) | |
544 | { | |
545 | unsigned int mask; | |
546 | ||
547 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
548 | return EXCPT_INTERRUPT; | |
549 | ||
550 | mask = 1 << vector; | |
551 | ||
5623f751 SC |
552 | /* |
553 | * #DBs can be trap-like or fault-like, the caller must check other CPU | |
554 | * state, e.g. DR6, to determine whether a #DB is a trap or fault. | |
555 | */ | |
556 | if (mask & (1 << DB_VECTOR)) | |
557 | return EXCPT_DB; | |
558 | ||
559 | if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
d6e8c854 NA |
560 | return EXCPT_TRAP; |
561 | ||
562 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
563 | return EXCPT_ABORT; | |
564 | ||
565 | /* Reserved exceptions will result in fault */ | |
566 | return EXCPT_FAULT; | |
567 | } | |
568 | ||
d4963e31 SC |
569 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu, |
570 | struct kvm_queued_exception *ex) | |
da998b46 | 571 | { |
d4963e31 | 572 | if (!ex->has_payload) |
da998b46 JM |
573 | return; |
574 | ||
d4963e31 | 575 | switch (ex->vector) { |
f10c729f JM |
576 | case DB_VECTOR: |
577 | /* | |
578 | * "Certain debug exceptions may clear bit 0-3. The | |
579 | * remaining contents of the DR6 register are never | |
580 | * cleared by the processor". | |
581 | */ | |
582 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
583 | /* | |
9a3ecd5e CQ |
584 | * In order to reflect the #DB exception payload in guest |
585 | * dr6, three components need to be considered: active low | |
586 | * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, | |
587 | * DR6_BS and DR6_BT) | |
588 | * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. | |
589 | * In the target guest dr6: | |
590 | * FIXED_1 bits should always be set. | |
591 | * Active low bits should be cleared if 1-setting in payload. | |
592 | * Active high bits should be set if 1-setting in payload. | |
593 | * | |
594 | * Note, the payload is compatible with the pending debug | |
595 | * exceptions/exit qualification under VMX, that active_low bits | |
596 | * are active high in payload. | |
597 | * So they need to be flipped for DR6. | |
f10c729f | 598 | */ |
9a3ecd5e | 599 | vcpu->arch.dr6 |= DR6_ACTIVE_LOW; |
d4963e31 SC |
600 | vcpu->arch.dr6 |= ex->payload; |
601 | vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW; | |
307f1cfa OU |
602 | |
603 | /* | |
604 | * The #DB payload is defined as compatible with the 'pending | |
605 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
606 | * defined in the 'pending debug exceptions' field (enabled | |
607 | * breakpoint), it is reserved and must be zero in DR6. | |
608 | */ | |
609 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 610 | break; |
da998b46 | 611 | case PF_VECTOR: |
d4963e31 | 612 | vcpu->arch.cr2 = ex->payload; |
da998b46 JM |
613 | break; |
614 | } | |
615 | ||
d4963e31 SC |
616 | ex->has_payload = false; |
617 | ex->payload = 0; | |
da998b46 JM |
618 | } |
619 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
620 | ||
7709aba8 SC |
621 | static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector, |
622 | bool has_error_code, u32 error_code, | |
623 | bool has_payload, unsigned long payload) | |
624 | { | |
625 | struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit; | |
626 | ||
627 | ex->vector = vector; | |
628 | ex->injected = false; | |
629 | ex->pending = true; | |
630 | ex->has_error_code = has_error_code; | |
631 | ex->error_code = error_code; | |
632 | ex->has_payload = has_payload; | |
633 | ex->payload = payload; | |
634 | } | |
635 | ||
f9697df2 ML |
636 | /* Forcibly leave the nested mode in cases like a vCPU reset */ |
637 | static void kvm_leave_nested(struct kvm_vcpu *vcpu) | |
638 | { | |
639 | kvm_x86_ops.nested_ops->leave_nested(vcpu); | |
640 | } | |
641 | ||
3fd28fce | 642 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 643 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 644 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
645 | { |
646 | u32 prev_nr; | |
647 | int class1, class2; | |
648 | ||
3842d135 AK |
649 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
650 | ||
7709aba8 SC |
651 | /* |
652 | * If the exception is destined for L2 and isn't being reinjected, | |
653 | * morph it to a VM-Exit if L1 wants to intercept the exception. A | |
654 | * previously injected exception is not checked because it was checked | |
655 | * when it was original queued, and re-checking is incorrect if _L1_ | |
656 | * injected the exception, in which case it's exempt from interception. | |
657 | */ | |
658 | if (!reinject && is_guest_mode(vcpu) && | |
659 | kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) { | |
660 | kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code, | |
661 | has_payload, payload); | |
662 | return; | |
663 | } | |
664 | ||
664f8e26 | 665 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 666 | queue: |
664f8e26 WL |
667 | if (reinject) { |
668 | /* | |
7709aba8 SC |
669 | * On VM-Entry, an exception can be pending if and only |
670 | * if event injection was blocked by nested_run_pending. | |
671 | * In that case, however, vcpu_enter_guest() requests an | |
672 | * immediate exit, and the guest shouldn't proceed far | |
673 | * enough to need reinjection. | |
664f8e26 | 674 | */ |
7709aba8 | 675 | WARN_ON_ONCE(kvm_is_exception_pending(vcpu)); |
664f8e26 | 676 | vcpu->arch.exception.injected = true; |
91e86d22 JM |
677 | if (WARN_ON_ONCE(has_payload)) { |
678 | /* | |
679 | * A reinjected event has already | |
680 | * delivered its payload. | |
681 | */ | |
682 | has_payload = false; | |
683 | payload = 0; | |
684 | } | |
664f8e26 WL |
685 | } else { |
686 | vcpu->arch.exception.pending = true; | |
687 | vcpu->arch.exception.injected = false; | |
688 | } | |
3fd28fce | 689 | vcpu->arch.exception.has_error_code = has_error; |
d4963e31 | 690 | vcpu->arch.exception.vector = nr; |
3fd28fce | 691 | vcpu->arch.exception.error_code = error_code; |
91e86d22 JM |
692 | vcpu->arch.exception.has_payload = has_payload; |
693 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 694 | if (!is_guest_mode(vcpu)) |
d4963e31 SC |
695 | kvm_deliver_exception_payload(vcpu, |
696 | &vcpu->arch.exception); | |
3fd28fce ED |
697 | return; |
698 | } | |
699 | ||
700 | /* to check exception */ | |
d4963e31 | 701 | prev_nr = vcpu->arch.exception.vector; |
3fd28fce ED |
702 | if (prev_nr == DF_VECTOR) { |
703 | /* triple fault -> shutdown */ | |
a8eeb04a | 704 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
705 | return; |
706 | } | |
707 | class1 = exception_class(prev_nr); | |
708 | class2 = exception_class(nr); | |
81601495 SC |
709 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) || |
710 | (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 | 711 | /* |
81601495 SC |
712 | * Synthesize #DF. Clear the previously injected or pending |
713 | * exception so as not to incorrectly trigger shutdown. | |
664f8e26 | 714 | */ |
664f8e26 | 715 | vcpu->arch.exception.injected = false; |
81601495 SC |
716 | vcpu->arch.exception.pending = false; |
717 | ||
718 | kvm_queue_exception_e(vcpu, DF_VECTOR, 0); | |
719 | } else { | |
3fd28fce ED |
720 | /* replace previous exception with a new one in a hope |
721 | that instruction re-execution will regenerate lost | |
722 | exception */ | |
723 | goto queue; | |
81601495 | 724 | } |
3fd28fce ED |
725 | } |
726 | ||
298101da AK |
727 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
728 | { | |
91e86d22 | 729 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
730 | } |
731 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
732 | ||
ce7ddec4 JR |
733 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
734 | { | |
91e86d22 | 735 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
736 | } |
737 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
738 | ||
4d5523cf PB |
739 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
740 | unsigned long payload) | |
f10c729f JM |
741 | { |
742 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
743 | } | |
4d5523cf | 744 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 745 | |
da998b46 JM |
746 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
747 | u32 error_code, unsigned long payload) | |
748 | { | |
749 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
750 | true, payload, false); | |
751 | } | |
752 | ||
6affcbed | 753 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 754 | { |
db8fcefa AP |
755 | if (err) |
756 | kvm_inject_gp(vcpu, 0); | |
757 | else | |
6affcbed KH |
758 | return kvm_skip_emulated_instruction(vcpu); |
759 | ||
760 | return 1; | |
db8fcefa AP |
761 | } |
762 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 763 | |
d2f7d498 HW |
764 | static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err) |
765 | { | |
766 | if (err) { | |
767 | kvm_inject_gp(vcpu, 0); | |
768 | return 1; | |
769 | } | |
770 | ||
771 | return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP | | |
772 | EMULTYPE_COMPLETE_USER_EXIT); | |
773 | } | |
774 | ||
6389ee94 | 775 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
776 | { |
777 | ++vcpu->stat.pf_guest; | |
7709aba8 SC |
778 | |
779 | /* | |
780 | * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of | |
781 | * whether or not L1 wants to intercept "regular" #PF. | |
782 | */ | |
783 | if (is_guest_mode(vcpu) && fault->async_page_fault) | |
784 | kvm_queue_exception_vmexit(vcpu, PF_VECTOR, | |
785 | true, fault->error_code, | |
786 | true, fault->address); | |
787 | else | |
da998b46 JM |
788 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, |
789 | fault->address); | |
c3c91fee AK |
790 | } |
791 | ||
7709aba8 | 792 | void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
53b3d8e9 | 793 | struct x86_exception *fault) |
d4f8cf66 | 794 | { |
0cd665bd | 795 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
796 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
797 | ||
0cd665bd PB |
798 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
799 | vcpu->arch.walk_mmu; | |
ef54bcfe | 800 | |
ee1fa209 JS |
801 | /* |
802 | * Invalidate the TLB entry for the faulting address, if it exists, | |
803 | * else the access will fault indefinitely (and to emulate hardware). | |
804 | */ | |
805 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
806 | !(fault->error_code & PFERR_RSVD_MASK)) | |
753b43c9 | 807 | kvm_mmu_invalidate_addr(vcpu, fault_mmu, fault->address, |
cd42853e | 808 | KVM_MMU_ROOT_CURRENT); |
ee1fa209 JS |
809 | |
810 | fault_mmu->inject_page_fault(vcpu, fault); | |
d4f8cf66 | 811 | } |
53b3d8e9 | 812 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 813 | |
3419ffc8 SY |
814 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
815 | { | |
7460fb4a AK |
816 | atomic_inc(&vcpu->arch.nmi_queued); |
817 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 | 818 | } |
3419ffc8 | 819 | |
298101da AK |
820 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
821 | { | |
91e86d22 | 822 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
823 | } |
824 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
825 | ||
ce7ddec4 JR |
826 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
827 | { | |
91e86d22 | 828 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
829 | } |
830 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
831 | ||
0a79b009 AK |
832 | /* |
833 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
834 | * a #GP and return false. | |
835 | */ | |
836 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 837 | { |
b3646477 | 838 | if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) |
0a79b009 AK |
839 | return true; |
840 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
841 | return false; | |
298101da AK |
842 | } |
843 | ||
16f8a6f9 NA |
844 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
845 | { | |
607475cf | 846 | if ((dr != 4 && dr != 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE)) |
16f8a6f9 NA |
847 | return true; |
848 | ||
849 | kvm_queue_exception(vcpu, UD_VECTOR); | |
850 | return false; | |
851 | } | |
852 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
853 | ||
16cfacc8 SC |
854 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
855 | { | |
5b7f575c | 856 | return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); |
16cfacc8 SC |
857 | } |
858 | ||
a03490ed | 859 | /* |
16cfacc8 | 860 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 861 | */ |
2df4a5eb | 862 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 863 | { |
2df4a5eb | 864 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
a03490ed | 865 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; |
15cabbc2 | 866 | gpa_t real_gpa; |
a03490ed CO |
867 | int i; |
868 | int ret; | |
ff03a073 | 869 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 870 | |
15cabbc2 SC |
871 | /* |
872 | * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated | |
873 | * to an L1 GPA. | |
874 | */ | |
c59a0f57 LJ |
875 | real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn), |
876 | PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); | |
6e1d2a3f | 877 | if (real_gpa == INVALID_GPA) |
15cabbc2 SC |
878 | return 0; |
879 | ||
94c641ba | 880 | /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ |
15cabbc2 | 881 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, |
94c641ba | 882 | cr3 & GENMASK(11, 5), sizeof(pdpte)); |
15cabbc2 SC |
883 | if (ret < 0) |
884 | return 0; | |
885 | ||
a03490ed | 886 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { |
812f30b2 | 887 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 888 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
15cabbc2 | 889 | return 0; |
a03490ed CO |
890 | } |
891 | } | |
a03490ed | 892 | |
6b123c3a LJ |
893 | /* |
894 | * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled. | |
895 | * Shadow page roots need to be reconstructed instead. | |
896 | */ | |
897 | if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs))) | |
0c1c92f1 | 898 | kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT); |
6b123c3a | 899 | |
46cbc040 PB |
900 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
901 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); | |
902 | kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); | |
158a48ec ML |
903 | vcpu->arch.pdptrs_from_userspace = false; |
904 | ||
15cabbc2 | 905 | return 1; |
a03490ed | 906 | } |
cc4b6871 | 907 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 908 | |
26a0652c SC |
909 | static bool kvm_is_valid_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
910 | { | |
911 | #ifdef CONFIG_X86_64 | |
912 | if (cr0 & 0xffffffff00000000UL) | |
913 | return false; | |
914 | #endif | |
915 | ||
916 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) | |
917 | return false; | |
918 | ||
919 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) | |
920 | return false; | |
921 | ||
922 | return static_call(kvm_x86_is_valid_cr0)(vcpu, cr0); | |
923 | } | |
924 | ||
f27ad38a TL |
925 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) |
926 | { | |
01b31714 MK |
927 | /* |
928 | * CR0.WP is incorporated into the MMU role, but only for non-nested, | |
e40bcf9f MK |
929 | * indirect shadow MMUs. If paging is disabled, no updates are needed |
930 | * as there are no permission bits to emulate. If TDP is enabled, the | |
931 | * MMU's metadata needs to be updated, e.g. so that emulating guest | |
932 | * translations does the right thing, but there's no need to unload the | |
933 | * root as CR0.WP doesn't affect SPTEs. | |
01b31714 | 934 | */ |
e40bcf9f MK |
935 | if ((cr0 ^ old_cr0) == X86_CR0_WP) { |
936 | if (!(cr0 & X86_CR0_PG)) | |
937 | return; | |
938 | ||
939 | if (tdp_enabled) { | |
940 | kvm_init_mmu(vcpu); | |
941 | return; | |
942 | } | |
01b31714 MK |
943 | } |
944 | ||
f27ad38a TL |
945 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
946 | kvm_clear_async_pf_completion_queue(vcpu); | |
947 | kvm_async_pf_hash_reset(vcpu); | |
b5f61c03 PB |
948 | |
949 | /* | |
950 | * Clearing CR0.PG is defined to flush the TLB from the guest's | |
951 | * perspective. | |
952 | */ | |
953 | if (!(cr0 & X86_CR0_PG)) | |
954 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
f27ad38a TL |
955 | } |
956 | ||
20f632bd | 957 | if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) |
f27ad38a TL |
958 | kvm_mmu_reset_context(vcpu); |
959 | ||
960 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && | |
961 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
962 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
963 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
964 | } | |
965 | EXPORT_SYMBOL_GPL(kvm_post_set_cr0); | |
966 | ||
49a9b07e | 967 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 968 | { |
aad82703 | 969 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
aad82703 | 970 | |
26a0652c | 971 | if (!kvm_is_valid_cr0(vcpu, cr0)) |
0f12244f | 972 | return 1; |
a03490ed | 973 | |
26a0652c | 974 | cr0 |= X86_CR0_ET; |
a03490ed | 975 | |
26a0652c SC |
976 | /* Write to CR0 reserved bits are ignored, even on Intel. */ |
977 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 978 | |
a03490ed | 979 | #ifdef CONFIG_X86_64 |
05487215 SC |
980 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
981 | (cr0 & X86_CR0_PG)) { | |
982 | int cs_db, cs_l; | |
983 | ||
984 | if (!is_pae(vcpu)) | |
985 | return 1; | |
b3646477 | 986 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
05487215 | 987 | if (cs_l) |
0f12244f | 988 | return 1; |
a03490ed | 989 | } |
05487215 SC |
990 | #endif |
991 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
e63f315d | 992 | is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) && |
2df4a5eb | 993 | !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) |
05487215 | 994 | return 1; |
a03490ed | 995 | |
777ab82d | 996 | if (!(cr0 & X86_CR0_PG) && |
607475cf | 997 | (is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))) |
ad756a16 MJ |
998 | return 1; |
999 | ||
b3646477 | 1000 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
a03490ed | 1001 | |
f27ad38a | 1002 | kvm_post_set_cr0(vcpu, old_cr0, cr0); |
b18d5431 | 1003 | |
0f12244f GN |
1004 | return 0; |
1005 | } | |
2d3ad1f4 | 1006 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 1007 | |
2d3ad1f4 | 1008 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 1009 | { |
49a9b07e | 1010 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 1011 | } |
2d3ad1f4 | 1012 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 1013 | |
139a12cf | 1014 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 1015 | { |
16809ecd TL |
1016 | if (vcpu->arch.guest_state_protected) |
1017 | return; | |
1018 | ||
607475cf | 1019 | if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) { |
139a12cf AL |
1020 | |
1021 | if (vcpu->arch.xcr0 != host_xcr0) | |
1022 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
1023 | ||
1024 | if (vcpu->arch.xsaves_enabled && | |
1025 | vcpu->arch.ia32_xss != host_xss) | |
1026 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
1027 | } | |
37486135 | 1028 | |
056b9919 | 1029 | if (cpu_feature_enabled(X86_FEATURE_PKU) && |
945024d7 JK |
1030 | vcpu->arch.pkru != vcpu->arch.host_pkru && |
1031 | ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || | |
607475cf | 1032 | kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) |
72a6c08c | 1033 | write_pkru(vcpu->arch.pkru); |
42bdf991 | 1034 | } |
139a12cf | 1035 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 1036 | |
139a12cf | 1037 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 1038 | { |
16809ecd TL |
1039 | if (vcpu->arch.guest_state_protected) |
1040 | return; | |
1041 | ||
056b9919 | 1042 | if (cpu_feature_enabled(X86_FEATURE_PKU) && |
945024d7 | 1043 | ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || |
607475cf | 1044 | kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) { |
37486135 BM |
1045 | vcpu->arch.pkru = rdpkru(); |
1046 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
72a6c08c | 1047 | write_pkru(vcpu->arch.host_pkru); |
37486135 BM |
1048 | } |
1049 | ||
607475cf | 1050 | if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) { |
139a12cf AL |
1051 | |
1052 | if (vcpu->arch.xcr0 != host_xcr0) | |
1053 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
1054 | ||
1055 | if (vcpu->arch.xsaves_enabled && | |
1056 | vcpu->arch.ia32_xss != host_xss) | |
1057 | wrmsrl(MSR_IA32_XSS, host_xss); | |
1058 | } | |
1059 | ||
42bdf991 | 1060 | } |
139a12cf | 1061 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 1062 | |
ba1f77c5 | 1063 | #ifdef CONFIG_X86_64 |
988896bb LB |
1064 | static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu) |
1065 | { | |
ee519b3a | 1066 | return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC; |
988896bb | 1067 | } |
ba1f77c5 | 1068 | #endif |
988896bb | 1069 | |
69b0049a | 1070 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 1071 | { |
56c103ec LJ |
1072 | u64 xcr0 = xcr; |
1073 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 1074 | u64 valid_bits; |
2acf923e DC |
1075 | |
1076 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
1077 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
1078 | return 1; | |
d91cab78 | 1079 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 1080 | return 1; |
d91cab78 | 1081 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 1082 | return 1; |
46c34cb0 PB |
1083 | |
1084 | /* | |
1085 | * Do not allow the guest to set bits that we do not support | |
1086 | * saving. However, xcr0 bit 0 is always set, even if the | |
e8f65b9b | 1087 | * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). |
46c34cb0 | 1088 | */ |
ee519b3a | 1089 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 1090 | if (xcr0 & ~valid_bits) |
2acf923e | 1091 | return 1; |
46c34cb0 | 1092 | |
d91cab78 DH |
1093 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
1094 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
1095 | return 1; |
1096 | ||
d91cab78 DH |
1097 | if (xcr0 & XFEATURE_MASK_AVX512) { |
1098 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 1099 | return 1; |
d91cab78 | 1100 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
1101 | return 1; |
1102 | } | |
86aff7a4 JL |
1103 | |
1104 | if ((xcr0 & XFEATURE_MASK_XTILE) && | |
1105 | ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE)) | |
1106 | return 1; | |
1107 | ||
2acf923e | 1108 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 1109 | |
d91cab78 | 1110 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 1111 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
1112 | return 0; |
1113 | } | |
1114 | ||
92f9895c | 1115 | int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) |
2acf923e | 1116 | { |
50b2d49b | 1117 | /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */ |
92f9895c SC |
1118 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || |
1119 | __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { | |
1120 | kvm_inject_gp(vcpu, 0); | |
1121 | return 1; | |
1122 | } | |
bbefd4fc | 1123 | |
92f9895c | 1124 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e | 1125 | } |
92f9895c | 1126 | EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); |
2acf923e | 1127 | |
c33f6f22 | 1128 | bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 1129 | { |
b11306b5 | 1130 | if (cr4 & cr4_reserved_bits) |
ee69c92b | 1131 | return false; |
b9baba86 | 1132 | |
b899c132 | 1133 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
ee69c92b | 1134 | return false; |
3ca94192 | 1135 | |
c33f6f22 SC |
1136 | return true; |
1137 | } | |
1138 | EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4); | |
1139 | ||
1140 | static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1141 | { | |
1142 | return __kvm_is_valid_cr4(vcpu, cr4) && | |
1143 | static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); | |
3ca94192 WL |
1144 | } |
1145 | ||
5b51cb13 TL |
1146 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) |
1147 | { | |
b5f61c03 PB |
1148 | if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) |
1149 | kvm_mmu_reset_context(vcpu); | |
1150 | ||
509bfe3d | 1151 | /* |
509bfe3d LJ |
1152 | * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB |
1153 | * according to the SDM; however, stale prev_roots could be reused | |
1154 | * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we | |
b5f61c03 PB |
1155 | * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST |
1156 | * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed, | |
1157 | * so fall through. | |
509bfe3d | 1158 | */ |
b5f61c03 PB |
1159 | if (!tdp_enabled && |
1160 | (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) | |
f6d0a252 | 1161 | kvm_mmu_unload(vcpu); |
b5f61c03 PB |
1162 | |
1163 | /* | |
1164 | * The TLB has to be flushed for all PCIDs if any of the following | |
1165 | * (architecturally required) changes happen: | |
1166 | * - CR4.PCIDE is changed from 1 to 0 | |
1167 | * - CR4.PGE is toggled | |
509bfe3d | 1168 | * |
b5f61c03 | 1169 | * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT. |
509bfe3d | 1170 | */ |
b5f61c03 PB |
1171 | if (((cr4 ^ old_cr4) & X86_CR4_PGE) || |
1172 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
55261738 | 1173 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
b5f61c03 PB |
1174 | |
1175 | /* | |
1176 | * The TLB has to be flushed for the current PCID if any of the | |
1177 | * following (architecturally required) changes happen: | |
1178 | * - CR4.SMEP is changed from 0 to 1 | |
1179 | * - CR4.PAE is toggled | |
1180 | */ | |
1181 | else if (((cr4 ^ old_cr4) & X86_CR4_PAE) || | |
1182 | ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP))) | |
1183 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
1184 | ||
3ca94192 | 1185 | } |
5b51cb13 | 1186 | EXPORT_SYMBOL_GPL(kvm_post_set_cr4); |
3ca94192 WL |
1187 | |
1188 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1189 | { | |
1190 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
3ca94192 | 1191 | |
ee69c92b | 1192 | if (!kvm_is_valid_cr4(vcpu, cr4)) |
ae3e61e1 PB |
1193 | return 1; |
1194 | ||
a03490ed | 1195 | if (is_long_mode(vcpu)) { |
0f12244f GN |
1196 | if (!(cr4 & X86_CR4_PAE)) |
1197 | return 1; | |
d74fcfc1 SC |
1198 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
1199 | return 1; | |
a2edf57f | 1200 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
a37ebdce | 1201 | && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS) |
2df4a5eb | 1202 | && !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) |
0f12244f GN |
1203 | return 1; |
1204 | ||
ad756a16 | 1205 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
ad756a16 MJ |
1206 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ |
1207 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1208 | return 1; | |
1209 | } | |
1210 | ||
b3646477 | 1211 | static_call(kvm_x86_set_cr4)(vcpu, cr4); |
a03490ed | 1212 | |
5b51cb13 | 1213 | kvm_post_set_cr4(vcpu, old_cr4, cr4); |
2acf923e | 1214 | |
0f12244f GN |
1215 | return 0; |
1216 | } | |
2d3ad1f4 | 1217 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1218 | |
21823fbd SC |
1219 | static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) |
1220 | { | |
1221 | struct kvm_mmu *mmu = vcpu->arch.mmu; | |
1222 | unsigned long roots_to_free = 0; | |
1223 | int i; | |
1224 | ||
e45e9e39 LJ |
1225 | /* |
1226 | * MOV CR3 and INVPCID are usually not intercepted when using TDP, but | |
1227 | * this is reachable when running EPT=1 and unrestricted_guest=0, and | |
1228 | * also via the emulator. KVM's TDP page tables are not in the scope of | |
1229 | * the invalidation, but the guest's TLB entries need to be flushed as | |
1230 | * the CPU may have cached entries in its TLB for the target PCID. | |
1231 | */ | |
1232 | if (unlikely(tdp_enabled)) { | |
1233 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
1234 | return; | |
1235 | } | |
1236 | ||
21823fbd SC |
1237 | /* |
1238 | * If neither the current CR3 nor any of the prev_roots use the given | |
1239 | * PCID, then nothing needs to be done here because a resync will | |
1240 | * happen anyway before switching to any other CR3. | |
1241 | */ | |
1242 | if (kvm_get_active_pcid(vcpu) == pcid) { | |
e62f1aa8 | 1243 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
21823fbd SC |
1244 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1245 | } | |
1246 | ||
509bfe3d LJ |
1247 | /* |
1248 | * If PCID is disabled, there is no need to free prev_roots even if the | |
1249 | * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB | |
1250 | * with PCIDE=0. | |
1251 | */ | |
607475cf | 1252 | if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) |
509bfe3d LJ |
1253 | return; |
1254 | ||
21823fbd SC |
1255 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
1256 | if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) | |
1257 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
1258 | ||
0c1c92f1 | 1259 | kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free); |
21823fbd SC |
1260 | } |
1261 | ||
2390218b | 1262 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1263 | { |
ade61e28 | 1264 | bool skip_tlb_flush = false; |
21823fbd | 1265 | unsigned long pcid = 0; |
ac146235 | 1266 | #ifdef CONFIG_X86_64 |
607475cf | 1267 | if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) { |
208320ba JS |
1268 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1269 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
21823fbd | 1270 | pcid = cr3 & X86_CR3_PCID_MASK; |
ade61e28 | 1271 | } |
ac146235 | 1272 | #endif |
9d88fca7 | 1273 | |
c7313155 | 1274 | /* PDPTRs are always reloaded for PAE paging. */ |
21823fbd SC |
1275 | if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) |
1276 | goto handle_tlb_flush; | |
d835dfec | 1277 | |
886bbcc7 SC |
1278 | /* |
1279 | * Do not condition the GPA check on long mode, this helper is used to | |
1280 | * stuff CR3, e.g. for RSM emulation, and there is no guarantee that | |
1281 | * the current vCPU mode is accurate. | |
1282 | */ | |
1283 | if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) | |
d1cd3ce9 | 1284 | return 1; |
886bbcc7 | 1285 | |
2df4a5eb | 1286 | if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) |
346874c9 | 1287 | return 1; |
a03490ed | 1288 | |
21823fbd | 1289 | if (cr3 != kvm_read_cr3(vcpu)) |
b5129100 | 1290 | kvm_mmu_new_pgd(vcpu, cr3); |
21823fbd | 1291 | |
0f12244f | 1292 | vcpu->arch.cr3 = cr3; |
3883bc9d | 1293 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); |
405329fc | 1294 | /* Do not call post_set_cr3, we do not get here for confidential guests. */ |
7c390d35 | 1295 | |
21823fbd SC |
1296 | handle_tlb_flush: |
1297 | /* | |
1298 | * A load of CR3 that flushes the TLB flushes only the current PCID, | |
1299 | * even if PCID is disabled, in which case PCID=0 is flushed. It's a | |
1300 | * moot point in the end because _disabling_ PCID will flush all PCIDs, | |
1301 | * and it's impossible to use a non-zero PCID when PCID is disabled, | |
1302 | * i.e. only PCID=0 can be relevant. | |
1303 | */ | |
1304 | if (!skip_tlb_flush) | |
1305 | kvm_invalidate_pcid(vcpu, pcid); | |
1306 | ||
0f12244f GN |
1307 | return 0; |
1308 | } | |
2d3ad1f4 | 1309 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1310 | |
eea1cff9 | 1311 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1312 | { |
0f12244f GN |
1313 | if (cr8 & CR8_RESERVED_BITS) |
1314 | return 1; | |
35754c98 | 1315 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1316 | kvm_lapic_set_tpr(vcpu, cr8); |
1317 | else | |
ad312c7c | 1318 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1319 | return 0; |
1320 | } | |
2d3ad1f4 | 1321 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1322 | |
2d3ad1f4 | 1323 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1324 | { |
35754c98 | 1325 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1326 | return kvm_lapic_get_cr8(vcpu); |
1327 | else | |
ad312c7c | 1328 | return vcpu->arch.cr8; |
a03490ed | 1329 | } |
2d3ad1f4 | 1330 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1331 | |
ae561ede NA |
1332 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1333 | { | |
1334 | int i; | |
1335 | ||
1336 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1337 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1338 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae561ede NA |
1339 | } |
1340 | } | |
1341 | ||
7c86663b | 1342 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1343 | { |
1344 | unsigned long dr7; | |
1345 | ||
1346 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1347 | dr7 = vcpu->arch.guest_debug_dr7; | |
1348 | else | |
1349 | dr7 = vcpu->arch.dr7; | |
b3646477 | 1350 | static_call(kvm_x86_set_dr7)(vcpu, dr7); |
360b948d PB |
1351 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1352 | if (dr7 & DR7_BP_EN_MASK) | |
1353 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1354 | } |
7c86663b | 1355 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1356 | |
6f43ed01 NA |
1357 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1358 | { | |
1359 | u64 fixed = DR6_FIXED_1; | |
1360 | ||
d6321d49 | 1361 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 | 1362 | fixed |= DR6_RTM; |
e8ea85fb CQ |
1363 | |
1364 | if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) | |
1365 | fixed |= DR6_BUS_LOCK; | |
6f43ed01 NA |
1366 | return fixed; |
1367 | } | |
1368 | ||
996ff542 | 1369 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1370 | { |
ea740059 MP |
1371 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1372 | ||
020df079 GN |
1373 | switch (dr) { |
1374 | case 0 ... 3: | |
ea740059 | 1375 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1376 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1377 | vcpu->arch.eff_db[dr] = val; | |
1378 | break; | |
1379 | case 4: | |
020df079 | 1380 | case 6: |
f5f6145e | 1381 | if (!kvm_dr6_valid(val)) |
996ff542 | 1382 | return 1; /* #GP */ |
6f43ed01 | 1383 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1384 | break; |
1385 | case 5: | |
020df079 | 1386 | default: /* 7 */ |
b91991bf | 1387 | if (!kvm_dr7_valid(val)) |
996ff542 | 1388 | return 1; /* #GP */ |
020df079 | 1389 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1390 | kvm_update_dr7(vcpu); |
020df079 GN |
1391 | break; |
1392 | } | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | EXPORT_SYMBOL_GPL(kvm_set_dr); | |
1397 | ||
29d6ca41 | 1398 | void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1399 | { |
ea740059 MP |
1400 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1401 | ||
020df079 GN |
1402 | switch (dr) { |
1403 | case 0 ... 3: | |
ea740059 | 1404 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1405 | break; |
1406 | case 4: | |
020df079 | 1407 | case 6: |
5679b803 | 1408 | *val = vcpu->arch.dr6; |
020df079 GN |
1409 | break; |
1410 | case 5: | |
020df079 GN |
1411 | default: /* 7 */ |
1412 | *val = vcpu->arch.dr7; | |
1413 | break; | |
1414 | } | |
338dbc97 | 1415 | } |
020df079 GN |
1416 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1417 | ||
c483c454 | 1418 | int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) |
022cd0e8 | 1419 | { |
de3cd117 | 1420 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 | 1421 | u64 data; |
022cd0e8 | 1422 | |
c483c454 SC |
1423 | if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { |
1424 | kvm_inject_gp(vcpu, 0); | |
1425 | return 1; | |
1426 | } | |
1427 | ||
de3cd117 SC |
1428 | kvm_rax_write(vcpu, (u32)data); |
1429 | kvm_rdx_write(vcpu, data >> 32); | |
c483c454 | 1430 | return kvm_skip_emulated_instruction(vcpu); |
022cd0e8 | 1431 | } |
c483c454 | 1432 | EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); |
022cd0e8 | 1433 | |
043405e1 | 1434 | /* |
a3064257 SC |
1435 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) track |
1436 | * the set of MSRs that KVM exposes to userspace through KVM_GET_MSRS, | |
1437 | * KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. msrs_to_save holds MSRs that | |
1438 | * require host support, i.e. should be probed via RDMSR. emulated_msrs holds | |
1439 | * MSRs that KVM emulates without strictly requiring host support. | |
1440 | * msr_based_features holds MSRs that enumerate features, i.e. are effectively | |
1441 | * CPUID leafs. Note, msr_based_features isn't mutually exclusive with | |
1442 | * msrs_to_save and emulated_msrs. | |
043405e1 | 1443 | */ |
e3267cbb | 1444 | |
2374b731 | 1445 | static const u32 msrs_to_save_base[] = { |
043405e1 | 1446 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1447 | MSR_STAR, |
043405e1 CO |
1448 | #ifdef CONFIG_X86_64 |
1449 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1450 | #endif | |
b3897a49 | 1451 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1452 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
b9846a69 | 1453 | MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL, |
bf8c55d8 CP |
1454 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1455 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1456 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1457 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1458 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1459 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1460 | MSR_IA32_UMWAIT_CONTROL, |
1461 | ||
2374b731 SC |
1462 | MSR_IA32_XFD, MSR_IA32_XFD_ERR, |
1463 | }; | |
1464 | ||
1465 | static const u32 msrs_to_save_pmu[] = { | |
e2ada66e | 1466 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
9fb12fe5 | 1467 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, |
e2ada66e JM |
1468 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, |
1469 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
4f1fa2a1 LX |
1470 | MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, |
1471 | ||
1472 | /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */ | |
e2ada66e JM |
1473 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, |
1474 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1475 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1476 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
e2ada66e JM |
1477 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1478 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1479 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1480 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
e1fc1553 FM |
1481 | |
1482 | MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, | |
1483 | MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, | |
556f3c9a LX |
1484 | |
1485 | /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */ | |
e1fc1553 FM |
1486 | MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, |
1487 | MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, | |
1488 | MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, | |
1489 | MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, | |
4a277189 LX |
1490 | |
1491 | MSR_AMD64_PERF_CNTR_GLOBAL_CTL, | |
1492 | MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, | |
1493 | MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, | |
043405e1 CO |
1494 | }; |
1495 | ||
2374b731 SC |
1496 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) + |
1497 | ARRAY_SIZE(msrs_to_save_pmu)]; | |
043405e1 CO |
1498 | static unsigned num_msrs_to_save; |
1499 | ||
7a5ee6ed | 1500 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1501 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1502 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1503 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1504 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1505 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1506 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1507 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1508 | HV_X64_MSR_RESET, |
11c4b1ca | 1509 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1510 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1511 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1512 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1513 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 | 1514 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
2be1bd3a | 1515 | HV_X64_MSR_TSC_EMULATION_STATUS, HV_X64_MSR_TSC_INVARIANT_CONTROL, |
f97f5a56 JD |
1516 | HV_X64_MSR_SYNDBG_OPTIONS, |
1517 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1518 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1519 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1520 | |
1521 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1522 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1523 | |
ba904635 | 1524 | MSR_IA32_TSC_ADJUST, |
09141ec0 | 1525 | MSR_IA32_TSC_DEADLINE, |
2bdb76c0 | 1526 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1527 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1528 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1529 | MSR_IA32_MCG_STATUS, |
1530 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1531 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1532 | MSR_IA32_SMBASE, |
52797bf9 | 1533 | MSR_SMI_COUNT, |
db2336a8 KH |
1534 | MSR_PLATFORM_INFO, |
1535 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1536 | MSR_AMD64_VIRT_SPEC_CTRL, |
5228eb96 | 1537 | MSR_AMD64_TSC_RATIO, |
6c6a2ab9 | 1538 | MSR_IA32_POWER_CTL, |
99634e3e | 1539 | MSR_IA32_UCODE_REV, |
191c8137 | 1540 | |
95c5c7c7 | 1541 | /* |
a3064257 SC |
1542 | * KVM always supports the "true" VMX control MSRs, even if the host |
1543 | * does not. The VMX MSRs as a whole are considered "emulated" as KVM | |
1544 | * doesn't strictly require them to exist in the host (ignoring that | |
1545 | * KVM would refuse to load in the first place if the core set of MSRs | |
1546 | * aren't supported). | |
95c5c7c7 PB |
1547 | */ |
1548 | MSR_IA32_VMX_BASIC, | |
1549 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1550 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1551 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1552 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1553 | MSR_IA32_VMX_MISC, | |
1554 | MSR_IA32_VMX_CR0_FIXED0, | |
1555 | MSR_IA32_VMX_CR4_FIXED0, | |
1556 | MSR_IA32_VMX_VMCS_ENUM, | |
1557 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1558 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1559 | MSR_IA32_VMX_VMFUNC, | |
1560 | ||
191c8137 | 1561 | MSR_K7_HWCR, |
2d5ba19b | 1562 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1563 | }; |
1564 | ||
7a5ee6ed | 1565 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1566 | static unsigned num_emulated_msrs; |
1567 | ||
801e459a | 1568 | /* |
9eb6ba31 SC |
1569 | * List of MSRs that control the existence of MSR-based features, i.e. MSRs |
1570 | * that are effectively CPUID leafs. VMX MSRs are also included in the set of | |
1571 | * feature MSRs, but are handled separately to allow expedited lookups. | |
801e459a | 1572 | */ |
9eb6ba31 | 1573 | static const u32 msr_based_features_all_except_vmx[] = { |
2632daeb | 1574 | MSR_AMD64_DE_CFG, |
518e7b94 | 1575 | MSR_IA32_UCODE_REV, |
cd283252 | 1576 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1577 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1578 | }; |
1579 | ||
9eb6ba31 SC |
1580 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all_except_vmx) + |
1581 | (KVM_LAST_EMULATED_VMX_MSR - KVM_FIRST_EMULATED_VMX_MSR + 1)]; | |
801e459a TL |
1582 | static unsigned int num_msr_based_features; |
1583 | ||
0094f62c SC |
1584 | /* |
1585 | * All feature MSRs except uCode revID, which tracks the currently loaded uCode | |
1586 | * patch, are immutable once the vCPU model is defined. | |
1587 | */ | |
1588 | static bool kvm_is_immutable_feature_msr(u32 msr) | |
1589 | { | |
1590 | int i; | |
1591 | ||
1592 | if (msr >= KVM_FIRST_EMULATED_VMX_MSR && msr <= KVM_LAST_EMULATED_VMX_MSR) | |
1593 | return true; | |
1594 | ||
1595 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) { | |
1596 | if (msr == msr_based_features_all_except_vmx[i]) | |
1597 | return msr != MSR_IA32_UCODE_REV; | |
1598 | } | |
1599 | ||
1600 | return false; | |
1601 | } | |
1602 | ||
0204750b JM |
1603 | /* |
1604 | * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM | |
1605 | * does not yet virtualize. These include: | |
1606 | * 10 - MISC_PACKAGE_CTRLS | |
1607 | * 11 - ENERGY_FILTERING_CTL | |
1608 | * 12 - DOITM | |
1609 | * 18 - FB_CLEAR_CTRL | |
1610 | * 21 - XAPIC_DISABLE_STATUS | |
1611 | * 23 - OVERCLOCKING_STATUS | |
1612 | */ | |
1613 | ||
1614 | #define KVM_SUPPORTED_ARCH_CAP \ | |
1615 | (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \ | |
1616 | ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \ | |
1617 | ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \ | |
1618 | ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \ | |
81ac7e5d | 1619 | ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO | ARCH_CAP_GDS_NO) |
0204750b | 1620 | |
4d22c17c | 1621 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1622 | { |
4d22c17c | 1623 | u64 data = 0; |
5b76a3cf | 1624 | |
0204750b | 1625 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { |
4d22c17c | 1626 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); |
0204750b JM |
1627 | data &= KVM_SUPPORTED_ARCH_CAP; |
1628 | } | |
5b76a3cf | 1629 | |
b8e8c830 PB |
1630 | /* |
1631 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1632 | * the nested hypervisor runs with NX huge pages. If it is not, | |
d9f6e12f | 1633 | * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other |
b8e8c830 PB |
1634 | * L1 guests, so it need not worry about its own (L2) guests. |
1635 | */ | |
1636 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1637 | ||
5b76a3cf PB |
1638 | /* |
1639 | * If we're doing cache flushes (either "always" or "cond") | |
1640 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1641 | * If an outer hypervisor is doing the cache flush for us | |
02f1b0b7 | 1642 | * (ARCH_CAP_SKIP_VMENTRY_L1DFLUSH), we can safely pass that |
5b76a3cf PB |
1643 | * capability to the guest too, and if EPT is disabled we're not |
1644 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1645 | * require a nested hypervisor to do a flush of its own. | |
1646 | */ | |
1647 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1648 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1649 | ||
0c54914d PB |
1650 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1651 | data |= ARCH_CAP_RDCL_NO; | |
1652 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1653 | data |= ARCH_CAP_SSB_NO; | |
1654 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1655 | data |= ARCH_CAP_MDS_NO; | |
1656 | ||
7131636e PB |
1657 | if (!boot_cpu_has(X86_FEATURE_RTM)) { |
1658 | /* | |
1659 | * If RTM=0 because the kernel has disabled TSX, the host might | |
1660 | * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 | |
1661 | * and therefore knows that there cannot be TAA) but keep | |
1662 | * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, | |
1663 | * and we want to allow migrating those guests to tsx=off hosts. | |
1664 | */ | |
1665 | data &= ~ARCH_CAP_TAA_NO; | |
1666 | } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
cbbaa272 | 1667 | data |= ARCH_CAP_TAA_NO; |
7131636e PB |
1668 | } else { |
1669 | /* | |
1670 | * Nothing to do here; we emulate TSX_CTRL if present on the | |
1671 | * host so the guest can choose between disabling TSX or | |
1672 | * using VERW to clear CPU buffers. | |
1673 | */ | |
1674 | } | |
e1d38b63 | 1675 | |
81ac7e5d DS |
1676 | if (!boot_cpu_has_bug(X86_BUG_GDS) || gds_ucode_mitigated()) |
1677 | data |= ARCH_CAP_GDS_NO; | |
1678 | ||
5b76a3cf PB |
1679 | return data; |
1680 | } | |
5b76a3cf | 1681 | |
66421c1e WL |
1682 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1683 | { | |
1684 | switch (msr->index) { | |
cd283252 | 1685 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1686 | msr->data = kvm_get_arch_capabilities(); |
1687 | break; | |
5fe9805d SC |
1688 | case MSR_IA32_PERF_CAPABILITIES: |
1689 | msr->data = kvm_caps.supported_perf_cap; | |
1690 | break; | |
5b76a3cf | 1691 | case MSR_IA32_UCODE_REV: |
cd283252 | 1692 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1693 | break; |
66421c1e | 1694 | default: |
b3646477 | 1695 | return static_call(kvm_x86_get_msr_feature)(msr); |
66421c1e WL |
1696 | } |
1697 | return 0; | |
1698 | } | |
1699 | ||
801e459a TL |
1700 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1701 | { | |
1702 | struct kvm_msr_entry msr; | |
66421c1e | 1703 | int r; |
801e459a TL |
1704 | |
1705 | msr.index = index; | |
66421c1e | 1706 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1707 | |
1708 | if (r == KVM_MSR_RET_INVALID) { | |
1709 | /* Unconditionally clear the output for simplicity */ | |
1710 | *data = 0; | |
d632826f | 1711 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1712 | r = 0; |
12bc2132 PX |
1713 | } |
1714 | ||
66421c1e WL |
1715 | if (r) |
1716 | return r; | |
801e459a TL |
1717 | |
1718 | *data = msr.data; | |
1719 | ||
1720 | return 0; | |
1721 | } | |
1722 | ||
11988499 | 1723 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1724 | { |
8c19b6f2 KP |
1725 | if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS)) |
1726 | return false; | |
1727 | ||
1b4d56b8 | 1728 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1729 | return false; |
1b2fd70c | 1730 | |
1b4d56b8 | 1731 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1732 | return false; |
d8017474 | 1733 | |
0a629563 SC |
1734 | if (efer & (EFER_LME | EFER_LMA) && |
1735 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1736 | return false; | |
1737 | ||
1738 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1739 | return false; | |
d8017474 | 1740 | |
384bb783 | 1741 | return true; |
11988499 SC |
1742 | |
1743 | } | |
1744 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1745 | { | |
1746 | if (efer & efer_reserved_bits) | |
1747 | return false; | |
1748 | ||
1749 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1750 | } |
1751 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1752 | ||
11988499 | 1753 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1754 | { |
1755 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1756 | u64 efer = msr_info->data; |
72f211ec | 1757 | int r; |
384bb783 | 1758 | |
11988499 | 1759 | if (efer & efer_reserved_bits) |
66f61c92 | 1760 | return 1; |
384bb783 | 1761 | |
11988499 SC |
1762 | if (!msr_info->host_initiated) { |
1763 | if (!__kvm_valid_efer(vcpu, efer)) | |
1764 | return 1; | |
1765 | ||
1766 | if (is_paging(vcpu) && | |
1767 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1768 | return 1; | |
1769 | } | |
384bb783 | 1770 | |
15c4a640 | 1771 | efer &= ~EFER_LMA; |
f6801dff | 1772 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1773 | |
b3646477 | 1774 | r = static_call(kvm_x86_set_efer)(vcpu, efer); |
72f211ec ML |
1775 | if (r) { |
1776 | WARN_ON(r > 0); | |
1777 | return r; | |
1778 | } | |
a3d204e2 | 1779 | |
d6174299 | 1780 | if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS) |
aad82703 SY |
1781 | kvm_mmu_reset_context(vcpu); |
1782 | ||
b69e8cae | 1783 | return 0; |
15c4a640 CO |
1784 | } |
1785 | ||
f2b4b7dd JR |
1786 | void kvm_enable_efer_bits(u64 mask) |
1787 | { | |
1788 | efer_reserved_bits &= ~mask; | |
1789 | } | |
1790 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1791 | ||
51de8151 AG |
1792 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1793 | { | |
b318e8de SC |
1794 | struct kvm_x86_msr_filter *msr_filter; |
1795 | struct msr_bitmap_range *ranges; | |
1a155254 | 1796 | struct kvm *kvm = vcpu->kvm; |
b318e8de | 1797 | bool allowed; |
1a155254 | 1798 | int idx; |
b318e8de | 1799 | u32 i; |
1a155254 | 1800 | |
b318e8de SC |
1801 | /* x2APIC MSRs do not support filtering. */ |
1802 | if (index >= 0x800 && index <= 0x8ff) | |
1a155254 AG |
1803 | return true; |
1804 | ||
1a155254 AG |
1805 | idx = srcu_read_lock(&kvm->srcu); |
1806 | ||
b318e8de SC |
1807 | msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); |
1808 | if (!msr_filter) { | |
1809 | allowed = true; | |
1810 | goto out; | |
1811 | } | |
1812 | ||
1813 | allowed = msr_filter->default_allow; | |
1814 | ranges = msr_filter->ranges; | |
1815 | ||
1816 | for (i = 0; i < msr_filter->count; i++) { | |
1a155254 AG |
1817 | u32 start = ranges[i].base; |
1818 | u32 end = start + ranges[i].nmsrs; | |
1819 | u32 flags = ranges[i].flags; | |
1820 | unsigned long *bitmap = ranges[i].bitmap; | |
1821 | ||
1822 | if ((index >= start) && (index < end) && (flags & type)) { | |
e12fa4b9 | 1823 | allowed = test_bit(index - start, bitmap); |
1a155254 AG |
1824 | break; |
1825 | } | |
1826 | } | |
1827 | ||
b318e8de | 1828 | out: |
1a155254 AG |
1829 | srcu_read_unlock(&kvm->srcu, idx); |
1830 | ||
b318e8de | 1831 | return allowed; |
51de8151 AG |
1832 | } |
1833 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1834 | ||
15c4a640 | 1835 | /* |
f20935d8 SC |
1836 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1837 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1838 | * Returns 0 on success, non-0 otherwise. |
1839 | * Assumes vcpu_load() was already called. | |
1840 | */ | |
f20935d8 SC |
1841 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1842 | bool host_initiated) | |
15c4a640 | 1843 | { |
f20935d8 SC |
1844 | struct msr_data msr; |
1845 | ||
1846 | switch (index) { | |
854e8bb1 NA |
1847 | case MSR_FS_BASE: |
1848 | case MSR_GS_BASE: | |
1849 | case MSR_KERNEL_GS_BASE: | |
1850 | case MSR_CSTAR: | |
1851 | case MSR_LSTAR: | |
f20935d8 | 1852 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1853 | return 1; |
1854 | break; | |
1855 | case MSR_IA32_SYSENTER_EIP: | |
1856 | case MSR_IA32_SYSENTER_ESP: | |
1857 | /* | |
1858 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1859 | * non-canonical address is written on Intel but not on | |
1860 | * AMD (which ignores the top 32-bits, because it does | |
1861 | * not implement 64-bit SYSENTER). | |
1862 | * | |
1863 | * 64-bit code should hence be able to write a non-canonical | |
1864 | * value on AMD. Making the address canonical ensures that | |
1865 | * vmentry does not fail on Intel after writing a non-canonical | |
1866 | * value, and that something deterministic happens if the guest | |
1867 | * invokes 64-bit SYSENTER. | |
1868 | */ | |
1fb85d06 | 1869 | data = __canonical_address(data, vcpu_virt_addr_bits(vcpu)); |
61a05d44 SC |
1870 | break; |
1871 | case MSR_TSC_AUX: | |
1872 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1873 | return 1; | |
1874 | ||
1875 | if (!host_initiated && | |
1876 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1877 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1878 | return 1; | |
1879 | ||
1880 | /* | |
1881 | * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has | |
1882 | * incomplete and conflicting architectural behavior. Current | |
1883 | * AMD CPUs completely ignore bits 63:32, i.e. they aren't | |
1884 | * reserved and always read as zeros. Enforce Intel's reserved | |
1885 | * bits check if and only if the guest CPU is Intel, and clear | |
1886 | * the bits in all other cases. This ensures cross-vendor | |
1887 | * migration will provide consistent behavior for the guest. | |
1888 | */ | |
1889 | if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) | |
1890 | return 1; | |
1891 | ||
1892 | data = (u32)data; | |
1893 | break; | |
854e8bb1 | 1894 | } |
f20935d8 SC |
1895 | |
1896 | msr.data = data; | |
1897 | msr.index = index; | |
1898 | msr.host_initiated = host_initiated; | |
1899 | ||
b3646477 | 1900 | return static_call(kvm_x86_set_msr)(vcpu, &msr); |
15c4a640 CO |
1901 | } |
1902 | ||
6abe9c13 PX |
1903 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1904 | u32 index, u64 data, bool host_initiated) | |
1905 | { | |
1906 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1907 | ||
1908 | if (ret == KVM_MSR_RET_INVALID) | |
d632826f | 1909 | if (kvm_msr_ignored_check(index, data, true)) |
cc4cb017 | 1910 | ret = 0; |
6abe9c13 PX |
1911 | |
1912 | return ret; | |
1913 | } | |
1914 | ||
313a3dc7 | 1915 | /* |
f20935d8 SC |
1916 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1917 | * checks are bypassed if @host_initiated is %true. | |
1918 | * Returns 0 on success, non-0 otherwise. | |
1919 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1920 | */ |
edef5c36 PB |
1921 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1922 | bool host_initiated) | |
609e36d3 PB |
1923 | { |
1924 | struct msr_data msr; | |
f20935d8 | 1925 | int ret; |
609e36d3 | 1926 | |
61a05d44 SC |
1927 | switch (index) { |
1928 | case MSR_TSC_AUX: | |
1929 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1930 | return 1; | |
1931 | ||
1932 | if (!host_initiated && | |
1933 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1934 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1935 | return 1; | |
1936 | break; | |
1937 | } | |
1938 | ||
609e36d3 | 1939 | msr.index = index; |
f20935d8 | 1940 | msr.host_initiated = host_initiated; |
609e36d3 | 1941 | |
b3646477 | 1942 | ret = static_call(kvm_x86_get_msr)(vcpu, &msr); |
f20935d8 SC |
1943 | if (!ret) |
1944 | *data = msr.data; | |
1945 | return ret; | |
609e36d3 PB |
1946 | } |
1947 | ||
6abe9c13 PX |
1948 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1949 | u32 index, u64 *data, bool host_initiated) | |
1950 | { | |
1951 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1952 | ||
1953 | if (ret == KVM_MSR_RET_INVALID) { | |
1954 | /* Unconditionally clear *data for simplicity */ | |
1955 | *data = 0; | |
d632826f | 1956 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1957 | ret = 0; |
6abe9c13 PX |
1958 | } |
1959 | ||
1960 | return ret; | |
1961 | } | |
1962 | ||
ac8d6cad HW |
1963 | static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
1964 | { | |
1965 | if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) | |
1966 | return KVM_MSR_RET_FILTERED; | |
1967 | return kvm_get_msr_ignored_check(vcpu, index, data, false); | |
1968 | } | |
1969 | ||
1970 | static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data) | |
1971 | { | |
1972 | if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) | |
1973 | return KVM_MSR_RET_FILTERED; | |
1974 | return kvm_set_msr_ignored_check(vcpu, index, data, false); | |
1975 | } | |
1976 | ||
f20935d8 | 1977 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1978 | { |
6abe9c13 | 1979 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1980 | } |
1981 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1982 | |
f20935d8 SC |
1983 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1984 | { | |
6abe9c13 | 1985 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1986 | } |
1987 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1988 | ||
d2f7d498 | 1989 | static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu) |
1ae09954 | 1990 | { |
d2f7d498 | 1991 | if (!vcpu->run->msr.error) { |
1ae09954 AG |
1992 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); |
1993 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1994 | } | |
d2f7d498 | 1995 | } |
1ae09954 | 1996 | |
d2f7d498 HW |
1997 | static int complete_emulated_msr_access(struct kvm_vcpu *vcpu) |
1998 | { | |
1999 | return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error); | |
1ae09954 AG |
2000 | } |
2001 | ||
d2f7d498 HW |
2002 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) |
2003 | { | |
2004 | complete_userspace_rdmsr(vcpu); | |
2005 | return complete_emulated_msr_access(vcpu); | |
2006 | } | |
2007 | ||
2008 | static int complete_fast_msr_access(struct kvm_vcpu *vcpu) | |
1ae09954 | 2009 | { |
b3646477 | 2010 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); |
1ae09954 AG |
2011 | } |
2012 | ||
d2f7d498 HW |
2013 | static int complete_fast_rdmsr(struct kvm_vcpu *vcpu) |
2014 | { | |
2015 | complete_userspace_rdmsr(vcpu); | |
2016 | return complete_fast_msr_access(vcpu); | |
2017 | } | |
2018 | ||
1ae09954 AG |
2019 | static u64 kvm_msr_reason(int r) |
2020 | { | |
2021 | switch (r) { | |
cc4cb017 | 2022 | case KVM_MSR_RET_INVALID: |
1ae09954 | 2023 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 2024 | case KVM_MSR_RET_FILTERED: |
1a155254 | 2025 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
2026 | default: |
2027 | return KVM_MSR_EXIT_REASON_INVAL; | |
2028 | } | |
2029 | } | |
2030 | ||
2031 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
2032 | u32 exit_reason, u64 data, | |
2033 | int (*completion)(struct kvm_vcpu *vcpu), | |
2034 | int r) | |
2035 | { | |
2036 | u64 msr_reason = kvm_msr_reason(r); | |
2037 | ||
2038 | /* Check if the user wanted to know about this MSR fault */ | |
2039 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
2040 | return 0; | |
2041 | ||
2042 | vcpu->run->exit_reason = exit_reason; | |
2043 | vcpu->run->msr.error = 0; | |
2044 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
2045 | vcpu->run->msr.reason = msr_reason; | |
2046 | vcpu->run->msr.index = index; | |
2047 | vcpu->run->msr.data = data; | |
2048 | vcpu->arch.complete_userspace_io = completion; | |
2049 | ||
2050 | return 1; | |
2051 | } | |
2052 | ||
1edce0a9 SC |
2053 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
2054 | { | |
2055 | u32 ecx = kvm_rcx_read(vcpu); | |
2056 | u64 data; | |
1ae09954 AG |
2057 | int r; |
2058 | ||
ac8d6cad | 2059 | r = kvm_get_msr_with_filter(vcpu, ecx, &data); |
1edce0a9 | 2060 | |
8b474427 PB |
2061 | if (!r) { |
2062 | trace_kvm_msr_read(ecx, data); | |
2063 | ||
2064 | kvm_rax_write(vcpu, data & -1u); | |
2065 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
2066 | } else { | |
d2f7d498 HW |
2067 | /* MSR read failed? See if we should ask user space */ |
2068 | if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0, | |
2069 | complete_fast_rdmsr, r)) | |
2070 | return 0; | |
1edce0a9 | 2071 | trace_kvm_msr_read_ex(ecx); |
1edce0a9 SC |
2072 | } |
2073 | ||
b3646477 | 2074 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
2075 | } |
2076 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
2077 | ||
2078 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
2079 | { | |
2080 | u32 ecx = kvm_rcx_read(vcpu); | |
2081 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 2082 | int r; |
1edce0a9 | 2083 | |
ac8d6cad | 2084 | r = kvm_set_msr_with_filter(vcpu, ecx, data); |
1ae09954 | 2085 | |
d2f7d498 | 2086 | if (!r) { |
8b474427 | 2087 | trace_kvm_msr_write(ecx, data); |
d2f7d498 HW |
2088 | } else { |
2089 | /* MSR write failed? See if we should ask user space */ | |
2090 | if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data, | |
2091 | complete_fast_msr_access, r)) | |
2092 | return 0; | |
2093 | /* Signal all other negative errors to userspace */ | |
2094 | if (r < 0) | |
2095 | return r; | |
1edce0a9 | 2096 | trace_kvm_msr_write_ex(ecx, data); |
d2f7d498 | 2097 | } |
1edce0a9 | 2098 | |
b3646477 | 2099 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
2100 | } |
2101 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
2102 | ||
5ff3a351 SC |
2103 | int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) |
2104 | { | |
2105 | return kvm_skip_emulated_instruction(vcpu); | |
2106 | } | |
5ff3a351 SC |
2107 | |
2108 | int kvm_emulate_invd(struct kvm_vcpu *vcpu) | |
2109 | { | |
2110 | /* Treat an INVD instruction as a NOP and just skip it. */ | |
2111 | return kvm_emulate_as_nop(vcpu); | |
2112 | } | |
2113 | EXPORT_SYMBOL_GPL(kvm_emulate_invd); | |
2114 | ||
5ff3a351 SC |
2115 | int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) |
2116 | { | |
2117 | kvm_queue_exception(vcpu, UD_VECTOR); | |
2118 | return 1; | |
2119 | } | |
2120 | EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); | |
2121 | ||
bfbcc81b SC |
2122 | |
2123 | static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn) | |
5ff3a351 | 2124 | { |
43bb9e00 | 2125 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) && |
bfbcc81b SC |
2126 | !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT)) |
2127 | return kvm_handle_invalid_op(vcpu); | |
2128 | ||
8d20bd63 | 2129 | pr_warn_once("%s instruction emulated as NOP!\n", insn); |
5ff3a351 SC |
2130 | return kvm_emulate_as_nop(vcpu); |
2131 | } | |
bfbcc81b SC |
2132 | int kvm_emulate_mwait(struct kvm_vcpu *vcpu) |
2133 | { | |
2134 | return kvm_emulate_monitor_mwait(vcpu, "MWAIT"); | |
2135 | } | |
2136 | EXPORT_SYMBOL_GPL(kvm_emulate_mwait); | |
2137 | ||
2138 | int kvm_emulate_monitor(struct kvm_vcpu *vcpu) | |
2139 | { | |
2140 | return kvm_emulate_monitor_mwait(vcpu, "MONITOR"); | |
2141 | } | |
5ff3a351 SC |
2142 | EXPORT_SYMBOL_GPL(kvm_emulate_monitor); |
2143 | ||
d89d04ab | 2144 | static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
5a9f5443 | 2145 | { |
4ae7dc97 | 2146 | xfer_to_guest_mode_prepare(); |
5a9f5443 | 2147 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || |
72c3c0fe | 2148 | xfer_to_guest_mode_work_pending(); |
5a9f5443 | 2149 | } |
5a9f5443 | 2150 | |
1e9e2622 WL |
2151 | /* |
2152 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
2153 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
2154 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
2155 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
2156 | * other cases which must be called after interrupts are enabled on the host. | |
2157 | */ | |
2158 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
2159 | { | |
e1be9ac8 WL |
2160 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
2161 | return 1; | |
2162 | ||
2163 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
bd17f417 SC |
2164 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
2165 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && | |
b9964ee3 SC |
2166 | ((u32)(data >> 32) != X2APIC_BROADCAST)) |
2167 | return kvm_x2apic_icr_write(vcpu->arch.apic, data); | |
1e9e2622 WL |
2168 | |
2169 | return 1; | |
2170 | } | |
2171 | ||
ae95f566 WL |
2172 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
2173 | { | |
2174 | if (!kvm_can_use_hv_timer(vcpu)) | |
2175 | return 1; | |
2176 | ||
2177 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2178 | return 0; | |
2179 | } | |
2180 | ||
404d5d7b | 2181 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
2182 | { |
2183 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 2184 | u64 data; |
404d5d7b | 2185 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 | 2186 | |
3f2739bd SC |
2187 | kvm_vcpu_srcu_read_lock(vcpu); |
2188 | ||
1e9e2622 WL |
2189 | switch (msr) { |
2190 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 2191 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
2192 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
2193 | kvm_skip_emulated_instruction(vcpu); | |
2194 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 2195 | } |
1e9e2622 | 2196 | break; |
09141ec0 | 2197 | case MSR_IA32_TSC_DEADLINE: |
ae95f566 WL |
2198 | data = kvm_read_edx_eax(vcpu); |
2199 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
2200 | kvm_skip_emulated_instruction(vcpu); | |
2201 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
2202 | } | |
2203 | break; | |
1e9e2622 | 2204 | default: |
404d5d7b | 2205 | break; |
1e9e2622 WL |
2206 | } |
2207 | ||
404d5d7b | 2208 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 2209 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 2210 | |
3f2739bd SC |
2211 | kvm_vcpu_srcu_read_unlock(vcpu); |
2212 | ||
404d5d7b | 2213 | return ret; |
1e9e2622 WL |
2214 | } |
2215 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
2216 | ||
f20935d8 SC |
2217 | /* |
2218 | * Adapt set_msr() to msr_io()'s calling convention | |
2219 | */ | |
2220 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2221 | { | |
6abe9c13 | 2222 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
2223 | } |
2224 | ||
2225 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2226 | { | |
0094f62c SC |
2227 | u64 val; |
2228 | ||
2229 | /* | |
2230 | * Disallow writes to immutable feature MSRs after KVM_RUN. KVM does | |
2231 | * not support modifying the guest vCPU model on the fly, e.g. changing | |
2232 | * the nVMX capabilities while L2 is running is nonsensical. Ignore | |
2233 | * writes of the same value, e.g. to allow userspace to blindly stuff | |
2234 | * all MSRs when emulating RESET. | |
2235 | */ | |
2236 | if (kvm_vcpu_has_run(vcpu) && kvm_is_immutable_feature_msr(index)) { | |
2237 | if (do_get_msr(vcpu, index, &val) || *data != val) | |
2238 | return -EINVAL; | |
2239 | ||
2240 | return 0; | |
2241 | } | |
2242 | ||
6abe9c13 | 2243 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
2244 | } |
2245 | ||
16e8d74d | 2246 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
2247 | struct pvclock_clock { |
2248 | int vclock_mode; | |
2249 | u64 cycle_last; | |
2250 | u64 mask; | |
2251 | u32 mult; | |
2252 | u32 shift; | |
917f9475 PB |
2253 | u64 base_cycles; |
2254 | u64 offset; | |
53fafdbb MT |
2255 | }; |
2256 | ||
16e8d74d MT |
2257 | struct pvclock_gtod_data { |
2258 | seqcount_t seq; | |
2259 | ||
53fafdbb MT |
2260 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
2261 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 2262 | |
917f9475 | 2263 | ktime_t offs_boot; |
55dd00a7 | 2264 | u64 wall_time_sec; |
16e8d74d MT |
2265 | }; |
2266 | ||
2267 | static struct pvclock_gtod_data pvclock_gtod_data; | |
2268 | ||
2269 | static void update_pvclock_gtod(struct timekeeper *tk) | |
2270 | { | |
2271 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
2272 | ||
2273 | write_seqcount_begin(&vdata->seq); | |
2274 | ||
2275 | /* copy pvclock gtod data */ | |
b95a8a27 | 2276 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
2277 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
2278 | vdata->clock.mask = tk->tkr_mono.mask; | |
2279 | vdata->clock.mult = tk->tkr_mono.mult; | |
2280 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
2281 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
2282 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 2283 | |
b95a8a27 | 2284 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
2285 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
2286 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
2287 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
2288 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
2289 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
2290 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 2291 | |
55dd00a7 MT |
2292 | vdata->wall_time_sec = tk->xtime_sec; |
2293 | ||
917f9475 | 2294 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 2295 | |
16e8d74d MT |
2296 | write_seqcount_end(&vdata->seq); |
2297 | } | |
8171cd68 PB |
2298 | |
2299 | static s64 get_kvmclock_base_ns(void) | |
2300 | { | |
2301 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
2302 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
2303 | } | |
2304 | #else | |
2305 | static s64 get_kvmclock_base_ns(void) | |
2306 | { | |
2307 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
2308 | return ktime_get_boottime_ns(); | |
2309 | } | |
16e8d74d MT |
2310 | #endif |
2311 | ||
55749769 | 2312 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) |
18068523 | 2313 | { |
9ed3c444 AK |
2314 | int version; |
2315 | int r; | |
50d0a0f9 | 2316 | struct pvclock_wall_clock wc; |
629b5348 | 2317 | u32 wc_sec_hi; |
8171cd68 | 2318 | u64 wall_nsec; |
18068523 GOC |
2319 | |
2320 | if (!wall_clock) | |
2321 | return; | |
2322 | ||
9ed3c444 AK |
2323 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
2324 | if (r) | |
2325 | return; | |
2326 | ||
2327 | if (version & 1) | |
2328 | ++version; /* first time write, random junk */ | |
2329 | ||
2330 | ++version; | |
18068523 | 2331 | |
1dab1345 NK |
2332 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
2333 | return; | |
18068523 | 2334 | |
50d0a0f9 GH |
2335 | /* |
2336 | * The guest calculates current wall clock time by adding | |
34c238a1 | 2337 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 2338 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 2339 | */ |
8171cd68 | 2340 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 2341 | |
8171cd68 PB |
2342 | wc.nsec = do_div(wall_nsec, 1000000000); |
2343 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 2344 | wc.version = version; |
18068523 GOC |
2345 | |
2346 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
2347 | ||
629b5348 JM |
2348 | if (sec_hi_ofs) { |
2349 | wc_sec_hi = wall_nsec >> 32; | |
2350 | kvm_write_guest(kvm, wall_clock + sec_hi_ofs, | |
2351 | &wc_sec_hi, sizeof(wc_sec_hi)); | |
2352 | } | |
2353 | ||
18068523 GOC |
2354 | version++; |
2355 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
2356 | } |
2357 | ||
5b9bb0eb OU |
2358 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
2359 | bool old_msr, bool host_initiated) | |
2360 | { | |
2361 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
2362 | ||
2363 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 2364 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
2365 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2366 | ||
2367 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
2368 | } | |
2369 | ||
2370 | vcpu->arch.time = system_time; | |
2371 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
2372 | ||
2373 | /* we verify if the enable bit is set... */ | |
8c82a0b3 ML |
2374 | if (system_time & 1) |
2375 | kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL, | |
52491a38 | 2376 | sizeof(struct pvclock_vcpu_time_info)); |
8c82a0b3 ML |
2377 | else |
2378 | kvm_gpc_deactivate(&vcpu->arch.pv_time); | |
5b9bb0eb OU |
2379 | |
2380 | return; | |
2381 | } | |
2382 | ||
50d0a0f9 GH |
2383 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
2384 | { | |
b51012de PB |
2385 | do_shl32_div32(dividend, divisor); |
2386 | return dividend; | |
50d0a0f9 GH |
2387 | } |
2388 | ||
3ae13faa | 2389 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2390 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2391 | { |
5f4e3f88 | 2392 | uint64_t scaled64; |
50d0a0f9 GH |
2393 | int32_t shift = 0; |
2394 | uint64_t tps64; | |
2395 | uint32_t tps32; | |
2396 | ||
3ae13faa PB |
2397 | tps64 = base_hz; |
2398 | scaled64 = scaled_hz; | |
50933623 | 2399 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2400 | tps64 >>= 1; |
2401 | shift--; | |
2402 | } | |
2403 | ||
2404 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2405 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2406 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2407 | scaled64 >>= 1; |
2408 | else | |
2409 | tps32 <<= 1; | |
50d0a0f9 GH |
2410 | shift++; |
2411 | } | |
2412 | ||
5f4e3f88 ZA |
2413 | *pshift = shift; |
2414 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2415 | } |
2416 | ||
d828199e | 2417 | #ifdef CONFIG_X86_64 |
16e8d74d | 2418 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2419 | #endif |
16e8d74d | 2420 | |
c8076604 | 2421 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2422 | static unsigned long max_tsc_khz; |
c8076604 | 2423 | |
cc578287 | 2424 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2425 | { |
cc578287 ZA |
2426 | u64 v = (u64)khz * (1000000 + ppm); |
2427 | do_div(v, 1000000); | |
2428 | return v; | |
1e993611 JR |
2429 | } |
2430 | ||
1ab9287a IS |
2431 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); |
2432 | ||
381d585c HZ |
2433 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2434 | { | |
2435 | u64 ratio; | |
2436 | ||
2437 | /* Guest TSC same frequency as host TSC? */ | |
2438 | if (!scale) { | |
938c8745 | 2439 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); |
381d585c HZ |
2440 | return 0; |
2441 | } | |
2442 | ||
2443 | /* TSC scaling supported? */ | |
938c8745 | 2444 | if (!kvm_caps.has_tsc_control) { |
381d585c HZ |
2445 | if (user_tsc_khz > tsc_khz) { |
2446 | vcpu->arch.tsc_catchup = 1; | |
2447 | vcpu->arch.tsc_always_catchup = 1; | |
2448 | return 0; | |
2449 | } else { | |
3f16a5c3 | 2450 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2451 | return -1; |
2452 | } | |
2453 | } | |
2454 | ||
2455 | /* TSC scaling required - calculate ratio */ | |
938c8745 | 2456 | ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits, |
381d585c HZ |
2457 | user_tsc_khz, tsc_khz); |
2458 | ||
938c8745 | 2459 | if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) { |
3f16a5c3 PB |
2460 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2461 | user_tsc_khz); | |
381d585c HZ |
2462 | return -1; |
2463 | } | |
2464 | ||
1ab9287a | 2465 | kvm_vcpu_write_tsc_multiplier(vcpu, ratio); |
381d585c HZ |
2466 | return 0; |
2467 | } | |
2468 | ||
4941b8cb | 2469 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2470 | { |
cc578287 ZA |
2471 | u32 thresh_lo, thresh_hi; |
2472 | int use_scaling = 0; | |
217fc9cf | 2473 | |
03ba32ca | 2474 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2475 | if (user_tsc_khz == 0) { |
ad721883 | 2476 | /* set tsc_scaling_ratio to a safe value */ |
938c8745 | 2477 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); |
381d585c | 2478 | return -1; |
ad721883 | 2479 | } |
03ba32ca | 2480 | |
c285545f | 2481 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2482 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2483 | &vcpu->arch.virtual_tsc_shift, |
2484 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2485 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2486 | |
2487 | /* | |
2488 | * Compute the variation in TSC rate which is acceptable | |
2489 | * within the range of tolerance and decide if the | |
2490 | * rate being applied is within that bounds of the hardware | |
2491 | * rate. If so, no scaling or compensation need be done. | |
2492 | */ | |
2493 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2494 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb | 2495 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
8d20bd63 SC |
2496 | pr_debug("requested TSC rate %u falls outside tolerance [%u,%u]\n", |
2497 | user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2498 | use_scaling = 1; |
2499 | } | |
4941b8cb | 2500 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2501 | } |
2502 | ||
2503 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2504 | { | |
e26101b1 | 2505 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2506 | vcpu->arch.virtual_tsc_mult, |
2507 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2508 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2509 | return tsc; |
2510 | } | |
2511 | ||
ba1f77c5 | 2512 | #ifdef CONFIG_X86_64 |
b0c39dc6 VK |
2513 | static inline int gtod_is_based_on_tsc(int mode) |
2514 | { | |
b95a8a27 | 2515 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 | 2516 | } |
ba1f77c5 | 2517 | #endif |
b0c39dc6 | 2518 | |
69b0049a | 2519 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
2520 | { |
2521 | #ifdef CONFIG_X86_64 | |
2522 | bool vcpus_matched; | |
b48aa97e MT |
2523 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2524 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2525 | ||
2526 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2527 | atomic_read(&vcpu->kvm->online_vcpus)); | |
2528 | ||
7f187922 MT |
2529 | /* |
2530 | * Once the masterclock is enabled, always perform request in | |
2531 | * order to update it. | |
2532 | * | |
2533 | * In order to enable masterclock, the host clocksource must be TSC | |
2534 | * and the vcpus need to have matched TSCs. When that happens, | |
2535 | * perform request to enable masterclock. | |
2536 | */ | |
2537 | if (ka->use_master_clock || | |
b0c39dc6 | 2538 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
2539 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2540 | ||
2541 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2542 | atomic_read(&vcpu->kvm->online_vcpus), | |
2543 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2544 | #endif | |
2545 | } | |
2546 | ||
35181e86 HZ |
2547 | /* |
2548 | * Multiply tsc by a fixed point number represented by ratio. | |
2549 | * | |
2550 | * The most significant 64-N bits (mult) of ratio represent the | |
2551 | * integral part of the fixed point number; the remaining N bits | |
2552 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2553 | * point number (mult + frac * 2^(-N)). | |
2554 | * | |
938c8745 | 2555 | * N equals to kvm_caps.tsc_scaling_ratio_frac_bits. |
35181e86 HZ |
2556 | */ |
2557 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2558 | { | |
938c8745 | 2559 | return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits); |
35181e86 HZ |
2560 | } |
2561 | ||
62711e5a | 2562 | u64 kvm_scale_tsc(u64 tsc, u64 ratio) |
35181e86 HZ |
2563 | { |
2564 | u64 _tsc = tsc; | |
35181e86 | 2565 | |
938c8745 | 2566 | if (ratio != kvm_caps.default_tsc_scaling_ratio) |
35181e86 HZ |
2567 | _tsc = __scale_tsc(ratio, tsc); |
2568 | ||
2569 | return _tsc; | |
2570 | } | |
35181e86 | 2571 | |
9b399dfd | 2572 | static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
07c1419a HZ |
2573 | { |
2574 | u64 tsc; | |
2575 | ||
62711e5a | 2576 | tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); |
07c1419a HZ |
2577 | |
2578 | return target_tsc - tsc; | |
2579 | } | |
2580 | ||
4ba76538 HZ |
2581 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2582 | { | |
fe3eb504 | 2583 | return vcpu->arch.l1_tsc_offset + |
62711e5a | 2584 | kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio); |
4ba76538 HZ |
2585 | } |
2586 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2587 | ||
83150f29 IS |
2588 | u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) |
2589 | { | |
2590 | u64 nested_offset; | |
2591 | ||
938c8745 | 2592 | if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio) |
83150f29 IS |
2593 | nested_offset = l1_offset; |
2594 | else | |
2595 | nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, | |
938c8745 | 2596 | kvm_caps.tsc_scaling_ratio_frac_bits); |
83150f29 IS |
2597 | |
2598 | nested_offset += l2_offset; | |
2599 | return nested_offset; | |
2600 | } | |
2601 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); | |
2602 | ||
2603 | u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) | |
2604 | { | |
938c8745 | 2605 | if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio) |
83150f29 | 2606 | return mul_u64_u64_shr(l1_multiplier, l2_multiplier, |
938c8745 | 2607 | kvm_caps.tsc_scaling_ratio_frac_bits); |
83150f29 IS |
2608 | |
2609 | return l1_multiplier; | |
2610 | } | |
2611 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); | |
2612 | ||
edcfe540 | 2613 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) |
a545ab6a | 2614 | { |
edcfe540 IS |
2615 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2616 | vcpu->arch.l1_tsc_offset, | |
2617 | l1_offset); | |
2618 | ||
2619 | vcpu->arch.l1_tsc_offset = l1_offset; | |
2620 | ||
2621 | /* | |
2622 | * If we are here because L1 chose not to trap WRMSR to TSC then | |
2623 | * according to the spec this should set L1's TSC (as opposed to | |
2624 | * setting L1's offset for L2). | |
2625 | */ | |
2626 | if (is_guest_mode(vcpu)) | |
2627 | vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( | |
2628 | l1_offset, | |
2629 | static_call(kvm_x86_get_l2_tsc_offset)(vcpu), | |
2630 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2631 | else | |
2632 | vcpu->arch.tsc_offset = l1_offset; | |
2633 | ||
2634 | static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); | |
a545ab6a LC |
2635 | } |
2636 | ||
1ab9287a IS |
2637 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) |
2638 | { | |
2639 | vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; | |
2640 | ||
2641 | /* Userspace is changing the multiplier while L2 is active */ | |
2642 | if (is_guest_mode(vcpu)) | |
2643 | vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( | |
2644 | l1_multiplier, | |
2645 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2646 | else | |
2647 | vcpu->arch.tsc_scaling_ratio = l1_multiplier; | |
2648 | ||
938c8745 | 2649 | if (kvm_caps.has_tsc_control) |
1ab9287a IS |
2650 | static_call(kvm_x86_write_tsc_multiplier)( |
2651 | vcpu, vcpu->arch.tsc_scaling_ratio); | |
2652 | } | |
2653 | ||
b0c39dc6 VK |
2654 | static inline bool kvm_check_tsc_unstable(void) |
2655 | { | |
2656 | #ifdef CONFIG_X86_64 | |
2657 | /* | |
2658 | * TSC is marked unstable when we're running on Hyper-V, | |
2659 | * 'TSC page' clocksource is good. | |
2660 | */ | |
b95a8a27 | 2661 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2662 | return false; |
2663 | #endif | |
2664 | return check_tsc_unstable(); | |
2665 | } | |
2666 | ||
58d4277b OU |
2667 | /* |
2668 | * Infers attempts to synchronize the guest's tsc from host writes. Sets the | |
2669 | * offset for the vcpu and tracks the TSC matching generation that the vcpu | |
2670 | * participates in. | |
2671 | */ | |
2672 | static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, | |
2673 | u64 ns, bool matched) | |
2674 | { | |
2675 | struct kvm *kvm = vcpu->kvm; | |
2676 | ||
2677 | lockdep_assert_held(&kvm->arch.tsc_write_lock); | |
2678 | ||
2679 | /* | |
2680 | * We also track th most recent recorded KHZ, write and time to | |
2681 | * allow the matching interval to be extended at each write. | |
2682 | */ | |
2683 | kvm->arch.last_tsc_nsec = ns; | |
2684 | kvm->arch.last_tsc_write = tsc; | |
2685 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; | |
828ca896 | 2686 | kvm->arch.last_tsc_offset = offset; |
58d4277b OU |
2687 | |
2688 | vcpu->arch.last_guest_tsc = tsc; | |
2689 | ||
2690 | kvm_vcpu_write_tsc_offset(vcpu, offset); | |
2691 | ||
2692 | if (!matched) { | |
2693 | /* | |
2694 | * We split periods of matched TSC writes into generations. | |
2695 | * For each generation, we track the original measured | |
2696 | * nanosecond time, offset, and write, so if TSCs are in | |
2697 | * sync, we can match exact offset, and if not, we can match | |
2698 | * exact software computation in compute_guest_tsc() | |
2699 | * | |
2700 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2701 | */ | |
2702 | kvm->arch.cur_tsc_generation++; | |
2703 | kvm->arch.cur_tsc_nsec = ns; | |
2704 | kvm->arch.cur_tsc_write = tsc; | |
2705 | kvm->arch.cur_tsc_offset = offset; | |
2706 | kvm->arch.nr_vcpus_matched_tsc = 0; | |
2707 | } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { | |
2708 | kvm->arch.nr_vcpus_matched_tsc++; | |
2709 | } | |
2710 | ||
2711 | /* Keep track of which generation this VCPU has synchronized to */ | |
2712 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2713 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2714 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2715 | ||
2716 | kvm_track_tsc_matching(vcpu); | |
2717 | } | |
2718 | ||
0c899c25 | 2719 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) |
99e3e30a ZA |
2720 | { |
2721 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2722 | u64 offset, ns, elapsed; |
99e3e30a | 2723 | unsigned long flags; |
58d4277b | 2724 | bool matched = false; |
c5e8ec8e | 2725 | bool synchronizing = false; |
99e3e30a | 2726 | |
038f8c11 | 2727 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
9b399dfd | 2728 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
8171cd68 | 2729 | ns = get_kvmclock_base_ns(); |
f38e098f | 2730 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2731 | |
03ba32ca | 2732 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2733 | if (data == 0) { |
bd8fab39 DP |
2734 | /* |
2735 | * detection of vcpu initialization -- need to sync | |
2736 | * with other vCPUs. This particularly helps to keep | |
2737 | * kvm_clock stable after CPU hotplug | |
2738 | */ | |
2739 | synchronizing = true; | |
2740 | } else { | |
2741 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2742 | nsec_to_cycles(vcpu, elapsed); | |
2743 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2744 | /* | |
2745 | * Special case: TSC write with a small delta (1 second) | |
2746 | * of virtual cycle time against real time is | |
2747 | * interpreted as an attempt to synchronize the CPU. | |
2748 | */ | |
2749 | synchronizing = data < tsc_exp + tsc_hz && | |
2750 | data + tsc_hz > tsc_exp; | |
2751 | } | |
c5e8ec8e | 2752 | } |
f38e098f ZA |
2753 | |
2754 | /* | |
5d3cb0f6 ZA |
2755 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2756 | * TSC, we add elapsed time in this computation. We could let the | |
2757 | * compensation code attempt to catch up if we fall behind, but | |
2758 | * it's better to try to match offsets from the beginning. | |
2759 | */ | |
c5e8ec8e | 2760 | if (synchronizing && |
5d3cb0f6 | 2761 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2762 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2763 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2764 | } else { |
857e4099 | 2765 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2766 | data += delta; |
9b399dfd | 2767 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
f38e098f | 2768 | } |
b48aa97e | 2769 | matched = true; |
f38e098f | 2770 | } |
e26101b1 | 2771 | |
58d4277b | 2772 | __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); |
e26101b1 | 2773 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
99e3e30a | 2774 | } |
e26101b1 | 2775 | |
58ea6767 HZ |
2776 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2777 | s64 adjustment) | |
2778 | { | |
56ba77a4 | 2779 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2780 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2781 | } |
2782 | ||
2783 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2784 | { | |
938c8745 | 2785 | if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio) |
58ea6767 | 2786 | WARN_ON(adjustment < 0); |
62711e5a | 2787 | adjustment = kvm_scale_tsc((u64) adjustment, |
fe3eb504 | 2788 | vcpu->arch.l1_tsc_scaling_ratio); |
ea26e4ec | 2789 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2790 | } |
2791 | ||
d828199e MT |
2792 | #ifdef CONFIG_X86_64 |
2793 | ||
a5a1d1c2 | 2794 | static u64 read_tsc(void) |
d828199e | 2795 | { |
a5a1d1c2 | 2796 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2797 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2798 | |
2799 | if (likely(ret >= last)) | |
2800 | return ret; | |
2801 | ||
2802 | /* | |
2803 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2804 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2805 | * very likely) and there's a data dependence, so force GCC |
2806 | * to generate a branch instead. I don't barrier() because | |
2807 | * we don't actually need a barrier, and if this function | |
2808 | * ever gets inlined it will generate worse code. | |
2809 | */ | |
2810 | asm volatile (""); | |
2811 | return last; | |
2812 | } | |
2813 | ||
53fafdbb MT |
2814 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2815 | int *mode) | |
d828199e | 2816 | { |
b0c39dc6 | 2817 | u64 tsc_pg_val; |
9397fa2e | 2818 | long v; |
b0c39dc6 | 2819 | |
53fafdbb | 2820 | switch (clock->vclock_mode) { |
b95a8a27 | 2821 | case VDSO_CLOCKMODE_HVCLOCK: |
9397fa2e PZ |
2822 | if (hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2823 | tsc_timestamp, &tsc_pg_val)) { | |
b0c39dc6 | 2824 | /* TSC page valid */ |
b95a8a27 | 2825 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2826 | v = (tsc_pg_val - clock->cycle_last) & |
2827 | clock->mask; | |
b0c39dc6 VK |
2828 | } else { |
2829 | /* TSC page invalid */ | |
b95a8a27 | 2830 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2831 | } |
2832 | break; | |
b95a8a27 TG |
2833 | case VDSO_CLOCKMODE_TSC: |
2834 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2835 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2836 | v = (*tsc_timestamp - clock->cycle_last) & |
2837 | clock->mask; | |
b0c39dc6 VK |
2838 | break; |
2839 | default: | |
b95a8a27 | 2840 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2841 | } |
d828199e | 2842 | |
b95a8a27 | 2843 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2844 | *tsc_timestamp = v = 0; |
d828199e | 2845 | |
53fafdbb | 2846 | return v * clock->mult; |
d828199e MT |
2847 | } |
2848 | ||
53fafdbb | 2849 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2850 | { |
cbcf2dd3 | 2851 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2852 | unsigned long seq; |
d828199e | 2853 | int mode; |
cbcf2dd3 | 2854 | u64 ns; |
d828199e | 2855 | |
d828199e MT |
2856 | do { |
2857 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2858 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2859 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2860 | ns >>= gtod->raw_clock.shift; |
2861 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2862 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2863 | *t = ns; |
d828199e MT |
2864 | |
2865 | return mode; | |
2866 | } | |
2867 | ||
899a31f5 | 2868 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2869 | { |
2870 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2871 | unsigned long seq; | |
2872 | int mode; | |
2873 | u64 ns; | |
2874 | ||
2875 | do { | |
2876 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2877 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2878 | ns = gtod->clock.base_cycles; |
53fafdbb | 2879 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2880 | ns >>= gtod->clock.shift; |
2881 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2882 | ||
2883 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2884 | ts->tv_nsec = ns; | |
2885 | ||
2886 | return mode; | |
2887 | } | |
2888 | ||
b0c39dc6 VK |
2889 | /* returns true if host is using TSC based clocksource */ |
2890 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2891 | { |
d828199e | 2892 | /* checked again under seqlock below */ |
b0c39dc6 | 2893 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2894 | return false; |
2895 | ||
53fafdbb | 2896 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2897 | tsc_timestamp)); |
d828199e | 2898 | } |
55dd00a7 | 2899 | |
b0c39dc6 | 2900 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2901 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2902 | u64 *tsc_timestamp) |
55dd00a7 MT |
2903 | { |
2904 | /* checked again under seqlock below */ | |
b0c39dc6 | 2905 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2906 | return false; |
2907 | ||
b0c39dc6 | 2908 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2909 | } |
d828199e MT |
2910 | #endif |
2911 | ||
2912 | /* | |
2913 | * | |
b48aa97e MT |
2914 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2915 | * across virtual CPUs, the following condition is possible. | |
2916 | * Each numbered line represents an event visible to both | |
d828199e MT |
2917 | * CPUs at the next numbered event. |
2918 | * | |
2919 | * "timespecX" represents host monotonic time. "tscX" represents | |
2920 | * RDTSC value. | |
2921 | * | |
2922 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2923 | * | |
2924 | * 1. read timespec0,tsc0 | |
2925 | * 2. | timespec1 = timespec0 + N | |
2926 | * | tsc1 = tsc0 + M | |
2927 | * 3. transition to guest | transition to guest | |
2928 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2929 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2930 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2931 | * | |
2932 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2933 | * | |
2934 | * - ret0 < ret1 | |
2935 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2936 | * ... | |
2937 | * - 0 < N - M => M < N | |
2938 | * | |
2939 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2940 | * always the case (the difference between two distinct xtime instances | |
2941 | * might be smaller then the difference between corresponding TSC reads, | |
2942 | * when updating guest vcpus pvclock areas). | |
2943 | * | |
2944 | * To avoid that problem, do not allow visibility of distinct | |
2945 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2946 | * copy of host monotonic time values. Update that master copy | |
2947 | * in lockstep. | |
2948 | * | |
b48aa97e | 2949 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2950 | * |
2951 | */ | |
2952 | ||
2953 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2954 | { | |
2955 | #ifdef CONFIG_X86_64 | |
2956 | struct kvm_arch *ka = &kvm->arch; | |
2957 | int vclock_mode; | |
b48aa97e MT |
2958 | bool host_tsc_clocksource, vcpus_matched; |
2959 | ||
869b4421 | 2960 | lockdep_assert_held(&kvm->arch.tsc_write_lock); |
b48aa97e MT |
2961 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == |
2962 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2963 | |
2964 | /* | |
2965 | * If the host uses TSC clock, then passthrough TSC as stable | |
2966 | * to the guest. | |
2967 | */ | |
b48aa97e | 2968 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2969 | &ka->master_kernel_ns, |
2970 | &ka->master_cycle_now); | |
2971 | ||
16a96021 | 2972 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2973 | && !ka->backwards_tsc_observed |
54750f2c | 2974 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2975 | |
d828199e MT |
2976 | if (ka->use_master_clock) |
2977 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2978 | ||
2979 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2980 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2981 | vcpus_matched); | |
d828199e MT |
2982 | #endif |
2983 | } | |
2984 | ||
6b6fcd28 | 2985 | static void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2860c4b1 PB |
2986 | { |
2987 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2988 | } | |
2989 | ||
869b4421 | 2990 | static void __kvm_start_pvclock_update(struct kvm *kvm) |
2e762ff7 | 2991 | { |
869b4421 PB |
2992 | raw_spin_lock_irq(&kvm->arch.tsc_write_lock); |
2993 | write_seqcount_begin(&kvm->arch.pvclock_sc); | |
2994 | } | |
e880c6ea | 2995 | |
869b4421 PB |
2996 | static void kvm_start_pvclock_update(struct kvm *kvm) |
2997 | { | |
2e762ff7 | 2998 | kvm_make_mclock_inprogress_request(kvm); |
c2c647f9 | 2999 | |
2e762ff7 | 3000 | /* no guest entries from this point */ |
869b4421 | 3001 | __kvm_start_pvclock_update(kvm); |
6b6fcd28 | 3002 | } |
2e762ff7 | 3003 | |
6b6fcd28 PB |
3004 | static void kvm_end_pvclock_update(struct kvm *kvm) |
3005 | { | |
3006 | struct kvm_arch *ka = &kvm->arch; | |
3007 | struct kvm_vcpu *vcpu; | |
46808a4c | 3008 | unsigned long i; |
2e762ff7 | 3009 | |
869b4421 PB |
3010 | write_seqcount_end(&ka->pvclock_sc); |
3011 | raw_spin_unlock_irq(&ka->tsc_write_lock); | |
2e762ff7 | 3012 | kvm_for_each_vcpu(i, vcpu, kvm) |
105b21bb | 3013 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
3014 | |
3015 | /* guest entries allowed */ | |
3016 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 3017 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
3018 | } |
3019 | ||
6b6fcd28 PB |
3020 | static void kvm_update_masterclock(struct kvm *kvm) |
3021 | { | |
42dcbe7d | 3022 | kvm_hv_request_tsc_page_update(kvm); |
6b6fcd28 PB |
3023 | kvm_start_pvclock_update(kvm); |
3024 | pvclock_update_vm_gtod_copy(kvm); | |
3025 | kvm_end_pvclock_update(kvm); | |
2e762ff7 MT |
3026 | } |
3027 | ||
3ebcbd22 AR |
3028 | /* |
3029 | * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's | |
3030 | * per-CPU value (which may be zero if a CPU is going offline). Note, tsc_khz | |
3031 | * can change during boot even if the TSC is constant, as it's possible for KVM | |
3032 | * to be loaded before TSC calibration completes. Ideally, KVM would get a | |
3033 | * notification when calibration completes, but practically speaking calibration | |
3034 | * will complete before userspace is alive enough to create VMs. | |
3035 | */ | |
3036 | static unsigned long get_cpu_tsc_khz(void) | |
3037 | { | |
3038 | if (static_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
3039 | return tsc_khz; | |
3040 | else | |
3041 | return __this_cpu_read(cpu_tsc_khz); | |
3042 | } | |
3043 | ||
869b4421 PB |
3044 | /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ |
3045 | static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) | |
108b249c | 3046 | { |
108b249c | 3047 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 3048 | struct pvclock_vcpu_time_info hv_clock; |
8b953440 | 3049 | |
e2c2206a WL |
3050 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
3051 | get_cpu(); | |
3052 | ||
869b4421 | 3053 | data->flags = 0; |
3ebcbd22 AR |
3054 | if (ka->use_master_clock && |
3055 | (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) { | |
c68dc1b5 OU |
3056 | #ifdef CONFIG_X86_64 |
3057 | struct timespec64 ts; | |
3058 | ||
3059 | if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { | |
3060 | data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; | |
3061 | data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; | |
3062 | } else | |
3063 | #endif | |
3064 | data->host_tsc = rdtsc(); | |
3065 | ||
869b4421 PB |
3066 | data->flags |= KVM_CLOCK_TSC_STABLE; |
3067 | hv_clock.tsc_timestamp = ka->master_cycle_now; | |
3068 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
3ebcbd22 | 3069 | kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL, |
e70b57a6 WL |
3070 | &hv_clock.tsc_shift, |
3071 | &hv_clock.tsc_to_system_mul); | |
c68dc1b5 | 3072 | data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); |
55c0cefb OU |
3073 | } else { |
3074 | data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; | |
3075 | } | |
e2c2206a WL |
3076 | |
3077 | put_cpu(); | |
55c0cefb | 3078 | } |
e2c2206a | 3079 | |
869b4421 PB |
3080 | static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) |
3081 | { | |
3082 | struct kvm_arch *ka = &kvm->arch; | |
3083 | unsigned seq; | |
3084 | ||
3085 | do { | |
3086 | seq = read_seqcount_begin(&ka->pvclock_sc); | |
3087 | __get_kvmclock(kvm, data); | |
3088 | } while (read_seqcount_retry(&ka->pvclock_sc, seq)); | |
3089 | } | |
3090 | ||
55c0cefb OU |
3091 | u64 get_kvmclock_ns(struct kvm *kvm) |
3092 | { | |
3093 | struct kvm_clock_data data; | |
3094 | ||
55c0cefb OU |
3095 | get_kvmclock(kvm, &data); |
3096 | return data.clock; | |
108b249c PB |
3097 | } |
3098 | ||
916d3608 DW |
3099 | static void kvm_setup_guest_pvclock(struct kvm_vcpu *v, |
3100 | struct gfn_to_pfn_cache *gpc, | |
3101 | unsigned int offset) | |
0d6dd2ff PB |
3102 | { |
3103 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
916d3608 DW |
3104 | struct pvclock_vcpu_time_info *guest_hv_clock; |
3105 | unsigned long flags; | |
0d6dd2ff | 3106 | |
916d3608 | 3107 | read_lock_irqsave(&gpc->lock, flags); |
58f5ee5f | 3108 | while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) { |
916d3608 DW |
3109 | read_unlock_irqrestore(&gpc->lock, flags); |
3110 | ||
58f5ee5f | 3111 | if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock))) |
916d3608 | 3112 | return; |
0d6dd2ff | 3113 | |
916d3608 DW |
3114 | read_lock_irqsave(&gpc->lock, flags); |
3115 | } | |
3116 | ||
3117 | guest_hv_clock = (void *)(gpc->khva + offset); | |
3118 | ||
3119 | /* | |
3120 | * This VCPU is paused, but it's legal for a guest to read another | |
0d6dd2ff PB |
3121 | * VCPU's kvmclock, so we really have to follow the specification where |
3122 | * it says that version is odd if data is being modified, and even after | |
3123 | * it is consistent. | |
0d6dd2ff | 3124 | */ |
0d6dd2ff | 3125 | |
916d3608 | 3126 | guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1; |
0d6dd2ff PB |
3127 | smp_wmb(); |
3128 | ||
3129 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
916d3608 | 3130 | vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED); |
0d6dd2ff PB |
3131 | |
3132 | if (vcpu->pvclock_set_guest_stopped_request) { | |
3133 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
3134 | vcpu->pvclock_set_guest_stopped_request = false; | |
3135 | } | |
3136 | ||
916d3608 DW |
3137 | memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock)); |
3138 | smp_wmb(); | |
0d6dd2ff | 3139 | |
916d3608 | 3140 | guest_hv_clock->version = ++vcpu->hv_clock.version; |
0d6dd2ff | 3141 | |
916d3608 DW |
3142 | mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT); |
3143 | read_unlock_irqrestore(&gpc->lock, flags); | |
0d6dd2ff | 3144 | |
916d3608 | 3145 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); |
0d6dd2ff PB |
3146 | } |
3147 | ||
34c238a1 | 3148 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 3149 | { |
78db6a50 | 3150 | unsigned long flags, tgt_tsc_khz; |
869b4421 | 3151 | unsigned seq; |
18068523 | 3152 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 3153 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 3154 | s64 kernel_ns; |
d828199e | 3155 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 3156 | u8 pvclock_flags; |
d828199e MT |
3157 | bool use_master_clock; |
3158 | ||
3159 | kernel_ns = 0; | |
3160 | host_tsc = 0; | |
18068523 | 3161 | |
d828199e MT |
3162 | /* |
3163 | * If the host uses TSC clock, then passthrough TSC as stable | |
3164 | * to the guest. | |
3165 | */ | |
869b4421 PB |
3166 | do { |
3167 | seq = read_seqcount_begin(&ka->pvclock_sc); | |
3168 | use_master_clock = ka->use_master_clock; | |
3169 | if (use_master_clock) { | |
3170 | host_tsc = ka->master_cycle_now; | |
3171 | kernel_ns = ka->master_kernel_ns; | |
3172 | } | |
3173 | } while (read_seqcount_retry(&ka->pvclock_sc, seq)); | |
c09664bb MT |
3174 | |
3175 | /* Keep irq disabled to prevent changes to the clock */ | |
3176 | local_irq_save(flags); | |
3ebcbd22 | 3177 | tgt_tsc_khz = get_cpu_tsc_khz(); |
78db6a50 | 3178 | if (unlikely(tgt_tsc_khz == 0)) { |
c09664bb MT |
3179 | local_irq_restore(flags); |
3180 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
3181 | return 1; | |
3182 | } | |
d828199e | 3183 | if (!use_master_clock) { |
4ea1636b | 3184 | host_tsc = rdtsc(); |
8171cd68 | 3185 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
3186 | } |
3187 | ||
4ba76538 | 3188 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 3189 | |
c285545f ZA |
3190 | /* |
3191 | * We may have to catch up the TSC to match elapsed wall clock | |
3192 | * time for two reasons, even if kvmclock is used. | |
3193 | * 1) CPU could have been running below the maximum TSC rate | |
3194 | * 2) Broken TSC compensation resets the base at each VCPU | |
3195 | * entry to avoid unknown leaps of TSC even when running | |
3196 | * again on the same CPU. This may cause apparent elapsed | |
3197 | * time to disappear, and the guest to stand still or run | |
3198 | * very slowly. | |
3199 | */ | |
3200 | if (vcpu->tsc_catchup) { | |
3201 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
3202 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 3203 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
3204 | tsc_timestamp = tsc; |
3205 | } | |
50d0a0f9 GH |
3206 | } |
3207 | ||
18068523 GOC |
3208 | local_irq_restore(flags); |
3209 | ||
0d6dd2ff | 3210 | /* With all the info we got, fill in the values */ |
18068523 | 3211 | |
938c8745 | 3212 | if (kvm_caps.has_tsc_control) |
62711e5a | 3213 | tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz, |
fe3eb504 | 3214 | v->arch.l1_tsc_scaling_ratio); |
78db6a50 PB |
3215 | |
3216 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 3217 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
3218 | &vcpu->hv_clock.tsc_shift, |
3219 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 3220 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
f422f853 | 3221 | kvm_xen_update_tsc_info(v); |
8cfdc000 ZA |
3222 | } |
3223 | ||
1d5f066e | 3224 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 3225 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 3226 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 3227 | |
d828199e | 3228 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 3229 | pvclock_flags = 0; |
d828199e MT |
3230 | if (use_master_clock) |
3231 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
3232 | ||
78c0337a MT |
3233 | vcpu->hv_clock.flags = pvclock_flags; |
3234 | ||
916d3608 DW |
3235 | if (vcpu->pv_time.active) |
3236 | kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0); | |
7caf9571 DW |
3237 | if (vcpu->xen.vcpu_info_cache.active) |
3238 | kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache, | |
3239 | offsetof(struct compat_vcpu_info, time)); | |
69d413cf DW |
3240 | if (vcpu->xen.vcpu_time_info_cache.active) |
3241 | kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0); | |
42dcbe7d | 3242 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); |
8cfdc000 | 3243 | return 0; |
c8076604 GH |
3244 | } |
3245 | ||
0061d53d MT |
3246 | /* |
3247 | * kvmclock updates which are isolated to a given vcpu, such as | |
3248 | * vcpu->cpu migration, should not allow system_timestamp from | |
3249 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
3250 | * correction applies to one vcpu's system_timestamp but not | |
3251 | * the others. | |
3252 | * | |
3253 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
3254 | * We need to rate-limit these requests though, as they can |
3255 | * considerably slow guests that have a large number of vcpus. | |
3256 | * The time for a remote vcpu to update its kvmclock is bound | |
3257 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
3258 | */ |
3259 | ||
7e44e449 AJ |
3260 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
3261 | ||
3262 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d | 3263 | { |
46808a4c | 3264 | unsigned long i; |
7e44e449 AJ |
3265 | struct delayed_work *dwork = to_delayed_work(work); |
3266 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
3267 | kvmclock_update_work); | |
3268 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
3269 | struct kvm_vcpu *vcpu; |
3270 | ||
3271 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 3272 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
3273 | kvm_vcpu_kick(vcpu); |
3274 | } | |
3275 | } | |
3276 | ||
7e44e449 AJ |
3277 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
3278 | { | |
3279 | struct kvm *kvm = v->kvm; | |
3280 | ||
105b21bb | 3281 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
3282 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
3283 | KVMCLOCK_UPDATE_DELAY); | |
3284 | } | |
3285 | ||
332967a3 AJ |
3286 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
3287 | ||
3288 | static void kvmclock_sync_fn(struct work_struct *work) | |
3289 | { | |
3290 | struct delayed_work *dwork = to_delayed_work(work); | |
3291 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
3292 | kvmclock_sync_work); | |
3293 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
3294 | ||
630994b3 MT |
3295 | if (!kvmclock_periodic_sync) |
3296 | return; | |
3297 | ||
332967a3 AJ |
3298 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
3299 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
3300 | KVMCLOCK_SYNC_PERIOD); | |
3301 | } | |
3302 | ||
281b5278 JW |
3303 | /* These helpers are safe iff @msr is known to be an MCx bank MSR. */ |
3304 | static bool is_mci_control_msr(u32 msr) | |
3305 | { | |
3306 | return (msr & 3) == 0; | |
3307 | } | |
3308 | static bool is_mci_status_msr(u32 msr) | |
3309 | { | |
3310 | return (msr & 3) == 1; | |
3311 | } | |
3312 | ||
191c8137 BP |
3313 | /* |
3314 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
3315 | */ | |
3316 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
3317 | { | |
3318 | /* McStatusWrEn enabled? */ | |
23493d0a | 3319 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
3320 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
3321 | ||
3322 | return false; | |
3323 | } | |
3324 | ||
9ffd986c | 3325 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3326 | { |
890ca9ae HY |
3327 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3328 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
3329 | u32 msr = msr_info->index; |
3330 | u64 data = msr_info->data; | |
281b5278 | 3331 | u32 offset, last_msr; |
890ca9ae | 3332 | |
15c4a640 | 3333 | switch (msr) { |
15c4a640 | 3334 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 3335 | vcpu->arch.mcg_status = data; |
15c4a640 | 3336 | break; |
c7ac679c | 3337 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
3338 | if (!(mcg_cap & MCG_CTL_P) && |
3339 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
3340 | return 1; |
3341 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 3342 | return 1; |
890ca9ae HY |
3343 | vcpu->arch.mcg_ctl = data; |
3344 | break; | |
281b5278 JW |
3345 | case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: |
3346 | last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; | |
3347 | if (msr > last_msr) | |
3348 | return 1; | |
191c8137 | 3349 | |
281b5278 JW |
3350 | if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated)) |
3351 | return 1; | |
3352 | /* An attempt to write a 1 to a reserved bit raises #GP */ | |
3353 | if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK)) | |
3354 | return 1; | |
3355 | offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, | |
3356 | last_msr + 1 - MSR_IA32_MC0_CTL2); | |
3357 | vcpu->arch.mci_ctl2_banks[offset] = data; | |
3358 | break; | |
3359 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: | |
3360 | last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; | |
3361 | if (msr > last_msr) | |
3362 | return 1; | |
3363 | ||
3364 | /* | |
3365 | * Only 0 or all 1s can be written to IA32_MCi_CTL, all other | |
3366 | * values are architecturally undefined. But, some Linux | |
3367 | * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB | |
3368 | * issue on AMD K8s, allow bit 10 to be clear when setting all | |
3369 | * other bits in order to avoid an uncaught #GP in the guest. | |
f5223a33 SC |
3370 | * |
3371 | * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable, | |
3372 | * single-bit ECC data errors. | |
281b5278 JW |
3373 | */ |
3374 | if (is_mci_control_msr(msr) && | |
3375 | data != 0 && (data | (1 << 10) | 1) != ~(u64)0) | |
3376 | return 1; | |
191c8137 | 3377 | |
281b5278 JW |
3378 | /* |
3379 | * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR. | |
3380 | * AMD-based CPUs allow non-zero values, but if and only if | |
3381 | * HWCR[McStatusWrEn] is set. | |
3382 | */ | |
3383 | if (!msr_info->host_initiated && is_mci_status_msr(msr) && | |
3384 | data != 0 && !can_set_mci_status(vcpu)) | |
3385 | return 1; | |
3386 | ||
3387 | offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, | |
3388 | last_msr + 1 - MSR_IA32_MC0_CTL); | |
3389 | vcpu->arch.mce_banks[offset] = data; | |
3390 | break; | |
3391 | default: | |
890ca9ae HY |
3392 | return 1; |
3393 | } | |
3394 | return 0; | |
3395 | } | |
3396 | ||
2635b5c4 VK |
3397 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
3398 | { | |
3399 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
3400 | ||
3401 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
3402 | } | |
3403 | ||
344d9588 GN |
3404 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
3405 | { | |
3406 | gpa_t gpa = data & ~0x3f; | |
3407 | ||
2635b5c4 VK |
3408 | /* Bits 4:5 are reserved, Should be zero */ |
3409 | if (data & 0x30) | |
344d9588 GN |
3410 | return 1; |
3411 | ||
66570e96 OU |
3412 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
3413 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
3414 | return 1; | |
3415 | ||
3416 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
3417 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
3418 | return 1; | |
3419 | ||
9d3c447c | 3420 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 3421 | return data ? 1 : 0; |
9d3c447c | 3422 | |
2635b5c4 | 3423 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 3424 | |
2635b5c4 | 3425 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
3426 | kvm_clear_async_pf_completion_queue(vcpu); |
3427 | kvm_async_pf_hash_reset(vcpu); | |
3428 | return 0; | |
3429 | } | |
3430 | ||
4e335d9e | 3431 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 3432 | sizeof(u64))) |
344d9588 GN |
3433 | return 1; |
3434 | ||
6adba527 | 3435 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 3436 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 3437 | |
344d9588 | 3438 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
3439 | |
3440 | return 0; | |
3441 | } | |
3442 | ||
3443 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
3444 | { | |
3445 | /* Bits 8-63 are reserved */ | |
3446 | if (data >> 8) | |
3447 | return 1; | |
3448 | ||
3449 | if (!lapic_in_kernel(vcpu)) | |
3450 | return 1; | |
3451 | ||
3452 | vcpu->arch.apf.msr_int_val = data; | |
3453 | ||
3454 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
3455 | ||
344d9588 GN |
3456 | return 0; |
3457 | } | |
3458 | ||
12f9a48f GC |
3459 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
3460 | { | |
8c82a0b3 | 3461 | kvm_gpc_deactivate(&vcpu->arch.pv_time); |
49dedf0d | 3462 | vcpu->arch.time = 0; |
12f9a48f GC |
3463 | } |
3464 | ||
7780938c | 3465 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
3466 | { |
3467 | ++vcpu->stat.tlb_flush; | |
e27bc044 | 3468 | static_call(kvm_x86_flush_tlb_all)(vcpu); |
e94cea09 SC |
3469 | |
3470 | /* Flushing all ASIDs flushes the current ASID... */ | |
3471 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
f38a7b75 WL |
3472 | } |
3473 | ||
0baedd79 VK |
3474 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
3475 | { | |
3476 | ++vcpu->stat.tlb_flush; | |
b53e84ee LJ |
3477 | |
3478 | if (!tdp_enabled) { | |
61b05a9f | 3479 | /* |
b53e84ee LJ |
3480 | * A TLB flush on behalf of the guest is equivalent to |
3481 | * INVPCID(all), toggling CR4.PGE, etc., which requires | |
61b05a9f LJ |
3482 | * a forced sync of the shadow page tables. Ensure all the |
3483 | * roots are synced and the guest TLB in hardware is clean. | |
b53e84ee | 3484 | */ |
61b05a9f LJ |
3485 | kvm_mmu_sync_roots(vcpu); |
3486 | kvm_mmu_sync_prev_roots(vcpu); | |
b53e84ee LJ |
3487 | } |
3488 | ||
e27bc044 | 3489 | static_call(kvm_x86_flush_tlb_guest)(vcpu); |
adc43caa VK |
3490 | |
3491 | /* | |
3492 | * Flushing all "guest" TLB is always a superset of Hyper-V's fine | |
3493 | * grained flushing. | |
3494 | */ | |
0823570f | 3495 | kvm_hv_vcpu_purge_flush_tlb(vcpu); |
0baedd79 VK |
3496 | } |
3497 | ||
40e5f908 SC |
3498 | |
3499 | static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) | |
3500 | { | |
3501 | ++vcpu->stat.tlb_flush; | |
e27bc044 | 3502 | static_call(kvm_x86_flush_tlb_current)(vcpu); |
40e5f908 SC |
3503 | } |
3504 | ||
3505 | /* | |
3506 | * Service "local" TLB flush requests, which are specific to the current MMU | |
3507 | * context. In addition to the generic event handling in vcpu_enter_guest(), | |
3508 | * TLB flushes that are targeted at an MMU context also need to be serviced | |
3509 | * prior before nested VM-Enter/VM-Exit. | |
3510 | */ | |
3511 | void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu) | |
3512 | { | |
3513 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
3514 | kvm_vcpu_flush_tlb_current(vcpu); | |
3515 | ||
3516 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) | |
3517 | kvm_vcpu_flush_tlb_guest(vcpu); | |
3518 | } | |
3519 | EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests); | |
3520 | ||
c9aaa895 GC |
3521 | static void record_steal_time(struct kvm_vcpu *vcpu) |
3522 | { | |
7e2175eb DW |
3523 | struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; |
3524 | struct kvm_steal_time __user *st; | |
3525 | struct kvm_memslots *slots; | |
901d3765 | 3526 | gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; |
7e2175eb DW |
3527 | u64 steal; |
3528 | u32 version; | |
b0431382 | 3529 | |
30b5c851 DW |
3530 | if (kvm_xen_msr_enabled(vcpu->kvm)) { |
3531 | kvm_xen_runstate_set_running(vcpu); | |
3532 | return; | |
3533 | } | |
3534 | ||
c9aaa895 GC |
3535 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
3536 | return; | |
3537 | ||
7e2175eb | 3538 | if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) |
c9aaa895 GC |
3539 | return; |
3540 | ||
7e2175eb DW |
3541 | slots = kvm_memslots(vcpu->kvm); |
3542 | ||
3543 | if (unlikely(slots->generation != ghc->generation || | |
901d3765 | 3544 | gpa != ghc->gpa || |
7e2175eb | 3545 | kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { |
7e2175eb DW |
3546 | /* We rely on the fact that it fits in a single page. */ |
3547 | BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); | |
3548 | ||
901d3765 | 3549 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) || |
7e2175eb DW |
3550 | kvm_is_error_hva(ghc->hva) || !ghc->memslot) |
3551 | return; | |
3552 | } | |
3553 | ||
3554 | st = (struct kvm_steal_time __user *)ghc->hva; | |
f38a7b75 WL |
3555 | /* |
3556 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
3557 | * expensive IPIs. | |
3558 | */ | |
66570e96 | 3559 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
7e2175eb DW |
3560 | u8 st_preempted = 0; |
3561 | int err = -EFAULT; | |
3562 | ||
3e067fd8 PB |
3563 | if (!user_access_begin(st, sizeof(*st))) |
3564 | return; | |
3565 | ||
7e2175eb DW |
3566 | asm volatile("1: xchgb %0, %2\n" |
3567 | "xor %1, %1\n" | |
3568 | "2:\n" | |
3569 | _ASM_EXTABLE_UA(1b, 2b) | |
964b7aa0 DW |
3570 | : "+q" (st_preempted), |
3571 | "+&r" (err), | |
3572 | "+m" (st->preempted)); | |
7e2175eb DW |
3573 | if (err) |
3574 | goto out; | |
3575 | ||
3576 | user_access_end(); | |
3577 | ||
3578 | vcpu->arch.st.preempted = 0; | |
af3511ff | 3579 | |
66570e96 | 3580 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, |
af3511ff LJ |
3581 | st_preempted & KVM_VCPU_FLUSH_TLB); |
3582 | if (st_preempted & KVM_VCPU_FLUSH_TLB) | |
66570e96 | 3583 | kvm_vcpu_flush_tlb_guest(vcpu); |
7e2175eb DW |
3584 | |
3585 | if (!user_access_begin(st, sizeof(*st))) | |
3586 | goto dirty; | |
1eff0ada | 3587 | } else { |
3e067fd8 PB |
3588 | if (!user_access_begin(st, sizeof(*st))) |
3589 | return; | |
3590 | ||
7e2175eb DW |
3591 | unsafe_put_user(0, &st->preempted, out); |
3592 | vcpu->arch.st.preempted = 0; | |
66570e96 | 3593 | } |
0b9f6c46 | 3594 | |
7e2175eb DW |
3595 | unsafe_get_user(version, &st->version, out); |
3596 | if (version & 1) | |
3597 | version += 1; /* first time write, random junk */ | |
35f3fae1 | 3598 | |
7e2175eb DW |
3599 | version += 1; |
3600 | unsafe_put_user(version, &st->version, out); | |
35f3fae1 WL |
3601 | |
3602 | smp_wmb(); | |
3603 | ||
7e2175eb DW |
3604 | unsafe_get_user(steal, &st->steal, out); |
3605 | steal += current->sched_info.run_delay - | |
c54cdf14 LC |
3606 | vcpu->arch.st.last_steal; |
3607 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
7e2175eb | 3608 | unsafe_put_user(steal, &st->steal, out); |
35f3fae1 | 3609 | |
7e2175eb DW |
3610 | version += 1; |
3611 | unsafe_put_user(version, &st->version, out); | |
35f3fae1 | 3612 | |
7e2175eb DW |
3613 | out: |
3614 | user_access_end(); | |
3615 | dirty: | |
3616 | mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); | |
c9aaa895 GC |
3617 | } |
3618 | ||
2de154f5 SC |
3619 | static bool kvm_is_msr_to_save(u32 msr_index) |
3620 | { | |
3621 | unsigned int i; | |
3622 | ||
3623 | for (i = 0; i < num_msrs_to_save; i++) { | |
3624 | if (msrs_to_save[i] == msr_index) | |
3625 | return true; | |
3626 | } | |
3627 | ||
3628 | return false; | |
3629 | } | |
3630 | ||
8fe8ab46 | 3631 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3632 | { |
8fe8ab46 WA |
3633 | u32 msr = msr_info->index; |
3634 | u64 data = msr_info->data; | |
5753785f | 3635 | |
1232f8e6 | 3636 | if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) |
23200b7a | 3637 | return kvm_xen_write_hypercall_page(vcpu, data); |
1232f8e6 | 3638 | |
15c4a640 | 3639 | switch (msr) { |
2e32b719 | 3640 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3641 | case MSR_IA32_UCODE_WRITE: |
3642 | case MSR_VM_HSAVE_PA: | |
3643 | case MSR_AMD64_PATCH_LOADER: | |
3644 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3645 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3646 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3647 | break; |
3648 | ||
518e7b94 WL |
3649 | case MSR_IA32_UCODE_REV: |
3650 | if (msr_info->host_initiated) | |
3651 | vcpu->arch.microcode_version = data; | |
3652 | break; | |
0cf9135b SC |
3653 | case MSR_IA32_ARCH_CAPABILITIES: |
3654 | if (!msr_info->host_initiated) | |
3655 | return 1; | |
3656 | vcpu->arch.arch_capabilities = data; | |
3657 | break; | |
686e0f03 | 3658 | case MSR_IA32_PERF_CAPABILITIES: |
d574c539 VK |
3659 | if (!msr_info->host_initiated) |
3660 | return 1; | |
686e0f03 | 3661 | if (data & ~kvm_caps.supported_perf_cap) |
d574c539 VK |
3662 | return 1; |
3663 | ||
3a6de51a SC |
3664 | /* |
3665 | * Note, this is not just a performance optimization! KVM | |
3666 | * disallows changing feature MSRs after the vCPU has run; PMU | |
3667 | * refresh will bug the VM if called after the vCPU has run. | |
3668 | */ | |
3669 | if (vcpu->arch.perf_capabilities == data) | |
3670 | break; | |
3671 | ||
d574c539 | 3672 | vcpu->arch.perf_capabilities = data; |
17a024a8 | 3673 | kvm_pmu_refresh(vcpu); |
3a6de51a | 3674 | break; |
903358c7 SC |
3675 | case MSR_IA32_PRED_CMD: |
3676 | if (!msr_info->host_initiated && !guest_has_pred_cmd_msr(vcpu)) | |
3677 | return 1; | |
3678 | ||
3679 | if (!boot_cpu_has(X86_FEATURE_IBPB) || (data & ~PRED_CMD_IBPB)) | |
3680 | return 1; | |
3681 | if (!data) | |
3682 | break; | |
3683 | ||
3684 | wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); | |
3685 | break; | |
da3db168 SC |
3686 | case MSR_IA32_FLUSH_CMD: |
3687 | if (!msr_info->host_initiated && | |
3688 | !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D)) | |
3689 | return 1; | |
3690 | ||
3691 | if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH)) | |
3692 | return 1; | |
3693 | if (!data) | |
3694 | break; | |
3695 | ||
3696 | wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); | |
3697 | break; | |
15c4a640 | 3698 | case MSR_EFER: |
11988499 | 3699 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3700 | case MSR_K7_HWCR: |
3701 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3702 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3703 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
3704 | |
3705 | /* Handle McStatusWrEn */ | |
3706 | if (data == BIT_ULL(18)) { | |
3707 | vcpu->arch.msr_hwcr = data; | |
3708 | } else if (data != 0) { | |
e76ae527 | 3709 | kvm_pr_unimpl_wrmsr(vcpu, msr, data); |
8f1589d9 AP |
3710 | return 1; |
3711 | } | |
15c4a640 | 3712 | break; |
f7c6d140 AP |
3713 | case MSR_FAM10H_MMIO_CONF_BASE: |
3714 | if (data != 0) { | |
e76ae527 | 3715 | kvm_pr_unimpl_wrmsr(vcpu, msr, data); |
f7c6d140 AP |
3716 | return 1; |
3717 | } | |
15c4a640 | 3718 | break; |
34a83dea | 3719 | case MSR_IA32_CR_PAT: |
bc7fe2f0 SC |
3720 | if (!kvm_pat_valid(data)) |
3721 | return 1; | |
3722 | ||
3723 | vcpu->arch.pat = data; | |
3724 | break; | |
34a83dea SC |
3725 | case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000: |
3726 | case MSR_MTRRdefType: | |
ff53604b | 3727 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3728 | case MSR_IA32_APICBASE: |
58cb628d | 3729 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3730 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3731 | return kvm_x2apic_msr_write(vcpu, msr, data); |
09141ec0 | 3732 | case MSR_IA32_TSC_DEADLINE: |
a3e06bbe LJ |
3733 | kvm_set_lapic_tscdeadline_msr(vcpu, data); |
3734 | break; | |
ba904635 | 3735 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3736 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3737 | if (!msr_info->host_initiated) { |
d913b904 | 3738 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3739 | adjust_tsc_offset_guest(vcpu, adj); |
d9130a2d ZD |
3740 | /* Before back to guest, tsc_timestamp must be adjusted |
3741 | * as well, otherwise guest's percpu pvclock time could jump. | |
3742 | */ | |
3743 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
ba904635 WA |
3744 | } |
3745 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3746 | } | |
3747 | break; | |
bef6ecca LX |
3748 | case MSR_IA32_MISC_ENABLE: { |
3749 | u64 old_val = vcpu->arch.ia32_misc_enable_msr; | |
d1055173 | 3750 | |
9fc22296 SC |
3751 | if (!msr_info->host_initiated) { |
3752 | /* RO bits */ | |
3753 | if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK) | |
3754 | return 1; | |
3755 | ||
3756 | /* R bits, i.e. writes are ignored, but don't fault. */ | |
3757 | data = data & ~MSR_IA32_MISC_ENABLE_EMON; | |
3758 | data |= old_val & MSR_IA32_MISC_ENABLE_EMON; | |
3759 | } | |
bef6ecca | 3760 | |
511a8556 | 3761 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
bef6ecca | 3762 | ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { |
511a8556 WL |
3763 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) |
3764 | return 1; | |
3765 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3766 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3767 | } else { |
3768 | vcpu->arch.ia32_misc_enable_msr = data; | |
3769 | } | |
15c4a640 | 3770 | break; |
bef6ecca | 3771 | } |
64d60670 | 3772 | case MSR_IA32_SMBASE: |
4b8e1b32 | 3773 | if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated) |
64d60670 PB |
3774 | return 1; |
3775 | vcpu->arch.smbase = data; | |
3776 | break; | |
73f624f4 PB |
3777 | case MSR_IA32_POWER_CTL: |
3778 | vcpu->arch.msr_ia32_power_ctl = data; | |
3779 | break; | |
dd259935 | 3780 | case MSR_IA32_TSC: |
0c899c25 PB |
3781 | if (msr_info->host_initiated) { |
3782 | kvm_synchronize_tsc(vcpu, data); | |
3783 | } else { | |
9b399dfd | 3784 | u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; |
0c899c25 PB |
3785 | adjust_tsc_offset_guest(vcpu, adj); |
3786 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3787 | } | |
dd259935 | 3788 | break; |
864e2ab2 AL |
3789 | case MSR_IA32_XSS: |
3790 | if (!msr_info->host_initiated && | |
3791 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3792 | return 1; | |
3793 | /* | |
a1bead2a SC |
3794 | * KVM supports exposing PT to the guest, but does not support |
3795 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3796 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3797 | */ |
938c8745 | 3798 | if (data & ~kvm_caps.supported_xss) |
864e2ab2 AL |
3799 | return 1; |
3800 | vcpu->arch.ia32_xss = data; | |
4c282e51 | 3801 | kvm_update_cpuid_runtime(vcpu); |
864e2ab2 | 3802 | break; |
52797bf9 LA |
3803 | case MSR_SMI_COUNT: |
3804 | if (!msr_info->host_initiated) | |
3805 | return 1; | |
3806 | vcpu->arch.smi_count = data; | |
3807 | break; | |
11c6bffa | 3808 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3809 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3810 | return 1; | |
3811 | ||
629b5348 JM |
3812 | vcpu->kvm->arch.wall_clock = data; |
3813 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
66570e96 | 3814 | break; |
18068523 | 3815 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3816 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3817 | return 1; | |
3818 | ||
629b5348 JM |
3819 | vcpu->kvm->arch.wall_clock = data; |
3820 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
18068523 | 3821 | break; |
11c6bffa | 3822 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3823 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3824 | return 1; | |
3825 | ||
5b9bb0eb OU |
3826 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3827 | break; | |
3828 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3829 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3830 | return 1; | |
3831 | ||
3832 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3833 | break; |
344d9588 | 3834 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3835 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3836 | return 1; | |
3837 | ||
344d9588 GN |
3838 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3839 | return 1; | |
3840 | break; | |
2635b5c4 | 3841 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3842 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3843 | return 1; | |
3844 | ||
2635b5c4 VK |
3845 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3846 | return 1; | |
3847 | break; | |
557a961a | 3848 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 3849 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
66570e96 | 3850 | return 1; |
557a961a VK |
3851 | if (data & 0x1) { |
3852 | vcpu->arch.apf.pageready_pending = false; | |
3853 | kvm_check_async_pf_completion(vcpu); | |
3854 | } | |
3855 | break; | |
c9aaa895 | 3856 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3857 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3858 | return 1; | |
c9aaa895 GC |
3859 | |
3860 | if (unlikely(!sched_info_on())) | |
3861 | return 1; | |
3862 | ||
3863 | if (data & KVM_STEAL_RESERVED_MASK) | |
3864 | return 1; | |
3865 | ||
c9aaa895 GC |
3866 | vcpu->arch.st.msr_val = data; |
3867 | ||
3868 | if (!(data & KVM_MSR_ENABLED)) | |
3869 | break; | |
3870 | ||
c9aaa895 GC |
3871 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3872 | ||
3873 | break; | |
ae7a2a3f | 3874 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
3875 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3876 | return 1; | |
3877 | ||
77c3323f | 3878 | if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3879 | return 1; |
3880 | break; | |
c9aaa895 | 3881 | |
2d5ba19b | 3882 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
3883 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3884 | return 1; | |
3885 | ||
2d5ba19b MT |
3886 | /* only enable bit supported */ |
3887 | if (data & (-1ULL << 1)) | |
3888 | return 1; | |
3889 | ||
3890 | vcpu->arch.msr_kvm_poll_control = data; | |
3891 | break; | |
3892 | ||
890ca9ae HY |
3893 | case MSR_IA32_MCG_CTL: |
3894 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3895 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
281b5278 | 3896 | case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3897 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3898 | |
6912ac32 WH |
3899 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3900 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
6912ac32 WH |
3901 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3902 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3903 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3904 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f | 3905 | |
e76ae527 SC |
3906 | if (data) |
3907 | kvm_pr_unimpl_wrmsr(vcpu, msr, data); | |
5753785f | 3908 | break; |
84e0cefa JS |
3909 | case MSR_K7_CLK_CTL: |
3910 | /* | |
3911 | * Ignore all writes to this no longer documented MSR. | |
3912 | * Writes are only relevant for old K7 processors, | |
3913 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3914 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3915 | * affected processor models on the command line, hence |
3916 | * the need to ignore the workaround. | |
3917 | */ | |
3918 | break; | |
55cd8e5a | 3919 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3920 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3921 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3922 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3923 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3924 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3925 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3926 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3927 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
2be1bd3a | 3928 | case HV_X64_MSR_TSC_INVARIANT_CONTROL: |
e7d9513b AS |
3929 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3930 | msr_info->host_initiated); | |
91c9c3ed | 3931 | case MSR_IA32_BBL_CR_CTL3: |
3932 | /* Drop writes to this legacy MSR -- see rdmsr | |
3933 | * counterpart for further detail. | |
3934 | */ | |
e76ae527 | 3935 | kvm_pr_unimpl_wrmsr(vcpu, msr, data); |
91c9c3ed | 3936 | break; |
2b036c6b | 3937 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3938 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3939 | return 1; |
3940 | vcpu->arch.osvw.length = data; | |
3941 | break; | |
3942 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3943 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3944 | return 1; |
3945 | vcpu->arch.osvw.status = data; | |
3946 | break; | |
db2336a8 KH |
3947 | case MSR_PLATFORM_INFO: |
3948 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3949 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3950 | cpuid_fault_enabled(vcpu))) | |
3951 | return 1; | |
3952 | vcpu->arch.msr_platform_info = data; | |
3953 | break; | |
3954 | case MSR_MISC_FEATURES_ENABLES: | |
3955 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3956 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3957 | !supports_cpuid_fault(vcpu))) | |
3958 | return 1; | |
3959 | vcpu->arch.msr_misc_features_enables = data; | |
3960 | break; | |
820a6ee9 JL |
3961 | #ifdef CONFIG_X86_64 |
3962 | case MSR_IA32_XFD: | |
3963 | if (!msr_info->host_initiated && | |
3964 | !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) | |
3965 | return 1; | |
3966 | ||
988896bb | 3967 | if (data & ~kvm_guest_supported_xfd(vcpu)) |
820a6ee9 JL |
3968 | return 1; |
3969 | ||
3970 | fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data); | |
3971 | break; | |
548e8365 JL |
3972 | case MSR_IA32_XFD_ERR: |
3973 | if (!msr_info->host_initiated && | |
3974 | !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) | |
3975 | return 1; | |
3976 | ||
988896bb | 3977 | if (data & ~kvm_guest_supported_xfd(vcpu)) |
548e8365 JL |
3978 | return 1; |
3979 | ||
3980 | vcpu->arch.guest_fpu.xfd_err = data; | |
3981 | break; | |
820a6ee9 | 3982 | #endif |
2de154f5 | 3983 | default: |
157fc497 SC |
3984 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
3985 | return kvm_pmu_set_msr(vcpu, msr_info); | |
2de154f5 | 3986 | |
157fc497 SC |
3987 | /* |
3988 | * Userspace is allowed to write '0' to MSRs that KVM reports | |
3989 | * as to-be-saved, even if an MSRs isn't fully supported. | |
3990 | */ | |
2de154f5 SC |
3991 | if (msr_info->host_initiated && !data && |
3992 | kvm_is_msr_to_save(msr)) | |
3993 | break; | |
3994 | ||
6abe9c13 | 3995 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3996 | } |
3997 | return 0; | |
3998 | } | |
3999 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
4000 | ||
44883f01 | 4001 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
4002 | { |
4003 | u64 data; | |
890ca9ae HY |
4004 | u64 mcg_cap = vcpu->arch.mcg_cap; |
4005 | unsigned bank_num = mcg_cap & 0xff; | |
281b5278 | 4006 | u32 offset, last_msr; |
15c4a640 CO |
4007 | |
4008 | switch (msr) { | |
15c4a640 CO |
4009 | case MSR_IA32_P5_MC_ADDR: |
4010 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
4011 | data = 0; |
4012 | break; | |
15c4a640 | 4013 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
4014 | data = vcpu->arch.mcg_cap; |
4015 | break; | |
c7ac679c | 4016 | case MSR_IA32_MCG_CTL: |
44883f01 | 4017 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
4018 | return 1; |
4019 | data = vcpu->arch.mcg_ctl; | |
4020 | break; | |
4021 | case MSR_IA32_MCG_STATUS: | |
4022 | data = vcpu->arch.mcg_status; | |
4023 | break; | |
281b5278 JW |
4024 | case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: |
4025 | last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; | |
4026 | if (msr > last_msr) | |
4027 | return 1; | |
6ec4c5ee | 4028 | |
281b5278 JW |
4029 | if (!(mcg_cap & MCG_CMCI_P) && !host) |
4030 | return 1; | |
4031 | offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, | |
4032 | last_msr + 1 - MSR_IA32_MC0_CTL2); | |
4033 | data = vcpu->arch.mci_ctl2_banks[offset]; | |
4034 | break; | |
4035 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: | |
4036 | last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; | |
4037 | if (msr > last_msr) | |
4038 | return 1; | |
4039 | ||
4040 | offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, | |
4041 | last_msr + 1 - MSR_IA32_MC0_CTL); | |
4042 | data = vcpu->arch.mce_banks[offset]; | |
4043 | break; | |
4044 | default: | |
890ca9ae HY |
4045 | return 1; |
4046 | } | |
4047 | *pdata = data; | |
4048 | return 0; | |
4049 | } | |
4050 | ||
609e36d3 | 4051 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 4052 | { |
609e36d3 | 4053 | switch (msr_info->index) { |
890ca9ae | 4054 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 4055 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
4056 | case MSR_IA32_LASTBRANCHFROMIP: |
4057 | case MSR_IA32_LASTBRANCHTOIP: | |
4058 | case MSR_IA32_LASTINTFROMIP: | |
4059 | case MSR_IA32_LASTINTTOIP: | |
059e5c32 | 4060 | case MSR_AMD64_SYSCFG: |
3afb1121 PB |
4061 | case MSR_K8_TSEG_ADDR: |
4062 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 4063 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 4064 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 4065 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 4066 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 4067 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 4068 | case MSR_IA32_PERF_CTL: |
405a353a | 4069 | case MSR_AMD64_DC_CFG: |
0e1b869f | 4070 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
4071 | /* |
4072 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
4073 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
4074 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
4075 | * so for existing CPU-specific MSRs. | |
4076 | */ | |
4077 | case MSR_RAPL_POWER_UNIT: | |
4078 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
4079 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
4080 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
4081 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 4082 | msr_info->data = 0; |
15c4a640 | 4083 | break; |
6912ac32 WH |
4084 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
4085 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
4086 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
4087 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 4088 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 4089 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 4090 | msr_info->data = 0; |
5753785f | 4091 | break; |
742bc670 | 4092 | case MSR_IA32_UCODE_REV: |
518e7b94 | 4093 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 4094 | break; |
0cf9135b SC |
4095 | case MSR_IA32_ARCH_CAPABILITIES: |
4096 | if (!msr_info->host_initiated && | |
4097 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
4098 | return 1; | |
4099 | msr_info->data = vcpu->arch.arch_capabilities; | |
4100 | break; | |
d574c539 VK |
4101 | case MSR_IA32_PERF_CAPABILITIES: |
4102 | if (!msr_info->host_initiated && | |
4103 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
4104 | return 1; | |
4105 | msr_info->data = vcpu->arch.perf_capabilities; | |
4106 | break; | |
73f624f4 PB |
4107 | case MSR_IA32_POWER_CTL: |
4108 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
4109 | break; | |
cc5b54dd ML |
4110 | case MSR_IA32_TSC: { |
4111 | /* | |
4112 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
4113 | * even when not intercepted. AMD manual doesn't explicitly | |
4114 | * state this but appears to behave the same. | |
4115 | * | |
ee6fa053 | 4116 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 4117 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 4118 | * behavior for migration. |
cc5b54dd | 4119 | */ |
fe3eb504 | 4120 | u64 offset, ratio; |
cc5b54dd | 4121 | |
fe3eb504 IS |
4122 | if (msr_info->host_initiated) { |
4123 | offset = vcpu->arch.l1_tsc_offset; | |
4124 | ratio = vcpu->arch.l1_tsc_scaling_ratio; | |
4125 | } else { | |
4126 | offset = vcpu->arch.tsc_offset; | |
4127 | ratio = vcpu->arch.tsc_scaling_ratio; | |
4128 | } | |
4129 | ||
62711e5a | 4130 | msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset; |
dd259935 | 4131 | break; |
cc5b54dd | 4132 | } |
34a83dea | 4133 | case MSR_IA32_CR_PAT: |
bc7fe2f0 SC |
4134 | msr_info->data = vcpu->arch.pat; |
4135 | break; | |
9ba075a6 | 4136 | case MSR_MTRRcap: |
34a83dea SC |
4137 | case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000: |
4138 | case MSR_MTRRdefType: | |
ff53604b | 4139 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 4140 | case 0xcd: /* fsb frequency */ |
609e36d3 | 4141 | msr_info->data = 3; |
15c4a640 | 4142 | break; |
7b914098 JS |
4143 | /* |
4144 | * MSR_EBC_FREQUENCY_ID | |
4145 | * Conservative value valid for even the basic CPU models. | |
4146 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
4147 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
4148 | * and 266MHz for model 3, or 4. Set Core Clock | |
4149 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
4150 | * 31:24) even though these are only valid for CPU | |
4151 | * models > 2, however guests may end up dividing or | |
4152 | * multiplying by zero otherwise. | |
4153 | */ | |
4154 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 4155 | msr_info->data = 1 << 24; |
7b914098 | 4156 | break; |
15c4a640 | 4157 | case MSR_IA32_APICBASE: |
609e36d3 | 4158 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 4159 | break; |
bf10bd0b | 4160 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 4161 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
09141ec0 | 4162 | case MSR_IA32_TSC_DEADLINE: |
609e36d3 | 4163 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 4164 | break; |
ba904635 | 4165 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 4166 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 4167 | break; |
15c4a640 | 4168 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 4169 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 4170 | break; |
64d60670 | 4171 | case MSR_IA32_SMBASE: |
4b8e1b32 | 4172 | if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated) |
64d60670 PB |
4173 | return 1; |
4174 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 4175 | break; |
52797bf9 LA |
4176 | case MSR_SMI_COUNT: |
4177 | msr_info->data = vcpu->arch.smi_count; | |
4178 | break; | |
847f0ad8 AG |
4179 | case MSR_IA32_PERF_STATUS: |
4180 | /* TSC increment by tick */ | |
609e36d3 | 4181 | msr_info->data = 1000ULL; |
847f0ad8 | 4182 | /* CPU multiplier */ |
b0996ae4 | 4183 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 4184 | break; |
15c4a640 | 4185 | case MSR_EFER: |
609e36d3 | 4186 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 4187 | break; |
18068523 | 4188 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
4189 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
4190 | return 1; | |
4191 | ||
4192 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
4193 | break; | |
11c6bffa | 4194 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
4195 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
4196 | return 1; | |
4197 | ||
609e36d3 | 4198 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
4199 | break; |
4200 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
4201 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
4202 | return 1; | |
4203 | ||
4204 | msr_info->data = vcpu->arch.time; | |
4205 | break; | |
11c6bffa | 4206 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
4207 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
4208 | return 1; | |
4209 | ||
609e36d3 | 4210 | msr_info->data = vcpu->arch.time; |
18068523 | 4211 | break; |
344d9588 | 4212 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
4213 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
4214 | return 1; | |
4215 | ||
2635b5c4 VK |
4216 | msr_info->data = vcpu->arch.apf.msr_en_val; |
4217 | break; | |
4218 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
4219 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
4220 | return 1; | |
4221 | ||
2635b5c4 | 4222 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 4223 | break; |
557a961a | 4224 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 4225 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
1930e5dd OU |
4226 | return 1; |
4227 | ||
557a961a VK |
4228 | msr_info->data = 0; |
4229 | break; | |
c9aaa895 | 4230 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
4231 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
4232 | return 1; | |
4233 | ||
609e36d3 | 4234 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 4235 | break; |
1d92128f | 4236 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
4237 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
4238 | return 1; | |
4239 | ||
609e36d3 | 4240 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 4241 | break; |
2d5ba19b | 4242 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
4243 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
4244 | return 1; | |
4245 | ||
2d5ba19b MT |
4246 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
4247 | break; | |
890ca9ae HY |
4248 | case MSR_IA32_P5_MC_ADDR: |
4249 | case MSR_IA32_P5_MC_TYPE: | |
4250 | case MSR_IA32_MCG_CAP: | |
4251 | case MSR_IA32_MCG_CTL: | |
4252 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 4253 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
281b5278 | 4254 | case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
4255 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
4256 | msr_info->host_initiated); | |
864e2ab2 AL |
4257 | case MSR_IA32_XSS: |
4258 | if (!msr_info->host_initiated && | |
4259 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
4260 | return 1; | |
4261 | msr_info->data = vcpu->arch.ia32_xss; | |
4262 | break; | |
84e0cefa JS |
4263 | case MSR_K7_CLK_CTL: |
4264 | /* | |
4265 | * Provide expected ramp-up count for K7. All other | |
4266 | * are set to zero, indicating minimum divisors for | |
4267 | * every field. | |
4268 | * | |
4269 | * This prevents guest kernels on AMD host with CPU | |
4270 | * type 6, model 8 and higher from exploding due to | |
4271 | * the rdmsr failing. | |
4272 | */ | |
609e36d3 | 4273 | msr_info->data = 0x20000000; |
84e0cefa | 4274 | break; |
55cd8e5a | 4275 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
4276 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
4277 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
4278 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
4279 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 4280 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
4281 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
4282 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
4283 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
2be1bd3a | 4284 | case HV_X64_MSR_TSC_INVARIANT_CONTROL: |
e83d5887 | 4285 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
4286 | msr_info->index, &msr_info->data, |
4287 | msr_info->host_initiated); | |
91c9c3ed | 4288 | case MSR_IA32_BBL_CR_CTL3: |
4289 | /* This legacy MSR exists but isn't fully documented in current | |
4290 | * silicon. It is however accessed by winxp in very narrow | |
4291 | * scenarios where it sets bit #19, itself documented as | |
4292 | * a "reserved" bit. Best effort attempt to source coherent | |
4293 | * read data here should the balance of the register be | |
4294 | * interpreted by the guest: | |
4295 | * | |
4296 | * L2 cache control register 3: 64GB range, 256KB size, | |
4297 | * enabled, latency 0x1, configured | |
4298 | */ | |
609e36d3 | 4299 | msr_info->data = 0xbe702111; |
91c9c3ed | 4300 | break; |
2b036c6b | 4301 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 4302 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 4303 | return 1; |
609e36d3 | 4304 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
4305 | break; |
4306 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 4307 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 4308 | return 1; |
609e36d3 | 4309 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 4310 | break; |
db2336a8 | 4311 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
4312 | if (!msr_info->host_initiated && |
4313 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
4314 | return 1; | |
db2336a8 KH |
4315 | msr_info->data = vcpu->arch.msr_platform_info; |
4316 | break; | |
4317 | case MSR_MISC_FEATURES_ENABLES: | |
4318 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
4319 | break; | |
191c8137 BP |
4320 | case MSR_K7_HWCR: |
4321 | msr_info->data = vcpu->arch.msr_hwcr; | |
4322 | break; | |
820a6ee9 JL |
4323 | #ifdef CONFIG_X86_64 |
4324 | case MSR_IA32_XFD: | |
4325 | if (!msr_info->host_initiated && | |
4326 | !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) | |
4327 | return 1; | |
4328 | ||
4329 | msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd; | |
4330 | break; | |
548e8365 JL |
4331 | case MSR_IA32_XFD_ERR: |
4332 | if (!msr_info->host_initiated && | |
4333 | !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) | |
4334 | return 1; | |
4335 | ||
4336 | msr_info->data = vcpu->arch.guest_fpu.xfd_err; | |
4337 | break; | |
820a6ee9 | 4338 | #endif |
15c4a640 | 4339 | default: |
c6702c9d | 4340 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 4341 | return kvm_pmu_get_msr(vcpu, msr_info); |
2de154f5 SC |
4342 | |
4343 | /* | |
4344 | * Userspace is allowed to read MSRs that KVM reports as | |
4345 | * to-be-saved, even if an MSR isn't fully supported. | |
4346 | */ | |
4347 | if (msr_info->host_initiated && | |
4348 | kvm_is_msr_to_save(msr_info->index)) { | |
4349 | msr_info->data = 0; | |
4350 | break; | |
4351 | } | |
4352 | ||
6abe9c13 | 4353 | return KVM_MSR_RET_INVALID; |
15c4a640 | 4354 | } |
15c4a640 CO |
4355 | return 0; |
4356 | } | |
4357 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
4358 | ||
313a3dc7 CO |
4359 | /* |
4360 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
4361 | * | |
4362 | * @return number of msrs set successfully. | |
4363 | */ | |
4364 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
4365 | struct kvm_msr_entry *entries, | |
4366 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
4367 | unsigned index, u64 *data)) | |
4368 | { | |
801e459a | 4369 | int i; |
313a3dc7 | 4370 | |
313a3dc7 CO |
4371 | for (i = 0; i < msrs->nmsrs; ++i) |
4372 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
4373 | break; | |
4374 | ||
313a3dc7 CO |
4375 | return i; |
4376 | } | |
4377 | ||
4378 | /* | |
4379 | * Read or write a bunch of msrs. Parameters are user addresses. | |
4380 | * | |
4381 | * @return number of msrs set successfully. | |
4382 | */ | |
4383 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
4384 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
4385 | unsigned index, u64 *data), | |
4386 | int writeback) | |
4387 | { | |
4388 | struct kvm_msrs msrs; | |
4389 | struct kvm_msr_entry *entries; | |
313a3dc7 | 4390 | unsigned size; |
e73ba25f | 4391 | int r; |
313a3dc7 CO |
4392 | |
4393 | r = -EFAULT; | |
0e96f31e | 4394 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
4395 | goto out; |
4396 | ||
4397 | r = -E2BIG; | |
4398 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
4399 | goto out; | |
4400 | ||
313a3dc7 | 4401 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
4402 | entries = memdup_user(user_msrs->entries, size); |
4403 | if (IS_ERR(entries)) { | |
4404 | r = PTR_ERR(entries); | |
313a3dc7 | 4405 | goto out; |
ff5c2c03 | 4406 | } |
313a3dc7 | 4407 | |
e73ba25f | 4408 | r = __msr_io(vcpu, &msrs, entries, do_msr); |
313a3dc7 | 4409 | |
313a3dc7 | 4410 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) |
e73ba25f | 4411 | r = -EFAULT; |
313a3dc7 | 4412 | |
7a73c028 | 4413 | kfree(entries); |
313a3dc7 CO |
4414 | out: |
4415 | return r; | |
4416 | } | |
4417 | ||
4d5422ce WL |
4418 | static inline bool kvm_can_mwait_in_guest(void) |
4419 | { | |
4420 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
4421 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
4422 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
4423 | } |
4424 | ||
c21d54f0 VK |
4425 | static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, |
4426 | struct kvm_cpuid2 __user *cpuid_arg) | |
4427 | { | |
4428 | struct kvm_cpuid2 cpuid; | |
4429 | int r; | |
4430 | ||
4431 | r = -EFAULT; | |
4432 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
4433 | return r; | |
4434 | ||
4435 | r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
4436 | if (r) | |
4437 | return r; | |
4438 | ||
4439 | r = -EFAULT; | |
4440 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
4441 | return r; | |
4442 | ||
4443 | return 0; | |
4444 | } | |
4445 | ||
784aa3d7 | 4446 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 4447 | { |
4d5422ce | 4448 | int r = 0; |
018d00d2 ZX |
4449 | |
4450 | switch (ext) { | |
4451 | case KVM_CAP_IRQCHIP: | |
4452 | case KVM_CAP_HLT: | |
4453 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 4454 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 4455 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 4456 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 4457 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 4458 | case KVM_CAP_PIT: |
a28e4f5a | 4459 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 4460 | case KVM_CAP_MP_STATE: |
ed848624 | 4461 | case KVM_CAP_SYNC_MMU: |
a355c85c | 4462 | case KVM_CAP_USER_NMI: |
52d939a0 | 4463 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 4464 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 4465 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 4466 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 4467 | case KVM_CAP_PIT2: |
e9f42757 | 4468 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 4469 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
3cfc3092 | 4470 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 4471 | case KVM_CAP_HYPERV: |
10388a07 | 4472 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 4473 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 4474 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 4475 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 4476 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 4477 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 4478 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 4479 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 4480 | case KVM_CAP_HYPERV_CPUID: |
644f7067 | 4481 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
c21d54f0 | 4482 | case KVM_CAP_SYS_HYPERV_CPUID: |
ab9f4ecb | 4483 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 4484 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 4485 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 4486 | case KVM_CAP_XSAVE: |
344d9588 | 4487 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 4488 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 4489 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 4490 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 4491 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 4492 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 4493 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 4494 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 4495 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 4496 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 4497 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 4498 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 4499 | case KVM_CAP_PMU_EVENT_FILTER: |
14329b82 | 4500 | case KVM_CAP_PMU_EVENT_MASKED_EVENTS: |
801e459a | 4501 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 4502 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 4503 | case KVM_CAP_EXCEPTION_PAYLOAD: |
ed235117 | 4504 | case KVM_CAP_X86_TRIPLE_FAULT_EVENT: |
b9b2782c | 4505 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 4506 | case KVM_CAP_LAST_CPU: |
1ae09954 | 4507 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 4508 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 4509 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
fe7e9488 SC |
4510 | #ifdef CONFIG_X86_SGX_KVM |
4511 | case KVM_CAP_SGX_ATTRIBUTE: | |
4512 | #endif | |
54526d1f | 4513 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
30d7c5d6 | 4514 | case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: |
6dba9403 | 4515 | case KVM_CAP_SREGS2: |
19238e75 | 4516 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
828ca896 | 4517 | case KVM_CAP_VCPU_ATTRIBUTES: |
dd6e6312 | 4518 | case KVM_CAP_SYS_ATTRIBUTES: |
8a289785 | 4519 | case KVM_CAP_VAPIC: |
127770ac | 4520 | case KVM_CAP_ENABLE_CAP: |
084cc29f | 4521 | case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: |
52882b9c | 4522 | case KVM_CAP_IRQFD_RESAMPLE: |
018d00d2 ZX |
4523 | r = 1; |
4524 | break; | |
0dbb1123 AK |
4525 | case KVM_CAP_EXIT_HYPERCALL: |
4526 | r = KVM_EXIT_HYPERCALL_VALID_MASK; | |
4527 | break; | |
7e582ccb ML |
4528 | case KVM_CAP_SET_GUEST_DEBUG2: |
4529 | return KVM_GUESTDBG_VALID_MASK; | |
b59b153d | 4530 | #ifdef CONFIG_KVM_XEN |
23200b7a JM |
4531 | case KVM_CAP_XEN_HVM: |
4532 | r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | | |
8d4e7e80 | 4533 | KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | |
14243b38 | 4534 | KVM_XEN_HVM_CONFIG_SHARED_INFO | |
661a20fa DW |
4535 | KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL | |
4536 | KVM_XEN_HVM_CONFIG_EVTCHN_SEND; | |
30b5c851 | 4537 | if (sched_info_on()) |
d8ba8ba4 DW |
4538 | r |= KVM_XEN_HVM_CONFIG_RUNSTATE | |
4539 | KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG; | |
23200b7a | 4540 | break; |
b59b153d | 4541 | #endif |
01643c51 KH |
4542 | case KVM_CAP_SYNC_REGS: |
4543 | r = KVM_SYNC_X86_VALID_FIELDS; | |
4544 | break; | |
e3fd9a93 | 4545 | case KVM_CAP_ADJUST_CLOCK: |
c68dc1b5 | 4546 | r = KVM_CLOCK_VALID_FLAGS; |
e3fd9a93 | 4547 | break; |
4d5422ce | 4548 | case KVM_CAP_X86_DISABLE_EXITS: |
6f0f2d5e TL |
4549 | r = KVM_X86_DISABLE_EXITS_PAUSE; |
4550 | ||
4551 | if (!mitigate_smt_rsb) { | |
4552 | r |= KVM_X86_DISABLE_EXITS_HLT | | |
4553 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4554 | ||
4555 | if (kvm_can_mwait_in_guest()) | |
4556 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
4557 | } | |
668fffa3 | 4558 | break; |
6d396b55 | 4559 | case KVM_CAP_X86_SMM: |
4b8e1b32 PB |
4560 | if (!IS_ENABLED(CONFIG_KVM_SMM)) |
4561 | break; | |
4562 | ||
6d396b55 PB |
4563 | /* SMBASE is usually relocated above 1M on modern chipsets, |
4564 | * and SMM handlers might indeed rely on 4G segment limits, | |
4565 | * so do not report SMM to be available if real mode is | |
4566 | * emulated via vm86 mode. Still, do not go to great lengths | |
4567 | * to avoid userspace's usage of the feature, because it is a | |
4568 | * fringe case that is not enabled except via specific settings | |
4569 | * of the module parameters. | |
4570 | */ | |
b3646477 | 4571 | r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); |
6d396b55 | 4572 | break; |
f725230a | 4573 | case KVM_CAP_NR_VCPUS: |
2845e735 | 4574 | r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); |
8c3ba334 SL |
4575 | break; |
4576 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
4577 | r = KVM_MAX_VCPUS; |
4578 | break; | |
a86cb413 | 4579 | case KVM_CAP_MAX_VCPU_ID: |
a1c42dde | 4580 | r = KVM_MAX_VCPU_IDS; |
a86cb413 | 4581 | break; |
a68a6a72 MT |
4582 | case KVM_CAP_PV_MMU: /* obsolete */ |
4583 | r = 0; | |
2f333bcb | 4584 | break; |
890ca9ae HY |
4585 | case KVM_CAP_MCE: |
4586 | r = KVM_MAX_MCE_BANKS; | |
4587 | break; | |
2d5b5a66 | 4588 | case KVM_CAP_XCRS: |
d366bf7e | 4589 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 4590 | break; |
92a1f12d | 4591 | case KVM_CAP_TSC_CONTROL: |
ffbb61d0 | 4592 | case KVM_CAP_VM_TSC_CONTROL: |
938c8745 | 4593 | r = kvm_caps.has_tsc_control; |
92a1f12d | 4594 | break; |
37131313 RK |
4595 | case KVM_CAP_X2APIC_API: |
4596 | r = KVM_X2APIC_API_VALID_FLAGS; | |
4597 | break; | |
8fcc4b59 | 4598 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
4599 | r = kvm_x86_ops.nested_ops->get_state ? |
4600 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 4601 | break; |
344c6c80 | 4602 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
b83237ad | 4603 | r = kvm_x86_ops.enable_l2_tlb_flush != NULL; |
5a0165f6 VK |
4604 | break; |
4605 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 4606 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 4607 | break; |
3edd6839 MG |
4608 | case KVM_CAP_SMALLER_MAXPHYADDR: |
4609 | r = (int) allow_smaller_maxphyaddr; | |
4610 | break; | |
004a0124 AJ |
4611 | case KVM_CAP_STEAL_TIME: |
4612 | r = sched_info_on(); | |
4613 | break; | |
fe6b6bc8 | 4614 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
938c8745 | 4615 | if (kvm_caps.has_bus_lock_exit) |
fe6b6bc8 CQ |
4616 | r = KVM_BUS_LOCK_DETECTION_OFF | |
4617 | KVM_BUS_LOCK_DETECTION_EXIT; | |
4618 | else | |
4619 | r = 0; | |
4620 | break; | |
be50b206 | 4621 | case KVM_CAP_XSAVE2: { |
6be3ae45 | 4622 | r = xstate_required_size(kvm_get_filtered_xcr0(), false); |
be50b206 GZ |
4623 | if (r < sizeof(struct kvm_xsave)) |
4624 | r = sizeof(struct kvm_xsave); | |
4625 | break; | |
1c4dc573 | 4626 | } |
ba7bb663 DD |
4627 | case KVM_CAP_PMU_CAPABILITY: |
4628 | r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0; | |
4629 | break; | |
6d849191 OU |
4630 | case KVM_CAP_DISABLE_QUIRKS2: |
4631 | r = KVM_X86_VALID_QUIRKS; | |
4632 | break; | |
2f4073e0 TX |
4633 | case KVM_CAP_X86_NOTIFY_VMEXIT: |
4634 | r = kvm_caps.has_notify_vmexit; | |
4635 | break; | |
018d00d2 | 4636 | default: |
018d00d2 ZX |
4637 | break; |
4638 | } | |
4639 | return r; | |
56f289a8 SC |
4640 | } |
4641 | ||
4642 | static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr) | |
4643 | { | |
4644 | void __user *uaddr = (void __user*)(unsigned long)attr->addr; | |
018d00d2 | 4645 | |
56f289a8 | 4646 | if ((u64)(unsigned long)uaddr != attr->addr) |
6e37ec88 | 4647 | return ERR_PTR_USR(-EFAULT); |
56f289a8 | 4648 | return uaddr; |
018d00d2 ZX |
4649 | } |
4650 | ||
dd6e6312 PB |
4651 | static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr) |
4652 | { | |
4653 | u64 __user *uaddr = kvm_get_attr_addr(attr); | |
4654 | ||
4655 | if (attr->group) | |
4656 | return -ENXIO; | |
4657 | ||
4658 | if (IS_ERR(uaddr)) | |
4659 | return PTR_ERR(uaddr); | |
4660 | ||
4661 | switch (attr->attr) { | |
4662 | case KVM_X86_XCOMP_GUEST_SUPP: | |
938c8745 | 4663 | if (put_user(kvm_caps.supported_xcr0, uaddr)) |
dd6e6312 PB |
4664 | return -EFAULT; |
4665 | return 0; | |
4666 | default: | |
4667 | return -ENXIO; | |
4668 | break; | |
4669 | } | |
4670 | } | |
4671 | ||
4672 | static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr) | |
4673 | { | |
4674 | if (attr->group) | |
4675 | return -ENXIO; | |
4676 | ||
4677 | switch (attr->attr) { | |
4678 | case KVM_X86_XCOMP_GUEST_SUPP: | |
4679 | return 0; | |
4680 | default: | |
4681 | return -ENXIO; | |
4682 | } | |
4683 | } | |
4684 | ||
043405e1 CO |
4685 | long kvm_arch_dev_ioctl(struct file *filp, |
4686 | unsigned int ioctl, unsigned long arg) | |
4687 | { | |
4688 | void __user *argp = (void __user *)arg; | |
4689 | long r; | |
4690 | ||
4691 | switch (ioctl) { | |
4692 | case KVM_GET_MSR_INDEX_LIST: { | |
4693 | struct kvm_msr_list __user *user_msr_list = argp; | |
4694 | struct kvm_msr_list msr_list; | |
4695 | unsigned n; | |
4696 | ||
4697 | r = -EFAULT; | |
0e96f31e | 4698 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
4699 | goto out; |
4700 | n = msr_list.nmsrs; | |
62ef68bb | 4701 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 4702 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
4703 | goto out; |
4704 | r = -E2BIG; | |
e125e7b6 | 4705 | if (n < msr_list.nmsrs) |
043405e1 CO |
4706 | goto out; |
4707 | r = -EFAULT; | |
4708 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
4709 | num_msrs_to_save * sizeof(u32))) | |
4710 | goto out; | |
e125e7b6 | 4711 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 4712 | &emulated_msrs, |
62ef68bb | 4713 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
4714 | goto out; |
4715 | r = 0; | |
4716 | break; | |
4717 | } | |
9c15bb1d BP |
4718 | case KVM_GET_SUPPORTED_CPUID: |
4719 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
4720 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
4721 | struct kvm_cpuid2 cpuid; | |
4722 | ||
4723 | r = -EFAULT; | |
0e96f31e | 4724 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 4725 | goto out; |
9c15bb1d BP |
4726 | |
4727 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
4728 | ioctl); | |
674eea0f AK |
4729 | if (r) |
4730 | goto out; | |
4731 | ||
4732 | r = -EFAULT; | |
0e96f31e | 4733 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
4734 | goto out; |
4735 | r = 0; | |
4736 | break; | |
4737 | } | |
cf6c26ec | 4738 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 4739 | r = -EFAULT; |
938c8745 SC |
4740 | if (copy_to_user(argp, &kvm_caps.supported_mce_cap, |
4741 | sizeof(kvm_caps.supported_mce_cap))) | |
890ca9ae HY |
4742 | goto out; |
4743 | r = 0; | |
4744 | break; | |
801e459a TL |
4745 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
4746 | struct kvm_msr_list __user *user_msr_list = argp; | |
4747 | struct kvm_msr_list msr_list; | |
4748 | unsigned int n; | |
4749 | ||
4750 | r = -EFAULT; | |
4751 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
4752 | goto out; | |
4753 | n = msr_list.nmsrs; | |
4754 | msr_list.nmsrs = num_msr_based_features; | |
4755 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
4756 | goto out; | |
4757 | r = -E2BIG; | |
4758 | if (n < msr_list.nmsrs) | |
4759 | goto out; | |
4760 | r = -EFAULT; | |
4761 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
4762 | num_msr_based_features * sizeof(u32))) | |
4763 | goto out; | |
4764 | r = 0; | |
4765 | break; | |
4766 | } | |
4767 | case KVM_GET_MSRS: | |
4768 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
4769 | break; | |
c21d54f0 VK |
4770 | case KVM_GET_SUPPORTED_HV_CPUID: |
4771 | r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); | |
4772 | break; | |
dd6e6312 PB |
4773 | case KVM_GET_DEVICE_ATTR: { |
4774 | struct kvm_device_attr attr; | |
4775 | r = -EFAULT; | |
4776 | if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) | |
4777 | break; | |
4778 | r = kvm_x86_dev_get_attr(&attr); | |
4779 | break; | |
4780 | } | |
4781 | case KVM_HAS_DEVICE_ATTR: { | |
4782 | struct kvm_device_attr attr; | |
4783 | r = -EFAULT; | |
4784 | if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) | |
4785 | break; | |
4786 | r = kvm_x86_dev_has_attr(&attr); | |
4787 | break; | |
4788 | } | |
043405e1 CO |
4789 | default: |
4790 | r = -EINVAL; | |
cf6c26ec | 4791 | break; |
043405e1 CO |
4792 | } |
4793 | out: | |
4794 | return r; | |
4795 | } | |
4796 | ||
f5f48ee1 SY |
4797 | static void wbinvd_ipi(void *garbage) |
4798 | { | |
4799 | wbinvd(); | |
4800 | } | |
4801 | ||
4802 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4803 | { | |
e0f0bbc5 | 4804 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
4805 | } |
4806 | ||
313a3dc7 CO |
4807 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
4808 | { | |
f5f48ee1 SY |
4809 | /* Address WBINVD may be executed by guest */ |
4810 | if (need_emulate_wbinvd(vcpu)) { | |
b3646477 | 4811 | if (static_call(kvm_x86_has_wbinvd_exit)()) |
f5f48ee1 SY |
4812 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
4813 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
4814 | smp_call_function_single(vcpu->cpu, | |
4815 | wbinvd_ipi, NULL, 1); | |
4816 | } | |
4817 | ||
b3646477 | 4818 | static_call(kvm_x86_vcpu_load)(vcpu, cpu); |
8f6055cb | 4819 | |
37486135 BM |
4820 | /* Save host pkru register if supported */ |
4821 | vcpu->arch.host_pkru = read_pkru(); | |
4822 | ||
0dd6a6ed ZA |
4823 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
4824 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
4825 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
4826 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 4827 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 4828 | } |
8f6055cb | 4829 | |
b0c39dc6 | 4830 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 4831 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 4832 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
4833 | if (tsc_delta < 0) |
4834 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 4835 | |
b0c39dc6 | 4836 | if (kvm_check_tsc_unstable()) { |
9b399dfd | 4837 | u64 offset = kvm_compute_l1_tsc_offset(vcpu, |
b183aa58 | 4838 | vcpu->arch.last_guest_tsc); |
a545ab6a | 4839 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 4840 | vcpu->arch.tsc_catchup = 1; |
c285545f | 4841 | } |
a749e247 PB |
4842 | |
4843 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
4844 | kvm_lapic_restart_hv_timer(vcpu); | |
4845 | ||
d98d07ca MT |
4846 | /* |
4847 | * On a host with synchronized TSC, there is no need to update | |
4848 | * kvmclock on vcpu->cpu migration | |
4849 | */ | |
4850 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 4851 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 4852 | if (vcpu->cpu != cpu) |
1bd2009e | 4853 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 4854 | vcpu->cpu = cpu; |
6b7d7e76 | 4855 | } |
c9aaa895 | 4856 | |
c9aaa895 | 4857 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
4858 | } |
4859 | ||
0b9f6c46 PX |
4860 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
4861 | { | |
7e2175eb DW |
4862 | struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; |
4863 | struct kvm_steal_time __user *st; | |
4864 | struct kvm_memslots *slots; | |
4865 | static const u8 preempted = KVM_VCPU_PREEMPTED; | |
c3c28d24 | 4866 | gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; |
b0431382 | 4867 | |
6cd88243 PB |
4868 | /* |
4869 | * The vCPU can be marked preempted if and only if the VM-Exit was on | |
4870 | * an instruction boundary and will not trigger guest emulation of any | |
4871 | * kind (see vcpu_run). Vendor specific code controls (conservatively) | |
4872 | * when this is true, for example allowing the vCPU to be marked | |
4873 | * preempted if and only if the VM-Exit was due to a host interrupt. | |
4874 | */ | |
4875 | if (!vcpu->arch.at_instruction_boundary) { | |
4876 | vcpu->stat.preemption_other++; | |
4877 | return; | |
4878 | } | |
4879 | ||
4880 | vcpu->stat.preemption_reported++; | |
0b9f6c46 PX |
4881 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
4882 | return; | |
4883 | ||
a6bd811f | 4884 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
4885 | return; |
4886 | ||
7e2175eb DW |
4887 | /* This happens on process exit */ |
4888 | if (unlikely(current->mm != vcpu->kvm->mm)) | |
9c1a0744 | 4889 | return; |
b0431382 | 4890 | |
7e2175eb DW |
4891 | slots = kvm_memslots(vcpu->kvm); |
4892 | ||
4893 | if (unlikely(slots->generation != ghc->generation || | |
c3c28d24 | 4894 | gpa != ghc->gpa || |
7e2175eb | 4895 | kvm_is_error_hva(ghc->hva) || !ghc->memslot)) |
9c1a0744 | 4896 | return; |
b0431382 | 4897 | |
7e2175eb DW |
4898 | st = (struct kvm_steal_time __user *)ghc->hva; |
4899 | BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); | |
0b9f6c46 | 4900 | |
7e2175eb DW |
4901 | if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) |
4902 | vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; | |
0b9f6c46 | 4903 | |
7e2175eb | 4904 | mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); |
0b9f6c46 PX |
4905 | } |
4906 | ||
313a3dc7 CO |
4907 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
4908 | { | |
9c1a0744 WL |
4909 | int idx; |
4910 | ||
54aa83c9 PB |
4911 | if (vcpu->preempted) { |
4912 | if (!vcpu->arch.guest_state_protected) | |
4913 | vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); | |
de63ad4c | 4914 | |
54aa83c9 PB |
4915 | /* |
4916 | * Take the srcu lock as memslots will be accessed to check the gfn | |
4917 | * cache generation against the memslots generation. | |
4918 | */ | |
4919 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
4920 | if (kvm_xen_msr_enabled(vcpu->kvm)) | |
4921 | kvm_xen_runstate_set_preempted(vcpu); | |
4922 | else | |
4923 | kvm_steal_time_set_preempted(vcpu); | |
4924 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
4925 | } | |
30b5c851 | 4926 | |
b3646477 | 4927 | static_call(kvm_x86_vcpu_put)(vcpu); |
4ea1636b | 4928 | vcpu->arch.last_host_tsc = rdtsc(); |
313a3dc7 CO |
4929 | } |
4930 | ||
313a3dc7 CO |
4931 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
4932 | struct kvm_lapic_state *s) | |
4933 | { | |
37c4dbf3 | 4934 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); |
d62caabb | 4935 | |
a92e2543 | 4936 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
4937 | } |
4938 | ||
4939 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
4940 | struct kvm_lapic_state *s) | |
4941 | { | |
a92e2543 RK |
4942 | int r; |
4943 | ||
4944 | r = kvm_apic_set_state(vcpu, s); | |
4945 | if (r) | |
4946 | return r; | |
cb142eb7 | 4947 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
4948 | |
4949 | return 0; | |
4950 | } | |
4951 | ||
127a457a MG |
4952 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
4953 | { | |
71cc849b PB |
4954 | /* |
4955 | * We can accept userspace's request for interrupt injection | |
4956 | * as long as we have a place to store the interrupt number. | |
4957 | * The actual injection will happen when the CPU is able to | |
4958 | * deliver the interrupt. | |
4959 | */ | |
4960 | if (kvm_cpu_has_extint(vcpu)) | |
4961 | return false; | |
4962 | ||
4963 | /* Acknowledging ExtINT does not happen if LINT0 is masked. */ | |
127a457a MG |
4964 | return (!lapic_in_kernel(vcpu) || |
4965 | kvm_apic_accept_pic_intr(vcpu)); | |
4966 | } | |
4967 | ||
782d422b MG |
4968 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
4969 | { | |
fa7a549d PB |
4970 | /* |
4971 | * Do not cause an interrupt window exit if an exception | |
4972 | * is pending or an event needs reinjection; userspace | |
4973 | * might want to inject the interrupt manually using KVM_SET_REGS | |
4974 | * or KVM_SET_SREGS. For that to work, we must be at an | |
4975 | * instruction boundary and with no events half-injected. | |
4976 | */ | |
4977 | return (kvm_arch_interrupt_allowed(vcpu) && | |
4978 | kvm_cpu_accept_dm_intr(vcpu) && | |
4979 | !kvm_event_needs_reinjection(vcpu) && | |
7709aba8 | 4980 | !kvm_is_exception_pending(vcpu)); |
782d422b MG |
4981 | } |
4982 | ||
f77bc6a4 ZX |
4983 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
4984 | struct kvm_interrupt *irq) | |
4985 | { | |
02cdb50f | 4986 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 4987 | return -EINVAL; |
1c1a9ce9 SR |
4988 | |
4989 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
4990 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
4991 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4992 | return 0; | |
4993 | } | |
4994 | ||
4995 | /* | |
4996 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
4997 | * fail for in-kernel 8259. | |
4998 | */ | |
4999 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 5000 | return -ENXIO; |
f77bc6a4 | 5001 | |
1c1a9ce9 SR |
5002 | if (vcpu->arch.pending_external_vector != -1) |
5003 | return -EEXIST; | |
f77bc6a4 | 5004 | |
1c1a9ce9 | 5005 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 5006 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
5007 | return 0; |
5008 | } | |
5009 | ||
c4abb7c9 JK |
5010 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
5011 | { | |
c4abb7c9 | 5012 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
5013 | |
5014 | return 0; | |
5015 | } | |
5016 | ||
b209749f AK |
5017 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
5018 | struct kvm_tpr_access_ctl *tac) | |
5019 | { | |
5020 | if (tac->flags) | |
5021 | return -EINVAL; | |
5022 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
5023 | return 0; | |
5024 | } | |
5025 | ||
890ca9ae HY |
5026 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
5027 | u64 mcg_cap) | |
5028 | { | |
5029 | int r; | |
5030 | unsigned bank_num = mcg_cap & 0xff, bank; | |
5031 | ||
5032 | r = -EINVAL; | |
c4e0e4ab | 5033 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 5034 | goto out; |
938c8745 | 5035 | if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000)) |
890ca9ae HY |
5036 | goto out; |
5037 | r = 0; | |
5038 | vcpu->arch.mcg_cap = mcg_cap; | |
5039 | /* Init IA32_MCG_CTL to all 1s */ | |
5040 | if (mcg_cap & MCG_CTL_P) | |
5041 | vcpu->arch.mcg_ctl = ~(u64)0; | |
281b5278 JW |
5042 | /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */ |
5043 | for (bank = 0; bank < bank_num; bank++) { | |
890ca9ae | 5044 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; |
281b5278 JW |
5045 | if (mcg_cap & MCG_CMCI_P) |
5046 | vcpu->arch.mci_ctl2_banks[bank] = 0; | |
5047 | } | |
f83894b2 SC |
5048 | |
5049 | kvm_apic_after_set_mcg_cap(vcpu); | |
c45dcc71 | 5050 | |
b3646477 | 5051 | static_call(kvm_x86_setup_mce)(vcpu); |
890ca9ae HY |
5052 | out: |
5053 | return r; | |
5054 | } | |
5055 | ||
aebc3ca1 JW |
5056 | /* |
5057 | * Validate this is an UCNA (uncorrectable no action) error by checking the | |
5058 | * MCG_STATUS and MCi_STATUS registers: | |
5059 | * - none of the bits for Machine Check Exceptions are set | |
5060 | * - both the VAL (valid) and UC (uncorrectable) bits are set | |
5061 | * MCI_STATUS_PCC - Processor Context Corrupted | |
5062 | * MCI_STATUS_S - Signaled as a Machine Check Exception | |
5063 | * MCI_STATUS_AR - Software recoverable Action Required | |
5064 | */ | |
5065 | static bool is_ucna(struct kvm_x86_mce *mce) | |
5066 | { | |
5067 | return !mce->mcg_status && | |
5068 | !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) && | |
5069 | (mce->status & MCI_STATUS_VAL) && | |
5070 | (mce->status & MCI_STATUS_UC); | |
5071 | } | |
5072 | ||
5073 | static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks) | |
5074 | { | |
5075 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
5076 | ||
5077 | banks[1] = mce->status; | |
5078 | banks[2] = mce->addr; | |
5079 | banks[3] = mce->misc; | |
5080 | vcpu->arch.mcg_status = mce->mcg_status; | |
5081 | ||
5082 | if (!(mcg_cap & MCG_CMCI_P) || | |
5083 | !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN)) | |
5084 | return 0; | |
5085 | ||
5086 | if (lapic_in_kernel(vcpu)) | |
5087 | kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI); | |
5088 | ||
5089 | return 0; | |
5090 | } | |
5091 | ||
890ca9ae HY |
5092 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, |
5093 | struct kvm_x86_mce *mce) | |
5094 | { | |
5095 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
5096 | unsigned bank_num = mcg_cap & 0xff; | |
5097 | u64 *banks = vcpu->arch.mce_banks; | |
5098 | ||
5099 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
5100 | return -EINVAL; | |
aebc3ca1 JW |
5101 | |
5102 | banks += array_index_nospec(4 * mce->bank, 4 * bank_num); | |
5103 | ||
5104 | if (is_ucna(mce)) | |
5105 | return kvm_vcpu_x86_set_ucna(vcpu, mce, banks); | |
5106 | ||
890ca9ae HY |
5107 | /* |
5108 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
5109 | * reporting is disabled | |
5110 | */ | |
5111 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
5112 | vcpu->arch.mcg_ctl != ~(u64)0) | |
5113 | return 0; | |
890ca9ae HY |
5114 | /* |
5115 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
5116 | * reporting is disabled for the bank | |
5117 | */ | |
5118 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
5119 | return 0; | |
5120 | if (mce->status & MCI_STATUS_UC) { | |
5121 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
607475cf | 5122 | !kvm_is_cr4_bit_set(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 5123 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
5124 | return 0; |
5125 | } | |
5126 | if (banks[1] & MCI_STATUS_VAL) | |
5127 | mce->status |= MCI_STATUS_OVER; | |
5128 | banks[2] = mce->addr; | |
5129 | banks[3] = mce->misc; | |
5130 | vcpu->arch.mcg_status = mce->mcg_status; | |
5131 | banks[1] = mce->status; | |
5132 | kvm_queue_exception(vcpu, MC_VECTOR); | |
5133 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
5134 | || !(banks[1] & MCI_STATUS_UC)) { | |
5135 | if (banks[1] & MCI_STATUS_VAL) | |
5136 | mce->status |= MCI_STATUS_OVER; | |
5137 | banks[2] = mce->addr; | |
5138 | banks[3] = mce->misc; | |
5139 | banks[1] = mce->status; | |
5140 | } else | |
5141 | banks[1] |= MCI_STATUS_OVER; | |
5142 | return 0; | |
5143 | } | |
5144 | ||
3cfc3092 JK |
5145 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
5146 | struct kvm_vcpu_events *events) | |
5147 | { | |
7709aba8 | 5148 | struct kvm_queued_exception *ex; |
d4963e31 | 5149 | |
7460fb4a | 5150 | process_nmi(vcpu); |
59073aaf | 5151 | |
cf7316d0 | 5152 | #ifdef CONFIG_KVM_SMM |
1f7becf1 JZ |
5153 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
5154 | process_smi(vcpu); | |
cf7316d0 | 5155 | #endif |
1f7becf1 | 5156 | |
a06230b6 | 5157 | /* |
7709aba8 SC |
5158 | * KVM's ABI only allows for one exception to be migrated. Luckily, |
5159 | * the only time there can be two queued exceptions is if there's a | |
5160 | * non-exiting _injected_ exception, and a pending exiting exception. | |
5161 | * In that case, ignore the VM-Exiting exception as it's an extension | |
5162 | * of the injected exception. | |
5163 | */ | |
5164 | if (vcpu->arch.exception_vmexit.pending && | |
5165 | !vcpu->arch.exception.pending && | |
5166 | !vcpu->arch.exception.injected) | |
5167 | ex = &vcpu->arch.exception_vmexit; | |
5168 | else | |
5169 | ex = &vcpu->arch.exception; | |
5170 | ||
a06230b6 | 5171 | /* |
d4963e31 SC |
5172 | * In guest mode, payload delivery should be deferred if the exception |
5173 | * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1 | |
5174 | * intercepts #PF, ditto for DR6 and #DBs. If the per-VM capability, | |
5175 | * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not | |
5176 | * propagate the payload and so it cannot be safely deferred. Deliver | |
5177 | * the payload if the capability hasn't been requested. | |
a06230b6 OU |
5178 | */ |
5179 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
d4963e31 SC |
5180 | ex->pending && ex->has_payload) |
5181 | kvm_deliver_exception_payload(vcpu, ex); | |
a06230b6 | 5182 | |
85672346 PB |
5183 | memset(events, 0, sizeof(*events)); |
5184 | ||
664f8e26 | 5185 | /* |
59073aaf JM |
5186 | * The API doesn't provide the instruction length for software |
5187 | * exceptions, so don't report them. As long as the guest RIP | |
5188 | * isn't advanced, we should expect to encounter the exception | |
5189 | * again. | |
664f8e26 | 5190 | */ |
85672346 | 5191 | if (!kvm_exception_is_soft(ex->vector)) { |
d4963e31 SC |
5192 | events->exception.injected = ex->injected; |
5193 | events->exception.pending = ex->pending; | |
59073aaf JM |
5194 | /* |
5195 | * For ABI compatibility, deliberately conflate | |
5196 | * pending and injected exceptions when | |
5197 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
5198 | */ | |
5199 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
d4963e31 | 5200 | events->exception.injected |= ex->pending; |
59073aaf | 5201 | } |
d4963e31 SC |
5202 | events->exception.nr = ex->vector; |
5203 | events->exception.has_error_code = ex->has_error_code; | |
5204 | events->exception.error_code = ex->error_code; | |
5205 | events->exception_has_payload = ex->has_payload; | |
5206 | events->exception_payload = ex->payload; | |
3cfc3092 | 5207 | |
03b82a30 | 5208 | events->interrupt.injected = |
04140b41 | 5209 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 5210 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
b3646477 | 5211 | events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
3cfc3092 JK |
5212 | |
5213 | events->nmi.injected = vcpu->arch.nmi_injected; | |
fa4c027a | 5214 | events->nmi.pending = kvm_get_nr_pending_nmis(vcpu); |
b3646477 | 5215 | events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); |
3cfc3092 | 5216 | |
85672346 | 5217 | /* events->sipi_vector is never valid when reporting to user space */ |
3cfc3092 | 5218 | |
a7662aa5 | 5219 | #ifdef CONFIG_KVM_SMM |
f077825a PB |
5220 | events->smi.smm = is_smm(vcpu); |
5221 | events->smi.pending = vcpu->arch.smi_pending; | |
5222 | events->smi.smm_inside_nmi = | |
5223 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
a7662aa5 | 5224 | #endif |
f077825a PB |
5225 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); |
5226 | ||
dab4b911 | 5227 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
5228 | | KVM_VCPUEVENT_VALID_SHADOW |
5229 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
5230 | if (vcpu->kvm->arch.exception_payload_enabled) |
5231 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
ed235117 CQ |
5232 | if (vcpu->kvm->arch.triple_fault_event) { |
5233 | events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
5234 | events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT; | |
5235 | } | |
3cfc3092 JK |
5236 | } |
5237 | ||
5238 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
5239 | struct kvm_vcpu_events *events) | |
5240 | { | |
dab4b911 | 5241 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 5242 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 5243 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf | 5244 | | KVM_VCPUEVENT_VALID_SMM |
ed235117 CQ |
5245 | | KVM_VCPUEVENT_VALID_PAYLOAD |
5246 | | KVM_VCPUEVENT_VALID_TRIPLE_FAULT)) | |
3cfc3092 JK |
5247 | return -EINVAL; |
5248 | ||
59073aaf JM |
5249 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
5250 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
5251 | return -EINVAL; | |
5252 | if (events->exception.pending) | |
5253 | events->exception.injected = 0; | |
5254 | else | |
5255 | events->exception_has_payload = 0; | |
5256 | } else { | |
5257 | events->exception.pending = 0; | |
5258 | events->exception_has_payload = 0; | |
5259 | } | |
5260 | ||
5261 | if ((events->exception.injected || events->exception.pending) && | |
5262 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
5263 | return -EINVAL; |
5264 | ||
28bf2888 DH |
5265 | /* INITs are latched while in SMM */ |
5266 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
5267 | (events->smi.smm || events->smi.pending) && | |
5268 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
5269 | return -EINVAL; | |
5270 | ||
7460fb4a | 5271 | process_nmi(vcpu); |
7709aba8 SC |
5272 | |
5273 | /* | |
5274 | * Flag that userspace is stuffing an exception, the next KVM_RUN will | |
5275 | * morph the exception to a VM-Exit if appropriate. Do this only for | |
5276 | * pending exceptions, already-injected exceptions are not subject to | |
5277 | * intercpetion. Note, userspace that conflates pending and injected | |
5278 | * is hosed, and will incorrectly convert an injected exception into a | |
5279 | * pending exception, which in turn may cause a spurious VM-Exit. | |
5280 | */ | |
5281 | vcpu->arch.exception_from_userspace = events->exception.pending; | |
5282 | ||
5283 | vcpu->arch.exception_vmexit.pending = false; | |
5284 | ||
59073aaf JM |
5285 | vcpu->arch.exception.injected = events->exception.injected; |
5286 | vcpu->arch.exception.pending = events->exception.pending; | |
d4963e31 | 5287 | vcpu->arch.exception.vector = events->exception.nr; |
3cfc3092 JK |
5288 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; |
5289 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
5290 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
5291 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 5292 | |
04140b41 | 5293 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
5294 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
5295 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 5296 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
b3646477 JB |
5297 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, |
5298 | events->interrupt.shadow); | |
3cfc3092 JK |
5299 | |
5300 | vcpu->arch.nmi_injected = events->nmi.injected; | |
ab2ee212 | 5301 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) { |
bdedff26 SC |
5302 | vcpu->arch.nmi_pending = 0; |
5303 | atomic_set(&vcpu->arch.nmi_queued, events->nmi.pending); | |
5304 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
ab2ee212 | 5305 | } |
b3646477 | 5306 | static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); |
3cfc3092 | 5307 | |
66450a21 | 5308 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 5309 | lapic_in_kernel(vcpu)) |
66450a21 | 5310 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 5311 | |
f077825a | 5312 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
4b8e1b32 | 5313 | #ifdef CONFIG_KVM_SMM |
f7e57078 | 5314 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
f9697df2 | 5315 | kvm_leave_nested(vcpu); |
dc87275f | 5316 | kvm_smm_changed(vcpu, events->smi.smm); |
f7e57078 | 5317 | } |
6ef4e07e | 5318 | |
f077825a | 5319 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
5320 | |
5321 | if (events->smi.smm) { | |
5322 | if (events->smi.smm_inside_nmi) | |
5323 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 5324 | else |
f4ef1910 | 5325 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
5326 | } |
5327 | ||
4b8e1b32 PB |
5328 | #else |
5329 | if (events->smi.smm || events->smi.pending || | |
5330 | events->smi.smm_inside_nmi) | |
5331 | return -EINVAL; | |
5332 | #endif | |
5333 | ||
ff90afa7 LA |
5334 | if (lapic_in_kernel(vcpu)) { |
5335 | if (events->smi.latched_init) | |
5336 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
5337 | else | |
5338 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
5339 | } |
5340 | } | |
5341 | ||
ed235117 CQ |
5342 | if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) { |
5343 | if (!vcpu->kvm->arch.triple_fault_event) | |
5344 | return -EINVAL; | |
5345 | if (events->triple_fault.pending) | |
5346 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
5347 | else | |
5348 | kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
5349 | } | |
5350 | ||
3842d135 AK |
5351 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5352 | ||
3cfc3092 JK |
5353 | return 0; |
5354 | } | |
5355 | ||
a1efbe77 JK |
5356 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
5357 | struct kvm_debugregs *dbgregs) | |
5358 | { | |
73aaf249 JK |
5359 | unsigned long val; |
5360 | ||
2c10b614 | 5361 | memset(dbgregs, 0, sizeof(*dbgregs)); |
a1efbe77 | 5362 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 5363 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 5364 | dbgregs->dr6 = val; |
a1efbe77 | 5365 | dbgregs->dr7 = vcpu->arch.dr7; |
a1efbe77 JK |
5366 | } |
5367 | ||
5368 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
5369 | struct kvm_debugregs *dbgregs) | |
5370 | { | |
5371 | if (dbgregs->flags) | |
5372 | return -EINVAL; | |
5373 | ||
fd238002 | 5374 | if (!kvm_dr6_valid(dbgregs->dr6)) |
d14bdb55 | 5375 | return -EINVAL; |
fd238002 | 5376 | if (!kvm_dr7_valid(dbgregs->dr7)) |
d14bdb55 PB |
5377 | return -EINVAL; |
5378 | ||
a1efbe77 | 5379 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 5380 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
5381 | vcpu->arch.dr6 = dbgregs->dr6; |
5382 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 5383 | kvm_update_dr7(vcpu); |
a1efbe77 | 5384 | |
a1efbe77 JK |
5385 | return 0; |
5386 | } | |
5387 | ||
2d5b5a66 SY |
5388 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
5389 | struct kvm_xsave *guest_xsave) | |
5390 | { | |
d69c1382 | 5391 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) |
ed02b213 TL |
5392 | return; |
5393 | ||
d69c1382 TG |
5394 | fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, |
5395 | guest_xsave->region, | |
5396 | sizeof(guest_xsave->region), | |
5397 | vcpu->arch.pkru); | |
2d5b5a66 SY |
5398 | } |
5399 | ||
be50b206 GZ |
5400 | static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu, |
5401 | u8 *state, unsigned int size) | |
5402 | { | |
5403 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) | |
5404 | return; | |
5405 | ||
5406 | fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, | |
5407 | state, size, vcpu->arch.pkru); | |
5408 | } | |
5409 | ||
2d5b5a66 SY |
5410 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
5411 | struct kvm_xsave *guest_xsave) | |
5412 | { | |
d69c1382 | 5413 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) |
ed02b213 TL |
5414 | return 0; |
5415 | ||
d69c1382 TG |
5416 | return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, |
5417 | guest_xsave->region, | |
938c8745 SC |
5418 | kvm_caps.supported_xcr0, |
5419 | &vcpu->arch.pkru); | |
2d5b5a66 SY |
5420 | } |
5421 | ||
5422 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
5423 | struct kvm_xcrs *guest_xcrs) | |
5424 | { | |
d366bf7e | 5425 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
5426 | guest_xcrs->nr_xcrs = 0; |
5427 | return; | |
5428 | } | |
5429 | ||
5430 | guest_xcrs->nr_xcrs = 1; | |
5431 | guest_xcrs->flags = 0; | |
5432 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
5433 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
5434 | } | |
5435 | ||
5436 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
5437 | struct kvm_xcrs *guest_xcrs) | |
5438 | { | |
5439 | int i, r = 0; | |
5440 | ||
d366bf7e | 5441 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
5442 | return -EINVAL; |
5443 | ||
5444 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
5445 | return -EINVAL; | |
5446 | ||
5447 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
5448 | /* Only support XCR0 currently */ | |
c67a04cb | 5449 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 5450 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 5451 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
5452 | break; |
5453 | } | |
5454 | if (r) | |
5455 | r = -EINVAL; | |
5456 | return r; | |
5457 | } | |
5458 | ||
1c0b28c2 EM |
5459 | /* |
5460 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
5461 | * stopped by the hypervisor. This function will be called from the host only. | |
5462 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
5463 | * does not support pv clocks. | |
5464 | */ | |
5465 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
5466 | { | |
916d3608 | 5467 | if (!vcpu->arch.pv_time.active) |
1c0b28c2 | 5468 | return -EINVAL; |
51d59c6b | 5469 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
5470 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
5471 | return 0; | |
5472 | } | |
5473 | ||
828ca896 OU |
5474 | static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, |
5475 | struct kvm_device_attr *attr) | |
5476 | { | |
5477 | int r; | |
5478 | ||
5479 | switch (attr->attr) { | |
5480 | case KVM_VCPU_TSC_OFFSET: | |
5481 | r = 0; | |
5482 | break; | |
5483 | default: | |
5484 | r = -ENXIO; | |
5485 | } | |
5486 | ||
5487 | return r; | |
5488 | } | |
5489 | ||
5490 | static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, | |
5491 | struct kvm_device_attr *attr) | |
5492 | { | |
56f289a8 | 5493 | u64 __user *uaddr = kvm_get_attr_addr(attr); |
828ca896 OU |
5494 | int r; |
5495 | ||
56f289a8 SC |
5496 | if (IS_ERR(uaddr)) |
5497 | return PTR_ERR(uaddr); | |
828ca896 OU |
5498 | |
5499 | switch (attr->attr) { | |
5500 | case KVM_VCPU_TSC_OFFSET: | |
5501 | r = -EFAULT; | |
5502 | if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) | |
5503 | break; | |
5504 | r = 0; | |
5505 | break; | |
5506 | default: | |
5507 | r = -ENXIO; | |
5508 | } | |
5509 | ||
5510 | return r; | |
5511 | } | |
5512 | ||
5513 | static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, | |
5514 | struct kvm_device_attr *attr) | |
5515 | { | |
56f289a8 | 5516 | u64 __user *uaddr = kvm_get_attr_addr(attr); |
828ca896 OU |
5517 | struct kvm *kvm = vcpu->kvm; |
5518 | int r; | |
5519 | ||
56f289a8 SC |
5520 | if (IS_ERR(uaddr)) |
5521 | return PTR_ERR(uaddr); | |
828ca896 OU |
5522 | |
5523 | switch (attr->attr) { | |
5524 | case KVM_VCPU_TSC_OFFSET: { | |
5525 | u64 offset, tsc, ns; | |
5526 | unsigned long flags; | |
5527 | bool matched; | |
5528 | ||
5529 | r = -EFAULT; | |
5530 | if (get_user(offset, uaddr)) | |
5531 | break; | |
5532 | ||
5533 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); | |
5534 | ||
5535 | matched = (vcpu->arch.virtual_tsc_khz && | |
5536 | kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && | |
5537 | kvm->arch.last_tsc_offset == offset); | |
5538 | ||
62711e5a | 5539 | tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; |
828ca896 OU |
5540 | ns = get_kvmclock_base_ns(); |
5541 | ||
5542 | __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); | |
5543 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
5544 | ||
5545 | r = 0; | |
5546 | break; | |
5547 | } | |
5548 | default: | |
5549 | r = -ENXIO; | |
5550 | } | |
5551 | ||
5552 | return r; | |
5553 | } | |
5554 | ||
5555 | static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, | |
5556 | unsigned int ioctl, | |
5557 | void __user *argp) | |
5558 | { | |
5559 | struct kvm_device_attr attr; | |
5560 | int r; | |
5561 | ||
5562 | if (copy_from_user(&attr, argp, sizeof(attr))) | |
5563 | return -EFAULT; | |
5564 | ||
5565 | if (attr.group != KVM_VCPU_TSC_CTRL) | |
5566 | return -ENXIO; | |
5567 | ||
5568 | switch (ioctl) { | |
5569 | case KVM_HAS_DEVICE_ATTR: | |
5570 | r = kvm_arch_tsc_has_attr(vcpu, &attr); | |
5571 | break; | |
5572 | case KVM_GET_DEVICE_ATTR: | |
5573 | r = kvm_arch_tsc_get_attr(vcpu, &attr); | |
5574 | break; | |
5575 | case KVM_SET_DEVICE_ATTR: | |
5576 | r = kvm_arch_tsc_set_attr(vcpu, &attr); | |
5577 | break; | |
5578 | } | |
5579 | ||
5580 | return r; | |
5581 | } | |
5582 | ||
5c919412 AS |
5583 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
5584 | struct kvm_enable_cap *cap) | |
5585 | { | |
57b119da VK |
5586 | int r; |
5587 | uint16_t vmcs_version; | |
5588 | void __user *user_ptr; | |
5589 | ||
5c919412 AS |
5590 | if (cap->flags) |
5591 | return -EINVAL; | |
5592 | ||
5593 | switch (cap->cap) { | |
efc479e6 RK |
5594 | case KVM_CAP_HYPERV_SYNIC2: |
5595 | if (cap->args[0]) | |
5596 | return -EINVAL; | |
df561f66 | 5597 | fallthrough; |
b2869f28 | 5598 | |
5c919412 | 5599 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
5600 | if (!irqchip_in_kernel(vcpu->kvm)) |
5601 | return -EINVAL; | |
efc479e6 RK |
5602 | return kvm_hv_activate_synic(vcpu, cap->cap == |
5603 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 5604 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 5605 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 5606 | return -ENOTTY; |
33b22172 | 5607 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
5608 | if (!r) { |
5609 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
5610 | if (copy_to_user(user_ptr, &vmcs_version, | |
5611 | sizeof(vmcs_version))) | |
5612 | r = -EFAULT; | |
5613 | } | |
5614 | return r; | |
344c6c80 | 5615 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
b83237ad | 5616 | if (!kvm_x86_ops.enable_l2_tlb_flush) |
344c6c80 TL |
5617 | return -ENOTTY; |
5618 | ||
b83237ad | 5619 | return static_call(kvm_x86_enable_l2_tlb_flush)(vcpu); |
57b119da | 5620 | |
644f7067 VK |
5621 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
5622 | return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); | |
5623 | ||
66570e96 OU |
5624 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
5625 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
5626 | if (vcpu->arch.pv_cpuid.enforce) |
5627 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
5628 | |
5629 | return 0; | |
5c919412 AS |
5630 | default: |
5631 | return -EINVAL; | |
5632 | } | |
5633 | } | |
5634 | ||
313a3dc7 CO |
5635 | long kvm_arch_vcpu_ioctl(struct file *filp, |
5636 | unsigned int ioctl, unsigned long arg) | |
5637 | { | |
5638 | struct kvm_vcpu *vcpu = filp->private_data; | |
5639 | void __user *argp = (void __user *)arg; | |
5640 | int r; | |
d1ac91d8 | 5641 | union { |
6dba9403 | 5642 | struct kvm_sregs2 *sregs2; |
d1ac91d8 AK |
5643 | struct kvm_lapic_state *lapic; |
5644 | struct kvm_xsave *xsave; | |
5645 | struct kvm_xcrs *xcrs; | |
5646 | void *buffer; | |
5647 | } u; | |
5648 | ||
9b062471 CD |
5649 | vcpu_load(vcpu); |
5650 | ||
d1ac91d8 | 5651 | u.buffer = NULL; |
313a3dc7 CO |
5652 | switch (ioctl) { |
5653 | case KVM_GET_LAPIC: { | |
2204ae3c | 5654 | r = -EINVAL; |
bce87cce | 5655 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 5656 | goto out; |
254272ce BG |
5657 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
5658 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 5659 | |
b772ff36 | 5660 | r = -ENOMEM; |
d1ac91d8 | 5661 | if (!u.lapic) |
b772ff36 | 5662 | goto out; |
d1ac91d8 | 5663 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
5664 | if (r) |
5665 | goto out; | |
5666 | r = -EFAULT; | |
d1ac91d8 | 5667 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
5668 | goto out; |
5669 | r = 0; | |
5670 | break; | |
5671 | } | |
5672 | case KVM_SET_LAPIC: { | |
2204ae3c | 5673 | r = -EINVAL; |
bce87cce | 5674 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 5675 | goto out; |
ff5c2c03 | 5676 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
5677 | if (IS_ERR(u.lapic)) { |
5678 | r = PTR_ERR(u.lapic); | |
5679 | goto out_nofree; | |
5680 | } | |
ff5c2c03 | 5681 | |
d1ac91d8 | 5682 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
5683 | break; |
5684 | } | |
f77bc6a4 ZX |
5685 | case KVM_INTERRUPT: { |
5686 | struct kvm_interrupt irq; | |
5687 | ||
5688 | r = -EFAULT; | |
0e96f31e | 5689 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
5690 | goto out; |
5691 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
5692 | break; |
5693 | } | |
c4abb7c9 JK |
5694 | case KVM_NMI: { |
5695 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
5696 | break; |
5697 | } | |
f077825a | 5698 | case KVM_SMI: { |
b0b42197 | 5699 | r = kvm_inject_smi(vcpu); |
f077825a PB |
5700 | break; |
5701 | } | |
313a3dc7 CO |
5702 | case KVM_SET_CPUID: { |
5703 | struct kvm_cpuid __user *cpuid_arg = argp; | |
5704 | struct kvm_cpuid cpuid; | |
5705 | ||
5706 | r = -EFAULT; | |
0e96f31e | 5707 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
5708 | goto out; |
5709 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
5710 | break; |
5711 | } | |
07716717 DK |
5712 | case KVM_SET_CPUID2: { |
5713 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5714 | struct kvm_cpuid2 cpuid; | |
5715 | ||
5716 | r = -EFAULT; | |
0e96f31e | 5717 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5718 | goto out; |
5719 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 5720 | cpuid_arg->entries); |
07716717 DK |
5721 | break; |
5722 | } | |
5723 | case KVM_GET_CPUID2: { | |
5724 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5725 | struct kvm_cpuid2 cpuid; | |
5726 | ||
5727 | r = -EFAULT; | |
0e96f31e | 5728 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5729 | goto out; |
5730 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 5731 | cpuid_arg->entries); |
07716717 DK |
5732 | if (r) |
5733 | goto out; | |
5734 | r = -EFAULT; | |
0e96f31e | 5735 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
5736 | goto out; |
5737 | r = 0; | |
5738 | break; | |
5739 | } | |
801e459a TL |
5740 | case KVM_GET_MSRS: { |
5741 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 5742 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 5743 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5744 | break; |
801e459a TL |
5745 | } |
5746 | case KVM_SET_MSRS: { | |
5747 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 5748 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 5749 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5750 | break; |
801e459a | 5751 | } |
b209749f AK |
5752 | case KVM_TPR_ACCESS_REPORTING: { |
5753 | struct kvm_tpr_access_ctl tac; | |
5754 | ||
5755 | r = -EFAULT; | |
0e96f31e | 5756 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
5757 | goto out; |
5758 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
5759 | if (r) | |
5760 | goto out; | |
5761 | r = -EFAULT; | |
0e96f31e | 5762 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
5763 | goto out; |
5764 | r = 0; | |
5765 | break; | |
5766 | }; | |
b93463aa AK |
5767 | case KVM_SET_VAPIC_ADDR: { |
5768 | struct kvm_vapic_addr va; | |
7301d6ab | 5769 | int idx; |
b93463aa AK |
5770 | |
5771 | r = -EINVAL; | |
35754c98 | 5772 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
5773 | goto out; |
5774 | r = -EFAULT; | |
0e96f31e | 5775 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 5776 | goto out; |
7301d6ab | 5777 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 5778 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 5779 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5780 | break; |
5781 | } | |
890ca9ae HY |
5782 | case KVM_X86_SETUP_MCE: { |
5783 | u64 mcg_cap; | |
5784 | ||
5785 | r = -EFAULT; | |
0e96f31e | 5786 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
5787 | goto out; |
5788 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
5789 | break; | |
5790 | } | |
5791 | case KVM_X86_SET_MCE: { | |
5792 | struct kvm_x86_mce mce; | |
5793 | ||
5794 | r = -EFAULT; | |
0e96f31e | 5795 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
5796 | goto out; |
5797 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
5798 | break; | |
5799 | } | |
3cfc3092 JK |
5800 | case KVM_GET_VCPU_EVENTS: { |
5801 | struct kvm_vcpu_events events; | |
5802 | ||
5803 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
5804 | ||
5805 | r = -EFAULT; | |
5806 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
5807 | break; | |
5808 | r = 0; | |
5809 | break; | |
5810 | } | |
5811 | case KVM_SET_VCPU_EVENTS: { | |
5812 | struct kvm_vcpu_events events; | |
5813 | ||
5814 | r = -EFAULT; | |
5815 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
5816 | break; | |
5817 | ||
5818 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
5819 | break; | |
5820 | } | |
a1efbe77 JK |
5821 | case KVM_GET_DEBUGREGS: { |
5822 | struct kvm_debugregs dbgregs; | |
5823 | ||
5824 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
5825 | ||
5826 | r = -EFAULT; | |
5827 | if (copy_to_user(argp, &dbgregs, | |
5828 | sizeof(struct kvm_debugregs))) | |
5829 | break; | |
5830 | r = 0; | |
5831 | break; | |
5832 | } | |
5833 | case KVM_SET_DEBUGREGS: { | |
5834 | struct kvm_debugregs dbgregs; | |
5835 | ||
5836 | r = -EFAULT; | |
5837 | if (copy_from_user(&dbgregs, argp, | |
5838 | sizeof(struct kvm_debugregs))) | |
5839 | break; | |
5840 | ||
5841 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
5842 | break; | |
5843 | } | |
2d5b5a66 | 5844 | case KVM_GET_XSAVE: { |
be50b206 GZ |
5845 | r = -EINVAL; |
5846 | if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave)) | |
5847 | break; | |
5848 | ||
254272ce | 5849 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5850 | r = -ENOMEM; |
d1ac91d8 | 5851 | if (!u.xsave) |
2d5b5a66 SY |
5852 | break; |
5853 | ||
d1ac91d8 | 5854 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5855 | |
5856 | r = -EFAULT; | |
d1ac91d8 | 5857 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
5858 | break; |
5859 | r = 0; | |
5860 | break; | |
5861 | } | |
5862 | case KVM_SET_XSAVE: { | |
be50b206 GZ |
5863 | int size = vcpu->arch.guest_fpu.uabi_size; |
5864 | ||
5865 | u.xsave = memdup_user(argp, size); | |
9b062471 CD |
5866 | if (IS_ERR(u.xsave)) { |
5867 | r = PTR_ERR(u.xsave); | |
5868 | goto out_nofree; | |
5869 | } | |
2d5b5a66 | 5870 | |
d1ac91d8 | 5871 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5872 | break; |
5873 | } | |
be50b206 GZ |
5874 | |
5875 | case KVM_GET_XSAVE2: { | |
5876 | int size = vcpu->arch.guest_fpu.uabi_size; | |
5877 | ||
5878 | u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT); | |
5879 | r = -ENOMEM; | |
5880 | if (!u.xsave) | |
5881 | break; | |
5882 | ||
5883 | kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size); | |
5884 | ||
5885 | r = -EFAULT; | |
5886 | if (copy_to_user(argp, u.xsave, size)) | |
5887 | break; | |
5888 | ||
5889 | r = 0; | |
5890 | break; | |
5891 | } | |
5892 | ||
2d5b5a66 | 5893 | case KVM_GET_XCRS: { |
254272ce | 5894 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5895 | r = -ENOMEM; |
d1ac91d8 | 5896 | if (!u.xcrs) |
2d5b5a66 SY |
5897 | break; |
5898 | ||
d1ac91d8 | 5899 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5900 | |
5901 | r = -EFAULT; | |
d1ac91d8 | 5902 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
5903 | sizeof(struct kvm_xcrs))) |
5904 | break; | |
5905 | r = 0; | |
5906 | break; | |
5907 | } | |
5908 | case KVM_SET_XCRS: { | |
ff5c2c03 | 5909 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
5910 | if (IS_ERR(u.xcrs)) { |
5911 | r = PTR_ERR(u.xcrs); | |
5912 | goto out_nofree; | |
5913 | } | |
2d5b5a66 | 5914 | |
d1ac91d8 | 5915 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5916 | break; |
5917 | } | |
92a1f12d JR |
5918 | case KVM_SET_TSC_KHZ: { |
5919 | u32 user_tsc_khz; | |
5920 | ||
5921 | r = -EINVAL; | |
92a1f12d JR |
5922 | user_tsc_khz = (u32)arg; |
5923 | ||
938c8745 SC |
5924 | if (kvm_caps.has_tsc_control && |
5925 | user_tsc_khz >= kvm_caps.max_guest_tsc_khz) | |
92a1f12d JR |
5926 | goto out; |
5927 | ||
cc578287 ZA |
5928 | if (user_tsc_khz == 0) |
5929 | user_tsc_khz = tsc_khz; | |
5930 | ||
381d585c HZ |
5931 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
5932 | r = 0; | |
92a1f12d | 5933 | |
92a1f12d JR |
5934 | goto out; |
5935 | } | |
5936 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 5937 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
5938 | goto out; |
5939 | } | |
1c0b28c2 EM |
5940 | case KVM_KVMCLOCK_CTRL: { |
5941 | r = kvm_set_guest_paused(vcpu); | |
5942 | goto out; | |
5943 | } | |
5c919412 AS |
5944 | case KVM_ENABLE_CAP: { |
5945 | struct kvm_enable_cap cap; | |
5946 | ||
5947 | r = -EFAULT; | |
5948 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
5949 | goto out; | |
5950 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
5951 | break; | |
5952 | } | |
8fcc4b59 JM |
5953 | case KVM_GET_NESTED_STATE: { |
5954 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5955 | u32 user_data_size; | |
5956 | ||
5957 | r = -EINVAL; | |
33b22172 | 5958 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
5959 | break; |
5960 | ||
5961 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 5962 | r = -EFAULT; |
8fcc4b59 | 5963 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 5964 | break; |
8fcc4b59 | 5965 | |
33b22172 PB |
5966 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
5967 | user_data_size); | |
8fcc4b59 | 5968 | if (r < 0) |
26b471c7 | 5969 | break; |
8fcc4b59 JM |
5970 | |
5971 | if (r > user_data_size) { | |
5972 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
5973 | r = -EFAULT; |
5974 | else | |
5975 | r = -E2BIG; | |
5976 | break; | |
8fcc4b59 | 5977 | } |
26b471c7 | 5978 | |
8fcc4b59 JM |
5979 | r = 0; |
5980 | break; | |
5981 | } | |
5982 | case KVM_SET_NESTED_STATE: { | |
5983 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5984 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 5985 | int idx; |
8fcc4b59 JM |
5986 | |
5987 | r = -EINVAL; | |
33b22172 | 5988 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
5989 | break; |
5990 | ||
26b471c7 | 5991 | r = -EFAULT; |
8fcc4b59 | 5992 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 5993 | break; |
8fcc4b59 | 5994 | |
26b471c7 | 5995 | r = -EINVAL; |
8fcc4b59 | 5996 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 5997 | break; |
8fcc4b59 JM |
5998 | |
5999 | if (kvm_state.flags & | |
8cab6507 | 6000 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
6001 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
6002 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 6003 | break; |
8fcc4b59 JM |
6004 | |
6005 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
6006 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
6007 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 6008 | break; |
8fcc4b59 | 6009 | |
ad5996d9 | 6010 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 6011 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 6012 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
6013 | break; |
6014 | } | |
c21d54f0 VK |
6015 | case KVM_GET_SUPPORTED_HV_CPUID: |
6016 | r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); | |
2bc39970 | 6017 | break; |
b59b153d | 6018 | #ifdef CONFIG_KVM_XEN |
3e324615 DW |
6019 | case KVM_XEN_VCPU_GET_ATTR: { |
6020 | struct kvm_xen_vcpu_attr xva; | |
6021 | ||
6022 | r = -EFAULT; | |
6023 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
6024 | goto out; | |
6025 | r = kvm_xen_vcpu_get_attr(vcpu, &xva); | |
6026 | if (!r && copy_to_user(argp, &xva, sizeof(xva))) | |
6027 | r = -EFAULT; | |
6028 | break; | |
6029 | } | |
6030 | case KVM_XEN_VCPU_SET_ATTR: { | |
6031 | struct kvm_xen_vcpu_attr xva; | |
6032 | ||
6033 | r = -EFAULT; | |
6034 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
6035 | goto out; | |
6036 | r = kvm_xen_vcpu_set_attr(vcpu, &xva); | |
6037 | break; | |
6038 | } | |
b59b153d | 6039 | #endif |
6dba9403 ML |
6040 | case KVM_GET_SREGS2: { |
6041 | u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); | |
6042 | r = -ENOMEM; | |
6043 | if (!u.sregs2) | |
6044 | goto out; | |
6045 | __get_sregs2(vcpu, u.sregs2); | |
6046 | r = -EFAULT; | |
6047 | if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) | |
6048 | goto out; | |
6049 | r = 0; | |
6050 | break; | |
6051 | } | |
6052 | case KVM_SET_SREGS2: { | |
6053 | u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); | |
6054 | if (IS_ERR(u.sregs2)) { | |
6055 | r = PTR_ERR(u.sregs2); | |
6056 | u.sregs2 = NULL; | |
6057 | goto out; | |
6058 | } | |
6059 | r = __set_sregs2(vcpu, u.sregs2); | |
6060 | break; | |
6061 | } | |
828ca896 OU |
6062 | case KVM_HAS_DEVICE_ATTR: |
6063 | case KVM_GET_DEVICE_ATTR: | |
6064 | case KVM_SET_DEVICE_ATTR: | |
6065 | r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); | |
6066 | break; | |
313a3dc7 CO |
6067 | default: |
6068 | r = -EINVAL; | |
6069 | } | |
6070 | out: | |
d1ac91d8 | 6071 | kfree(u.buffer); |
9b062471 CD |
6072 | out_nofree: |
6073 | vcpu_put(vcpu); | |
313a3dc7 CO |
6074 | return r; |
6075 | } | |
6076 | ||
1499fa80 | 6077 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
6078 | { |
6079 | return VM_FAULT_SIGBUS; | |
6080 | } | |
6081 | ||
1fe779f8 CO |
6082 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
6083 | { | |
6084 | int ret; | |
6085 | ||
6086 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 6087 | return -EINVAL; |
b3646477 | 6088 | ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); |
1fe779f8 CO |
6089 | return ret; |
6090 | } | |
6091 | ||
b927a3ce SY |
6092 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
6093 | u64 ident_addr) | |
6094 | { | |
b3646477 | 6095 | return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); |
b927a3ce SY |
6096 | } |
6097 | ||
1fe779f8 | 6098 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 6099 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
6100 | { |
6101 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
6102 | return -EINVAL; | |
6103 | ||
79fac95e | 6104 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
6105 | |
6106 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 6107 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 6108 | |
79fac95e | 6109 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
6110 | return 0; |
6111 | } | |
6112 | ||
1fe779f8 CO |
6113 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
6114 | { | |
90bca052 | 6115 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
6116 | int r; |
6117 | ||
6118 | r = 0; | |
6119 | switch (chip->chip_id) { | |
6120 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 6121 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
6122 | sizeof(struct kvm_pic_state)); |
6123 | break; | |
6124 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 6125 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
6126 | sizeof(struct kvm_pic_state)); |
6127 | break; | |
6128 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 6129 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
6130 | break; |
6131 | default: | |
6132 | r = -EINVAL; | |
6133 | break; | |
6134 | } | |
6135 | return r; | |
6136 | } | |
6137 | ||
6138 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
6139 | { | |
90bca052 | 6140 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
6141 | int r; |
6142 | ||
6143 | r = 0; | |
6144 | switch (chip->chip_id) { | |
6145 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
6146 | spin_lock(&pic->lock); |
6147 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 6148 | sizeof(struct kvm_pic_state)); |
90bca052 | 6149 | spin_unlock(&pic->lock); |
1fe779f8 CO |
6150 | break; |
6151 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
6152 | spin_lock(&pic->lock); |
6153 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 6154 | sizeof(struct kvm_pic_state)); |
90bca052 | 6155 | spin_unlock(&pic->lock); |
1fe779f8 CO |
6156 | break; |
6157 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 6158 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
6159 | break; |
6160 | default: | |
6161 | r = -EINVAL; | |
6162 | break; | |
6163 | } | |
90bca052 | 6164 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
6165 | return r; |
6166 | } | |
6167 | ||
e0f63cb9 SY |
6168 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
6169 | { | |
34f3941c RK |
6170 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
6171 | ||
6172 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
6173 | ||
6174 | mutex_lock(&kps->lock); | |
6175 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
6176 | mutex_unlock(&kps->lock); | |
2da29bcc | 6177 | return 0; |
e0f63cb9 SY |
6178 | } |
6179 | ||
6180 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
6181 | { | |
0185604c | 6182 | int i; |
09edea72 RK |
6183 | struct kvm_pit *pit = kvm->arch.vpit; |
6184 | ||
6185 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 6186 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 6187 | for (i = 0; i < 3; i++) |
09edea72 RK |
6188 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
6189 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 6190 | return 0; |
e9f42757 BK |
6191 | } |
6192 | ||
6193 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
6194 | { | |
e9f42757 BK |
6195 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
6196 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
6197 | sizeof(ps->channels)); | |
6198 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
6199 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 6200 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 6201 | return 0; |
e9f42757 BK |
6202 | } |
6203 | ||
6204 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
6205 | { | |
2da29bcc | 6206 | int start = 0; |
0185604c | 6207 | int i; |
e9f42757 | 6208 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
6209 | struct kvm_pit *pit = kvm->arch.vpit; |
6210 | ||
6211 | mutex_lock(&pit->pit_state.lock); | |
6212 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
6213 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
6214 | if (!prev_legacy && cur_legacy) | |
6215 | start = 1; | |
09edea72 RK |
6216 | memcpy(&pit->pit_state.channels, &ps->channels, |
6217 | sizeof(pit->pit_state.channels)); | |
6218 | pit->pit_state.flags = ps->flags; | |
0185604c | 6219 | for (i = 0; i < 3; i++) |
09edea72 | 6220 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 6221 | start && i == 0); |
09edea72 | 6222 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 6223 | return 0; |
e0f63cb9 SY |
6224 | } |
6225 | ||
52d939a0 MT |
6226 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
6227 | struct kvm_reinject_control *control) | |
6228 | { | |
71474e2f RK |
6229 | struct kvm_pit *pit = kvm->arch.vpit; |
6230 | ||
71474e2f RK |
6231 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
6232 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
6233 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
6234 | */ | |
6235 | mutex_lock(&pit->pit_state.lock); | |
6236 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
6237 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 6238 | |
52d939a0 MT |
6239 | return 0; |
6240 | } | |
6241 | ||
0dff0846 | 6242 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 6243 | { |
a018eba5 | 6244 | |
88178fd4 | 6245 | /* |
a018eba5 SC |
6246 | * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called |
6247 | * before reporting dirty_bitmap to userspace. KVM flushes the buffers | |
6248 | * on all VM-Exits, thus we only need to kick running vCPUs to force a | |
6249 | * VM-Exit. | |
88178fd4 | 6250 | */ |
a018eba5 | 6251 | struct kvm_vcpu *vcpu; |
46808a4c | 6252 | unsigned long i; |
a018eba5 SC |
6253 | |
6254 | kvm_for_each_vcpu(i, vcpu, kvm) | |
6255 | kvm_vcpu_kick(vcpu); | |
5bb064dc ZX |
6256 | } |
6257 | ||
aa2fbe6d YZ |
6258 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
6259 | bool line_status) | |
23d43cf9 CD |
6260 | { |
6261 | if (!irqchip_in_kernel(kvm)) | |
6262 | return -ENXIO; | |
6263 | ||
6264 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
6265 | irq_event->irq, irq_event->level, |
6266 | line_status); | |
23d43cf9 CD |
6267 | return 0; |
6268 | } | |
6269 | ||
e5d83c74 PB |
6270 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
6271 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
6272 | { |
6273 | int r; | |
6274 | ||
6275 | if (cap->flags) | |
6276 | return -EINVAL; | |
6277 | ||
6278 | switch (cap->cap) { | |
6d849191 OU |
6279 | case KVM_CAP_DISABLE_QUIRKS2: |
6280 | r = -EINVAL; | |
6281 | if (cap->args[0] & ~KVM_X86_VALID_QUIRKS) | |
6282 | break; | |
6283 | fallthrough; | |
90de4a18 NA |
6284 | case KVM_CAP_DISABLE_QUIRKS: |
6285 | kvm->arch.disabled_quirks = cap->args[0]; | |
6286 | r = 0; | |
6287 | break; | |
49df6397 SR |
6288 | case KVM_CAP_SPLIT_IRQCHIP: { |
6289 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
6290 | r = -EINVAL; |
6291 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
6292 | goto split_irqchip_unlock; | |
49df6397 SR |
6293 | r = -EEXIST; |
6294 | if (irqchip_in_kernel(kvm)) | |
6295 | goto split_irqchip_unlock; | |
557abc40 | 6296 | if (kvm->created_vcpus) |
49df6397 SR |
6297 | goto split_irqchip_unlock; |
6298 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 6299 | if (r) |
49df6397 SR |
6300 | goto split_irqchip_unlock; |
6301 | /* Pairs with irqchip_in_kernel. */ | |
6302 | smp_wmb(); | |
49776faf | 6303 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 6304 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
320af55a | 6305 | kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); |
49df6397 SR |
6306 | r = 0; |
6307 | split_irqchip_unlock: | |
6308 | mutex_unlock(&kvm->lock); | |
6309 | break; | |
6310 | } | |
37131313 RK |
6311 | case KVM_CAP_X2APIC_API: |
6312 | r = -EINVAL; | |
6313 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
6314 | break; | |
6315 | ||
6316 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
6317 | kvm->arch.x2apic_format = true; | |
c519265f RK |
6318 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
6319 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
6320 | |
6321 | r = 0; | |
6322 | break; | |
4d5422ce WL |
6323 | case KVM_CAP_X86_DISABLE_EXITS: |
6324 | r = -EINVAL; | |
6325 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
6326 | break; | |
6327 | ||
b31c114b WL |
6328 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
6329 | kvm->arch.pause_in_guest = true; | |
6f0f2d5e TL |
6330 | |
6331 | #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \ | |
6332 | "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests." | |
6333 | ||
6334 | if (!mitigate_smt_rsb) { | |
6335 | if (boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible() && | |
6336 | (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE)) | |
6337 | pr_warn_once(SMT_RSB_MSG); | |
6338 | ||
6339 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
6340 | kvm_can_mwait_in_guest()) | |
6341 | kvm->arch.mwait_in_guest = true; | |
6342 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) | |
6343 | kvm->arch.hlt_in_guest = true; | |
6344 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) | |
6345 | kvm->arch.cstate_in_guest = true; | |
6346 | } | |
6347 | ||
4d5422ce WL |
6348 | r = 0; |
6349 | break; | |
6fbbde9a DS |
6350 | case KVM_CAP_MSR_PLATFORM_INFO: |
6351 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
6352 | r = 0; | |
c4f55198 JM |
6353 | break; |
6354 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
6355 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
6356 | r = 0; | |
6fbbde9a | 6357 | break; |
ed235117 CQ |
6358 | case KVM_CAP_X86_TRIPLE_FAULT_EVENT: |
6359 | kvm->arch.triple_fault_event = cap->args[0]; | |
6360 | r = 0; | |
6361 | break; | |
1ae09954 | 6362 | case KVM_CAP_X86_USER_SPACE_MSR: |
cf5029d5 | 6363 | r = -EINVAL; |
db205f7e | 6364 | if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK) |
cf5029d5 | 6365 | break; |
1ae09954 AG |
6366 | kvm->arch.user_space_msr_mask = cap->args[0]; |
6367 | r = 0; | |
6368 | break; | |
fe6b6bc8 CQ |
6369 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
6370 | r = -EINVAL; | |
6371 | if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) | |
6372 | break; | |
6373 | ||
6374 | if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && | |
6375 | (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) | |
6376 | break; | |
6377 | ||
938c8745 | 6378 | if (kvm_caps.has_bus_lock_exit && |
fe6b6bc8 CQ |
6379 | cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) |
6380 | kvm->arch.bus_lock_detection_enabled = true; | |
6381 | r = 0; | |
6382 | break; | |
fe7e9488 SC |
6383 | #ifdef CONFIG_X86_SGX_KVM |
6384 | case KVM_CAP_SGX_ATTRIBUTE: { | |
6385 | unsigned long allowed_attributes = 0; | |
6386 | ||
6387 | r = sgx_set_attribute(&allowed_attributes, cap->args[0]); | |
6388 | if (r) | |
6389 | break; | |
6390 | ||
6391 | /* KVM only supports the PROVISIONKEY privileged attribute. */ | |
6392 | if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && | |
6393 | !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) | |
6394 | kvm->arch.sgx_provisioning_allowed = true; | |
6395 | else | |
6396 | r = -EINVAL; | |
6397 | break; | |
6398 | } | |
6399 | #endif | |
54526d1f NT |
6400 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
6401 | r = -EINVAL; | |
7ad02ef0 SC |
6402 | if (!kvm_x86_ops.vm_copy_enc_context_from) |
6403 | break; | |
6404 | ||
6405 | r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]); | |
6406 | break; | |
b5663931 PG |
6407 | case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: |
6408 | r = -EINVAL; | |
7ad02ef0 SC |
6409 | if (!kvm_x86_ops.vm_move_enc_context_from) |
6410 | break; | |
6411 | ||
6412 | r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]); | |
6413 | break; | |
0dbb1123 AK |
6414 | case KVM_CAP_EXIT_HYPERCALL: |
6415 | if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { | |
6416 | r = -EINVAL; | |
6417 | break; | |
6418 | } | |
6419 | kvm->arch.hypercall_exit_enabled = cap->args[0]; | |
6420 | r = 0; | |
6421 | break; | |
19238e75 AL |
6422 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
6423 | r = -EINVAL; | |
6424 | if (cap->args[0] & ~1) | |
6425 | break; | |
6426 | kvm->arch.exit_on_emulation_error = cap->args[0]; | |
6427 | r = 0; | |
6428 | break; | |
ba7bb663 DD |
6429 | case KVM_CAP_PMU_CAPABILITY: |
6430 | r = -EINVAL; | |
6431 | if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK)) | |
6432 | break; | |
6433 | ||
6434 | mutex_lock(&kvm->lock); | |
6435 | if (!kvm->created_vcpus) { | |
6436 | kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE); | |
6437 | r = 0; | |
6438 | } | |
6439 | mutex_unlock(&kvm->lock); | |
6440 | break; | |
35875316 ZG |
6441 | case KVM_CAP_MAX_VCPU_ID: |
6442 | r = -EINVAL; | |
6443 | if (cap->args[0] > KVM_MAX_VCPU_IDS) | |
6444 | break; | |
6445 | ||
6446 | mutex_lock(&kvm->lock); | |
6447 | if (kvm->arch.max_vcpu_ids == cap->args[0]) { | |
6448 | r = 0; | |
6449 | } else if (!kvm->arch.max_vcpu_ids) { | |
6450 | kvm->arch.max_vcpu_ids = cap->args[0]; | |
6451 | r = 0; | |
6452 | } | |
6453 | mutex_unlock(&kvm->lock); | |
6454 | break; | |
2f4073e0 TX |
6455 | case KVM_CAP_X86_NOTIFY_VMEXIT: |
6456 | r = -EINVAL; | |
6457 | if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS) | |
6458 | break; | |
6459 | if (!kvm_caps.has_notify_vmexit) | |
6460 | break; | |
6461 | if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED)) | |
6462 | break; | |
6463 | mutex_lock(&kvm->lock); | |
6464 | if (!kvm->created_vcpus) { | |
6465 | kvm->arch.notify_window = cap->args[0] >> 32; | |
6466 | kvm->arch.notify_vmexit_flags = (u32)cap->args[0]; | |
6467 | r = 0; | |
6468 | } | |
6469 | mutex_unlock(&kvm->lock); | |
6470 | break; | |
084cc29f BG |
6471 | case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: |
6472 | r = -EINVAL; | |
6473 | ||
6474 | /* | |
6475 | * Since the risk of disabling NX hugepages is a guest crashing | |
6476 | * the system, ensure the userspace process has permission to | |
6477 | * reboot the system. | |
6478 | * | |
6479 | * Note that unlike the reboot() syscall, the process must have | |
6480 | * this capability in the root namespace because exposing | |
6481 | * /dev/kvm into a container does not limit the scope of the | |
6482 | * iTLB multihit bug to that container. In other words, | |
6483 | * this must use capable(), not ns_capable(). | |
6484 | */ | |
6485 | if (!capable(CAP_SYS_BOOT)) { | |
6486 | r = -EPERM; | |
6487 | break; | |
6488 | } | |
6489 | ||
6490 | if (cap->args[0]) | |
6491 | break; | |
6492 | ||
6493 | mutex_lock(&kvm->lock); | |
6494 | if (!kvm->created_vcpus) { | |
6495 | kvm->arch.disable_nx_huge_pages = true; | |
6496 | r = 0; | |
6497 | } | |
6498 | mutex_unlock(&kvm->lock); | |
6499 | break; | |
90de4a18 NA |
6500 | default: |
6501 | r = -EINVAL; | |
6502 | break; | |
6503 | } | |
6504 | return r; | |
6505 | } | |
6506 | ||
b318e8de SC |
6507 | static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) |
6508 | { | |
6509 | struct kvm_x86_msr_filter *msr_filter; | |
6510 | ||
6511 | msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); | |
6512 | if (!msr_filter) | |
6513 | return NULL; | |
6514 | ||
6515 | msr_filter->default_allow = default_allow; | |
6516 | return msr_filter; | |
6517 | } | |
6518 | ||
6519 | static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) | |
1a155254 AG |
6520 | { |
6521 | u32 i; | |
1a155254 | 6522 | |
b318e8de SC |
6523 | if (!msr_filter) |
6524 | return; | |
6525 | ||
6526 | for (i = 0; i < msr_filter->count; i++) | |
6527 | kfree(msr_filter->ranges[i].bitmap); | |
1a155254 | 6528 | |
b318e8de | 6529 | kfree(msr_filter); |
1a155254 AG |
6530 | } |
6531 | ||
b318e8de SC |
6532 | static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, |
6533 | struct kvm_msr_filter_range *user_range) | |
1a155254 | 6534 | { |
1a155254 AG |
6535 | unsigned long *bitmap = NULL; |
6536 | size_t bitmap_size; | |
1a155254 AG |
6537 | |
6538 | if (!user_range->nmsrs) | |
6539 | return 0; | |
6540 | ||
8aff460f | 6541 | if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK) |
aca35288 SC |
6542 | return -EINVAL; |
6543 | ||
6544 | if (!user_range->flags) | |
6545 | return -EINVAL; | |
6546 | ||
1a155254 AG |
6547 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); |
6548 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
6549 | return -EINVAL; | |
6550 | ||
6551 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
6552 | if (IS_ERR(bitmap)) | |
6553 | return PTR_ERR(bitmap); | |
6554 | ||
aca35288 | 6555 | msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { |
1a155254 AG |
6556 | .flags = user_range->flags, |
6557 | .base = user_range->base, | |
6558 | .nmsrs = user_range->nmsrs, | |
6559 | .bitmap = bitmap, | |
6560 | }; | |
6561 | ||
b318e8de | 6562 | msr_filter->count++; |
1a155254 | 6563 | return 0; |
1a155254 AG |
6564 | } |
6565 | ||
2e3272bc AG |
6566 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, |
6567 | struct kvm_msr_filter *filter) | |
1a155254 | 6568 | { |
b318e8de | 6569 | struct kvm_x86_msr_filter *new_filter, *old_filter; |
1a155254 | 6570 | bool default_allow; |
043248b3 | 6571 | bool empty = true; |
4559e6cf | 6572 | int r; |
1a155254 AG |
6573 | u32 i; |
6574 | ||
c1340fe3 | 6575 | if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK) |
cf5029d5 AL |
6576 | return -EINVAL; |
6577 | ||
2e3272bc AG |
6578 | for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) |
6579 | empty &= !filter->ranges[i].nmsrs; | |
1a155254 | 6580 | |
2e3272bc | 6581 | default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY); |
043248b3 PB |
6582 | if (empty && !default_allow) |
6583 | return -EINVAL; | |
6584 | ||
b318e8de SC |
6585 | new_filter = kvm_alloc_msr_filter(default_allow); |
6586 | if (!new_filter) | |
6587 | return -ENOMEM; | |
1a155254 | 6588 | |
2e3272bc AG |
6589 | for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) { |
6590 | r = kvm_add_msr_filter(new_filter, &filter->ranges[i]); | |
b318e8de SC |
6591 | if (r) { |
6592 | kvm_free_msr_filter(new_filter); | |
6593 | return r; | |
6594 | } | |
1a155254 AG |
6595 | } |
6596 | ||
b318e8de | 6597 | mutex_lock(&kvm->lock); |
1fdefb8b ML |
6598 | old_filter = rcu_replace_pointer(kvm->arch.msr_filter, new_filter, |
6599 | mutex_is_locked(&kvm->lock)); | |
708f799d | 6600 | mutex_unlock(&kvm->lock); |
b318e8de SC |
6601 | synchronize_srcu(&kvm->srcu); |
6602 | ||
6603 | kvm_free_msr_filter(old_filter); | |
6604 | ||
1a155254 | 6605 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); |
1a155254 | 6606 | |
b318e8de | 6607 | return 0; |
1a155254 AG |
6608 | } |
6609 | ||
1739c701 AG |
6610 | #ifdef CONFIG_KVM_COMPAT |
6611 | /* for KVM_X86_SET_MSR_FILTER */ | |
6612 | struct kvm_msr_filter_range_compat { | |
6613 | __u32 flags; | |
6614 | __u32 nmsrs; | |
6615 | __u32 base; | |
6616 | __u32 bitmap; | |
6617 | }; | |
6618 | ||
6619 | struct kvm_msr_filter_compat { | |
6620 | __u32 flags; | |
6621 | struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES]; | |
6622 | }; | |
6623 | ||
6624 | #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat) | |
6625 | ||
6626 | long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl, | |
6627 | unsigned long arg) | |
6628 | { | |
6629 | void __user *argp = (void __user *)arg; | |
6630 | struct kvm *kvm = filp->private_data; | |
6631 | long r = -ENOTTY; | |
6632 | ||
6633 | switch (ioctl) { | |
6634 | case KVM_X86_SET_MSR_FILTER_COMPAT: { | |
6635 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
6636 | struct kvm_msr_filter_compat filter_compat; | |
6637 | struct kvm_msr_filter filter; | |
6638 | int i; | |
6639 | ||
6640 | if (copy_from_user(&filter_compat, user_msr_filter, | |
6641 | sizeof(filter_compat))) | |
6642 | return -EFAULT; | |
6643 | ||
6644 | filter.flags = filter_compat.flags; | |
6645 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { | |
6646 | struct kvm_msr_filter_range_compat *cr; | |
6647 | ||
6648 | cr = &filter_compat.ranges[i]; | |
6649 | filter.ranges[i] = (struct kvm_msr_filter_range) { | |
6650 | .flags = cr->flags, | |
6651 | .nmsrs = cr->nmsrs, | |
6652 | .base = cr->base, | |
6653 | .bitmap = (__u8 *)(ulong)cr->bitmap, | |
6654 | }; | |
6655 | } | |
6656 | ||
6657 | r = kvm_vm_ioctl_set_msr_filter(kvm, &filter); | |
6658 | break; | |
6659 | } | |
6660 | } | |
6661 | ||
6662 | return r; | |
6663 | } | |
6664 | #endif | |
6665 | ||
7d62874f SS |
6666 | #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER |
6667 | static int kvm_arch_suspend_notifier(struct kvm *kvm) | |
6668 | { | |
6669 | struct kvm_vcpu *vcpu; | |
46808a4c MZ |
6670 | unsigned long i; |
6671 | int ret = 0; | |
7d62874f SS |
6672 | |
6673 | mutex_lock(&kvm->lock); | |
6674 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
916d3608 | 6675 | if (!vcpu->arch.pv_time.active) |
7d62874f SS |
6676 | continue; |
6677 | ||
6678 | ret = kvm_set_guest_paused(vcpu); | |
6679 | if (ret) { | |
6680 | kvm_err("Failed to pause guest VCPU%d: %d\n", | |
6681 | vcpu->vcpu_id, ret); | |
6682 | break; | |
6683 | } | |
6684 | } | |
6685 | mutex_unlock(&kvm->lock); | |
6686 | ||
6687 | return ret ? NOTIFY_BAD : NOTIFY_DONE; | |
6688 | } | |
6689 | ||
6690 | int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) | |
6691 | { | |
6692 | switch (state) { | |
6693 | case PM_HIBERNATION_PREPARE: | |
6694 | case PM_SUSPEND_PREPARE: | |
6695 | return kvm_arch_suspend_notifier(kvm); | |
6696 | } | |
6697 | ||
6698 | return NOTIFY_DONE; | |
6699 | } | |
6700 | #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ | |
6701 | ||
45e6c2fa PB |
6702 | static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) |
6703 | { | |
869b4421 | 6704 | struct kvm_clock_data data = { 0 }; |
45e6c2fa | 6705 | |
55c0cefb | 6706 | get_kvmclock(kvm, &data); |
45e6c2fa PB |
6707 | if (copy_to_user(argp, &data, sizeof(data))) |
6708 | return -EFAULT; | |
6709 | ||
6710 | return 0; | |
6711 | } | |
6712 | ||
6713 | static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) | |
6714 | { | |
6715 | struct kvm_arch *ka = &kvm->arch; | |
6716 | struct kvm_clock_data data; | |
c68dc1b5 | 6717 | u64 now_raw_ns; |
45e6c2fa PB |
6718 | |
6719 | if (copy_from_user(&data, argp, sizeof(data))) | |
6720 | return -EFAULT; | |
6721 | ||
c68dc1b5 OU |
6722 | /* |
6723 | * Only KVM_CLOCK_REALTIME is used, but allow passing the | |
6724 | * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. | |
6725 | */ | |
6726 | if (data.flags & ~KVM_CLOCK_VALID_FLAGS) | |
45e6c2fa PB |
6727 | return -EINVAL; |
6728 | ||
42dcbe7d | 6729 | kvm_hv_request_tsc_page_update(kvm); |
45e6c2fa PB |
6730 | kvm_start_pvclock_update(kvm); |
6731 | pvclock_update_vm_gtod_copy(kvm); | |
6732 | ||
6733 | /* | |
6734 | * This pairs with kvm_guest_time_update(): when masterclock is | |
6735 | * in use, we use master_kernel_ns + kvmclock_offset to set | |
6736 | * unsigned 'system_time' so if we use get_kvmclock_ns() (which | |
6737 | * is slightly ahead) here we risk going negative on unsigned | |
6738 | * 'system_time' when 'data.clock' is very small. | |
6739 | */ | |
c68dc1b5 OU |
6740 | if (data.flags & KVM_CLOCK_REALTIME) { |
6741 | u64 now_real_ns = ktime_get_real_ns(); | |
6742 | ||
6743 | /* | |
6744 | * Avoid stepping the kvmclock backwards. | |
6745 | */ | |
6746 | if (now_real_ns > data.realtime) | |
6747 | data.clock += now_real_ns - data.realtime; | |
6748 | } | |
6749 | ||
6750 | if (ka->use_master_clock) | |
6751 | now_raw_ns = ka->master_kernel_ns; | |
45e6c2fa | 6752 | else |
c68dc1b5 OU |
6753 | now_raw_ns = get_kvmclock_base_ns(); |
6754 | ka->kvmclock_offset = data.clock - now_raw_ns; | |
45e6c2fa PB |
6755 | kvm_end_pvclock_update(kvm); |
6756 | return 0; | |
6757 | } | |
6758 | ||
d8708b80 | 6759 | int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) |
1fe779f8 CO |
6760 | { |
6761 | struct kvm *kvm = filp->private_data; | |
6762 | void __user *argp = (void __user *)arg; | |
367e1319 | 6763 | int r = -ENOTTY; |
f0d66275 DH |
6764 | /* |
6765 | * This union makes it completely explicit to gcc-3.x | |
6766 | * that these two variables' stack usage should be | |
6767 | * combined, not added together. | |
6768 | */ | |
6769 | union { | |
6770 | struct kvm_pit_state ps; | |
e9f42757 | 6771 | struct kvm_pit_state2 ps2; |
c5ff41ce | 6772 | struct kvm_pit_config pit_config; |
f0d66275 | 6773 | } u; |
1fe779f8 CO |
6774 | |
6775 | switch (ioctl) { | |
6776 | case KVM_SET_TSS_ADDR: | |
6777 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 6778 | break; |
b927a3ce SY |
6779 | case KVM_SET_IDENTITY_MAP_ADDR: { |
6780 | u64 ident_addr; | |
6781 | ||
1af1ac91 DH |
6782 | mutex_lock(&kvm->lock); |
6783 | r = -EINVAL; | |
6784 | if (kvm->created_vcpus) | |
6785 | goto set_identity_unlock; | |
b927a3ce | 6786 | r = -EFAULT; |
0e96f31e | 6787 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 6788 | goto set_identity_unlock; |
b927a3ce | 6789 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
6790 | set_identity_unlock: |
6791 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
6792 | break; |
6793 | } | |
1fe779f8 CO |
6794 | case KVM_SET_NR_MMU_PAGES: |
6795 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 | 6796 | break; |
3ddea128 | 6797 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 6798 | mutex_lock(&kvm->lock); |
09941366 | 6799 | |
3ddea128 | 6800 | r = -EEXIST; |
35e6eaa3 | 6801 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 6802 | goto create_irqchip_unlock; |
09941366 | 6803 | |
3e515705 | 6804 | r = -EINVAL; |
557abc40 | 6805 | if (kvm->created_vcpus) |
3e515705 | 6806 | goto create_irqchip_unlock; |
09941366 RK |
6807 | |
6808 | r = kvm_pic_init(kvm); | |
6809 | if (r) | |
3ddea128 | 6810 | goto create_irqchip_unlock; |
09941366 RK |
6811 | |
6812 | r = kvm_ioapic_init(kvm); | |
6813 | if (r) { | |
09941366 | 6814 | kvm_pic_destroy(kvm); |
3ddea128 | 6815 | goto create_irqchip_unlock; |
09941366 RK |
6816 | } |
6817 | ||
399ec807 AK |
6818 | r = kvm_setup_default_irq_routing(kvm); |
6819 | if (r) { | |
72bb2fcd | 6820 | kvm_ioapic_destroy(kvm); |
09941366 | 6821 | kvm_pic_destroy(kvm); |
71ba994c | 6822 | goto create_irqchip_unlock; |
399ec807 | 6823 | } |
49776faf | 6824 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 6825 | smp_wmb(); |
49776faf | 6826 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
320af55a | 6827 | kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); |
3ddea128 MT |
6828 | create_irqchip_unlock: |
6829 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 6830 | break; |
3ddea128 | 6831 | } |
7837699f | 6832 | case KVM_CREATE_PIT: |
c5ff41ce JK |
6833 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
6834 | goto create_pit; | |
6835 | case KVM_CREATE_PIT2: | |
6836 | r = -EFAULT; | |
6837 | if (copy_from_user(&u.pit_config, argp, | |
6838 | sizeof(struct kvm_pit_config))) | |
6839 | goto out; | |
6840 | create_pit: | |
250715a6 | 6841 | mutex_lock(&kvm->lock); |
269e05e4 AK |
6842 | r = -EEXIST; |
6843 | if (kvm->arch.vpit) | |
6844 | goto create_pit_unlock; | |
7837699f | 6845 | r = -ENOMEM; |
c5ff41ce | 6846 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
6847 | if (kvm->arch.vpit) |
6848 | r = 0; | |
269e05e4 | 6849 | create_pit_unlock: |
250715a6 | 6850 | mutex_unlock(&kvm->lock); |
7837699f | 6851 | break; |
1fe779f8 CO |
6852 | case KVM_GET_IRQCHIP: { |
6853 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 6854 | struct kvm_irqchip *chip; |
1fe779f8 | 6855 | |
ff5c2c03 SL |
6856 | chip = memdup_user(argp, sizeof(*chip)); |
6857 | if (IS_ERR(chip)) { | |
6858 | r = PTR_ERR(chip); | |
1fe779f8 | 6859 | goto out; |
ff5c2c03 SL |
6860 | } |
6861 | ||
1fe779f8 | 6862 | r = -ENXIO; |
826da321 | 6863 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
6864 | goto get_irqchip_out; |
6865 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 6866 | if (r) |
f0d66275 | 6867 | goto get_irqchip_out; |
1fe779f8 | 6868 | r = -EFAULT; |
0e96f31e | 6869 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 6870 | goto get_irqchip_out; |
1fe779f8 | 6871 | r = 0; |
f0d66275 DH |
6872 | get_irqchip_out: |
6873 | kfree(chip); | |
1fe779f8 CO |
6874 | break; |
6875 | } | |
6876 | case KVM_SET_IRQCHIP: { | |
6877 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 6878 | struct kvm_irqchip *chip; |
1fe779f8 | 6879 | |
ff5c2c03 SL |
6880 | chip = memdup_user(argp, sizeof(*chip)); |
6881 | if (IS_ERR(chip)) { | |
6882 | r = PTR_ERR(chip); | |
1fe779f8 | 6883 | goto out; |
ff5c2c03 SL |
6884 | } |
6885 | ||
1fe779f8 | 6886 | r = -ENXIO; |
826da321 | 6887 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
6888 | goto set_irqchip_out; |
6889 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
6890 | set_irqchip_out: |
6891 | kfree(chip); | |
1fe779f8 CO |
6892 | break; |
6893 | } | |
e0f63cb9 | 6894 | case KVM_GET_PIT: { |
e0f63cb9 | 6895 | r = -EFAULT; |
f0d66275 | 6896 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
6897 | goto out; |
6898 | r = -ENXIO; | |
6899 | if (!kvm->arch.vpit) | |
6900 | goto out; | |
f0d66275 | 6901 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
6902 | if (r) |
6903 | goto out; | |
6904 | r = -EFAULT; | |
f0d66275 | 6905 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
6906 | goto out; |
6907 | r = 0; | |
6908 | break; | |
6909 | } | |
6910 | case KVM_SET_PIT: { | |
e0f63cb9 | 6911 | r = -EFAULT; |
0e96f31e | 6912 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 6913 | goto out; |
7289fdb5 | 6914 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
6915 | r = -ENXIO; |
6916 | if (!kvm->arch.vpit) | |
7289fdb5 | 6917 | goto set_pit_out; |
f0d66275 | 6918 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
6919 | set_pit_out: |
6920 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
6921 | break; |
6922 | } | |
e9f42757 BK |
6923 | case KVM_GET_PIT2: { |
6924 | r = -ENXIO; | |
6925 | if (!kvm->arch.vpit) | |
6926 | goto out; | |
6927 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
6928 | if (r) | |
6929 | goto out; | |
6930 | r = -EFAULT; | |
6931 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
6932 | goto out; | |
6933 | r = 0; | |
6934 | break; | |
6935 | } | |
6936 | case KVM_SET_PIT2: { | |
6937 | r = -EFAULT; | |
6938 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
6939 | goto out; | |
7289fdb5 | 6940 | mutex_lock(&kvm->lock); |
e9f42757 BK |
6941 | r = -ENXIO; |
6942 | if (!kvm->arch.vpit) | |
7289fdb5 | 6943 | goto set_pit2_out; |
e9f42757 | 6944 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
6945 | set_pit2_out: |
6946 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
6947 | break; |
6948 | } | |
52d939a0 MT |
6949 | case KVM_REINJECT_CONTROL: { |
6950 | struct kvm_reinject_control control; | |
6951 | r = -EFAULT; | |
6952 | if (copy_from_user(&control, argp, sizeof(control))) | |
6953 | goto out; | |
cad23e72 ML |
6954 | r = -ENXIO; |
6955 | if (!kvm->arch.vpit) | |
6956 | goto out; | |
52d939a0 | 6957 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
6958 | break; |
6959 | } | |
d71ba788 PB |
6960 | case KVM_SET_BOOT_CPU_ID: |
6961 | r = 0; | |
6962 | mutex_lock(&kvm->lock); | |
557abc40 | 6963 | if (kvm->created_vcpus) |
d71ba788 PB |
6964 | r = -EBUSY; |
6965 | else | |
6966 | kvm->arch.bsp_vcpu_id = arg; | |
6967 | mutex_unlock(&kvm->lock); | |
6968 | break; | |
b59b153d | 6969 | #ifdef CONFIG_KVM_XEN |
ffde22ac | 6970 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 6971 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 6972 | r = -EFAULT; |
51776043 | 6973 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac | 6974 | goto out; |
78e9878c | 6975 | r = kvm_xen_hvm_config(kvm, &xhc); |
ffde22ac ES |
6976 | break; |
6977 | } | |
a76b9641 JM |
6978 | case KVM_XEN_HVM_GET_ATTR: { |
6979 | struct kvm_xen_hvm_attr xha; | |
6980 | ||
6981 | r = -EFAULT; | |
6982 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
ffde22ac | 6983 | goto out; |
a76b9641 JM |
6984 | r = kvm_xen_hvm_get_attr(kvm, &xha); |
6985 | if (!r && copy_to_user(argp, &xha, sizeof(xha))) | |
6986 | r = -EFAULT; | |
6987 | break; | |
6988 | } | |
6989 | case KVM_XEN_HVM_SET_ATTR: { | |
6990 | struct kvm_xen_hvm_attr xha; | |
6991 | ||
6992 | r = -EFAULT; | |
6993 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
6994 | goto out; | |
6995 | r = kvm_xen_hvm_set_attr(kvm, &xha); | |
ffde22ac ES |
6996 | break; |
6997 | } | |
35025735 DW |
6998 | case KVM_XEN_HVM_EVTCHN_SEND: { |
6999 | struct kvm_irq_routing_xen_evtchn uxe; | |
7000 | ||
7001 | r = -EFAULT; | |
7002 | if (copy_from_user(&uxe, argp, sizeof(uxe))) | |
7003 | goto out; | |
7004 | r = kvm_xen_hvm_evtchn_send(kvm, &uxe); | |
7005 | break; | |
7006 | } | |
b59b153d | 7007 | #endif |
45e6c2fa PB |
7008 | case KVM_SET_CLOCK: |
7009 | r = kvm_vm_ioctl_set_clock(kvm, argp); | |
afbcf7ab | 7010 | break; |
45e6c2fa PB |
7011 | case KVM_GET_CLOCK: |
7012 | r = kvm_vm_ioctl_get_clock(kvm, argp); | |
afbcf7ab | 7013 | break; |
ffbb61d0 DW |
7014 | case KVM_SET_TSC_KHZ: { |
7015 | u32 user_tsc_khz; | |
7016 | ||
7017 | r = -EINVAL; | |
7018 | user_tsc_khz = (u32)arg; | |
7019 | ||
938c8745 SC |
7020 | if (kvm_caps.has_tsc_control && |
7021 | user_tsc_khz >= kvm_caps.max_guest_tsc_khz) | |
ffbb61d0 DW |
7022 | goto out; |
7023 | ||
7024 | if (user_tsc_khz == 0) | |
7025 | user_tsc_khz = tsc_khz; | |
7026 | ||
7027 | WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz); | |
7028 | r = 0; | |
7029 | ||
7030 | goto out; | |
7031 | } | |
7032 | case KVM_GET_TSC_KHZ: { | |
7033 | r = READ_ONCE(kvm->arch.default_tsc_khz); | |
7034 | goto out; | |
7035 | } | |
5acc5c06 BS |
7036 | case KVM_MEMORY_ENCRYPT_OP: { |
7037 | r = -ENOTTY; | |
03d004cd SC |
7038 | if (!kvm_x86_ops.mem_enc_ioctl) |
7039 | goto out; | |
7040 | ||
7041 | r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp); | |
5acc5c06 BS |
7042 | break; |
7043 | } | |
69eaedee BS |
7044 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
7045 | struct kvm_enc_region region; | |
7046 | ||
7047 | r = -EFAULT; | |
7048 | if (copy_from_user(®ion, argp, sizeof(region))) | |
7049 | goto out; | |
7050 | ||
7051 | r = -ENOTTY; | |
03d004cd SC |
7052 | if (!kvm_x86_ops.mem_enc_register_region) |
7053 | goto out; | |
7054 | ||
7055 | r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion); | |
69eaedee BS |
7056 | break; |
7057 | } | |
7058 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
7059 | struct kvm_enc_region region; | |
7060 | ||
7061 | r = -EFAULT; | |
7062 | if (copy_from_user(®ion, argp, sizeof(region))) | |
7063 | goto out; | |
7064 | ||
7065 | r = -ENOTTY; | |
03d004cd SC |
7066 | if (!kvm_x86_ops.mem_enc_unregister_region) |
7067 | goto out; | |
7068 | ||
7069 | r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion); | |
69eaedee BS |
7070 | break; |
7071 | } | |
faeb7833 RK |
7072 | case KVM_HYPERV_EVENTFD: { |
7073 | struct kvm_hyperv_eventfd hvevfd; | |
7074 | ||
7075 | r = -EFAULT; | |
7076 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
7077 | goto out; | |
7078 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
7079 | break; | |
7080 | } | |
66bb8a06 EH |
7081 | case KVM_SET_PMU_EVENT_FILTER: |
7082 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
7083 | break; | |
2e3272bc AG |
7084 | case KVM_X86_SET_MSR_FILTER: { |
7085 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
7086 | struct kvm_msr_filter filter; | |
7087 | ||
7088 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
7089 | return -EFAULT; | |
7090 | ||
7091 | r = kvm_vm_ioctl_set_msr_filter(kvm, &filter); | |
1a155254 | 7092 | break; |
2e3272bc | 7093 | } |
1fe779f8 | 7094 | default: |
ad6260da | 7095 | r = -ENOTTY; |
1fe779f8 CO |
7096 | } |
7097 | out: | |
7098 | return r; | |
7099 | } | |
7100 | ||
9eb6ba31 SC |
7101 | static void kvm_probe_feature_msr(u32 msr_index) |
7102 | { | |
7103 | struct kvm_msr_entry msr = { | |
7104 | .index = msr_index, | |
7105 | }; | |
7106 | ||
7107 | if (kvm_get_msr_feature(&msr)) | |
7108 | return; | |
7109 | ||
7110 | msr_based_features[num_msr_based_features++] = msr_index; | |
7111 | } | |
7112 | ||
2374b731 | 7113 | static void kvm_probe_msr_to_save(u32 msr_index) |
043405e1 CO |
7114 | { |
7115 | u32 dummy[2]; | |
2374b731 SC |
7116 | |
7117 | if (rdmsr_safe(msr_index, &dummy[0], &dummy[1])) | |
7118 | return; | |
7119 | ||
7120 | /* | |
7121 | * Even MSRs that are valid in the host may not be exposed to guests in | |
7122 | * some cases. | |
7123 | */ | |
7124 | switch (msr_index) { | |
7125 | case MSR_IA32_BNDCFGS: | |
7126 | if (!kvm_mpx_supported()) | |
7127 | return; | |
7128 | break; | |
7129 | case MSR_TSC_AUX: | |
7130 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && | |
7131 | !kvm_cpu_cap_has(X86_FEATURE_RDPID)) | |
7132 | return; | |
7133 | break; | |
7134 | case MSR_IA32_UMWAIT_CONTROL: | |
7135 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
7136 | return; | |
7137 | break; | |
7138 | case MSR_IA32_RTIT_CTL: | |
7139 | case MSR_IA32_RTIT_STATUS: | |
7140 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) | |
7141 | return; | |
7142 | break; | |
7143 | case MSR_IA32_RTIT_CR3_MATCH: | |
7144 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || | |
7145 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) | |
7146 | return; | |
7147 | break; | |
7148 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
7149 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7150 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || | |
7151 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && | |
7152 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
7153 | return; | |
7154 | break; | |
7155 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: | |
7156 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || | |
7157 | (msr_index - MSR_IA32_RTIT_ADDR0_A >= | |
7158 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)) | |
7159 | return; | |
7160 | break; | |
7161 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX: | |
7162 | if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >= | |
7163 | kvm_pmu_cap.num_counters_gp) | |
7164 | return; | |
7165 | break; | |
7166 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX: | |
7167 | if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >= | |
7168 | kvm_pmu_cap.num_counters_gp) | |
7169 | return; | |
7170 | break; | |
e33b6d79 LX |
7171 | case MSR_ARCH_PERFMON_FIXED_CTR0 ... MSR_ARCH_PERFMON_FIXED_CTR_MAX: |
7172 | if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >= | |
7173 | kvm_pmu_cap.num_counters_fixed) | |
7174 | return; | |
7175 | break; | |
4a277189 LX |
7176 | case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: |
7177 | case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: | |
7178 | case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: | |
7179 | if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) | |
7180 | return; | |
7181 | break; | |
2374b731 SC |
7182 | case MSR_IA32_XFD: |
7183 | case MSR_IA32_XFD_ERR: | |
7184 | if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) | |
7185 | return; | |
7186 | break; | |
b9846a69 MZ |
7187 | case MSR_IA32_TSX_CTRL: |
7188 | if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR)) | |
7189 | return; | |
7190 | break; | |
2374b731 SC |
7191 | default: |
7192 | break; | |
7193 | } | |
7194 | ||
7195 | msrs_to_save[num_msrs_to_save++] = msr_index; | |
7196 | } | |
7197 | ||
b1932c5c | 7198 | static void kvm_init_msr_lists(void) |
2374b731 | 7199 | { |
7a5ee6ed | 7200 | unsigned i; |
043405e1 | 7201 | |
0144ba0c | 7202 | BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3, |
2374b731 | 7203 | "Please update the fixed PMCs in msrs_to_save_pmu[]"); |
24c29b7a | 7204 | |
6cbee2b9 XL |
7205 | num_msrs_to_save = 0; |
7206 | num_emulated_msrs = 0; | |
7207 | num_msr_based_features = 0; | |
7208 | ||
2374b731 SC |
7209 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_base); i++) |
7210 | kvm_probe_msr_to_save(msrs_to_save_base[i]); | |
93c4adc7 | 7211 | |
c3531edc SC |
7212 | if (enable_pmu) { |
7213 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_pmu); i++) | |
7214 | kvm_probe_msr_to_save(msrs_to_save_pmu[i]); | |
043405e1 | 7215 | } |
62ef68bb | 7216 | |
7a5ee6ed | 7217 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
b3646477 | 7218 | if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) |
bc226f07 | 7219 | continue; |
62ef68bb | 7220 | |
7a5ee6ed | 7221 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 7222 | } |
801e459a | 7223 | |
9eb6ba31 SC |
7224 | for (i = KVM_FIRST_EMULATED_VMX_MSR; i <= KVM_LAST_EMULATED_VMX_MSR; i++) |
7225 | kvm_probe_feature_msr(i); | |
801e459a | 7226 | |
9eb6ba31 SC |
7227 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) |
7228 | kvm_probe_feature_msr(msr_based_features_all_except_vmx[i]); | |
043405e1 CO |
7229 | } |
7230 | ||
bda9020e MT |
7231 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
7232 | const void *v) | |
bbd9b64e | 7233 | { |
70252a10 AK |
7234 | int handled = 0; |
7235 | int n; | |
7236 | ||
7237 | do { | |
7238 | n = min(len, 8); | |
bce87cce | 7239 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
7240 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
7241 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
7242 | break; |
7243 | handled += n; | |
7244 | addr += n; | |
7245 | len -= n; | |
7246 | v += n; | |
7247 | } while (len); | |
bbd9b64e | 7248 | |
70252a10 | 7249 | return handled; |
bbd9b64e CO |
7250 | } |
7251 | ||
bda9020e | 7252 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 7253 | { |
70252a10 AK |
7254 | int handled = 0; |
7255 | int n; | |
7256 | ||
7257 | do { | |
7258 | n = min(len, 8); | |
bce87cce | 7259 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
7260 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
7261 | addr, n, v)) | |
7262 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 7263 | break; |
e39d200f | 7264 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
7265 | handled += n; |
7266 | addr += n; | |
7267 | len -= n; | |
7268 | v += n; | |
7269 | } while (len); | |
bbd9b64e | 7270 | |
70252a10 | 7271 | return handled; |
bbd9b64e CO |
7272 | } |
7273 | ||
c53da4f3 PB |
7274 | void kvm_set_segment(struct kvm_vcpu *vcpu, |
7275 | struct kvm_segment *var, int seg) | |
2dafc6c2 | 7276 | { |
b3646477 | 7277 | static_call(kvm_x86_set_segment)(vcpu, var, seg); |
2dafc6c2 GN |
7278 | } |
7279 | ||
7280 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
7281 | struct kvm_segment *var, int seg) | |
7282 | { | |
b3646477 | 7283 | static_call(kvm_x86_get_segment)(vcpu, var, seg); |
2dafc6c2 GN |
7284 | } |
7285 | ||
5b22bbe7 | 7286 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access, |
54987b7a | 7287 | struct x86_exception *exception) |
02f59dc9 | 7288 | { |
1f5a21ee | 7289 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
02f59dc9 | 7290 | gpa_t t_gpa; |
02f59dc9 JR |
7291 | |
7292 | BUG_ON(!mmu_is_nested(vcpu)); | |
7293 | ||
7294 | /* NPT walks are always user-walks */ | |
7295 | access |= PFERR_USER_MASK; | |
1f5a21ee | 7296 | t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception); |
02f59dc9 JR |
7297 | |
7298 | return t_gpa; | |
7299 | } | |
7300 | ||
ab9ae313 AK |
7301 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
7302 | struct x86_exception *exception) | |
1871c602 | 7303 | { |
1f5a21ee LJ |
7304 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
7305 | ||
5b22bbe7 | 7306 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1f5a21ee | 7307 | return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); |
1871c602 | 7308 | } |
54f958cd | 7309 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); |
1871c602 | 7310 | |
ab9ae313 AK |
7311 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
7312 | struct x86_exception *exception) | |
1871c602 | 7313 | { |
1f5a21ee LJ |
7314 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
7315 | ||
5b22bbe7 | 7316 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 7317 | access |= PFERR_WRITE_MASK; |
1f5a21ee | 7318 | return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); |
1871c602 | 7319 | } |
54f958cd | 7320 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); |
1871c602 GN |
7321 | |
7322 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
7323 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
7324 | struct x86_exception *exception) | |
1871c602 | 7325 | { |
1f5a21ee LJ |
7326 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
7327 | ||
7328 | return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception); | |
1871c602 GN |
7329 | } |
7330 | ||
7331 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
5b22bbe7 | 7332 | struct kvm_vcpu *vcpu, u64 access, |
bcc55cba | 7333 | struct x86_exception *exception) |
bbd9b64e | 7334 | { |
1f5a21ee | 7335 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
bbd9b64e | 7336 | void *data = val; |
10589a46 | 7337 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
7338 | |
7339 | while (bytes) { | |
1f5a21ee | 7340 | gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); |
bbd9b64e | 7341 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 7342 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
7343 | int ret; |
7344 | ||
6e1d2a3f | 7345 | if (gpa == INVALID_GPA) |
ab9ae313 | 7346 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
7347 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
7348 | offset, toread); | |
10589a46 | 7349 | if (ret < 0) { |
c3cd7ffa | 7350 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
7351 | goto out; |
7352 | } | |
bbd9b64e | 7353 | |
77c2002e IE |
7354 | bytes -= toread; |
7355 | data += toread; | |
7356 | addr += toread; | |
bbd9b64e | 7357 | } |
10589a46 | 7358 | out: |
10589a46 | 7359 | return r; |
bbd9b64e | 7360 | } |
77c2002e | 7361 | |
1871c602 | 7362 | /* used for instruction fetching */ |
0f65dd70 AK |
7363 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
7364 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 7365 | struct x86_exception *exception) |
1871c602 | 7366 | { |
0f65dd70 | 7367 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1f5a21ee | 7368 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
5b22bbe7 | 7369 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
7370 | unsigned offset; |
7371 | int ret; | |
0f65dd70 | 7372 | |
44583cba | 7373 | /* Inline kvm_read_guest_virt_helper for speed. */ |
1f5a21ee LJ |
7374 | gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK, |
7375 | exception); | |
6e1d2a3f | 7376 | if (unlikely(gpa == INVALID_GPA)) |
44583cba PB |
7377 | return X86EMUL_PROPAGATE_FAULT; |
7378 | ||
7379 | offset = addr & (PAGE_SIZE-1); | |
7380 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
7381 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
7382 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
7383 | offset, bytes); | |
44583cba PB |
7384 | if (unlikely(ret < 0)) |
7385 | return X86EMUL_IO_NEEDED; | |
7386 | ||
7387 | return X86EMUL_CONTINUE; | |
1871c602 GN |
7388 | } |
7389 | ||
ce14e868 | 7390 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 7391 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 7392 | struct x86_exception *exception) |
1871c602 | 7393 | { |
5b22bbe7 | 7394 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 7395 | |
353c0956 PB |
7396 | /* |
7397 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
7398 | * is returned, but our callers are not ready for that and they blindly | |
7399 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
7400 | * uninitialized kernel stack memory into cr2 and error code. | |
7401 | */ | |
7402 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 7403 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 7404 | exception); |
1871c602 | 7405 | } |
064aea77 | 7406 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 7407 | |
ce14e868 PB |
7408 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
7409 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 7410 | struct x86_exception *exception, bool system) |
1871c602 | 7411 | { |
0f65dd70 | 7412 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
5b22bbe7 | 7413 | u64 access = 0; |
3c9fa24c | 7414 | |
4f4aa80e LJ |
7415 | if (system) |
7416 | access |= PFERR_IMPLICIT_ACCESS; | |
7417 | else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) | |
3c9fa24c PB |
7418 | access |= PFERR_USER_MASK; |
7419 | ||
7420 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
7421 | } |
7422 | ||
ce14e868 | 7423 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
5b22bbe7 | 7424 | struct kvm_vcpu *vcpu, u64 access, |
ce14e868 | 7425 | struct x86_exception *exception) |
77c2002e | 7426 | { |
1f5a21ee | 7427 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
77c2002e IE |
7428 | void *data = val; |
7429 | int r = X86EMUL_CONTINUE; | |
7430 | ||
7431 | while (bytes) { | |
1f5a21ee | 7432 | gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); |
77c2002e IE |
7433 | unsigned offset = addr & (PAGE_SIZE-1); |
7434 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
7435 | int ret; | |
7436 | ||
6e1d2a3f | 7437 | if (gpa == INVALID_GPA) |
ab9ae313 | 7438 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 7439 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 7440 | if (ret < 0) { |
c3cd7ffa | 7441 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
7442 | goto out; |
7443 | } | |
7444 | ||
7445 | bytes -= towrite; | |
7446 | data += towrite; | |
7447 | addr += towrite; | |
7448 | } | |
7449 | out: | |
7450 | return r; | |
7451 | } | |
ce14e868 PB |
7452 | |
7453 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
7454 | unsigned int bytes, struct x86_exception *exception, |
7455 | bool system) | |
ce14e868 PB |
7456 | { |
7457 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5b22bbe7 | 7458 | u64 access = PFERR_WRITE_MASK; |
3c9fa24c | 7459 | |
4f4aa80e LJ |
7460 | if (system) |
7461 | access |= PFERR_IMPLICIT_ACCESS; | |
7462 | else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) | |
3c9fa24c | 7463 | access |= PFERR_USER_MASK; |
ce14e868 PB |
7464 | |
7465 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 7466 | access, exception); |
ce14e868 PB |
7467 | } |
7468 | ||
7469 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
7470 | unsigned int bytes, struct x86_exception *exception) | |
7471 | { | |
c595ceee PB |
7472 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
7473 | vcpu->arch.l1tf_flush_l1d = true; | |
7474 | ||
ce14e868 PB |
7475 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
7476 | PFERR_WRITE_MASK, exception); | |
7477 | } | |
6a4d7550 | 7478 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 7479 | |
4d31d9ef SC |
7480 | static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type, |
7481 | void *insn, int insn_len) | |
7482 | { | |
7483 | return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type, | |
7484 | insn, insn_len); | |
7485 | } | |
7486 | ||
082d06ed WL |
7487 | int handle_ud(struct kvm_vcpu *vcpu) |
7488 | { | |
b3dc0695 | 7489 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
40aaa5b6 | 7490 | int fep_flags = READ_ONCE(force_emulation_prefix); |
6c86eedc | 7491 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
7492 | char sig[5]; /* ud2; .ascii "kvm" */ |
7493 | struct x86_exception e; | |
7494 | ||
4d31d9ef | 7495 | if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0))) |
09e3e2a1 SC |
7496 | return 1; |
7497 | ||
40aaa5b6 | 7498 | if (fep_flags && |
3c9fa24c PB |
7499 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
7500 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 7501 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
40aaa5b6 | 7502 | if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF) |
d500e1ed | 7503 | kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF); |
6c86eedc | 7504 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 7505 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 7506 | } |
082d06ed | 7507 | |
60fc3d02 | 7508 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
7509 | } |
7510 | EXPORT_SYMBOL_GPL(handle_ud); | |
7511 | ||
0f89b207 TL |
7512 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
7513 | gpa_t gpa, bool write) | |
7514 | { | |
7515 | /* For APIC access vmexit */ | |
7516 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
7517 | return 1; | |
7518 | ||
7519 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
7520 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
7521 | return 1; | |
7522 | } | |
7523 | ||
7524 | return 0; | |
7525 | } | |
7526 | ||
af7cc7d1 XG |
7527 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
7528 | gpa_t *gpa, struct x86_exception *exception, | |
7529 | bool write) | |
7530 | { | |
1f5a21ee | 7531 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
5b22bbe7 | 7532 | u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 7533 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 7534 | |
be94f6b7 HH |
7535 | /* |
7536 | * currently PKRU is only applied to ept enabled guest so | |
7537 | * there is no pkey in EPT page table for L1 guest or EPT | |
7538 | * shadow page table for L2 guest. | |
7539 | */ | |
908b7d43 SC |
7540 | if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || |
7541 | !permission_fault(vcpu, vcpu->arch.walk_mmu, | |
7542 | vcpu->arch.mmio_access, 0, access))) { | |
bebb106a XG |
7543 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
7544 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 7545 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
7546 | return 1; |
7547 | } | |
7548 | ||
1f5a21ee | 7549 | *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); |
af7cc7d1 | 7550 | |
6e1d2a3f | 7551 | if (*gpa == INVALID_GPA) |
af7cc7d1 XG |
7552 | return -1; |
7553 | ||
0f89b207 | 7554 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
7555 | } |
7556 | ||
3200f405 | 7557 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 7558 | const void *val, int bytes) |
bbd9b64e CO |
7559 | { |
7560 | int ret; | |
7561 | ||
54bf36aa | 7562 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 7563 | if (ret < 0) |
bbd9b64e | 7564 | return 0; |
0eb05bf2 | 7565 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
7566 | return 1; |
7567 | } | |
7568 | ||
77d197b2 XG |
7569 | struct read_write_emulator_ops { |
7570 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
7571 | int bytes); | |
7572 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7573 | void *val, int bytes); | |
7574 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7575 | int bytes, void *val); | |
7576 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7577 | void *val, int bytes); | |
7578 | bool write; | |
7579 | }; | |
7580 | ||
7581 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
7582 | { | |
7583 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 7584 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 7585 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
7586 | vcpu->mmio_read_completed = 0; |
7587 | return 1; | |
7588 | } | |
7589 | ||
7590 | return 0; | |
7591 | } | |
7592 | ||
7593 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7594 | void *val, int bytes) | |
7595 | { | |
54bf36aa | 7596 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
7597 | } |
7598 | ||
7599 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7600 | void *val, int bytes) | |
7601 | { | |
7602 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
7603 | } | |
7604 | ||
7605 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
7606 | { | |
e39d200f | 7607 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
7608 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
7609 | } | |
7610 | ||
7611 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7612 | void *val, int bytes) | |
7613 | { | |
e39d200f | 7614 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
7615 | return X86EMUL_IO_NEEDED; |
7616 | } | |
7617 | ||
7618 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7619 | void *val, int bytes) | |
7620 | { | |
f78146b0 AK |
7621 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
7622 | ||
87da7e66 | 7623 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
7624 | return X86EMUL_CONTINUE; |
7625 | } | |
7626 | ||
0fbe9b0b | 7627 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
7628 | .read_write_prepare = read_prepare, |
7629 | .read_write_emulate = read_emulate, | |
7630 | .read_write_mmio = vcpu_mmio_read, | |
7631 | .read_write_exit_mmio = read_exit_mmio, | |
7632 | }; | |
7633 | ||
0fbe9b0b | 7634 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
7635 | .read_write_emulate = write_emulate, |
7636 | .read_write_mmio = write_mmio, | |
7637 | .read_write_exit_mmio = write_exit_mmio, | |
7638 | .write = true, | |
7639 | }; | |
7640 | ||
22388a3c XG |
7641 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
7642 | unsigned int bytes, | |
7643 | struct x86_exception *exception, | |
7644 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 7645 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 7646 | { |
af7cc7d1 XG |
7647 | gpa_t gpa; |
7648 | int handled, ret; | |
22388a3c | 7649 | bool write = ops->write; |
f78146b0 | 7650 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 7651 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
7652 | |
7653 | /* | |
7654 | * If the exit was due to a NPF we may already have a GPA. | |
7655 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
7656 | * Note, this cannot be used on string operations since string | |
7657 | * operation using rep will only have the initial GPA from the NPF | |
7658 | * occurred. | |
7659 | */ | |
744e699c SC |
7660 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
7661 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
7662 | gpa = ctxt->gpa_val; | |
618232e2 BS |
7663 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
7664 | } else { | |
7665 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
7666 | if (ret < 0) | |
7667 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 7668 | } |
10589a46 | 7669 | |
618232e2 | 7670 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
7671 | return X86EMUL_CONTINUE; |
7672 | ||
bbd9b64e CO |
7673 | /* |
7674 | * Is this MMIO handled locally? | |
7675 | */ | |
22388a3c | 7676 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 7677 | if (handled == bytes) |
bbd9b64e | 7678 | return X86EMUL_CONTINUE; |
bbd9b64e | 7679 | |
70252a10 AK |
7680 | gpa += handled; |
7681 | bytes -= handled; | |
7682 | val += handled; | |
7683 | ||
87da7e66 XG |
7684 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
7685 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
7686 | frag->gpa = gpa; | |
7687 | frag->data = val; | |
7688 | frag->len = bytes; | |
f78146b0 | 7689 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
7690 | } |
7691 | ||
52eb5a6d XL |
7692 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
7693 | unsigned long addr, | |
22388a3c XG |
7694 | void *val, unsigned int bytes, |
7695 | struct x86_exception *exception, | |
0fbe9b0b | 7696 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 7697 | { |
0f65dd70 | 7698 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
7699 | gpa_t gpa; |
7700 | int rc; | |
7701 | ||
7702 | if (ops->read_write_prepare && | |
7703 | ops->read_write_prepare(vcpu, val, bytes)) | |
7704 | return X86EMUL_CONTINUE; | |
7705 | ||
7706 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 7707 | |
bbd9b64e CO |
7708 | /* Crossing a page boundary? */ |
7709 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 7710 | int now; |
bbd9b64e CO |
7711 | |
7712 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
7713 | rc = emulator_read_write_onepage(addr, val, now, exception, |
7714 | vcpu, ops); | |
7715 | ||
bbd9b64e CO |
7716 | if (rc != X86EMUL_CONTINUE) |
7717 | return rc; | |
7718 | addr += now; | |
bac15531 NA |
7719 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
7720 | addr = (u32)addr; | |
bbd9b64e CO |
7721 | val += now; |
7722 | bytes -= now; | |
7723 | } | |
22388a3c | 7724 | |
f78146b0 AK |
7725 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
7726 | vcpu, ops); | |
7727 | if (rc != X86EMUL_CONTINUE) | |
7728 | return rc; | |
7729 | ||
7730 | if (!vcpu->mmio_nr_fragments) | |
7731 | return rc; | |
7732 | ||
7733 | gpa = vcpu->mmio_fragments[0].gpa; | |
7734 | ||
7735 | vcpu->mmio_needed = 1; | |
7736 | vcpu->mmio_cur_fragment = 0; | |
7737 | ||
87da7e66 | 7738 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
7739 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
7740 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
7741 | vcpu->run->mmio.phys_addr = gpa; | |
7742 | ||
7743 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
7744 | } |
7745 | ||
7746 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
7747 | unsigned long addr, | |
7748 | void *val, | |
7749 | unsigned int bytes, | |
7750 | struct x86_exception *exception) | |
7751 | { | |
7752 | return emulator_read_write(ctxt, addr, val, bytes, | |
7753 | exception, &read_emultor); | |
7754 | } | |
7755 | ||
52eb5a6d | 7756 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
7757 | unsigned long addr, |
7758 | const void *val, | |
7759 | unsigned int bytes, | |
7760 | struct x86_exception *exception) | |
7761 | { | |
7762 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
7763 | exception, &write_emultor); | |
bbd9b64e | 7764 | } |
bbd9b64e | 7765 | |
1c2361f6 SC |
7766 | #define emulator_try_cmpxchg_user(t, ptr, old, new) \ |
7767 | (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t)) | |
daea3e73 | 7768 | |
0f65dd70 AK |
7769 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
7770 | unsigned long addr, | |
bbd9b64e CO |
7771 | const void *old, |
7772 | const void *new, | |
7773 | unsigned int bytes, | |
0f65dd70 | 7774 | struct x86_exception *exception) |
bbd9b64e | 7775 | { |
0f65dd70 | 7776 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 7777 | u64 page_line_mask; |
1c2361f6 | 7778 | unsigned long hva; |
daea3e73 | 7779 | gpa_t gpa; |
1c2361f6 | 7780 | int r; |
2bacc55c | 7781 | |
daea3e73 AK |
7782 | /* guests cmpxchg8b have to be emulated atomically */ |
7783 | if (bytes > 8 || (bytes & (bytes - 1))) | |
7784 | goto emul_write; | |
10589a46 | 7785 | |
daea3e73 | 7786 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 7787 | |
6e1d2a3f | 7788 | if (gpa == INVALID_GPA || |
daea3e73 AK |
7789 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) |
7790 | goto emul_write; | |
2bacc55c | 7791 | |
9de6fe3c XL |
7792 | /* |
7793 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
7794 | * enabled in the host and the access splits a cache line. | |
7795 | */ | |
7796 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
7797 | page_line_mask = ~(cache_line_size() - 1); | |
7798 | else | |
7799 | page_line_mask = PAGE_MASK; | |
7800 | ||
7801 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 7802 | goto emul_write; |
72dc67a6 | 7803 | |
1c2361f6 | 7804 | hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa)); |
33fbe6be | 7805 | if (kvm_is_error_hva(hva)) |
c19b8bd6 | 7806 | goto emul_write; |
72dc67a6 | 7807 | |
1c2361f6 | 7808 | hva += offset_in_page(gpa); |
42e35f80 | 7809 | |
daea3e73 AK |
7810 | switch (bytes) { |
7811 | case 1: | |
1c2361f6 | 7812 | r = emulator_try_cmpxchg_user(u8, hva, old, new); |
daea3e73 AK |
7813 | break; |
7814 | case 2: | |
1c2361f6 | 7815 | r = emulator_try_cmpxchg_user(u16, hva, old, new); |
daea3e73 AK |
7816 | break; |
7817 | case 4: | |
1c2361f6 | 7818 | r = emulator_try_cmpxchg_user(u32, hva, old, new); |
daea3e73 AK |
7819 | break; |
7820 | case 8: | |
1c2361f6 | 7821 | r = emulator_try_cmpxchg_user(u64, hva, old, new); |
daea3e73 AK |
7822 | break; |
7823 | default: | |
7824 | BUG(); | |
2bacc55c | 7825 | } |
42e35f80 | 7826 | |
1c2361f6 | 7827 | if (r < 0) |
5d6c7de6 | 7828 | return X86EMUL_UNHANDLEABLE; |
1c2361f6 | 7829 | if (r) |
daea3e73 AK |
7830 | return X86EMUL_CMPXCHG_FAILED; |
7831 | ||
0eb05bf2 | 7832 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
7833 | |
7834 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 7835 | |
3200f405 | 7836 | emul_write: |
8d20bd63 | 7837 | pr_warn_once("emulating exchange as write\n"); |
2bacc55c | 7838 | |
0f65dd70 | 7839 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
7840 | } |
7841 | ||
6f6fbe98 | 7842 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
30d583fd | 7843 | unsigned short port, void *data, |
6f6fbe98 | 7844 | unsigned int count, bool in) |
cf8f70bf | 7845 | { |
0f87ac23 PB |
7846 | unsigned i; |
7847 | int r; | |
cf8f70bf | 7848 | |
30d583fd | 7849 | WARN_ON_ONCE(vcpu->arch.pio.count); |
0f87ac23 PB |
7850 | for (i = 0; i < count; i++) { |
7851 | if (in) | |
7852 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data); | |
cbfc6c91 | 7853 | else |
0f87ac23 | 7854 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data); |
35ab3b77 PB |
7855 | |
7856 | if (r) { | |
7857 | if (i == 0) | |
7858 | goto userspace_io; | |
7859 | ||
7860 | /* | |
7861 | * Userspace must have unregistered the device while PIO | |
0c05e10b | 7862 | * was running. Drop writes / read as 0. |
35ab3b77 | 7863 | */ |
0c05e10b PB |
7864 | if (in) |
7865 | memset(data, 0, size * (count - i)); | |
cbfc6c91 | 7866 | break; |
35ab3b77 PB |
7867 | } |
7868 | ||
0f87ac23 | 7869 | data += size; |
cbfc6c91 | 7870 | } |
0f87ac23 | 7871 | return 1; |
cf8f70bf | 7872 | |
0f87ac23 | 7873 | userspace_io: |
cf8f70bf | 7874 | vcpu->arch.pio.port = port; |
6f6fbe98 | 7875 | vcpu->arch.pio.in = in; |
0c05e10b | 7876 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
7877 | vcpu->arch.pio.size = size; |
7878 | ||
0c05e10b PB |
7879 | if (in) |
7880 | memset(vcpu->arch.pio_data, 0, size * count); | |
7881 | else | |
7882 | memcpy(vcpu->arch.pio_data, data, size * count); | |
cf8f70bf GN |
7883 | |
7884 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 7885 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
7886 | vcpu->run->io.size = size; |
7887 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
7888 | vcpu->run->io.count = count; | |
7889 | vcpu->run->io.port = port; | |
cf8f70bf GN |
7890 | return 0; |
7891 | } | |
7892 | ||
f35cee4a PB |
7893 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
7894 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 7895 | { |
0c05e10b PB |
7896 | int r = emulator_pio_in_out(vcpu, size, port, val, count, true); |
7897 | if (r) | |
7898 | trace_kvm_pio(KVM_PIO_IN, port, size, count, val); | |
7899 | ||
7900 | return r; | |
3b27de27 | 7901 | } |
ca1d4a9e | 7902 | |
6b5efc93 | 7903 | static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) |
3b27de27 | 7904 | { |
6b5efc93 | 7905 | int size = vcpu->arch.pio.size; |
0c05e10b | 7906 | unsigned int count = vcpu->arch.pio.count; |
6b5efc93 PB |
7907 | memcpy(val, vcpu->arch.pio_data, size * count); |
7908 | trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); | |
3b27de27 PB |
7909 | vcpu->arch.pio.count = 0; |
7910 | } | |
cf8f70bf | 7911 | |
f35cee4a PB |
7912 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
7913 | int size, unsigned short port, void *val, | |
7914 | unsigned int count) | |
3b27de27 | 7915 | { |
f35cee4a | 7916 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3b27de27 | 7917 | if (vcpu->arch.pio.count) { |
d07898ea SC |
7918 | /* |
7919 | * Complete a previous iteration that required userspace I/O. | |
7920 | * Note, @count isn't guaranteed to match pio.count as userspace | |
7921 | * can modify ECX before rerunning the vCPU. Ignore any such | |
7922 | * shenanigans as KVM doesn't support modifying the rep count, | |
7923 | * and the emulator ensures @count doesn't overflow the buffer. | |
7924 | */ | |
0c05e10b PB |
7925 | complete_emulator_pio_in(vcpu, val); |
7926 | return 1; | |
cf8f70bf GN |
7927 | } |
7928 | ||
f35cee4a | 7929 | return emulator_pio_in(vcpu, size, port, val, count); |
2e3bb4d8 | 7930 | } |
6f6fbe98 | 7931 | |
2e3bb4d8 SC |
7932 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
7933 | unsigned short port, const void *val, | |
7934 | unsigned int count) | |
7935 | { | |
30d583fd | 7936 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, val); |
0c05e10b | 7937 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
6f6fbe98 XG |
7938 | } |
7939 | ||
2e3bb4d8 SC |
7940 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
7941 | int size, unsigned short port, | |
7942 | const void *val, unsigned int count) | |
7943 | { | |
7944 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
7945 | } | |
7946 | ||
bbd9b64e CO |
7947 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
7948 | { | |
b3646477 | 7949 | return static_call(kvm_x86_get_segment_base)(vcpu, seg); |
bbd9b64e CO |
7950 | } |
7951 | ||
3cb16fe7 | 7952 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 7953 | { |
3cb16fe7 | 7954 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
7955 | } |
7956 | ||
ae6a2375 | 7957 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
7958 | { |
7959 | if (!need_emulate_wbinvd(vcpu)) | |
7960 | return X86EMUL_CONTINUE; | |
7961 | ||
b3646477 | 7962 | if (static_call(kvm_x86_has_wbinvd_exit)()) { |
2eec7343 JK |
7963 | int cpu = get_cpu(); |
7964 | ||
7965 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
c2162e13 | 7966 | on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, |
f5f48ee1 | 7967 | wbinvd_ipi, NULL, 1); |
2eec7343 | 7968 | put_cpu(); |
f5f48ee1 | 7969 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
7970 | } else |
7971 | wbinvd(); | |
f5f48ee1 SY |
7972 | return X86EMUL_CONTINUE; |
7973 | } | |
5cb56059 JS |
7974 | |
7975 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
7976 | { | |
6affcbed KH |
7977 | kvm_emulate_wbinvd_noskip(vcpu); |
7978 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 7979 | } |
f5f48ee1 SY |
7980 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
7981 | ||
5cb56059 JS |
7982 | |
7983 | ||
bcaf5cc5 AK |
7984 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
7985 | { | |
5cb56059 | 7986 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
7987 | } |
7988 | ||
29d6ca41 PB |
7989 | static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
7990 | unsigned long *dest) | |
bbd9b64e | 7991 | { |
29d6ca41 | 7992 | kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
7993 | } |
7994 | ||
52eb5a6d XL |
7995 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
7996 | unsigned long value) | |
bbd9b64e | 7997 | { |
338dbc97 | 7998 | |
996ff542 | 7999 | return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
8000 | } |
8001 | ||
52a46617 | 8002 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 8003 | { |
52a46617 | 8004 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
8005 | } |
8006 | ||
717746e3 | 8007 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 8008 | { |
717746e3 | 8009 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
8010 | unsigned long value; |
8011 | ||
8012 | switch (cr) { | |
8013 | case 0: | |
8014 | value = kvm_read_cr0(vcpu); | |
8015 | break; | |
8016 | case 2: | |
8017 | value = vcpu->arch.cr2; | |
8018 | break; | |
8019 | case 3: | |
9f8fe504 | 8020 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
8021 | break; |
8022 | case 4: | |
8023 | value = kvm_read_cr4(vcpu); | |
8024 | break; | |
8025 | case 8: | |
8026 | value = kvm_get_cr8(vcpu); | |
8027 | break; | |
8028 | default: | |
a737f256 | 8029 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
8030 | return 0; |
8031 | } | |
8032 | ||
8033 | return value; | |
8034 | } | |
8035 | ||
717746e3 | 8036 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 8037 | { |
717746e3 | 8038 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
8039 | int res = 0; |
8040 | ||
52a46617 GN |
8041 | switch (cr) { |
8042 | case 0: | |
49a9b07e | 8043 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
8044 | break; |
8045 | case 2: | |
8046 | vcpu->arch.cr2 = val; | |
8047 | break; | |
8048 | case 3: | |
2390218b | 8049 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
8050 | break; |
8051 | case 4: | |
a83b29c6 | 8052 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
8053 | break; |
8054 | case 8: | |
eea1cff9 | 8055 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
8056 | break; |
8057 | default: | |
a737f256 | 8058 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 8059 | res = -1; |
52a46617 | 8060 | } |
0f12244f GN |
8061 | |
8062 | return res; | |
52a46617 GN |
8063 | } |
8064 | ||
717746e3 | 8065 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 8066 | { |
b3646477 | 8067 | return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); |
9c537244 GN |
8068 | } |
8069 | ||
4bff1e86 | 8070 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 8071 | { |
b3646477 | 8072 | static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
8073 | } |
8074 | ||
4bff1e86 | 8075 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 8076 | { |
b3646477 | 8077 | static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
8078 | } |
8079 | ||
1ac9d0cf AK |
8080 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
8081 | { | |
b3646477 | 8082 | static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
8083 | } |
8084 | ||
8085 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
8086 | { | |
b3646477 | 8087 | static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
8088 | } |
8089 | ||
4bff1e86 AK |
8090 | static unsigned long emulator_get_cached_segment_base( |
8091 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 8092 | { |
4bff1e86 | 8093 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
8094 | } |
8095 | ||
1aa36616 AK |
8096 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
8097 | struct desc_struct *desc, u32 *base3, | |
8098 | int seg) | |
2dafc6c2 GN |
8099 | { |
8100 | struct kvm_segment var; | |
8101 | ||
4bff1e86 | 8102 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 8103 | *selector = var.selector; |
2dafc6c2 | 8104 | |
378a8b09 GN |
8105 | if (var.unusable) { |
8106 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
8107 | if (base3) |
8108 | *base3 = 0; | |
2dafc6c2 | 8109 | return false; |
378a8b09 | 8110 | } |
2dafc6c2 GN |
8111 | |
8112 | if (var.g) | |
8113 | var.limit >>= 12; | |
8114 | set_desc_limit(desc, var.limit); | |
8115 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
8116 | #ifdef CONFIG_X86_64 |
8117 | if (base3) | |
8118 | *base3 = var.base >> 32; | |
8119 | #endif | |
2dafc6c2 GN |
8120 | desc->type = var.type; |
8121 | desc->s = var.s; | |
8122 | desc->dpl = var.dpl; | |
8123 | desc->p = var.present; | |
8124 | desc->avl = var.avl; | |
8125 | desc->l = var.l; | |
8126 | desc->d = var.db; | |
8127 | desc->g = var.g; | |
8128 | ||
8129 | return true; | |
8130 | } | |
8131 | ||
1aa36616 AK |
8132 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
8133 | struct desc_struct *desc, u32 base3, | |
8134 | int seg) | |
2dafc6c2 | 8135 | { |
4bff1e86 | 8136 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
8137 | struct kvm_segment var; |
8138 | ||
1aa36616 | 8139 | var.selector = selector; |
2dafc6c2 | 8140 | var.base = get_desc_base(desc); |
5601d05b GN |
8141 | #ifdef CONFIG_X86_64 |
8142 | var.base |= ((u64)base3) << 32; | |
8143 | #endif | |
2dafc6c2 GN |
8144 | var.limit = get_desc_limit(desc); |
8145 | if (desc->g) | |
8146 | var.limit = (var.limit << 12) | 0xfff; | |
8147 | var.type = desc->type; | |
2dafc6c2 GN |
8148 | var.dpl = desc->dpl; |
8149 | var.db = desc->d; | |
8150 | var.s = desc->s; | |
8151 | var.l = desc->l; | |
8152 | var.g = desc->g; | |
8153 | var.avl = desc->avl; | |
8154 | var.present = desc->p; | |
8155 | var.unusable = !var.present; | |
8156 | var.padding = 0; | |
8157 | ||
8158 | kvm_set_segment(vcpu, &var, seg); | |
8159 | return; | |
8160 | } | |
8161 | ||
ac8d6cad HW |
8162 | static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt, |
8163 | u32 msr_index, u64 *pdata) | |
717746e3 | 8164 | { |
1ae09954 AG |
8165 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8166 | int r; | |
8167 | ||
ac8d6cad | 8168 | r = kvm_get_msr_with_filter(vcpu, msr_index, pdata); |
36d546d5 HW |
8169 | if (r < 0) |
8170 | return X86EMUL_UNHANDLEABLE; | |
1ae09954 | 8171 | |
36d546d5 HW |
8172 | if (r) { |
8173 | if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0, | |
8174 | complete_emulated_rdmsr, r)) | |
8175 | return X86EMUL_IO_NEEDED; | |
794663e1 HW |
8176 | |
8177 | trace_kvm_msr_read_ex(msr_index); | |
36d546d5 | 8178 | return X86EMUL_PROPAGATE_FAULT; |
1ae09954 AG |
8179 | } |
8180 | ||
794663e1 | 8181 | trace_kvm_msr_read(msr_index, *pdata); |
36d546d5 | 8182 | return X86EMUL_CONTINUE; |
717746e3 AK |
8183 | } |
8184 | ||
ac8d6cad HW |
8185 | static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt, |
8186 | u32 msr_index, u64 data) | |
717746e3 | 8187 | { |
1ae09954 AG |
8188 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8189 | int r; | |
8190 | ||
ac8d6cad | 8191 | r = kvm_set_msr_with_filter(vcpu, msr_index, data); |
36d546d5 HW |
8192 | if (r < 0) |
8193 | return X86EMUL_UNHANDLEABLE; | |
1ae09954 | 8194 | |
36d546d5 HW |
8195 | if (r) { |
8196 | if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data, | |
8197 | complete_emulated_msr_access, r)) | |
8198 | return X86EMUL_IO_NEEDED; | |
794663e1 HW |
8199 | |
8200 | trace_kvm_msr_write_ex(msr_index, data); | |
36d546d5 | 8201 | return X86EMUL_PROPAGATE_FAULT; |
1ae09954 AG |
8202 | } |
8203 | ||
794663e1 | 8204 | trace_kvm_msr_write(msr_index, data); |
36d546d5 | 8205 | return X86EMUL_CONTINUE; |
717746e3 AK |
8206 | } |
8207 | ||
ac8d6cad HW |
8208 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
8209 | u32 msr_index, u64 *pdata) | |
8210 | { | |
8211 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); | |
8212 | } | |
8213 | ||
67f4d428 NA |
8214 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
8215 | u32 pmc) | |
8216 | { | |
e6cd31f1 JM |
8217 | if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc)) |
8218 | return 0; | |
8219 | return -EINVAL; | |
67f4d428 NA |
8220 | } |
8221 | ||
222d21aa AK |
8222 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
8223 | u32 pmc, u64 *pdata) | |
8224 | { | |
c6702c9d | 8225 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
8226 | } |
8227 | ||
6c3287f7 AK |
8228 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
8229 | { | |
8230 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
8231 | } | |
8232 | ||
2953538e | 8233 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 8234 | struct x86_instruction_info *info, |
c4f035c6 AK |
8235 | enum x86_intercept_stage stage) |
8236 | { | |
b3646477 | 8237 | return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 8238 | &ctxt->exception); |
c4f035c6 AK |
8239 | } |
8240 | ||
e911eb3b | 8241 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
8242 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
8243 | bool exact_only) | |
bdb42f5a | 8244 | { |
f91af517 | 8245 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
8246 | } |
8247 | ||
5ae78e95 SC |
8248 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
8249 | { | |
8250 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
8251 | } | |
8252 | ||
8253 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
8254 | { | |
8255 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
8256 | } | |
8257 | ||
8258 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
8259 | { | |
8260 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
8261 | } | |
8262 | ||
a836839c HW |
8263 | static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt) |
8264 | { | |
8265 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID); | |
8266 | } | |
8267 | ||
dd856efa AK |
8268 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
8269 | { | |
27b4a9c4 | 8270 | return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); |
dd856efa AK |
8271 | } |
8272 | ||
8273 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
8274 | { | |
27b4a9c4 | 8275 | kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); |
dd856efa AK |
8276 | } |
8277 | ||
801806d9 NA |
8278 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
8279 | { | |
b3646477 | 8280 | static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
8281 | } |
8282 | ||
32e69f23 | 8283 | static bool emulator_is_smm(struct x86_emulate_ctxt *ctxt) |
6ed071f0 | 8284 | { |
32e69f23 ML |
8285 | return is_smm(emul_to_vcpu(ctxt)); |
8286 | } | |
8287 | ||
8288 | static bool emulator_is_guest_mode(struct x86_emulate_ctxt *ctxt) | |
6ed071f0 | 8289 | { |
32e69f23 | 8290 | return is_guest_mode(emul_to_vcpu(ctxt)); |
6ed071f0 LP |
8291 | } |
8292 | ||
4b8e1b32 PB |
8293 | #ifndef CONFIG_KVM_SMM |
8294 | static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt) | |
6ed071f0 | 8295 | { |
4b8e1b32 PB |
8296 | WARN_ON_ONCE(1); |
8297 | return X86EMUL_UNHANDLEABLE; | |
0234bf88 | 8298 | } |
4b8e1b32 | 8299 | #endif |
0234bf88 | 8300 | |
25b17226 SC |
8301 | static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) |
8302 | { | |
8303 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); | |
8304 | } | |
8305 | ||
02d4160f VK |
8306 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
8307 | { | |
8308 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
8309 | } | |
8310 | ||
1cca2f8c SC |
8311 | static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt) |
8312 | { | |
8313 | struct kvm *kvm = emul_to_vcpu(ctxt)->kvm; | |
8314 | ||
8315 | if (!kvm->vm_bugged) | |
8316 | kvm_vm_bugged(kvm); | |
8317 | } | |
8318 | ||
0225fb50 | 8319 | static const struct x86_emulate_ops emulate_ops = { |
1cca2f8c | 8320 | .vm_bugged = emulator_vm_bugged, |
dd856efa AK |
8321 | .read_gpr = emulator_read_gpr, |
8322 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
8323 | .read_std = emulator_read_std, |
8324 | .write_std = emulator_write_std, | |
1871c602 | 8325 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
8326 | .read_emulated = emulator_read_emulated, |
8327 | .write_emulated = emulator_write_emulated, | |
8328 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 8329 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
8330 | .pio_in_emulated = emulator_pio_in_emulated, |
8331 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
8332 | .get_segment = emulator_get_segment, |
8333 | .set_segment = emulator_set_segment, | |
5951c442 | 8334 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 8335 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 8336 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
8337 | .set_gdt = emulator_set_gdt, |
8338 | .set_idt = emulator_set_idt, | |
52a46617 GN |
8339 | .get_cr = emulator_get_cr, |
8340 | .set_cr = emulator_set_cr, | |
9c537244 | 8341 | .cpl = emulator_get_cpl, |
35aa5375 GN |
8342 | .get_dr = emulator_get_dr, |
8343 | .set_dr = emulator_set_dr, | |
ac8d6cad HW |
8344 | .set_msr_with_filter = emulator_set_msr_with_filter, |
8345 | .get_msr_with_filter = emulator_get_msr_with_filter, | |
717746e3 | 8346 | .get_msr = emulator_get_msr, |
67f4d428 | 8347 | .check_pmc = emulator_check_pmc, |
222d21aa | 8348 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 8349 | .halt = emulator_halt, |
bcaf5cc5 | 8350 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 8351 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 8352 | .intercept = emulator_intercept, |
bdb42f5a | 8353 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
8354 | .guest_has_long_mode = emulator_guest_has_long_mode, |
8355 | .guest_has_movbe = emulator_guest_has_movbe, | |
8356 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
a836839c | 8357 | .guest_has_rdpid = emulator_guest_has_rdpid, |
801806d9 | 8358 | .set_nmi_mask = emulator_set_nmi_mask, |
32e69f23 ML |
8359 | .is_smm = emulator_is_smm, |
8360 | .is_guest_mode = emulator_is_guest_mode, | |
ecc513e5 | 8361 | .leave_smm = emulator_leave_smm, |
25b17226 | 8362 | .triple_fault = emulator_triple_fault, |
02d4160f | 8363 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
8364 | }; |
8365 | ||
95cb2295 GN |
8366 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
8367 | { | |
b3646477 | 8368 | u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
95cb2295 GN |
8369 | /* |
8370 | * an sti; sti; sequence only disable interrupts for the first | |
8371 | * instruction. So, if the last instruction, be it emulated or | |
8372 | * not, left the system with the INT_STI flag enabled, it | |
8373 | * means that the last instruction is an sti. We should not | |
8374 | * leave the flag on in this case. The same goes for mov ss | |
8375 | */ | |
37ccdcbe PB |
8376 | if (int_shadow & mask) |
8377 | mask = 0; | |
6addfc42 | 8378 | if (unlikely(int_shadow || mask)) { |
b3646477 | 8379 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); |
6addfc42 PB |
8380 | if (!mask) |
8381 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8382 | } | |
95cb2295 GN |
8383 | } |
8384 | ||
7709aba8 | 8385 | static void inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 8386 | { |
c9b8b07c | 8387 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
ef54bcfe | 8388 | |
7709aba8 SC |
8389 | if (ctxt->exception.vector == PF_VECTOR) |
8390 | kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); | |
8391 | else if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
8392 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
8393 | ctxt->exception.error_code); | |
54b8486f | 8394 | else |
da9cb575 | 8395 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
54b8486f GN |
8396 | } |
8397 | ||
c9b8b07c SC |
8398 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
8399 | { | |
8400 | struct x86_emulate_ctxt *ctxt; | |
8401 | ||
8402 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
8403 | if (!ctxt) { | |
8d20bd63 | 8404 | pr_err("failed to allocate vcpu's emulator\n"); |
c9b8b07c SC |
8405 | return NULL; |
8406 | } | |
8407 | ||
8408 | ctxt->vcpu = vcpu; | |
8409 | ctxt->ops = &emulate_ops; | |
8410 | vcpu->arch.emulate_ctxt = ctxt; | |
8411 | ||
8412 | return ctxt; | |
8413 | } | |
8414 | ||
8ec4722d MG |
8415 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
8416 | { | |
c9b8b07c | 8417 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
8418 | int cs_db, cs_l; |
8419 | ||
b3646477 | 8420 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
8ec4722d | 8421 | |
744e699c | 8422 | ctxt->gpa_available = false; |
adf52235 | 8423 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
8424 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
8425 | ||
adf52235 TY |
8426 | ctxt->eip = kvm_rip_read(vcpu); |
8427 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
8428 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 8429 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
8430 | cs_db ? X86EMUL_MODE_PROT32 : |
8431 | X86EMUL_MODE_PROT16; | |
da6393cd WL |
8432 | ctxt->interruptibility = 0; |
8433 | ctxt->have_exception = false; | |
8434 | ctxt->exception.vector = -1; | |
8435 | ctxt->perm_ok = false; | |
8436 | ||
dd856efa | 8437 | init_decode_cache(ctxt); |
7ae441ea | 8438 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
8439 | } |
8440 | ||
9497e1f2 | 8441 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 8442 | { |
c9b8b07c | 8443 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
8444 | int ret; |
8445 | ||
8446 | init_emulate_ctxt(vcpu); | |
8447 | ||
9dac77fa AK |
8448 | ctxt->op_bytes = 2; |
8449 | ctxt->ad_bytes = 2; | |
8450 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 8451 | ret = emulate_int_real(ctxt, irq); |
63995653 | 8452 | |
9497e1f2 SC |
8453 | if (ret != X86EMUL_CONTINUE) { |
8454 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
8455 | } else { | |
8456 | ctxt->eip = ctxt->_eip; | |
8457 | kvm_rip_write(vcpu, ctxt->eip); | |
8458 | kvm_set_rflags(vcpu, ctxt->eflags); | |
8459 | } | |
63995653 MG |
8460 | } |
8461 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
8462 | ||
e615e355 DE |
8463 | static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, |
8464 | u8 ndata, u8 *insn_bytes, u8 insn_size) | |
19238e75 | 8465 | { |
19238e75 | 8466 | struct kvm_run *run = vcpu->run; |
e615e355 DE |
8467 | u64 info[5]; |
8468 | u8 info_start; | |
8469 | ||
8470 | /* | |
8471 | * Zero the whole array used to retrieve the exit info, as casting to | |
8472 | * u32 for select entries will leave some chunks uninitialized. | |
8473 | */ | |
8474 | memset(&info, 0, sizeof(info)); | |
8475 | ||
8476 | static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1], | |
8477 | &info[2], (u32 *)&info[3], | |
8478 | (u32 *)&info[4]); | |
19238e75 AL |
8479 | |
8480 | run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
8481 | run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
e615e355 DE |
8482 | |
8483 | /* | |
8484 | * There's currently space for 13 entries, but 5 are used for the exit | |
8485 | * reason and info. Restrict to 4 to reduce the maintenance burden | |
8486 | * when expanding kvm_run.emulation_failure in the future. | |
8487 | */ | |
8488 | if (WARN_ON_ONCE(ndata > 4)) | |
8489 | ndata = 4; | |
8490 | ||
8491 | /* Always include the flags as a 'data' entry. */ | |
8492 | info_start = 1; | |
19238e75 AL |
8493 | run->emulation_failure.flags = 0; |
8494 | ||
8495 | if (insn_size) { | |
e615e355 DE |
8496 | BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + |
8497 | sizeof(run->emulation_failure.insn_bytes) != 16)); | |
8498 | info_start += 2; | |
19238e75 AL |
8499 | run->emulation_failure.flags |= |
8500 | KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; | |
8501 | run->emulation_failure.insn_size = insn_size; | |
8502 | memset(run->emulation_failure.insn_bytes, 0x90, | |
8503 | sizeof(run->emulation_failure.insn_bytes)); | |
e615e355 | 8504 | memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); |
19238e75 | 8505 | } |
e615e355 DE |
8506 | |
8507 | memcpy(&run->internal.data[info_start], info, sizeof(info)); | |
8508 | memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, | |
8509 | ndata * sizeof(data[0])); | |
8510 | ||
8511 | run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; | |
19238e75 AL |
8512 | } |
8513 | ||
e615e355 DE |
8514 | static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) |
8515 | { | |
8516 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
8517 | ||
8518 | prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, | |
8519 | ctxt->fetch.end - ctxt->fetch.data); | |
8520 | } | |
8521 | ||
8522 | void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, | |
8523 | u8 ndata) | |
8524 | { | |
8525 | prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); | |
19238e75 | 8526 | } |
e615e355 DE |
8527 | EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); |
8528 | ||
8529 | void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) | |
8530 | { | |
8531 | __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); | |
8532 | } | |
8533 | EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); | |
19238e75 | 8534 | |
e2366171 | 8535 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 8536 | { |
19238e75 AL |
8537 | struct kvm *kvm = vcpu->kvm; |
8538 | ||
6d77dbfc GN |
8539 | ++vcpu->stat.insn_emulation_fail; |
8540 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 8541 | |
42cbf068 SC |
8542 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
8543 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 8544 | return 1; |
42cbf068 | 8545 | } |
e2366171 | 8546 | |
19238e75 AL |
8547 | if (kvm->arch.exit_on_emulation_error || |
8548 | (emulation_type & EMULTYPE_SKIP)) { | |
e615e355 | 8549 | prepare_emulation_ctxt_failure_exit(vcpu); |
60fc3d02 | 8550 | return 0; |
738fece4 SC |
8551 | } |
8552 | ||
22da61c9 SC |
8553 | kvm_queue_exception(vcpu, UD_VECTOR); |
8554 | ||
b3646477 | 8555 | if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { |
e615e355 | 8556 | prepare_emulation_ctxt_failure_exit(vcpu); |
60fc3d02 | 8557 | return 0; |
fc3a9157 | 8558 | } |
e2366171 | 8559 | |
60fc3d02 | 8560 | return 1; |
6d77dbfc GN |
8561 | } |
8562 | ||
736c291c | 8563 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 | 8564 | int emulation_type) |
a6f177ef | 8565 | { |
736c291c | 8566 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 8567 | kvm_pfn_t pfn; |
a6f177ef | 8568 | |
92daa48b | 8569 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
8570 | return false; |
8571 | ||
92daa48b SC |
8572 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
8573 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
8574 | return false; |
8575 | ||
347a0d0d | 8576 | if (!vcpu->arch.mmu->root_role.direct) { |
95b3cf69 XG |
8577 | /* |
8578 | * Write permission should be allowed since only | |
8579 | * write access need to be emulated. | |
8580 | */ | |
736c291c | 8581 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 8582 | |
95b3cf69 XG |
8583 | /* |
8584 | * If the mapping is invalid in guest, let cpu retry | |
8585 | * it to generate fault. | |
8586 | */ | |
6e1d2a3f | 8587 | if (gpa == INVALID_GPA) |
95b3cf69 XG |
8588 | return true; |
8589 | } | |
a6f177ef | 8590 | |
8e3d9d06 XG |
8591 | /* |
8592 | * Do not retry the unhandleable instruction if it faults on the | |
8593 | * readonly host memory, otherwise it will goto a infinite loop: | |
8594 | * retry instruction -> write #PF -> emulation fail -> retry | |
8595 | * instruction -> ... | |
8596 | */ | |
8597 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
8598 | |
8599 | /* | |
8600 | * If the instruction failed on the error pfn, it can not be fixed, | |
8601 | * report the error to userspace. | |
8602 | */ | |
8603 | if (is_error_noslot_pfn(pfn)) | |
8604 | return false; | |
8605 | ||
8606 | kvm_release_pfn_clean(pfn); | |
8607 | ||
8608 | /* The instructions are well-emulated on direct mmu. */ | |
347a0d0d | 8609 | if (vcpu->arch.mmu->root_role.direct) { |
95b3cf69 XG |
8610 | unsigned int indirect_shadow_pages; |
8611 | ||
531810ca | 8612 | write_lock(&vcpu->kvm->mmu_lock); |
95b3cf69 | 8613 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; |
531810ca | 8614 | write_unlock(&vcpu->kvm->mmu_lock); |
95b3cf69 XG |
8615 | |
8616 | if (indirect_shadow_pages) | |
8617 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
8618 | ||
a6f177ef | 8619 | return true; |
8e3d9d06 | 8620 | } |
a6f177ef | 8621 | |
95b3cf69 XG |
8622 | /* |
8623 | * if emulation was due to access to shadowed page table | |
8624 | * and it failed try to unshadow page and re-enter the | |
8625 | * guest to let CPU execute the instruction. | |
8626 | */ | |
8627 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
8628 | |
8629 | /* | |
8630 | * If the access faults on its page table, it can not | |
8631 | * be fixed by unprotecting shadow page and it should | |
8632 | * be reported to userspace. | |
8633 | */ | |
258d985f | 8634 | return !(emulation_type & EMULTYPE_WRITE_PF_TO_SP); |
a6f177ef GN |
8635 | } |
8636 | ||
1cb3f3ae | 8637 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 8638 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
8639 | { |
8640 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 8641 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
8642 | |
8643 | last_retry_eip = vcpu->arch.last_retry_eip; | |
8644 | last_retry_addr = vcpu->arch.last_retry_addr; | |
8645 | ||
8646 | /* | |
8647 | * If the emulation is caused by #PF and it is non-page_table | |
8648 | * writing instruction, it means the VM-EXIT is caused by shadow | |
8649 | * page protected, we can zap the shadow page and retry this | |
8650 | * instruction directly. | |
8651 | * | |
8652 | * Note: if the guest uses a non-page-table modifying instruction | |
8653 | * on the PDE that points to the instruction, then we will unmap | |
8654 | * the instruction and go to an infinite loop. So, we cache the | |
8655 | * last retried eip and the last fault address, if we meet the eip | |
8656 | * and the address again, we can break out of the potential infinite | |
8657 | * loop. | |
8658 | */ | |
8659 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
8660 | ||
92daa48b | 8661 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
8662 | return false; |
8663 | ||
92daa48b SC |
8664 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
8665 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
8666 | return false; |
8667 | ||
1cb3f3ae XG |
8668 | if (x86_page_table_writing_insn(ctxt)) |
8669 | return false; | |
8670 | ||
736c291c | 8671 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
8672 | return false; |
8673 | ||
8674 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 8675 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 8676 | |
347a0d0d | 8677 | if (!vcpu->arch.mmu->root_role.direct) |
736c291c | 8678 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 8679 | |
22368028 | 8680 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
8681 | |
8682 | return true; | |
8683 | } | |
8684 | ||
716d51ab GN |
8685 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
8686 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
8687 | ||
4a1e10d5 PB |
8688 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
8689 | unsigned long *db) | |
8690 | { | |
8691 | u32 dr6 = 0; | |
8692 | int i; | |
8693 | u32 enable, rwlen; | |
8694 | ||
8695 | enable = dr7; | |
8696 | rwlen = dr7 >> 16; | |
8697 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
8698 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
8699 | dr6 |= (1 << i); | |
8700 | return dr6; | |
8701 | } | |
8702 | ||
120c2c4f | 8703 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
8704 | { |
8705 | struct kvm_run *kvm_run = vcpu->run; | |
8706 | ||
c8401dda | 8707 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
9a3ecd5e | 8708 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; |
d5d260c5 | 8709 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
8710 | kvm_run->debug.arch.exception = DB_VECTOR; |
8711 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 8712 | return 0; |
663f4c61 | 8713 | } |
120c2c4f | 8714 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 8715 | return 1; |
663f4c61 PB |
8716 | } |
8717 | ||
6affcbed KH |
8718 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
8719 | { | |
b3646477 | 8720 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
f8ea7c60 | 8721 | int r; |
6affcbed | 8722 | |
b3646477 | 8723 | r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); |
60fc3d02 | 8724 | if (unlikely(!r)) |
f8ea7c60 | 8725 | return 0; |
c8401dda | 8726 | |
9cd803d4 EH |
8727 | kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); |
8728 | ||
c8401dda PB |
8729 | /* |
8730 | * rflags is the old, "raw" value of the flags. The new value has | |
8731 | * not been saved yet. | |
8732 | * | |
8733 | * This is correct even for TF set by the guest, because "the | |
8734 | * processor will not generate this exception after the instruction | |
8735 | * that sets the TF flag". | |
8736 | */ | |
8737 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 8738 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 8739 | return r; |
6affcbed KH |
8740 | } |
8741 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
8742 | ||
baf67ca8 | 8743 | static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu) |
4a1e10d5 | 8744 | { |
baf67ca8 SC |
8745 | u32 shadow; |
8746 | ||
8747 | if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF) | |
8748 | return true; | |
8749 | ||
8750 | /* | |
8751 | * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active, | |
8752 | * but AMD CPUs do not. MOV/POP SS blocking is rare, check that first | |
8753 | * to avoid the relatively expensive CPUID lookup. | |
8754 | */ | |
8755 | shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); | |
8756 | return (shadow & KVM_X86_SHADOW_INT_MOV_SS) && | |
8757 | guest_cpuid_is_intel(vcpu); | |
8758 | } | |
8759 | ||
750f8fcb SC |
8760 | static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu, |
8761 | int emulation_type, int *r) | |
4a1e10d5 | 8762 | { |
750f8fcb SC |
8763 | WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE); |
8764 | ||
8765 | /* | |
8766 | * Do not check for code breakpoints if hardware has already done the | |
8767 | * checks, as inferred from the emulation type. On NO_DECODE and SKIP, | |
8768 | * the instruction has passed all exception checks, and all intercepted | |
8769 | * exceptions that trigger emulation have lower priority than code | |
8770 | * breakpoints, i.e. the fact that the intercepted exception occurred | |
8771 | * means any code breakpoints have already been serviced. | |
8772 | * | |
8773 | * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as | |
8774 | * hardware has checked the RIP of the magic prefix, but not the RIP of | |
8775 | * the instruction being emulated. The intent of forced emulation is | |
8776 | * to behave as if KVM intercepted the instruction without an exception | |
8777 | * and without a prefix. | |
8778 | */ | |
8779 | if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP | | |
8780 | EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF)) | |
8781 | return false; | |
8782 | ||
4a1e10d5 PB |
8783 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
8784 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
8785 | struct kvm_run *kvm_run = vcpu->run; |
8786 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
8787 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
8788 | vcpu->arch.guest_debug_dr7, |
8789 | vcpu->arch.eff_db); | |
8790 | ||
8791 | if (dr6 != 0) { | |
9a3ecd5e | 8792 | kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; |
82b32774 | 8793 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
8794 | kvm_run->debug.arch.exception = DB_VECTOR; |
8795 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 8796 | *r = 0; |
4a1e10d5 PB |
8797 | return true; |
8798 | } | |
8799 | } | |
8800 | ||
4161a569 | 8801 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
baf67ca8 | 8802 | !kvm_is_code_breakpoint_inhibited(vcpu)) { |
82b32774 NA |
8803 | unsigned long eip = kvm_get_linear_rip(vcpu); |
8804 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
8805 | vcpu->arch.dr7, |
8806 | vcpu->arch.db); | |
8807 | ||
8808 | if (dr6 != 0) { | |
4d5523cf | 8809 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 8810 | *r = 1; |
4a1e10d5 PB |
8811 | return true; |
8812 | } | |
8813 | } | |
8814 | ||
8815 | return false; | |
8816 | } | |
8817 | ||
04789b66 LA |
8818 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
8819 | { | |
2d7921c4 AM |
8820 | switch (ctxt->opcode_len) { |
8821 | case 1: | |
8822 | switch (ctxt->b) { | |
8823 | case 0xe4: /* IN */ | |
8824 | case 0xe5: | |
8825 | case 0xec: | |
8826 | case 0xed: | |
8827 | case 0xe6: /* OUT */ | |
8828 | case 0xe7: | |
8829 | case 0xee: | |
8830 | case 0xef: | |
8831 | case 0x6c: /* INS */ | |
8832 | case 0x6d: | |
8833 | case 0x6e: /* OUTS */ | |
8834 | case 0x6f: | |
8835 | return true; | |
8836 | } | |
8837 | break; | |
8838 | case 2: | |
8839 | switch (ctxt->b) { | |
8840 | case 0x33: /* RDPMC */ | |
8841 | return true; | |
8842 | } | |
8843 | break; | |
04789b66 LA |
8844 | } |
8845 | ||
8846 | return false; | |
8847 | } | |
8848 | ||
4aa2691d | 8849 | /* |
fee060cd SC |
8850 | * Decode an instruction for emulation. The caller is responsible for handling |
8851 | * code breakpoints. Note, manually detecting code breakpoints is unnecessary | |
8852 | * (and wrong) when emulating on an intercepted fault-like exception[*], as | |
8853 | * code breakpoints have higher priority and thus have already been done by | |
8854 | * hardware. | |
8855 | * | |
8856 | * [*] Except #MC, which is higher priority, but KVM should never emulate in | |
8857 | * response to a machine check. | |
4aa2691d WH |
8858 | */ |
8859 | int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, | |
8860 | void *insn, int insn_len) | |
8861 | { | |
4aa2691d | 8862 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
fee060cd | 8863 | int r; |
4aa2691d WH |
8864 | |
8865 | init_emulate_ctxt(vcpu); | |
8866 | ||
b35491e6 | 8867 | r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); |
4aa2691d WH |
8868 | |
8869 | trace_kvm_emulate_insn_start(vcpu); | |
8870 | ++vcpu->stat.insn_emulation; | |
8871 | ||
8872 | return r; | |
8873 | } | |
8874 | EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); | |
8875 | ||
736c291c SC |
8876 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
8877 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 8878 | { |
95cb2295 | 8879 | int r; |
c9b8b07c | 8880 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 8881 | bool writeback = true; |
09e3e2a1 | 8882 | |
4d31d9ef | 8883 | if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len))) |
09e3e2a1 | 8884 | return 1; |
bbd9b64e | 8885 | |
c595ceee PB |
8886 | vcpu->arch.l1tf_flush_l1d = true; |
8887 | ||
571008da | 8888 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
4aa2691d | 8889 | kvm_clear_exception_queue(vcpu); |
4a1e10d5 | 8890 | |
fee060cd SC |
8891 | /* |
8892 | * Return immediately if RIP hits a code breakpoint, such #DBs | |
8893 | * are fault-like and are higher priority than any faults on | |
8894 | * the code fetch itself. | |
8895 | */ | |
750f8fcb | 8896 | if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r)) |
fee060cd SC |
8897 | return r; |
8898 | ||
4aa2691d WH |
8899 | r = x86_decode_emulated_instruction(vcpu, emulation_type, |
8900 | insn, insn_len); | |
1d2887e2 | 8901 | if (r != EMULATION_OK) { |
b4000606 | 8902 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
8903 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
8904 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 8905 | return 1; |
c83fad65 | 8906 | } |
736c291c | 8907 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
736c291c | 8908 | emulation_type)) |
60fc3d02 | 8909 | return 1; |
17122c06 SC |
8910 | |
8911 | if (ctxt->have_exception && | |
8912 | !(emulation_type & EMULTYPE_SKIP)) { | |
c8848cee JD |
8913 | /* |
8914 | * #UD should result in just EMULATION_FAILED, and trap-like | |
8915 | * exception should not be encountered during decode. | |
8916 | */ | |
8917 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
8918 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 8919 | inject_emulated_exception(vcpu); |
60fc3d02 | 8920 | return 1; |
8530a79c | 8921 | } |
e2366171 | 8922 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
8923 | } |
8924 | } | |
8925 | ||
42cbf068 SC |
8926 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
8927 | !is_vmware_backdoor_opcode(ctxt)) { | |
8928 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 8929 | return 1; |
42cbf068 | 8930 | } |
04789b66 | 8931 | |
1957aa63 | 8932 | /* |
906fa904 HW |
8933 | * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for |
8934 | * use *only* by vendor callbacks for kvm_skip_emulated_instruction(). | |
8935 | * The caller is responsible for updating interruptibility state and | |
8936 | * injecting single-step #DBs. | |
1957aa63 | 8937 | */ |
ba8afb6b | 8938 | if (emulation_type & EMULTYPE_SKIP) { |
5e854864 SC |
8939 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
8940 | ctxt->eip = (u32)ctxt->_eip; | |
8941 | else | |
8942 | ctxt->eip = ctxt->_eip; | |
8943 | ||
906fa904 HW |
8944 | if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) { |
8945 | r = 1; | |
8946 | goto writeback; | |
8947 | } | |
8948 | ||
5e854864 | 8949 | kvm_rip_write(vcpu, ctxt->eip); |
bb663c7a NA |
8950 | if (ctxt->eflags & X86_EFLAGS_RF) |
8951 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 8952 | return 1; |
ba8afb6b GN |
8953 | } |
8954 | ||
736c291c | 8955 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 8956 | return 1; |
1cb3f3ae | 8957 | |
7ae441ea | 8958 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 8959 | changes registers values during IO operation */ |
7ae441ea GN |
8960 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
8961 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 8962 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 8963 | } |
4d2179e1 | 8964 | |
5cd21917 | 8965 | restart: |
92daa48b SC |
8966 | if (emulation_type & EMULTYPE_PF) { |
8967 | /* Save the faulting GPA (cr2) in the address field */ | |
8968 | ctxt->exception.address = cr2_or_gpa; | |
8969 | ||
8970 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
347a0d0d | 8971 | if (vcpu->arch.mmu->root_role.direct) { |
744e699c SC |
8972 | ctxt->gpa_available = true; |
8973 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
8974 | } |
8975 | } else { | |
8976 | /* Sanitize the address out of an abundance of paranoia. */ | |
8977 | ctxt->exception.address = 0; | |
8978 | } | |
0f89b207 | 8979 | |
9d74191a | 8980 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 8981 | |
775fde86 | 8982 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 8983 | return 1; |
775fde86 | 8984 | |
d2ddd1c4 | 8985 | if (r == EMULATION_FAILED) { |
258d985f | 8986 | if (reexecute_instruction(vcpu, cr2_or_gpa, emulation_type)) |
60fc3d02 | 8987 | return 1; |
c3cd7ffa | 8988 | |
e2366171 | 8989 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
8990 | } |
8991 | ||
9d74191a | 8992 | if (ctxt->have_exception) { |
0dc90226 SC |
8993 | WARN_ON_ONCE(vcpu->mmio_needed && !vcpu->mmio_is_write); |
8994 | vcpu->mmio_needed = false; | |
60fc3d02 | 8995 | r = 1; |
7709aba8 | 8996 | inject_emulated_exception(vcpu); |
d2ddd1c4 | 8997 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
8998 | if (!vcpu->arch.pio.in) { |
8999 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 9000 | vcpu->arch.pio.count = 0; |
0912c977 | 9001 | } else { |
7ae441ea | 9002 | writeback = false; |
716d51ab GN |
9003 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
9004 | } | |
60fc3d02 | 9005 | r = 0; |
7ae441ea | 9006 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
9007 | ++vcpu->stat.mmio_exits; |
9008 | ||
7ae441ea GN |
9009 | if (!vcpu->mmio_is_write) |
9010 | writeback = false; | |
60fc3d02 | 9011 | r = 0; |
716d51ab | 9012 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
adbfb12d HW |
9013 | } else if (vcpu->arch.complete_userspace_io) { |
9014 | writeback = false; | |
9015 | r = 0; | |
7ae441ea | 9016 | } else if (r == EMULATION_RESTART) |
5cd21917 | 9017 | goto restart; |
d2ddd1c4 | 9018 | else |
60fc3d02 | 9019 | r = 1; |
f850e2e6 | 9020 | |
906fa904 | 9021 | writeback: |
7ae441ea | 9022 | if (writeback) { |
b3646477 | 9023 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
9d74191a | 9024 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 9025 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
5623f751 SC |
9026 | |
9027 | /* | |
9028 | * Note, EXCPT_DB is assumed to be fault-like as the emulator | |
9029 | * only supports code breakpoints and general detect #DB, both | |
9030 | * of which are fault-like. | |
9031 | */ | |
38827dbd | 9032 | if (!ctxt->have_exception || |
75ee23b3 | 9033 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
9cd803d4 | 9034 | kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); |
018d70ff EH |
9035 | if (ctxt->is_branch) |
9036 | kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS); | |
75ee23b3 | 9037 | kvm_rip_write(vcpu, ctxt->eip); |
384dea1c | 9038 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 9039 | r = kvm_vcpu_do_singlestep(vcpu); |
2a890614 | 9040 | static_call_cond(kvm_x86_update_emulated_instruction)(vcpu); |
38827dbd | 9041 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 9042 | } |
6addfc42 PB |
9043 | |
9044 | /* | |
9045 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
9046 | * do nothing, and it will be requested again as soon as | |
9047 | * the shadow expires. But we still need to check here, | |
9048 | * because POPF has no interrupt shadow. | |
9049 | */ | |
9050 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
9051 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
9052 | } else |
9053 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
9054 | |
9055 | return r; | |
de7d789a | 9056 | } |
c60658d1 SC |
9057 | |
9058 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
9059 | { | |
9060 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
9061 | } | |
9062 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
9063 | ||
9064 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
9065 | void *insn, int insn_len) | |
9066 | { | |
9067 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
9068 | } | |
9069 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 9070 | |
8764ed55 SC |
9071 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
9072 | { | |
9073 | vcpu->arch.pio.count = 0; | |
9074 | return 1; | |
9075 | } | |
9076 | ||
45def77e SC |
9077 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
9078 | { | |
9079 | vcpu->arch.pio.count = 0; | |
9080 | ||
9081 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
9082 | return 1; | |
9083 | ||
9084 | return kvm_skip_emulated_instruction(vcpu); | |
9085 | } | |
9086 | ||
dca7f128 SC |
9087 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
9088 | unsigned short port) | |
de7d789a | 9089 | { |
de3cd117 | 9090 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
9091 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
9092 | ||
8764ed55 SC |
9093 | if (ret) |
9094 | return ret; | |
45def77e | 9095 | |
8764ed55 SC |
9096 | /* |
9097 | * Workaround userspace that relies on old KVM behavior of %rip being | |
9098 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
9099 | */ | |
9100 | if (port == 0x7e && | |
9101 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
9102 | vcpu->arch.complete_userspace_io = | |
9103 | complete_fast_pio_out_port_0x7e; | |
9104 | kvm_skip_emulated_instruction(vcpu); | |
9105 | } else { | |
45def77e SC |
9106 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
9107 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
9108 | } | |
8764ed55 | 9109 | return 0; |
de7d789a | 9110 | } |
de7d789a | 9111 | |
8370c3d0 TL |
9112 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
9113 | { | |
9114 | unsigned long val; | |
9115 | ||
9116 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
9117 | BUG_ON(vcpu->arch.pio.count != 1); | |
9118 | ||
45def77e SC |
9119 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
9120 | vcpu->arch.pio.count = 0; | |
9121 | return 1; | |
9122 | } | |
9123 | ||
8370c3d0 | 9124 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 9125 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 9126 | |
7a6177d6 | 9127 | complete_emulator_pio_in(vcpu, &val); |
de3cd117 | 9128 | kvm_rax_write(vcpu, val); |
8370c3d0 | 9129 | |
45def77e | 9130 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
9131 | } |
9132 | ||
dca7f128 SC |
9133 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
9134 | unsigned short port) | |
8370c3d0 TL |
9135 | { |
9136 | unsigned long val; | |
9137 | int ret; | |
9138 | ||
9139 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 9140 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 9141 | |
2e3bb4d8 | 9142 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 9143 | if (ret) { |
de3cd117 | 9144 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
9145 | return ret; |
9146 | } | |
9147 | ||
45def77e | 9148 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
9149 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
9150 | ||
9151 | return 0; | |
9152 | } | |
dca7f128 SC |
9153 | |
9154 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
9155 | { | |
45def77e | 9156 | int ret; |
dca7f128 | 9157 | |
dca7f128 | 9158 | if (in) |
45def77e | 9159 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 9160 | else |
45def77e SC |
9161 | ret = kvm_fast_pio_out(vcpu, size, port); |
9162 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
9163 | } |
9164 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 9165 | |
251a5fd6 | 9166 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 9167 | { |
0a3aee0d | 9168 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 9169 | return 0; |
8cfdc000 ZA |
9170 | } |
9171 | ||
9172 | static void tsc_khz_changed(void *data) | |
c8076604 | 9173 | { |
8cfdc000 ZA |
9174 | struct cpufreq_freqs *freq = data; |
9175 | unsigned long khz = 0; | |
9176 | ||
3ebcbd22 AR |
9177 | WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC)); |
9178 | ||
8cfdc000 ZA |
9179 | if (data) |
9180 | khz = freq->new; | |
3ebcbd22 | 9181 | else |
8cfdc000 ZA |
9182 | khz = cpufreq_quick_get(raw_smp_processor_id()); |
9183 | if (!khz) | |
9184 | khz = tsc_khz; | |
0a3aee0d | 9185 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
9186 | } |
9187 | ||
5fa4ec9c | 9188 | #ifdef CONFIG_X86_64 |
0092e434 VK |
9189 | static void kvm_hyperv_tsc_notifier(void) |
9190 | { | |
0092e434 | 9191 | struct kvm *kvm; |
0092e434 VK |
9192 | int cpu; |
9193 | ||
0d9ce162 | 9194 | mutex_lock(&kvm_lock); |
0092e434 VK |
9195 | list_for_each_entry(kvm, &vm_list, vm_list) |
9196 | kvm_make_mclock_inprogress_request(kvm); | |
9197 | ||
6b6fcd28 | 9198 | /* no guest entries from this point */ |
0092e434 VK |
9199 | hyperv_stop_tsc_emulation(); |
9200 | ||
9201 | /* TSC frequency always matches when on Hyper-V */ | |
3ebcbd22 AR |
9202 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
9203 | for_each_present_cpu(cpu) | |
9204 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
9205 | } | |
938c8745 | 9206 | kvm_caps.max_guest_tsc_khz = tsc_khz; |
0092e434 VK |
9207 | |
9208 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
869b4421 | 9209 | __kvm_start_pvclock_update(kvm); |
0092e434 | 9210 | pvclock_update_vm_gtod_copy(kvm); |
6b6fcd28 | 9211 | kvm_end_pvclock_update(kvm); |
0092e434 | 9212 | } |
6b6fcd28 | 9213 | |
0d9ce162 | 9214 | mutex_unlock(&kvm_lock); |
0092e434 | 9215 | } |
5fa4ec9c | 9216 | #endif |
0092e434 | 9217 | |
df24014a | 9218 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 9219 | { |
c8076604 GH |
9220 | struct kvm *kvm; |
9221 | struct kvm_vcpu *vcpu; | |
46808a4c MZ |
9222 | int send_ipi = 0; |
9223 | unsigned long i; | |
c8076604 | 9224 | |
8cfdc000 ZA |
9225 | /* |
9226 | * We allow guests to temporarily run on slowing clocks, | |
9227 | * provided we notify them after, or to run on accelerating | |
9228 | * clocks, provided we notify them before. Thus time never | |
9229 | * goes backwards. | |
9230 | * | |
9231 | * However, we have a problem. We can't atomically update | |
9232 | * the frequency of a given CPU from this function; it is | |
9233 | * merely a notifier, which can be called from any CPU. | |
9234 | * Changing the TSC frequency at arbitrary points in time | |
9235 | * requires a recomputation of local variables related to | |
9236 | * the TSC for each VCPU. We must flag these local variables | |
9237 | * to be updated and be sure the update takes place with the | |
9238 | * new frequency before any guests proceed. | |
9239 | * | |
9240 | * Unfortunately, the combination of hotplug CPU and frequency | |
9241 | * change creates an intractable locking scenario; the order | |
9242 | * of when these callouts happen is undefined with respect to | |
9243 | * CPU hotplug, and they can race with each other. As such, | |
9244 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
9245 | * undefined; you can actually have a CPU frequency change take | |
9246 | * place in between the computation of X and the setting of the | |
9247 | * variable. To protect against this problem, all updates of | |
9248 | * the per_cpu tsc_khz variable are done in an interrupt | |
9249 | * protected IPI, and all callers wishing to update the value | |
9250 | * must wait for a synchronous IPI to complete (which is trivial | |
9251 | * if the caller is on the CPU already). This establishes the | |
9252 | * necessary total order on variable updates. | |
9253 | * | |
9254 | * Note that because a guest time update may take place | |
9255 | * anytime after the setting of the VCPU's request bit, the | |
9256 | * correct TSC value must be set before the request. However, | |
9257 | * to ensure the update actually makes it to any guest which | |
9258 | * starts running in hardware virtualization between the set | |
9259 | * and the acquisition of the spinlock, we must also ping the | |
9260 | * CPU after setting the request bit. | |
9261 | * | |
9262 | */ | |
9263 | ||
df24014a | 9264 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 9265 | |
0d9ce162 | 9266 | mutex_lock(&kvm_lock); |
c8076604 | 9267 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 9268 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 9269 | if (vcpu->cpu != cpu) |
c8076604 | 9270 | continue; |
c285545f | 9271 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 9272 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 9273 | send_ipi = 1; |
c8076604 GH |
9274 | } |
9275 | } | |
0d9ce162 | 9276 | mutex_unlock(&kvm_lock); |
c8076604 GH |
9277 | |
9278 | if (freq->old < freq->new && send_ipi) { | |
9279 | /* | |
9280 | * We upscale the frequency. Must make the guest | |
9281 | * doesn't see old kvmclock values while running with | |
9282 | * the new frequency, otherwise we risk the guest sees | |
9283 | * time go backwards. | |
9284 | * | |
9285 | * In case we update the frequency for another cpu | |
9286 | * (which might be in guest context) send an interrupt | |
9287 | * to kick the cpu out of guest context. Next time | |
9288 | * guest context is entered kvmclock will be updated, | |
9289 | * so the guest will not see stale values. | |
9290 | */ | |
df24014a | 9291 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 9292 | } |
df24014a VK |
9293 | } |
9294 | ||
9295 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
9296 | void *data) | |
9297 | { | |
9298 | struct cpufreq_freqs *freq = data; | |
9299 | int cpu; | |
9300 | ||
9301 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
9302 | return 0; | |
9303 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
9304 | return 0; | |
9305 | ||
9306 | for_each_cpu(cpu, freq->policy->cpus) | |
9307 | __kvmclock_cpufreq_notifier(freq, cpu); | |
9308 | ||
c8076604 GH |
9309 | return 0; |
9310 | } | |
9311 | ||
9312 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
9313 | .notifier_call = kvmclock_cpufreq_notifier |
9314 | }; | |
9315 | ||
251a5fd6 | 9316 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 9317 | { |
251a5fd6 SAS |
9318 | tsc_khz_changed(NULL); |
9319 | return 0; | |
8cfdc000 ZA |
9320 | } |
9321 | ||
b820cc0c ZA |
9322 | static void kvm_timer_init(void) |
9323 | { | |
b820cc0c | 9324 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
741e511b SC |
9325 | max_tsc_khz = tsc_khz; |
9326 | ||
9327 | if (IS_ENABLED(CONFIG_CPU_FREQ)) { | |
9328 | struct cpufreq_policy *policy; | |
9329 | int cpu; | |
9330 | ||
9331 | cpu = get_cpu(); | |
9332 | policy = cpufreq_cpu_get(cpu); | |
9333 | if (policy) { | |
9334 | if (policy->cpuinfo.max_freq) | |
9335 | max_tsc_khz = policy->cpuinfo.max_freq; | |
9336 | cpufreq_cpu_put(policy); | |
9337 | } | |
9338 | put_cpu(); | |
9a11997e | 9339 | } |
b820cc0c ZA |
9340 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
9341 | CPUFREQ_TRANSITION_NOTIFIER); | |
460dd42e | 9342 | |
3ebcbd22 AR |
9343 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
9344 | kvmclock_cpu_online, kvmclock_cpu_down_prep); | |
9345 | } | |
b820cc0c ZA |
9346 | } |
9347 | ||
16e8d74d MT |
9348 | #ifdef CONFIG_X86_64 |
9349 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
9350 | { | |
d828199e | 9351 | struct kvm *kvm; |
d828199e | 9352 | struct kvm_vcpu *vcpu; |
46808a4c | 9353 | unsigned long i; |
d828199e | 9354 | |
0d9ce162 | 9355 | mutex_lock(&kvm_lock); |
d828199e MT |
9356 | list_for_each_entry(kvm, &vm_list, vm_list) |
9357 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 9358 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 9359 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 9360 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
9361 | } |
9362 | ||
9363 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
9364 | ||
3f804f6d TG |
9365 | /* |
9366 | * Indirection to move queue_work() out of the tk_core.seq write held | |
9367 | * region to prevent possible deadlocks against time accessors which | |
9368 | * are invoked with work related locks held. | |
9369 | */ | |
9370 | static void pvclock_irq_work_fn(struct irq_work *w) | |
9371 | { | |
9372 | queue_work(system_long_wq, &pvclock_gtod_work); | |
9373 | } | |
9374 | ||
9375 | static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); | |
9376 | ||
16e8d74d MT |
9377 | /* |
9378 | * Notification about pvclock gtod data update. | |
9379 | */ | |
9380 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
9381 | void *priv) | |
9382 | { | |
9383 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
9384 | struct timekeeper *tk = priv; | |
9385 | ||
9386 | update_pvclock_gtod(tk); | |
9387 | ||
3f804f6d TG |
9388 | /* |
9389 | * Disable master clock if host does not trust, or does not use, | |
9390 | * TSC based clocksource. Delegate queue_work() to irq_work as | |
9391 | * this is invoked with tk_core.seq write held. | |
16e8d74d | 9392 | */ |
b0c39dc6 | 9393 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d | 9394 | atomic_read(&kvm_guest_has_master_clock) != 0) |
3f804f6d | 9395 | irq_work_queue(&pvclock_irq_work); |
16e8d74d MT |
9396 | return 0; |
9397 | } | |
9398 | ||
9399 | static struct notifier_block pvclock_gtod_notifier = { | |
9400 | .notifier_call = pvclock_gtod_notify, | |
9401 | }; | |
9402 | #endif | |
9403 | ||
b7483387 SC |
9404 | static inline void kvm_ops_update(struct kvm_x86_init_ops *ops) |
9405 | { | |
9406 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); | |
9407 | ||
9408 | #define __KVM_X86_OP(func) \ | |
9409 | static_call_update(kvm_x86_##func, kvm_x86_ops.func); | |
9410 | #define KVM_X86_OP(func) \ | |
9411 | WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func) | |
9412 | #define KVM_X86_OP_OPTIONAL __KVM_X86_OP | |
9413 | #define KVM_X86_OP_OPTIONAL_RET0(func) \ | |
9414 | static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \ | |
9415 | (void *)__static_call_return0); | |
9416 | #include <asm/kvm-x86-ops.h> | |
9417 | #undef __KVM_X86_OP | |
9418 | ||
9419 | kvm_pmu_ops_update(ops->pmu_ops); | |
9420 | } | |
9421 | ||
d83420c2 | 9422 | static int kvm_x86_check_processor_compatibility(void) |
3045c483 | 9423 | { |
e4aa7f88 CG |
9424 | int cpu = smp_processor_id(); |
9425 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
9426 | ||
9427 | /* | |
9428 | * Compatibility checks are done when loading KVM and when enabling | |
9429 | * hardware, e.g. during CPU hotplug, to ensure all online CPUs are | |
9430 | * compatible, i.e. KVM should never perform a compatibility check on | |
9431 | * an offline CPU. | |
9432 | */ | |
9433 | WARN_ON(!cpu_online(cpu)); | |
3045c483 | 9434 | |
3045c483 SC |
9435 | if (__cr4_reserved_bits(cpu_has, c) != |
9436 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
9437 | return -EIO; | |
9438 | ||
d83420c2 | 9439 | return static_call(kvm_x86_check_processor_compatibility)(); |
3045c483 SC |
9440 | } |
9441 | ||
d83420c2 | 9442 | static void kvm_x86_check_cpu_compat(void *ret) |
3045c483 | 9443 | { |
d83420c2 | 9444 | *(int *)ret = kvm_x86_check_processor_compatibility(); |
3045c483 SC |
9445 | } |
9446 | ||
3af4a9e6 | 9447 | static int __kvm_x86_vendor_init(struct kvm_x86_init_ops *ops) |
043405e1 | 9448 | { |
94bda2f4 | 9449 | u64 host_pat; |
3045c483 | 9450 | int r, cpu; |
f8c16bba | 9451 | |
afaf0b2f | 9452 | if (kvm_x86_ops.hardware_enable) { |
8d20bd63 | 9453 | pr_err("already loaded vendor module '%s'\n", kvm_x86_ops.name); |
82ffad2d | 9454 | return -EEXIST; |
f8c16bba ZX |
9455 | } |
9456 | ||
b666a4b6 MO |
9457 | /* |
9458 | * KVM explicitly assumes that the guest has an FPU and | |
9459 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
9460 | * vCPU's FPU state as a fxregs_state struct. | |
9461 | */ | |
9462 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
8d20bd63 | 9463 | pr_err("inadequate fpu\n"); |
82ffad2d | 9464 | return -EOPNOTSUPP; |
b666a4b6 MO |
9465 | } |
9466 | ||
5e17b2ee TG |
9467 | if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
9468 | pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n"); | |
82ffad2d | 9469 | return -EOPNOTSUPP; |
b666a4b6 MO |
9470 | } |
9471 | ||
94bda2f4 SC |
9472 | /* |
9473 | * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes | |
9474 | * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something | |
9475 | * other than WB. Note, EPT doesn't utilize the PAT, but don't bother | |
9476 | * with an exception. PAT[0] is set to WB on RESET and also by the | |
9477 | * kernel, i.e. failure indicates a kernel bug or broken firmware. | |
9478 | */ | |
9479 | if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) || | |
9480 | (host_pat & GENMASK(2, 0)) != 6) { | |
8d20bd63 | 9481 | pr_err("host PAT[0] is not WB\n"); |
82ffad2d | 9482 | return -EIO; |
94bda2f4 | 9483 | } |
b666a4b6 | 9484 | |
c9b8b07c SC |
9485 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
9486 | if (!x86_emulator_cache) { | |
8d20bd63 | 9487 | pr_err("failed to allocate cache for x86 emulator\n"); |
82ffad2d | 9488 | return -ENOMEM; |
c9b8b07c SC |
9489 | } |
9490 | ||
7e34fbd0 SC |
9491 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
9492 | if (!user_return_msrs) { | |
8d20bd63 | 9493 | pr_err("failed to allocate percpu kvm_user_return_msrs\n"); |
82ffad2d | 9494 | r = -ENOMEM; |
c9b8b07c | 9495 | goto out_free_x86_emulator_cache; |
013f6a5d | 9496 | } |
e5fda4bb | 9497 | kvm_nr_uret_msrs = 0; |
013f6a5d | 9498 | |
1d0e8480 | 9499 | r = kvm_mmu_vendor_module_init(); |
97db56ce | 9500 | if (r) |
013f6a5d | 9501 | goto out_free_percpu; |
97db56ce | 9502 | |
cfc48181 | 9503 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 9504 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
938c8745 | 9505 | kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
cfc48181 | 9506 | } |
2acf923e | 9507 | |
b7483387 SC |
9508 | rdmsrl_safe(MSR_EFER, &host_efer); |
9509 | ||
9510 | if (boot_cpu_has(X86_FEATURE_XSAVES)) | |
9511 | rdmsrl(MSR_IA32_XSS, host_xss); | |
9512 | ||
8911ce66 | 9513 | kvm_init_pmu_capability(ops->pmu_ops); |
b7483387 SC |
9514 | |
9515 | r = ops->hardware_setup(); | |
9516 | if (r != 0) | |
9517 | goto out_mmu_exit; | |
9518 | ||
d83420c2 SC |
9519 | kvm_ops_update(ops); |
9520 | ||
3045c483 | 9521 | for_each_online_cpu(cpu) { |
d83420c2 | 9522 | smp_call_function_single(cpu, kvm_x86_check_cpu_compat, &r, 1); |
3045c483 | 9523 | if (r < 0) |
d83420c2 | 9524 | goto out_unwind_ops; |
3045c483 SC |
9525 | } |
9526 | ||
b7483387 SC |
9527 | /* |
9528 | * Point of no return! DO NOT add error paths below this point unless | |
9529 | * absolutely necessary, as most operations from this point forward | |
9530 | * require unwinding. | |
9531 | */ | |
1935542a SC |
9532 | kvm_timer_init(); |
9533 | ||
0c5f81da | 9534 | if (pi_inject_timer == -1) |
04d4e665 | 9535 | pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER); |
16e8d74d MT |
9536 | #ifdef CONFIG_X86_64 |
9537 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 9538 | |
5fa4ec9c | 9539 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 9540 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
9541 | #endif |
9542 | ||
b7483387 SC |
9543 | kvm_register_perf_callbacks(ops->handle_intel_pt_intr); |
9544 | ||
9545 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) | |
9546 | kvm_caps.supported_xss = 0; | |
9547 | ||
9548 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) | |
9549 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
9550 | #undef __kvm_cpu_cap_has | |
9551 | ||
9552 | if (kvm_caps.has_tsc_control) { | |
9553 | /* | |
9554 | * Make sure the user can only configure tsc_khz values that | |
9555 | * fit into a signed integer. | |
9556 | * A min value is not calculated because it will always | |
9557 | * be 1 on all machines. | |
9558 | */ | |
9559 | u64 max = min(0x7fffffffULL, | |
9560 | __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz)); | |
9561 | kvm_caps.max_guest_tsc_khz = max; | |
9562 | } | |
9563 | kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits; | |
b1932c5c | 9564 | kvm_init_msr_lists(); |
f8c16bba | 9565 | return 0; |
56c6d28a | 9566 | |
d83420c2 SC |
9567 | out_unwind_ops: |
9568 | kvm_x86_ops.hardware_enable = NULL; | |
9569 | static_call(kvm_x86_hardware_unsetup)(); | |
b7483387 SC |
9570 | out_mmu_exit: |
9571 | kvm_mmu_vendor_module_exit(); | |
013f6a5d | 9572 | out_free_percpu: |
7e34fbd0 | 9573 | free_percpu(user_return_msrs); |
c9b8b07c SC |
9574 | out_free_x86_emulator_cache: |
9575 | kmem_cache_destroy(x86_emulator_cache); | |
56c6d28a | 9576 | return r; |
043405e1 | 9577 | } |
8776e519 | 9578 | |
3af4a9e6 SC |
9579 | int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops) |
9580 | { | |
9581 | int r; | |
9582 | ||
9583 | mutex_lock(&vendor_module_lock); | |
9584 | r = __kvm_x86_vendor_init(ops); | |
9585 | mutex_unlock(&vendor_module_lock); | |
9586 | ||
9587 | return r; | |
9588 | } | |
4f8396b9 | 9589 | EXPORT_SYMBOL_GPL(kvm_x86_vendor_init); |
8776e519 | 9590 | |
4f8396b9 | 9591 | void kvm_x86_vendor_exit(void) |
f8c16bba | 9592 | { |
b7483387 SC |
9593 | kvm_unregister_perf_callbacks(); |
9594 | ||
0092e434 | 9595 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 9596 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
9597 | clear_hv_tscchange_cb(); |
9598 | #endif | |
cef84c30 | 9599 | kvm_lapic_exit(); |
ff9d07a0 | 9600 | |
3ebcbd22 | 9601 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
888d256e JK |
9602 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, |
9603 | CPUFREQ_TRANSITION_NOTIFIER); | |
3ebcbd22 AR |
9604 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
9605 | } | |
16e8d74d MT |
9606 | #ifdef CONFIG_X86_64 |
9607 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
3f804f6d | 9608 | irq_work_sync(&pvclock_irq_work); |
594b27e6 | 9609 | cancel_work_sync(&pvclock_gtod_work); |
16e8d74d | 9610 | #endif |
b7483387 | 9611 | static_call(kvm_x86_hardware_unsetup)(); |
1d0e8480 | 9612 | kvm_mmu_vendor_module_exit(); |
7e34fbd0 | 9613 | free_percpu(user_return_msrs); |
dfdc0a71 | 9614 | kmem_cache_destroy(x86_emulator_cache); |
b59b153d | 9615 | #ifdef CONFIG_KVM_XEN |
c462f859 | 9616 | static_key_deferred_flush(&kvm_xen_enabled); |
7d6bbebb | 9617 | WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); |
b59b153d | 9618 | #endif |
3af4a9e6 SC |
9619 | mutex_lock(&vendor_module_lock); |
9620 | kvm_x86_ops.hardware_enable = NULL; | |
9621 | mutex_unlock(&vendor_module_lock); | |
56c6d28a | 9622 | } |
4f8396b9 | 9623 | EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit); |
f8c16bba | 9624 | |
1460179d | 9625 | static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason) |
8776e519 | 9626 | { |
91b99ea7 SC |
9627 | /* |
9628 | * The vCPU has halted, e.g. executed HLT. Update the run state if the | |
9629 | * local APIC is in-kernel, the run loop will detect the non-runnable | |
9630 | * state and halt the vCPU. Exit to userspace if the local APIC is | |
9631 | * managed by userspace, in which case userspace is responsible for | |
9632 | * handling wake events. | |
9633 | */ | |
8776e519 | 9634 | ++vcpu->stat.halt_exits; |
35754c98 | 9635 | if (lapic_in_kernel(vcpu)) { |
647daca2 | 9636 | vcpu->arch.mp_state = state; |
8776e519 HB |
9637 | return 1; |
9638 | } else { | |
647daca2 | 9639 | vcpu->run->exit_reason = reason; |
8776e519 HB |
9640 | return 0; |
9641 | } | |
9642 | } | |
647daca2 | 9643 | |
1460179d | 9644 | int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu) |
647daca2 | 9645 | { |
1460179d | 9646 | return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); |
647daca2 | 9647 | } |
1460179d | 9648 | EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip); |
5cb56059 JS |
9649 | |
9650 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
9651 | { | |
6affcbed KH |
9652 | int ret = kvm_skip_emulated_instruction(vcpu); |
9653 | /* | |
9654 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
9655 | * KVM_EXIT_DEBUG here. | |
9656 | */ | |
1460179d | 9657 | return kvm_emulate_halt_noskip(vcpu) && ret; |
5cb56059 | 9658 | } |
8776e519 HB |
9659 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
9660 | ||
647daca2 TL |
9661 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) |
9662 | { | |
9663 | int ret = kvm_skip_emulated_instruction(vcpu); | |
9664 | ||
1460179d SC |
9665 | return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, |
9666 | KVM_EXIT_AP_RESET_HOLD) && ret; | |
647daca2 TL |
9667 | } |
9668 | EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); | |
9669 | ||
8ef81a9a | 9670 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
9671 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
9672 | unsigned long clock_type) | |
9673 | { | |
9674 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 9675 | struct timespec64 ts; |
80fbd89c | 9676 | u64 cycle; |
55dd00a7 MT |
9677 | int ret; |
9678 | ||
9679 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
9680 | return -KVM_EOPNOTSUPP; | |
9681 | ||
3a55f729 AR |
9682 | /* |
9683 | * When tsc is in permanent catchup mode guests won't be able to use | |
9684 | * pvclock_read_retry loop to get consistent view of pvclock | |
9685 | */ | |
9686 | if (vcpu->arch.tsc_always_catchup) | |
9687 | return -KVM_EOPNOTSUPP; | |
9688 | ||
7ca7f3b9 | 9689 | if (!kvm_get_walltime_and_clockread(&ts, &cycle)) |
55dd00a7 MT |
9690 | return -KVM_EOPNOTSUPP; |
9691 | ||
9692 | clock_pairing.sec = ts.tv_sec; | |
9693 | clock_pairing.nsec = ts.tv_nsec; | |
9694 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
9695 | clock_pairing.flags = 0; | |
bcbfbd8e | 9696 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
9697 | |
9698 | ret = 0; | |
9699 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
9700 | sizeof(struct kvm_clock_pairing))) | |
9701 | ret = -KVM_EFAULT; | |
9702 | ||
9703 | return ret; | |
9704 | } | |
8ef81a9a | 9705 | #endif |
55dd00a7 | 9706 | |
6aef266c SV |
9707 | /* |
9708 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
9709 | * | |
9710 | * @apicid - apicid of vcpu to be kicked. | |
9711 | */ | |
9d68c6f6 | 9712 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid) |
6aef266c | 9713 | { |
8a414f94 VK |
9714 | /* |
9715 | * All other fields are unused for APIC_DM_REMRD, but may be consumed by | |
9716 | * common code, e.g. for tracing. Defer initialization to the compiler. | |
9717 | */ | |
9718 | struct kvm_lapic_irq lapic_irq = { | |
9719 | .delivery_mode = APIC_DM_REMRD, | |
9720 | .dest_mode = APIC_DEST_PHYSICAL, | |
9721 | .shorthand = APIC_DEST_NOSHORT, | |
9722 | .dest_id = apicid, | |
9723 | }; | |
6aef266c | 9724 | |
795a149e | 9725 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
9726 | } |
9727 | ||
4e19c36f SS |
9728 | bool kvm_apicv_activated(struct kvm *kvm) |
9729 | { | |
9730 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
9731 | } | |
9732 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
9733 | ||
d5fa597e ML |
9734 | bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu) |
9735 | { | |
9736 | ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons); | |
9737 | ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu); | |
9738 | ||
9739 | return (vm_reasons | vcpu_reasons) == 0; | |
9740 | } | |
9741 | EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated); | |
4f4c4a3e SC |
9742 | |
9743 | static void set_or_clear_apicv_inhibit(unsigned long *inhibits, | |
9744 | enum kvm_apicv_inhibit reason, bool set) | |
9745 | { | |
9746 | if (set) | |
9747 | __set_bit(reason, inhibits); | |
9748 | else | |
9749 | __clear_bit(reason, inhibits); | |
9750 | ||
9751 | trace_kvm_apicv_inhibit_changed(reason, set, *inhibits); | |
9752 | } | |
9753 | ||
4651fc56 | 9754 | static void kvm_apicv_init(struct kvm *kvm) |
4e19c36f | 9755 | { |
4f4c4a3e SC |
9756 | unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons; |
9757 | ||
187c8833 | 9758 | init_rwsem(&kvm->arch.apicv_update_lock); |
b0a1637f | 9759 | |
4f4c4a3e SC |
9760 | set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true); |
9761 | ||
ef8b4b72 | 9762 | if (!enable_apicv) |
4f4c4a3e | 9763 | set_or_clear_apicv_inhibit(inhibits, |
80f0497c | 9764 | APICV_INHIBIT_REASON_DISABLE, true); |
4e19c36f | 9765 | } |
4e19c36f | 9766 | |
4a7132ef | 9767 | static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) |
71506297 WL |
9768 | { |
9769 | struct kvm_vcpu *target = NULL; | |
9770 | struct kvm_apic_map *map; | |
9771 | ||
4a7132ef WL |
9772 | vcpu->stat.directed_yield_attempted++; |
9773 | ||
72b268a8 WL |
9774 | if (single_task_running()) |
9775 | goto no_yield; | |
9776 | ||
71506297 | 9777 | rcu_read_lock(); |
4a7132ef | 9778 | map = rcu_dereference(vcpu->kvm->arch.apic_map); |
71506297 WL |
9779 | |
9780 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
9781 | target = map->phys_map[dest_id]->vcpu; | |
9782 | ||
9783 | rcu_read_unlock(); | |
9784 | ||
4a7132ef WL |
9785 | if (!target || !READ_ONCE(target->ready)) |
9786 | goto no_yield; | |
9787 | ||
a1fa4cbd WL |
9788 | /* Ignore requests to yield to self */ |
9789 | if (vcpu == target) | |
9790 | goto no_yield; | |
9791 | ||
4a7132ef WL |
9792 | if (kvm_vcpu_yield_to(target) <= 0) |
9793 | goto no_yield; | |
9794 | ||
9795 | vcpu->stat.directed_yield_successful++; | |
9796 | ||
9797 | no_yield: | |
9798 | return; | |
71506297 WL |
9799 | } |
9800 | ||
0dbb1123 AK |
9801 | static int complete_hypercall_exit(struct kvm_vcpu *vcpu) |
9802 | { | |
9803 | u64 ret = vcpu->run->hypercall.ret; | |
9804 | ||
9805 | if (!is_64_bit_mode(vcpu)) | |
9806 | ret = (u32)ret; | |
9807 | kvm_rax_write(vcpu, ret); | |
9808 | ++vcpu->stat.hypercalls; | |
9809 | return kvm_skip_emulated_instruction(vcpu); | |
9810 | } | |
9811 | ||
8776e519 HB |
9812 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
9813 | { | |
9814 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 9815 | int op_64_bit; |
8776e519 | 9816 | |
23200b7a JM |
9817 | if (kvm_xen_hypercall_enabled(vcpu->kvm)) |
9818 | return kvm_xen_hypercall(vcpu); | |
9819 | ||
8f014550 | 9820 | if (kvm_hv_hypercall_enabled(vcpu)) |
696ca779 | 9821 | return kvm_hv_hypercall(vcpu); |
55cd8e5a | 9822 | |
de3cd117 SC |
9823 | nr = kvm_rax_read(vcpu); |
9824 | a0 = kvm_rbx_read(vcpu); | |
9825 | a1 = kvm_rcx_read(vcpu); | |
9826 | a2 = kvm_rdx_read(vcpu); | |
9827 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 9828 | |
229456fc | 9829 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 9830 | |
b5aead00 | 9831 | op_64_bit = is_64_bit_hypercall(vcpu); |
a449c7aa | 9832 | if (!op_64_bit) { |
8776e519 HB |
9833 | nr &= 0xFFFFFFFF; |
9834 | a0 &= 0xFFFFFFFF; | |
9835 | a1 &= 0xFFFFFFFF; | |
9836 | a2 &= 0xFFFFFFFF; | |
9837 | a3 &= 0xFFFFFFFF; | |
9838 | } | |
9839 | ||
b3646477 | 9840 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { |
07708c4a | 9841 | ret = -KVM_EPERM; |
696ca779 | 9842 | goto out; |
07708c4a JK |
9843 | } |
9844 | ||
66570e96 OU |
9845 | ret = -KVM_ENOSYS; |
9846 | ||
8776e519 | 9847 | switch (nr) { |
b93463aa AK |
9848 | case KVM_HC_VAPIC_POLL_IRQ: |
9849 | ret = 0; | |
9850 | break; | |
6aef266c | 9851 | case KVM_HC_KICK_CPU: |
66570e96 OU |
9852 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
9853 | break; | |
9854 | ||
9d68c6f6 | 9855 | kvm_pv_kick_cpu_op(vcpu->kvm, a1); |
4a7132ef | 9856 | kvm_sched_yield(vcpu, a1); |
6aef266c SV |
9857 | ret = 0; |
9858 | break; | |
8ef81a9a | 9859 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
9860 | case KVM_HC_CLOCK_PAIRING: |
9861 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
9862 | break; | |
1ed199a4 | 9863 | #endif |
4180bf1b | 9864 | case KVM_HC_SEND_IPI: |
66570e96 OU |
9865 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
9866 | break; | |
9867 | ||
4180bf1b WL |
9868 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
9869 | break; | |
71506297 | 9870 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
9871 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
9872 | break; | |
9873 | ||
4a7132ef | 9874 | kvm_sched_yield(vcpu, a0); |
71506297 WL |
9875 | ret = 0; |
9876 | break; | |
0dbb1123 AK |
9877 | case KVM_HC_MAP_GPA_RANGE: { |
9878 | u64 gpa = a0, npages = a1, attrs = a2; | |
9879 | ||
9880 | ret = -KVM_ENOSYS; | |
9881 | if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) | |
9882 | break; | |
9883 | ||
9884 | if (!PAGE_ALIGNED(gpa) || !npages || | |
9885 | gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { | |
9886 | ret = -KVM_EINVAL; | |
9887 | break; | |
9888 | } | |
9889 | ||
9890 | vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; | |
9891 | vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; | |
9892 | vcpu->run->hypercall.args[0] = gpa; | |
9893 | vcpu->run->hypercall.args[1] = npages; | |
9894 | vcpu->run->hypercall.args[2] = attrs; | |
e65733b5 OU |
9895 | vcpu->run->hypercall.flags = 0; |
9896 | if (op_64_bit) | |
9897 | vcpu->run->hypercall.flags |= KVM_EXIT_HYPERCALL_LONG_MODE; | |
9898 | ||
9899 | WARN_ON_ONCE(vcpu->run->hypercall.flags & KVM_EXIT_HYPERCALL_MBZ); | |
0dbb1123 AK |
9900 | vcpu->arch.complete_userspace_io = complete_hypercall_exit; |
9901 | return 0; | |
9902 | } | |
8776e519 HB |
9903 | default: |
9904 | ret = -KVM_ENOSYS; | |
9905 | break; | |
9906 | } | |
696ca779 | 9907 | out: |
a449c7aa NA |
9908 | if (!op_64_bit) |
9909 | ret = (u32)ret; | |
de3cd117 | 9910 | kvm_rax_write(vcpu, ret); |
6356ee0c | 9911 | |
f11c3a8d | 9912 | ++vcpu->stat.hypercalls; |
6356ee0c | 9913 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
9914 | } |
9915 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
9916 | ||
b6785def | 9917 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 9918 | { |
d6aa1000 | 9919 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 9920 | char instruction[3]; |
5fdbf976 | 9921 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 9922 | |
f1a9761f OU |
9923 | /* |
9924 | * If the quirk is disabled, synthesize a #UD and let the guest pick up | |
9925 | * the pieces. | |
9926 | */ | |
9927 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) { | |
9928 | ctxt->exception.error_code_valid = false; | |
9929 | ctxt->exception.vector = UD_VECTOR; | |
9930 | ctxt->have_exception = true; | |
9931 | return X86EMUL_PROPAGATE_FAULT; | |
9932 | } | |
9933 | ||
b3646477 | 9934 | static_call(kvm_x86_patch_hypercall)(vcpu, instruction); |
8776e519 | 9935 | |
ce2e852e DV |
9936 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
9937 | &ctxt->exception); | |
8776e519 HB |
9938 | } |
9939 | ||
851ba692 | 9940 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9941 | { |
782d422b MG |
9942 | return vcpu->run->request_interrupt_window && |
9943 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
9944 | } |
9945 | ||
8d25b7be | 9946 | /* Called within kvm->srcu read side. */ |
851ba692 | 9947 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9948 | { |
851ba692 AK |
9949 | struct kvm_run *kvm_run = vcpu->run; |
9950 | ||
c5063551 | 9951 | kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu); |
2d3ad1f4 | 9952 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 9953 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
f3d1436d | 9954 | |
127a457a MG |
9955 | kvm_run->ready_for_interrupt_injection = |
9956 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 9957 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
15aad3be CQ |
9958 | |
9959 | if (is_smm(vcpu)) | |
9960 | kvm_run->flags |= KVM_RUN_X86_SMM; | |
b6c7a5dc HB |
9961 | } |
9962 | ||
95ba8273 GN |
9963 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
9964 | { | |
9965 | int max_irr, tpr; | |
9966 | ||
afaf0b2f | 9967 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
9968 | return; |
9969 | ||
bce87cce | 9970 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
9971 | return; |
9972 | ||
ce0a58f4 | 9973 | if (vcpu->arch.apic->apicv_active) |
d62caabb AS |
9974 | return; |
9975 | ||
8db3baa2 GN |
9976 | if (!vcpu->arch.apic->vapic_addr) |
9977 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
9978 | else | |
9979 | max_irr = -1; | |
95ba8273 GN |
9980 | |
9981 | if (max_irr != -1) | |
9982 | max_irr >>= 4; | |
9983 | ||
9984 | tpr = kvm_lapic_get_cr8(vcpu); | |
9985 | ||
b3646477 | 9986 | static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); |
95ba8273 GN |
9987 | } |
9988 | ||
b97f0745 | 9989 | |
cb6a32c2 SC |
9990 | int kvm_check_nested_events(struct kvm_vcpu *vcpu) |
9991 | { | |
92e7d5c8 | 9992 | if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
cb6a32c2 SC |
9993 | kvm_x86_ops.nested_ops->triple_fault(vcpu); |
9994 | return 1; | |
9995 | } | |
9996 | ||
9997 | return kvm_x86_ops.nested_ops->check_events(vcpu); | |
9998 | } | |
9999 | ||
b97f0745 ML |
10000 | static void kvm_inject_exception(struct kvm_vcpu *vcpu) |
10001 | { | |
6c41468c SC |
10002 | /* |
10003 | * Suppress the error code if the vCPU is in Real Mode, as Real Mode | |
10004 | * exceptions don't report error codes. The presence of an error code | |
10005 | * is carried with the exception and only stripped when the exception | |
10006 | * is injected as intercepted #PF VM-Exits for AMD's Paged Real Mode do | |
10007 | * report an error code despite the CPU being in Real Mode. | |
10008 | */ | |
10009 | vcpu->arch.exception.has_error_code &= is_protmode(vcpu); | |
10010 | ||
d4963e31 | 10011 | trace_kvm_inj_exception(vcpu->arch.exception.vector, |
a61d7c54 SC |
10012 | vcpu->arch.exception.has_error_code, |
10013 | vcpu->arch.exception.error_code, | |
10014 | vcpu->arch.exception.injected); | |
10015 | ||
6ad75c5c | 10016 | static_call(kvm_x86_inject_exception)(vcpu); |
b97f0745 ML |
10017 | } |
10018 | ||
e746c1f1 SC |
10019 | /* |
10020 | * Check for any event (interrupt or exception) that is ready to be injected, | |
10021 | * and if there is at least one event, inject the event with the highest | |
10022 | * priority. This handles both "pending" events, i.e. events that have never | |
10023 | * been injected into the guest, and "injected" events, i.e. events that were | |
10024 | * injected as part of a previous VM-Enter, but weren't successfully delivered | |
10025 | * and need to be re-injected. | |
10026 | * | |
10027 | * Note, this is not guaranteed to be invoked on a guest instruction boundary, | |
10028 | * i.e. doesn't guarantee that there's an event window in the guest. KVM must | |
10029 | * be able to inject exceptions in the "middle" of an instruction, and so must | |
10030 | * also be able to re-inject NMIs and IRQs in the middle of an instruction. | |
10031 | * I.e. for exceptions and re-injected events, NOT invoking this on instruction | |
10032 | * boundaries is necessary and correct. | |
10033 | * | |
10034 | * For simplicity, KVM uses a single path to inject all events (except events | |
10035 | * that are injected directly from L1 to L2) and doesn't explicitly track | |
10036 | * instruction boundaries for asynchronous events. However, because VM-Exits | |
10037 | * that can occur during instruction execution typically result in KVM skipping | |
10038 | * the instruction or injecting an exception, e.g. instruction and exception | |
10039 | * intercepts, and because pending exceptions have higher priority than pending | |
10040 | * interrupts, KVM still honors instruction boundaries in most scenarios. | |
10041 | * | |
10042 | * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip | |
10043 | * the instruction or inject an exception, then KVM can incorrecty inject a new | |
10044 | * asynchrounous event if the event became pending after the CPU fetched the | |
10045 | * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation) | |
10046 | * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be | |
10047 | * injected on the restarted instruction instead of being deferred until the | |
10048 | * instruction completes. | |
10049 | * | |
10050 | * In practice, this virtualization hole is unlikely to be observed by the | |
10051 | * guest, and even less likely to cause functional problems. To detect the | |
10052 | * hole, the guest would have to trigger an event on a side effect of an early | |
10053 | * phase of instruction execution, e.g. on the instruction fetch from memory. | |
10054 | * And for it to be a functional problem, the guest would need to depend on the | |
10055 | * ordering between that side effect, the instruction completing, _and_ the | |
10056 | * delivery of the asynchronous event. | |
10057 | */ | |
10058 | static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu, | |
10059 | bool *req_immediate_exit) | |
95ba8273 | 10060 | { |
28360f88 | 10061 | bool can_inject; |
b6b8a145 JK |
10062 | int r; |
10063 | ||
6c593b52 SC |
10064 | /* |
10065 | * Process nested events first, as nested VM-Exit supercedes event | |
10066 | * re-injection. If there's an event queued for re-injection, it will | |
10067 | * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit. | |
10068 | */ | |
10069 | if (is_guest_mode(vcpu)) | |
10070 | r = kvm_check_nested_events(vcpu); | |
10071 | else | |
10072 | r = 0; | |
664f8e26 WL |
10073 | |
10074 | /* | |
6c593b52 SC |
10075 | * Re-inject exceptions and events *especially* if immediate entry+exit |
10076 | * to/from L2 is needed, as any event that has already been injected | |
10077 | * into L2 needs to complete its lifecycle before injecting a new event. | |
10078 | * | |
10079 | * Don't re-inject an NMI or interrupt if there is a pending exception. | |
10080 | * This collision arises if an exception occurred while vectoring the | |
10081 | * injected event, KVM intercepted said exception, and KVM ultimately | |
10082 | * determined the fault belongs to the guest and queues the exception | |
10083 | * for injection back into the guest. | |
10084 | * | |
10085 | * "Injected" interrupts can also collide with pending exceptions if | |
10086 | * userspace ignores the "ready for injection" flag and blindly queues | |
10087 | * an interrupt. In that case, prioritizing the exception is correct, | |
10088 | * as the exception "occurred" before the exit to userspace. Trap-like | |
10089 | * exceptions, e.g. most #DBs, have higher priority than interrupts. | |
10090 | * And while fault-like exceptions, e.g. #GP and #PF, are the lowest | |
10091 | * priority, they're only generated (pended) during instruction | |
10092 | * execution, and interrupts are recognized at instruction boundaries. | |
10093 | * Thus a pending fault-like exception means the fault occurred on the | |
10094 | * *previous* instruction and must be serviced prior to recognizing any | |
10095 | * new events in order to fully complete the previous instruction. | |
664f8e26 | 10096 | */ |
6c593b52 SC |
10097 | if (vcpu->arch.exception.injected) |
10098 | kvm_inject_exception(vcpu); | |
7709aba8 | 10099 | else if (kvm_is_exception_pending(vcpu)) |
6c593b52 SC |
10100 | ; /* see above */ |
10101 | else if (vcpu->arch.nmi_injected) | |
10102 | static_call(kvm_x86_inject_nmi)(vcpu); | |
10103 | else if (vcpu->arch.interrupt.injected) | |
10104 | static_call(kvm_x86_inject_irq)(vcpu, true); | |
664f8e26 | 10105 | |
6c593b52 SC |
10106 | /* |
10107 | * Exceptions that morph to VM-Exits are handled above, and pending | |
10108 | * exceptions on top of injected exceptions that do not VM-Exit should | |
10109 | * either morph to #DF or, sadly, override the injected exception. | |
10110 | */ | |
3b82b8d7 SC |
10111 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
10112 | vcpu->arch.exception.pending); | |
10113 | ||
1a680e35 | 10114 | /* |
6c593b52 SC |
10115 | * Bail if immediate entry+exit to/from the guest is needed to complete |
10116 | * nested VM-Enter or event re-injection so that a different pending | |
10117 | * event can be serviced (or if KVM needs to exit to userspace). | |
10118 | * | |
10119 | * Otherwise, continue processing events even if VM-Exit occurred. The | |
10120 | * VM-Exit will have cleared exceptions that were meant for L2, but | |
10121 | * there may now be events that can be injected into L1. | |
1a680e35 | 10122 | */ |
6c593b52 SC |
10123 | if (r < 0) |
10124 | goto out; | |
664f8e26 | 10125 | |
7709aba8 SC |
10126 | /* |
10127 | * A pending exception VM-Exit should either result in nested VM-Exit | |
10128 | * or force an immediate re-entry and exit to/from L2, and exception | |
10129 | * VM-Exits cannot be injected (flag should _never_ be set). | |
10130 | */ | |
10131 | WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected || | |
10132 | vcpu->arch.exception_vmexit.pending); | |
10133 | ||
28360f88 SC |
10134 | /* |
10135 | * New events, other than exceptions, cannot be injected if KVM needs | |
10136 | * to re-inject a previous event. See above comments on re-injecting | |
10137 | * for why pending exceptions get priority. | |
10138 | */ | |
10139 | can_inject = !kvm_event_needs_reinjection(vcpu); | |
664f8e26 | 10140 | |
b59bb7bd | 10141 | if (vcpu->arch.exception.pending) { |
5623f751 SC |
10142 | /* |
10143 | * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS | |
10144 | * value pushed on the stack. Trap-like exception and all #DBs | |
10145 | * leave RF as-is (KVM follows Intel's behavior in this regard; | |
10146 | * AMD states that code breakpoint #DBs excplitly clear RF=0). | |
10147 | * | |
10148 | * Note, most versions of Intel's SDM and AMD's APM incorrectly | |
10149 | * describe the behavior of General Detect #DBs, which are | |
10150 | * fault-like. They do _not_ set RF, a la code breakpoints. | |
10151 | */ | |
d4963e31 | 10152 | if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT) |
d6e8c854 NA |
10153 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | |
10154 | X86_EFLAGS_RF); | |
10155 | ||
d4963e31 SC |
10156 | if (vcpu->arch.exception.vector == DB_VECTOR) { |
10157 | kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception); | |
f10c729f JM |
10158 | if (vcpu->arch.dr7 & DR7_GD) { |
10159 | vcpu->arch.dr7 &= ~DR7_GD; | |
10160 | kvm_update_dr7(vcpu); | |
10161 | } | |
6bdf0662 NA |
10162 | } |
10163 | ||
b97f0745 | 10164 | kvm_inject_exception(vcpu); |
a61d7c54 SC |
10165 | |
10166 | vcpu->arch.exception.pending = false; | |
10167 | vcpu->arch.exception.injected = true; | |
10168 | ||
c6b22f59 | 10169 | can_inject = false; |
1a680e35 LA |
10170 | } |
10171 | ||
61e5f69e ML |
10172 | /* Don't inject interrupts if the user asked to avoid doing so */ |
10173 | if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) | |
10174 | return 0; | |
10175 | ||
c9d40913 PB |
10176 | /* |
10177 | * Finally, inject interrupt events. If an event cannot be injected | |
10178 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
10179 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
10180 | * and can architecturally be injected, but we cannot do it right now: | |
10181 | * an interrupt could have arrived just now and we have to inject it | |
10182 | * as a vmexit, or there could already an event in the queue, which is | |
10183 | * indicated by can_inject. In that case we request an immediate exit | |
10184 | * in order to make progress and get back here for another iteration. | |
10185 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
10186 | */ | |
31e83e21 | 10187 | #ifdef CONFIG_KVM_SMM |
c9d40913 | 10188 | if (vcpu->arch.smi_pending) { |
b3646477 | 10189 | r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 10190 | if (r < 0) |
a5f6909a | 10191 | goto out; |
c9d40913 PB |
10192 | if (r) { |
10193 | vcpu->arch.smi_pending = false; | |
10194 | ++vcpu->arch.smi_count; | |
10195 | enter_smm(vcpu); | |
10196 | can_inject = false; | |
10197 | } else | |
b3646477 | 10198 | static_call(kvm_x86_enable_smi_window)(vcpu); |
c9d40913 | 10199 | } |
31e83e21 | 10200 | #endif |
c9d40913 PB |
10201 | |
10202 | if (vcpu->arch.nmi_pending) { | |
b3646477 | 10203 | r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 10204 | if (r < 0) |
a5f6909a | 10205 | goto out; |
c9d40913 PB |
10206 | if (r) { |
10207 | --vcpu->arch.nmi_pending; | |
10208 | vcpu->arch.nmi_injected = true; | |
e27bc044 | 10209 | static_call(kvm_x86_inject_nmi)(vcpu); |
c9d40913 | 10210 | can_inject = false; |
b3646477 | 10211 | WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); |
c9d40913 PB |
10212 | } |
10213 | if (vcpu->arch.nmi_pending) | |
b3646477 | 10214 | static_call(kvm_x86_enable_nmi_window)(vcpu); |
c9d40913 | 10215 | } |
1a680e35 | 10216 | |
c9d40913 | 10217 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
b3646477 | 10218 | r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 10219 | if (r < 0) |
a5f6909a | 10220 | goto out; |
c9d40913 | 10221 | if (r) { |
bf672720 ML |
10222 | int irq = kvm_cpu_get_interrupt(vcpu); |
10223 | ||
10224 | if (!WARN_ON_ONCE(irq == -1)) { | |
10225 | kvm_queue_interrupt(vcpu, irq, false); | |
10226 | static_call(kvm_x86_inject_irq)(vcpu, false); | |
10227 | WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); | |
10228 | } | |
c9d40913 PB |
10229 | } |
10230 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
b3646477 | 10231 | static_call(kvm_x86_enable_irq_window)(vcpu); |
95ba8273 | 10232 | } |
ee2cd4b7 | 10233 | |
c9d40913 | 10234 | if (is_guest_mode(vcpu) && |
5b4ac1a1 PB |
10235 | kvm_x86_ops.nested_ops->has_events && |
10236 | kvm_x86_ops.nested_ops->has_events(vcpu)) | |
c9d40913 PB |
10237 | *req_immediate_exit = true; |
10238 | ||
dea0d5a2 SC |
10239 | /* |
10240 | * KVM must never queue a new exception while injecting an event; KVM | |
10241 | * is done emulating and should only propagate the to-be-injected event | |
10242 | * to the VMCS/VMCB. Queueing a new exception can put the vCPU into an | |
10243 | * infinite loop as KVM will bail from VM-Enter to inject the pending | |
10244 | * exception and start the cycle all over. | |
10245 | * | |
10246 | * Exempt triple faults as they have special handling and won't put the | |
10247 | * vCPU into an infinite loop. Triple fault can be queued when running | |
10248 | * VMX without unrestricted guest, as that requires KVM to emulate Real | |
10249 | * Mode events (see kvm_inject_realmode_interrupt()). | |
10250 | */ | |
10251 | WARN_ON_ONCE(vcpu->arch.exception.pending || | |
10252 | vcpu->arch.exception_vmexit.pending); | |
a5f6909a | 10253 | return 0; |
c9d40913 | 10254 | |
a5f6909a JM |
10255 | out: |
10256 | if (r == -EBUSY) { | |
10257 | *req_immediate_exit = true; | |
10258 | r = 0; | |
10259 | } | |
10260 | return r; | |
95ba8273 GN |
10261 | } |
10262 | ||
7460fb4a AK |
10263 | static void process_nmi(struct kvm_vcpu *vcpu) |
10264 | { | |
400fee8c | 10265 | unsigned int limit; |
7460fb4a AK |
10266 | |
10267 | /* | |
400fee8c SC |
10268 | * x86 is limited to one NMI pending, but because KVM can't react to |
10269 | * incoming NMIs as quickly as bare metal, e.g. if the vCPU is | |
10270 | * scheduled out, KVM needs to play nice with two queued NMIs showing | |
10271 | * up at the same time. To handle this scenario, allow two NMIs to be | |
10272 | * (temporarily) pending so long as NMIs are not blocked and KVM is not | |
10273 | * waiting for a previous NMI injection to complete (which effectively | |
10274 | * blocks NMIs). KVM will immediately inject one of the two NMIs, and | |
10275 | * will request an NMI window to handle the second NMI. | |
7460fb4a | 10276 | */ |
b3646477 | 10277 | if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a | 10278 | limit = 1; |
400fee8c SC |
10279 | else |
10280 | limit = 2; | |
7460fb4a | 10281 | |
fa4c027a SS |
10282 | /* |
10283 | * Adjust the limit to account for pending virtual NMIs, which aren't | |
10284 | * tracked in vcpu->arch.nmi_pending. | |
10285 | */ | |
10286 | if (static_call(kvm_x86_is_vnmi_pending)(vcpu)) | |
10287 | limit--; | |
7460fb4a AK |
10288 | |
10289 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
10290 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
2cb93173 | 10291 | |
fa4c027a SS |
10292 | if (vcpu->arch.nmi_pending && |
10293 | (static_call(kvm_x86_set_vnmi_pending)(vcpu))) | |
10294 | vcpu->arch.nmi_pending--; | |
10295 | ||
2cb93173 SC |
10296 | if (vcpu->arch.nmi_pending) |
10297 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7460fb4a AK |
10298 | } |
10299 | ||
fa4c027a SS |
10300 | /* Return total number of NMIs pending injection to the VM */ |
10301 | int kvm_get_nr_pending_nmis(struct kvm_vcpu *vcpu) | |
10302 | { | |
10303 | return vcpu->arch.nmi_pending + | |
10304 | static_call(kvm_x86_is_vnmi_pending)(vcpu); | |
7460fb4a AK |
10305 | } |
10306 | ||
7ee30bc1 NNL |
10307 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
10308 | unsigned long *vcpu_bitmap) | |
10309 | { | |
620b2438 | 10310 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); |
7ee30bc1 NNL |
10311 | } |
10312 | ||
2860c4b1 PB |
10313 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
10314 | { | |
10315 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
10316 | } | |
10317 | ||
2008fab3 | 10318 | void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
8df14af4 | 10319 | { |
ce0a58f4 | 10320 | struct kvm_lapic *apic = vcpu->arch.apic; |
06ef8134 ML |
10321 | bool activate; |
10322 | ||
8df14af4 SS |
10323 | if (!lapic_in_kernel(vcpu)) |
10324 | return; | |
10325 | ||
187c8833 | 10326 | down_read(&vcpu->kvm->arch.apicv_update_lock); |
66c768d3 | 10327 | preempt_disable(); |
b0a1637f | 10328 | |
8fc9c7a3 SS |
10329 | /* Do not activate APICV when APIC is disabled */ |
10330 | activate = kvm_vcpu_apicv_activated(vcpu) && | |
10331 | (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED); | |
d5fa597e | 10332 | |
ce0a58f4 | 10333 | if (apic->apicv_active == activate) |
06ef8134 ML |
10334 | goto out; |
10335 | ||
ce0a58f4 | 10336 | apic->apicv_active = activate; |
8df14af4 | 10337 | kvm_apic_update_apicv(vcpu); |
b3646477 | 10338 | static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); |
bca66dbc VK |
10339 | |
10340 | /* | |
10341 | * When APICv gets disabled, we may still have injected interrupts | |
10342 | * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was | |
10343 | * still active when the interrupt got accepted. Make sure | |
e746c1f1 | 10344 | * kvm_check_and_inject_events() is called to check for that. |
bca66dbc | 10345 | */ |
ce0a58f4 | 10346 | if (!apic->apicv_active) |
bca66dbc | 10347 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
b0a1637f | 10348 | |
06ef8134 | 10349 | out: |
66c768d3 | 10350 | preempt_enable(); |
187c8833 | 10351 | up_read(&vcpu->kvm->arch.apicv_update_lock); |
8df14af4 | 10352 | } |
2008fab3 SC |
10353 | EXPORT_SYMBOL_GPL(__kvm_vcpu_update_apicv); |
10354 | ||
10355 | static void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) | |
10356 | { | |
10357 | if (!lapic_in_kernel(vcpu)) | |
10358 | return; | |
10359 | ||
10360 | /* | |
10361 | * Due to sharing page tables across vCPUs, the xAPIC memslot must be | |
10362 | * deleted if any vCPU has xAPIC virtualization and x2APIC enabled, but | |
10363 | * and hardware doesn't support x2APIC virtualization. E.g. some AMD | |
10364 | * CPUs support AVIC but not x2APIC. KVM still allows enabling AVIC in | |
10365 | * this case so that KVM can the AVIC doorbell to inject interrupts to | |
10366 | * running vCPUs, but KVM must not create SPTEs for the APIC base as | |
10367 | * the vCPU would incorrectly be able to access the vAPIC page via MMIO | |
10368 | * despite being in x2APIC mode. For simplicity, inhibiting the APIC | |
10369 | * access page is sticky. | |
10370 | */ | |
10371 | if (apic_x2apic_mode(vcpu->arch.apic) && | |
10372 | kvm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization) | |
10373 | kvm_inhibit_apic_access_page(vcpu); | |
10374 | ||
10375 | __kvm_vcpu_update_apicv(vcpu); | |
10376 | } | |
8df14af4 | 10377 | |
320af55a SC |
10378 | void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, |
10379 | enum kvm_apicv_inhibit reason, bool set) | |
8df14af4 | 10380 | { |
b0a1637f | 10381 | unsigned long old, new; |
8e205a6b | 10382 | |
187c8833 SC |
10383 | lockdep_assert_held_write(&kvm->arch.apicv_update_lock); |
10384 | ||
b3f257a8 | 10385 | if (!(kvm_x86_ops.required_apicv_inhibits & BIT(reason))) |
ef8efd7a SS |
10386 | return; |
10387 | ||
b0a1637f ML |
10388 | old = new = kvm->arch.apicv_inhibit_reasons; |
10389 | ||
4f4c4a3e | 10390 | set_or_clear_apicv_inhibit(&new, reason, set); |
8e205a6b | 10391 | |
36222b11 | 10392 | if (!!old != !!new) { |
ee49a893 SC |
10393 | /* |
10394 | * Kick all vCPUs before setting apicv_inhibit_reasons to avoid | |
10395 | * false positives in the sanity check WARN in svm_vcpu_run(). | |
10396 | * This task will wait for all vCPUs to ack the kick IRQ before | |
10397 | * updating apicv_inhibit_reasons, and all other vCPUs will | |
10398 | * block on acquiring apicv_update_lock so that vCPUs can't | |
10399 | * redo svm_vcpu_run() without seeing the new inhibit state. | |
10400 | * | |
10401 | * Note, holding apicv_update_lock and taking it in the read | |
10402 | * side (handling the request) also prevents other vCPUs from | |
10403 | * servicing the request with a stale apicv_inhibit_reasons. | |
10404 | */ | |
36222b11 | 10405 | kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); |
b0a1637f | 10406 | kvm->arch.apicv_inhibit_reasons = new; |
36222b11 ML |
10407 | if (new) { |
10408 | unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); | |
074c0080 BG |
10409 | int idx = srcu_read_lock(&kvm->srcu); |
10410 | ||
36222b11 | 10411 | kvm_zap_gfn_range(kvm, gfn, gfn+1); |
074c0080 | 10412 | srcu_read_unlock(&kvm->srcu, idx); |
36222b11 | 10413 | } |
7491b7b2 | 10414 | } else { |
b0a1637f | 10415 | kvm->arch.apicv_inhibit_reasons = new; |
7491b7b2 | 10416 | } |
b0a1637f | 10417 | } |
7d611233 | 10418 | |
320af55a SC |
10419 | void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, |
10420 | enum kvm_apicv_inhibit reason, bool set) | |
b0a1637f | 10421 | { |
f1575642 SC |
10422 | if (!enable_apicv) |
10423 | return; | |
10424 | ||
187c8833 | 10425 | down_write(&kvm->arch.apicv_update_lock); |
320af55a | 10426 | __kvm_set_or_clear_apicv_inhibit(kvm, reason, set); |
187c8833 | 10427 | up_write(&kvm->arch.apicv_update_lock); |
8df14af4 | 10428 | } |
320af55a | 10429 | EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit); |
8df14af4 | 10430 | |
3d81bc7e | 10431 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 10432 | { |
dcbd3e49 | 10433 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 10434 | return; |
c7c9c56c | 10435 | |
6308630b | 10436 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 10437 | |
b053b2ae | 10438 | if (irqchip_split(vcpu->kvm)) |
6308630b | 10439 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 10440 | else { |
37c4dbf3 | 10441 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); |
e97f852f WL |
10442 | if (ioapic_in_kernel(vcpu->kvm)) |
10443 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 10444 | } |
e40ff1d6 LA |
10445 | |
10446 | if (is_guest_mode(vcpu)) | |
10447 | vcpu->arch.load_eoi_exitmap_pending = true; | |
10448 | else | |
10449 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
10450 | } | |
10451 | ||
10452 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
10453 | { | |
10454 | u64 eoi_exit_bitmap[4]; | |
10455 | ||
10456 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
10457 | return; | |
10458 | ||
c5adbb3a | 10459 | if (to_hv_vcpu(vcpu)) { |
f2bc14b6 VK |
10460 | bitmap_or((ulong *)eoi_exit_bitmap, |
10461 | vcpu->arch.ioapic_handled_vectors, | |
10462 | to_hv_synic(vcpu)->vec_bitmap, 256); | |
abb6d479 | 10463 | static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); |
c5adbb3a | 10464 | return; |
10465 | } | |
f2bc14b6 | 10466 | |
abb6d479 | 10467 | static_call_cond(kvm_x86_load_eoi_exitmap)( |
c5adbb3a | 10468 | vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors); |
c7c9c56c YZ |
10469 | } |
10470 | ||
683412cc MZ |
10471 | void kvm_arch_guest_memory_reclaimed(struct kvm *kvm) |
10472 | { | |
10473 | static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm); | |
10474 | } | |
10475 | ||
d081a343 | 10476 | static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
4256f43f | 10477 | { |
35754c98 | 10478 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
10479 | return; |
10480 | ||
2a890614 | 10481 | static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu); |
4256f43f | 10482 | } |
4256f43f | 10483 | |
d264ee0c SC |
10484 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
10485 | { | |
10486 | smp_send_reschedule(vcpu->cpu); | |
10487 | } | |
10488 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
10489 | ||
9357d939 | 10490 | /* |
8d25b7be | 10491 | * Called within kvm->srcu read side. |
362c698f | 10492 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
10493 | * exiting to the userspace. Otherwise, the value will be returned to the |
10494 | * userspace. | |
10495 | */ | |
851ba692 | 10496 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
10497 | { |
10498 | int r; | |
62a193ed MG |
10499 | bool req_int_win = |
10500 | dm_request_for_irq_injection(vcpu) && | |
10501 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 10502 | fastpath_t exit_fastpath; |
62a193ed | 10503 | |
730dca42 | 10504 | bool req_immediate_exit = false; |
b6c7a5dc | 10505 | |
2fa6e1e1 | 10506 | if (kvm_request_pending(vcpu)) { |
f4d31653 | 10507 | if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) { |
67369273 SC |
10508 | r = -EIO; |
10509 | goto out; | |
10510 | } | |
cf87ac73 GS |
10511 | |
10512 | if (kvm_dirty_ring_check_request(vcpu)) { | |
10513 | r = 0; | |
10514 | goto out; | |
10515 | } | |
10516 | ||
729c15c2 | 10517 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
9a78e158 | 10518 | if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { |
671ddc70 JM |
10519 | r = 0; |
10520 | goto out; | |
10521 | } | |
10522 | } | |
527d5cd7 SC |
10523 | if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu)) |
10524 | kvm_mmu_free_obsolete_roots(vcpu); | |
a8eeb04a | 10525 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 10526 | __kvm_migrate_timers(vcpu); |
d828199e | 10527 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
6b6fcd28 | 10528 | kvm_update_masterclock(vcpu->kvm); |
0061d53d MT |
10529 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
10530 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
10531 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
10532 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
10533 | if (unlikely(r)) |
10534 | goto out; | |
10535 | } | |
a8eeb04a | 10536 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 10537 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
10538 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
10539 | kvm_mmu_load_pgd(vcpu); | |
e94cea09 SC |
10540 | |
10541 | /* | |
10542 | * Note, the order matters here, as flushing "all" TLB entries | |
10543 | * also flushes the "current" TLB entries, i.e. servicing the | |
10544 | * flush "all" will clear any request to flush "current". | |
10545 | */ | |
10546 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) | |
7780938c | 10547 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 | 10548 | |
40e5f908 | 10549 | kvm_service_local_tlb_flush_requests(vcpu); |
eeeb4f67 | 10550 | |
0823570f VK |
10551 | /* |
10552 | * Fall back to a "full" guest flush if Hyper-V's precise | |
10553 | * flushing fails. Note, Hyper-V's flushing is per-vCPU, but | |
10554 | * the flushes are considered "remote" and not "local" because | |
10555 | * the requests can be initiated from other vCPUs. | |
10556 | */ | |
10557 | if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) && | |
10558 | kvm_hv_vcpu_flush_tlb(vcpu)) | |
adc43caa VK |
10559 | kvm_vcpu_flush_tlb_guest(vcpu); |
10560 | ||
a8eeb04a | 10561 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 10562 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
10563 | r = 0; |
10564 | goto out; | |
10565 | } | |
92e7d5c8 ML |
10566 | if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
10567 | if (is_guest_mode(vcpu)) | |
cb6a32c2 | 10568 | kvm_x86_ops.nested_ops->triple_fault(vcpu); |
92e7d5c8 ML |
10569 | |
10570 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { | |
cb6a32c2 SC |
10571 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
10572 | vcpu->mmio_needed = 0; | |
10573 | r = 0; | |
e542baf3 | 10574 | goto out; |
cb6a32c2 | 10575 | } |
71c4dfaf | 10576 | } |
af585b92 GN |
10577 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
10578 | /* Page is swapped out. Do synthetic halt */ | |
10579 | vcpu->arch.apf.halted = true; | |
10580 | r = 1; | |
10581 | goto out; | |
10582 | } | |
c9aaa895 GC |
10583 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
10584 | record_steal_time(vcpu); | |
cf7316d0 | 10585 | #ifdef CONFIG_KVM_SMM |
64d60670 PB |
10586 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
10587 | process_smi(vcpu); | |
cf7316d0 | 10588 | #endif |
7460fb4a AK |
10589 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
10590 | process_nmi(vcpu); | |
f5132b01 | 10591 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 10592 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 10593 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 10594 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
10595 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
10596 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
10597 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 10598 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
10599 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
10600 | vcpu->run->eoi.vector = | |
10601 | vcpu->arch.pending_ioapic_eoi; | |
10602 | r = 0; | |
10603 | goto out; | |
10604 | } | |
10605 | } | |
3d81bc7e YZ |
10606 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
10607 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
10608 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
10609 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
10610 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
10611 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
10612 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
10613 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
10614 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
d495f942 | 10615 | vcpu->run->system_event.ndata = 0; |
2ce79189 AS |
10616 | r = 0; |
10617 | goto out; | |
10618 | } | |
e516cebb AS |
10619 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
10620 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
10621 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
d495f942 | 10622 | vcpu->run->system_event.ndata = 0; |
e516cebb AS |
10623 | r = 0; |
10624 | goto out; | |
10625 | } | |
db397571 | 10626 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
9ff5e030 VK |
10627 | struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); |
10628 | ||
db397571 | 10629 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; |
9ff5e030 | 10630 | vcpu->run->hyperv = hv_vcpu->exit; |
db397571 AS |
10631 | r = 0; |
10632 | goto out; | |
10633 | } | |
f3b138c5 AS |
10634 | |
10635 | /* | |
10636 | * KVM_REQ_HV_STIMER has to be processed after | |
10637 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
10638 | * depend on the guest clock being up-to-date | |
10639 | */ | |
1f4b34f8 AS |
10640 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
10641 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
10642 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
10643 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
10644 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
10645 | kvm_check_async_pf_completion(vcpu); | |
1a155254 | 10646 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
b3646477 | 10647 | static_call(kvm_x86_msr_filter_changed)(vcpu); |
a85863c2 MS |
10648 | |
10649 | if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) | |
10650 | static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); | |
2f52d58c | 10651 | } |
b93463aa | 10652 | |
40da8ccd DW |
10653 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || |
10654 | kvm_xen_has_interrupt(vcpu)) { | |
0f1e261e | 10655 | ++vcpu->stat.req_event; |
4fe09bcf JM |
10656 | r = kvm_apic_accept_events(vcpu); |
10657 | if (r < 0) { | |
10658 | r = 0; | |
10659 | goto out; | |
10660 | } | |
66450a21 JK |
10661 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
10662 | r = 1; | |
10663 | goto out; | |
10664 | } | |
10665 | ||
e746c1f1 | 10666 | r = kvm_check_and_inject_events(vcpu, &req_immediate_exit); |
a5f6909a JM |
10667 | if (r < 0) { |
10668 | r = 0; | |
10669 | goto out; | |
10670 | } | |
c9d40913 | 10671 | if (req_int_win) |
b3646477 | 10672 | static_call(kvm_x86_enable_irq_window)(vcpu); |
b463a6f7 AK |
10673 | |
10674 | if (kvm_lapic_enabled(vcpu)) { | |
10675 | update_cr8_intercept(vcpu); | |
10676 | kvm_lapic_sync_to_vapic(vcpu); | |
10677 | } | |
10678 | } | |
10679 | ||
d8368af8 AK |
10680 | r = kvm_mmu_reload(vcpu); |
10681 | if (unlikely(r)) { | |
d905c069 | 10682 | goto cancel_injection; |
d8368af8 AK |
10683 | } |
10684 | ||
b6c7a5dc HB |
10685 | preempt_disable(); |
10686 | ||
e27bc044 | 10687 | static_call(kvm_x86_prepare_switch_to_guest)(vcpu); |
b95234c8 PB |
10688 | |
10689 | /* | |
10690 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
10691 | * IPI are then delayed after guest entry, which ensures that they | |
10692 | * result in virtual interrupt delivery. | |
10693 | */ | |
10694 | local_irq_disable(); | |
66fa226c ML |
10695 | |
10696 | /* Store vcpu->apicv_active before vcpu->mode. */ | |
10697 | smp_store_release(&vcpu->mode, IN_GUEST_MODE); | |
6b7e2d09 | 10698 | |
2031f287 | 10699 | kvm_vcpu_srcu_read_unlock(vcpu); |
01b71917 | 10700 | |
0f127d12 | 10701 | /* |
b95234c8 | 10702 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 10703 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 10704 | * |
81b01667 | 10705 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
10706 | * pairs with the memory barrier implicit in pi_test_and_set_on |
10707 | * (see vmx_deliver_posted_interrupt). | |
10708 | * | |
10709 | * 3) This also orders the write to mode from any reads to the page | |
10710 | * tables done while the VCPU is running. Please see the comment | |
10711 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 10712 | */ |
01b71917 | 10713 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 10714 | |
b95234c8 | 10715 | /* |
0f65a9d3 SC |
10716 | * Process pending posted interrupts to handle the case where the |
10717 | * notification IRQ arrived in the host, or was never sent (because the | |
10718 | * target vCPU wasn't running). Do this regardless of the vCPU's APICv | |
10719 | * status, KVM doesn't update assigned devices when APICv is inhibited, | |
10720 | * i.e. they can post interrupts even if APICv is temporarily disabled. | |
b95234c8 | 10721 | */ |
37c4dbf3 PB |
10722 | if (kvm_lapic_enabled(vcpu)) |
10723 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); | |
32f88400 | 10724 | |
5a9f5443 | 10725 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 10726 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 10727 | smp_wmb(); |
6c142801 AK |
10728 | local_irq_enable(); |
10729 | preempt_enable(); | |
2031f287 | 10730 | kvm_vcpu_srcu_read_lock(vcpu); |
6c142801 | 10731 | r = 1; |
d905c069 | 10732 | goto cancel_injection; |
6c142801 AK |
10733 | } |
10734 | ||
c43203ca PB |
10735 | if (req_immediate_exit) { |
10736 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 10737 | static_call(kvm_x86_request_immediate_exit)(vcpu); |
c43203ca | 10738 | } |
d6185f20 | 10739 | |
2620fe26 SC |
10740 | fpregs_assert_state_consistent(); |
10741 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
10742 | switch_fpu_return(); | |
5f409e20 | 10743 | |
ec5be88a JL |
10744 | if (vcpu->arch.guest_fpu.xfd_err) |
10745 | wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); | |
10746 | ||
42dbaa5a | 10747 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
10748 | set_debugreg(0, 7); |
10749 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
10750 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
10751 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
10752 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
f85d4016 LJ |
10753 | } else if (unlikely(hw_breakpoint_active())) { |
10754 | set_debugreg(0, 7); | |
42dbaa5a | 10755 | } |
b6c7a5dc | 10756 | |
b2d2af7e MR |
10757 | guest_timing_enter_irqoff(); |
10758 | ||
d89d04ab | 10759 | for (;;) { |
ee49a893 SC |
10760 | /* |
10761 | * Assert that vCPU vs. VM APICv state is consistent. An APICv | |
10762 | * update must kick and wait for all vCPUs before toggling the | |
10763 | * per-VM state, and responsing vCPUs must wait for the update | |
10764 | * to complete before servicing KVM_REQ_APICV_UPDATE. | |
10765 | */ | |
f8d8ac21 SS |
10766 | WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) && |
10767 | (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED)); | |
ee49a893 | 10768 | |
e27bc044 | 10769 | exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu); |
d89d04ab PB |
10770 | if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) |
10771 | break; | |
10772 | ||
37c4dbf3 PB |
10773 | if (kvm_lapic_enabled(vcpu)) |
10774 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); | |
de7cd3f6 PB |
10775 | |
10776 | if (unlikely(kvm_vcpu_exit_request(vcpu))) { | |
d89d04ab PB |
10777 | exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; |
10778 | break; | |
10779 | } | |
8b703a49 SC |
10780 | |
10781 | /* Note, VM-Exits that go down the "slow" path are accounted below. */ | |
10782 | ++vcpu->stat.exits; | |
de7cd3f6 | 10783 | } |
b6c7a5dc | 10784 | |
c77fb5fe PB |
10785 | /* |
10786 | * Do this here before restoring debug registers on the host. And | |
10787 | * since we do this before handling the vmexit, a DR access vmexit | |
10788 | * can (a) read the correct value of the debug registers, (b) set | |
10789 | * KVM_DEBUGREG_WONT_EXIT again. | |
10790 | */ | |
10791 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 10792 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
b3646477 | 10793 | static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); |
70e4da7a | 10794 | kvm_update_dr0123(vcpu); |
70e4da7a | 10795 | kvm_update_dr7(vcpu); |
c77fb5fe PB |
10796 | } |
10797 | ||
24f1e32c FW |
10798 | /* |
10799 | * If the guest has used debug registers, at least dr7 | |
10800 | * will be disabled while returning to the host. | |
10801 | * If we don't have active breakpoints in the host, we don't | |
10802 | * care about the messed up debug address registers. But if | |
10803 | * we have some of them active, restore the old state. | |
10804 | */ | |
59d8eb53 | 10805 | if (hw_breakpoint_active()) |
24f1e32c | 10806 | hw_breakpoint_restore(); |
42dbaa5a | 10807 | |
c967118d | 10808 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 10809 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 10810 | |
6b7e2d09 | 10811 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 10812 | smp_wmb(); |
a547c6db | 10813 | |
b5274b1b KT |
10814 | /* |
10815 | * Sync xfd before calling handle_exit_irqoff() which may | |
10816 | * rely on the fact that guest_fpu::xfd is up-to-date (e.g. | |
10817 | * in #NM irqoff handler). | |
10818 | */ | |
10819 | if (vcpu->arch.xfd_no_write_intercept) | |
10820 | fpu_sync_guest_vmexit_xfd_state(); | |
10821 | ||
b3646477 | 10822 | static_call(kvm_x86_handle_exit_irqoff)(vcpu); |
b6c7a5dc | 10823 | |
ec5be88a JL |
10824 | if (vcpu->arch.guest_fpu.xfd_err) |
10825 | wrmsrl(MSR_IA32_XFD_ERR, 0); | |
10826 | ||
d7a08882 SC |
10827 | /* |
10828 | * Consume any pending interrupts, including the possible source of | |
10829 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
10830 | * An instruction is required after local_irq_enable() to fully unblock | |
10831 | * interrupts on processors that implement an interrupt shadow, the | |
10832 | * stat.exits increment will do nicely. | |
10833 | */ | |
db215756 | 10834 | kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); |
d7a08882 | 10835 | local_irq_enable(); |
b6c7a5dc | 10836 | ++vcpu->stat.exits; |
d7a08882 SC |
10837 | local_irq_disable(); |
10838 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 10839 | |
16045714 WL |
10840 | /* |
10841 | * Wait until after servicing IRQs to account guest time so that any | |
10842 | * ticks that occurred while running the guest are properly accounted | |
10843 | * to the guest. Waiting until IRQs are enabled degrades the accuracy | |
10844 | * of accounting via context tracking, but the loss of accuracy is | |
10845 | * acceptable for all known use cases. | |
10846 | */ | |
b2d2af7e | 10847 | guest_timing_exit_irqoff(); |
16045714 | 10848 | |
f2485b3e | 10849 | local_irq_enable(); |
b6c7a5dc HB |
10850 | preempt_enable(); |
10851 | ||
2031f287 | 10852 | kvm_vcpu_srcu_read_lock(vcpu); |
3200f405 | 10853 | |
b6c7a5dc HB |
10854 | /* |
10855 | * Profile KVM exit RIPs: | |
10856 | */ | |
10857 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
10858 | unsigned long rip = kvm_rip_read(vcpu); |
10859 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
10860 | } |
10861 | ||
cc578287 ZA |
10862 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
10863 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 10864 | |
5cfb1d5a MT |
10865 | if (vcpu->arch.apic_attention) |
10866 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 10867 | |
b3646477 | 10868 | r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); |
d905c069 MT |
10869 | return r; |
10870 | ||
10871 | cancel_injection: | |
8081ad06 SC |
10872 | if (req_immediate_exit) |
10873 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 10874 | static_call(kvm_x86_cancel_injection)(vcpu); |
ae7a2a3f MT |
10875 | if (unlikely(vcpu->arch.apic_attention)) |
10876 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
10877 | out: |
10878 | return r; | |
10879 | } | |
b6c7a5dc | 10880 | |
8d25b7be | 10881 | /* Called within kvm->srcu read side. */ |
2031f287 | 10882 | static inline int vcpu_block(struct kvm_vcpu *vcpu) |
362c698f | 10883 | { |
98c25ead SC |
10884 | bool hv_timer; |
10885 | ||
c3e8abf0 | 10886 | if (!kvm_arch_vcpu_runnable(vcpu)) { |
98c25ead SC |
10887 | /* |
10888 | * Switch to the software timer before halt-polling/blocking as | |
10889 | * the guest's timer may be a break event for the vCPU, and the | |
10890 | * hypervisor timer runs only when the CPU is in guest mode. | |
10891 | * Switch before halt-polling so that KVM recognizes an expired | |
10892 | * timer before blocking. | |
10893 | */ | |
10894 | hv_timer = kvm_lapic_hv_timer_in_use(vcpu); | |
10895 | if (hv_timer) | |
10896 | kvm_lapic_switch_to_sw_timer(vcpu); | |
10897 | ||
2031f287 | 10898 | kvm_vcpu_srcu_read_unlock(vcpu); |
cdafece4 SC |
10899 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
10900 | kvm_vcpu_halt(vcpu); | |
10901 | else | |
10902 | kvm_vcpu_block(vcpu); | |
2031f287 | 10903 | kvm_vcpu_srcu_read_lock(vcpu); |
bf9f6ac8 | 10904 | |
98c25ead SC |
10905 | if (hv_timer) |
10906 | kvm_lapic_switch_to_hv_timer(vcpu); | |
10907 | ||
599275c0 PB |
10908 | /* |
10909 | * If the vCPU is not runnable, a signal or another host event | |
10910 | * of some kind is pending; service it without changing the | |
10911 | * vCPU's activity state. | |
10912 | */ | |
10913 | if (!kvm_arch_vcpu_runnable(vcpu)) | |
9c8fd1ba PB |
10914 | return 1; |
10915 | } | |
362c698f | 10916 | |
26844fee PB |
10917 | /* |
10918 | * Evaluate nested events before exiting the halted state. This allows | |
10919 | * the halt state to be recorded properly in the VMCS12's activity | |
10920 | * state field (AMD does not have a similar field and a VM-Exit always | |
10921 | * causes a spurious wakeup from HLT). | |
10922 | */ | |
10923 | if (is_guest_mode(vcpu)) { | |
10924 | if (kvm_check_nested_events(vcpu) < 0) | |
10925 | return 0; | |
10926 | } | |
10927 | ||
4fe09bcf JM |
10928 | if (kvm_apic_accept_events(vcpu) < 0) |
10929 | return 0; | |
362c698f PB |
10930 | switch(vcpu->arch.mp_state) { |
10931 | case KVM_MP_STATE_HALTED: | |
647daca2 | 10932 | case KVM_MP_STATE_AP_RESET_HOLD: |
362c698f PB |
10933 | vcpu->arch.pv.pv_unhalted = false; |
10934 | vcpu->arch.mp_state = | |
10935 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 10936 | fallthrough; |
362c698f PB |
10937 | case KVM_MP_STATE_RUNNABLE: |
10938 | vcpu->arch.apf.halted = false; | |
10939 | break; | |
10940 | case KVM_MP_STATE_INIT_RECEIVED: | |
10941 | break; | |
10942 | default: | |
22c6a0ef PB |
10943 | WARN_ON_ONCE(1); |
10944 | break; | |
362c698f PB |
10945 | } |
10946 | return 1; | |
10947 | } | |
09cec754 | 10948 | |
5d9bc648 PB |
10949 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
10950 | { | |
10951 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && | |
10952 | !vcpu->arch.apf.halted); | |
10953 | } | |
10954 | ||
8d25b7be | 10955 | /* Called within kvm->srcu read side. */ |
362c698f | 10956 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
10957 | { |
10958 | int r; | |
10959 | ||
c595ceee | 10960 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 10961 | |
362c698f | 10962 | for (;;) { |
6cd88243 PB |
10963 | /* |
10964 | * If another guest vCPU requests a PV TLB flush in the middle | |
10965 | * of instruction emulation, the rest of the emulation could | |
10966 | * use a stale page translation. Assume that any code after | |
10967 | * this point can start executing an instruction. | |
10968 | */ | |
10969 | vcpu->arch.at_instruction_boundary = false; | |
58f800d5 | 10970 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 10971 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 10972 | } else { |
2031f287 | 10973 | r = vcpu_block(vcpu); |
bf9f6ac8 FW |
10974 | } |
10975 | ||
09cec754 GN |
10976 | if (r <= 0) |
10977 | break; | |
10978 | ||
084071d5 | 10979 | kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); |
7caf9571 DW |
10980 | if (kvm_xen_has_pending_events(vcpu)) |
10981 | kvm_xen_inject_pending_events(vcpu); | |
10982 | ||
09cec754 GN |
10983 | if (kvm_cpu_has_pending_timer(vcpu)) |
10984 | kvm_inject_pending_timer_irqs(vcpu); | |
10985 | ||
782d422b MG |
10986 | if (dm_request_for_irq_injection(vcpu) && |
10987 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
10988 | r = 0; |
10989 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 10990 | ++vcpu->stat.request_irq_exits; |
362c698f | 10991 | break; |
09cec754 | 10992 | } |
af585b92 | 10993 | |
f3020b88 | 10994 | if (__xfer_to_guest_mode_work_pending()) { |
2031f287 | 10995 | kvm_vcpu_srcu_read_unlock(vcpu); |
72c3c0fe | 10996 | r = xfer_to_guest_mode_handle_work(vcpu); |
2031f287 | 10997 | kvm_vcpu_srcu_read_lock(vcpu); |
72c3c0fe TG |
10998 | if (r) |
10999 | return r; | |
d7690175 | 11000 | } |
b6c7a5dc HB |
11001 | } |
11002 | ||
b6c7a5dc HB |
11003 | return r; |
11004 | } | |
11005 | ||
716d51ab GN |
11006 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
11007 | { | |
2d089356 | 11008 | return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab GN |
11009 | } |
11010 | ||
11011 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
11012 | { | |
11013 | BUG_ON(!vcpu->arch.pio.count); | |
11014 | ||
11015 | return complete_emulated_io(vcpu); | |
11016 | } | |
11017 | ||
f78146b0 AK |
11018 | /* |
11019 | * Implements the following, as a state machine: | |
11020 | * | |
11021 | * read: | |
11022 | * for each fragment | |
87da7e66 XG |
11023 | * for each mmio piece in the fragment |
11024 | * write gpa, len | |
11025 | * exit | |
11026 | * copy data | |
f78146b0 AK |
11027 | * execute insn |
11028 | * | |
11029 | * write: | |
11030 | * for each fragment | |
87da7e66 XG |
11031 | * for each mmio piece in the fragment |
11032 | * write gpa, len | |
11033 | * copy data | |
11034 | * exit | |
f78146b0 | 11035 | */ |
716d51ab | 11036 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
11037 | { |
11038 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 11039 | struct kvm_mmio_fragment *frag; |
87da7e66 | 11040 | unsigned len; |
5287f194 | 11041 | |
716d51ab | 11042 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 11043 | |
716d51ab | 11044 | /* Complete previous fragment */ |
87da7e66 XG |
11045 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
11046 | len = min(8u, frag->len); | |
716d51ab | 11047 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
11048 | memcpy(frag->data, run->mmio.data, len); |
11049 | ||
11050 | if (frag->len <= 8) { | |
11051 | /* Switch to the next fragment. */ | |
11052 | frag++; | |
11053 | vcpu->mmio_cur_fragment++; | |
11054 | } else { | |
11055 | /* Go forward to the next mmio piece. */ | |
11056 | frag->data += len; | |
11057 | frag->gpa += len; | |
11058 | frag->len -= len; | |
11059 | } | |
11060 | ||
a08d3b3b | 11061 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 11062 | vcpu->mmio_needed = 0; |
0912c977 PB |
11063 | |
11064 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 11065 | if (vcpu->mmio_is_write) |
716d51ab GN |
11066 | return 1; |
11067 | vcpu->mmio_read_completed = 1; | |
11068 | return complete_emulated_io(vcpu); | |
11069 | } | |
87da7e66 | 11070 | |
716d51ab GN |
11071 | run->exit_reason = KVM_EXIT_MMIO; |
11072 | run->mmio.phys_addr = frag->gpa; | |
11073 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
11074 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
11075 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
11076 | run->mmio.is_write = vcpu->mmio_is_write; |
11077 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
11078 | return 0; | |
5287f194 AK |
11079 | } |
11080 | ||
822f312d SAS |
11081 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
11082 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
11083 | { | |
e27bc044 | 11084 | /* Exclude PKRU, it's restored separately immediately after VM-Exit. */ |
d69c1382 | 11085 | fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); |
822f312d SAS |
11086 | trace_kvm_fpu(1); |
11087 | } | |
11088 | ||
11089 | /* When vcpu_run ends, restore user space FPU context. */ | |
11090 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
11091 | { | |
d69c1382 | 11092 | fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); |
822f312d SAS |
11093 | ++vcpu->stat.fpu_reload; |
11094 | trace_kvm_fpu(0); | |
11095 | } | |
11096 | ||
1b94f6f8 | 11097 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 11098 | { |
7709aba8 | 11099 | struct kvm_queued_exception *ex = &vcpu->arch.exception; |
1b94f6f8 | 11100 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 11101 | int r; |
b6c7a5dc | 11102 | |
accb757d | 11103 | vcpu_load(vcpu); |
20b7035c | 11104 | kvm_sigset_activate(vcpu); |
15aad3be | 11105 | kvm_run->flags = 0; |
5663d8f9 PX |
11106 | kvm_load_guest_fpu(vcpu); |
11107 | ||
2031f287 | 11108 | kvm_vcpu_srcu_read_lock(vcpu); |
a4535290 | 11109 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
11110 | if (kvm_run->immediate_exit) { |
11111 | r = -EINTR; | |
11112 | goto out; | |
11113 | } | |
98c25ead SC |
11114 | /* |
11115 | * It should be impossible for the hypervisor timer to be in | |
11116 | * use before KVM has ever run the vCPU. | |
11117 | */ | |
11118 | WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu)); | |
8d25b7be | 11119 | |
2031f287 | 11120 | kvm_vcpu_srcu_read_unlock(vcpu); |
c91d4497 | 11121 | kvm_vcpu_block(vcpu); |
2031f287 | 11122 | kvm_vcpu_srcu_read_lock(vcpu); |
8d25b7be | 11123 | |
4fe09bcf JM |
11124 | if (kvm_apic_accept_events(vcpu) < 0) { |
11125 | r = 0; | |
11126 | goto out; | |
11127 | } | |
ac9f6dc0 | 11128 | r = -EAGAIN; |
a0595000 JS |
11129 | if (signal_pending(current)) { |
11130 | r = -EINTR; | |
1b94f6f8 | 11131 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
11132 | ++vcpu->stat.signal_exits; |
11133 | } | |
ac9f6dc0 | 11134 | goto out; |
b6c7a5dc HB |
11135 | } |
11136 | ||
e489a4a6 SC |
11137 | if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || |
11138 | (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { | |
01643c51 KH |
11139 | r = -EINVAL; |
11140 | goto out; | |
11141 | } | |
11142 | ||
1b94f6f8 | 11143 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
11144 | r = sync_regs(vcpu); |
11145 | if (r != 0) | |
11146 | goto out; | |
11147 | } | |
11148 | ||
b6c7a5dc | 11149 | /* re-sync apic's tpr */ |
35754c98 | 11150 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
11151 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
11152 | r = -EINVAL; | |
11153 | goto out; | |
11154 | } | |
11155 | } | |
b6c7a5dc | 11156 | |
7709aba8 SC |
11157 | /* |
11158 | * If userspace set a pending exception and L2 is active, convert it to | |
11159 | * a pending VM-Exit if L1 wants to intercept the exception. | |
11160 | */ | |
11161 | if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) && | |
11162 | kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector, | |
11163 | ex->error_code)) { | |
11164 | kvm_queue_exception_vmexit(vcpu, ex->vector, | |
11165 | ex->has_error_code, ex->error_code, | |
11166 | ex->has_payload, ex->payload); | |
11167 | ex->injected = false; | |
11168 | ex->pending = false; | |
11169 | } | |
11170 | vcpu->arch.exception_from_userspace = false; | |
11171 | ||
716d51ab GN |
11172 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
11173 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
11174 | vcpu->arch.complete_userspace_io = NULL; | |
11175 | r = cui(vcpu); | |
11176 | if (r <= 0) | |
5663d8f9 | 11177 | goto out; |
0bc27326 SC |
11178 | } else { |
11179 | WARN_ON_ONCE(vcpu->arch.pio.count); | |
11180 | WARN_ON_ONCE(vcpu->mmio_needed); | |
11181 | } | |
5287f194 | 11182 | |
fc4fad79 | 11183 | if (kvm_run->immediate_exit) { |
460df4c1 | 11184 | r = -EINTR; |
fc4fad79 SC |
11185 | goto out; |
11186 | } | |
11187 | ||
11188 | r = static_call(kvm_x86_vcpu_pre_run)(vcpu); | |
11189 | if (r <= 0) | |
11190 | goto out; | |
11191 | ||
11192 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
11193 | |
11194 | out: | |
5663d8f9 | 11195 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 11196 | if (kvm_run->kvm_valid_regs) |
01643c51 | 11197 | store_regs(vcpu); |
f1d86e46 | 11198 | post_kvm_run_save(vcpu); |
2031f287 | 11199 | kvm_vcpu_srcu_read_unlock(vcpu); |
b6c7a5dc | 11200 | |
8d25b7be | 11201 | kvm_sigset_deactivate(vcpu); |
accb757d | 11202 | vcpu_put(vcpu); |
b6c7a5dc HB |
11203 | return r; |
11204 | } | |
11205 | ||
01643c51 | 11206 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 11207 | { |
7ae441ea GN |
11208 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
11209 | /* | |
11210 | * We are here if userspace calls get_regs() in the middle of | |
11211 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 11212 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
11213 | * that usually, but some bad designed PV devices (vmware |
11214 | * backdoor interface) need this to work | |
11215 | */ | |
c9b8b07c | 11216 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
11217 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
11218 | } | |
de3cd117 SC |
11219 | regs->rax = kvm_rax_read(vcpu); |
11220 | regs->rbx = kvm_rbx_read(vcpu); | |
11221 | regs->rcx = kvm_rcx_read(vcpu); | |
11222 | regs->rdx = kvm_rdx_read(vcpu); | |
11223 | regs->rsi = kvm_rsi_read(vcpu); | |
11224 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 11225 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 11226 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 11227 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
11228 | regs->r8 = kvm_r8_read(vcpu); |
11229 | regs->r9 = kvm_r9_read(vcpu); | |
11230 | regs->r10 = kvm_r10_read(vcpu); | |
11231 | regs->r11 = kvm_r11_read(vcpu); | |
11232 | regs->r12 = kvm_r12_read(vcpu); | |
11233 | regs->r13 = kvm_r13_read(vcpu); | |
11234 | regs->r14 = kvm_r14_read(vcpu); | |
11235 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
11236 | #endif |
11237 | ||
5fdbf976 | 11238 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 11239 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 11240 | } |
b6c7a5dc | 11241 | |
01643c51 KH |
11242 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
11243 | { | |
11244 | vcpu_load(vcpu); | |
11245 | __get_regs(vcpu, regs); | |
1fc9b76b | 11246 | vcpu_put(vcpu); |
b6c7a5dc HB |
11247 | return 0; |
11248 | } | |
11249 | ||
01643c51 | 11250 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 11251 | { |
7ae441ea GN |
11252 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
11253 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
11254 | ||
de3cd117 SC |
11255 | kvm_rax_write(vcpu, regs->rax); |
11256 | kvm_rbx_write(vcpu, regs->rbx); | |
11257 | kvm_rcx_write(vcpu, regs->rcx); | |
11258 | kvm_rdx_write(vcpu, regs->rdx); | |
11259 | kvm_rsi_write(vcpu, regs->rsi); | |
11260 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 11261 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 11262 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 11263 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
11264 | kvm_r8_write(vcpu, regs->r8); |
11265 | kvm_r9_write(vcpu, regs->r9); | |
11266 | kvm_r10_write(vcpu, regs->r10); | |
11267 | kvm_r11_write(vcpu, regs->r11); | |
11268 | kvm_r12_write(vcpu, regs->r12); | |
11269 | kvm_r13_write(vcpu, regs->r13); | |
11270 | kvm_r14_write(vcpu, regs->r14); | |
11271 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
11272 | #endif |
11273 | ||
5fdbf976 | 11274 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 11275 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 11276 | |
b4f14abd | 11277 | vcpu->arch.exception.pending = false; |
7709aba8 | 11278 | vcpu->arch.exception_vmexit.pending = false; |
b4f14abd | 11279 | |
3842d135 | 11280 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 11281 | } |
3842d135 | 11282 | |
01643c51 KH |
11283 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
11284 | { | |
11285 | vcpu_load(vcpu); | |
11286 | __set_regs(vcpu, regs); | |
875656fe | 11287 | vcpu_put(vcpu); |
b6c7a5dc HB |
11288 | return 0; |
11289 | } | |
11290 | ||
6dba9403 | 11291 | static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 11292 | { |
89a27f4d | 11293 | struct desc_ptr dt; |
b6c7a5dc | 11294 | |
5265713a TL |
11295 | if (vcpu->arch.guest_state_protected) |
11296 | goto skip_protected_regs; | |
11297 | ||
3e6e0aab GT |
11298 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
11299 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
11300 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
11301 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
11302 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
11303 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 11304 | |
3e6e0aab GT |
11305 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
11306 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 11307 | |
b3646477 | 11308 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
89a27f4d GN |
11309 | sregs->idt.limit = dt.size; |
11310 | sregs->idt.base = dt.address; | |
b3646477 | 11311 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
89a27f4d GN |
11312 | sregs->gdt.limit = dt.size; |
11313 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 11314 | |
ad312c7c | 11315 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 11316 | sregs->cr3 = kvm_read_cr3(vcpu); |
5265713a TL |
11317 | |
11318 | skip_protected_regs: | |
11319 | sregs->cr0 = kvm_read_cr0(vcpu); | |
fc78f519 | 11320 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 11321 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 11322 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc | 11323 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6dba9403 | 11324 | } |
b6c7a5dc | 11325 | |
6dba9403 ML |
11326 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
11327 | { | |
11328 | __get_sregs_common(vcpu, sregs); | |
11329 | ||
11330 | if (vcpu->arch.guest_state_protected) | |
11331 | return; | |
b6c7a5dc | 11332 | |
04140b41 | 11333 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
11334 | set_bit(vcpu->arch.interrupt.nr, |
11335 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 11336 | } |
16d7a191 | 11337 | |
6dba9403 ML |
11338 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
11339 | { | |
11340 | int i; | |
11341 | ||
11342 | __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); | |
11343 | ||
11344 | if (vcpu->arch.guest_state_protected) | |
11345 | return; | |
11346 | ||
11347 | if (is_pae_paging(vcpu)) { | |
11348 | for (i = 0 ; i < 4 ; i++) | |
11349 | sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); | |
11350 | sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
11351 | } | |
11352 | } | |
11353 | ||
01643c51 KH |
11354 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
11355 | struct kvm_sregs *sregs) | |
11356 | { | |
11357 | vcpu_load(vcpu); | |
11358 | __get_sregs(vcpu, sregs); | |
bcdec41c | 11359 | vcpu_put(vcpu); |
b6c7a5dc HB |
11360 | return 0; |
11361 | } | |
11362 | ||
62d9f0db MT |
11363 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
11364 | struct kvm_mp_state *mp_state) | |
11365 | { | |
4fe09bcf JM |
11366 | int r; |
11367 | ||
fd232561 | 11368 | vcpu_load(vcpu); |
f958bd23 SC |
11369 | if (kvm_mpx_supported()) |
11370 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 11371 | |
4fe09bcf JM |
11372 | r = kvm_apic_accept_events(vcpu); |
11373 | if (r < 0) | |
11374 | goto out; | |
11375 | r = 0; | |
11376 | ||
647daca2 TL |
11377 | if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || |
11378 | vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && | |
11379 | vcpu->arch.pv.pv_unhalted) | |
6aef266c SV |
11380 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; |
11381 | else | |
11382 | mp_state->mp_state = vcpu->arch.mp_state; | |
11383 | ||
4fe09bcf | 11384 | out: |
f958bd23 SC |
11385 | if (kvm_mpx_supported()) |
11386 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 11387 | vcpu_put(vcpu); |
4fe09bcf | 11388 | return r; |
62d9f0db MT |
11389 | } |
11390 | ||
11391 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
11392 | struct kvm_mp_state *mp_state) | |
11393 | { | |
e83dff5e CD |
11394 | int ret = -EINVAL; |
11395 | ||
11396 | vcpu_load(vcpu); | |
11397 | ||
22c6a0ef PB |
11398 | switch (mp_state->mp_state) { |
11399 | case KVM_MP_STATE_UNINITIALIZED: | |
11400 | case KVM_MP_STATE_HALTED: | |
11401 | case KVM_MP_STATE_AP_RESET_HOLD: | |
11402 | case KVM_MP_STATE_INIT_RECEIVED: | |
11403 | case KVM_MP_STATE_SIPI_RECEIVED: | |
11404 | if (!lapic_in_kernel(vcpu)) | |
11405 | goto out; | |
11406 | break; | |
11407 | ||
11408 | case KVM_MP_STATE_RUNNABLE: | |
11409 | break; | |
11410 | ||
11411 | default: | |
e83dff5e | 11412 | goto out; |
22c6a0ef | 11413 | } |
66450a21 | 11414 | |
27cbe7d6 | 11415 | /* |
1b7a1b78 SC |
11416 | * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow |
11417 | * forcing the guest into INIT/SIPI if those events are supposed to be | |
11418 | * blocked. KVM prioritizes SMI over INIT, so reject INIT/SIPI state | |
11419 | * if an SMI is pending as well. | |
27cbe7d6 | 11420 | */ |
1b7a1b78 | 11421 | if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) && |
28bf2888 DH |
11422 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
11423 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 11424 | goto out; |
28bf2888 | 11425 | |
66450a21 JK |
11426 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
11427 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
11428 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
11429 | } else | |
11430 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 11431 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
11432 | |
11433 | ret = 0; | |
11434 | out: | |
11435 | vcpu_put(vcpu); | |
11436 | return ret; | |
62d9f0db MT |
11437 | } |
11438 | ||
7f3d35fd KW |
11439 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
11440 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 11441 | { |
c9b8b07c | 11442 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 11443 | int ret; |
e01c2426 | 11444 | |
8ec4722d | 11445 | init_emulate_ctxt(vcpu); |
c697518a | 11446 | |
7f3d35fd | 11447 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 11448 | has_error_code, error_code); |
1051778f SC |
11449 | if (ret) { |
11450 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
11451 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
11452 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 11453 | return 0; |
1051778f | 11454 | } |
37817f29 | 11455 | |
9d74191a TY |
11456 | kvm_rip_write(vcpu, ctxt->eip); |
11457 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 11458 | return 1; |
37817f29 IE |
11459 | } |
11460 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
11461 | ||
ee69c92b | 11462 | static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 11463 | { |
37b95951 | 11464 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
11465 | /* |
11466 | * When EFER.LME and CR0.PG are set, the processor is in | |
11467 | * 64-bit mode (though maybe in a 32-bit code segment). | |
11468 | * CR4.PAE and EFER.LMA must be set. | |
11469 | */ | |
ee69c92b SC |
11470 | if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) |
11471 | return false; | |
ca29e145 | 11472 | if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) |
c1c35cf7 | 11473 | return false; |
f2981033 LT |
11474 | } else { |
11475 | /* | |
11476 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
11477 | * segment cannot be 64-bit. | |
11478 | */ | |
11479 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
ee69c92b | 11480 | return false; |
f2981033 LT |
11481 | } |
11482 | ||
26a0652c SC |
11483 | return kvm_is_valid_cr4(vcpu, sregs->cr4) && |
11484 | kvm_is_valid_cr0(vcpu, sregs->cr0); | |
f2981033 LT |
11485 | } |
11486 | ||
6dba9403 ML |
11487 | static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, |
11488 | int *mmu_reset_needed, bool update_pdptrs) | |
b6c7a5dc | 11489 | { |
58cb628d | 11490 | struct msr_data apic_base_msr; |
6dba9403 | 11491 | int idx; |
89a27f4d | 11492 | struct desc_ptr dt; |
b4ef9d4e | 11493 | |
ee69c92b | 11494 | if (!kvm_is_valid_sregs(vcpu, sregs)) |
6dba9403 | 11495 | return -EINVAL; |
f2981033 | 11496 | |
d3802286 JM |
11497 | apic_base_msr.data = sregs->apic_base; |
11498 | apic_base_msr.host_initiated = true; | |
11499 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
6dba9403 | 11500 | return -EINVAL; |
6d1068b3 | 11501 | |
5265713a | 11502 | if (vcpu->arch.guest_state_protected) |
6dba9403 | 11503 | return 0; |
5265713a | 11504 | |
89a27f4d GN |
11505 | dt.size = sregs->idt.limit; |
11506 | dt.address = sregs->idt.base; | |
b3646477 | 11507 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
89a27f4d GN |
11508 | dt.size = sregs->gdt.limit; |
11509 | dt.address = sregs->gdt.base; | |
b3646477 | 11510 | static_call(kvm_x86_set_gdt)(vcpu, &dt); |
b6c7a5dc | 11511 | |
ad312c7c | 11512 | vcpu->arch.cr2 = sregs->cr2; |
6dba9403 | 11513 | *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 11514 | vcpu->arch.cr3 = sregs->cr3; |
3883bc9d | 11515 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); |
405329fc | 11516 | static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3); |
b6c7a5dc | 11517 | |
2d3ad1f4 | 11518 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 11519 | |
6dba9403 | 11520 | *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b3646477 | 11521 | static_call(kvm_x86_set_efer)(vcpu, sregs->efer); |
b6c7a5dc | 11522 | |
6dba9403 | 11523 | *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b3646477 | 11524 | static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); |
d7306163 | 11525 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 11526 | |
6dba9403 | 11527 | *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b3646477 | 11528 | static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); |
63f42e02 | 11529 | |
6dba9403 ML |
11530 | if (update_pdptrs) { |
11531 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
11532 | if (is_pae_paging(vcpu)) { | |
2df4a5eb | 11533 | load_pdptrs(vcpu, kvm_read_cr3(vcpu)); |
6dba9403 ML |
11534 | *mmu_reset_needed = 1; |
11535 | } | |
11536 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
7c93be44 | 11537 | } |
b6c7a5dc | 11538 | |
3e6e0aab GT |
11539 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
11540 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
11541 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
11542 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
11543 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
11544 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 11545 | |
3e6e0aab GT |
11546 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
11547 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 11548 | |
5f0269f5 ME |
11549 | update_cr8_intercept(vcpu); |
11550 | ||
9c3e4aab | 11551 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 11552 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 11553 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 11554 | !is_protmode(vcpu)) |
9c3e4aab MT |
11555 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
11556 | ||
6dba9403 ML |
11557 | return 0; |
11558 | } | |
11559 | ||
11560 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
11561 | { | |
11562 | int pending_vec, max_bits; | |
11563 | int mmu_reset_needed = 0; | |
11564 | int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); | |
11565 | ||
11566 | if (ret) | |
11567 | return ret; | |
11568 | ||
11569 | if (mmu_reset_needed) | |
11570 | kvm_mmu_reset_context(vcpu); | |
11571 | ||
5265713a TL |
11572 | max_bits = KVM_NR_INTERRUPTS; |
11573 | pending_vec = find_first_bit( | |
11574 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6dba9403 | 11575 | |
5265713a TL |
11576 | if (pending_vec < max_bits) { |
11577 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
11578 | pr_debug("Set back pending irq %d\n", pending_vec); | |
6dba9403 | 11579 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5265713a | 11580 | } |
6dba9403 ML |
11581 | return 0; |
11582 | } | |
5265713a | 11583 | |
6dba9403 ML |
11584 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
11585 | { | |
11586 | int mmu_reset_needed = 0; | |
11587 | bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
11588 | bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && | |
11589 | !(sregs2->efer & EFER_LMA); | |
11590 | int i, ret; | |
3842d135 | 11591 | |
6dba9403 ML |
11592 | if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) |
11593 | return -EINVAL; | |
11594 | ||
11595 | if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) | |
11596 | return -EINVAL; | |
11597 | ||
11598 | ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, | |
11599 | &mmu_reset_needed, !valid_pdptrs); | |
11600 | if (ret) | |
11601 | return ret; | |
11602 | ||
11603 | if (valid_pdptrs) { | |
11604 | for (i = 0; i < 4 ; i++) | |
11605 | kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); | |
11606 | ||
11607 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); | |
11608 | mmu_reset_needed = 1; | |
158a48ec | 11609 | vcpu->arch.pdptrs_from_userspace = true; |
6dba9403 ML |
11610 | } |
11611 | if (mmu_reset_needed) | |
11612 | kvm_mmu_reset_context(vcpu); | |
11613 | return 0; | |
01643c51 KH |
11614 | } |
11615 | ||
11616 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
11617 | struct kvm_sregs *sregs) | |
11618 | { | |
11619 | int ret; | |
11620 | ||
11621 | vcpu_load(vcpu); | |
11622 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
11623 | vcpu_put(vcpu); |
11624 | return ret; | |
b6c7a5dc HB |
11625 | } |
11626 | ||
cae72dcc ML |
11627 | static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) |
11628 | { | |
320af55a | 11629 | bool set = false; |
cae72dcc | 11630 | struct kvm_vcpu *vcpu; |
46808a4c | 11631 | unsigned long i; |
cae72dcc | 11632 | |
0047fb33 SC |
11633 | if (!enable_apicv) |
11634 | return; | |
11635 | ||
cae72dcc ML |
11636 | down_write(&kvm->arch.apicv_update_lock); |
11637 | ||
11638 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
11639 | if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { | |
320af55a | 11640 | set = true; |
cae72dcc ML |
11641 | break; |
11642 | } | |
11643 | } | |
320af55a | 11644 | __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set); |
cae72dcc ML |
11645 | up_write(&kvm->arch.apicv_update_lock); |
11646 | } | |
11647 | ||
d0bfb940 JK |
11648 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
11649 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 11650 | { |
355be0b9 | 11651 | unsigned long rflags; |
ae675ef0 | 11652 | int i, r; |
b6c7a5dc | 11653 | |
8d4846b9 TL |
11654 | if (vcpu->arch.guest_state_protected) |
11655 | return -EINVAL; | |
11656 | ||
66b56562 CD |
11657 | vcpu_load(vcpu); |
11658 | ||
4f926bf2 JK |
11659 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
11660 | r = -EBUSY; | |
7709aba8 | 11661 | if (kvm_is_exception_pending(vcpu)) |
2122ff5e | 11662 | goto out; |
4f926bf2 JK |
11663 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
11664 | kvm_queue_exception(vcpu, DB_VECTOR); | |
11665 | else | |
11666 | kvm_queue_exception(vcpu, BP_VECTOR); | |
11667 | } | |
11668 | ||
91586a3b JK |
11669 | /* |
11670 | * Read rflags as long as potentially injected trace flags are still | |
11671 | * filtered out. | |
11672 | */ | |
11673 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
11674 | |
11675 | vcpu->guest_debug = dbg->control; | |
11676 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
11677 | vcpu->guest_debug = 0; | |
11678 | ||
11679 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
11680 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
11681 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 11682 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
11683 | } else { |
11684 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
11685 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 11686 | } |
c8639010 | 11687 | kvm_update_dr7(vcpu); |
ae675ef0 | 11688 | |
f92653ee | 11689 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
e87e46d5 | 11690 | vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); |
94fe45da | 11691 | |
91586a3b JK |
11692 | /* |
11693 | * Trigger an rflags update that will inject or remove the trace | |
11694 | * flags. | |
11695 | */ | |
11696 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 11697 | |
b3646477 | 11698 | static_call(kvm_x86_update_exception_bitmap)(vcpu); |
b6c7a5dc | 11699 | |
cae72dcc ML |
11700 | kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); |
11701 | ||
4f926bf2 | 11702 | r = 0; |
d0bfb940 | 11703 | |
2122ff5e | 11704 | out: |
66b56562 | 11705 | vcpu_put(vcpu); |
b6c7a5dc HB |
11706 | return r; |
11707 | } | |
11708 | ||
8b006791 ZX |
11709 | /* |
11710 | * Translate a guest virtual address to a guest physical address. | |
11711 | */ | |
11712 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
11713 | struct kvm_translation *tr) | |
11714 | { | |
11715 | unsigned long vaddr = tr->linear_address; | |
11716 | gpa_t gpa; | |
f656ce01 | 11717 | int idx; |
8b006791 | 11718 | |
1da5b61d CD |
11719 | vcpu_load(vcpu); |
11720 | ||
f656ce01 | 11721 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 11722 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 11723 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 | 11724 | tr->physical_address = gpa; |
6e1d2a3f | 11725 | tr->valid = gpa != INVALID_GPA; |
8b006791 ZX |
11726 | tr->writeable = 1; |
11727 | tr->usermode = 0; | |
8b006791 | 11728 | |
1da5b61d | 11729 | vcpu_put(vcpu); |
8b006791 ZX |
11730 | return 0; |
11731 | } | |
11732 | ||
d0752060 HB |
11733 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
11734 | { | |
1393123e | 11735 | struct fxregs_state *fxsave; |
d0752060 | 11736 | |
d69c1382 | 11737 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) |
ed02b213 TL |
11738 | return 0; |
11739 | ||
1393123e | 11740 | vcpu_load(vcpu); |
d0752060 | 11741 | |
d69c1382 | 11742 | fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; |
d0752060 HB |
11743 | memcpy(fpu->fpr, fxsave->st_space, 128); |
11744 | fpu->fcw = fxsave->cwd; | |
11745 | fpu->fsw = fxsave->swd; | |
11746 | fpu->ftwx = fxsave->twd; | |
11747 | fpu->last_opcode = fxsave->fop; | |
11748 | fpu->last_ip = fxsave->rip; | |
11749 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 11750 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 11751 | |
1393123e | 11752 | vcpu_put(vcpu); |
d0752060 HB |
11753 | return 0; |
11754 | } | |
11755 | ||
11756 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
11757 | { | |
6a96bc7f CD |
11758 | struct fxregs_state *fxsave; |
11759 | ||
d69c1382 | 11760 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) |
ed02b213 TL |
11761 | return 0; |
11762 | ||
6a96bc7f CD |
11763 | vcpu_load(vcpu); |
11764 | ||
d69c1382 | 11765 | fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; |
d0752060 | 11766 | |
d0752060 HB |
11767 | memcpy(fxsave->st_space, fpu->fpr, 128); |
11768 | fxsave->cwd = fpu->fcw; | |
11769 | fxsave->swd = fpu->fsw; | |
11770 | fxsave->twd = fpu->ftwx; | |
11771 | fxsave->fop = fpu->last_opcode; | |
11772 | fxsave->rip = fpu->last_ip; | |
11773 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 11774 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 11775 | |
6a96bc7f | 11776 | vcpu_put(vcpu); |
d0752060 HB |
11777 | return 0; |
11778 | } | |
11779 | ||
01643c51 KH |
11780 | static void store_regs(struct kvm_vcpu *vcpu) |
11781 | { | |
11782 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
11783 | ||
11784 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
11785 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
11786 | ||
11787 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
11788 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
11789 | ||
11790 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
11791 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
11792 | vcpu, &vcpu->run->s.regs.events); | |
11793 | } | |
11794 | ||
11795 | static int sync_regs(struct kvm_vcpu *vcpu) | |
11796 | { | |
01643c51 KH |
11797 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { |
11798 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
11799 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
11800 | } | |
11801 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
11802 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
11803 | return -EINVAL; | |
11804 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
11805 | } | |
11806 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
11807 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
11808 | vcpu, &vcpu->run->s.regs.events)) | |
11809 | return -EINVAL; | |
11810 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
11811 | } | |
11812 | ||
11813 | return 0; | |
11814 | } | |
11815 | ||
897cc38e | 11816 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 11817 | { |
1d5e740d | 11818 | if (kvm_check_tsc_unstable() && kvm->created_vcpus) |
8d20bd63 | 11819 | pr_warn_once("SMP vm created on host with unstable TSC; " |
897cc38e | 11820 | "guest TSC will not be reliable\n"); |
7f1ea208 | 11821 | |
35875316 ZG |
11822 | if (!kvm->arch.max_vcpu_ids) |
11823 | kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS; | |
11824 | ||
11825 | if (id >= kvm->arch.max_vcpu_ids) | |
11826 | return -EINVAL; | |
11827 | ||
d588bb9b | 11828 | return static_call(kvm_x86_vcpu_precreate)(kvm); |
e9b11c17 ZX |
11829 | } |
11830 | ||
e529ef66 | 11831 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 11832 | { |
95a0d01e SC |
11833 | struct page *page; |
11834 | int r; | |
c447e76b | 11835 | |
63f5a190 | 11836 | vcpu->arch.last_vmentry_cpu = -1; |
7117003f SC |
11837 | vcpu->arch.regs_avail = ~0; |
11838 | vcpu->arch.regs_dirty = ~0; | |
63f5a190 | 11839 | |
8c82a0b3 | 11840 | kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm, vcpu, KVM_HOST_USES_PFN); |
52491a38 | 11841 | |
95a0d01e SC |
11842 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
11843 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
11844 | else | |
11845 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 11846 | |
95a0d01e SC |
11847 | r = kvm_mmu_create(vcpu); |
11848 | if (r < 0) | |
11849 | return r; | |
11850 | ||
11851 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
11852 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
11853 | if (r < 0) | |
11854 | goto fail_mmu_destroy; | |
423ecfea SC |
11855 | |
11856 | /* | |
11857 | * Defer evaluating inhibits until the vCPU is first run, as | |
11858 | * this vCPU will not get notified of any changes until this | |
11859 | * vCPU is visible to other vCPUs (marked online and added to | |
11860 | * the set of vCPUs). Opportunistically mark APICv active as | |
11861 | * VMX in particularly is highly unlikely to have inhibits. | |
11862 | * Ignore the current per-VM APICv state so that vCPU creation | |
11863 | * is guaranteed to run with a deterministic value, the request | |
11864 | * will ensure the vCPU gets the correct state before VM-Entry. | |
11865 | */ | |
11866 | if (enable_apicv) { | |
ce0a58f4 | 11867 | vcpu->arch.apic->apicv_active = true; |
423ecfea SC |
11868 | kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu); |
11869 | } | |
95a0d01e | 11870 | } else |
6e4e3b4d | 11871 | static_branch_inc(&kvm_has_noapic_vcpu); |
95a0d01e SC |
11872 | |
11873 | r = -ENOMEM; | |
11874 | ||
93bb59ca | 11875 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
95a0d01e SC |
11876 | if (!page) |
11877 | goto fail_free_lapic; | |
11878 | vcpu->arch.pio_data = page_address(page); | |
11879 | ||
087acc4e | 11880 | vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64), |
95a0d01e | 11881 | GFP_KERNEL_ACCOUNT); |
281b5278 JW |
11882 | vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64), |
11883 | GFP_KERNEL_ACCOUNT); | |
11884 | if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks) | |
3c0ba05c | 11885 | goto fail_free_mce_banks; |
95a0d01e SC |
11886 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; |
11887 | ||
11888 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
11889 | GFP_KERNEL_ACCOUNT)) | |
11890 | goto fail_free_mce_banks; | |
11891 | ||
c9b8b07c SC |
11892 | if (!alloc_emulate_ctxt(vcpu)) |
11893 | goto free_wbinvd_dirty_mask; | |
11894 | ||
d69c1382 | 11895 | if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { |
8d20bd63 | 11896 | pr_err("failed to allocate vcpu's fpu\n"); |
c9b8b07c | 11897 | goto free_emulate_ctxt; |
95a0d01e SC |
11898 | } |
11899 | ||
95a0d01e | 11900 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
a8ac864a | 11901 | vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); |
95a0d01e SC |
11902 | |
11903 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
11904 | ||
11905 | kvm_async_pf_hash_reset(vcpu); | |
6c6f82be SC |
11906 | |
11907 | vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap; | |
95a0d01e SC |
11908 | kvm_pmu_init(vcpu); |
11909 | ||
11910 | vcpu->arch.pending_external_vector = -1; | |
11911 | vcpu->arch.preempted_in_kernel = false; | |
11912 | ||
3c86c0d3 VP |
11913 | #if IS_ENABLED(CONFIG_HYPERV) |
11914 | vcpu->arch.hv_root_tdp = INVALID_PAGE; | |
11915 | #endif | |
11916 | ||
b3646477 | 11917 | r = static_call(kvm_x86_vcpu_create)(vcpu); |
95a0d01e SC |
11918 | if (r) |
11919 | goto free_guest_fpu; | |
e9b11c17 | 11920 | |
0cf9135b | 11921 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 11922 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
942c2490 | 11923 | kvm_xen_init_vcpu(vcpu); |
19efffa2 | 11924 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 11925 | vcpu_load(vcpu); |
ffbb61d0 | 11926 | kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz); |
d28bc9dd | 11927 | kvm_vcpu_reset(vcpu, false); |
c9060662 | 11928 | kvm_init_mmu(vcpu); |
e9b11c17 | 11929 | vcpu_put(vcpu); |
ec7660cc | 11930 | return 0; |
95a0d01e SC |
11931 | |
11932 | free_guest_fpu: | |
d69c1382 | 11933 | fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); |
c9b8b07c SC |
11934 | free_emulate_ctxt: |
11935 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
11936 | free_wbinvd_dirty_mask: |
11937 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
11938 | fail_free_mce_banks: | |
11939 | kfree(vcpu->arch.mce_banks); | |
281b5278 | 11940 | kfree(vcpu->arch.mci_ctl2_banks); |
95a0d01e SC |
11941 | free_page((unsigned long)vcpu->arch.pio_data); |
11942 | fail_free_lapic: | |
11943 | kvm_free_lapic(vcpu); | |
11944 | fail_mmu_destroy: | |
11945 | kvm_mmu_destroy(vcpu); | |
11946 | return r; | |
e9b11c17 ZX |
11947 | } |
11948 | ||
31928aa5 | 11949 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 11950 | { |
332967a3 | 11951 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 11952 | |
ec7660cc | 11953 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 11954 | return; |
ec7660cc | 11955 | vcpu_load(vcpu); |
0c899c25 | 11956 | kvm_synchronize_tsc(vcpu, 0); |
42897d86 | 11957 | vcpu_put(vcpu); |
2d5ba19b MT |
11958 | |
11959 | /* poll control enabled by default */ | |
11960 | vcpu->arch.msr_kvm_poll_control = 1; | |
11961 | ||
ec7660cc | 11962 | mutex_unlock(&vcpu->mutex); |
42897d86 | 11963 | |
b34de572 WL |
11964 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
11965 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
11966 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
11967 | } |
11968 | ||
d40ccc62 | 11969 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 11970 | { |
95a0d01e | 11971 | int idx; |
344d9588 | 11972 | |
50b143e1 | 11973 | kvmclock_reset(vcpu); |
e9b11c17 | 11974 | |
b3646477 | 11975 | static_call(kvm_x86_vcpu_free)(vcpu); |
50b143e1 | 11976 | |
c9b8b07c | 11977 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 | 11978 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
d69c1382 | 11979 | fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); |
95a0d01e | 11980 | |
a795cd43 | 11981 | kvm_xen_destroy_vcpu(vcpu); |
95a0d01e SC |
11982 | kvm_hv_vcpu_uninit(vcpu); |
11983 | kvm_pmu_destroy(vcpu); | |
11984 | kfree(vcpu->arch.mce_banks); | |
281b5278 | 11985 | kfree(vcpu->arch.mci_ctl2_banks); |
95a0d01e SC |
11986 | kvm_free_lapic(vcpu); |
11987 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
11988 | kvm_mmu_destroy(vcpu); | |
11989 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
11990 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 11991 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e | 11992 | if (!lapic_in_kernel(vcpu)) |
6e4e3b4d | 11993 | static_branch_dec(&kvm_has_noapic_vcpu); |
e9b11c17 ZX |
11994 | } |
11995 | ||
d28bc9dd | 11996 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 11997 | { |
25b97845 | 11998 | struct kvm_cpuid_entry2 *cpuid_0x1; |
0aa18375 | 11999 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
4c72ab5a | 12000 | unsigned long new_cr0; |
0aa18375 | 12001 | |
62dd57dd SC |
12002 | /* |
12003 | * Several of the "set" flows, e.g. ->set_cr0(), read other registers | |
12004 | * to handle side effects. RESET emulation hits those flows and relies | |
12005 | * on emulated/virtualized registers, including those that are loaded | |
12006 | * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel | |
12007 | * to detect improper or missing initialization. | |
12008 | */ | |
12009 | WARN_ON_ONCE(!init_event && | |
12010 | (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); | |
0aa18375 | 12011 | |
ed129ec9 ML |
12012 | /* |
12013 | * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's | |
12014 | * possible to INIT the vCPU while L2 is active. Force the vCPU back | |
12015 | * into L1 as EFER.SVME is cleared on INIT (along with all other EFER | |
12016 | * bits), i.e. virtualization is disabled. | |
12017 | */ | |
12018 | if (is_guest_mode(vcpu)) | |
12019 | kvm_leave_nested(vcpu); | |
12020 | ||
b7e31be3 RK |
12021 | kvm_lapic_reset(vcpu, init_event); |
12022 | ||
ed129ec9 | 12023 | WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu)); |
e69fab5d PB |
12024 | vcpu->arch.hflags = 0; |
12025 | ||
c43203ca | 12026 | vcpu->arch.smi_pending = 0; |
52797bf9 | 12027 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
12028 | atomic_set(&vcpu->arch.nmi_queued, 0); |
12029 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 12030 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
12031 | kvm_clear_interrupt_queue(vcpu); |
12032 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 12033 | |
42dbaa5a | 12034 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 12035 | kvm_update_dr0123(vcpu); |
9a3ecd5e | 12036 | vcpu->arch.dr6 = DR6_ACTIVE_LOW; |
42dbaa5a | 12037 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 12038 | kvm_update_dr7(vcpu); |
42dbaa5a | 12039 | |
1119022c NA |
12040 | vcpu->arch.cr2 = 0; |
12041 | ||
3842d135 | 12042 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
12043 | vcpu->arch.apf.msr_en_val = 0; |
12044 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 12045 | vcpu->arch.st.msr_val = 0; |
3842d135 | 12046 | |
12f9a48f GC |
12047 | kvmclock_reset(vcpu); |
12048 | ||
af585b92 GN |
12049 | kvm_clear_async_pf_completion_queue(vcpu); |
12050 | kvm_async_pf_hash_reset(vcpu); | |
12051 | vcpu->arch.apf.halted = false; | |
3842d135 | 12052 | |
d69c1382 TG |
12053 | if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { |
12054 | struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; | |
a554d207 WL |
12055 | |
12056 | /* | |
a61353ac SC |
12057 | * All paths that lead to INIT are required to load the guest's |
12058 | * FPU state (because most paths are buried in KVM_RUN). | |
a554d207 | 12059 | */ |
f775b13e RR |
12060 | if (init_event) |
12061 | kvm_put_guest_fpu(vcpu); | |
087df48c TG |
12062 | |
12063 | fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); | |
12064 | fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); | |
12065 | ||
f775b13e RR |
12066 | if (init_event) |
12067 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
12068 | } |
12069 | ||
64d60670 | 12070 | if (!init_event) { |
d28bc9dd | 12071 | kvm_pmu_reset(vcpu); |
64d60670 | 12072 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 12073 | |
db2336a8 | 12074 | vcpu->arch.msr_misc_features_enables = 0; |
9fc22296 SC |
12075 | vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | |
12076 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL; | |
a554d207 | 12077 | |
05a9e065 LX |
12078 | __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP); |
12079 | __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true); | |
64d60670 | 12080 | } |
f5132b01 | 12081 | |
ff8828c8 | 12082 | /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ |
66f7b72e | 12083 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
ff8828c8 | 12084 | kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); |
66f7b72e | 12085 | |
49d8665c SC |
12086 | /* |
12087 | * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) | |
12088 | * if no CPUID match is found. Note, it's impossible to get a match at | |
12089 | * RESET since KVM emulates RESET before exposing the vCPU to userspace, | |
25b97845 SC |
12090 | * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry |
12091 | * on RESET. But, go through the motions in case that's ever remedied. | |
49d8665c | 12092 | */ |
277ad7d5 | 12093 | cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1); |
25b97845 | 12094 | kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); |
49d8665c | 12095 | |
b3646477 | 12096 | static_call(kvm_x86_vcpu_reset)(vcpu, init_event); |
0aa18375 | 12097 | |
f39e805e SC |
12098 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); |
12099 | kvm_rip_write(vcpu, 0xfff0); | |
12100 | ||
03a6e840 SC |
12101 | vcpu->arch.cr3 = 0; |
12102 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); | |
12103 | ||
4c72ab5a SC |
12104 | /* |
12105 | * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions | |
12106 | * of Intel's SDM list CD/NW as being set on INIT, but they contradict | |
12107 | * (or qualify) that with a footnote stating that CD/NW are preserved. | |
12108 | */ | |
12109 | new_cr0 = X86_CR0_ET; | |
12110 | if (init_event) | |
12111 | new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); | |
12112 | else | |
12113 | new_cr0 |= X86_CR0_NW | X86_CR0_CD; | |
12114 | ||
12115 | static_call(kvm_x86_set_cr0)(vcpu, new_cr0); | |
f39e805e SC |
12116 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
12117 | static_call(kvm_x86_set_efer)(vcpu, 0); | |
12118 | static_call(kvm_x86_update_exception_bitmap)(vcpu); | |
12119 | ||
0aa18375 | 12120 | /* |
b5f61c03 PB |
12121 | * On the standard CR0/CR4/EFER modification paths, there are several |
12122 | * complex conditions determining whether the MMU has to be reset and/or | |
12123 | * which PCIDs have to be flushed. However, CR0.WP and the paging-related | |
12124 | * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush | |
12125 | * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as | |
12126 | * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here. | |
0aa18375 | 12127 | */ |
b5f61c03 PB |
12128 | if (old_cr0 & X86_CR0_PG) { |
12129 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
0aa18375 | 12130 | kvm_mmu_reset_context(vcpu); |
b5f61c03 | 12131 | } |
df37ed38 SC |
12132 | |
12133 | /* | |
12134 | * Intel's SDM states that all TLB entries are flushed on INIT. AMD's | |
12135 | * APM states the TLBs are untouched by INIT, but it also states that | |
12136 | * the TLBs are flushed on "External initialization of the processor." | |
12137 | * Flush the guest TLB regardless of vendor, there is no meaningful | |
12138 | * benefit in relying on the guest to flush the TLB immediately after | |
12139 | * INIT. A spurious TLB flush is benign and likely negligible from a | |
12140 | * performance perspective. | |
12141 | */ | |
12142 | if (init_event) | |
12143 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
e9b11c17 | 12144 | } |
265e4353 | 12145 | EXPORT_SYMBOL_GPL(kvm_vcpu_reset); |
e9b11c17 | 12146 | |
2b4a273b | 12147 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
12148 | { |
12149 | struct kvm_segment cs; | |
12150 | ||
12151 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
12152 | cs.selector = vector << 8; | |
12153 | cs.base = vector << 12; | |
12154 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
12155 | kvm_rip_write(vcpu, 0); | |
e9b11c17 | 12156 | } |
647daca2 | 12157 | EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); |
e9b11c17 | 12158 | |
13a34e06 | 12159 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 12160 | { |
ca84d1a2 ZA |
12161 | struct kvm *kvm; |
12162 | struct kvm_vcpu *vcpu; | |
46808a4c | 12163 | unsigned long i; |
0dd6a6ed ZA |
12164 | int ret; |
12165 | u64 local_tsc; | |
12166 | u64 max_tsc = 0; | |
12167 | bool stable, backwards_tsc = false; | |
18863bdd | 12168 | |
7e34fbd0 | 12169 | kvm_user_return_msr_cpu_online(); |
c82a5c5c CG |
12170 | |
12171 | ret = kvm_x86_check_processor_compatibility(); | |
12172 | if (ret) | |
12173 | return ret; | |
12174 | ||
b3646477 | 12175 | ret = static_call(kvm_x86_hardware_enable)(); |
0dd6a6ed ZA |
12176 | if (ret != 0) |
12177 | return ret; | |
12178 | ||
4ea1636b | 12179 | local_tsc = rdtsc(); |
b0c39dc6 | 12180 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
12181 | list_for_each_entry(kvm, &vm_list, vm_list) { |
12182 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
12183 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 12184 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
12185 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
12186 | backwards_tsc = true; | |
12187 | if (vcpu->arch.last_host_tsc > max_tsc) | |
12188 | max_tsc = vcpu->arch.last_host_tsc; | |
12189 | } | |
12190 | } | |
12191 | } | |
12192 | ||
12193 | /* | |
12194 | * Sometimes, even reliable TSCs go backwards. This happens on | |
12195 | * platforms that reset TSC during suspend or hibernate actions, but | |
12196 | * maintain synchronization. We must compensate. Fortunately, we can | |
12197 | * detect that condition here, which happens early in CPU bringup, | |
12198 | * before any KVM threads can be running. Unfortunately, we can't | |
12199 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
12200 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 12201 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
12202 | * variables that haven't been updated yet. |
12203 | * | |
12204 | * So we simply find the maximum observed TSC above, then record the | |
12205 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
12206 | * the adjustment will be applied. Note that we accumulate | |
12207 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
12208 | * gets a chance to run again. In the event that no KVM threads get a | |
12209 | * chance to run, we will miss the entire elapsed period, as we'll have | |
12210 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
12211 | * loose cycle time. This isn't too big a deal, since the loss will be | |
12212 | * uniform across all VCPUs (not to mention the scenario is extremely | |
12213 | * unlikely). It is possible that a second hibernate recovery happens | |
12214 | * much faster than a first, causing the observed TSC here to be | |
12215 | * smaller; this would require additional padding adjustment, which is | |
12216 | * why we set last_host_tsc to the local tsc observed here. | |
12217 | * | |
12218 | * N.B. - this code below runs only on platforms with reliable TSC, | |
12219 | * as that is the only way backwards_tsc is set above. Also note | |
12220 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
12221 | * have the same delta_cyc adjustment applied if backwards_tsc | |
12222 | * is detected. Note further, this adjustment is only done once, | |
12223 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
12224 | * called multiple times (one for each physical CPU bringup). | |
12225 | * | |
4a969980 | 12226 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
12227 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
12228 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
12229 | * guarantee that they stay in perfect synchronization. | |
12230 | */ | |
12231 | if (backwards_tsc) { | |
12232 | u64 delta_cyc = max_tsc - local_tsc; | |
12233 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 12234 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
12235 | kvm_for_each_vcpu(i, vcpu, kvm) { |
12236 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
12237 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 12238 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
12239 | } |
12240 | ||
12241 | /* | |
12242 | * We have to disable TSC offset matching.. if you were | |
12243 | * booting a VM while issuing an S4 host suspend.... | |
12244 | * you may have some problem. Solving this issue is | |
12245 | * left as an exercise to the reader. | |
12246 | */ | |
12247 | kvm->arch.last_tsc_nsec = 0; | |
12248 | kvm->arch.last_tsc_write = 0; | |
12249 | } | |
12250 | ||
12251 | } | |
12252 | return 0; | |
e9b11c17 ZX |
12253 | } |
12254 | ||
13a34e06 | 12255 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 12256 | { |
b3646477 | 12257 | static_call(kvm_x86_hardware_disable)(); |
13a34e06 | 12258 | drop_user_return_notifiers(); |
e9b11c17 ZX |
12259 | } |
12260 | ||
d71ba788 PB |
12261 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) |
12262 | { | |
12263 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
12264 | } | |
d71ba788 PB |
12265 | |
12266 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
12267 | { | |
12268 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
12269 | } |
12270 | ||
6e4e3b4d CL |
12271 | __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); |
12272 | EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); | |
54e9818f | 12273 | |
e790d9ef RK |
12274 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
12275 | { | |
b35e5548 LX |
12276 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
12277 | ||
c595ceee | 12278 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
12279 | if (pmu->version && unlikely(pmu->event_count)) { |
12280 | pmu->need_cleanup = true; | |
12281 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
12282 | } | |
b3646477 | 12283 | static_call(kvm_x86_sched_in)(vcpu, cpu); |
e790d9ef RK |
12284 | } |
12285 | ||
562b6b08 SC |
12286 | void kvm_arch_free_vm(struct kvm *kvm) |
12287 | { | |
05f04ae4 | 12288 | kfree(to_kvm_hv(kvm)->hv_pa_pg); |
78b497f2 | 12289 | __kvm_arch_free_vm(kvm); |
e790d9ef RK |
12290 | } |
12291 | ||
562b6b08 | 12292 | |
e08b9637 | 12293 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 12294 | { |
eb7511bf | 12295 | int ret; |
869b4421 | 12296 | unsigned long flags; |
eb7511bf | 12297 | |
e08b9637 CO |
12298 | if (type) |
12299 | return -EINVAL; | |
12300 | ||
eb7511bf HZ |
12301 | ret = kvm_page_track_init(kvm); |
12302 | if (ret) | |
a1a39128 PB |
12303 | goto out; |
12304 | ||
12305 | ret = kvm_mmu_init_vm(kvm); | |
12306 | if (ret) | |
12307 | goto out_page_track; | |
eb7511bf | 12308 | |
b24ede22 JS |
12309 | ret = static_call(kvm_x86_vm_init)(kvm); |
12310 | if (ret) | |
12311 | goto out_uninit_mmu; | |
12312 | ||
6ef768fa | 12313 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
4d5c5d0f | 12314 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 12315 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 12316 | |
5550af4d SY |
12317 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
12318 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
12319 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
12320 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
12321 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 12322 | |
038f8c11 | 12323 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 12324 | mutex_init(&kvm->arch.apic_map_lock); |
869b4421 | 12325 | seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); |
8171cd68 | 12326 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
869b4421 PB |
12327 | |
12328 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); | |
d828199e | 12329 | pvclock_update_vm_gtod_copy(kvm); |
869b4421 | 12330 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
53f658b3 | 12331 | |
741e511b | 12332 | kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz; |
6fbbde9a | 12333 | kvm->arch.guest_can_read_msr_platform_info = true; |
ba7bb663 | 12334 | kvm->arch.enable_pmu = enable_pmu; |
6fbbde9a | 12335 | |
3c86c0d3 VP |
12336 | #if IS_ENABLED(CONFIG_HYPERV) |
12337 | spin_lock_init(&kvm->arch.hv_root_tdp_lock); | |
12338 | kvm->arch.hv_root_tdp = INVALID_PAGE; | |
12339 | #endif | |
12340 | ||
7e44e449 | 12341 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 12342 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 12343 | |
4651fc56 | 12344 | kvm_apicv_init(kvm); |
cbc0236a | 12345 | kvm_hv_init_vm(kvm); |
319afe68 | 12346 | kvm_xen_init_vm(kvm); |
0eb05bf2 | 12347 | |
b24ede22 | 12348 | return 0; |
a1a39128 | 12349 | |
b24ede22 JS |
12350 | out_uninit_mmu: |
12351 | kvm_mmu_uninit_vm(kvm); | |
a1a39128 PB |
12352 | out_page_track: |
12353 | kvm_page_track_cleanup(kvm); | |
12354 | out: | |
12355 | return ret; | |
d19a9cd2 ZX |
12356 | } |
12357 | ||
1aa9b957 JS |
12358 | int kvm_arch_post_init_vm(struct kvm *kvm) |
12359 | { | |
12360 | return kvm_mmu_post_init_vm(kvm); | |
12361 | } | |
12362 | ||
d19a9cd2 ZX |
12363 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
12364 | { | |
ec7660cc | 12365 | vcpu_load(vcpu); |
d19a9cd2 ZX |
12366 | kvm_mmu_unload(vcpu); |
12367 | vcpu_put(vcpu); | |
12368 | } | |
12369 | ||
6fcee03d | 12370 | static void kvm_unload_vcpu_mmus(struct kvm *kvm) |
d19a9cd2 | 12371 | { |
46808a4c | 12372 | unsigned long i; |
988a2cae | 12373 | struct kvm_vcpu *vcpu; |
d19a9cd2 | 12374 | |
af585b92 GN |
12375 | kvm_for_each_vcpu(i, vcpu, kvm) { |
12376 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 12377 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 12378 | } |
d19a9cd2 ZX |
12379 | } |
12380 | ||
ad8ba2cd SY |
12381 | void kvm_arch_sync_events(struct kvm *kvm) |
12382 | { | |
332967a3 | 12383 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 12384 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 12385 | kvm_free_pit(kvm); |
ad8ba2cd SY |
12386 | } |
12387 | ||
ff5a983c PX |
12388 | /** |
12389 | * __x86_set_memory_region: Setup KVM internal memory slot | |
12390 | * | |
12391 | * @kvm: the kvm pointer to the VM. | |
12392 | * @id: the slot ID to setup. | |
12393 | * @gpa: the GPA to install the slot (unused when @size == 0). | |
12394 | * @size: the size of the slot. Set to zero to uninstall a slot. | |
12395 | * | |
12396 | * This function helps to setup a KVM internal memory slot. Specify | |
12397 | * @size > 0 to install a new slot, while @size == 0 to uninstall a | |
12398 | * slot. The return code can be one of the following: | |
12399 | * | |
12400 | * HVA: on success (uninstall will return a bogus HVA) | |
12401 | * -errno: on error | |
12402 | * | |
12403 | * The caller should always use IS_ERR() to check the return value | |
12404 | * before use. Note, the KVM internal memory slots are guaranteed to | |
12405 | * remain valid and unchanged until the VM is destroyed, i.e., the | |
12406 | * GPA->HVA translation will not change. However, the HVA is a user | |
12407 | * address, i.e. its accessibility is not guaranteed, and must be | |
12408 | * accessed via __copy_{to,from}_user(). | |
12409 | */ | |
12410 | void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, | |
12411 | u32 size) | |
9da0e4d5 PB |
12412 | { |
12413 | int i, r; | |
3f649ab7 | 12414 | unsigned long hva, old_npages; |
f0d648bd | 12415 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 12416 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
12417 | |
12418 | /* Called with kvm->slots_lock held. */ | |
1d8007bd | 12419 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
ff5a983c | 12420 | return ERR_PTR_USR(-EINVAL); |
9da0e4d5 | 12421 | |
f0d648bd PB |
12422 | slot = id_to_memslot(slots, id); |
12423 | if (size) { | |
0577d1ab | 12424 | if (slot && slot->npages) |
ff5a983c | 12425 | return ERR_PTR_USR(-EEXIST); |
f0d648bd PB |
12426 | |
12427 | /* | |
12428 | * MAP_SHARED to prevent internal slot pages from being moved | |
12429 | * by fork()/COW. | |
12430 | */ | |
12431 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
12432 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
2eb398df | 12433 | if (IS_ERR_VALUE(hva)) |
ff5a983c | 12434 | return (void __user *)hva; |
f0d648bd | 12435 | } else { |
0577d1ab | 12436 | if (!slot || !slot->npages) |
46914534 | 12437 | return NULL; |
f0d648bd | 12438 | |
0577d1ab | 12439 | old_npages = slot->npages; |
b66f9bab | 12440 | hva = slot->userspace_addr; |
f0d648bd PB |
12441 | } |
12442 | ||
9da0e4d5 | 12443 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 12444 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 12445 | |
1d8007bd PB |
12446 | m.slot = id | (i << 16); |
12447 | m.flags = 0; | |
12448 | m.guest_phys_addr = gpa; | |
f0d648bd | 12449 | m.userspace_addr = hva; |
1d8007bd | 12450 | m.memory_size = size; |
9da0e4d5 PB |
12451 | r = __kvm_set_memory_region(kvm, &m); |
12452 | if (r < 0) | |
ff5a983c | 12453 | return ERR_PTR_USR(r); |
9da0e4d5 PB |
12454 | } |
12455 | ||
103c763c | 12456 | if (!size) |
0577d1ab | 12457 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 12458 | |
ff5a983c | 12459 | return (void __user *)hva; |
9da0e4d5 PB |
12460 | } |
12461 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
12462 | ||
1aa9b957 JS |
12463 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
12464 | { | |
12465 | kvm_mmu_pre_destroy_vm(kvm); | |
12466 | } | |
12467 | ||
d19a9cd2 ZX |
12468 | void kvm_arch_destroy_vm(struct kvm *kvm) |
12469 | { | |
27469d29 AH |
12470 | if (current->mm == kvm->mm) { |
12471 | /* | |
12472 | * Free memory regions allocated on behalf of userspace, | |
f7081834 | 12473 | * unless the memory map has changed due to process exit |
27469d29 AH |
12474 | * or fd copying. |
12475 | */ | |
6a3c623b PX |
12476 | mutex_lock(&kvm->slots_lock); |
12477 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
12478 | 0, 0); | |
12479 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
12480 | 0, 0); | |
12481 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
12482 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 12483 | } |
6fcee03d | 12484 | kvm_unload_vcpu_mmus(kvm); |
b3646477 | 12485 | static_call_cond(kvm_x86_vm_destroy)(kvm); |
b318e8de | 12486 | kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); |
c761159c PX |
12487 | kvm_pic_destroy(kvm); |
12488 | kvm_ioapic_destroy(kvm); | |
6fcee03d | 12489 | kvm_destroy_vcpus(kvm); |
af1bae54 | 12490 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 12491 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 12492 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 12493 | kvm_page_track_cleanup(kvm); |
7d6bbebb | 12494 | kvm_xen_destroy_vm(kvm); |
cbc0236a | 12495 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 12496 | } |
0de10343 | 12497 | |
c9b929b3 | 12498 | static void memslot_rmap_free(struct kvm_memory_slot *slot) |
db3fe4eb TY |
12499 | { |
12500 | int i; | |
12501 | ||
d89cc617 | 12502 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
12503 | kvfree(slot->arch.rmap[i]); |
12504 | slot->arch.rmap[i] = NULL; | |
c9b929b3 BG |
12505 | } |
12506 | } | |
e96c81ee | 12507 | |
c9b929b3 BG |
12508 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
12509 | { | |
12510 | int i; | |
12511 | ||
12512 | memslot_rmap_free(slot); | |
d89cc617 | 12513 | |
c9b929b3 | 12514 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
12515 | kvfree(slot->arch.lpage_info[i - 1]); |
12516 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 12517 | } |
21ebbeda | 12518 | |
e96c81ee | 12519 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
12520 | } |
12521 | ||
1e76a3ce | 12522 | int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) |
56dd1019 BG |
12523 | { |
12524 | const int sz = sizeof(*slot->arch.rmap[0]); | |
12525 | int i; | |
12526 | ||
12527 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { | |
12528 | int level = i + 1; | |
4139b197 | 12529 | int lpages = __kvm_mmu_slot_lpages(slot, npages, level); |
56dd1019 | 12530 | |
fa13843d PB |
12531 | if (slot->arch.rmap[i]) |
12532 | continue; | |
d501f747 | 12533 | |
37b2a651 | 12534 | slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); |
56dd1019 BG |
12535 | if (!slot->arch.rmap[i]) { |
12536 | memslot_rmap_free(slot); | |
12537 | return -ENOMEM; | |
12538 | } | |
12539 | } | |
12540 | ||
12541 | return 0; | |
12542 | } | |
12543 | ||
a2557408 | 12544 | static int kvm_alloc_memslot_metadata(struct kvm *kvm, |
9d7d18ee | 12545 | struct kvm_memory_slot *slot) |
db3fe4eb | 12546 | { |
9d7d18ee | 12547 | unsigned long npages = slot->npages; |
56dd1019 | 12548 | int i, r; |
db3fe4eb | 12549 | |
edd4fa37 SC |
12550 | /* |
12551 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
12552 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
12553 | * the new memslot is successful. | |
12554 | */ | |
12555 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
12556 | ||
e2209710 | 12557 | if (kvm_memslots_have_rmaps(kvm)) { |
a2557408 BG |
12558 | r = memslot_rmap_alloc(slot, npages); |
12559 | if (r) | |
12560 | return r; | |
12561 | } | |
56dd1019 BG |
12562 | |
12563 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { | |
92f94f1e | 12564 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
12565 | unsigned long ugfn; |
12566 | int lpages; | |
d89cc617 | 12567 | int level = i + 1; |
db3fe4eb | 12568 | |
4139b197 | 12569 | lpages = __kvm_mmu_slot_lpages(slot, npages, level); |
db3fe4eb | 12570 | |
37b2a651 | 12571 | linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 12572 | if (!linfo) |
db3fe4eb TY |
12573 | goto out_free; |
12574 | ||
92f94f1e XG |
12575 | slot->arch.lpage_info[i - 1] = linfo; |
12576 | ||
db3fe4eb | 12577 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 12578 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 12579 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 12580 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
12581 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
12582 | /* | |
12583 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 12584 | * other, disable large page support for this slot. |
db3fe4eb | 12585 | */ |
600087b6 | 12586 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
12587 | unsigned long j; |
12588 | ||
12589 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 12590 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
12591 | } |
12592 | } | |
12593 | ||
deae4a10 | 12594 | if (kvm_page_track_create_memslot(kvm, slot, npages)) |
21ebbeda XG |
12595 | goto out_free; |
12596 | ||
db3fe4eb TY |
12597 | return 0; |
12598 | ||
12599 | out_free: | |
c9b929b3 | 12600 | memslot_rmap_free(slot); |
d89cc617 | 12601 | |
c9b929b3 | 12602 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 12603 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 12604 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
12605 | } |
12606 | return -ENOMEM; | |
12607 | } | |
12608 | ||
15248258 | 12609 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 12610 | { |
91724814 | 12611 | struct kvm_vcpu *vcpu; |
46808a4c | 12612 | unsigned long i; |
91724814 | 12613 | |
e6dff7d1 TY |
12614 | /* |
12615 | * memslots->generation has been incremented. | |
12616 | * mmio generation may have reached its maximum value. | |
12617 | */ | |
15248258 | 12618 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
12619 | |
12620 | /* Force re-initialization of steal_time cache */ | |
12621 | kvm_for_each_vcpu(i, vcpu, kvm) | |
12622 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
12623 | } |
12624 | ||
f7784b8e | 12625 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
537a17b3 SC |
12626 | const struct kvm_memory_slot *old, |
12627 | struct kvm_memory_slot *new, | |
12628 | enum kvm_mr_change change) | |
0de10343 | 12629 | { |
86931ff7 SC |
12630 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) { |
12631 | if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn()) | |
12632 | return -EINVAL; | |
12633 | ||
9d7d18ee | 12634 | return kvm_alloc_memslot_metadata(kvm, new); |
86931ff7 | 12635 | } |
537a17b3 SC |
12636 | |
12637 | if (change == KVM_MR_FLAGS_ONLY) | |
12638 | memcpy(&new->arch, &old->arch, sizeof(old->arch)); | |
12639 | else if (WARN_ON_ONCE(change != KVM_MR_DELETE)) | |
12640 | return -EIO; | |
12641 | ||
f7784b8e MT |
12642 | return 0; |
12643 | } | |
12644 | ||
a85863c2 MS |
12645 | |
12646 | static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) | |
12647 | { | |
ee661d8e | 12648 | int nr_slots; |
a85863c2 MS |
12649 | |
12650 | if (!kvm_x86_ops.cpu_dirty_log_size) | |
12651 | return; | |
12652 | ||
ee661d8e DM |
12653 | nr_slots = atomic_read(&kvm->nr_memslots_dirty_logging); |
12654 | if ((enable && nr_slots == 1) || !nr_slots) | |
a85863c2 | 12655 | kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); |
a85863c2 MS |
12656 | } |
12657 | ||
88178fd4 | 12658 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b | 12659 | struct kvm_memory_slot *old, |
269e9552 | 12660 | const struct kvm_memory_slot *new, |
3741679b | 12661 | enum kvm_mr_change change) |
88178fd4 | 12662 | { |
77aedf26 SC |
12663 | u32 old_flags = old ? old->flags : 0; |
12664 | u32 new_flags = new ? new->flags : 0; | |
12665 | bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES; | |
a85863c2 | 12666 | |
3741679b | 12667 | /* |
a85863c2 MS |
12668 | * Update CPU dirty logging if dirty logging is being toggled. This |
12669 | * applies to all operations. | |
3741679b | 12670 | */ |
77aedf26 | 12671 | if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES) |
a85863c2 | 12672 | kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); |
88178fd4 KH |
12673 | |
12674 | /* | |
a85863c2 | 12675 | * Nothing more to do for RO slots (which can't be dirtied and can't be |
b6e16ae5 | 12676 | * made writable) or CREATE/MOVE/DELETE of a slot. |
88178fd4 | 12677 | * |
b6e16ae5 | 12678 | * For a memslot with dirty logging disabled: |
3741679b AY |
12679 | * CREATE: No dirty mappings will already exist. |
12680 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
12681 | * kvm_arch_flush_shadow_memslot() | |
b6e16ae5 SC |
12682 | * |
12683 | * For a memslot with dirty logging enabled: | |
12684 | * CREATE: No shadow pages exist, thus nothing to write-protect | |
12685 | * and no dirty bits to clear. | |
12686 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
12687 | * kvm_arch_flush_shadow_memslot(). | |
3741679b | 12688 | */ |
77aedf26 | 12689 | if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY)) |
88178fd4 | 12690 | return; |
3741679b AY |
12691 | |
12692 | /* | |
52f46079 SC |
12693 | * READONLY and non-flags changes were filtered out above, and the only |
12694 | * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty | |
12695 | * logging isn't being toggled on or off. | |
88178fd4 | 12696 | */ |
77aedf26 | 12697 | if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES))) |
52f46079 SC |
12698 | return; |
12699 | ||
b6e16ae5 SC |
12700 | if (!log_dirty_pages) { |
12701 | /* | |
12702 | * Dirty logging tracks sptes in 4k granularity, meaning that | |
12703 | * large sptes have to be split. If live migration succeeds, | |
12704 | * the guest in the source machine will be destroyed and large | |
12705 | * sptes will be created in the destination. However, if the | |
12706 | * guest continues to run in the source machine (for example if | |
12707 | * live migration fails), small sptes will remain around and | |
12708 | * cause bad performance. | |
12709 | * | |
12710 | * Scan sptes if dirty logging has been stopped, dropping those | |
12711 | * which can be collapsed into a single large-page spte. Later | |
12712 | * page faults will create the large-page sptes. | |
12713 | */ | |
3741679b | 12714 | kvm_mmu_zap_collapsible_sptes(kvm, new); |
b6e16ae5 | 12715 | } else { |
89212919 KZ |
12716 | /* |
12717 | * Initially-all-set does not require write protecting any page, | |
12718 | * because they're all assumed to be dirty. | |
12719 | */ | |
12720 | if (kvm_dirty_log_manual_protect_and_init_set(kvm)) | |
12721 | return; | |
a1419f8b | 12722 | |
a3fe5dbd DM |
12723 | if (READ_ONCE(eager_page_split)) |
12724 | kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K); | |
12725 | ||
a018eba5 | 12726 | if (kvm_x86_ops.cpu_dirty_log_size) { |
89212919 KZ |
12727 | kvm_mmu_slot_leaf_clear_dirty(kvm, new); |
12728 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); | |
12729 | } else { | |
12730 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); | |
3c9bd400 | 12731 | } |
b64d740e JS |
12732 | |
12733 | /* | |
12734 | * Unconditionally flush the TLBs after enabling dirty logging. | |
12735 | * A flush is almost always going to be necessary (see below), | |
12736 | * and unconditionally flushing allows the helpers to omit | |
12737 | * the subtly complex checks when removing write access. | |
12738 | * | |
12739 | * Do the flush outside of mmu_lock to reduce the amount of | |
12740 | * time mmu_lock is held. Flushing after dropping mmu_lock is | |
12741 | * safe as KVM only needs to guarantee the slot is fully | |
12742 | * write-protected before returning to userspace, i.e. before | |
12743 | * userspace can consume the dirty status. | |
12744 | * | |
12745 | * Flushing outside of mmu_lock requires KVM to be careful when | |
12746 | * making decisions based on writable status of an SPTE, e.g. a | |
12747 | * !writable SPTE doesn't guarantee a CPU can't perform writes. | |
12748 | * | |
12749 | * Specifically, KVM also write-protects guest page tables to | |
12750 | * monitor changes when using shadow paging, and must guarantee | |
12751 | * no CPUs can write to those page before mmu_lock is dropped. | |
12752 | * Because CPUs may have stale TLB entries at this point, a | |
12753 | * !writable SPTE doesn't guarantee CPUs can't perform writes. | |
12754 | * | |
12755 | * KVM also allows making SPTES writable outside of mmu_lock, | |
12756 | * e.g. to allow dirty logging without taking mmu_lock. | |
12757 | * | |
12758 | * To handle these scenarios, KVM uses a separate software-only | |
12759 | * bit (MMU-writable) to track if a SPTE is !writable due to | |
12760 | * a guest page table being write-protected (KVM clears the | |
12761 | * MMU-writable flag when write-protecting for shadow paging). | |
12762 | * | |
12763 | * The use of MMU-writable is also the primary motivation for | |
12764 | * the unconditional flush. Because KVM must guarantee that a | |
12765 | * CPU doesn't contain stale, writable TLB entries for a | |
12766 | * !MMU-writable SPTE, KVM must flush if it encounters any | |
12767 | * MMU-writable SPTE regardless of whether the actual hardware | |
12768 | * writable bit was set. I.e. KVM is almost guaranteed to need | |
12769 | * to flush, while unconditionally flushing allows the "remove | |
12770 | * write access" helpers to ignore MMU-writable entirely. | |
12771 | * | |
12772 | * See is_writable_pte() for more details (the case involving | |
12773 | * access-tracked SPTEs is particularly relevant). | |
12774 | */ | |
12775 | kvm_arch_flush_remote_tlbs_memslot(kvm, new); | |
88178fd4 KH |
12776 | } |
12777 | } | |
12778 | ||
f7784b8e | 12779 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
9d4c197c | 12780 | struct kvm_memory_slot *old, |
f36f3f28 | 12781 | const struct kvm_memory_slot *new, |
8482644a | 12782 | enum kvm_mr_change change) |
f7784b8e | 12783 | { |
e0c2b633 | 12784 | if (!kvm->arch.n_requested_mmu_pages && |
f5756029 MS |
12785 | (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) { |
12786 | unsigned long nr_mmu_pages; | |
12787 | ||
12788 | nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO; | |
12789 | nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); | |
12790 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
12791 | } | |
1c91cad4 | 12792 | |
269e9552 | 12793 | kvm_mmu_slot_apply_flags(kvm, old, new, change); |
21198846 SC |
12794 | |
12795 | /* Free the arrays associated with the old memslot. */ | |
12796 | if (change == KVM_MR_MOVE) | |
e96c81ee | 12797 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 12798 | } |
1d737c8a | 12799 | |
2df72e9b | 12800 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 12801 | { |
7390de1e | 12802 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
12803 | } |
12804 | ||
2df72e9b MT |
12805 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
12806 | struct kvm_memory_slot *slot) | |
12807 | { | |
ae7cd873 | 12808 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
12809 | } |
12810 | ||
e6c67d8c LA |
12811 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
12812 | { | |
12813 | return (is_guest_mode(vcpu) && | |
5be2226f | 12814 | static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); |
e6c67d8c LA |
12815 | } |
12816 | ||
5d9bc648 PB |
12817 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
12818 | { | |
12819 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
12820 | return true; | |
12821 | ||
bf7f9352 PB |
12822 | if (kvm_apic_has_pending_init_or_sipi(vcpu) && |
12823 | kvm_apic_init_sipi_allowed(vcpu)) | |
5d9bc648 PB |
12824 | return true; |
12825 | ||
12826 | if (vcpu->arch.pv.pv_unhalted) | |
12827 | return true; | |
12828 | ||
7709aba8 | 12829 | if (kvm_is_exception_pending(vcpu)) |
a5f01f8e WL |
12830 | return true; |
12831 | ||
47a66eed Z |
12832 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
12833 | (vcpu->arch.nmi_pending && | |
b3646477 | 12834 | static_call(kvm_x86_nmi_allowed)(vcpu, false))) |
5d9bc648 PB |
12835 | return true; |
12836 | ||
31e83e21 | 12837 | #ifdef CONFIG_KVM_SMM |
47a66eed | 12838 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 12839 | (vcpu->arch.smi_pending && |
b3646477 | 12840 | static_call(kvm_x86_smi_allowed)(vcpu, false))) |
73917739 | 12841 | return true; |
31e83e21 | 12842 | #endif |
73917739 | 12843 | |
5d9bc648 | 12844 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
12845 | (kvm_cpu_has_interrupt(vcpu) || |
12846 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
12847 | return true; |
12848 | ||
1f4b34f8 AS |
12849 | if (kvm_hv_has_stimer_pending(vcpu)) |
12850 | return true; | |
12851 | ||
d2060bd4 | 12852 | if (is_guest_mode(vcpu) && |
5b4ac1a1 PB |
12853 | kvm_x86_ops.nested_ops->has_events && |
12854 | kvm_x86_ops.nested_ops->has_events(vcpu)) | |
d2060bd4 SC |
12855 | return true; |
12856 | ||
7caf9571 DW |
12857 | if (kvm_xen_has_pending_events(vcpu)) |
12858 | return true; | |
12859 | ||
5d9bc648 PB |
12860 | return false; |
12861 | } | |
12862 | ||
1d737c8a ZX |
12863 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
12864 | { | |
5d9bc648 | 12865 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 12866 | } |
5736199a | 12867 | |
10dbdf98 | 12868 | bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) |
17e433b5 | 12869 | { |
ae801e13 SC |
12870 | if (kvm_vcpu_apicv_active(vcpu) && |
12871 | static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) | |
52acd22f WL |
12872 | return true; |
12873 | ||
12874 | return false; | |
12875 | } | |
12876 | ||
17e433b5 WL |
12877 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
12878 | { | |
12879 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
12880 | return true; | |
12881 | ||
12882 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
cf7316d0 | 12883 | #ifdef CONFIG_KVM_SMM |
17e433b5 | 12884 | kvm_test_request(KVM_REQ_SMI, vcpu) || |
cf7316d0 | 12885 | #endif |
17e433b5 WL |
12886 | kvm_test_request(KVM_REQ_EVENT, vcpu)) |
12887 | return true; | |
12888 | ||
10dbdf98 | 12889 | return kvm_arch_dy_has_pending_interrupt(vcpu); |
17e433b5 WL |
12890 | } |
12891 | ||
199b5763 LM |
12892 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
12893 | { | |
b86bb11e WL |
12894 | if (vcpu->arch.guest_state_protected) |
12895 | return true; | |
12896 | ||
de63ad4c | 12897 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
12898 | } |
12899 | ||
e1bfc245 SC |
12900 | unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu) |
12901 | { | |
12902 | return kvm_rip_read(vcpu); | |
12903 | } | |
12904 | ||
b6d33834 | 12905 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 12906 | { |
b6d33834 | 12907 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 12908 | } |
78646121 GN |
12909 | |
12910 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
12911 | { | |
b3646477 | 12912 | return static_call(kvm_x86_interrupt_allowed)(vcpu, false); |
78646121 | 12913 | } |
229456fc | 12914 | |
82b32774 | 12915 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 12916 | { |
7ed9abfe TL |
12917 | /* Can't read the RIP when guest state is protected, just return 0 */ |
12918 | if (vcpu->arch.guest_state_protected) | |
12919 | return 0; | |
12920 | ||
82b32774 NA |
12921 | if (is_64_bit_mode(vcpu)) |
12922 | return kvm_rip_read(vcpu); | |
12923 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
12924 | kvm_rip_read(vcpu)); | |
12925 | } | |
12926 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 12927 | |
82b32774 NA |
12928 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
12929 | { | |
12930 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
12931 | } |
12932 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
12933 | ||
94fe45da JK |
12934 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
12935 | { | |
12936 | unsigned long rflags; | |
12937 | ||
b3646477 | 12938 | rflags = static_call(kvm_x86_get_rflags)(vcpu); |
94fe45da | 12939 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 12940 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
12941 | return rflags; |
12942 | } | |
12943 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
12944 | ||
6addfc42 | 12945 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
12946 | { |
12947 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 12948 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 12949 | rflags |= X86_EFLAGS_TF; |
b3646477 | 12950 | static_call(kvm_x86_set_rflags)(vcpu, rflags); |
6addfc42 PB |
12951 | } |
12952 | ||
12953 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
12954 | { | |
12955 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 12956 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
12957 | } |
12958 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
12959 | ||
af585b92 GN |
12960 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
12961 | { | |
dd03bcaa PX |
12962 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
12963 | ||
af585b92 GN |
12964 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
12965 | } | |
12966 | ||
12967 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
12968 | { | |
dd03bcaa | 12969 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
12970 | } |
12971 | ||
12972 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
12973 | { | |
12974 | u32 key = kvm_async_pf_hash_fn(gfn); | |
12975 | ||
12976 | while (vcpu->arch.apf.gfns[key] != ~0) | |
12977 | key = kvm_async_pf_next_probe(key); | |
12978 | ||
12979 | vcpu->arch.apf.gfns[key] = gfn; | |
12980 | } | |
12981 | ||
12982 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
12983 | { | |
12984 | int i; | |
12985 | u32 key = kvm_async_pf_hash_fn(gfn); | |
12986 | ||
dd03bcaa | 12987 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
12988 | (vcpu->arch.apf.gfns[key] != gfn && |
12989 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
12990 | key = kvm_async_pf_next_probe(key); |
12991 | ||
12992 | return key; | |
12993 | } | |
12994 | ||
12995 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
12996 | { | |
12997 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
12998 | } | |
12999 | ||
13000 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
13001 | { | |
13002 | u32 i, j, k; | |
13003 | ||
13004 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
13005 | |
13006 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
13007 | return; | |
13008 | ||
af585b92 GN |
13009 | while (true) { |
13010 | vcpu->arch.apf.gfns[i] = ~0; | |
13011 | do { | |
13012 | j = kvm_async_pf_next_probe(j); | |
13013 | if (vcpu->arch.apf.gfns[j] == ~0) | |
13014 | return; | |
13015 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
13016 | /* | |
13017 | * k lies cyclically in ]i,j] | |
13018 | * | i.k.j | | |
13019 | * |....j i.k.| or |.k..j i...| | |
13020 | */ | |
13021 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
13022 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
13023 | i = j; | |
13024 | } | |
13025 | } | |
13026 | ||
68fd66f1 | 13027 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 13028 | { |
68fd66f1 VK |
13029 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
13030 | ||
13031 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
13032 | sizeof(reason)); | |
13033 | } | |
13034 | ||
13035 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
13036 | { | |
2635b5c4 | 13037 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 13038 | |
2635b5c4 VK |
13039 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
13040 | &token, offset, sizeof(token)); | |
13041 | } | |
13042 | ||
13043 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
13044 | { | |
13045 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
13046 | u32 val; | |
13047 | ||
13048 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
13049 | &val, offset, sizeof(val))) | |
13050 | return false; | |
13051 | ||
13052 | return !val; | |
7c90705b GN |
13053 | } |
13054 | ||
1dfdb45e PB |
13055 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
13056 | { | |
57cb3bb0 PB |
13057 | |
13058 | if (!kvm_pv_async_pf_enabled(vcpu)) | |
1dfdb45e PB |
13059 | return false; |
13060 | ||
57cb3bb0 PB |
13061 | if (vcpu->arch.apf.send_user_only && |
13062 | static_call(kvm_x86_get_cpl)(vcpu) == 0) | |
1dfdb45e PB |
13063 | return false; |
13064 | ||
57cb3bb0 PB |
13065 | if (is_guest_mode(vcpu)) { |
13066 | /* | |
13067 | * L1 needs to opt into the special #PF vmexits that are | |
13068 | * used to deliver async page faults. | |
13069 | */ | |
13070 | return vcpu->arch.apf.delivery_as_pf_vmexit; | |
13071 | } else { | |
13072 | /* | |
13073 | * Play it safe in case the guest temporarily disables paging. | |
13074 | * The real mode IDT in particular is unlikely to have a #PF | |
13075 | * exception setup. | |
13076 | */ | |
13077 | return is_paging(vcpu); | |
13078 | } | |
1dfdb45e PB |
13079 | } |
13080 | ||
13081 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
13082 | { | |
13083 | if (unlikely(!lapic_in_kernel(vcpu) || | |
13084 | kvm_event_needs_reinjection(vcpu) || | |
7709aba8 | 13085 | kvm_is_exception_pending(vcpu))) |
1dfdb45e PB |
13086 | return false; |
13087 | ||
13088 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
13089 | return false; | |
13090 | ||
13091 | /* | |
13092 | * If interrupts are off we cannot even use an artificial | |
13093 | * halt state. | |
13094 | */ | |
c300ab9f | 13095 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
13096 | } |
13097 | ||
2a18b7e7 | 13098 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
13099 | struct kvm_async_pf *work) |
13100 | { | |
6389ee94 AK |
13101 | struct x86_exception fault; |
13102 | ||
736c291c | 13103 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 13104 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 13105 | |
1dfdb45e | 13106 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 13107 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
13108 | fault.vector = PF_VECTOR; |
13109 | fault.error_code_valid = true; | |
13110 | fault.error_code = 0; | |
13111 | fault.nested_page_fault = false; | |
13112 | fault.address = work->arch.token; | |
adfe20fb | 13113 | fault.async_page_fault = true; |
6389ee94 | 13114 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 13115 | return true; |
1dfdb45e PB |
13116 | } else { |
13117 | /* | |
13118 | * It is not possible to deliver a paravirtualized asynchronous | |
13119 | * page fault, but putting the guest in an artificial halt state | |
13120 | * can be beneficial nevertheless: if an interrupt arrives, we | |
13121 | * can deliver it timely and perhaps the guest will schedule | |
13122 | * another process. When the instruction that triggered a page | |
13123 | * fault is retried, hopefully the page will be ready in the host. | |
13124 | */ | |
13125 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 13126 | return false; |
7c90705b | 13127 | } |
af585b92 GN |
13128 | } |
13129 | ||
13130 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
13131 | struct kvm_async_pf *work) | |
13132 | { | |
2635b5c4 VK |
13133 | struct kvm_lapic_irq irq = { |
13134 | .delivery_mode = APIC_DM_FIXED, | |
13135 | .vector = vcpu->arch.apf.vec | |
13136 | }; | |
6389ee94 | 13137 | |
f2e10669 | 13138 | if (work->wakeup_all) |
7c90705b GN |
13139 | work->arch.token = ~0; /* broadcast wakeup */ |
13140 | else | |
13141 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 13142 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 13143 | |
2a18b7e7 VK |
13144 | if ((work->wakeup_all || work->notpresent_injected) && |
13145 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
13146 | !apf_put_user_ready(vcpu, work->arch.token)) { |
13147 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 13148 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 13149 | } |
2635b5c4 | 13150 | |
e6d53e3b | 13151 | vcpu->arch.apf.halted = false; |
a4fa1635 | 13152 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
13153 | } |
13154 | ||
557a961a VK |
13155 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
13156 | { | |
13157 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
13158 | if (!vcpu->arch.apf.pageready_pending) | |
13159 | kvm_vcpu_kick(vcpu); | |
13160 | } | |
13161 | ||
7c0ade6c | 13162 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 13163 | { |
2635b5c4 | 13164 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
13165 | return true; |
13166 | else | |
2f15d027 | 13167 | return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); |
af585b92 GN |
13168 | } |
13169 | ||
5544eb9b PB |
13170 | void kvm_arch_start_assignment(struct kvm *kvm) |
13171 | { | |
57ab8794 | 13172 | if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) |
e27bc044 | 13173 | static_call_cond(kvm_x86_pi_start_assignment)(kvm); |
5544eb9b PB |
13174 | } |
13175 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
13176 | ||
13177 | void kvm_arch_end_assignment(struct kvm *kvm) | |
13178 | { | |
13179 | atomic_dec(&kvm->arch.assigned_device_count); | |
13180 | } | |
13181 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
13182 | ||
742ab6df | 13183 | bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm) |
5544eb9b | 13184 | { |
0f613bfa | 13185 | return raw_atomic_read(&kvm->arch.assigned_device_count); |
5544eb9b PB |
13186 | } |
13187 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
13188 | ||
e0f0bbc5 AW |
13189 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
13190 | { | |
13191 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
13192 | } | |
13193 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
13194 | ||
13195 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
13196 | { | |
13197 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
13198 | } | |
13199 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
13200 | ||
13201 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
13202 | { | |
13203 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
13204 | } | |
13205 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
13206 | ||
14717e20 AW |
13207 | bool kvm_arch_has_irq_bypass(void) |
13208 | { | |
5e1fe4a2 | 13209 | return enable_apicv && irq_remapping_cap(IRQ_POSTING_CAP); |
14717e20 AW |
13210 | } |
13211 | ||
87276880 FW |
13212 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
13213 | struct irq_bypass_producer *prod) | |
13214 | { | |
13215 | struct kvm_kernel_irqfd *irqfd = | |
13216 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 13217 | int ret; |
87276880 | 13218 | |
14717e20 | 13219 | irqfd->producer = prod; |
2edd9cb7 | 13220 | kvm_arch_start_assignment(irqfd->kvm); |
e27bc044 | 13221 | ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, |
2edd9cb7 ZL |
13222 | prod->irq, irqfd->gsi, 1); |
13223 | ||
13224 | if (ret) | |
13225 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 13226 | |
2edd9cb7 | 13227 | return ret; |
87276880 FW |
13228 | } |
13229 | ||
13230 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
13231 | struct irq_bypass_producer *prod) | |
13232 | { | |
13233 | int ret; | |
13234 | struct kvm_kernel_irqfd *irqfd = | |
13235 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
13236 | ||
87276880 FW |
13237 | WARN_ON(irqfd->producer != prod); |
13238 | irqfd->producer = NULL; | |
13239 | ||
13240 | /* | |
13241 | * When producer of consumer is unregistered, we change back to | |
13242 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 13243 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
13244 | * int this case doesn't want to receive the interrupts. |
13245 | */ | |
e27bc044 | 13246 | ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
13247 | if (ret) |
13248 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
13249 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
13250 | |
13251 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
13252 | } |
13253 | ||
13254 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
13255 | uint32_t guest_irq, bool set) | |
13256 | { | |
e27bc044 | 13257 | return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set); |
87276880 FW |
13258 | } |
13259 | ||
515a0c79 LM |
13260 | bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, |
13261 | struct kvm_kernel_irq_routing_entry *new) | |
13262 | { | |
13263 | if (new->type != KVM_IRQ_ROUTING_MSI) | |
13264 | return true; | |
13265 | ||
13266 | return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); | |
13267 | } | |
13268 | ||
52004014 FW |
13269 | bool kvm_vector_hashing_enabled(void) |
13270 | { | |
13271 | return vector_hashing; | |
13272 | } | |
52004014 | 13273 | |
2d5ba19b MT |
13274 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
13275 | { | |
13276 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
13277 | } | |
13278 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
13279 | ||
841c2be0 ML |
13280 | |
13281 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 13282 | { |
841c2be0 ML |
13283 | /* |
13284 | * test that setting IA32_SPEC_CTRL to given value | |
13285 | * is allowed by the host processor | |
13286 | */ | |
6441fa61 | 13287 | |
841c2be0 ML |
13288 | u64 saved_value; |
13289 | unsigned long flags; | |
13290 | int ret = 0; | |
6441fa61 | 13291 | |
841c2be0 | 13292 | local_irq_save(flags); |
6441fa61 | 13293 | |
841c2be0 ML |
13294 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
13295 | ret = 1; | |
13296 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
13297 | ret = 1; | |
13298 | else | |
13299 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 13300 | |
841c2be0 | 13301 | local_irq_restore(flags); |
6441fa61 | 13302 | |
841c2be0 | 13303 | return ret; |
6441fa61 | 13304 | } |
841c2be0 | 13305 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 13306 | |
89786147 MG |
13307 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
13308 | { | |
1f5a21ee | 13309 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
89786147 | 13310 | struct x86_exception fault; |
5b22bbe7 | 13311 | u64 access = error_code & |
19cf4b7e | 13312 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); |
89786147 MG |
13313 | |
13314 | if (!(error_code & PFERR_PRESENT_MASK) || | |
6e1d2a3f | 13315 | mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) { |
89786147 MG |
13316 | /* |
13317 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
13318 | * tables probably do not match the TLB. Just proceed | |
13319 | * with the error code that the processor gave. | |
13320 | */ | |
13321 | fault.vector = PF_VECTOR; | |
13322 | fault.error_code_valid = true; | |
13323 | fault.error_code = error_code; | |
13324 | fault.nested_page_fault = false; | |
13325 | fault.address = gva; | |
2bc685e6 | 13326 | fault.async_page_fault = false; |
89786147 MG |
13327 | } |
13328 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 13329 | } |
89786147 | 13330 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 13331 | |
3f3393b3 BM |
13332 | /* |
13333 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
13334 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
13335 | * indicates whether exit to userspace is needed. | |
13336 | */ | |
13337 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
13338 | struct x86_exception *e) | |
13339 | { | |
13340 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
77b1908e SC |
13341 | if (KVM_BUG_ON(!e, vcpu->kvm)) |
13342 | return -EIO; | |
13343 | ||
3f3393b3 BM |
13344 | kvm_inject_emulated_page_fault(vcpu, e); |
13345 | return 1; | |
13346 | } | |
13347 | ||
13348 | /* | |
13349 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
13350 | * while handling a VMX instruction KVM could've handled the request | |
13351 | * correctly by exiting to userspace and performing I/O but there | |
13352 | * doesn't seem to be a real use-case behind such requests, just return | |
13353 | * KVM_EXIT_INTERNAL_ERROR for now. | |
13354 | */ | |
e615e355 | 13355 | kvm_prepare_emulation_failure_exit(vcpu); |
3f3393b3 BM |
13356 | |
13357 | return 0; | |
13358 | } | |
13359 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
13360 | ||
9715092f BM |
13361 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
13362 | { | |
13363 | bool pcid_enabled; | |
13364 | struct x86_exception e; | |
9715092f BM |
13365 | struct { |
13366 | u64 pcid; | |
13367 | u64 gla; | |
13368 | } operand; | |
13369 | int r; | |
13370 | ||
13371 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
13372 | if (r != X86EMUL_CONTINUE) | |
13373 | return kvm_handle_memory_failure(vcpu, r, &e); | |
13374 | ||
13375 | if (operand.pcid >> 12 != 0) { | |
13376 | kvm_inject_gp(vcpu, 0); | |
13377 | return 1; | |
13378 | } | |
13379 | ||
607475cf | 13380 | pcid_enabled = kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE); |
9715092f BM |
13381 | |
13382 | switch (type) { | |
13383 | case INVPCID_TYPE_INDIV_ADDR: | |
13384 | if ((!pcid_enabled && (operand.pcid != 0)) || | |
13385 | is_noncanonical_address(operand.gla, vcpu)) { | |
13386 | kvm_inject_gp(vcpu, 0); | |
13387 | return 1; | |
13388 | } | |
13389 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
13390 | return kvm_skip_emulated_instruction(vcpu); | |
13391 | ||
13392 | case INVPCID_TYPE_SINGLE_CTXT: | |
13393 | if (!pcid_enabled && (operand.pcid != 0)) { | |
13394 | kvm_inject_gp(vcpu, 0); | |
13395 | return 1; | |
13396 | } | |
13397 | ||
21823fbd | 13398 | kvm_invalidate_pcid(vcpu, operand.pcid); |
9715092f BM |
13399 | return kvm_skip_emulated_instruction(vcpu); |
13400 | ||
13401 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
13402 | /* | |
13403 | * Currently, KVM doesn't mark global entries in the shadow | |
13404 | * page tables, so a non-global flush just degenerates to a | |
13405 | * global flush. If needed, we could optimize this later by | |
13406 | * keeping track of global entries in shadow page tables. | |
13407 | */ | |
13408 | ||
13409 | fallthrough; | |
13410 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
28f28d45 | 13411 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
9715092f BM |
13412 | return kvm_skip_emulated_instruction(vcpu); |
13413 | ||
13414 | default: | |
796c83c5 VS |
13415 | kvm_inject_gp(vcpu, 0); |
13416 | return 1; | |
9715092f BM |
13417 | } |
13418 | } | |
13419 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
13420 | ||
8f423a80 TL |
13421 | static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) |
13422 | { | |
13423 | struct kvm_run *run = vcpu->run; | |
13424 | struct kvm_mmio_fragment *frag; | |
13425 | unsigned int len; | |
13426 | ||
13427 | BUG_ON(!vcpu->mmio_needed); | |
13428 | ||
13429 | /* Complete previous fragment */ | |
13430 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
13431 | len = min(8u, frag->len); | |
13432 | if (!vcpu->mmio_is_write) | |
13433 | memcpy(frag->data, run->mmio.data, len); | |
13434 | ||
13435 | if (frag->len <= 8) { | |
13436 | /* Switch to the next fragment. */ | |
13437 | frag++; | |
13438 | vcpu->mmio_cur_fragment++; | |
13439 | } else { | |
13440 | /* Go forward to the next mmio piece. */ | |
13441 | frag->data += len; | |
13442 | frag->gpa += len; | |
13443 | frag->len -= len; | |
13444 | } | |
13445 | ||
13446 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { | |
13447 | vcpu->mmio_needed = 0; | |
13448 | ||
13449 | // VMG change, at this point, we're always done | |
13450 | // RIP has already been advanced | |
13451 | return 1; | |
13452 | } | |
13453 | ||
13454 | // More MMIO is needed | |
13455 | run->mmio.phys_addr = frag->gpa; | |
13456 | run->mmio.len = min(8u, frag->len); | |
13457 | run->mmio.is_write = vcpu->mmio_is_write; | |
13458 | if (run->mmio.is_write) | |
13459 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
13460 | run->exit_reason = KVM_EXIT_MMIO; | |
13461 | ||
13462 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
13463 | ||
13464 | return 0; | |
13465 | } | |
13466 | ||
13467 | int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
13468 | void *data) | |
13469 | { | |
13470 | int handled; | |
13471 | struct kvm_mmio_fragment *frag; | |
13472 | ||
13473 | if (!data) | |
13474 | return -EINVAL; | |
13475 | ||
13476 | handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
13477 | if (handled == bytes) | |
13478 | return 1; | |
13479 | ||
13480 | bytes -= handled; | |
13481 | gpa += handled; | |
13482 | data += handled; | |
13483 | ||
13484 | /*TODO: Check if need to increment number of frags */ | |
13485 | frag = vcpu->mmio_fragments; | |
13486 | vcpu->mmio_nr_fragments = 1; | |
13487 | frag->len = bytes; | |
13488 | frag->gpa = gpa; | |
13489 | frag->data = data; | |
13490 | ||
13491 | vcpu->mmio_needed = 1; | |
13492 | vcpu->mmio_cur_fragment = 0; | |
13493 | ||
13494 | vcpu->run->mmio.phys_addr = gpa; | |
13495 | vcpu->run->mmio.len = min(8u, frag->len); | |
13496 | vcpu->run->mmio.is_write = 1; | |
13497 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
13498 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
13499 | ||
13500 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
13501 | ||
13502 | return 0; | |
13503 | } | |
13504 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); | |
13505 | ||
13506 | int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
13507 | void *data) | |
13508 | { | |
13509 | int handled; | |
13510 | struct kvm_mmio_fragment *frag; | |
13511 | ||
13512 | if (!data) | |
13513 | return -EINVAL; | |
13514 | ||
13515 | handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
13516 | if (handled == bytes) | |
13517 | return 1; | |
13518 | ||
13519 | bytes -= handled; | |
13520 | gpa += handled; | |
13521 | data += handled; | |
13522 | ||
13523 | /*TODO: Check if need to increment number of frags */ | |
13524 | frag = vcpu->mmio_fragments; | |
13525 | vcpu->mmio_nr_fragments = 1; | |
13526 | frag->len = bytes; | |
13527 | frag->gpa = gpa; | |
13528 | frag->data = data; | |
13529 | ||
13530 | vcpu->mmio_needed = 1; | |
13531 | vcpu->mmio_cur_fragment = 0; | |
13532 | ||
13533 | vcpu->run->mmio.phys_addr = gpa; | |
13534 | vcpu->run->mmio.len = min(8u, frag->len); | |
13535 | vcpu->run->mmio.is_write = 0; | |
13536 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
13537 | ||
13538 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
13539 | ||
13540 | return 0; | |
13541 | } | |
13542 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); | |
13543 | ||
db209369 PB |
13544 | static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size) |
13545 | { | |
13546 | vcpu->arch.sev_pio_count -= count; | |
13547 | vcpu->arch.sev_pio_data += count * size; | |
13548 | } | |
13549 | ||
7ed9abfe | 13550 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, |
95e16b47 PB |
13551 | unsigned int port); |
13552 | ||
13553 | static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) | |
7ed9abfe | 13554 | { |
95e16b47 PB |
13555 | int size = vcpu->arch.pio.size; |
13556 | int port = vcpu->arch.pio.port; | |
13557 | ||
13558 | vcpu->arch.pio.count = 0; | |
13559 | if (vcpu->arch.sev_pio_count) | |
13560 | return kvm_sev_es_outs(vcpu, size, port); | |
13561 | return 1; | |
13562 | } | |
13563 | ||
13564 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, | |
13565 | unsigned int port) | |
13566 | { | |
13567 | for (;;) { | |
13568 | unsigned int count = | |
13569 | min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); | |
13570 | int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); | |
13571 | ||
13572 | /* memcpy done already by emulator_pio_out. */ | |
db209369 | 13573 | advance_sev_es_emulated_pio(vcpu, count, size); |
95e16b47 PB |
13574 | if (!ret) |
13575 | break; | |
7ed9abfe | 13576 | |
ea724ea4 | 13577 | /* Emulation done by the kernel. */ |
95e16b47 PB |
13578 | if (!vcpu->arch.sev_pio_count) |
13579 | return 1; | |
ea724ea4 | 13580 | } |
7ed9abfe | 13581 | |
95e16b47 | 13582 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; |
7ed9abfe TL |
13583 | return 0; |
13584 | } | |
13585 | ||
95e16b47 PB |
13586 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, |
13587 | unsigned int port); | |
13588 | ||
4fa4b38d PB |
13589 | static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) |
13590 | { | |
0c05e10b | 13591 | unsigned count = vcpu->arch.pio.count; |
95e16b47 PB |
13592 | int size = vcpu->arch.pio.size; |
13593 | int port = vcpu->arch.pio.port; | |
4fa4b38d | 13594 | |
0c05e10b | 13595 | complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); |
db209369 | 13596 | advance_sev_es_emulated_pio(vcpu, count, size); |
95e16b47 PB |
13597 | if (vcpu->arch.sev_pio_count) |
13598 | return kvm_sev_es_ins(vcpu, size, port); | |
4fa4b38d PB |
13599 | return 1; |
13600 | } | |
13601 | ||
7ed9abfe | 13602 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, |
95e16b47 | 13603 | unsigned int port) |
7ed9abfe | 13604 | { |
95e16b47 PB |
13605 | for (;;) { |
13606 | unsigned int count = | |
13607 | min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); | |
f35cee4a | 13608 | if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count)) |
95e16b47 | 13609 | break; |
7ed9abfe | 13610 | |
ea724ea4 | 13611 | /* Emulation done by the kernel. */ |
db209369 | 13612 | advance_sev_es_emulated_pio(vcpu, count, size); |
95e16b47 PB |
13613 | if (!vcpu->arch.sev_pio_count) |
13614 | return 1; | |
7ed9abfe TL |
13615 | } |
13616 | ||
ea724ea4 | 13617 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; |
7ed9abfe TL |
13618 | return 0; |
13619 | } | |
13620 | ||
13621 | int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, | |
13622 | unsigned int port, void *data, unsigned int count, | |
13623 | int in) | |
13624 | { | |
ea724ea4 | 13625 | vcpu->arch.sev_pio_data = data; |
95e16b47 PB |
13626 | vcpu->arch.sev_pio_count = count; |
13627 | return in ? kvm_sev_es_ins(vcpu, size, port) | |
13628 | : kvm_sev_es_outs(vcpu, size, port); | |
7ed9abfe TL |
13629 | } |
13630 | EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); | |
13631 | ||
d95df951 | 13632 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); |
229456fc | 13633 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 13634 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
13635 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
13636 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
13637 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
13638 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
89e54ec5 | 13639 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter); |
d8cabddf | 13640 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 13641 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 13642 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 13643 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 13644 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 13645 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 13646 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 13647 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 13648 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 13649 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 13650 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
13651 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
13652 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 13653 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
9f084f7c | 13654 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath); |
39b6b8c3 | 13655 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell); |
8e819d75 | 13656 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq); |
d523ab6b TL |
13657 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); |
13658 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); | |
59e38b58 TL |
13659 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); |
13660 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); | |
1d0e8480 SC |
13661 | |
13662 | static int __init kvm_x86_init(void) | |
13663 | { | |
13664 | kvm_mmu_x86_module_init(); | |
6f0f2d5e | 13665 | mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible(); |
1d0e8480 SC |
13666 | return 0; |
13667 | } | |
13668 | module_init(kvm_x86_init); | |
13669 | ||
13670 | static void __exit kvm_x86_exit(void) | |
13671 | { | |
13672 | /* | |
13673 | * If module_init() is implemented, module_exit() must also be | |
13674 | * implemented to allow module unload. | |
13675 | */ | |
13676 | } | |
13677 | module_exit(kvm_x86_exit); |