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KVM: x86/vPMU: refine kvm_pmu err msg when event creation failed
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
043405e1
CO		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 17 */
18
edf88417 19#include <linux/kvm_host.h>
313a3dc7 20#include "irq.h"
1d737c8a 21#include "mmu.h"
7837699f 22#include "i8254.h"
37817f29 23#include "tss.h"
5fdbf976 24#include "kvm_cache_regs.h"
26eef70c 25#include "x86.h"
00b27a3e 26#include "cpuid.h"
474a5bb9 27#include "pmu.h"
e83d5887 28#include "hyperv.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
1767e931
PG		 35#include <linux/export.h>
36#include <linux/moduleparam.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
87276880
FW		 51#include <linux/kvm_irqfd.h>
52#include <linux/irqbypass.h>
3905f9ad 53#include <linux/sched/stat.h>
0c5f81da 54#include <linux/sched/isolation.h>
d0ec49d4 55#include <linux/mem_encrypt.h>
3905f9ad 56
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
b0c39dc6 68#include <asm/mshyperv.h>
0092e434 69#include <asm/hypervisor.h>
bf8c55d8 70#include <asm/intel_pt.h>
dd2cb348 71#include <clocksource/hyperv_timer.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
c3941d9e
SC		 138/*
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
143 */
144static int __read_mostly lapic_timer_advance_ns = -1;
0e6edceb 145module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
d0659d94 146
52004014
FW		 147static bool __read_mostly vector_hashing = true;
148module_param(vector_hashing, bool, S_IRUGO);
149
c4ae60e4
LA		 150bool __read_mostly enable_vmware_backdoor = false;
151module_param(enable_vmware_backdoor, bool, S_IRUGO);
152EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
153
6c86eedc
WL		 154static bool __read_mostly force_emulation_prefix = false;
155module_param(force_emulation_prefix, bool, S_IRUGO);
156
0c5f81da
WL		 157int __read_mostly pi_inject_timer = -1;
158module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
159
18863bdd
AK		 160#define KVM_NR_SHARED_MSRS 16
161
162struct kvm_shared_msrs_global {
163 int nr;
2bf78fa7 164 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 165};
166
167struct kvm_shared_msrs {
168 struct user_return_notifier urn;
169 bool registered;
2bf78fa7
SY		 170 struct kvm_shared_msr_values {
171 u64 host;
172 u64 curr;
173 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 174};
175
176static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 177static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 178
417bc304 179struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 190 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 195 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 202 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 203 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 204 { "req_event", VCPU_STAT(req_event) },
c595ceee 205 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 213 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 215 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 218 { NULL }
219};
220
2acf923e
DC		 221u64 __read_mostly host_xcr0;
222
b666a4b6
MO		 223struct kmem_cache *x86_fpu_cache;
224EXPORT_SYMBOL_GPL(x86_fpu_cache);
225
b6785def 226static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 227
af585b92
GN		 228static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
229{
230 int i;
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
233}
234
18863bdd
AK		 235static void kvm_on_user_return(struct user_return_notifier *urn)
236{
237 unsigned slot;
18863bdd
AK		 238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 240 struct kvm_shared_msr_values *values;
1650b4eb
IA		 241 unsigned long flags;
242
243 /*
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
246 */
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
251 }
252 local_irq_restore(flags);
18863bdd 253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
18863bdd
AK		 258 }
259 }
18863bdd
AK		 260}
261
2bf78fa7 262static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 263{
18863bdd 264 u64 value;
013f6a5d
MT		 265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 267
2bf78fa7
SY		 268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
272 return;
273 }
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
277}
278
279void kvm_define_shared_msr(unsigned slot, u32 msr)
280{
0123be42 281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 282 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 285}
286EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
287
288static void kvm_shared_msr_cpu_online(void)
289{
290 unsigned i;
18863bdd
AK		 291
292 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 293 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 294}
295
8b3c3104 296int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 300 int err;
18863bdd 301
2bf78fa7 302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 303 return 0;
2bf78fa7 304 smsr->values[slot].curr = value;
8b3c3104
AH		 305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
306 if (err)
307 return 1;
308
18863bdd
AK		 309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
313 }
8b3c3104 314 return 0;
18863bdd
AK		 315}
316EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
317
13a34e06 318static void drop_user_return_notifiers(void)
3548bab5 319{
013f6a5d
MT		 320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 322
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
325}
326
6866b83e
CO		 327u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
328{
8a5a87d9 329 return vcpu->arch.apic_base;
6866b83e
CO		 330}
331EXPORT_SYMBOL_GPL(kvm_get_apic_base);
332
58871649
JM		 333enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
334{
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
336}
337EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
338
58cb628d
JK		 339int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
340{
58871649
JM		 341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 345
58871649 346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 347 return 1;
58871649
JM		 348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
350 return 1;
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
352 return 1;
353 }
58cb628d
JK		 354
355 kvm_lapic_set_base(vcpu, msr_info->data);
356 return 0;
6866b83e
CO		 357}
358EXPORT_SYMBOL_GPL(kvm_set_apic_base);
359
2605fc21 360asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 361{
362 /* Fault while not rebooting. We want the trace. */
363 BUG();
364}
365EXPORT_SYMBOL_GPL(kvm_spurious_fault);
366
3fd28fce
ED		 367#define EXCPT_BENIGN 0
368#define EXCPT_CONTRIBUTORY 1
369#define EXCPT_PF 2
370
371static int exception_class(int vector)
372{
373 switch (vector) {
374 case PF_VECTOR:
375 return EXCPT_PF;
376 case DE_VECTOR:
377 case TS_VECTOR:
378 case NP_VECTOR:
379 case SS_VECTOR:
380 case GP_VECTOR:
381 return EXCPT_CONTRIBUTORY;
382 default:
383 break;
384 }
385 return EXCPT_BENIGN;
386}
387
d6e8c854
NA		 388#define EXCPT_FAULT 0
389#define EXCPT_TRAP 1
390#define EXCPT_ABORT 2
391#define EXCPT_INTERRUPT 3
392
393static int exception_type(int vector)
394{
395 unsigned int mask;
396
397 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
398 return EXCPT_INTERRUPT;
399
400 mask = 1 << vector;
401
402 /* #DB is trap, as instruction watchpoints are handled elsewhere */
403 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
404 return EXCPT_TRAP;
405
406 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
407 return EXCPT_ABORT;
408
409 /* Reserved exceptions will result in fault */
410 return EXCPT_FAULT;
411}
412
da998b46
JM		 413void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
414{
415 unsigned nr = vcpu->arch.exception.nr;
416 bool has_payload = vcpu->arch.exception.has_payload;
417 unsigned long payload = vcpu->arch.exception.payload;
418
419 if (!has_payload)
420 return;
421
422 switch (nr) {
f10c729f
JM		 423 case DB_VECTOR:
424 /*
425 * "Certain debug exceptions may clear bit 0-3. The
426 * remaining contents of the DR6 register are never
427 * cleared by the processor".
428 */
429 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
430 /*
431 * DR6.RTM is set by all #DB exceptions that don't clear it.
432 */
433 vcpu->arch.dr6 |= DR6_RTM;
434 vcpu->arch.dr6 |= payload;
435 /*
436 * Bit 16 should be set in the payload whenever the #DB
437 * exception should clear DR6.RTM. This makes the payload
438 * compatible with the pending debug exceptions under VMX.
439 * Though not currently documented in the SDM, this also
440 * makes the payload compatible with the exit qualification
441 * for #DB exceptions under VMX.
442 */
443 vcpu->arch.dr6 ^= payload & DR6_RTM;
444 break;
da998b46
JM		 445 case PF_VECTOR:
446 vcpu->arch.cr2 = payload;
447 break;
448 }
449
450 vcpu->arch.exception.has_payload = false;
451 vcpu->arch.exception.payload = 0;
452}
453EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
454
3fd28fce 455static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 456 unsigned nr, bool has_error, u32 error_code,
91e86d22 457 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 458{
459 u32 prev_nr;
460 int class1, class2;
461
3842d135
AK		 462 kvm_make_request(KVM_REQ_EVENT, vcpu);
463
664f8e26 464 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 465 queue:
3ffb2468
NA		 466 if (has_error && !is_protmode(vcpu))
467 has_error = false;
664f8e26
WL		 468 if (reinject) {
469 /*
470 * On vmentry, vcpu->arch.exception.pending is only
471 * true if an event injection was blocked by
472 * nested_run_pending. In that case, however,
473 * vcpu_enter_guest requests an immediate exit,
474 * and the guest shouldn't proceed far enough to
475 * need reinjection.
476 */
477 WARN_ON_ONCE(vcpu->arch.exception.pending);
478 vcpu->arch.exception.injected = true;
91e86d22
JM		 479 if (WARN_ON_ONCE(has_payload)) {
480 /*
481 * A reinjected event has already
482 * delivered its payload.
483 */
484 has_payload = false;
485 payload = 0;
486 }
664f8e26
WL		 487 } else {
488 vcpu->arch.exception.pending = true;
489 vcpu->arch.exception.injected = false;
490 }
3fd28fce
ED		 491 vcpu->arch.exception.has_error_code = has_error;
492 vcpu->arch.exception.nr = nr;
493 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 494 vcpu->arch.exception.has_payload = has_payload;
495 vcpu->arch.exception.payload = payload;
da998b46
JM		 496 /*
497 * In guest mode, payload delivery should be deferred,
498 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 499 * CR2 is modified (or intercept #DB before DR6 is
500 * modified under nVMX). However, for ABI
501 * compatibility with KVM_GET_VCPU_EVENTS and
502 * KVM_SET_VCPU_EVENTS, we can't delay payload
503 * delivery unless userspace has enabled this
504 * functionality via the per-VM capability,
505 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 506 */
507 if (!vcpu->kvm->arch.exception_payload_enabled ||
508 !is_guest_mode(vcpu))
509 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 510 return;
511 }
512
513 /* to check exception */
514 prev_nr = vcpu->arch.exception.nr;
515 if (prev_nr == DF_VECTOR) {
516 /* triple fault -> shutdown */
a8eeb04a 517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 518 return;
519 }
520 class1 = exception_class(prev_nr);
521 class2 = exception_class(nr);
522 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
523 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 524 /*
525 * Generate double fault per SDM Table 5-5. Set
526 * exception.pending = true so that the double fault
527 * can trigger a nested vmexit.
528 */
3fd28fce 529 vcpu->arch.exception.pending = true;
664f8e26 530 vcpu->arch.exception.injected = false;
3fd28fce
ED		 531 vcpu->arch.exception.has_error_code = true;
532 vcpu->arch.exception.nr = DF_VECTOR;
533 vcpu->arch.exception.error_code = 0;
c851436a
JM		 534 vcpu->arch.exception.has_payload = false;
535 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 536 } else
537 /* replace previous exception with a new one in a hope
538 that instruction re-execution will regenerate lost
539 exception */
540 goto queue;
541}
542
298101da
AK		 543void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544{
91e86d22 545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 546}
547EXPORT_SYMBOL_GPL(kvm_queue_exception);
548
ce7ddec4
JR		 549void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
550{
91e86d22 551 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 552}
553EXPORT_SYMBOL_GPL(kvm_requeue_exception);
554
f10c729f
JM		 555static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
556 unsigned long payload)
557{
558 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
559}
560
da998b46
JM		 561static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
562 u32 error_code, unsigned long payload)
563{
564 kvm_multiple_exception(vcpu, nr, true, error_code,
565 true, payload, false);
566}
567
6affcbed 568int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 569{
db8fcefa
AP		 570 if (err)
571 kvm_inject_gp(vcpu, 0);
572 else
6affcbed
KH		 573 return kvm_skip_emulated_instruction(vcpu);
574
575 return 1;
db8fcefa
AP		 576}
577EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 578
6389ee94 579void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 580{
581 ++vcpu->stat.pf_guest;
adfe20fb
WL		 582 vcpu->arch.exception.nested_apf =
583 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 584 if (vcpu->arch.exception.nested_apf) {
adfe20fb 585 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 586 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
587 } else {
588 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
589 fault->address);
590 }
c3c91fee 591}
27d6c865 592EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 593
ef54bcfe 594static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 595{
6389ee94
AK		 596 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
597 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 598 else
44dd3ffa 599 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 600
601 return fault->nested_page_fault;
d4f8cf66
JR		 602}
603
3419ffc8
SY		 604void kvm_inject_nmi(struct kvm_vcpu *vcpu)
605{
7460fb4a
AK		 606 atomic_inc(&vcpu->arch.nmi_queued);
607 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 608}
609EXPORT_SYMBOL_GPL(kvm_inject_nmi);
610
298101da
AK		 611void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612{
91e86d22 613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 614}
615EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
616
ce7ddec4
JR		 617void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
618{
91e86d22 619 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 620}
621EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
622
0a79b009
AK		 623/*
624 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
625 * a #GP and return false.
626 */
627bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 628{
0a79b009
AK		 629 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
630 return true;
631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
632 return false;
298101da 633}
0a79b009 634EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 635
16f8a6f9
NA		 636bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
637{
638 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
639 return true;
640
641 kvm_queue_exception(vcpu, UD_VECTOR);
642 return false;
643}
644EXPORT_SYMBOL_GPL(kvm_require_dr);
645
ec92fe44
JR		 646/*
647 * This function will be used to read from the physical memory of the currently
54bf36aa 648 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 649 * can read from guest physical or from the guest's guest physical memory.
650 */
651int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
652 gfn_t ngfn, void *data, int offset, int len,
653 u32 access)
654{
54987b7a 655 struct x86_exception exception;
ec92fe44
JR		 656 gfn_t real_gfn;
657 gpa_t ngpa;
658
659 ngpa = gfn_to_gpa(ngfn);
54987b7a 660 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 661 if (real_gfn == UNMAPPED_GVA)
662 return -EFAULT;
663
664 real_gfn = gpa_to_gfn(real_gfn);
665
54bf36aa 666 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 667}
668EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
669
69b0049a 670static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 671 void *data, int offset, int len, u32 access)
672{
673 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
674 data, offset, len, access);
675}
676
a03490ed
CO		 677/*
678 * Load the pae pdptrs. Return true is they are all valid.
679 */
ff03a073 680int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 681{
682 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
683 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
684 int i;
685 int ret;
ff03a073 686 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 687
ff03a073
JR		 688 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
689 offset * sizeof(u64), sizeof(pdpte),
690 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 691 if (ret < 0) {
692 ret = 0;
693 goto out;
694 }
695 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 696 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 697 (pdpte[i] &
44dd3ffa 698 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 699 ret = 0;
700 goto out;
701 }
702 }
703 ret = 1;
704
ff03a073 705 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 706 __set_bit(VCPU_EXREG_PDPTR,
707 (unsigned long *)&vcpu->arch.regs_avail);
708 __set_bit(VCPU_EXREG_PDPTR,
709 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 710out:
a03490ed
CO		 711
712 return ret;
713}
cc4b6871 714EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 715
9ed38ffa 716bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 717{
ff03a073 718 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 719 bool changed = true;
3d06b8bf
JR		 720 int offset;
721 gfn_t gfn;
d835dfec
AK		 722 int r;
723
bf03d4f9 724 if (!is_pae_paging(vcpu))
d835dfec
AK		 725 return false;
726
6de4f3ad
AK		 727 if (!test_bit(VCPU_EXREG_PDPTR,
728 (unsigned long *)&vcpu->arch.regs_avail))
729 return true;
730
a512177e
PB		 731 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
732 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 733 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
734 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 735 if (r < 0)
736 goto out;
ff03a073 737 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 738out:
d835dfec
AK		 739
740 return changed;
741}
9ed38ffa 742EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 743
49a9b07e 744int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 745{
aad82703 746 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 747 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 748
f9a48e6a
AK		 749 cr0 |= X86_CR0_ET;
750
ab344828 751#ifdef CONFIG_X86_64
0f12244f
GN		 752 if (cr0 & 0xffffffff00000000UL)
753 return 1;
ab344828
GN		 754#endif
755
756 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 757
0f12244f
GN		 758 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
759 return 1;
a03490ed 760
0f12244f
GN		 761 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
762 return 1;
a03490ed
CO		 763
764 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
765#ifdef CONFIG_X86_64
f6801dff 766 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 767 int cs_db, cs_l;
768
0f12244f
GN		 769 if (!is_pae(vcpu))
770 return 1;
a03490ed 771 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 772 if (cs_l)
773 return 1;
a03490ed
CO		 774 } else
775#endif
ff03a073 776 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 777 kvm_read_cr3(vcpu)))
0f12244f 778 return 1;
a03490ed
CO		 779 }
780
ad756a16
MJ		 781 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
782 return 1;
783
a03490ed 784 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 785
d170c419 786 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 787 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 788 kvm_async_pf_hash_reset(vcpu);
789 }
e5f3f027 790
aad82703
SY		 791 if ((cr0 ^ old_cr0) & update_bits)
792 kvm_mmu_reset_context(vcpu);
b18d5431 793
879ae188
LE		 794 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
795 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
796 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 797 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
798
0f12244f
GN		 799 return 0;
800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 802
2d3ad1f4 803void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 804{
49a9b07e 805 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 806}
2d3ad1f4 807EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 808
1811d979 809void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 810{
811 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
812 !vcpu->guest_xcr0_loaded) {
813 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 814 if (vcpu->arch.xcr0 != host_xcr0)
815 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 816 vcpu->guest_xcr0_loaded = 1;
817 }
818}
1811d979 819EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
42bdf991 820
1811d979 821void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 822{
823 if (vcpu->guest_xcr0_loaded) {
824 if (vcpu->arch.xcr0 != host_xcr0)
825 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
826 vcpu->guest_xcr0_loaded = 0;
827 }
828}
1811d979 829EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
42bdf991 830
69b0049a 831static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 832{
56c103ec
LJ		 833 u64 xcr0 = xcr;
834 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 835 u64 valid_bits;
2acf923e
DC		 836
837 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
838 if (index != XCR_XFEATURE_ENABLED_MASK)
839 return 1;
d91cab78 840 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 841 return 1;
d91cab78 842 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 843 return 1;
46c34cb0
PB		 844
845 /*
846 * Do not allow the guest to set bits that we do not support
847 * saving. However, xcr0 bit 0 is always set, even if the
848 * emulated CPU does not support XSAVE (see fx_init).
849 */
d91cab78 850 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 851 if (xcr0 & ~valid_bits)
2acf923e 852 return 1;
46c34cb0 853
d91cab78
DH		 854 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
855 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 856 return 1;
857
d91cab78
DH		 858 if (xcr0 & XFEATURE_MASK_AVX512) {
859 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 860 return 1;
d91cab78 861 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 862 return 1;
863 }
2acf923e 864 vcpu->arch.xcr0 = xcr0;
56c103ec 865
d91cab78 866 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 867 kvm_update_cpuid(vcpu);
2acf923e
DC		 868 return 0;
869}
870
871int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
872{
764bcbc5
Z		 873 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
874 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 875 kvm_inject_gp(vcpu, 0);
876 return 1;
877 }
878 return 0;
879}
880EXPORT_SYMBOL_GPL(kvm_set_xcr);
881
a83b29c6 882int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 883{
fc78f519 884 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 885 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 886 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 887
0f12244f
GN		 888 if (cr4 & CR4_RESERVED_BITS)
889 return 1;
a03490ed 890
d6321d49 891 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 892 return 1;
893
d6321d49 894 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 895 return 1;
896
d6321d49 897 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 898 return 1;
899
d6321d49 900 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 901 return 1;
902
d6321d49 903 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 904 return 1;
905
fd8cb433 906 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 907 return 1;
908
ae3e61e1
PB		 909 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
910 return 1;
911
a03490ed 912 if (is_long_mode(vcpu)) {
0f12244f
GN		 913 if (!(cr4 & X86_CR4_PAE))
914 return 1;
a2edf57f
AK		 915 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
916 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 917 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
918 kvm_read_cr3(vcpu)))
0f12244f
GN		 919 return 1;
920
ad756a16 921 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 922 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 923 return 1;
924
925 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
926 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
927 return 1;
928 }
929
5e1746d6 930 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 931 return 1;
a03490ed 932
ad756a16
MJ		 933 if (((cr4 ^ old_cr4) & pdptr_bits) ||
934 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 935 kvm_mmu_reset_context(vcpu);
0f12244f 936
b9baba86 937 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 938 kvm_update_cpuid(vcpu);
2acf923e 939
0f12244f
GN		 940 return 0;
941}
2d3ad1f4 942EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 943
2390218b 944int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 945{
ade61e28 946 bool skip_tlb_flush = false;
ac146235 947#ifdef CONFIG_X86_64
c19986fe
JS		 948 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
949
ade61e28 950 if (pcid_enabled) {
208320ba
JS		 951 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
952 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 953 }
ac146235 954#endif
9d88fca7 955
9f8fe504 956 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 957 if (!skip_tlb_flush) {
958 kvm_mmu_sync_roots(vcpu);
ade61e28 959 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 960 }
0f12244f 961 return 0;
d835dfec
AK		 962 }
963
d1cd3ce9 964 if (is_long_mode(vcpu) &&
a780a3ea 965 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9 966 return 1;
bf03d4f9
PB		 967 else if (is_pae_paging(vcpu) &&
968 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 969 return 1;
a03490ed 970
ade61e28 971 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 972 vcpu->arch.cr3 = cr3;
aff48baa 973 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 974
0f12244f
GN		 975 return 0;
976}
2d3ad1f4 977EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 978
eea1cff9 979int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 980{
0f12244f
GN		 981 if (cr8 & CR8_RESERVED_BITS)
982 return 1;
35754c98 983 if (lapic_in_kernel(vcpu))
a03490ed
CO		 984 kvm_lapic_set_tpr(vcpu, cr8);
985 else
ad312c7c 986 vcpu->arch.cr8 = cr8;
0f12244f
GN		 987 return 0;
988}
2d3ad1f4 989EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 990
2d3ad1f4 991unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 992{
35754c98 993 if (lapic_in_kernel(vcpu))
a03490ed
CO		 994 return kvm_lapic_get_cr8(vcpu);
995 else
ad312c7c 996 return vcpu->arch.cr8;
a03490ed 997}
2d3ad1f4 998EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 999
ae561ede
NA		 1000static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1001{
1002 int i;
1003
1004 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1005 for (i = 0; i < KVM_NR_DB_REGS; i++)
1006 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1007 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1008 }
1009}
1010
73aaf249
JK		 1011static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1012{
1013 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1014 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1015}
1016
c8639010
JK		 1017static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1018{
1019 unsigned long dr7;
1020
1021 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1022 dr7 = vcpu->arch.guest_debug_dr7;
1023 else
1024 dr7 = vcpu->arch.dr7;
1025 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1026 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1027 if (dr7 & DR7_BP_EN_MASK)
1028 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1029}
1030
6f43ed01
NA		 1031static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1032{
1033 u64 fixed = DR6_FIXED_1;
1034
d6321d49 1035 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1036 fixed |= DR6_RTM;
1037 return fixed;
1038}
1039
338dbc97 1040static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1041{
1042 switch (dr) {
1043 case 0 ... 3:
1044 vcpu->arch.db[dr] = val;
1045 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1046 vcpu->arch.eff_db[dr] = val;
1047 break;
1048 case 4:
020df079
GN		 1049 /* fall through */
1050 case 6:
338dbc97
GN		 1051 if (val & 0xffffffff00000000ULL)
1052 return -1; /* #GP */
6f43ed01 1053 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1054 kvm_update_dr6(vcpu);
020df079
GN		 1055 break;
1056 case 5:
020df079
GN		 1057 /* fall through */
1058 default: /* 7 */
338dbc97
GN		 1059 if (val & 0xffffffff00000000ULL)
1060 return -1; /* #GP */
020df079 1061 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1062 kvm_update_dr7(vcpu);
020df079
GN		 1063 break;
1064 }
1065
1066 return 0;
1067}
338dbc97
GN		 1068
1069int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1070{
16f8a6f9 1071 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1072 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1073 return 1;
1074 }
1075 return 0;
338dbc97 1076}
020df079
GN		 1077EXPORT_SYMBOL_GPL(kvm_set_dr);
1078
16f8a6f9 1079int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1080{
1081 switch (dr) {
1082 case 0 ... 3:
1083 *val = vcpu->arch.db[dr];
1084 break;
1085 case 4:
020df079
GN		 1086 /* fall through */
1087 case 6:
73aaf249
JK		 1088 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1089 *val = vcpu->arch.dr6;
1090 else
1091 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1092 break;
1093 case 5:
020df079
GN		 1094 /* fall through */
1095 default: /* 7 */
1096 *val = vcpu->arch.dr7;
1097 break;
1098 }
338dbc97
GN		 1099 return 0;
1100}
020df079
GN		 1101EXPORT_SYMBOL_GPL(kvm_get_dr);
1102
022cd0e8
AK		 1103bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1104{
de3cd117 1105 u32 ecx = kvm_rcx_read(vcpu);
022cd0e8
AK		 1106 u64 data;
1107 int err;
1108
c6702c9d 1109 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1110 if (err)
1111 return err;
de3cd117
SC		 1112 kvm_rax_write(vcpu, (u32)data);
1113 kvm_rdx_write(vcpu, data >> 32);
022cd0e8
AK		 1114 return err;
1115}
1116EXPORT_SYMBOL_GPL(kvm_rdpmc);
1117
043405e1
CO		 1118/*
1119 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1120 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1121 *
1122 * This list is modified at module load time to reflect the
e3267cbb 1123 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1124 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1125 * may depend on host virtualization features rather than host cpu features.
043405e1 1126 */
e3267cbb 1127
043405e1
CO		 1128static u32 msrs_to_save[] = {
1129 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1130 MSR_STAR,
043405e1
CO		 1131#ifdef CONFIG_X86_64
1132 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1133#endif
b3897a49 1134 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1135 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1136 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1137 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1138 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1139 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1140 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1141 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1142 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
043405e1
CO		 1143};
1144
1145static unsigned num_msrs_to_save;
1146
62ef68bb
PB		 1147static u32 emulated_msrs[] = {
1148 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1149 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1150 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1151 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1152 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1153 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1154 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1155 HV_X64_MSR_RESET,
11c4b1ca 1156 HV_X64_MSR_VP_INDEX,
9eec50b8 1157 HV_X64_MSR_VP_RUNTIME,
5c919412 1158 HV_X64_MSR_SCONTROL,
1f4b34f8 1159 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1160 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1161 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1162 HV_X64_MSR_TSC_EMULATION_STATUS,
1163
1164 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1165 MSR_KVM_PV_EOI_EN,
1166
ba904635 1167 MSR_IA32_TSC_ADJUST,
a3e06bbe 1168 MSR_IA32_TSCDEADLINE,
2bdb76c0 1169 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1170 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1171 MSR_IA32_MCG_STATUS,
1172 MSR_IA32_MCG_CTL,
c45dcc71 1173 MSR_IA32_MCG_EXT_CTL,
64d60670 1174 MSR_IA32_SMBASE,
52797bf9 1175 MSR_SMI_COUNT,
db2336a8
KH		 1176 MSR_PLATFORM_INFO,
1177 MSR_MISC_FEATURES_ENABLES,
bc226f07 1178 MSR_AMD64_VIRT_SPEC_CTRL,
6c6a2ab9 1179 MSR_IA32_POWER_CTL,
191c8137 1180
95c5c7c7
PB		 1181 /*
1182 * The following list leaves out MSRs whose values are determined
1183 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1184 * We always support the "true" VMX control MSRs, even if the host
1185 * processor does not, so I am putting these registers here rather
1186 * than in msrs_to_save.
1187 */
1188 MSR_IA32_VMX_BASIC,
1189 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1190 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1191 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1192 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1193 MSR_IA32_VMX_MISC,
1194 MSR_IA32_VMX_CR0_FIXED0,
1195 MSR_IA32_VMX_CR4_FIXED0,
1196 MSR_IA32_VMX_VMCS_ENUM,
1197 MSR_IA32_VMX_PROCBASED_CTLS2,
1198 MSR_IA32_VMX_EPT_VPID_CAP,
1199 MSR_IA32_VMX_VMFUNC,
1200
191c8137 1201 MSR_K7_HWCR,
2d5ba19b 1202 MSR_KVM_POLL_CONTROL,
043405e1
CO		 1203};
1204
62ef68bb
PB		 1205static unsigned num_emulated_msrs;
1206
801e459a
TL		 1207/*
1208 * List of msr numbers which are used to expose MSR-based features that
1209 * can be used by a hypervisor to validate requested CPU features.
1210 */
1211static u32 msr_based_features[] = {
1389309c
PB		 1212 MSR_IA32_VMX_BASIC,
1213 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1214 MSR_IA32_VMX_PINBASED_CTLS,
1215 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1216 MSR_IA32_VMX_PROCBASED_CTLS,
1217 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1218 MSR_IA32_VMX_EXIT_CTLS,
1219 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1220 MSR_IA32_VMX_ENTRY_CTLS,
1221 MSR_IA32_VMX_MISC,
1222 MSR_IA32_VMX_CR0_FIXED0,
1223 MSR_IA32_VMX_CR0_FIXED1,
1224 MSR_IA32_VMX_CR4_FIXED0,
1225 MSR_IA32_VMX_CR4_FIXED1,
1226 MSR_IA32_VMX_VMCS_ENUM,
1227 MSR_IA32_VMX_PROCBASED_CTLS2,
1228 MSR_IA32_VMX_EPT_VPID_CAP,
1229 MSR_IA32_VMX_VMFUNC,
1230
d1d93fa9 1231 MSR_F10H_DECFG,
518e7b94 1232 MSR_IA32_UCODE_REV,
cd283252 1233 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1234};
1235
1236static unsigned int num_msr_based_features;
1237
4d22c17c 1238static u64 kvm_get_arch_capabilities(void)
5b76a3cf 1239{
4d22c17c 1240 u64 data = 0;
5b76a3cf 1241
4d22c17c
XL		 1242 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1243 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
5b76a3cf
PB		 1244
1245 /*
1246 * If we're doing cache flushes (either "always" or "cond")
1247 * we will do one whenever the guest does a vmlaunch/vmresume.
1248 * If an outer hypervisor is doing the cache flush for us
1249 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1250 * capability to the guest too, and if EPT is disabled we're not
1251 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1252 * require a nested hypervisor to do a flush of its own.
1253 */
1254 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1255 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1256
1257 return data;
1258}
5b76a3cf 1259
66421c1e
WL		 1260static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1261{
1262 switch (msr->index) {
cd283252 1263 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1264 msr->data = kvm_get_arch_capabilities();
1265 break;
1266 case MSR_IA32_UCODE_REV:
cd283252 1267 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1268 break;
66421c1e
WL		 1269 default:
1270 if (kvm_x86_ops->get_msr_feature(msr))
1271 return 1;
1272 }
1273 return 0;
1274}
1275
801e459a
TL		 1276static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1277{
1278 struct kvm_msr_entry msr;
66421c1e 1279 int r;
801e459a
TL		 1280
1281 msr.index = index;
66421c1e
WL		 1282 r = kvm_get_msr_feature(&msr);
1283 if (r)
1284 return r;
801e459a
TL		 1285
1286 *data = msr.data;
1287
1288 return 0;
1289}
1290
11988499 1291static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1292{
1b4d56b8 1293 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
11988499 1294 return false;
1b2fd70c 1295
1b4d56b8 1296 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
11988499 1297 return false;
d8017474 1298
0a629563
SC		 1299 if (efer & (EFER_LME | EFER_LMA) &&
1300 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1301 return false;
1302
1303 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1304 return false;
d8017474 1305
384bb783 1306 return true;
11988499
SC		 1307
1308}
1309bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1310{
1311 if (efer & efer_reserved_bits)
1312 return false;
1313
1314 return __kvm_valid_efer(vcpu, efer);
384bb783
JK		 1315}
1316EXPORT_SYMBOL_GPL(kvm_valid_efer);
1317
11988499 1318static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
384bb783
JK		 1319{
1320 u64 old_efer = vcpu->arch.efer;
11988499 1321 u64 efer = msr_info->data;
384bb783 1322
11988499 1323 if (efer & efer_reserved_bits)
66f61c92 1324 return 1;
384bb783 1325
11988499
SC		 1326 if (!msr_info->host_initiated) {
1327 if (!__kvm_valid_efer(vcpu, efer))
1328 return 1;
1329
1330 if (is_paging(vcpu) &&
1331 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1332 return 1;
1333 }
384bb783 1334
15c4a640 1335 efer &= ~EFER_LMA;
f6801dff 1336 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1337
a3d204e2
SY		 1338 kvm_x86_ops->set_efer(vcpu, efer);
1339
aad82703
SY		 1340 /* Update reserved bits */
1341 if ((efer ^ old_efer) & EFER_NX)
1342 kvm_mmu_reset_context(vcpu);
1343
b69e8cae 1344 return 0;
15c4a640
CO		 1345}
1346
f2b4b7dd
JR		 1347void kvm_enable_efer_bits(u64 mask)
1348{
1349 efer_reserved_bits &= ~mask;
1350}
1351EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1352
15c4a640
CO		 1353/*
1354 * Writes msr value into into the appropriate "register".
1355 * Returns 0 on success, non-0 otherwise.
1356 * Assumes vcpu_load() was already called.
1357 */
8fe8ab46 1358int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1359{
854e8bb1
NA		 1360 switch (msr->index) {
1361 case MSR_FS_BASE:
1362 case MSR_GS_BASE:
1363 case MSR_KERNEL_GS_BASE:
1364 case MSR_CSTAR:
1365 case MSR_LSTAR:
fd8cb433 1366 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1367 return 1;
1368 break;
1369 case MSR_IA32_SYSENTER_EIP:
1370 case MSR_IA32_SYSENTER_ESP:
1371 /*
1372 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1373 * non-canonical address is written on Intel but not on
1374 * AMD (which ignores the top 32-bits, because it does
1375 * not implement 64-bit SYSENTER).
1376 *
1377 * 64-bit code should hence be able to write a non-canonical
1378 * value on AMD. Making the address canonical ensures that
1379 * vmentry does not fail on Intel after writing a non-canonical
1380 * value, and that something deterministic happens if the guest
1381 * invokes 64-bit SYSENTER.
1382 */
fd8cb433 1383 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1384 }
8fe8ab46 1385 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1386}
854e8bb1 1387EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1388
313a3dc7
CO		 1389/*
1390 * Adapt set_msr() to msr_io()'s calling convention
1391 */
609e36d3
PB		 1392static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1393{
1394 struct msr_data msr;
1395 int r;
1396
1397 msr.index = index;
1398 msr.host_initiated = true;
1399 r = kvm_get_msr(vcpu, &msr);
1400 if (r)
1401 return r;
1402
1403 *data = msr.data;
1404 return 0;
1405}
1406
313a3dc7
CO		 1407static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1408{
8fe8ab46
WA		 1409 struct msr_data msr;
1410
1411 msr.data = *data;
1412 msr.index = index;
1413 msr.host_initiated = true;
1414 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1415}
1416
16e8d74d
MT		 1417#ifdef CONFIG_X86_64
1418struct pvclock_gtod_data {
1419 seqcount_t seq;
1420
1421 struct { /* extract of a clocksource struct */
1422 int vclock_mode;
a5a1d1c2
TG		 1423 u64 cycle_last;
1424 u64 mask;
16e8d74d
MT		 1425 u32 mult;
1426 u32 shift;
1427 } clock;
1428
cbcf2dd3
TG		 1429 u64 boot_ns;
1430 u64 nsec_base;
55dd00a7 1431 u64 wall_time_sec;
16e8d74d
MT		 1432};
1433
1434static struct pvclock_gtod_data pvclock_gtod_data;
1435
1436static void update_pvclock_gtod(struct timekeeper *tk)
1437{
1438 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1439 u64 boot_ns;
1440
876e7881 1441 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1442
1443 write_seqcount_begin(&vdata->seq);
1444
1445 /* copy pvclock gtod data */
876e7881
PZ		 1446 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1447 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1448 vdata->clock.mask = tk->tkr_mono.mask;
1449 vdata->clock.mult = tk->tkr_mono.mult;
1450 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1451
cbcf2dd3 1452 vdata->boot_ns = boot_ns;
876e7881 1453 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1454
55dd00a7
MT		 1455 vdata->wall_time_sec = tk->xtime_sec;
1456
16e8d74d
MT		 1457 write_seqcount_end(&vdata->seq);
1458}
1459#endif
1460
bab5bb39
NK		 1461void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1462{
bab5bb39 1463 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
4d151bf3 1464 kvm_vcpu_kick(vcpu);
bab5bb39 1465}
16e8d74d 1466
18068523
GOC		 1467static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1468{
9ed3c444
AK		 1469 int version;
1470 int r;
50d0a0f9 1471 struct pvclock_wall_clock wc;
87aeb54f 1472 struct timespec64 boot;
18068523
GOC		 1473
1474 if (!wall_clock)
1475 return;
1476
9ed3c444
AK		 1477 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1478 if (r)
1479 return;
1480
1481 if (version & 1)
1482 ++version; /* first time write, random junk */
1483
1484 ++version;
18068523 1485
1dab1345
NK		 1486 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1487 return;
18068523 1488
50d0a0f9
GH		 1489 /*
1490 * The guest calculates current wall clock time by adding
34c238a1 1491 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1492 * wall clock specified here. guest system time equals host
1493 * system time for us, thus we must fill in host boot time here.
1494 */
87aeb54f 1495 getboottime64(&boot);
50d0a0f9 1496
4b648665 1497 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1498 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1499 boot = timespec64_sub(boot, ts);
4b648665 1500 }
87aeb54f 1501 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1502 wc.nsec = boot.tv_nsec;
1503 wc.version = version;
18068523
GOC		 1504
1505 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1506
1507 version++;
1508 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1509}
1510
50d0a0f9
GH		 1511static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1512{
b51012de
PB		 1513 do_shl32_div32(dividend, divisor);
1514 return dividend;
50d0a0f9
GH		 1515}
1516
3ae13faa 1517static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1518 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1519{
5f4e3f88 1520 uint64_t scaled64;
50d0a0f9
GH		 1521 int32_t shift = 0;
1522 uint64_t tps64;
1523 uint32_t tps32;
1524
3ae13faa
PB		 1525 tps64 = base_hz;
1526 scaled64 = scaled_hz;
50933623 1527 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1528 tps64 >>= 1;
1529 shift--;
1530 }
1531
1532 tps32 = (uint32_t)tps64;
50933623
JK		 1533 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1534 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1535 scaled64 >>= 1;
1536 else
1537 tps32 <<= 1;
50d0a0f9
GH		 1538 shift++;
1539 }
1540
5f4e3f88
ZA		 1541 *pshift = shift;
1542 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9
GH		 1543}
1544
d828199e 1545#ifdef CONFIG_X86_64
16e8d74d 1546static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1547#endif
16e8d74d 1548
c8076604 1549static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1550static unsigned long max_tsc_khz;
c8076604 1551
cc578287 1552static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1553{
cc578287
ZA		 1554 u64 v = (u64)khz * (1000000 + ppm);
1555 do_div(v, 1000000);
1556 return v;
1e993611
JR		 1557}
1558
381d585c
HZ		 1559static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1560{
1561 u64 ratio;
1562
1563 /* Guest TSC same frequency as host TSC? */
1564 if (!scale) {
1565 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1566 return 0;
1567 }
1568
1569 /* TSC scaling supported? */
1570 if (!kvm_has_tsc_control) {
1571 if (user_tsc_khz > tsc_khz) {
1572 vcpu->arch.tsc_catchup = 1;
1573 vcpu->arch.tsc_always_catchup = 1;
1574 return 0;
1575 } else {
3f16a5c3 1576 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
381d585c
HZ		 1577 return -1;
1578 }
1579 }
1580
1581 /* TSC scaling required - calculate ratio */
1582 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1583 user_tsc_khz, tsc_khz);
1584
1585 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
3f16a5c3
PB		 1586 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1587 user_tsc_khz);
381d585c
HZ		 1588 return -1;
1589 }
1590
1591 vcpu->arch.tsc_scaling_ratio = ratio;
1592 return 0;
1593}
1594
4941b8cb 1595static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1596{
cc578287
ZA		 1597 u32 thresh_lo, thresh_hi;
1598 int use_scaling = 0;
217fc9cf 1599
03ba32ca 1600 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1601 if (user_tsc_khz == 0) {
ad721883
HZ		 1602 /* set tsc_scaling_ratio to a safe value */
1603 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1604 return -1;
ad721883 1605 }
03ba32ca 1606
c285545f 1607 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1608 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1609 &vcpu->arch.virtual_tsc_shift,
1610 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1611 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1612
1613 /*
1614 * Compute the variation in TSC rate which is acceptable
1615 * within the range of tolerance and decide if the
1616 * rate being applied is within that bounds of the hardware
1617 * rate. If so, no scaling or compensation need be done.
1618 */
1619 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1620 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1621 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1622 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1623 use_scaling = 1;
1624 }
4941b8cb 1625 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1626}
1627
1628static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1629{
e26101b1 1630 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1631 vcpu->arch.virtual_tsc_mult,
1632 vcpu->arch.virtual_tsc_shift);
e26101b1 1633 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1634 return tsc;
1635}
1636
b0c39dc6
VK		 1637static inline int gtod_is_based_on_tsc(int mode)
1638{
1639 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1640}
1641
69b0049a 1642static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1643{
1644#ifdef CONFIG_X86_64
1645 bool vcpus_matched;
b48aa97e
MT		 1646 struct kvm_arch *ka = &vcpu->kvm->arch;
1647 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1648
1649 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1650 atomic_read(&vcpu->kvm->online_vcpus));
1651
7f187922
MT		 1652 /*
1653 * Once the masterclock is enabled, always perform request in
1654 * order to update it.
1655 *
1656 * In order to enable masterclock, the host clocksource must be TSC
1657 * and the vcpus need to have matched TSCs. When that happens,
1658 * perform request to enable masterclock.
1659 */
1660 if (ka->use_master_clock ||
b0c39dc6 1661 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1662 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1663
1664 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1665 atomic_read(&vcpu->kvm->online_vcpus),
1666 ka->use_master_clock, gtod->clock.vclock_mode);
1667#endif
1668}
1669
ba904635
WA		 1670static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1671{
e79f245d 1672 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1673 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1674}
1675
35181e86
HZ		 1676/*
1677 * Multiply tsc by a fixed point number represented by ratio.
1678 *
1679 * The most significant 64-N bits (mult) of ratio represent the
1680 * integral part of the fixed point number; the remaining N bits
1681 * (frac) represent the fractional part, ie. ratio represents a fixed
1682 * point number (mult + frac * 2^(-N)).
1683 *
1684 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1685 */
1686static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1687{
1688 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1689}
1690
1691u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1692{
1693 u64 _tsc = tsc;
1694 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1695
1696 if (ratio != kvm_default_tsc_scaling_ratio)
1697 _tsc = __scale_tsc(ratio, tsc);
1698
1699 return _tsc;
1700}
1701EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1702
07c1419a
HZ		 1703static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1704{
1705 u64 tsc;
1706
1707 tsc = kvm_scale_tsc(vcpu, rdtsc());
1708
1709 return target_tsc - tsc;
1710}
1711
4ba76538
HZ		 1712u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1713{
e79f245d
KA		 1714 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1715
1716 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1717}
1718EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1719
a545ab6a
LC		 1720static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1721{
326e7425 1722 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1723}
1724
b0c39dc6
VK		 1725static inline bool kvm_check_tsc_unstable(void)
1726{
1727#ifdef CONFIG_X86_64
1728 /*
1729 * TSC is marked unstable when we're running on Hyper-V,
1730 * 'TSC page' clocksource is good.
1731 */
1732 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1733 return false;
1734#endif
1735 return check_tsc_unstable();
1736}
1737
8fe8ab46 1738void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1739{
1740 struct kvm *kvm = vcpu->kvm;
f38e098f 1741 u64 offset, ns, elapsed;
99e3e30a 1742 unsigned long flags;
b48aa97e 1743 bool matched;
0d3da0d2 1744 bool already_matched;
8fe8ab46 1745 u64 data = msr->data;
c5e8ec8e 1746 bool synchronizing = false;
99e3e30a 1747
038f8c11 1748 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1749 offset = kvm_compute_tsc_offset(vcpu, data);
9285ec4c 1750 ns = ktime_get_boottime_ns();
f38e098f 1751 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1752
03ba32ca 1753 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1754 if (data == 0 && msr->host_initiated) {
1755 /*
1756 * detection of vcpu initialization -- need to sync
1757 * with other vCPUs. This particularly helps to keep
1758 * kvm_clock stable after CPU hotplug
1759 */
1760 synchronizing = true;
1761 } else {
1762 u64 tsc_exp = kvm->arch.last_tsc_write +
1763 nsec_to_cycles(vcpu, elapsed);
1764 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1765 /*
1766 * Special case: TSC write with a small delta (1 second)
1767 * of virtual cycle time against real time is
1768 * interpreted as an attempt to synchronize the CPU.
1769 */
1770 synchronizing = data < tsc_exp + tsc_hz &&
1771 data + tsc_hz > tsc_exp;
1772 }
c5e8ec8e 1773 }
f38e098f
ZA		 1774
1775 /*
5d3cb0f6
ZA		 1776 * For a reliable TSC, we can match TSC offsets, and for an unstable
1777 * TSC, we add elapsed time in this computation. We could let the
1778 * compensation code attempt to catch up if we fall behind, but
1779 * it's better to try to match offsets from the beginning.
1780 */
c5e8ec8e 1781 if (synchronizing &&
5d3cb0f6 1782 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1783 if (!kvm_check_tsc_unstable()) {
e26101b1 1784 offset = kvm->arch.cur_tsc_offset;
f38e098f 1785 } else {
857e4099 1786 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1787 data += delta;
07c1419a 1788 offset = kvm_compute_tsc_offset(vcpu, data);
f38e098f 1789 }
b48aa97e 1790 matched = true;
0d3da0d2 1791 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1792 } else {
1793 /*
1794 * We split periods of matched TSC writes into generations.
1795 * For each generation, we track the original measured
1796 * nanosecond time, offset, and write, so if TSCs are in
1797 * sync, we can match exact offset, and if not, we can match
4a969980 1798 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1799 *
1800 * These values are tracked in kvm->arch.cur_xxx variables.
1801 */
1802 kvm->arch.cur_tsc_generation++;
1803 kvm->arch.cur_tsc_nsec = ns;
1804 kvm->arch.cur_tsc_write = data;
1805 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1806 matched = false;
f38e098f 1807 }
e26101b1
ZA		 1808
1809 /*
1810 * We also track th most recent recorded KHZ, write and time to
1811 * allow the matching interval to be extended at each write.
1812 */
f38e098f
ZA		 1813 kvm->arch.last_tsc_nsec = ns;
1814 kvm->arch.last_tsc_write = data;
5d3cb0f6 1815 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1816
b183aa58 1817 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1818
1819 /* Keep track of which generation this VCPU has synchronized to */
1820 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1821 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1822 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1823
d6321d49 1824 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1825 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1826
a545ab6a 1827 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1828 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1829
1830 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1831 if (!matched) {
b48aa97e 1832 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1833 } else if (!already_matched) {
1834 kvm->arch.nr_vcpus_matched_tsc++;
1835 }
b48aa97e
MT		 1836
1837 kvm_track_tsc_matching(vcpu);
1838 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1839}
e26101b1 1840
99e3e30a
ZA		 1841EXPORT_SYMBOL_GPL(kvm_write_tsc);
1842
58ea6767
HZ		 1843static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1844 s64 adjustment)
1845{
326e7425
LS		 1846 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1847 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1848}
1849
1850static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1851{
1852 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1853 WARN_ON(adjustment < 0);
1854 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1855 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1856}
1857
d828199e
MT		 1858#ifdef CONFIG_X86_64
1859
a5a1d1c2 1860static u64 read_tsc(void)
d828199e 1861{
a5a1d1c2 1862 u64 ret = (u64)rdtsc_ordered();
03b9730b 1863 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1864
1865 if (likely(ret >= last))
1866 return ret;
1867
1868 /*
1869 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1870 * predictable (it's just a function of time and the likely is
d828199e
MT		 1871 * very likely) and there's a data dependence, so force GCC
1872 * to generate a branch instead. I don't barrier() because
1873 * we don't actually need a barrier, and if this function
1874 * ever gets inlined it will generate worse code.
1875 */
1876 asm volatile ("");
1877 return last;
1878}
1879
b0c39dc6 1880static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1881{
1882 long v;
1883 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1884 u64 tsc_pg_val;
1885
1886 switch (gtod->clock.vclock_mode) {
1887 case VCLOCK_HVCLOCK:
1888 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1889 tsc_timestamp);
1890 if (tsc_pg_val != U64_MAX) {
1891 /* TSC page valid */
1892 *mode = VCLOCK_HVCLOCK;
1893 v = (tsc_pg_val - gtod->clock.cycle_last) &
1894 gtod->clock.mask;
1895 } else {
1896 /* TSC page invalid */
1897 *mode = VCLOCK_NONE;
1898 }
1899 break;
1900 case VCLOCK_TSC:
1901 *mode = VCLOCK_TSC;
1902 *tsc_timestamp = read_tsc();
1903 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1904 gtod->clock.mask;
1905 break;
1906 default:
1907 *mode = VCLOCK_NONE;
1908 }
d828199e 1909
b0c39dc6
VK		 1910 if (*mode == VCLOCK_NONE)
1911 *tsc_timestamp = v = 0;
d828199e 1912
d828199e
MT		 1913 return v * gtod->clock.mult;
1914}
1915
b0c39dc6 1916static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1917{
cbcf2dd3 1918 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1919 unsigned long seq;
d828199e 1920 int mode;
cbcf2dd3 1921 u64 ns;
d828199e 1922
d828199e
MT		 1923 do {
1924 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1925 ns = gtod->nsec_base;
b0c39dc6 1926 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1927 ns >>= gtod->clock.shift;
cbcf2dd3 1928 ns += gtod->boot_ns;
d828199e 1929 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1930 *t = ns;
d828199e
MT		 1931
1932 return mode;
1933}
1934
899a31f5 1935static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1936{
1937 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1938 unsigned long seq;
1939 int mode;
1940 u64 ns;
1941
1942 do {
1943 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1944 ts->tv_sec = gtod->wall_time_sec;
1945 ns = gtod->nsec_base;
b0c39dc6 1946 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1947 ns >>= gtod->clock.shift;
1948 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1949
1950 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1951 ts->tv_nsec = ns;
1952
1953 return mode;
1954}
1955
b0c39dc6
VK		 1956/* returns true if host is using TSC based clocksource */
1957static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1958{
d828199e 1959 /* checked again under seqlock below */
b0c39dc6 1960 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1961 return false;
1962
b0c39dc6
VK		 1963 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1964 tsc_timestamp));
d828199e 1965}
55dd00a7 1966
b0c39dc6 1967/* returns true if host is using TSC based clocksource */
899a31f5 1968static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1969 u64 *tsc_timestamp)
55dd00a7
MT		 1970{
1971 /* checked again under seqlock below */
b0c39dc6 1972 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1973 return false;
1974
b0c39dc6 1975 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1976}
d828199e
MT		 1977#endif
1978
1979/*
1980 *
b48aa97e
MT		 1981 * Assuming a stable TSC across physical CPUS, and a stable TSC
1982 * across virtual CPUs, the following condition is possible.
1983 * Each numbered line represents an event visible to both
d828199e
MT		 1984 * CPUs at the next numbered event.
1985 *
1986 * "timespecX" represents host monotonic time. "tscX" represents
1987 * RDTSC value.
1988 *
1989 * VCPU0 on CPU0 | VCPU1 on CPU1
1990 *
1991 * 1. read timespec0,tsc0
1992 * 2. | timespec1 = timespec0 + N
1993 * | tsc1 = tsc0 + M
1994 * 3. transition to guest | transition to guest
1995 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1996 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1997 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1998 *
1999 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2000 *
2001 * - ret0 < ret1
2002 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2003 * ...
2004 * - 0 < N - M => M < N
2005 *
2006 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2007 * always the case (the difference between two distinct xtime instances
2008 * might be smaller then the difference between corresponding TSC reads,
2009 * when updating guest vcpus pvclock areas).
2010 *
2011 * To avoid that problem, do not allow visibility of distinct
2012 * system_timestamp/tsc_timestamp values simultaneously: use a master
2013 * copy of host monotonic time values. Update that master copy
2014 * in lockstep.
2015 *
b48aa97e 2016 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 2017 *
2018 */
2019
2020static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2021{
2022#ifdef CONFIG_X86_64
2023 struct kvm_arch *ka = &kvm->arch;
2024 int vclock_mode;
b48aa97e
MT		 2025 bool host_tsc_clocksource, vcpus_matched;
2026
2027 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2028 atomic_read(&kvm->online_vcpus));
d828199e
MT		 2029
2030 /*
2031 * If the host uses TSC clock, then passthrough TSC as stable
2032 * to the guest.
2033 */
b48aa97e 2034 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 2035 &ka->master_kernel_ns,
2036 &ka->master_cycle_now);
2037
16a96021 2038 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2039 && !ka->backwards_tsc_observed
54750f2c 2040 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2041
d828199e
MT		 2042 if (ka->use_master_clock)
2043 atomic_set(&kvm_guest_has_master_clock, 1);
2044
2045 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2046 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2047 vcpus_matched);
d828199e
MT		 2048#endif
2049}
2050
2860c4b1
PB		 2051void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2052{
2053 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2054}
2055
2e762ff7
MT		 2056static void kvm_gen_update_masterclock(struct kvm *kvm)
2057{
2058#ifdef CONFIG_X86_64
2059 int i;
2060 struct kvm_vcpu *vcpu;
2061 struct kvm_arch *ka = &kvm->arch;
2062
2063 spin_lock(&ka->pvclock_gtod_sync_lock);
2064 kvm_make_mclock_inprogress_request(kvm);
2065 /* no guest entries from this point */
2066 pvclock_update_vm_gtod_copy(kvm);
2067
2068 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2069 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2070
2071 /* guest entries allowed */
2072 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2073 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2074
2075 spin_unlock(&ka->pvclock_gtod_sync_lock);
2076#endif
2077}
2078
e891a32e 2079u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2080{
108b249c 2081 struct kvm_arch *ka = &kvm->arch;
8b953440 2082 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2083 u64 ret;
108b249c 2084
8b953440
PB		 2085 spin_lock(&ka->pvclock_gtod_sync_lock);
2086 if (!ka->use_master_clock) {
2087 spin_unlock(&ka->pvclock_gtod_sync_lock);
9285ec4c 2088 return ktime_get_boottime_ns() + ka->kvmclock_offset;
108b249c
PB		 2089 }
2090
8b953440
PB		 2091 hv_clock.tsc_timestamp = ka->master_cycle_now;
2092 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2093 spin_unlock(&ka->pvclock_gtod_sync_lock);
2094
e2c2206a
WL		 2095 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2096 get_cpu();
2097
e70b57a6
WL		 2098 if (__this_cpu_read(cpu_tsc_khz)) {
2099 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2100 &hv_clock.tsc_shift,
2101 &hv_clock.tsc_to_system_mul);
2102 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2103 } else
9285ec4c 2104 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2105
2106 put_cpu();
2107
2108 return ret;
108b249c
PB		 2109}
2110
0d6dd2ff
PB		 2111static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2112{
2113 struct kvm_vcpu_arch *vcpu = &v->arch;
2114 struct pvclock_vcpu_time_info guest_hv_clock;
2115
4e335d9e 2116 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2117 &guest_hv_clock, sizeof(guest_hv_clock))))
2118 return;
2119
2120 /* This VCPU is paused, but it's legal for a guest to read another
2121 * VCPU's kvmclock, so we really have to follow the specification where
2122 * it says that version is odd if data is being modified, and even after
2123 * it is consistent.
2124 *
2125 * Version field updates must be kept separate. This is because
2126 * kvm_write_guest_cached might use a "rep movs" instruction, and
2127 * writes within a string instruction are weakly ordered. So there
2128 * are three writes overall.
2129 *
2130 * As a small optimization, only write the version field in the first
2131 * and third write. The vcpu->pv_time cache is still valid, because the
2132 * version field is the first in the struct.
2133 */
2134 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2135
51c4b8bb
LA		 2136 if (guest_hv_clock.version & 1)
2137 ++guest_hv_clock.version; /* first time write, random junk */
2138
0d6dd2ff 2139 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2140 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2141 &vcpu->hv_clock,
2142 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2143
2144 smp_wmb();
2145
2146 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2147 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2148
2149 if (vcpu->pvclock_set_guest_stopped_request) {
2150 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2151 vcpu->pvclock_set_guest_stopped_request = false;
2152 }
2153
2154 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2155
4e335d9e
PB		 2156 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2157 &vcpu->hv_clock,
2158 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2159
2160 smp_wmb();
2161
2162 vcpu->hv_clock.version++;
4e335d9e
PB		 2163 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2164 &vcpu->hv_clock,
2165 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2166}
2167
34c238a1 2168static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2169{
78db6a50 2170 unsigned long flags, tgt_tsc_khz;
18068523 2171 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2172 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2173 s64 kernel_ns;
d828199e 2174 u64 tsc_timestamp, host_tsc;
51d59c6b 2175 u8 pvclock_flags;
d828199e
MT		 2176 bool use_master_clock;
2177
2178 kernel_ns = 0;
2179 host_tsc = 0;
18068523 2180
d828199e
MT		 2181 /*
2182 * If the host uses TSC clock, then passthrough TSC as stable
2183 * to the guest.
2184 */
2185 spin_lock(&ka->pvclock_gtod_sync_lock);
2186 use_master_clock = ka->use_master_clock;
2187 if (use_master_clock) {
2188 host_tsc = ka->master_cycle_now;
2189 kernel_ns = ka->master_kernel_ns;
2190 }
2191 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2192
2193 /* Keep irq disabled to prevent changes to the clock */
2194 local_irq_save(flags);
78db6a50
PB		 2195 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2196 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2197 local_irq_restore(flags);
2198 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2199 return 1;
2200 }
d828199e 2201 if (!use_master_clock) {
4ea1636b 2202 host_tsc = rdtsc();
9285ec4c 2203 kernel_ns = ktime_get_boottime_ns();
d828199e
MT		 2204 }
2205
4ba76538 2206 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2207
c285545f
ZA		 2208 /*
2209 * We may have to catch up the TSC to match elapsed wall clock
2210 * time for two reasons, even if kvmclock is used.
2211 * 1) CPU could have been running below the maximum TSC rate
2212 * 2) Broken TSC compensation resets the base at each VCPU
2213 * entry to avoid unknown leaps of TSC even when running
2214 * again on the same CPU. This may cause apparent elapsed
2215 * time to disappear, and the guest to stand still or run
2216 * very slowly.
2217 */
2218 if (vcpu->tsc_catchup) {
2219 u64 tsc = compute_guest_tsc(v, kernel_ns);
2220 if (tsc > tsc_timestamp) {
f1e2b260 2221 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2222 tsc_timestamp = tsc;
2223 }
50d0a0f9
GH		 2224 }
2225
18068523
GOC		 2226 local_irq_restore(flags);
2227
0d6dd2ff 2228 /* With all the info we got, fill in the values */
18068523 2229
78db6a50
PB		 2230 if (kvm_has_tsc_control)
2231 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2232
2233 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2234 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2235 &vcpu->hv_clock.tsc_shift,
2236 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2237 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2238 }
2239
1d5f066e 2240 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2241 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2242 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2243
d828199e 2244 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2245 pvclock_flags = 0;
d828199e
MT		 2246 if (use_master_clock)
2247 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2248
78c0337a
MT		 2249 vcpu->hv_clock.flags = pvclock_flags;
2250
095cf55d
PB		 2251 if (vcpu->pv_time_enabled)
2252 kvm_setup_pvclock_page(v);
2253 if (v == kvm_get_vcpu(v->kvm, 0))
2254 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2255 return 0;
c8076604
GH		 2256}
2257
0061d53d
MT		 2258/*
2259 * kvmclock updates which are isolated to a given vcpu, such as
2260 * vcpu->cpu migration, should not allow system_timestamp from
2261 * the rest of the vcpus to remain static. Otherwise ntp frequency
2262 * correction applies to one vcpu's system_timestamp but not
2263 * the others.
2264 *
2265 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2266 * We need to rate-limit these requests though, as they can
2267 * considerably slow guests that have a large number of vcpus.
2268 * The time for a remote vcpu to update its kvmclock is bound
2269 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2270 */
2271
7e44e449
AJ		 2272#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2273
2274static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2275{
2276 int i;
7e44e449
AJ		 2277 struct delayed_work *dwork = to_delayed_work(work);
2278 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2279 kvmclock_update_work);
2280 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2281 struct kvm_vcpu *vcpu;
2282
2283 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2284 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2285 kvm_vcpu_kick(vcpu);
2286 }
2287}
2288
7e44e449
AJ		 2289static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2290{
2291 struct kvm *kvm = v->kvm;
2292
105b21bb 2293 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2294 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2295 KVMCLOCK_UPDATE_DELAY);
2296}
2297
332967a3
AJ		 2298#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2299
2300static void kvmclock_sync_fn(struct work_struct *work)
2301{
2302 struct delayed_work *dwork = to_delayed_work(work);
2303 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2304 kvmclock_sync_work);
2305 struct kvm *kvm = container_of(ka, struct kvm, arch);
2306
630994b3
MT		 2307 if (!kvmclock_periodic_sync)
2308 return;
2309
332967a3
AJ		 2310 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2311 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2312 KVMCLOCK_SYNC_PERIOD);
2313}
2314
191c8137
BP		 2315/*
2316 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2317 */
2318static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2319{
2320 /* McStatusWrEn enabled? */
2321 if (guest_cpuid_is_amd(vcpu))
2322 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2323
2324 return false;
2325}
2326
9ffd986c 2327static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2328{
890ca9ae
HY		 2329 u64 mcg_cap = vcpu->arch.mcg_cap;
2330 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2331 u32 msr = msr_info->index;
2332 u64 data = msr_info->data;
890ca9ae 2333
15c4a640 2334 switch (msr) {
15c4a640 2335 case MSR_IA32_MCG_STATUS:
890ca9ae 2336 vcpu->arch.mcg_status = data;
15c4a640 2337 break;
c7ac679c 2338 case MSR_IA32_MCG_CTL:
44883f01
PB		 2339 if (!(mcg_cap & MCG_CTL_P) &&
2340 (data || !msr_info->host_initiated))
890ca9ae
HY		 2341 return 1;
2342 if (data != 0 && data != ~(u64)0)
44883f01 2343 return 1;
890ca9ae
HY		 2344 vcpu->arch.mcg_ctl = data;
2345 break;
2346 default:
2347 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2348 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2349 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2350 /* only 0 or all 1s can be written to IA32_MCi_CTL
2351 * some Linux kernels though clear bit 10 in bank 4 to
2352 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2353 * this to avoid an uncatched #GP in the guest
2354 */
890ca9ae 2355 if ((offset & 0x3) == 0 &&
114be429 2356 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2357 return -1;
191c8137
BP		 2358
2359 /* MCi_STATUS */
9ffd986c 2360 if (!msr_info->host_initiated &&
191c8137
BP		 2361 (offset & 0x3) == 1 && data != 0) {
2362 if (!can_set_mci_status(vcpu))
2363 return -1;
2364 }
2365
890ca9ae
HY		 2366 vcpu->arch.mce_banks[offset] = data;
2367 break;
2368 }
2369 return 1;
2370 }
2371 return 0;
2372}
2373
ffde22ac
ES		 2374static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2375{
2376 struct kvm *kvm = vcpu->kvm;
2377 int lm = is_long_mode(vcpu);
2378 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2379 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2380 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2381 : kvm->arch.xen_hvm_config.blob_size_32;
2382 u32 page_num = data & ~PAGE_MASK;
2383 u64 page_addr = data & PAGE_MASK;
2384 u8 *page;
2385 int r;
2386
2387 r = -E2BIG;
2388 if (page_num >= blob_size)
2389 goto out;
2390 r = -ENOMEM;
ff5c2c03
SL		 2391 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2392 if (IS_ERR(page)) {
2393 r = PTR_ERR(page);
ffde22ac 2394 goto out;
ff5c2c03 2395 }
54bf36aa 2396 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2397 goto out_free;
2398 r = 0;
2399out_free:
2400 kfree(page);
2401out:
2402 return r;
2403}
2404
344d9588
GN		 2405static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2406{
2407 gpa_t gpa = data & ~0x3f;
2408
52a5c155
WL		 2409 /* Bits 3:5 are reserved, Should be zero */
2410 if (data & 0x38)
344d9588
GN		 2411 return 1;
2412
2413 vcpu->arch.apf.msr_val = data;
2414
2415 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2416 kvm_clear_async_pf_completion_queue(vcpu);
2417 kvm_async_pf_hash_reset(vcpu);
2418 return 0;
2419 }
2420
4e335d9e 2421 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2422 sizeof(u32)))
344d9588
GN		 2423 return 1;
2424
6adba527 2425 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2426 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2427 kvm_async_pf_wakeup_all(vcpu);
2428 return 0;
2429}
2430
12f9a48f
GC		 2431static void kvmclock_reset(struct kvm_vcpu *vcpu)
2432{
0b79459b 2433 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2434}
2435
f38a7b75
WL		 2436static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2437{
2438 ++vcpu->stat.tlb_flush;
2439 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2440}
2441
c9aaa895
GC		 2442static void record_steal_time(struct kvm_vcpu *vcpu)
2443{
2444 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2445 return;
2446
4e335d9e 2447 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2448 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2449 return;
2450
f38a7b75
WL		 2451 /*
2452 * Doing a TLB flush here, on the guest's behalf, can avoid
2453 * expensive IPIs.
2454 */
2455 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2456 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2457
35f3fae1
WL		 2458 if (vcpu->arch.st.steal.version & 1)
2459 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2460
2461 vcpu->arch.st.steal.version += 1;
2462
4e335d9e 2463 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2464 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2465
2466 smp_wmb();
2467
c54cdf14
LC		 2468 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2469 vcpu->arch.st.last_steal;
2470 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2471
4e335d9e 2472 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2473 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2474
2475 smp_wmb();
2476
2477 vcpu->arch.st.steal.version += 1;
c9aaa895 2478
4e335d9e 2479 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2480 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2481}
2482
8fe8ab46 2483int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2484{
5753785f 2485 bool pr = false;
8fe8ab46
WA		 2486 u32 msr = msr_info->index;
2487 u64 data = msr_info->data;
5753785f 2488
15c4a640 2489 switch (msr) {
2e32b719 2490 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2491 case MSR_IA32_UCODE_WRITE:
2492 case MSR_VM_HSAVE_PA:
2493 case MSR_AMD64_PATCH_LOADER:
2494 case MSR_AMD64_BU_CFG2:
405a353a 2495 case MSR_AMD64_DC_CFG:
0e1b869f 2496 case MSR_F15H_EX_CFG:
2e32b719
BP		 2497 break;
2498
518e7b94
WL		 2499 case MSR_IA32_UCODE_REV:
2500 if (msr_info->host_initiated)
2501 vcpu->arch.microcode_version = data;
2502 break;
0cf9135b
SC		 2503 case MSR_IA32_ARCH_CAPABILITIES:
2504 if (!msr_info->host_initiated)
2505 return 1;
2506 vcpu->arch.arch_capabilities = data;
2507 break;
15c4a640 2508 case MSR_EFER:
11988499 2509 return set_efer(vcpu, msr_info);
8f1589d9
AP		 2510 case MSR_K7_HWCR:
2511 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2512 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2513 data &= ~(u64)0x8; /* ignore TLB cache disable */
191c8137
BP		 2514
2515 /* Handle McStatusWrEn */
2516 if (data == BIT_ULL(18)) {
2517 vcpu->arch.msr_hwcr = data;
2518 } else if (data != 0) {
a737f256
CD		 2519 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2520 data);
8f1589d9
AP		 2521 return 1;
2522 }
15c4a640 2523 break;
f7c6d140
AP		 2524 case MSR_FAM10H_MMIO_CONF_BASE:
2525 if (data != 0) {
a737f256
CD		 2526 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2527 "0x%llx\n", data);
f7c6d140
AP		 2528 return 1;
2529 }
15c4a640 2530 break;
b5e2fec0
AG		 2531 case MSR_IA32_DEBUGCTLMSR:
2532 if (!data) {
2533 /* We support the non-activated case already */
2534 break;
2535 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2536 /* Values other than LBR and BTF are vendor-specific,
2537 thus reserved and should throw a #GP */
2538 return 1;
2539 }
a737f256
CD		 2540 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2541 __func__, data);
b5e2fec0 2542 break;
9ba075a6 2543 case 0x200 ... 0x2ff:
ff53604b 2544 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2545 case MSR_IA32_APICBASE:
58cb628d 2546 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2547 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2548 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2549 case MSR_IA32_TSCDEADLINE:
2550 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2551 break;
ba904635 2552 case MSR_IA32_TSC_ADJUST:
d6321d49 2553 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2554 if (!msr_info->host_initiated) {
d913b904 2555 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2556 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2557 }
2558 vcpu->arch.ia32_tsc_adjust_msr = data;
2559 }
2560 break;
15c4a640 2561 case MSR_IA32_MISC_ENABLE:
511a8556
WL		 2562 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2563 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2564 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2565 return 1;
2566 vcpu->arch.ia32_misc_enable_msr = data;
2567 kvm_update_cpuid(vcpu);
2568 } else {
2569 vcpu->arch.ia32_misc_enable_msr = data;
2570 }
15c4a640 2571 break;
64d60670
PB		 2572 case MSR_IA32_SMBASE:
2573 if (!msr_info->host_initiated)
2574 return 1;
2575 vcpu->arch.smbase = data;
2576 break;
73f624f4
PB		 2577 case MSR_IA32_POWER_CTL:
2578 vcpu->arch.msr_ia32_power_ctl = data;
2579 break;
dd259935
PB		 2580 case MSR_IA32_TSC:
2581 kvm_write_tsc(vcpu, msr_info);
2582 break;
52797bf9
LA		 2583 case MSR_SMI_COUNT:
2584 if (!msr_info->host_initiated)
2585 return 1;
2586 vcpu->arch.smi_count = data;
2587 break;
11c6bffa 2588 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2589 case MSR_KVM_WALL_CLOCK:
2590 vcpu->kvm->arch.wall_clock = data;
2591 kvm_write_wall_clock(vcpu->kvm, data);
2592 break;
11c6bffa 2593 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2594 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2595 struct kvm_arch *ka = &vcpu->kvm->arch;
2596
12f9a48f 2597 kvmclock_reset(vcpu);
18068523 2598
54750f2c
MT		 2599 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2600 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2601
2602 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2603 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2604
2605 ka->boot_vcpu_runs_old_kvmclock = tmp;
2606 }
2607
18068523 2608 vcpu->arch.time = data;
0061d53d 2609 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2610
2611 /* we verify if the enable bit is set... */
2612 if (!(data & 1))
2613 break;
2614
4e335d9e 2615 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2616 &vcpu->arch.pv_time, data & ~1ULL,
2617 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2618 vcpu->arch.pv_time_enabled = false;
2619 else
2620 vcpu->arch.pv_time_enabled = true;
32cad84f 2621
18068523
GOC		 2622 break;
2623 }
344d9588
GN		 2624 case MSR_KVM_ASYNC_PF_EN:
2625 if (kvm_pv_enable_async_pf(vcpu, data))
2626 return 1;
2627 break;
c9aaa895
GC		 2628 case MSR_KVM_STEAL_TIME:
2629
2630 if (unlikely(!sched_info_on()))
2631 return 1;
2632
2633 if (data & KVM_STEAL_RESERVED_MASK)
2634 return 1;
2635
4e335d9e 2636 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2637 data & KVM_STEAL_VALID_BITS,
2638 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2639 return 1;
2640
2641 vcpu->arch.st.msr_val = data;
2642
2643 if (!(data & KVM_MSR_ENABLED))
2644 break;
2645
c9aaa895
GC		 2646 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2647
2648 break;
ae7a2a3f 2649 case MSR_KVM_PV_EOI_EN:
72bbf935 2650 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2651 return 1;
2652 break;
c9aaa895 2653
2d5ba19b
MT		 2654 case MSR_KVM_POLL_CONTROL:
2655 /* only enable bit supported */
2656 if (data & (-1ULL << 1))
2657 return 1;
2658
2659 vcpu->arch.msr_kvm_poll_control = data;
2660 break;
2661
890ca9ae
HY		 2662 case MSR_IA32_MCG_CTL:
2663 case MSR_IA32_MCG_STATUS:
81760dcc 2664 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2665 return set_msr_mce(vcpu, msr_info);
71db6023 2666
6912ac32
WH		 2667 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2668 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2669 pr = true; /* fall through */
2670 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2671 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2672 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2673 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2674
2675 if (pr || data != 0)
a737f256
CD		 2676 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2677 "0x%x data 0x%llx\n", msr, data);
5753785f 2678 break;
84e0cefa
JS		 2679 case MSR_K7_CLK_CTL:
2680 /*
2681 * Ignore all writes to this no longer documented MSR.
2682 * Writes are only relevant for old K7 processors,
2683 * all pre-dating SVM, but a recommended workaround from
4a969980 2684 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2685 * affected processor models on the command line, hence
2686 * the need to ignore the workaround.
2687 */
2688 break;
55cd8e5a 2689 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2690 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2691 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2692 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2693 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2694 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2695 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2696 return kvm_hv_set_msr_common(vcpu, msr, data,
2697 msr_info->host_initiated);
91c9c3ed 2698 case MSR_IA32_BBL_CR_CTL3:
2699 /* Drop writes to this legacy MSR -- see rdmsr
2700 * counterpart for further detail.
2701 */
fab0aa3b
EM		 2702 if (report_ignored_msrs)
2703 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2704 msr, data);
91c9c3ed 2705 break;
2b036c6b 2706 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2707 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2708 return 1;
2709 vcpu->arch.osvw.length = data;
2710 break;
2711 case MSR_AMD64_OSVW_STATUS:
d6321d49 2712 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2713 return 1;
2714 vcpu->arch.osvw.status = data;
2715 break;
db2336a8
KH		 2716 case MSR_PLATFORM_INFO:
2717 if (!msr_info->host_initiated ||
db2336a8
KH		 2718 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2719 cpuid_fault_enabled(vcpu)))
2720 return 1;
2721 vcpu->arch.msr_platform_info = data;
2722 break;
2723 case MSR_MISC_FEATURES_ENABLES:
2724 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2725 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2726 !supports_cpuid_fault(vcpu)))
2727 return 1;
2728 vcpu->arch.msr_misc_features_enables = data;
2729 break;
15c4a640 2730 default:
ffde22ac
ES		 2731 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2732 return xen_hvm_config(vcpu, data);
c6702c9d 2733 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2734 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2735 if (!ignore_msrs) {
ae0f5499 2736 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2737 msr, data);
ed85c068
AP		 2738 return 1;
2739 } else {
fab0aa3b
EM		 2740 if (report_ignored_msrs)
2741 vcpu_unimpl(vcpu,
2742 "ignored wrmsr: 0x%x data 0x%llx\n",
2743 msr, data);
ed85c068
AP		 2744 break;
2745 }
15c4a640
CO		 2746 }
2747 return 0;
2748}
2749EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2750
2751
2752/*
2753 * Reads an msr value (of 'msr_index') into 'pdata'.
2754 * Returns 0 on success, non-0 otherwise.
2755 * Assumes vcpu_load() was already called.
2756 */
609e36d3 2757int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2758{
609e36d3 2759 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2760}
ff651cb6 2761EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2762
44883f01 2763static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2764{
2765 u64 data;
890ca9ae
HY		 2766 u64 mcg_cap = vcpu->arch.mcg_cap;
2767 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2768
2769 switch (msr) {
15c4a640
CO		 2770 case MSR_IA32_P5_MC_ADDR:
2771 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2772 data = 0;
2773 break;
15c4a640 2774 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2775 data = vcpu->arch.mcg_cap;
2776 break;
c7ac679c 2777 case MSR_IA32_MCG_CTL:
44883f01 2778 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2779 return 1;
2780 data = vcpu->arch.mcg_ctl;
2781 break;
2782 case MSR_IA32_MCG_STATUS:
2783 data = vcpu->arch.mcg_status;
2784 break;
2785 default:
2786 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2787 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2788 u32 offset = msr - MSR_IA32_MC0_CTL;
2789 data = vcpu->arch.mce_banks[offset];
2790 break;
2791 }
2792 return 1;
2793 }
2794 *pdata = data;
2795 return 0;
2796}
2797
609e36d3 2798int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2799{
609e36d3 2800 switch (msr_info->index) {
890ca9ae 2801 case MSR_IA32_PLATFORM_ID:
15c4a640 2802 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2803 case MSR_IA32_DEBUGCTLMSR:
2804 case MSR_IA32_LASTBRANCHFROMIP:
2805 case MSR_IA32_LASTBRANCHTOIP:
2806 case MSR_IA32_LASTINTFROMIP:
2807 case MSR_IA32_LASTINTTOIP:
60af2ecd 2808 case MSR_K8_SYSCFG:
3afb1121
PB		 2809 case MSR_K8_TSEG_ADDR:
2810 case MSR_K8_TSEG_MASK:
61a6bd67 2811 case MSR_VM_HSAVE_PA:
1fdbd48c 2812 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2813 case MSR_AMD64_NB_CFG:
f7c6d140 2814 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2815 case MSR_AMD64_BU_CFG2:
0c2df2a1 2816 case MSR_IA32_PERF_CTL:
405a353a 2817 case MSR_AMD64_DC_CFG:
0e1b869f 2818 case MSR_F15H_EX_CFG:
609e36d3 2819 msr_info->data = 0;
15c4a640 2820 break;
c51eb52b 2821 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2822 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2823 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2824 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2825 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2826 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2827 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2828 msr_info->data = 0;
5753785f 2829 break;
742bc670 2830 case MSR_IA32_UCODE_REV:
518e7b94 2831 msr_info->data = vcpu->arch.microcode_version;
742bc670 2832 break;
0cf9135b
SC		 2833 case MSR_IA32_ARCH_CAPABILITIES:
2834 if (!msr_info->host_initiated &&
2835 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2836 return 1;
2837 msr_info->data = vcpu->arch.arch_capabilities;
2838 break;
73f624f4
PB		 2839 case MSR_IA32_POWER_CTL:
2840 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2841 break;
dd259935
PB		 2842 case MSR_IA32_TSC:
2843 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2844 break;
9ba075a6 2845 case MSR_MTRRcap:
9ba075a6 2846 case 0x200 ... 0x2ff:
ff53604b 2847 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2848 case 0xcd: /* fsb frequency */
609e36d3 2849 msr_info->data = 3;
15c4a640 2850 break;
7b914098
JS		 2851 /*
2852 * MSR_EBC_FREQUENCY_ID
2853 * Conservative value valid for even the basic CPU models.
2854 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2855 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2856 * and 266MHz for model 3, or 4. Set Core Clock
2857 * Frequency to System Bus Frequency Ratio to 1 (bits
2858 * 31:24) even though these are only valid for CPU
2859 * models > 2, however guests may end up dividing or
2860 * multiplying by zero otherwise.
2861 */
2862 case MSR_EBC_FREQUENCY_ID:
609e36d3 2863 msr_info->data = 1 << 24;
7b914098 2864 break;
15c4a640 2865 case MSR_IA32_APICBASE:
609e36d3 2866 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2867 break;
0105d1a5 2868 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2869 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2870 break;
a3e06bbe 2871 case MSR_IA32_TSCDEADLINE:
609e36d3 2872 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2873 break;
ba904635 2874 case MSR_IA32_TSC_ADJUST:
609e36d3 2875 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2876 break;
15c4a640 2877 case MSR_IA32_MISC_ENABLE:
609e36d3 2878 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2879 break;
64d60670
PB		 2880 case MSR_IA32_SMBASE:
2881 if (!msr_info->host_initiated)
2882 return 1;
2883 msr_info->data = vcpu->arch.smbase;
15c4a640 2884 break;
52797bf9
LA		 2885 case MSR_SMI_COUNT:
2886 msr_info->data = vcpu->arch.smi_count;
2887 break;
847f0ad8
AG		 2888 case MSR_IA32_PERF_STATUS:
2889 /* TSC increment by tick */
609e36d3 2890 msr_info->data = 1000ULL;
847f0ad8 2891 /* CPU multiplier */
b0996ae4 2892 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2893 break;
15c4a640 2894 case MSR_EFER:
609e36d3 2895 msr_info->data = vcpu->arch.efer;
15c4a640 2896 break;
18068523 2897 case MSR_KVM_WALL_CLOCK:
11c6bffa 2898 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2899 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2900 break;
2901 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2902 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2903 msr_info->data = vcpu->arch.time;
18068523 2904 break;
344d9588 2905 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2906 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2907 break;
c9aaa895 2908 case MSR_KVM_STEAL_TIME:
609e36d3 2909 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2910 break;
1d92128f 2911 case MSR_KVM_PV_EOI_EN:
609e36d3 2912 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2913 break;
2d5ba19b
MT		 2914 case MSR_KVM_POLL_CONTROL:
2915 msr_info->data = vcpu->arch.msr_kvm_poll_control;
2916 break;
890ca9ae
HY		 2917 case MSR_IA32_P5_MC_ADDR:
2918 case MSR_IA32_P5_MC_TYPE:
2919 case MSR_IA32_MCG_CAP:
2920 case MSR_IA32_MCG_CTL:
2921 case MSR_IA32_MCG_STATUS:
81760dcc 2922 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2923 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2924 msr_info->host_initiated);
84e0cefa
JS		 2925 case MSR_K7_CLK_CTL:
2926 /*
2927 * Provide expected ramp-up count for K7. All other
2928 * are set to zero, indicating minimum divisors for
2929 * every field.
2930 *
2931 * This prevents guest kernels on AMD host with CPU
2932 * type 6, model 8 and higher from exploding due to
2933 * the rdmsr failing.
2934 */
609e36d3 2935 msr_info->data = 0x20000000;
84e0cefa 2936 break;
55cd8e5a 2937 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2938 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2939 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2940 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2941 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2942 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2943 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2944 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2945 msr_info->index, &msr_info->data,
2946 msr_info->host_initiated);
55cd8e5a 2947 break;
91c9c3ed 2948 case MSR_IA32_BBL_CR_CTL3:
2949 /* This legacy MSR exists but isn't fully documented in current
2950 * silicon. It is however accessed by winxp in very narrow
2951 * scenarios where it sets bit #19, itself documented as
2952 * a "reserved" bit. Best effort attempt to source coherent
2953 * read data here should the balance of the register be
2954 * interpreted by the guest:
2955 *
2956 * L2 cache control register 3: 64GB range, 256KB size,
2957 * enabled, latency 0x1, configured
2958 */
609e36d3 2959 msr_info->data = 0xbe702111;
91c9c3ed 2960 break;
2b036c6b 2961 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2962 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2963 return 1;
609e36d3 2964 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2965 break;
2966 case MSR_AMD64_OSVW_STATUS:
d6321d49 2967 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2968 return 1;
609e36d3 2969 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2970 break;
db2336a8 2971 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2972 if (!msr_info->host_initiated &&
2973 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2974 return 1;
db2336a8
KH		 2975 msr_info->data = vcpu->arch.msr_platform_info;
2976 break;
2977 case MSR_MISC_FEATURES_ENABLES:
2978 msr_info->data = vcpu->arch.msr_misc_features_enables;
2979 break;
191c8137
BP		 2980 case MSR_K7_HWCR:
2981 msr_info->data = vcpu->arch.msr_hwcr;
2982 break;
15c4a640 2983 default:
c6702c9d 2984 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2985 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2986 if (!ignore_msrs) {
ae0f5499
BD		 2987 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2988 msr_info->index);
ed85c068
AP		 2989 return 1;
2990 } else {
fab0aa3b
EM		 2991 if (report_ignored_msrs)
2992 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2993 msr_info->index);
609e36d3 2994 msr_info->data = 0;
ed85c068
AP		 2995 }
2996 break;
15c4a640 2997 }
15c4a640
CO		 2998 return 0;
2999}
3000EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3001
313a3dc7
CO		 3002/*
3003 * Read or write a bunch of msrs. All parameters are kernel addresses.
3004 *
3005 * @return number of msrs set successfully.
3006 */
3007static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3008 struct kvm_msr_entry *entries,
3009 int (*do_msr)(struct kvm_vcpu *vcpu,
3010 unsigned index, u64 *data))
3011{
801e459a 3012 int i;
313a3dc7 3013
313a3dc7
CO		 3014 for (i = 0; i < msrs->nmsrs; ++i)
3015 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3016 break;
3017
313a3dc7
CO		 3018 return i;
3019}
3020
3021/*
3022 * Read or write a bunch of msrs. Parameters are user addresses.
3023 *
3024 * @return number of msrs set successfully.
3025 */
3026static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3027 int (*do_msr)(struct kvm_vcpu *vcpu,
3028 unsigned index, u64 *data),
3029 int writeback)
3030{
3031 struct kvm_msrs msrs;
3032 struct kvm_msr_entry *entries;
3033 int r, n;
3034 unsigned size;
3035
3036 r = -EFAULT;
0e96f31e 3037 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 3038 goto out;
3039
3040 r = -E2BIG;
3041 if (msrs.nmsrs >= MAX_IO_MSRS)
3042 goto out;
3043
313a3dc7 3044 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 3045 entries = memdup_user(user_msrs->entries, size);
3046 if (IS_ERR(entries)) {
3047 r = PTR_ERR(entries);
313a3dc7 3048 goto out;
ff5c2c03 3049 }
313a3dc7
CO		 3050
3051 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3052 if (r < 0)
3053 goto out_free;
3054
3055 r = -EFAULT;
3056 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3057 goto out_free;
3058
3059 r = n;
3060
3061out_free:
7a73c028 3062 kfree(entries);
313a3dc7
CO		 3063out:
3064 return r;
3065}
3066
4d5422ce
WL		 3067static inline bool kvm_can_mwait_in_guest(void)
3068{
3069 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 3070 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3071 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 3072}
3073
784aa3d7 3074int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 3075{
4d5422ce 3076 int r = 0;
018d00d2
ZX		 3077
3078 switch (ext) {
3079 case KVM_CAP_IRQCHIP:
3080 case KVM_CAP_HLT:
3081 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 3082 case KVM_CAP_SET_TSS_ADDR:
07716717 3083 case KVM_CAP_EXT_CPUID:
9c15bb1d 3084 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3085 case KVM_CAP_CLOCKSOURCE:
7837699f 3086 case KVM_CAP_PIT:
a28e4f5a 3087 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3088 case KVM_CAP_MP_STATE:
ed848624 3089 case KVM_CAP_SYNC_MMU:
a355c85c 3090 case KVM_CAP_USER_NMI:
52d939a0 3091 case KVM_CAP_REINJECT_CONTROL:
4925663a 3092 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3093 case KVM_CAP_IOEVENTFD:
f848a5a8 3094 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3095 case KVM_CAP_PIT2:
e9f42757 3096 case KVM_CAP_PIT_STATE2:
b927a3ce 3097 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3098 case KVM_CAP_XEN_HVM:
3cfc3092 3099 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3100 case KVM_CAP_HYPERV:
10388a07 3101 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3102 case KVM_CAP_HYPERV_SPIN:
5c919412 3103 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3104 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3105 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3106 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3107 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3108 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 3109 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
2bc39970 3110 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3111 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3112 case KVM_CAP_DEBUGREGS:
d2be1651 3113 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3114 case KVM_CAP_XSAVE:
344d9588 3115 case KVM_CAP_ASYNC_PF:
92a1f12d 3116 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3117 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3118 case KVM_CAP_READONLY_MEM:
5f66b620 3119 case KVM_CAP_HYPERV_TIME:
100943c5 3120 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3121 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3122 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3123 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3124 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3125 case KVM_CAP_IMMEDIATE_EXIT:
66bb8a06 3126 case KVM_CAP_PMU_EVENT_FILTER:
801e459a 3127 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3128 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3129 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3130 r = 1;
3131 break;
01643c51
KH		 3132 case KVM_CAP_SYNC_REGS:
3133 r = KVM_SYNC_X86_VALID_FIELDS;
3134 break;
e3fd9a93
PB		 3135 case KVM_CAP_ADJUST_CLOCK:
3136 r = KVM_CLOCK_TSC_STABLE;
3137 break;
4d5422ce 3138 case KVM_CAP_X86_DISABLE_EXITS:
b5170063
WL		 3139 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3140 KVM_X86_DISABLE_EXITS_CSTATE;
4d5422ce
WL		 3141 if(kvm_can_mwait_in_guest())
3142 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3143 break;
6d396b55
PB		 3144 case KVM_CAP_X86_SMM:
3145 /* SMBASE is usually relocated above 1M on modern chipsets,
3146 * and SMM handlers might indeed rely on 4G segment limits,
3147 * so do not report SMM to be available if real mode is
3148 * emulated via vm86 mode. Still, do not go to great lengths
3149 * to avoid userspace's usage of the feature, because it is a
3150 * fringe case that is not enabled except via specific settings
3151 * of the module parameters.
3152 */
bc226f07 3153 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3154 break;
774ead3a
AK		 3155 case KVM_CAP_VAPIC:
3156 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3157 break;
f725230a 3158 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3159 r = KVM_SOFT_MAX_VCPUS;
3160 break;
3161 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3162 r = KVM_MAX_VCPUS;
3163 break;
a86cb413
TH		 3164 case KVM_CAP_MAX_VCPU_ID:
3165 r = KVM_MAX_VCPU_ID;
3166 break;
a68a6a72
MT		 3167 case KVM_CAP_PV_MMU: /* obsolete */
3168 r = 0;
2f333bcb 3169 break;
890ca9ae
HY		 3170 case KVM_CAP_MCE:
3171 r = KVM_MAX_MCE_BANKS;
3172 break;
2d5b5a66 3173 case KVM_CAP_XCRS:
d366bf7e 3174 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3175 break;
92a1f12d
JR		 3176 case KVM_CAP_TSC_CONTROL:
3177 r = kvm_has_tsc_control;
3178 break;
37131313
RK		 3179 case KVM_CAP_X2APIC_API:
3180 r = KVM_X2APIC_API_VALID_FLAGS;
3181 break;
8fcc4b59
JM		 3182 case KVM_CAP_NESTED_STATE:
3183 r = kvm_x86_ops->get_nested_state ?
be43c440 3184 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3185 break;
018d00d2 3186 default:
018d00d2
ZX		 3187 break;
3188 }
3189 return r;
3190
3191}
3192
043405e1
CO		 3193long kvm_arch_dev_ioctl(struct file *filp,
3194 unsigned int ioctl, unsigned long arg)
3195{
3196 void __user *argp = (void __user *)arg;
3197 long r;
3198
3199 switch (ioctl) {
3200 case KVM_GET_MSR_INDEX_LIST: {
3201 struct kvm_msr_list __user *user_msr_list = argp;
3202 struct kvm_msr_list msr_list;
3203 unsigned n;
3204
3205 r = -EFAULT;
0e96f31e 3206 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3207 goto out;
3208 n = msr_list.nmsrs;
62ef68bb 3209 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3210 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3211 goto out;
3212 r = -E2BIG;
e125e7b6 3213 if (n < msr_list.nmsrs)
043405e1
CO		 3214 goto out;
3215 r = -EFAULT;
3216 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3217 num_msrs_to_save * sizeof(u32)))
3218 goto out;
e125e7b6 3219 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3220 &emulated_msrs,
62ef68bb 3221 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3222 goto out;
3223 r = 0;
3224 break;
3225 }
9c15bb1d
BP		 3226 case KVM_GET_SUPPORTED_CPUID:
3227 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3228 struct kvm_cpuid2 __user *cpuid_arg = argp;
3229 struct kvm_cpuid2 cpuid;
3230
3231 r = -EFAULT;
0e96f31e 3232 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3233 goto out;
9c15bb1d
BP		 3234
3235 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3236 ioctl);
674eea0f
AK		 3237 if (r)
3238 goto out;
3239
3240 r = -EFAULT;
0e96f31e 3241 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3242 goto out;
3243 r = 0;
3244 break;
3245 }
890ca9ae 3246 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3247 r = -EFAULT;
c45dcc71
AR		 3248 if (copy_to_user(argp, &kvm_mce_cap_supported,
3249 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3250 goto out;
3251 r = 0;
3252 break;
801e459a
TL		 3253 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3254 struct kvm_msr_list __user *user_msr_list = argp;
3255 struct kvm_msr_list msr_list;
3256 unsigned int n;
3257
3258 r = -EFAULT;
3259 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3260 goto out;
3261 n = msr_list.nmsrs;
3262 msr_list.nmsrs = num_msr_based_features;
3263 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3264 goto out;
3265 r = -E2BIG;
3266 if (n < msr_list.nmsrs)
3267 goto out;
3268 r = -EFAULT;
3269 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3270 num_msr_based_features * sizeof(u32)))
3271 goto out;
3272 r = 0;
3273 break;
3274 }
3275 case KVM_GET_MSRS:
3276 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3277 break;
890ca9ae 3278 }
043405e1
CO		 3279 default:
3280 r = -EINVAL;
3281 }
3282out:
3283 return r;
3284}
3285
f5f48ee1
SY		 3286static void wbinvd_ipi(void *garbage)
3287{
3288 wbinvd();
3289}
3290
3291static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3292{
e0f0bbc5 3293 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3294}
3295
313a3dc7
CO		 3296void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3297{
f5f48ee1
SY		 3298 /* Address WBINVD may be executed by guest */
3299 if (need_emulate_wbinvd(vcpu)) {
3300 if (kvm_x86_ops->has_wbinvd_exit())
3301 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3302 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3303 smp_call_function_single(vcpu->cpu,
3304 wbinvd_ipi, NULL, 1);
3305 }
3306
313a3dc7 3307 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3308
0dd6a6ed
ZA		 3309 /* Apply any externally detected TSC adjustments (due to suspend) */
3310 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3311 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3312 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3313 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3314 }
8f6055cb 3315
b0c39dc6 3316 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3317 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3318 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3319 if (tsc_delta < 0)
3320 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3321
b0c39dc6 3322 if (kvm_check_tsc_unstable()) {
07c1419a 3323 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3324 vcpu->arch.last_guest_tsc);
a545ab6a 3325 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3326 vcpu->arch.tsc_catchup = 1;
c285545f 3327 }
a749e247
PB		 3328
3329 if (kvm_lapic_hv_timer_in_use(vcpu))
3330 kvm_lapic_restart_hv_timer(vcpu);
3331
d98d07ca
MT		 3332 /*
3333 * On a host with synchronized TSC, there is no need to update
3334 * kvmclock on vcpu->cpu migration
3335 */
3336 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3337 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3338 if (vcpu->cpu != cpu)
1bd2009e 3339 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3340 vcpu->cpu = cpu;
6b7d7e76 3341 }
c9aaa895 3342
c9aaa895 3343 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3344}
3345
0b9f6c46
PX		 3346static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3347{
3348 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3349 return;
3350
fa55eedd 3351 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3352
4e335d9e 3353 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3354 &vcpu->arch.st.steal.preempted,
3355 offsetof(struct kvm_steal_time, preempted),
3356 sizeof(vcpu->arch.st.steal.preempted));
3357}
3358
313a3dc7
CO		 3359void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3360{
cc0d907c 3361 int idx;
de63ad4c
LM		 3362
3363 if (vcpu->preempted)
3364 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3365
931f261b
AA		 3366 /*
3367 * Disable page faults because we're in atomic context here.
3368 * kvm_write_guest_offset_cached() would call might_fault()
3369 * that relies on pagefault_disable() to tell if there's a
3370 * bug. NOTE: the write to guest memory may not go through if
3371 * during postcopy live migration or if there's heavy guest
3372 * paging.
3373 */
3374 pagefault_disable();
cc0d907c
AA		 3375 /*
3376 * kvm_memslots() will be called by
3377 * kvm_write_guest_offset_cached() so take the srcu lock.
3378 */
3379 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3380 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3381 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3382 pagefault_enable();
02daab21 3383 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3384 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3385 /*
f9dcf08e
RK		 3386 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3387 * on every vmexit, but if not, we might have a stale dr6 from the
3388 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3389 */
f9dcf08e 3390 set_debugreg(0, 6);
313a3dc7
CO		 3391}
3392
313a3dc7
CO		 3393static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3394 struct kvm_lapic_state *s)
3395{
fa59cc00 3396 if (vcpu->arch.apicv_active)
d62caabb
AS		 3397 kvm_x86_ops->sync_pir_to_irr(vcpu);
3398
a92e2543 3399 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3400}
3401
3402static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3403 struct kvm_lapic_state *s)
3404{
a92e2543
RK		 3405 int r;
3406
3407 r = kvm_apic_set_state(vcpu, s);
3408 if (r)
3409 return r;
cb142eb7 3410 update_cr8_intercept(vcpu);
313a3dc7
CO		 3411
3412 return 0;
3413}
3414
127a457a
MG		 3415static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3416{
3417 return (!lapic_in_kernel(vcpu) ||
3418 kvm_apic_accept_pic_intr(vcpu));
3419}
3420
782d422b
MG		 3421/*
3422 * if userspace requested an interrupt window, check that the
3423 * interrupt window is open.
3424 *
3425 * No need to exit to userspace if we already have an interrupt queued.
3426 */
3427static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3428{
3429 return kvm_arch_interrupt_allowed(vcpu) &&
3430 !kvm_cpu_has_interrupt(vcpu) &&
3431 !kvm_event_needs_reinjection(vcpu) &&
3432 kvm_cpu_accept_dm_intr(vcpu);
3433}
3434
f77bc6a4
ZX		 3435static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3436 struct kvm_interrupt *irq)
3437{
02cdb50f 3438 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3439 return -EINVAL;
1c1a9ce9
SR		 3440
3441 if (!irqchip_in_kernel(vcpu->kvm)) {
3442 kvm_queue_interrupt(vcpu, irq->irq, false);
3443 kvm_make_request(KVM_REQ_EVENT, vcpu);
3444 return 0;
3445 }
3446
3447 /*
3448 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3449 * fail for in-kernel 8259.
3450 */
3451 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3452 return -ENXIO;
f77bc6a4 3453
1c1a9ce9
SR		 3454 if (vcpu->arch.pending_external_vector != -1)
3455 return -EEXIST;
f77bc6a4 3456
1c1a9ce9 3457 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3458 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3459 return 0;
3460}
3461
c4abb7c9
JK		 3462static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3463{
c4abb7c9 3464 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3465
3466 return 0;
3467}
3468
f077825a
PB		 3469static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3470{
64d60670
PB		 3471 kvm_make_request(KVM_REQ_SMI, vcpu);
3472
f077825a
PB		 3473 return 0;
3474}
3475
b209749f
AK		 3476static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3477 struct kvm_tpr_access_ctl *tac)
3478{
3479 if (tac->flags)
3480 return -EINVAL;
3481 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3482 return 0;
3483}
3484
890ca9ae
HY		 3485static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3486 u64 mcg_cap)
3487{
3488 int r;
3489 unsigned bank_num = mcg_cap & 0xff, bank;
3490
3491 r = -EINVAL;
a9e38c3e 3492 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3493 goto out;
c45dcc71 3494 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3495 goto out;
3496 r = 0;
3497 vcpu->arch.mcg_cap = mcg_cap;
3498 /* Init IA32_MCG_CTL to all 1s */
3499 if (mcg_cap & MCG_CTL_P)
3500 vcpu->arch.mcg_ctl = ~(u64)0;
3501 /* Init IA32_MCi_CTL to all 1s */
3502 for (bank = 0; bank < bank_num; bank++)
3503 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3504
3505 if (kvm_x86_ops->setup_mce)
3506 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3507out:
3508 return r;
3509}
3510
3511static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3512 struct kvm_x86_mce *mce)
3513{
3514 u64 mcg_cap = vcpu->arch.mcg_cap;
3515 unsigned bank_num = mcg_cap & 0xff;
3516 u64 *banks = vcpu->arch.mce_banks;
3517
3518 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3519 return -EINVAL;
3520 /*
3521 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3522 * reporting is disabled
3523 */
3524 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3525 vcpu->arch.mcg_ctl != ~(u64)0)
3526 return 0;
3527 banks += 4 * mce->bank;
3528 /*
3529 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3530 * reporting is disabled for the bank
3531 */
3532 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3533 return 0;
3534 if (mce->status & MCI_STATUS_UC) {
3535 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3536 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3537 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3538 return 0;
3539 }
3540 if (banks[1] & MCI_STATUS_VAL)
3541 mce->status |= MCI_STATUS_OVER;
3542 banks[2] = mce->addr;
3543 banks[3] = mce->misc;
3544 vcpu->arch.mcg_status = mce->mcg_status;
3545 banks[1] = mce->status;
3546 kvm_queue_exception(vcpu, MC_VECTOR);
3547 } else if (!(banks[1] & MCI_STATUS_VAL)
3548 || !(banks[1] & MCI_STATUS_UC)) {
3549 if (banks[1] & MCI_STATUS_VAL)
3550 mce->status |= MCI_STATUS_OVER;
3551 banks[2] = mce->addr;
3552 banks[3] = mce->misc;
3553 banks[1] = mce->status;
3554 } else
3555 banks[1] |= MCI_STATUS_OVER;
3556 return 0;
3557}
3558
3cfc3092
JK		 3559static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3560 struct kvm_vcpu_events *events)
3561{
7460fb4a 3562 process_nmi(vcpu);
59073aaf 3563
664f8e26 3564 /*
59073aaf
JM		 3565 * The API doesn't provide the instruction length for software
3566 * exceptions, so don't report them. As long as the guest RIP
3567 * isn't advanced, we should expect to encounter the exception
3568 * again.
664f8e26 3569 */
59073aaf
JM		 3570 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3571 events->exception.injected = 0;
3572 events->exception.pending = 0;
3573 } else {
3574 events->exception.injected = vcpu->arch.exception.injected;
3575 events->exception.pending = vcpu->arch.exception.pending;
3576 /*
3577 * For ABI compatibility, deliberately conflate
3578 * pending and injected exceptions when
3579 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3580 */
3581 if (!vcpu->kvm->arch.exception_payload_enabled)
3582 events->exception.injected |=
3583 vcpu->arch.exception.pending;
3584 }
3cfc3092
JK		 3585 events->exception.nr = vcpu->arch.exception.nr;
3586 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3587 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3588 events->exception_has_payload = vcpu->arch.exception.has_payload;
3589 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3590
03b82a30 3591 events->interrupt.injected =
04140b41 3592 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3593 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3594 events->interrupt.soft = 0;
37ccdcbe 3595 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3596
3597 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3598 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3599 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3600 events->nmi.pad = 0;
3cfc3092 3601
66450a21 3602 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3603
f077825a
PB		 3604 events->smi.smm = is_smm(vcpu);
3605 events->smi.pending = vcpu->arch.smi_pending;
3606 events->smi.smm_inside_nmi =
3607 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3608 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3609
dab4b911 3610 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3611 | KVM_VCPUEVENT_VALID_SHADOW
3612 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3613 if (vcpu->kvm->arch.exception_payload_enabled)
3614 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3615
97e69aa6 3616 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3617}
3618
c5833c7a 3619static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3620
3cfc3092
JK		 3621static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3622 struct kvm_vcpu_events *events)
3623{
dab4b911 3624 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3625 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3626 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3627 | KVM_VCPUEVENT_VALID_SMM
3628 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3629 return -EINVAL;
3630
59073aaf
JM		 3631 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3632 if (!vcpu->kvm->arch.exception_payload_enabled)
3633 return -EINVAL;
3634 if (events->exception.pending)
3635 events->exception.injected = 0;
3636 else
3637 events->exception_has_payload = 0;
3638 } else {
3639 events->exception.pending = 0;
3640 events->exception_has_payload = 0;
3641 }
3642
3643 if ((events->exception.injected || events->exception.pending) &&
3644 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3645 return -EINVAL;
3646
28bf2888
DH		 3647 /* INITs are latched while in SMM */
3648 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3649 (events->smi.smm || events->smi.pending) &&
3650 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3651 return -EINVAL;
3652
7460fb4a 3653 process_nmi(vcpu);
59073aaf
JM		 3654 vcpu->arch.exception.injected = events->exception.injected;
3655 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3656 vcpu->arch.exception.nr = events->exception.nr;
3657 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3658 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3659 vcpu->arch.exception.has_payload = events->exception_has_payload;
3660 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3661
04140b41 3662 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3663 vcpu->arch.interrupt.nr = events->interrupt.nr;
3664 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3665 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3666 kvm_x86_ops->set_interrupt_shadow(vcpu,
3667 events->interrupt.shadow);
3cfc3092
JK		 3668
3669 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3670 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3671 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3672 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3673
66450a21 3674 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3675 lapic_in_kernel(vcpu))
66450a21 3676 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3677
f077825a 3678 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3679 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3680 if (events->smi.smm)
3681 vcpu->arch.hflags |= HF_SMM_MASK;
3682 else
3683 vcpu->arch.hflags &= ~HF_SMM_MASK;
3684 kvm_smm_changed(vcpu);
3685 }
6ef4e07e 3686
f077825a 3687 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3688
3689 if (events->smi.smm) {
3690 if (events->smi.smm_inside_nmi)
3691 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3692 else
f4ef1910
WL		 3693 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3694 if (lapic_in_kernel(vcpu)) {
3695 if (events->smi.latched_init)
3696 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3697 else
3698 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3699 }
f077825a
PB		 3700 }
3701 }
3702
3842d135
AK		 3703 kvm_make_request(KVM_REQ_EVENT, vcpu);
3704
3cfc3092
JK		 3705 return 0;
3706}
3707
a1efbe77
JK		 3708static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3709 struct kvm_debugregs *dbgregs)
3710{
73aaf249
JK		 3711 unsigned long val;
3712
a1efbe77 3713 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3714 kvm_get_dr(vcpu, 6, &val);
73aaf249 3715 dbgregs->dr6 = val;
a1efbe77
JK		 3716 dbgregs->dr7 = vcpu->arch.dr7;
3717 dbgregs->flags = 0;
97e69aa6 3718 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3719}
3720
3721static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3722 struct kvm_debugregs *dbgregs)
3723{
3724 if (dbgregs->flags)
3725 return -EINVAL;
3726
d14bdb55
PB		 3727 if (dbgregs->dr6 & ~0xffffffffull)
3728 return -EINVAL;
3729 if (dbgregs->dr7 & ~0xffffffffull)
3730 return -EINVAL;
3731
a1efbe77 3732 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3733 kvm_update_dr0123(vcpu);
a1efbe77 3734 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3735 kvm_update_dr6(vcpu);
a1efbe77 3736 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3737 kvm_update_dr7(vcpu);
a1efbe77 3738
a1efbe77
JK		 3739 return 0;
3740}
3741
df1daba7
PB		 3742#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3743
3744static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3745{
b666a4b6 3746 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3747 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3748 u64 valid;
3749
3750 /*
3751 * Copy legacy XSAVE area, to avoid complications with CPUID
3752 * leaves 0 and 1 in the loop below.
3753 */
3754 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3755
3756 /* Set XSTATE_BV */
00c87e9a 3757 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3758 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3759
3760 /*
3761 * Copy each region from the possibly compacted offset to the
3762 * non-compacted offset.
3763 */
d91cab78 3764 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3765 while (valid) {
abd16d68
SAS		 3766 u64 xfeature_mask = valid & -valid;
3767 int xfeature_nr = fls64(xfeature_mask) - 1;
3768 void *src = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3769
3770 if (src) {
3771 u32 size, offset, ecx, edx;
abd16d68 3772 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3773 &size, &offset, &ecx, &edx);
abd16d68 3774 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3775 memcpy(dest + offset, &vcpu->arch.pkru,
3776 sizeof(vcpu->arch.pkru));
3777 else
3778 memcpy(dest + offset, src, size);
3779
df1daba7
PB		 3780 }
3781
abd16d68 3782 valid -= xfeature_mask;
df1daba7
PB		 3783 }
3784}
3785
3786static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3787{
b666a4b6 3788 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3789 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3790 u64 valid;
3791
3792 /*
3793 * Copy legacy XSAVE area, to avoid complications with CPUID
3794 * leaves 0 and 1 in the loop below.
3795 */
3796 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3797
3798 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3799 xsave->header.xfeatures = xstate_bv;
782511b0 3800 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3801 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3802
3803 /*
3804 * Copy each region from the non-compacted offset to the
3805 * possibly compacted offset.
3806 */
d91cab78 3807 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3808 while (valid) {
abd16d68
SAS		 3809 u64 xfeature_mask = valid & -valid;
3810 int xfeature_nr = fls64(xfeature_mask) - 1;
3811 void *dest = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3812
3813 if (dest) {
3814 u32 size, offset, ecx, edx;
abd16d68 3815 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3816 &size, &offset, &ecx, &edx);
abd16d68 3817 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3818 memcpy(&vcpu->arch.pkru, src + offset,
3819 sizeof(vcpu->arch.pkru));
3820 else
3821 memcpy(dest, src + offset, size);
ee4100da 3822 }
df1daba7 3823
abd16d68 3824 valid -= xfeature_mask;
df1daba7
PB		 3825 }
3826}
3827
2d5b5a66
SY		 3828static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3829 struct kvm_xsave *guest_xsave)
3830{
d366bf7e 3831 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3832 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3833 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3834 } else {
2d5b5a66 3835 memcpy(guest_xsave->region,
b666a4b6 3836 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3837 sizeof(struct fxregs_state));
2d5b5a66 3838 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3839 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3840 }
3841}
3842
a575813b
WL		 3843#define XSAVE_MXCSR_OFFSET 24
3844
2d5b5a66
SY		 3845static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3846 struct kvm_xsave *guest_xsave)
3847{
3848 u64 xstate_bv =
3849 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3850 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3851
d366bf7e 3852 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3853 /*
3854 * Here we allow setting states that are not present in
3855 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3856 * with old userspace.
3857 */
a575813b
WL		 3858 if (xstate_bv & ~kvm_supported_xcr0() ||
3859 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3860 return -EINVAL;
df1daba7 3861 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3862 } else {
a575813b
WL		 3863 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3864 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3865 return -EINVAL;
b666a4b6 3866 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3867 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3868 }
3869 return 0;
3870}
3871
3872static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3873 struct kvm_xcrs *guest_xcrs)
3874{
d366bf7e 3875 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3876 guest_xcrs->nr_xcrs = 0;
3877 return;
3878 }
3879
3880 guest_xcrs->nr_xcrs = 1;
3881 guest_xcrs->flags = 0;
3882 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3883 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3884}
3885
3886static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3887 struct kvm_xcrs *guest_xcrs)
3888{
3889 int i, r = 0;
3890
d366bf7e 3891 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3892 return -EINVAL;
3893
3894 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3895 return -EINVAL;
3896
3897 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3898 /* Only support XCR0 currently */
c67a04cb 3899 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3900 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3901 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3902 break;
3903 }
3904 if (r)
3905 r = -EINVAL;
3906 return r;
3907}
3908
1c0b28c2
EM		 3909/*
3910 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3911 * stopped by the hypervisor. This function will be called from the host only.
3912 * EINVAL is returned when the host attempts to set the flag for a guest that
3913 * does not support pv clocks.
3914 */
3915static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3916{
0b79459b 3917 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3918 return -EINVAL;
51d59c6b 3919 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3920 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3921 return 0;
3922}
3923
5c919412
AS		 3924static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3925 struct kvm_enable_cap *cap)
3926{
57b119da
VK		 3927 int r;
3928 uint16_t vmcs_version;
3929 void __user *user_ptr;
3930
5c919412
AS		 3931 if (cap->flags)
3932 return -EINVAL;
3933
3934 switch (cap->cap) {
efc479e6
RK		 3935 case KVM_CAP_HYPERV_SYNIC2:
3936 if (cap->args[0])
3937 return -EINVAL;
b2869f28
GS		 3938 /* fall through */
3939
5c919412 3940 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3941 if (!irqchip_in_kernel(vcpu->kvm))
3942 return -EINVAL;
efc479e6
RK		 3943 return kvm_hv_activate_synic(vcpu, cap->cap ==
3944 KVM_CAP_HYPERV_SYNIC2);
57b119da 3945 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 3946 if (!kvm_x86_ops->nested_enable_evmcs)
3947 return -ENOTTY;
57b119da
VK		 3948 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3949 if (!r) {
3950 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3951 if (copy_to_user(user_ptr, &vmcs_version,
3952 sizeof(vmcs_version)))
3953 r = -EFAULT;
3954 }
3955 return r;
3956
5c919412
AS		 3957 default:
3958 return -EINVAL;
3959 }
3960}
3961
313a3dc7
CO		 3962long kvm_arch_vcpu_ioctl(struct file *filp,
3963 unsigned int ioctl, unsigned long arg)
3964{
3965 struct kvm_vcpu *vcpu = filp->private_data;
3966 void __user *argp = (void __user *)arg;
3967 int r;
d1ac91d8
AK		 3968 union {
3969 struct kvm_lapic_state *lapic;
3970 struct kvm_xsave *xsave;
3971 struct kvm_xcrs *xcrs;
3972 void *buffer;
3973 } u;
3974
9b062471
CD		 3975 vcpu_load(vcpu);
3976
d1ac91d8 3977 u.buffer = NULL;
313a3dc7
CO		 3978 switch (ioctl) {
3979 case KVM_GET_LAPIC: {
2204ae3c 3980 r = -EINVAL;
bce87cce 3981 if (!lapic_in_kernel(vcpu))
2204ae3c 3982 goto out;
254272ce
BG		 3983 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
3984 GFP_KERNEL_ACCOUNT);
313a3dc7 3985
b772ff36 3986 r = -ENOMEM;
d1ac91d8 3987 if (!u.lapic)
b772ff36 3988 goto out;
d1ac91d8 3989 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3990 if (r)
3991 goto out;
3992 r = -EFAULT;
d1ac91d8 3993 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3994 goto out;
3995 r = 0;
3996 break;
3997 }
3998 case KVM_SET_LAPIC: {
2204ae3c 3999 r = -EINVAL;
bce87cce 4000 if (!lapic_in_kernel(vcpu))
2204ae3c 4001 goto out;
ff5c2c03 4002 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 4003 if (IS_ERR(u.lapic)) {
4004 r = PTR_ERR(u.lapic);
4005 goto out_nofree;
4006 }
ff5c2c03 4007
d1ac91d8 4008 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 4009 break;
4010 }
f77bc6a4
ZX		 4011 case KVM_INTERRUPT: {
4012 struct kvm_interrupt irq;
4013
4014 r = -EFAULT;
0e96f31e 4015 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 4016 goto out;
4017 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 4018 break;
4019 }
c4abb7c9
JK		 4020 case KVM_NMI: {
4021 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 4022 break;
4023 }
f077825a
PB		 4024 case KVM_SMI: {
4025 r = kvm_vcpu_ioctl_smi(vcpu);
4026 break;
4027 }
313a3dc7
CO		 4028 case KVM_SET_CPUID: {
4029 struct kvm_cpuid __user *cpuid_arg = argp;
4030 struct kvm_cpuid cpuid;
4031
4032 r = -EFAULT;
0e96f31e 4033 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 4034 goto out;
4035 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 4036 break;
4037 }
07716717
DK		 4038 case KVM_SET_CPUID2: {
4039 struct kvm_cpuid2 __user *cpuid_arg = argp;
4040 struct kvm_cpuid2 cpuid;
4041
4042 r = -EFAULT;
0e96f31e 4043 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4044 goto out;
4045 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 4046 cpuid_arg->entries);
07716717
DK		 4047 break;
4048 }
4049 case KVM_GET_CPUID2: {
4050 struct kvm_cpuid2 __user *cpuid_arg = argp;
4051 struct kvm_cpuid2 cpuid;
4052
4053 r = -EFAULT;
0e96f31e 4054 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4055 goto out;
4056 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 4057 cpuid_arg->entries);
07716717
DK		 4058 if (r)
4059 goto out;
4060 r = -EFAULT;
0e96f31e 4061 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 4062 goto out;
4063 r = 0;
4064 break;
4065 }
801e459a
TL		 4066 case KVM_GET_MSRS: {
4067 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 4068 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 4069 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4070 break;
801e459a
TL		 4071 }
4072 case KVM_SET_MSRS: {
4073 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 4074 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 4075 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4076 break;
801e459a 4077 }
b209749f
AK		 4078 case KVM_TPR_ACCESS_REPORTING: {
4079 struct kvm_tpr_access_ctl tac;
4080
4081 r = -EFAULT;
0e96f31e 4082 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 4083 goto out;
4084 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4085 if (r)
4086 goto out;
4087 r = -EFAULT;
0e96f31e 4088 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4089 goto out;
4090 r = 0;
4091 break;
4092 };
b93463aa
AK		 4093 case KVM_SET_VAPIC_ADDR: {
4094 struct kvm_vapic_addr va;
7301d6ab 4095 int idx;
b93463aa
AK		 4096
4097 r = -EINVAL;
35754c98 4098 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4099 goto out;
4100 r = -EFAULT;
0e96f31e 4101 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4102 goto out;
7301d6ab 4103 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4104 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4105 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4106 break;
4107 }
890ca9ae
HY		 4108 case KVM_X86_SETUP_MCE: {
4109 u64 mcg_cap;
4110
4111 r = -EFAULT;
0e96f31e 4112 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4113 goto out;
4114 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4115 break;
4116 }
4117 case KVM_X86_SET_MCE: {
4118 struct kvm_x86_mce mce;
4119
4120 r = -EFAULT;
0e96f31e 4121 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4122 goto out;
4123 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4124 break;
4125 }
3cfc3092
JK		 4126 case KVM_GET_VCPU_EVENTS: {
4127 struct kvm_vcpu_events events;
4128
4129 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4130
4131 r = -EFAULT;
4132 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4133 break;
4134 r = 0;
4135 break;
4136 }
4137 case KVM_SET_VCPU_EVENTS: {
4138 struct kvm_vcpu_events events;
4139
4140 r = -EFAULT;
4141 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4142 break;
4143
4144 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4145 break;
4146 }
a1efbe77
JK		 4147 case KVM_GET_DEBUGREGS: {
4148 struct kvm_debugregs dbgregs;
4149
4150 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4151
4152 r = -EFAULT;
4153 if (copy_to_user(argp, &dbgregs,
4154 sizeof(struct kvm_debugregs)))
4155 break;
4156 r = 0;
4157 break;
4158 }
4159 case KVM_SET_DEBUGREGS: {
4160 struct kvm_debugregs dbgregs;
4161
4162 r = -EFAULT;
4163 if (copy_from_user(&dbgregs, argp,
4164 sizeof(struct kvm_debugregs)))
4165 break;
4166
4167 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4168 break;
4169 }
2d5b5a66 4170 case KVM_GET_XSAVE: {
254272ce 4171 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4172 r = -ENOMEM;
d1ac91d8 4173 if (!u.xsave)
2d5b5a66
SY		 4174 break;
4175
d1ac91d8 4176 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4177
4178 r = -EFAULT;
d1ac91d8 4179 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4180 break;
4181 r = 0;
4182 break;
4183 }
4184 case KVM_SET_XSAVE: {
ff5c2c03 4185 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4186 if (IS_ERR(u.xsave)) {
4187 r = PTR_ERR(u.xsave);
4188 goto out_nofree;
4189 }
2d5b5a66 4190
d1ac91d8 4191 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4192 break;
4193 }
4194 case KVM_GET_XCRS: {
254272ce 4195 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4196 r = -ENOMEM;
d1ac91d8 4197 if (!u.xcrs)
2d5b5a66
SY		 4198 break;
4199
d1ac91d8 4200 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4201
4202 r = -EFAULT;
d1ac91d8 4203 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4204 sizeof(struct kvm_xcrs)))
4205 break;
4206 r = 0;
4207 break;
4208 }
4209 case KVM_SET_XCRS: {
ff5c2c03 4210 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4211 if (IS_ERR(u.xcrs)) {
4212 r = PTR_ERR(u.xcrs);
4213 goto out_nofree;
4214 }
2d5b5a66 4215
d1ac91d8 4216 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4217 break;
4218 }
92a1f12d
JR		 4219 case KVM_SET_TSC_KHZ: {
4220 u32 user_tsc_khz;
4221
4222 r = -EINVAL;
92a1f12d
JR		 4223 user_tsc_khz = (u32)arg;
4224
4225 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4226 goto out;
4227
cc578287
ZA		 4228 if (user_tsc_khz == 0)
4229 user_tsc_khz = tsc_khz;
4230
381d585c
HZ		 4231 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4232 r = 0;
92a1f12d 4233
92a1f12d
JR		 4234 goto out;
4235 }
4236 case KVM_GET_TSC_KHZ: {
cc578287 4237 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4238 goto out;
4239 }
1c0b28c2
EM		 4240 case KVM_KVMCLOCK_CTRL: {
4241 r = kvm_set_guest_paused(vcpu);
4242 goto out;
4243 }
5c919412
AS		 4244 case KVM_ENABLE_CAP: {
4245 struct kvm_enable_cap cap;
4246
4247 r = -EFAULT;
4248 if (copy_from_user(&cap, argp, sizeof(cap)))
4249 goto out;
4250 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4251 break;
4252 }
8fcc4b59
JM		 4253 case KVM_GET_NESTED_STATE: {
4254 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4255 u32 user_data_size;
4256
4257 r = -EINVAL;
4258 if (!kvm_x86_ops->get_nested_state)
4259 break;
4260
4261 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4262 r = -EFAULT;
8fcc4b59 4263 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4264 break;
8fcc4b59
JM		 4265
4266 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4267 user_data_size);
4268 if (r < 0)
26b471c7 4269 break;
8fcc4b59
JM		 4270
4271 if (r > user_data_size) {
4272 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4273 r = -EFAULT;
4274 else
4275 r = -E2BIG;
4276 break;
8fcc4b59 4277 }
26b471c7 4278
8fcc4b59
JM		 4279 r = 0;
4280 break;
4281 }
4282 case KVM_SET_NESTED_STATE: {
4283 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4284 struct kvm_nested_state kvm_state;
4285
4286 r = -EINVAL;
4287 if (!kvm_x86_ops->set_nested_state)
4288 break;
4289
26b471c7 4290 r = -EFAULT;
8fcc4b59 4291 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4292 break;
8fcc4b59 4293
26b471c7 4294 r = -EINVAL;
8fcc4b59 4295 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4296 break;
8fcc4b59
JM		 4297
4298 if (kvm_state.flags &
8cab6507
VK		 4299 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4300 | KVM_STATE_NESTED_EVMCS))
26b471c7 4301 break;
8fcc4b59
JM		 4302
4303 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4304 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4305 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4306 break;
8fcc4b59
JM		 4307
4308 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4309 break;
4310 }
2bc39970
VK		 4311 case KVM_GET_SUPPORTED_HV_CPUID: {
4312 struct kvm_cpuid2 __user *cpuid_arg = argp;
4313 struct kvm_cpuid2 cpuid;
4314
4315 r = -EFAULT;
4316 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4317 goto out;
4318
4319 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4320 cpuid_arg->entries);
4321 if (r)
4322 goto out;
4323
4324 r = -EFAULT;
4325 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4326 goto out;
4327 r = 0;
4328 break;
4329 }
313a3dc7
CO		 4330 default:
4331 r = -EINVAL;
4332 }
4333out:
d1ac91d8 4334 kfree(u.buffer);
9b062471
CD		 4335out_nofree:
4336 vcpu_put(vcpu);
313a3dc7
CO		 4337 return r;
4338}
4339
1499fa80 4340vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4341{
4342 return VM_FAULT_SIGBUS;
4343}
4344
1fe779f8
CO		 4345static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4346{
4347 int ret;
4348
4349 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4350 return -EINVAL;
1fe779f8
CO		 4351 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4352 return ret;
4353}
4354
b927a3ce
SY		 4355static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4356 u64 ident_addr)
4357{
2ac52ab8 4358 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4359}
4360
1fe779f8 4361static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4362 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4363{
4364 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4365 return -EINVAL;
4366
79fac95e 4367 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4368
4369 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4370 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4371
79fac95e 4372 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4373 return 0;
4374}
4375
bc8a3d89 4376static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4377{
39de71ec 4378 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4379}
4380
1fe779f8
CO		 4381static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4382{
90bca052 4383 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4384 int r;
4385
4386 r = 0;
4387 switch (chip->chip_id) {
4388 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4389 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4390 sizeof(struct kvm_pic_state));
4391 break;
4392 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4393 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4394 sizeof(struct kvm_pic_state));
4395 break;
4396 case KVM_IRQCHIP_IOAPIC:
33392b49 4397 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4398 break;
4399 default:
4400 r = -EINVAL;
4401 break;
4402 }
4403 return r;
4404}
4405
4406static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4407{
90bca052 4408 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4409 int r;
4410
4411 r = 0;
4412 switch (chip->chip_id) {
4413 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4414 spin_lock(&pic->lock);
4415 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4416 sizeof(struct kvm_pic_state));
90bca052 4417 spin_unlock(&pic->lock);
1fe779f8
CO		 4418 break;
4419 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4420 spin_lock(&pic->lock);
4421 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4422 sizeof(struct kvm_pic_state));
90bca052 4423 spin_unlock(&pic->lock);
1fe779f8
CO		 4424 break;
4425 case KVM_IRQCHIP_IOAPIC:
33392b49 4426 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4427 break;
4428 default:
4429 r = -EINVAL;
4430 break;
4431 }
90bca052 4432 kvm_pic_update_irq(pic);
1fe779f8
CO		 4433 return r;
4434}
4435
e0f63cb9
SY		 4436static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4437{
34f3941c
RK		 4438 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4439
4440 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4441
4442 mutex_lock(&kps->lock);
4443 memcpy(ps, &kps->channels, sizeof(*ps));
4444 mutex_unlock(&kps->lock);
2da29bcc 4445 return 0;
e0f63cb9
SY		 4446}
4447
4448static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4449{
0185604c 4450 int i;
09edea72
RK		 4451 struct kvm_pit *pit = kvm->arch.vpit;
4452
4453 mutex_lock(&pit->pit_state.lock);
34f3941c 4454 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4455 for (i = 0; i < 3; i++)
09edea72
RK		 4456 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4457 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4458 return 0;
e9f42757
BK		 4459}
4460
4461static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4462{
e9f42757
BK		 4463 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4464 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4465 sizeof(ps->channels));
4466 ps->flags = kvm->arch.vpit->pit_state.flags;
4467 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4468 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4469 return 0;
e9f42757
BK		 4470}
4471
4472static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4473{
2da29bcc 4474 int start = 0;
0185604c 4475 int i;
e9f42757 4476 u32 prev_legacy, cur_legacy;
09edea72
RK		 4477 struct kvm_pit *pit = kvm->arch.vpit;
4478
4479 mutex_lock(&pit->pit_state.lock);
4480 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4481 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4482 if (!prev_legacy && cur_legacy)
4483 start = 1;
09edea72
RK		 4484 memcpy(&pit->pit_state.channels, &ps->channels,
4485 sizeof(pit->pit_state.channels));
4486 pit->pit_state.flags = ps->flags;
0185604c 4487 for (i = 0; i < 3; i++)
09edea72 4488 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4489 start && i == 0);
09edea72 4490 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4491 return 0;
e0f63cb9
SY		 4492}
4493
52d939a0
MT		 4494static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4495 struct kvm_reinject_control *control)
4496{
71474e2f
RK		 4497 struct kvm_pit *pit = kvm->arch.vpit;
4498
4499 if (!pit)
52d939a0 4500 return -ENXIO;
b39c90b6 4501
71474e2f
RK		 4502 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4503 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4504 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4505 */
4506 mutex_lock(&pit->pit_state.lock);
4507 kvm_pit_set_reinject(pit, control->pit_reinject);
4508 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4509
52d939a0
MT		 4510 return 0;
4511}
4512
95d4c16c 4513/**
60c34612
TY		 4514 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4515 * @kvm: kvm instance
4516 * @log: slot id and address to which we copy the log
95d4c16c 4517 *
e108ff2f
PB		 4518 * Steps 1-4 below provide general overview of dirty page logging. See
4519 * kvm_get_dirty_log_protect() function description for additional details.
4520 *
4521 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4522 * always flush the TLB (step 4) even if previous step failed and the dirty
4523 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4524 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4525 * writes will be marked dirty for next log read.
95d4c16c 4526 *
60c34612
TY		 4527 * 1. Take a snapshot of the bit and clear it if needed.
4528 * 2. Write protect the corresponding page.
e108ff2f
PB		 4529 * 3. Copy the snapshot to the userspace.
4530 * 4. Flush TLB's if needed.
5bb064dc 4531 */
60c34612 4532int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4533{
8fe65a82 4534 bool flush = false;
e108ff2f 4535 int r;
5bb064dc 4536
79fac95e 4537 mutex_lock(&kvm->slots_lock);
5bb064dc 4538
88178fd4
KH		 4539 /*
4540 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4541 */
4542 if (kvm_x86_ops->flush_log_dirty)
4543 kvm_x86_ops->flush_log_dirty(kvm);
4544
8fe65a82 4545 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4546
4547 /*
4548 * All the TLBs can be flushed out of mmu lock, see the comments in
4549 * kvm_mmu_slot_remove_write_access().
4550 */
e108ff2f 4551 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4552 if (flush)
2a31b9db
PB		 4553 kvm_flush_remote_tlbs(kvm);
4554
4555 mutex_unlock(&kvm->slots_lock);
4556 return r;
4557}
4558
4559int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4560{
4561 bool flush = false;
4562 int r;
4563
4564 mutex_lock(&kvm->slots_lock);
4565
4566 /*
4567 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4568 */
4569 if (kvm_x86_ops->flush_log_dirty)
4570 kvm_x86_ops->flush_log_dirty(kvm);
4571
4572 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4573
4574 /*
4575 * All the TLBs can be flushed out of mmu lock, see the comments in
4576 * kvm_mmu_slot_remove_write_access().
4577 */
4578 lockdep_assert_held(&kvm->slots_lock);
4579 if (flush)
198c74f4
XG		 4580 kvm_flush_remote_tlbs(kvm);
4581
79fac95e 4582 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4583 return r;
4584}
4585
aa2fbe6d
YZ		 4586int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4587 bool line_status)
23d43cf9
CD		 4588{
4589 if (!irqchip_in_kernel(kvm))
4590 return -ENXIO;
4591
4592 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4593 irq_event->irq, irq_event->level,
4594 line_status);
23d43cf9
CD		 4595 return 0;
4596}
4597
e5d83c74
PB		 4598int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4599 struct kvm_enable_cap *cap)
90de4a18
NA		 4600{
4601 int r;
4602
4603 if (cap->flags)
4604 return -EINVAL;
4605
4606 switch (cap->cap) {
4607 case KVM_CAP_DISABLE_QUIRKS:
4608 kvm->arch.disabled_quirks = cap->args[0];
4609 r = 0;
4610 break;
49df6397
SR		 4611 case KVM_CAP_SPLIT_IRQCHIP: {
4612 mutex_lock(&kvm->lock);
b053b2ae
SR		 4613 r = -EINVAL;
4614 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4615 goto split_irqchip_unlock;
49df6397
SR		 4616 r = -EEXIST;
4617 if (irqchip_in_kernel(kvm))
4618 goto split_irqchip_unlock;
557abc40 4619 if (kvm->created_vcpus)
49df6397
SR		 4620 goto split_irqchip_unlock;
4621 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4622 if (r)
49df6397
SR		 4623 goto split_irqchip_unlock;
4624 /* Pairs with irqchip_in_kernel. */
4625 smp_wmb();
49776faf 4626 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4627 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4628 r = 0;
4629split_irqchip_unlock:
4630 mutex_unlock(&kvm->lock);
4631 break;
4632 }
37131313
RK		 4633 case KVM_CAP_X2APIC_API:
4634 r = -EINVAL;
4635 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4636 break;
4637
4638 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4639 kvm->arch.x2apic_format = true;
c519265f
RK		 4640 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4641 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4642
4643 r = 0;
4644 break;
4d5422ce
WL		 4645 case KVM_CAP_X86_DISABLE_EXITS:
4646 r = -EINVAL;
4647 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4648 break;
4649
4650 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4651 kvm_can_mwait_in_guest())
4652 kvm->arch.mwait_in_guest = true;
766d3571 4653 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4654 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4655 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4656 kvm->arch.pause_in_guest = true;
b5170063
WL		 4657 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4658 kvm->arch.cstate_in_guest = true;
4d5422ce
WL		 4659 r = 0;
4660 break;
6fbbde9a
DS		 4661 case KVM_CAP_MSR_PLATFORM_INFO:
4662 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4663 r = 0;
c4f55198
JM		 4664 break;
4665 case KVM_CAP_EXCEPTION_PAYLOAD:
4666 kvm->arch.exception_payload_enabled = cap->args[0];
4667 r = 0;
6fbbde9a 4668 break;
90de4a18
NA		 4669 default:
4670 r = -EINVAL;
4671 break;
4672 }
4673 return r;
4674}
4675
1fe779f8
CO		 4676long kvm_arch_vm_ioctl(struct file *filp,
4677 unsigned int ioctl, unsigned long arg)
4678{
4679 struct kvm *kvm = filp->private_data;
4680 void __user *argp = (void __user *)arg;
367e1319 4681 int r = -ENOTTY;
f0d66275
DH		 4682 /*
4683 * This union makes it completely explicit to gcc-3.x
4684 * that these two variables' stack usage should be
4685 * combined, not added together.
4686 */
4687 union {
4688 struct kvm_pit_state ps;
e9f42757 4689 struct kvm_pit_state2 ps2;
c5ff41ce 4690 struct kvm_pit_config pit_config;
f0d66275 4691 } u;
1fe779f8
CO		 4692
4693 switch (ioctl) {
4694 case KVM_SET_TSS_ADDR:
4695 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4696 break;
b927a3ce
SY		 4697 case KVM_SET_IDENTITY_MAP_ADDR: {
4698 u64 ident_addr;
4699
1af1ac91
DH		 4700 mutex_lock(&kvm->lock);
4701 r = -EINVAL;
4702 if (kvm->created_vcpus)
4703 goto set_identity_unlock;
b927a3ce 4704 r = -EFAULT;
0e96f31e 4705 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4706 goto set_identity_unlock;
b927a3ce 4707 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4708set_identity_unlock:
4709 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4710 break;
4711 }
1fe779f8
CO		 4712 case KVM_SET_NR_MMU_PAGES:
4713 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4714 break;
4715 case KVM_GET_NR_MMU_PAGES:
4716 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4717 break;
3ddea128 4718 case KVM_CREATE_IRQCHIP: {
3ddea128 4719 mutex_lock(&kvm->lock);
09941366 4720
3ddea128 4721 r = -EEXIST;
35e6eaa3 4722 if (irqchip_in_kernel(kvm))
3ddea128 4723 goto create_irqchip_unlock;
09941366 4724
3e515705 4725 r = -EINVAL;
557abc40 4726 if (kvm->created_vcpus)
3e515705 4727 goto create_irqchip_unlock;
09941366
RK		 4728
4729 r = kvm_pic_init(kvm);
4730 if (r)
3ddea128 4731 goto create_irqchip_unlock;
09941366
RK		 4732
4733 r = kvm_ioapic_init(kvm);
4734 if (r) {
09941366 4735 kvm_pic_destroy(kvm);
3ddea128 4736 goto create_irqchip_unlock;
09941366
RK		 4737 }
4738
399ec807
AK		 4739 r = kvm_setup_default_irq_routing(kvm);
4740 if (r) {
72bb2fcd 4741 kvm_ioapic_destroy(kvm);
09941366 4742 kvm_pic_destroy(kvm);
71ba994c 4743 goto create_irqchip_unlock;
399ec807 4744 }
49776faf 4745 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4746 smp_wmb();
49776faf 4747 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4748 create_irqchip_unlock:
4749 mutex_unlock(&kvm->lock);
1fe779f8 4750 break;
3ddea128 4751 }
7837699f 4752 case KVM_CREATE_PIT:
c5ff41ce
JK		 4753 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4754 goto create_pit;
4755 case KVM_CREATE_PIT2:
4756 r = -EFAULT;
4757 if (copy_from_user(&u.pit_config, argp,
4758 sizeof(struct kvm_pit_config)))
4759 goto out;
4760 create_pit:
250715a6 4761 mutex_lock(&kvm->lock);
269e05e4
AK		 4762 r = -EEXIST;
4763 if (kvm->arch.vpit)
4764 goto create_pit_unlock;
7837699f 4765 r = -ENOMEM;
c5ff41ce 4766 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4767 if (kvm->arch.vpit)
4768 r = 0;
269e05e4 4769 create_pit_unlock:
250715a6 4770 mutex_unlock(&kvm->lock);
7837699f 4771 break;
1fe779f8
CO		 4772 case KVM_GET_IRQCHIP: {
4773 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4774 struct kvm_irqchip *chip;
1fe779f8 4775
ff5c2c03
SL		 4776 chip = memdup_user(argp, sizeof(*chip));
4777 if (IS_ERR(chip)) {
4778 r = PTR_ERR(chip);
1fe779f8 4779 goto out;
ff5c2c03
SL		 4780 }
4781
1fe779f8 4782 r = -ENXIO;
826da321 4783 if (!irqchip_kernel(kvm))
f0d66275
DH		 4784 goto get_irqchip_out;
4785 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4786 if (r)
f0d66275 4787 goto get_irqchip_out;
1fe779f8 4788 r = -EFAULT;
0e96f31e 4789 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4790 goto get_irqchip_out;
1fe779f8 4791 r = 0;
f0d66275
DH		 4792 get_irqchip_out:
4793 kfree(chip);
1fe779f8
CO		 4794 break;
4795 }
4796 case KVM_SET_IRQCHIP: {
4797 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4798 struct kvm_irqchip *chip;
1fe779f8 4799
ff5c2c03
SL		 4800 chip = memdup_user(argp, sizeof(*chip));
4801 if (IS_ERR(chip)) {
4802 r = PTR_ERR(chip);
1fe779f8 4803 goto out;
ff5c2c03
SL		 4804 }
4805
1fe779f8 4806 r = -ENXIO;
826da321 4807 if (!irqchip_kernel(kvm))
f0d66275
DH		 4808 goto set_irqchip_out;
4809 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4810 if (r)
f0d66275 4811 goto set_irqchip_out;
1fe779f8 4812 r = 0;
f0d66275
DH		 4813 set_irqchip_out:
4814 kfree(chip);
1fe779f8
CO		 4815 break;
4816 }
e0f63cb9 4817 case KVM_GET_PIT: {
e0f63cb9 4818 r = -EFAULT;
f0d66275 4819 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4820 goto out;
4821 r = -ENXIO;
4822 if (!kvm->arch.vpit)
4823 goto out;
f0d66275 4824 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4825 if (r)
4826 goto out;
4827 r = -EFAULT;
f0d66275 4828 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4829 goto out;
4830 r = 0;
4831 break;
4832 }
4833 case KVM_SET_PIT: {
e0f63cb9 4834 r = -EFAULT;
0e96f31e 4835 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4836 goto out;
4837 r = -ENXIO;
4838 if (!kvm->arch.vpit)
4839 goto out;
f0d66275 4840 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4841 break;
4842 }
e9f42757
BK		 4843 case KVM_GET_PIT2: {
4844 r = -ENXIO;
4845 if (!kvm->arch.vpit)
4846 goto out;
4847 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4848 if (r)
4849 goto out;
4850 r = -EFAULT;
4851 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4852 goto out;
4853 r = 0;
4854 break;
4855 }
4856 case KVM_SET_PIT2: {
4857 r = -EFAULT;
4858 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4859 goto out;
4860 r = -ENXIO;
4861 if (!kvm->arch.vpit)
4862 goto out;
4863 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4864 break;
4865 }
52d939a0
MT		 4866 case KVM_REINJECT_CONTROL: {
4867 struct kvm_reinject_control control;
4868 r = -EFAULT;
4869 if (copy_from_user(&control, argp, sizeof(control)))
4870 goto out;
4871 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4872 break;
4873 }
d71ba788
PB		 4874 case KVM_SET_BOOT_CPU_ID:
4875 r = 0;
4876 mutex_lock(&kvm->lock);
557abc40 4877 if (kvm->created_vcpus)
d71ba788
PB		 4878 r = -EBUSY;
4879 else
4880 kvm->arch.bsp_vcpu_id = arg;
4881 mutex_unlock(&kvm->lock);
4882 break;
ffde22ac 4883 case KVM_XEN_HVM_CONFIG: {
51776043 4884 struct kvm_xen_hvm_config xhc;
ffde22ac 4885 r = -EFAULT;
51776043 4886 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4887 goto out;
4888 r = -EINVAL;
51776043 4889 if (xhc.flags)
ffde22ac 4890 goto out;
51776043 4891 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4892 r = 0;
4893 break;
4894 }
afbcf7ab 4895 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4896 struct kvm_clock_data user_ns;
4897 u64 now_ns;
afbcf7ab
GC		 4898
4899 r = -EFAULT;
4900 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4901 goto out;
4902
4903 r = -EINVAL;
4904 if (user_ns.flags)
4905 goto out;
4906
4907 r = 0;
0bc48bea
RK		 4908 /*
4909 * TODO: userspace has to take care of races with VCPU_RUN, so
4910 * kvm_gen_update_masterclock() can be cut down to locked
4911 * pvclock_update_vm_gtod_copy().
4912 */
4913 kvm_gen_update_masterclock(kvm);
e891a32e 4914 now_ns = get_kvmclock_ns(kvm);
108b249c 4915 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4916 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4917 break;
4918 }
4919 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4920 struct kvm_clock_data user_ns;
4921 u64 now_ns;
4922
e891a32e 4923 now_ns = get_kvmclock_ns(kvm);
108b249c 4924 user_ns.clock = now_ns;
e3fd9a93 4925 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4926 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4927
4928 r = -EFAULT;
4929 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4930 goto out;
4931 r = 0;
4932 break;
4933 }
5acc5c06
BS		 4934 case KVM_MEMORY_ENCRYPT_OP: {
4935 r = -ENOTTY;
4936 if (kvm_x86_ops->mem_enc_op)
4937 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4938 break;
4939 }
69eaedee
BS		 4940 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4941 struct kvm_enc_region region;
4942
4943 r = -EFAULT;
4944 if (copy_from_user(&region, argp, sizeof(region)))
4945 goto out;
4946
4947 r = -ENOTTY;
4948 if (kvm_x86_ops->mem_enc_reg_region)
4949 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4950 break;
4951 }
4952 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4953 struct kvm_enc_region region;
4954
4955 r = -EFAULT;
4956 if (copy_from_user(&region, argp, sizeof(region)))
4957 goto out;
4958
4959 r = -ENOTTY;
4960 if (kvm_x86_ops->mem_enc_unreg_region)
4961 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4962 break;
4963 }
faeb7833
RK		 4964 case KVM_HYPERV_EVENTFD: {
4965 struct kvm_hyperv_eventfd hvevfd;
4966
4967 r = -EFAULT;
4968 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4969 goto out;
4970 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4971 break;
4972 }
66bb8a06
EH		 4973 case KVM_SET_PMU_EVENT_FILTER:
4974 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
4975 break;
1fe779f8 4976 default:
ad6260da 4977 r = -ENOTTY;
1fe779f8
CO		 4978 }
4979out:
4980 return r;
4981}
4982
a16b043c 4983static void kvm_init_msr_list(void)
043405e1
CO		 4984{
4985 u32 dummy[2];
4986 unsigned i, j;
4987
62ef68bb 4988 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4989 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4990 continue;
93c4adc7
PB		 4991
4992 /*
4993 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4994 * to the guests in some cases.
93c4adc7
PB		 4995 */
4996 switch (msrs_to_save[i]) {
4997 case MSR_IA32_BNDCFGS:
503234b3 4998 if (!kvm_mpx_supported())
93c4adc7
PB		 4999 continue;
5000 break;
9dbe6cf9
PB		 5001 case MSR_TSC_AUX:
5002 if (!kvm_x86_ops->rdtscp_supported())
5003 continue;
5004 break;
bf8c55d8
CP		 5005 case MSR_IA32_RTIT_CTL:
5006 case MSR_IA32_RTIT_STATUS:
5007 if (!kvm_x86_ops->pt_supported())
5008 continue;
5009 break;
5010 case MSR_IA32_RTIT_CR3_MATCH:
5011 if (!kvm_x86_ops->pt_supported() ||
5012 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5013 continue;
5014 break;
5015 case MSR_IA32_RTIT_OUTPUT_BASE:
5016 case MSR_IA32_RTIT_OUTPUT_MASK:
5017 if (!kvm_x86_ops->pt_supported() ||
5018 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5019 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5020 continue;
5021 break;
5022 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5023 if (!kvm_x86_ops->pt_supported() ||
5024 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5025 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5026 continue;
5027 break;
5028 }
93c4adc7
PB		 5029 default:
5030 break;
5031 }
5032
043405e1
CO		 5033 if (j < i)
5034 msrs_to_save[j] = msrs_to_save[i];
5035 j++;
5036 }
5037 num_msrs_to_save = j;
62ef68bb
PB		 5038
5039 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 5040 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5041 continue;
62ef68bb
PB		 5042
5043 if (j < i)
5044 emulated_msrs[j] = emulated_msrs[i];
5045 j++;
5046 }
5047 num_emulated_msrs = j;
801e459a
TL		 5048
5049 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5050 struct kvm_msr_entry msr;
5051
5052 msr.index = msr_based_features[i];
66421c1e 5053 if (kvm_get_msr_feature(&msr))
801e459a
TL		 5054 continue;
5055
5056 if (j < i)
5057 msr_based_features[j] = msr_based_features[i];
5058 j++;
5059 }
5060 num_msr_based_features = j;
043405e1
CO		 5061}
5062
bda9020e
MT		 5063static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5064 const void *v)
bbd9b64e 5065{
70252a10
AK		 5066 int handled = 0;
5067 int n;
5068
5069 do {
5070 n = min(len, 8);
bce87cce 5071 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5072 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5073 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 5074 break;
5075 handled += n;
5076 addr += n;
5077 len -= n;
5078 v += n;
5079 } while (len);
bbd9b64e 5080
70252a10 5081 return handled;
bbd9b64e
CO		 5082}
5083
bda9020e 5084static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 5085{
70252a10
AK		 5086 int handled = 0;
5087 int n;
5088
5089 do {
5090 n = min(len, 8);
bce87cce 5091 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5092 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5093 addr, n, v))
5094 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5095 break;
e39d200f 5096 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5097 handled += n;
5098 addr += n;
5099 len -= n;
5100 v += n;
5101 } while (len);
bbd9b64e 5102
70252a10 5103 return handled;
bbd9b64e
CO		 5104}
5105
2dafc6c2
GN		 5106static void kvm_set_segment(struct kvm_vcpu *vcpu,
5107 struct kvm_segment *var, int seg)
5108{
5109 kvm_x86_ops->set_segment(vcpu, var, seg);
5110}
5111
5112void kvm_get_segment(struct kvm_vcpu *vcpu,
5113 struct kvm_segment *var, int seg)
5114{
5115 kvm_x86_ops->get_segment(vcpu, var, seg);
5116}
5117
54987b7a
PB		 5118gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5119 struct x86_exception *exception)
02f59dc9
JR		 5120{
5121 gpa_t t_gpa;
02f59dc9
JR		 5122
5123 BUG_ON(!mmu_is_nested(vcpu));
5124
5125 /* NPT walks are always user-walks */
5126 access |= PFERR_USER_MASK;
44dd3ffa 5127 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5128
5129 return t_gpa;
5130}
5131
ab9ae313
AK		 5132gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5133 struct x86_exception *exception)
1871c602
GN		 5134{
5135 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5136 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5137}
5138
ab9ae313
AK		 5139 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5140 struct x86_exception *exception)
1871c602
GN		 5141{
5142 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5143 access |= PFERR_FETCH_MASK;
ab9ae313 5144 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5145}
5146
ab9ae313
AK		 5147gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5148 struct x86_exception *exception)
1871c602
GN		 5149{
5150 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5151 access |= PFERR_WRITE_MASK;
ab9ae313 5152 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5153}
5154
5155/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5156gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5157 struct x86_exception *exception)
1871c602 5158{
ab9ae313 5159 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5160}
5161
5162static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5163 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5164 struct x86_exception *exception)
bbd9b64e
CO		 5165{
5166 void *data = val;
10589a46 5167 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5168
5169 while (bytes) {
14dfe855 5170 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5171 exception);
bbd9b64e 5172 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5173 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5174 int ret;
5175
bcc55cba 5176 if (gpa == UNMAPPED_GVA)
ab9ae313 5177 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5178 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5179 offset, toread);
10589a46 5180 if (ret < 0) {
c3cd7ffa 5181 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5182 goto out;
5183 }
bbd9b64e 5184
77c2002e
IE		 5185 bytes -= toread;
5186 data += toread;
5187 addr += toread;
bbd9b64e 5188 }
10589a46 5189out:
10589a46 5190 return r;
bbd9b64e 5191}
77c2002e 5192
1871c602 5193/* used for instruction fetching */
0f65dd70
AK		 5194static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5195 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5196 struct x86_exception *exception)
1871c602 5197{
0f65dd70 5198 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5199 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5200 unsigned offset;
5201 int ret;
0f65dd70 5202
44583cba
PB		 5203 /* Inline kvm_read_guest_virt_helper for speed. */
5204 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5205 exception);
5206 if (unlikely(gpa == UNMAPPED_GVA))
5207 return X86EMUL_PROPAGATE_FAULT;
5208
5209 offset = addr & (PAGE_SIZE-1);
5210 if (WARN_ON(offset + bytes > PAGE_SIZE))
5211 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5212 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5213 offset, bytes);
44583cba
PB		 5214 if (unlikely(ret < 0))
5215 return X86EMUL_IO_NEEDED;
5216
5217 return X86EMUL_CONTINUE;
1871c602
GN		 5218}
5219
ce14e868 5220int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5221 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5222 struct x86_exception *exception)
1871c602
GN		 5223{
5224 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5225
353c0956
PB		 5226 /*
5227 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5228 * is returned, but our callers are not ready for that and they blindly
5229 * call kvm_inject_page_fault. Ensure that they at least do not leak
5230 * uninitialized kernel stack memory into cr2 and error code.
5231 */
5232 memset(exception, 0, sizeof(*exception));
1871c602 5233 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5234 exception);
1871c602 5235}
064aea77 5236EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5237
ce14e868
PB		 5238static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5239 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5240 struct x86_exception *exception, bool system)
1871c602 5241{
0f65dd70 5242 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5243 u32 access = 0;
5244
5245 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5246 access |= PFERR_USER_MASK;
5247
5248 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5249}
5250
7a036a6f
RK		 5251static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5252 unsigned long addr, void *val, unsigned int bytes)
5253{
5254 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5255 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5256
5257 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5258}
5259
ce14e868
PB		 5260static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5261 struct kvm_vcpu *vcpu, u32 access,
5262 struct x86_exception *exception)
77c2002e
IE		 5263{
5264 void *data = val;
5265 int r = X86EMUL_CONTINUE;
5266
5267 while (bytes) {
14dfe855 5268 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5269 access,
ab9ae313 5270 exception);
77c2002e
IE		 5271 unsigned offset = addr & (PAGE_SIZE-1);
5272 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5273 int ret;
5274
bcc55cba 5275 if (gpa == UNMAPPED_GVA)
ab9ae313 5276 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5277 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5278 if (ret < 0) {
c3cd7ffa 5279 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5280 goto out;
5281 }
5282
5283 bytes -= towrite;
5284 data += towrite;
5285 addr += towrite;
5286 }
5287out:
5288 return r;
5289}
ce14e868
PB		 5290
5291static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5292 unsigned int bytes, struct x86_exception *exception,
5293 bool system)
ce14e868
PB		 5294{
5295 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5296 u32 access = PFERR_WRITE_MASK;
5297
5298 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5299 access |= PFERR_USER_MASK;
ce14e868
PB		 5300
5301 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5302 access, exception);
ce14e868
PB		 5303}
5304
5305int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5306 unsigned int bytes, struct x86_exception *exception)
5307{
c595ceee
PB		 5308 /* kvm_write_guest_virt_system can pull in tons of pages. */
5309 vcpu->arch.l1tf_flush_l1d = true;
5310
ce14e868
PB		 5311 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5312 PFERR_WRITE_MASK, exception);
5313}
6a4d7550 5314EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5315
082d06ed
WL		 5316int handle_ud(struct kvm_vcpu *vcpu)
5317{
6c86eedc 5318 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5319 enum emulation_result er;
6c86eedc
WL		 5320 char sig[5]; /* ud2; .ascii "kvm" */
5321 struct x86_exception e;
5322
5323 if (force_emulation_prefix &&
3c9fa24c
PB		 5324 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5325 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5326 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5327 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5328 emul_type = 0;
5329 }
082d06ed 5330
0ce97a2b 5331 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5332 if (er == EMULATE_USER_EXIT)
5333 return 0;
5334 if (er != EMULATE_DONE)
5335 kvm_queue_exception(vcpu, UD_VECTOR);
5336 return 1;
5337}
5338EXPORT_SYMBOL_GPL(handle_ud);
5339
0f89b207
TL		 5340static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5341 gpa_t gpa, bool write)
5342{
5343 /* For APIC access vmexit */
5344 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5345 return 1;
5346
5347 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5348 trace_vcpu_match_mmio(gva, gpa, write, true);
5349 return 1;
5350 }
5351
5352 return 0;
5353}
5354
af7cc7d1
XG		 5355static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5356 gpa_t *gpa, struct x86_exception *exception,
5357 bool write)
5358{
97d64b78
AK		 5359 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5360 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5361
be94f6b7
HH		 5362 /*
5363 * currently PKRU is only applied to ept enabled guest so
5364 * there is no pkey in EPT page table for L1 guest or EPT
5365 * shadow page table for L2 guest.
5366 */
97d64b78 5367 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5368 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5369 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5370 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5371 (gva & (PAGE_SIZE - 1));
4f022648 5372 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5373 return 1;
5374 }
5375
af7cc7d1
XG		 5376 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5377
5378 if (*gpa == UNMAPPED_GVA)
5379 return -1;
5380
0f89b207 5381 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5382}
5383
3200f405 5384int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5385 const void *val, int bytes)
bbd9b64e
CO		 5386{
5387 int ret;
5388
54bf36aa 5389 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5390 if (ret < 0)
bbd9b64e 5391 return 0;
0eb05bf2 5392 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5393 return 1;
5394}
5395
77d197b2
XG		 5396struct read_write_emulator_ops {
5397 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5398 int bytes);
5399 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5400 void *val, int bytes);
5401 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5402 int bytes, void *val);
5403 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5404 void *val, int bytes);
5405 bool write;
5406};
5407
5408static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5409{
5410 if (vcpu->mmio_read_completed) {
77d197b2 5411 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5412 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5413 vcpu->mmio_read_completed = 0;
5414 return 1;
5415 }
5416
5417 return 0;
5418}
5419
5420static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5421 void *val, int bytes)
5422{
54bf36aa 5423 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5424}
5425
5426static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5427 void *val, int bytes)
5428{
5429 return emulator_write_phys(vcpu, gpa, val, bytes);
5430}
5431
5432static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5433{
e39d200f 5434 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5435 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5436}
5437
5438static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5439 void *val, int bytes)
5440{
e39d200f 5441 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5442 return X86EMUL_IO_NEEDED;
5443}
5444
5445static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5446 void *val, int bytes)
5447{
f78146b0
AK		 5448 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5449
87da7e66 5450 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5451 return X86EMUL_CONTINUE;
5452}
5453
0fbe9b0b 5454static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5455 .read_write_prepare = read_prepare,
5456 .read_write_emulate = read_emulate,
5457 .read_write_mmio = vcpu_mmio_read,
5458 .read_write_exit_mmio = read_exit_mmio,
5459};
5460
0fbe9b0b 5461static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5462 .read_write_emulate = write_emulate,
5463 .read_write_mmio = write_mmio,
5464 .read_write_exit_mmio = write_exit_mmio,
5465 .write = true,
5466};
5467
22388a3c
XG		 5468static int emulator_read_write_onepage(unsigned long addr, void *val,
5469 unsigned int bytes,
5470 struct x86_exception *exception,
5471 struct kvm_vcpu *vcpu,
0fbe9b0b 5472 const struct read_write_emulator_ops *ops)
bbd9b64e 5473{
af7cc7d1
XG		 5474 gpa_t gpa;
5475 int handled, ret;
22388a3c 5476 bool write = ops->write;
f78146b0 5477 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5478 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5479
5480 /*
5481 * If the exit was due to a NPF we may already have a GPA.
5482 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5483 * Note, this cannot be used on string operations since string
5484 * operation using rep will only have the initial GPA from the NPF
5485 * occurred.
5486 */
5487 if (vcpu->arch.gpa_available &&
5488 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5489 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5490 gpa = vcpu->arch.gpa_val;
5491 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5492 } else {
5493 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5494 if (ret < 0)
5495 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5496 }
10589a46 5497
618232e2 5498 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5499 return X86EMUL_CONTINUE;
5500
bbd9b64e
CO		 5501 /*
5502 * Is this MMIO handled locally?
5503 */
22388a3c 5504 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5505 if (handled == bytes)
bbd9b64e 5506 return X86EMUL_CONTINUE;
bbd9b64e 5507
70252a10
AK		 5508 gpa += handled;
5509 bytes -= handled;
5510 val += handled;
5511
87da7e66
XG		 5512 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5513 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5514 frag->gpa = gpa;
5515 frag->data = val;
5516 frag->len = bytes;
f78146b0 5517 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5518}
5519
52eb5a6d
XL		 5520static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5521 unsigned long addr,
22388a3c
XG		 5522 void *val, unsigned int bytes,
5523 struct x86_exception *exception,
0fbe9b0b 5524 const struct read_write_emulator_ops *ops)
bbd9b64e 5525{
0f65dd70 5526 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5527 gpa_t gpa;
5528 int rc;
5529
5530 if (ops->read_write_prepare &&
5531 ops->read_write_prepare(vcpu, val, bytes))
5532 return X86EMUL_CONTINUE;
5533
5534 vcpu->mmio_nr_fragments = 0;
0f65dd70 5535
bbd9b64e
CO		 5536 /* Crossing a page boundary? */
5537 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5538 int now;
bbd9b64e
CO		 5539
5540 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5541 rc = emulator_read_write_onepage(addr, val, now, exception,
5542 vcpu, ops);
5543
bbd9b64e
CO		 5544 if (rc != X86EMUL_CONTINUE)
5545 return rc;
5546 addr += now;
bac15531
NA		 5547 if (ctxt->mode != X86EMUL_MODE_PROT64)
5548 addr = (u32)addr;
bbd9b64e
CO		 5549 val += now;
5550 bytes -= now;
5551 }
22388a3c 5552
f78146b0
AK		 5553 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5554 vcpu, ops);
5555 if (rc != X86EMUL_CONTINUE)
5556 return rc;
5557
5558 if (!vcpu->mmio_nr_fragments)
5559 return rc;
5560
5561 gpa = vcpu->mmio_fragments[0].gpa;
5562
5563 vcpu->mmio_needed = 1;
5564 vcpu->mmio_cur_fragment = 0;
5565
87da7e66 5566 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5567 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5568 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5569 vcpu->run->mmio.phys_addr = gpa;
5570
5571 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5572}
5573
5574static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5575 unsigned long addr,
5576 void *val,
5577 unsigned int bytes,
5578 struct x86_exception *exception)
5579{
5580 return emulator_read_write(ctxt, addr, val, bytes,
5581 exception, &read_emultor);
5582}
5583
52eb5a6d 5584static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5585 unsigned long addr,
5586 const void *val,
5587 unsigned int bytes,
5588 struct x86_exception *exception)
5589{
5590 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5591 exception, &write_emultor);
bbd9b64e 5592}
bbd9b64e 5593
daea3e73
AK		 5594#define CMPXCHG_TYPE(t, ptr, old, new) \
5595 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5596
5597#ifdef CONFIG_X86_64
5598# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5599#else
5600# define CMPXCHG64(ptr, old, new) \
9749a6c0 5601 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5602#endif
5603
0f65dd70
AK		 5604static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5605 unsigned long addr,
bbd9b64e
CO		 5606 const void *old,
5607 const void *new,
5608 unsigned int bytes,
0f65dd70 5609 struct x86_exception *exception)
bbd9b64e 5610{
42e35f80 5611 struct kvm_host_map map;
0f65dd70 5612 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73 5613 gpa_t gpa;
daea3e73
AK		 5614 char *kaddr;
5615 bool exchanged;
2bacc55c 5616
daea3e73
AK		 5617 /* guests cmpxchg8b have to be emulated atomically */
5618 if (bytes > 8 || (bytes & (bytes - 1)))
5619 goto emul_write;
10589a46 5620
daea3e73 5621 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5622
daea3e73
AK		 5623 if (gpa == UNMAPPED_GVA ||
5624 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5625 goto emul_write;
2bacc55c 5626
daea3e73
AK		 5627 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5628 goto emul_write;
72dc67a6 5629
42e35f80 5630 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
c19b8bd6 5631 goto emul_write;
72dc67a6 5632
42e35f80
KA		 5633 kaddr = map.hva + offset_in_page(gpa);
5634
daea3e73
AK		 5635 switch (bytes) {
5636 case 1:
5637 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5638 break;
5639 case 2:
5640 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5641 break;
5642 case 4:
5643 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5644 break;
5645 case 8:
5646 exchanged = CMPXCHG64(kaddr, old, new);
5647 break;
5648 default:
5649 BUG();
2bacc55c 5650 }
42e35f80
KA		 5651
5652 kvm_vcpu_unmap(vcpu, &map, true);
daea3e73
AK		 5653
5654 if (!exchanged)
5655 return X86EMUL_CMPXCHG_FAILED;
5656
0eb05bf2 5657 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5658
5659 return X86EMUL_CONTINUE;
4a5f48f6 5660
3200f405 5661emul_write:
daea3e73 5662 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5663
0f65dd70 5664 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5665}
5666
cf8f70bf
GN		 5667static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5668{
cbfc6c91 5669 int r = 0, i;
cf8f70bf 5670
cbfc6c91
WL		 5671 for (i = 0; i < vcpu->arch.pio.count; i++) {
5672 if (vcpu->arch.pio.in)
5673 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5674 vcpu->arch.pio.size, pd);
5675 else
5676 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5677 vcpu->arch.pio.port, vcpu->arch.pio.size,
5678 pd);
5679 if (r)
5680 break;
5681 pd += vcpu->arch.pio.size;
5682 }
cf8f70bf
GN		 5683 return r;
5684}
5685
6f6fbe98
XG		 5686static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5687 unsigned short port, void *val,
5688 unsigned int count, bool in)
cf8f70bf 5689{
cf8f70bf 5690 vcpu->arch.pio.port = port;
6f6fbe98 5691 vcpu->arch.pio.in = in;
7972995b 5692 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5693 vcpu->arch.pio.size = size;
5694
5695 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5696 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5697 return 1;
5698 }
5699
5700 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5701 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5702 vcpu->run->io.size = size;
5703 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5704 vcpu->run->io.count = count;
5705 vcpu->run->io.port = port;
5706
5707 return 0;
5708}
5709
6f6fbe98
XG		 5710static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5711 int size, unsigned short port, void *val,
5712 unsigned int count)
cf8f70bf 5713{
ca1d4a9e 5714 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5715 int ret;
ca1d4a9e 5716
6f6fbe98
XG		 5717 if (vcpu->arch.pio.count)
5718 goto data_avail;
cf8f70bf 5719
cbfc6c91
WL		 5720 memset(vcpu->arch.pio_data, 0, size * count);
5721
6f6fbe98
XG		 5722 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5723 if (ret) {
5724data_avail:
5725 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5726 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5727 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5728 return 1;
5729 }
5730
cf8f70bf
GN		 5731 return 0;
5732}
5733
6f6fbe98
XG		 5734static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5735 int size, unsigned short port,
5736 const void *val, unsigned int count)
5737{
5738 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5739
5740 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5741 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5742 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5743}
5744
bbd9b64e
CO		 5745static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5746{
5747 return kvm_x86_ops->get_segment_base(vcpu, seg);
5748}
5749
3cb16fe7 5750static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5751{
3cb16fe7 5752 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5753}
5754
ae6a2375 5755static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5756{
5757 if (!need_emulate_wbinvd(vcpu))
5758 return X86EMUL_CONTINUE;
5759
5760 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5761 int cpu = get_cpu();
5762
5763 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5764 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5765 wbinvd_ipi, NULL, 1);
2eec7343 5766 put_cpu();
f5f48ee1 5767 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5768 } else
5769 wbinvd();
f5f48ee1
SY		 5770 return X86EMUL_CONTINUE;
5771}
5cb56059
JS		 5772
5773int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5774{
6affcbed
KH		 5775 kvm_emulate_wbinvd_noskip(vcpu);
5776 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5777}
f5f48ee1
SY		 5778EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5779
5cb56059
JS		 5780
5781
bcaf5cc5
AK		 5782static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5783{
5cb56059 5784 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5785}
5786
52eb5a6d
XL		 5787static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5788 unsigned long *dest)
bbd9b64e 5789{
16f8a6f9 5790 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5791}
5792
52eb5a6d
XL		 5793static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5794 unsigned long value)
bbd9b64e 5795{
338dbc97 5796
717746e3 5797 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5798}
5799
52a46617 5800static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5801{
52a46617 5802 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5803}
5804
717746e3 5805static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5806{
717746e3 5807 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5808 unsigned long value;
5809
5810 switch (cr) {
5811 case 0:
5812 value = kvm_read_cr0(vcpu);
5813 break;
5814 case 2:
5815 value = vcpu->arch.cr2;
5816 break;
5817 case 3:
9f8fe504 5818 value = kvm_read_cr3(vcpu);
52a46617
GN		 5819 break;
5820 case 4:
5821 value = kvm_read_cr4(vcpu);
5822 break;
5823 case 8:
5824 value = kvm_get_cr8(vcpu);
5825 break;
5826 default:
a737f256 5827 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5828 return 0;
5829 }
5830
5831 return value;
5832}
5833
717746e3 5834static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5835{
717746e3 5836 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5837 int res = 0;
5838
52a46617
GN		 5839 switch (cr) {
5840 case 0:
49a9b07e 5841 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5842 break;
5843 case 2:
5844 vcpu->arch.cr2 = val;
5845 break;
5846 case 3:
2390218b 5847 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5848 break;
5849 case 4:
a83b29c6 5850 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5851 break;
5852 case 8:
eea1cff9 5853 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5854 break;
5855 default:
a737f256 5856 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5857 res = -1;
52a46617 5858 }
0f12244f
GN		 5859
5860 return res;
52a46617
GN		 5861}
5862
717746e3 5863static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5864{
717746e3 5865 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5866}
5867
4bff1e86 5868static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5869{
4bff1e86 5870 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5871}
5872
4bff1e86 5873static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5874{
4bff1e86 5875 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5876}
5877
1ac9d0cf
AK		 5878static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5879{
5880 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5881}
5882
5883static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5884{
5885 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5886}
5887
4bff1e86
AK		 5888static unsigned long emulator_get_cached_segment_base(
5889 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5890{
4bff1e86 5891 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5892}
5893
1aa36616
AK		 5894static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5895 struct desc_struct *desc, u32 *base3,
5896 int seg)
2dafc6c2
GN		 5897{
5898 struct kvm_segment var;
5899
4bff1e86 5900 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5901 *selector = var.selector;
2dafc6c2 5902
378a8b09
GN		 5903 if (var.unusable) {
5904 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5905 if (base3)
5906 *base3 = 0;
2dafc6c2 5907 return false;
378a8b09 5908 }
2dafc6c2
GN		 5909
5910 if (var.g)
5911 var.limit >>= 12;
5912 set_desc_limit(desc, var.limit);
5913 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5914#ifdef CONFIG_X86_64
5915 if (base3)
5916 *base3 = var.base >> 32;
5917#endif
2dafc6c2
GN		 5918 desc->type = var.type;
5919 desc->s = var.s;
5920 desc->dpl = var.dpl;
5921 desc->p = var.present;
5922 desc->avl = var.avl;
5923 desc->l = var.l;
5924 desc->d = var.db;
5925 desc->g = var.g;
5926
5927 return true;
5928}
5929
1aa36616
AK		 5930static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5931 struct desc_struct *desc, u32 base3,
5932 int seg)
2dafc6c2 5933{
4bff1e86 5934 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5935 struct kvm_segment var;
5936
1aa36616 5937 var.selector = selector;
2dafc6c2 5938 var.base = get_desc_base(desc);
5601d05b
GN		 5939#ifdef CONFIG_X86_64
5940 var.base |= ((u64)base3) << 32;
5941#endif
2dafc6c2
GN		 5942 var.limit = get_desc_limit(desc);
5943 if (desc->g)
5944 var.limit = (var.limit << 12) | 0xfff;
5945 var.type = desc->type;
2dafc6c2
GN		 5946 var.dpl = desc->dpl;
5947 var.db = desc->d;
5948 var.s = desc->s;
5949 var.l = desc->l;
5950 var.g = desc->g;
5951 var.avl = desc->avl;
5952 var.present = desc->p;
5953 var.unusable = !var.present;
5954 var.padding = 0;
5955
5956 kvm_set_segment(vcpu, &var, seg);
5957 return;
5958}
5959
717746e3
AK		 5960static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5961 u32 msr_index, u64 *pdata)
5962{
609e36d3
PB		 5963 struct msr_data msr;
5964 int r;
5965
5966 msr.index = msr_index;
5967 msr.host_initiated = false;
5968 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5969 if (r)
5970 return r;
5971
5972 *pdata = msr.data;
5973 return 0;
717746e3
AK		 5974}
5975
5976static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5977 u32 msr_index, u64 data)
5978{
8fe8ab46
WA		 5979 struct msr_data msr;
5980
5981 msr.data = data;
5982 msr.index = msr_index;
5983 msr.host_initiated = false;
5984 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5985}
5986
64d60670
PB		 5987static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5988{
5989 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5990
5991 return vcpu->arch.smbase;
5992}
5993
5994static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5995{
5996 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5997
5998 vcpu->arch.smbase = smbase;
5999}
6000
67f4d428
NA		 6001static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6002 u32 pmc)
6003{
c6702c9d 6004 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 6005}
6006
222d21aa
AK		 6007static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6008 u32 pmc, u64 *pdata)
6009{
c6702c9d 6010 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 6011}
6012
6c3287f7
AK		 6013static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6014{
6015 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6016}
6017
2953538e 6018static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 6019 struct x86_instruction_info *info,
c4f035c6
AK		 6020 enum x86_intercept_stage stage)
6021{
2953538e 6022 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 6023}
6024
e911eb3b
YZ		 6025static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6026 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 6027{
e911eb3b 6028 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 6029}
6030
dd856efa
AK		 6031static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6032{
6033 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6034}
6035
6036static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6037{
6038 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6039}
6040
801806d9
NA		 6041static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6042{
6043 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6044}
6045
6ed071f0
LP		 6046static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6047{
6048 return emul_to_vcpu(ctxt)->arch.hflags;
6049}
6050
6051static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6052{
c5833c7a 6053 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 6054}
6055
ed19321f
SC		 6056static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6057 const char *smstate)
0234bf88 6058{
ed19321f 6059 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 6060}
6061
c5833c7a
SC		 6062static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6063{
6064 kvm_smm_changed(emul_to_vcpu(ctxt));
6065}
6066
0225fb50 6067static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 6068 .read_gpr = emulator_read_gpr,
6069 .write_gpr = emulator_write_gpr,
ce14e868
PB		 6070 .read_std = emulator_read_std,
6071 .write_std = emulator_write_std,
7a036a6f 6072 .read_phys = kvm_read_guest_phys_system,
1871c602 6073 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 6074 .read_emulated = emulator_read_emulated,
6075 .write_emulated = emulator_write_emulated,
6076 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 6077 .invlpg = emulator_invlpg,
cf8f70bf
GN		 6078 .pio_in_emulated = emulator_pio_in_emulated,
6079 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 6080 .get_segment = emulator_get_segment,
6081 .set_segment = emulator_set_segment,
5951c442 6082 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 6083 .get_gdt = emulator_get_gdt,
160ce1f1 6084 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 6085 .set_gdt = emulator_set_gdt,
6086 .set_idt = emulator_set_idt,
52a46617
GN		 6087 .get_cr = emulator_get_cr,
6088 .set_cr = emulator_set_cr,
9c537244 6089 .cpl = emulator_get_cpl,
35aa5375
GN		 6090 .get_dr = emulator_get_dr,
6091 .set_dr = emulator_set_dr,
64d60670
PB		 6092 .get_smbase = emulator_get_smbase,
6093 .set_smbase = emulator_set_smbase,
717746e3
AK		 6094 .set_msr = emulator_set_msr,
6095 .get_msr = emulator_get_msr,
67f4d428 6096 .check_pmc = emulator_check_pmc,
222d21aa 6097 .read_pmc = emulator_read_pmc,
6c3287f7 6098 .halt = emulator_halt,
bcaf5cc5 6099 .wbinvd = emulator_wbinvd,
d6aa1000 6100 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6101 .intercept = emulator_intercept,
bdb42f5a 6102 .get_cpuid = emulator_get_cpuid,
801806d9 6103 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6104 .get_hflags = emulator_get_hflags,
6105 .set_hflags = emulator_set_hflags,
0234bf88 6106 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6107 .post_leave_smm = emulator_post_leave_smm,
bbd9b64e
CO		 6108};
6109
95cb2295
GN		 6110static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6111{
37ccdcbe 6112 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6113 /*
6114 * an sti; sti; sequence only disable interrupts for the first
6115 * instruction. So, if the last instruction, be it emulated or
6116 * not, left the system with the INT_STI flag enabled, it
6117 * means that the last instruction is an sti. We should not
6118 * leave the flag on in this case. The same goes for mov ss
6119 */
37ccdcbe
PB		 6120 if (int_shadow & mask)
6121 mask = 0;
6addfc42 6122 if (unlikely(int_shadow || mask)) {
95cb2295 6123 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6124 if (!mask)
6125 kvm_make_request(KVM_REQ_EVENT, vcpu);
6126 }
95cb2295
GN		 6127}
6128
ef54bcfe 6129static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6130{
6131 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6132 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6133 return kvm_propagate_fault(vcpu, &ctxt->exception);
6134
6135 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6136 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6137 ctxt->exception.error_code);
54b8486f 6138 else
da9cb575 6139 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6140 return false;
54b8486f
GN		 6141}
6142
8ec4722d
MG		 6143static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6144{
adf52235 6145 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6146 int cs_db, cs_l;
6147
8ec4722d
MG		 6148 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6149
adf52235 6150 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6151 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6152
adf52235
TY		 6153 ctxt->eip = kvm_rip_read(vcpu);
6154 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6155 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6156 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6157 cs_db ? X86EMUL_MODE_PROT32 :
6158 X86EMUL_MODE_PROT16;
a584539b 6159 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6160 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6161 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6162
dd856efa 6163 init_decode_cache(ctxt);
7ae441ea 6164 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6165}
6166
71f9833b 6167int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6168{
9d74191a 6169 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6170 int ret;
6171
6172 init_emulate_ctxt(vcpu);
6173
9dac77fa
AK		 6174 ctxt->op_bytes = 2;
6175 ctxt->ad_bytes = 2;
6176 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6177 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6178
6179 if (ret != X86EMUL_CONTINUE)
6180 return EMULATE_FAIL;
6181
9dac77fa 6182 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6183 kvm_rip_write(vcpu, ctxt->eip);
6184 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6185
63995653
MG		 6186 return EMULATE_DONE;
6187}
6188EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6189
e2366171 6190static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6191{
fc3a9157
JR		 6192 int r = EMULATE_DONE;
6193
6d77dbfc
GN		 6194 ++vcpu->stat.insn_emulation_fail;
6195 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6196
6197 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6198 return EMULATE_FAIL;
6199
a2b9e6c1 6200 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6201 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6202 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6203 vcpu->run->internal.ndata = 0;
1f4dcb3b 6204 r = EMULATE_USER_EXIT;
fc3a9157 6205 }
e2366171 6206
6d77dbfc 6207 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6208
6209 return r;
6d77dbfc
GN		 6210}
6211
93c05d3e 6212static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6213 bool write_fault_to_shadow_pgtable,
6214 int emulation_type)
a6f177ef 6215{
95b3cf69 6216 gpa_t gpa = cr2;
ba049e93 6217 kvm_pfn_t pfn;
a6f177ef 6218
384bf221 6219 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6220 return false;
6221
6c3dfeb6
SC		 6222 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6223 return false;
6224
44dd3ffa 6225 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6226 /*
6227 * Write permission should be allowed since only
6228 * write access need to be emulated.
6229 */
6230 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6231
95b3cf69
XG		 6232 /*
6233 * If the mapping is invalid in guest, let cpu retry
6234 * it to generate fault.
6235 */
6236 if (gpa == UNMAPPED_GVA)
6237 return true;
6238 }
a6f177ef 6239
8e3d9d06
XG		 6240 /*
6241 * Do not retry the unhandleable instruction if it faults on the
6242 * readonly host memory, otherwise it will goto a infinite loop:
6243 * retry instruction -> write #PF -> emulation fail -> retry
6244 * instruction -> ...
6245 */
6246 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6247
6248 /*
6249 * If the instruction failed on the error pfn, it can not be fixed,
6250 * report the error to userspace.
6251 */
6252 if (is_error_noslot_pfn(pfn))
6253 return false;
6254
6255 kvm_release_pfn_clean(pfn);
6256
6257 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6258 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6259 unsigned int indirect_shadow_pages;
6260
6261 spin_lock(&vcpu->kvm->mmu_lock);
6262 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6263 spin_unlock(&vcpu->kvm->mmu_lock);
6264
6265 if (indirect_shadow_pages)
6266 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6267
a6f177ef 6268 return true;
8e3d9d06 6269 }
a6f177ef 6270
95b3cf69
XG		 6271 /*
6272 * if emulation was due to access to shadowed page table
6273 * and it failed try to unshadow page and re-enter the
6274 * guest to let CPU execute the instruction.
6275 */
6276 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6277
6278 /*
6279 * If the access faults on its page table, it can not
6280 * be fixed by unprotecting shadow page and it should
6281 * be reported to userspace.
6282 */
6283 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6284}
6285
1cb3f3ae
XG		 6286static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6287 unsigned long cr2, int emulation_type)
6288{
6289 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6290 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6291
6292 last_retry_eip = vcpu->arch.last_retry_eip;
6293 last_retry_addr = vcpu->arch.last_retry_addr;
6294
6295 /*
6296 * If the emulation is caused by #PF and it is non-page_table
6297 * writing instruction, it means the VM-EXIT is caused by shadow
6298 * page protected, we can zap the shadow page and retry this
6299 * instruction directly.
6300 *
6301 * Note: if the guest uses a non-page-table modifying instruction
6302 * on the PDE that points to the instruction, then we will unmap
6303 * the instruction and go to an infinite loop. So, we cache the
6304 * last retried eip and the last fault address, if we meet the eip
6305 * and the address again, we can break out of the potential infinite
6306 * loop.
6307 */
6308 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6309
384bf221 6310 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6311 return false;
6312
6c3dfeb6
SC		 6313 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6314 return false;
6315
1cb3f3ae
XG		 6316 if (x86_page_table_writing_insn(ctxt))
6317 return false;
6318
6319 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6320 return false;
6321
6322 vcpu->arch.last_retry_eip = ctxt->eip;
6323 vcpu->arch.last_retry_addr = cr2;
6324
44dd3ffa 6325 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6326 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6327
22368028 6328 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6329
6330 return true;
6331}
6332
716d51ab
GN		 6333static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6334static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6335
64d60670 6336static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6337{
64d60670 6338 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6339 /* This is a good place to trace that we are exiting SMM. */
6340 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6341
c43203ca
PB		 6342 /* Process a latched INIT or SMI, if any. */
6343 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6344 }
699023e2
PB		 6345
6346 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6347}
6348
4a1e10d5
PB		 6349static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6350 unsigned long *db)
6351{
6352 u32 dr6 = 0;
6353 int i;
6354 u32 enable, rwlen;
6355
6356 enable = dr7;
6357 rwlen = dr7 >> 16;
6358 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6359 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6360 dr6 |= (1 << i);
6361 return dr6;
6362}
6363
c8401dda 6364static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6365{
6366 struct kvm_run *kvm_run = vcpu->run;
6367
c8401dda
PB		 6368 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6369 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6370 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6371 kvm_run->debug.arch.exception = DB_VECTOR;
6372 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6373 *r = EMULATE_USER_EXIT;
6374 } else {
f10c729f 6375 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6376 }
6377}
6378
6affcbed
KH		 6379int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6380{
6381 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6382 int r = EMULATE_DONE;
6383
6384 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6385
6386 /*
6387 * rflags is the old, "raw" value of the flags. The new value has
6388 * not been saved yet.
6389 *
6390 * This is correct even for TF set by the guest, because "the
6391 * processor will not generate this exception after the instruction
6392 * that sets the TF flag".
6393 */
6394 if (unlikely(rflags & X86_EFLAGS_TF))
6395 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6396 return r == EMULATE_DONE;
6397}
6398EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6399
4a1e10d5
PB		 6400static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6401{
4a1e10d5
PB		 6402 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6403 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6404 struct kvm_run *kvm_run = vcpu->run;
6405 unsigned long eip = kvm_get_linear_rip(vcpu);
6406 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6407 vcpu->arch.guest_debug_dr7,
6408 vcpu->arch.eff_db);
6409
6410 if (dr6 != 0) {
6f43ed01 6411 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6412 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6413 kvm_run->debug.arch.exception = DB_VECTOR;
6414 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6415 *r = EMULATE_USER_EXIT;
6416 return true;
6417 }
6418 }
6419
4161a569
NA		 6420 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6421 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6422 unsigned long eip = kvm_get_linear_rip(vcpu);
6423 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6424 vcpu->arch.dr7,
6425 vcpu->arch.db);
6426
6427 if (dr6 != 0) {
1fc5d194 6428 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 6429 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6430 kvm_queue_exception(vcpu, DB_VECTOR);
6431 *r = EMULATE_DONE;
6432 return true;
6433 }
6434 }
6435
6436 return false;
6437}
6438
04789b66
LA		 6439static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6440{
2d7921c4
AM		 6441 switch (ctxt->opcode_len) {
6442 case 1:
6443 switch (ctxt->b) {
6444 case 0xe4: /* IN */
6445 case 0xe5:
6446 case 0xec:
6447 case 0xed:
6448 case 0xe6: /* OUT */
6449 case 0xe7:
6450 case 0xee:
6451 case 0xef:
6452 case 0x6c: /* INS */
6453 case 0x6d:
6454 case 0x6e: /* OUTS */
6455 case 0x6f:
6456 return true;
6457 }
6458 break;
6459 case 2:
6460 switch (ctxt->b) {
6461 case 0x33: /* RDPMC */
6462 return true;
6463 }
6464 break;
04789b66
LA		 6465 }
6466
6467 return false;
6468}
6469
51d8b661
AP		 6470int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6471 unsigned long cr2,
dc25e89e
AP		 6472 int emulation_type,
6473 void *insn,
6474 int insn_len)
bbd9b64e 6475{
95cb2295 6476 int r;
9d74191a 6477 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6478 bool writeback = true;
93c05d3e 6479 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6480
c595ceee
PB		 6481 vcpu->arch.l1tf_flush_l1d = true;
6482
93c05d3e
XG		 6483 /*
6484 * Clear write_fault_to_shadow_pgtable here to ensure it is
6485 * never reused.
6486 */
6487 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6488 kvm_clear_exception_queue(vcpu);
8d7d8102 6489
571008da 6490 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6491 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6492
6493 /*
6494 * We will reenter on the same instruction since
6495 * we do not set complete_userspace_io. This does not
6496 * handle watchpoints yet, those would be handled in
6497 * the emulate_ops.
6498 */
d391f120
VK		 6499 if (!(emulation_type & EMULTYPE_SKIP) &&
6500 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6501 return r;
6502
9d74191a
TY		 6503 ctxt->interruptibility = 0;
6504 ctxt->have_exception = false;
e0ad0b47 6505 ctxt->exception.vector = -1;
9d74191a 6506 ctxt->perm_ok = false;
bbd9b64e 6507
b51e974f 6508 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6509
9d74191a 6510 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6511
e46479f8 6512 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6513 ++vcpu->stat.insn_emulation;
1d2887e2 6514 if (r != EMULATION_OK) {
4005996e
AK		 6515 if (emulation_type & EMULTYPE_TRAP_UD)
6516 return EMULATE_FAIL;
991eebf9
GN		 6517 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6518 emulation_type))
bbd9b64e 6519 return EMULATE_DONE;
6ea6e843
PB		 6520 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6521 return EMULATE_DONE;
6d77dbfc
GN		 6522 if (emulation_type & EMULTYPE_SKIP)
6523 return EMULATE_FAIL;
e2366171 6524 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6525 }
6526 }
6527
04789b66
LA		 6528 if ((emulation_type & EMULTYPE_VMWARE) &&
6529 !is_vmware_backdoor_opcode(ctxt))
6530 return EMULATE_FAIL;
6531
ba8afb6b 6532 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6533 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6534 if (ctxt->eflags & X86_EFLAGS_RF)
6535 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6536 return EMULATE_DONE;
6537 }
6538
1cb3f3ae
XG		 6539 if (retry_instruction(ctxt, cr2, emulation_type))
6540 return EMULATE_DONE;
6541
7ae441ea 6542 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6543 changes registers values during IO operation */
7ae441ea
GN		 6544 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6545 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6546 emulator_invalidate_register_cache(ctxt);
7ae441ea 6547 }
4d2179e1 6548
5cd21917 6549restart:
0f89b207
TL		 6550 /* Save the faulting GPA (cr2) in the address field */
6551 ctxt->exception.address = cr2;
6552
9d74191a 6553 r = x86_emulate_insn(ctxt);
bbd9b64e 6554
775fde86
JR		 6555 if (r == EMULATION_INTERCEPTED)
6556 return EMULATE_DONE;
6557
d2ddd1c4 6558 if (r == EMULATION_FAILED) {
991eebf9
GN		 6559 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6560 emulation_type))
c3cd7ffa
GN		 6561 return EMULATE_DONE;
6562
e2366171 6563 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6564 }
6565
9d74191a 6566 if (ctxt->have_exception) {
d2ddd1c4 6567 r = EMULATE_DONE;
ef54bcfe
PB		 6568 if (inject_emulated_exception(vcpu))
6569 return r;
d2ddd1c4 6570 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6571 if (!vcpu->arch.pio.in) {
6572 /* FIXME: return into emulator if single-stepping. */
3457e419 6573 vcpu->arch.pio.count = 0;
0912c977 6574 } else {
7ae441ea 6575 writeback = false;
716d51ab
GN		 6576 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6577 }
ac0a48c3 6578 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6579 } else if (vcpu->mmio_needed) {
6580 if (!vcpu->mmio_is_write)
6581 writeback = false;
ac0a48c3 6582 r = EMULATE_USER_EXIT;
716d51ab 6583 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6584 } else if (r == EMULATION_RESTART)
5cd21917 6585 goto restart;
d2ddd1c4
GN		 6586 else
6587 r = EMULATE_DONE;
f850e2e6 6588
7ae441ea 6589 if (writeback) {
6addfc42 6590 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6591 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6592 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6593 kvm_rip_write(vcpu, ctxt->eip);
5cc244a2 6594 if (r == EMULATE_DONE && ctxt->tf)
c8401dda 6595 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6596 if (!ctxt->have_exception ||
6597 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6598 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6599
6600 /*
6601 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6602 * do nothing, and it will be requested again as soon as
6603 * the shadow expires. But we still need to check here,
6604 * because POPF has no interrupt shadow.
6605 */
6606 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6607 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6608 } else
6609 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6610
6611 return r;
de7d789a 6612}
c60658d1
SC		 6613
6614int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6615{
6616 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6617}
6618EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6619
6620int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6621 void *insn, int insn_len)
6622{
6623 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6624}
6625EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6626
8764ed55
SC		 6627static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6628{
6629 vcpu->arch.pio.count = 0;
6630 return 1;
6631}
6632
45def77e
SC		 6633static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6634{
6635 vcpu->arch.pio.count = 0;
6636
6637 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6638 return 1;
6639
6640 return kvm_skip_emulated_instruction(vcpu);
6641}
6642
dca7f128
SC		 6643static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6644 unsigned short port)
de7d789a 6645{
de3cd117 6646 unsigned long val = kvm_rax_read(vcpu);
ca1d4a9e
AK		 6647 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6648 size, port, &val, 1);
8764ed55
SC		 6649 if (ret)
6650 return ret;
45def77e 6651
8764ed55
SC		 6652 /*
6653 * Workaround userspace that relies on old KVM behavior of %rip being
6654 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6655 */
6656 if (port == 0x7e &&
6657 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6658 vcpu->arch.complete_userspace_io =
6659 complete_fast_pio_out_port_0x7e;
6660 kvm_skip_emulated_instruction(vcpu);
6661 } else {
45def77e
SC		 6662 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6663 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6664 }
8764ed55 6665 return 0;
de7d789a 6666}
de7d789a 6667
8370c3d0
TL		 6668static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6669{
6670 unsigned long val;
6671
6672 /* We should only ever be called with arch.pio.count equal to 1 */
6673 BUG_ON(vcpu->arch.pio.count != 1);
6674
45def77e
SC		 6675 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6676 vcpu->arch.pio.count = 0;
6677 return 1;
6678 }
6679
8370c3d0 6680 /* For size less than 4 we merge, else we zero extend */
de3cd117 6681 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6682
6683 /*
6684 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6685 * the copy and tracing
6686 */
6687 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6688 vcpu->arch.pio.port, &val, 1);
de3cd117 6689 kvm_rax_write(vcpu, val);
8370c3d0 6690
45def77e 6691 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6692}
6693
dca7f128
SC		 6694static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6695 unsigned short port)
8370c3d0
TL		 6696{
6697 unsigned long val;
6698 int ret;
6699
6700 /* For size less than 4 we merge, else we zero extend */
de3cd117 6701 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6702
6703 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6704 &val, 1);
6705 if (ret) {
de3cd117 6706 kvm_rax_write(vcpu, val);
8370c3d0
TL		 6707 return ret;
6708 }
6709
45def77e 6710 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6711 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6712
6713 return 0;
6714}
dca7f128
SC		 6715
6716int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6717{
45def77e 6718 int ret;
dca7f128 6719
dca7f128 6720 if (in)
45def77e 6721 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6722 else
45def77e
SC		 6723 ret = kvm_fast_pio_out(vcpu, size, port);
6724 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 6725}
6726EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6727
251a5fd6 6728static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6729{
0a3aee0d 6730 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6731 return 0;
8cfdc000
ZA		 6732}
6733
6734static void tsc_khz_changed(void *data)
c8076604 6735{
8cfdc000
ZA		 6736 struct cpufreq_freqs *freq = data;
6737 unsigned long khz = 0;
6738
6739 if (data)
6740 khz = freq->new;
6741 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6742 khz = cpufreq_quick_get(raw_smp_processor_id());
6743 if (!khz)
6744 khz = tsc_khz;
0a3aee0d 6745 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6746}
6747
5fa4ec9c 6748#ifdef CONFIG_X86_64
0092e434
VK		 6749static void kvm_hyperv_tsc_notifier(void)
6750{
0092e434
VK		 6751 struct kvm *kvm;
6752 struct kvm_vcpu *vcpu;
6753 int cpu;
6754
0d9ce162 6755 mutex_lock(&kvm_lock);
0092e434
VK		 6756 list_for_each_entry(kvm, &vm_list, vm_list)
6757 kvm_make_mclock_inprogress_request(kvm);
6758
6759 hyperv_stop_tsc_emulation();
6760
6761 /* TSC frequency always matches when on Hyper-V */
6762 for_each_present_cpu(cpu)
6763 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6764 kvm_max_guest_tsc_khz = tsc_khz;
6765
6766 list_for_each_entry(kvm, &vm_list, vm_list) {
6767 struct kvm_arch *ka = &kvm->arch;
6768
6769 spin_lock(&ka->pvclock_gtod_sync_lock);
6770
6771 pvclock_update_vm_gtod_copy(kvm);
6772
6773 kvm_for_each_vcpu(cpu, vcpu, kvm)
6774 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6775
6776 kvm_for_each_vcpu(cpu, vcpu, kvm)
6777 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6778
6779 spin_unlock(&ka->pvclock_gtod_sync_lock);
6780 }
0d9ce162 6781 mutex_unlock(&kvm_lock);
0092e434 6782}
5fa4ec9c 6783#endif
0092e434 6784
df24014a 6785static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
c8076604 6786{
c8076604
GH		 6787 struct kvm *kvm;
6788 struct kvm_vcpu *vcpu;
6789 int i, send_ipi = 0;
6790
8cfdc000
ZA		 6791 /*
6792 * We allow guests to temporarily run on slowing clocks,
6793 * provided we notify them after, or to run on accelerating
6794 * clocks, provided we notify them before. Thus time never
6795 * goes backwards.
6796 *
6797 * However, we have a problem. We can't atomically update
6798 * the frequency of a given CPU from this function; it is
6799 * merely a notifier, which can be called from any CPU.
6800 * Changing the TSC frequency at arbitrary points in time
6801 * requires a recomputation of local variables related to
6802 * the TSC for each VCPU. We must flag these local variables
6803 * to be updated and be sure the update takes place with the
6804 * new frequency before any guests proceed.
6805 *
6806 * Unfortunately, the combination of hotplug CPU and frequency
6807 * change creates an intractable locking scenario; the order
6808 * of when these callouts happen is undefined with respect to
6809 * CPU hotplug, and they can race with each other. As such,
6810 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6811 * undefined; you can actually have a CPU frequency change take
6812 * place in between the computation of X and the setting of the
6813 * variable. To protect against this problem, all updates of
6814 * the per_cpu tsc_khz variable are done in an interrupt
6815 * protected IPI, and all callers wishing to update the value
6816 * must wait for a synchronous IPI to complete (which is trivial
6817 * if the caller is on the CPU already). This establishes the
6818 * necessary total order on variable updates.
6819 *
6820 * Note that because a guest time update may take place
6821 * anytime after the setting of the VCPU's request bit, the
6822 * correct TSC value must be set before the request. However,
6823 * to ensure the update actually makes it to any guest which
6824 * starts running in hardware virtualization between the set
6825 * and the acquisition of the spinlock, we must also ping the
6826 * CPU after setting the request bit.
6827 *
6828 */
6829
df24014a 6830 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6831
0d9ce162 6832 mutex_lock(&kvm_lock);
c8076604 6833 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6834 kvm_for_each_vcpu(i, vcpu, kvm) {
df24014a 6835 if (vcpu->cpu != cpu)
c8076604 6836 continue;
c285545f 6837 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0d9ce162 6838 if (vcpu->cpu != raw_smp_processor_id())
8cfdc000 6839 send_ipi = 1;
c8076604
GH		 6840 }
6841 }
0d9ce162 6842 mutex_unlock(&kvm_lock);
c8076604
GH		 6843
6844 if (freq->old < freq->new && send_ipi) {
6845 /*
6846 * We upscale the frequency. Must make the guest
6847 * doesn't see old kvmclock values while running with
6848 * the new frequency, otherwise we risk the guest sees
6849 * time go backwards.
6850 *
6851 * In case we update the frequency for another cpu
6852 * (which might be in guest context) send an interrupt
6853 * to kick the cpu out of guest context. Next time
6854 * guest context is entered kvmclock will be updated,
6855 * so the guest will not see stale values.
6856 */
df24014a 6857 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6858 }
df24014a
VK		 6859}
6860
6861static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6862 void *data)
6863{
6864 struct cpufreq_freqs *freq = data;
6865 int cpu;
6866
6867 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6868 return 0;
6869 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6870 return 0;
6871
6872 for_each_cpu(cpu, freq->policy->cpus)
6873 __kvmclock_cpufreq_notifier(freq, cpu);
6874
c8076604
GH		 6875 return 0;
6876}
6877
6878static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6879 .notifier_call = kvmclock_cpufreq_notifier
6880};
6881
251a5fd6 6882static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6883{
251a5fd6
SAS		 6884 tsc_khz_changed(NULL);
6885 return 0;
8cfdc000
ZA		 6886}
6887
b820cc0c
ZA		 6888static void kvm_timer_init(void)
6889{
c285545f 6890 max_tsc_khz = tsc_khz;
460dd42e 6891
b820cc0c 6892 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6893#ifdef CONFIG_CPU_FREQ
6894 struct cpufreq_policy policy;
758f588d
BP		 6895 int cpu;
6896
c285545f 6897 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6898 cpu = get_cpu();
6899 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6900 if (policy.cpuinfo.max_freq)
6901 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6902 put_cpu();
c285545f 6903#endif
b820cc0c
ZA		 6904 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6905 CPUFREQ_TRANSITION_NOTIFIER);
6906 }
460dd42e 6907
73c1b41e 6908 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6909 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6910}
6911
dd60d217
AK		 6912DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6913EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6914
f5132b01 6915int kvm_is_in_guest(void)
ff9d07a0 6916{
086c9855 6917 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6918}
6919
6920static int kvm_is_user_mode(void)
6921{
6922 int user_mode = 3;
dcf46b94 6923
086c9855
AS		 6924 if (__this_cpu_read(current_vcpu))
6925 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6926
ff9d07a0
ZY		 6927 return user_mode != 0;
6928}
6929
6930static unsigned long kvm_get_guest_ip(void)
6931{
6932 unsigned long ip = 0;
dcf46b94 6933
086c9855
AS		 6934 if (__this_cpu_read(current_vcpu))
6935 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6936
ff9d07a0
ZY		 6937 return ip;
6938}
6939
8479e04e
LK		 6940static void kvm_handle_intel_pt_intr(void)
6941{
6942 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6943
6944 kvm_make_request(KVM_REQ_PMI, vcpu);
6945 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6946 (unsigned long *)&vcpu->arch.pmu.global_status);
6947}
6948
ff9d07a0
ZY		 6949static struct perf_guest_info_callbacks kvm_guest_cbs = {
6950 .is_in_guest = kvm_is_in_guest,
6951 .is_user_mode = kvm_is_user_mode,
6952 .get_guest_ip = kvm_get_guest_ip,
8479e04e 6953 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
ff9d07a0
ZY		 6954};
6955
16e8d74d
MT		 6956#ifdef CONFIG_X86_64
6957static void pvclock_gtod_update_fn(struct work_struct *work)
6958{
d828199e
MT		 6959 struct kvm *kvm;
6960
6961 struct kvm_vcpu *vcpu;
6962 int i;
6963
0d9ce162 6964 mutex_lock(&kvm_lock);
d828199e
MT		 6965 list_for_each_entry(kvm, &vm_list, vm_list)
6966 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6967 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6968 atomic_set(&kvm_guest_has_master_clock, 0);
0d9ce162 6969 mutex_unlock(&kvm_lock);
16e8d74d
MT		 6970}
6971
6972static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6973
6974/*
6975 * Notification about pvclock gtod data update.
6976 */
6977static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6978 void *priv)
6979{
6980 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6981 struct timekeeper *tk = priv;
6982
6983 update_pvclock_gtod(tk);
6984
6985 /* disable master clock if host does not trust, or does not
b0c39dc6 6986 * use, TSC based clocksource.
16e8d74d 6987 */
b0c39dc6 6988 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6989 atomic_read(&kvm_guest_has_master_clock) != 0)
6990 queue_work(system_long_wq, &pvclock_gtod_work);
6991
6992 return 0;
6993}
6994
6995static struct notifier_block pvclock_gtod_notifier = {
6996 .notifier_call = pvclock_gtod_notify,
6997};
6998#endif
6999
f8c16bba 7000int kvm_arch_init(void *opaque)
043405e1 7001{
b820cc0c 7002 int r;
6b61edf7 7003 struct kvm_x86_ops *ops = opaque;
f8c16bba 7004
f8c16bba
ZX		 7005 if (kvm_x86_ops) {
7006 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 7007 r = -EEXIST;
7008 goto out;
f8c16bba
ZX		 7009 }
7010
7011 if (!ops->cpu_has_kvm_support()) {
7012 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 7013 r = -EOPNOTSUPP;
7014 goto out;
f8c16bba
ZX		 7015 }
7016 if (ops->disabled_by_bios()) {
7017 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 7018 r = -EOPNOTSUPP;
7019 goto out;
f8c16bba
ZX		 7020 }
7021
b666a4b6
MO		 7022 /*
7023 * KVM explicitly assumes that the guest has an FPU and
7024 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7025 * vCPU's FPU state as a fxregs_state struct.
7026 */
7027 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7028 printk(KERN_ERR "kvm: inadequate fpu\n");
7029 r = -EOPNOTSUPP;
7030 goto out;
7031 }
7032
013f6a5d 7033 r = -ENOMEM;
ed8e4812 7034 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 7035 __alignof__(struct fpu), SLAB_ACCOUNT,
7036 NULL);
7037 if (!x86_fpu_cache) {
7038 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7039 goto out;
7040 }
7041
013f6a5d
MT		 7042 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7043 if (!shared_msrs) {
7044 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 7045 goto out_free_x86_fpu_cache;
013f6a5d
MT		 7046 }
7047
97db56ce
AK		 7048 r = kvm_mmu_module_init();
7049 if (r)
013f6a5d 7050 goto out_free_percpu;
97db56ce 7051
f8c16bba 7052 kvm_x86_ops = ops;
920c8377 7053
7b52345e 7054 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 7055 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 7056 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 7057 kvm_timer_init();
c8076604 7058
ff9d07a0
ZY		 7059 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7060
d366bf7e 7061 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 7062 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7063
c5cc421b 7064 kvm_lapic_init();
0c5f81da
WL		 7065 if (pi_inject_timer == -1)
7066 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
16e8d74d
MT		 7067#ifdef CONFIG_X86_64
7068 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 7069
5fa4ec9c 7070 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 7071 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 7072#endif
7073
f8c16bba 7074 return 0;
56c6d28a 7075
013f6a5d
MT		 7076out_free_percpu:
7077 free_percpu(shared_msrs);
b666a4b6
MO		 7078out_free_x86_fpu_cache:
7079 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7080out:
56c6d28a 7081 return r;
043405e1 7082}
8776e519 7083
f8c16bba
ZX		 7084void kvm_arch_exit(void)
7085{
0092e434 7086#ifdef CONFIG_X86_64
5fa4ec9c 7087 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 7088 clear_hv_tscchange_cb();
7089#endif
cef84c30 7090 kvm_lapic_exit();
ff9d07a0
ZY		 7091 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7092
888d256e
JK		 7093 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7094 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7095 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7096 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7097#ifdef CONFIG_X86_64
7098 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7099#endif
f8c16bba 7100 kvm_x86_ops = NULL;
56c6d28a 7101 kvm_mmu_module_exit();
013f6a5d 7102 free_percpu(shared_msrs);
b666a4b6 7103 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7104}
f8c16bba 7105
5cb56059 7106int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7107{
7108 ++vcpu->stat.halt_exits;
35754c98 7109 if (lapic_in_kernel(vcpu)) {
a4535290 7110 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7111 return 1;
7112 } else {
7113 vcpu->run->exit_reason = KVM_EXIT_HLT;
7114 return 0;
7115 }
7116}
5cb56059
JS		 7117EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7118
7119int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7120{
6affcbed
KH		 7121 int ret = kvm_skip_emulated_instruction(vcpu);
7122 /*
7123 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7124 * KVM_EXIT_DEBUG here.
7125 */
7126 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7127}
8776e519
HB		 7128EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7129
8ef81a9a 7130#ifdef CONFIG_X86_64
55dd00a7
MT		 7131static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7132 unsigned long clock_type)
7133{
7134 struct kvm_clock_pairing clock_pairing;
899a31f5 7135 struct timespec64 ts;
80fbd89c 7136 u64 cycle;
55dd00a7
MT		 7137 int ret;
7138
7139 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7140 return -KVM_EOPNOTSUPP;
7141
7142 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7143 return -KVM_EOPNOTSUPP;
7144
7145 clock_pairing.sec = ts.tv_sec;
7146 clock_pairing.nsec = ts.tv_nsec;
7147 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7148 clock_pairing.flags = 0;
bcbfbd8e 7149 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7150
7151 ret = 0;
7152 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7153 sizeof(struct kvm_clock_pairing)))
7154 ret = -KVM_EFAULT;
7155
7156 return ret;
7157}
8ef81a9a 7158#endif
55dd00a7 7159
6aef266c
SV		 7160/*
7161 * kvm_pv_kick_cpu_op: Kick a vcpu.
7162 *
7163 * @apicid - apicid of vcpu to be kicked.
7164 */
7165static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7166{
24d2166b 7167 struct kvm_lapic_irq lapic_irq;
6aef266c 7168
24d2166b
R		 7169 lapic_irq.shorthand = 0;
7170 lapic_irq.dest_mode = 0;
ebd28fcb 7171 lapic_irq.level = 0;
24d2166b 7172 lapic_irq.dest_id = apicid;
93bbf0b8 7173 lapic_irq.msi_redir_hint = false;
6aef266c 7174
24d2166b 7175 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7176 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7177}
7178
d62caabb
AS		 7179void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7180{
f7589cca
PB		 7181 if (!lapic_in_kernel(vcpu)) {
7182 WARN_ON_ONCE(vcpu->arch.apicv_active);
7183 return;
7184 }
7185 if (!vcpu->arch.apicv_active)
7186 return;
7187
d62caabb
AS		 7188 vcpu->arch.apicv_active = false;
7189 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7190}
7191
71506297
WL		 7192static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7193{
7194 struct kvm_vcpu *target = NULL;
7195 struct kvm_apic_map *map;
7196
7197 rcu_read_lock();
7198 map = rcu_dereference(kvm->arch.apic_map);
7199
7200 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7201 target = map->phys_map[dest_id]->vcpu;
7202
7203 rcu_read_unlock();
7204
7205 if (target)
7206 kvm_vcpu_yield_to(target);
7207}
7208
8776e519
HB		 7209int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7210{
7211 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7212 int op_64_bit;
8776e519 7213
696ca779
RK		 7214 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7215 return kvm_hv_hypercall(vcpu);
55cd8e5a 7216
de3cd117
SC		 7217 nr = kvm_rax_read(vcpu);
7218 a0 = kvm_rbx_read(vcpu);
7219 a1 = kvm_rcx_read(vcpu);
7220 a2 = kvm_rdx_read(vcpu);
7221 a3 = kvm_rsi_read(vcpu);
8776e519 7222
229456fc 7223 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7224
a449c7aa
NA		 7225 op_64_bit = is_64_bit_mode(vcpu);
7226 if (!op_64_bit) {
8776e519
HB		 7227 nr &= 0xFFFFFFFF;
7228 a0 &= 0xFFFFFFFF;
7229 a1 &= 0xFFFFFFFF;
7230 a2 &= 0xFFFFFFFF;
7231 a3 &= 0xFFFFFFFF;
7232 }
7233
07708c4a
JK		 7234 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7235 ret = -KVM_EPERM;
696ca779 7236 goto out;
07708c4a
JK		 7237 }
7238
8776e519 7239 switch (nr) {
b93463aa
AK		 7240 case KVM_HC_VAPIC_POLL_IRQ:
7241 ret = 0;
7242 break;
6aef266c
SV		 7243 case KVM_HC_KICK_CPU:
7244 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7245 ret = 0;
7246 break;
8ef81a9a 7247#ifdef CONFIG_X86_64
55dd00a7
MT		 7248 case KVM_HC_CLOCK_PAIRING:
7249 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7250 break;
1ed199a4 7251#endif
4180bf1b
WL		 7252 case KVM_HC_SEND_IPI:
7253 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7254 break;
71506297
WL		 7255 case KVM_HC_SCHED_YIELD:
7256 kvm_sched_yield(vcpu->kvm, a0);
7257 ret = 0;
7258 break;
8776e519
HB		 7259 default:
7260 ret = -KVM_ENOSYS;
7261 break;
7262 }
696ca779 7263out:
a449c7aa
NA		 7264 if (!op_64_bit)
7265 ret = (u32)ret;
de3cd117 7266 kvm_rax_write(vcpu, ret);
6356ee0c 7267
f11c3a8d 7268 ++vcpu->stat.hypercalls;
6356ee0c 7269 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7270}
7271EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7272
b6785def 7273static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7274{
d6aa1000 7275 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7276 char instruction[3];
5fdbf976 7277 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7278
8776e519 7279 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7280
ce2e852e
DV		 7281 return emulator_write_emulated(ctxt, rip, instruction, 3,
7282 &ctxt->exception);
8776e519
HB		 7283}
7284
851ba692 7285static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7286{
782d422b
MG		 7287 return vcpu->run->request_interrupt_window &&
7288 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7289}
7290
851ba692 7291static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7292{
851ba692
AK		 7293 struct kvm_run *kvm_run = vcpu->run;
7294
91586a3b 7295 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7296 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7297 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7298 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7299 kvm_run->ready_for_interrupt_injection =
7300 pic_in_kernel(vcpu->kvm) ||
782d422b 7301 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7302}
7303
95ba8273
GN		 7304static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7305{
7306 int max_irr, tpr;
7307
7308 if (!kvm_x86_ops->update_cr8_intercept)
7309 return;
7310
bce87cce 7311 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7312 return;
7313
d62caabb
AS		 7314 if (vcpu->arch.apicv_active)
7315 return;
7316
8db3baa2
GN		 7317 if (!vcpu->arch.apic->vapic_addr)
7318 max_irr = kvm_lapic_find_highest_irr(vcpu);
7319 else
7320 max_irr = -1;
95ba8273
GN		 7321
7322 if (max_irr != -1)
7323 max_irr >>= 4;
7324
7325 tpr = kvm_lapic_get_cr8(vcpu);
7326
7327 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7328}
7329
b6b8a145 7330static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7331{
b6b8a145
JK		 7332 int r;
7333
95ba8273 7334 /* try to reinject previous events if any */
664f8e26 7335
1a680e35
LA		 7336 if (vcpu->arch.exception.injected)
7337 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7338 /*
a042c26f
LA		 7339 * Do not inject an NMI or interrupt if there is a pending
7340 * exception. Exceptions and interrupts are recognized at
7341 * instruction boundaries, i.e. the start of an instruction.
7342 * Trap-like exceptions, e.g. #DB, have higher priority than
7343 * NMIs and interrupts, i.e. traps are recognized before an
7344 * NMI/interrupt that's pending on the same instruction.
7345 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7346 * priority, but are only generated (pended) during instruction
7347 * execution, i.e. a pending fault-like exception means the
7348 * fault occurred on the *previous* instruction and must be
7349 * serviced prior to recognizing any new events in order to
7350 * fully complete the previous instruction.
664f8e26 7351 */
1a680e35
LA		 7352 else if (!vcpu->arch.exception.pending) {
7353 if (vcpu->arch.nmi_injected)
664f8e26 7354 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7355 else if (vcpu->arch.interrupt.injected)
664f8e26 7356 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7357 }
7358
1a680e35
LA		 7359 /*
7360 * Call check_nested_events() even if we reinjected a previous event
7361 * in order for caller to determine if it should require immediate-exit
7362 * from L2 to L1 due to pending L1 events which require exit
7363 * from L2 to L1.
7364 */
664f8e26
WL		 7365 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7366 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7367 if (r != 0)
7368 return r;
7369 }
7370
7371 /* try to inject new event if pending */
b59bb7bd 7372 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7373 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7374 vcpu->arch.exception.has_error_code,
7375 vcpu->arch.exception.error_code);
d6e8c854 7376
1a680e35 7377 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7378 vcpu->arch.exception.pending = false;
7379 vcpu->arch.exception.injected = true;
7380
d6e8c854
NA		 7381 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7382 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7383 X86_EFLAGS_RF);
7384
f10c729f
JM		 7385 if (vcpu->arch.exception.nr == DB_VECTOR) {
7386 /*
7387 * This code assumes that nSVM doesn't use
7388 * check_nested_events(). If it does, the
7389 * DR6/DR7 changes should happen before L1
7390 * gets a #VMEXIT for an intercepted #DB in
7391 * L2. (Under VMX, on the other hand, the
7392 * DR6/DR7 changes should not happen in the
7393 * event of a VM-exit to L1 for an intercepted
7394 * #DB in L2.)
7395 */
7396 kvm_deliver_exception_payload(vcpu);
7397 if (vcpu->arch.dr7 & DR7_GD) {
7398 vcpu->arch.dr7 &= ~DR7_GD;
7399 kvm_update_dr7(vcpu);
7400 }
6bdf0662
NA		 7401 }
7402
cfcd20e5 7403 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7404 }
7405
7406 /* Don't consider new event if we re-injected an event */
7407 if (kvm_event_needs_reinjection(vcpu))
7408 return 0;
7409
7410 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7411 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7412 vcpu->arch.smi_pending = false;
52797bf9 7413 ++vcpu->arch.smi_count;
ee2cd4b7 7414 enter_smm(vcpu);
c43203ca 7415 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7416 --vcpu->arch.nmi_pending;
7417 vcpu->arch.nmi_injected = true;
7418 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7419 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7420 /*
7421 * Because interrupts can be injected asynchronously, we are
7422 * calling check_nested_events again here to avoid a race condition.
7423 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7424 * proposal and current concerns. Perhaps we should be setting
7425 * KVM_REQ_EVENT only on certain events and not unconditionally?
7426 */
7427 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7428 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7429 if (r != 0)
7430 return r;
7431 }
95ba8273 7432 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7433 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7434 false);
7435 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7436 }
7437 }
ee2cd4b7 7438
b6b8a145 7439 return 0;
95ba8273
GN		 7440}
7441
7460fb4a
AK		 7442static void process_nmi(struct kvm_vcpu *vcpu)
7443{
7444 unsigned limit = 2;
7445
7446 /*
7447 * x86 is limited to one NMI running, and one NMI pending after it.
7448 * If an NMI is already in progress, limit further NMIs to just one.
7449 * Otherwise, allow two (and we'll inject the first one immediately).
7450 */
7451 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7452 limit = 1;
7453
7454 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7455 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7456 kvm_make_request(KVM_REQ_EVENT, vcpu);
7457}
7458
ee2cd4b7 7459static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7460{
7461 u32 flags = 0;
7462 flags |= seg->g << 23;
7463 flags |= seg->db << 22;
7464 flags |= seg->l << 21;
7465 flags |= seg->avl << 20;
7466 flags |= seg->present << 15;
7467 flags |= seg->dpl << 13;
7468 flags |= seg->s << 12;
7469 flags |= seg->type << 8;
7470 return flags;
7471}
7472
ee2cd4b7 7473static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7474{
7475 struct kvm_segment seg;
7476 int offset;
7477
7478 kvm_get_segment(vcpu, &seg, n);
7479 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7480
7481 if (n < 3)
7482 offset = 0x7f84 + n * 12;
7483 else
7484 offset = 0x7f2c + (n - 3) * 12;
7485
7486 put_smstate(u32, buf, offset + 8, seg.base);
7487 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7488 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7489}
7490
efbb288a 7491#ifdef CONFIG_X86_64
ee2cd4b7 7492static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7493{
7494 struct kvm_segment seg;
7495 int offset;
7496 u16 flags;
7497
7498 kvm_get_segment(vcpu, &seg, n);
7499 offset = 0x7e00 + n * 16;
7500
ee2cd4b7 7501 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7502 put_smstate(u16, buf, offset, seg.selector);
7503 put_smstate(u16, buf, offset + 2, flags);
7504 put_smstate(u32, buf, offset + 4, seg.limit);
7505 put_smstate(u64, buf, offset + 8, seg.base);
7506}
efbb288a 7507#endif
660a5d51 7508
ee2cd4b7 7509static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7510{
7511 struct desc_ptr dt;
7512 struct kvm_segment seg;
7513 unsigned long val;
7514 int i;
7515
7516 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7517 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7518 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7519 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7520
7521 for (i = 0; i < 8; i++)
7522 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7523
7524 kvm_get_dr(vcpu, 6, &val);
7525 put_smstate(u32, buf, 0x7fcc, (u32)val);
7526 kvm_get_dr(vcpu, 7, &val);
7527 put_smstate(u32, buf, 0x7fc8, (u32)val);
7528
7529 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7530 put_smstate(u32, buf, 0x7fc4, seg.selector);
7531 put_smstate(u32, buf, 0x7f64, seg.base);
7532 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7533 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7534
7535 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7536 put_smstate(u32, buf, 0x7fc0, seg.selector);
7537 put_smstate(u32, buf, 0x7f80, seg.base);
7538 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7539 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7540
7541 kvm_x86_ops->get_gdt(vcpu, &dt);
7542 put_smstate(u32, buf, 0x7f74, dt.address);
7543 put_smstate(u32, buf, 0x7f70, dt.size);
7544
7545 kvm_x86_ops->get_idt(vcpu, &dt);
7546 put_smstate(u32, buf, 0x7f58, dt.address);
7547 put_smstate(u32, buf, 0x7f54, dt.size);
7548
7549 for (i = 0; i < 6; i++)
ee2cd4b7 7550 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7551
7552 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7553
7554 /* revision id */
7555 put_smstate(u32, buf, 0x7efc, 0x00020000);
7556 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7557}
7558
b68f3cc7 7559#ifdef CONFIG_X86_64
ee2cd4b7 7560static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7561{
660a5d51
PB		 7562 struct desc_ptr dt;
7563 struct kvm_segment seg;
7564 unsigned long val;
7565 int i;
7566
7567 for (i = 0; i < 16; i++)
7568 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7569
7570 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7571 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7572
7573 kvm_get_dr(vcpu, 6, &val);
7574 put_smstate(u64, buf, 0x7f68, val);
7575 kvm_get_dr(vcpu, 7, &val);
7576 put_smstate(u64, buf, 0x7f60, val);
7577
7578 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7579 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7580 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7581
7582 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7583
7584 /* revision id */
7585 put_smstate(u32, buf, 0x7efc, 0x00020064);
7586
7587 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7588
7589 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7590 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7591 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7592 put_smstate(u32, buf, 0x7e94, seg.limit);
7593 put_smstate(u64, buf, 0x7e98, seg.base);
7594
7595 kvm_x86_ops->get_idt(vcpu, &dt);
7596 put_smstate(u32, buf, 0x7e84, dt.size);
7597 put_smstate(u64, buf, 0x7e88, dt.address);
7598
7599 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7600 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7601 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7602 put_smstate(u32, buf, 0x7e74, seg.limit);
7603 put_smstate(u64, buf, 0x7e78, seg.base);
7604
7605 kvm_x86_ops->get_gdt(vcpu, &dt);
7606 put_smstate(u32, buf, 0x7e64, dt.size);
7607 put_smstate(u64, buf, 0x7e68, dt.address);
7608
7609 for (i = 0; i < 6; i++)
ee2cd4b7 7610 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7611}
b68f3cc7 7612#endif
660a5d51 7613
ee2cd4b7 7614static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7615{
660a5d51 7616 struct kvm_segment cs, ds;
18c3626e 7617 struct desc_ptr dt;
660a5d51
PB		 7618 char buf[512];
7619 u32 cr0;
7620
660a5d51 7621 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7622 memset(buf, 0, 512);
b68f3cc7 7623#ifdef CONFIG_X86_64
d6321d49 7624 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7625 enter_smm_save_state_64(vcpu, buf);
660a5d51 7626 else
b68f3cc7 7627#endif
ee2cd4b7 7628 enter_smm_save_state_32(vcpu, buf);
660a5d51 7629
0234bf88
LP		 7630 /*
7631 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7632 * vCPU state (e.g. leave guest mode) after we've saved the state into
7633 * the SMM state-save area.
7634 */
7635 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7636
7637 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7638 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7639
7640 if (kvm_x86_ops->get_nmi_mask(vcpu))
7641 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7642 else
7643 kvm_x86_ops->set_nmi_mask(vcpu, true);
7644
7645 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7646 kvm_rip_write(vcpu, 0x8000);
7647
7648 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7649 kvm_x86_ops->set_cr0(vcpu, cr0);
7650 vcpu->arch.cr0 = cr0;
7651
7652 kvm_x86_ops->set_cr4(vcpu, 0);
7653
18c3626e
PB		 7654 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7655 dt.address = dt.size = 0;
7656 kvm_x86_ops->set_idt(vcpu, &dt);
7657
660a5d51
PB		 7658 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7659
7660 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7661 cs.base = vcpu->arch.smbase;
7662
7663 ds.selector = 0;
7664 ds.base = 0;
7665
7666 cs.limit = ds.limit = 0xffffffff;
7667 cs.type = ds.type = 0x3;
7668 cs.dpl = ds.dpl = 0;
7669 cs.db = ds.db = 0;
7670 cs.s = ds.s = 1;
7671 cs.l = ds.l = 0;
7672 cs.g = ds.g = 1;
7673 cs.avl = ds.avl = 0;
7674 cs.present = ds.present = 1;
7675 cs.unusable = ds.unusable = 0;
7676 cs.padding = ds.padding = 0;
7677
7678 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7679 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7680 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7681 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7682 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7683 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7684
b68f3cc7 7685#ifdef CONFIG_X86_64
d6321d49 7686 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7687 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7688#endif
660a5d51
PB		 7689
7690 kvm_update_cpuid(vcpu);
7691 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7692}
7693
ee2cd4b7 7694static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7695{
7696 vcpu->arch.smi_pending = true;
7697 kvm_make_request(KVM_REQ_EVENT, vcpu);
7698}
7699
2860c4b1
PB		 7700void kvm_make_scan_ioapic_request(struct kvm *kvm)
7701{
7702 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7703}
7704
3d81bc7e 7705static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7706{
dcbd3e49 7707 if (!kvm_apic_present(vcpu))
3d81bc7e 7708 return;
c7c9c56c 7709
6308630b 7710 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7711
b053b2ae 7712 if (irqchip_split(vcpu->kvm))
6308630b 7713 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7714 else {
fa59cc00 7715 if (vcpu->arch.apicv_active)
d62caabb 7716 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7717 if (ioapic_in_kernel(vcpu->kvm))
7718 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7719 }
e40ff1d6
LA		 7720
7721 if (is_guest_mode(vcpu))
7722 vcpu->arch.load_eoi_exitmap_pending = true;
7723 else
7724 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7725}
7726
7727static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7728{
7729 u64 eoi_exit_bitmap[4];
7730
7731 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7732 return;
7733
5c919412
AS		 7734 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7735 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7736 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7737}
7738
93065ac7
MH		 7739int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7740 unsigned long start, unsigned long end,
7741 bool blockable)
b1394e74
RK		 7742{
7743 unsigned long apic_address;
7744
7745 /*
7746 * The physical address of apic access page is stored in the VMCS.
7747 * Update it when it becomes invalid.
7748 */
7749 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7750 if (start <= apic_address && apic_address < end)
7751 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7752
7753 return 0;
b1394e74
RK		 7754}
7755
4256f43f
TC		 7756void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7757{
c24ae0dc
TC		 7758 struct page *page = NULL;
7759
35754c98 7760 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7761 return;
7762
4256f43f
TC		 7763 if (!kvm_x86_ops->set_apic_access_page_addr)
7764 return;
7765
c24ae0dc 7766 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7767 if (is_error_page(page))
7768 return;
c24ae0dc
TC		 7769 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7770
7771 /*
7772 * Do not pin apic access page in memory, the MMU notifier
7773 * will call us again if it is migrated or swapped out.
7774 */
7775 put_page(page);
4256f43f
TC		 7776}
7777EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7778
d264ee0c
SC		 7779void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7780{
7781 smp_send_reschedule(vcpu->cpu);
7782}
7783EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7784
9357d939 7785/*
362c698f 7786 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7787 * exiting to the userspace. Otherwise, the value will be returned to the
7788 * userspace.
7789 */
851ba692 7790static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7791{
7792 int r;
62a193ed
MG		 7793 bool req_int_win =
7794 dm_request_for_irq_injection(vcpu) &&
7795 kvm_cpu_accept_dm_intr(vcpu);
7796
730dca42 7797 bool req_immediate_exit = false;
b6c7a5dc 7798
2fa6e1e1 7799 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7800 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7801 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7802 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7803 kvm_mmu_unload(vcpu);
a8eeb04a 7804 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7805 __kvm_migrate_timers(vcpu);
d828199e
MT		 7806 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7807 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7808 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7809 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7810 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7811 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7812 if (unlikely(r))
7813 goto out;
7814 }
a8eeb04a 7815 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7816 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7817 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7818 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7819 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7820 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7821 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7822 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7823 r = 0;
7824 goto out;
7825 }
a8eeb04a 7826 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7827 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7828 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7829 r = 0;
7830 goto out;
7831 }
af585b92
GN		 7832 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7833 /* Page is swapped out. Do synthetic halt */
7834 vcpu->arch.apf.halted = true;
7835 r = 1;
7836 goto out;
7837 }
c9aaa895
GC		 7838 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7839 record_steal_time(vcpu);
64d60670
PB		 7840 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7841 process_smi(vcpu);
7460fb4a
AK		 7842 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7843 process_nmi(vcpu);
f5132b01 7844 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7845 kvm_pmu_handle_event(vcpu);
f5132b01 7846 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7847 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7848 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7849 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7850 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7851 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7852 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7853 vcpu->run->eoi.vector =
7854 vcpu->arch.pending_ioapic_eoi;
7855 r = 0;
7856 goto out;
7857 }
7858 }
3d81bc7e
YZ		 7859 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7860 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7861 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7862 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7863 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7864 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7865 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7866 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7867 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7868 r = 0;
7869 goto out;
7870 }
e516cebb
AS		 7871 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7872 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7873 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7874 r = 0;
7875 goto out;
7876 }
db397571
AS		 7877 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7878 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7879 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7880 r = 0;
7881 goto out;
7882 }
f3b138c5
AS		 7883
7884 /*
7885 * KVM_REQ_HV_STIMER has to be processed after
7886 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7887 * depend on the guest clock being up-to-date
7888 */
1f4b34f8
AS		 7889 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7890 kvm_hv_process_stimers(vcpu);
2f52d58c 7891 }
b93463aa 7892
b463a6f7 7893 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7894 ++vcpu->stat.req_event;
66450a21
JK		 7895 kvm_apic_accept_events(vcpu);
7896 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7897 r = 1;
7898 goto out;
7899 }
7900
b6b8a145
JK		 7901 if (inject_pending_event(vcpu, req_int_win) != 0)
7902 req_immediate_exit = true;
321c5658 7903 else {
cc3d967f 7904 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7905 *
cc3d967f
LP		 7906 * SMIs have three cases:
7907 * 1) They can be nested, and then there is nothing to
7908 * do here because RSM will cause a vmexit anyway.
7909 * 2) There is an ISA-specific reason why SMI cannot be
7910 * injected, and the moment when this changes can be
7911 * intercepted.
7912 * 3) Or the SMI can be pending because
7913 * inject_pending_event has completed the injection
7914 * of an IRQ or NMI from the previous vmexit, and
7915 * then we request an immediate exit to inject the
7916 * SMI.
c43203ca
PB		 7917 */
7918 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7919 if (!kvm_x86_ops->enable_smi_window(vcpu))
7920 req_immediate_exit = true;
321c5658
YS		 7921 if (vcpu->arch.nmi_pending)
7922 kvm_x86_ops->enable_nmi_window(vcpu);
7923 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7924 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7925 WARN_ON(vcpu->arch.exception.pending);
321c5658 7926 }
b463a6f7
AK		 7927
7928 if (kvm_lapic_enabled(vcpu)) {
7929 update_cr8_intercept(vcpu);
7930 kvm_lapic_sync_to_vapic(vcpu);
7931 }
7932 }
7933
d8368af8
AK		 7934 r = kvm_mmu_reload(vcpu);
7935 if (unlikely(r)) {
d905c069 7936 goto cancel_injection;
d8368af8
AK		 7937 }
7938
b6c7a5dc
HB		 7939 preempt_disable();
7940
7941 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7942
7943 /*
7944 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7945 * IPI are then delayed after guest entry, which ensures that they
7946 * result in virtual interrupt delivery.
7947 */
7948 local_irq_disable();
6b7e2d09
XG		 7949 vcpu->mode = IN_GUEST_MODE;
7950
01b71917
MT		 7951 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7952
0f127d12 7953 /*
b95234c8 7954 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7955 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 7956 *
81b01667 7957 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 7958 * pairs with the memory barrier implicit in pi_test_and_set_on
7959 * (see vmx_deliver_posted_interrupt).
7960 *
7961 * 3) This also orders the write to mode from any reads to the page
7962 * tables done while the VCPU is running. Please see the comment
7963 * in kvm_flush_remote_tlbs.
6b7e2d09 7964 */
01b71917 7965 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7966
b95234c8
PB		 7967 /*
7968 * This handles the case where a posted interrupt was
7969 * notified with kvm_vcpu_kick.
7970 */
fa59cc00
LA		 7971 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7972 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7973
2fa6e1e1 7974 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7975 || need_resched() || signal_pending(current)) {
6b7e2d09 7976 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7977 smp_wmb();
6c142801
AK		 7978 local_irq_enable();
7979 preempt_enable();
01b71917 7980 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7981 r = 1;
d905c069 7982 goto cancel_injection;
6c142801
AK		 7983 }
7984
c43203ca
PB		 7985 if (req_immediate_exit) {
7986 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7987 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7988 }
d6185f20 7989
8b89fe1f 7990 trace_kvm_entry(vcpu->vcpu_id);
6edaa530 7991 guest_enter_irqoff();
b6c7a5dc 7992
5f409e20
RR		 7993 fpregs_assert_state_consistent();
7994 if (test_thread_flag(TIF_NEED_FPU_LOAD))
7995 switch_fpu_return();
7996
42dbaa5a 7997 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7998 set_debugreg(0, 7);
7999 set_debugreg(vcpu->arch.eff_db[0], 0);
8000 set_debugreg(vcpu->arch.eff_db[1], 1);
8001 set_debugreg(vcpu->arch.eff_db[2], 2);
8002 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 8003 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 8004 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 8005 }
b6c7a5dc 8006
851ba692 8007 kvm_x86_ops->run(vcpu);
b6c7a5dc 8008
c77fb5fe
PB		 8009 /*
8010 * Do this here before restoring debug registers on the host. And
8011 * since we do this before handling the vmexit, a DR access vmexit
8012 * can (a) read the correct value of the debug registers, (b) set
8013 * KVM_DEBUGREG_WONT_EXIT again.
8014 */
8015 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 8016 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8017 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 8018 kvm_update_dr0123(vcpu);
8019 kvm_update_dr6(vcpu);
8020 kvm_update_dr7(vcpu);
8021 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 8022 }
8023
24f1e32c
FW		 8024 /*
8025 * If the guest has used debug registers, at least dr7
8026 * will be disabled while returning to the host.
8027 * If we don't have active breakpoints in the host, we don't
8028 * care about the messed up debug address registers. But if
8029 * we have some of them active, restore the old state.
8030 */
59d8eb53 8031 if (hw_breakpoint_active())
24f1e32c 8032 hw_breakpoint_restore();
42dbaa5a 8033
4ba76538 8034 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 8035
6b7e2d09 8036 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8037 smp_wmb();
a547c6db 8038
95b5a48c 8039 kvm_x86_ops->handle_exit_irqoff(vcpu);
b6c7a5dc 8040
d7a08882
SC		 8041 /*
8042 * Consume any pending interrupts, including the possible source of
8043 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8044 * An instruction is required after local_irq_enable() to fully unblock
8045 * interrupts on processors that implement an interrupt shadow, the
8046 * stat.exits increment will do nicely.
8047 */
8048 kvm_before_interrupt(vcpu);
8049 local_irq_enable();
b6c7a5dc 8050 ++vcpu->stat.exits;
d7a08882
SC		 8051 local_irq_disable();
8052 kvm_after_interrupt(vcpu);
b6c7a5dc 8053
f2485b3e 8054 guest_exit_irqoff();
ec0671d5
WL		 8055 if (lapic_in_kernel(vcpu)) {
8056 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8057 if (delta != S64_MIN) {
8058 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8059 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8060 }
8061 }
b6c7a5dc 8062
f2485b3e 8063 local_irq_enable();
b6c7a5dc
HB		 8064 preempt_enable();
8065
f656ce01 8066 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 8067
b6c7a5dc
HB		 8068 /*
8069 * Profile KVM exit RIPs:
8070 */
8071 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 8072 unsigned long rip = kvm_rip_read(vcpu);
8073 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 8074 }
8075
cc578287
ZA		 8076 if (unlikely(vcpu->arch.tsc_always_catchup))
8077 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 8078
5cfb1d5a
MT		 8079 if (vcpu->arch.apic_attention)
8080 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 8081
618232e2 8082 vcpu->arch.gpa_available = false;
851ba692 8083 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 8084 return r;
8085
8086cancel_injection:
8087 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 8088 if (unlikely(vcpu->arch.apic_attention))
8089 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 8090out:
8091 return r;
8092}
b6c7a5dc 8093
362c698f
PB		 8094static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8095{
bf9f6ac8
FW		 8096 if (!kvm_arch_vcpu_runnable(vcpu) &&
8097 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 8098 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8099 kvm_vcpu_block(vcpu);
8100 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 8101
8102 if (kvm_x86_ops->post_block)
8103 kvm_x86_ops->post_block(vcpu);
8104
9c8fd1ba
PB		 8105 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8106 return 1;
8107 }
362c698f
PB		 8108
8109 kvm_apic_accept_events(vcpu);
8110 switch(vcpu->arch.mp_state) {
8111 case KVM_MP_STATE_HALTED:
8112 vcpu->arch.pv.pv_unhalted = false;
8113 vcpu->arch.mp_state =
8114 KVM_MP_STATE_RUNNABLE;
b2869f28 8115 /* fall through */
362c698f
PB		 8116 case KVM_MP_STATE_RUNNABLE:
8117 vcpu->arch.apf.halted = false;
8118 break;
8119 case KVM_MP_STATE_INIT_RECEIVED:
8120 break;
8121 default:
8122 return -EINTR;
8123 break;
8124 }
8125 return 1;
8126}
09cec754 8127
5d9bc648
PB		 8128static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8129{
0ad3bed6
PB		 8130 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8131 kvm_x86_ops->check_nested_events(vcpu, false);
8132
5d9bc648
PB		 8133 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8134 !vcpu->arch.apf.halted);
8135}
8136
362c698f 8137static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8138{
8139 int r;
f656ce01 8140 struct kvm *kvm = vcpu->kvm;
d7690175 8141
f656ce01 8142 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8143 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8144
362c698f 8145 for (;;) {
58f800d5 8146 if (kvm_vcpu_running(vcpu)) {
851ba692 8147 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8148 } else {
362c698f 8149 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8150 }
8151
09cec754
GN		 8152 if (r <= 0)
8153 break;
8154
72875d8a 8155 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8156 if (kvm_cpu_has_pending_timer(vcpu))
8157 kvm_inject_pending_timer_irqs(vcpu);
8158
782d422b
MG		 8159 if (dm_request_for_irq_injection(vcpu) &&
8160 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8161 r = 0;
8162 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8163 ++vcpu->stat.request_irq_exits;
362c698f 8164 break;
09cec754 8165 }
af585b92
GN		 8166
8167 kvm_check_async_pf_completion(vcpu);
8168
09cec754
GN		 8169 if (signal_pending(current)) {
8170 r = -EINTR;
851ba692 8171 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8172 ++vcpu->stat.signal_exits;
362c698f 8173 break;
09cec754
GN		 8174 }
8175 if (need_resched()) {
f656ce01 8176 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8177 cond_resched();
f656ce01 8178 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8179 }
b6c7a5dc
HB		 8180 }
8181
f656ce01 8182 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8183
8184 return r;
8185}
8186
716d51ab
GN		 8187static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8188{
8189 int r;
8190 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8191 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 8192 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8193 if (r != EMULATE_DONE)
8194 return 0;
8195 return 1;
8196}
8197
8198static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8199{
8200 BUG_ON(!vcpu->arch.pio.count);
8201
8202 return complete_emulated_io(vcpu);
8203}
8204
f78146b0
AK		 8205/*
8206 * Implements the following, as a state machine:
8207 *
8208 * read:
8209 * for each fragment
87da7e66
XG		 8210 * for each mmio piece in the fragment
8211 * write gpa, len
8212 * exit
8213 * copy data
f78146b0
AK		 8214 * execute insn
8215 *
8216 * write:
8217 * for each fragment
87da7e66
XG		 8218 * for each mmio piece in the fragment
8219 * write gpa, len
8220 * copy data
8221 * exit
f78146b0 8222 */
716d51ab 8223static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8224{
8225 struct kvm_run *run = vcpu->run;
f78146b0 8226 struct kvm_mmio_fragment *frag;
87da7e66 8227 unsigned len;
5287f194 8228
716d51ab 8229 BUG_ON(!vcpu->mmio_needed);
5287f194 8230
716d51ab 8231 /* Complete previous fragment */
87da7e66
XG		 8232 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8233 len = min(8u, frag->len);
716d51ab 8234 if (!vcpu->mmio_is_write)
87da7e66
XG		 8235 memcpy(frag->data, run->mmio.data, len);
8236
8237 if (frag->len <= 8) {
8238 /* Switch to the next fragment. */
8239 frag++;
8240 vcpu->mmio_cur_fragment++;
8241 } else {
8242 /* Go forward to the next mmio piece. */
8243 frag->data += len;
8244 frag->gpa += len;
8245 frag->len -= len;
8246 }
8247
a08d3b3b 8248 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8249 vcpu->mmio_needed = 0;
0912c977
PB		 8250
8251 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8252 if (vcpu->mmio_is_write)
716d51ab
GN		 8253 return 1;
8254 vcpu->mmio_read_completed = 1;
8255 return complete_emulated_io(vcpu);
8256 }
87da7e66 8257
716d51ab
GN		 8258 run->exit_reason = KVM_EXIT_MMIO;
8259 run->mmio.phys_addr = frag->gpa;
8260 if (vcpu->mmio_is_write)
87da7e66
XG		 8261 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8262 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8263 run->mmio.is_write = vcpu->mmio_is_write;
8264 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8265 return 0;
5287f194
AK		 8266}
8267
822f312d
SAS		 8268/* Swap (qemu) user FPU context for the guest FPU context. */
8269static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8270{
5f409e20
RR		 8271 fpregs_lock();
8272
240c35a3 8273 copy_fpregs_to_fpstate(&current->thread.fpu);
822f312d 8274 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8275 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d 8276 ~XFEATURE_MASK_PKRU);
5f409e20
RR		 8277
8278 fpregs_mark_activate();
8279 fpregs_unlock();
8280
822f312d
SAS		 8281 trace_kvm_fpu(1);
8282}
8283
8284/* When vcpu_run ends, restore user space FPU context. */
8285static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8286{
5f409e20
RR		 8287 fpregs_lock();
8288
b666a4b6 8289 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
240c35a3 8290 copy_kernel_to_fpregs(&current->thread.fpu.state);
5f409e20
RR		 8291
8292 fpregs_mark_activate();
8293 fpregs_unlock();
8294
822f312d
SAS		 8295 ++vcpu->stat.fpu_reload;
8296 trace_kvm_fpu(0);
8297}
8298
b6c7a5dc
HB		 8299int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8300{
8301 int r;
b6c7a5dc 8302
accb757d 8303 vcpu_load(vcpu);
20b7035c 8304 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8305 kvm_load_guest_fpu(vcpu);
8306
a4535290 8307 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8308 if (kvm_run->immediate_exit) {
8309 r = -EINTR;
8310 goto out;
8311 }
b6c7a5dc 8312 kvm_vcpu_block(vcpu);
66450a21 8313 kvm_apic_accept_events(vcpu);
72875d8a 8314 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8315 r = -EAGAIN;
a0595000
JS		 8316 if (signal_pending(current)) {
8317 r = -EINTR;
8318 vcpu->run->exit_reason = KVM_EXIT_INTR;
8319 ++vcpu->stat.signal_exits;
8320 }
ac9f6dc0 8321 goto out;
b6c7a5dc
HB		 8322 }
8323
01643c51
KH		 8324 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8325 r = -EINVAL;
8326 goto out;
8327 }
8328
8329 if (vcpu->run->kvm_dirty_regs) {
8330 r = sync_regs(vcpu);
8331 if (r != 0)
8332 goto out;
8333 }
8334
b6c7a5dc 8335 /* re-sync apic's tpr */
35754c98 8336 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8337 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8338 r = -EINVAL;
8339 goto out;
8340 }
8341 }
b6c7a5dc 8342
716d51ab
GN		 8343 if (unlikely(vcpu->arch.complete_userspace_io)) {
8344 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8345 vcpu->arch.complete_userspace_io = NULL;
8346 r = cui(vcpu);
8347 if (r <= 0)
5663d8f9 8348 goto out;
716d51ab
GN		 8349 } else
8350 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8351
460df4c1
PB		 8352 if (kvm_run->immediate_exit)
8353 r = -EINTR;
8354 else
8355 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8356
8357out:
5663d8f9 8358 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8359 if (vcpu->run->kvm_valid_regs)
8360 store_regs(vcpu);
f1d86e46 8361 post_kvm_run_save(vcpu);
20b7035c 8362 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8363
accb757d 8364 vcpu_put(vcpu);
b6c7a5dc
HB		 8365 return r;
8366}
8367
01643c51 8368static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8369{
7ae441ea
GN		 8370 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8371 /*
8372 * We are here if userspace calls get_regs() in the middle of
8373 * instruction emulation. Registers state needs to be copied
4a969980 8374 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8375 * that usually, but some bad designed PV devices (vmware
8376 * backdoor interface) need this to work
8377 */
dd856efa 8378 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8379 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8380 }
de3cd117
SC		 8381 regs->rax = kvm_rax_read(vcpu);
8382 regs->rbx = kvm_rbx_read(vcpu);
8383 regs->rcx = kvm_rcx_read(vcpu);
8384 regs->rdx = kvm_rdx_read(vcpu);
8385 regs->rsi = kvm_rsi_read(vcpu);
8386 regs->rdi = kvm_rdi_read(vcpu);
e9c16c78 8387 regs->rsp = kvm_rsp_read(vcpu);
de3cd117 8388 regs->rbp = kvm_rbp_read(vcpu);
b6c7a5dc 8389#ifdef CONFIG_X86_64
de3cd117
SC		 8390 regs->r8 = kvm_r8_read(vcpu);
8391 regs->r9 = kvm_r9_read(vcpu);
8392 regs->r10 = kvm_r10_read(vcpu);
8393 regs->r11 = kvm_r11_read(vcpu);
8394 regs->r12 = kvm_r12_read(vcpu);
8395 regs->r13 = kvm_r13_read(vcpu);
8396 regs->r14 = kvm_r14_read(vcpu);
8397 regs->r15 = kvm_r15_read(vcpu);
b6c7a5dc
HB		 8398#endif
8399
5fdbf976 8400 regs->rip = kvm_rip_read(vcpu);
91586a3b 8401 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8402}
b6c7a5dc 8403
01643c51
KH		 8404int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8405{
8406 vcpu_load(vcpu);
8407 __get_regs(vcpu, regs);
1fc9b76b 8408 vcpu_put(vcpu);
b6c7a5dc
HB		 8409 return 0;
8410}
8411
01643c51 8412static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8413{
7ae441ea
GN		 8414 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8415 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8416
de3cd117
SC		 8417 kvm_rax_write(vcpu, regs->rax);
8418 kvm_rbx_write(vcpu, regs->rbx);
8419 kvm_rcx_write(vcpu, regs->rcx);
8420 kvm_rdx_write(vcpu, regs->rdx);
8421 kvm_rsi_write(vcpu, regs->rsi);
8422 kvm_rdi_write(vcpu, regs->rdi);
e9c16c78 8423 kvm_rsp_write(vcpu, regs->rsp);
de3cd117 8424 kvm_rbp_write(vcpu, regs->rbp);
b6c7a5dc 8425#ifdef CONFIG_X86_64
de3cd117
SC		 8426 kvm_r8_write(vcpu, regs->r8);
8427 kvm_r9_write(vcpu, regs->r9);
8428 kvm_r10_write(vcpu, regs->r10);
8429 kvm_r11_write(vcpu, regs->r11);
8430 kvm_r12_write(vcpu, regs->r12);
8431 kvm_r13_write(vcpu, regs->r13);
8432 kvm_r14_write(vcpu, regs->r14);
8433 kvm_r15_write(vcpu, regs->r15);
b6c7a5dc
HB		 8434#endif
8435
5fdbf976 8436 kvm_rip_write(vcpu, regs->rip);
d73235d1 8437 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8438
b4f14abd
JK		 8439 vcpu->arch.exception.pending = false;
8440
3842d135 8441 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8442}
3842d135 8443
01643c51
KH		 8444int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8445{
8446 vcpu_load(vcpu);
8447 __set_regs(vcpu, regs);
875656fe 8448 vcpu_put(vcpu);
b6c7a5dc
HB		 8449 return 0;
8450}
8451
b6c7a5dc
HB		 8452void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8453{
8454 struct kvm_segment cs;
8455
3e6e0aab 8456 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8457 *db = cs.db;
8458 *l = cs.l;
8459}
8460EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8461
01643c51 8462static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8463{
89a27f4d 8464 struct desc_ptr dt;
b6c7a5dc 8465
3e6e0aab
GT		 8466 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8467 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8468 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8469 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8470 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8471 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8472
3e6e0aab
GT		 8473 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8474 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8475
8476 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8477 sregs->idt.limit = dt.size;
8478 sregs->idt.base = dt.address;
b6c7a5dc 8479 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8480 sregs->gdt.limit = dt.size;
8481 sregs->gdt.base = dt.address;
b6c7a5dc 8482
4d4ec087 8483 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8484 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8485 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8486 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8487 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8488 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8489 sregs->apic_base = kvm_get_apic_base(vcpu);
8490
0e96f31e 8491 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8492
04140b41 8493 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8494 set_bit(vcpu->arch.interrupt.nr,
8495 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8496}
16d7a191 8497
01643c51
KH		 8498int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8499 struct kvm_sregs *sregs)
8500{
8501 vcpu_load(vcpu);
8502 __get_sregs(vcpu, sregs);
bcdec41c 8503 vcpu_put(vcpu);
b6c7a5dc
HB		 8504 return 0;
8505}
8506
62d9f0db
MT		 8507int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8508 struct kvm_mp_state *mp_state)
8509{
fd232561
CD		 8510 vcpu_load(vcpu);
8511
66450a21 8512 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8513 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8514 vcpu->arch.pv.pv_unhalted)
8515 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8516 else
8517 mp_state->mp_state = vcpu->arch.mp_state;
8518
fd232561 8519 vcpu_put(vcpu);
62d9f0db
MT		 8520 return 0;
8521}
8522
8523int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8524 struct kvm_mp_state *mp_state)
8525{
e83dff5e
CD		 8526 int ret = -EINVAL;
8527
8528 vcpu_load(vcpu);
8529
bce87cce 8530 if (!lapic_in_kernel(vcpu) &&
66450a21 8531 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8532 goto out;
66450a21 8533
28bf2888
DH		 8534 /* INITs are latched while in SMM */
8535 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8536 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8537 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8538 goto out;
28bf2888 8539
66450a21
JK		 8540 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8541 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8542 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8543 } else
8544 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8545 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8546
8547 ret = 0;
8548out:
8549 vcpu_put(vcpu);
8550 return ret;
62d9f0db
MT		 8551}
8552
7f3d35fd
KW		 8553int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8554 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8555{
9d74191a 8556 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8557 int ret;
e01c2426 8558
8ec4722d 8559 init_emulate_ctxt(vcpu);
c697518a 8560
7f3d35fd 8561 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8562 has_error_code, error_code);
c697518a 8563
c697518a 8564 if (ret)
19d04437 8565 return EMULATE_FAIL;
37817f29 8566
9d74191a
TY		 8567 kvm_rip_write(vcpu, ctxt->eip);
8568 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8569 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8570 return EMULATE_DONE;
37817f29
IE		 8571}
8572EXPORT_SYMBOL_GPL(kvm_task_switch);
8573
3140c156 8574static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8575{
74fec5b9
TL		 8576 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8577 (sregs->cr4 & X86_CR4_OSXSAVE))
8578 return -EINVAL;
8579
37b95951 8580 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8581 /*
8582 * When EFER.LME and CR0.PG are set, the processor is in
8583 * 64-bit mode (though maybe in a 32-bit code segment).
8584 * CR4.PAE and EFER.LMA must be set.
8585 */
37b95951 8586 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8587 || !(sregs->efer & EFER_LMA))
8588 return -EINVAL;
8589 } else {
8590 /*
8591 * Not in 64-bit mode: EFER.LMA is clear and the code
8592 * segment cannot be 64-bit.
8593 */
8594 if (sregs->efer & EFER_LMA || sregs->cs.l)
8595 return -EINVAL;
8596 }
8597
8598 return 0;
8599}
8600
01643c51 8601static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8602{
58cb628d 8603 struct msr_data apic_base_msr;
b6c7a5dc 8604 int mmu_reset_needed = 0;
c4d21882 8605 int cpuid_update_needed = 0;
63f42e02 8606 int pending_vec, max_bits, idx;
89a27f4d 8607 struct desc_ptr dt;
b4ef9d4e
CD		 8608 int ret = -EINVAL;
8609
f2981033 8610 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8611 goto out;
f2981033 8612
d3802286
JM		 8613 apic_base_msr.data = sregs->apic_base;
8614 apic_base_msr.host_initiated = true;
8615 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8616 goto out;
6d1068b3 8617
89a27f4d
GN		 8618 dt.size = sregs->idt.limit;
8619 dt.address = sregs->idt.base;
b6c7a5dc 8620 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8621 dt.size = sregs->gdt.limit;
8622 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8623 kvm_x86_ops->set_gdt(vcpu, &dt);
8624
ad312c7c 8625 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8626 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8627 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8628 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8629
2d3ad1f4 8630 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8631
f6801dff 8632 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8633 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8634
4d4ec087 8635 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8636 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8637 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8638
fc78f519 8639 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8640 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8641 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8642 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8643 if (cpuid_update_needed)
00b27a3e 8644 kvm_update_cpuid(vcpu);
63f42e02
XG		 8645
8646 idx = srcu_read_lock(&vcpu->kvm->srcu);
bf03d4f9 8647 if (is_pae_paging(vcpu)) {
9f8fe504 8648 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8649 mmu_reset_needed = 1;
8650 }
63f42e02 8651 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8652
8653 if (mmu_reset_needed)
8654 kvm_mmu_reset_context(vcpu);
8655
a50abc3b 8656 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8657 pending_vec = find_first_bit(
8658 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8659 if (pending_vec < max_bits) {
66fd3f7f 8660 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8661 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8662 }
8663
3e6e0aab
GT		 8664 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8665 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8666 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8667 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8668 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8669 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8670
3e6e0aab
GT		 8671 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8672 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8673
5f0269f5
ME		 8674 update_cr8_intercept(vcpu);
8675
9c3e4aab 8676 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8677 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8678 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8679 !is_protmode(vcpu))
9c3e4aab
MT		 8680 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8681
3842d135
AK		 8682 kvm_make_request(KVM_REQ_EVENT, vcpu);
8683
b4ef9d4e
CD		 8684 ret = 0;
8685out:
01643c51
KH		 8686 return ret;
8687}
8688
8689int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8690 struct kvm_sregs *sregs)
8691{
8692 int ret;
8693
8694 vcpu_load(vcpu);
8695 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8696 vcpu_put(vcpu);
8697 return ret;
b6c7a5dc
HB		 8698}
8699
d0bfb940
JK		 8700int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8701 struct kvm_guest_debug *dbg)
b6c7a5dc 8702{
355be0b9 8703 unsigned long rflags;
ae675ef0 8704 int i, r;
b6c7a5dc 8705
66b56562
CD		 8706 vcpu_load(vcpu);
8707
4f926bf2
JK		 8708 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8709 r = -EBUSY;
8710 if (vcpu->arch.exception.pending)
2122ff5e 8711 goto out;
4f926bf2
JK		 8712 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8713 kvm_queue_exception(vcpu, DB_VECTOR);
8714 else
8715 kvm_queue_exception(vcpu, BP_VECTOR);
8716 }
8717
91586a3b
JK		 8718 /*
8719 * Read rflags as long as potentially injected trace flags are still
8720 * filtered out.
8721 */
8722 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8723
8724 vcpu->guest_debug = dbg->control;
8725 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8726 vcpu->guest_debug = 0;
8727
8728 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8729 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8730 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8731 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8732 } else {
8733 for (i = 0; i < KVM_NR_DB_REGS; i++)
8734 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8735 }
c8639010 8736 kvm_update_dr7(vcpu);
ae675ef0 8737
f92653ee
JK		 8738 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8739 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8740 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8741
91586a3b
JK		 8742 /*
8743 * Trigger an rflags update that will inject or remove the trace
8744 * flags.
8745 */
8746 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8747
a96036b8 8748 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8749
4f926bf2 8750 r = 0;
d0bfb940 8751
2122ff5e 8752out:
66b56562 8753 vcpu_put(vcpu);
b6c7a5dc
HB		 8754 return r;
8755}
8756
8b006791
ZX		 8757/*
8758 * Translate a guest virtual address to a guest physical address.
8759 */
8760int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8761 struct kvm_translation *tr)
8762{
8763 unsigned long vaddr = tr->linear_address;
8764 gpa_t gpa;
f656ce01 8765 int idx;
8b006791 8766
1da5b61d
CD		 8767 vcpu_load(vcpu);
8768
f656ce01 8769 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8770 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8771 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8772 tr->physical_address = gpa;
8773 tr->valid = gpa != UNMAPPED_GVA;
8774 tr->writeable = 1;
8775 tr->usermode = 0;
8b006791 8776
1da5b61d 8777 vcpu_put(vcpu);
8b006791
ZX		 8778 return 0;
8779}
8780
d0752060
HB		 8781int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8782{
1393123e 8783 struct fxregs_state *fxsave;
d0752060 8784
1393123e 8785 vcpu_load(vcpu);
d0752060 8786
b666a4b6 8787 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8788 memcpy(fpu->fpr, fxsave->st_space, 128);
8789 fpu->fcw = fxsave->cwd;
8790 fpu->fsw = fxsave->swd;
8791 fpu->ftwx = fxsave->twd;
8792 fpu->last_opcode = fxsave->fop;
8793 fpu->last_ip = fxsave->rip;
8794 fpu->last_dp = fxsave->rdp;
0e96f31e 8795 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8796
1393123e 8797 vcpu_put(vcpu);
d0752060
HB		 8798 return 0;
8799}
8800
8801int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8802{
6a96bc7f
CD		 8803 struct fxregs_state *fxsave;
8804
8805 vcpu_load(vcpu);
8806
b666a4b6 8807 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8808
d0752060
HB		 8809 memcpy(fxsave->st_space, fpu->fpr, 128);
8810 fxsave->cwd = fpu->fcw;
8811 fxsave->swd = fpu->fsw;
8812 fxsave->twd = fpu->ftwx;
8813 fxsave->fop = fpu->last_opcode;
8814 fxsave->rip = fpu->last_ip;
8815 fxsave->rdp = fpu->last_dp;
0e96f31e 8816 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8817
6a96bc7f 8818 vcpu_put(vcpu);
d0752060
HB		 8819 return 0;
8820}
8821
01643c51
KH		 8822static void store_regs(struct kvm_vcpu *vcpu)
8823{
8824 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8825
8826 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8827 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8828
8829 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8830 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8831
8832 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8833 kvm_vcpu_ioctl_x86_get_vcpu_events(
8834 vcpu, &vcpu->run->s.regs.events);
8835}
8836
8837static int sync_regs(struct kvm_vcpu *vcpu)
8838{
8839 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8840 return -EINVAL;
8841
8842 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8843 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8844 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8845 }
8846 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8847 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8848 return -EINVAL;
8849 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8850 }
8851 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8852 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8853 vcpu, &vcpu->run->s.regs.events))
8854 return -EINVAL;
8855 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8856 }
8857
8858 return 0;
8859}
8860
0ee6a517 8861static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8862{
b666a4b6 8863 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 8864 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 8865 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 8866 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8867
2acf923e
DC		 8868 /*
8869 * Ensure guest xcr0 is valid for loading
8870 */
d91cab78 8871 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8872
ad312c7c 8873 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8874}
d0752060 8875
e9b11c17
ZX		 8876void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8877{
bd768e14
IY		 8878 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8879
12f9a48f 8880 kvmclock_reset(vcpu);
7f1ea208 8881
e9b11c17 8882 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8883 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8884}
8885
8886struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8887 unsigned int id)
8888{
c447e76b
LL		 8889 struct kvm_vcpu *vcpu;
8890
b0c39dc6 8891 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8892 printk_once(KERN_WARNING
8893 "kvm: SMP vm created on host with unstable TSC; "
8894 "guest TSC will not be reliable\n");
c447e76b
LL		 8895
8896 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8897
c447e76b 8898 return vcpu;
26e5215f 8899}
e9b11c17 8900
26e5215f
AK		 8901int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8902{
0cf9135b 8903 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 8904 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 8905 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8906 vcpu_load(vcpu);
d28bc9dd 8907 kvm_vcpu_reset(vcpu, false);
e1732991 8908 kvm_init_mmu(vcpu, false);
e9b11c17 8909 vcpu_put(vcpu);
ec7660cc 8910 return 0;
e9b11c17
ZX		 8911}
8912
31928aa5 8913void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8914{
8fe8ab46 8915 struct msr_data msr;
332967a3 8916 struct kvm *kvm = vcpu->kvm;
42897d86 8917
d3457c87
RK		 8918 kvm_hv_vcpu_postcreate(vcpu);
8919
ec7660cc 8920 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8921 return;
ec7660cc 8922 vcpu_load(vcpu);
8fe8ab46
WA		 8923 msr.data = 0x0;
8924 msr.index = MSR_IA32_TSC;
8925 msr.host_initiated = true;
8926 kvm_write_tsc(vcpu, &msr);
42897d86 8927 vcpu_put(vcpu);
2d5ba19b
MT		 8928
8929 /* poll control enabled by default */
8930 vcpu->arch.msr_kvm_poll_control = 1;
8931
ec7660cc 8932 mutex_unlock(&vcpu->mutex);
42897d86 8933
630994b3
MT		 8934 if (!kvmclock_periodic_sync)
8935 return;
8936
332967a3
AJ		 8937 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8938 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8939}
8940
d40ccc62 8941void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8942{
344d9588
GN		 8943 vcpu->arch.apf.msr_val = 0;
8944
ec7660cc 8945 vcpu_load(vcpu);
e9b11c17
ZX		 8946 kvm_mmu_unload(vcpu);
8947 vcpu_put(vcpu);
8948
8949 kvm_x86_ops->vcpu_free(vcpu);
8950}
8951
d28bc9dd 8952void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8953{
b7e31be3
RK		 8954 kvm_lapic_reset(vcpu, init_event);
8955
e69fab5d
PB		 8956 vcpu->arch.hflags = 0;
8957
c43203ca 8958 vcpu->arch.smi_pending = 0;
52797bf9 8959 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8960 atomic_set(&vcpu->arch.nmi_queued, 0);
8961 vcpu->arch.nmi_pending = 0;
448fa4a9 8962 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8963 kvm_clear_interrupt_queue(vcpu);
8964 kvm_clear_exception_queue(vcpu);
664f8e26 8965 vcpu->arch.exception.pending = false;
448fa4a9 8966
42dbaa5a 8967 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8968 kvm_update_dr0123(vcpu);
6f43ed01 8969 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8970 kvm_update_dr6(vcpu);
42dbaa5a 8971 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8972 kvm_update_dr7(vcpu);
42dbaa5a 8973
1119022c
NA		 8974 vcpu->arch.cr2 = 0;
8975
3842d135 8976 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8977 vcpu->arch.apf.msr_val = 0;
c9aaa895 8978 vcpu->arch.st.msr_val = 0;
3842d135 8979
12f9a48f
GC		 8980 kvmclock_reset(vcpu);
8981
af585b92
GN		 8982 kvm_clear_async_pf_completion_queue(vcpu);
8983 kvm_async_pf_hash_reset(vcpu);
8984 vcpu->arch.apf.halted = false;
3842d135 8985
a554d207
WL		 8986 if (kvm_mpx_supported()) {
8987 void *mpx_state_buffer;
8988
8989 /*
8990 * To avoid have the INIT path from kvm_apic_has_events() that be
8991 * called with loaded FPU and does not let userspace fix the state.
8992 */
f775b13e
RR		 8993 if (init_event)
8994 kvm_put_guest_fpu(vcpu);
b666a4b6 8995 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 8996 XFEATURE_BNDREGS);
a554d207
WL		 8997 if (mpx_state_buffer)
8998 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 8999 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9000 XFEATURE_BNDCSR);
a554d207
WL		 9001 if (mpx_state_buffer)
9002 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 9003 if (init_event)
9004 kvm_load_guest_fpu(vcpu);
a554d207
WL		 9005 }
9006
64d60670 9007 if (!init_event) {
d28bc9dd 9008 kvm_pmu_reset(vcpu);
64d60670 9009 vcpu->arch.smbase = 0x30000;
db2336a8 9010
db2336a8 9011 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 9012
9013 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 9014 }
f5132b01 9015
66f7b72e
JS		 9016 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9017 vcpu->arch.regs_avail = ~0;
9018 vcpu->arch.regs_dirty = ~0;
9019
a554d207
WL		 9020 vcpu->arch.ia32_xss = 0;
9021
d28bc9dd 9022 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 9023}
9024
2b4a273b 9025void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 9026{
9027 struct kvm_segment cs;
9028
9029 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9030 cs.selector = vector << 8;
9031 cs.base = vector << 12;
9032 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9033 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 9034}
9035
13a34e06 9036int kvm_arch_hardware_enable(void)
e9b11c17 9037{
ca84d1a2
ZA		 9038 struct kvm *kvm;
9039 struct kvm_vcpu *vcpu;
9040 int i;
0dd6a6ed
ZA		 9041 int ret;
9042 u64 local_tsc;
9043 u64 max_tsc = 0;
9044 bool stable, backwards_tsc = false;
18863bdd
AK		 9045
9046 kvm_shared_msr_cpu_online();
13a34e06 9047 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 9048 if (ret != 0)
9049 return ret;
9050
4ea1636b 9051 local_tsc = rdtsc();
b0c39dc6 9052 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 9053 list_for_each_entry(kvm, &vm_list, vm_list) {
9054 kvm_for_each_vcpu(i, vcpu, kvm) {
9055 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 9056 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9057 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9058 backwards_tsc = true;
9059 if (vcpu->arch.last_host_tsc > max_tsc)
9060 max_tsc = vcpu->arch.last_host_tsc;
9061 }
9062 }
9063 }
9064
9065 /*
9066 * Sometimes, even reliable TSCs go backwards. This happens on
9067 * platforms that reset TSC during suspend or hibernate actions, but
9068 * maintain synchronization. We must compensate. Fortunately, we can
9069 * detect that condition here, which happens early in CPU bringup,
9070 * before any KVM threads can be running. Unfortunately, we can't
9071 * bring the TSCs fully up to date with real time, as we aren't yet far
9072 * enough into CPU bringup that we know how much real time has actually
9285ec4c 9073 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
0dd6a6ed
ZA		 9074 * variables that haven't been updated yet.
9075 *
9076 * So we simply find the maximum observed TSC above, then record the
9077 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9078 * the adjustment will be applied. Note that we accumulate
9079 * adjustments, in case multiple suspend cycles happen before some VCPU
9080 * gets a chance to run again. In the event that no KVM threads get a
9081 * chance to run, we will miss the entire elapsed period, as we'll have
9082 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9083 * loose cycle time. This isn't too big a deal, since the loss will be
9084 * uniform across all VCPUs (not to mention the scenario is extremely
9085 * unlikely). It is possible that a second hibernate recovery happens
9086 * much faster than a first, causing the observed TSC here to be
9087 * smaller; this would require additional padding adjustment, which is
9088 * why we set last_host_tsc to the local tsc observed here.
9089 *
9090 * N.B. - this code below runs only on platforms with reliable TSC,
9091 * as that is the only way backwards_tsc is set above. Also note
9092 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9093 * have the same delta_cyc adjustment applied if backwards_tsc
9094 * is detected. Note further, this adjustment is only done once,
9095 * as we reset last_host_tsc on all VCPUs to stop this from being
9096 * called multiple times (one for each physical CPU bringup).
9097 *
4a969980 9098 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 9099 * will be compensated by the logic in vcpu_load, which sets the TSC to
9100 * catchup mode. This will catchup all VCPUs to real time, but cannot
9101 * guarantee that they stay in perfect synchronization.
9102 */
9103 if (backwards_tsc) {
9104 u64 delta_cyc = max_tsc - local_tsc;
9105 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 9106 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 9107 kvm_for_each_vcpu(i, vcpu, kvm) {
9108 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9109 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 9110 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9111 }
9112
9113 /*
9114 * We have to disable TSC offset matching.. if you were
9115 * booting a VM while issuing an S4 host suspend....
9116 * you may have some problem. Solving this issue is
9117 * left as an exercise to the reader.
9118 */
9119 kvm->arch.last_tsc_nsec = 0;
9120 kvm->arch.last_tsc_write = 0;
9121 }
9122
9123 }
9124 return 0;
e9b11c17
ZX		 9125}
9126
13a34e06 9127void kvm_arch_hardware_disable(void)
e9b11c17 9128{
13a34e06
RK		 9129 kvm_x86_ops->hardware_disable();
9130 drop_user_return_notifiers();
e9b11c17
ZX		 9131}
9132
9133int kvm_arch_hardware_setup(void)
9134{
9e9c3fe4
NA		 9135 int r;
9136
9137 r = kvm_x86_ops->hardware_setup();
9138 if (r != 0)
9139 return r;
9140
35181e86
HZ		 9141 if (kvm_has_tsc_control) {
9142 /*
9143 * Make sure the user can only configure tsc_khz values that
9144 * fit into a signed integer.
273ba457 9145 * A min value is not calculated because it will always
35181e86
HZ		 9146 * be 1 on all machines.
9147 */
9148 u64 max = min(0x7fffffffULL,
9149 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9150 kvm_max_guest_tsc_khz = max;
9151
ad721883 9152 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9153 }
ad721883 9154
9e9c3fe4
NA		 9155 kvm_init_msr_list();
9156 return 0;
e9b11c17
ZX		 9157}
9158
9159void kvm_arch_hardware_unsetup(void)
9160{
9161 kvm_x86_ops->hardware_unsetup();
9162}
9163
f257d6dc 9164int kvm_arch_check_processor_compat(void)
e9b11c17 9165{
f257d6dc 9166 return kvm_x86_ops->check_processor_compatibility();
d71ba788
PB		 9167}
9168
9169bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9170{
9171 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9172}
9173EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9174
9175bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9176{
9177 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9178}
9179
54e9818f 9180struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9181EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9182
e9b11c17
ZX		 9183int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9184{
9185 struct page *page;
e9b11c17
ZX		 9186 int r;
9187
9aabc88f 9188 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9189 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9190 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9191 else
a4535290 9192 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9193
9194 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9195 if (!page) {
9196 r = -ENOMEM;
9197 goto fail;
9198 }
ad312c7c 9199 vcpu->arch.pio_data = page_address(page);
e9b11c17 9200
cc578287 9201 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9202
e9b11c17
ZX		 9203 r = kvm_mmu_create(vcpu);
9204 if (r < 0)
9205 goto fail_free_pio_data;
9206
26de7988 9207 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9208 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
39497d76 9209 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
e9b11c17
ZX		 9210 if (r < 0)
9211 goto fail_mmu_destroy;
54e9818f
GN		 9212 } else
9213 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9214
890ca9ae 9215 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
254272ce 9216 GFP_KERNEL_ACCOUNT);
890ca9ae
HY		 9217 if (!vcpu->arch.mce_banks) {
9218 r = -ENOMEM;
443c39bc 9219 goto fail_free_lapic;
890ca9ae
HY		 9220 }
9221 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9222
254272ce
BG		 9223 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9224 GFP_KERNEL_ACCOUNT)) {
f1797359 9225 r = -ENOMEM;
f5f48ee1 9226 goto fail_free_mce_banks;
f1797359 9227 }
f5f48ee1 9228
0ee6a517 9229 fx_init(vcpu);
66f7b72e 9230
4344ee98 9231 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9232
5a4f55cd
EK		 9233 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9234
74545705
RK		 9235 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9236
af585b92 9237 kvm_async_pf_hash_reset(vcpu);
f5132b01 9238 kvm_pmu_init(vcpu);
af585b92 9239
1c1a9ce9 9240 vcpu->arch.pending_external_vector = -1;
de63ad4c 9241 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9242
5c919412
AS		 9243 kvm_hv_vcpu_init(vcpu);
9244
e9b11c17 9245 return 0;
0ee6a517 9246
f5f48ee1
SY		 9247fail_free_mce_banks:
9248 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9249fail_free_lapic:
9250 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9251fail_mmu_destroy:
9252 kvm_mmu_destroy(vcpu);
9253fail_free_pio_data:
ad312c7c 9254 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9255fail:
9256 return r;
9257}
9258
9259void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9260{
f656ce01
MT		 9261 int idx;
9262
1f4b34f8 9263 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9264 kvm_pmu_destroy(vcpu);
36cb93fd 9265 kfree(vcpu->arch.mce_banks);
e9b11c17 9266 kvm_free_lapic(vcpu);
f656ce01 9267 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9268 kvm_mmu_destroy(vcpu);
f656ce01 9269 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9270 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9271 if (!lapic_in_kernel(vcpu))
54e9818f 9272 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9273}
d19a9cd2 9274
e790d9ef
RK		 9275void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9276{
c595ceee 9277 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9278 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9279}
9280
e08b9637 9281int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9282{
e08b9637
CO		 9283 if (type)
9284 return -EINVAL;
9285
6ef768fa 9286 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9287 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 9288 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9289 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9290
5550af4d
SY		 9291 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9292 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9293 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9294 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9295 &kvm->arch.irq_sources_bitmap);
5550af4d 9296
038f8c11 9297 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9298 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9299 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9300
9285ec4c 9301 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
d828199e 9302 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9303
6fbbde9a
DS		 9304 kvm->arch.guest_can_read_msr_platform_info = true;
9305
7e44e449 9306 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9307 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9308
cbc0236a 9309 kvm_hv_init_vm(kvm);
0eb05bf2 9310 kvm_page_track_init(kvm);
13d268ca 9311 kvm_mmu_init_vm(kvm);
0eb05bf2 9312
03543133
SS		 9313 if (kvm_x86_ops->vm_init)
9314 return kvm_x86_ops->vm_init(kvm);
9315
d89f5eff 9316 return 0;
d19a9cd2
ZX		 9317}
9318
9319static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9320{
ec7660cc 9321 vcpu_load(vcpu);
d19a9cd2
ZX		 9322 kvm_mmu_unload(vcpu);
9323 vcpu_put(vcpu);
9324}
9325
9326static void kvm_free_vcpus(struct kvm *kvm)
9327{
9328 unsigned int i;
988a2cae 9329 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9330
9331 /*
9332 * Unpin any mmu pages first.
9333 */
af585b92
GN		 9334 kvm_for_each_vcpu(i, vcpu, kvm) {
9335 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9336 kvm_unload_vcpu_mmu(vcpu);
af585b92 9337 }
988a2cae
GN		 9338 kvm_for_each_vcpu(i, vcpu, kvm)
9339 kvm_arch_vcpu_free(vcpu);
9340
9341 mutex_lock(&kvm->lock);
9342 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9343 kvm->vcpus[i] = NULL;
d19a9cd2 9344
988a2cae
GN		 9345 atomic_set(&kvm->online_vcpus, 0);
9346 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9347}
9348
ad8ba2cd
SY		 9349void kvm_arch_sync_events(struct kvm *kvm)
9350{
332967a3 9351 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9352 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9353 kvm_free_pit(kvm);
ad8ba2cd
SY		 9354}
9355
1d8007bd 9356int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9357{
9358 int i, r;
25188b99 9359 unsigned long hva;
f0d648bd
PB		 9360 struct kvm_memslots *slots = kvm_memslots(kvm);
9361 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9362
9363 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9364 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9365 return -EINVAL;
9da0e4d5 9366
f0d648bd
PB		 9367 slot = id_to_memslot(slots, id);
9368 if (size) {
b21629da 9369 if (slot->npages)
f0d648bd
PB		 9370 return -EEXIST;
9371
9372 /*
9373 * MAP_SHARED to prevent internal slot pages from being moved
9374 * by fork()/COW.
9375 */
9376 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9377 MAP_SHARED | MAP_ANONYMOUS, 0);
9378 if (IS_ERR((void *)hva))
9379 return PTR_ERR((void *)hva);
9380 } else {
9381 if (!slot->npages)
9382 return 0;
9383
9384 hva = 0;
9385 }
9386
9387 old = *slot;
9da0e4d5 9388 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9389 struct kvm_userspace_memory_region m;
9da0e4d5 9390
1d8007bd
PB		 9391 m.slot = id | (i << 16);
9392 m.flags = 0;
9393 m.guest_phys_addr = gpa;
f0d648bd 9394 m.userspace_addr = hva;
1d8007bd 9395 m.memory_size = size;
9da0e4d5
PB		 9396 r = __kvm_set_memory_region(kvm, &m);
9397 if (r < 0)
9398 return r;
9399 }
9400
103c763c
EB		 9401 if (!size)
9402 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9403
9da0e4d5
PB		 9404 return 0;
9405}
9406EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9407
1d8007bd 9408int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9409{
9410 int r;
9411
9412 mutex_lock(&kvm->slots_lock);
1d8007bd 9413 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9414 mutex_unlock(&kvm->slots_lock);
9415
9416 return r;
9417}
9418EXPORT_SYMBOL_GPL(x86_set_memory_region);
9419
d19a9cd2
ZX		 9420void kvm_arch_destroy_vm(struct kvm *kvm)
9421{
27469d29
AH		 9422 if (current->mm == kvm->mm) {
9423 /*
9424 * Free memory regions allocated on behalf of userspace,
9425 * unless the the memory map has changed due to process exit
9426 * or fd copying.
9427 */
1d8007bd
PB		 9428 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9429 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9430 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9431 }
03543133
SS		 9432 if (kvm_x86_ops->vm_destroy)
9433 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9434 kvm_pic_destroy(kvm);
9435 kvm_ioapic_destroy(kvm);
d19a9cd2 9436 kvm_free_vcpus(kvm);
af1bae54 9437 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
66bb8a06 9438 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
13d268ca 9439 kvm_mmu_uninit_vm(kvm);
2beb6dad 9440 kvm_page_track_cleanup(kvm);
cbc0236a 9441 kvm_hv_destroy_vm(kvm);
d19a9cd2 9442}
0de10343 9443
5587027c 9444void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9445 struct kvm_memory_slot *dont)
9446{
9447 int i;
9448
d89cc617
TY		 9449 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9450 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9451 kvfree(free->arch.rmap[i]);
d89cc617 9452 free->arch.rmap[i] = NULL;
77d11309 9453 }
d89cc617
TY		 9454 if (i == 0)
9455 continue;
9456
9457 if (!dont || free->arch.lpage_info[i - 1] !=
9458 dont->arch.lpage_info[i - 1]) {
548ef284 9459 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9460 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9461 }
9462 }
21ebbeda
XG		 9463
9464 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9465}
9466
5587027c
AK		 9467int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9468 unsigned long npages)
db3fe4eb
TY		 9469{
9470 int i;
9471
d89cc617 9472 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9473 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9474 unsigned long ugfn;
9475 int lpages;
d89cc617 9476 int level = i + 1;
db3fe4eb
TY		 9477
9478 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9479 slot->base_gfn, level) + 1;
9480
d89cc617 9481 slot->arch.rmap[i] =
778e1cdd 9482 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9483 GFP_KERNEL_ACCOUNT);
d89cc617 9484 if (!slot->arch.rmap[i])
77d11309 9485 goto out_free;
d89cc617
TY		 9486 if (i == 0)
9487 continue;
77d11309 9488
254272ce 9489 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9490 if (!linfo)
db3fe4eb
TY		 9491 goto out_free;
9492
92f94f1e
XG		 9493 slot->arch.lpage_info[i - 1] = linfo;
9494
db3fe4eb 9495 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9496 linfo[0].disallow_lpage = 1;
db3fe4eb 9497 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9498 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9499 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9500 /*
9501 * If the gfn and userspace address are not aligned wrt each
9502 * other, or if explicitly asked to, disable large page
9503 * support for this slot
9504 */
9505 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9506 !kvm_largepages_enabled()) {
9507 unsigned long j;
9508
9509 for (j = 0; j < lpages; ++j)
92f94f1e 9510 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9511 }
9512 }
9513
21ebbeda
XG		 9514 if (kvm_page_track_create_memslot(slot, npages))
9515 goto out_free;
9516
db3fe4eb
TY		 9517 return 0;
9518
9519out_free:
d89cc617 9520 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9521 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9522 slot->arch.rmap[i] = NULL;
9523 if (i == 0)
9524 continue;
9525
548ef284 9526 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9527 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9528 }
9529 return -ENOMEM;
9530}
9531
15248258 9532void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9533{
e6dff7d1
TY		 9534 /*
9535 * memslots->generation has been incremented.
9536 * mmio generation may have reached its maximum value.
9537 */
15248258 9538 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9539}
9540
f7784b8e
MT		 9541int kvm_arch_prepare_memory_region(struct kvm *kvm,
9542 struct kvm_memory_slot *memslot,
09170a49 9543 const struct kvm_userspace_memory_region *mem,
7b6195a9 9544 enum kvm_mr_change change)
0de10343 9545{
f7784b8e
MT		 9546 return 0;
9547}
9548
88178fd4
KH		 9549static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9550 struct kvm_memory_slot *new)
9551{
9552 /* Still write protect RO slot */
9553 if (new->flags & KVM_MEM_READONLY) {
9554 kvm_mmu_slot_remove_write_access(kvm, new);
9555 return;
9556 }
9557
9558 /*
9559 * Call kvm_x86_ops dirty logging hooks when they are valid.
9560 *
9561 * kvm_x86_ops->slot_disable_log_dirty is called when:
9562 *
9563 * - KVM_MR_CREATE with dirty logging is disabled
9564 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9565 *
9566 * The reason is, in case of PML, we need to set D-bit for any slots
9567 * with dirty logging disabled in order to eliminate unnecessary GPA
9568 * logging in PML buffer (and potential PML buffer full VMEXT). This
9569 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9570 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9571 * logging disabled for memory slots.
9572 *
9573 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9574 * to dirty logging mode.
9575 *
9576 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9577 *
9578 * In case of write protect:
9579 *
9580 * Write protect all pages for dirty logging.
9581 *
9582 * All the sptes including the large sptes which point to this
9583 * slot are set to readonly. We can not create any new large
9584 * spte on this slot until the end of the logging.
9585 *
9586 * See the comments in fast_page_fault().
9587 */
9588 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9589 if (kvm_x86_ops->slot_enable_log_dirty)
9590 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9591 else
9592 kvm_mmu_slot_remove_write_access(kvm, new);
9593 } else {
9594 if (kvm_x86_ops->slot_disable_log_dirty)
9595 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9596 }
9597}
9598
f7784b8e 9599void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9600 const struct kvm_userspace_memory_region *mem,
8482644a 9601 const struct kvm_memory_slot *old,
f36f3f28 9602 const struct kvm_memory_slot *new,
8482644a 9603 enum kvm_mr_change change)
f7784b8e 9604{
48c0e4e9 9605 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9606 kvm_mmu_change_mmu_pages(kvm,
9607 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9608
3ea3b7fa
WL		 9609 /*
9610 * Dirty logging tracks sptes in 4k granularity, meaning that large
9611 * sptes have to be split. If live migration is successful, the guest
9612 * in the source machine will be destroyed and large sptes will be
9613 * created in the destination. However, if the guest continues to run
9614 * in the source machine (for example if live migration fails), small
9615 * sptes will remain around and cause bad performance.
9616 *
9617 * Scan sptes if dirty logging has been stopped, dropping those
9618 * which can be collapsed into a single large-page spte. Later
9619 * page faults will create the large-page sptes.
9620 */
9621 if ((change != KVM_MR_DELETE) &&
9622 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9623 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9624 kvm_mmu_zap_collapsible_sptes(kvm, new);
9625
c972f3b1 9626 /*
88178fd4 9627 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9628 *
88178fd4
KH		 9629 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9630 * been zapped so no dirty logging staff is needed for old slot. For
9631 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9632 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9633 *
9634 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9635 */
88178fd4 9636 if (change != KVM_MR_DELETE)
f36f3f28 9637 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9638}
1d737c8a 9639
2df72e9b 9640void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9641{
7390de1e 9642 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9643}
9644
2df72e9b
MT		 9645void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9646 struct kvm_memory_slot *slot)
9647{
ae7cd873 9648 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9649}
9650
e6c67d8c
LA		 9651static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9652{
9653 return (is_guest_mode(vcpu) &&
9654 kvm_x86_ops->guest_apic_has_interrupt &&
9655 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9656}
9657
5d9bc648
PB		 9658static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9659{
9660 if (!list_empty_careful(&vcpu->async_pf.done))
9661 return true;
9662
9663 if (kvm_apic_has_events(vcpu))
9664 return true;
9665
9666 if (vcpu->arch.pv.pv_unhalted)
9667 return true;
9668
a5f01f8e
WL		 9669 if (vcpu->arch.exception.pending)
9670 return true;
9671
47a66eed
Z		 9672 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9673 (vcpu->arch.nmi_pending &&
9674 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9675 return true;
9676
47a66eed
Z		 9677 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9678 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9679 return true;
9680
5d9bc648 9681 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9682 (kvm_cpu_has_interrupt(vcpu) ||
9683 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9684 return true;
9685
1f4b34f8
AS		 9686 if (kvm_hv_has_stimer_pending(vcpu))
9687 return true;
9688
5d9bc648
PB		 9689 return false;
9690}
9691
1d737c8a
ZX		 9692int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9693{
5d9bc648 9694 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9695}
5736199a 9696
199b5763
LM		 9697bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9698{
de63ad4c 9699 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9700}
9701
b6d33834 9702int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9703{
b6d33834 9704 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9705}
78646121
GN		 9706
9707int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9708{
9709 return kvm_x86_ops->interrupt_allowed(vcpu);
9710}
229456fc 9711
82b32774 9712unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9713{
82b32774
NA		 9714 if (is_64_bit_mode(vcpu))
9715 return kvm_rip_read(vcpu);
9716 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9717 kvm_rip_read(vcpu));
9718}
9719EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9720
82b32774
NA		 9721bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9722{
9723 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9724}
9725EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9726
94fe45da
JK		 9727unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9728{
9729 unsigned long rflags;
9730
9731 rflags = kvm_x86_ops->get_rflags(vcpu);
9732 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9733 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9734 return rflags;
9735}
9736EXPORT_SYMBOL_GPL(kvm_get_rflags);
9737
6addfc42 9738static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9739{
9740 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9741 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9742 rflags |= X86_EFLAGS_TF;
94fe45da 9743 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9744}
9745
9746void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9747{
9748 __kvm_set_rflags(vcpu, rflags);
3842d135 9749 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9750}
9751EXPORT_SYMBOL_GPL(kvm_set_rflags);
9752
56028d08
GN		 9753void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9754{
9755 int r;
9756
44dd3ffa 9757 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9758 work->wakeup_all)
56028d08
GN		 9759 return;
9760
9761 r = kvm_mmu_reload(vcpu);
9762 if (unlikely(r))
9763 return;
9764
44dd3ffa
VK		 9765 if (!vcpu->arch.mmu->direct_map &&
9766 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9767 return;
9768
44dd3ffa 9769 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9770}
9771
af585b92
GN		 9772static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9773{
9774 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9775}
9776
9777static inline u32 kvm_async_pf_next_probe(u32 key)
9778{
9779 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9780}
9781
9782static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9783{
9784 u32 key = kvm_async_pf_hash_fn(gfn);
9785
9786 while (vcpu->arch.apf.gfns[key] != ~0)
9787 key = kvm_async_pf_next_probe(key);
9788
9789 vcpu->arch.apf.gfns[key] = gfn;
9790}
9791
9792static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9793{
9794 int i;
9795 u32 key = kvm_async_pf_hash_fn(gfn);
9796
9797 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9798 (vcpu->arch.apf.gfns[key] != gfn &&
9799 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9800 key = kvm_async_pf_next_probe(key);
9801
9802 return key;
9803}
9804
9805bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9806{
9807 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9808}
9809
9810static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9811{
9812 u32 i, j, k;
9813
9814 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9815 while (true) {
9816 vcpu->arch.apf.gfns[i] = ~0;
9817 do {
9818 j = kvm_async_pf_next_probe(j);
9819 if (vcpu->arch.apf.gfns[j] == ~0)
9820 return;
9821 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9822 /*
9823 * k lies cyclically in ]i,j]
9824 * | i.k.j |
9825 * |....j i.k.| or |.k..j i...|
9826 */
9827 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9828 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9829 i = j;
9830 }
9831}
9832
7c90705b
GN		 9833static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9834{
4e335d9e
PB		 9835
9836 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9837 sizeof(val));
7c90705b
GN		 9838}
9839
9a6e7c39
WL		 9840static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9841{
9842
9843 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9844 sizeof(u32));
9845}
9846
1dfdb45e
PB		 9847static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
9848{
9849 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
9850 return false;
9851
9852 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9853 (vcpu->arch.apf.send_user_only &&
9854 kvm_x86_ops->get_cpl(vcpu) == 0))
9855 return false;
9856
9857 return true;
9858}
9859
9860bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
9861{
9862 if (unlikely(!lapic_in_kernel(vcpu) ||
9863 kvm_event_needs_reinjection(vcpu) ||
9864 vcpu->arch.exception.pending))
9865 return false;
9866
9867 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
9868 return false;
9869
9870 /*
9871 * If interrupts are off we cannot even use an artificial
9872 * halt state.
9873 */
9874 return kvm_x86_ops->interrupt_allowed(vcpu);
9875}
9876
af585b92
GN		 9877void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9878 struct kvm_async_pf *work)
9879{
6389ee94
AK		 9880 struct x86_exception fault;
9881
7c90705b 9882 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9883 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b 9884
1dfdb45e
PB		 9885 if (kvm_can_deliver_async_pf(vcpu) &&
9886 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9887 fault.vector = PF_VECTOR;
9888 fault.error_code_valid = true;
9889 fault.error_code = 0;
9890 fault.nested_page_fault = false;
9891 fault.address = work->arch.token;
adfe20fb 9892 fault.async_page_fault = true;
6389ee94 9893 kvm_inject_page_fault(vcpu, &fault);
1dfdb45e
PB		 9894 } else {
9895 /*
9896 * It is not possible to deliver a paravirtualized asynchronous
9897 * page fault, but putting the guest in an artificial halt state
9898 * can be beneficial nevertheless: if an interrupt arrives, we
9899 * can deliver it timely and perhaps the guest will schedule
9900 * another process. When the instruction that triggered a page
9901 * fault is retried, hopefully the page will be ready in the host.
9902 */
9903 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7c90705b 9904 }
af585b92
GN		 9905}
9906
9907void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9908 struct kvm_async_pf *work)
9909{
6389ee94 9910 struct x86_exception fault;
9a6e7c39 9911 u32 val;
6389ee94 9912
f2e10669 9913 if (work->wakeup_all)
7c90705b
GN		 9914 work->arch.token = ~0; /* broadcast wakeup */
9915 else
9916 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9917 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9918
9a6e7c39
WL		 9919 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9920 !apf_get_user(vcpu, &val)) {
9921 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9922 vcpu->arch.exception.pending &&
9923 vcpu->arch.exception.nr == PF_VECTOR &&
9924 !apf_put_user(vcpu, 0)) {
9925 vcpu->arch.exception.injected = false;
9926 vcpu->arch.exception.pending = false;
9927 vcpu->arch.exception.nr = 0;
9928 vcpu->arch.exception.has_error_code = false;
9929 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9930 vcpu->arch.exception.has_payload = false;
9931 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9932 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9933 fault.vector = PF_VECTOR;
9934 fault.error_code_valid = true;
9935 fault.error_code = 0;
9936 fault.nested_page_fault = false;
9937 fault.address = work->arch.token;
9938 fault.async_page_fault = true;
9939 kvm_inject_page_fault(vcpu, &fault);
9940 }
7c90705b 9941 }
e6d53e3b 9942 vcpu->arch.apf.halted = false;
a4fa1635 9943 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9944}
9945
9946bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9947{
9948 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9949 return true;
9950 else
9bc1f09f 9951 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9952}
9953
5544eb9b
PB		 9954void kvm_arch_start_assignment(struct kvm *kvm)
9955{
9956 atomic_inc(&kvm->arch.assigned_device_count);
9957}
9958EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9959
9960void kvm_arch_end_assignment(struct kvm *kvm)
9961{
9962 atomic_dec(&kvm->arch.assigned_device_count);
9963}
9964EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9965
9966bool kvm_arch_has_assigned_device(struct kvm *kvm)
9967{
9968 return atomic_read(&kvm->arch.assigned_device_count);
9969}
9970EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9971
e0f0bbc5
AW		 9972void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9973{
9974 atomic_inc(&kvm->arch.noncoherent_dma_count);
9975}
9976EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9977
9978void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9979{
9980 atomic_dec(&kvm->arch.noncoherent_dma_count);
9981}
9982EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9983
9984bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9985{
9986 return atomic_read(&kvm->arch.noncoherent_dma_count);
9987}
9988EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9989
14717e20
AW		 9990bool kvm_arch_has_irq_bypass(void)
9991{
9992 return kvm_x86_ops->update_pi_irte != NULL;
9993}
9994
87276880
FW		 9995int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9996 struct irq_bypass_producer *prod)
9997{
9998 struct kvm_kernel_irqfd *irqfd =
9999 container_of(cons, struct kvm_kernel_irqfd, consumer);
10000
14717e20 10001 irqfd->producer = prod;
87276880 10002
14717e20
AW		 10003 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10004 prod->irq, irqfd->gsi, 1);
87276880
FW		 10005}
10006
10007void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10008 struct irq_bypass_producer *prod)
10009{
10010 int ret;
10011 struct kvm_kernel_irqfd *irqfd =
10012 container_of(cons, struct kvm_kernel_irqfd, consumer);
10013
87276880
FW		 10014 WARN_ON(irqfd->producer != prod);
10015 irqfd->producer = NULL;
10016
10017 /*
10018 * When producer of consumer is unregistered, we change back to
10019 * remapped mode, so we can re-use the current implementation
bb3541f1 10020 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 10021 * int this case doesn't want to receive the interrupts.
10022 */
10023 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10024 if (ret)
10025 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10026 " fails: %d\n", irqfd->consumer.token, ret);
10027}
10028
10029int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10030 uint32_t guest_irq, bool set)
10031{
10032 if (!kvm_x86_ops->update_pi_irte)
10033 return -EINVAL;
10034
10035 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10036}
10037
52004014
FW		 10038bool kvm_vector_hashing_enabled(void)
10039{
10040 return vector_hashing;
10041}
10042EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10043
2d5ba19b
MT		 10044bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10045{
10046 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10047}
10048EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10049
10050
229456fc 10051EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 10052EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 10053EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10054EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10055EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10056EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 10057EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 10058EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 10059EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 10060EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 10061EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 10062EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 10063EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 10064EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 10065EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 10066EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 10067EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 10068EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10069EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)