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KVM: x86: allow guest to use cflushopt and clwb
[linux-block.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
af658dca 31#include <linux/trace_events.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
952f07ec 43#include <asm/fpu/internal.h>
d7cd9796 44#include <asm/perf_event.h>
81908bf4 45#include <asm/debugreg.h>
8f536b76 46#include <asm/kexec.h>
dab2087d 47#include <asm/apic.h>
6aa8b732 48
229456fc 49#include "trace.h"
25462f7f 50#include "pmu.h"
229456fc 51
4ecac3fd 52#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 53#define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 55
6aa8b732
AK		 56MODULE_AUTHOR("Qumranet");
57MODULE_LICENSE("GPL");
58
e9bda3b3
JT		 59static const struct x86_cpu_id vmx_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX),
61 {}
62};
63MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64
476bc001 65static bool __read_mostly enable_vpid = 1;
736caefe 66module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 67
476bc001 68static bool __read_mostly flexpriority_enabled = 1;
736caefe 69module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 70
476bc001 71static bool __read_mostly enable_ept = 1;
736caefe 72module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 73
476bc001 74static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 75module_param_named(unrestricted_guest,
76 enable_unrestricted_guest, bool, S_IRUGO);
77
83c3a331
XH		 78static bool __read_mostly enable_ept_ad_bits = 1;
79module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80
a27685c3 81static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 82module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 83
476bc001 84static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 85module_param(vmm_exclusive, bool, S_IRUGO);
86
476bc001 87static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 88module_param(fasteoi, bool, S_IRUGO);
89
5a71785d 90static bool __read_mostly enable_apicv = 1;
01e439be 91module_param(enable_apicv, bool, S_IRUGO);
83d4c286 92
abc4fc58
AG		 93static bool __read_mostly enable_shadow_vmcs = 1;
94module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 95/*
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
99 */
476bc001 100static bool __read_mostly nested = 0;
801d3424
NHE		 101module_param(nested, bool, S_IRUGO);
102
20300099
WL		 103static u64 __read_mostly host_xss;
104
843e4330
KH		 105static bool __read_mostly enable_pml = 1;
106module_param_named(pml, enable_pml, bool, S_IRUGO);
107
5037878e
GN		 108#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 110#define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 112#define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 115
cdc0e244
AK		 116#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118
78ac8b47
AK		 119#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120
f4124500
JK		 121#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
122
4b8d54f9
ZE		 123/*
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 127 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
133 */
b4a2d31d
RK		 134#define KVM_VMX_DEFAULT_PLE_GAP 128
135#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140
4b8d54f9
ZE		 141static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142module_param(ple_gap, int, S_IRUGO);
143
144static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145module_param(ple_window, int, S_IRUGO);
146
b4a2d31d
RK		 147/* Default doubles per-vcpu window every exit. */
148static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149module_param(ple_window_grow, int, S_IRUGO);
150
151/* Default resets per-vcpu window every exit to ple_window. */
152static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153module_param(ple_window_shrink, int, S_IRUGO);
154
155/* Default is to compute the maximum so we can never overflow. */
156static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158module_param(ple_window_max, int, S_IRUGO);
159
83287ea4
AK		 160extern const ulong vmx_return;
161
8bf00a52 162#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 163#define VMCS02_POOL_SIZE 1
61d2ef2c 164
a2fa3e9f
GH		 165struct vmcs {
166 u32 revision_id;
167 u32 abort;
168 char data[0];
169};
170
d462b819
NHE		 171/*
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
175 */
176struct loaded_vmcs {
177 struct vmcs *vmcs;
178 int cpu;
179 int launched;
180 struct list_head loaded_vmcss_on_cpu_link;
181};
182
26bb0981
AK		 183struct shared_msr_entry {
184 unsigned index;
185 u64 data;
d5696725 186 u64 mask;
26bb0981
AK		 187};
188
a9d30f33
NHE		 189/*
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
201 */
22bd0358 202typedef u64 natural_width;
a9d30f33
NHE		 203struct __packed vmcs12 {
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
206 */
207 u32 revision_id;
208 u32 abort;
22bd0358 209
27d6c865
NHE		 210 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding[7]; /* room for future expansion */
212
22bd0358
NHE		 213 u64 io_bitmap_a;
214 u64 io_bitmap_b;
215 u64 msr_bitmap;
216 u64 vm_exit_msr_store_addr;
217 u64 vm_exit_msr_load_addr;
218 u64 vm_entry_msr_load_addr;
219 u64 tsc_offset;
220 u64 virtual_apic_page_addr;
221 u64 apic_access_addr;
705699a1 222 u64 posted_intr_desc_addr;
22bd0358 223 u64 ept_pointer;
608406e2
WV		 224 u64 eoi_exit_bitmap0;
225 u64 eoi_exit_bitmap1;
226 u64 eoi_exit_bitmap2;
227 u64 eoi_exit_bitmap3;
81dc01f7 228 u64 xss_exit_bitmap;
22bd0358
NHE		 229 u64 guest_physical_address;
230 u64 vmcs_link_pointer;
231 u64 guest_ia32_debugctl;
232 u64 guest_ia32_pat;
233 u64 guest_ia32_efer;
234 u64 guest_ia32_perf_global_ctrl;
235 u64 guest_pdptr0;
236 u64 guest_pdptr1;
237 u64 guest_pdptr2;
238 u64 guest_pdptr3;
36be0b9d 239 u64 guest_bndcfgs;
22bd0358
NHE		 240 u64 host_ia32_pat;
241 u64 host_ia32_efer;
242 u64 host_ia32_perf_global_ctrl;
243 u64 padding64[8]; /* room for future expansion */
244 /*
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
249 */
250 natural_width cr0_guest_host_mask;
251 natural_width cr4_guest_host_mask;
252 natural_width cr0_read_shadow;
253 natural_width cr4_read_shadow;
254 natural_width cr3_target_value0;
255 natural_width cr3_target_value1;
256 natural_width cr3_target_value2;
257 natural_width cr3_target_value3;
258 natural_width exit_qualification;
259 natural_width guest_linear_address;
260 natural_width guest_cr0;
261 natural_width guest_cr3;
262 natural_width guest_cr4;
263 natural_width guest_es_base;
264 natural_width guest_cs_base;
265 natural_width guest_ss_base;
266 natural_width guest_ds_base;
267 natural_width guest_fs_base;
268 natural_width guest_gs_base;
269 natural_width guest_ldtr_base;
270 natural_width guest_tr_base;
271 natural_width guest_gdtr_base;
272 natural_width guest_idtr_base;
273 natural_width guest_dr7;
274 natural_width guest_rsp;
275 natural_width guest_rip;
276 natural_width guest_rflags;
277 natural_width guest_pending_dbg_exceptions;
278 natural_width guest_sysenter_esp;
279 natural_width guest_sysenter_eip;
280 natural_width host_cr0;
281 natural_width host_cr3;
282 natural_width host_cr4;
283 natural_width host_fs_base;
284 natural_width host_gs_base;
285 natural_width host_tr_base;
286 natural_width host_gdtr_base;
287 natural_width host_idtr_base;
288 natural_width host_ia32_sysenter_esp;
289 natural_width host_ia32_sysenter_eip;
290 natural_width host_rsp;
291 natural_width host_rip;
292 natural_width paddingl[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control;
294 u32 cpu_based_vm_exec_control;
295 u32 exception_bitmap;
296 u32 page_fault_error_code_mask;
297 u32 page_fault_error_code_match;
298 u32 cr3_target_count;
299 u32 vm_exit_controls;
300 u32 vm_exit_msr_store_count;
301 u32 vm_exit_msr_load_count;
302 u32 vm_entry_controls;
303 u32 vm_entry_msr_load_count;
304 u32 vm_entry_intr_info_field;
305 u32 vm_entry_exception_error_code;
306 u32 vm_entry_instruction_len;
307 u32 tpr_threshold;
308 u32 secondary_vm_exec_control;
309 u32 vm_instruction_error;
310 u32 vm_exit_reason;
311 u32 vm_exit_intr_info;
312 u32 vm_exit_intr_error_code;
313 u32 idt_vectoring_info_field;
314 u32 idt_vectoring_error_code;
315 u32 vm_exit_instruction_len;
316 u32 vmx_instruction_info;
317 u32 guest_es_limit;
318 u32 guest_cs_limit;
319 u32 guest_ss_limit;
320 u32 guest_ds_limit;
321 u32 guest_fs_limit;
322 u32 guest_gs_limit;
323 u32 guest_ldtr_limit;
324 u32 guest_tr_limit;
325 u32 guest_gdtr_limit;
326 u32 guest_idtr_limit;
327 u32 guest_es_ar_bytes;
328 u32 guest_cs_ar_bytes;
329 u32 guest_ss_ar_bytes;
330 u32 guest_ds_ar_bytes;
331 u32 guest_fs_ar_bytes;
332 u32 guest_gs_ar_bytes;
333 u32 guest_ldtr_ar_bytes;
334 u32 guest_tr_ar_bytes;
335 u32 guest_interruptibility_info;
336 u32 guest_activity_state;
337 u32 guest_sysenter_cs;
338 u32 host_ia32_sysenter_cs;
0238ea91
JK		 339 u32 vmx_preemption_timer_value;
340 u32 padding32[7]; /* room for future expansion */
22bd0358 341 u16 virtual_processor_id;
705699a1 342 u16 posted_intr_nv;
22bd0358
NHE		 343 u16 guest_es_selector;
344 u16 guest_cs_selector;
345 u16 guest_ss_selector;
346 u16 guest_ds_selector;
347 u16 guest_fs_selector;
348 u16 guest_gs_selector;
349 u16 guest_ldtr_selector;
350 u16 guest_tr_selector;
608406e2 351 u16 guest_intr_status;
22bd0358
NHE		 352 u16 host_es_selector;
353 u16 host_cs_selector;
354 u16 host_ss_selector;
355 u16 host_ds_selector;
356 u16 host_fs_selector;
357 u16 host_gs_selector;
358 u16 host_tr_selector;
a9d30f33
NHE		 359};
360
361/*
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365 */
366#define VMCS12_REVISION 0x11e57ed0
367
368/*
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
372 */
373#define VMCS12_SIZE 0x1000
374
ff2f6fe9
NHE		 375/* Used to remember the last vmcs02 used for some recently used vmcs12s */
376struct vmcs02_list {
377 struct list_head list;
378 gpa_t vmptr;
379 struct loaded_vmcs vmcs02;
380};
381
ec378aee
NHE		 382/*
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
385 */
386struct nested_vmx {
387 /* Has the level1 guest done vmxon? */
388 bool vmxon;
3573e22c 389 gpa_t vmxon_ptr;
a9d30f33
NHE		 390
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
392 gpa_t current_vmptr;
393 /* The host-usable pointer to the above */
394 struct page *current_vmcs12_page;
395 struct vmcs12 *current_vmcs12;
8de48833 396 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 397 /*
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
400 */
401 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 402
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool;
405 int vmcs02_num;
fe3ef05c 406 u64 vmcs01_tsc_offset;
644d711a
NHE		 407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending;
fe3ef05c
NHE		 409 /*
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
412 */
413 struct page *apic_access_page;
a7c0b07d 414 struct page *virtual_apic_page;
705699a1
WV		 415 struct page *pi_desc_page;
416 struct pi_desc *pi_desc;
417 bool pi_pending;
418 u16 posted_intr_nv;
b3897a49 419 u64 msr_ia32_feature_control;
f4124500
JK		 420
421 struct hrtimer preemption_timer;
422 bool preemption_timer_expired;
2996fca0
JK		 423
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
425 u64 vmcs01_debugctl;
b9c237bb
WV		 426
427 u32 nested_vmx_procbased_ctls_low;
428 u32 nested_vmx_procbased_ctls_high;
429 u32 nested_vmx_true_procbased_ctls_low;
430 u32 nested_vmx_secondary_ctls_low;
431 u32 nested_vmx_secondary_ctls_high;
432 u32 nested_vmx_pinbased_ctls_low;
433 u32 nested_vmx_pinbased_ctls_high;
434 u32 nested_vmx_exit_ctls_low;
435 u32 nested_vmx_exit_ctls_high;
436 u32 nested_vmx_true_exit_ctls_low;
437 u32 nested_vmx_entry_ctls_low;
438 u32 nested_vmx_entry_ctls_high;
439 u32 nested_vmx_true_entry_ctls_low;
440 u32 nested_vmx_misc_low;
441 u32 nested_vmx_misc_high;
442 u32 nested_vmx_ept_caps;
ec378aee
NHE		 443};
444
01e439be
YZ		 445#define POSTED_INTR_ON 0
446/* Posted-Interrupt Descriptor */
447struct pi_desc {
448 u32 pir[8]; /* Posted interrupt requested */
449 u32 control; /* bit 0 of control is outstanding notification bit */
450 u32 rsvd[7];
451} __aligned(64);
452
a20ed54d
YZ		 453static bool pi_test_and_set_on(struct pi_desc *pi_desc)
454{
455 return test_and_set_bit(POSTED_INTR_ON,
456 (unsigned long *)&pi_desc->control);
457}
458
459static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
460{
461 return test_and_clear_bit(POSTED_INTR_ON,
462 (unsigned long *)&pi_desc->control);
463}
464
465static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
466{
467 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
468}
469
a2fa3e9f 470struct vcpu_vmx {
fb3f0f51 471 struct kvm_vcpu vcpu;
313dbd49 472 unsigned long host_rsp;
29bd8a78 473 u8 fail;
9d58b931 474 bool nmi_known_unmasked;
51aa01d1 475 u32 exit_intr_info;
1155f76a 476 u32 idt_vectoring_info;
6de12732 477 ulong rflags;
26bb0981 478 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 479 int nmsrs;
480 int save_nmsrs;
a547c6db 481 unsigned long host_idt_base;
a2fa3e9f 482#ifdef CONFIG_X86_64
44ea2b17
AK		 483 u64 msr_host_kernel_gs_base;
484 u64 msr_guest_kernel_gs_base;
a2fa3e9f 485#endif
2961e876
GN		 486 u32 vm_entry_controls_shadow;
487 u32 vm_exit_controls_shadow;
d462b819
NHE		 488 /*
489 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490 * non-nested (L1) guest, it always points to vmcs01. For a nested
491 * guest (L2), it points to a different VMCS.
492 */
493 struct loaded_vmcs vmcs01;
494 struct loaded_vmcs *loaded_vmcs;
495 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 496 struct msr_autoload {
497 unsigned nr;
498 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
499 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
500 } msr_autoload;
a2fa3e9f
GH		 501 struct {
502 int loaded;
503 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 504#ifdef CONFIG_X86_64
505 u16 ds_sel, es_sel;
506#endif
152d3f2f
LV		 507 int gs_ldt_reload_needed;
508 int fs_reload_needed;
da8999d3 509 u64 msr_host_bndcfgs;
d974baa3 510 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 511 } host_state;
9c8cba37 512 struct {
7ffd92c5 513 int vm86_active;
78ac8b47 514 ulong save_rflags;
f5f7b2fe
AK		 515 struct kvm_segment segs[8];
516 } rmode;
517 struct {
518 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 519 struct kvm_save_segment {
520 u16 selector;
521 unsigned long base;
522 u32 limit;
523 u32 ar;
f5f7b2fe 524 } seg[8];
2fb92db1 525 } segment_cache;
2384d2b3 526 int vpid;
04fa4d32 527 bool emulation_required;
3b86cd99
JK		 528
529 /* Support for vnmi-less CPUs */
530 int soft_vnmi_blocked;
531 ktime_t entry_time;
532 s64 vnmi_blocked_time;
a0861c02 533 u32 exit_reason;
4e47c7a6
SY		 534
535 bool rdtscp_enabled;
ec378aee 536
01e439be
YZ		 537 /* Posted interrupt descriptor */
538 struct pi_desc pi_desc;
539
ec378aee
NHE		 540 /* Support for a guest hypervisor (nested VMX) */
541 struct nested_vmx nested;
a7653ecd
RK		 542
543 /* Dynamic PLE window. */
544 int ple_window;
545 bool ple_window_dirty;
843e4330
KH		 546
547 /* Support for PML */
548#define PML_ENTITY_NUM 512
549 struct page *pml_pg;
a2fa3e9f
GH		 550};
551
2fb92db1
AK		 552enum segment_cache_field {
553 SEG_FIELD_SEL = 0,
554 SEG_FIELD_BASE = 1,
555 SEG_FIELD_LIMIT = 2,
556 SEG_FIELD_AR = 3,
557
558 SEG_FIELD_NR = 4
559};
560
a2fa3e9f
GH		 561static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
562{
fb3f0f51 563 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 564}
565
22bd0358
NHE		 566#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
568#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
569 [number##_HIGH] = VMCS12_OFFSET(name)+4
570
4607c2d7 571
fe2b201b 572static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 573 /*
574 * We do NOT shadow fields that are modified when L0
575 * traps and emulates any vmx instruction (e.g. VMPTRLD,
576 * VMXON...) executed by L1.
577 * For example, VM_INSTRUCTION_ERROR is read
578 * by L1 if a vmx instruction fails (part of the error path).
579 * Note the code assumes this logic. If for some reason
580 * we start shadowing these fields then we need to
581 * force a shadow sync when L0 emulates vmx instructions
582 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583 * by nested_vmx_failValid)
584 */
585 VM_EXIT_REASON,
586 VM_EXIT_INTR_INFO,
587 VM_EXIT_INSTRUCTION_LEN,
588 IDT_VECTORING_INFO_FIELD,
589 IDT_VECTORING_ERROR_CODE,
590 VM_EXIT_INTR_ERROR_CODE,
591 EXIT_QUALIFICATION,
592 GUEST_LINEAR_ADDRESS,
593 GUEST_PHYSICAL_ADDRESS
594};
fe2b201b 595static int max_shadow_read_only_fields =
4607c2d7
AG		 596 ARRAY_SIZE(shadow_read_only_fields);
597
fe2b201b 598static unsigned long shadow_read_write_fields[] = {
a7c0b07d 599 TPR_THRESHOLD,
4607c2d7
AG		 600 GUEST_RIP,
601 GUEST_RSP,
602 GUEST_CR0,
603 GUEST_CR3,
604 GUEST_CR4,
605 GUEST_INTERRUPTIBILITY_INFO,
606 GUEST_RFLAGS,
607 GUEST_CS_SELECTOR,
608 GUEST_CS_AR_BYTES,
609 GUEST_CS_LIMIT,
610 GUEST_CS_BASE,
611 GUEST_ES_BASE,
36be0b9d 612 GUEST_BNDCFGS,
4607c2d7
AG		 613 CR0_GUEST_HOST_MASK,
614 CR0_READ_SHADOW,
615 CR4_READ_SHADOW,
616 TSC_OFFSET,
617 EXCEPTION_BITMAP,
618 CPU_BASED_VM_EXEC_CONTROL,
619 VM_ENTRY_EXCEPTION_ERROR_CODE,
620 VM_ENTRY_INTR_INFO_FIELD,
621 VM_ENTRY_INSTRUCTION_LEN,
622 VM_ENTRY_EXCEPTION_ERROR_CODE,
623 HOST_FS_BASE,
624 HOST_GS_BASE,
625 HOST_FS_SELECTOR,
626 HOST_GS_SELECTOR
627};
fe2b201b 628static int max_shadow_read_write_fields =
4607c2d7
AG		 629 ARRAY_SIZE(shadow_read_write_fields);
630
772e0318 631static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 632 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 633 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 634 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
635 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
636 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
637 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
638 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
639 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
640 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
641 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 642 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 643 FIELD(HOST_ES_SELECTOR, host_es_selector),
644 FIELD(HOST_CS_SELECTOR, host_cs_selector),
645 FIELD(HOST_SS_SELECTOR, host_ss_selector),
646 FIELD(HOST_DS_SELECTOR, host_ds_selector),
647 FIELD(HOST_FS_SELECTOR, host_fs_selector),
648 FIELD(HOST_GS_SELECTOR, host_gs_selector),
649 FIELD(HOST_TR_SELECTOR, host_tr_selector),
650 FIELD64(IO_BITMAP_A, io_bitmap_a),
651 FIELD64(IO_BITMAP_B, io_bitmap_b),
652 FIELD64(MSR_BITMAP, msr_bitmap),
653 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
654 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
655 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
656 FIELD64(TSC_OFFSET, tsc_offset),
657 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
658 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 659 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 660 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 661 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
662 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
663 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
664 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 665 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 666 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
667 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
668 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
669 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
670 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
671 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
672 FIELD64(GUEST_PDPTR0, guest_pdptr0),
673 FIELD64(GUEST_PDPTR1, guest_pdptr1),
674 FIELD64(GUEST_PDPTR2, guest_pdptr2),
675 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 676 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 677 FIELD64(HOST_IA32_PAT, host_ia32_pat),
678 FIELD64(HOST_IA32_EFER, host_ia32_efer),
679 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
680 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
681 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
682 FIELD(EXCEPTION_BITMAP, exception_bitmap),
683 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
684 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
685 FIELD(CR3_TARGET_COUNT, cr3_target_count),
686 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
687 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
688 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
689 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
690 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
691 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
692 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
693 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
694 FIELD(TPR_THRESHOLD, tpr_threshold),
695 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
696 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
697 FIELD(VM_EXIT_REASON, vm_exit_reason),
698 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
699 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
700 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
701 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
702 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
703 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
704 FIELD(GUEST_ES_LIMIT, guest_es_limit),
705 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
706 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
707 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
708 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
709 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
710 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
711 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
712 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
713 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
714 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
715 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
716 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
717 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
718 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
719 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
720 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
721 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
722 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
723 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
724 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
725 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 726 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 727 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
728 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
729 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
730 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
731 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
732 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
733 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
734 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
735 FIELD(EXIT_QUALIFICATION, exit_qualification),
736 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
737 FIELD(GUEST_CR0, guest_cr0),
738 FIELD(GUEST_CR3, guest_cr3),
739 FIELD(GUEST_CR4, guest_cr4),
740 FIELD(GUEST_ES_BASE, guest_es_base),
741 FIELD(GUEST_CS_BASE, guest_cs_base),
742 FIELD(GUEST_SS_BASE, guest_ss_base),
743 FIELD(GUEST_DS_BASE, guest_ds_base),
744 FIELD(GUEST_FS_BASE, guest_fs_base),
745 FIELD(GUEST_GS_BASE, guest_gs_base),
746 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
747 FIELD(GUEST_TR_BASE, guest_tr_base),
748 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
749 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
750 FIELD(GUEST_DR7, guest_dr7),
751 FIELD(GUEST_RSP, guest_rsp),
752 FIELD(GUEST_RIP, guest_rip),
753 FIELD(GUEST_RFLAGS, guest_rflags),
754 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
755 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
756 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
757 FIELD(HOST_CR0, host_cr0),
758 FIELD(HOST_CR3, host_cr3),
759 FIELD(HOST_CR4, host_cr4),
760 FIELD(HOST_FS_BASE, host_fs_base),
761 FIELD(HOST_GS_BASE, host_gs_base),
762 FIELD(HOST_TR_BASE, host_tr_base),
763 FIELD(HOST_GDTR_BASE, host_gdtr_base),
764 FIELD(HOST_IDTR_BASE, host_idtr_base),
765 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
766 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
767 FIELD(HOST_RSP, host_rsp),
768 FIELD(HOST_RIP, host_rip),
769};
22bd0358
NHE		 770
771static inline short vmcs_field_to_offset(unsigned long field)
772{
a2ae9df7
PB		 773 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
774
775 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
776 vmcs_field_to_offset_table[field] == 0)
777 return -ENOENT;
778
22bd0358
NHE		 779 return vmcs_field_to_offset_table[field];
780}
781
a9d30f33
NHE		 782static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
783{
784 return to_vmx(vcpu)->nested.current_vmcs12;
785}
786
787static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
788{
54bf36aa 789 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 790 if (is_error_page(page))
a9d30f33 791 return NULL;
32cad84f 792
a9d30f33
NHE		 793 return page;
794}
795
796static void nested_release_page(struct page *page)
797{
798 kvm_release_page_dirty(page);
799}
800
801static void nested_release_page_clean(struct page *page)
802{
803 kvm_release_page_clean(page);
804}
805
bfd0a56b 806static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 807static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 808static void kvm_cpu_vmxon(u64 addr);
809static void kvm_cpu_vmxoff(void);
93c4adc7 810static bool vmx_mpx_supported(void);
f53cd63c 811static bool vmx_xsaves_supported(void);
d50ab6c1 812static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
776e58ea 813static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 814static void vmx_set_segment(struct kvm_vcpu *vcpu,
815 struct kvm_segment *var, int seg);
816static void vmx_get_segment(struct kvm_vcpu *vcpu,
817 struct kvm_segment *var, int seg);
d99e4152
GN		 818static bool guest_state_valid(struct kvm_vcpu *vcpu);
819static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 820static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 821static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 822static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 823static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 824
6aa8b732
AK		 825static DEFINE_PER_CPU(struct vmcs *, vmxarea);
826static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 827/*
828 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
829 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
830 */
831static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 832static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 833
3e7c73e9
AK		 834static unsigned long *vmx_io_bitmap_a;
835static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 836static unsigned long *vmx_msr_bitmap_legacy;
837static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 838static unsigned long *vmx_msr_bitmap_legacy_x2apic;
839static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 840static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 841static unsigned long *vmx_vmread_bitmap;
842static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 843
110312c8 844static bool cpu_has_load_ia32_efer;
8bf00a52 845static bool cpu_has_load_perf_global_ctrl;
110312c8 846
2384d2b3
SY		 847static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
848static DEFINE_SPINLOCK(vmx_vpid_lock);
849
1c3d14fe 850static struct vmcs_config {
6aa8b732
AK		 851 int size;
852 int order;
853 u32 revision_id;
1c3d14fe
YS		 854 u32 pin_based_exec_ctrl;
855 u32 cpu_based_exec_ctrl;
f78e0e2e 856 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 857 u32 vmexit_ctrl;
858 u32 vmentry_ctrl;
859} vmcs_config;
6aa8b732 860
efff9e53 861static struct vmx_capability {
d56f546d
SY		 862 u32 ept;
863 u32 vpid;
864} vmx_capability;
865
6aa8b732
AK		 866#define VMX_SEGMENT_FIELD(seg) \
867 [VCPU_SREG_##seg] = { \
868 .selector = GUEST_##seg##_SELECTOR, \
869 .base = GUEST_##seg##_BASE, \
870 .limit = GUEST_##seg##_LIMIT, \
871 .ar_bytes = GUEST_##seg##_AR_BYTES, \
872 }
873
772e0318 874static const struct kvm_vmx_segment_field {
6aa8b732
AK		 875 unsigned selector;
876 unsigned base;
877 unsigned limit;
878 unsigned ar_bytes;
879} kvm_vmx_segment_fields[] = {
880 VMX_SEGMENT_FIELD(CS),
881 VMX_SEGMENT_FIELD(DS),
882 VMX_SEGMENT_FIELD(ES),
883 VMX_SEGMENT_FIELD(FS),
884 VMX_SEGMENT_FIELD(GS),
885 VMX_SEGMENT_FIELD(SS),
886 VMX_SEGMENT_FIELD(TR),
887 VMX_SEGMENT_FIELD(LDTR),
888};
889
26bb0981
AK		 890static u64 host_efer;
891
6de4f3ad
AK		 892static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
893
4d56c8a7 894/*
8c06585d 895 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 896 * away by decrementing the array size.
897 */
6aa8b732 898static const u32 vmx_msr_index[] = {
05b3e0c2 899#ifdef CONFIG_X86_64
44ea2b17 900 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 901#endif
8c06585d 902 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 903};
6aa8b732 904
31299944 905static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 906{
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
908 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 909 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 910}
911
31299944 912static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 913{
914 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
915 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 916 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 917}
918
31299944 919static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 920{
921 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
922 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 923 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 924}
925
31299944 926static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 927{
928 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
929 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
930}
931
31299944 932static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 933{
934 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
935 INTR_INFO_VALID_MASK)) ==
936 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
937}
938
31299944 939static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 940{
04547156 941 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 942}
943
31299944 944static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 945{
04547156 946 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 947}
948
35754c98 949static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 950{
35754c98 951 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS		 952}
953
31299944 954static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 955{
04547156
SY		 956 return vmcs_config.cpu_based_exec_ctrl &
957 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 958}
959
774ead3a 960static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 961{
04547156
SY		 962 return vmcs_config.cpu_based_2nd_exec_ctrl &
963 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
964}
965
8d14695f
YZ		 966static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
967{
968 return vmcs_config.cpu_based_2nd_exec_ctrl &
969 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
970}
971
83d4c286
YZ		 972static inline bool cpu_has_vmx_apic_register_virt(void)
973{
974 return vmcs_config.cpu_based_2nd_exec_ctrl &
975 SECONDARY_EXEC_APIC_REGISTER_VIRT;
976}
977
c7c9c56c
YZ		 978static inline bool cpu_has_vmx_virtual_intr_delivery(void)
979{
980 return vmcs_config.cpu_based_2nd_exec_ctrl &
981 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
982}
983
01e439be
YZ		 984static inline bool cpu_has_vmx_posted_intr(void)
985{
d6a858d1
PB		 986 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
987 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
01e439be
YZ		 988}
989
990static inline bool cpu_has_vmx_apicv(void)
991{
992 return cpu_has_vmx_apic_register_virt() &&
993 cpu_has_vmx_virtual_intr_delivery() &&
994 cpu_has_vmx_posted_intr();
995}
996
04547156
SY		 997static inline bool cpu_has_vmx_flexpriority(void)
998{
999 return cpu_has_vmx_tpr_shadow() &&
1000 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1001}
1002
e799794e
MT		 1003static inline bool cpu_has_vmx_ept_execute_only(void)
1004{
31299944 1005 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1006}
1007
e799794e
MT		 1008static inline bool cpu_has_vmx_ept_2m_page(void)
1009{
31299944 1010 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1011}
1012
878403b7
SY		 1013static inline bool cpu_has_vmx_ept_1g_page(void)
1014{
31299944 1015 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1016}
1017
4bc9b982
SY		 1018static inline bool cpu_has_vmx_ept_4levels(void)
1019{
1020 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1021}
1022
83c3a331
XH		 1023static inline bool cpu_has_vmx_ept_ad_bits(void)
1024{
1025 return vmx_capability.ept & VMX_EPT_AD_BIT;
1026}
1027
31299944 1028static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1029{
31299944 1030 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1031}
1032
31299944 1033static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1034{
31299944 1035 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1036}
1037
518c8aee
GJ		 1038static inline bool cpu_has_vmx_invvpid_single(void)
1039{
1040 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1041}
1042
b9d762fa
GJ		 1043static inline bool cpu_has_vmx_invvpid_global(void)
1044{
1045 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1046}
1047
31299944 1048static inline bool cpu_has_vmx_ept(void)
d56f546d 1049{
04547156
SY		 1050 return vmcs_config.cpu_based_2nd_exec_ctrl &
1051 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1052}
1053
31299944 1054static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1055{
1056 return vmcs_config.cpu_based_2nd_exec_ctrl &
1057 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1058}
1059
31299944 1060static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1061{
1062 return vmcs_config.cpu_based_2nd_exec_ctrl &
1063 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1064}
1065
35754c98 1066static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1067{
35754c98 1068 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 1069}
1070
31299944 1071static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1072{
04547156
SY		 1073 return vmcs_config.cpu_based_2nd_exec_ctrl &
1074 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1075}
1076
31299944 1077static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1078{
1079 return vmcs_config.cpu_based_2nd_exec_ctrl &
1080 SECONDARY_EXEC_RDTSCP;
1081}
1082
ad756a16
MJ		 1083static inline bool cpu_has_vmx_invpcid(void)
1084{
1085 return vmcs_config.cpu_based_2nd_exec_ctrl &
1086 SECONDARY_EXEC_ENABLE_INVPCID;
1087}
1088
31299944 1089static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1090{
1091 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1092}
1093
f5f48ee1
SY		 1094static inline bool cpu_has_vmx_wbinvd_exit(void)
1095{
1096 return vmcs_config.cpu_based_2nd_exec_ctrl &
1097 SECONDARY_EXEC_WBINVD_EXITING;
1098}
1099
abc4fc58
AG		 1100static inline bool cpu_has_vmx_shadow_vmcs(void)
1101{
1102 u64 vmx_msr;
1103 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1104 /* check if the cpu supports writing r/o exit information fields */
1105 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1106 return false;
1107
1108 return vmcs_config.cpu_based_2nd_exec_ctrl &
1109 SECONDARY_EXEC_SHADOW_VMCS;
1110}
1111
843e4330
KH		 1112static inline bool cpu_has_vmx_pml(void)
1113{
1114 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1115}
1116
04547156
SY		 1117static inline bool report_flexpriority(void)
1118{
1119 return flexpriority_enabled;
1120}
1121
fe3ef05c
NHE		 1122static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1123{
1124 return vmcs12->cpu_based_vm_exec_control & bit;
1125}
1126
1127static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1128{
1129 return (vmcs12->cpu_based_vm_exec_control &
1130 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1131 (vmcs12->secondary_vm_exec_control & bit);
1132}
1133
f5c4368f 1134static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1135{
1136 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1137}
1138
f4124500
JK		 1139static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1140{
1141 return vmcs12->pin_based_vm_exec_control &
1142 PIN_BASED_VMX_PREEMPTION_TIMER;
1143}
1144
155a97a3
NHE		 1145static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1146{
1147 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1148}
1149
81dc01f7
WL		 1150static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1151{
1152 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1153 vmx_xsaves_supported();
1154}
1155
f2b93280
WV		 1156static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1157{
1158 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1159}
1160
82f0dd4b
WV		 1161static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1162{
1163 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1164}
1165
608406e2
WV		 1166static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1167{
1168 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1169}
1170
705699a1
WV		 1171static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1172{
1173 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1174}
1175
644d711a
NHE		 1176static inline bool is_exception(u32 intr_info)
1177{
1178 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1179 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1180}
1181
533558bc
JK		 1182static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1183 u32 exit_intr_info,
1184 unsigned long exit_qualification);
7c177938
NHE		 1185static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1186 struct vmcs12 *vmcs12,
1187 u32 reason, unsigned long qualification);
1188
8b9cf98c 1189static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1190{
1191 int i;
1192
a2fa3e9f 1193 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1194 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1195 return i;
1196 return -1;
1197}
1198
2384d2b3
SY		 1199static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1200{
1201 struct {
1202 u64 vpid : 16;
1203 u64 rsvd : 48;
1204 u64 gva;
1205 } operand = { vpid, 0, gva };
1206
4ecac3fd 1207 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1208 /* CF==1 or ZF==1 --> rc = -1 */
1209 "; ja 1f ; ud2 ; 1:"
1210 : : "a"(&operand), "c"(ext) : "cc", "memory");
1211}
1212
1439442c
SY		 1213static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1214{
1215 struct {
1216 u64 eptp, gpa;
1217 } operand = {eptp, gpa};
1218
4ecac3fd 1219 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1220 /* CF==1 or ZF==1 --> rc = -1 */
1221 "; ja 1f ; ud2 ; 1:\n"
1222 : : "a" (&operand), "c" (ext) : "cc", "memory");
1223}
1224
26bb0981 1225static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1226{
1227 int i;
1228
8b9cf98c 1229 i = __find_msr_index(vmx, msr);
a75beee6 1230 if (i >= 0)
a2fa3e9f 1231 return &vmx->guest_msrs[i];
8b6d44c7 1232 return NULL;
7725f0ba
AK		 1233}
1234
6aa8b732
AK		 1235static void vmcs_clear(struct vmcs *vmcs)
1236{
1237 u64 phys_addr = __pa(vmcs);
1238 u8 error;
1239
4ecac3fd 1240 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1241 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1242 : "cc", "memory");
1243 if (error)
1244 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1245 vmcs, phys_addr);
1246}
1247
d462b819
NHE		 1248static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1249{
1250 vmcs_clear(loaded_vmcs->vmcs);
1251 loaded_vmcs->cpu = -1;
1252 loaded_vmcs->launched = 0;
1253}
1254
7725b894
DX		 1255static void vmcs_load(struct vmcs *vmcs)
1256{
1257 u64 phys_addr = __pa(vmcs);
1258 u8 error;
1259
1260 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1261 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1262 : "cc", "memory");
1263 if (error)
2844d849 1264 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1265 vmcs, phys_addr);
1266}
1267
2965faa5 1268#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 1269/*
1270 * This bitmap is used to indicate whether the vmclear
1271 * operation is enabled on all cpus. All disabled by
1272 * default.
1273 */
1274static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1275
1276static inline void crash_enable_local_vmclear(int cpu)
1277{
1278 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1279}
1280
1281static inline void crash_disable_local_vmclear(int cpu)
1282{
1283 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1284}
1285
1286static inline int crash_local_vmclear_enabled(int cpu)
1287{
1288 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1289}
1290
1291static void crash_vmclear_local_loaded_vmcss(void)
1292{
1293 int cpu = raw_smp_processor_id();
1294 struct loaded_vmcs *v;
1295
1296 if (!crash_local_vmclear_enabled(cpu))
1297 return;
1298
1299 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1300 loaded_vmcss_on_cpu_link)
1301 vmcs_clear(v->vmcs);
1302}
1303#else
1304static inline void crash_enable_local_vmclear(int cpu) { }
1305static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1306#endif /* CONFIG_KEXEC_CORE */
8f536b76 1307
d462b819 1308static void __loaded_vmcs_clear(void *arg)
6aa8b732 1309{
d462b819 1310 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1311 int cpu = raw_smp_processor_id();
6aa8b732 1312
d462b819
NHE		 1313 if (loaded_vmcs->cpu != cpu)
1314 return; /* vcpu migration can race with cpu offline */
1315 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1316 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1317 crash_disable_local_vmclear(cpu);
d462b819 1318 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1319
1320 /*
1321 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1322 * is before setting loaded_vmcs->vcpu to -1 which is done in
1323 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1324 * then adds the vmcs into percpu list before it is deleted.
1325 */
1326 smp_wmb();
1327
d462b819 1328 loaded_vmcs_init(loaded_vmcs);
8f536b76 1329 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1330}
1331
d462b819 1332static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1333{
e6c7d321
XG		 1334 int cpu = loaded_vmcs->cpu;
1335
1336 if (cpu != -1)
1337 smp_call_function_single(cpu,
1338 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1339}
1340
1760dd49 1341static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1342{
1343 if (vmx->vpid == 0)
1344 return;
1345
518c8aee
GJ		 1346 if (cpu_has_vmx_invvpid_single())
1347 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1348}
1349
b9d762fa
GJ		 1350static inline void vpid_sync_vcpu_global(void)
1351{
1352 if (cpu_has_vmx_invvpid_global())
1353 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1354}
1355
1356static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1357{
1358 if (cpu_has_vmx_invvpid_single())
1760dd49 1359 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1360 else
1361 vpid_sync_vcpu_global();
1362}
1363
1439442c
SY		 1364static inline void ept_sync_global(void)
1365{
1366 if (cpu_has_vmx_invept_global())
1367 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1368}
1369
1370static inline void ept_sync_context(u64 eptp)
1371{
089d034e 1372 if (enable_ept) {
1439442c
SY		 1373 if (cpu_has_vmx_invept_context())
1374 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1375 else
1376 ept_sync_global();
1377 }
1378}
1379
96304217 1380static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1381{
5e520e62 1382 unsigned long value;
6aa8b732 1383
5e520e62
AK		 1384 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1385 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1386 return value;
1387}
1388
96304217 1389static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1390{
1391 return vmcs_readl(field);
1392}
1393
96304217 1394static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1395{
1396 return vmcs_readl(field);
1397}
1398
96304217 1399static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1400{
05b3e0c2 1401#ifdef CONFIG_X86_64
6aa8b732
AK		 1402 return vmcs_readl(field);
1403#else
1404 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1405#endif
1406}
1407
e52de1b8
AK		 1408static noinline void vmwrite_error(unsigned long field, unsigned long value)
1409{
1410 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1411 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1412 dump_stack();
1413}
1414
6aa8b732
AK		 1415static void vmcs_writel(unsigned long field, unsigned long value)
1416{
1417 u8 error;
1418
4ecac3fd 1419 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1420 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1421 if (unlikely(error))
1422 vmwrite_error(field, value);
6aa8b732
AK		 1423}
1424
1425static void vmcs_write16(unsigned long field, u16 value)
1426{
1427 vmcs_writel(field, value);
1428}
1429
1430static void vmcs_write32(unsigned long field, u32 value)
1431{
1432 vmcs_writel(field, value);
1433}
1434
1435static void vmcs_write64(unsigned long field, u64 value)
1436{
6aa8b732 1437 vmcs_writel(field, value);
7682f2d0 1438#ifndef CONFIG_X86_64
6aa8b732
AK		 1439 asm volatile ("");
1440 vmcs_writel(field+1, value >> 32);
1441#endif
1442}
1443
2ab455cc
AL		 1444static void vmcs_clear_bits(unsigned long field, u32 mask)
1445{
1446 vmcs_writel(field, vmcs_readl(field) & ~mask);
1447}
1448
1449static void vmcs_set_bits(unsigned long field, u32 mask)
1450{
1451 vmcs_writel(field, vmcs_readl(field) | mask);
1452}
1453
2961e876
GN		 1454static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1455{
1456 vmcs_write32(VM_ENTRY_CONTROLS, val);
1457 vmx->vm_entry_controls_shadow = val;
1458}
1459
1460static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1461{
1462 if (vmx->vm_entry_controls_shadow != val)
1463 vm_entry_controls_init(vmx, val);
1464}
1465
1466static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1467{
1468 return vmx->vm_entry_controls_shadow;
1469}
1470
1471
1472static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1473{
1474 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1475}
1476
1477static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1478{
1479 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1480}
1481
1482static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1483{
1484 vmcs_write32(VM_EXIT_CONTROLS, val);
1485 vmx->vm_exit_controls_shadow = val;
1486}
1487
1488static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1489{
1490 if (vmx->vm_exit_controls_shadow != val)
1491 vm_exit_controls_init(vmx, val);
1492}
1493
1494static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1495{
1496 return vmx->vm_exit_controls_shadow;
1497}
1498
1499
1500static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1501{
1502 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1503}
1504
1505static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1506{
1507 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1508}
1509
2fb92db1
AK		 1510static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1511{
1512 vmx->segment_cache.bitmask = 0;
1513}
1514
1515static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1516 unsigned field)
1517{
1518 bool ret;
1519 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1520
1521 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1522 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1523 vmx->segment_cache.bitmask = 0;
1524 }
1525 ret = vmx->segment_cache.bitmask & mask;
1526 vmx->segment_cache.bitmask |= mask;
1527 return ret;
1528}
1529
1530static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1531{
1532 u16 *p = &vmx->segment_cache.seg[seg].selector;
1533
1534 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1535 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1536 return *p;
1537}
1538
1539static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1540{
1541 ulong *p = &vmx->segment_cache.seg[seg].base;
1542
1543 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1544 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1545 return *p;
1546}
1547
1548static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1549{
1550 u32 *p = &vmx->segment_cache.seg[seg].limit;
1551
1552 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1553 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1554 return *p;
1555}
1556
1557static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1558{
1559 u32 *p = &vmx->segment_cache.seg[seg].ar;
1560
1561 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1562 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1563 return *p;
1564}
1565
abd3f2d6
AK		 1566static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1567{
1568 u32 eb;
1569
fd7373cc
JK		 1570 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1571 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1572 if ((vcpu->guest_debug &
1573 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1574 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1575 eb |= 1u << BP_VECTOR;
7ffd92c5 1576 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1577 eb = ~0;
089d034e 1578 if (enable_ept)
1439442c 1579 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1580 if (vcpu->fpu_active)
1581 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1582
1583 /* When we are running a nested L2 guest and L1 specified for it a
1584 * certain exception bitmap, we must trap the same exceptions and pass
1585 * them to L1. When running L2, we will only handle the exceptions
1586 * specified above if L1 did not want them.
1587 */
1588 if (is_guest_mode(vcpu))
1589 eb |= get_vmcs12(vcpu)->exception_bitmap;
1590
abd3f2d6
AK		 1591 vmcs_write32(EXCEPTION_BITMAP, eb);
1592}
1593
2961e876
GN		 1594static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1595 unsigned long entry, unsigned long exit)
8bf00a52 1596{
2961e876
GN		 1597 vm_entry_controls_clearbit(vmx, entry);
1598 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1599}
1600
61d2ef2c
AK		 1601static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1602{
1603 unsigned i;
1604 struct msr_autoload *m = &vmx->msr_autoload;
1605
8bf00a52
GN		 1606 switch (msr) {
1607 case MSR_EFER:
1608 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1609 clear_atomic_switch_msr_special(vmx,
1610 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1611 VM_EXIT_LOAD_IA32_EFER);
1612 return;
1613 }
1614 break;
1615 case MSR_CORE_PERF_GLOBAL_CTRL:
1616 if (cpu_has_load_perf_global_ctrl) {
2961e876 1617 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1618 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1619 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1620 return;
1621 }
1622 break;
110312c8
AK		 1623 }
1624
61d2ef2c
AK		 1625 for (i = 0; i < m->nr; ++i)
1626 if (m->guest[i].index == msr)
1627 break;
1628
1629 if (i == m->nr)
1630 return;
1631 --m->nr;
1632 m->guest[i] = m->guest[m->nr];
1633 m->host[i] = m->host[m->nr];
1634 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1635 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1636}
1637
2961e876
GN		 1638static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1639 unsigned long entry, unsigned long exit,
1640 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1641 u64 guest_val, u64 host_val)
8bf00a52
GN		 1642{
1643 vmcs_write64(guest_val_vmcs, guest_val);
1644 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1645 vm_entry_controls_setbit(vmx, entry);
1646 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1647}
1648
61d2ef2c
AK		 1649static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1650 u64 guest_val, u64 host_val)
1651{
1652 unsigned i;
1653 struct msr_autoload *m = &vmx->msr_autoload;
1654
8bf00a52
GN		 1655 switch (msr) {
1656 case MSR_EFER:
1657 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1658 add_atomic_switch_msr_special(vmx,
1659 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1660 VM_EXIT_LOAD_IA32_EFER,
1661 GUEST_IA32_EFER,
1662 HOST_IA32_EFER,
1663 guest_val, host_val);
1664 return;
1665 }
1666 break;
1667 case MSR_CORE_PERF_GLOBAL_CTRL:
1668 if (cpu_has_load_perf_global_ctrl) {
2961e876 1669 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1670 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1671 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1672 GUEST_IA32_PERF_GLOBAL_CTRL,
1673 HOST_IA32_PERF_GLOBAL_CTRL,
1674 guest_val, host_val);
1675 return;
1676 }
1677 break;
110312c8
AK		 1678 }
1679
61d2ef2c
AK		 1680 for (i = 0; i < m->nr; ++i)
1681 if (m->guest[i].index == msr)
1682 break;
1683
e7fc6f93 1684 if (i == NR_AUTOLOAD_MSRS) {
60266204 1685 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1686 "Can't add msr %x\n", msr);
1687 return;
1688 } else if (i == m->nr) {
61d2ef2c
AK		 1689 ++m->nr;
1690 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1691 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1692 }
1693
1694 m->guest[i].index = msr;
1695 m->guest[i].value = guest_val;
1696 m->host[i].index = msr;
1697 m->host[i].value = host_val;
1698}
1699
33ed6329
AK		 1700static void reload_tss(void)
1701{
33ed6329
AK		 1702 /*
1703 * VT restores TR but not its size. Useless.
1704 */
89cbc767 1705 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1706 struct desc_struct *descs;
33ed6329 1707
d359192f 1708 descs = (void *)gdt->address;
33ed6329
AK		 1709 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1710 load_TR_desc();
33ed6329
AK		 1711}
1712
92c0d900 1713static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1714{
3a34a881 1715 u64 guest_efer;
51c6cf66
AK		 1716 u64 ignore_bits;
1717
f6801dff 1718 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1719
51c6cf66 1720 /*
0fa06071 1721 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1722 * outside long mode
1723 */
1724 ignore_bits = EFER_NX | EFER_SCE;
1725#ifdef CONFIG_X86_64
1726 ignore_bits |= EFER_LMA | EFER_LME;
1727 /* SCE is meaningful only in long mode on Intel */
1728 if (guest_efer & EFER_LMA)
1729 ignore_bits &= ~(u64)EFER_SCE;
1730#endif
51c6cf66
AK		 1731 guest_efer &= ~ignore_bits;
1732 guest_efer |= host_efer & ignore_bits;
26bb0981 1733 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1734 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1735
1736 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1737
1738 /*
1739 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1740 * On CPUs that support "load IA32_EFER", always switch EFER
1741 * atomically, since it's faster than switching it manually.
1742 */
1743 if (cpu_has_load_ia32_efer ||
1744 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1745 guest_efer = vmx->vcpu.arch.efer;
1746 if (!(guest_efer & EFER_LMA))
1747 guest_efer &= ~EFER_LME;
54b98bff
AL		 1748 if (guest_efer != host_efer)
1749 add_atomic_switch_msr(vmx, MSR_EFER,
1750 guest_efer, host_efer);
84ad33ef
AK		 1751 return false;
1752 }
1753
26bb0981 1754 return true;
51c6cf66
AK		 1755}
1756
2d49ec72
GN		 1757static unsigned long segment_base(u16 selector)
1758{
89cbc767 1759 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1760 struct desc_struct *d;
1761 unsigned long table_base;
1762 unsigned long v;
1763
1764 if (!(selector & ~3))
1765 return 0;
1766
d359192f 1767 table_base = gdt->address;
2d49ec72
GN		 1768
1769 if (selector & 4) { /* from ldt */
1770 u16 ldt_selector = kvm_read_ldt();
1771
1772 if (!(ldt_selector & ~3))
1773 return 0;
1774
1775 table_base = segment_base(ldt_selector);
1776 }
1777 d = (struct desc_struct *)(table_base + (selector & ~7));
1778 v = get_desc_base(d);
1779#ifdef CONFIG_X86_64
1780 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1781 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1782#endif
1783 return v;
1784}
1785
1786static inline unsigned long kvm_read_tr_base(void)
1787{
1788 u16 tr;
1789 asm("str %0" : "=g"(tr));
1790 return segment_base(tr);
1791}
1792
04d2cc77 1793static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1794{
04d2cc77 1795 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1796 int i;
04d2cc77 1797
a2fa3e9f 1798 if (vmx->host_state.loaded)
33ed6329
AK		 1799 return;
1800
a2fa3e9f 1801 vmx->host_state.loaded = 1;
33ed6329
AK		 1802 /*
1803 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1804 * allow segment selectors with cpl > 0 or ti == 1.
1805 */
d6e88aec 1806 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1807 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1808 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1809 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1810 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1811 vmx->host_state.fs_reload_needed = 0;
1812 } else {
33ed6329 1813 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1814 vmx->host_state.fs_reload_needed = 1;
33ed6329 1815 }
9581d442 1816 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1817 if (!(vmx->host_state.gs_sel & 7))
1818 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1819 else {
1820 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1821 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1822 }
1823
b2da15ac
AK		 1824#ifdef CONFIG_X86_64
1825 savesegment(ds, vmx->host_state.ds_sel);
1826 savesegment(es, vmx->host_state.es_sel);
1827#endif
1828
33ed6329
AK		 1829#ifdef CONFIG_X86_64
1830 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1831 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1832#else
a2fa3e9f
GH		 1833 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1834 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1835#endif
707c0874
AK		 1836
1837#ifdef CONFIG_X86_64
c8770e7b
AK		 1838 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1839 if (is_long_mode(&vmx->vcpu))
44ea2b17 1840 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1841#endif
da8999d3
LJ		 1842 if (boot_cpu_has(X86_FEATURE_MPX))
1843 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1844 for (i = 0; i < vmx->save_nmsrs; ++i)
1845 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1846 vmx->guest_msrs[i].data,
1847 vmx->guest_msrs[i].mask);
33ed6329
AK		 1848}
1849
a9b21b62 1850static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1851{
a2fa3e9f 1852 if (!vmx->host_state.loaded)
33ed6329
AK		 1853 return;
1854
e1beb1d3 1855 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1856 vmx->host_state.loaded = 0;
c8770e7b
AK		 1857#ifdef CONFIG_X86_64
1858 if (is_long_mode(&vmx->vcpu))
1859 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1860#endif
152d3f2f 1861 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1862 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1863#ifdef CONFIG_X86_64
9581d442 1864 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1865#else
1866 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1867#endif
33ed6329 1868 }
0a77fe4c
AK		 1869 if (vmx->host_state.fs_reload_needed)
1870 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1871#ifdef CONFIG_X86_64
1872 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1873 loadsegment(ds, vmx->host_state.ds_sel);
1874 loadsegment(es, vmx->host_state.es_sel);
1875 }
b2da15ac 1876#endif
152d3f2f 1877 reload_tss();
44ea2b17 1878#ifdef CONFIG_X86_64
c8770e7b 1879 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1880#endif
da8999d3
LJ		 1881 if (vmx->host_state.msr_host_bndcfgs)
1882 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1883 /*
1884 * If the FPU is not active (through the host task or
1885 * the guest vcpu), then restore the cr0.TS bit.
1886 */
3c6dffa9 1887 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
b1a74bf8 1888 stts();
89cbc767 1889 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1890}
1891
a9b21b62
AK		 1892static void vmx_load_host_state(struct vcpu_vmx *vmx)
1893{
1894 preempt_disable();
1895 __vmx_load_host_state(vmx);
1896 preempt_enable();
1897}
1898
6aa8b732
AK		 1899/*
1900 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1901 * vcpu mutex is already taken.
1902 */
15ad7146 1903static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1904{
a2fa3e9f 1905 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1906 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1907
4610c9cc
DX		 1908 if (!vmm_exclusive)
1909 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1910 else if (vmx->loaded_vmcs->cpu != cpu)
1911 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1912
d462b819
NHE		 1913 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1914 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1915 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1916 }
1917
d462b819 1918 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1919 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1920 unsigned long sysenter_esp;
1921
a8eeb04a 1922 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1923 local_irq_disable();
8f536b76 1924 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1925
1926 /*
1927 * Read loaded_vmcs->cpu should be before fetching
1928 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1929 * See the comments in __loaded_vmcs_clear().
1930 */
1931 smp_rmb();
1932
d462b819
NHE		 1933 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1934 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1935 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1936 local_irq_enable();
1937
6aa8b732
AK		 1938 /*
1939 * Linux uses per-cpu TSS and GDT, so set these when switching
1940 * processors.
1941 */
d6e88aec 1942 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1943 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1944
1945 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1946 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1947 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1948 }
6aa8b732
AK		 1949}
1950
1951static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1952{
a9b21b62 1953 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1954 if (!vmm_exclusive) {
d462b819
NHE		 1955 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1956 vcpu->cpu = -1;
4610c9cc
DX		 1957 kvm_cpu_vmxoff();
1958 }
6aa8b732
AK		 1959}
1960
5fd86fcf
AK		 1961static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1962{
81231c69
AK		 1963 ulong cr0;
1964
5fd86fcf
AK		 1965 if (vcpu->fpu_active)
1966 return;
1967 vcpu->fpu_active = 1;
81231c69
AK		 1968 cr0 = vmcs_readl(GUEST_CR0);
1969 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1970 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1971 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1972 update_exception_bitmap(vcpu);
edcafe3c 1973 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1974 if (is_guest_mode(vcpu))
1975 vcpu->arch.cr0_guest_owned_bits &=
1976 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1977 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1978}
1979
edcafe3c
AK		 1980static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1981
fe3ef05c
NHE		 1982/*
1983 * Return the cr0 value that a nested guest would read. This is a combination
1984 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1985 * its hypervisor (cr0_read_shadow).
1986 */
1987static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1988{
1989 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1990 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1991}
1992static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1993{
1994 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1995 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1996}
1997
5fd86fcf
AK		 1998static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1999{
36cf24e0
NHE		 2000 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2001 * set this *before* calling this function.
2002 */
edcafe3c 2003 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2004 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2005 update_exception_bitmap(vcpu);
edcafe3c
AK		 2006 vcpu->arch.cr0_guest_owned_bits = 0;
2007 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2008 if (is_guest_mode(vcpu)) {
2009 /*
2010 * L1's specified read shadow might not contain the TS bit,
2011 * so now that we turned on shadowing of this bit, we need to
2012 * set this bit of the shadow. Like in nested_vmx_run we need
2013 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2014 * up-to-date here because we just decached cr0.TS (and we'll
2015 * only update vmcs12->guest_cr0 on nested exit).
2016 */
2017 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2018 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2019 (vcpu->arch.cr0 & X86_CR0_TS);
2020 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2021 } else
2022 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2023}
2024
6aa8b732
AK		 2025static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2026{
78ac8b47 2027 unsigned long rflags, save_rflags;
345dcaa8 2028
6de12732
AK		 2029 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2030 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2031 rflags = vmcs_readl(GUEST_RFLAGS);
2032 if (to_vmx(vcpu)->rmode.vm86_active) {
2033 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2034 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2035 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2036 }
2037 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2038 }
6de12732 2039 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2040}
2041
2042static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2043{
6de12732
AK		 2044 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2045 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2046 if (to_vmx(vcpu)->rmode.vm86_active) {
2047 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2048 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2049 }
6aa8b732
AK		 2050 vmcs_writel(GUEST_RFLAGS, rflags);
2051}
2052
37ccdcbe 2053static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2054{
2055 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2056 int ret = 0;
2057
2058 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2059 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2060 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2061 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2062
37ccdcbe 2063 return ret;
2809f5d2
GC		 2064}
2065
2066static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2067{
2068 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2069 u32 interruptibility = interruptibility_old;
2070
2071 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2072
48005f64 2073 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2074 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2075 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2076 interruptibility |= GUEST_INTR_STATE_STI;
2077
2078 if ((interruptibility != interruptibility_old))
2079 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2080}
2081
6aa8b732
AK		 2082static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2083{
2084 unsigned long rip;
6aa8b732 2085
5fdbf976 2086 rip = kvm_rip_read(vcpu);
6aa8b732 2087 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2088 kvm_rip_write(vcpu, rip);
6aa8b732 2089
2809f5d2
GC		 2090 /* skipping an emulated instruction also counts */
2091 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2092}
2093
0b6ac343
NHE		 2094/*
2095 * KVM wants to inject page-faults which it got to the guest. This function
2096 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2097 */
e011c663 2098static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2099{
2100 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2101
e011c663 2102 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2103 return 0;
2104
533558bc
JK		 2105 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2106 vmcs_read32(VM_EXIT_INTR_INFO),
2107 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2108 return 1;
2109}
2110
298101da 2111static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2112 bool has_error_code, u32 error_code,
2113 bool reinject)
298101da 2114{
77ab6db0 2115 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2116 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2117
e011c663
GN		 2118 if (!reinject && is_guest_mode(vcpu) &&
2119 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2120 return;
2121
8ab2d2e2 2122 if (has_error_code) {
77ab6db0 2123 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2124 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2125 }
77ab6db0 2126
7ffd92c5 2127 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2128 int inc_eip = 0;
2129 if (kvm_exception_is_soft(nr))
2130 inc_eip = vcpu->arch.event_exit_inst_len;
2131 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2132 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2133 return;
2134 }
2135
66fd3f7f
GN		 2136 if (kvm_exception_is_soft(nr)) {
2137 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2138 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2139 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2140 } else
2141 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2142
2143 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2144}
2145
4e47c7a6
SY		 2146static bool vmx_rdtscp_supported(void)
2147{
2148 return cpu_has_vmx_rdtscp();
2149}
2150
ad756a16
MJ		 2151static bool vmx_invpcid_supported(void)
2152{
2153 return cpu_has_vmx_invpcid() && enable_ept;
2154}
2155
a75beee6
ED		 2156/*
2157 * Swap MSR entry in host/guest MSR entry array.
2158 */
8b9cf98c 2159static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2160{
26bb0981 2161 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2162
2163 tmp = vmx->guest_msrs[to];
2164 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2165 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2166}
2167
8d14695f
YZ		 2168static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2169{
2170 unsigned long *msr_bitmap;
2171
670125bd
WV		 2172 if (is_guest_mode(vcpu))
2173 msr_bitmap = vmx_msr_bitmap_nested;
8a9781f7 2174 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
8d14695f
YZ		 2175 if (is_long_mode(vcpu))
2176 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2177 else
2178 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2179 } else {
2180 if (is_long_mode(vcpu))
2181 msr_bitmap = vmx_msr_bitmap_longmode;
2182 else
2183 msr_bitmap = vmx_msr_bitmap_legacy;
2184 }
2185
2186 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2187}
2188
e38aea3e
AK		 2189/*
2190 * Set up the vmcs to automatically save and restore system
2191 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2192 * mode, as fiddling with msrs is very expensive.
2193 */
8b9cf98c 2194static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2195{
26bb0981 2196 int save_nmsrs, index;
e38aea3e 2197
a75beee6
ED		 2198 save_nmsrs = 0;
2199#ifdef CONFIG_X86_64
8b9cf98c 2200 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2201 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2202 if (index >= 0)
8b9cf98c
RR		 2203 move_msr_up(vmx, index, save_nmsrs++);
2204 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2205 if (index >= 0)
8b9cf98c
RR		 2206 move_msr_up(vmx, index, save_nmsrs++);
2207 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2208 if (index >= 0)
8b9cf98c 2209 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2210 index = __find_msr_index(vmx, MSR_TSC_AUX);
2211 if (index >= 0 && vmx->rdtscp_enabled)
2212 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2213 /*
8c06585d 2214 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2215 * if efer.sce is enabled.
2216 */
8c06585d 2217 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2218 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2219 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2220 }
2221#endif
92c0d900
AK		 2222 index = __find_msr_index(vmx, MSR_EFER);
2223 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2224 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2225
26bb0981 2226 vmx->save_nmsrs = save_nmsrs;
5897297b 2227
8d14695f
YZ		 2228 if (cpu_has_vmx_msr_bitmap())
2229 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2230}
2231
6aa8b732
AK		 2232/*
2233 * reads and returns guest's timestamp counter "register"
2234 * guest_tsc = host_tsc + tsc_offset -- 21.3
2235 */
2236static u64 guest_read_tsc(void)
2237{
2238 u64 host_tsc, tsc_offset;
2239
4ea1636b 2240 host_tsc = rdtsc();
6aa8b732
AK		 2241 tsc_offset = vmcs_read64(TSC_OFFSET);
2242 return host_tsc + tsc_offset;
2243}
2244
d5c1785d
NHE		 2245/*
2246 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2247 * counter, even if a nested guest (L2) is currently running.
2248 */
48d89b92 2249static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2250{
886b470c 2251 u64 tsc_offset;
d5c1785d 2252
d5c1785d
NHE		 2253 tsc_offset = is_guest_mode(vcpu) ?
2254 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2255 vmcs_read64(TSC_OFFSET);
2256 return host_tsc + tsc_offset;
2257}
2258
4051b188 2259/*
cc578287
ZA		 2260 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2261 * software catchup for faster rates on slower CPUs.
4051b188 2262 */
cc578287 2263static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2264{
cc578287
ZA		 2265 if (!scale)
2266 return;
2267
2268 if (user_tsc_khz > tsc_khz) {
2269 vcpu->arch.tsc_catchup = 1;
2270 vcpu->arch.tsc_always_catchup = 1;
2271 } else
2272 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2273}
2274
ba904635
WA		 2275static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2276{
2277 return vmcs_read64(TSC_OFFSET);
2278}
2279
6aa8b732 2280/*
99e3e30a 2281 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2282 */
99e3e30a 2283static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2284{
27fc51b2 2285 if (is_guest_mode(vcpu)) {
7991825b 2286 /*
27fc51b2
NHE		 2287 * We're here if L1 chose not to trap WRMSR to TSC. According
2288 * to the spec, this should set L1's TSC; The offset that L1
2289 * set for L2 remains unchanged, and still needs to be added
2290 * to the newly set TSC to get L2's TSC.
7991825b 2291 */
27fc51b2
NHE		 2292 struct vmcs12 *vmcs12;
2293 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2294 /* recalculate vmcs02.TSC_OFFSET: */
2295 vmcs12 = get_vmcs12(vcpu);
2296 vmcs_write64(TSC_OFFSET, offset +
2297 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2298 vmcs12->tsc_offset : 0));
2299 } else {
489223ed
YY		 2300 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2301 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2302 vmcs_write64(TSC_OFFSET, offset);
2303 }
6aa8b732
AK		 2304}
2305
f1e2b260 2306static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2307{
2308 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2309
e48672fa 2310 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2311 if (is_guest_mode(vcpu)) {
2312 /* Even when running L2, the adjustment needs to apply to L1 */
2313 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2314 } else
2315 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2316 offset + adjustment);
e48672fa
ZA		 2317}
2318
857e4099
JR		 2319static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2320{
4ea1636b 2321 return target_tsc - rdtsc();
857e4099
JR		 2322}
2323
801d3424
NHE		 2324static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2325{
2326 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2327 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2328}
2329
2330/*
2331 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2332 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2333 * all guests if the "nested" module option is off, and can also be disabled
2334 * for a single guest by disabling its VMX cpuid bit.
2335 */
2336static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2337{
2338 return nested && guest_cpuid_has_vmx(vcpu);
2339}
2340
b87a51ae
NHE		 2341/*
2342 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2343 * returned for the various VMX controls MSRs when nested VMX is enabled.
2344 * The same values should also be used to verify that vmcs12 control fields are
2345 * valid during nested entry from L1 to L2.
2346 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2347 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2348 * bit in the high half is on if the corresponding bit in the control field
2349 * may be on. See also vmx_control_verify().
b87a51ae 2350 */
b9c237bb 2351static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2352{
2353 /*
2354 * Note that as a general rule, the high half of the MSRs (bits in
2355 * the control fields which may be 1) should be initialized by the
2356 * intersection of the underlying hardware's MSR (i.e., features which
2357 * can be supported) and the list of features we want to expose -
2358 * because they are known to be properly supported in our code.
2359 * Also, usually, the low half of the MSRs (bits which must be 1) can
2360 * be set to 0, meaning that L1 may turn off any of these bits. The
2361 * reason is that if one of these bits is necessary, it will appear
2362 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2363 * fields of vmcs01 and vmcs02, will turn these bits off - and
2364 * nested_vmx_exit_handled() will not pass related exits to L1.
2365 * These rules have exceptions below.
2366 */
2367
2368 /* pin-based controls */
eabeaacc 2369 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2370 vmx->nested.nested_vmx_pinbased_ctls_low,
2371 vmx->nested.nested_vmx_pinbased_ctls_high);
2372 vmx->nested.nested_vmx_pinbased_ctls_low |=
2373 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2374 vmx->nested.nested_vmx_pinbased_ctls_high &=
2375 PIN_BASED_EXT_INTR_MASK |
2376 PIN_BASED_NMI_EXITING |
2377 PIN_BASED_VIRTUAL_NMIS;
2378 vmx->nested.nested_vmx_pinbased_ctls_high |=
2379 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2380 PIN_BASED_VMX_PREEMPTION_TIMER;
35754c98 2381 if (vmx_cpu_uses_apicv(&vmx->vcpu))
705699a1
WV		 2382 vmx->nested.nested_vmx_pinbased_ctls_high |=
2383 PIN_BASED_POSTED_INTR;
b87a51ae 2384
3dbcd8da 2385 /* exit controls */
c0dfee58 2386 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2387 vmx->nested.nested_vmx_exit_ctls_low,
2388 vmx->nested.nested_vmx_exit_ctls_high);
2389 vmx->nested.nested_vmx_exit_ctls_low =
2390 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2391
b9c237bb 2392 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2393#ifdef CONFIG_X86_64
c0dfee58 2394 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2395#endif
f4124500 2396 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2397 vmx->nested.nested_vmx_exit_ctls_high |=
2398 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2399 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2400 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2401
36be0b9d 2402 if (vmx_mpx_supported())
b9c237bb 2403 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2404
2996fca0 2405 /* We support free control of debug control saving. */
b9c237bb
WV		 2406 vmx->nested.nested_vmx_true_exit_ctls_low =
2407 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2408 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2409
b87a51ae
NHE		 2410 /* entry controls */
2411 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2412 vmx->nested.nested_vmx_entry_ctls_low,
2413 vmx->nested.nested_vmx_entry_ctls_high);
2414 vmx->nested.nested_vmx_entry_ctls_low =
2415 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2416 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2417#ifdef CONFIG_X86_64
2418 VM_ENTRY_IA32E_MODE |
2419#endif
2420 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2421 vmx->nested.nested_vmx_entry_ctls_high |=
2422 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2423 if (vmx_mpx_supported())
b9c237bb 2424 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2425
2996fca0 2426 /* We support free control of debug control loading. */
b9c237bb
WV		 2427 vmx->nested.nested_vmx_true_entry_ctls_low =
2428 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2429 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2430
b87a51ae
NHE		 2431 /* cpu-based controls */
2432 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2433 vmx->nested.nested_vmx_procbased_ctls_low,
2434 vmx->nested.nested_vmx_procbased_ctls_high);
2435 vmx->nested.nested_vmx_procbased_ctls_low =
2436 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2437 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2438 CPU_BASED_VIRTUAL_INTR_PENDING |
2439 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2440 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2441 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2442 CPU_BASED_CR3_STORE_EXITING |
2443#ifdef CONFIG_X86_64
2444 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2445#endif
2446 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD		 2447 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2448 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2449 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2450 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE		 2451 /*
2452 * We can allow some features even when not supported by the
2453 * hardware. For example, L1 can specify an MSR bitmap - and we
2454 * can use it to avoid exits to L1 - even when L0 runs L2
2455 * without MSR bitmaps.
2456 */
b9c237bb
WV		 2457 vmx->nested.nested_vmx_procbased_ctls_high |=
2458 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2459 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2460
3dcdf3ec 2461 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2462 vmx->nested.nested_vmx_true_procbased_ctls_low =
2463 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2464 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2465
b87a51ae
NHE		 2466 /* secondary cpu-based controls */
2467 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2468 vmx->nested.nested_vmx_secondary_ctls_low,
2469 vmx->nested.nested_vmx_secondary_ctls_high);
2470 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2471 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2472 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2473 SECONDARY_EXEC_RDTSCP |
f2b93280 2474 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2475 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2476 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7
WL		 2477 SECONDARY_EXEC_WBINVD_EXITING |
2478 SECONDARY_EXEC_XSAVES;
c18911a2 2479
afa61f75
NHE		 2480 if (enable_ept) {
2481 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2482 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2483 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2484 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2485 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2486 VMX_EPT_INVEPT_BIT;
b9c237bb 2487 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2488 /*
4b855078
BD		 2489 * For nested guests, we don't do anything specific
2490 * for single context invalidation. Hence, only advertise
2491 * support for global context invalidation.
afa61f75 2492 */
b9c237bb 2493 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2494 } else
b9c237bb 2495 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2496
0790ec17
RK		 2497 if (enable_unrestricted_guest)
2498 vmx->nested.nested_vmx_secondary_ctls_high |=
2499 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2500
c18911a2 2501 /* miscellaneous data */
b9c237bb
WV		 2502 rdmsr(MSR_IA32_VMX_MISC,
2503 vmx->nested.nested_vmx_misc_low,
2504 vmx->nested.nested_vmx_misc_high);
2505 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2506 vmx->nested.nested_vmx_misc_low |=
2507 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2508 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2509 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2510}
2511
2512static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2513{
2514 /*
2515 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2516 */
2517 return ((control & high) | low) == control;
2518}
2519
2520static inline u64 vmx_control_msr(u32 low, u32 high)
2521{
2522 return low | ((u64)high << 32);
2523}
2524
cae50139 2525/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2526static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2527{
b9c237bb
WV		 2528 struct vcpu_vmx *vmx = to_vmx(vcpu);
2529
b87a51ae 2530 switch (msr_index) {
b87a51ae
NHE		 2531 case MSR_IA32_VMX_BASIC:
2532 /*
2533 * This MSR reports some information about VMX support. We
2534 * should return information about the VMX we emulate for the
2535 * guest, and the VMCS structure we give it - not about the
2536 * VMX support of the underlying hardware.
2537 */
3dbcd8da 2538 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2539 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2540 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2541 break;
2542 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2543 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2544 *pdata = vmx_control_msr(
2545 vmx->nested.nested_vmx_pinbased_ctls_low,
2546 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2547 break;
2548 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2549 *pdata = vmx_control_msr(
2550 vmx->nested.nested_vmx_true_procbased_ctls_low,
2551 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2552 break;
b87a51ae 2553 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2554 *pdata = vmx_control_msr(
2555 vmx->nested.nested_vmx_procbased_ctls_low,
2556 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2557 break;
2558 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2559 *pdata = vmx_control_msr(
2560 vmx->nested.nested_vmx_true_exit_ctls_low,
2561 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2562 break;
b87a51ae 2563 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2564 *pdata = vmx_control_msr(
2565 vmx->nested.nested_vmx_exit_ctls_low,
2566 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2567 break;
2568 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2569 *pdata = vmx_control_msr(
2570 vmx->nested.nested_vmx_true_entry_ctls_low,
2571 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2572 break;
b87a51ae 2573 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2574 *pdata = vmx_control_msr(
2575 vmx->nested.nested_vmx_entry_ctls_low,
2576 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2577 break;
2578 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2579 *pdata = vmx_control_msr(
2580 vmx->nested.nested_vmx_misc_low,
2581 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2582 break;
2583 /*
2584 * These MSRs specify bits which the guest must keep fixed (on or off)
2585 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2586 * We picked the standard core2 setting.
2587 */
2588#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2589#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2590 case MSR_IA32_VMX_CR0_FIXED0:
2591 *pdata = VMXON_CR0_ALWAYSON;
2592 break;
2593 case MSR_IA32_VMX_CR0_FIXED1:
2594 *pdata = -1ULL;
2595 break;
2596 case MSR_IA32_VMX_CR4_FIXED0:
2597 *pdata = VMXON_CR4_ALWAYSON;
2598 break;
2599 case MSR_IA32_VMX_CR4_FIXED1:
2600 *pdata = -1ULL;
2601 break;
2602 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2603 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2604 break;
2605 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2606 *pdata = vmx_control_msr(
2607 vmx->nested.nested_vmx_secondary_ctls_low,
2608 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2609 break;
2610 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2611 /* Currently, no nested vpid support */
b9c237bb 2612 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2613 break;
2614 default:
b87a51ae 2615 return 1;
b3897a49
NHE		 2616 }
2617
b87a51ae
NHE		 2618 return 0;
2619}
2620
6aa8b732
AK		 2621/*
2622 * Reads an msr value (of 'msr_index') into 'pdata'.
2623 * Returns 0 on success, non-0 otherwise.
2624 * Assumes vcpu_load() was already called.
2625 */
609e36d3 2626static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2627{
26bb0981 2628 struct shared_msr_entry *msr;
6aa8b732 2629
609e36d3 2630 switch (msr_info->index) {
05b3e0c2 2631#ifdef CONFIG_X86_64
6aa8b732 2632 case MSR_FS_BASE:
609e36d3 2633 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK		 2634 break;
2635 case MSR_GS_BASE:
609e36d3 2636 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 2637 break;
44ea2b17
AK		 2638 case MSR_KERNEL_GS_BASE:
2639 vmx_load_host_state(to_vmx(vcpu));
609e36d3 2640 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 2641 break;
26bb0981 2642#endif
6aa8b732 2643 case MSR_EFER:
609e36d3 2644 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 2645 case MSR_IA32_TSC:
609e36d3 2646 msr_info->data = guest_read_tsc();
6aa8b732
AK		 2647 break;
2648 case MSR_IA32_SYSENTER_CS:
609e36d3 2649 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 2650 break;
2651 case MSR_IA32_SYSENTER_EIP:
609e36d3 2652 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2653 break;
2654 case MSR_IA32_SYSENTER_ESP:
609e36d3 2655 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2656 break;
0dd376e7 2657 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2658 if (!vmx_mpx_supported())
2659 return 1;
609e36d3 2660 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 2661 break;
cae50139
JK		 2662 case MSR_IA32_FEATURE_CONTROL:
2663 if (!nested_vmx_allowed(vcpu))
2664 return 1;
609e36d3 2665 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
cae50139
JK		 2666 break;
2667 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2668 if (!nested_vmx_allowed(vcpu))
2669 return 1;
609e36d3 2670 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL		 2671 case MSR_IA32_XSS:
2672 if (!vmx_xsaves_supported())
2673 return 1;
609e36d3 2674 msr_info->data = vcpu->arch.ia32_xss;
20300099 2675 break;
4e47c7a6
SY		 2676 case MSR_TSC_AUX:
2677 if (!to_vmx(vcpu)->rdtscp_enabled)
2678 return 1;
2679 /* Otherwise falls through */
6aa8b732 2680 default:
609e36d3 2681 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 2682 if (msr) {
609e36d3 2683 msr_info->data = msr->data;
3bab1f5d 2684 break;
6aa8b732 2685 }
609e36d3 2686 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2687 }
2688
6aa8b732
AK		 2689 return 0;
2690}
2691
cae50139
JK		 2692static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2693
6aa8b732
AK		 2694/*
2695 * Writes msr value into into the appropriate "register".
2696 * Returns 0 on success, non-0 otherwise.
2697 * Assumes vcpu_load() was already called.
2698 */
8fe8ab46 2699static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2700{
a2fa3e9f 2701 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2702 struct shared_msr_entry *msr;
2cc51560 2703 int ret = 0;
8fe8ab46
WA		 2704 u32 msr_index = msr_info->index;
2705 u64 data = msr_info->data;
2cc51560 2706
6aa8b732 2707 switch (msr_index) {
3bab1f5d 2708 case MSR_EFER:
8fe8ab46 2709 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2710 break;
16175a79 2711#ifdef CONFIG_X86_64
6aa8b732 2712 case MSR_FS_BASE:
2fb92db1 2713 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2714 vmcs_writel(GUEST_FS_BASE, data);
2715 break;
2716 case MSR_GS_BASE:
2fb92db1 2717 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2718 vmcs_writel(GUEST_GS_BASE, data);
2719 break;
44ea2b17
AK		 2720 case MSR_KERNEL_GS_BASE:
2721 vmx_load_host_state(vmx);
2722 vmx->msr_guest_kernel_gs_base = data;
2723 break;
6aa8b732
AK		 2724#endif
2725 case MSR_IA32_SYSENTER_CS:
2726 vmcs_write32(GUEST_SYSENTER_CS, data);
2727 break;
2728 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2729 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2730 break;
2731 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2732 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2733 break;
0dd376e7 2734 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2735 if (!vmx_mpx_supported())
2736 return 1;
0dd376e7
LJ		 2737 vmcs_write64(GUEST_BNDCFGS, data);
2738 break;
af24a4e4 2739 case MSR_IA32_TSC:
8fe8ab46 2740 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2741 break;
468d472f
SY		 2742 case MSR_IA32_CR_PAT:
2743 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2744 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2745 return 1;
468d472f
SY		 2746 vmcs_write64(GUEST_IA32_PAT, data);
2747 vcpu->arch.pat = data;
2748 break;
2749 }
8fe8ab46 2750 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2751 break;
ba904635
WA		 2752 case MSR_IA32_TSC_ADJUST:
2753 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2754 break;
cae50139
JK		 2755 case MSR_IA32_FEATURE_CONTROL:
2756 if (!nested_vmx_allowed(vcpu) ||
2757 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2758 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2759 return 1;
2760 vmx->nested.msr_ia32_feature_control = data;
2761 if (msr_info->host_initiated && data == 0)
2762 vmx_leave_nested(vcpu);
2763 break;
2764 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2765 return 1; /* they are read-only */
20300099
WL		 2766 case MSR_IA32_XSS:
2767 if (!vmx_xsaves_supported())
2768 return 1;
2769 /*
2770 * The only supported bit as of Skylake is bit 8, but
2771 * it is not supported on KVM.
2772 */
2773 if (data != 0)
2774 return 1;
2775 vcpu->arch.ia32_xss = data;
2776 if (vcpu->arch.ia32_xss != host_xss)
2777 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2778 vcpu->arch.ia32_xss, host_xss);
2779 else
2780 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2781 break;
4e47c7a6
SY		 2782 case MSR_TSC_AUX:
2783 if (!vmx->rdtscp_enabled)
2784 return 1;
2785 /* Check reserved bit, higher 32 bits should be zero */
2786 if ((data >> 32) != 0)
2787 return 1;
2788 /* Otherwise falls through */
6aa8b732 2789 default:
8b9cf98c 2790 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2791 if (msr) {
8b3c3104 2792 u64 old_msr_data = msr->data;
3bab1f5d 2793 msr->data = data;
2225fd56
AK		 2794 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2795 preempt_disable();
8b3c3104
AH		 2796 ret = kvm_set_shared_msr(msr->index, msr->data,
2797 msr->mask);
2225fd56 2798 preempt_enable();
8b3c3104
AH		 2799 if (ret)
2800 msr->data = old_msr_data;
2225fd56 2801 }
3bab1f5d 2802 break;
6aa8b732 2803 }
8fe8ab46 2804 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2805 }
2806
2cc51560 2807 return ret;
6aa8b732
AK		 2808}
2809
5fdbf976 2810static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2811{
5fdbf976
MT		 2812 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2813 switch (reg) {
2814 case VCPU_REGS_RSP:
2815 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2816 break;
2817 case VCPU_REGS_RIP:
2818 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2819 break;
6de4f3ad
AK		 2820 case VCPU_EXREG_PDPTR:
2821 if (enable_ept)
2822 ept_save_pdptrs(vcpu);
2823 break;
5fdbf976
MT		 2824 default:
2825 break;
2826 }
6aa8b732
AK		 2827}
2828
6aa8b732
AK		 2829static __init int cpu_has_kvm_support(void)
2830{
6210e37b 2831 return cpu_has_vmx();
6aa8b732
AK		 2832}
2833
2834static __init int vmx_disabled_by_bios(void)
2835{
2836 u64 msr;
2837
2838 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2839 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2840 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2841 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2842 && tboot_enabled())
2843 return 1;
23f3e991 2844 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2845 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2846 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2847 && !tboot_enabled()) {
2848 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2849 "activate TXT before enabling KVM\n");
cafd6659 2850 return 1;
f9335afe 2851 }
23f3e991
JC		 2852 /* launched w/o TXT and VMX disabled */
2853 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2854 && !tboot_enabled())
2855 return 1;
cafd6659
SW		 2856 }
2857
2858 return 0;
6aa8b732
AK		 2859}
2860
7725b894
DX		 2861static void kvm_cpu_vmxon(u64 addr)
2862{
2863 asm volatile (ASM_VMX_VMXON_RAX
2864 : : "a"(&addr), "m"(addr)
2865 : "memory", "cc");
2866}
2867
13a34e06 2868static int hardware_enable(void)
6aa8b732
AK		 2869{
2870 int cpu = raw_smp_processor_id();
2871 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2872 u64 old, test_bits;
6aa8b732 2873
1e02ce4c 2874 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2875 return -EBUSY;
2876
d462b819 2877 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2878
2879 /*
2880 * Now we can enable the vmclear operation in kdump
2881 * since the loaded_vmcss_on_cpu list on this cpu
2882 * has been initialized.
2883 *
2884 * Though the cpu is not in VMX operation now, there
2885 * is no problem to enable the vmclear operation
2886 * for the loaded_vmcss_on_cpu list is empty!
2887 */
2888 crash_enable_local_vmclear(cpu);
2889
6aa8b732 2890 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2891
2892 test_bits = FEATURE_CONTROL_LOCKED;
2893 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2894 if (tboot_enabled())
2895 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2896
2897 if ((old & test_bits) != test_bits) {
6aa8b732 2898 /* enable and lock */
cafd6659
SW		 2899 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2900 }
375074cc 2901 cr4_set_bits(X86_CR4_VMXE);
10474ae8 2902
4610c9cc
DX		 2903 if (vmm_exclusive) {
2904 kvm_cpu_vmxon(phys_addr);
2905 ept_sync_global();
2906 }
10474ae8 2907
89cbc767 2908 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2909
10474ae8 2910 return 0;
6aa8b732
AK		 2911}
2912
d462b819 2913static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2914{
2915 int cpu = raw_smp_processor_id();
d462b819 2916 struct loaded_vmcs *v, *n;
543e4243 2917
d462b819
NHE		 2918 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2919 loaded_vmcss_on_cpu_link)
2920 __loaded_vmcs_clear(v);
543e4243
AK		 2921}
2922
710ff4a8
EH		 2923
2924/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2925 * tricks.
2926 */
2927static void kvm_cpu_vmxoff(void)
6aa8b732 2928{
4ecac3fd 2929 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2930}
2931
13a34e06 2932static void hardware_disable(void)
710ff4a8 2933{
4610c9cc 2934 if (vmm_exclusive) {
d462b819 2935 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2936 kvm_cpu_vmxoff();
2937 }
375074cc 2938 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 2939}
2940
1c3d14fe 2941static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2942 u32 msr, u32 *result)
1c3d14fe
YS		 2943{
2944 u32 vmx_msr_low, vmx_msr_high;
2945 u32 ctl = ctl_min | ctl_opt;
2946
2947 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2948
2949 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2950 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2951
2952 /* Ensure minimum (required) set of control bits are supported. */
2953 if (ctl_min & ~ctl)
002c7f7c 2954 return -EIO;
1c3d14fe
YS		 2955
2956 *result = ctl;
2957 return 0;
2958}
2959
110312c8
AK		 2960static __init bool allow_1_setting(u32 msr, u32 ctl)
2961{
2962 u32 vmx_msr_low, vmx_msr_high;
2963
2964 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2965 return vmx_msr_high & ctl;
2966}
2967
002c7f7c 2968static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2969{
2970 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2971 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2972 u32 _pin_based_exec_control = 0;
2973 u32 _cpu_based_exec_control = 0;
f78e0e2e 2974 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2975 u32 _vmexit_control = 0;
2976 u32 _vmentry_control = 0;
2977
10166744 2978 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2979#ifdef CONFIG_X86_64
2980 CPU_BASED_CR8_LOAD_EXITING |
2981 CPU_BASED_CR8_STORE_EXITING |
2982#endif
d56f546d
SY		 2983 CPU_BASED_CR3_LOAD_EXITING |
2984 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2985 CPU_BASED_USE_IO_BITMAPS |
2986 CPU_BASED_MOV_DR_EXITING |
a7052897 2987 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2988 CPU_BASED_MWAIT_EXITING |
2989 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2990 CPU_BASED_INVLPG_EXITING |
2991 CPU_BASED_RDPMC_EXITING;
443381a8 2992
f78e0e2e 2993 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2994 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2995 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2996 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2997 &_cpu_based_exec_control) < 0)
002c7f7c 2998 return -EIO;
6e5d865c
YS		 2999#ifdef CONFIG_X86_64
3000 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3001 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3002 ~CPU_BASED_CR8_STORE_EXITING;
3003#endif
f78e0e2e 3004 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3005 min2 = 0;
3006 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3007 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3008 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3009 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3010 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3011 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3012 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3013 SECONDARY_EXEC_RDTSCP |
83d4c286 3014 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3015 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3016 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3017 SECONDARY_EXEC_SHADOW_VMCS |
843e4330
KH		 3018 SECONDARY_EXEC_XSAVES |
3019 SECONDARY_EXEC_ENABLE_PML;
d56f546d
SY		 3020 if (adjust_vmx_controls(min2, opt2,
3021 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3022 &_cpu_based_2nd_exec_control) < 0)
3023 return -EIO;
3024 }
3025#ifndef CONFIG_X86_64
3026 if (!(_cpu_based_2nd_exec_control &
3027 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3028 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3029#endif
83d4c286
YZ		 3030
3031 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3032 _cpu_based_2nd_exec_control &= ~(
8d14695f 3033 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3034 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3035 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3036
d56f546d 3037 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3038 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3039 enabled */
5fff7d27
GN		 3040 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3041 CPU_BASED_CR3_STORE_EXITING |
3042 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3043 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3044 vmx_capability.ept, vmx_capability.vpid);
3045 }
1c3d14fe 3046
81908bf4 3047 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3048#ifdef CONFIG_X86_64
3049 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3050#endif
a547c6db 3051 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3052 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3053 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3054 &_vmexit_control) < 0)
002c7f7c 3055 return -EIO;
1c3d14fe 3056
01e439be
YZ		 3057 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3058 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3059 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3060 &_pin_based_exec_control) < 0)
3061 return -EIO;
3062
3063 if (!(_cpu_based_2nd_exec_control &
3064 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3065 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3066 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3067
c845f9c6 3068 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3069 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3070 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3071 &_vmentry_control) < 0)
002c7f7c 3072 return -EIO;
6aa8b732 3073
c68876fd 3074 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3075
3076 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3077 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3078 return -EIO;
1c3d14fe
YS		 3079
3080#ifdef CONFIG_X86_64
3081 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3082 if (vmx_msr_high & (1u<<16))
002c7f7c 3083 return -EIO;
1c3d14fe
YS		 3084#endif
3085
3086 /* Require Write-Back (WB) memory type for VMCS accesses. */
3087 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3088 return -EIO;
1c3d14fe 3089
002c7f7c
YS		 3090 vmcs_conf->size = vmx_msr_high & 0x1fff;
3091 vmcs_conf->order = get_order(vmcs_config.size);
3092 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3093
002c7f7c
YS		 3094 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3095 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3096 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3097 vmcs_conf->vmexit_ctrl = _vmexit_control;
3098 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3099
110312c8
AK		 3100 cpu_has_load_ia32_efer =
3101 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3102 VM_ENTRY_LOAD_IA32_EFER)
3103 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3104 VM_EXIT_LOAD_IA32_EFER);
3105
8bf00a52
GN		 3106 cpu_has_load_perf_global_ctrl =
3107 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3108 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3109 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3110 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3111
3112 /*
3113 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3114 * but due to arrata below it can't be used. Workaround is to use
3115 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3116 *
3117 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3118 *
3119 * AAK155 (model 26)
3120 * AAP115 (model 30)
3121 * AAT100 (model 37)
3122 * BC86,AAY89,BD102 (model 44)
3123 * BA97 (model 46)
3124 *
3125 */
3126 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3127 switch (boot_cpu_data.x86_model) {
3128 case 26:
3129 case 30:
3130 case 37:
3131 case 44:
3132 case 46:
3133 cpu_has_load_perf_global_ctrl = false;
3134 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3135 "does not work properly. Using workaround\n");
3136 break;
3137 default:
3138 break;
3139 }
3140 }
3141
20300099
WL		 3142 if (cpu_has_xsaves)
3143 rdmsrl(MSR_IA32_XSS, host_xss);
3144
1c3d14fe 3145 return 0;
c68876fd 3146}
6aa8b732
AK		 3147
3148static struct vmcs *alloc_vmcs_cpu(int cpu)
3149{
3150 int node = cpu_to_node(cpu);
3151 struct page *pages;
3152 struct vmcs *vmcs;
3153
96db800f 3154 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3155 if (!pages)
3156 return NULL;
3157 vmcs = page_address(pages);
1c3d14fe
YS		 3158 memset(vmcs, 0, vmcs_config.size);
3159 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3160 return vmcs;
3161}
3162
3163static struct vmcs *alloc_vmcs(void)
3164{
d3b2c338 3165 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3166}
3167
3168static void free_vmcs(struct vmcs *vmcs)
3169{
1c3d14fe 3170 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3171}
3172
d462b819
NHE		 3173/*
3174 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3175 */
3176static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3177{
3178 if (!loaded_vmcs->vmcs)
3179 return;
3180 loaded_vmcs_clear(loaded_vmcs);
3181 free_vmcs(loaded_vmcs->vmcs);
3182 loaded_vmcs->vmcs = NULL;
3183}
3184
39959588 3185static void free_kvm_area(void)
6aa8b732
AK		 3186{
3187 int cpu;
3188
3230bb47 3189 for_each_possible_cpu(cpu) {
6aa8b732 3190 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3191 per_cpu(vmxarea, cpu) = NULL;
3192 }
6aa8b732
AK		 3193}
3194
fe2b201b
BD		 3195static void init_vmcs_shadow_fields(void)
3196{
3197 int i, j;
3198
3199 /* No checks for read only fields yet */
3200
3201 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3202 switch (shadow_read_write_fields[i]) {
3203 case GUEST_BNDCFGS:
3204 if (!vmx_mpx_supported())
3205 continue;
3206 break;
3207 default:
3208 break;
3209 }
3210
3211 if (j < i)
3212 shadow_read_write_fields[j] =
3213 shadow_read_write_fields[i];
3214 j++;
3215 }
3216 max_shadow_read_write_fields = j;
3217
3218 /* shadowed fields guest access without vmexit */
3219 for (i = 0; i < max_shadow_read_write_fields; i++) {
3220 clear_bit(shadow_read_write_fields[i],
3221 vmx_vmwrite_bitmap);
3222 clear_bit(shadow_read_write_fields[i],
3223 vmx_vmread_bitmap);
3224 }
3225 for (i = 0; i < max_shadow_read_only_fields; i++)
3226 clear_bit(shadow_read_only_fields[i],
3227 vmx_vmread_bitmap);
3228}
3229
6aa8b732
AK		 3230static __init int alloc_kvm_area(void)
3231{
3232 int cpu;
3233
3230bb47 3234 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3235 struct vmcs *vmcs;
3236
3237 vmcs = alloc_vmcs_cpu(cpu);
3238 if (!vmcs) {
3239 free_kvm_area();
3240 return -ENOMEM;
3241 }
3242
3243 per_cpu(vmxarea, cpu) = vmcs;
3244 }
3245 return 0;
3246}
3247
14168786
GN		 3248static bool emulation_required(struct kvm_vcpu *vcpu)
3249{
3250 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3251}
3252
91b0aa2c 3253static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3254 struct kvm_segment *save)
6aa8b732 3255{
d99e4152
GN		 3256 if (!emulate_invalid_guest_state) {
3257 /*
3258 * CS and SS RPL should be equal during guest entry according
3259 * to VMX spec, but in reality it is not always so. Since vcpu
3260 * is in the middle of the transition from real mode to
3261 * protected mode it is safe to assume that RPL 0 is a good
3262 * default value.
3263 */
3264 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 3265 save->selector &= ~SEGMENT_RPL_MASK;
3266 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3267 save->s = 1;
6aa8b732 3268 }
d99e4152 3269 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3270}
3271
3272static void enter_pmode(struct kvm_vcpu *vcpu)
3273{
3274 unsigned long flags;
a89a8fb9 3275 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3276
d99e4152
GN		 3277 /*
3278 * Update real mode segment cache. It may be not up-to-date if sement
3279 * register was written while vcpu was in a guest mode.
3280 */
3281 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3282 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3283 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3284 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3285 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3286 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3287
7ffd92c5 3288 vmx->rmode.vm86_active = 0;
6aa8b732 3289
2fb92db1
AK		 3290 vmx_segment_cache_clear(vmx);
3291
f5f7b2fe 3292 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3293
3294 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3295 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3296 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3297 vmcs_writel(GUEST_RFLAGS, flags);
3298
66aee91a
RR		 3299 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3300 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3301
3302 update_exception_bitmap(vcpu);
3303
91b0aa2c
GN		 3304 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3305 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3306 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3307 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3308 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3309 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3310}
3311
f5f7b2fe 3312static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3313{
772e0318 3314 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3315 struct kvm_segment var = *save;
3316
3317 var.dpl = 0x3;
3318 if (seg == VCPU_SREG_CS)
3319 var.type = 0x3;
3320
3321 if (!emulate_invalid_guest_state) {
3322 var.selector = var.base >> 4;
3323 var.base = var.base & 0xffff0;
3324 var.limit = 0xffff;
3325 var.g = 0;
3326 var.db = 0;
3327 var.present = 1;
3328 var.s = 1;
3329 var.l = 0;
3330 var.unusable = 0;
3331 var.type = 0x3;
3332 var.avl = 0;
3333 if (save->base & 0xf)
3334 printk_once(KERN_WARNING "kvm: segment base is not "
3335 "paragraph aligned when entering "
3336 "protected mode (seg=%d)", seg);
3337 }
6aa8b732 3338
d99e4152
GN		 3339 vmcs_write16(sf->selector, var.selector);
3340 vmcs_write32(sf->base, var.base);
3341 vmcs_write32(sf->limit, var.limit);
3342 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3343}
3344
3345static void enter_rmode(struct kvm_vcpu *vcpu)
3346{
3347 unsigned long flags;
a89a8fb9 3348 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3349
f5f7b2fe
AK		 3350 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3351 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3352 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3353 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3354 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3355 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3356 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3357
7ffd92c5 3358 vmx->rmode.vm86_active = 1;
6aa8b732 3359
776e58ea
GN		 3360 /*
3361 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3362 * vcpu. Warn the user that an update is overdue.
776e58ea 3363 */
4918c6ca 3364 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3365 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3366 "called before entering vcpu\n");
776e58ea 3367
2fb92db1
AK		 3368 vmx_segment_cache_clear(vmx);
3369
4918c6ca 3370 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3371 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3372 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3373
3374 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3375 vmx->rmode.save_rflags = flags;
6aa8b732 3376
053de044 3377 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3378
3379 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3380 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3381 update_exception_bitmap(vcpu);
3382
d99e4152
GN		 3383 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3384 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3385 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3386 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3387 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3388 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3389
8668a3c4 3390 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3391}
3392
401d10de
AS		 3393static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3394{
3395 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3396 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3397
3398 if (!msr)
3399 return;
401d10de 3400
44ea2b17
AK		 3401 /*
3402 * Force kernel_gs_base reloading before EFER changes, as control
3403 * of this msr depends on is_long_mode().
3404 */
3405 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3406 vcpu->arch.efer = efer;
401d10de 3407 if (efer & EFER_LMA) {
2961e876 3408 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3409 msr->data = efer;
3410 } else {
2961e876 3411 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3412
3413 msr->data = efer & ~EFER_LME;
3414 }
3415 setup_msrs(vmx);
3416}
3417
05b3e0c2 3418#ifdef CONFIG_X86_64
6aa8b732
AK		 3419
3420static void enter_lmode(struct kvm_vcpu *vcpu)
3421{
3422 u32 guest_tr_ar;
3423
2fb92db1
AK		 3424 vmx_segment_cache_clear(to_vmx(vcpu));
3425
6aa8b732 3426 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 3427 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3428 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3429 __func__);
6aa8b732 3430 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 3431 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3432 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 3433 }
da38f438 3434 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3435}
3436
3437static void exit_lmode(struct kvm_vcpu *vcpu)
3438{
2961e876 3439 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3440 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3441}
3442
3443#endif
3444
2384d2b3
SY		 3445static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3446{
b9d762fa 3447 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3448 if (enable_ept) {
3449 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3450 return;
4e1096d2 3451 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3452 }
2384d2b3
SY		 3453}
3454
e8467fda
AK		 3455static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3456{
3457 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3458
3459 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3460 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3461}
3462
aff48baa
AK		 3463static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3464{
3465 if (enable_ept && is_paging(vcpu))
3466 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3467 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3468}
3469
25c4c276 3470static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3471{
fc78f519
AK		 3472 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3473
3474 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3475 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3476}
3477
1439442c
SY		 3478static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3479{
d0d538b9
GN		 3480 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3481
6de4f3ad
AK		 3482 if (!test_bit(VCPU_EXREG_PDPTR,
3483 (unsigned long *)&vcpu->arch.regs_dirty))
3484 return;
3485
1439442c 3486 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3487 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3488 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3489 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3490 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3491 }
3492}
3493
8f5d549f
AK		 3494static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3495{
d0d538b9
GN		 3496 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3497
8f5d549f 3498 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3499 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3500 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3501 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3502 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3503 }
6de4f3ad
AK		 3504
3505 __set_bit(VCPU_EXREG_PDPTR,
3506 (unsigned long *)&vcpu->arch.regs_avail);
3507 __set_bit(VCPU_EXREG_PDPTR,
3508 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3509}
3510
5e1746d6 3511static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3512
3513static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3514 unsigned long cr0,
3515 struct kvm_vcpu *vcpu)
3516{
5233dd51
MT		 3517 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3518 vmx_decache_cr3(vcpu);
1439442c
SY		 3519 if (!(cr0 & X86_CR0_PG)) {
3520 /* From paging/starting to nonpaging */
3521 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3522 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3523 (CPU_BASED_CR3_LOAD_EXITING |
3524 CPU_BASED_CR3_STORE_EXITING));
3525 vcpu->arch.cr0 = cr0;
fc78f519 3526 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3527 } else if (!is_paging(vcpu)) {
3528 /* From nonpaging to paging */
3529 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3530 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3531 ~(CPU_BASED_CR3_LOAD_EXITING |
3532 CPU_BASED_CR3_STORE_EXITING));
3533 vcpu->arch.cr0 = cr0;
fc78f519 3534 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3535 }
95eb84a7
SY		 3536
3537 if (!(cr0 & X86_CR0_WP))
3538 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3539}
3540
6aa8b732
AK		 3541static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3542{
7ffd92c5 3543 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3544 unsigned long hw_cr0;
3545
5037878e 3546 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3547 if (enable_unrestricted_guest)
5037878e 3548 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3549 else {
5037878e 3550 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3551
218e763f
GN		 3552 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3553 enter_pmode(vcpu);
6aa8b732 3554
218e763f
GN		 3555 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3556 enter_rmode(vcpu);
3557 }
6aa8b732 3558
05b3e0c2 3559#ifdef CONFIG_X86_64
f6801dff 3560 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3561 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3562 enter_lmode(vcpu);
707d92fa 3563 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3564 exit_lmode(vcpu);
3565 }
3566#endif
3567
089d034e 3568 if (enable_ept)
1439442c
SY		 3569 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3570
02daab21 3571 if (!vcpu->fpu_active)
81231c69 3572 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3573
6aa8b732 3574 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3575 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3576 vcpu->arch.cr0 = cr0;
14168786
GN		 3577
3578 /* depends on vcpu->arch.cr0 to be set to a new value */
3579 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3580}
3581
1439442c
SY		 3582static u64 construct_eptp(unsigned long root_hpa)
3583{
3584 u64 eptp;
3585
3586 /* TODO write the value reading from MSR */
3587 eptp = VMX_EPT_DEFAULT_MT |
3588 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3589 if (enable_ept_ad_bits)
3590 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3591 eptp |= (root_hpa & PAGE_MASK);
3592
3593 return eptp;
3594}
3595
6aa8b732
AK		 3596static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3597{
1439442c
SY		 3598 unsigned long guest_cr3;
3599 u64 eptp;
3600
3601 guest_cr3 = cr3;
089d034e 3602 if (enable_ept) {
1439442c
SY		 3603 eptp = construct_eptp(cr3);
3604 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3605 if (is_paging(vcpu) || is_guest_mode(vcpu))
3606 guest_cr3 = kvm_read_cr3(vcpu);
3607 else
3608 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3609 ept_load_pdptrs(vcpu);
1439442c
SY		 3610 }
3611
2384d2b3 3612 vmx_flush_tlb(vcpu);
1439442c 3613 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3614}
3615
5e1746d6 3616static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3617{
085e68ee
BS		 3618 /*
3619 * Pass through host's Machine Check Enable value to hw_cr4, which
3620 * is in force while we are in guest mode. Do not let guests control
3621 * this bit, even if host CR4.MCE == 0.
3622 */
3623 unsigned long hw_cr4 =
3624 (cr4_read_shadow() & X86_CR4_MCE) |
3625 (cr4 & ~X86_CR4_MCE) |
3626 (to_vmx(vcpu)->rmode.vm86_active ?
3627 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 3628
5e1746d6
NHE		 3629 if (cr4 & X86_CR4_VMXE) {
3630 /*
3631 * To use VMXON (and later other VMX instructions), a guest
3632 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3633 * So basically the check on whether to allow nested VMX
3634 * is here.
3635 */
3636 if (!nested_vmx_allowed(vcpu))
3637 return 1;
1a0d74e6
JK		 3638 }
3639 if (to_vmx(vcpu)->nested.vmxon &&
3640 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3641 return 1;
3642
ad312c7c 3643 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3644 if (enable_ept) {
3645 if (!is_paging(vcpu)) {
3646 hw_cr4 &= ~X86_CR4_PAE;
3647 hw_cr4 |= X86_CR4_PSE;
c08800a5 3648 /*
e1e746b3
FW		 3649 * SMEP/SMAP is disabled if CPU is in non-paging mode
3650 * in hardware. However KVM always uses paging mode to
c08800a5 3651 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3652 * To emulate this behavior, SMEP/SMAP needs to be
3653 * manually disabled when guest switches to non-paging
3654 * mode.
c08800a5 3655 */
e1e746b3 3656 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3657 } else if (!(cr4 & X86_CR4_PAE)) {
3658 hw_cr4 &= ~X86_CR4_PAE;
3659 }
3660 }
1439442c
SY		 3661
3662 vmcs_writel(CR4_READ_SHADOW, cr4);
3663 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3664 return 0;
6aa8b732
AK		 3665}
3666
6aa8b732
AK		 3667static void vmx_get_segment(struct kvm_vcpu *vcpu,
3668 struct kvm_segment *var, int seg)
3669{
a9179499 3670 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3671 u32 ar;
3672
c6ad1153 3673 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3674 *var = vmx->rmode.segs[seg];
a9179499 3675 if (seg == VCPU_SREG_TR
2fb92db1 3676 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3677 return;
1390a28b
AK		 3678 var->base = vmx_read_guest_seg_base(vmx, seg);
3679 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3680 return;
a9179499 3681 }
2fb92db1
AK		 3682 var->base = vmx_read_guest_seg_base(vmx, seg);
3683 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3684 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3685 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3686 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3687 var->type = ar & 15;
3688 var->s = (ar >> 4) & 1;
3689 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3690 /*
3691 * Some userspaces do not preserve unusable property. Since usable
3692 * segment has to be present according to VMX spec we can use present
3693 * property to amend userspace bug by making unusable segment always
3694 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3695 * segment as unusable.
3696 */
3697 var->present = !var->unusable;
6aa8b732
AK		 3698 var->avl = (ar >> 12) & 1;
3699 var->l = (ar >> 13) & 1;
3700 var->db = (ar >> 14) & 1;
3701 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3702}
3703
a9179499
AK		 3704static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3705{
a9179499
AK		 3706 struct kvm_segment s;
3707
3708 if (to_vmx(vcpu)->rmode.vm86_active) {
3709 vmx_get_segment(vcpu, &s, seg);
3710 return s.base;
3711 }
2fb92db1 3712 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3713}
3714
b09408d0 3715static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3716{
b09408d0
MT		 3717 struct vcpu_vmx *vmx = to_vmx(vcpu);
3718
ae9fedc7 3719 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3720 return 0;
ae9fedc7
PB		 3721 else {
3722 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3723 return VMX_AR_DPL(ar);
69c73028 3724 }
69c73028
AK		 3725}
3726
653e3108 3727static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3728{
6aa8b732
AK		 3729 u32 ar;
3730
f0495f9b 3731 if (var->unusable || !var->present)
6aa8b732
AK		 3732 ar = 1 << 16;
3733 else {
3734 ar = var->type & 15;
3735 ar |= (var->s & 1) << 4;
3736 ar |= (var->dpl & 3) << 5;
3737 ar |= (var->present & 1) << 7;
3738 ar |= (var->avl & 1) << 12;
3739 ar |= (var->l & 1) << 13;
3740 ar |= (var->db & 1) << 14;
3741 ar |= (var->g & 1) << 15;
3742 }
653e3108
AK		 3743
3744 return ar;
3745}
3746
3747static void vmx_set_segment(struct kvm_vcpu *vcpu,
3748 struct kvm_segment *var, int seg)
3749{
7ffd92c5 3750 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3751 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3752
2fb92db1
AK		 3753 vmx_segment_cache_clear(vmx);
3754
1ecd50a9
GN		 3755 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3756 vmx->rmode.segs[seg] = *var;
3757 if (seg == VCPU_SREG_TR)
3758 vmcs_write16(sf->selector, var->selector);
3759 else if (var->s)
3760 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3761 goto out;
653e3108 3762 }
1ecd50a9 3763
653e3108
AK		 3764 vmcs_writel(sf->base, var->base);
3765 vmcs_write32(sf->limit, var->limit);
3766 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3767
3768 /*
3769 * Fix the "Accessed" bit in AR field of segment registers for older
3770 * qemu binaries.
3771 * IA32 arch specifies that at the time of processor reset the
3772 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3773 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3774 * state vmexit when "unrestricted guest" mode is turned on.
3775 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3776 * tree. Newer qemu binaries with that qemu fix would not need this
3777 * kvm hack.
3778 */
3779 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3780 var->type |= 0x1; /* Accessed */
3a624e29 3781
f924d66d 3782 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3783
3784out:
98eb2f8b 3785 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3786}
3787
6aa8b732
AK		 3788static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3789{
2fb92db1 3790 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3791
3792 *db = (ar >> 14) & 1;
3793 *l = (ar >> 13) & 1;
3794}
3795
89a27f4d 3796static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3797{
89a27f4d
GN		 3798 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3799 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3800}
3801
89a27f4d 3802static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3803{
89a27f4d
GN		 3804 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3805 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3806}
3807
89a27f4d 3808static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3809{
89a27f4d
GN		 3810 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3811 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3812}
3813
89a27f4d 3814static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3815{
89a27f4d
GN		 3816 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3817 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3818}
3819
648dfaa7
MG		 3820static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3821{
3822 struct kvm_segment var;
3823 u32 ar;
3824
3825 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3826 var.dpl = 0x3;
0647f4aa
GN		 3827 if (seg == VCPU_SREG_CS)
3828 var.type = 0x3;
648dfaa7
MG		 3829 ar = vmx_segment_access_rights(&var);
3830
3831 if (var.base != (var.selector << 4))
3832 return false;
89efbed0 3833 if (var.limit != 0xffff)
648dfaa7 3834 return false;
07f42f5f 3835 if (ar != 0xf3)
648dfaa7
MG		 3836 return false;
3837
3838 return true;
3839}
3840
3841static bool code_segment_valid(struct kvm_vcpu *vcpu)
3842{
3843 struct kvm_segment cs;
3844 unsigned int cs_rpl;
3845
3846 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3847 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3848
1872a3f4
AK		 3849 if (cs.unusable)
3850 return false;
4d283ec9 3851 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3852 return false;
3853 if (!cs.s)
3854 return false;
4d283ec9 3855 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3856 if (cs.dpl > cs_rpl)
3857 return false;
1872a3f4 3858 } else {
648dfaa7
MG		 3859 if (cs.dpl != cs_rpl)
3860 return false;
3861 }
3862 if (!cs.present)
3863 return false;
3864
3865 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3866 return true;
3867}
3868
3869static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3870{
3871 struct kvm_segment ss;
3872 unsigned int ss_rpl;
3873
3874 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3875 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3876
1872a3f4
AK		 3877 if (ss.unusable)
3878 return true;
3879 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3880 return false;
3881 if (!ss.s)
3882 return false;
3883 if (ss.dpl != ss_rpl) /* DPL != RPL */
3884 return false;
3885 if (!ss.present)
3886 return false;
3887
3888 return true;
3889}
3890
3891static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3892{
3893 struct kvm_segment var;
3894 unsigned int rpl;
3895
3896 vmx_get_segment(vcpu, &var, seg);
b32a9918 3897 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3898
1872a3f4
AK		 3899 if (var.unusable)
3900 return true;
648dfaa7
MG		 3901 if (!var.s)
3902 return false;
3903 if (!var.present)
3904 return false;
4d283ec9 3905 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3906 if (var.dpl < rpl) /* DPL < RPL */
3907 return false;
3908 }
3909
3910 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3911 * rights flags
3912 */
3913 return true;
3914}
3915
3916static bool tr_valid(struct kvm_vcpu *vcpu)
3917{
3918 struct kvm_segment tr;
3919
3920 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3921
1872a3f4
AK		 3922 if (tr.unusable)
3923 return false;
b32a9918 3924 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3925 return false;
1872a3f4 3926 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3927 return false;
3928 if (!tr.present)
3929 return false;
3930
3931 return true;
3932}
3933
3934static bool ldtr_valid(struct kvm_vcpu *vcpu)
3935{
3936 struct kvm_segment ldtr;
3937
3938 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3939
1872a3f4
AK		 3940 if (ldtr.unusable)
3941 return true;
b32a9918 3942 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3943 return false;
3944 if (ldtr.type != 2)
3945 return false;
3946 if (!ldtr.present)
3947 return false;
3948
3949 return true;
3950}
3951
3952static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3953{
3954 struct kvm_segment cs, ss;
3955
3956 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3957 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3958
b32a9918
NA		 3959 return ((cs.selector & SEGMENT_RPL_MASK) ==
3960 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3961}
3962
3963/*
3964 * Check if guest state is valid. Returns true if valid, false if
3965 * not.
3966 * We assume that registers are always usable
3967 */
3968static bool guest_state_valid(struct kvm_vcpu *vcpu)
3969{
c5e97c80
GN		 3970 if (enable_unrestricted_guest)
3971 return true;
3972
648dfaa7 3973 /* real mode guest state checks */
f13882d8 3974 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3975 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3976 return false;
3977 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3978 return false;
3979 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3980 return false;
3981 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3982 return false;
3983 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3984 return false;
3985 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3986 return false;
3987 } else {
3988 /* protected mode guest state checks */
3989 if (!cs_ss_rpl_check(vcpu))
3990 return false;
3991 if (!code_segment_valid(vcpu))
3992 return false;
3993 if (!stack_segment_valid(vcpu))
3994 return false;
3995 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3996 return false;
3997 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3998 return false;
3999 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4000 return false;
4001 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4002 return false;
4003 if (!tr_valid(vcpu))
4004 return false;
4005 if (!ldtr_valid(vcpu))
4006 return false;
4007 }
4008 /* TODO:
4009 * - Add checks on RIP
4010 * - Add checks on RFLAGS
4011 */
4012
4013 return true;
4014}
4015
d77c26fc 4016static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4017{
40dcaa9f 4018 gfn_t fn;
195aefde 4019 u16 data = 0;
1f755a82 4020 int idx, r;
6aa8b732 4021
40dcaa9f 4022 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4023 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4024 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4025 if (r < 0)
10589a46 4026 goto out;
195aefde 4027 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4028 r = kvm_write_guest_page(kvm, fn++, &data,
4029 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4030 if (r < 0)
10589a46 4031 goto out;
195aefde
IE		 4032 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4033 if (r < 0)
10589a46 4034 goto out;
195aefde
IE		 4035 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4036 if (r < 0)
10589a46 4037 goto out;
195aefde 4038 data = ~0;
10589a46
MT		 4039 r = kvm_write_guest_page(kvm, fn, &data,
4040 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4041 sizeof(u8));
10589a46 4042out:
40dcaa9f 4043 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4044 return r;
6aa8b732
AK		 4045}
4046
b7ebfb05
SY		 4047static int init_rmode_identity_map(struct kvm *kvm)
4048{
f51770ed 4049 int i, idx, r = 0;
b7ebfb05
SY		 4050 pfn_t identity_map_pfn;
4051 u32 tmp;
4052
089d034e 4053 if (!enable_ept)
f51770ed 4054 return 0;
a255d479
TC		 4055
4056 /* Protect kvm->arch.ept_identity_pagetable_done. */
4057 mutex_lock(&kvm->slots_lock);
4058
f51770ed 4059 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4060 goto out2;
a255d479 4061
b927a3ce 4062 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4063
4064 r = alloc_identity_pagetable(kvm);
f51770ed 4065 if (r < 0)
a255d479
TC		 4066 goto out2;
4067
40dcaa9f 4068 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4069 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4070 if (r < 0)
4071 goto out;
4072 /* Set up identity-mapping pagetable for EPT in real mode */
4073 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4074 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4075 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4076 r = kvm_write_guest_page(kvm, identity_map_pfn,
4077 &tmp, i * sizeof(tmp), sizeof(tmp));
4078 if (r < 0)
4079 goto out;
4080 }
4081 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4082
b7ebfb05 4083out:
40dcaa9f 4084 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4085
4086out2:
4087 mutex_unlock(&kvm->slots_lock);
f51770ed 4088 return r;
b7ebfb05
SY		 4089}
4090
6aa8b732
AK		 4091static void seg_setup(int seg)
4092{
772e0318 4093 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4094 unsigned int ar;
6aa8b732
AK		 4095
4096 vmcs_write16(sf->selector, 0);
4097 vmcs_writel(sf->base, 0);
4098 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4099 ar = 0x93;
4100 if (seg == VCPU_SREG_CS)
4101 ar |= 0x08; /* code segment */
3a624e29
NK		 4102
4103 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4104}
4105
f78e0e2e
SY		 4106static int alloc_apic_access_page(struct kvm *kvm)
4107{
4484141a 4108 struct page *page;
f78e0e2e
SY		 4109 struct kvm_userspace_memory_region kvm_userspace_mem;
4110 int r = 0;
4111
79fac95e 4112 mutex_lock(&kvm->slots_lock);
c24ae0dc 4113 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4114 goto out;
4115 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4116 kvm_userspace_mem.flags = 0;
73a6d941 4117 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4118 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4119 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4120 if (r)
4121 goto out;
72dc67a6 4122
73a6d941 4123 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4124 if (is_error_page(page)) {
4125 r = -EFAULT;
4126 goto out;
4127 }
4128
c24ae0dc
TC		 4129 /*
4130 * Do not pin the page in memory, so that memory hot-unplug
4131 * is able to migrate it.
4132 */
4133 put_page(page);
4134 kvm->arch.apic_access_page_done = true;
f78e0e2e 4135out:
79fac95e 4136 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4137 return r;
4138}
4139
b7ebfb05
SY		 4140static int alloc_identity_pagetable(struct kvm *kvm)
4141{
a255d479
TC		 4142 /* Called with kvm->slots_lock held. */
4143
b7ebfb05
SY		 4144 struct kvm_userspace_memory_region kvm_userspace_mem;
4145 int r = 0;
4146
a255d479
TC		 4147 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4148
b7ebfb05
SY		 4149 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4150 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4151 kvm_userspace_mem.guest_phys_addr =
4152 kvm->arch.ept_identity_map_addr;
b7ebfb05 4153 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4154 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4155
b7ebfb05
SY		 4156 return r;
4157}
4158
2384d2b3
SY		 4159static void allocate_vpid(struct vcpu_vmx *vmx)
4160{
4161 int vpid;
4162
4163 vmx->vpid = 0;
919818ab 4164 if (!enable_vpid)
2384d2b3
SY		 4165 return;
4166 spin_lock(&vmx_vpid_lock);
4167 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4168 if (vpid < VMX_NR_VPIDS) {
4169 vmx->vpid = vpid;
4170 __set_bit(vpid, vmx_vpid_bitmap);
4171 }
4172 spin_unlock(&vmx_vpid_lock);
4173}
4174
cdbecfc3
LJ		 4175static void free_vpid(struct vcpu_vmx *vmx)
4176{
4177 if (!enable_vpid)
4178 return;
4179 spin_lock(&vmx_vpid_lock);
4180 if (vmx->vpid != 0)
4181 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4182 spin_unlock(&vmx_vpid_lock);
4183}
4184
8d14695f
YZ		 4185#define MSR_TYPE_R 1
4186#define MSR_TYPE_W 2
4187static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4188 u32 msr, int type)
25c5f225 4189{
3e7c73e9 4190 int f = sizeof(unsigned long);
25c5f225
SY		 4191
4192 if (!cpu_has_vmx_msr_bitmap())
4193 return;
4194
4195 /*
4196 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4197 * have the write-low and read-high bitmap offsets the wrong way round.
4198 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4199 */
25c5f225 4200 if (msr <= 0x1fff) {
8d14695f
YZ		 4201 if (type & MSR_TYPE_R)
4202 /* read-low */
4203 __clear_bit(msr, msr_bitmap + 0x000 / f);
4204
4205 if (type & MSR_TYPE_W)
4206 /* write-low */
4207 __clear_bit(msr, msr_bitmap + 0x800 / f);
4208
25c5f225
SY		 4209 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4210 msr &= 0x1fff;
8d14695f
YZ		 4211 if (type & MSR_TYPE_R)
4212 /* read-high */
4213 __clear_bit(msr, msr_bitmap + 0x400 / f);
4214
4215 if (type & MSR_TYPE_W)
4216 /* write-high */
4217 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4218
4219 }
4220}
4221
4222static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4223 u32 msr, int type)
4224{
4225 int f = sizeof(unsigned long);
4226
4227 if (!cpu_has_vmx_msr_bitmap())
4228 return;
4229
4230 /*
4231 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4232 * have the write-low and read-high bitmap offsets the wrong way round.
4233 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4234 */
4235 if (msr <= 0x1fff) {
4236 if (type & MSR_TYPE_R)
4237 /* read-low */
4238 __set_bit(msr, msr_bitmap + 0x000 / f);
4239
4240 if (type & MSR_TYPE_W)
4241 /* write-low */
4242 __set_bit(msr, msr_bitmap + 0x800 / f);
4243
4244 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4245 msr &= 0x1fff;
4246 if (type & MSR_TYPE_R)
4247 /* read-high */
4248 __set_bit(msr, msr_bitmap + 0x400 / f);
4249
4250 if (type & MSR_TYPE_W)
4251 /* write-high */
4252 __set_bit(msr, msr_bitmap + 0xc00 / f);
4253
25c5f225 4254 }
25c5f225
SY		 4255}
4256
f2b93280
WV		 4257/*
4258 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4259 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4260 */
4261static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4262 unsigned long *msr_bitmap_nested,
4263 u32 msr, int type)
4264{
4265 int f = sizeof(unsigned long);
4266
4267 if (!cpu_has_vmx_msr_bitmap()) {
4268 WARN_ON(1);
4269 return;
4270 }
4271
4272 /*
4273 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4274 * have the write-low and read-high bitmap offsets the wrong way round.
4275 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4276 */
4277 if (msr <= 0x1fff) {
4278 if (type & MSR_TYPE_R &&
4279 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4280 /* read-low */
4281 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4282
4283 if (type & MSR_TYPE_W &&
4284 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4285 /* write-low */
4286 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4287
4288 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4289 msr &= 0x1fff;
4290 if (type & MSR_TYPE_R &&
4291 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4292 /* read-high */
4293 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4294
4295 if (type & MSR_TYPE_W &&
4296 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4297 /* write-high */
4298 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4299
4300 }
4301}
4302
5897297b
AK		 4303static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4304{
4305 if (!longmode_only)
8d14695f
YZ		 4306 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4307 msr, MSR_TYPE_R | MSR_TYPE_W);
4308 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4309 msr, MSR_TYPE_R | MSR_TYPE_W);
4310}
4311
4312static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4313{
4314 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4315 msr, MSR_TYPE_R);
4316 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4317 msr, MSR_TYPE_R);
4318}
4319
4320static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4321{
4322 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4323 msr, MSR_TYPE_R);
4324 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4325 msr, MSR_TYPE_R);
4326}
4327
4328static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4329{
4330 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4331 msr, MSR_TYPE_W);
4332 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4333 msr, MSR_TYPE_W);
5897297b
AK		 4334}
4335
d50ab6c1
PB		 4336static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4337{
35754c98 4338 return enable_apicv && lapic_in_kernel(vcpu);
d50ab6c1
PB		 4339}
4340
705699a1
WV		 4341static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4342{
4343 struct vcpu_vmx *vmx = to_vmx(vcpu);
4344 int max_irr;
4345 void *vapic_page;
4346 u16 status;
4347
4348 if (vmx->nested.pi_desc &&
4349 vmx->nested.pi_pending) {
4350 vmx->nested.pi_pending = false;
4351 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4352 return 0;
4353
4354 max_irr = find_last_bit(
4355 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4356
4357 if (max_irr == 256)
4358 return 0;
4359
4360 vapic_page = kmap(vmx->nested.virtual_apic_page);
4361 if (!vapic_page) {
4362 WARN_ON(1);
4363 return -ENOMEM;
4364 }
4365 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4366 kunmap(vmx->nested.virtual_apic_page);
4367
4368 status = vmcs_read16(GUEST_INTR_STATUS);
4369 if ((u8)max_irr > ((u8)status & 0xff)) {
4370 status &= ~0xff;
4371 status |= (u8)max_irr;
4372 vmcs_write16(GUEST_INTR_STATUS, status);
4373 }
4374 }
4375 return 0;
4376}
4377
21bc8dc5
RK		 4378static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4379{
4380#ifdef CONFIG_SMP
4381 if (vcpu->mode == IN_GUEST_MODE) {
4382 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4383 POSTED_INTR_VECTOR);
4384 return true;
4385 }
4386#endif
4387 return false;
4388}
4389
705699a1
WV		 4390static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4391 int vector)
4392{
4393 struct vcpu_vmx *vmx = to_vmx(vcpu);
4394
4395 if (is_guest_mode(vcpu) &&
4396 vector == vmx->nested.posted_intr_nv) {
4397 /* the PIR and ON have been set by L1. */
21bc8dc5 4398 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4399 /*
4400 * If a posted intr is not recognized by hardware,
4401 * we will accomplish it in the next vmentry.
4402 */
4403 vmx->nested.pi_pending = true;
4404 kvm_make_request(KVM_REQ_EVENT, vcpu);
4405 return 0;
4406 }
4407 return -1;
4408}
a20ed54d
YZ		 4409/*
4410 * Send interrupt to vcpu via posted interrupt way.
4411 * 1. If target vcpu is running(non-root mode), send posted interrupt
4412 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4413 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4414 * interrupt from PIR in next vmentry.
4415 */
4416static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4417{
4418 struct vcpu_vmx *vmx = to_vmx(vcpu);
4419 int r;
4420
705699a1
WV		 4421 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4422 if (!r)
4423 return;
4424
a20ed54d
YZ		 4425 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4426 return;
4427
4428 r = pi_test_and_set_on(&vmx->pi_desc);
4429 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4430 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4431 kvm_vcpu_kick(vcpu);
4432}
4433
4434static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4435{
4436 struct vcpu_vmx *vmx = to_vmx(vcpu);
4437
4438 if (!pi_test_and_clear_on(&vmx->pi_desc))
4439 return;
4440
4441 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4442}
4443
4444static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4445{
4446 return;
4447}
4448
a3a8ff8e
NHE		 4449/*
4450 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4451 * will not change in the lifetime of the guest.
4452 * Note that host-state that does change is set elsewhere. E.g., host-state
4453 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4454 */
a547c6db 4455static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4456{
4457 u32 low32, high32;
4458 unsigned long tmpl;
4459 struct desc_ptr dt;
d974baa3 4460 unsigned long cr4;
a3a8ff8e 4461
b1a74bf8 4462 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4463 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4464
d974baa3 4465 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4466 cr4 = cr4_read_shadow();
d974baa3
AL		 4467 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4468 vmx->host_state.vmcs_host_cr4 = cr4;
4469
a3a8ff8e 4470 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4471#ifdef CONFIG_X86_64
4472 /*
4473 * Load null selectors, so we can avoid reloading them in
4474 * __vmx_load_host_state(), in case userspace uses the null selectors
4475 * too (the expected case).
4476 */
4477 vmcs_write16(HOST_DS_SELECTOR, 0);
4478 vmcs_write16(HOST_ES_SELECTOR, 0);
4479#else
a3a8ff8e
NHE		 4480 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4481 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4482#endif
a3a8ff8e
NHE		 4483 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4484 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4485
4486 native_store_idt(&dt);
4487 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4488 vmx->host_idt_base = dt.address;
a3a8ff8e 4489
83287ea4 4490 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4491
4492 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4493 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4494 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4495 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4496
4497 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4498 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4499 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4500 }
4501}
4502
bf8179a0
NHE		 4503static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4504{
4505 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4506 if (enable_ept)
4507 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4508 if (is_guest_mode(&vmx->vcpu))
4509 vmx->vcpu.arch.cr4_guest_owned_bits &=
4510 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4511 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4512}
4513
01e439be
YZ		 4514static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4515{
4516 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4517
35754c98 4518 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
01e439be
YZ		 4519 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4520 return pin_based_exec_ctrl;
4521}
4522
bf8179a0
NHE		 4523static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4524{
4525 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4526
4527 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4528 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4529
35754c98 4530 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE		 4531 exec_control &= ~CPU_BASED_TPR_SHADOW;
4532#ifdef CONFIG_X86_64
4533 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4534 CPU_BASED_CR8_LOAD_EXITING;
4535#endif
4536 }
4537 if (!enable_ept)
4538 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4539 CPU_BASED_CR3_LOAD_EXITING |
4540 CPU_BASED_INVLPG_EXITING;
4541 return exec_control;
4542}
4543
4544static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4545{
4546 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 4547 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE		 4548 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4549 if (vmx->vpid == 0)
4550 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4551 if (!enable_ept) {
4552 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4553 enable_unrestricted_guest = 0;
ad756a16
MJ		 4554 /* Enable INVPCID for non-ept guests may cause performance regression. */
4555 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4556 }
4557 if (!enable_unrestricted_guest)
4558 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4559 if (!ple_gap)
4560 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
35754c98 4561 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
c7c9c56c
YZ		 4562 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4563 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4564 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4565 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4566 (handle_vmptrld).
4567 We can NOT enable shadow_vmcs here because we don't have yet
4568 a current VMCS12
4569 */
4570 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4571 /* PML is enabled/disabled in creating/destorying vcpu */
4572 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4573
bf8179a0
NHE		 4574 return exec_control;
4575}
4576
ce88decf
XG		 4577static void ept_set_mmio_spte_mask(void)
4578{
4579 /*
4580 * EPT Misconfigurations can be generated if the value of bits 2:0
4581 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4582 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4583 * spte.
4584 */
885032b9 4585 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4586}
4587
f53cd63c 4588#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4589/*
4590 * Sets up the vmcs for emulated real mode.
4591 */
8b9cf98c 4592static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4593{
2e4ce7f5 4594#ifdef CONFIG_X86_64
6aa8b732 4595 unsigned long a;
2e4ce7f5 4596#endif
6aa8b732 4597 int i;
6aa8b732 4598
6aa8b732 4599 /* I/O */
3e7c73e9
AK		 4600 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4601 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4602
4607c2d7
AG		 4603 if (enable_shadow_vmcs) {
4604 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4605 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4606 }
25c5f225 4607 if (cpu_has_vmx_msr_bitmap())
5897297b 4608 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4609
6aa8b732
AK		 4610 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4611
6aa8b732 4612 /* Control */
01e439be 4613 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4614
bf8179a0 4615 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4616
83ff3b9d 4617 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4618 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4619 vmx_secondary_exec_control(vmx));
83ff3b9d 4620 }
f78e0e2e 4621
35754c98 4622 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
c7c9c56c
YZ		 4623 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4624 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4625 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4626 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4627
4628 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4629
4630 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4631 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4632 }
4633
4b8d54f9
ZE		 4634 if (ple_gap) {
4635 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4636 vmx->ple_window = ple_window;
4637 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4638 }
4639
c3707958
XG		 4640 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4641 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4642 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4643
9581d442
AK		 4644 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4645 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4646 vmx_set_constant_host_state(vmx);
05b3e0c2 4647#ifdef CONFIG_X86_64
6aa8b732
AK		 4648 rdmsrl(MSR_FS_BASE, a);
4649 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4650 rdmsrl(MSR_GS_BASE, a);
4651 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4652#else
4653 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4654 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4655#endif
4656
2cc51560
ED		 4657 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4658 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4659 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4660 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4661 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4662
74545705
RK		 4663 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4664 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4665
03916db9 4666 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4667 u32 index = vmx_msr_index[i];
4668 u32 data_low, data_high;
a2fa3e9f 4669 int j = vmx->nmsrs;
6aa8b732
AK		 4670
4671 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4672 continue;
432bd6cb
AK		 4673 if (wrmsr_safe(index, data_low, data_high) < 0)
4674 continue;
26bb0981
AK		 4675 vmx->guest_msrs[j].index = i;
4676 vmx->guest_msrs[j].data = 0;
d5696725 4677 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4678 ++vmx->nmsrs;
6aa8b732 4679 }
6aa8b732 4680
2961e876
GN		 4681
4682 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4683
4684 /* 22.2.1, 20.8.1 */
2961e876 4685 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4686
e00c8cf2 4687 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4688 set_cr4_guest_host_mask(vmx);
e00c8cf2 4689
f53cd63c
WL		 4690 if (vmx_xsaves_supported())
4691 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4692
e00c8cf2
AK		 4693 return 0;
4694}
4695
d28bc9dd 4696static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4697{
4698 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4699 struct msr_data apic_base_msr;
d28bc9dd 4700 u64 cr0;
e00c8cf2 4701
7ffd92c5 4702 vmx->rmode.vm86_active = 0;
e00c8cf2 4703
3b86cd99
JK		 4704 vmx->soft_vnmi_blocked = 0;
4705
ad312c7c 4706 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4707 kvm_set_cr8(vcpu, 0);
4708
4709 if (!init_event) {
4710 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4711 MSR_IA32_APICBASE_ENABLE;
4712 if (kvm_vcpu_is_reset_bsp(vcpu))
4713 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4714 apic_base_msr.host_initiated = true;
4715 kvm_set_apic_base(vcpu, &apic_base_msr);
4716 }
e00c8cf2 4717
2fb92db1
AK		 4718 vmx_segment_cache_clear(vmx);
4719
5706be0d 4720 seg_setup(VCPU_SREG_CS);
66450a21 4721 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4722 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4723
4724 seg_setup(VCPU_SREG_DS);
4725 seg_setup(VCPU_SREG_ES);
4726 seg_setup(VCPU_SREG_FS);
4727 seg_setup(VCPU_SREG_GS);
4728 seg_setup(VCPU_SREG_SS);
4729
4730 vmcs_write16(GUEST_TR_SELECTOR, 0);
4731 vmcs_writel(GUEST_TR_BASE, 0);
4732 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4733 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4734
4735 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4736 vmcs_writel(GUEST_LDTR_BASE, 0);
4737 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4738 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4739
d28bc9dd
NA		 4740 if (!init_event) {
4741 vmcs_write32(GUEST_SYSENTER_CS, 0);
4742 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4743 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4744 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4745 }
e00c8cf2
AK		 4746
4747 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4748 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4749
e00c8cf2
AK		 4750 vmcs_writel(GUEST_GDTR_BASE, 0);
4751 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4752
4753 vmcs_writel(GUEST_IDTR_BASE, 0);
4754 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4755
443381a8 4756 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4757 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4758 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4759
e00c8cf2
AK		 4760 setup_msrs(vmx);
4761
6aa8b732
AK		 4762 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4763
d28bc9dd 4764 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4765 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4766 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4767 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4768 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4769 vmcs_write32(TPR_THRESHOLD, 0);
4770 }
4771
a73896cb 4772 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4773
35754c98 4774 if (vmx_cpu_uses_apicv(vcpu))
01e439be
YZ		 4775 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4776
2384d2b3
SY		 4777 if (vmx->vpid != 0)
4778 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4779
d28bc9dd
NA		 4780 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4781 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4782 vmx->vcpu.arch.cr0 = cr0;
4783 vmx_set_cr4(vcpu, 0);
4784 if (!init_event)
4785 vmx_set_efer(vcpu, 0);
4786 vmx_fpu_activate(vcpu);
4787 update_exception_bitmap(vcpu);
6aa8b732 4788
b9d762fa 4789 vpid_sync_context(vmx);
6aa8b732
AK		 4790}
4791
b6f1250e
NHE		 4792/*
4793 * In nested virtualization, check if L1 asked to exit on external interrupts.
4794 * For most existing hypervisors, this will always return true.
4795 */
4796static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4797{
4798 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4799 PIN_BASED_EXT_INTR_MASK;
4800}
4801
77b0f5d6
BD		 4802/*
4803 * In nested virtualization, check if L1 has set
4804 * VM_EXIT_ACK_INTR_ON_EXIT
4805 */
4806static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4807{
4808 return get_vmcs12(vcpu)->vm_exit_controls &
4809 VM_EXIT_ACK_INTR_ON_EXIT;
4810}
4811
ea8ceb83
JK		 4812static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4813{
4814 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4815 PIN_BASED_NMI_EXITING;
4816}
4817
c9a7953f 4818static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4819{
4820 u32 cpu_based_vm_exec_control;
730dca42 4821
3b86cd99
JK		 4822 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4823 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4824 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4825}
4826
c9a7953f 4827static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4828{
4829 u32 cpu_based_vm_exec_control;
4830
c9a7953f
JK		 4831 if (!cpu_has_virtual_nmis() ||
4832 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4833 enable_irq_window(vcpu);
4834 return;
4835 }
3b86cd99
JK		 4836
4837 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4838 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4839 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4840}
4841
66fd3f7f 4842static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4843{
9c8cba37 4844 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4845 uint32_t intr;
4846 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4847
229456fc 4848 trace_kvm_inj_virq(irq);
2714d1d3 4849
fa89a817 4850 ++vcpu->stat.irq_injections;
7ffd92c5 4851 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4852 int inc_eip = 0;
4853 if (vcpu->arch.interrupt.soft)
4854 inc_eip = vcpu->arch.event_exit_inst_len;
4855 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4856 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4857 return;
4858 }
66fd3f7f
GN		 4859 intr = irq | INTR_INFO_VALID_MASK;
4860 if (vcpu->arch.interrupt.soft) {
4861 intr |= INTR_TYPE_SOFT_INTR;
4862 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4863 vmx->vcpu.arch.event_exit_inst_len);
4864 } else
4865 intr |= INTR_TYPE_EXT_INTR;
4866 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4867}
4868
f08864b4
SY		 4869static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4870{
66a5a347
JK		 4871 struct vcpu_vmx *vmx = to_vmx(vcpu);
4872
0b6ac343
NHE		 4873 if (is_guest_mode(vcpu))
4874 return;
4875
3b86cd99
JK		 4876 if (!cpu_has_virtual_nmis()) {
4877 /*
4878 * Tracking the NMI-blocked state in software is built upon
4879 * finding the next open IRQ window. This, in turn, depends on
4880 * well-behaving guests: They have to keep IRQs disabled at
4881 * least as long as the NMI handler runs. Otherwise we may
4882 * cause NMI nesting, maybe breaking the guest. But as this is
4883 * highly unlikely, we can live with the residual risk.
4884 */
4885 vmx->soft_vnmi_blocked = 1;
4886 vmx->vnmi_blocked_time = 0;
4887 }
4888
487b391d 4889 ++vcpu->stat.nmi_injections;
9d58b931 4890 vmx->nmi_known_unmasked = false;
7ffd92c5 4891 if (vmx->rmode.vm86_active) {
71f9833b 4892 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4893 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4894 return;
4895 }
f08864b4
SY		 4896 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4897 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4898}
4899
3cfc3092
JK		 4900static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4901{
4902 if (!cpu_has_virtual_nmis())
4903 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4904 if (to_vmx(vcpu)->nmi_known_unmasked)
4905 return false;
c332c83a 4906 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4907}
4908
4909static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4910{
4911 struct vcpu_vmx *vmx = to_vmx(vcpu);
4912
4913 if (!cpu_has_virtual_nmis()) {
4914 if (vmx->soft_vnmi_blocked != masked) {
4915 vmx->soft_vnmi_blocked = masked;
4916 vmx->vnmi_blocked_time = 0;
4917 }
4918 } else {
9d58b931 4919 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4920 if (masked)
4921 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4922 GUEST_INTR_STATE_NMI);
4923 else
4924 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4925 GUEST_INTR_STATE_NMI);
4926 }
4927}
4928
2505dc9f
JK		 4929static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4930{
b6b8a145
JK		 4931 if (to_vmx(vcpu)->nested.nested_run_pending)
4932 return 0;
ea8ceb83 4933
2505dc9f
JK		 4934 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4935 return 0;
4936
4937 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4938 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4939 | GUEST_INTR_STATE_NMI));
4940}
4941
78646121
GN		 4942static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4943{
b6b8a145
JK		 4944 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4945 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4946 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4947 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4948}
4949
cbc94022
IE		 4950static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4951{
4952 int ret;
4953 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4954 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4955 .guest_phys_addr = addr,
4956 .memory_size = PAGE_SIZE * 3,
4957 .flags = 0,
4958 };
4959
9da0e4d5 4960 ret = x86_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4961 if (ret)
4962 return ret;
bfc6d222 4963 kvm->arch.tss_addr = addr;
1f755a82 4964 return init_rmode_tss(kvm);
cbc94022
IE		 4965}
4966
0ca1b4f4 4967static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4968{
77ab6db0 4969 switch (vec) {
77ab6db0 4970 case BP_VECTOR:
c573cd22
JK		 4971 /*
4972 * Update instruction length as we may reinject the exception
4973 * from user space while in guest debugging mode.
4974 */
4975 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4976 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4977 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4978 return false;
4979 /* fall through */
4980 case DB_VECTOR:
4981 if (vcpu->guest_debug &
4982 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4983 return false;
d0bfb940
JK		 4984 /* fall through */
4985 case DE_VECTOR:
77ab6db0
JK		 4986 case OF_VECTOR:
4987 case BR_VECTOR:
4988 case UD_VECTOR:
4989 case DF_VECTOR:
4990 case SS_VECTOR:
4991 case GP_VECTOR:
4992 case MF_VECTOR:
0ca1b4f4
GN		 4993 return true;
4994 break;
77ab6db0 4995 }
0ca1b4f4
GN		 4996 return false;
4997}
4998
4999static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5000 int vec, u32 err_code)
5001{
5002 /*
5003 * Instruction with address size override prefix opcode 0x67
5004 * Cause the #SS fault with 0 error code in VM86 mode.
5005 */
5006 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5007 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5008 if (vcpu->arch.halt_request) {
5009 vcpu->arch.halt_request = 0;
5cb56059 5010 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 5011 }
5012 return 1;
5013 }
5014 return 0;
5015 }
5016
5017 /*
5018 * Forward all other exceptions that are valid in real mode.
5019 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5020 * the required debugging infrastructure rework.
5021 */
5022 kvm_queue_exception(vcpu, vec);
5023 return 1;
6aa8b732
AK		 5024}
5025
a0861c02
AK		 5026/*
5027 * Trigger machine check on the host. We assume all the MSRs are already set up
5028 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5029 * We pass a fake environment to the machine check handler because we want
5030 * the guest to be always treated like user space, no matter what context
5031 * it used internally.
5032 */
5033static void kvm_machine_check(void)
5034{
5035#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5036 struct pt_regs regs = {
5037 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5038 .flags = X86_EFLAGS_IF,
5039 };
5040
5041 do_machine_check(&regs, 0);
5042#endif
5043}
5044
851ba692 5045static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5046{
5047 /* already handled by vcpu_run */
5048 return 1;
5049}
5050
851ba692 5051static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5052{
1155f76a 5053 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5054 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5055 u32 intr_info, ex_no, error_code;
42dbaa5a 5056 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5057 u32 vect_info;
5058 enum emulation_result er;
5059
1155f76a 5060 vect_info = vmx->idt_vectoring_info;
88786475 5061 intr_info = vmx->exit_intr_info;
6aa8b732 5062
a0861c02 5063 if (is_machine_check(intr_info))
851ba692 5064 return handle_machine_check(vcpu);
a0861c02 5065
e4a41889 5066 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5067 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5068
5069 if (is_no_device(intr_info)) {
5fd86fcf 5070 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5071 return 1;
5072 }
5073
7aa81cc0 5074 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK		 5075 if (is_guest_mode(vcpu)) {
5076 kvm_queue_exception(vcpu, UD_VECTOR);
5077 return 1;
5078 }
51d8b661 5079 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5080 if (er != EMULATE_DONE)
7ee5d940 5081 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5082 return 1;
5083 }
5084
6aa8b732 5085 error_code = 0;
2e11384c 5086 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5087 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5088
5089 /*
5090 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5091 * MMIO, it is better to report an internal error.
5092 * See the comments in vmx_handle_exit.
5093 */
5094 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5095 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5096 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5097 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5098 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 5099 vcpu->run->internal.data[0] = vect_info;
5100 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5101 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 5102 return 0;
5103 }
5104
6aa8b732 5105 if (is_page_fault(intr_info)) {
1439442c 5106 /* EPT won't cause page fault directly */
cf3ace79 5107 BUG_ON(enable_ept);
6aa8b732 5108 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5109 trace_kvm_page_fault(cr2, error_code);
5110
3298b75c 5111 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5112 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5113 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5114 }
5115
d0bfb940 5116 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5117
5118 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5119 return handle_rmode_exception(vcpu, ex_no, error_code);
5120
42dbaa5a
JK		 5121 switch (ex_no) {
5122 case DB_VECTOR:
5123 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5124 if (!(vcpu->guest_debug &
5125 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5126 vcpu->arch.dr6 &= ~15;
6f43ed01 5127 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5128 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5129 skip_emulated_instruction(vcpu);
5130
42dbaa5a
JK		 5131 kvm_queue_exception(vcpu, DB_VECTOR);
5132 return 1;
5133 }
5134 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5135 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5136 /* fall through */
5137 case BP_VECTOR:
c573cd22
JK		 5138 /*
5139 * Update instruction length as we may reinject #BP from
5140 * user space while in guest debugging mode. Reading it for
5141 * #DB as well causes no harm, it is not used in that case.
5142 */
5143 vmx->vcpu.arch.event_exit_inst_len =
5144 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5145 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5146 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5147 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5148 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5149 break;
5150 default:
d0bfb940
JK		 5151 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5152 kvm_run->ex.exception = ex_no;
5153 kvm_run->ex.error_code = error_code;
42dbaa5a 5154 break;
6aa8b732 5155 }
6aa8b732
AK		 5156 return 0;
5157}
5158
851ba692 5159static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5160{
1165f5fe 5161 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5162 return 1;
5163}
5164
851ba692 5165static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5166{
851ba692 5167 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5168 return 0;
5169}
6aa8b732 5170
851ba692 5171static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5172{
bfdaab09 5173 unsigned long exit_qualification;
34c33d16 5174 int size, in, string;
039576c0 5175 unsigned port;
6aa8b732 5176
bfdaab09 5177 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5178 string = (exit_qualification & 16) != 0;
cf8f70bf 5179 in = (exit_qualification & 8) != 0;
e70669ab 5180
cf8f70bf 5181 ++vcpu->stat.io_exits;
e70669ab 5182
cf8f70bf 5183 if (string || in)
51d8b661 5184 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5185
cf8f70bf
GN		 5186 port = exit_qualification >> 16;
5187 size = (exit_qualification & 7) + 1;
e93f36bc 5188 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5189
5190 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5191}
5192
102d8325
IM		 5193static void
5194vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5195{
5196 /*
5197 * Patch in the VMCALL instruction:
5198 */
5199 hypercall[0] = 0x0f;
5200 hypercall[1] = 0x01;
5201 hypercall[2] = 0xc1;
102d8325
IM		 5202}
5203
b9c237bb 5204static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5205{
5206 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5207 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5208
b9c237bb 5209 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5210 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5211 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5212 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5213 return (val & always_on) == always_on;
5214}
5215
0fa06071 5216/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5217static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5218{
eeadf9e7 5219 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5220 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5221 unsigned long orig_val = val;
5222
eeadf9e7
NHE		 5223 /*
5224 * We get here when L2 changed cr0 in a way that did not change
5225 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5226 * but did change L0 shadowed bits. So we first calculate the
5227 * effective cr0 value that L1 would like to write into the
5228 * hardware. It consists of the L2-owned bits from the new
5229 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5230 */
1a0d74e6
JK		 5231 val = (val & ~vmcs12->cr0_guest_host_mask) |
5232 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5233
b9c237bb 5234 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5235 return 1;
1a0d74e6
JK		 5236
5237 if (kvm_set_cr0(vcpu, val))
5238 return 1;
5239 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5240 return 0;
1a0d74e6
JK		 5241 } else {
5242 if (to_vmx(vcpu)->nested.vmxon &&
5243 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5244 return 1;
eeadf9e7 5245 return kvm_set_cr0(vcpu, val);
1a0d74e6 5246 }
eeadf9e7
NHE		 5247}
5248
5249static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5250{
5251 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5252 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5253 unsigned long orig_val = val;
5254
5255 /* analogously to handle_set_cr0 */
5256 val = (val & ~vmcs12->cr4_guest_host_mask) |
5257 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5258 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5259 return 1;
1a0d74e6 5260 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5261 return 0;
5262 } else
5263 return kvm_set_cr4(vcpu, val);
5264}
5265
5266/* called to set cr0 as approriate for clts instruction exit. */
5267static void handle_clts(struct kvm_vcpu *vcpu)
5268{
5269 if (is_guest_mode(vcpu)) {
5270 /*
5271 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5272 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5273 * just pretend it's off (also in arch.cr0 for fpu_activate).
5274 */
5275 vmcs_writel(CR0_READ_SHADOW,
5276 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5277 vcpu->arch.cr0 &= ~X86_CR0_TS;
5278 } else
5279 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5280}
5281
851ba692 5282static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5283{
229456fc 5284 unsigned long exit_qualification, val;
6aa8b732
AK		 5285 int cr;
5286 int reg;
49a9b07e 5287 int err;
6aa8b732 5288
bfdaab09 5289 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5290 cr = exit_qualification & 15;
5291 reg = (exit_qualification >> 8) & 15;
5292 switch ((exit_qualification >> 4) & 3) {
5293 case 0: /* mov to cr */
1e32c079 5294 val = kvm_register_readl(vcpu, reg);
229456fc 5295 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5296 switch (cr) {
5297 case 0:
eeadf9e7 5298 err = handle_set_cr0(vcpu, val);
db8fcefa 5299 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5300 return 1;
5301 case 3:
2390218b 5302 err = kvm_set_cr3(vcpu, val);
db8fcefa 5303 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5304 return 1;
5305 case 4:
eeadf9e7 5306 err = handle_set_cr4(vcpu, val);
db8fcefa 5307 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5308 return 1;
0a5fff19
GN		 5309 case 8: {
5310 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5311 u8 cr8 = (u8)val;
eea1cff9 5312 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5313 kvm_complete_insn_gp(vcpu, err);
35754c98 5314 if (lapic_in_kernel(vcpu))
0a5fff19
GN		 5315 return 1;
5316 if (cr8_prev <= cr8)
5317 return 1;
851ba692 5318 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5319 return 0;
5320 }
4b8073e4 5321 }
6aa8b732 5322 break;
25c4c276 5323 case 2: /* clts */
eeadf9e7 5324 handle_clts(vcpu);
4d4ec087 5325 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5326 skip_emulated_instruction(vcpu);
6b52d186 5327 vmx_fpu_activate(vcpu);
25c4c276 5328 return 1;
6aa8b732
AK		 5329 case 1: /*mov from cr*/
5330 switch (cr) {
5331 case 3:
9f8fe504
AK		 5332 val = kvm_read_cr3(vcpu);
5333 kvm_register_write(vcpu, reg, val);
5334 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5335 skip_emulated_instruction(vcpu);
5336 return 1;
5337 case 8:
229456fc
MT		 5338 val = kvm_get_cr8(vcpu);
5339 kvm_register_write(vcpu, reg, val);
5340 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5341 skip_emulated_instruction(vcpu);
5342 return 1;
5343 }
5344 break;
5345 case 3: /* lmsw */
a1f83a74 5346 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5347 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5348 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5349
5350 skip_emulated_instruction(vcpu);
5351 return 1;
5352 default:
5353 break;
5354 }
851ba692 5355 vcpu->run->exit_reason = 0;
a737f256 5356 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5357 (int)(exit_qualification >> 4) & 3, cr);
5358 return 0;
5359}
5360
851ba692 5361static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5362{
bfdaab09 5363 unsigned long exit_qualification;
16f8a6f9
NA		 5364 int dr, dr7, reg;
5365
5366 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5367 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5368
5369 /* First, if DR does not exist, trigger UD */
5370 if (!kvm_require_dr(vcpu, dr))
5371 return 1;
6aa8b732 5372
f2483415 5373 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5374 if (!kvm_require_cpl(vcpu, 0))
5375 return 1;
16f8a6f9
NA		 5376 dr7 = vmcs_readl(GUEST_DR7);
5377 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5378 /*
5379 * As the vm-exit takes precedence over the debug trap, we
5380 * need to emulate the latter, either for the host or the
5381 * guest debugging itself.
5382 */
5383 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5384 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5385 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5386 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5387 vcpu->run->debug.arch.exception = DB_VECTOR;
5388 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5389 return 0;
5390 } else {
7305eb5d 5391 vcpu->arch.dr6 &= ~15;
6f43ed01 5392 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5393 kvm_queue_exception(vcpu, DB_VECTOR);
5394 return 1;
5395 }
5396 }
5397
81908bf4
PB		 5398 if (vcpu->guest_debug == 0) {
5399 u32 cpu_based_vm_exec_control;
5400
5401 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5402 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5403 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5404
5405 /*
5406 * No more DR vmexits; force a reload of the debug registers
5407 * and reenter on this instruction. The next vmexit will
5408 * retrieve the full state of the debug registers.
5409 */
5410 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5411 return 1;
5412 }
5413
42dbaa5a
JK		 5414 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5415 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5416 unsigned long val;
4c4d563b
JK		 5417
5418 if (kvm_get_dr(vcpu, dr, &val))
5419 return 1;
5420 kvm_register_write(vcpu, reg, val);
020df079 5421 } else
5777392e 5422 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5423 return 1;
5424
6aa8b732
AK		 5425 skip_emulated_instruction(vcpu);
5426 return 1;
5427}
5428
73aaf249
JK		 5429static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5430{
5431 return vcpu->arch.dr6;
5432}
5433
5434static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5435{
5436}
5437
81908bf4
PB		 5438static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5439{
5440 u32 cpu_based_vm_exec_control;
5441
5442 get_debugreg(vcpu->arch.db[0], 0);
5443 get_debugreg(vcpu->arch.db[1], 1);
5444 get_debugreg(vcpu->arch.db[2], 2);
5445 get_debugreg(vcpu->arch.db[3], 3);
5446 get_debugreg(vcpu->arch.dr6, 6);
5447 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5448
5449 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5450
5451 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5452 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5453 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5454}
5455
020df079
GN		 5456static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5457{
5458 vmcs_writel(GUEST_DR7, val);
5459}
5460
851ba692 5461static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5462{
06465c5a
AK		 5463 kvm_emulate_cpuid(vcpu);
5464 return 1;
6aa8b732
AK		 5465}
5466
851ba692 5467static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5468{
ad312c7c 5469 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 5470 struct msr_data msr_info;
6aa8b732 5471
609e36d3
PB		 5472 msr_info.index = ecx;
5473 msr_info.host_initiated = false;
5474 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 5475 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5476 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5477 return 1;
5478 }
5479
609e36d3 5480 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 5481
6aa8b732 5482 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB		 5483 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5484 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6aa8b732
AK		 5485 skip_emulated_instruction(vcpu);
5486 return 1;
5487}
5488
851ba692 5489static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5490{
8fe8ab46 5491 struct msr_data msr;
ad312c7c
ZX		 5492 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5493 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5494 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5495
8fe8ab46
WA		 5496 msr.data = data;
5497 msr.index = ecx;
5498 msr.host_initiated = false;
854e8bb1 5499 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5500 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5501 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5502 return 1;
5503 }
5504
59200273 5505 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5506 skip_emulated_instruction(vcpu);
5507 return 1;
5508}
5509
851ba692 5510static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5511{
3842d135 5512 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5513 return 1;
5514}
5515
851ba692 5516static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5517{
85f455f7
ED		 5518 u32 cpu_based_vm_exec_control;
5519
5520 /* clear pending irq */
5521 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5522 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5523 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5524
3842d135
AK		 5525 kvm_make_request(KVM_REQ_EVENT, vcpu);
5526
a26bf12a 5527 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 5528 return 1;
5529}
5530
851ba692 5531static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 5532{
d3bef15f 5533 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5534}
5535
851ba692 5536static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5537{
7aa81cc0
AL		 5538 kvm_emulate_hypercall(vcpu);
5539 return 1;
c21415e8
IM		 5540}
5541
ec25d5e6
GN		 5542static int handle_invd(struct kvm_vcpu *vcpu)
5543{
51d8b661 5544 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5545}
5546
851ba692 5547static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5548{
f9c617f6 5549 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5550
5551 kvm_mmu_invlpg(vcpu, exit_qualification);
5552 skip_emulated_instruction(vcpu);
5553 return 1;
5554}
5555
fee84b07
AK		 5556static int handle_rdpmc(struct kvm_vcpu *vcpu)
5557{
5558 int err;
5559
5560 err = kvm_rdpmc(vcpu);
5561 kvm_complete_insn_gp(vcpu, err);
5562
5563 return 1;
5564}
5565
851ba692 5566static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5567{
f5f48ee1 5568 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5569 return 1;
5570}
5571
2acf923e
DC		 5572static int handle_xsetbv(struct kvm_vcpu *vcpu)
5573{
5574 u64 new_bv = kvm_read_edx_eax(vcpu);
5575 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5576
5577 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5578 skip_emulated_instruction(vcpu);
5579 return 1;
5580}
5581
f53cd63c
WL		 5582static int handle_xsaves(struct kvm_vcpu *vcpu)
5583{
5584 skip_emulated_instruction(vcpu);
5585 WARN(1, "this should never happen\n");
5586 return 1;
5587}
5588
5589static int handle_xrstors(struct kvm_vcpu *vcpu)
5590{
5591 skip_emulated_instruction(vcpu);
5592 WARN(1, "this should never happen\n");
5593 return 1;
5594}
5595
851ba692 5596static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5597{
58fbbf26
KT		 5598 if (likely(fasteoi)) {
5599 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5600 int access_type, offset;
5601
5602 access_type = exit_qualification & APIC_ACCESS_TYPE;
5603 offset = exit_qualification & APIC_ACCESS_OFFSET;
5604 /*
5605 * Sane guest uses MOV to write EOI, with written value
5606 * not cared. So make a short-circuit here by avoiding
5607 * heavy instruction emulation.
5608 */
5609 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5610 (offset == APIC_EOI)) {
5611 kvm_lapic_set_eoi(vcpu);
5612 skip_emulated_instruction(vcpu);
5613 return 1;
5614 }
5615 }
51d8b661 5616 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5617}
5618
c7c9c56c
YZ		 5619static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5620{
5621 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5622 int vector = exit_qualification & 0xff;
5623
5624 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5625 kvm_apic_set_eoi_accelerated(vcpu, vector);
5626 return 1;
5627}
5628
83d4c286
YZ		 5629static int handle_apic_write(struct kvm_vcpu *vcpu)
5630{
5631 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5632 u32 offset = exit_qualification & 0xfff;
5633
5634 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5635 kvm_apic_write_nodecode(vcpu, offset);
5636 return 1;
5637}
5638
851ba692 5639static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5640{
60637aac 5641 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5642 unsigned long exit_qualification;
e269fb21
JK		 5643 bool has_error_code = false;
5644 u32 error_code = 0;
37817f29 5645 u16 tss_selector;
7f3d35fd 5646 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5647
5648 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5649 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5650 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5651
5652 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5653
5654 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5655 if (reason == TASK_SWITCH_GATE && idt_v) {
5656 switch (type) {
5657 case INTR_TYPE_NMI_INTR:
5658 vcpu->arch.nmi_injected = false;
654f06fc 5659 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5660 break;
5661 case INTR_TYPE_EXT_INTR:
66fd3f7f 5662 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5663 kvm_clear_interrupt_queue(vcpu);
5664 break;
5665 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5666 if (vmx->idt_vectoring_info &
5667 VECTORING_INFO_DELIVER_CODE_MASK) {
5668 has_error_code = true;
5669 error_code =
5670 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5671 }
5672 /* fall through */
64a7ec06
GN		 5673 case INTR_TYPE_SOFT_EXCEPTION:
5674 kvm_clear_exception_queue(vcpu);
5675 break;
5676 default:
5677 break;
5678 }
60637aac 5679 }
37817f29
IE		 5680 tss_selector = exit_qualification;
5681
64a7ec06
GN		 5682 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5683 type != INTR_TYPE_EXT_INTR &&
5684 type != INTR_TYPE_NMI_INTR))
5685 skip_emulated_instruction(vcpu);
5686
7f3d35fd
KW		 5687 if (kvm_task_switch(vcpu, tss_selector,
5688 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5689 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5690 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5691 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5692 vcpu->run->internal.ndata = 0;
42dbaa5a 5693 return 0;
acb54517 5694 }
42dbaa5a 5695
42dbaa5a
JK		 5696 /*
5697 * TODO: What about debug traps on tss switch?
5698 * Are we supposed to inject them and update dr6?
5699 */
5700
5701 return 1;
37817f29
IE		 5702}
5703
851ba692 5704static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5705{
f9c617f6 5706 unsigned long exit_qualification;
1439442c 5707 gpa_t gpa;
4f5982a5 5708 u32 error_code;
1439442c 5709 int gla_validity;
1439442c 5710
f9c617f6 5711 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5712
1439442c
SY		 5713 gla_validity = (exit_qualification >> 7) & 0x3;
5714 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5715 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5716 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5717 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5718 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5719 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5720 (long unsigned int)exit_qualification);
851ba692
AK		 5721 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5722 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5723 return 0;
1439442c
SY		 5724 }
5725
0be9c7a8
GN		 5726 /*
5727 * EPT violation happened while executing iret from NMI,
5728 * "blocked by NMI" bit has to be set before next VM entry.
5729 * There are errata that may cause this bit to not be set:
5730 * AAK134, BY25.
5731 */
bcd1c294
GN		 5732 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5733 cpu_has_virtual_nmis() &&
5734 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5735 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5736
1439442c 5737 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5738 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5739
5740 /* It is a write fault? */
81ed33e4 5741 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5742 /* It is a fetch fault? */
81ed33e4 5743 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5744 /* ept page table is present? */
81ed33e4 5745 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5746
25d92081
YZ		 5747 vcpu->arch.exit_qualification = exit_qualification;
5748
4f5982a5 5749 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5750}
5751
851ba692 5752static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5753{
f735d4af 5754 int ret;
68f89400
MT		 5755 gpa_t gpa;
5756
5757 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 5758 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
68c3b4d1 5759 skip_emulated_instruction(vcpu);
931c33b1 5760 trace_kvm_fast_mmio(gpa);
68c3b4d1
MT		 5761 return 1;
5762 }
68f89400 5763
ce88decf 5764 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5765 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5766 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5767 EMULATE_DONE;
f8f55942
XG		 5768
5769 if (unlikely(ret == RET_MMIO_PF_INVALID))
5770 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5771
b37fbea6 5772 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5773 return 1;
5774
5775 /* It is the real ept misconfig */
f735d4af 5776 WARN_ON(1);
68f89400 5777
851ba692
AK		 5778 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5779 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5780
5781 return 0;
5782}
5783
851ba692 5784static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5785{
5786 u32 cpu_based_vm_exec_control;
5787
5788 /* clear pending NMI */
5789 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5790 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5791 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5792 ++vcpu->stat.nmi_window_exits;
3842d135 5793 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5794
5795 return 1;
5796}
5797
80ced186 5798static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5799{
8b3079a5
AK		 5800 struct vcpu_vmx *vmx = to_vmx(vcpu);
5801 enum emulation_result err = EMULATE_DONE;
80ced186 5802 int ret = 1;
49e9d557
AK		 5803 u32 cpu_exec_ctrl;
5804 bool intr_window_requested;
b8405c18 5805 unsigned count = 130;
49e9d557
AK		 5806
5807 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5808 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5809
98eb2f8b 5810 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5811 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5812 return handle_interrupt_window(&vmx->vcpu);
5813
de87dcdd
AK		 5814 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5815 return 1;
5816
991eebf9 5817 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5818
ac0a48c3 5819 if (err == EMULATE_USER_EXIT) {
94452b9e 5820 ++vcpu->stat.mmio_exits;
80ced186
MG		 5821 ret = 0;
5822 goto out;
5823 }
1d5a4d9b 5824
de5f70e0
AK		 5825 if (err != EMULATE_DONE) {
5826 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5827 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5828 vcpu->run->internal.ndata = 0;
6d77dbfc 5829 return 0;
de5f70e0 5830 }
ea953ef0 5831
8d76c49e
GN		 5832 if (vcpu->arch.halt_request) {
5833 vcpu->arch.halt_request = 0;
5cb56059 5834 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5835 goto out;
5836 }
5837
ea953ef0 5838 if (signal_pending(current))
80ced186 5839 goto out;
ea953ef0
MG		 5840 if (need_resched())
5841 schedule();
5842 }
5843
80ced186
MG		 5844out:
5845 return ret;
ea953ef0
MG		 5846}
5847
b4a2d31d
RK		 5848static int __grow_ple_window(int val)
5849{
5850 if (ple_window_grow < 1)
5851 return ple_window;
5852
5853 val = min(val, ple_window_actual_max);
5854
5855 if (ple_window_grow < ple_window)
5856 val *= ple_window_grow;
5857 else
5858 val += ple_window_grow;
5859
5860 return val;
5861}
5862
5863static int __shrink_ple_window(int val, int modifier, int minimum)
5864{
5865 if (modifier < 1)
5866 return ple_window;
5867
5868 if (modifier < ple_window)
5869 val /= modifier;
5870 else
5871 val -= modifier;
5872
5873 return max(val, minimum);
5874}
5875
5876static void grow_ple_window(struct kvm_vcpu *vcpu)
5877{
5878 struct vcpu_vmx *vmx = to_vmx(vcpu);
5879 int old = vmx->ple_window;
5880
5881 vmx->ple_window = __grow_ple_window(old);
5882
5883 if (vmx->ple_window != old)
5884 vmx->ple_window_dirty = true;
7b46268d
RK		 5885
5886 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5887}
5888
5889static void shrink_ple_window(struct kvm_vcpu *vcpu)
5890{
5891 struct vcpu_vmx *vmx = to_vmx(vcpu);
5892 int old = vmx->ple_window;
5893
5894 vmx->ple_window = __shrink_ple_window(old,
5895 ple_window_shrink, ple_window);
5896
5897 if (vmx->ple_window != old)
5898 vmx->ple_window_dirty = true;
7b46268d
RK		 5899
5900 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5901}
5902
5903/*
5904 * ple_window_actual_max is computed to be one grow_ple_window() below
5905 * ple_window_max. (See __grow_ple_window for the reason.)
5906 * This prevents overflows, because ple_window_max is int.
5907 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5908 * this process.
5909 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5910 */
5911static void update_ple_window_actual_max(void)
5912{
5913 ple_window_actual_max =
5914 __shrink_ple_window(max(ple_window_max, ple_window),
5915 ple_window_grow, INT_MIN);
5916}
5917
f2c7648d
TC		 5918static __init int hardware_setup(void)
5919{
34a1cd60
TC		 5920 int r = -ENOMEM, i, msr;
5921
5922 rdmsrl_safe(MSR_EFER, &host_efer);
5923
5924 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5925 kvm_define_shared_msr(i, vmx_msr_index[i]);
5926
5927 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5928 if (!vmx_io_bitmap_a)
5929 return r;
5930
5931 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5932 if (!vmx_io_bitmap_b)
5933 goto out;
5934
5935 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5936 if (!vmx_msr_bitmap_legacy)
5937 goto out1;
5938
5939 vmx_msr_bitmap_legacy_x2apic =
5940 (unsigned long *)__get_free_page(GFP_KERNEL);
5941 if (!vmx_msr_bitmap_legacy_x2apic)
5942 goto out2;
5943
5944 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5945 if (!vmx_msr_bitmap_longmode)
5946 goto out3;
5947
5948 vmx_msr_bitmap_longmode_x2apic =
5949 (unsigned long *)__get_free_page(GFP_KERNEL);
5950 if (!vmx_msr_bitmap_longmode_x2apic)
5951 goto out4;
3af18d9c
WV		 5952
5953 if (nested) {
5954 vmx_msr_bitmap_nested =
5955 (unsigned long *)__get_free_page(GFP_KERNEL);
5956 if (!vmx_msr_bitmap_nested)
5957 goto out5;
5958 }
5959
34a1cd60
TC		 5960 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5961 if (!vmx_vmread_bitmap)
3af18d9c 5962 goto out6;
34a1cd60
TC		 5963
5964 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5965 if (!vmx_vmwrite_bitmap)
3af18d9c 5966 goto out7;
34a1cd60
TC		 5967
5968 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5969 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5970
5971 /*
5972 * Allow direct access to the PC debug port (it is often used for I/O
5973 * delays, but the vmexits simply slow things down).
5974 */
5975 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5976 clear_bit(0x80, vmx_io_bitmap_a);
5977
5978 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5979
5980 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5981 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 5982 if (nested)
5983 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 5984
34a1cd60
TC		 5985 if (setup_vmcs_config(&vmcs_config) < 0) {
5986 r = -EIO;
3af18d9c 5987 goto out8;
baa03522 5988 }
f2c7648d
TC		 5989
5990 if (boot_cpu_has(X86_FEATURE_NX))
5991 kvm_enable_efer_bits(EFER_NX);
5992
5993 if (!cpu_has_vmx_vpid())
5994 enable_vpid = 0;
5995 if (!cpu_has_vmx_shadow_vmcs())
5996 enable_shadow_vmcs = 0;
5997 if (enable_shadow_vmcs)
5998 init_vmcs_shadow_fields();
5999
6000 if (!cpu_has_vmx_ept() ||
6001 !cpu_has_vmx_ept_4levels()) {
6002 enable_ept = 0;
6003 enable_unrestricted_guest = 0;
6004 enable_ept_ad_bits = 0;
6005 }
6006
6007 if (!cpu_has_vmx_ept_ad_bits())
6008 enable_ept_ad_bits = 0;
6009
6010 if (!cpu_has_vmx_unrestricted_guest())
6011 enable_unrestricted_guest = 0;
6012
ad15a296 6013 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6014 flexpriority_enabled = 0;
6015
ad15a296
PB		 6016 /*
6017 * set_apic_access_page_addr() is used to reload apic access
6018 * page upon invalidation. No need to do anything if not
6019 * using the APIC_ACCESS_ADDR VMCS field.
6020 */
6021 if (!flexpriority_enabled)
f2c7648d 6022 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6023
6024 if (!cpu_has_vmx_tpr_shadow())
6025 kvm_x86_ops->update_cr8_intercept = NULL;
6026
6027 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6028 kvm_disable_largepages();
6029
6030 if (!cpu_has_vmx_ple())
6031 ple_gap = 0;
6032
6033 if (!cpu_has_vmx_apicv())
6034 enable_apicv = 0;
6035
6036 if (enable_apicv)
6037 kvm_x86_ops->update_cr8_intercept = NULL;
6038 else {
6039 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6040 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6041 kvm_x86_ops->deliver_posted_interrupt = NULL;
6042 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6043 }
6044
baa03522
TC		 6045 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6046 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6047 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6048 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6049 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6050 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6051 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6052
6053 memcpy(vmx_msr_bitmap_legacy_x2apic,
6054 vmx_msr_bitmap_legacy, PAGE_SIZE);
6055 memcpy(vmx_msr_bitmap_longmode_x2apic,
6056 vmx_msr_bitmap_longmode, PAGE_SIZE);
6057
04bb92e4
WL		 6058 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6059
baa03522
TC		 6060 if (enable_apicv) {
6061 for (msr = 0x800; msr <= 0x8ff; msr++)
6062 vmx_disable_intercept_msr_read_x2apic(msr);
6063
6064 /* According SDM, in x2apic mode, the whole id reg is used.
6065 * But in KVM, it only use the highest eight bits. Need to
6066 * intercept it */
6067 vmx_enable_intercept_msr_read_x2apic(0x802);
6068 /* TMCCT */
6069 vmx_enable_intercept_msr_read_x2apic(0x839);
6070 /* TPR */
6071 vmx_disable_intercept_msr_write_x2apic(0x808);
6072 /* EOI */
6073 vmx_disable_intercept_msr_write_x2apic(0x80b);
6074 /* SELF-IPI */
6075 vmx_disable_intercept_msr_write_x2apic(0x83f);
6076 }
6077
6078 if (enable_ept) {
6079 kvm_mmu_set_mask_ptes(0ull,
6080 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6081 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6082 0ull, VMX_EPT_EXECUTABLE_MASK);
6083 ept_set_mmio_spte_mask();
6084 kvm_enable_tdp();
6085 } else
6086 kvm_disable_tdp();
6087
6088 update_ple_window_actual_max();
6089
843e4330
KH		 6090 /*
6091 * Only enable PML when hardware supports PML feature, and both EPT
6092 * and EPT A/D bit features are enabled -- PML depends on them to work.
6093 */
6094 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6095 enable_pml = 0;
6096
6097 if (!enable_pml) {
6098 kvm_x86_ops->slot_enable_log_dirty = NULL;
6099 kvm_x86_ops->slot_disable_log_dirty = NULL;
6100 kvm_x86_ops->flush_log_dirty = NULL;
6101 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6102 }
6103
f2c7648d 6104 return alloc_kvm_area();
34a1cd60 6105
3af18d9c 6106out8:
34a1cd60 6107 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6108out7:
34a1cd60 6109 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6110out6:
6111 if (nested)
6112 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6113out5:
6114 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6115out4:
6116 free_page((unsigned long)vmx_msr_bitmap_longmode);
6117out3:
6118 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6119out2:
6120 free_page((unsigned long)vmx_msr_bitmap_legacy);
6121out1:
6122 free_page((unsigned long)vmx_io_bitmap_b);
6123out:
6124 free_page((unsigned long)vmx_io_bitmap_a);
6125
6126 return r;
f2c7648d
TC		 6127}
6128
6129static __exit void hardware_unsetup(void)
6130{
34a1cd60
TC		 6131 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6132 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6133 free_page((unsigned long)vmx_msr_bitmap_legacy);
6134 free_page((unsigned long)vmx_msr_bitmap_longmode);
6135 free_page((unsigned long)vmx_io_bitmap_b);
6136 free_page((unsigned long)vmx_io_bitmap_a);
6137 free_page((unsigned long)vmx_vmwrite_bitmap);
6138 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6139 if (nested)
6140 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6141
f2c7648d
TC		 6142 free_kvm_area();
6143}
6144
4b8d54f9
ZE		 6145/*
6146 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6147 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6148 */
9fb41ba8 6149static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6150{
b4a2d31d
RK		 6151 if (ple_gap)
6152 grow_ple_window(vcpu);
6153
4b8d54f9
ZE		 6154 skip_emulated_instruction(vcpu);
6155 kvm_vcpu_on_spin(vcpu);
6156
6157 return 1;
6158}
6159
87c00572 6160static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6161{
87c00572 6162 skip_emulated_instruction(vcpu);
59708670
SY		 6163 return 1;
6164}
6165
87c00572
GS		 6166static int handle_mwait(struct kvm_vcpu *vcpu)
6167{
6168 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6169 return handle_nop(vcpu);
6170}
6171
5f3d45e7
MD		 6172static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6173{
6174 return 1;
6175}
6176
87c00572
GS		 6177static int handle_monitor(struct kvm_vcpu *vcpu)
6178{
6179 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6180 return handle_nop(vcpu);
6181}
6182
ff2f6fe9
NHE		 6183/*
6184 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6185 * We could reuse a single VMCS for all the L2 guests, but we also want the
6186 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6187 * allows keeping them loaded on the processor, and in the future will allow
6188 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6189 * every entry if they never change.
6190 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6191 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6192 *
6193 * The following functions allocate and free a vmcs02 in this pool.
6194 */
6195
6196/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6197static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6198{
6199 struct vmcs02_list *item;
6200 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6201 if (item->vmptr == vmx->nested.current_vmptr) {
6202 list_move(&item->list, &vmx->nested.vmcs02_pool);
6203 return &item->vmcs02;
6204 }
6205
6206 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6207 /* Recycle the least recently used VMCS. */
6208 item = list_entry(vmx->nested.vmcs02_pool.prev,
6209 struct vmcs02_list, list);
6210 item->vmptr = vmx->nested.current_vmptr;
6211 list_move(&item->list, &vmx->nested.vmcs02_pool);
6212 return &item->vmcs02;
6213 }
6214
6215 /* Create a new VMCS */
0fa24ce3 6216 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6217 if (!item)
6218 return NULL;
6219 item->vmcs02.vmcs = alloc_vmcs();
6220 if (!item->vmcs02.vmcs) {
6221 kfree(item);
6222 return NULL;
6223 }
6224 loaded_vmcs_init(&item->vmcs02);
6225 item->vmptr = vmx->nested.current_vmptr;
6226 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6227 vmx->nested.vmcs02_num++;
6228 return &item->vmcs02;
6229}
6230
6231/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6232static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6233{
6234 struct vmcs02_list *item;
6235 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6236 if (item->vmptr == vmptr) {
6237 free_loaded_vmcs(&item->vmcs02);
6238 list_del(&item->list);
6239 kfree(item);
6240 vmx->nested.vmcs02_num--;
6241 return;
6242 }
6243}
6244
6245/*
6246 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6247 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6248 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6249 */
6250static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6251{
6252 struct vmcs02_list *item, *n;
4fa7734c
PB		 6253
6254 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6255 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6256 /*
6257 * Something will leak if the above WARN triggers. Better than
6258 * a use-after-free.
6259 */
6260 if (vmx->loaded_vmcs == &item->vmcs02)
6261 continue;
6262
6263 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6264 list_del(&item->list);
6265 kfree(item);
4fa7734c 6266 vmx->nested.vmcs02_num--;
ff2f6fe9 6267 }
ff2f6fe9
NHE		 6268}
6269
0658fbaa
ACL		 6270/*
6271 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6272 * set the success or error code of an emulated VMX instruction, as specified
6273 * by Vol 2B, VMX Instruction Reference, "Conventions".
6274 */
6275static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6276{
6277 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6278 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6279 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6280}
6281
6282static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6283{
6284 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6285 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6286 X86_EFLAGS_SF | X86_EFLAGS_OF))
6287 | X86_EFLAGS_CF);
6288}
6289
145c28dd 6290static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6291 u32 vm_instruction_error)
6292{
6293 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6294 /*
6295 * failValid writes the error number to the current VMCS, which
6296 * can't be done there isn't a current VMCS.
6297 */
6298 nested_vmx_failInvalid(vcpu);
6299 return;
6300 }
6301 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6302 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6303 X86_EFLAGS_SF | X86_EFLAGS_OF))
6304 | X86_EFLAGS_ZF);
6305 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6306 /*
6307 * We don't need to force a shadow sync because
6308 * VM_INSTRUCTION_ERROR is not shadowed
6309 */
6310}
145c28dd 6311
ff651cb6
WV		 6312static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6313{
6314 /* TODO: not to reset guest simply here. */
6315 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6316 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6317}
6318
f4124500
JK		 6319static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6320{
6321 struct vcpu_vmx *vmx =
6322 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6323
6324 vmx->nested.preemption_timer_expired = true;
6325 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6326 kvm_vcpu_kick(&vmx->vcpu);
6327
6328 return HRTIMER_NORESTART;
6329}
6330
19677e32
BD		 6331/*
6332 * Decode the memory-address operand of a vmx instruction, as recorded on an
6333 * exit caused by such an instruction (run by a guest hypervisor).
6334 * On success, returns 0. When the operand is invalid, returns 1 and throws
6335 * #UD or #GP.
6336 */
6337static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6338 unsigned long exit_qualification,
f9eb4af6 6339 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6340{
f9eb4af6
EK		 6341 gva_t off;
6342 bool exn;
6343 struct kvm_segment s;
6344
19677e32
BD		 6345 /*
6346 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6347 * Execution", on an exit, vmx_instruction_info holds most of the
6348 * addressing components of the operand. Only the displacement part
6349 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6350 * For how an actual address is calculated from all these components,
6351 * refer to Vol. 1, "Operand Addressing".
6352 */
6353 int scaling = vmx_instruction_info & 3;
6354 int addr_size = (vmx_instruction_info >> 7) & 7;
6355 bool is_reg = vmx_instruction_info & (1u << 10);
6356 int seg_reg = (vmx_instruction_info >> 15) & 7;
6357 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6358 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6359 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6360 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6361
6362 if (is_reg) {
6363 kvm_queue_exception(vcpu, UD_VECTOR);
6364 return 1;
6365 }
6366
6367 /* Addr = segment_base + offset */
6368 /* offset = base + [index * scale] + displacement */
f9eb4af6 6369 off = exit_qualification; /* holds the displacement */
19677e32 6370 if (base_is_valid)
f9eb4af6 6371 off += kvm_register_read(vcpu, base_reg);
19677e32 6372 if (index_is_valid)
f9eb4af6
EK		 6373 off += kvm_register_read(vcpu, index_reg)<<scaling;
6374 vmx_get_segment(vcpu, &s, seg_reg);
6375 *ret = s.base + off;
19677e32
BD		 6376
6377 if (addr_size == 1) /* 32 bit */
6378 *ret &= 0xffffffff;
6379
f9eb4af6
EK		 6380 /* Checks for #GP/#SS exceptions. */
6381 exn = false;
6382 if (is_protmode(vcpu)) {
6383 /* Protected mode: apply checks for segment validity in the
6384 * following order:
6385 * - segment type check (#GP(0) may be thrown)
6386 * - usability check (#GP(0)/#SS(0))
6387 * - limit check (#GP(0)/#SS(0))
6388 */
6389 if (wr)
6390 /* #GP(0) if the destination operand is located in a
6391 * read-only data segment or any code segment.
6392 */
6393 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6394 else
6395 /* #GP(0) if the source operand is located in an
6396 * execute-only code segment
6397 */
6398 exn = ((s.type & 0xa) == 8);
6399 }
6400 if (exn) {
6401 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6402 return 1;
6403 }
6404 if (is_long_mode(vcpu)) {
6405 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6406 * non-canonical form. This is an only check for long mode.
6407 */
6408 exn = is_noncanonical_address(*ret);
6409 } else if (is_protmode(vcpu)) {
6410 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6411 */
6412 exn = (s.unusable != 0);
6413 /* Protected mode: #GP(0)/#SS(0) if the memory
6414 * operand is outside the segment limit.
6415 */
6416 exn = exn || (off + sizeof(u64) > s.limit);
6417 }
6418 if (exn) {
6419 kvm_queue_exception_e(vcpu,
6420 seg_reg == VCPU_SREG_SS ?
6421 SS_VECTOR : GP_VECTOR,
6422 0);
6423 return 1;
6424 }
6425
19677e32
BD		 6426 return 0;
6427}
6428
3573e22c
BD		 6429/*
6430 * This function performs the various checks including
6431 * - if it's 4KB aligned
6432 * - No bits beyond the physical address width are set
6433 * - Returns 0 on success or else 1
4291b588 6434 * (Intel SDM Section 30.3)
3573e22c 6435 */
4291b588
BD		 6436static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6437 gpa_t *vmpointer)
3573e22c
BD		 6438{
6439 gva_t gva;
6440 gpa_t vmptr;
6441 struct x86_exception e;
6442 struct page *page;
6443 struct vcpu_vmx *vmx = to_vmx(vcpu);
6444 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6445
6446 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6447 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD		 6448 return 1;
6449
6450 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6451 sizeof(vmptr), &e)) {
6452 kvm_inject_page_fault(vcpu, &e);
6453 return 1;
6454 }
6455
6456 switch (exit_reason) {
6457 case EXIT_REASON_VMON:
6458 /*
6459 * SDM 3: 24.11.5
6460 * The first 4 bytes of VMXON region contain the supported
6461 * VMCS revision identifier
6462 *
6463 * Note - IA32_VMX_BASIC[48] will never be 1
6464 * for the nested case;
6465 * which replaces physical address width with 32
6466 *
6467 */
bc39c4db 6468 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6469 nested_vmx_failInvalid(vcpu);
6470 skip_emulated_instruction(vcpu);
6471 return 1;
6472 }
6473
6474 page = nested_get_page(vcpu, vmptr);
6475 if (page == NULL ||
6476 *(u32 *)kmap(page) != VMCS12_REVISION) {
6477 nested_vmx_failInvalid(vcpu);
6478 kunmap(page);
6479 skip_emulated_instruction(vcpu);
6480 return 1;
6481 }
6482 kunmap(page);
6483 vmx->nested.vmxon_ptr = vmptr;
6484 break;
4291b588 6485 case EXIT_REASON_VMCLEAR:
bc39c4db 6486 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6487 nested_vmx_failValid(vcpu,
6488 VMXERR_VMCLEAR_INVALID_ADDRESS);
6489 skip_emulated_instruction(vcpu);
6490 return 1;
6491 }
6492
6493 if (vmptr == vmx->nested.vmxon_ptr) {
6494 nested_vmx_failValid(vcpu,
6495 VMXERR_VMCLEAR_VMXON_POINTER);
6496 skip_emulated_instruction(vcpu);
6497 return 1;
6498 }
6499 break;
6500 case EXIT_REASON_VMPTRLD:
bc39c4db 6501 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6502 nested_vmx_failValid(vcpu,
6503 VMXERR_VMPTRLD_INVALID_ADDRESS);
6504 skip_emulated_instruction(vcpu);
6505 return 1;
6506 }
3573e22c 6507
4291b588
BD		 6508 if (vmptr == vmx->nested.vmxon_ptr) {
6509 nested_vmx_failValid(vcpu,
6510 VMXERR_VMCLEAR_VMXON_POINTER);
6511 skip_emulated_instruction(vcpu);
6512 return 1;
6513 }
6514 break;
3573e22c
BD		 6515 default:
6516 return 1; /* shouldn't happen */
6517 }
6518
4291b588
BD		 6519 if (vmpointer)
6520 *vmpointer = vmptr;
3573e22c
BD		 6521 return 0;
6522}
6523
ec378aee
NHE		 6524/*
6525 * Emulate the VMXON instruction.
6526 * Currently, we just remember that VMX is active, and do not save or even
6527 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6528 * do not currently need to store anything in that guest-allocated memory
6529 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6530 * argument is different from the VMXON pointer (which the spec says they do).
6531 */
6532static int handle_vmon(struct kvm_vcpu *vcpu)
6533{
6534 struct kvm_segment cs;
6535 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6536 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6537 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6538 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6539
6540 /* The Intel VMX Instruction Reference lists a bunch of bits that
6541 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6542 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6543 * Otherwise, we should fail with #UD. We test these now:
6544 */
6545 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6546 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6547 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6548 kvm_queue_exception(vcpu, UD_VECTOR);
6549 return 1;
6550 }
6551
6552 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6553 if (is_long_mode(vcpu) && !cs.l) {
6554 kvm_queue_exception(vcpu, UD_VECTOR);
6555 return 1;
6556 }
6557
6558 if (vmx_get_cpl(vcpu)) {
6559 kvm_inject_gp(vcpu, 0);
6560 return 1;
6561 }
3573e22c 6562
4291b588 6563 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6564 return 1;
6565
145c28dd
AG		 6566 if (vmx->nested.vmxon) {
6567 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6568 skip_emulated_instruction(vcpu);
6569 return 1;
6570 }
b3897a49
NHE		 6571
6572 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6573 != VMXON_NEEDED_FEATURES) {
6574 kvm_inject_gp(vcpu, 0);
6575 return 1;
6576 }
6577
8de48833
AG		 6578 if (enable_shadow_vmcs) {
6579 shadow_vmcs = alloc_vmcs();
6580 if (!shadow_vmcs)
6581 return -ENOMEM;
6582 /* mark vmcs as shadow */
6583 shadow_vmcs->revision_id |= (1u << 31);
6584 /* init shadow vmcs */
6585 vmcs_clear(shadow_vmcs);
6586 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6587 }
ec378aee 6588
ff2f6fe9
NHE		 6589 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6590 vmx->nested.vmcs02_num = 0;
6591
f4124500
JK		 6592 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6593 HRTIMER_MODE_REL);
6594 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6595
ec378aee
NHE		 6596 vmx->nested.vmxon = true;
6597
6598 skip_emulated_instruction(vcpu);
a25eb114 6599 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6600 return 1;
6601}
6602
6603/*
6604 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6605 * for running VMX instructions (except VMXON, whose prerequisites are
6606 * slightly different). It also specifies what exception to inject otherwise.
6607 */
6608static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6609{
6610 struct kvm_segment cs;
6611 struct vcpu_vmx *vmx = to_vmx(vcpu);
6612
6613 if (!vmx->nested.vmxon) {
6614 kvm_queue_exception(vcpu, UD_VECTOR);
6615 return 0;
6616 }
6617
6618 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6619 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6620 (is_long_mode(vcpu) && !cs.l)) {
6621 kvm_queue_exception(vcpu, UD_VECTOR);
6622 return 0;
6623 }
6624
6625 if (vmx_get_cpl(vcpu)) {
6626 kvm_inject_gp(vcpu, 0);
6627 return 0;
6628 }
6629
6630 return 1;
6631}
6632
e7953d7f
AG		 6633static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6634{
8a1b9dd0 6635 u32 exec_control;
9a2a05b9
PB		 6636 if (vmx->nested.current_vmptr == -1ull)
6637 return;
6638
6639 /* current_vmptr and current_vmcs12 are always set/reset together */
6640 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6641 return;
6642
012f83cb 6643 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6644 /* copy to memory all shadowed fields in case
6645 they were modified */
6646 copy_shadow_to_vmcs12(vmx);
6647 vmx->nested.sync_shadow_vmcs = false;
6648 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6649 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6650 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6651 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6652 }
705699a1 6653 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6654 kunmap(vmx->nested.current_vmcs12_page);
6655 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6656 vmx->nested.current_vmptr = -1ull;
6657 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6658}
6659
ec378aee
NHE		 6660/*
6661 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6662 * just stops using VMX.
6663 */
6664static void free_nested(struct vcpu_vmx *vmx)
6665{
6666 if (!vmx->nested.vmxon)
6667 return;
9a2a05b9 6668
ec378aee 6669 vmx->nested.vmxon = false;
9a2a05b9 6670 nested_release_vmcs12(vmx);
e7953d7f
AG		 6671 if (enable_shadow_vmcs)
6672 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6673 /* Unpin physical memory we referred to in current vmcs02 */
6674 if (vmx->nested.apic_access_page) {
6675 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6676 vmx->nested.apic_access_page = NULL;
fe3ef05c 6677 }
a7c0b07d
WL		 6678 if (vmx->nested.virtual_apic_page) {
6679 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6680 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6681 }
705699a1
WV		 6682 if (vmx->nested.pi_desc_page) {
6683 kunmap(vmx->nested.pi_desc_page);
6684 nested_release_page(vmx->nested.pi_desc_page);
6685 vmx->nested.pi_desc_page = NULL;
6686 vmx->nested.pi_desc = NULL;
6687 }
ff2f6fe9
NHE		 6688
6689 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6690}
6691
6692/* Emulate the VMXOFF instruction */
6693static int handle_vmoff(struct kvm_vcpu *vcpu)
6694{
6695 if (!nested_vmx_check_permission(vcpu))
6696 return 1;
6697 free_nested(to_vmx(vcpu));
6698 skip_emulated_instruction(vcpu);
a25eb114 6699 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6700 return 1;
6701}
6702
27d6c865
NHE		 6703/* Emulate the VMCLEAR instruction */
6704static int handle_vmclear(struct kvm_vcpu *vcpu)
6705{
6706 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6707 gpa_t vmptr;
6708 struct vmcs12 *vmcs12;
6709 struct page *page;
27d6c865
NHE		 6710
6711 if (!nested_vmx_check_permission(vcpu))
6712 return 1;
6713
4291b588 6714 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6715 return 1;
27d6c865 6716
9a2a05b9 6717 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6718 nested_release_vmcs12(vmx);
27d6c865
NHE		 6719
6720 page = nested_get_page(vcpu, vmptr);
6721 if (page == NULL) {
6722 /*
6723 * For accurate processor emulation, VMCLEAR beyond available
6724 * physical memory should do nothing at all. However, it is
6725 * possible that a nested vmx bug, not a guest hypervisor bug,
6726 * resulted in this case, so let's shut down before doing any
6727 * more damage:
6728 */
6729 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6730 return 1;
6731 }
6732 vmcs12 = kmap(page);
6733 vmcs12->launch_state = 0;
6734 kunmap(page);
6735 nested_release_page(page);
6736
6737 nested_free_vmcs02(vmx, vmptr);
6738
6739 skip_emulated_instruction(vcpu);
6740 nested_vmx_succeed(vcpu);
6741 return 1;
6742}
6743
cd232ad0
NHE		 6744static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6745
6746/* Emulate the VMLAUNCH instruction */
6747static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6748{
6749 return nested_vmx_run(vcpu, true);
6750}
6751
6752/* Emulate the VMRESUME instruction */
6753static int handle_vmresume(struct kvm_vcpu *vcpu)
6754{
6755
6756 return nested_vmx_run(vcpu, false);
6757}
6758
49f705c5
NHE		 6759enum vmcs_field_type {
6760 VMCS_FIELD_TYPE_U16 = 0,
6761 VMCS_FIELD_TYPE_U64 = 1,
6762 VMCS_FIELD_TYPE_U32 = 2,
6763 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6764};
6765
6766static inline int vmcs_field_type(unsigned long field)
6767{
6768 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6769 return VMCS_FIELD_TYPE_U32;
6770 return (field >> 13) & 0x3 ;
6771}
6772
6773static inline int vmcs_field_readonly(unsigned long field)
6774{
6775 return (((field >> 10) & 0x3) == 1);
6776}
6777
6778/*
6779 * Read a vmcs12 field. Since these can have varying lengths and we return
6780 * one type, we chose the biggest type (u64) and zero-extend the return value
6781 * to that size. Note that the caller, handle_vmread, might need to use only
6782 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6783 * 64-bit fields are to be returned).
6784 */
a2ae9df7
PB		 6785static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6786 unsigned long field, u64 *ret)
49f705c5
NHE		 6787{
6788 short offset = vmcs_field_to_offset(field);
6789 char *p;
6790
6791 if (offset < 0)
a2ae9df7 6792 return offset;
49f705c5
NHE		 6793
6794 p = ((char *)(get_vmcs12(vcpu))) + offset;
6795
6796 switch (vmcs_field_type(field)) {
6797 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6798 *ret = *((natural_width *)p);
a2ae9df7 6799 return 0;
49f705c5
NHE		 6800 case VMCS_FIELD_TYPE_U16:
6801 *ret = *((u16 *)p);
a2ae9df7 6802 return 0;
49f705c5
NHE		 6803 case VMCS_FIELD_TYPE_U32:
6804 *ret = *((u32 *)p);
a2ae9df7 6805 return 0;
49f705c5
NHE		 6806 case VMCS_FIELD_TYPE_U64:
6807 *ret = *((u64 *)p);
a2ae9df7 6808 return 0;
49f705c5 6809 default:
a2ae9df7
PB		 6810 WARN_ON(1);
6811 return -ENOENT;
49f705c5
NHE		 6812 }
6813}
6814
20b97fea 6815
a2ae9df7
PB		 6816static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6817 unsigned long field, u64 field_value){
20b97fea
AG		 6818 short offset = vmcs_field_to_offset(field);
6819 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6820 if (offset < 0)
a2ae9df7 6821 return offset;
20b97fea
AG		 6822
6823 switch (vmcs_field_type(field)) {
6824 case VMCS_FIELD_TYPE_U16:
6825 *(u16 *)p = field_value;
a2ae9df7 6826 return 0;
20b97fea
AG		 6827 case VMCS_FIELD_TYPE_U32:
6828 *(u32 *)p = field_value;
a2ae9df7 6829 return 0;
20b97fea
AG		 6830 case VMCS_FIELD_TYPE_U64:
6831 *(u64 *)p = field_value;
a2ae9df7 6832 return 0;
20b97fea
AG		 6833 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6834 *(natural_width *)p = field_value;
a2ae9df7 6835 return 0;
20b97fea 6836 default:
a2ae9df7
PB		 6837 WARN_ON(1);
6838 return -ENOENT;
20b97fea
AG		 6839 }
6840
6841}
6842
16f5b903
AG		 6843static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6844{
6845 int i;
6846 unsigned long field;
6847 u64 field_value;
6848 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6849 const unsigned long *fields = shadow_read_write_fields;
6850 const int num_fields = max_shadow_read_write_fields;
16f5b903 6851
282da870
JK		 6852 preempt_disable();
6853
16f5b903
AG		 6854 vmcs_load(shadow_vmcs);
6855
6856 for (i = 0; i < num_fields; i++) {
6857 field = fields[i];
6858 switch (vmcs_field_type(field)) {
6859 case VMCS_FIELD_TYPE_U16:
6860 field_value = vmcs_read16(field);
6861 break;
6862 case VMCS_FIELD_TYPE_U32:
6863 field_value = vmcs_read32(field);
6864 break;
6865 case VMCS_FIELD_TYPE_U64:
6866 field_value = vmcs_read64(field);
6867 break;
6868 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6869 field_value = vmcs_readl(field);
6870 break;
a2ae9df7
PB		 6871 default:
6872 WARN_ON(1);
6873 continue;
16f5b903
AG		 6874 }
6875 vmcs12_write_any(&vmx->vcpu, field, field_value);
6876 }
6877
6878 vmcs_clear(shadow_vmcs);
6879 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6880
6881 preempt_enable();
16f5b903
AG		 6882}
6883
c3114420
AG		 6884static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6885{
c2bae893
MK		 6886 const unsigned long *fields[] = {
6887 shadow_read_write_fields,
6888 shadow_read_only_fields
c3114420 6889 };
c2bae893 6890 const int max_fields[] = {
c3114420
AG		 6891 max_shadow_read_write_fields,
6892 max_shadow_read_only_fields
6893 };
6894 int i, q;
6895 unsigned long field;
6896 u64 field_value = 0;
6897 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6898
6899 vmcs_load(shadow_vmcs);
6900
c2bae893 6901 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6902 for (i = 0; i < max_fields[q]; i++) {
6903 field = fields[q][i];
6904 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6905
6906 switch (vmcs_field_type(field)) {
6907 case VMCS_FIELD_TYPE_U16:
6908 vmcs_write16(field, (u16)field_value);
6909 break;
6910 case VMCS_FIELD_TYPE_U32:
6911 vmcs_write32(field, (u32)field_value);
6912 break;
6913 case VMCS_FIELD_TYPE_U64:
6914 vmcs_write64(field, (u64)field_value);
6915 break;
6916 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6917 vmcs_writel(field, (long)field_value);
6918 break;
a2ae9df7
PB		 6919 default:
6920 WARN_ON(1);
6921 break;
c3114420
AG		 6922 }
6923 }
6924 }
6925
6926 vmcs_clear(shadow_vmcs);
6927 vmcs_load(vmx->loaded_vmcs->vmcs);
6928}
6929
49f705c5
NHE		 6930/*
6931 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6932 * used before) all generate the same failure when it is missing.
6933 */
6934static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6935{
6936 struct vcpu_vmx *vmx = to_vmx(vcpu);
6937 if (vmx->nested.current_vmptr == -1ull) {
6938 nested_vmx_failInvalid(vcpu);
6939 skip_emulated_instruction(vcpu);
6940 return 0;
6941 }
6942 return 1;
6943}
6944
6945static int handle_vmread(struct kvm_vcpu *vcpu)
6946{
6947 unsigned long field;
6948 u64 field_value;
6949 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6950 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6951 gva_t gva = 0;
6952
6953 if (!nested_vmx_check_permission(vcpu) ||
6954 !nested_vmx_check_vmcs12(vcpu))
6955 return 1;
6956
6957 /* Decode instruction info and find the field to read */
27e6fb5d 6958 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6959 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6960 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6961 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6962 skip_emulated_instruction(vcpu);
6963 return 1;
6964 }
6965 /*
6966 * Now copy part of this value to register or memory, as requested.
6967 * Note that the number of bits actually copied is 32 or 64 depending
6968 * on the guest's mode (32 or 64 bit), not on the given field's length.
6969 */
6970 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6971 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6972 field_value);
6973 } else {
6974 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 6975 vmx_instruction_info, true, &gva))
49f705c5
NHE		 6976 return 1;
6977 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6978 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6979 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6980 }
6981
6982 nested_vmx_succeed(vcpu);
6983 skip_emulated_instruction(vcpu);
6984 return 1;
6985}
6986
6987
6988static int handle_vmwrite(struct kvm_vcpu *vcpu)
6989{
6990 unsigned long field;
6991 gva_t gva;
6992 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6993 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6994 /* The value to write might be 32 or 64 bits, depending on L1's long
6995 * mode, and eventually we need to write that into a field of several
6996 * possible lengths. The code below first zero-extends the value to 64
6997 * bit (field_value), and then copies only the approriate number of
6998 * bits into the vmcs12 field.
6999 */
7000 u64 field_value = 0;
7001 struct x86_exception e;
7002
7003 if (!nested_vmx_check_permission(vcpu) ||
7004 !nested_vmx_check_vmcs12(vcpu))
7005 return 1;
7006
7007 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7008 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7009 (((vmx_instruction_info) >> 3) & 0xf));
7010 else {
7011 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7012 vmx_instruction_info, false, &gva))
49f705c5
NHE		 7013 return 1;
7014 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7015 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7016 kvm_inject_page_fault(vcpu, &e);
7017 return 1;
7018 }
7019 }
7020
7021
27e6fb5d 7022 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7023 if (vmcs_field_readonly(field)) {
7024 nested_vmx_failValid(vcpu,
7025 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7026 skip_emulated_instruction(vcpu);
7027 return 1;
7028 }
7029
a2ae9df7 7030 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7031 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7032 skip_emulated_instruction(vcpu);
7033 return 1;
7034 }
7035
7036 nested_vmx_succeed(vcpu);
7037 skip_emulated_instruction(vcpu);
7038 return 1;
7039}
7040
63846663
NHE		 7041/* Emulate the VMPTRLD instruction */
7042static int handle_vmptrld(struct kvm_vcpu *vcpu)
7043{
7044 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7045 gpa_t vmptr;
8a1b9dd0 7046 u32 exec_control;
63846663
NHE		 7047
7048 if (!nested_vmx_check_permission(vcpu))
7049 return 1;
7050
4291b588 7051 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7052 return 1;
63846663
NHE		 7053
7054 if (vmx->nested.current_vmptr != vmptr) {
7055 struct vmcs12 *new_vmcs12;
7056 struct page *page;
7057 page = nested_get_page(vcpu, vmptr);
7058 if (page == NULL) {
7059 nested_vmx_failInvalid(vcpu);
7060 skip_emulated_instruction(vcpu);
7061 return 1;
7062 }
7063 new_vmcs12 = kmap(page);
7064 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7065 kunmap(page);
7066 nested_release_page_clean(page);
7067 nested_vmx_failValid(vcpu,
7068 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7069 skip_emulated_instruction(vcpu);
7070 return 1;
7071 }
63846663 7072
9a2a05b9 7073 nested_release_vmcs12(vmx);
63846663
NHE		 7074 vmx->nested.current_vmptr = vmptr;
7075 vmx->nested.current_vmcs12 = new_vmcs12;
7076 vmx->nested.current_vmcs12_page = page;
012f83cb 7077 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 7078 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7079 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7080 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7081 vmcs_write64(VMCS_LINK_POINTER,
7082 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7083 vmx->nested.sync_shadow_vmcs = true;
7084 }
63846663
NHE		 7085 }
7086
7087 nested_vmx_succeed(vcpu);
7088 skip_emulated_instruction(vcpu);
7089 return 1;
7090}
7091
6a4d7550
NHE		 7092/* Emulate the VMPTRST instruction */
7093static int handle_vmptrst(struct kvm_vcpu *vcpu)
7094{
7095 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7096 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7097 gva_t vmcs_gva;
7098 struct x86_exception e;
7099
7100 if (!nested_vmx_check_permission(vcpu))
7101 return 1;
7102
7103 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7104 vmx_instruction_info, true, &vmcs_gva))
6a4d7550
NHE		 7105 return 1;
7106 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7107 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7108 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7109 sizeof(u64), &e)) {
7110 kvm_inject_page_fault(vcpu, &e);
7111 return 1;
7112 }
7113 nested_vmx_succeed(vcpu);
7114 skip_emulated_instruction(vcpu);
7115 return 1;
7116}
7117
bfd0a56b
NHE		 7118/* Emulate the INVEPT instruction */
7119static int handle_invept(struct kvm_vcpu *vcpu)
7120{
b9c237bb 7121 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7122 u32 vmx_instruction_info, types;
7123 unsigned long type;
7124 gva_t gva;
7125 struct x86_exception e;
7126 struct {
7127 u64 eptp, gpa;
7128 } operand;
bfd0a56b 7129
b9c237bb
WV		 7130 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7131 SECONDARY_EXEC_ENABLE_EPT) ||
7132 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7133 kvm_queue_exception(vcpu, UD_VECTOR);
7134 return 1;
7135 }
7136
7137 if (!nested_vmx_check_permission(vcpu))
7138 return 1;
7139
7140 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7141 kvm_queue_exception(vcpu, UD_VECTOR);
7142 return 1;
7143 }
7144
7145 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7146 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7147
b9c237bb 7148 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7149
7150 if (!(types & (1UL << type))) {
7151 nested_vmx_failValid(vcpu,
7152 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7153 return 1;
7154 }
7155
7156 /* According to the Intel VMX instruction reference, the memory
7157 * operand is read even if it isn't needed (e.g., for type==global)
7158 */
7159 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7160 vmx_instruction_info, false, &gva))
bfd0a56b
NHE		 7161 return 1;
7162 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7163 sizeof(operand), &e)) {
7164 kvm_inject_page_fault(vcpu, &e);
7165 return 1;
7166 }
7167
7168 switch (type) {
bfd0a56b
NHE		 7169 case VMX_EPT_EXTENT_GLOBAL:
7170 kvm_mmu_sync_roots(vcpu);
77c3913b 7171 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7172 nested_vmx_succeed(vcpu);
7173 break;
7174 default:
4b855078 7175 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7176 BUG_ON(1);
7177 break;
7178 }
7179
7180 skip_emulated_instruction(vcpu);
7181 return 1;
7182}
7183
a642fc30
PM		 7184static int handle_invvpid(struct kvm_vcpu *vcpu)
7185{
7186 kvm_queue_exception(vcpu, UD_VECTOR);
7187 return 1;
7188}
7189
843e4330
KH		 7190static int handle_pml_full(struct kvm_vcpu *vcpu)
7191{
7192 unsigned long exit_qualification;
7193
7194 trace_kvm_pml_full(vcpu->vcpu_id);
7195
7196 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7197
7198 /*
7199 * PML buffer FULL happened while executing iret from NMI,
7200 * "blocked by NMI" bit has to be set before next VM entry.
7201 */
7202 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7203 cpu_has_virtual_nmis() &&
7204 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7205 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7206 GUEST_INTR_STATE_NMI);
7207
7208 /*
7209 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7210 * here.., and there's no userspace involvement needed for PML.
7211 */
7212 return 1;
7213}
7214
6aa8b732
AK		 7215/*
7216 * The exit handlers return 1 if the exit was handled fully and guest execution
7217 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7218 * to be done to userspace and return 0.
7219 */
772e0318 7220static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7221 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7222 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7223 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7224 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7225 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7226 [EXIT_REASON_CR_ACCESS] = handle_cr,
7227 [EXIT_REASON_DR_ACCESS] = handle_dr,
7228 [EXIT_REASON_CPUID] = handle_cpuid,
7229 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7230 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7231 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7232 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7233 [EXIT_REASON_INVD] = handle_invd,
a7052897 7234 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7235 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7236 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7237 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7238 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7239 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7240 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7241 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7242 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7243 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7244 [EXIT_REASON_VMOFF] = handle_vmoff,
7245 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7246 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7247 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7248 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7249 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7250 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7251 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7252 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7253 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7254 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7255 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7256 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7257 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7258 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7259 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7260 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7261 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7262 [EXIT_REASON_XSAVES] = handle_xsaves,
7263 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7264 [EXIT_REASON_PML_FULL] = handle_pml_full,
6aa8b732
AK		 7265};
7266
7267static const int kvm_vmx_max_exit_handlers =
50a3485c 7268 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7269
908a7bdd
JK		 7270static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7271 struct vmcs12 *vmcs12)
7272{
7273 unsigned long exit_qualification;
7274 gpa_t bitmap, last_bitmap;
7275 unsigned int port;
7276 int size;
7277 u8 b;
7278
908a7bdd 7279 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7280 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7281
7282 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7283
7284 port = exit_qualification >> 16;
7285 size = (exit_qualification & 7) + 1;
7286
7287 last_bitmap = (gpa_t)-1;
7288 b = -1;
7289
7290 while (size > 0) {
7291 if (port < 0x8000)
7292 bitmap = vmcs12->io_bitmap_a;
7293 else if (port < 0x10000)
7294 bitmap = vmcs12->io_bitmap_b;
7295 else
1d804d07 7296 return true;
908a7bdd
JK		 7297 bitmap += (port & 0x7fff) / 8;
7298
7299 if (last_bitmap != bitmap)
54bf36aa 7300 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7301 return true;
908a7bdd 7302 if (b & (1 << (port & 7)))
1d804d07 7303 return true;
908a7bdd
JK		 7304
7305 port++;
7306 size--;
7307 last_bitmap = bitmap;
7308 }
7309
1d804d07 7310 return false;
908a7bdd
JK		 7311}
7312
644d711a
NHE		 7313/*
7314 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7315 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7316 * disinterest in the current event (read or write a specific MSR) by using an
7317 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7318 */
7319static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7320 struct vmcs12 *vmcs12, u32 exit_reason)
7321{
7322 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7323 gpa_t bitmap;
7324
cbd29cb6 7325 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7326 return true;
644d711a
NHE		 7327
7328 /*
7329 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7330 * for the four combinations of read/write and low/high MSR numbers.
7331 * First we need to figure out which of the four to use:
7332 */
7333 bitmap = vmcs12->msr_bitmap;
7334 if (exit_reason == EXIT_REASON_MSR_WRITE)
7335 bitmap += 2048;
7336 if (msr_index >= 0xc0000000) {
7337 msr_index -= 0xc0000000;
7338 bitmap += 1024;
7339 }
7340
7341 /* Then read the msr_index'th bit from this bitmap: */
7342 if (msr_index < 1024*8) {
7343 unsigned char b;
54bf36aa 7344 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7345 return true;
644d711a
NHE		 7346 return 1 & (b >> (msr_index & 7));
7347 } else
1d804d07 7348 return true; /* let L1 handle the wrong parameter */
644d711a
NHE		 7349}
7350
7351/*
7352 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7353 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7354 * intercept (via guest_host_mask etc.) the current event.
7355 */
7356static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7357 struct vmcs12 *vmcs12)
7358{
7359 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7360 int cr = exit_qualification & 15;
7361 int reg = (exit_qualification >> 8) & 15;
1e32c079 7362 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7363
7364 switch ((exit_qualification >> 4) & 3) {
7365 case 0: /* mov to cr */
7366 switch (cr) {
7367 case 0:
7368 if (vmcs12->cr0_guest_host_mask &
7369 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7370 return true;
644d711a
NHE		 7371 break;
7372 case 3:
7373 if ((vmcs12->cr3_target_count >= 1 &&
7374 vmcs12->cr3_target_value0 == val) ||
7375 (vmcs12->cr3_target_count >= 2 &&
7376 vmcs12->cr3_target_value1 == val) ||
7377 (vmcs12->cr3_target_count >= 3 &&
7378 vmcs12->cr3_target_value2 == val) ||
7379 (vmcs12->cr3_target_count >= 4 &&
7380 vmcs12->cr3_target_value3 == val))
1d804d07 7381 return false;
644d711a 7382 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7383 return true;
644d711a
NHE		 7384 break;
7385 case 4:
7386 if (vmcs12->cr4_guest_host_mask &
7387 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7388 return true;
644d711a
NHE		 7389 break;
7390 case 8:
7391 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7392 return true;
644d711a
NHE		 7393 break;
7394 }
7395 break;
7396 case 2: /* clts */
7397 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7398 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7399 return true;
644d711a
NHE		 7400 break;
7401 case 1: /* mov from cr */
7402 switch (cr) {
7403 case 3:
7404 if (vmcs12->cpu_based_vm_exec_control &
7405 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7406 return true;
644d711a
NHE		 7407 break;
7408 case 8:
7409 if (vmcs12->cpu_based_vm_exec_control &
7410 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7411 return true;
644d711a
NHE		 7412 break;
7413 }
7414 break;
7415 case 3: /* lmsw */
7416 /*
7417 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7418 * cr0. Other attempted changes are ignored, with no exit.
7419 */
7420 if (vmcs12->cr0_guest_host_mask & 0xe &
7421 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7422 return true;
644d711a
NHE		 7423 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7424 !(vmcs12->cr0_read_shadow & 0x1) &&
7425 (val & 0x1))
1d804d07 7426 return true;
644d711a
NHE		 7427 break;
7428 }
1d804d07 7429 return false;
644d711a
NHE		 7430}
7431
7432/*
7433 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7434 * should handle it ourselves in L0 (and then continue L2). Only call this
7435 * when in is_guest_mode (L2).
7436 */
7437static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7438{
644d711a
NHE		 7439 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7440 struct vcpu_vmx *vmx = to_vmx(vcpu);
7441 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7442 u32 exit_reason = vmx->exit_reason;
644d711a 7443
542060ea
JK		 7444 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7445 vmcs_readl(EXIT_QUALIFICATION),
7446 vmx->idt_vectoring_info,
7447 intr_info,
7448 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7449 KVM_ISA_VMX);
7450
644d711a 7451 if (vmx->nested.nested_run_pending)
1d804d07 7452 return false;
644d711a
NHE		 7453
7454 if (unlikely(vmx->fail)) {
bd80158a
JK		 7455 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7456 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7457 return true;
644d711a
NHE		 7458 }
7459
7460 switch (exit_reason) {
7461 case EXIT_REASON_EXCEPTION_NMI:
7462 if (!is_exception(intr_info))
1d804d07 7463 return false;
644d711a
NHE		 7464 else if (is_page_fault(intr_info))
7465 return enable_ept;
e504c909 7466 else if (is_no_device(intr_info) &&
ccf9844e 7467 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 7468 return false;
644d711a
NHE		 7469 return vmcs12->exception_bitmap &
7470 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7471 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 7472 return false;
644d711a 7473 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 7474 return true;
644d711a 7475 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7476 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7477 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7478 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 7479 case EXIT_REASON_TASK_SWITCH:
1d804d07 7480 return true;
644d711a 7481 case EXIT_REASON_CPUID:
bc613494 7482 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
1d804d07
JP		 7483 return false;
7484 return true;
644d711a
NHE		 7485 case EXIT_REASON_HLT:
7486 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7487 case EXIT_REASON_INVD:
1d804d07 7488 return true;
644d711a
NHE		 7489 case EXIT_REASON_INVLPG:
7490 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7491 case EXIT_REASON_RDPMC:
7492 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
b3a2a907 7493 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE		 7494 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7495 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7496 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7497 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7498 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7499 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7500 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7501 /*
7502 * VMX instructions trap unconditionally. This allows L1 to
7503 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7504 */
1d804d07 7505 return true;
644d711a
NHE		 7506 case EXIT_REASON_CR_ACCESS:
7507 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7508 case EXIT_REASON_DR_ACCESS:
7509 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7510 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7511 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7512 case EXIT_REASON_MSR_READ:
7513 case EXIT_REASON_MSR_WRITE:
7514 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7515 case EXIT_REASON_INVALID_STATE:
1d804d07 7516 return true;
644d711a
NHE		 7517 case EXIT_REASON_MWAIT_INSTRUCTION:
7518 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD		 7519 case EXIT_REASON_MONITOR_TRAP_FLAG:
7520 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE		 7521 case EXIT_REASON_MONITOR_INSTRUCTION:
7522 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7523 case EXIT_REASON_PAUSE_INSTRUCTION:
7524 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7525 nested_cpu_has2(vmcs12,
7526 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7527 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 7528 return false;
644d711a 7529 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7530 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7531 case EXIT_REASON_APIC_ACCESS:
7532 return nested_cpu_has2(vmcs12,
7533 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7534 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7535 case EXIT_REASON_EOI_INDUCED:
7536 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 7537 return true;
644d711a 7538 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7539 /*
7540 * L0 always deals with the EPT violation. If nested EPT is
7541 * used, and the nested mmu code discovers that the address is
7542 * missing in the guest EPT table (EPT12), the EPT violation
7543 * will be injected with nested_ept_inject_page_fault()
7544 */
1d804d07 7545 return false;
644d711a 7546 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7547 /*
7548 * L2 never uses directly L1's EPT, but rather L0's own EPT
7549 * table (shadow on EPT) or a merged EPT table that L0 built
7550 * (EPT on EPT). So any problems with the structure of the
7551 * table is L0's fault.
7552 */
1d804d07 7553 return false;
644d711a
NHE		 7554 case EXIT_REASON_WBINVD:
7555 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7556 case EXIT_REASON_XSETBV:
1d804d07 7557 return true;
81dc01f7
WL		 7558 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7559 /*
7560 * This should never happen, since it is not possible to
7561 * set XSS to a non-zero value---neither in L1 nor in L2.
7562 * If if it were, XSS would have to be checked against
7563 * the XSS exit bitmap in vmcs12.
7564 */
7565 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
644d711a 7566 default:
1d804d07 7567 return true;
644d711a
NHE		 7568 }
7569}
7570
586f9607
AK		 7571static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7572{
7573 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7574 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7575}
7576
843e4330
KH		 7577static int vmx_enable_pml(struct vcpu_vmx *vmx)
7578{
7579 struct page *pml_pg;
7580 u32 exec_control;
7581
7582 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7583 if (!pml_pg)
7584 return -ENOMEM;
7585
7586 vmx->pml_pg = pml_pg;
7587
7588 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7589 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7590
7591 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7592 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7593 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7594
7595 return 0;
7596}
7597
7598static void vmx_disable_pml(struct vcpu_vmx *vmx)
7599{
7600 u32 exec_control;
7601
7602 ASSERT(vmx->pml_pg);
7603 __free_page(vmx->pml_pg);
7604 vmx->pml_pg = NULL;
7605
7606 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7607 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7608 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7609}
7610
54bf36aa 7611static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 7612{
54bf36aa 7613 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH		 7614 u64 *pml_buf;
7615 u16 pml_idx;
7616
7617 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7618
7619 /* Do nothing if PML buffer is empty */
7620 if (pml_idx == (PML_ENTITY_NUM - 1))
7621 return;
7622
7623 /* PML index always points to next available PML buffer entity */
7624 if (pml_idx >= PML_ENTITY_NUM)
7625 pml_idx = 0;
7626 else
7627 pml_idx++;
7628
7629 pml_buf = page_address(vmx->pml_pg);
7630 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7631 u64 gpa;
7632
7633 gpa = pml_buf[pml_idx];
7634 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 7635 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH		 7636 }
7637
7638 /* reset PML index */
7639 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7640}
7641
7642/*
7643 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7644 * Called before reporting dirty_bitmap to userspace.
7645 */
7646static void kvm_flush_pml_buffers(struct kvm *kvm)
7647{
7648 int i;
7649 struct kvm_vcpu *vcpu;
7650 /*
7651 * We only need to kick vcpu out of guest mode here, as PML buffer
7652 * is flushed at beginning of all VMEXITs, and it's obvious that only
7653 * vcpus running in guest are possible to have unflushed GPAs in PML
7654 * buffer.
7655 */
7656 kvm_for_each_vcpu(i, vcpu, kvm)
7657 kvm_vcpu_kick(vcpu);
7658}
7659
4eb64dce
PB		 7660static void vmx_dump_sel(char *name, uint32_t sel)
7661{
7662 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7663 name, vmcs_read32(sel),
7664 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7665 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7666 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7667}
7668
7669static void vmx_dump_dtsel(char *name, uint32_t limit)
7670{
7671 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7672 name, vmcs_read32(limit),
7673 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7674}
7675
7676static void dump_vmcs(void)
7677{
7678 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7679 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7680 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7681 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7682 u32 secondary_exec_control = 0;
7683 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7684 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7685 int i, n;
7686
7687 if (cpu_has_secondary_exec_ctrls())
7688 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7689
7690 pr_err("*** Guest State ***\n");
7691 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7692 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7693 vmcs_readl(CR0_GUEST_HOST_MASK));
7694 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7695 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7696 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7697 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7698 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7699 {
7700 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7701 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7702 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7703 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7704 }
7705 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7706 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7707 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7708 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7709 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7710 vmcs_readl(GUEST_SYSENTER_ESP),
7711 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7712 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7713 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7714 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7715 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7716 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7717 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7718 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7719 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7720 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7721 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7722 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7723 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7724 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7725 efer, vmcs_readl(GUEST_IA32_PAT));
7726 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7727 vmcs_readl(GUEST_IA32_DEBUGCTL),
7728 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7729 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7730 pr_err("PerfGlobCtl = 0x%016lx\n",
7731 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7732 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7733 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7734 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7735 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7736 vmcs_read32(GUEST_ACTIVITY_STATE));
7737 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7738 pr_err("InterruptStatus = %04x\n",
7739 vmcs_read16(GUEST_INTR_STATUS));
7740
7741 pr_err("*** Host State ***\n");
7742 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7743 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7744 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7745 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7746 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7747 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7748 vmcs_read16(HOST_TR_SELECTOR));
7749 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7750 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7751 vmcs_readl(HOST_TR_BASE));
7752 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7753 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7754 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7755 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7756 vmcs_readl(HOST_CR4));
7757 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7758 vmcs_readl(HOST_IA32_SYSENTER_ESP),
7759 vmcs_read32(HOST_IA32_SYSENTER_CS),
7760 vmcs_readl(HOST_IA32_SYSENTER_EIP));
7761 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7762 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7763 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7764 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7765 pr_err("PerfGlobCtl = 0x%016lx\n",
7766 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7767
7768 pr_err("*** Control State ***\n");
7769 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7770 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7771 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7772 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7773 vmcs_read32(EXCEPTION_BITMAP),
7774 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7775 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7776 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7777 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7778 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
7779 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
7780 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7781 vmcs_read32(VM_EXIT_INTR_INFO),
7782 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7783 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
7784 pr_err(" reason=%08x qualification=%016lx\n",
7785 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
7786 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7787 vmcs_read32(IDT_VECTORING_INFO_FIELD),
7788 vmcs_read32(IDT_VECTORING_ERROR_CODE));
7789 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
7790 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
7791 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
7792 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
7793 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
7794 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
7795 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
7796 n = vmcs_read32(CR3_TARGET_COUNT);
7797 for (i = 0; i + 1 < n; i += 4)
7798 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
7799 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
7800 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
7801 if (i < n)
7802 pr_err("CR3 target%u=%016lx\n",
7803 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
7804 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
7805 pr_err("PLE Gap=%08x Window=%08x\n",
7806 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
7807 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
7808 pr_err("Virtual processor ID = 0x%04x\n",
7809 vmcs_read16(VIRTUAL_PROCESSOR_ID));
7810}
7811
6aa8b732
AK		 7812/*
7813 * The guest has exited. See if we can fix it or if we need userspace
7814 * assistance.
7815 */
851ba692 7816static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7817{
29bd8a78 7818 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7819 u32 exit_reason = vmx->exit_reason;
1155f76a 7820 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7821
843e4330
KH		 7822 /*
7823 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7824 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7825 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7826 * mode as if vcpus is in root mode, the PML buffer must has been
7827 * flushed already.
7828 */
7829 if (enable_pml)
54bf36aa 7830 vmx_flush_pml_buffer(vcpu);
843e4330 7831
80ced186 7832 /* If guest state is invalid, start emulating */
14168786 7833 if (vmx->emulation_required)
80ced186 7834 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7835
644d711a 7836 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7837 nested_vmx_vmexit(vcpu, exit_reason,
7838 vmcs_read32(VM_EXIT_INTR_INFO),
7839 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7840 return 1;
7841 }
7842
5120702e 7843 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 7844 dump_vmcs();
5120702e
MG		 7845 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7846 vcpu->run->fail_entry.hardware_entry_failure_reason
7847 = exit_reason;
7848 return 0;
7849 }
7850
29bd8a78 7851 if (unlikely(vmx->fail)) {
851ba692
AK		 7852 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7853 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7854 = vmcs_read32(VM_INSTRUCTION_ERROR);
7855 return 0;
7856 }
6aa8b732 7857
b9bf6882
XG		 7858 /*
7859 * Note:
7860 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7861 * delivery event since it indicates guest is accessing MMIO.
7862 * The vm-exit can be triggered again after return to guest that
7863 * will cause infinite loop.
7864 */
d77c26fc 7865 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7866 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7867 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7868 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7869 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7870 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7871 vcpu->run->internal.ndata = 2;
7872 vcpu->run->internal.data[0] = vectoring_info;
7873 vcpu->run->internal.data[1] = exit_reason;
7874 return 0;
7875 }
3b86cd99 7876
644d711a
NHE		 7877 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7878 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7879 get_vmcs12(vcpu))))) {
c4282df9 7880 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7881 vmx->soft_vnmi_blocked = 0;
3b86cd99 7882 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7883 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7884 /*
7885 * This CPU don't support us in finding the end of an
7886 * NMI-blocked window if the guest runs with IRQs
7887 * disabled. So we pull the trigger after 1 s of
7888 * futile waiting, but inform the user about this.
7889 */
7890 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7891 "state on VCPU %d after 1 s timeout\n",
7892 __func__, vcpu->vcpu_id);
7893 vmx->soft_vnmi_blocked = 0;
3b86cd99 7894 }
3b86cd99
JK		 7895 }
7896
6aa8b732
AK		 7897 if (exit_reason < kvm_vmx_max_exit_handlers
7898 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7899 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7900 else {
2bc19dc3
MT		 7901 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7902 kvm_queue_exception(vcpu, UD_VECTOR);
7903 return 1;
6aa8b732 7904 }
6aa8b732
AK		 7905}
7906
95ba8273 7907static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7908{
a7c0b07d
WL		 7909 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7910
7911 if (is_guest_mode(vcpu) &&
7912 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7913 return;
7914
95ba8273 7915 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7916 vmcs_write32(TPR_THRESHOLD, 0);
7917 return;
7918 }
7919
95ba8273 7920 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7921}
7922
8d14695f
YZ		 7923static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7924{
7925 u32 sec_exec_control;
7926
7927 /*
7928 * There is not point to enable virtualize x2apic without enable
7929 * apicv
7930 */
c7c9c56c 7931 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
35754c98 7932 !vmx_cpu_uses_apicv(vcpu))
8d14695f
YZ		 7933 return;
7934
35754c98 7935 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ		 7936 return;
7937
7938 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7939
7940 if (set) {
7941 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7942 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7943 } else {
7944 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7945 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7946 }
7947 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7948
7949 vmx_set_msr_bitmap(vcpu);
7950}
7951
38b99173
TC		 7952static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7953{
7954 struct vcpu_vmx *vmx = to_vmx(vcpu);
7955
7956 /*
7957 * Currently we do not handle the nested case where L2 has an
7958 * APIC access page of its own; that page is still pinned.
7959 * Hence, we skip the case where the VCPU is in guest mode _and_
7960 * L1 prepared an APIC access page for L2.
7961 *
7962 * For the case where L1 and L2 share the same APIC access page
7963 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7964 * in the vmcs12), this function will only update either the vmcs01
7965 * or the vmcs02. If the former, the vmcs02 will be updated by
7966 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7967 * the next L2->L1 exit.
7968 */
7969 if (!is_guest_mode(vcpu) ||
7970 !nested_cpu_has2(vmx->nested.current_vmcs12,
7971 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7972 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7973}
7974
c7c9c56c
YZ		 7975static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7976{
7977 u16 status;
7978 u8 old;
7979
c7c9c56c
YZ		 7980 if (isr == -1)
7981 isr = 0;
7982
7983 status = vmcs_read16(GUEST_INTR_STATUS);
7984 old = status >> 8;
7985 if (isr != old) {
7986 status &= 0xff;
7987 status |= isr << 8;
7988 vmcs_write16(GUEST_INTR_STATUS, status);
7989 }
7990}
7991
7992static void vmx_set_rvi(int vector)
7993{
7994 u16 status;
7995 u8 old;
7996
4114c27d
WW		 7997 if (vector == -1)
7998 vector = 0;
7999
c7c9c56c
YZ		 8000 status = vmcs_read16(GUEST_INTR_STATUS);
8001 old = (u8)status & 0xff;
8002 if ((u8)vector != old) {
8003 status &= ~0xff;
8004 status |= (u8)vector;
8005 vmcs_write16(GUEST_INTR_STATUS, status);
8006 }
8007}
8008
8009static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8010{
4114c27d
WW		 8011 if (!is_guest_mode(vcpu)) {
8012 vmx_set_rvi(max_irr);
8013 return;
8014 }
8015
c7c9c56c
YZ		 8016 if (max_irr == -1)
8017 return;
8018
963fee16 8019 /*
4114c27d
WW		 8020 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8021 * handles it.
963fee16 8022 */
4114c27d 8023 if (nested_exit_on_intr(vcpu))
963fee16
WL		 8024 return;
8025
963fee16 8026 /*
4114c27d 8027 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 8028 * is run without virtual interrupt delivery.
8029 */
8030 if (!kvm_event_needs_reinjection(vcpu) &&
8031 vmx_interrupt_allowed(vcpu)) {
8032 kvm_queue_interrupt(vcpu, max_irr, false);
8033 vmx_inject_irq(vcpu);
8034 }
c7c9c56c
YZ		 8035}
8036
3bb345f3 8037static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
c7c9c56c 8038{
3bb345f3 8039 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
35754c98 8040 if (!vmx_cpu_uses_apicv(vcpu))
3d81bc7e
YZ		 8041 return;
8042
c7c9c56c
YZ		 8043 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8044 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8045 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8046 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8047}
8048
51aa01d1 8049static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8050{
00eba012
AK		 8051 u32 exit_intr_info;
8052
8053 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8054 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8055 return;
8056
c5ca8e57 8057 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8058 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 8059
8060 /* Handle machine checks before interrupts are enabled */
00eba012 8061 if (is_machine_check(exit_intr_info))
a0861c02
AK		 8062 kvm_machine_check();
8063
20f65983 8064 /* We need to handle NMIs before interrupts are enabled */
00eba012 8065 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 8066 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8067 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8068 asm("int $2");
ff9d07a0
ZY		 8069 kvm_after_handle_nmi(&vmx->vcpu);
8070 }
51aa01d1 8071}
20f65983 8072
a547c6db
YZ		 8073static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8074{
8075 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8076
8077 /*
8078 * If external interrupt exists, IF bit is set in rflags/eflags on the
8079 * interrupt stack frame, and interrupt will be enabled on a return
8080 * from interrupt handler.
8081 */
8082 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8083 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8084 unsigned int vector;
8085 unsigned long entry;
8086 gate_desc *desc;
8087 struct vcpu_vmx *vmx = to_vmx(vcpu);
8088#ifdef CONFIG_X86_64
8089 unsigned long tmp;
8090#endif
8091
8092 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8093 desc = (gate_desc *)vmx->host_idt_base + vector;
8094 entry = gate_offset(*desc);
8095 asm volatile(
8096#ifdef CONFIG_X86_64
8097 "mov %%" _ASM_SP ", %[sp]\n\t"
8098 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8099 "push $%c[ss]\n\t"
8100 "push %[sp]\n\t"
8101#endif
8102 "pushf\n\t"
8103 "orl $0x200, (%%" _ASM_SP ")\n\t"
8104 __ASM_SIZE(push) " $%c[cs]\n\t"
8105 "call *%[entry]\n\t"
8106 :
8107#ifdef CONFIG_X86_64
8108 [sp]"=&r"(tmp)
8109#endif
8110 :
8111 [entry]"r"(entry),
8112 [ss]"i"(__KERNEL_DS),
8113 [cs]"i"(__KERNEL_CS)
8114 );
8115 } else
8116 local_irq_enable();
8117}
8118
6d396b55
PB		 8119static bool vmx_has_high_real_mode_segbase(void)
8120{
8121 return enable_unrestricted_guest || emulate_invalid_guest_state;
8122}
8123
da8999d3
LJ		 8124static bool vmx_mpx_supported(void)
8125{
8126 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8127 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8128}
8129
55412b2e
WL		 8130static bool vmx_xsaves_supported(void)
8131{
8132 return vmcs_config.cpu_based_2nd_exec_ctrl &
8133 SECONDARY_EXEC_XSAVES;
8134}
8135
51aa01d1
AK		 8136static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8137{
c5ca8e57 8138 u32 exit_intr_info;
51aa01d1
AK		 8139 bool unblock_nmi;
8140 u8 vector;
8141 bool idtv_info_valid;
8142
8143 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8144
cf393f75 8145 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8146 if (vmx->nmi_known_unmasked)
8147 return;
c5ca8e57
AK		 8148 /*
8149 * Can't use vmx->exit_intr_info since we're not sure what
8150 * the exit reason is.
8151 */
8152 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8153 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8154 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8155 /*
7b4a25cb 8156 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8157 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8158 * a guest IRET fault.
7b4a25cb
GN		 8159 * SDM 3: 23.2.2 (September 2008)
8160 * Bit 12 is undefined in any of the following cases:
8161 * If the VM exit sets the valid bit in the IDT-vectoring
8162 * information field.
8163 * If the VM exit is due to a double fault.
cf393f75 8164 */
7b4a25cb
GN		 8165 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8166 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8167 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8168 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8169 else
8170 vmx->nmi_known_unmasked =
8171 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8172 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8173 } else if (unlikely(vmx->soft_vnmi_blocked))
8174 vmx->vnmi_blocked_time +=
8175 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8176}
8177
3ab66e8a 8178static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8179 u32 idt_vectoring_info,
8180 int instr_len_field,
8181 int error_code_field)
51aa01d1 8182{
51aa01d1
AK		 8183 u8 vector;
8184 int type;
8185 bool idtv_info_valid;
8186
8187 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8188
3ab66e8a
JK		 8189 vcpu->arch.nmi_injected = false;
8190 kvm_clear_exception_queue(vcpu);
8191 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8192
8193 if (!idtv_info_valid)
8194 return;
8195
3ab66e8a 8196 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8197
668f612f
AK		 8198 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8199 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8200
64a7ec06 8201 switch (type) {
37b96e98 8202 case INTR_TYPE_NMI_INTR:
3ab66e8a 8203 vcpu->arch.nmi_injected = true;
668f612f 8204 /*
7b4a25cb 8205 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8206 * Clear bit "block by NMI" before VM entry if a NMI
8207 * delivery faulted.
668f612f 8208 */
3ab66e8a 8209 vmx_set_nmi_mask(vcpu, false);
37b96e98 8210 break;
37b96e98 8211 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8212 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8213 /* fall through */
8214 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8215 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8216 u32 err = vmcs_read32(error_code_field);
851eb667 8217 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8218 } else
851eb667 8219 kvm_requeue_exception(vcpu, vector);
37b96e98 8220 break;
66fd3f7f 8221 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8222 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8223 /* fall through */
37b96e98 8224 case INTR_TYPE_EXT_INTR:
3ab66e8a 8225 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8226 break;
8227 default:
8228 break;
f7d9238f 8229 }
cf393f75
AK		 8230}
8231
83422e17
AK		 8232static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8233{
3ab66e8a 8234 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8235 VM_EXIT_INSTRUCTION_LEN,
8236 IDT_VECTORING_ERROR_CODE);
8237}
8238
b463a6f7
AK		 8239static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8240{
3ab66e8a 8241 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8242 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8243 VM_ENTRY_INSTRUCTION_LEN,
8244 VM_ENTRY_EXCEPTION_ERROR_CODE);
8245
8246 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8247}
8248
d7cd9796
GN		 8249static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8250{
8251 int i, nr_msrs;
8252 struct perf_guest_switch_msr *msrs;
8253
8254 msrs = perf_guest_get_msrs(&nr_msrs);
8255
8256 if (!msrs)
8257 return;
8258
8259 for (i = 0; i < nr_msrs; i++)
8260 if (msrs[i].host == msrs[i].guest)
8261 clear_atomic_switch_msr(vmx, msrs[i].msr);
8262 else
8263 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8264 msrs[i].host);
8265}
8266
a3b5ba49 8267static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8268{
a2fa3e9f 8269 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8270 unsigned long debugctlmsr, cr4;
104f226b
AK		 8271
8272 /* Record the guest's net vcpu time for enforced NMI injections. */
8273 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8274 vmx->entry_time = ktime_get();
8275
8276 /* Don't enter VMX if guest state is invalid, let the exit handler
8277 start emulation until we arrive back to a valid state */
14168786 8278 if (vmx->emulation_required)
104f226b
AK		 8279 return;
8280
a7653ecd
RK		 8281 if (vmx->ple_window_dirty) {
8282 vmx->ple_window_dirty = false;
8283 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8284 }
8285
012f83cb
AG		 8286 if (vmx->nested.sync_shadow_vmcs) {
8287 copy_vmcs12_to_shadow(vmx);
8288 vmx->nested.sync_shadow_vmcs = false;
8289 }
8290
104f226b
AK		 8291 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8292 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8293 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8294 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8295
1e02ce4c 8296 cr4 = cr4_read_shadow();
d974baa3
AL		 8297 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8298 vmcs_writel(HOST_CR4, cr4);
8299 vmx->host_state.vmcs_host_cr4 = cr4;
8300 }
8301
104f226b
AK		 8302 /* When single-stepping over STI and MOV SS, we must clear the
8303 * corresponding interruptibility bits in the guest state. Otherwise
8304 * vmentry fails as it then expects bit 14 (BS) in pending debug
8305 * exceptions being set, but that's not correct for the guest debugging
8306 * case. */
8307 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8308 vmx_set_interrupt_shadow(vcpu, 0);
8309
d7cd9796 8310 atomic_switch_perf_msrs(vmx);
2a7921b7 8311 debugctlmsr = get_debugctlmsr();
d7cd9796 8312
d462b819 8313 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8314 asm(
6aa8b732 8315 /* Store host registers */
b188c81f
AK		 8316 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8317 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8318 "push %%" _ASM_CX " \n\t"
8319 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8320 "je 1f \n\t"
b188c81f 8321 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8322 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8323 "1: \n\t"
d3edefc0 8324 /* Reload cr2 if changed */
b188c81f
AK		 8325 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8326 "mov %%cr2, %%" _ASM_DX " \n\t"
8327 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8328 "je 2f \n\t"
b188c81f 8329 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8330 "2: \n\t"
6aa8b732 8331 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8332 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8333 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8334 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8335 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8336 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8337 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8338 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8339 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8340#ifdef CONFIG_X86_64
e08aa78a
AK		 8341 "mov %c[r8](%0), %%r8 \n\t"
8342 "mov %c[r9](%0), %%r9 \n\t"
8343 "mov %c[r10](%0), %%r10 \n\t"
8344 "mov %c[r11](%0), %%r11 \n\t"
8345 "mov %c[r12](%0), %%r12 \n\t"
8346 "mov %c[r13](%0), %%r13 \n\t"
8347 "mov %c[r14](%0), %%r14 \n\t"
8348 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8349#endif
b188c81f 8350 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8351
6aa8b732 8352 /* Enter guest mode */
83287ea4 8353 "jne 1f \n\t"
4ecac3fd 8354 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8355 "jmp 2f \n\t"
8356 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8357 "2: "
6aa8b732 8358 /* Save guest registers, load host registers, keep flags */
b188c81f 8359 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8360 "pop %0 \n\t"
b188c81f
AK		 8361 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8362 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8363 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8364 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8365 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8366 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8367 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8368#ifdef CONFIG_X86_64
e08aa78a
AK		 8369 "mov %%r8, %c[r8](%0) \n\t"
8370 "mov %%r9, %c[r9](%0) \n\t"
8371 "mov %%r10, %c[r10](%0) \n\t"
8372 "mov %%r11, %c[r11](%0) \n\t"
8373 "mov %%r12, %c[r12](%0) \n\t"
8374 "mov %%r13, %c[r13](%0) \n\t"
8375 "mov %%r14, %c[r14](%0) \n\t"
8376 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8377#endif
b188c81f
AK		 8378 "mov %%cr2, %%" _ASM_AX " \n\t"
8379 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8380
b188c81f 8381 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8382 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8383 ".pushsection .rodata \n\t"
8384 ".global vmx_return \n\t"
8385 "vmx_return: " _ASM_PTR " 2b \n\t"
8386 ".popsection"
e08aa78a 8387 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8388 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8389 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8390 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8391 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8392 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8393 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8394 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8395 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8396 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8397 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8398#ifdef CONFIG_X86_64
ad312c7c
ZX		 8399 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8400 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8401 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8402 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8403 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8404 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8405 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8406 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8407#endif
40712fae
AK		 8408 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8409 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8410 : "cc", "memory"
8411#ifdef CONFIG_X86_64
b188c81f 8412 , "rax", "rbx", "rdi", "rsi"
c2036300 8413 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8414#else
8415 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8416#endif
8417 );
6aa8b732 8418
2a7921b7
GN		 8419 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8420 if (debugctlmsr)
8421 update_debugctlmsr(debugctlmsr);
8422
aa67f609
AK		 8423#ifndef CONFIG_X86_64
8424 /*
8425 * The sysexit path does not restore ds/es, so we must set them to
8426 * a reasonable value ourselves.
8427 *
8428 * We can't defer this to vmx_load_host_state() since that function
8429 * may be executed in interrupt context, which saves and restore segments
8430 * around it, nullifying its effect.
8431 */
8432 loadsegment(ds, __USER_DS);
8433 loadsegment(es, __USER_DS);
8434#endif
8435
6de4f3ad 8436 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8437 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8438 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8439 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8440 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8441 vcpu->arch.regs_dirty = 0;
8442
1155f76a
AK		 8443 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8444
d462b819 8445 vmx->loaded_vmcs->launched = 1;
1b6269db 8446
51aa01d1 8447 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8448 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8449
e0b890d3
GN		 8450 /*
8451 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8452 * we did not inject a still-pending event to L1 now because of
8453 * nested_run_pending, we need to re-enable this bit.
8454 */
8455 if (vmx->nested.nested_run_pending)
8456 kvm_make_request(KVM_REQ_EVENT, vcpu);
8457
8458 vmx->nested.nested_run_pending = 0;
8459
51aa01d1
AK		 8460 vmx_complete_atomic_exit(vmx);
8461 vmx_recover_nmi_blocking(vmx);
cf393f75 8462 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8463}
8464
4fa7734c
PB		 8465static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8466{
8467 struct vcpu_vmx *vmx = to_vmx(vcpu);
8468 int cpu;
8469
8470 if (vmx->loaded_vmcs == &vmx->vmcs01)
8471 return;
8472
8473 cpu = get_cpu();
8474 vmx->loaded_vmcs = &vmx->vmcs01;
8475 vmx_vcpu_put(vcpu);
8476 vmx_vcpu_load(vcpu, cpu);
8477 vcpu->cpu = cpu;
8478 put_cpu();
8479}
8480
6aa8b732
AK		 8481static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8482{
fb3f0f51
RR		 8483 struct vcpu_vmx *vmx = to_vmx(vcpu);
8484
843e4330
KH		 8485 if (enable_pml)
8486 vmx_disable_pml(vmx);
cdbecfc3 8487 free_vpid(vmx);
4fa7734c
PB		 8488 leave_guest_mode(vcpu);
8489 vmx_load_vmcs01(vcpu);
26a865f4 8490 free_nested(vmx);
4fa7734c 8491 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8492 kfree(vmx->guest_msrs);
8493 kvm_vcpu_uninit(vcpu);
a4770347 8494 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8495}
8496
fb3f0f51 8497static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8498{
fb3f0f51 8499 int err;
c16f862d 8500 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8501 int cpu;
6aa8b732 8502
a2fa3e9f 8503 if (!vmx)
fb3f0f51
RR		 8504 return ERR_PTR(-ENOMEM);
8505
2384d2b3
SY		 8506 allocate_vpid(vmx);
8507
fb3f0f51
RR		 8508 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8509 if (err)
8510 goto free_vcpu;
965b58a5 8511
a2fa3e9f 8512 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8513 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8514 > PAGE_SIZE);
0123be42 8515
be6d05cf 8516 err = -ENOMEM;
fb3f0f51 8517 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8518 goto uninit_vcpu;
8519 }
965b58a5 8520
d462b819
NHE		 8521 vmx->loaded_vmcs = &vmx->vmcs01;
8522 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8523 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8524 goto free_msrs;
d462b819
NHE		 8525 if (!vmm_exclusive)
8526 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8527 loaded_vmcs_init(vmx->loaded_vmcs);
8528 if (!vmm_exclusive)
8529 kvm_cpu_vmxoff();
a2fa3e9f 8530
15ad7146
AK		 8531 cpu = get_cpu();
8532 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8533 vmx->vcpu.cpu = cpu;
8b9cf98c 8534 err = vmx_vcpu_setup(vmx);
fb3f0f51 8535 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8536 put_cpu();
fb3f0f51
RR		 8537 if (err)
8538 goto free_vmcs;
35754c98 8539 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK		 8540 err = alloc_apic_access_page(kvm);
8541 if (err)
5e4a0b3c 8542 goto free_vmcs;
a63cb560 8543 }
fb3f0f51 8544
b927a3ce
SY		 8545 if (enable_ept) {
8546 if (!kvm->arch.ept_identity_map_addr)
8547 kvm->arch.ept_identity_map_addr =
8548 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8549 err = init_rmode_identity_map(kvm);
8550 if (err)
93ea5388 8551 goto free_vmcs;
b927a3ce 8552 }
b7ebfb05 8553
b9c237bb
WV		 8554 if (nested)
8555 nested_vmx_setup_ctls_msrs(vmx);
8556
705699a1 8557 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8558 vmx->nested.current_vmptr = -1ull;
8559 vmx->nested.current_vmcs12 = NULL;
8560
843e4330
KH		 8561 /*
8562 * If PML is turned on, failure on enabling PML just results in failure
8563 * of creating the vcpu, therefore we can simplify PML logic (by
8564 * avoiding dealing with cases, such as enabling PML partially on vcpus
8565 * for the guest, etc.
8566 */
8567 if (enable_pml) {
8568 err = vmx_enable_pml(vmx);
8569 if (err)
8570 goto free_vmcs;
8571 }
8572
fb3f0f51
RR		 8573 return &vmx->vcpu;
8574
8575free_vmcs:
5f3fbc34 8576 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8577free_msrs:
fb3f0f51
RR		 8578 kfree(vmx->guest_msrs);
8579uninit_vcpu:
8580 kvm_vcpu_uninit(&vmx->vcpu);
8581free_vcpu:
cdbecfc3 8582 free_vpid(vmx);
a4770347 8583 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8584 return ERR_PTR(err);
6aa8b732
AK		 8585}
8586
002c7f7c
YS		 8587static void __init vmx_check_processor_compat(void *rtn)
8588{
8589 struct vmcs_config vmcs_conf;
8590
8591 *(int *)rtn = 0;
8592 if (setup_vmcs_config(&vmcs_conf) < 0)
8593 *(int *)rtn = -EIO;
8594 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8595 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8596 smp_processor_id());
8597 *(int *)rtn = -EIO;
8598 }
8599}
8600
67253af5
SY		 8601static int get_ept_level(void)
8602{
8603 return VMX_EPT_DEFAULT_GAW + 1;
8604}
8605
4b12f0de 8606static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8607{
b18d5431
XG		 8608 u8 cache;
8609 u64 ipat = 0;
4b12f0de 8610
522c68c4 8611 /* For VT-d and EPT combination
606decd6 8612 * 1. MMIO: always map as UC
522c68c4
SY		 8613 * 2. EPT with VT-d:
8614 * a. VT-d without snooping control feature: can't guarantee the
606decd6 8615 * result, try to trust guest.
522c68c4
SY		 8616 * b. VT-d with snooping control feature: snooping control feature of
8617 * VT-d engine can guarantee the cache correctness. Just set it
8618 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8619 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8620 * consistent with host MTRR
8621 */
606decd6
PB		 8622 if (is_mmio) {
8623 cache = MTRR_TYPE_UNCACHABLE;
8624 goto exit;
8625 }
8626
8627 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG		 8628 ipat = VMX_EPT_IPAT_BIT;
8629 cache = MTRR_TYPE_WRBACK;
8630 goto exit;
8631 }
8632
8633 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8634 ipat = VMX_EPT_IPAT_BIT;
0da029ed 8635 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG		 8636 cache = MTRR_TYPE_WRBACK;
8637 else
8638 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG		 8639 goto exit;
8640 }
8641
ff53604b 8642 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG		 8643
8644exit:
8645 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY		 8646}
8647
17cc3935 8648static int vmx_get_lpage_level(void)
344f414f 8649{
878403b7
SY		 8650 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8651 return PT_DIRECTORY_LEVEL;
8652 else
8653 /* For shadow and EPT supported 1GB page */
8654 return PT_PDPE_LEVEL;
344f414f
JR		 8655}
8656
0e851880
SY		 8657static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8658{
4e47c7a6
SY		 8659 struct kvm_cpuid_entry2 *best;
8660 struct vcpu_vmx *vmx = to_vmx(vcpu);
8661 u32 exec_control;
8662
8663 vmx->rdtscp_enabled = false;
8664 if (vmx_rdtscp_supported()) {
8665 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8666 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8667 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8668 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8669 vmx->rdtscp_enabled = true;
8670 else {
8671 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8672 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8673 exec_control);
8674 }
8675 }
b3a2a907
JK		 8676 if (nested && !vmx->rdtscp_enabled)
8677 vmx->nested.nested_vmx_secondary_ctls_high &=
8678 ~SECONDARY_EXEC_RDTSCP;
4e47c7a6 8679 }
ad756a16 8680
ad756a16
MJ		 8681 /* Exposing INVPCID only when PCID is exposed */
8682 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8683 if (vmx_invpcid_supported() &&
4f977045 8684 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8685 guest_cpuid_has_pcid(vcpu)) {
29282fde 8686 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8687 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8688 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8689 exec_control);
8690 } else {
29282fde
TI		 8691 if (cpu_has_secondary_exec_ctrls()) {
8692 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8693 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8694 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8695 exec_control);
8696 }
ad756a16 8697 if (best)
4f977045 8698 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8699 }
0e851880
SY		 8700}
8701
d4330ef2
JR		 8702static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8703{
7b8050f5
NHE		 8704 if (func == 1 && nested)
8705 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8706}
8707
25d92081
YZ		 8708static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8709 struct x86_exception *fault)
8710{
533558bc
JK		 8711 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8712 u32 exit_reason;
25d92081
YZ		 8713
8714 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8715 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8716 else
533558bc
JK		 8717 exit_reason = EXIT_REASON_EPT_VIOLATION;
8718 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8719 vmcs12->guest_physical_address = fault->address;
8720}
8721
155a97a3
NHE		 8722/* Callbacks for nested_ept_init_mmu_context: */
8723
8724static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8725{
8726 /* return the page table to be shadowed - in our case, EPT12 */
8727 return get_vmcs12(vcpu)->ept_pointer;
8728}
8729
8a3c1a33 8730static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8731{
ad896af0
PB		 8732 WARN_ON(mmu_is_nested(vcpu));
8733 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8734 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8735 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8736 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8737 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8738 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8739
8740 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8741}
8742
8743static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8744{
8745 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8746}
8747
19d5f10b
EK		 8748static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8749 u16 error_code)
8750{
8751 bool inequality, bit;
8752
8753 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8754 inequality =
8755 (error_code & vmcs12->page_fault_error_code_mask) !=
8756 vmcs12->page_fault_error_code_match;
8757 return inequality ^ bit;
8758}
8759
feaf0c7d
GN		 8760static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8761 struct x86_exception *fault)
8762{
8763 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8764
8765 WARN_ON(!is_guest_mode(vcpu));
8766
19d5f10b 8767 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8768 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8769 vmcs_read32(VM_EXIT_INTR_INFO),
8770 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8771 else
8772 kvm_inject_page_fault(vcpu, fault);
8773}
8774
a2bcba50
WL		 8775static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8776 struct vmcs12 *vmcs12)
8777{
8778 struct vcpu_vmx *vmx = to_vmx(vcpu);
9090422f 8779 int maxphyaddr = cpuid_maxphyaddr(vcpu);
a2bcba50
WL		 8780
8781 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090422f
EK		 8782 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8783 vmcs12->apic_access_addr >> maxphyaddr)
a2bcba50
WL		 8784 return false;
8785
8786 /*
8787 * Translate L1 physical address to host physical
8788 * address for vmcs02. Keep the page pinned, so this
8789 * physical address remains valid. We keep a reference
8790 * to it so we can release it later.
8791 */
8792 if (vmx->nested.apic_access_page) /* shouldn't happen */
8793 nested_release_page(vmx->nested.apic_access_page);
8794 vmx->nested.apic_access_page =
8795 nested_get_page(vcpu, vmcs12->apic_access_addr);
8796 }
a7c0b07d
WL		 8797
8798 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9090422f
EK		 8799 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8800 vmcs12->virtual_apic_page_addr >> maxphyaddr)
a7c0b07d
WL		 8801 return false;
8802
8803 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8804 nested_release_page(vmx->nested.virtual_apic_page);
8805 vmx->nested.virtual_apic_page =
8806 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8807
8808 /*
8809 * Failing the vm entry is _not_ what the processor does
8810 * but it's basically the only possibility we have.
8811 * We could still enter the guest if CR8 load exits are
8812 * enabled, CR8 store exits are enabled, and virtualize APIC
8813 * access is disabled; in this case the processor would never
8814 * use the TPR shadow and we could simply clear the bit from
8815 * the execution control. But such a configuration is useless,
8816 * so let's keep the code simple.
8817 */
8818 if (!vmx->nested.virtual_apic_page)
8819 return false;
8820 }
8821
705699a1 8822 if (nested_cpu_has_posted_intr(vmcs12)) {
9090422f
EK		 8823 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8824 vmcs12->posted_intr_desc_addr >> maxphyaddr)
705699a1
WV		 8825 return false;
8826
8827 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8828 kunmap(vmx->nested.pi_desc_page);
8829 nested_release_page(vmx->nested.pi_desc_page);
8830 }
8831 vmx->nested.pi_desc_page =
8832 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8833 if (!vmx->nested.pi_desc_page)
8834 return false;
8835
8836 vmx->nested.pi_desc =
8837 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8838 if (!vmx->nested.pi_desc) {
8839 nested_release_page_clean(vmx->nested.pi_desc_page);
8840 return false;
8841 }
8842 vmx->nested.pi_desc =
8843 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8844 (unsigned long)(vmcs12->posted_intr_desc_addr &
8845 (PAGE_SIZE - 1)));
8846 }
8847
a2bcba50
WL		 8848 return true;
8849}
8850
f4124500
JK		 8851static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8852{
8853 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8854 struct vcpu_vmx *vmx = to_vmx(vcpu);
8855
8856 if (vcpu->arch.virtual_tsc_khz == 0)
8857 return;
8858
8859 /* Make sure short timeouts reliably trigger an immediate vmexit.
8860 * hrtimer_start does not guarantee this. */
8861 if (preemption_timeout <= 1) {
8862 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8863 return;
8864 }
8865
8866 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8867 preemption_timeout *= 1000000;
8868 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8869 hrtimer_start(&vmx->nested.preemption_timer,
8870 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8871}
8872
3af18d9c
WV		 8873static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8874 struct vmcs12 *vmcs12)
8875{
8876 int maxphyaddr;
8877 u64 addr;
8878
8879 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8880 return 0;
8881
8882 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8883 WARN_ON(1);
8884 return -EINVAL;
8885 }
8886 maxphyaddr = cpuid_maxphyaddr(vcpu);
8887
8888 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8889 ((addr + PAGE_SIZE) >> maxphyaddr))
8890 return -EINVAL;
8891
8892 return 0;
8893}
8894
8895/*
8896 * Merge L0's and L1's MSR bitmap, return false to indicate that
8897 * we do not use the hardware.
8898 */
8899static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8900 struct vmcs12 *vmcs12)
8901{
82f0dd4b 8902 int msr;
f2b93280
WV		 8903 struct page *page;
8904 unsigned long *msr_bitmap;
8905
8906 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8907 return false;
8908
8909 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8910 if (!page) {
8911 WARN_ON(1);
8912 return false;
8913 }
8914 msr_bitmap = (unsigned long *)kmap(page);
8915 if (!msr_bitmap) {
8916 nested_release_page_clean(page);
8917 WARN_ON(1);
8918 return false;
8919 }
8920
8921 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 8922 if (nested_cpu_has_apic_reg_virt(vmcs12))
8923 for (msr = 0x800; msr <= 0x8ff; msr++)
8924 nested_vmx_disable_intercept_for_msr(
8925 msr_bitmap,
8926 vmx_msr_bitmap_nested,
8927 msr, MSR_TYPE_R);
f2b93280
WV		 8928 /* TPR is allowed */
8929 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8930 vmx_msr_bitmap_nested,
8931 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8932 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 8933 if (nested_cpu_has_vid(vmcs12)) {
8934 /* EOI and self-IPI are allowed */
8935 nested_vmx_disable_intercept_for_msr(
8936 msr_bitmap,
8937 vmx_msr_bitmap_nested,
8938 APIC_BASE_MSR + (APIC_EOI >> 4),
8939 MSR_TYPE_W);
8940 nested_vmx_disable_intercept_for_msr(
8941 msr_bitmap,
8942 vmx_msr_bitmap_nested,
8943 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8944 MSR_TYPE_W);
8945 }
82f0dd4b
WV		 8946 } else {
8947 /*
8948 * Enable reading intercept of all the x2apic
8949 * MSRs. We should not rely on vmcs12 to do any
8950 * optimizations here, it may have been modified
8951 * by L1.
8952 */
8953 for (msr = 0x800; msr <= 0x8ff; msr++)
8954 __vmx_enable_intercept_for_msr(
8955 vmx_msr_bitmap_nested,
8956 msr,
8957 MSR_TYPE_R);
8958
f2b93280
WV		 8959 __vmx_enable_intercept_for_msr(
8960 vmx_msr_bitmap_nested,
8961 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 8962 MSR_TYPE_W);
608406e2
WV		 8963 __vmx_enable_intercept_for_msr(
8964 vmx_msr_bitmap_nested,
8965 APIC_BASE_MSR + (APIC_EOI >> 4),
8966 MSR_TYPE_W);
8967 __vmx_enable_intercept_for_msr(
8968 vmx_msr_bitmap_nested,
8969 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8970 MSR_TYPE_W);
82f0dd4b 8971 }
f2b93280
WV		 8972 kunmap(page);
8973 nested_release_page_clean(page);
8974
8975 return true;
8976}
8977
8978static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8979 struct vmcs12 *vmcs12)
8980{
82f0dd4b 8981 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 8982 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 8983 !nested_cpu_has_vid(vmcs12) &&
8984 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 8985 return 0;
8986
8987 /*
8988 * If virtualize x2apic mode is enabled,
8989 * virtualize apic access must be disabled.
8990 */
82f0dd4b
WV		 8991 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8992 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 8993 return -EINVAL;
8994
608406e2
WV		 8995 /*
8996 * If virtual interrupt delivery is enabled,
8997 * we must exit on external interrupts.
8998 */
8999 if (nested_cpu_has_vid(vmcs12) &&
9000 !nested_exit_on_intr(vcpu))
9001 return -EINVAL;
9002
705699a1
WV		 9003 /*
9004 * bits 15:8 should be zero in posted_intr_nv,
9005 * the descriptor address has been already checked
9006 * in nested_get_vmcs12_pages.
9007 */
9008 if (nested_cpu_has_posted_intr(vmcs12) &&
9009 (!nested_cpu_has_vid(vmcs12) ||
9010 !nested_exit_intr_ack_set(vcpu) ||
9011 vmcs12->posted_intr_nv & 0xff00))
9012 return -EINVAL;
9013
f2b93280
WV		 9014 /* tpr shadow is needed by all apicv features. */
9015 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9016 return -EINVAL;
9017
9018 return 0;
3af18d9c
WV		 9019}
9020
e9ac033e
EK		 9021static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9022 unsigned long count_field,
92d71bc6 9023 unsigned long addr_field)
ff651cb6 9024{
92d71bc6 9025 int maxphyaddr;
e9ac033e
EK		 9026 u64 count, addr;
9027
9028 if (vmcs12_read_any(vcpu, count_field, &count) ||
9029 vmcs12_read_any(vcpu, addr_field, &addr)) {
9030 WARN_ON(1);
9031 return -EINVAL;
9032 }
9033 if (count == 0)
9034 return 0;
92d71bc6 9035 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK		 9036 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9037 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9038 pr_warn_ratelimited(
9039 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9040 addr_field, maxphyaddr, count, addr);
9041 return -EINVAL;
9042 }
9043 return 0;
9044}
9045
9046static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9047 struct vmcs12 *vmcs12)
9048{
e9ac033e
EK		 9049 if (vmcs12->vm_exit_msr_load_count == 0 &&
9050 vmcs12->vm_exit_msr_store_count == 0 &&
9051 vmcs12->vm_entry_msr_load_count == 0)
9052 return 0; /* Fast path */
e9ac033e 9053 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9054 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9055 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9056 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9057 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9058 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK		 9059 return -EINVAL;
9060 return 0;
9061}
9062
9063static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9064 struct vmx_msr_entry *e)
9065{
9066 /* x2APIC MSR accesses are not allowed */
8a9781f7 9067 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK		 9068 return -EINVAL;
9069 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9070 e->index == MSR_IA32_UCODE_REV)
9071 return -EINVAL;
9072 if (e->reserved != 0)
ff651cb6
WV		 9073 return -EINVAL;
9074 return 0;
9075}
9076
e9ac033e
EK		 9077static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9078 struct vmx_msr_entry *e)
ff651cb6
WV		 9079{
9080 if (e->index == MSR_FS_BASE ||
9081 e->index == MSR_GS_BASE ||
e9ac033e
EK		 9082 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9083 nested_vmx_msr_check_common(vcpu, e))
9084 return -EINVAL;
9085 return 0;
9086}
9087
9088static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9089 struct vmx_msr_entry *e)
9090{
9091 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9092 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 9093 return -EINVAL;
9094 return 0;
9095}
9096
9097/*
9098 * Load guest's/host's msr at nested entry/exit.
9099 * return 0 for success, entry index for failure.
9100 */
9101static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9102{
9103 u32 i;
9104 struct vmx_msr_entry e;
9105 struct msr_data msr;
9106
9107 msr.host_initiated = false;
9108 for (i = 0; i < count; i++) {
54bf36aa
PB		 9109 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9110 &e, sizeof(e))) {
e9ac033e
EK		 9111 pr_warn_ratelimited(
9112 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9113 __func__, i, gpa + i * sizeof(e));
ff651cb6 9114 goto fail;
e9ac033e
EK		 9115 }
9116 if (nested_vmx_load_msr_check(vcpu, &e)) {
9117 pr_warn_ratelimited(
9118 "%s check failed (%u, 0x%x, 0x%x)\n",
9119 __func__, i, e.index, e.reserved);
9120 goto fail;
9121 }
ff651cb6
WV		 9122 msr.index = e.index;
9123 msr.data = e.value;
e9ac033e
EK		 9124 if (kvm_set_msr(vcpu, &msr)) {
9125 pr_warn_ratelimited(
9126 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9127 __func__, i, e.index, e.value);
ff651cb6 9128 goto fail;
e9ac033e 9129 }
ff651cb6
WV		 9130 }
9131 return 0;
9132fail:
9133 return i + 1;
9134}
9135
9136static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9137{
9138 u32 i;
9139 struct vmx_msr_entry e;
9140
9141 for (i = 0; i < count; i++) {
609e36d3 9142 struct msr_data msr_info;
54bf36aa
PB		 9143 if (kvm_vcpu_read_guest(vcpu,
9144 gpa + i * sizeof(e),
9145 &e, 2 * sizeof(u32))) {
e9ac033e
EK		 9146 pr_warn_ratelimited(
9147 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9148 __func__, i, gpa + i * sizeof(e));
ff651cb6 9149 return -EINVAL;
e9ac033e
EK		 9150 }
9151 if (nested_vmx_store_msr_check(vcpu, &e)) {
9152 pr_warn_ratelimited(
9153 "%s check failed (%u, 0x%x, 0x%x)\n",
9154 __func__, i, e.index, e.reserved);
ff651cb6 9155 return -EINVAL;
e9ac033e 9156 }
609e36d3
PB		 9157 msr_info.host_initiated = false;
9158 msr_info.index = e.index;
9159 if (kvm_get_msr(vcpu, &msr_info)) {
e9ac033e
EK		 9160 pr_warn_ratelimited(
9161 "%s cannot read MSR (%u, 0x%x)\n",
9162 __func__, i, e.index);
9163 return -EINVAL;
9164 }
54bf36aa
PB		 9165 if (kvm_vcpu_write_guest(vcpu,
9166 gpa + i * sizeof(e) +
9167 offsetof(struct vmx_msr_entry, value),
9168 &msr_info.data, sizeof(msr_info.data))) {
e9ac033e
EK		 9169 pr_warn_ratelimited(
9170 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9171 __func__, i, e.index, msr_info.data);
e9ac033e
EK		 9172 return -EINVAL;
9173 }
ff651cb6
WV		 9174 }
9175 return 0;
9176}
9177
fe3ef05c
NHE		 9178/*
9179 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9180 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9181 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9182 * guest in a way that will both be appropriate to L1's requests, and our
9183 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9184 * function also has additional necessary side-effects, like setting various
9185 * vcpu->arch fields.
9186 */
9187static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9188{
9189 struct vcpu_vmx *vmx = to_vmx(vcpu);
9190 u32 exec_control;
9191
9192 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9193 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9194 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9195 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9196 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9197 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9198 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9199 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9200 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9201 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9202 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9203 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9204 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9205 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9206 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9207 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9208 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9209 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9210 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9211 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9212 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9213 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9214 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9215 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9216 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9217 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9218 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9219 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9220 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9221 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9222 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9223 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9224 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9225 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9226 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9227 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9228
2996fca0
JK		 9229 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9230 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9231 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9232 } else {
9233 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9234 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9235 }
fe3ef05c
NHE		 9236 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9237 vmcs12->vm_entry_intr_info_field);
9238 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9239 vmcs12->vm_entry_exception_error_code);
9240 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9241 vmcs12->vm_entry_instruction_len);
9242 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9243 vmcs12->guest_interruptibility_info);
fe3ef05c 9244 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9245 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9246 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9247 vmcs12->guest_pending_dbg_exceptions);
9248 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9249 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9250
81dc01f7
WL		 9251 if (nested_cpu_has_xsaves(vmcs12))
9252 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9253 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9254
f4124500
JK		 9255 exec_control = vmcs12->pin_based_vm_exec_control;
9256 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9257 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9258
9259 if (nested_cpu_has_posted_intr(vmcs12)) {
9260 /*
9261 * Note that we use L0's vector here and in
9262 * vmx_deliver_nested_posted_interrupt.
9263 */
9264 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9265 vmx->nested.pi_pending = false;
9266 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9267 vmcs_write64(POSTED_INTR_DESC_ADDR,
9268 page_to_phys(vmx->nested.pi_desc_page) +
9269 (unsigned long)(vmcs12->posted_intr_desc_addr &
9270 (PAGE_SIZE - 1)));
9271 } else
9272 exec_control &= ~PIN_BASED_POSTED_INTR;
9273
f4124500 9274 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9275
f4124500
JK		 9276 vmx->nested.preemption_timer_expired = false;
9277 if (nested_cpu_has_preemption_timer(vmcs12))
9278 vmx_start_preemption_timer(vcpu);
0238ea91 9279
fe3ef05c
NHE		 9280 /*
9281 * Whether page-faults are trapped is determined by a combination of
9282 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9283 * If enable_ept, L0 doesn't care about page faults and we should
9284 * set all of these to L1's desires. However, if !enable_ept, L0 does
9285 * care about (at least some) page faults, and because it is not easy
9286 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9287 * to exit on each and every L2 page fault. This is done by setting
9288 * MASK=MATCH=0 and (see below) EB.PF=1.
9289 * Note that below we don't need special code to set EB.PF beyond the
9290 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9291 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9292 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9293 *
9294 * A problem with this approach (when !enable_ept) is that L1 may be
9295 * injected with more page faults than it asked for. This could have
9296 * caused problems, but in practice existing hypervisors don't care.
9297 * To fix this, we will need to emulate the PFEC checking (on the L1
9298 * page tables), using walk_addr(), when injecting PFs to L1.
9299 */
9300 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9301 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9302 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9303 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9304
9305 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9306 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 9307 if (!vmx->rdtscp_enabled)
9308 exec_control &= ~SECONDARY_EXEC_RDTSCP;
9309 /* Take the following fields only from vmcs12 */
696dfd95 9310 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 9311 SECONDARY_EXEC_RDTSCP |
696dfd95 9312 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
b3a2a907 9313 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 9314 if (nested_cpu_has(vmcs12,
9315 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9316 exec_control |= vmcs12->secondary_vm_exec_control;
9317
9318 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9319 /*
9320 * If translation failed, no matter: This feature asks
9321 * to exit when accessing the given address, and if it
9322 * can never be accessed, this feature won't do
9323 * anything anyway.
9324 */
9325 if (!vmx->nested.apic_access_page)
9326 exec_control &=
9327 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9328 else
9329 vmcs_write64(APIC_ACCESS_ADDR,
9330 page_to_phys(vmx->nested.apic_access_page));
f2b93280 9331 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
35754c98 9332 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
ca3f257a
JK		 9333 exec_control |=
9334 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9335 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9336 }
9337
608406e2
WV		 9338 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9339 vmcs_write64(EOI_EXIT_BITMAP0,
9340 vmcs12->eoi_exit_bitmap0);
9341 vmcs_write64(EOI_EXIT_BITMAP1,
9342 vmcs12->eoi_exit_bitmap1);
9343 vmcs_write64(EOI_EXIT_BITMAP2,
9344 vmcs12->eoi_exit_bitmap2);
9345 vmcs_write64(EOI_EXIT_BITMAP3,
9346 vmcs12->eoi_exit_bitmap3);
9347 vmcs_write16(GUEST_INTR_STATUS,
9348 vmcs12->guest_intr_status);
9349 }
9350
fe3ef05c
NHE		 9351 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9352 }
9353
9354
9355 /*
9356 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9357 * Some constant fields are set here by vmx_set_constant_host_state().
9358 * Other fields are different per CPU, and will be set later when
9359 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9360 */
a547c6db 9361 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9362
9363 /*
9364 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9365 * entry, but only if the current (host) sp changed from the value
9366 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9367 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9368 * here we just force the write to happen on entry.
9369 */
9370 vmx->host_rsp = 0;
9371
9372 exec_control = vmx_exec_control(vmx); /* L0's desires */
9373 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9374 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9375 exec_control &= ~CPU_BASED_TPR_SHADOW;
9376 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9377
9378 if (exec_control & CPU_BASED_TPR_SHADOW) {
9379 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9380 page_to_phys(vmx->nested.virtual_apic_page));
9381 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9382 }
9383
3af18d9c 9384 if (cpu_has_vmx_msr_bitmap() &&
670125bd
WV		 9385 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9386 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9387 /* MSR_BITMAP will be set by following vmx_set_efer. */
3af18d9c
WV		 9388 } else
9389 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9390
fe3ef05c 9391 /*
3af18d9c 9392 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9393 * Rather, exit every time.
9394 */
fe3ef05c
NHE		 9395 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9396 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9397
9398 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9399
9400 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9401 * bitwise-or of what L1 wants to trap for L2, and what we want to
9402 * trap. Note that CR0.TS also needs updating - we do this later.
9403 */
9404 update_exception_bitmap(vcpu);
9405 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9406 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9407
8049d651
NHE		 9408 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9409 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9410 * bits are further modified by vmx_set_efer() below.
9411 */
f4124500 9412 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9413
9414 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9415 * emulated by vmx_set_efer(), below.
9416 */
2961e876 9417 vm_entry_controls_init(vmx,
8049d651
NHE		 9418 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9419 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9420 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9421
44811c02 9422 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9423 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9424 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9425 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9426 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9427
9428
9429 set_cr4_guest_host_mask(vmx);
9430
36be0b9d
PB		 9431 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9432 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9433
27fc51b2
NHE		 9434 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9435 vmcs_write64(TSC_OFFSET,
9436 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9437 else
9438 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9439
9440 if (enable_vpid) {
9441 /*
9442 * Trivially support vpid by letting L2s share their parent
9443 * L1's vpid. TODO: move to a more elaborate solution, giving
9444 * each L2 its own vpid and exposing the vpid feature to L1.
9445 */
9446 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9447 vmx_flush_tlb(vcpu);
9448 }
9449
155a97a3
NHE		 9450 if (nested_cpu_has_ept(vmcs12)) {
9451 kvm_mmu_unload(vcpu);
9452 nested_ept_init_mmu_context(vcpu);
9453 }
9454
fe3ef05c
NHE		 9455 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9456 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9457 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9458 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9459 else
9460 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9461 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9462 vmx_set_efer(vcpu, vcpu->arch.efer);
9463
9464 /*
9465 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9466 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9467 * The CR0_READ_SHADOW is what L2 should have expected to read given
9468 * the specifications by L1; It's not enough to take
9469 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9470 * have more bits than L1 expected.
9471 */
9472 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9473 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9474
9475 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9476 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9477
9478 /* shadow page tables on either EPT or shadow page tables */
9479 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9480 kvm_mmu_reset_context(vcpu);
9481
feaf0c7d
GN		 9482 if (!enable_ept)
9483 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9484
3633cfc3
NHE		 9485 /*
9486 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9487 */
9488 if (enable_ept) {
9489 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9490 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9491 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9492 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9493 }
9494
fe3ef05c
NHE		 9495 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9496 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9497}
9498
cd232ad0
NHE		 9499/*
9500 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9501 * for running an L2 nested guest.
9502 */
9503static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9504{
9505 struct vmcs12 *vmcs12;
9506 struct vcpu_vmx *vmx = to_vmx(vcpu);
9507 int cpu;
9508 struct loaded_vmcs *vmcs02;
384bb783 9509 bool ia32e;
ff651cb6 9510 u32 msr_entry_idx;
cd232ad0
NHE		 9511
9512 if (!nested_vmx_check_permission(vcpu) ||
9513 !nested_vmx_check_vmcs12(vcpu))
9514 return 1;
9515
9516 skip_emulated_instruction(vcpu);
9517 vmcs12 = get_vmcs12(vcpu);
9518
012f83cb
AG		 9519 if (enable_shadow_vmcs)
9520 copy_shadow_to_vmcs12(vmx);
9521
7c177938
NHE		 9522 /*
9523 * The nested entry process starts with enforcing various prerequisites
9524 * on vmcs12 as required by the Intel SDM, and act appropriately when
9525 * they fail: As the SDM explains, some conditions should cause the
9526 * instruction to fail, while others will cause the instruction to seem
9527 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9528 * To speed up the normal (success) code path, we should avoid checking
9529 * for misconfigurations which will anyway be caught by the processor
9530 * when using the merged vmcs02.
9531 */
9532 if (vmcs12->launch_state == launch) {
9533 nested_vmx_failValid(vcpu,
9534 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9535 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9536 return 1;
9537 }
9538
6dfacadd
JK		 9539 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9540 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9541 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9542 return 1;
9543 }
9544
3af18d9c 9545 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9546 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9547 return 1;
9548 }
9549
3af18d9c 9550 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9551 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9552 return 1;
9553 }
9554
f2b93280
WV		 9555 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9556 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9557 return 1;
9558 }
9559
e9ac033e
EK		 9560 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9561 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9562 return 1;
9563 }
9564
7c177938 9565 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9566 vmx->nested.nested_vmx_true_procbased_ctls_low,
9567 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9568 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9569 vmx->nested.nested_vmx_secondary_ctls_low,
9570 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9571 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9572 vmx->nested.nested_vmx_pinbased_ctls_low,
9573 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9574 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9575 vmx->nested.nested_vmx_true_exit_ctls_low,
9576 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9577 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9578 vmx->nested.nested_vmx_true_entry_ctls_low,
9579 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9580 {
9581 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9582 return 1;
9583 }
9584
9585 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9586 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9587 nested_vmx_failValid(vcpu,
9588 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9589 return 1;
9590 }
9591
b9c237bb 9592 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9593 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9594 nested_vmx_entry_failure(vcpu, vmcs12,
9595 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9596 return 1;
9597 }
9598 if (vmcs12->vmcs_link_pointer != -1ull) {
9599 nested_vmx_entry_failure(vcpu, vmcs12,
9600 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9601 return 1;
9602 }
9603
384bb783 9604 /*
cb0c8cda 9605 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9606 * are performed on the field for the IA32_EFER MSR:
9607 * - Bits reserved in the IA32_EFER MSR must be 0.
9608 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9609 * the IA-32e mode guest VM-exit control. It must also be identical
9610 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9611 * CR0.PG) is 1.
9612 */
9613 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9614 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9615 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9616 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9617 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9618 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9619 nested_vmx_entry_failure(vcpu, vmcs12,
9620 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9621 return 1;
9622 }
9623 }
9624
9625 /*
9626 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9627 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9628 * the values of the LMA and LME bits in the field must each be that of
9629 * the host address-space size VM-exit control.
9630 */
9631 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9632 ia32e = (vmcs12->vm_exit_controls &
9633 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9634 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9635 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9636 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9637 nested_vmx_entry_failure(vcpu, vmcs12,
9638 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9639 return 1;
9640 }
9641 }
9642
7c177938
NHE		 9643 /*
9644 * We're finally done with prerequisite checking, and can start with
9645 * the nested entry.
9646 */
9647
cd232ad0
NHE		 9648 vmcs02 = nested_get_current_vmcs02(vmx);
9649 if (!vmcs02)
9650 return -ENOMEM;
9651
9652 enter_guest_mode(vcpu);
9653
9654 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9655
2996fca0
JK		 9656 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9657 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9658
cd232ad0
NHE		 9659 cpu = get_cpu();
9660 vmx->loaded_vmcs = vmcs02;
9661 vmx_vcpu_put(vcpu);
9662 vmx_vcpu_load(vcpu, cpu);
9663 vcpu->cpu = cpu;
9664 put_cpu();
9665
36c3cc42
JK		 9666 vmx_segment_cache_clear(vmx);
9667
cd232ad0
NHE		 9668 prepare_vmcs02(vcpu, vmcs12);
9669
ff651cb6
WV		 9670 msr_entry_idx = nested_vmx_load_msr(vcpu,
9671 vmcs12->vm_entry_msr_load_addr,
9672 vmcs12->vm_entry_msr_load_count);
9673 if (msr_entry_idx) {
9674 leave_guest_mode(vcpu);
9675 vmx_load_vmcs01(vcpu);
9676 nested_vmx_entry_failure(vcpu, vmcs12,
9677 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9678 return 1;
9679 }
9680
9681 vmcs12->launch_state = 1;
9682
6dfacadd 9683 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 9684 return kvm_vcpu_halt(vcpu);
6dfacadd 9685
7af40ad3
JK		 9686 vmx->nested.nested_run_pending = 1;
9687
cd232ad0
NHE		 9688 /*
9689 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9690 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9691 * returned as far as L1 is concerned. It will only return (and set
9692 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9693 */
9694 return 1;
9695}
9696
4704d0be
NHE		 9697/*
9698 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9699 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9700 * This function returns the new value we should put in vmcs12.guest_cr0.
9701 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9702 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9703 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9704 * didn't trap the bit, because if L1 did, so would L0).
9705 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9706 * been modified by L2, and L1 knows it. So just leave the old value of
9707 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9708 * isn't relevant, because if L0 traps this bit it can set it to anything.
9709 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9710 * changed these bits, and therefore they need to be updated, but L0
9711 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9712 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9713 */
9714static inline unsigned long
9715vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9716{
9717 return
9718 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9719 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9720 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9721 vcpu->arch.cr0_guest_owned_bits));
9722}
9723
9724static inline unsigned long
9725vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9726{
9727 return
9728 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9729 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9730 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9731 vcpu->arch.cr4_guest_owned_bits));
9732}
9733
5f3d5799
JK		 9734static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9735 struct vmcs12 *vmcs12)
9736{
9737 u32 idt_vectoring;
9738 unsigned int nr;
9739
851eb667 9740 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9741 nr = vcpu->arch.exception.nr;
9742 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9743
9744 if (kvm_exception_is_soft(nr)) {
9745 vmcs12->vm_exit_instruction_len =
9746 vcpu->arch.event_exit_inst_len;
9747 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9748 } else
9749 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9750
9751 if (vcpu->arch.exception.has_error_code) {
9752 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9753 vmcs12->idt_vectoring_error_code =
9754 vcpu->arch.exception.error_code;
9755 }
9756
9757 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9758 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9759 vmcs12->idt_vectoring_info_field =
9760 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9761 } else if (vcpu->arch.interrupt.pending) {
9762 nr = vcpu->arch.interrupt.nr;
9763 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9764
9765 if (vcpu->arch.interrupt.soft) {
9766 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9767 vmcs12->vm_entry_instruction_len =
9768 vcpu->arch.event_exit_inst_len;
9769 } else
9770 idt_vectoring |= INTR_TYPE_EXT_INTR;
9771
9772 vmcs12->idt_vectoring_info_field = idt_vectoring;
9773 }
9774}
9775
b6b8a145
JK		 9776static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9777{
9778 struct vcpu_vmx *vmx = to_vmx(vcpu);
9779
f4124500
JK		 9780 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9781 vmx->nested.preemption_timer_expired) {
9782 if (vmx->nested.nested_run_pending)
9783 return -EBUSY;
9784 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9785 return 0;
9786 }
9787
b6b8a145 9788 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9789 if (vmx->nested.nested_run_pending ||
9790 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9791 return -EBUSY;
9792 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9793 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9794 INTR_INFO_VALID_MASK, 0);
9795 /*
9796 * The NMI-triggered VM exit counts as injection:
9797 * clear this one and block further NMIs.
9798 */
9799 vcpu->arch.nmi_pending = 0;
9800 vmx_set_nmi_mask(vcpu, true);
9801 return 0;
9802 }
9803
9804 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9805 nested_exit_on_intr(vcpu)) {
9806 if (vmx->nested.nested_run_pending)
9807 return -EBUSY;
9808 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 9809 return 0;
b6b8a145
JK		 9810 }
9811
705699a1 9812 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 9813}
9814
f4124500
JK		 9815static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9816{
9817 ktime_t remaining =
9818 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9819 u64 value;
9820
9821 if (ktime_to_ns(remaining) <= 0)
9822 return 0;
9823
9824 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9825 do_div(value, 1000000);
9826 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9827}
9828
4704d0be
NHE		 9829/*
9830 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9831 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9832 * and this function updates it to reflect the changes to the guest state while
9833 * L2 was running (and perhaps made some exits which were handled directly by L0
9834 * without going back to L1), and to reflect the exit reason.
9835 * Note that we do not have to copy here all VMCS fields, just those that
9836 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9837 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9838 * which already writes to vmcs12 directly.
9839 */
533558bc
JK		 9840static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9841 u32 exit_reason, u32 exit_intr_info,
9842 unsigned long exit_qualification)
4704d0be
NHE		 9843{
9844 /* update guest state fields: */
9845 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9846 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9847
4704d0be
NHE		 9848 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9849 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9850 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9851
9852 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9853 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9854 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9855 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9856 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9857 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9858 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9859 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9860 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9861 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9862 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9863 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9864 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9865 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9866 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9867 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9868 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9869 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9870 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9871 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9872 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9873 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9874 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9875 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9876 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9877 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9878 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9879 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9880 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9881 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9882 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9883 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9884 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9885 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9886 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9887 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9888
4704d0be
NHE		 9889 vmcs12->guest_interruptibility_info =
9890 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9891 vmcs12->guest_pending_dbg_exceptions =
9892 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9893 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9894 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9895 else
9896 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9897
f4124500
JK		 9898 if (nested_cpu_has_preemption_timer(vmcs12)) {
9899 if (vmcs12->vm_exit_controls &
9900 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9901 vmcs12->vmx_preemption_timer_value =
9902 vmx_get_preemption_timer_value(vcpu);
9903 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9904 }
7854cbca 9905
3633cfc3
NHE		 9906 /*
9907 * In some cases (usually, nested EPT), L2 is allowed to change its
9908 * own CR3 without exiting. If it has changed it, we must keep it.
9909 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9910 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9911 *
9912 * Additionally, restore L2's PDPTR to vmcs12.
9913 */
9914 if (enable_ept) {
9915 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9916 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9917 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9918 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9919 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9920 }
9921
608406e2
WV		 9922 if (nested_cpu_has_vid(vmcs12))
9923 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9924
c18911a2
JK		 9925 vmcs12->vm_entry_controls =
9926 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9927 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9928
2996fca0
JK		 9929 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9930 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9931 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9932 }
9933
4704d0be
NHE		 9934 /* TODO: These cannot have changed unless we have MSR bitmaps and
9935 * the relevant bit asks not to trap the change */
b8c07d55 9936 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9937 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9938 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9939 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9940 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9941 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9942 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9943 if (vmx_mpx_supported())
9944 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9945 if (nested_cpu_has_xsaves(vmcs12))
9946 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9947
9948 /* update exit information fields: */
9949
533558bc
JK		 9950 vmcs12->vm_exit_reason = exit_reason;
9951 vmcs12->exit_qualification = exit_qualification;
4704d0be 9952
533558bc 9953 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9954 if ((vmcs12->vm_exit_intr_info &
9955 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9956 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9957 vmcs12->vm_exit_intr_error_code =
9958 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9959 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9960 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9961 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9962
5f3d5799
JK		 9963 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9964 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9965 * instead of reading the real value. */
4704d0be 9966 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9967
9968 /*
9969 * Transfer the event that L0 or L1 may wanted to inject into
9970 * L2 to IDT_VECTORING_INFO_FIELD.
9971 */
9972 vmcs12_save_pending_event(vcpu, vmcs12);
9973 }
9974
9975 /*
9976 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9977 * preserved above and would only end up incorrectly in L1.
9978 */
9979 vcpu->arch.nmi_injected = false;
9980 kvm_clear_exception_queue(vcpu);
9981 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 9982}
9983
9984/*
9985 * A part of what we need to when the nested L2 guest exits and we want to
9986 * run its L1 parent, is to reset L1's guest state to the host state specified
9987 * in vmcs12.
9988 * This function is to be called not only on normal nested exit, but also on
9989 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9990 * Failures During or After Loading Guest State").
9991 * This function should be called when the active VMCS is L1's (vmcs01).
9992 */
733568f9
JK		 9993static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9994 struct vmcs12 *vmcs12)
4704d0be 9995{
21feb4eb
ACL		 9996 struct kvm_segment seg;
9997
4704d0be
NHE		 9998 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9999 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 10000 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 10001 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10002 else
10003 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10004 vmx_set_efer(vcpu, vcpu->arch.efer);
10005
10006 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10007 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10008 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 10009 /*
10010 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10011 * actually changed, because it depends on the current state of
10012 * fpu_active (which may have changed).
10013 * Note that vmx_set_cr0 refers to efer set above.
10014 */
9e3e4dbf 10015 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 10016 /*
10017 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10018 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10019 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10020 */
10021 update_exception_bitmap(vcpu);
10022 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10023 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10024
10025 /*
10026 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10027 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10028 */
10029 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10030 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10031
29bf08f1 10032 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10033
4704d0be
NHE		 10034 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10035 kvm_mmu_reset_context(vcpu);
10036
feaf0c7d
GN		 10037 if (!enable_ept)
10038 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10039
4704d0be
NHE		 10040 if (enable_vpid) {
10041 /*
10042 * Trivially support vpid by letting L2s share their parent
10043 * L1's vpid. TODO: move to a more elaborate solution, giving
10044 * each L2 its own vpid and exposing the vpid feature to L1.
10045 */
10046 vmx_flush_tlb(vcpu);
10047 }
10048
10049
10050 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10051 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10052 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10053 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10054 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10055
36be0b9d
PB		 10056 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10057 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10058 vmcs_write64(GUEST_BNDCFGS, 0);
10059
44811c02 10060 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10061 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 10062 vcpu->arch.pat = vmcs12->host_ia32_pat;
10063 }
4704d0be
NHE		 10064 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10065 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10066 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10067
21feb4eb
ACL		 10068 /* Set L1 segment info according to Intel SDM
10069 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10070 seg = (struct kvm_segment) {
10071 .base = 0,
10072 .limit = 0xFFFFFFFF,
10073 .selector = vmcs12->host_cs_selector,
10074 .type = 11,
10075 .present = 1,
10076 .s = 1,
10077 .g = 1
10078 };
10079 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10080 seg.l = 1;
10081 else
10082 seg.db = 1;
10083 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10084 seg = (struct kvm_segment) {
10085 .base = 0,
10086 .limit = 0xFFFFFFFF,
10087 .type = 3,
10088 .present = 1,
10089 .s = 1,
10090 .db = 1,
10091 .g = 1
10092 };
10093 seg.selector = vmcs12->host_ds_selector;
10094 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10095 seg.selector = vmcs12->host_es_selector;
10096 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10097 seg.selector = vmcs12->host_ss_selector;
10098 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10099 seg.selector = vmcs12->host_fs_selector;
10100 seg.base = vmcs12->host_fs_base;
10101 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10102 seg.selector = vmcs12->host_gs_selector;
10103 seg.base = vmcs12->host_gs_base;
10104 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10105 seg = (struct kvm_segment) {
205befd9 10106 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 10107 .limit = 0x67,
10108 .selector = vmcs12->host_tr_selector,
10109 .type = 11,
10110 .present = 1
10111 };
10112 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10113
503cd0c5
JK		 10114 kvm_set_dr(vcpu, 7, 0x400);
10115 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10116
3af18d9c
WV		 10117 if (cpu_has_vmx_msr_bitmap())
10118 vmx_set_msr_bitmap(vcpu);
10119
ff651cb6
WV		 10120 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10121 vmcs12->vm_exit_msr_load_count))
10122 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 10123}
10124
10125/*
10126 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10127 * and modify vmcs12 to make it see what it would expect to see there if
10128 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10129 */
533558bc
JK		 10130static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10131 u32 exit_intr_info,
10132 unsigned long exit_qualification)
4704d0be
NHE		 10133{
10134 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 10135 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10136
5f3d5799
JK		 10137 /* trying to cancel vmlaunch/vmresume is a bug */
10138 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10139
4704d0be 10140 leave_guest_mode(vcpu);
533558bc
JK		 10141 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10142 exit_qualification);
4704d0be 10143
ff651cb6
WV		 10144 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10145 vmcs12->vm_exit_msr_store_count))
10146 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10147
f3380ca5
WL		 10148 vmx_load_vmcs01(vcpu);
10149
77b0f5d6
BD		 10150 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10151 && nested_exit_intr_ack_set(vcpu)) {
10152 int irq = kvm_cpu_get_interrupt(vcpu);
10153 WARN_ON(irq < 0);
10154 vmcs12->vm_exit_intr_info = irq |
10155 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10156 }
10157
542060ea
JK		 10158 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10159 vmcs12->exit_qualification,
10160 vmcs12->idt_vectoring_info_field,
10161 vmcs12->vm_exit_intr_info,
10162 vmcs12->vm_exit_intr_error_code,
10163 KVM_ISA_VMX);
4704d0be 10164
2961e876
GN		 10165 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10166 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10167 vmx_segment_cache_clear(vmx);
10168
4704d0be
NHE		 10169 /* if no vmcs02 cache requested, remove the one we used */
10170 if (VMCS02_POOL_SIZE == 0)
10171 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10172
10173 load_vmcs12_host_state(vcpu, vmcs12);
10174
27fc51b2 10175 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10176 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10177
10178 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10179 vmx->host_rsp = 0;
10180
10181 /* Unpin physical memory we referred to in vmcs02 */
10182 if (vmx->nested.apic_access_page) {
10183 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10184 vmx->nested.apic_access_page = NULL;
4704d0be 10185 }
a7c0b07d
WL		 10186 if (vmx->nested.virtual_apic_page) {
10187 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10188 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10189 }
705699a1
WV		 10190 if (vmx->nested.pi_desc_page) {
10191 kunmap(vmx->nested.pi_desc_page);
10192 nested_release_page(vmx->nested.pi_desc_page);
10193 vmx->nested.pi_desc_page = NULL;
10194 vmx->nested.pi_desc = NULL;
10195 }
4704d0be 10196
38b99173
TC		 10197 /*
10198 * We are now running in L2, mmu_notifier will force to reload the
10199 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10200 */
10201 kvm_vcpu_reload_apic_access_page(vcpu);
10202
4704d0be
NHE		 10203 /*
10204 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10205 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10206 * success or failure flag accordingly.
10207 */
10208 if (unlikely(vmx->fail)) {
10209 vmx->fail = 0;
10210 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10211 } else
10212 nested_vmx_succeed(vcpu);
012f83cb
AG		 10213 if (enable_shadow_vmcs)
10214 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10215
10216 /* in case we halted in L2 */
10217 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10218}
10219
42124925
JK		 10220/*
10221 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10222 */
10223static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10224{
10225 if (is_guest_mode(vcpu))
533558bc 10226 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10227 free_nested(to_vmx(vcpu));
10228}
10229
7c177938
NHE		 10230/*
10231 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10232 * 23.7 "VM-entry failures during or after loading guest state" (this also
10233 * lists the acceptable exit-reason and exit-qualification parameters).
10234 * It should only be called before L2 actually succeeded to run, and when
10235 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10236 */
10237static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10238 struct vmcs12 *vmcs12,
10239 u32 reason, unsigned long qualification)
10240{
10241 load_vmcs12_host_state(vcpu, vmcs12);
10242 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10243 vmcs12->exit_qualification = qualification;
10244 nested_vmx_succeed(vcpu);
012f83cb
AG		 10245 if (enable_shadow_vmcs)
10246 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10247}
10248
8a76d7f2
JR		 10249static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10250 struct x86_instruction_info *info,
10251 enum x86_intercept_stage stage)
10252{
10253 return X86EMUL_CONTINUE;
10254}
10255
48d89b92 10256static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10257{
b4a2d31d
RK		 10258 if (ple_gap)
10259 shrink_ple_window(vcpu);
ae97a3b8
RK		 10260}
10261
843e4330
KH		 10262static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10263 struct kvm_memory_slot *slot)
10264{
10265 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10266 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10267}
10268
10269static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10270 struct kvm_memory_slot *slot)
10271{
10272 kvm_mmu_slot_set_dirty(kvm, slot);
10273}
10274
10275static void vmx_flush_log_dirty(struct kvm *kvm)
10276{
10277 kvm_flush_pml_buffers(kvm);
10278}
10279
10280static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10281 struct kvm_memory_slot *memslot,
10282 gfn_t offset, unsigned long mask)
10283{
10284 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10285}
10286
cbdd1bea 10287static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10288 .cpu_has_kvm_support = cpu_has_kvm_support,
10289 .disabled_by_bios = vmx_disabled_by_bios,
10290 .hardware_setup = hardware_setup,
10291 .hardware_unsetup = hardware_unsetup,
002c7f7c 10292 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10293 .hardware_enable = hardware_enable,
10294 .hardware_disable = hardware_disable,
04547156 10295 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 10296 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK		 10297
10298 .vcpu_create = vmx_create_vcpu,
10299 .vcpu_free = vmx_free_vcpu,
04d2cc77 10300 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10301
04d2cc77 10302 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10303 .vcpu_load = vmx_vcpu_load,
10304 .vcpu_put = vmx_vcpu_put,
10305
c8639010 10306 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10307 .get_msr = vmx_get_msr,
10308 .set_msr = vmx_set_msr,
10309 .get_segment_base = vmx_get_segment_base,
10310 .get_segment = vmx_get_segment,
10311 .set_segment = vmx_set_segment,
2e4d2653 10312 .get_cpl = vmx_get_cpl,
6aa8b732 10313 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10314 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10315 .decache_cr3 = vmx_decache_cr3,
25c4c276 10316 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10317 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10318 .set_cr3 = vmx_set_cr3,
10319 .set_cr4 = vmx_set_cr4,
6aa8b732 10320 .set_efer = vmx_set_efer,
6aa8b732
AK		 10321 .get_idt = vmx_get_idt,
10322 .set_idt = vmx_set_idt,
10323 .get_gdt = vmx_get_gdt,
10324 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10325 .get_dr6 = vmx_get_dr6,
10326 .set_dr6 = vmx_set_dr6,
020df079 10327 .set_dr7 = vmx_set_dr7,
81908bf4 10328 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10329 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10330 .get_rflags = vmx_get_rflags,
10331 .set_rflags = vmx_set_rflags,
0fdd74f7 10332 .fpu_activate = vmx_fpu_activate,
02daab21 10333 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10334
10335 .tlb_flush = vmx_flush_tlb,
6aa8b732 10336
6aa8b732 10337 .run = vmx_vcpu_run,
6062d012 10338 .handle_exit = vmx_handle_exit,
6aa8b732 10339 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10340 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10341 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10342 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10343 .set_irq = vmx_inject_irq,
95ba8273 10344 .set_nmi = vmx_inject_nmi,
298101da 10345 .queue_exception = vmx_queue_exception,
b463a6f7 10346 .cancel_injection = vmx_cancel_injection,
78646121 10347 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10348 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10349 .get_nmi_mask = vmx_get_nmi_mask,
10350 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10351 .enable_nmi_window = enable_nmi_window,
10352 .enable_irq_window = enable_irq_window,
10353 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10354 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10355 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d50ab6c1 10356 .cpu_uses_apicv = vmx_cpu_uses_apicv,
c7c9c56c
YZ		 10357 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10358 .hwapic_irr_update = vmx_hwapic_irr_update,
10359 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10360 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10361 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10362
cbc94022 10363 .set_tss_addr = vmx_set_tss_addr,
67253af5 10364 .get_tdp_level = get_ept_level,
4b12f0de 10365 .get_mt_mask = vmx_get_mt_mask,
229456fc 10366
586f9607 10367 .get_exit_info = vmx_get_exit_info,
586f9607 10368
17cc3935 10369 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10370
10371 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10372
10373 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10374 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10375
10376 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10377
10378 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10379
4051b188 10380 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10381 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10382 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10383 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10384 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10385 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10386
10387 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10388
10389 .check_intercept = vmx_check_intercept,
a547c6db 10390 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10391 .mpx_supported = vmx_mpx_supported,
55412b2e 10392 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10393
10394 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10395
10396 .sched_in = vmx_sched_in,
843e4330
KH		 10397
10398 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10399 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10400 .flush_log_dirty = vmx_flush_log_dirty,
10401 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
25462f7f
WH		 10402
10403 .pmu_ops = &intel_pmu_ops,
6aa8b732
AK		 10404};
10405
10406static int __init vmx_init(void)
10407{
34a1cd60
TC		 10408 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10409 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10410 if (r)
34a1cd60 10411 return r;
25c5f225 10412
2965faa5 10413#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 10414 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10415 crash_vmclear_local_loaded_vmcss);
10416#endif
10417
fdef3ad1 10418 return 0;
6aa8b732
AK		 10419}
10420
10421static void __exit vmx_exit(void)
10422{
2965faa5 10423#ifdef CONFIG_KEXEC_CORE
3b63a43f 10424 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10425 synchronize_rcu();
10426#endif
10427
cb498ea2 10428 kvm_exit();
6aa8b732
AK		 10429}
10430
10431module_init(vmx_init)
10432module_exit(vmx_exit)
Linux 6.x block layer and io_uring tree(s)