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KVM: remove the unused parameter of gfn_to_pfn_memslot
[linux-block.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
6aa8b732 45
229456fc
MT		 46#include "trace.h"
47
4ecac3fd 48#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 49#define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 51
6aa8b732
AK		 52MODULE_AUTHOR("Qumranet");
53MODULE_LICENSE("GPL");
54
e9bda3b3
JT		 55static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
57 {}
58};
59MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
476bc001 61static bool __read_mostly enable_vpid = 1;
736caefe 62module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 63
476bc001 64static bool __read_mostly flexpriority_enabled = 1;
736caefe 65module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 66
476bc001 67static bool __read_mostly enable_ept = 1;
736caefe 68module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 69
476bc001 70static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 71module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
73
83c3a331
XH		 74static bool __read_mostly enable_ept_ad_bits = 1;
75module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
a27685c3 77static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 78module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 79
476bc001 80static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 81module_param(vmm_exclusive, bool, S_IRUGO);
82
476bc001 83static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 84module_param(fasteoi, bool, S_IRUGO);
85
801d3424
NHE		 86/*
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
90 */
476bc001 91static bool __read_mostly nested = 0;
801d3424
NHE		 92module_param(nested, bool, S_IRUGO);
93
cdc0e244
AK		 94#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96#define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 99 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 100#define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 102#define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
cdc0e244
AK		 106#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
78ac8b47
AK		 109#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
4b8d54f9
ZE		 111/*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 115 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
00c25bce 122#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 123#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125module_param(ple_gap, int, S_IRUGO);
126
127static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128module_param(ple_window, int, S_IRUGO);
129
8bf00a52 130#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 131#define VMCS02_POOL_SIZE 1
61d2ef2c 132
a2fa3e9f
GH		 133struct vmcs {
134 u32 revision_id;
135 u32 abort;
136 char data[0];
137};
138
d462b819
NHE		 139/*
140 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
141 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
142 * loaded on this CPU (so we can clear them if the CPU goes down).
143 */
144struct loaded_vmcs {
145 struct vmcs *vmcs;
146 int cpu;
147 int launched;
148 struct list_head loaded_vmcss_on_cpu_link;
149};
150
26bb0981
AK		 151struct shared_msr_entry {
152 unsigned index;
153 u64 data;
d5696725 154 u64 mask;
26bb0981
AK		 155};
156
a9d30f33
NHE		 157/*
158 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
159 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
160 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
161 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
162 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
163 * More than one of these structures may exist, if L1 runs multiple L2 guests.
164 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
165 * underlying hardware which will be used to run L2.
166 * This structure is packed to ensure that its layout is identical across
167 * machines (necessary for live migration).
168 * If there are changes in this struct, VMCS12_REVISION must be changed.
169 */
22bd0358 170typedef u64 natural_width;
a9d30f33
NHE		 171struct __packed vmcs12 {
172 /* According to the Intel spec, a VMCS region must start with the
173 * following two fields. Then follow implementation-specific data.
174 */
175 u32 revision_id;
176 u32 abort;
22bd0358 177
27d6c865
NHE		 178 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
179 u32 padding[7]; /* room for future expansion */
180
22bd0358
NHE		 181 u64 io_bitmap_a;
182 u64 io_bitmap_b;
183 u64 msr_bitmap;
184 u64 vm_exit_msr_store_addr;
185 u64 vm_exit_msr_load_addr;
186 u64 vm_entry_msr_load_addr;
187 u64 tsc_offset;
188 u64 virtual_apic_page_addr;
189 u64 apic_access_addr;
190 u64 ept_pointer;
191 u64 guest_physical_address;
192 u64 vmcs_link_pointer;
193 u64 guest_ia32_debugctl;
194 u64 guest_ia32_pat;
195 u64 guest_ia32_efer;
196 u64 guest_ia32_perf_global_ctrl;
197 u64 guest_pdptr0;
198 u64 guest_pdptr1;
199 u64 guest_pdptr2;
200 u64 guest_pdptr3;
201 u64 host_ia32_pat;
202 u64 host_ia32_efer;
203 u64 host_ia32_perf_global_ctrl;
204 u64 padding64[8]; /* room for future expansion */
205 /*
206 * To allow migration of L1 (complete with its L2 guests) between
207 * machines of different natural widths (32 or 64 bit), we cannot have
208 * unsigned long fields with no explict size. We use u64 (aliased
209 * natural_width) instead. Luckily, x86 is little-endian.
210 */
211 natural_width cr0_guest_host_mask;
212 natural_width cr4_guest_host_mask;
213 natural_width cr0_read_shadow;
214 natural_width cr4_read_shadow;
215 natural_width cr3_target_value0;
216 natural_width cr3_target_value1;
217 natural_width cr3_target_value2;
218 natural_width cr3_target_value3;
219 natural_width exit_qualification;
220 natural_width guest_linear_address;
221 natural_width guest_cr0;
222 natural_width guest_cr3;
223 natural_width guest_cr4;
224 natural_width guest_es_base;
225 natural_width guest_cs_base;
226 natural_width guest_ss_base;
227 natural_width guest_ds_base;
228 natural_width guest_fs_base;
229 natural_width guest_gs_base;
230 natural_width guest_ldtr_base;
231 natural_width guest_tr_base;
232 natural_width guest_gdtr_base;
233 natural_width guest_idtr_base;
234 natural_width guest_dr7;
235 natural_width guest_rsp;
236 natural_width guest_rip;
237 natural_width guest_rflags;
238 natural_width guest_pending_dbg_exceptions;
239 natural_width guest_sysenter_esp;
240 natural_width guest_sysenter_eip;
241 natural_width host_cr0;
242 natural_width host_cr3;
243 natural_width host_cr4;
244 natural_width host_fs_base;
245 natural_width host_gs_base;
246 natural_width host_tr_base;
247 natural_width host_gdtr_base;
248 natural_width host_idtr_base;
249 natural_width host_ia32_sysenter_esp;
250 natural_width host_ia32_sysenter_eip;
251 natural_width host_rsp;
252 natural_width host_rip;
253 natural_width paddingl[8]; /* room for future expansion */
254 u32 pin_based_vm_exec_control;
255 u32 cpu_based_vm_exec_control;
256 u32 exception_bitmap;
257 u32 page_fault_error_code_mask;
258 u32 page_fault_error_code_match;
259 u32 cr3_target_count;
260 u32 vm_exit_controls;
261 u32 vm_exit_msr_store_count;
262 u32 vm_exit_msr_load_count;
263 u32 vm_entry_controls;
264 u32 vm_entry_msr_load_count;
265 u32 vm_entry_intr_info_field;
266 u32 vm_entry_exception_error_code;
267 u32 vm_entry_instruction_len;
268 u32 tpr_threshold;
269 u32 secondary_vm_exec_control;
270 u32 vm_instruction_error;
271 u32 vm_exit_reason;
272 u32 vm_exit_intr_info;
273 u32 vm_exit_intr_error_code;
274 u32 idt_vectoring_info_field;
275 u32 idt_vectoring_error_code;
276 u32 vm_exit_instruction_len;
277 u32 vmx_instruction_info;
278 u32 guest_es_limit;
279 u32 guest_cs_limit;
280 u32 guest_ss_limit;
281 u32 guest_ds_limit;
282 u32 guest_fs_limit;
283 u32 guest_gs_limit;
284 u32 guest_ldtr_limit;
285 u32 guest_tr_limit;
286 u32 guest_gdtr_limit;
287 u32 guest_idtr_limit;
288 u32 guest_es_ar_bytes;
289 u32 guest_cs_ar_bytes;
290 u32 guest_ss_ar_bytes;
291 u32 guest_ds_ar_bytes;
292 u32 guest_fs_ar_bytes;
293 u32 guest_gs_ar_bytes;
294 u32 guest_ldtr_ar_bytes;
295 u32 guest_tr_ar_bytes;
296 u32 guest_interruptibility_info;
297 u32 guest_activity_state;
298 u32 guest_sysenter_cs;
299 u32 host_ia32_sysenter_cs;
300 u32 padding32[8]; /* room for future expansion */
301 u16 virtual_processor_id;
302 u16 guest_es_selector;
303 u16 guest_cs_selector;
304 u16 guest_ss_selector;
305 u16 guest_ds_selector;
306 u16 guest_fs_selector;
307 u16 guest_gs_selector;
308 u16 guest_ldtr_selector;
309 u16 guest_tr_selector;
310 u16 host_es_selector;
311 u16 host_cs_selector;
312 u16 host_ss_selector;
313 u16 host_ds_selector;
314 u16 host_fs_selector;
315 u16 host_gs_selector;
316 u16 host_tr_selector;
a9d30f33
NHE		 317};
318
319/*
320 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
321 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
322 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
323 */
324#define VMCS12_REVISION 0x11e57ed0
325
326/*
327 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
328 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
329 * current implementation, 4K are reserved to avoid future complications.
330 */
331#define VMCS12_SIZE 0x1000
332
ff2f6fe9
NHE		 333/* Used to remember the last vmcs02 used for some recently used vmcs12s */
334struct vmcs02_list {
335 struct list_head list;
336 gpa_t vmptr;
337 struct loaded_vmcs vmcs02;
338};
339
ec378aee
NHE		 340/*
341 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
342 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
343 */
344struct nested_vmx {
345 /* Has the level1 guest done vmxon? */
346 bool vmxon;
a9d30f33
NHE		 347
348 /* The guest-physical address of the current VMCS L1 keeps for L2 */
349 gpa_t current_vmptr;
350 /* The host-usable pointer to the above */
351 struct page *current_vmcs12_page;
352 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 353
354 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
355 struct list_head vmcs02_pool;
356 int vmcs02_num;
fe3ef05c 357 u64 vmcs01_tsc_offset;
644d711a
NHE		 358 /* L2 must run next, and mustn't decide to exit to L1. */
359 bool nested_run_pending;
fe3ef05c
NHE		 360 /*
361 * Guest pages referred to in vmcs02 with host-physical pointers, so
362 * we must keep them pinned while L2 runs.
363 */
364 struct page *apic_access_page;
ec378aee
NHE		 365};
366
a2fa3e9f 367struct vcpu_vmx {
fb3f0f51 368 struct kvm_vcpu vcpu;
313dbd49 369 unsigned long host_rsp;
29bd8a78 370 u8 fail;
69c73028 371 u8 cpl;
9d58b931 372 bool nmi_known_unmasked;
51aa01d1 373 u32 exit_intr_info;
1155f76a 374 u32 idt_vectoring_info;
6de12732 375 ulong rflags;
26bb0981 376 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 377 int nmsrs;
378 int save_nmsrs;
a2fa3e9f 379#ifdef CONFIG_X86_64
44ea2b17
AK		 380 u64 msr_host_kernel_gs_base;
381 u64 msr_guest_kernel_gs_base;
a2fa3e9f 382#endif
d462b819
NHE		 383 /*
384 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
385 * non-nested (L1) guest, it always points to vmcs01. For a nested
386 * guest (L2), it points to a different VMCS.
387 */
388 struct loaded_vmcs vmcs01;
389 struct loaded_vmcs *loaded_vmcs;
390 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 391 struct msr_autoload {
392 unsigned nr;
393 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
394 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
395 } msr_autoload;
a2fa3e9f
GH		 396 struct {
397 int loaded;
398 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 399#ifdef CONFIG_X86_64
400 u16 ds_sel, es_sel;
401#endif
152d3f2f
LV		 402 int gs_ldt_reload_needed;
403 int fs_reload_needed;
d77c26fc 404 } host_state;
9c8cba37 405 struct {
7ffd92c5 406 int vm86_active;
78ac8b47 407 ulong save_rflags;
7ffd92c5
AK		 408 struct kvm_save_segment {
409 u16 selector;
410 unsigned long base;
411 u32 limit;
412 u32 ar;
413 } tr, es, ds, fs, gs;
9c8cba37 414 } rmode;
2fb92db1
AK		 415 struct {
416 u32 bitmask; /* 4 bits per segment (1 bit per field) */
417 struct kvm_save_segment seg[8];
418 } segment_cache;
2384d2b3 419 int vpid;
04fa4d32 420 bool emulation_required;
3b86cd99
JK		 421
422 /* Support for vnmi-less CPUs */
423 int soft_vnmi_blocked;
424 ktime_t entry_time;
425 s64 vnmi_blocked_time;
a0861c02 426 u32 exit_reason;
4e47c7a6
SY		 427
428 bool rdtscp_enabled;
ec378aee
NHE		 429
430 /* Support for a guest hypervisor (nested VMX) */
431 struct nested_vmx nested;
a2fa3e9f
GH		 432};
433
2fb92db1
AK		 434enum segment_cache_field {
435 SEG_FIELD_SEL = 0,
436 SEG_FIELD_BASE = 1,
437 SEG_FIELD_LIMIT = 2,
438 SEG_FIELD_AR = 3,
439
440 SEG_FIELD_NR = 4
441};
442
a2fa3e9f
GH		 443static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
444{
fb3f0f51 445 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 446}
447
22bd0358
NHE		 448#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
449#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
450#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
451 [number##_HIGH] = VMCS12_OFFSET(name)+4
452
453static unsigned short vmcs_field_to_offset_table[] = {
454 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
455 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
456 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
457 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
458 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
459 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
460 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
461 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
462 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
463 FIELD(HOST_ES_SELECTOR, host_es_selector),
464 FIELD(HOST_CS_SELECTOR, host_cs_selector),
465 FIELD(HOST_SS_SELECTOR, host_ss_selector),
466 FIELD(HOST_DS_SELECTOR, host_ds_selector),
467 FIELD(HOST_FS_SELECTOR, host_fs_selector),
468 FIELD(HOST_GS_SELECTOR, host_gs_selector),
469 FIELD(HOST_TR_SELECTOR, host_tr_selector),
470 FIELD64(IO_BITMAP_A, io_bitmap_a),
471 FIELD64(IO_BITMAP_B, io_bitmap_b),
472 FIELD64(MSR_BITMAP, msr_bitmap),
473 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
474 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
475 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
476 FIELD64(TSC_OFFSET, tsc_offset),
477 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
478 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
479 FIELD64(EPT_POINTER, ept_pointer),
480 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
481 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
482 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
483 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
484 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
485 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
486 FIELD64(GUEST_PDPTR0, guest_pdptr0),
487 FIELD64(GUEST_PDPTR1, guest_pdptr1),
488 FIELD64(GUEST_PDPTR2, guest_pdptr2),
489 FIELD64(GUEST_PDPTR3, guest_pdptr3),
490 FIELD64(HOST_IA32_PAT, host_ia32_pat),
491 FIELD64(HOST_IA32_EFER, host_ia32_efer),
492 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
493 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
494 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
495 FIELD(EXCEPTION_BITMAP, exception_bitmap),
496 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
497 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
498 FIELD(CR3_TARGET_COUNT, cr3_target_count),
499 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
500 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
501 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
502 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
503 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
504 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
505 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
506 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
507 FIELD(TPR_THRESHOLD, tpr_threshold),
508 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
509 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
510 FIELD(VM_EXIT_REASON, vm_exit_reason),
511 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
512 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
513 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
514 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
515 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
516 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
517 FIELD(GUEST_ES_LIMIT, guest_es_limit),
518 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
519 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
520 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
521 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
522 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
523 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
524 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
525 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
526 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
527 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
528 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
529 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
530 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
531 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
532 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
533 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
534 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
535 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
536 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
537 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
538 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
539 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
540 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
541 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
542 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
543 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
544 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
545 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
546 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
547 FIELD(EXIT_QUALIFICATION, exit_qualification),
548 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
549 FIELD(GUEST_CR0, guest_cr0),
550 FIELD(GUEST_CR3, guest_cr3),
551 FIELD(GUEST_CR4, guest_cr4),
552 FIELD(GUEST_ES_BASE, guest_es_base),
553 FIELD(GUEST_CS_BASE, guest_cs_base),
554 FIELD(GUEST_SS_BASE, guest_ss_base),
555 FIELD(GUEST_DS_BASE, guest_ds_base),
556 FIELD(GUEST_FS_BASE, guest_fs_base),
557 FIELD(GUEST_GS_BASE, guest_gs_base),
558 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
559 FIELD(GUEST_TR_BASE, guest_tr_base),
560 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
561 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
562 FIELD(GUEST_DR7, guest_dr7),
563 FIELD(GUEST_RSP, guest_rsp),
564 FIELD(GUEST_RIP, guest_rip),
565 FIELD(GUEST_RFLAGS, guest_rflags),
566 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
567 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
568 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
569 FIELD(HOST_CR0, host_cr0),
570 FIELD(HOST_CR3, host_cr3),
571 FIELD(HOST_CR4, host_cr4),
572 FIELD(HOST_FS_BASE, host_fs_base),
573 FIELD(HOST_GS_BASE, host_gs_base),
574 FIELD(HOST_TR_BASE, host_tr_base),
575 FIELD(HOST_GDTR_BASE, host_gdtr_base),
576 FIELD(HOST_IDTR_BASE, host_idtr_base),
577 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
578 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
579 FIELD(HOST_RSP, host_rsp),
580 FIELD(HOST_RIP, host_rip),
581};
582static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
583
584static inline short vmcs_field_to_offset(unsigned long field)
585{
586 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
587 return -1;
588 return vmcs_field_to_offset_table[field];
589}
590
a9d30f33
NHE		 591static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
592{
593 return to_vmx(vcpu)->nested.current_vmcs12;
594}
595
596static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
597{
598 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
599 if (is_error_page(page)) {
600 kvm_release_page_clean(page);
601 return NULL;
602 }
603 return page;
604}
605
606static void nested_release_page(struct page *page)
607{
608 kvm_release_page_dirty(page);
609}
610
611static void nested_release_page_clean(struct page *page)
612{
613 kvm_release_page_clean(page);
614}
615
4e1096d2 616static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 617static void kvm_cpu_vmxon(u64 addr);
618static void kvm_cpu_vmxoff(void);
aff48baa 619static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 620static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 621static void vmx_set_segment(struct kvm_vcpu *vcpu,
622 struct kvm_segment *var, int seg);
623static void vmx_get_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
75880a01 625
6aa8b732
AK		 626static DEFINE_PER_CPU(struct vmcs *, vmxarea);
627static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 628/*
629 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
630 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
631 */
632static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 633static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 634
3e7c73e9
AK		 635static unsigned long *vmx_io_bitmap_a;
636static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 637static unsigned long *vmx_msr_bitmap_legacy;
638static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 639
110312c8 640static bool cpu_has_load_ia32_efer;
8bf00a52 641static bool cpu_has_load_perf_global_ctrl;
110312c8 642
2384d2b3
SY		 643static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
644static DEFINE_SPINLOCK(vmx_vpid_lock);
645
1c3d14fe 646static struct vmcs_config {
6aa8b732
AK		 647 int size;
648 int order;
649 u32 revision_id;
1c3d14fe
YS		 650 u32 pin_based_exec_ctrl;
651 u32 cpu_based_exec_ctrl;
f78e0e2e 652 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 653 u32 vmexit_ctrl;
654 u32 vmentry_ctrl;
655} vmcs_config;
6aa8b732 656
efff9e53 657static struct vmx_capability {
d56f546d
SY		 658 u32 ept;
659 u32 vpid;
660} vmx_capability;
661
6aa8b732
AK		 662#define VMX_SEGMENT_FIELD(seg) \
663 [VCPU_SREG_##seg] = { \
664 .selector = GUEST_##seg##_SELECTOR, \
665 .base = GUEST_##seg##_BASE, \
666 .limit = GUEST_##seg##_LIMIT, \
667 .ar_bytes = GUEST_##seg##_AR_BYTES, \
668 }
669
670static struct kvm_vmx_segment_field {
671 unsigned selector;
672 unsigned base;
673 unsigned limit;
674 unsigned ar_bytes;
675} kvm_vmx_segment_fields[] = {
676 VMX_SEGMENT_FIELD(CS),
677 VMX_SEGMENT_FIELD(DS),
678 VMX_SEGMENT_FIELD(ES),
679 VMX_SEGMENT_FIELD(FS),
680 VMX_SEGMENT_FIELD(GS),
681 VMX_SEGMENT_FIELD(SS),
682 VMX_SEGMENT_FIELD(TR),
683 VMX_SEGMENT_FIELD(LDTR),
684};
685
26bb0981
AK		 686static u64 host_efer;
687
6de4f3ad
AK		 688static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
689
4d56c8a7 690/*
8c06585d 691 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 692 * away by decrementing the array size.
693 */
6aa8b732 694static const u32 vmx_msr_index[] = {
05b3e0c2 695#ifdef CONFIG_X86_64
44ea2b17 696 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 697#endif
8c06585d 698 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 699};
9d8f549d 700#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 701
31299944 702static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 703{
704 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
705 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 706 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 707}
708
31299944 709static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 710{
711 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
712 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 713 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 714}
715
31299944 716static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 717{
718 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
719 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 720 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 721}
722
31299944 723static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 724{
725 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
726 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
727}
728
31299944 729static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 730{
731 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
732 INTR_INFO_VALID_MASK)) ==
733 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
734}
735
31299944 736static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 737{
04547156 738 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 739}
740
31299944 741static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 742{
04547156 743 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 744}
745
31299944 746static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 747{
04547156 748 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 749}
750
31299944 751static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 752{
04547156
SY		 753 return vmcs_config.cpu_based_exec_ctrl &
754 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 755}
756
774ead3a 757static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 758{
04547156
SY		 759 return vmcs_config.cpu_based_2nd_exec_ctrl &
760 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
761}
762
763static inline bool cpu_has_vmx_flexpriority(void)
764{
765 return cpu_has_vmx_tpr_shadow() &&
766 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 767}
768
e799794e
MT		 769static inline bool cpu_has_vmx_ept_execute_only(void)
770{
31299944 771 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 772}
773
774static inline bool cpu_has_vmx_eptp_uncacheable(void)
775{
31299944 776 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 777}
778
779static inline bool cpu_has_vmx_eptp_writeback(void)
780{
31299944 781 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 782}
783
784static inline bool cpu_has_vmx_ept_2m_page(void)
785{
31299944 786 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 787}
788
878403b7
SY		 789static inline bool cpu_has_vmx_ept_1g_page(void)
790{
31299944 791 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 792}
793
4bc9b982
SY		 794static inline bool cpu_has_vmx_ept_4levels(void)
795{
796 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
797}
798
83c3a331
XH		 799static inline bool cpu_has_vmx_ept_ad_bits(void)
800{
801 return vmx_capability.ept & VMX_EPT_AD_BIT;
802}
803
31299944 804static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 805{
31299944 806 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 807}
808
31299944 809static inline bool cpu_has_vmx_invept_context(void)
d56f546d 810{
31299944 811 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 812}
813
31299944 814static inline bool cpu_has_vmx_invept_global(void)
d56f546d 815{
31299944 816 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 817}
818
518c8aee
GJ		 819static inline bool cpu_has_vmx_invvpid_single(void)
820{
821 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
822}
823
b9d762fa
GJ		 824static inline bool cpu_has_vmx_invvpid_global(void)
825{
826 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
827}
828
31299944 829static inline bool cpu_has_vmx_ept(void)
d56f546d 830{
04547156
SY		 831 return vmcs_config.cpu_based_2nd_exec_ctrl &
832 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 833}
834
31299944 835static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 836{
837 return vmcs_config.cpu_based_2nd_exec_ctrl &
838 SECONDARY_EXEC_UNRESTRICTED_GUEST;
839}
840
31299944 841static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 842{
843 return vmcs_config.cpu_based_2nd_exec_ctrl &
844 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
845}
846
31299944 847static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 848{
6d3e435e 849 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 850}
851
31299944 852static inline bool cpu_has_vmx_vpid(void)
2384d2b3 853{
04547156
SY		 854 return vmcs_config.cpu_based_2nd_exec_ctrl &
855 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 856}
857
31299944 858static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 859{
860 return vmcs_config.cpu_based_2nd_exec_ctrl &
861 SECONDARY_EXEC_RDTSCP;
862}
863
ad756a16
MJ		 864static inline bool cpu_has_vmx_invpcid(void)
865{
866 return vmcs_config.cpu_based_2nd_exec_ctrl &
867 SECONDARY_EXEC_ENABLE_INVPCID;
868}
869
31299944 870static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 871{
872 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
873}
874
f5f48ee1
SY		 875static inline bool cpu_has_vmx_wbinvd_exit(void)
876{
877 return vmcs_config.cpu_based_2nd_exec_ctrl &
878 SECONDARY_EXEC_WBINVD_EXITING;
879}
880
04547156
SY		 881static inline bool report_flexpriority(void)
882{
883 return flexpriority_enabled;
884}
885
fe3ef05c
NHE		 886static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
887{
888 return vmcs12->cpu_based_vm_exec_control & bit;
889}
890
891static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
892{
893 return (vmcs12->cpu_based_vm_exec_control &
894 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
895 (vmcs12->secondary_vm_exec_control & bit);
896}
897
644d711a
NHE		 898static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
899 struct kvm_vcpu *vcpu)
900{
901 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
902}
903
904static inline bool is_exception(u32 intr_info)
905{
906 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
907 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
908}
909
910static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 911static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
912 struct vmcs12 *vmcs12,
913 u32 reason, unsigned long qualification);
914
8b9cf98c 915static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 916{
917 int i;
918
a2fa3e9f 919 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 920 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 921 return i;
922 return -1;
923}
924
2384d2b3
SY		 925static inline void __invvpid(int ext, u16 vpid, gva_t gva)
926{
927 struct {
928 u64 vpid : 16;
929 u64 rsvd : 48;
930 u64 gva;
931 } operand = { vpid, 0, gva };
932
4ecac3fd 933 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 934 /* CF==1 or ZF==1 --> rc = -1 */
935 "; ja 1f ; ud2 ; 1:"
936 : : "a"(&operand), "c"(ext) : "cc", "memory");
937}
938
1439442c
SY		 939static inline void __invept(int ext, u64 eptp, gpa_t gpa)
940{
941 struct {
942 u64 eptp, gpa;
943 } operand = {eptp, gpa};
944
4ecac3fd 945 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 946 /* CF==1 or ZF==1 --> rc = -1 */
947 "; ja 1f ; ud2 ; 1:\n"
948 : : "a" (&operand), "c" (ext) : "cc", "memory");
949}
950
26bb0981 951static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 952{
953 int i;
954
8b9cf98c 955 i = __find_msr_index(vmx, msr);
a75beee6 956 if (i >= 0)
a2fa3e9f 957 return &vmx->guest_msrs[i];
8b6d44c7 958 return NULL;
7725f0ba
AK		 959}
960
6aa8b732
AK		 961static void vmcs_clear(struct vmcs *vmcs)
962{
963 u64 phys_addr = __pa(vmcs);
964 u8 error;
965
4ecac3fd 966 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 967 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 968 : "cc", "memory");
969 if (error)
970 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
971 vmcs, phys_addr);
972}
973
d462b819
NHE		 974static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
975{
976 vmcs_clear(loaded_vmcs->vmcs);
977 loaded_vmcs->cpu = -1;
978 loaded_vmcs->launched = 0;
979}
980
7725b894
DX		 981static void vmcs_load(struct vmcs *vmcs)
982{
983 u64 phys_addr = __pa(vmcs);
984 u8 error;
985
986 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 987 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 988 : "cc", "memory");
989 if (error)
2844d849 990 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 991 vmcs, phys_addr);
992}
993
d462b819 994static void __loaded_vmcs_clear(void *arg)
6aa8b732 995{
d462b819 996 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 997 int cpu = raw_smp_processor_id();
6aa8b732 998
d462b819
NHE		 999 if (loaded_vmcs->cpu != cpu)
1000 return; /* vcpu migration can race with cpu offline */
1001 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1002 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 1003 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1004 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 1005}
1006
d462b819 1007static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1008{
d462b819
NHE		 1009 if (loaded_vmcs->cpu != -1)
1010 smp_call_function_single(
1011 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1012}
1013
1760dd49 1014static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1015{
1016 if (vmx->vpid == 0)
1017 return;
1018
518c8aee
GJ		 1019 if (cpu_has_vmx_invvpid_single())
1020 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1021}
1022
b9d762fa
GJ		 1023static inline void vpid_sync_vcpu_global(void)
1024{
1025 if (cpu_has_vmx_invvpid_global())
1026 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1027}
1028
1029static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1030{
1031 if (cpu_has_vmx_invvpid_single())
1760dd49 1032 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1033 else
1034 vpid_sync_vcpu_global();
1035}
1036
1439442c
SY		 1037static inline void ept_sync_global(void)
1038{
1039 if (cpu_has_vmx_invept_global())
1040 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1041}
1042
1043static inline void ept_sync_context(u64 eptp)
1044{
089d034e 1045 if (enable_ept) {
1439442c
SY		 1046 if (cpu_has_vmx_invept_context())
1047 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1048 else
1049 ept_sync_global();
1050 }
1051}
1052
1053static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1054{
089d034e 1055 if (enable_ept) {
1439442c
SY		 1056 if (cpu_has_vmx_invept_individual_addr())
1057 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1058 eptp, gpa);
1059 else
1060 ept_sync_context(eptp);
1061 }
1062}
1063
96304217 1064static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1065{
5e520e62 1066 unsigned long value;
6aa8b732 1067
5e520e62
AK		 1068 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1069 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1070 return value;
1071}
1072
96304217 1073static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1074{
1075 return vmcs_readl(field);
1076}
1077
96304217 1078static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1079{
1080 return vmcs_readl(field);
1081}
1082
96304217 1083static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1084{
05b3e0c2 1085#ifdef CONFIG_X86_64
6aa8b732
AK		 1086 return vmcs_readl(field);
1087#else
1088 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1089#endif
1090}
1091
e52de1b8
AK		 1092static noinline void vmwrite_error(unsigned long field, unsigned long value)
1093{
1094 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1095 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1096 dump_stack();
1097}
1098
6aa8b732
AK		 1099static void vmcs_writel(unsigned long field, unsigned long value)
1100{
1101 u8 error;
1102
4ecac3fd 1103 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1104 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1105 if (unlikely(error))
1106 vmwrite_error(field, value);
6aa8b732
AK		 1107}
1108
1109static void vmcs_write16(unsigned long field, u16 value)
1110{
1111 vmcs_writel(field, value);
1112}
1113
1114static void vmcs_write32(unsigned long field, u32 value)
1115{
1116 vmcs_writel(field, value);
1117}
1118
1119static void vmcs_write64(unsigned long field, u64 value)
1120{
6aa8b732 1121 vmcs_writel(field, value);
7682f2d0 1122#ifndef CONFIG_X86_64
6aa8b732
AK		 1123 asm volatile ("");
1124 vmcs_writel(field+1, value >> 32);
1125#endif
1126}
1127
2ab455cc
AL		 1128static void vmcs_clear_bits(unsigned long field, u32 mask)
1129{
1130 vmcs_writel(field, vmcs_readl(field) & ~mask);
1131}
1132
1133static void vmcs_set_bits(unsigned long field, u32 mask)
1134{
1135 vmcs_writel(field, vmcs_readl(field) | mask);
1136}
1137
2fb92db1
AK		 1138static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1139{
1140 vmx->segment_cache.bitmask = 0;
1141}
1142
1143static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1144 unsigned field)
1145{
1146 bool ret;
1147 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1148
1149 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1150 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1151 vmx->segment_cache.bitmask = 0;
1152 }
1153 ret = vmx->segment_cache.bitmask & mask;
1154 vmx->segment_cache.bitmask |= mask;
1155 return ret;
1156}
1157
1158static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1159{
1160 u16 *p = &vmx->segment_cache.seg[seg].selector;
1161
1162 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1163 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1164 return *p;
1165}
1166
1167static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1168{
1169 ulong *p = &vmx->segment_cache.seg[seg].base;
1170
1171 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1172 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1173 return *p;
1174}
1175
1176static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1177{
1178 u32 *p = &vmx->segment_cache.seg[seg].limit;
1179
1180 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1181 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1182 return *p;
1183}
1184
1185static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1186{
1187 u32 *p = &vmx->segment_cache.seg[seg].ar;
1188
1189 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1190 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1191 return *p;
1192}
1193
abd3f2d6
AK		 1194static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1195{
1196 u32 eb;
1197
fd7373cc
JK		 1198 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1199 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1200 if ((vcpu->guest_debug &
1201 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1202 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1203 eb |= 1u << BP_VECTOR;
7ffd92c5 1204 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1205 eb = ~0;
089d034e 1206 if (enable_ept)
1439442c 1207 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1208 if (vcpu->fpu_active)
1209 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1210
1211 /* When we are running a nested L2 guest and L1 specified for it a
1212 * certain exception bitmap, we must trap the same exceptions and pass
1213 * them to L1. When running L2, we will only handle the exceptions
1214 * specified above if L1 did not want them.
1215 */
1216 if (is_guest_mode(vcpu))
1217 eb |= get_vmcs12(vcpu)->exception_bitmap;
1218
abd3f2d6
AK		 1219 vmcs_write32(EXCEPTION_BITMAP, eb);
1220}
1221
8bf00a52
GN		 1222static void clear_atomic_switch_msr_special(unsigned long entry,
1223 unsigned long exit)
1224{
1225 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1226 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1227}
1228
61d2ef2c
AK		 1229static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1230{
1231 unsigned i;
1232 struct msr_autoload *m = &vmx->msr_autoload;
1233
8bf00a52
GN		 1234 switch (msr) {
1235 case MSR_EFER:
1236 if (cpu_has_load_ia32_efer) {
1237 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1238 VM_EXIT_LOAD_IA32_EFER);
1239 return;
1240 }
1241 break;
1242 case MSR_CORE_PERF_GLOBAL_CTRL:
1243 if (cpu_has_load_perf_global_ctrl) {
1244 clear_atomic_switch_msr_special(
1245 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1246 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1247 return;
1248 }
1249 break;
110312c8
AK		 1250 }
1251
61d2ef2c
AK		 1252 for (i = 0; i < m->nr; ++i)
1253 if (m->guest[i].index == msr)
1254 break;
1255
1256 if (i == m->nr)
1257 return;
1258 --m->nr;
1259 m->guest[i] = m->guest[m->nr];
1260 m->host[i] = m->host[m->nr];
1261 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1262 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1263}
1264
8bf00a52
GN		 1265static void add_atomic_switch_msr_special(unsigned long entry,
1266 unsigned long exit, unsigned long guest_val_vmcs,
1267 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1268{
1269 vmcs_write64(guest_val_vmcs, guest_val);
1270 vmcs_write64(host_val_vmcs, host_val);
1271 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1272 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1273}
1274
61d2ef2c
AK		 1275static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1276 u64 guest_val, u64 host_val)
1277{
1278 unsigned i;
1279 struct msr_autoload *m = &vmx->msr_autoload;
1280
8bf00a52
GN		 1281 switch (msr) {
1282 case MSR_EFER:
1283 if (cpu_has_load_ia32_efer) {
1284 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1285 VM_EXIT_LOAD_IA32_EFER,
1286 GUEST_IA32_EFER,
1287 HOST_IA32_EFER,
1288 guest_val, host_val);
1289 return;
1290 }
1291 break;
1292 case MSR_CORE_PERF_GLOBAL_CTRL:
1293 if (cpu_has_load_perf_global_ctrl) {
1294 add_atomic_switch_msr_special(
1295 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1296 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1297 GUEST_IA32_PERF_GLOBAL_CTRL,
1298 HOST_IA32_PERF_GLOBAL_CTRL,
1299 guest_val, host_val);
1300 return;
1301 }
1302 break;
110312c8
AK		 1303 }
1304
61d2ef2c
AK		 1305 for (i = 0; i < m->nr; ++i)
1306 if (m->guest[i].index == msr)
1307 break;
1308
e7fc6f93
GN		 1309 if (i == NR_AUTOLOAD_MSRS) {
1310 printk_once(KERN_WARNING"Not enough mst switch entries. "
1311 "Can't add msr %x\n", msr);
1312 return;
1313 } else if (i == m->nr) {
61d2ef2c
AK		 1314 ++m->nr;
1315 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1316 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1317 }
1318
1319 m->guest[i].index = msr;
1320 m->guest[i].value = guest_val;
1321 m->host[i].index = msr;
1322 m->host[i].value = host_val;
1323}
1324
33ed6329
AK		 1325static void reload_tss(void)
1326{
33ed6329
AK		 1327 /*
1328 * VT restores TR but not its size. Useless.
1329 */
d359192f 1330 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1331 struct desc_struct *descs;
33ed6329 1332
d359192f 1333 descs = (void *)gdt->address;
33ed6329
AK		 1334 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1335 load_TR_desc();
33ed6329
AK		 1336}
1337
92c0d900 1338static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1339{
3a34a881 1340 u64 guest_efer;
51c6cf66
AK		 1341 u64 ignore_bits;
1342
f6801dff 1343 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1344
51c6cf66
AK		 1345 /*
1346 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1347 * outside long mode
1348 */
1349 ignore_bits = EFER_NX | EFER_SCE;
1350#ifdef CONFIG_X86_64
1351 ignore_bits |= EFER_LMA | EFER_LME;
1352 /* SCE is meaningful only in long mode on Intel */
1353 if (guest_efer & EFER_LMA)
1354 ignore_bits &= ~(u64)EFER_SCE;
1355#endif
51c6cf66
AK		 1356 guest_efer &= ~ignore_bits;
1357 guest_efer |= host_efer & ignore_bits;
26bb0981 1358 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1359 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1360
1361 clear_atomic_switch_msr(vmx, MSR_EFER);
1362 /* On ept, can't emulate nx, and must switch nx atomically */
1363 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1364 guest_efer = vmx->vcpu.arch.efer;
1365 if (!(guest_efer & EFER_LMA))
1366 guest_efer &= ~EFER_LME;
1367 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1368 return false;
1369 }
1370
26bb0981 1371 return true;
51c6cf66
AK		 1372}
1373
2d49ec72
GN		 1374static unsigned long segment_base(u16 selector)
1375{
d359192f 1376 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1377 struct desc_struct *d;
1378 unsigned long table_base;
1379 unsigned long v;
1380
1381 if (!(selector & ~3))
1382 return 0;
1383
d359192f 1384 table_base = gdt->address;
2d49ec72
GN		 1385
1386 if (selector & 4) { /* from ldt */
1387 u16 ldt_selector = kvm_read_ldt();
1388
1389 if (!(ldt_selector & ~3))
1390 return 0;
1391
1392 table_base = segment_base(ldt_selector);
1393 }
1394 d = (struct desc_struct *)(table_base + (selector & ~7));
1395 v = get_desc_base(d);
1396#ifdef CONFIG_X86_64
1397 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1398 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1399#endif
1400 return v;
1401}
1402
1403static inline unsigned long kvm_read_tr_base(void)
1404{
1405 u16 tr;
1406 asm("str %0" : "=g"(tr));
1407 return segment_base(tr);
1408}
1409
04d2cc77 1410static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1411{
04d2cc77 1412 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1413 int i;
04d2cc77 1414
a2fa3e9f 1415 if (vmx->host_state.loaded)
33ed6329
AK		 1416 return;
1417
a2fa3e9f 1418 vmx->host_state.loaded = 1;
33ed6329
AK		 1419 /*
1420 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1421 * allow segment selectors with cpl > 0 or ti == 1.
1422 */
d6e88aec 1423 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1424 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1425 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1426 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1427 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1428 vmx->host_state.fs_reload_needed = 0;
1429 } else {
33ed6329 1430 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1431 vmx->host_state.fs_reload_needed = 1;
33ed6329 1432 }
9581d442 1433 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1434 if (!(vmx->host_state.gs_sel & 7))
1435 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1436 else {
1437 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1438 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1439 }
1440
b2da15ac
AK		 1441#ifdef CONFIG_X86_64
1442 savesegment(ds, vmx->host_state.ds_sel);
1443 savesegment(es, vmx->host_state.es_sel);
1444#endif
1445
33ed6329
AK		 1446#ifdef CONFIG_X86_64
1447 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1448 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1449#else
a2fa3e9f
GH		 1450 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1451 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1452#endif
707c0874
AK		 1453
1454#ifdef CONFIG_X86_64
c8770e7b
AK		 1455 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1456 if (is_long_mode(&vmx->vcpu))
44ea2b17 1457 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1458#endif
26bb0981
AK		 1459 for (i = 0; i < vmx->save_nmsrs; ++i)
1460 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1461 vmx->guest_msrs[i].data,
1462 vmx->guest_msrs[i].mask);
33ed6329
AK		 1463}
1464
a9b21b62 1465static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1466{
a2fa3e9f 1467 if (!vmx->host_state.loaded)
33ed6329
AK		 1468 return;
1469
e1beb1d3 1470 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1471 vmx->host_state.loaded = 0;
c8770e7b
AK		 1472#ifdef CONFIG_X86_64
1473 if (is_long_mode(&vmx->vcpu))
1474 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1475#endif
152d3f2f 1476 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1477 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1478#ifdef CONFIG_X86_64
9581d442 1479 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1480#else
1481 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1482#endif
33ed6329 1483 }
0a77fe4c
AK		 1484 if (vmx->host_state.fs_reload_needed)
1485 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1486#ifdef CONFIG_X86_64
1487 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1488 loadsegment(ds, vmx->host_state.ds_sel);
1489 loadsegment(es, vmx->host_state.es_sel);
1490 }
1491#else
1492 /*
1493 * The sysexit path does not restore ds/es, so we must set them to
1494 * a reasonable value ourselves.
1495 */
1496 loadsegment(ds, __USER_DS);
1497 loadsegment(es, __USER_DS);
1498#endif
152d3f2f 1499 reload_tss();
44ea2b17 1500#ifdef CONFIG_X86_64
c8770e7b 1501 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1502#endif
1361b83a 1503 if (user_has_fpu())
1c11e713 1504 clts();
3444d7da 1505 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1506}
1507
a9b21b62
AK		 1508static void vmx_load_host_state(struct vcpu_vmx *vmx)
1509{
1510 preempt_disable();
1511 __vmx_load_host_state(vmx);
1512 preempt_enable();
1513}
1514
6aa8b732
AK		 1515/*
1516 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1517 * vcpu mutex is already taken.
1518 */
15ad7146 1519static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1520{
a2fa3e9f 1521 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1522 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1523
4610c9cc
DX		 1524 if (!vmm_exclusive)
1525 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1526 else if (vmx->loaded_vmcs->cpu != cpu)
1527 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1528
d462b819
NHE		 1529 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1530 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1531 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1532 }
1533
d462b819 1534 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1535 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1536 unsigned long sysenter_esp;
1537
a8eeb04a 1538 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1539 local_irq_disable();
d462b819
NHE		 1540 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1541 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1542 local_irq_enable();
1543
6aa8b732
AK		 1544 /*
1545 * Linux uses per-cpu TSS and GDT, so set these when switching
1546 * processors.
1547 */
d6e88aec 1548 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1549 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1550
1551 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1552 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1553 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1554 }
6aa8b732
AK		 1555}
1556
1557static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1558{
a9b21b62 1559 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1560 if (!vmm_exclusive) {
d462b819
NHE		 1561 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1562 vcpu->cpu = -1;
4610c9cc
DX		 1563 kvm_cpu_vmxoff();
1564 }
6aa8b732
AK		 1565}
1566
5fd86fcf
AK		 1567static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1568{
81231c69
AK		 1569 ulong cr0;
1570
5fd86fcf
AK		 1571 if (vcpu->fpu_active)
1572 return;
1573 vcpu->fpu_active = 1;
81231c69
AK		 1574 cr0 = vmcs_readl(GUEST_CR0);
1575 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1576 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1577 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1578 update_exception_bitmap(vcpu);
edcafe3c 1579 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1580 if (is_guest_mode(vcpu))
1581 vcpu->arch.cr0_guest_owned_bits &=
1582 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1583 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1584}
1585
edcafe3c
AK		 1586static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1587
fe3ef05c
NHE		 1588/*
1589 * Return the cr0 value that a nested guest would read. This is a combination
1590 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1591 * its hypervisor (cr0_read_shadow).
1592 */
1593static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1594{
1595 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1596 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1597}
1598static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1599{
1600 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1601 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1602}
1603
5fd86fcf
AK		 1604static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1605{
36cf24e0
NHE		 1606 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1607 * set this *before* calling this function.
1608 */
edcafe3c 1609 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1610 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1611 update_exception_bitmap(vcpu);
edcafe3c
AK		 1612 vcpu->arch.cr0_guest_owned_bits = 0;
1613 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1614 if (is_guest_mode(vcpu)) {
1615 /*
1616 * L1's specified read shadow might not contain the TS bit,
1617 * so now that we turned on shadowing of this bit, we need to
1618 * set this bit of the shadow. Like in nested_vmx_run we need
1619 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1620 * up-to-date here because we just decached cr0.TS (and we'll
1621 * only update vmcs12->guest_cr0 on nested exit).
1622 */
1623 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1624 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1625 (vcpu->arch.cr0 & X86_CR0_TS);
1626 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1627 } else
1628 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1629}
1630
6aa8b732
AK		 1631static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1632{
78ac8b47 1633 unsigned long rflags, save_rflags;
345dcaa8 1634
6de12732
AK		 1635 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1636 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1637 rflags = vmcs_readl(GUEST_RFLAGS);
1638 if (to_vmx(vcpu)->rmode.vm86_active) {
1639 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1640 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1641 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1642 }
1643 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1644 }
6de12732 1645 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1646}
1647
1648static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1649{
6de12732 1650 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1651 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1652 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1653 if (to_vmx(vcpu)->rmode.vm86_active) {
1654 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1655 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1656 }
6aa8b732
AK		 1657 vmcs_writel(GUEST_RFLAGS, rflags);
1658}
1659
2809f5d2
GC		 1660static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1661{
1662 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1663 int ret = 0;
1664
1665 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1666 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1667 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1668 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1669
1670 return ret & mask;
1671}
1672
1673static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1674{
1675 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1676 u32 interruptibility = interruptibility_old;
1677
1678 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1679
48005f64 1680 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1681 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1682 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1683 interruptibility |= GUEST_INTR_STATE_STI;
1684
1685 if ((interruptibility != interruptibility_old))
1686 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1687}
1688
6aa8b732
AK		 1689static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1690{
1691 unsigned long rip;
6aa8b732 1692
5fdbf976 1693 rip = kvm_rip_read(vcpu);
6aa8b732 1694 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1695 kvm_rip_write(vcpu, rip);
6aa8b732 1696
2809f5d2
GC		 1697 /* skipping an emulated instruction also counts */
1698 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1699}
1700
0b6ac343
NHE		 1701/*
1702 * KVM wants to inject page-faults which it got to the guest. This function
1703 * checks whether in a nested guest, we need to inject them to L1 or L2.
1704 * This function assumes it is called with the exit reason in vmcs02 being
1705 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1706 * is running).
1707 */
1708static int nested_pf_handled(struct kvm_vcpu *vcpu)
1709{
1710 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1711
1712 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1713 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1714 return 0;
1715
1716 nested_vmx_vmexit(vcpu);
1717 return 1;
1718}
1719
298101da 1720static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1721 bool has_error_code, u32 error_code,
1722 bool reinject)
298101da 1723{
77ab6db0 1724 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1725 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1726
0b6ac343
NHE		 1727 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1728 nested_pf_handled(vcpu))
1729 return;
1730
8ab2d2e2 1731 if (has_error_code) {
77ab6db0 1732 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1733 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1734 }
77ab6db0 1735
7ffd92c5 1736 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1737 int inc_eip = 0;
1738 if (kvm_exception_is_soft(nr))
1739 inc_eip = vcpu->arch.event_exit_inst_len;
1740 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1741 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1742 return;
1743 }
1744
66fd3f7f
GN		 1745 if (kvm_exception_is_soft(nr)) {
1746 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1747 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1748 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1749 } else
1750 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1751
1752 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1753}
1754
4e47c7a6
SY		 1755static bool vmx_rdtscp_supported(void)
1756{
1757 return cpu_has_vmx_rdtscp();
1758}
1759
ad756a16
MJ		 1760static bool vmx_invpcid_supported(void)
1761{
1762 return cpu_has_vmx_invpcid() && enable_ept;
1763}
1764
a75beee6
ED		 1765/*
1766 * Swap MSR entry in host/guest MSR entry array.
1767 */
8b9cf98c 1768static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1769{
26bb0981 1770 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1771
1772 tmp = vmx->guest_msrs[to];
1773 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1774 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1775}
1776
e38aea3e
AK		 1777/*
1778 * Set up the vmcs to automatically save and restore system
1779 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1780 * mode, as fiddling with msrs is very expensive.
1781 */
8b9cf98c 1782static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1783{
26bb0981 1784 int save_nmsrs, index;
5897297b 1785 unsigned long *msr_bitmap;
e38aea3e 1786
a75beee6
ED		 1787 save_nmsrs = 0;
1788#ifdef CONFIG_X86_64
8b9cf98c 1789 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1790 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1791 if (index >= 0)
8b9cf98c
RR		 1792 move_msr_up(vmx, index, save_nmsrs++);
1793 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1794 if (index >= 0)
8b9cf98c
RR		 1795 move_msr_up(vmx, index, save_nmsrs++);
1796 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1797 if (index >= 0)
8b9cf98c 1798 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1799 index = __find_msr_index(vmx, MSR_TSC_AUX);
1800 if (index >= 0 && vmx->rdtscp_enabled)
1801 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1802 /*
8c06585d 1803 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1804 * if efer.sce is enabled.
1805 */
8c06585d 1806 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1807 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1808 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1809 }
1810#endif
92c0d900
AK		 1811 index = __find_msr_index(vmx, MSR_EFER);
1812 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1813 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1814
26bb0981 1815 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1816
1817 if (cpu_has_vmx_msr_bitmap()) {
1818 if (is_long_mode(&vmx->vcpu))
1819 msr_bitmap = vmx_msr_bitmap_longmode;
1820 else
1821 msr_bitmap = vmx_msr_bitmap_legacy;
1822
1823 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1824 }
e38aea3e
AK		 1825}
1826
6aa8b732
AK		 1827/*
1828 * reads and returns guest's timestamp counter "register"
1829 * guest_tsc = host_tsc + tsc_offset -- 21.3
1830 */
1831static u64 guest_read_tsc(void)
1832{
1833 u64 host_tsc, tsc_offset;
1834
1835 rdtscll(host_tsc);
1836 tsc_offset = vmcs_read64(TSC_OFFSET);
1837 return host_tsc + tsc_offset;
1838}
1839
d5c1785d
NHE		 1840/*
1841 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1842 * counter, even if a nested guest (L2) is currently running.
1843 */
1844u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1845{
1846 u64 host_tsc, tsc_offset;
1847
1848 rdtscll(host_tsc);
1849 tsc_offset = is_guest_mode(vcpu) ?
1850 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1851 vmcs_read64(TSC_OFFSET);
1852 return host_tsc + tsc_offset;
1853}
1854
4051b188 1855/*
cc578287
ZA		 1856 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1857 * software catchup for faster rates on slower CPUs.
4051b188 1858 */
cc578287 1859static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1860{
cc578287
ZA		 1861 if (!scale)
1862 return;
1863
1864 if (user_tsc_khz > tsc_khz) {
1865 vcpu->arch.tsc_catchup = 1;
1866 vcpu->arch.tsc_always_catchup = 1;
1867 } else
1868 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1869}
1870
6aa8b732 1871/*
99e3e30a 1872 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1873 */
99e3e30a 1874static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1875{
27fc51b2 1876 if (is_guest_mode(vcpu)) {
7991825b 1877 /*
27fc51b2
NHE		 1878 * We're here if L1 chose not to trap WRMSR to TSC. According
1879 * to the spec, this should set L1's TSC; The offset that L1
1880 * set for L2 remains unchanged, and still needs to be added
1881 * to the newly set TSC to get L2's TSC.
7991825b 1882 */
27fc51b2
NHE		 1883 struct vmcs12 *vmcs12;
1884 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1885 /* recalculate vmcs02.TSC_OFFSET: */
1886 vmcs12 = get_vmcs12(vcpu);
1887 vmcs_write64(TSC_OFFSET, offset +
1888 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1889 vmcs12->tsc_offset : 0));
1890 } else {
1891 vmcs_write64(TSC_OFFSET, offset);
1892 }
6aa8b732
AK		 1893}
1894
f1e2b260 1895static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1896{
1897 u64 offset = vmcs_read64(TSC_OFFSET);
1898 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1899 if (is_guest_mode(vcpu)) {
1900 /* Even when running L2, the adjustment needs to apply to L1 */
1901 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1902 }
e48672fa
ZA		 1903}
1904
857e4099
JR		 1905static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1906{
1907 return target_tsc - native_read_tsc();
1908}
1909
801d3424
NHE		 1910static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1911{
1912 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1913 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1914}
1915
1916/*
1917 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1918 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1919 * all guests if the "nested" module option is off, and can also be disabled
1920 * for a single guest by disabling its VMX cpuid bit.
1921 */
1922static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1923{
1924 return nested && guest_cpuid_has_vmx(vcpu);
1925}
1926
b87a51ae
NHE		 1927/*
1928 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1929 * returned for the various VMX controls MSRs when nested VMX is enabled.
1930 * The same values should also be used to verify that vmcs12 control fields are
1931 * valid during nested entry from L1 to L2.
1932 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1933 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1934 * bit in the high half is on if the corresponding bit in the control field
1935 * may be on. See also vmx_control_verify().
1936 * TODO: allow these variables to be modified (downgraded) by module options
1937 * or other means.
1938 */
1939static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1940static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1941static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1942static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1943static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1944static __init void nested_vmx_setup_ctls_msrs(void)
1945{
1946 /*
1947 * Note that as a general rule, the high half of the MSRs (bits in
1948 * the control fields which may be 1) should be initialized by the
1949 * intersection of the underlying hardware's MSR (i.e., features which
1950 * can be supported) and the list of features we want to expose -
1951 * because they are known to be properly supported in our code.
1952 * Also, usually, the low half of the MSRs (bits which must be 1) can
1953 * be set to 0, meaning that L1 may turn off any of these bits. The
1954 * reason is that if one of these bits is necessary, it will appear
1955 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1956 * fields of vmcs01 and vmcs02, will turn these bits off - and
1957 * nested_vmx_exit_handled() will not pass related exits to L1.
1958 * These rules have exceptions below.
1959 */
1960
1961 /* pin-based controls */
1962 /*
1963 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1964 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1965 */
1966 nested_vmx_pinbased_ctls_low = 0x16 ;
1967 nested_vmx_pinbased_ctls_high = 0x16 |
1968 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1969 PIN_BASED_VIRTUAL_NMIS;
1970
1971 /* exit controls */
1972 nested_vmx_exit_ctls_low = 0;
b6f1250e 1973 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1974#ifdef CONFIG_X86_64
1975 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1976#else
1977 nested_vmx_exit_ctls_high = 0;
1978#endif
1979
1980 /* entry controls */
1981 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1982 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1983 nested_vmx_entry_ctls_low = 0;
1984 nested_vmx_entry_ctls_high &=
1985 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1986
1987 /* cpu-based controls */
1988 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1989 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1990 nested_vmx_procbased_ctls_low = 0;
1991 nested_vmx_procbased_ctls_high &=
1992 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1993 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1994 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1995 CPU_BASED_CR3_STORE_EXITING |
1996#ifdef CONFIG_X86_64
1997 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1998#endif
1999 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2000 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
fee84b07 2001 CPU_BASED_RDPMC_EXITING |
b87a51ae
NHE		 2002 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2003 /*
2004 * We can allow some features even when not supported by the
2005 * hardware. For example, L1 can specify an MSR bitmap - and we
2006 * can use it to avoid exits to L1 - even when L0 runs L2
2007 * without MSR bitmaps.
2008 */
2009 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2010
2011 /* secondary cpu-based controls */
2012 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2013 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2014 nested_vmx_secondary_ctls_low = 0;
2015 nested_vmx_secondary_ctls_high &=
2016 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2017}
2018
2019static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2020{
2021 /*
2022 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2023 */
2024 return ((control & high) | low) == control;
2025}
2026
2027static inline u64 vmx_control_msr(u32 low, u32 high)
2028{
2029 return low | ((u64)high << 32);
2030}
2031
2032/*
2033 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2034 * also let it use VMX-specific MSRs.
2035 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2036 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2037 * like all other MSRs).
2038 */
2039static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2040{
2041 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2042 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2043 /*
2044 * According to the spec, processors which do not support VMX
2045 * should throw a #GP(0) when VMX capability MSRs are read.
2046 */
2047 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2048 return 1;
2049 }
2050
2051 switch (msr_index) {
2052 case MSR_IA32_FEATURE_CONTROL:
2053 *pdata = 0;
2054 break;
2055 case MSR_IA32_VMX_BASIC:
2056 /*
2057 * This MSR reports some information about VMX support. We
2058 * should return information about the VMX we emulate for the
2059 * guest, and the VMCS structure we give it - not about the
2060 * VMX support of the underlying hardware.
2061 */
2062 *pdata = VMCS12_REVISION |
2063 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2064 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2065 break;
2066 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2067 case MSR_IA32_VMX_PINBASED_CTLS:
2068 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2069 nested_vmx_pinbased_ctls_high);
2070 break;
2071 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2072 case MSR_IA32_VMX_PROCBASED_CTLS:
2073 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2074 nested_vmx_procbased_ctls_high);
2075 break;
2076 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2077 case MSR_IA32_VMX_EXIT_CTLS:
2078 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2079 nested_vmx_exit_ctls_high);
2080 break;
2081 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2082 case MSR_IA32_VMX_ENTRY_CTLS:
2083 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2084 nested_vmx_entry_ctls_high);
2085 break;
2086 case MSR_IA32_VMX_MISC:
2087 *pdata = 0;
2088 break;
2089 /*
2090 * These MSRs specify bits which the guest must keep fixed (on or off)
2091 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2092 * We picked the standard core2 setting.
2093 */
2094#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2095#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2096 case MSR_IA32_VMX_CR0_FIXED0:
2097 *pdata = VMXON_CR0_ALWAYSON;
2098 break;
2099 case MSR_IA32_VMX_CR0_FIXED1:
2100 *pdata = -1ULL;
2101 break;
2102 case MSR_IA32_VMX_CR4_FIXED0:
2103 *pdata = VMXON_CR4_ALWAYSON;
2104 break;
2105 case MSR_IA32_VMX_CR4_FIXED1:
2106 *pdata = -1ULL;
2107 break;
2108 case MSR_IA32_VMX_VMCS_ENUM:
2109 *pdata = 0x1f;
2110 break;
2111 case MSR_IA32_VMX_PROCBASED_CTLS2:
2112 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2113 nested_vmx_secondary_ctls_high);
2114 break;
2115 case MSR_IA32_VMX_EPT_VPID_CAP:
2116 /* Currently, no nested ept or nested vpid */
2117 *pdata = 0;
2118 break;
2119 default:
2120 return 0;
2121 }
2122
2123 return 1;
2124}
2125
2126static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2127{
2128 if (!nested_vmx_allowed(vcpu))
2129 return 0;
2130
2131 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2132 /* TODO: the right thing. */
2133 return 1;
2134 /*
2135 * No need to treat VMX capability MSRs specially: If we don't handle
2136 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2137 */
2138 return 0;
2139}
2140
6aa8b732
AK		 2141/*
2142 * Reads an msr value (of 'msr_index') into 'pdata'.
2143 * Returns 0 on success, non-0 otherwise.
2144 * Assumes vcpu_load() was already called.
2145 */
2146static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2147{
2148 u64 data;
26bb0981 2149 struct shared_msr_entry *msr;
6aa8b732
AK		 2150
2151 if (!pdata) {
2152 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2153 return -EINVAL;
2154 }
2155
2156 switch (msr_index) {
05b3e0c2 2157#ifdef CONFIG_X86_64
6aa8b732
AK		 2158 case MSR_FS_BASE:
2159 data = vmcs_readl(GUEST_FS_BASE);
2160 break;
2161 case MSR_GS_BASE:
2162 data = vmcs_readl(GUEST_GS_BASE);
2163 break;
44ea2b17
AK		 2164 case MSR_KERNEL_GS_BASE:
2165 vmx_load_host_state(to_vmx(vcpu));
2166 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2167 break;
26bb0981 2168#endif
6aa8b732 2169 case MSR_EFER:
3bab1f5d 2170 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2171 case MSR_IA32_TSC:
6aa8b732
AK		 2172 data = guest_read_tsc();
2173 break;
2174 case MSR_IA32_SYSENTER_CS:
2175 data = vmcs_read32(GUEST_SYSENTER_CS);
2176 break;
2177 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2178 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2179 break;
2180 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2181 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2182 break;
4e47c7a6
SY		 2183 case MSR_TSC_AUX:
2184 if (!to_vmx(vcpu)->rdtscp_enabled)
2185 return 1;
2186 /* Otherwise falls through */
6aa8b732 2187 default:
b87a51ae
NHE		 2188 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2189 return 0;
8b9cf98c 2190 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2191 if (msr) {
2192 data = msr->data;
2193 break;
6aa8b732 2194 }
3bab1f5d 2195 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2196 }
2197
2198 *pdata = data;
2199 return 0;
2200}
2201
2202/*
2203 * Writes msr value into into the appropriate "register".
2204 * Returns 0 on success, non-0 otherwise.
2205 * Assumes vcpu_load() was already called.
2206 */
2207static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2208{
a2fa3e9f 2209 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2210 struct shared_msr_entry *msr;
2cc51560
ED		 2211 int ret = 0;
2212
6aa8b732 2213 switch (msr_index) {
3bab1f5d 2214 case MSR_EFER:
2cc51560 2215 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2216 break;
16175a79 2217#ifdef CONFIG_X86_64
6aa8b732 2218 case MSR_FS_BASE:
2fb92db1 2219 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2220 vmcs_writel(GUEST_FS_BASE, data);
2221 break;
2222 case MSR_GS_BASE:
2fb92db1 2223 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2224 vmcs_writel(GUEST_GS_BASE, data);
2225 break;
44ea2b17
AK		 2226 case MSR_KERNEL_GS_BASE:
2227 vmx_load_host_state(vmx);
2228 vmx->msr_guest_kernel_gs_base = data;
2229 break;
6aa8b732
AK		 2230#endif
2231 case MSR_IA32_SYSENTER_CS:
2232 vmcs_write32(GUEST_SYSENTER_CS, data);
2233 break;
2234 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2235 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2236 break;
2237 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2238 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2239 break;
af24a4e4 2240 case MSR_IA32_TSC:
99e3e30a 2241 kvm_write_tsc(vcpu, data);
6aa8b732 2242 break;
468d472f
SY		 2243 case MSR_IA32_CR_PAT:
2244 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2245 vmcs_write64(GUEST_IA32_PAT, data);
2246 vcpu->arch.pat = data;
2247 break;
2248 }
4e47c7a6
SY		 2249 ret = kvm_set_msr_common(vcpu, msr_index, data);
2250 break;
2251 case MSR_TSC_AUX:
2252 if (!vmx->rdtscp_enabled)
2253 return 1;
2254 /* Check reserved bit, higher 32 bits should be zero */
2255 if ((data >> 32) != 0)
2256 return 1;
2257 /* Otherwise falls through */
6aa8b732 2258 default:
b87a51ae
NHE		 2259 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2260 break;
8b9cf98c 2261 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2262 if (msr) {
2263 msr->data = data;
2225fd56
AK		 2264 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2265 preempt_disable();
9ee73970
AK		 2266 kvm_set_shared_msr(msr->index, msr->data,
2267 msr->mask);
2225fd56
AK		 2268 preempt_enable();
2269 }
3bab1f5d 2270 break;
6aa8b732 2271 }
2cc51560 2272 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2273 }
2274
2cc51560 2275 return ret;
6aa8b732
AK		 2276}
2277
5fdbf976 2278static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2279{
5fdbf976
MT		 2280 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2281 switch (reg) {
2282 case VCPU_REGS_RSP:
2283 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2284 break;
2285 case VCPU_REGS_RIP:
2286 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2287 break;
6de4f3ad
AK		 2288 case VCPU_EXREG_PDPTR:
2289 if (enable_ept)
2290 ept_save_pdptrs(vcpu);
2291 break;
5fdbf976
MT		 2292 default:
2293 break;
2294 }
6aa8b732
AK		 2295}
2296
355be0b9 2297static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2298{
ae675ef0
JK		 2299 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2300 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2301 else
2302 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2303
abd3f2d6 2304 update_exception_bitmap(vcpu);
6aa8b732
AK		 2305}
2306
2307static __init int cpu_has_kvm_support(void)
2308{
6210e37b 2309 return cpu_has_vmx();
6aa8b732
AK		 2310}
2311
2312static __init int vmx_disabled_by_bios(void)
2313{
2314 u64 msr;
2315
2316 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2317 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2318 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2319 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2320 && tboot_enabled())
2321 return 1;
23f3e991 2322 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2323 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2324 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2325 && !tboot_enabled()) {
2326 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2327 "activate TXT before enabling KVM\n");
cafd6659 2328 return 1;
f9335afe 2329 }
23f3e991
JC		 2330 /* launched w/o TXT and VMX disabled */
2331 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2332 && !tboot_enabled())
2333 return 1;
cafd6659
SW		 2334 }
2335
2336 return 0;
6aa8b732
AK		 2337}
2338
7725b894
DX		 2339static void kvm_cpu_vmxon(u64 addr)
2340{
2341 asm volatile (ASM_VMX_VMXON_RAX
2342 : : "a"(&addr), "m"(addr)
2343 : "memory", "cc");
2344}
2345
10474ae8 2346static int hardware_enable(void *garbage)
6aa8b732
AK		 2347{
2348 int cpu = raw_smp_processor_id();
2349 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2350 u64 old, test_bits;
6aa8b732 2351
10474ae8
AG		 2352 if (read_cr4() & X86_CR4_VMXE)
2353 return -EBUSY;
2354
d462b819 2355 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2356 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2357
2358 test_bits = FEATURE_CONTROL_LOCKED;
2359 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2360 if (tboot_enabled())
2361 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2362
2363 if ((old & test_bits) != test_bits) {
6aa8b732 2364 /* enable and lock */
cafd6659
SW		 2365 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2366 }
66aee91a 2367 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2368
4610c9cc
DX		 2369 if (vmm_exclusive) {
2370 kvm_cpu_vmxon(phys_addr);
2371 ept_sync_global();
2372 }
10474ae8 2373
3444d7da
AK		 2374 store_gdt(&__get_cpu_var(host_gdt));
2375
10474ae8 2376 return 0;
6aa8b732
AK		 2377}
2378
d462b819 2379static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2380{
2381 int cpu = raw_smp_processor_id();
d462b819 2382 struct loaded_vmcs *v, *n;
543e4243 2383
d462b819
NHE		 2384 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2385 loaded_vmcss_on_cpu_link)
2386 __loaded_vmcs_clear(v);
543e4243
AK		 2387}
2388
710ff4a8
EH		 2389
2390/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2391 * tricks.
2392 */
2393static void kvm_cpu_vmxoff(void)
6aa8b732 2394{
4ecac3fd 2395 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2396}
2397
710ff4a8
EH		 2398static void hardware_disable(void *garbage)
2399{
4610c9cc 2400 if (vmm_exclusive) {
d462b819 2401 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2402 kvm_cpu_vmxoff();
2403 }
7725b894 2404 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2405}
2406
1c3d14fe 2407static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2408 u32 msr, u32 *result)
1c3d14fe
YS		 2409{
2410 u32 vmx_msr_low, vmx_msr_high;
2411 u32 ctl = ctl_min | ctl_opt;
2412
2413 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2414
2415 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2416 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2417
2418 /* Ensure minimum (required) set of control bits are supported. */
2419 if (ctl_min & ~ctl)
002c7f7c 2420 return -EIO;
1c3d14fe
YS		 2421
2422 *result = ctl;
2423 return 0;
2424}
2425
110312c8
AK		 2426static __init bool allow_1_setting(u32 msr, u32 ctl)
2427{
2428 u32 vmx_msr_low, vmx_msr_high;
2429
2430 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2431 return vmx_msr_high & ctl;
2432}
2433
002c7f7c 2434static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2435{
2436 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2437 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2438 u32 _pin_based_exec_control = 0;
2439 u32 _cpu_based_exec_control = 0;
f78e0e2e 2440 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2441 u32 _vmexit_control = 0;
2442 u32 _vmentry_control = 0;
2443
2444 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2445 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2446 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2447 &_pin_based_exec_control) < 0)
002c7f7c 2448 return -EIO;
1c3d14fe 2449
10166744 2450 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2451#ifdef CONFIG_X86_64
2452 CPU_BASED_CR8_LOAD_EXITING |
2453 CPU_BASED_CR8_STORE_EXITING |
2454#endif
d56f546d
SY		 2455 CPU_BASED_CR3_LOAD_EXITING |
2456 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2457 CPU_BASED_USE_IO_BITMAPS |
2458 CPU_BASED_MOV_DR_EXITING |
a7052897 2459 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2460 CPU_BASED_MWAIT_EXITING |
2461 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2462 CPU_BASED_INVLPG_EXITING |
2463 CPU_BASED_RDPMC_EXITING;
443381a8 2464
f78e0e2e 2465 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2466 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2467 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2468 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2469 &_cpu_based_exec_control) < 0)
002c7f7c 2470 return -EIO;
6e5d865c
YS		 2471#ifdef CONFIG_X86_64
2472 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2473 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2474 ~CPU_BASED_CR8_STORE_EXITING;
2475#endif
f78e0e2e 2476 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2477 min2 = 0;
2478 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2479 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2480 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2481 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2482 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2483 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16
MJ		 2484 SECONDARY_EXEC_RDTSCP |
2485 SECONDARY_EXEC_ENABLE_INVPCID;
d56f546d
SY		 2486 if (adjust_vmx_controls(min2, opt2,
2487 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2488 &_cpu_based_2nd_exec_control) < 0)
2489 return -EIO;
2490 }
2491#ifndef CONFIG_X86_64
2492 if (!(_cpu_based_2nd_exec_control &
2493 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2494 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2495#endif
d56f546d 2496 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2497 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2498 enabled */
5fff7d27
GN		 2499 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2500 CPU_BASED_CR3_STORE_EXITING |
2501 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2502 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2503 vmx_capability.ept, vmx_capability.vpid);
2504 }
1c3d14fe
YS		 2505
2506 min = 0;
2507#ifdef CONFIG_X86_64
2508 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2509#endif
468d472f 2510 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2511 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2512 &_vmexit_control) < 0)
002c7f7c 2513 return -EIO;
1c3d14fe 2514
468d472f
SY		 2515 min = 0;
2516 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2517 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2518 &_vmentry_control) < 0)
002c7f7c 2519 return -EIO;
6aa8b732 2520
c68876fd 2521 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2522
2523 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2524 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2525 return -EIO;
1c3d14fe
YS		 2526
2527#ifdef CONFIG_X86_64
2528 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2529 if (vmx_msr_high & (1u<<16))
002c7f7c 2530 return -EIO;
1c3d14fe
YS		 2531#endif
2532
2533 /* Require Write-Back (WB) memory type for VMCS accesses. */
2534 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2535 return -EIO;
1c3d14fe 2536
002c7f7c
YS		 2537 vmcs_conf->size = vmx_msr_high & 0x1fff;
2538 vmcs_conf->order = get_order(vmcs_config.size);
2539 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2540
002c7f7c
YS		 2541 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2542 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2543 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2544 vmcs_conf->vmexit_ctrl = _vmexit_control;
2545 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2546
110312c8
AK		 2547 cpu_has_load_ia32_efer =
2548 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2549 VM_ENTRY_LOAD_IA32_EFER)
2550 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2551 VM_EXIT_LOAD_IA32_EFER);
2552
8bf00a52
GN		 2553 cpu_has_load_perf_global_ctrl =
2554 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2555 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2556 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2557 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2558
2559 /*
2560 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2561 * but due to arrata below it can't be used. Workaround is to use
2562 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2563 *
2564 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2565 *
2566 * AAK155 (model 26)
2567 * AAP115 (model 30)
2568 * AAT100 (model 37)
2569 * BC86,AAY89,BD102 (model 44)
2570 * BA97 (model 46)
2571 *
2572 */
2573 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2574 switch (boot_cpu_data.x86_model) {
2575 case 26:
2576 case 30:
2577 case 37:
2578 case 44:
2579 case 46:
2580 cpu_has_load_perf_global_ctrl = false;
2581 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2582 "does not work properly. Using workaround\n");
2583 break;
2584 default:
2585 break;
2586 }
2587 }
2588
1c3d14fe 2589 return 0;
c68876fd 2590}
6aa8b732
AK		 2591
2592static struct vmcs *alloc_vmcs_cpu(int cpu)
2593{
2594 int node = cpu_to_node(cpu);
2595 struct page *pages;
2596 struct vmcs *vmcs;
2597
6484eb3e 2598 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2599 if (!pages)
2600 return NULL;
2601 vmcs = page_address(pages);
1c3d14fe
YS		 2602 memset(vmcs, 0, vmcs_config.size);
2603 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2604 return vmcs;
2605}
2606
2607static struct vmcs *alloc_vmcs(void)
2608{
d3b2c338 2609 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2610}
2611
2612static void free_vmcs(struct vmcs *vmcs)
2613{
1c3d14fe 2614 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2615}
2616
d462b819
NHE		 2617/*
2618 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2619 */
2620static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2621{
2622 if (!loaded_vmcs->vmcs)
2623 return;
2624 loaded_vmcs_clear(loaded_vmcs);
2625 free_vmcs(loaded_vmcs->vmcs);
2626 loaded_vmcs->vmcs = NULL;
2627}
2628
39959588 2629static void free_kvm_area(void)
6aa8b732
AK		 2630{
2631 int cpu;
2632
3230bb47 2633 for_each_possible_cpu(cpu) {
6aa8b732 2634 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2635 per_cpu(vmxarea, cpu) = NULL;
2636 }
6aa8b732
AK		 2637}
2638
6aa8b732
AK		 2639static __init int alloc_kvm_area(void)
2640{
2641 int cpu;
2642
3230bb47 2643 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2644 struct vmcs *vmcs;
2645
2646 vmcs = alloc_vmcs_cpu(cpu);
2647 if (!vmcs) {
2648 free_kvm_area();
2649 return -ENOMEM;
2650 }
2651
2652 per_cpu(vmxarea, cpu) = vmcs;
2653 }
2654 return 0;
2655}
2656
2657static __init int hardware_setup(void)
2658{
002c7f7c
YS		 2659 if (setup_vmcs_config(&vmcs_config) < 0)
2660 return -EIO;
50a37eb4
JR		 2661
2662 if (boot_cpu_has(X86_FEATURE_NX))
2663 kvm_enable_efer_bits(EFER_NX);
2664
93ba03c2
SY		 2665 if (!cpu_has_vmx_vpid())
2666 enable_vpid = 0;
2667
4bc9b982
SY		 2668 if (!cpu_has_vmx_ept() ||
2669 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2670 enable_ept = 0;
3a624e29 2671 enable_unrestricted_guest = 0;
83c3a331 2672 enable_ept_ad_bits = 0;
3a624e29
NK		 2673 }
2674
83c3a331
XH		 2675 if (!cpu_has_vmx_ept_ad_bits())
2676 enable_ept_ad_bits = 0;
2677
3a624e29
NK		 2678 if (!cpu_has_vmx_unrestricted_guest())
2679 enable_unrestricted_guest = 0;
93ba03c2
SY		 2680
2681 if (!cpu_has_vmx_flexpriority())
2682 flexpriority_enabled = 0;
2683
95ba8273
GN		 2684 if (!cpu_has_vmx_tpr_shadow())
2685 kvm_x86_ops->update_cr8_intercept = NULL;
2686
54dee993
MT		 2687 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2688 kvm_disable_largepages();
2689
4b8d54f9
ZE		 2690 if (!cpu_has_vmx_ple())
2691 ple_gap = 0;
2692
b87a51ae
NHE		 2693 if (nested)
2694 nested_vmx_setup_ctls_msrs();
2695
6aa8b732
AK		 2696 return alloc_kvm_area();
2697}
2698
2699static __exit void hardware_unsetup(void)
2700{
2701 free_kvm_area();
2702}
2703
6aa8b732
AK		 2704static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2705{
2706 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2707
6af11b9e 2708 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2709 vmcs_write16(sf->selector, save->selector);
2710 vmcs_writel(sf->base, save->base);
2711 vmcs_write32(sf->limit, save->limit);
2712 vmcs_write32(sf->ar_bytes, save->ar);
2713 } else {
2714 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2715 << AR_DPL_SHIFT;
2716 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2717 }
2718}
2719
2720static void enter_pmode(struct kvm_vcpu *vcpu)
2721{
2722 unsigned long flags;
a89a8fb9 2723 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2724
a89a8fb9 2725 vmx->emulation_required = 1;
7ffd92c5 2726 vmx->rmode.vm86_active = 0;
6aa8b732 2727
2fb92db1
AK		 2728 vmx_segment_cache_clear(vmx);
2729
d0ba64f9 2730 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2731 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2732 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2733 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2734
2735 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2736 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2737 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2738 vmcs_writel(GUEST_RFLAGS, flags);
2739
66aee91a
RR		 2740 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2741 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2742
2743 update_exception_bitmap(vcpu);
2744
a89a8fb9
MG		 2745 if (emulate_invalid_guest_state)
2746 return;
2747
7ffd92c5
AK		 2748 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2749 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2750 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2751 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2752
2fb92db1
AK		 2753 vmx_segment_cache_clear(vmx);
2754
6aa8b732
AK		 2755 vmcs_write16(GUEST_SS_SELECTOR, 0);
2756 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2757
2758 vmcs_write16(GUEST_CS_SELECTOR,
2759 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2760 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2761}
2762
d77c26fc 2763static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2764{
bfc6d222 2765 if (!kvm->arch.tss_addr) {
bc6678a3 2766 struct kvm_memslots *slots;
28a37544 2767 struct kvm_memory_slot *slot;
bc6678a3
MT		 2768 gfn_t base_gfn;
2769
90d83dc3 2770 slots = kvm_memslots(kvm);
28a37544
XG		 2771 slot = id_to_memslot(slots, 0);
2772 base_gfn = slot->base_gfn + slot->npages - 3;
2773
cbc94022
IE		 2774 return base_gfn << PAGE_SHIFT;
2775 }
bfc6d222 2776 return kvm->arch.tss_addr;
6aa8b732
AK		 2777}
2778
2779static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2780{
2781 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2782
2783 save->selector = vmcs_read16(sf->selector);
2784 save->base = vmcs_readl(sf->base);
2785 save->limit = vmcs_read32(sf->limit);
2786 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2787 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2788 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2789 vmcs_write32(sf->limit, 0xffff);
2790 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2791 if (save->base & 0xf)
2792 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2793 " aligned when entering protected mode (seg=%d)",
2794 seg);
6aa8b732
AK		 2795}
2796
2797static void enter_rmode(struct kvm_vcpu *vcpu)
2798{
2799 unsigned long flags;
a89a8fb9 2800 struct vcpu_vmx *vmx = to_vmx(vcpu);
b246dd5d 2801 struct kvm_segment var;
6aa8b732 2802
3a624e29
NK		 2803 if (enable_unrestricted_guest)
2804 return;
2805
a89a8fb9 2806 vmx->emulation_required = 1;
7ffd92c5 2807 vmx->rmode.vm86_active = 1;
6aa8b732 2808
776e58ea
GN		 2809 /*
2810 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2811 * vcpu. Call it here with phys address pointing 16M below 4G.
2812 */
2813 if (!vcpu->kvm->arch.tss_addr) {
2814 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2815 "called before entering vcpu\n");
2816 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2817 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2818 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2819 }
2820
2fb92db1
AK		 2821 vmx_segment_cache_clear(vmx);
2822
d0ba64f9 2823 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2824 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2825 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2826
7ffd92c5 2827 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2828 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2829
7ffd92c5 2830 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2831 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2832
2833 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2834 vmx->rmode.save_rflags = flags;
6aa8b732 2835
053de044 2836 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2837
2838 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2839 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2840 update_exception_bitmap(vcpu);
2841
a89a8fb9
MG		 2842 if (emulate_invalid_guest_state)
2843 goto continue_rmode;
2844
b246dd5d
OW		 2845 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2846 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2847
2848 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2849 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2850
2851 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2852 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2853
2854 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2855 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
6aa8b732 2856
b246dd5d
OW		 2857 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2858 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
6aa8b732 2859
b246dd5d
OW		 2860 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2861 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
75880a01 2862
a89a8fb9 2863continue_rmode:
8668a3c4 2864 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2865}
2866
401d10de
AS		 2867static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2868{
2869 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2870 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2871
2872 if (!msr)
2873 return;
401d10de 2874
44ea2b17
AK		 2875 /*
2876 * Force kernel_gs_base reloading before EFER changes, as control
2877 * of this msr depends on is_long_mode().
2878 */
2879 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2880 vcpu->arch.efer = efer;
401d10de
AS		 2881 if (efer & EFER_LMA) {
2882 vmcs_write32(VM_ENTRY_CONTROLS,
2883 vmcs_read32(VM_ENTRY_CONTROLS) |
2884 VM_ENTRY_IA32E_MODE);
2885 msr->data = efer;
2886 } else {
2887 vmcs_write32(VM_ENTRY_CONTROLS,
2888 vmcs_read32(VM_ENTRY_CONTROLS) &
2889 ~VM_ENTRY_IA32E_MODE);
2890
2891 msr->data = efer & ~EFER_LME;
2892 }
2893 setup_msrs(vmx);
2894}
2895
05b3e0c2 2896#ifdef CONFIG_X86_64
6aa8b732
AK		 2897
2898static void enter_lmode(struct kvm_vcpu *vcpu)
2899{
2900 u32 guest_tr_ar;
2901
2fb92db1
AK		 2902 vmx_segment_cache_clear(to_vmx(vcpu));
2903
6aa8b732
AK		 2904 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2905 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2906 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2907 __func__);
6aa8b732
AK		 2908 vmcs_write32(GUEST_TR_AR_BYTES,
2909 (guest_tr_ar & ~AR_TYPE_MASK)
2910 | AR_TYPE_BUSY_64_TSS);
2911 }
da38f438 2912 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2913}
2914
2915static void exit_lmode(struct kvm_vcpu *vcpu)
2916{
6aa8b732
AK		 2917 vmcs_write32(VM_ENTRY_CONTROLS,
2918 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2919 & ~VM_ENTRY_IA32E_MODE);
da38f438 2920 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2921}
2922
2923#endif
2924
2384d2b3
SY		 2925static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2926{
b9d762fa 2927 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2928 if (enable_ept) {
2929 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2930 return;
4e1096d2 2931 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2932 }
2384d2b3
SY		 2933}
2934
e8467fda
AK		 2935static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2936{
2937 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2938
2939 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2940 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2941}
2942
aff48baa
AK		 2943static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2944{
2945 if (enable_ept && is_paging(vcpu))
2946 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2947 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2948}
2949
25c4c276 2950static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2951{
fc78f519
AK		 2952 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2953
2954 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2955 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2956}
2957
1439442c
SY		 2958static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2959{
6de4f3ad
AK		 2960 if (!test_bit(VCPU_EXREG_PDPTR,
2961 (unsigned long *)&vcpu->arch.regs_dirty))
2962 return;
2963
1439442c 2964 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2965 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2966 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2967 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2968 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2969 }
2970}
2971
8f5d549f
AK		 2972static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2973{
2974 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2975 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2976 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2977 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2978 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2979 }
6de4f3ad
AK		 2980
2981 __set_bit(VCPU_EXREG_PDPTR,
2982 (unsigned long *)&vcpu->arch.regs_avail);
2983 __set_bit(VCPU_EXREG_PDPTR,
2984 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2985}
2986
5e1746d6 2987static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2988
2989static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2990 unsigned long cr0,
2991 struct kvm_vcpu *vcpu)
2992{
5233dd51
MT		 2993 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2994 vmx_decache_cr3(vcpu);
1439442c
SY		 2995 if (!(cr0 & X86_CR0_PG)) {
2996 /* From paging/starting to nonpaging */
2997 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2998 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2999 (CPU_BASED_CR3_LOAD_EXITING |
3000 CPU_BASED_CR3_STORE_EXITING));
3001 vcpu->arch.cr0 = cr0;
fc78f519 3002 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3003 } else if (!is_paging(vcpu)) {
3004 /* From nonpaging to paging */
3005 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3006 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3007 ~(CPU_BASED_CR3_LOAD_EXITING |
3008 CPU_BASED_CR3_STORE_EXITING));
3009 vcpu->arch.cr0 = cr0;
fc78f519 3010 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3011 }
95eb84a7
SY		 3012
3013 if (!(cr0 & X86_CR0_WP))
3014 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3015}
3016
6aa8b732
AK		 3017static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3018{
7ffd92c5 3019 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3020 unsigned long hw_cr0;
3021
3022 if (enable_unrestricted_guest)
3023 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3024 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3025 else
3026 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3027
7ffd92c5 3028 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3029 enter_pmode(vcpu);
3030
7ffd92c5 3031 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3032 enter_rmode(vcpu);
3033
05b3e0c2 3034#ifdef CONFIG_X86_64
f6801dff 3035 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3036 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3037 enter_lmode(vcpu);
707d92fa 3038 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3039 exit_lmode(vcpu);
3040 }
3041#endif
3042
089d034e 3043 if (enable_ept)
1439442c
SY		 3044 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3045
02daab21 3046 if (!vcpu->fpu_active)
81231c69 3047 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3048
6aa8b732 3049 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3050 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3051 vcpu->arch.cr0 = cr0;
69c73028 3052 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3053}
3054
1439442c
SY		 3055static u64 construct_eptp(unsigned long root_hpa)
3056{
3057 u64 eptp;
3058
3059 /* TODO write the value reading from MSR */
3060 eptp = VMX_EPT_DEFAULT_MT |
3061 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3062 if (enable_ept_ad_bits)
3063 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3064 eptp |= (root_hpa & PAGE_MASK);
3065
3066 return eptp;
3067}
3068
6aa8b732
AK		 3069static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3070{
1439442c
SY		 3071 unsigned long guest_cr3;
3072 u64 eptp;
3073
3074 guest_cr3 = cr3;
089d034e 3075 if (enable_ept) {
1439442c
SY		 3076 eptp = construct_eptp(cr3);
3077 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3078 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3079 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3080 ept_load_pdptrs(vcpu);
1439442c
SY		 3081 }
3082
2384d2b3 3083 vmx_flush_tlb(vcpu);
1439442c 3084 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3085}
3086
5e1746d6 3087static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3088{
7ffd92c5 3089 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3090 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3091
5e1746d6
NHE		 3092 if (cr4 & X86_CR4_VMXE) {
3093 /*
3094 * To use VMXON (and later other VMX instructions), a guest
3095 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3096 * So basically the check on whether to allow nested VMX
3097 * is here.
3098 */
3099 if (!nested_vmx_allowed(vcpu))
3100 return 1;
3101 } else if (to_vmx(vcpu)->nested.vmxon)
3102 return 1;
3103
ad312c7c 3104 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3105 if (enable_ept) {
3106 if (!is_paging(vcpu)) {
3107 hw_cr4 &= ~X86_CR4_PAE;
3108 hw_cr4 |= X86_CR4_PSE;
3109 } else if (!(cr4 & X86_CR4_PAE)) {
3110 hw_cr4 &= ~X86_CR4_PAE;
3111 }
3112 }
1439442c
SY		 3113
3114 vmcs_writel(CR4_READ_SHADOW, cr4);
3115 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3116 return 0;
6aa8b732
AK		 3117}
3118
6aa8b732
AK		 3119static void vmx_get_segment(struct kvm_vcpu *vcpu,
3120 struct kvm_segment *var, int seg)
3121{
a9179499 3122 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 3123 struct kvm_save_segment *save;
6aa8b732
AK		 3124 u32 ar;
3125
a9179499
AK		 3126 if (vmx->rmode.vm86_active
3127 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3128 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3129 || seg == VCPU_SREG_GS)
3130 && !emulate_invalid_guest_state) {
3131 switch (seg) {
3132 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3133 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3134 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3135 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3136 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3137 default: BUG();
3138 }
3139 var->selector = save->selector;
3140 var->base = save->base;
3141 var->limit = save->limit;
3142 ar = save->ar;
3143 if (seg == VCPU_SREG_TR
2fb92db1 3144 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 3145 goto use_saved_rmode_seg;
3146 }
2fb92db1
AK		 3147 var->base = vmx_read_guest_seg_base(vmx, seg);
3148 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3149 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3150 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 3151use_saved_rmode_seg:
9fd4a3b7 3152 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3153 ar = 0;
3154 var->type = ar & 15;
3155 var->s = (ar >> 4) & 1;
3156 var->dpl = (ar >> 5) & 3;
3157 var->present = (ar >> 7) & 1;
3158 var->avl = (ar >> 12) & 1;
3159 var->l = (ar >> 13) & 1;
3160 var->db = (ar >> 14) & 1;
3161 var->g = (ar >> 15) & 1;
3162 var->unusable = (ar >> 16) & 1;
3163}
3164
a9179499
AK		 3165static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3166{
a9179499
AK		 3167 struct kvm_segment s;
3168
3169 if (to_vmx(vcpu)->rmode.vm86_active) {
3170 vmx_get_segment(vcpu, &s, seg);
3171 return s.base;
3172 }
2fb92db1 3173 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3174}
3175
69c73028 3176static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3177{
3eeb3288 3178 if (!is_protmode(vcpu))
2e4d2653
IE		 3179 return 0;
3180
f4c63e5d
AK		 3181 if (!is_long_mode(vcpu)
3182 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3183 return 3;
3184
2fb92db1 3185 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3186}
3187
69c73028
AK		 3188static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3189{
d881e6f6
AK		 3190 struct vcpu_vmx *vmx = to_vmx(vcpu);
3191
3192 /*
3193 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3194 * fail; use the cache instead.
3195 */
3196 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3197 return vmx->cpl;
3198 }
3199
69c73028
AK		 3200 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3201 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
d881e6f6 3202 vmx->cpl = __vmx_get_cpl(vcpu);
69c73028 3203 }
d881e6f6
AK		 3204
3205 return vmx->cpl;
69c73028
AK		 3206}
3207
3208
653e3108 3209static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3210{
6aa8b732
AK		 3211 u32 ar;
3212
f0495f9b 3213 if (var->unusable || !var->present)
6aa8b732
AK		 3214 ar = 1 << 16;
3215 else {
3216 ar = var->type & 15;
3217 ar |= (var->s & 1) << 4;
3218 ar |= (var->dpl & 3) << 5;
3219 ar |= (var->present & 1) << 7;
3220 ar |= (var->avl & 1) << 12;
3221 ar |= (var->l & 1) << 13;
3222 ar |= (var->db & 1) << 14;
3223 ar |= (var->g & 1) << 15;
3224 }
653e3108
AK		 3225
3226 return ar;
3227}
3228
3229static void vmx_set_segment(struct kvm_vcpu *vcpu,
3230 struct kvm_segment *var, int seg)
3231{
7ffd92c5 3232 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3233 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3234 u32 ar;
3235
2fb92db1
AK		 3236 vmx_segment_cache_clear(vmx);
3237
7ffd92c5 3238 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3239 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3240 vmx->rmode.tr.selector = var->selector;
3241 vmx->rmode.tr.base = var->base;
3242 vmx->rmode.tr.limit = var->limit;
3243 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3244 return;
3245 }
3246 vmcs_writel(sf->base, var->base);
3247 vmcs_write32(sf->limit, var->limit);
3248 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3249 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3250 /*
3251 * Hack real-mode segments into vm86 compatibility.
3252 */
3253 if (var->base == 0xffff0000 && var->selector == 0xf000)
3254 vmcs_writel(sf->base, 0xf0000);
3255 ar = 0xf3;
3256 } else
3257 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3258
3259 /*
3260 * Fix the "Accessed" bit in AR field of segment registers for older
3261 * qemu binaries.
3262 * IA32 arch specifies that at the time of processor reset the
3263 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3264 * is setting it to 0 in the usedland code. This causes invalid guest
3265 * state vmexit when "unrestricted guest" mode is turned on.
3266 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3267 * tree. Newer qemu binaries with that qemu fix would not need this
3268 * kvm hack.
3269 */
3270 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3271 ar |= 0x1; /* Accessed */
3272
6aa8b732 3273 vmcs_write32(sf->ar_bytes, ar);
69c73028 3274 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b246dd5d
OW		 3275
3276 /*
3277 * Fix segments for real mode guest in hosts that don't have
3278 * "unrestricted_mode" or it was disabled.
3279 * This is done to allow migration of the guests from hosts with
3280 * unrestricted guest like Westmere to older host that don't have
3281 * unrestricted guest like Nehelem.
3282 */
3283 if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3284 switch (seg) {
3285 case VCPU_SREG_CS:
3286 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3287 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3288 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3289 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3290 vmcs_write16(GUEST_CS_SELECTOR,
3291 vmcs_readl(GUEST_CS_BASE) >> 4);
3292 break;
3293 case VCPU_SREG_ES:
3294 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
3295 break;
3296 case VCPU_SREG_DS:
3297 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
3298 break;
3299 case VCPU_SREG_GS:
3300 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
3301 break;
3302 case VCPU_SREG_FS:
3303 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
3304 break;
3305 case VCPU_SREG_SS:
3306 vmcs_write16(GUEST_SS_SELECTOR,
3307 vmcs_readl(GUEST_SS_BASE) >> 4);
3308 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3309 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3310 break;
3311 }
3312 }
6aa8b732
AK		 3313}
3314
6aa8b732
AK		 3315static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3316{
2fb92db1 3317 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3318
3319 *db = (ar >> 14) & 1;
3320 *l = (ar >> 13) & 1;
3321}
3322
89a27f4d 3323static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3324{
89a27f4d
GN		 3325 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3326 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3327}
3328
89a27f4d 3329static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3330{
89a27f4d
GN		 3331 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3332 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3333}
3334
89a27f4d 3335static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3336{
89a27f4d
GN		 3337 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3338 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3339}
3340
89a27f4d 3341static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3342{
89a27f4d
GN		 3343 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3344 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3345}
3346
648dfaa7
MG		 3347static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3348{
3349 struct kvm_segment var;
3350 u32 ar;
3351
3352 vmx_get_segment(vcpu, &var, seg);
3353 ar = vmx_segment_access_rights(&var);
3354
3355 if (var.base != (var.selector << 4))
3356 return false;
3357 if (var.limit != 0xffff)
3358 return false;
3359 if (ar != 0xf3)
3360 return false;
3361
3362 return true;
3363}
3364
3365static bool code_segment_valid(struct kvm_vcpu *vcpu)
3366{
3367 struct kvm_segment cs;
3368 unsigned int cs_rpl;
3369
3370 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3371 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3372
1872a3f4
AK		 3373 if (cs.unusable)
3374 return false;
648dfaa7
MG		 3375 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3376 return false;
3377 if (!cs.s)
3378 return false;
1872a3f4 3379 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3380 if (cs.dpl > cs_rpl)
3381 return false;
1872a3f4 3382 } else {
648dfaa7
MG		 3383 if (cs.dpl != cs_rpl)
3384 return false;
3385 }
3386 if (!cs.present)
3387 return false;
3388
3389 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3390 return true;
3391}
3392
3393static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3394{
3395 struct kvm_segment ss;
3396 unsigned int ss_rpl;
3397
3398 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3399 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3400
1872a3f4
AK		 3401 if (ss.unusable)
3402 return true;
3403 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3404 return false;
3405 if (!ss.s)
3406 return false;
3407 if (ss.dpl != ss_rpl) /* DPL != RPL */
3408 return false;
3409 if (!ss.present)
3410 return false;
3411
3412 return true;
3413}
3414
3415static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3416{
3417 struct kvm_segment var;
3418 unsigned int rpl;
3419
3420 vmx_get_segment(vcpu, &var, seg);
3421 rpl = var.selector & SELECTOR_RPL_MASK;
3422
1872a3f4
AK		 3423 if (var.unusable)
3424 return true;
648dfaa7
MG		 3425 if (!var.s)
3426 return false;
3427 if (!var.present)
3428 return false;
3429 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3430 if (var.dpl < rpl) /* DPL < RPL */
3431 return false;
3432 }
3433
3434 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3435 * rights flags
3436 */
3437 return true;
3438}
3439
3440static bool tr_valid(struct kvm_vcpu *vcpu)
3441{
3442 struct kvm_segment tr;
3443
3444 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3445
1872a3f4
AK		 3446 if (tr.unusable)
3447 return false;
648dfaa7
MG		 3448 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3449 return false;
1872a3f4 3450 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3451 return false;
3452 if (!tr.present)
3453 return false;
3454
3455 return true;
3456}
3457
3458static bool ldtr_valid(struct kvm_vcpu *vcpu)
3459{
3460 struct kvm_segment ldtr;
3461
3462 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3463
1872a3f4
AK		 3464 if (ldtr.unusable)
3465 return true;
648dfaa7
MG		 3466 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3467 return false;
3468 if (ldtr.type != 2)
3469 return false;
3470 if (!ldtr.present)
3471 return false;
3472
3473 return true;
3474}
3475
3476static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3477{
3478 struct kvm_segment cs, ss;
3479
3480 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3481 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3482
3483 return ((cs.selector & SELECTOR_RPL_MASK) ==
3484 (ss.selector & SELECTOR_RPL_MASK));
3485}
3486
3487/*
3488 * Check if guest state is valid. Returns true if valid, false if
3489 * not.
3490 * We assume that registers are always usable
3491 */
3492static bool guest_state_valid(struct kvm_vcpu *vcpu)
3493{
3494 /* real mode guest state checks */
3eeb3288 3495 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3496 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3497 return false;
3498 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3499 return false;
3500 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3501 return false;
3502 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3503 return false;
3504 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3505 return false;
3506 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3507 return false;
3508 } else {
3509 /* protected mode guest state checks */
3510 if (!cs_ss_rpl_check(vcpu))
3511 return false;
3512 if (!code_segment_valid(vcpu))
3513 return false;
3514 if (!stack_segment_valid(vcpu))
3515 return false;
3516 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3517 return false;
3518 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3519 return false;
3520 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3521 return false;
3522 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3523 return false;
3524 if (!tr_valid(vcpu))
3525 return false;
3526 if (!ldtr_valid(vcpu))
3527 return false;
3528 }
3529 /* TODO:
3530 * - Add checks on RIP
3531 * - Add checks on RFLAGS
3532 */
3533
3534 return true;
3535}
3536
d77c26fc 3537static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3538{
40dcaa9f 3539 gfn_t fn;
195aefde 3540 u16 data = 0;
40dcaa9f 3541 int r, idx, ret = 0;
6aa8b732 3542
40dcaa9f
XG		 3543 idx = srcu_read_lock(&kvm->srcu);
3544 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3545 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3546 if (r < 0)
10589a46 3547 goto out;
195aefde 3548 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3549 r = kvm_write_guest_page(kvm, fn++, &data,
3550 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3551 if (r < 0)
10589a46 3552 goto out;
195aefde
IE		 3553 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3554 if (r < 0)
10589a46 3555 goto out;
195aefde
IE		 3556 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3557 if (r < 0)
10589a46 3558 goto out;
195aefde 3559 data = ~0;
10589a46
MT		 3560 r = kvm_write_guest_page(kvm, fn, &data,
3561 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3562 sizeof(u8));
195aefde 3563 if (r < 0)
10589a46
MT		 3564 goto out;
3565
3566 ret = 1;
3567out:
40dcaa9f 3568 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3569 return ret;
6aa8b732
AK		 3570}
3571
b7ebfb05
SY		 3572static int init_rmode_identity_map(struct kvm *kvm)
3573{
40dcaa9f 3574 int i, idx, r, ret;
b7ebfb05
SY		 3575 pfn_t identity_map_pfn;
3576 u32 tmp;
3577
089d034e 3578 if (!enable_ept)
b7ebfb05
SY		 3579 return 1;
3580 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3581 printk(KERN_ERR "EPT: identity-mapping pagetable "
3582 "haven't been allocated!\n");
3583 return 0;
3584 }
3585 if (likely(kvm->arch.ept_identity_pagetable_done))
3586 return 1;
3587 ret = 0;
b927a3ce 3588 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3589 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3590 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3591 if (r < 0)
3592 goto out;
3593 /* Set up identity-mapping pagetable for EPT in real mode */
3594 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3595 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3596 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3597 r = kvm_write_guest_page(kvm, identity_map_pfn,
3598 &tmp, i * sizeof(tmp), sizeof(tmp));
3599 if (r < 0)
3600 goto out;
3601 }
3602 kvm->arch.ept_identity_pagetable_done = true;
3603 ret = 1;
3604out:
40dcaa9f 3605 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3606 return ret;
3607}
3608
6aa8b732
AK		 3609static void seg_setup(int seg)
3610{
3611 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3612 unsigned int ar;
6aa8b732
AK		 3613
3614 vmcs_write16(sf->selector, 0);
3615 vmcs_writel(sf->base, 0);
3616 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3617 if (enable_unrestricted_guest) {
3618 ar = 0x93;
3619 if (seg == VCPU_SREG_CS)
3620 ar |= 0x08; /* code segment */
3621 } else
3622 ar = 0xf3;
3623
3624 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3625}
3626
f78e0e2e
SY		 3627static int alloc_apic_access_page(struct kvm *kvm)
3628{
3629 struct kvm_userspace_memory_region kvm_userspace_mem;
3630 int r = 0;
3631
79fac95e 3632 mutex_lock(&kvm->slots_lock);
bfc6d222 3633 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3634 goto out;
3635 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3636 kvm_userspace_mem.flags = 0;
3637 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3638 kvm_userspace_mem.memory_size = PAGE_SIZE;
3639 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3640 if (r)
3641 goto out;
72dc67a6 3642
bfc6d222 3643 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3644out:
79fac95e 3645 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3646 return r;
3647}
3648
b7ebfb05
SY		 3649static int alloc_identity_pagetable(struct kvm *kvm)
3650{
3651 struct kvm_userspace_memory_region kvm_userspace_mem;
3652 int r = 0;
3653
79fac95e 3654 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3655 if (kvm->arch.ept_identity_pagetable)
3656 goto out;
3657 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3658 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3659 kvm_userspace_mem.guest_phys_addr =
3660 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3661 kvm_userspace_mem.memory_size = PAGE_SIZE;
3662 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3663 if (r)
3664 goto out;
3665
b7ebfb05 3666 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3667 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3668out:
79fac95e 3669 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3670 return r;
3671}
3672
2384d2b3
SY		 3673static void allocate_vpid(struct vcpu_vmx *vmx)
3674{
3675 int vpid;
3676
3677 vmx->vpid = 0;
919818ab 3678 if (!enable_vpid)
2384d2b3
SY		 3679 return;
3680 spin_lock(&vmx_vpid_lock);
3681 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3682 if (vpid < VMX_NR_VPIDS) {
3683 vmx->vpid = vpid;
3684 __set_bit(vpid, vmx_vpid_bitmap);
3685 }
3686 spin_unlock(&vmx_vpid_lock);
3687}
3688
cdbecfc3
LJ		 3689static void free_vpid(struct vcpu_vmx *vmx)
3690{
3691 if (!enable_vpid)
3692 return;
3693 spin_lock(&vmx_vpid_lock);
3694 if (vmx->vpid != 0)
3695 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3696 spin_unlock(&vmx_vpid_lock);
3697}
3698
5897297b 3699static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3700{
3e7c73e9 3701 int f = sizeof(unsigned long);
25c5f225
SY		 3702
3703 if (!cpu_has_vmx_msr_bitmap())
3704 return;
3705
3706 /*
3707 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3708 * have the write-low and read-high bitmap offsets the wrong way round.
3709 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3710 */
25c5f225 3711 if (msr <= 0x1fff) {
3e7c73e9
AK		 3712 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3713 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3714 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3715 msr &= 0x1fff;
3e7c73e9
AK		 3716 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3717 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3718 }
25c5f225
SY		 3719}
3720
5897297b
AK		 3721static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3722{
3723 if (!longmode_only)
3724 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3725 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3726}
3727
a3a8ff8e
NHE		 3728/*
3729 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3730 * will not change in the lifetime of the guest.
3731 * Note that host-state that does change is set elsewhere. E.g., host-state
3732 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3733 */
3734static void vmx_set_constant_host_state(void)
3735{
3736 u32 low32, high32;
3737 unsigned long tmpl;
3738 struct desc_ptr dt;
3739
3740 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3741 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3742 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3743
3744 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3745#ifdef CONFIG_X86_64
3746 /*
3747 * Load null selectors, so we can avoid reloading them in
3748 * __vmx_load_host_state(), in case userspace uses the null selectors
3749 * too (the expected case).
3750 */
3751 vmcs_write16(HOST_DS_SELECTOR, 0);
3752 vmcs_write16(HOST_ES_SELECTOR, 0);
3753#else
a3a8ff8e
NHE		 3754 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3755 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3756#endif
a3a8ff8e
NHE		 3757 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3758 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3759
3760 native_store_idt(&dt);
3761 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3762
3763 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3764 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3765
3766 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3767 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3768 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3769 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3770
3771 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3772 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3773 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3774 }
3775}
3776
bf8179a0
NHE		 3777static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3778{
3779 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3780 if (enable_ept)
3781 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3782 if (is_guest_mode(&vmx->vcpu))
3783 vmx->vcpu.arch.cr4_guest_owned_bits &=
3784 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3785 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3786}
3787
3788static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3789{
3790 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3791 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3792 exec_control &= ~CPU_BASED_TPR_SHADOW;
3793#ifdef CONFIG_X86_64
3794 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3795 CPU_BASED_CR8_LOAD_EXITING;
3796#endif
3797 }
3798 if (!enable_ept)
3799 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3800 CPU_BASED_CR3_LOAD_EXITING |
3801 CPU_BASED_INVLPG_EXITING;
3802 return exec_control;
3803}
3804
3805static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3806{
3807 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3808 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3809 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3810 if (vmx->vpid == 0)
3811 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3812 if (!enable_ept) {
3813 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3814 enable_unrestricted_guest = 0;
ad756a16
MJ		 3815 /* Enable INVPCID for non-ept guests may cause performance regression. */
3816 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3817 }
3818 if (!enable_unrestricted_guest)
3819 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3820 if (!ple_gap)
3821 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3822 return exec_control;
3823}
3824
ce88decf
XG		 3825static void ept_set_mmio_spte_mask(void)
3826{
3827 /*
3828 * EPT Misconfigurations can be generated if the value of bits 2:0
3829 * of an EPT paging-structure entry is 110b (write/execute).
3830 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3831 * spte.
3832 */
3833 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3834}
3835
6aa8b732
AK		 3836/*
3837 * Sets up the vmcs for emulated real mode.
3838 */
8b9cf98c 3839static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3840{
2e4ce7f5 3841#ifdef CONFIG_X86_64
6aa8b732 3842 unsigned long a;
2e4ce7f5 3843#endif
6aa8b732 3844 int i;
6aa8b732 3845
6aa8b732 3846 /* I/O */
3e7c73e9
AK		 3847 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3848 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3849
25c5f225 3850 if (cpu_has_vmx_msr_bitmap())
5897297b 3851 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3852
6aa8b732
AK		 3853 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3854
6aa8b732 3855 /* Control */
1c3d14fe
YS		 3856 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3857 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3858
bf8179a0 3859 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3860
83ff3b9d 3861 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3862 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3863 vmx_secondary_exec_control(vmx));
83ff3b9d 3864 }
f78e0e2e 3865
4b8d54f9
ZE		 3866 if (ple_gap) {
3867 vmcs_write32(PLE_GAP, ple_gap);
3868 vmcs_write32(PLE_WINDOW, ple_window);
3869 }
3870
c3707958
XG		 3871 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3872 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3873 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3874
9581d442
AK		 3875 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3876 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3877 vmx_set_constant_host_state();
05b3e0c2 3878#ifdef CONFIG_X86_64
6aa8b732
AK		 3879 rdmsrl(MSR_FS_BASE, a);
3880 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3881 rdmsrl(MSR_GS_BASE, a);
3882 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3883#else
3884 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3885 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3886#endif
3887
2cc51560
ED		 3888 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3889 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3890 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3891 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3892 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3893
468d472f 3894 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3895 u32 msr_low, msr_high;
3896 u64 host_pat;
468d472f
SY		 3897 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3898 host_pat = msr_low | ((u64) msr_high << 32);
3899 /* Write the default value follow host pat */
3900 vmcs_write64(GUEST_IA32_PAT, host_pat);
3901 /* Keep arch.pat sync with GUEST_IA32_PAT */
3902 vmx->vcpu.arch.pat = host_pat;
3903 }
3904
6aa8b732
AK		 3905 for (i = 0; i < NR_VMX_MSR; ++i) {
3906 u32 index = vmx_msr_index[i];
3907 u32 data_low, data_high;
a2fa3e9f 3908 int j = vmx->nmsrs;
6aa8b732
AK		 3909
3910 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3911 continue;
432bd6cb
AK		 3912 if (wrmsr_safe(index, data_low, data_high) < 0)
3913 continue;
26bb0981
AK		 3914 vmx->guest_msrs[j].index = i;
3915 vmx->guest_msrs[j].data = 0;
d5696725 3916 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3917 ++vmx->nmsrs;
6aa8b732 3918 }
6aa8b732 3919
1c3d14fe 3920 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3921
3922 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3923 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3924
e00c8cf2 3925 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3926 set_cr4_guest_host_mask(vmx);
e00c8cf2 3927
99e3e30a 3928 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3929
e00c8cf2
AK		 3930 return 0;
3931}
3932
3933static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3934{
3935 struct vcpu_vmx *vmx = to_vmx(vcpu);
3936 u64 msr;
4b9d3a04 3937 int ret;
e00c8cf2 3938
5fdbf976 3939 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3940
7ffd92c5 3941 vmx->rmode.vm86_active = 0;
e00c8cf2 3942
3b86cd99
JK		 3943 vmx->soft_vnmi_blocked = 0;
3944
ad312c7c 3945 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3946 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3947 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3948 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3949 msr |= MSR_IA32_APICBASE_BSP;
3950 kvm_set_apic_base(&vmx->vcpu, msr);
3951
10ab25cd
JK		 3952 ret = fx_init(&vmx->vcpu);
3953 if (ret != 0)
3954 goto out;
e00c8cf2 3955
2fb92db1
AK		 3956 vmx_segment_cache_clear(vmx);
3957
5706be0d 3958 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3959 /*
3960 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3961 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3962 */
c5af89b6 3963 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3964 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3965 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3966 } else {
ad312c7c
ZX		 3967 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3968 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3969 }
e00c8cf2
AK		 3970
3971 seg_setup(VCPU_SREG_DS);
3972 seg_setup(VCPU_SREG_ES);
3973 seg_setup(VCPU_SREG_FS);
3974 seg_setup(VCPU_SREG_GS);
3975 seg_setup(VCPU_SREG_SS);
3976
3977 vmcs_write16(GUEST_TR_SELECTOR, 0);
3978 vmcs_writel(GUEST_TR_BASE, 0);
3979 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3980 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3981
3982 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3983 vmcs_writel(GUEST_LDTR_BASE, 0);
3984 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3985 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3986
3987 vmcs_write32(GUEST_SYSENTER_CS, 0);
3988 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3989 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3990
3991 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3992 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3993 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3994 else
5fdbf976
MT		 3995 kvm_rip_write(vcpu, 0);
3996 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3997
e00c8cf2
AK		 3998 vmcs_writel(GUEST_DR7, 0x400);
3999
4000 vmcs_writel(GUEST_GDTR_BASE, 0);
4001 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4002
4003 vmcs_writel(GUEST_IDTR_BASE, 0);
4004 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4005
443381a8 4006 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4007 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4008 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4009
e00c8cf2
AK		 4010 /* Special registers */
4011 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4012
4013 setup_msrs(vmx);
4014
6aa8b732
AK		 4015 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4016
f78e0e2e
SY		 4017 if (cpu_has_vmx_tpr_shadow()) {
4018 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4019 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4020 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4021 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4022 vmcs_write32(TPR_THRESHOLD, 0);
4023 }
4024
4025 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4026 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4027 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4028
2384d2b3
SY		 4029 if (vmx->vpid != 0)
4030 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4031
fa40052c 4032 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4033 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4034 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4035 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4036 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4037 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4038 vmx_fpu_activate(&vmx->vcpu);
4039 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4040
b9d762fa 4041 vpid_sync_context(vmx);
2384d2b3 4042
3200f405 4043 ret = 0;
6aa8b732 4044
a89a8fb9
MG		 4045 /* HACK: Don't enable emulation on guest boot/reset */
4046 vmx->emulation_required = 0;
4047
6aa8b732
AK		 4048out:
4049 return ret;
4050}
4051
b6f1250e
NHE		 4052/*
4053 * In nested virtualization, check if L1 asked to exit on external interrupts.
4054 * For most existing hypervisors, this will always return true.
4055 */
4056static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4057{
4058 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4059 PIN_BASED_EXT_INTR_MASK;
4060}
4061
3b86cd99
JK		 4062static void enable_irq_window(struct kvm_vcpu *vcpu)
4063{
4064 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4065 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4066 /*
4067 * We get here if vmx_interrupt_allowed() said we can't
4068 * inject to L1 now because L2 must run. Ask L2 to exit
4069 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4070 */
d6185f20 4071 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4072 return;
d6185f20 4073 }
3b86cd99
JK		 4074
4075 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4076 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4077 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4078}
4079
4080static void enable_nmi_window(struct kvm_vcpu *vcpu)
4081{
4082 u32 cpu_based_vm_exec_control;
4083
4084 if (!cpu_has_virtual_nmis()) {
4085 enable_irq_window(vcpu);
4086 return;
4087 }
4088
30bd0c4c
AK		 4089 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4090 enable_irq_window(vcpu);
4091 return;
4092 }
3b86cd99
JK		 4093 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4094 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4095 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4096}
4097
66fd3f7f 4098static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4099{
9c8cba37 4100 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4101 uint32_t intr;
4102 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4103
229456fc 4104 trace_kvm_inj_virq(irq);
2714d1d3 4105
fa89a817 4106 ++vcpu->stat.irq_injections;
7ffd92c5 4107 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4108 int inc_eip = 0;
4109 if (vcpu->arch.interrupt.soft)
4110 inc_eip = vcpu->arch.event_exit_inst_len;
4111 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4112 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4113 return;
4114 }
66fd3f7f
GN		 4115 intr = irq | INTR_INFO_VALID_MASK;
4116 if (vcpu->arch.interrupt.soft) {
4117 intr |= INTR_TYPE_SOFT_INTR;
4118 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4119 vmx->vcpu.arch.event_exit_inst_len);
4120 } else
4121 intr |= INTR_TYPE_EXT_INTR;
4122 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4123}
4124
f08864b4
SY		 4125static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4126{
66a5a347
JK		 4127 struct vcpu_vmx *vmx = to_vmx(vcpu);
4128
0b6ac343
NHE		 4129 if (is_guest_mode(vcpu))
4130 return;
4131
3b86cd99
JK		 4132 if (!cpu_has_virtual_nmis()) {
4133 /*
4134 * Tracking the NMI-blocked state in software is built upon
4135 * finding the next open IRQ window. This, in turn, depends on
4136 * well-behaving guests: They have to keep IRQs disabled at
4137 * least as long as the NMI handler runs. Otherwise we may
4138 * cause NMI nesting, maybe breaking the guest. But as this is
4139 * highly unlikely, we can live with the residual risk.
4140 */
4141 vmx->soft_vnmi_blocked = 1;
4142 vmx->vnmi_blocked_time = 0;
4143 }
4144
487b391d 4145 ++vcpu->stat.nmi_injections;
9d58b931 4146 vmx->nmi_known_unmasked = false;
7ffd92c5 4147 if (vmx->rmode.vm86_active) {
71f9833b 4148 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4149 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4150 return;
4151 }
f08864b4
SY		 4152 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4153 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4154}
4155
c4282df9 4156static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4157{
3b86cd99 4158 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4159 return 0;
33f089ca 4160
c4282df9 4161 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4162 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4163 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4164}
4165
3cfc3092
JK		 4166static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4167{
4168 if (!cpu_has_virtual_nmis())
4169 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4170 if (to_vmx(vcpu)->nmi_known_unmasked)
4171 return false;
c332c83a 4172 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4173}
4174
4175static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4176{
4177 struct vcpu_vmx *vmx = to_vmx(vcpu);
4178
4179 if (!cpu_has_virtual_nmis()) {
4180 if (vmx->soft_vnmi_blocked != masked) {
4181 vmx->soft_vnmi_blocked = masked;
4182 vmx->vnmi_blocked_time = 0;
4183 }
4184 } else {
9d58b931 4185 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4186 if (masked)
4187 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4188 GUEST_INTR_STATE_NMI);
4189 else
4190 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4191 GUEST_INTR_STATE_NMI);
4192 }
4193}
4194
78646121
GN		 4195static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4196{
b6f1250e 4197 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4198 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4199 if (to_vmx(vcpu)->nested.nested_run_pending ||
4200 (vmcs12->idt_vectoring_info_field &
4201 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4202 return 0;
4203 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4204 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4205 vmcs12->vm_exit_intr_info = 0;
4206 /* fall through to normal code, but now in L1, not L2 */
4207 }
4208
c4282df9
GN		 4209 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4210 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4211 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4212}
4213
cbc94022
IE		 4214static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4215{
4216 int ret;
4217 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4218 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4219 .guest_phys_addr = addr,
4220 .memory_size = PAGE_SIZE * 3,
4221 .flags = 0,
4222 };
4223
4224 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4225 if (ret)
4226 return ret;
bfc6d222 4227 kvm->arch.tss_addr = addr;
93ea5388
GN		 4228 if (!init_rmode_tss(kvm))
4229 return -ENOMEM;
4230
cbc94022
IE		 4231 return 0;
4232}
4233
6aa8b732
AK		 4234static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4235 int vec, u32 err_code)
4236{
b3f37707
NK		 4237 /*
4238 * Instruction with address size override prefix opcode 0x67
4239 * Cause the #SS fault with 0 error code in VM86 mode.
4240 */
4241 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4242 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4243 return 1;
77ab6db0
JK		 4244 /*
4245 * Forward all other exceptions that are valid in real mode.
4246 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4247 * the required debugging infrastructure rework.
4248 */
4249 switch (vec) {
77ab6db0 4250 case DB_VECTOR:
d0bfb940
JK		 4251 if (vcpu->guest_debug &
4252 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4253 return 0;
4254 kvm_queue_exception(vcpu, vec);
4255 return 1;
77ab6db0 4256 case BP_VECTOR:
c573cd22
JK		 4257 /*
4258 * Update instruction length as we may reinject the exception
4259 * from user space while in guest debugging mode.
4260 */
4261 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4262 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4263 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4264 return 0;
4265 /* fall through */
4266 case DE_VECTOR:
77ab6db0
JK		 4267 case OF_VECTOR:
4268 case BR_VECTOR:
4269 case UD_VECTOR:
4270 case DF_VECTOR:
4271 case SS_VECTOR:
4272 case GP_VECTOR:
4273 case MF_VECTOR:
4274 kvm_queue_exception(vcpu, vec);
4275 return 1;
4276 }
6aa8b732
AK		 4277 return 0;
4278}
4279
a0861c02
AK		 4280/*
4281 * Trigger machine check on the host. We assume all the MSRs are already set up
4282 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4283 * We pass a fake environment to the machine check handler because we want
4284 * the guest to be always treated like user space, no matter what context
4285 * it used internally.
4286 */
4287static void kvm_machine_check(void)
4288{
4289#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4290 struct pt_regs regs = {
4291 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4292 .flags = X86_EFLAGS_IF,
4293 };
4294
4295 do_machine_check(&regs, 0);
4296#endif
4297}
4298
851ba692 4299static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4300{
4301 /* already handled by vcpu_run */
4302 return 1;
4303}
4304
851ba692 4305static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4306{
1155f76a 4307 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4308 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4309 u32 intr_info, ex_no, error_code;
42dbaa5a 4310 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4311 u32 vect_info;
4312 enum emulation_result er;
4313
1155f76a 4314 vect_info = vmx->idt_vectoring_info;
88786475 4315 intr_info = vmx->exit_intr_info;
6aa8b732 4316
a0861c02 4317 if (is_machine_check(intr_info))
851ba692 4318 return handle_machine_check(vcpu);
a0861c02 4319
6aa8b732 4320 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4321 !is_page_fault(intr_info)) {
4322 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4323 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4324 vcpu->run->internal.ndata = 2;
4325 vcpu->run->internal.data[0] = vect_info;
4326 vcpu->run->internal.data[1] = intr_info;
4327 return 0;
4328 }
6aa8b732 4329
e4a41889 4330 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4331 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4332
4333 if (is_no_device(intr_info)) {
5fd86fcf 4334 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4335 return 1;
4336 }
4337
7aa81cc0 4338 if (is_invalid_opcode(intr_info)) {
51d8b661 4339 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4340 if (er != EMULATE_DONE)
7ee5d940 4341 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4342 return 1;
4343 }
4344
6aa8b732 4345 error_code = 0;
2e11384c 4346 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4347 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4348 if (is_page_fault(intr_info)) {
1439442c 4349 /* EPT won't cause page fault directly */
cf3ace79 4350 BUG_ON(enable_ept);
6aa8b732 4351 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4352 trace_kvm_page_fault(cr2, error_code);
4353
3298b75c 4354 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4355 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4356 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4357 }
4358
7ffd92c5 4359 if (vmx->rmode.vm86_active &&
6aa8b732 4360 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4361 error_code)) {
ad312c7c
ZX		 4362 if (vcpu->arch.halt_request) {
4363 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4364 return kvm_emulate_halt(vcpu);
4365 }
6aa8b732 4366 return 1;
72d6e5a0 4367 }
6aa8b732 4368
d0bfb940 4369 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4370 switch (ex_no) {
4371 case DB_VECTOR:
4372 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4373 if (!(vcpu->guest_debug &
4374 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4375 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4376 kvm_queue_exception(vcpu, DB_VECTOR);
4377 return 1;
4378 }
4379 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4380 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4381 /* fall through */
4382 case BP_VECTOR:
c573cd22
JK		 4383 /*
4384 * Update instruction length as we may reinject #BP from
4385 * user space while in guest debugging mode. Reading it for
4386 * #DB as well causes no harm, it is not used in that case.
4387 */
4388 vmx->vcpu.arch.event_exit_inst_len =
4389 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4390 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4391 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4392 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4393 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4394 break;
4395 default:
d0bfb940
JK		 4396 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4397 kvm_run->ex.exception = ex_no;
4398 kvm_run->ex.error_code = error_code;
42dbaa5a 4399 break;
6aa8b732 4400 }
6aa8b732
AK		 4401 return 0;
4402}
4403
851ba692 4404static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4405{
1165f5fe 4406 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4407 return 1;
4408}
4409
851ba692 4410static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4411{
851ba692 4412 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4413 return 0;
4414}
6aa8b732 4415
851ba692 4416static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4417{
bfdaab09 4418 unsigned long exit_qualification;
34c33d16 4419 int size, in, string;
039576c0 4420 unsigned port;
6aa8b732 4421
bfdaab09 4422 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4423 string = (exit_qualification & 16) != 0;
cf8f70bf 4424 in = (exit_qualification & 8) != 0;
e70669ab 4425
cf8f70bf 4426 ++vcpu->stat.io_exits;
e70669ab 4427
cf8f70bf 4428 if (string || in)
51d8b661 4429 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4430
cf8f70bf
GN		 4431 port = exit_qualification >> 16;
4432 size = (exit_qualification & 7) + 1;
e93f36bc 4433 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4434
4435 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4436}
4437
102d8325
IM		 4438static void
4439vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4440{
4441 /*
4442 * Patch in the VMCALL instruction:
4443 */
4444 hypercall[0] = 0x0f;
4445 hypercall[1] = 0x01;
4446 hypercall[2] = 0xc1;
102d8325
IM		 4447}
4448
eeadf9e7
NHE		 4449/* called to set cr0 as approriate for a mov-to-cr0 exit. */
4450static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4451{
4452 if (to_vmx(vcpu)->nested.vmxon &&
4453 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4454 return 1;
4455
4456 if (is_guest_mode(vcpu)) {
4457 /*
4458 * We get here when L2 changed cr0 in a way that did not change
4459 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4460 * but did change L0 shadowed bits. This can currently happen
4461 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4462 * loading) while pretending to allow the guest to change it.
4463 */
4464 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4465 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4466 return 1;
4467 vmcs_writel(CR0_READ_SHADOW, val);
4468 return 0;
4469 } else
4470 return kvm_set_cr0(vcpu, val);
4471}
4472
4473static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4474{
4475 if (is_guest_mode(vcpu)) {
4476 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4477 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4478 return 1;
4479 vmcs_writel(CR4_READ_SHADOW, val);
4480 return 0;
4481 } else
4482 return kvm_set_cr4(vcpu, val);
4483}
4484
4485/* called to set cr0 as approriate for clts instruction exit. */
4486static void handle_clts(struct kvm_vcpu *vcpu)
4487{
4488 if (is_guest_mode(vcpu)) {
4489 /*
4490 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4491 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4492 * just pretend it's off (also in arch.cr0 for fpu_activate).
4493 */
4494 vmcs_writel(CR0_READ_SHADOW,
4495 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4496 vcpu->arch.cr0 &= ~X86_CR0_TS;
4497 } else
4498 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4499}
4500
851ba692 4501static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4502{
229456fc 4503 unsigned long exit_qualification, val;
6aa8b732
AK		 4504 int cr;
4505 int reg;
49a9b07e 4506 int err;
6aa8b732 4507
bfdaab09 4508 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4509 cr = exit_qualification & 15;
4510 reg = (exit_qualification >> 8) & 15;
4511 switch ((exit_qualification >> 4) & 3) {
4512 case 0: /* mov to cr */
229456fc
MT		 4513 val = kvm_register_read(vcpu, reg);
4514 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4515 switch (cr) {
4516 case 0:
eeadf9e7 4517 err = handle_set_cr0(vcpu, val);
db8fcefa 4518 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4519 return 1;
4520 case 3:
2390218b 4521 err = kvm_set_cr3(vcpu, val);
db8fcefa 4522 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4523 return 1;
4524 case 4:
eeadf9e7 4525 err = handle_set_cr4(vcpu, val);
db8fcefa 4526 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4527 return 1;
0a5fff19
GN		 4528 case 8: {
4529 u8 cr8_prev = kvm_get_cr8(vcpu);
4530 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4531 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4532 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4533 if (irqchip_in_kernel(vcpu->kvm))
4534 return 1;
4535 if (cr8_prev <= cr8)
4536 return 1;
851ba692 4537 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4538 return 0;
4539 }
6aa8b732
AK		 4540 };
4541 break;
25c4c276 4542 case 2: /* clts */
eeadf9e7 4543 handle_clts(vcpu);
4d4ec087 4544 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4545 skip_emulated_instruction(vcpu);
6b52d186 4546 vmx_fpu_activate(vcpu);
25c4c276 4547 return 1;
6aa8b732
AK		 4548 case 1: /*mov from cr*/
4549 switch (cr) {
4550 case 3:
9f8fe504
AK		 4551 val = kvm_read_cr3(vcpu);
4552 kvm_register_write(vcpu, reg, val);
4553 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4554 skip_emulated_instruction(vcpu);
4555 return 1;
4556 case 8:
229456fc
MT		 4557 val = kvm_get_cr8(vcpu);
4558 kvm_register_write(vcpu, reg, val);
4559 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4560 skip_emulated_instruction(vcpu);
4561 return 1;
4562 }
4563 break;
4564 case 3: /* lmsw */
a1f83a74 4565 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4566 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4567 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4568
4569 skip_emulated_instruction(vcpu);
4570 return 1;
4571 default:
4572 break;
4573 }
851ba692 4574 vcpu->run->exit_reason = 0;
a737f256 4575 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4576 (int)(exit_qualification >> 4) & 3, cr);
4577 return 0;
4578}
4579
851ba692 4580static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4581{
bfdaab09 4582 unsigned long exit_qualification;
6aa8b732
AK		 4583 int dr, reg;
4584
f2483415 4585 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4586 if (!kvm_require_cpl(vcpu, 0))
4587 return 1;
42dbaa5a
JK		 4588 dr = vmcs_readl(GUEST_DR7);
4589 if (dr & DR7_GD) {
4590 /*
4591 * As the vm-exit takes precedence over the debug trap, we
4592 * need to emulate the latter, either for the host or the
4593 * guest debugging itself.
4594 */
4595 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4596 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4597 vcpu->run->debug.arch.dr7 = dr;
4598 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4599 vmcs_readl(GUEST_CS_BASE) +
4600 vmcs_readl(GUEST_RIP);
851ba692
AK		 4601 vcpu->run->debug.arch.exception = DB_VECTOR;
4602 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4603 return 0;
4604 } else {
4605 vcpu->arch.dr7 &= ~DR7_GD;
4606 vcpu->arch.dr6 |= DR6_BD;
4607 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4608 kvm_queue_exception(vcpu, DB_VECTOR);
4609 return 1;
4610 }
4611 }
4612
bfdaab09 4613 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4614 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4615 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4616 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4617 unsigned long val;
4618 if (!kvm_get_dr(vcpu, dr, &val))
4619 kvm_register_write(vcpu, reg, val);
4620 } else
4621 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4622 skip_emulated_instruction(vcpu);
4623 return 1;
4624}
4625
020df079
GN		 4626static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4627{
4628 vmcs_writel(GUEST_DR7, val);
4629}
4630
851ba692 4631static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4632{
06465c5a
AK		 4633 kvm_emulate_cpuid(vcpu);
4634 return 1;
6aa8b732
AK		 4635}
4636
851ba692 4637static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4638{
ad312c7c 4639 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4640 u64 data;
4641
4642 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4643 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4644 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4645 return 1;
4646 }
4647
229456fc 4648 trace_kvm_msr_read(ecx, data);
2714d1d3 4649
6aa8b732 4650 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4651 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4652 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4653 skip_emulated_instruction(vcpu);
4654 return 1;
4655}
4656
851ba692 4657static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4658{
ad312c7c
ZX		 4659 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4660 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4661 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4662
4663 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4664 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4665 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4666 return 1;
4667 }
4668
59200273 4669 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4670 skip_emulated_instruction(vcpu);
4671 return 1;
4672}
4673
851ba692 4674static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4675{
3842d135 4676 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4677 return 1;
4678}
4679
851ba692 4680static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4681{
85f455f7
ED		 4682 u32 cpu_based_vm_exec_control;
4683
4684 /* clear pending irq */
4685 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4686 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4687 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4688
3842d135
AK		 4689 kvm_make_request(KVM_REQ_EVENT, vcpu);
4690
a26bf12a 4691 ++vcpu->stat.irq_window_exits;
2714d1d3 4692
c1150d8c
DL		 4693 /*
4694 * If the user space waits to inject interrupts, exit as soon as
4695 * possible
4696 */
8061823a 4697 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4698 vcpu->run->request_interrupt_window &&
8061823a 4699 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4700 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4701 return 0;
4702 }
6aa8b732
AK		 4703 return 1;
4704}
4705
851ba692 4706static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4707{
4708 skip_emulated_instruction(vcpu);
d3bef15f 4709 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4710}
4711
851ba692 4712static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4713{
510043da 4714 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4715 kvm_emulate_hypercall(vcpu);
4716 return 1;
c21415e8
IM		 4717}
4718
ec25d5e6
GN		 4719static int handle_invd(struct kvm_vcpu *vcpu)
4720{
51d8b661 4721 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4722}
4723
851ba692 4724static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4725{
f9c617f6 4726 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4727
4728 kvm_mmu_invlpg(vcpu, exit_qualification);
4729 skip_emulated_instruction(vcpu);
4730 return 1;
4731}
4732
fee84b07
AK		 4733static int handle_rdpmc(struct kvm_vcpu *vcpu)
4734{
4735 int err;
4736
4737 err = kvm_rdpmc(vcpu);
4738 kvm_complete_insn_gp(vcpu, err);
4739
4740 return 1;
4741}
4742
851ba692 4743static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4744{
4745 skip_emulated_instruction(vcpu);
f5f48ee1 4746 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4747 return 1;
4748}
4749
2acf923e
DC		 4750static int handle_xsetbv(struct kvm_vcpu *vcpu)
4751{
4752 u64 new_bv = kvm_read_edx_eax(vcpu);
4753 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4754
4755 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4756 skip_emulated_instruction(vcpu);
4757 return 1;
4758}
4759
851ba692 4760static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4761{
58fbbf26
KT		 4762 if (likely(fasteoi)) {
4763 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4764 int access_type, offset;
4765
4766 access_type = exit_qualification & APIC_ACCESS_TYPE;
4767 offset = exit_qualification & APIC_ACCESS_OFFSET;
4768 /*
4769 * Sane guest uses MOV to write EOI, with written value
4770 * not cared. So make a short-circuit here by avoiding
4771 * heavy instruction emulation.
4772 */
4773 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4774 (offset == APIC_EOI)) {
4775 kvm_lapic_set_eoi(vcpu);
4776 skip_emulated_instruction(vcpu);
4777 return 1;
4778 }
4779 }
51d8b661 4780 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4781}
4782
851ba692 4783static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4784{
60637aac 4785 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4786 unsigned long exit_qualification;
e269fb21
JK		 4787 bool has_error_code = false;
4788 u32 error_code = 0;
37817f29 4789 u16 tss_selector;
7f3d35fd 4790 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4791
4792 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4793 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4794 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4795
4796 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4797
4798 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4799 if (reason == TASK_SWITCH_GATE && idt_v) {
4800 switch (type) {
4801 case INTR_TYPE_NMI_INTR:
4802 vcpu->arch.nmi_injected = false;
654f06fc 4803 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4804 break;
4805 case INTR_TYPE_EXT_INTR:
66fd3f7f 4806 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4807 kvm_clear_interrupt_queue(vcpu);
4808 break;
4809 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4810 if (vmx->idt_vectoring_info &
4811 VECTORING_INFO_DELIVER_CODE_MASK) {
4812 has_error_code = true;
4813 error_code =
4814 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4815 }
4816 /* fall through */
64a7ec06
GN		 4817 case INTR_TYPE_SOFT_EXCEPTION:
4818 kvm_clear_exception_queue(vcpu);
4819 break;
4820 default:
4821 break;
4822 }
60637aac 4823 }
37817f29
IE		 4824 tss_selector = exit_qualification;
4825
64a7ec06
GN		 4826 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4827 type != INTR_TYPE_EXT_INTR &&
4828 type != INTR_TYPE_NMI_INTR))
4829 skip_emulated_instruction(vcpu);
4830
7f3d35fd
KW		 4831 if (kvm_task_switch(vcpu, tss_selector,
4832 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4833 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4834 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4835 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4836 vcpu->run->internal.ndata = 0;
42dbaa5a 4837 return 0;
acb54517 4838 }
42dbaa5a
JK		 4839
4840 /* clear all local breakpoint enable flags */
4841 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4842
4843 /*
4844 * TODO: What about debug traps on tss switch?
4845 * Are we supposed to inject them and update dr6?
4846 */
4847
4848 return 1;
37817f29
IE		 4849}
4850
851ba692 4851static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4852{
f9c617f6 4853 unsigned long exit_qualification;
1439442c 4854 gpa_t gpa;
4f5982a5 4855 u32 error_code;
1439442c 4856 int gla_validity;
1439442c 4857
f9c617f6 4858 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4859
4860 if (exit_qualification & (1 << 6)) {
4861 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4862 return -EINVAL;
1439442c
SY		 4863 }
4864
4865 gla_validity = (exit_qualification >> 7) & 0x3;
4866 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4867 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4868 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4869 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4870 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4871 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4872 (long unsigned int)exit_qualification);
851ba692
AK		 4873 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4874 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4875 return 0;
1439442c
SY		 4876 }
4877
4878 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4879 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 4880
4881 /* It is a write fault? */
4882 error_code = exit_qualification & (1U << 1);
4883 /* ept page table is present? */
4884 error_code |= (exit_qualification >> 3) & 0x1;
4885
4886 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 4887}
4888
68f89400
MT		 4889static u64 ept_rsvd_mask(u64 spte, int level)
4890{
4891 int i;
4892 u64 mask = 0;
4893
4894 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4895 mask |= (1ULL << i);
4896
4897 if (level > 2)
4898 /* bits 7:3 reserved */
4899 mask |= 0xf8;
4900 else if (level == 2) {
4901 if (spte & (1ULL << 7))
4902 /* 2MB ref, bits 20:12 reserved */
4903 mask |= 0x1ff000;
4904 else
4905 /* bits 6:3 reserved */
4906 mask |= 0x78;
4907 }
4908
4909 return mask;
4910}
4911
4912static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4913 int level)
4914{
4915 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4916
4917 /* 010b (write-only) */
4918 WARN_ON((spte & 0x7) == 0x2);
4919
4920 /* 110b (write/execute) */
4921 WARN_ON((spte & 0x7) == 0x6);
4922
4923 /* 100b (execute-only) and value not supported by logical processor */
4924 if (!cpu_has_vmx_ept_execute_only())
4925 WARN_ON((spte & 0x7) == 0x4);
4926
4927 /* not 000b */
4928 if ((spte & 0x7)) {
4929 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4930
4931 if (rsvd_bits != 0) {
4932 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4933 __func__, rsvd_bits);
4934 WARN_ON(1);
4935 }
4936
4937 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4938 u64 ept_mem_type = (spte & 0x38) >> 3;
4939
4940 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4941 ept_mem_type == 7) {
4942 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4943 __func__, ept_mem_type);
4944 WARN_ON(1);
4945 }
4946 }
4947 }
4948}
4949
851ba692 4950static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4951{
4952 u64 sptes[4];
ce88decf 4953 int nr_sptes, i, ret;
68f89400
MT		 4954 gpa_t gpa;
4955
4956 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4957
ce88decf
XG		 4958 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4959 if (likely(ret == 1))
4960 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4961 EMULATE_DONE;
4962 if (unlikely(!ret))
4963 return 1;
4964
4965 /* It is the real ept misconfig */
68f89400
MT		 4966 printk(KERN_ERR "EPT: Misconfiguration.\n");
4967 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4968
4969 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4970
4971 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4972 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4973
851ba692
AK		 4974 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4975 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4976
4977 return 0;
4978}
4979
851ba692 4980static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4981{
4982 u32 cpu_based_vm_exec_control;
4983
4984 /* clear pending NMI */
4985 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4986 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4987 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4988 ++vcpu->stat.nmi_window_exits;
3842d135 4989 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4990
4991 return 1;
4992}
4993
80ced186 4994static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4995{
8b3079a5
AK		 4996 struct vcpu_vmx *vmx = to_vmx(vcpu);
4997 enum emulation_result err = EMULATE_DONE;
80ced186 4998 int ret = 1;
49e9d557
AK		 4999 u32 cpu_exec_ctrl;
5000 bool intr_window_requested;
b8405c18 5001 unsigned count = 130;
49e9d557
AK		 5002
5003 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5004 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5005
b8405c18 5006 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5007 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5008 return handle_interrupt_window(&vmx->vcpu);
5009
de87dcdd
AK		 5010 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5011 return 1;
5012
51d8b661 5013 err = emulate_instruction(vcpu, 0);
ea953ef0 5014
80ced186
MG		 5015 if (err == EMULATE_DO_MMIO) {
5016 ret = 0;
5017 goto out;
5018 }
1d5a4d9b 5019
de5f70e0
AK		 5020 if (err != EMULATE_DONE) {
5021 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5022 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5023 vcpu->run->internal.ndata = 0;
6d77dbfc 5024 return 0;
de5f70e0 5025 }
ea953ef0
MG		 5026
5027 if (signal_pending(current))
80ced186 5028 goto out;
ea953ef0
MG		 5029 if (need_resched())
5030 schedule();
5031 }
5032
7c068e45 5033 vmx->emulation_required = !guest_state_valid(vcpu);
80ced186
MG		 5034out:
5035 return ret;
ea953ef0
MG		 5036}
5037
4b8d54f9
ZE		 5038/*
5039 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5040 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5041 */
9fb41ba8 5042static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5043{
5044 skip_emulated_instruction(vcpu);
5045 kvm_vcpu_on_spin(vcpu);
5046
5047 return 1;
5048}
5049
59708670
SY		 5050static int handle_invalid_op(struct kvm_vcpu *vcpu)
5051{
5052 kvm_queue_exception(vcpu, UD_VECTOR);
5053 return 1;
5054}
5055
ff2f6fe9
NHE		 5056/*
5057 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5058 * We could reuse a single VMCS for all the L2 guests, but we also want the
5059 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5060 * allows keeping them loaded on the processor, and in the future will allow
5061 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5062 * every entry if they never change.
5063 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5064 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5065 *
5066 * The following functions allocate and free a vmcs02 in this pool.
5067 */
5068
5069/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5070static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5071{
5072 struct vmcs02_list *item;
5073 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5074 if (item->vmptr == vmx->nested.current_vmptr) {
5075 list_move(&item->list, &vmx->nested.vmcs02_pool);
5076 return &item->vmcs02;
5077 }
5078
5079 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5080 /* Recycle the least recently used VMCS. */
5081 item = list_entry(vmx->nested.vmcs02_pool.prev,
5082 struct vmcs02_list, list);
5083 item->vmptr = vmx->nested.current_vmptr;
5084 list_move(&item->list, &vmx->nested.vmcs02_pool);
5085 return &item->vmcs02;
5086 }
5087
5088 /* Create a new VMCS */
5089 item = (struct vmcs02_list *)
5090 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5091 if (!item)
5092 return NULL;
5093 item->vmcs02.vmcs = alloc_vmcs();
5094 if (!item->vmcs02.vmcs) {
5095 kfree(item);
5096 return NULL;
5097 }
5098 loaded_vmcs_init(&item->vmcs02);
5099 item->vmptr = vmx->nested.current_vmptr;
5100 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5101 vmx->nested.vmcs02_num++;
5102 return &item->vmcs02;
5103}
5104
5105/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5106static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5107{
5108 struct vmcs02_list *item;
5109 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5110 if (item->vmptr == vmptr) {
5111 free_loaded_vmcs(&item->vmcs02);
5112 list_del(&item->list);
5113 kfree(item);
5114 vmx->nested.vmcs02_num--;
5115 return;
5116 }
5117}
5118
5119/*
5120 * Free all VMCSs saved for this vcpu, except the one pointed by
5121 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5122 * currently used, if running L2), and vmcs01 when running L2.
5123 */
5124static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5125{
5126 struct vmcs02_list *item, *n;
5127 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5128 if (vmx->loaded_vmcs != &item->vmcs02)
5129 free_loaded_vmcs(&item->vmcs02);
5130 list_del(&item->list);
5131 kfree(item);
5132 }
5133 vmx->nested.vmcs02_num = 0;
5134
5135 if (vmx->loaded_vmcs != &vmx->vmcs01)
5136 free_loaded_vmcs(&vmx->vmcs01);
5137}
5138
ec378aee
NHE		 5139/*
5140 * Emulate the VMXON instruction.
5141 * Currently, we just remember that VMX is active, and do not save or even
5142 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5143 * do not currently need to store anything in that guest-allocated memory
5144 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5145 * argument is different from the VMXON pointer (which the spec says they do).
5146 */
5147static int handle_vmon(struct kvm_vcpu *vcpu)
5148{
5149 struct kvm_segment cs;
5150 struct vcpu_vmx *vmx = to_vmx(vcpu);
5151
5152 /* The Intel VMX Instruction Reference lists a bunch of bits that
5153 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5154 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5155 * Otherwise, we should fail with #UD. We test these now:
5156 */
5157 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5158 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5159 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5160 kvm_queue_exception(vcpu, UD_VECTOR);
5161 return 1;
5162 }
5163
5164 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5165 if (is_long_mode(vcpu) && !cs.l) {
5166 kvm_queue_exception(vcpu, UD_VECTOR);
5167 return 1;
5168 }
5169
5170 if (vmx_get_cpl(vcpu)) {
5171 kvm_inject_gp(vcpu, 0);
5172 return 1;
5173 }
5174
ff2f6fe9
NHE		 5175 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5176 vmx->nested.vmcs02_num = 0;
5177
ec378aee
NHE		 5178 vmx->nested.vmxon = true;
5179
5180 skip_emulated_instruction(vcpu);
5181 return 1;
5182}
5183
5184/*
5185 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5186 * for running VMX instructions (except VMXON, whose prerequisites are
5187 * slightly different). It also specifies what exception to inject otherwise.
5188 */
5189static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5190{
5191 struct kvm_segment cs;
5192 struct vcpu_vmx *vmx = to_vmx(vcpu);
5193
5194 if (!vmx->nested.vmxon) {
5195 kvm_queue_exception(vcpu, UD_VECTOR);
5196 return 0;
5197 }
5198
5199 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5200 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5201 (is_long_mode(vcpu) && !cs.l)) {
5202 kvm_queue_exception(vcpu, UD_VECTOR);
5203 return 0;
5204 }
5205
5206 if (vmx_get_cpl(vcpu)) {
5207 kvm_inject_gp(vcpu, 0);
5208 return 0;
5209 }
5210
5211 return 1;
5212}
5213
5214/*
5215 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5216 * just stops using VMX.
5217 */
5218static void free_nested(struct vcpu_vmx *vmx)
5219{
5220 if (!vmx->nested.vmxon)
5221 return;
5222 vmx->nested.vmxon = false;
a9d30f33
NHE		 5223 if (vmx->nested.current_vmptr != -1ull) {
5224 kunmap(vmx->nested.current_vmcs12_page);
5225 nested_release_page(vmx->nested.current_vmcs12_page);
5226 vmx->nested.current_vmptr = -1ull;
5227 vmx->nested.current_vmcs12 = NULL;
5228 }
fe3ef05c
NHE		 5229 /* Unpin physical memory we referred to in current vmcs02 */
5230 if (vmx->nested.apic_access_page) {
5231 nested_release_page(vmx->nested.apic_access_page);
5232 vmx->nested.apic_access_page = 0;
5233 }
ff2f6fe9
NHE		 5234
5235 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5236}
5237
5238/* Emulate the VMXOFF instruction */
5239static int handle_vmoff(struct kvm_vcpu *vcpu)
5240{
5241 if (!nested_vmx_check_permission(vcpu))
5242 return 1;
5243 free_nested(to_vmx(vcpu));
5244 skip_emulated_instruction(vcpu);
5245 return 1;
5246}
5247
064aea77
NHE		 5248/*
5249 * Decode the memory-address operand of a vmx instruction, as recorded on an
5250 * exit caused by such an instruction (run by a guest hypervisor).
5251 * On success, returns 0. When the operand is invalid, returns 1 and throws
5252 * #UD or #GP.
5253 */
5254static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5255 unsigned long exit_qualification,
5256 u32 vmx_instruction_info, gva_t *ret)
5257{
5258 /*
5259 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5260 * Execution", on an exit, vmx_instruction_info holds most of the
5261 * addressing components of the operand. Only the displacement part
5262 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5263 * For how an actual address is calculated from all these components,
5264 * refer to Vol. 1, "Operand Addressing".
5265 */
5266 int scaling = vmx_instruction_info & 3;
5267 int addr_size = (vmx_instruction_info >> 7) & 7;
5268 bool is_reg = vmx_instruction_info & (1u << 10);
5269 int seg_reg = (vmx_instruction_info >> 15) & 7;
5270 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5271 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5272 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5273 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5274
5275 if (is_reg) {
5276 kvm_queue_exception(vcpu, UD_VECTOR);
5277 return 1;
5278 }
5279
5280 /* Addr = segment_base + offset */
5281 /* offset = base + [index * scale] + displacement */
5282 *ret = vmx_get_segment_base(vcpu, seg_reg);
5283 if (base_is_valid)
5284 *ret += kvm_register_read(vcpu, base_reg);
5285 if (index_is_valid)
5286 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5287 *ret += exit_qualification; /* holds the displacement */
5288
5289 if (addr_size == 1) /* 32 bit */
5290 *ret &= 0xffffffff;
5291
5292 /*
5293 * TODO: throw #GP (and return 1) in various cases that the VM*
5294 * instructions require it - e.g., offset beyond segment limit,
5295 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5296 * address, and so on. Currently these are not checked.
5297 */
5298 return 0;
5299}
5300
0140caea
NHE		 5301/*
5302 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5303 * set the success or error code of an emulated VMX instruction, as specified
5304 * by Vol 2B, VMX Instruction Reference, "Conventions".
5305 */
5306static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5307{
5308 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5309 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5310 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5311}
5312
5313static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5314{
5315 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5316 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5317 X86_EFLAGS_SF | X86_EFLAGS_OF))
5318 | X86_EFLAGS_CF);
5319}
5320
5321static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5322 u32 vm_instruction_error)
5323{
5324 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5325 /*
5326 * failValid writes the error number to the current VMCS, which
5327 * can't be done there isn't a current VMCS.
5328 */
5329 nested_vmx_failInvalid(vcpu);
5330 return;
5331 }
5332 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5333 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5334 X86_EFLAGS_SF | X86_EFLAGS_OF))
5335 | X86_EFLAGS_ZF);
5336 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5337}
5338
27d6c865
NHE		 5339/* Emulate the VMCLEAR instruction */
5340static int handle_vmclear(struct kvm_vcpu *vcpu)
5341{
5342 struct vcpu_vmx *vmx = to_vmx(vcpu);
5343 gva_t gva;
5344 gpa_t vmptr;
5345 struct vmcs12 *vmcs12;
5346 struct page *page;
5347 struct x86_exception e;
5348
5349 if (!nested_vmx_check_permission(vcpu))
5350 return 1;
5351
5352 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5353 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5354 return 1;
5355
5356 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5357 sizeof(vmptr), &e)) {
5358 kvm_inject_page_fault(vcpu, &e);
5359 return 1;
5360 }
5361
5362 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5363 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5364 skip_emulated_instruction(vcpu);
5365 return 1;
5366 }
5367
5368 if (vmptr == vmx->nested.current_vmptr) {
5369 kunmap(vmx->nested.current_vmcs12_page);
5370 nested_release_page(vmx->nested.current_vmcs12_page);
5371 vmx->nested.current_vmptr = -1ull;
5372 vmx->nested.current_vmcs12 = NULL;
5373 }
5374
5375 page = nested_get_page(vcpu, vmptr);
5376 if (page == NULL) {
5377 /*
5378 * For accurate processor emulation, VMCLEAR beyond available
5379 * physical memory should do nothing at all. However, it is
5380 * possible that a nested vmx bug, not a guest hypervisor bug,
5381 * resulted in this case, so let's shut down before doing any
5382 * more damage:
5383 */
5384 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5385 return 1;
5386 }
5387 vmcs12 = kmap(page);
5388 vmcs12->launch_state = 0;
5389 kunmap(page);
5390 nested_release_page(page);
5391
5392 nested_free_vmcs02(vmx, vmptr);
5393
5394 skip_emulated_instruction(vcpu);
5395 nested_vmx_succeed(vcpu);
5396 return 1;
5397}
5398
cd232ad0
NHE		 5399static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5400
5401/* Emulate the VMLAUNCH instruction */
5402static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5403{
5404 return nested_vmx_run(vcpu, true);
5405}
5406
5407/* Emulate the VMRESUME instruction */
5408static int handle_vmresume(struct kvm_vcpu *vcpu)
5409{
5410
5411 return nested_vmx_run(vcpu, false);
5412}
5413
49f705c5
NHE		 5414enum vmcs_field_type {
5415 VMCS_FIELD_TYPE_U16 = 0,
5416 VMCS_FIELD_TYPE_U64 = 1,
5417 VMCS_FIELD_TYPE_U32 = 2,
5418 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5419};
5420
5421static inline int vmcs_field_type(unsigned long field)
5422{
5423 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5424 return VMCS_FIELD_TYPE_U32;
5425 return (field >> 13) & 0x3 ;
5426}
5427
5428static inline int vmcs_field_readonly(unsigned long field)
5429{
5430 return (((field >> 10) & 0x3) == 1);
5431}
5432
5433/*
5434 * Read a vmcs12 field. Since these can have varying lengths and we return
5435 * one type, we chose the biggest type (u64) and zero-extend the return value
5436 * to that size. Note that the caller, handle_vmread, might need to use only
5437 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5438 * 64-bit fields are to be returned).
5439 */
5440static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5441 unsigned long field, u64 *ret)
5442{
5443 short offset = vmcs_field_to_offset(field);
5444 char *p;
5445
5446 if (offset < 0)
5447 return 0;
5448
5449 p = ((char *)(get_vmcs12(vcpu))) + offset;
5450
5451 switch (vmcs_field_type(field)) {
5452 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5453 *ret = *((natural_width *)p);
5454 return 1;
5455 case VMCS_FIELD_TYPE_U16:
5456 *ret = *((u16 *)p);
5457 return 1;
5458 case VMCS_FIELD_TYPE_U32:
5459 *ret = *((u32 *)p);
5460 return 1;
5461 case VMCS_FIELD_TYPE_U64:
5462 *ret = *((u64 *)p);
5463 return 1;
5464 default:
5465 return 0; /* can never happen. */
5466 }
5467}
5468
5469/*
5470 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5471 * used before) all generate the same failure when it is missing.
5472 */
5473static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5474{
5475 struct vcpu_vmx *vmx = to_vmx(vcpu);
5476 if (vmx->nested.current_vmptr == -1ull) {
5477 nested_vmx_failInvalid(vcpu);
5478 skip_emulated_instruction(vcpu);
5479 return 0;
5480 }
5481 return 1;
5482}
5483
5484static int handle_vmread(struct kvm_vcpu *vcpu)
5485{
5486 unsigned long field;
5487 u64 field_value;
5488 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5489 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5490 gva_t gva = 0;
5491
5492 if (!nested_vmx_check_permission(vcpu) ||
5493 !nested_vmx_check_vmcs12(vcpu))
5494 return 1;
5495
5496 /* Decode instruction info and find the field to read */
5497 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5498 /* Read the field, zero-extended to a u64 field_value */
5499 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5500 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5501 skip_emulated_instruction(vcpu);
5502 return 1;
5503 }
5504 /*
5505 * Now copy part of this value to register or memory, as requested.
5506 * Note that the number of bits actually copied is 32 or 64 depending
5507 * on the guest's mode (32 or 64 bit), not on the given field's length.
5508 */
5509 if (vmx_instruction_info & (1u << 10)) {
5510 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5511 field_value);
5512 } else {
5513 if (get_vmx_mem_address(vcpu, exit_qualification,
5514 vmx_instruction_info, &gva))
5515 return 1;
5516 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5517 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5518 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5519 }
5520
5521 nested_vmx_succeed(vcpu);
5522 skip_emulated_instruction(vcpu);
5523 return 1;
5524}
5525
5526
5527static int handle_vmwrite(struct kvm_vcpu *vcpu)
5528{
5529 unsigned long field;
5530 gva_t gva;
5531 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5532 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5533 char *p;
5534 short offset;
5535 /* The value to write might be 32 or 64 bits, depending on L1's long
5536 * mode, and eventually we need to write that into a field of several
5537 * possible lengths. The code below first zero-extends the value to 64
5538 * bit (field_value), and then copies only the approriate number of
5539 * bits into the vmcs12 field.
5540 */
5541 u64 field_value = 0;
5542 struct x86_exception e;
5543
5544 if (!nested_vmx_check_permission(vcpu) ||
5545 !nested_vmx_check_vmcs12(vcpu))
5546 return 1;
5547
5548 if (vmx_instruction_info & (1u << 10))
5549 field_value = kvm_register_read(vcpu,
5550 (((vmx_instruction_info) >> 3) & 0xf));
5551 else {
5552 if (get_vmx_mem_address(vcpu, exit_qualification,
5553 vmx_instruction_info, &gva))
5554 return 1;
5555 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5556 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5557 kvm_inject_page_fault(vcpu, &e);
5558 return 1;
5559 }
5560 }
5561
5562
5563 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5564 if (vmcs_field_readonly(field)) {
5565 nested_vmx_failValid(vcpu,
5566 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5567 skip_emulated_instruction(vcpu);
5568 return 1;
5569 }
5570
5571 offset = vmcs_field_to_offset(field);
5572 if (offset < 0) {
5573 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5574 skip_emulated_instruction(vcpu);
5575 return 1;
5576 }
5577 p = ((char *) get_vmcs12(vcpu)) + offset;
5578
5579 switch (vmcs_field_type(field)) {
5580 case VMCS_FIELD_TYPE_U16:
5581 *(u16 *)p = field_value;
5582 break;
5583 case VMCS_FIELD_TYPE_U32:
5584 *(u32 *)p = field_value;
5585 break;
5586 case VMCS_FIELD_TYPE_U64:
5587 *(u64 *)p = field_value;
5588 break;
5589 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5590 *(natural_width *)p = field_value;
5591 break;
5592 default:
5593 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5594 skip_emulated_instruction(vcpu);
5595 return 1;
5596 }
5597
5598 nested_vmx_succeed(vcpu);
5599 skip_emulated_instruction(vcpu);
5600 return 1;
5601}
5602
63846663
NHE		 5603/* Emulate the VMPTRLD instruction */
5604static int handle_vmptrld(struct kvm_vcpu *vcpu)
5605{
5606 struct vcpu_vmx *vmx = to_vmx(vcpu);
5607 gva_t gva;
5608 gpa_t vmptr;
5609 struct x86_exception e;
5610
5611 if (!nested_vmx_check_permission(vcpu))
5612 return 1;
5613
5614 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5615 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5616 return 1;
5617
5618 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5619 sizeof(vmptr), &e)) {
5620 kvm_inject_page_fault(vcpu, &e);
5621 return 1;
5622 }
5623
5624 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5625 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5626 skip_emulated_instruction(vcpu);
5627 return 1;
5628 }
5629
5630 if (vmx->nested.current_vmptr != vmptr) {
5631 struct vmcs12 *new_vmcs12;
5632 struct page *page;
5633 page = nested_get_page(vcpu, vmptr);
5634 if (page == NULL) {
5635 nested_vmx_failInvalid(vcpu);
5636 skip_emulated_instruction(vcpu);
5637 return 1;
5638 }
5639 new_vmcs12 = kmap(page);
5640 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5641 kunmap(page);
5642 nested_release_page_clean(page);
5643 nested_vmx_failValid(vcpu,
5644 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5645 skip_emulated_instruction(vcpu);
5646 return 1;
5647 }
5648 if (vmx->nested.current_vmptr != -1ull) {
5649 kunmap(vmx->nested.current_vmcs12_page);
5650 nested_release_page(vmx->nested.current_vmcs12_page);
5651 }
5652
5653 vmx->nested.current_vmptr = vmptr;
5654 vmx->nested.current_vmcs12 = new_vmcs12;
5655 vmx->nested.current_vmcs12_page = page;
5656 }
5657
5658 nested_vmx_succeed(vcpu);
5659 skip_emulated_instruction(vcpu);
5660 return 1;
5661}
5662
6a4d7550
NHE		 5663/* Emulate the VMPTRST instruction */
5664static int handle_vmptrst(struct kvm_vcpu *vcpu)
5665{
5666 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5667 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5668 gva_t vmcs_gva;
5669 struct x86_exception e;
5670
5671 if (!nested_vmx_check_permission(vcpu))
5672 return 1;
5673
5674 if (get_vmx_mem_address(vcpu, exit_qualification,
5675 vmx_instruction_info, &vmcs_gva))
5676 return 1;
5677 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5678 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5679 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5680 sizeof(u64), &e)) {
5681 kvm_inject_page_fault(vcpu, &e);
5682 return 1;
5683 }
5684 nested_vmx_succeed(vcpu);
5685 skip_emulated_instruction(vcpu);
5686 return 1;
5687}
5688
6aa8b732
AK		 5689/*
5690 * The exit handlers return 1 if the exit was handled fully and guest execution
5691 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5692 * to be done to userspace and return 0.
5693 */
851ba692 5694static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5695 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5696 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5697 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5698 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5699 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5700 [EXIT_REASON_CR_ACCESS] = handle_cr,
5701 [EXIT_REASON_DR_ACCESS] = handle_dr,
5702 [EXIT_REASON_CPUID] = handle_cpuid,
5703 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5704 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5705 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5706 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5707 [EXIT_REASON_INVD] = handle_invd,
a7052897 5708 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5709 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5710 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5711 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5712 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5713 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5714 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5715 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5716 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5717 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5718 [EXIT_REASON_VMOFF] = handle_vmoff,
5719 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5720 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5721 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5722 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5723 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5724 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5725 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5726 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5727 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5728 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5729 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5730 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5731};
5732
5733static const int kvm_vmx_max_exit_handlers =
50a3485c 5734 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5735
644d711a
NHE		 5736/*
5737 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5738 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5739 * disinterest in the current event (read or write a specific MSR) by using an
5740 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5741 */
5742static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5743 struct vmcs12 *vmcs12, u32 exit_reason)
5744{
5745 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5746 gpa_t bitmap;
5747
5748 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5749 return 1;
5750
5751 /*
5752 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5753 * for the four combinations of read/write and low/high MSR numbers.
5754 * First we need to figure out which of the four to use:
5755 */
5756 bitmap = vmcs12->msr_bitmap;
5757 if (exit_reason == EXIT_REASON_MSR_WRITE)
5758 bitmap += 2048;
5759 if (msr_index >= 0xc0000000) {
5760 msr_index -= 0xc0000000;
5761 bitmap += 1024;
5762 }
5763
5764 /* Then read the msr_index'th bit from this bitmap: */
5765 if (msr_index < 1024*8) {
5766 unsigned char b;
5767 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5768 return 1 & (b >> (msr_index & 7));
5769 } else
5770 return 1; /* let L1 handle the wrong parameter */
5771}
5772
5773/*
5774 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5775 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5776 * intercept (via guest_host_mask etc.) the current event.
5777 */
5778static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5779 struct vmcs12 *vmcs12)
5780{
5781 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5782 int cr = exit_qualification & 15;
5783 int reg = (exit_qualification >> 8) & 15;
5784 unsigned long val = kvm_register_read(vcpu, reg);
5785
5786 switch ((exit_qualification >> 4) & 3) {
5787 case 0: /* mov to cr */
5788 switch (cr) {
5789 case 0:
5790 if (vmcs12->cr0_guest_host_mask &
5791 (val ^ vmcs12->cr0_read_shadow))
5792 return 1;
5793 break;
5794 case 3:
5795 if ((vmcs12->cr3_target_count >= 1 &&
5796 vmcs12->cr3_target_value0 == val) ||
5797 (vmcs12->cr3_target_count >= 2 &&
5798 vmcs12->cr3_target_value1 == val) ||
5799 (vmcs12->cr3_target_count >= 3 &&
5800 vmcs12->cr3_target_value2 == val) ||
5801 (vmcs12->cr3_target_count >= 4 &&
5802 vmcs12->cr3_target_value3 == val))
5803 return 0;
5804 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5805 return 1;
5806 break;
5807 case 4:
5808 if (vmcs12->cr4_guest_host_mask &
5809 (vmcs12->cr4_read_shadow ^ val))
5810 return 1;
5811 break;
5812 case 8:
5813 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5814 return 1;
5815 break;
5816 }
5817 break;
5818 case 2: /* clts */
5819 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5820 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5821 return 1;
5822 break;
5823 case 1: /* mov from cr */
5824 switch (cr) {
5825 case 3:
5826 if (vmcs12->cpu_based_vm_exec_control &
5827 CPU_BASED_CR3_STORE_EXITING)
5828 return 1;
5829 break;
5830 case 8:
5831 if (vmcs12->cpu_based_vm_exec_control &
5832 CPU_BASED_CR8_STORE_EXITING)
5833 return 1;
5834 break;
5835 }
5836 break;
5837 case 3: /* lmsw */
5838 /*
5839 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5840 * cr0. Other attempted changes are ignored, with no exit.
5841 */
5842 if (vmcs12->cr0_guest_host_mask & 0xe &
5843 (val ^ vmcs12->cr0_read_shadow))
5844 return 1;
5845 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5846 !(vmcs12->cr0_read_shadow & 0x1) &&
5847 (val & 0x1))
5848 return 1;
5849 break;
5850 }
5851 return 0;
5852}
5853
5854/*
5855 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5856 * should handle it ourselves in L0 (and then continue L2). Only call this
5857 * when in is_guest_mode (L2).
5858 */
5859static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5860{
5861 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5862 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5863 struct vcpu_vmx *vmx = to_vmx(vcpu);
5864 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5865
5866 if (vmx->nested.nested_run_pending)
5867 return 0;
5868
5869 if (unlikely(vmx->fail)) {
bd80158a
JK		 5870 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5871 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5872 return 1;
5873 }
5874
5875 switch (exit_reason) {
5876 case EXIT_REASON_EXCEPTION_NMI:
5877 if (!is_exception(intr_info))
5878 return 0;
5879 else if (is_page_fault(intr_info))
5880 return enable_ept;
5881 return vmcs12->exception_bitmap &
5882 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5883 case EXIT_REASON_EXTERNAL_INTERRUPT:
5884 return 0;
5885 case EXIT_REASON_TRIPLE_FAULT:
5886 return 1;
5887 case EXIT_REASON_PENDING_INTERRUPT:
5888 case EXIT_REASON_NMI_WINDOW:
5889 /*
5890 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5891 * (aka Interrupt Window Exiting) only when L1 turned it on,
5892 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5893 * Same for NMI Window Exiting.
5894 */
5895 return 1;
5896 case EXIT_REASON_TASK_SWITCH:
5897 return 1;
5898 case EXIT_REASON_CPUID:
5899 return 1;
5900 case EXIT_REASON_HLT:
5901 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5902 case EXIT_REASON_INVD:
5903 return 1;
5904 case EXIT_REASON_INVLPG:
5905 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5906 case EXIT_REASON_RDPMC:
5907 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5908 case EXIT_REASON_RDTSC:
5909 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5910 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5911 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5912 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5913 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5914 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5915 /*
5916 * VMX instructions trap unconditionally. This allows L1 to
5917 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5918 */
5919 return 1;
5920 case EXIT_REASON_CR_ACCESS:
5921 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5922 case EXIT_REASON_DR_ACCESS:
5923 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5924 case EXIT_REASON_IO_INSTRUCTION:
5925 /* TODO: support IO bitmaps */
5926 return 1;
5927 case EXIT_REASON_MSR_READ:
5928 case EXIT_REASON_MSR_WRITE:
5929 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5930 case EXIT_REASON_INVALID_STATE:
5931 return 1;
5932 case EXIT_REASON_MWAIT_INSTRUCTION:
5933 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5934 case EXIT_REASON_MONITOR_INSTRUCTION:
5935 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5936 case EXIT_REASON_PAUSE_INSTRUCTION:
5937 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5938 nested_cpu_has2(vmcs12,
5939 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5940 case EXIT_REASON_MCE_DURING_VMENTRY:
5941 return 0;
5942 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5943 return 1;
5944 case EXIT_REASON_APIC_ACCESS:
5945 return nested_cpu_has2(vmcs12,
5946 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5947 case EXIT_REASON_EPT_VIOLATION:
5948 case EXIT_REASON_EPT_MISCONFIG:
5949 return 0;
5950 case EXIT_REASON_WBINVD:
5951 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5952 case EXIT_REASON_XSETBV:
5953 return 1;
5954 default:
5955 return 1;
5956 }
5957}
5958
586f9607
AK		 5959static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5960{
5961 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5962 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5963}
5964
6aa8b732
AK		 5965/*
5966 * The guest has exited. See if we can fix it or if we need userspace
5967 * assistance.
5968 */
851ba692 5969static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5970{
29bd8a78 5971 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5972 u32 exit_reason = vmx->exit_reason;
1155f76a 5973 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5974
80ced186
MG		 5975 /* If guest state is invalid, start emulating */
5976 if (vmx->emulation_required && emulate_invalid_guest_state)
5977 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5978
b6f1250e
NHE		 5979 /*
5980 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5981 * we did not inject a still-pending event to L1 now because of
5982 * nested_run_pending, we need to re-enable this bit.
5983 */
5984 if (vmx->nested.nested_run_pending)
5985 kvm_make_request(KVM_REQ_EVENT, vcpu);
5986
509c75ea
NHE		 5987 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5988 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5989 vmx->nested.nested_run_pending = 1;
5990 else
5991 vmx->nested.nested_run_pending = 0;
5992
5993 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5994 nested_vmx_vmexit(vcpu);
5995 return 1;
5996 }
5997
5120702e
MG		 5998 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5999 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6000 vcpu->run->fail_entry.hardware_entry_failure_reason
6001 = exit_reason;
6002 return 0;
6003 }
6004
29bd8a78 6005 if (unlikely(vmx->fail)) {
851ba692
AK		 6006 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6007 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6008 = vmcs_read32(VM_INSTRUCTION_ERROR);
6009 return 0;
6010 }
6aa8b732 6011
d77c26fc 6012 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6013 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 6014 exit_reason != EXIT_REASON_EPT_VIOLATION &&
6015 exit_reason != EXIT_REASON_TASK_SWITCH))
6016 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
6017 "(0x%x) and exit reason is 0x%x\n",
6018 __func__, vectoring_info, exit_reason);
3b86cd99 6019
644d711a
NHE		 6020 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6021 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6022 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6023 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6024 vmx->soft_vnmi_blocked = 0;
3b86cd99 6025 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6026 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6027 /*
6028 * This CPU don't support us in finding the end of an
6029 * NMI-blocked window if the guest runs with IRQs
6030 * disabled. So we pull the trigger after 1 s of
6031 * futile waiting, but inform the user about this.
6032 */
6033 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6034 "state on VCPU %d after 1 s timeout\n",
6035 __func__, vcpu->vcpu_id);
6036 vmx->soft_vnmi_blocked = 0;
3b86cd99 6037 }
3b86cd99
JK		 6038 }
6039
6aa8b732
AK		 6040 if (exit_reason < kvm_vmx_max_exit_handlers
6041 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6042 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6043 else {
851ba692
AK		 6044 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6045 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6046 }
6047 return 0;
6048}
6049
95ba8273 6050static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6051{
95ba8273 6052 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6053 vmcs_write32(TPR_THRESHOLD, 0);
6054 return;
6055 }
6056
95ba8273 6057 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6058}
6059
51aa01d1 6060static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6061{
00eba012
AK		 6062 u32 exit_intr_info;
6063
6064 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6065 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6066 return;
6067
c5ca8e57 6068 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6069 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6070
6071 /* Handle machine checks before interrupts are enabled */
00eba012 6072 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6073 kvm_machine_check();
6074
20f65983 6075 /* We need to handle NMIs before interrupts are enabled */
00eba012 6076 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6077 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6078 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6079 asm("int $2");
ff9d07a0
ZY		 6080 kvm_after_handle_nmi(&vmx->vcpu);
6081 }
51aa01d1 6082}
20f65983 6083
51aa01d1
AK		 6084static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6085{
c5ca8e57 6086 u32 exit_intr_info;
51aa01d1
AK		 6087 bool unblock_nmi;
6088 u8 vector;
6089 bool idtv_info_valid;
6090
6091 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6092
cf393f75 6093 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6094 if (vmx->nmi_known_unmasked)
6095 return;
c5ca8e57
AK		 6096 /*
6097 * Can't use vmx->exit_intr_info since we're not sure what
6098 * the exit reason is.
6099 */
6100 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6101 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6102 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6103 /*
7b4a25cb 6104 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6105 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6106 * a guest IRET fault.
7b4a25cb
GN		 6107 * SDM 3: 23.2.2 (September 2008)
6108 * Bit 12 is undefined in any of the following cases:
6109 * If the VM exit sets the valid bit in the IDT-vectoring
6110 * information field.
6111 * If the VM exit is due to a double fault.
cf393f75 6112 */
7b4a25cb
GN		 6113 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6114 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6115 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6116 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6117 else
6118 vmx->nmi_known_unmasked =
6119 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6120 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6121 } else if (unlikely(vmx->soft_vnmi_blocked))
6122 vmx->vnmi_blocked_time +=
6123 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6124}
6125
83422e17
AK		 6126static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6127 u32 idt_vectoring_info,
6128 int instr_len_field,
6129 int error_code_field)
51aa01d1 6130{
51aa01d1
AK		 6131 u8 vector;
6132 int type;
6133 bool idtv_info_valid;
6134
6135 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6136
37b96e98
GN		 6137 vmx->vcpu.arch.nmi_injected = false;
6138 kvm_clear_exception_queue(&vmx->vcpu);
6139 kvm_clear_interrupt_queue(&vmx->vcpu);
6140
6141 if (!idtv_info_valid)
6142 return;
6143
3842d135
AK		 6144 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6145
668f612f
AK		 6146 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6147 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6148
64a7ec06 6149 switch (type) {
37b96e98
GN		 6150 case INTR_TYPE_NMI_INTR:
6151 vmx->vcpu.arch.nmi_injected = true;
668f612f 6152 /*
7b4a25cb 6153 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6154 * Clear bit "block by NMI" before VM entry if a NMI
6155 * delivery faulted.
668f612f 6156 */
654f06fc 6157 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6158 break;
37b96e98 6159 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6160 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6161 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6162 /* fall through */
6163 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6164 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6165 u32 err = vmcs_read32(error_code_field);
37b96e98 6166 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6167 } else
6168 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6169 break;
66fd3f7f
GN		 6170 case INTR_TYPE_SOFT_INTR:
6171 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6172 vmcs_read32(instr_len_field);
66fd3f7f 6173 /* fall through */
37b96e98 6174 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6175 kvm_queue_interrupt(&vmx->vcpu, vector,
6176 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6177 break;
6178 default:
6179 break;
f7d9238f 6180 }
cf393f75
AK		 6181}
6182
83422e17
AK		 6183static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6184{
66c78ae4
NHE		 6185 if (is_guest_mode(&vmx->vcpu))
6186 return;
83422e17
AK		 6187 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6188 VM_EXIT_INSTRUCTION_LEN,
6189 IDT_VECTORING_ERROR_CODE);
6190}
6191
b463a6f7
AK		 6192static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6193{
66c78ae4
NHE		 6194 if (is_guest_mode(vcpu))
6195 return;
b463a6f7
AK		 6196 __vmx_complete_interrupts(to_vmx(vcpu),
6197 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6198 VM_ENTRY_INSTRUCTION_LEN,
6199 VM_ENTRY_EXCEPTION_ERROR_CODE);
6200
6201 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6202}
6203
d7cd9796
GN		 6204static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6205{
6206 int i, nr_msrs;
6207 struct perf_guest_switch_msr *msrs;
6208
6209 msrs = perf_guest_get_msrs(&nr_msrs);
6210
6211 if (!msrs)
6212 return;
6213
6214 for (i = 0; i < nr_msrs; i++)
6215 if (msrs[i].host == msrs[i].guest)
6216 clear_atomic_switch_msr(vmx, msrs[i].msr);
6217 else
6218 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6219 msrs[i].host);
6220}
6221
c801949d
AK		 6222#ifdef CONFIG_X86_64
6223#define R "r"
6224#define Q "q"
6225#else
6226#define R "e"
6227#define Q "l"
6228#endif
6229
a3b5ba49 6230static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6231{
a2fa3e9f 6232 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 6233
66c78ae4
NHE		 6234 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6235 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6236 if (vmcs12->idt_vectoring_info_field &
6237 VECTORING_INFO_VALID_MASK) {
6238 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6239 vmcs12->idt_vectoring_info_field);
6240 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6241 vmcs12->vm_exit_instruction_len);
6242 if (vmcs12->idt_vectoring_info_field &
6243 VECTORING_INFO_DELIVER_CODE_MASK)
6244 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6245 vmcs12->idt_vectoring_error_code);
6246 }
6247 }
6248
104f226b
AK		 6249 /* Record the guest's net vcpu time for enforced NMI injections. */
6250 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6251 vmx->entry_time = ktime_get();
6252
6253 /* Don't enter VMX if guest state is invalid, let the exit handler
6254 start emulation until we arrive back to a valid state */
6255 if (vmx->emulation_required && emulate_invalid_guest_state)
6256 return;
6257
6258 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6259 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6260 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6261 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6262
6263 /* When single-stepping over STI and MOV SS, we must clear the
6264 * corresponding interruptibility bits in the guest state. Otherwise
6265 * vmentry fails as it then expects bit 14 (BS) in pending debug
6266 * exceptions being set, but that's not correct for the guest debugging
6267 * case. */
6268 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6269 vmx_set_interrupt_shadow(vcpu, 0);
6270
d7cd9796
GN		 6271 atomic_switch_perf_msrs(vmx);
6272
d462b819 6273 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6274 asm(
6aa8b732 6275 /* Store host registers */
c801949d 6276 "push %%"R"dx; push %%"R"bp;"
40712fae 6277 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 6278 "push %%"R"cx \n\t"
313dbd49
AK		 6279 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6280 "je 1f \n\t"
6281 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 6282 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6283 "1: \n\t"
d3edefc0
AK		 6284 /* Reload cr2 if changed */
6285 "mov %c[cr2](%0), %%"R"ax \n\t"
6286 "mov %%cr2, %%"R"dx \n\t"
6287 "cmp %%"R"ax, %%"R"dx \n\t"
6288 "je 2f \n\t"
6289 "mov %%"R"ax, %%cr2 \n\t"
6290 "2: \n\t"
6aa8b732 6291 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6292 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6293 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 6294 "mov %c[rax](%0), %%"R"ax \n\t"
6295 "mov %c[rbx](%0), %%"R"bx \n\t"
6296 "mov %c[rdx](%0), %%"R"dx \n\t"
6297 "mov %c[rsi](%0), %%"R"si \n\t"
6298 "mov %c[rdi](%0), %%"R"di \n\t"
6299 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 6300#ifdef CONFIG_X86_64
e08aa78a
AK		 6301 "mov %c[r8](%0), %%r8 \n\t"
6302 "mov %c[r9](%0), %%r9 \n\t"
6303 "mov %c[r10](%0), %%r10 \n\t"
6304 "mov %c[r11](%0), %%r11 \n\t"
6305 "mov %c[r12](%0), %%r12 \n\t"
6306 "mov %c[r13](%0), %%r13 \n\t"
6307 "mov %c[r14](%0), %%r14 \n\t"
6308 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6309#endif
c801949d
AK		 6310 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6311
6aa8b732 6312 /* Enter guest mode */
cd2276a7 6313 "jne .Llaunched \n\t"
4ecac3fd 6314 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 6315 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 6316 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 6317 ".Lkvm_vmx_return: "
6aa8b732 6318 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 6319 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6320 "pop %0 \n\t"
c801949d
AK		 6321 "mov %%"R"ax, %c[rax](%0) \n\t"
6322 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 6323 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 6324 "mov %%"R"dx, %c[rdx](%0) \n\t"
6325 "mov %%"R"si, %c[rsi](%0) \n\t"
6326 "mov %%"R"di, %c[rdi](%0) \n\t"
6327 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 6328#ifdef CONFIG_X86_64
e08aa78a
AK		 6329 "mov %%r8, %c[r8](%0) \n\t"
6330 "mov %%r9, %c[r9](%0) \n\t"
6331 "mov %%r10, %c[r10](%0) \n\t"
6332 "mov %%r11, %c[r11](%0) \n\t"
6333 "mov %%r12, %c[r12](%0) \n\t"
6334 "mov %%r13, %c[r13](%0) \n\t"
6335 "mov %%r14, %c[r14](%0) \n\t"
6336 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6337#endif
c801949d
AK		 6338 "mov %%cr2, %%"R"ax \n\t"
6339 "mov %%"R"ax, %c[cr2](%0) \n\t"
6340
1c696d0e 6341 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 6342 "setbe %c[fail](%0) \n\t"
6343 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6344 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6345 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6346 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6347 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6348 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6349 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6350 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6351 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6352 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6353 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6354#ifdef CONFIG_X86_64
ad312c7c
ZX		 6355 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6356 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6357 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6358 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6359 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6360 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6361 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6362 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6363#endif
40712fae
AK		 6364 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6365 [wordsize]"i"(sizeof(ulong))
c2036300 6366 : "cc", "memory"
07d6f555 6367 , R"ax", R"bx", R"di", R"si"
c2036300 6368#ifdef CONFIG_X86_64
c2036300
LV		 6369 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6370#endif
6371 );
6aa8b732 6372
6de4f3ad 6373 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6374 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6375 | (1 << VCPU_EXREG_CPL)
aff48baa 6376 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6377 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6378 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6379 vcpu->arch.regs_dirty = 0;
6380
1155f76a
AK		 6381 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6382
66c78ae4
NHE		 6383 if (is_guest_mode(vcpu)) {
6384 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6385 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6386 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6387 vmcs12->idt_vectoring_error_code =
6388 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6389 vmcs12->vm_exit_instruction_len =
6390 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6391 }
6392 }
6393
d462b819 6394 vmx->loaded_vmcs->launched = 1;
1b6269db 6395
51aa01d1 6396 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6397 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6398
6399 vmx_complete_atomic_exit(vmx);
6400 vmx_recover_nmi_blocking(vmx);
cf393f75 6401 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6402}
6403
c801949d
AK		 6404#undef R
6405#undef Q
6406
6aa8b732
AK		 6407static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6408{
fb3f0f51
RR		 6409 struct vcpu_vmx *vmx = to_vmx(vcpu);
6410
cdbecfc3 6411 free_vpid(vmx);
ec378aee 6412 free_nested(vmx);
d462b819 6413 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6414 kfree(vmx->guest_msrs);
6415 kvm_vcpu_uninit(vcpu);
a4770347 6416 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6417}
6418
fb3f0f51 6419static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6420{
fb3f0f51 6421 int err;
c16f862d 6422 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6423 int cpu;
6aa8b732 6424
a2fa3e9f 6425 if (!vmx)
fb3f0f51
RR		 6426 return ERR_PTR(-ENOMEM);
6427
2384d2b3
SY		 6428 allocate_vpid(vmx);
6429
fb3f0f51
RR		 6430 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6431 if (err)
6432 goto free_vcpu;
965b58a5 6433
a2fa3e9f 6434 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6435 err = -ENOMEM;
fb3f0f51 6436 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6437 goto uninit_vcpu;
6438 }
965b58a5 6439
d462b819
NHE		 6440 vmx->loaded_vmcs = &vmx->vmcs01;
6441 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6442 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6443 goto free_msrs;
d462b819
NHE		 6444 if (!vmm_exclusive)
6445 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6446 loaded_vmcs_init(vmx->loaded_vmcs);
6447 if (!vmm_exclusive)
6448 kvm_cpu_vmxoff();
a2fa3e9f 6449
15ad7146
AK		 6450 cpu = get_cpu();
6451 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6452 vmx->vcpu.cpu = cpu;
8b9cf98c 6453 err = vmx_vcpu_setup(vmx);
fb3f0f51 6454 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6455 put_cpu();
fb3f0f51
RR		 6456 if (err)
6457 goto free_vmcs;
5e4a0b3c 6458 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6459 err = alloc_apic_access_page(kvm);
6460 if (err)
5e4a0b3c 6461 goto free_vmcs;
fb3f0f51 6462
b927a3ce
SY		 6463 if (enable_ept) {
6464 if (!kvm->arch.ept_identity_map_addr)
6465 kvm->arch.ept_identity_map_addr =
6466 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6467 err = -ENOMEM;
b7ebfb05
SY		 6468 if (alloc_identity_pagetable(kvm) != 0)
6469 goto free_vmcs;
93ea5388
GN		 6470 if (!init_rmode_identity_map(kvm))
6471 goto free_vmcs;
b927a3ce 6472 }
b7ebfb05 6473
a9d30f33
NHE		 6474 vmx->nested.current_vmptr = -1ull;
6475 vmx->nested.current_vmcs12 = NULL;
6476
fb3f0f51
RR		 6477 return &vmx->vcpu;
6478
6479free_vmcs:
5f3fbc34 6480 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6481free_msrs:
fb3f0f51
RR		 6482 kfree(vmx->guest_msrs);
6483uninit_vcpu:
6484 kvm_vcpu_uninit(&vmx->vcpu);
6485free_vcpu:
cdbecfc3 6486 free_vpid(vmx);
a4770347 6487 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6488 return ERR_PTR(err);
6aa8b732
AK		 6489}
6490
002c7f7c
YS		 6491static void __init vmx_check_processor_compat(void *rtn)
6492{
6493 struct vmcs_config vmcs_conf;
6494
6495 *(int *)rtn = 0;
6496 if (setup_vmcs_config(&vmcs_conf) < 0)
6497 *(int *)rtn = -EIO;
6498 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6499 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6500 smp_processor_id());
6501 *(int *)rtn = -EIO;
6502 }
6503}
6504
67253af5
SY		 6505static int get_ept_level(void)
6506{
6507 return VMX_EPT_DEFAULT_GAW + 1;
6508}
6509
4b12f0de 6510static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6511{
4b12f0de
SY		 6512 u64 ret;
6513
522c68c4
SY		 6514 /* For VT-d and EPT combination
6515 * 1. MMIO: always map as UC
6516 * 2. EPT with VT-d:
6517 * a. VT-d without snooping control feature: can't guarantee the
6518 * result, try to trust guest.
6519 * b. VT-d with snooping control feature: snooping control feature of
6520 * VT-d engine can guarantee the cache correctness. Just set it
6521 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6522 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6523 * consistent with host MTRR
6524 */
4b12f0de
SY		 6525 if (is_mmio)
6526 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6527 else if (vcpu->kvm->arch.iommu_domain &&
6528 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6529 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6530 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6531 else
522c68c4 6532 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6533 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6534
6535 return ret;
64d4d521
SY		 6536}
6537
17cc3935 6538static int vmx_get_lpage_level(void)
344f414f 6539{
878403b7
SY		 6540 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6541 return PT_DIRECTORY_LEVEL;
6542 else
6543 /* For shadow and EPT supported 1GB page */
6544 return PT_PDPE_LEVEL;
344f414f
JR		 6545}
6546
0e851880
SY		 6547static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6548{
4e47c7a6
SY		 6549 struct kvm_cpuid_entry2 *best;
6550 struct vcpu_vmx *vmx = to_vmx(vcpu);
6551 u32 exec_control;
6552
6553 vmx->rdtscp_enabled = false;
6554 if (vmx_rdtscp_supported()) {
6555 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6556 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6557 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6558 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6559 vmx->rdtscp_enabled = true;
6560 else {
6561 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6562 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6563 exec_control);
6564 }
6565 }
6566 }
ad756a16
MJ		 6567
6568 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6569 /* Exposing INVPCID only when PCID is exposed */
6570 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6571 if (vmx_invpcid_supported() &&
6572 best && (best->ecx & bit(X86_FEATURE_INVPCID)) &&
6573 guest_cpuid_has_pcid(vcpu)) {
6574 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6575 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6576 exec_control);
6577 } else {
6578 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6579 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6580 exec_control);
6581 if (best)
6582 best->ecx &= ~bit(X86_FEATURE_INVPCID);
6583 }
0e851880
SY		 6584}
6585
d4330ef2
JR		 6586static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6587{
7b8050f5
NHE		 6588 if (func == 1 && nested)
6589 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6590}
6591
fe3ef05c
NHE		 6592/*
6593 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6594 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6595 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6596 * guest in a way that will both be appropriate to L1's requests, and our
6597 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6598 * function also has additional necessary side-effects, like setting various
6599 * vcpu->arch fields.
6600 */
6601static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6602{
6603 struct vcpu_vmx *vmx = to_vmx(vcpu);
6604 u32 exec_control;
6605
6606 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6607 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6608 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6609 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6610 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6611 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6612 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6613 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6614 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6615 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6616 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6617 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6618 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6619 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6620 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6621 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6622 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6623 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6624 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6625 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6626 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6627 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6628 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6629 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6630 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6631 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6632 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6633 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6634 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6635 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6636 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6637 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6638 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6639 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6640 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6641 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6642
6643 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6644 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6645 vmcs12->vm_entry_intr_info_field);
6646 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6647 vmcs12->vm_entry_exception_error_code);
6648 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6649 vmcs12->vm_entry_instruction_len);
6650 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6651 vmcs12->guest_interruptibility_info);
6652 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6653 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6654 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6655 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6656 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6657 vmcs12->guest_pending_dbg_exceptions);
6658 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6659 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6660
6661 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6662
6663 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6664 (vmcs_config.pin_based_exec_ctrl |
6665 vmcs12->pin_based_vm_exec_control));
6666
6667 /*
6668 * Whether page-faults are trapped is determined by a combination of
6669 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6670 * If enable_ept, L0 doesn't care about page faults and we should
6671 * set all of these to L1's desires. However, if !enable_ept, L0 does
6672 * care about (at least some) page faults, and because it is not easy
6673 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6674 * to exit on each and every L2 page fault. This is done by setting
6675 * MASK=MATCH=0 and (see below) EB.PF=1.
6676 * Note that below we don't need special code to set EB.PF beyond the
6677 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6678 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6679 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6680 *
6681 * A problem with this approach (when !enable_ept) is that L1 may be
6682 * injected with more page faults than it asked for. This could have
6683 * caused problems, but in practice existing hypervisors don't care.
6684 * To fix this, we will need to emulate the PFEC checking (on the L1
6685 * page tables), using walk_addr(), when injecting PFs to L1.
6686 */
6687 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6688 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6689 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6690 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6691
6692 if (cpu_has_secondary_exec_ctrls()) {
6693 u32 exec_control = vmx_secondary_exec_control(vmx);
6694 if (!vmx->rdtscp_enabled)
6695 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6696 /* Take the following fields only from vmcs12 */
6697 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6698 if (nested_cpu_has(vmcs12,
6699 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6700 exec_control |= vmcs12->secondary_vm_exec_control;
6701
6702 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6703 /*
6704 * Translate L1 physical address to host physical
6705 * address for vmcs02. Keep the page pinned, so this
6706 * physical address remains valid. We keep a reference
6707 * to it so we can release it later.
6708 */
6709 if (vmx->nested.apic_access_page) /* shouldn't happen */
6710 nested_release_page(vmx->nested.apic_access_page);
6711 vmx->nested.apic_access_page =
6712 nested_get_page(vcpu, vmcs12->apic_access_addr);
6713 /*
6714 * If translation failed, no matter: This feature asks
6715 * to exit when accessing the given address, and if it
6716 * can never be accessed, this feature won't do
6717 * anything anyway.
6718 */
6719 if (!vmx->nested.apic_access_page)
6720 exec_control &=
6721 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6722 else
6723 vmcs_write64(APIC_ACCESS_ADDR,
6724 page_to_phys(vmx->nested.apic_access_page));
6725 }
6726
6727 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6728 }
6729
6730
6731 /*
6732 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6733 * Some constant fields are set here by vmx_set_constant_host_state().
6734 * Other fields are different per CPU, and will be set later when
6735 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6736 */
6737 vmx_set_constant_host_state();
6738
6739 /*
6740 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6741 * entry, but only if the current (host) sp changed from the value
6742 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6743 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6744 * here we just force the write to happen on entry.
6745 */
6746 vmx->host_rsp = 0;
6747
6748 exec_control = vmx_exec_control(vmx); /* L0's desires */
6749 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6750 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6751 exec_control &= ~CPU_BASED_TPR_SHADOW;
6752 exec_control |= vmcs12->cpu_based_vm_exec_control;
6753 /*
6754 * Merging of IO and MSR bitmaps not currently supported.
6755 * Rather, exit every time.
6756 */
6757 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6758 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6759 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6760
6761 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6762
6763 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6764 * bitwise-or of what L1 wants to trap for L2, and what we want to
6765 * trap. Note that CR0.TS also needs updating - we do this later.
6766 */
6767 update_exception_bitmap(vcpu);
6768 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6769 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6770
6771 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6772 vmcs_write32(VM_EXIT_CONTROLS,
6773 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6774 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6775 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6776
6777 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6778 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6779 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6780 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6781
6782
6783 set_cr4_guest_host_mask(vmx);
6784
27fc51b2
NHE		 6785 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6786 vmcs_write64(TSC_OFFSET,
6787 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6788 else
6789 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6790
6791 if (enable_vpid) {
6792 /*
6793 * Trivially support vpid by letting L2s share their parent
6794 * L1's vpid. TODO: move to a more elaborate solution, giving
6795 * each L2 its own vpid and exposing the vpid feature to L1.
6796 */
6797 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6798 vmx_flush_tlb(vcpu);
6799 }
6800
6801 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6802 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6803 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6804 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6805 else
6806 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6807 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6808 vmx_set_efer(vcpu, vcpu->arch.efer);
6809
6810 /*
6811 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6812 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6813 * The CR0_READ_SHADOW is what L2 should have expected to read given
6814 * the specifications by L1; It's not enough to take
6815 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6816 * have more bits than L1 expected.
6817 */
6818 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6819 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6820
6821 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6822 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6823
6824 /* shadow page tables on either EPT or shadow page tables */
6825 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6826 kvm_mmu_reset_context(vcpu);
6827
6828 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6829 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6830}
6831
cd232ad0
NHE		 6832/*
6833 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6834 * for running an L2 nested guest.
6835 */
6836static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6837{
6838 struct vmcs12 *vmcs12;
6839 struct vcpu_vmx *vmx = to_vmx(vcpu);
6840 int cpu;
6841 struct loaded_vmcs *vmcs02;
6842
6843 if (!nested_vmx_check_permission(vcpu) ||
6844 !nested_vmx_check_vmcs12(vcpu))
6845 return 1;
6846
6847 skip_emulated_instruction(vcpu);
6848 vmcs12 = get_vmcs12(vcpu);
6849
7c177938
NHE		 6850 /*
6851 * The nested entry process starts with enforcing various prerequisites
6852 * on vmcs12 as required by the Intel SDM, and act appropriately when
6853 * they fail: As the SDM explains, some conditions should cause the
6854 * instruction to fail, while others will cause the instruction to seem
6855 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6856 * To speed up the normal (success) code path, we should avoid checking
6857 * for misconfigurations which will anyway be caught by the processor
6858 * when using the merged vmcs02.
6859 */
6860 if (vmcs12->launch_state == launch) {
6861 nested_vmx_failValid(vcpu,
6862 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6863 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6864 return 1;
6865 }
6866
6867 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6868 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6869 /*TODO: Also verify bits beyond physical address width are 0*/
6870 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6871 return 1;
6872 }
6873
6874 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6875 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6876 /*TODO: Also verify bits beyond physical address width are 0*/
6877 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6878 return 1;
6879 }
6880
6881 if (vmcs12->vm_entry_msr_load_count > 0 ||
6882 vmcs12->vm_exit_msr_load_count > 0 ||
6883 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6884 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6885 __func__);
7c177938
NHE		 6886 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6887 return 1;
6888 }
6889
6890 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6891 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6892 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6893 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6894 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6895 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6896 !vmx_control_verify(vmcs12->vm_exit_controls,
6897 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6898 !vmx_control_verify(vmcs12->vm_entry_controls,
6899 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6900 {
6901 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6902 return 1;
6903 }
6904
6905 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6906 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6907 nested_vmx_failValid(vcpu,
6908 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6909 return 1;
6910 }
6911
6912 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6913 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6914 nested_vmx_entry_failure(vcpu, vmcs12,
6915 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6916 return 1;
6917 }
6918 if (vmcs12->vmcs_link_pointer != -1ull) {
6919 nested_vmx_entry_failure(vcpu, vmcs12,
6920 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6921 return 1;
6922 }
6923
6924 /*
6925 * We're finally done with prerequisite checking, and can start with
6926 * the nested entry.
6927 */
6928
cd232ad0
NHE		 6929 vmcs02 = nested_get_current_vmcs02(vmx);
6930 if (!vmcs02)
6931 return -ENOMEM;
6932
6933 enter_guest_mode(vcpu);
6934
6935 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6936
6937 cpu = get_cpu();
6938 vmx->loaded_vmcs = vmcs02;
6939 vmx_vcpu_put(vcpu);
6940 vmx_vcpu_load(vcpu, cpu);
6941 vcpu->cpu = cpu;
6942 put_cpu();
6943
6944 vmcs12->launch_state = 1;
6945
6946 prepare_vmcs02(vcpu, vmcs12);
6947
6948 /*
6949 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6950 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6951 * returned as far as L1 is concerned. It will only return (and set
6952 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6953 */
6954 return 1;
6955}
6956
4704d0be
NHE		 6957/*
6958 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6959 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6960 * This function returns the new value we should put in vmcs12.guest_cr0.
6961 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6962 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6963 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6964 * didn't trap the bit, because if L1 did, so would L0).
6965 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6966 * been modified by L2, and L1 knows it. So just leave the old value of
6967 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6968 * isn't relevant, because if L0 traps this bit it can set it to anything.
6969 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6970 * changed these bits, and therefore they need to be updated, but L0
6971 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6972 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6973 */
6974static inline unsigned long
6975vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6976{
6977 return
6978 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6979 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6980 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6981 vcpu->arch.cr0_guest_owned_bits));
6982}
6983
6984static inline unsigned long
6985vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6986{
6987 return
6988 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6989 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6990 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6991 vcpu->arch.cr4_guest_owned_bits));
6992}
6993
6994/*
6995 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6996 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6997 * and this function updates it to reflect the changes to the guest state while
6998 * L2 was running (and perhaps made some exits which were handled directly by L0
6999 * without going back to L1), and to reflect the exit reason.
7000 * Note that we do not have to copy here all VMCS fields, just those that
7001 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7002 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7003 * which already writes to vmcs12 directly.
7004 */
7005void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7006{
7007 /* update guest state fields: */
7008 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7009 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7010
7011 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7012 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7013 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7014 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7015
7016 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7017 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7018 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7019 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7020 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7021 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7022 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7023 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7024 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7025 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7026 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7027 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7028 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7029 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7030 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7031 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7032 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7033 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7034 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7035 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7036 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7037 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7038 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7039 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7040 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7041 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7042 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7043 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7044 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7045 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7046 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7047 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7048 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7049 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7050 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7051 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7052
7053 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7054 vmcs12->guest_interruptibility_info =
7055 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7056 vmcs12->guest_pending_dbg_exceptions =
7057 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7058
7059 /* TODO: These cannot have changed unless we have MSR bitmaps and
7060 * the relevant bit asks not to trap the change */
7061 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7062 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7063 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7064 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7065 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7066 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7067
7068 /* update exit information fields: */
7069
7070 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7071 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7072
7073 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7074 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7075 vmcs12->idt_vectoring_info_field =
7076 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7077 vmcs12->idt_vectoring_error_code =
7078 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7079 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7080 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7081
7082 /* clear vm-entry fields which are to be cleared on exit */
7083 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7084 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7085}
7086
7087/*
7088 * A part of what we need to when the nested L2 guest exits and we want to
7089 * run its L1 parent, is to reset L1's guest state to the host state specified
7090 * in vmcs12.
7091 * This function is to be called not only on normal nested exit, but also on
7092 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7093 * Failures During or After Loading Guest State").
7094 * This function should be called when the active VMCS is L1's (vmcs01).
7095 */
7096void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7097{
7098 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7099 vcpu->arch.efer = vmcs12->host_ia32_efer;
7100 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7101 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7102 else
7103 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7104 vmx_set_efer(vcpu, vcpu->arch.efer);
7105
7106 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7107 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7108 /*
7109 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7110 * actually changed, because it depends on the current state of
7111 * fpu_active (which may have changed).
7112 * Note that vmx_set_cr0 refers to efer set above.
7113 */
7114 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7115 /*
7116 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7117 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7118 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7119 */
7120 update_exception_bitmap(vcpu);
7121 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7122 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7123
7124 /*
7125 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7126 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7127 */
7128 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7129 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7130
7131 /* shadow page tables on either EPT or shadow page tables */
7132 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7133 kvm_mmu_reset_context(vcpu);
7134
7135 if (enable_vpid) {
7136 /*
7137 * Trivially support vpid by letting L2s share their parent
7138 * L1's vpid. TODO: move to a more elaborate solution, giving
7139 * each L2 its own vpid and exposing the vpid feature to L1.
7140 */
7141 vmx_flush_tlb(vcpu);
7142 }
7143
7144
7145 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7146 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7147 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7148 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7149 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7150 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7151 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7152 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7153 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7154 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7155 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7156 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7157 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7158 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7159 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7160
7161 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7162 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7163 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7164 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7165 vmcs12->host_ia32_perf_global_ctrl);
7166}
7167
7168/*
7169 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7170 * and modify vmcs12 to make it see what it would expect to see there if
7171 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7172 */
7173static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7174{
7175 struct vcpu_vmx *vmx = to_vmx(vcpu);
7176 int cpu;
7177 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7178
7179 leave_guest_mode(vcpu);
7180 prepare_vmcs12(vcpu, vmcs12);
7181
7182 cpu = get_cpu();
7183 vmx->loaded_vmcs = &vmx->vmcs01;
7184 vmx_vcpu_put(vcpu);
7185 vmx_vcpu_load(vcpu, cpu);
7186 vcpu->cpu = cpu;
7187 put_cpu();
7188
7189 /* if no vmcs02 cache requested, remove the one we used */
7190 if (VMCS02_POOL_SIZE == 0)
7191 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7192
7193 load_vmcs12_host_state(vcpu, vmcs12);
7194
27fc51b2 7195 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7196 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7197
7198 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7199 vmx->host_rsp = 0;
7200
7201 /* Unpin physical memory we referred to in vmcs02 */
7202 if (vmx->nested.apic_access_page) {
7203 nested_release_page(vmx->nested.apic_access_page);
7204 vmx->nested.apic_access_page = 0;
7205 }
7206
7207 /*
7208 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7209 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7210 * success or failure flag accordingly.
7211 */
7212 if (unlikely(vmx->fail)) {
7213 vmx->fail = 0;
7214 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7215 } else
7216 nested_vmx_succeed(vcpu);
7217}
7218
7c177938
NHE		 7219/*
7220 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7221 * 23.7 "VM-entry failures during or after loading guest state" (this also
7222 * lists the acceptable exit-reason and exit-qualification parameters).
7223 * It should only be called before L2 actually succeeded to run, and when
7224 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7225 */
7226static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7227 struct vmcs12 *vmcs12,
7228 u32 reason, unsigned long qualification)
7229{
7230 load_vmcs12_host_state(vcpu, vmcs12);
7231 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7232 vmcs12->exit_qualification = qualification;
7233 nested_vmx_succeed(vcpu);
7234}
7235
8a76d7f2
JR		 7236static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7237 struct x86_instruction_info *info,
7238 enum x86_intercept_stage stage)
7239{
7240 return X86EMUL_CONTINUE;
7241}
7242
cbdd1bea 7243static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7244 .cpu_has_kvm_support = cpu_has_kvm_support,
7245 .disabled_by_bios = vmx_disabled_by_bios,
7246 .hardware_setup = hardware_setup,
7247 .hardware_unsetup = hardware_unsetup,
002c7f7c 7248 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7249 .hardware_enable = hardware_enable,
7250 .hardware_disable = hardware_disable,
04547156 7251 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7252
7253 .vcpu_create = vmx_create_vcpu,
7254 .vcpu_free = vmx_free_vcpu,
04d2cc77 7255 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7256
04d2cc77 7257 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7258 .vcpu_load = vmx_vcpu_load,
7259 .vcpu_put = vmx_vcpu_put,
7260
7261 .set_guest_debug = set_guest_debug,
7262 .get_msr = vmx_get_msr,
7263 .set_msr = vmx_set_msr,
7264 .get_segment_base = vmx_get_segment_base,
7265 .get_segment = vmx_get_segment,
7266 .set_segment = vmx_set_segment,
2e4d2653 7267 .get_cpl = vmx_get_cpl,
6aa8b732 7268 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7269 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7270 .decache_cr3 = vmx_decache_cr3,
25c4c276 7271 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7272 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7273 .set_cr3 = vmx_set_cr3,
7274 .set_cr4 = vmx_set_cr4,
6aa8b732 7275 .set_efer = vmx_set_efer,
6aa8b732
AK		 7276 .get_idt = vmx_get_idt,
7277 .set_idt = vmx_set_idt,
7278 .get_gdt = vmx_get_gdt,
7279 .set_gdt = vmx_set_gdt,
020df079 7280 .set_dr7 = vmx_set_dr7,
5fdbf976 7281 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7282 .get_rflags = vmx_get_rflags,
7283 .set_rflags = vmx_set_rflags,
ebcbab4c 7284 .fpu_activate = vmx_fpu_activate,
02daab21 7285 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7286
7287 .tlb_flush = vmx_flush_tlb,
6aa8b732 7288
6aa8b732 7289 .run = vmx_vcpu_run,
6062d012 7290 .handle_exit = vmx_handle_exit,
6aa8b732 7291 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7292 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7293 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7294 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7295 .set_irq = vmx_inject_irq,
95ba8273 7296 .set_nmi = vmx_inject_nmi,
298101da 7297 .queue_exception = vmx_queue_exception,
b463a6f7 7298 .cancel_injection = vmx_cancel_injection,
78646121 7299 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7300 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7301 .get_nmi_mask = vmx_get_nmi_mask,
7302 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7303 .enable_nmi_window = enable_nmi_window,
7304 .enable_irq_window = enable_irq_window,
7305 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7306
cbc94022 7307 .set_tss_addr = vmx_set_tss_addr,
67253af5 7308 .get_tdp_level = get_ept_level,
4b12f0de 7309 .get_mt_mask = vmx_get_mt_mask,
229456fc 7310
586f9607 7311 .get_exit_info = vmx_get_exit_info,
586f9607 7312
17cc3935 7313 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7314
7315 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7316
7317 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7318 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7319
7320 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7321
7322 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7323
4051b188 7324 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7325 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7326 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7327 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7328 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7329
7330 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7331
7332 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7333};
7334
7335static int __init vmx_init(void)
7336{
26bb0981
AK		 7337 int r, i;
7338
7339 rdmsrl_safe(MSR_EFER, &host_efer);
7340
7341 for (i = 0; i < NR_VMX_MSR; ++i)
7342 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7343
3e7c73e9 7344 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7345 if (!vmx_io_bitmap_a)
7346 return -ENOMEM;
7347
2106a548
GC		 7348 r = -ENOMEM;
7349
3e7c73e9 7350 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7351 if (!vmx_io_bitmap_b)
fdef3ad1 7352 goto out;
fdef3ad1 7353
5897297b 7354 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7355 if (!vmx_msr_bitmap_legacy)
25c5f225 7356 goto out1;
2106a548 7357
25c5f225 7358
5897297b 7359 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7360 if (!vmx_msr_bitmap_longmode)
5897297b 7361 goto out2;
2106a548 7362
5897297b 7363
fdef3ad1
HQ		 7364 /*
7365 * Allow direct access to the PC debug port (it is often used for I/O
7366 * delays, but the vmexits simply slow things down).
7367 */
3e7c73e9
AK		 7368 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7369 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7370
3e7c73e9 7371 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7372
5897297b
AK		 7373 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7374 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7375
2384d2b3
SY		 7376 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7377
0ee75bea
AK		 7378 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7379 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7380 if (r)
5897297b 7381 goto out3;
25c5f225 7382
5897297b
AK		 7383 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7384 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7385 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7386 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7387 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7388 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7389
089d034e 7390 if (enable_ept) {
3f6d8c8a
XH		 7391 kvm_mmu_set_mask_ptes(0ull,
7392 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7393 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7394 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7395 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7396 kvm_enable_tdp();
7397 } else
7398 kvm_disable_tdp();
1439442c 7399
fdef3ad1
HQ		 7400 return 0;
7401
5897297b
AK		 7402out3:
7403 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7404out2:
5897297b 7405 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7406out1:
3e7c73e9 7407 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7408out:
3e7c73e9 7409 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7410 return r;
6aa8b732
AK		 7411}
7412
7413static void __exit vmx_exit(void)
7414{
5897297b
AK		 7415 free_page((unsigned long)vmx_msr_bitmap_legacy);
7416 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7417 free_page((unsigned long)vmx_io_bitmap_b);
7418 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7419
cb498ea2 7420 kvm_exit();
6aa8b732
AK		 7421}
7422
7423module_init(vmx_init)
7424module_exit(vmx_exit)
Linux 6.x block layer and io_uring tree(s)